1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
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13 * When distributing Covered Code, include this CDDL HEADER in each
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15 * If applicable, add the following below this CDDL HEADER, with the
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21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 #ifndef REG_ADDR_H
37 #define REG_ADDR_H
38 
39 #define PGLCS_REG_INT_STS                                                                            0x001d00UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40     #define PGLCS_REG_INT_STS_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
41     #define PGLCS_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                    0
42     #define PGLCS_REG_INT_STS_RASDP_ERROR                                                            (0x1<<1) // It indicates rasdp error
43     #define PGLCS_REG_INT_STS_RASDP_ERROR_SHIFT                                                      1
44 #define PGLCS_REG_INT_MASK                                                                           0x001d04UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
45     #define PGLCS_REG_INT_MASK_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.ADDRESS_ERROR .
46     #define PGLCS_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                   0
47     #define PGLCS_REG_INT_MASK_RASDP_ERROR                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLCS_REG_INT_STS.RASDP_ERROR .
48     #define PGLCS_REG_INT_MASK_RASDP_ERROR_SHIFT                                                     1
49 #define PGLCS_REG_INT_STS_WR                                                                         0x001d08UL //Access:WR   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50     #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
51     #define PGLCS_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                 0
52     #define PGLCS_REG_INT_STS_WR_RASDP_ERROR                                                         (0x1<<1) // It indicates rasdp error
53     #define PGLCS_REG_INT_STS_WR_RASDP_ERROR_SHIFT                                                   1
54 #define PGLCS_REG_INT_STS_CLR                                                                        0x001d0cUL //Access:RC   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
55     #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
56     #define PGLCS_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                0
57     #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR                                                        (0x1<<1) // It indicates rasdp error
58     #define PGLCS_REG_INT_STS_CLR_RASDP_ERROR_SHIFT                                                  1
59 #define PGLCS_REG_RASDP_ERROR_MODE_EN_OFF                                                            0x001d10UL //Access:RW   DataWidth:0x1   Disable rasdp error mode check  Chips: K2
60 #define PGLCS_REG_DBG_SELECT                                                                         0x001d14UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
61 #define PGLCS_REG_DBG_DWORD_ENABLE                                                                   0x001d18UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
62 #define PGLCS_REG_DBG_SHIFT                                                                          0x001d1cUL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
63 #define PGLCS_REG_DBG_FORCE_VALID                                                                    0x001d20UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
64 #define PGLCS_REG_DBG_FORCE_FRAME                                                                    0x001d24UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
65 #define PGLCS_REG_PGL_CS                                                                             0x002000UL //Access:RW   DataWidth:0x20  Control and status interface for PCIE IP.  Chips: BB_A0 BB_B0 K2
66 #define PGLCS_REG_PGL_CS_SIZE                                                                        1024
67 #define PGLCS_REG_PGL_CS_VF_1                                                                        0x003000UL //Access:RW   DataWidth:0x20    Chips: K2
68 #define PGLCS_REG_PGL_CS_VF_1_SIZE                                                                   256
69 #define PGLCS_REG_PGL_CS_SHADOW                                                                      0x003400UL //Access:RW   DataWidth:0x20    Chips: K2
70 #define PGLCS_REG_PGL_CS_SHADOW_SIZE                                                                 128
71 #define PGLCS_REG_PGL_CS_SHADOW_VF                                                                   0x003600UL //Access:RW   DataWidth:0x20    Chips: K2
72 #define PGLCS_REG_PGL_CS_SHADOW_VF_SIZE                                                              128
73 #define PGLCS_REG_FIRST_VF_K2                                                                        0x003800UL //Access:RW   DataWidth:0x8   First VF  Chips: K2
74 #define PGLCS_REG_DISCARD_POISONED_MCTP_TGTWR_K2                                                     0x003804UL //Access:RW   DataWidth:0x2   Discard when poisoned  Chips: K2
75 #define PGLCS_REG_RX_HDR_ALMOST_FULL_THR_HIGH_K2                                                     0x003808UL //Access:RW   DataWidth:0x8   rx_hdr_almost_full_thr_high  Chips: K2
76 #define PGLCS_REG_RX_HDR_ALMOST_FULL_THR_LOW_K2                                                      0x00380cUL //Access:RW   DataWidth:0x8   rx_hdr_almost_full_thr_low  Chips: K2
77 #define PGLCS_REG_RX_DATA_ALMOST_FULL_THR_HIGH_K2                                                    0x003810UL //Access:RW   DataWidth:0x8   rx_data_almost_full_thr_high  Chips: K2
78 #define PGLCS_REG_RX_DATA_ALMOST_FULL_THR_LOW_K2                                                     0x003814UL //Access:RW   DataWidth:0x8   rx_data_almost_full_thr_low  Chips: K2
79 #define PGLCS_REG_STATISTIC_MASK_K2                                                                  0x003818UL //Access:RW   DataWidth:0x6   Statistic mask enable Bit5 :  Mask Message VDM Bit4 :  Mask memory read Bit3 :  Mask memory write Bit2 :  Mask Completion Bit1 :  Mask TX Bit0 :  Mask RX  Chips: K2
80 #define PGLCS_REG_RX_TLP_NUM_K2                                                                      0x00381cUL //Access:R    DataWidth:0x20  Number of RX tlp  are received  Chips: K2
81 #define PGLCS_REG_RX_TLP_BYTE_NUM_K2                                                                 0x003820UL //Access:R    DataWidth:0x20  Byte number of RX are received  Chips: K2
82 #define PGLCS_REG_TX_TLP_NUM_K2                                                                      0x003824UL //Access:R    DataWidth:0x20  tx number of tlp  sent  Chips: K2
83 #define PGLCS_REG_TX_TLP_BYTE_NUM                                                                    0x003828UL //Access:R    DataWidth:0x20  byte number of tlp sent  Chips: K2
84 #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_K2                                                        0x000000UL //Access:RW   DataWidth:0x20  Device ID and Vendor ID Register.  Chips: K2
85     #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID                                   (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
86     #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_SHIFT                             0
87     #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID                                   (0xffff<<16) // Device ID. Vendor Assigned Device Identifier.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
88     #define PCIEIP_REG_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_SHIFT                             16
89 #define PCIEIP_REG_DEVICE_VENDOR_ID_BB_A0                                                            0x000000UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
90 #define PCIEIP_REG_DEVICE_VENDOR_ID_BB_B0                                                            0x000000UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
91     #define PCIEIP_REG_DEVICE_VENDOR_ID_VENDOR_ID                                                    (0xffff<<0) // This register identifies the PCI adapter. This value can be written by firmware through the PCIE private register space VENDOR_ID to modify this read value to the host. Path = i_cfg_func.i_cfg_private
92     #define PCIEIP_REG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT                                              0
93     #define PCIEIP_REG_DEVICE_VENDOR_ID_DEVICE_ID                                                    (0xffff<<16) // This register identifies the device on the PCIE adapter. This value can be written by firmware through the PCIE private register space DEVICE_ID, which modifes the value read by host. The default value reflects the value of DEVICE_ID in version.v or strap pins user_device_id depending on build options chosen by user. Path = i_cfg_func.i_cfg_private
94     #define PCIEIP_REG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT                                              16
95 #define PCIEIP_REG_STATUS_COMMAND_REG_K2                                                             0x000004UL //Access:RW   DataWidth:0x20  Command and Status Register.  Chips: K2
96     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN                                            (0x1<<0) // Enables IO Access Response.   You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
97     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_SHIFT                                      0
98     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN                                     (0x1<<1) // Enables Memory Access Response.   You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
99     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_SHIFT                               1
100     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN                                    (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests.
101     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_SHIFT                              2
102     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION                          (0x1<<3) // Special Cycle Enable.
103     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_SHIFT                    3
104     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE                                        (0x1<<4) // Memory Write and Invalidate.
105     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_SHIFT                                  4
106     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP                                 (0x1<<5) // VGA Palette Snoop.
107     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_SHIFT                           5
108     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN                                    (0x1<<6) // Controls Logging of Poisoned TLPs.
109     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_SHIFT                              6
110     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING                                    (0x1<<7) // IDSEL Stepping.
111     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_SHIFT                              7
112     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN                                           (0x1<<8) // Enables Error Reporting.
113     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_SHIFT                                     8
114     #define PCIEIP_REG_STATUS_COMMAND_REG_RSVDP_9                                                    (0x1<<9) // Reserved for future use.
115     #define PCIEIP_REG_STATUS_COMMAND_REG_RSVDP_9_SHIFT                                              9
116     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN                                           (0x1<<10) // Controls generation of interrupts by a function.
117     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_SHIFT                                     10
118     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_RESERV                                            (0x1f<<11) // Reserved.
119     #define PCIEIP_REG_STATUS_COMMAND_REG_PCI_TYPE_RESERV_SHIFT                                      11
120     #define PCIEIP_REG_STATUS_COMMAND_REG_UNUSED_0                                                   (0x1<<16) // reserved
121     #define PCIEIP_REG_STATUS_COMMAND_REG_UNUSED_0_SHIFT                                             16
122     #define PCIEIP_REG_STATUS_COMMAND_REG_RSVDP_17                                                   (0x3<<17) // Reserved for future use.
123     #define PCIEIP_REG_STATUS_COMMAND_REG_RSVDP_17_SHIFT                                             17
124     #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS                                                 (0x1<<19) // Emulation interrupt pending.
125     #define PCIEIP_REG_STATUS_COMMAND_REG_INT_STATUS_SHIFT                                           19
126     #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST                                                   (0x1<<20) // Extended Capability.
127     #define PCIEIP_REG_STATUS_COMMAND_REG_CAP_LIST_SHIFT                                             20
128     #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP                                             (0x1<<21) // PCI 66MHz Capability.
129     #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT                                       21
130     #define PCIEIP_REG_STATUS_COMMAND_REG_RSVDP_22                                                   (0x1<<22) // Reserved for future use.
131     #define PCIEIP_REG_STATUS_COMMAND_REG_RSVDP_22_SHIFT                                             22
132     #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP                                               (0x1<<23) // Fast Back to Back Transaction Capable and Enable.
133     #define PCIEIP_REG_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT                                         23
134     #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE                                                 (0x1<<24) // Controls poisoned Completion and Request error reporting.
135     #define PCIEIP_REG_STATUS_COMMAND_REG_MASTER_DPE_SHIFT                                           24
136     #define PCIEIP_REG_STATUS_COMMAND_REG_DEV_SEL_TIMING                                             (0x3<<25) // Device Select Timing.
137     #define PCIEIP_REG_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT                                       25
138     #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT                                      (0x1<<27) // Completer Abort Error.
139     #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT                                27
140     #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT                                          (0x1<<28) // Completer Abort received.
141     #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT                                    28
142     #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT                                          (0x1<<29) // Unsupported request completion status received.
143     #define PCIEIP_REG_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT                                    29
144     #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR                                           (0x1<<30) // Fatal or Non-Fatal Error Message sent by function.
145     #define PCIEIP_REG_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_SHIFT                                     30
146     #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR                                        (0x1<<31) // Poisoned TLP received by function.
147     #define PCIEIP_REG_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_SHIFT                                  31
148 #define PCIEIP_REG_STATUS_COMMAND_BB_A0                                                              0x000004UL //Access:RW   DataWidth:0x20  This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)  Chips: BB_A0
149 #define PCIEIP_REG_STATUS_COMMAND_BB_B0                                                              0x000004UL //Access:RW   DataWidth:0x20  This is the PCIE compliant status/command register (bits 31-16: status, bits 15-0: command)  Chips: BB_B0
150     #define PCIEIP_REG_STATUS_COMMAND_IO_SPACE                                                       (0x1<<0) // This bit indicates that the device does not support I/O space access because it is zero and can not be modified. IO transactions targeting this device return completion with UR status . Path = i_cfg_func.i_cfg_public.i_cfg_dec
151     #define PCIEIP_REG_STATUS_COMMAND_IO_SPACE_SHIFT                                                 0
152     #define PCIEIP_REG_STATUS_COMMAND_MEM_SPACE                                                      (0x1<<1) // This bit controls the enabling of the memory space. When disabled, memory transactions targeting this device return completion with UR status Path = i_cfg_func.i_cfg_public.i_cfg_dec
153     #define PCIEIP_REG_STATUS_COMMAND_MEM_SPACE_SHIFT                                                1
154     #define PCIEIP_REG_STATUS_COMMAND_BUS_MASTER                                                     (0x1<<2) // This bit controls the enabling of the bus master activity by this device. When low, it disables an Endpoint function from issuing memory or IO requests. Also disables the ability to issue MSI messages. Path = i_cfg_func.i_cfg_public.i_cfg_dec
155     #define PCIEIP_REG_STATUS_COMMAND_BUS_MASTER_SHIFT                                               2
156     #define PCIEIP_REG_STATUS_COMMAND_SPECIAL_CYCLES                                                 (0x1<<3) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
157     #define PCIEIP_REG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT                                           3
158     #define PCIEIP_REG_STATUS_COMMAND_MWI_CYCLES                                                     (0x1<<4) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
159     #define PCIEIP_REG_STATUS_COMMAND_MWI_CYCLES_SHIFT                                               4
160     #define PCIEIP_REG_STATUS_COMMAND_VGA_SNOOP                                                      (0x1<<5) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
161     #define PCIEIP_REG_STATUS_COMMAND_VGA_SNOOP_SHIFT                                                5
162     #define PCIEIP_REG_STATUS_COMMAND_PERR_ENA                                                       (0x1<<6) // This bit enables the write to the Master data parity error status bit. If this bit is cleared , the master data parity error status bit will never be set. Path = i_cfg_func.i_cfg_public.i_cfg_dec
163     #define PCIEIP_REG_STATUS_COMMAND_PERR_ENA_SHIFT                                                 6
164     #define PCIEIP_REG_STATUS_COMMAND_STEPPING                                                       (0x1<<7) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
165     #define PCIEIP_REG_STATUS_COMMAND_STEPPING_SHIFT                                                 7
166     #define PCIEIP_REG_STATUS_COMMAND_SERR_ENA                                                       (0x1<<8) // When set, this bit enables the non fatal and fatal errors detected by the function to be reported to the Root Complex. The function reports such errors to the Root Complex if it is enabled to do so either through this bit or though PCI express specific bits in DCR Path = i_cfg_func.i_cfg_public.i_cfg_dec
167     #define PCIEIP_REG_STATUS_COMMAND_SERR_ENA_SHIFT                                                 8
168     #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B                                                       (0x1<<9) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_dec
169     #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B_SHIFT                                                 9
170     #define PCIEIP_REG_STATUS_COMMAND_INT_DISABLE                                                    (0x1<<10) // When this bit is set, function is not permitted to generate IntX interrupt messages (de-asserted) regardless of any internal chip logic. Setting this bit has no effect on the INT_STATUS bit below. Writing this bit to '0' will un-mask the interrupt and let it run normally. Path = i_cfg_func.i_cfg_public.i_cfg_dec
171     #define PCIEIP_REG_STATUS_COMMAND_INT_DISABLE_SHIFT                                              10
172     #define PCIEIP_REG_STATUS_COMMAND_RESERVED                                                       (0x1f<<11) // These bits are reserved and tied low per the PCIE specification. Path = i_cfg_func.i_cfg_public.i_cfg_dec
173     #define PCIEIP_REG_STATUS_COMMAND_RESERVED_SHIFT                                                 11
174     #define PCIEIP_REG_STATUS_COMMAND_RESERVED1                                                      (0x7<<16) // These bits are reserved and tied low per the PCIE specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
175     #define PCIEIP_REG_STATUS_COMMAND_RESERVED1_SHIFT                                                16
176     #define PCIEIP_REG_STATUS_COMMAND_INT_STATUS                                                     (0x1<<19) // This bit indicates the internal interrupt request state (before being masked by INT_DISABLE. A '0' indicates that no interrupt is pending. A '1' indicates that there is an interrupt pending. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
177     #define PCIEIP_REG_STATUS_COMMAND_INT_STATUS_SHIFT                                               19
178     #define PCIEIP_REG_STATUS_COMMAND_CAP_LIST                                                       (0x1<<20) // This bit is tied high to indicate that the device supports a capability list. The list starts at address 0x40. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
179     #define PCIEIP_REG_STATUS_COMMAND_CAP_LIST_SHIFT                                                 20
180     #define PCIEIP_REG_STATUS_COMMAND_CAP_66MHZ                                                      (0x1<<21) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
181     #define PCIEIP_REG_STATUS_COMMAND_CAP_66MHZ_SHIFT                                                21
182     #define PCIEIP_REG_STATUS_COMMAND_RESERVED2                                                      (0x1<<22) // These bits are reserved and tied low per the PCI specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
183     #define PCIEIP_REG_STATUS_COMMAND_RESERVED2_SHIFT                                                22
184     #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B_CAP                                                   (0x1<<23) // Does not apply to PCIE. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
185     #define PCIEIP_REG_STATUS_COMMAND_FAST_B2B_CAP_SHIFT                                             23
186     #define PCIEIP_REG_STATUS_COMMAND_PRI_MSTR_PERR                                                  (0x1<<24) // The master data parity error bit is set by a requester if the parity error enable bit is set in its command register and either of the following 2 conditions occur. If the requester receives a poisoned completion if the requester poisons a write request If the parity Error enable bit is cleared , the master data parity error status bit is never set Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
187     #define PCIEIP_REG_STATUS_COMMAND_PRI_MSTR_PERR_SHIFT                                            24
188     #define PCIEIP_REG_STATUS_COMMAND_DEVSEL_TIMING                                                  (0x3<<25) // Does not apply to PCIE Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
189     #define PCIEIP_REG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT                                            25
190     #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_TGT_ABT                                                (0x1<<27) // This bit is set when a function acting as a completer terminates a request by issuing Completer abort completion status to the requester Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
191     #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_TGT_ABT_SHIFT                                          27
192     #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_TGT_ABT                                                (0x1<<28) // This bit is set when a requester receives a completion with completer abort completion status. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
193     #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_TGT_ABT_SHIFT                                          28
194     #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_MSTR_ABT                                               (0x1<<29) // This bit is set when a requester receives a completion with UR completion status Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
195     #define PCIEIP_REG_STATUS_COMMAND_PRI_RCV_MSTR_ABT_SHIFT                                         29
196     #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_SERR                                                   (0x1<<30) // This bit is set when a function sends an ERR_FATAL or ERR_NONFATAL message and the SERR enable bit in the command register is set Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
197     #define PCIEIP_REG_STATUS_COMMAND_PRI_SIG_SERR_SHIFT                                             30
198     #define PCIEIP_REG_STATUS_COMMAND_PRI_PAR_ERR                                                    (0x1<<31) // When this bit is set, it indicates that the function has received a poisoned TLP Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
199     #define PCIEIP_REG_STATUS_COMMAND_PRI_PAR_ERR_SHIFT                                              31
200 #define PCIEIP_REG_CLASS_CODE_REVISION_ID_K2                                                         0x000008UL //Access:RW   DataWidth:0x20  Class Code and Revision ID Register.  Chips: K2
201     #define PCIEIP_REG_CLASS_CODE_REVISION_ID_REVISION_ID                                            (0xff<<0) // Vendor chosen Revision ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
202     #define PCIEIP_REG_CLASS_CODE_REVISION_ID_REVISION_ID_SHIFT                                      0
203     #define PCIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE                                      (0xff<<8) // Class Code Programming Interface.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
204     #define PCIEIP_REG_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_SHIFT                                8
205     #define PCIEIP_REG_CLASS_CODE_REVISION_ID_SUBCLASS_CODE                                          (0xff<<16) // Subclass Code to represent Device Type.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
206     #define PCIEIP_REG_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_SHIFT                                    16
207     #define PCIEIP_REG_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE                                        (0xff<<24) // Base Class Code to represent Device Type.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
208     #define PCIEIP_REG_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_SHIFT                                  24
209 #define PCIEIP_REG_REV_ID_CLASS_CODE_BB_A0                                                           0x000008UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
210 #define PCIEIP_REG_REV_ID_CLASS_CODE_BB_B0                                                           0x000008UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
211     #define PCIEIP_REG_REV_ID_CLASS_CODE_REV_ID                                                      (0xff<<0) // This register identifies the revision of the PCI adapter. This value is written by firmware through the PCI register space REVISION_ID value to modify the read value to the host. The default value is provided by user_revision_id strap pins.
212     #define PCIEIP_REG_REV_ID_CLASS_CODE_REV_ID_SHIFT                                                0
213     #define PCIEIP_REG_REV_ID_CLASS_CODE_CLASS_CODE                                                  (0xffffff<<8) // The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specified in the PCI specification. This read value is controlled by the CLASS_CODE valid value in the PCI register space. The default value reflects the value of CLASS_CODE in version.v defined by user. Path = i_cfg_func.i_cfg_private
214     #define PCIEIP_REG_REV_ID_CLASS_CODE_CLASS_CODE_SHIFT                                            8
215 #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_K2                                   0x00000cUL //Access:RW   DataWidth:0x20  BIST, Header Type, Cache Line Size, and Latency Timer Registers.  Chips: K2
216     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE                  (0xff<<0) // Cache Line Size. Has no effect on PCIe device behavior.
217     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT            0
218     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER             (0xff<<8) // Does not apply to PCI Express.
219     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT       8
220     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE                      (0x7f<<16) // Specifies Header Type.
221     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT                16
222     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC                       (0x1<<23) // Specifies whether device is multifunction.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
223     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT                 23
224     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST                             (0xff<<24) // Optional for BIST support.
225     #define PCIEIP_REG_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_SHIFT                       24
226 #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BB_A0                                                0x00000cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
227 #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BB_B0                                                0x00000cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
228     #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE                                  (0xff<<0) // This field is implemented by PCIE device as a read/write field for legacy compatibility purposes. Path = i_cfg_func.i_cfg_public.i_cfg_dec
229     #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_CACHE_LINE_SIZE_SHIFT                            0
230     #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER                                    (0xff<<8) // This register does not apply to PCI express and must be hardwired to zero Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
231     #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_LATENCY_TIMER_SHIFT                              8
232     #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE                                      (0xff<<16) // The 8-bit Header Type register identifies both the layout of bytes 10h through 3Fh of the Configuration space, as well as whether this adapter contains multiple functions. A value of 0x80 indicates a multi function device (Type 0) using the format specified in the PCI specification, while a value of 0x0 indicates a single function Type 0 device. Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
233     #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_HEADER_TYPE_SHIFT                                16
234     #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BIST                                             (0xff<<24) // The 8-bit BIST register is used to initiate and report the results of any Built-In-Self-Test. This value can be written by firmware through the PCI register space BIST register to modify the read value to the host. Path = i_cfg_func.i_cfg_public.i_cfg_dec
235     #define PCIEIP_REG_HEADERTYPE_LAT_CACHELINESIZE_BIST_SHIFT                                       24
236 #define PCIEIP_REG_BAR0_REG_K2                                                                       0x000010UL //Access:RW   DataWidth:0x20  BAR0 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
237     #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO                                                          (0x1<<0) // BAR0 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
238     #define PCIEIP_REG_BAR0_REG_BAR0_MEM_IO_SHIFT                                                    0
239     #define PCIEIP_REG_BAR0_REG_BAR0_TYPE                                                            (0x3<<1) // BAR0 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
240     #define PCIEIP_REG_BAR0_REG_BAR0_TYPE_SHIFT                                                      1
241     #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH                                                        (0x1<<3) // BAR0 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
242     #define PCIEIP_REG_BAR0_REG_BAR0_PREFETCH_SHIFT                                                  3
243     #define PCIEIP_REG_BAR0_REG_BAR0_START                                                           (0xfffffff<<4) // BAR0 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
244     #define PCIEIP_REG_BAR0_REG_BAR0_START_SHIFT                                                     4
245 #define PCIEIP_REG_BAR_1_BB_A0                                                                       0x000010UL //Access:RW   DataWidth:0x20  The 32-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_2 to make a 64-bit address for supporting Dual Address cycles systems. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_A0
246 #define PCIEIP_REG_BAR_1_BB_B0                                                                       0x000010UL //Access:RW   DataWidth:0x20  The 32-bit BAR_1 register programs the base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_2 to make a 64-bit address for supporting Dual Address cycles systems. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_B0
247     #define PCIEIP_REG_BAR_1_MEM_SPACE                                                               (0x1<<0) // This bit indicates that BAR_1 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
248     #define PCIEIP_REG_BAR_1_MEM_SPACE_SHIFT                                                         0
249     #define PCIEIP_REG_BAR_1_SPACE_TYPE                                                              (0x3<<1) // These bits indicate that BAR_1 may be programmed to map this adapter to anywhere in the 64-bit address space. Path = i_cfg_func.i_cfg_private
250     #define PCIEIP_REG_BAR_1_SPACE_TYPE_SHIFT                                                        1
251     #define PCIEIP_REG_BAR_1_PREFETCH                                                                (0x1<<3) // This bit indicates that the area mapped by BAR_1 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register. Path = i_cfg_func.i_cfg_private
252     #define PCIEIP_REG_BAR_1_PREFETCH_SHIFT                                                          3
253     #define PCIEIP_REG_BAR_1_ADDRESS                                                                 (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_2 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR1_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
254     #define PCIEIP_REG_BAR_1_ADDRESS_SHIFT                                                           4
255 #define PCIEIP_REG_BAR1_REG_K2                                                                       0x000014UL //Access:RW   DataWidth:0x20  BAR1 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
256     #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO                                                          (0x1<<0) // BAR1 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
257     #define PCIEIP_REG_BAR1_REG_BAR1_MEM_IO_SHIFT                                                    0
258     #define PCIEIP_REG_BAR1_REG_BAR1_TYPE                                                            (0x3<<1) // BAR1 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
259     #define PCIEIP_REG_BAR1_REG_BAR1_TYPE_SHIFT                                                      1
260     #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH                                                        (0x1<<3) // BAR1 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
261     #define PCIEIP_REG_BAR1_REG_BAR1_PREFETCH_SHIFT                                                  3
262     #define PCIEIP_REG_BAR1_REG_BAR1_START                                                           (0xfffffff<<4) // BAR1 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
263     #define PCIEIP_REG_BAR1_REG_BAR1_START_SHIFT                                                     4
264 #define PCIEIP_REG_BAR_2_BB_A0                                                                       0x000014UL //Access:RW   DataWidth:0x20  The 32-bit BAR_2 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_A0
265 #define PCIEIP_REG_BAR_2_BB_B0                                                                       0x000014UL //Access:RW   DataWidth:0x20  The 32-bit BAR_2 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_B0
266 #define PCIEIP_REG_BAR2_REG_K2                                                                       0x000018UL //Access:RW   DataWidth:0x20  BAR2 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
267     #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO                                                          (0x1<<0) // BAR2 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
268     #define PCIEIP_REG_BAR2_REG_BAR2_MEM_IO_SHIFT                                                    0
269     #define PCIEIP_REG_BAR2_REG_BAR2_TYPE                                                            (0x3<<1) // BAR2 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
270     #define PCIEIP_REG_BAR2_REG_BAR2_TYPE_SHIFT                                                      1
271     #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH                                                        (0x1<<3) // BAR2 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
272     #define PCIEIP_REG_BAR2_REG_BAR2_PREFETCH_SHIFT                                                  3
273     #define PCIEIP_REG_BAR2_REG_BAR2_START                                                           (0xfffffff<<4) // BAR2 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
274     #define PCIEIP_REG_BAR2_REG_BAR2_START_SHIFT                                                     4
275 #define PCIEIP_REG_BAR_3_BB_A0                                                                       0x000018UL //Access:RW   DataWidth:0x20  The 32-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_4 to make a 64-bit address for supporting Dual Address cycles systems.  Chips: BB_A0
276 #define PCIEIP_REG_BAR_3_BB_B0                                                                       0x000018UL //Access:RW   DataWidth:0x20  The 32-bit BAR_3 register programs the 2nd base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_4 to make a 64-bit address for supporting Dual Address cycles systems.  Chips: BB_B0
277     #define PCIEIP_REG_BAR_3_MEM_SPACE                                                               (0x1<<0) // This bit indicates that BAR_2 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
278     #define PCIEIP_REG_BAR_3_MEM_SPACE_SHIFT                                                         0
279     #define PCIEIP_REG_BAR_3_SPACE_TYPE                                                              (0x3<<1) // These bits indicate that BAR_2 may be programmed to map this adapter to anywhere in the 64-bit address space. Path = i_cfg_func.i_cfg_private
280     #define PCIEIP_REG_BAR_3_SPACE_TYPE_SHIFT                                                        1
281     #define PCIEIP_REG_BAR_3_PREFETCH                                                                (0x1<<3) // This bit indicates that the area mapped by BAR_2 may be pre-fetched or cached by the system without side effects. Path = i_cfg_func.i_cfg_private
282     #define PCIEIP_REG_BAR_3_PREFETCH_SHIFT                                                          3
283     #define PCIEIP_REG_BAR_3_ADDRESS                                                                 (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_4 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR2_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
284     #define PCIEIP_REG_BAR_3_ADDRESS_SHIFT                                                           4
285 #define PCIEIP_REG_BAR3_REG_K2                                                                       0x00001cUL //Access:RW   DataWidth:0x20  BAR3 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
286     #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO                                                          (0x1<<0) // BAR3 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
287     #define PCIEIP_REG_BAR3_REG_BAR3_MEM_IO_SHIFT                                                    0
288     #define PCIEIP_REG_BAR3_REG_BAR3_TYPE                                                            (0x3<<1) // BAR3 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
289     #define PCIEIP_REG_BAR3_REG_BAR3_TYPE_SHIFT                                                      1
290     #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH                                                        (0x1<<3) // BAR3 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
291     #define PCIEIP_REG_BAR3_REG_BAR3_PREFETCH_SHIFT                                                  3
292     #define PCIEIP_REG_BAR3_REG_BAR3_START                                                           (0xfffffff<<4) // BAR3 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
293     #define PCIEIP_REG_BAR3_REG_BAR3_START_SHIFT                                                     4
294 #define PCIEIP_REG_BAR_4_BB_A0                                                                       0x00001cUL //Access:RW   DataWidth:0x20  The 32-bit BAR_4 register programs the upper half of the 2nd base address for the memory space mapped by the card onto the PCI bus. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_A0
295 #define PCIEIP_REG_BAR_4_BB_B0                                                                       0x00001cUL //Access:RW   DataWidth:0x20  The 32-bit BAR_4 register programs the upper half of the 2nd base address for the memory space mapped by the card onto the PCI bus. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_B0
296 #define PCIEIP_REG_BAR4_REG_K2                                                                       0x000020UL //Access:RW   DataWidth:0x20  BAR4 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
297     #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO                                                          (0x1<<0) // BAR4 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
298     #define PCIEIP_REG_BAR4_REG_BAR4_MEM_IO_SHIFT                                                    0
299     #define PCIEIP_REG_BAR4_REG_BAR4_TYPE                                                            (0x3<<1) // BAR4 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
300     #define PCIEIP_REG_BAR4_REG_BAR4_TYPE_SHIFT                                                      1
301     #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH                                                        (0x1<<3) // BAR4 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
302     #define PCIEIP_REG_BAR4_REG_BAR4_PREFETCH_SHIFT                                                  3
303     #define PCIEIP_REG_BAR4_REG_BAR4_START                                                           (0xfffffff<<4) // BAR4 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
304     #define PCIEIP_REG_BAR4_REG_BAR4_START_SHIFT                                                     4
305 #define PCIEIP_REG_BAR_5_BB_A0                                                                       0x000020UL //Access:RW   DataWidth:0x20  The 32-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_4 to make a 64-bit address for supporting Dual Address cycles systems. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_A0
306 #define PCIEIP_REG_BAR_5_BB_B0                                                                       0x000020UL //Access:RW   DataWidth:0x20  The 32-bit BAR_5 register programs the 3rd base address for the memory space mapped by the card onto the PCI bus. This register can be combined with BAR_4 to make a 64-bit address for supporting Dual Address cycles systems. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_B0
307     #define PCIEIP_REG_BAR_5_MEM_SPACE                                                               (0x1<<0) // This bit indicates that BAR_3 maps a memory space and is always read as 0. Path = i_cfg_func.i_cfg_private
308     #define PCIEIP_REG_BAR_5_MEM_SPACE_SHIFT                                                         0
309     #define PCIEIP_REG_BAR_5_SPACE_TYPE                                                              (0x3<<1) // These bits indicate that BAR_3 may be programmed to map this adapter to anywhere in the 64-bit address space. Path = i_cfg_func.i_cfg_private
310     #define PCIEIP_REG_BAR_5_SPACE_TYPE_SHIFT                                                        1
311     #define PCIEIP_REG_BAR_5_PREFETCH                                                                (0x1<<3) // This bit indicates that the area mapped by BAR_3 may be pre-fetched or cached by the system without side effects. Path = i_cfg_func.i_cfg_private
312     #define PCIEIP_REG_BAR_5_PREFETCH_SHIFT                                                          3
313     #define PCIEIP_REG_BAR_5_ADDRESS                                                                 (0xfffffff<<4) // These bits set the address within a 32-bit address space that will be card will respond in. These bits may be combined with the bits in BAR_6 to create a full 64 bit address decode. Only the bits that address blocks bigger than the setting in the BAR3_SIZE value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
314     #define PCIEIP_REG_BAR_5_ADDRESS_SHIFT                                                           4
315 #define PCIEIP_REG_BAR5_REG_K2                                                                       0x000024UL //Access:RW   DataWidth:0x20  BAR5 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
316     #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO                                                          (0x1<<0) // BAR5 Memory Space Indicator.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
317     #define PCIEIP_REG_BAR5_REG_BAR5_MEM_IO_SHIFT                                                    0
318     #define PCIEIP_REG_BAR5_REG_BAR5_TYPE                                                            (0x3<<1) // BAR5 32-bit or 64-bit.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
319     #define PCIEIP_REG_BAR5_REG_BAR5_TYPE_SHIFT                                                      1
320     #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH                                                        (0x1<<3) // BAR5 Prefetchable.   Note: The access attributes of this field are as follows:  - Dbi: if (BAR_ENABLED == 1) then (if [DBI_RO_WR_EN == 1] then R/W else R) else RO
321     #define PCIEIP_REG_BAR5_REG_BAR5_PREFETCH_SHIFT                                                  3
322     #define PCIEIP_REG_BAR5_REG_BAR5_START                                                           (0xfffffff<<4) // BAR5 Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W if enabled else R
323     #define PCIEIP_REG_BAR5_REG_BAR5_START_SHIFT                                                     4
324 #define PCIEIP_REG_BAR_6_BB_A0                                                                       0x000024UL //Access:RW   DataWidth:0x20  The 32-bit BAR_4 register programs the upper half of the 3nd base address for the memory space mapped by the card onto the PCI bus.  Chips: BB_A0
325 #define PCIEIP_REG_BAR_6_BB_B0                                                                       0x000024UL //Access:RW   DataWidth:0x20  The 32-bit BAR_4 register programs the upper half of the 3nd base address for the memory space mapped by the card onto the PCI bus.  Chips: BB_B0
326 #define PCIEIP_REG_CARDBUS_CIS_PTR_REG_K2                                                            0x000028UL //Access:RW   DataWidth:0x20  CardBus CIS Pointer Register.  Chips: K2
327 #define PCIEIP_REG_CARDBUS_CIS_BB_A0                                                                 0x000028UL //Access:R    DataWidth:0x20  This register is not supported. Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux  Chips: BB_A0
328 #define PCIEIP_REG_CARDBUS_CIS_BB_B0                                                                 0x000028UL //Access:R    DataWidth:0x20  This register is not supported. Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux  Chips: BB_B0
329 #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_K2                                           0x00002cUL //Access:RW   DataWidth:0x20  Subsystem ID and Subsystem Vendor ID Register.  Chips: K2
330     #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID                         (0xffff<<0) // Subsystem Vendor ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
331     #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_SHIFT                   0
332     #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID                            (0xffff<<16) // Subsystem Device ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
333     #define PCIEIP_REG_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_SHIFT                      16
334 #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_BB_A0                                                      0x00002cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
335 #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_BB_B0                                                      0x00002cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
336     #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_VENDOR_ID                                    (0xffff<<0) // The 16-bit Subsystem Vendor ID register is used by the adapter manufacturer for identification. This value can be written by firmware through the PCI register space SUBSYSTEM_VENDOR_ID value to modify the read value to the host. Path = i_cfg_func.i_cfg_private
337     #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT                              0
338     #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_ID                                           (0xffff<<16) // The 16-bit Subsystem ID register is used by the adapter manufacturer for identification. This value can be written by firmware through the PCI register space SUBSYSTEM_ID value to modify the read value to the host. Default values are the same as the DEVICE_ID register. Path = i_cfg_func.i_cfg_private
339     #define PCIEIP_REG_SUBSYSTEM_ID_VENDOR_ID_SUBSYSTEM_ID_SHIFT                                     16
340 #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_K2                                                          0x000030UL //Access:RW   DataWidth:0x20  Expansion ROM BAR and Mask Register.  The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
341     #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE                                          (0x1<<0) // Expansion ROM Enable.   Note: The access attributes of this field are as follows:  - Dbi: R
342     #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_ROM_BAR_ENABLE_SHIFT                                    0
343     #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_RSVDP_1                                                 (0x3ff<<1) // Reserved for future use.
344     #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_RSVDP_1_SHIFT                                           1
345     #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS                                    (0x1fffff<<11) // Expansion ROM Base Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W
346     #define PCIEIP_REG_EXP_ROM_BASE_ADDR_REG_EXP_ROM_BASE_ADDRESS_SHIFT                              11
347 #define PCIEIP_REG_EXP_ROM_BAR_BB_A0                                                                 0x000030UL //Access:RW   DataWidth:0x20  The 32-bit Expansion ROM BAR register programs the base address for the memory space mapped by the chip for use as the expansion ROM. For more information on the operation of Expansion ROM, see the Theory of Ops specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg  Chips: BB_A0
348 #define PCIEIP_REG_EXP_ROM_BAR_BB_B0                                                                 0x000030UL //Access:RW   DataWidth:0x20  The 32-bit Expansion ROM BAR register programs the base address for the memory space mapped by the chip for use as the expansion ROM. For more information on the operation of Expansion ROM, see the Theory of Ops specification. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg  Chips: BB_B0
349     #define PCIEIP_REG_EXP_ROM_BAR_BAR_ENA                                                           (0x1<<0) // This bit indicates that the Expansion ROM BAR is valid when set to one. If it is zero, the expansion BAR should not be programmed or used. This bit will only be RW if it is enabled by the EXP_ROM_ENA bit which defaults to 0. Path = i_cfg_func.i_cfg_private
350     #define PCIEIP_REG_EXP_ROM_BAR_BAR_ENA_SHIFT                                                     0
351     #define PCIEIP_REG_EXP_ROM_BAR_LOW                                                               (0x3ff<<1) // These bits indicate that the Expansion ROM area is at least 2k bytes. They always read as zero. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
352     #define PCIEIP_REG_EXP_ROM_BAR_LOW_SHIFT                                                         1
353     #define PCIEIP_REG_EXP_ROM_BAR_SIZE                                                              (0x1fff<<11) // These bits indicate the size of the Expansion ROM area or the address of it. The boundary form RO bits to RW bits is controlled by the EXP_ROM_SIZE bits. Path = i_cfg_func.i_cfg_private
354     #define PCIEIP_REG_EXP_ROM_BAR_SIZE_SHIFT                                                        11
355     #define PCIEIP_REG_EXP_ROM_BAR_ADDRESS                                                           (0xff<<24) // These bits indicate the address of the Expansion ROM area.
356     #define PCIEIP_REG_EXP_ROM_BAR_ADDRESS_SHIFT                                                     24
357 #define PCIEIP_REG_PCI_CAP_PTR_REG_K2                                                                0x000034UL //Access:RW   DataWidth:0x20  Capability Pointer Register.  Chips: K2
358     #define PCIEIP_REG_PCI_CAP_PTR_REG_CAP_POINTER                                                   (0xff<<0) // Pointer to first item in the PCI Capability Structure.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
359     #define PCIEIP_REG_PCI_CAP_PTR_REG_CAP_POINTER_SHIFT                                             0
360     #define PCIEIP_REG_PCI_CAP_PTR_REG_RSVDP_8                                                       (0xffffff<<8) // Reserved for future use.
361     #define PCIEIP_REG_PCI_CAP_PTR_REG_RSVDP_8_SHIFT                                                 8
362 #define PCIEIP_REG_CAP_POINTER_BB_A0                                                                 0x000034UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
363 #define PCIEIP_REG_CAP_POINTER_BB_B0                                                                 0x000034UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
364     #define PCIEIP_REG_CAP_POINTER_CAP_POINTER                                                       (0xff<<0) // The 8-bit Capabilities Pointer register specifies an offset in the PCI address space of a linked list of new capabilities. The capabilities are PCI-X, PCI Power Management, Vital Product Data (VPD), and Message Signaled Interrupts (MSI) is supported. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
365     #define PCIEIP_REG_CAP_POINTER_CAP_POINTER_SHIFT                                                 0
366 #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_K2                         0x00003cUL //Access:RW   DataWidth:0x20  Interrupt Line and Pin Register.  Chips: K2
367     #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE               (0xff<<0) // PCI Compatible Interrupt Line Routing Register Field.
368     #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_SHIFT         0
369     #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN                (0xff<<8) // PCI Compatible Interrupt Pin Register Field.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
370     #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_SHIFT          8
371     #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16               (0xffff<<16) // Reserved for future use.
372     #define PCIEIP_REG_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_SHIFT         16
373 #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_BB_A0                                              0x00003cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
374 #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_BB_B0                                              0x00003cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
375     #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_LINE                                       (0xff<<0) // The 8-bit Interrupt Line register is used to communicate interrupt line routing information. This field is set by the host and later used by any driver which needs to know which physical interrupt on the system interrupt controller is assigned to this device. Path = i_cfg_func.i_cfg_private
376     #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_LINE_SHIFT                                 0
377     #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_PIN                                        (0xff<<8) // The 8-bit Interrupt Pin register is used to indicate which interrupt pin the device uses. Path = i_cfg_multi
378     #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_INT_PIN_SHIFT                                  8
379     #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MIN_GRANT                                      (0xff<<16) // Hardwired to zero Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
380     #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MIN_GRANT_SHIFT                                16
381     #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MAXIMUM_LATENCY                                (0xff<<24) // Hardwired to zero Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
382     #define PCIEIP_REG_LAT_MIN_GRANT_INT_PIN_INT_LINE_MAXIMUM_LATENCY_SHIFT                          24
383 #define PCIEIP_REG_CAP_ID_NXT_PTR_REG                                                                0x000040UL //Access:RW   DataWidth:0x20  Power Management Capabilities Register.  Chips: K2
384     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_CAP_ID                                                  (0xff<<0) // Power Management Capability ID.
385     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_CAP_ID_SHIFT                                            0
386     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER                                            (0xff<<8) // Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
387     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_NEXT_POINTER_SHIFT                                      8
388     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_SPEC_VER                                                (0x7<<16) // Power Management Spec Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
389     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PM_SPEC_VER_SHIFT                                          16
390     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK                                                    (0x1<<19) // PCI Clock Requirement.
391     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_CLK_SHIFT                                              19
392     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO                                    (0x1<<20) // Immediate Readiness on Return to D0.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
393     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_IMM_READI_RETURN_DO_SHIFT                              20
394     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI                                                        (0x1<<21) // Device Specific Initialization Bit.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
395     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_DSI_SHIFT                                                  21
396     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_AUX_CURR                                                   (0x7<<22) // Auxiliary Current Requirements.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
397     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_AUX_CURR_SHIFT                                             22
398     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT                                                 (0x1<<25) // D1 State Support.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
399     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D1_SUPPORT_SHIFT                                           25
400     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT                                                 (0x1<<26) // D2 State Support.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
401     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_D2_SUPPORT_SHIFT                                           26
402     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_SUPPORT                                                (0x1f<<27) // Power Management Event Support.   The read value from this field is the write value && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where D1_SUPPORT and D2_SUPPORT are fields in this register.  The reset value PME_SUPPORT_n && {sys_aux_pwr_det, 1'b1, D2_SUPPORT, D1_SUPPORT, 1'b1}, where PME_SUPPORT_n is a configuration parameter.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
403     #define PCIEIP_REG_CAP_ID_NXT_PTR_REG_PME_SUPPORT_SHIFT                                          27
404 #define PCIEIP_REG_CON_STATUS_REG                                                                    0x000044UL //Access:RW   DataWidth:0x20  Power Management Control and Status Register.  Chips: K2
405     #define PCIEIP_REG_CON_STATUS_REG_POWER_STATE                                                    (0x3<<0) // Power State.   You can write to this register. However, the read-back value is the actual power state, not the write value.  Note: The access attributes of this field are as follows:  - Dbi: R/W
406     #define PCIEIP_REG_CON_STATUS_REG_POWER_STATE_SHIFT                                              0
407     #define PCIEIP_REG_CON_STATUS_REG_RSVDP_2                                                        (0x1<<2) // Reserved for future use.
408     #define PCIEIP_REG_CON_STATUS_REG_RSVDP_2_SHIFT                                                  2
409     #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST                                                    (0x1<<3) // No soft Reset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
410     #define PCIEIP_REG_CON_STATUS_REG_NO_SOFT_RST_SHIFT                                              3
411     #define PCIEIP_REG_CON_STATUS_REG_RSVDP_4                                                        (0xf<<4) // Reserved for future use.
412     #define PCIEIP_REG_CON_STATUS_REG_RSVDP_4_SHIFT                                                  4
413     #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE                                                     (0x1<<8) // PME Enable.   The PMC registers this value under aux power. Sometimes it might remember the old value, even if you try to clear it by writing '0'.  Note: This register field is sticky.
414     #define PCIEIP_REG_CON_STATUS_REG_PME_ENABLE_SHIFT                                               8
415     #define PCIEIP_REG_CON_STATUS_REG_DATA_SELECT                                                    (0xf<<9) // Data Select.
416     #define PCIEIP_REG_CON_STATUS_REG_DATA_SELECT_SHIFT                                              9
417     #define PCIEIP_REG_CON_STATUS_REG_DATA_SCALE                                                     (0x3<<13) // Data Scaling Factor.
418     #define PCIEIP_REG_CON_STATUS_REG_DATA_SCALE_SHIFT                                               13
419     #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS                                                     (0x1<<15) // PME Status.
420     #define PCIEIP_REG_CON_STATUS_REG_PME_STATUS_SHIFT                                               15
421     #define PCIEIP_REG_CON_STATUS_REG_RSVDP_16                                                       (0x3f<<16) // Reserved for future use.
422     #define PCIEIP_REG_CON_STATUS_REG_RSVDP_16_SHIFT                                                 16
423     #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT                                                  (0x1<<22) // B2B3 Support for D3hot.
424     #define PCIEIP_REG_CON_STATUS_REG_B2_B3_SUPPORT_SHIFT                                            22
425     #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN                                             (0x1<<23) // Bus Power/Clock Control Enable.
426     #define PCIEIP_REG_CON_STATUS_REG_BUS_PWR_CLK_CON_EN_SHIFT                                       23
427     #define PCIEIP_REG_CON_STATUS_REG_DATA_REG_ADD_INFO                                              (0xff<<24) // Power Data Information Register.
428     #define PCIEIP_REG_CON_STATUS_REG_DATA_REG_ADD_INFO_SHIFT                                        24
429 #define PCIEIP_REG_PM_CAP                                                                            0x000048UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
430     #define PCIEIP_REG_PM_CAP_PM_CAP_ID                                                              (0xff<<0) // The 8-bit Power Management Capability ID is set to 1 to indicate that the next 8 bytes are a Power Management capability block. Hardwired to 1. Path = cfg_defs
431     #define PCIEIP_REG_PM_CAP_PM_CAP_ID_SHIFT                                                        0
432     #define PCIEIP_REG_PM_CAP_PM_NEXT_CAP_PTR                                                        (0xff<<8) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
433     #define PCIEIP_REG_PM_CAP_PM_NEXT_CAP_PTR_SHIFT                                                  8
434     #define PCIEIP_REG_PM_CAP_VERSION                                                                (0x3<<16) // These bits indicate that this device complies with revision 1.2 of the PCI Power Management Interface Specification. Bit is programmable through register space. Path = i_cfg_func.i_cfg_private
435     #define PCIEIP_REG_PM_CAP_VERSION_SHIFT                                                          16
436     #define PCIEIP_REG_PM_CAP_UNUSED0                                                                (0x1<<18) //
437     #define PCIEIP_REG_PM_CAP_UNUSED0_SHIFT                                                          18
438     #define PCIEIP_REG_PM_CAP_CLOCK                                                                  (0x1<<19) // This bit indicates that the device relies on the presence of the PCI clock for PME# operation. This chip does not require the PCI clock to generate PME#, therefore this bit is hardwired to '0'. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
439     #define PCIEIP_REG_PM_CAP_CLOCK_SHIFT                                                            19
440     #define PCIEIP_REG_PM_CAP_RESERVED                                                               (0x1<<20) // Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
441     #define PCIEIP_REG_PM_CAP_RESERVED_SHIFT                                                         20
442     #define PCIEIP_REG_PM_CAP_DSI                                                                    (0x1<<21) // This bit indicates that the device requires a specific initialization (DSI) sequence following a transition to the D0 un-initialized state. This device does not need this support, so the bit is hardwired to '0'. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
443     #define PCIEIP_REG_PM_CAP_DSI_SHIFT                                                              21
444     #define PCIEIP_REG_PM_CAP_AUX_CURRENT                                                            (0x7<<22) // These bits report the 3.3Vaux auxiliary current requirements for the device. This chip uses the Data Register feature for this so this field is hardwired to '0'. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
445     #define PCIEIP_REG_PM_CAP_AUX_CURRENT_SHIFT                                                      22
446     #define PCIEIP_REG_PM_CAP_D1_SUPPORT                                                             (0x1<<25) // This bit indicates whether the device supports the D1 power management state. This bit is controlled by the D1_SUPPORT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
447     #define PCIEIP_REG_PM_CAP_D1_SUPPORT_SHIFT                                                       25
448     #define PCIEIP_REG_PM_CAP_D2_SUPPORT                                                             (0x1<<26) // This bit indicates whether the device supports the D2 power management state. This bit is controlled by the D2_SUPPORT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
449     #define PCIEIP_REG_PM_CAP_D2_SUPPORT_SHIFT                                                       26
450     #define PCIEIP_REG_PM_CAP_PME_IN_D0                                                              (0x1<<27) // This bit indicates whether the device supports transmiting PME message from the D0 power state. This bit is controlled by the PME_IN_D0 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
451     #define PCIEIP_REG_PM_CAP_PME_IN_D0_SHIFT                                                        27
452     #define PCIEIP_REG_PM_CAP_PME_IN_D1                                                              (0x1<<28) // This bit indicates whether the device supports transmiting PME message from the D1 power state. This bit is controlled by the PME_IN_D1 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
453     #define PCIEIP_REG_PM_CAP_PME_IN_D1_SHIFT                                                        28
454     #define PCIEIP_REG_PM_CAP_PME_IN_D2                                                              (0x1<<29) // This bit indicates whether the device supports transmiting PME message from the D2 power state. This bit is controlled by the PME_IN_D2 bit in the PCI register space. Path = i_cfg_func.i_cfg_private
455     #define PCIEIP_REG_PM_CAP_PME_IN_D2_SHIFT                                                        29
456     #define PCIEIP_REG_PM_CAP_PME_IN_D3_HOT                                                          (0x1<<30) // This bit indicates whether the device supports transmiting PME message from the D3hot power state. This bit is controlled by the PME_IN_D3_HOT bit in the PCI register space. Path = i_cfg_func.i_cfg_private
457     #define PCIEIP_REG_PM_CAP_PME_IN_D3_HOT_SHIFT                                                    30
458     #define PCIEIP_REG_PM_CAP_PME_IN_D3_COLD                                                         (0x1<<31) // This bit indicates whether the device supports transmiting PME message from the D3cold power state. This is supported if the VAUX_PRESENT input pin is high. This bit reflects the input value of the VAUX_PRESENT input pin. Path = input pins to pcie_vaux
459     #define PCIEIP_REG_PM_CAP_PME_IN_D3_COLD_SHIFT                                                   31
460 #define PCIEIP_REG_PM_CSR                                                                            0x00004cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
461     #define PCIEIP_REG_PM_CSR_STATE                                                                  (0x3<<0) // These bits may be used by the system to set the power state. The register is implemented as two banks of two bits each. Can be written from both configuration space and from the PCI register space as the PM_STATE bits. When written from the PCI bus, only values of 0 and 3 will be accepted. This is the register returned on reads of this register from configuration space. The second bank catches all writes values. The value of the second register is returned when the PM_STATE bits are read from register space. The idea of these registers is to a) Provide compatible operation to 5701 b) Allow implementation of other power states though firmware. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
462     #define PCIEIP_REG_PM_CSR_STATE_SHIFT                                                            0
463     #define PCIEIP_REG_PM_CSR_RESERVED0                                                              (0x1<<2) // Reserved Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
464     #define PCIEIP_REG_PM_CSR_RESERVED0_SHIFT                                                        2
465     #define PCIEIP_REG_PM_CSR_NO_SOFT_RESET                                                          (0x1<<3) // When device transitions from D3 to D0, device does not perform an internal reset. This bit can be programmed through reg space Path = i_cfg_func.i_cfg_private
466     #define PCIEIP_REG_PM_CSR_NO_SOFT_RESET_SHIFT                                                    3
467     #define PCIEIP_REG_PM_CSR_RESERVED1                                                              (0xf<<4) // Reserved Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
468     #define PCIEIP_REG_PM_CSR_RESERVED1_SHIFT                                                        4
469     #define PCIEIP_REG_PM_CSR_PME_ENABLE                                                             (0x1<<8) // This bit enables the device to transmit PME messages. On HARD reset, this bit resets to '1'. this bit is sticky and is not modified by PERST_B. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
470     #define PCIEIP_REG_PM_CSR_PME_ENABLE_SHIFT                                                       8
471     #define PCIEIP_REG_PM_CSR_DATA_SEL                                                               (0xf<<9) // These bits select which data is to be reported through the pm_data register. (Offset 0x4f) Select values other than those listed cause the pm_data register to return zero. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
472     #define PCIEIP_REG_PM_CSR_DATA_SEL_SHIFT                                                         9
473     #define PCIEIP_REG_PM_CSR_DATA_SCALE                                                             (0x3<<13) // These bits indicate the scaling factor to be used when interpreting the values in the PM data register. The hardware default value for this field is 0x1, but this value can be written by firmware through the PCI register space (SCALE_PRG) to modify the read value to the host. Path = i_cfg_func.i_cfg_private
474     #define PCIEIP_REG_PM_CSR_DATA_SCALE_SHIFT                                                       13
475     #define PCIEIP_REG_PM_CSR_PME_STATUS                                                             (0x1<<15) // This bit is set when a PME is asserted from the MAC or RX Parser blocks, regardless of the state of the PME_ENABLE bit. If both this bit and the PME_ENABLE bit are high, then the PME output will be asserted low. This bit is cleared by writing a 1 in this bit position. At power-up, the chip must clear this bit, but on assertions of PCI_RST# after that, this bit is sticky and not modified. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap
476     #define PCIEIP_REG_PM_CSR_PME_STATUS_SHIFT                                                       15
477     #define PCIEIP_REG_PM_CSR_PM_CSR_BSE                                                             (0xff<<16) // This register (PMCSR PCI to PCI Bridge Support Extensions) is not supported and always reads as zero. Path = i_cfg_func.i_cfg_public.i_cfg_rd_mux
478     #define PCIEIP_REG_PM_CSR_PM_CSR_BSE_SHIFT                                                       16
479     #define PCIEIP_REG_PM_CSR_PM_DATA                                                                (0xff<<24) // The value for this register is selected from one of eight values by the DATA_SEL bits of the PM_CSR register. The reset value of all 9 of the register values is zero. These values can be written by firmware through the PCI register space (PM_Data_0_prg to PM_Data_8_prg) to modify the read values to the host. Path = i_cfg_func.i_cfg_public.i_cfg_pw_cap (for pm_data_select) Path = i_cfg_func.i_cfg_private (pm_data)
480     #define PCIEIP_REG_PM_CSR_PM_DATA_SHIFT                                                          24
481 #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_K2                                                   0x000050UL //Access:RW   DataWidth:0x20  MSI Capability ID, Next Pointer, Capability/Control Registers.  Chips: K2
482     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID                                   (0xff<<0) // MSI Capability ID.
483     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_ID_SHIFT                             0
484     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET                          (0xff<<8) // MSI Capability Next Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
485     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_CAP_NEXT_OFFSET_SHIFT                    8
486     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE                                   (0x1<<16) // MSI Enable.
487     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_ENABLE_SHIFT                             16
488     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP                         (0x7<<17) // MSI Multiple Message Capable.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
489     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_CAP_SHIFT                   17
490     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN                          (0x7<<20) // MSI Multiple Message Enable.
491     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_MULTIPLE_MSG_EN_SHIFT                    20
492     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP                          (0x1<<23) // MSI 64-bit Address Capable.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
493     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_MSI_64_BIT_ADDR_CAP_SHIFT                    23
494     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT                                  (0x1<<24) // MSI Per Vector Masking Capable.
495     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_PCI_PVM_SUPPORT_SHIFT                            24
496     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_25                                         (0x7f<<25) // Reserved for future use.
497     #define PCIEIP_REG_PCI_MSI_CAP_ID_NEXT_CTRL_REG_RSVDP_25_SHIFT                                   25
498 #define PCIEIP_REG_VPD_CAP_BB_A0                                                                     0x000050UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
499 #define PCIEIP_REG_VPD_CAP_BB_B0                                                                     0x000050UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
500     #define PCIEIP_REG_VPD_CAP_VPD_CAP_ID                                                            (0xff<<0) // The 8-bit VPD Capability ID is set to 3 to indicate that the next 8 bytes are a Vital Product Data capability block. Path = cfg_defs
501     #define PCIEIP_REG_VPD_CAP_VPD_CAP_ID_SHIFT                                                      0
502     #define PCIEIP_REG_VPD_CAP_VPD_NEXT_CAP_PTR                                                      (0xff<<8) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
503     #define PCIEIP_REG_VPD_CAP_VPD_NEXT_CAP_PTR_SHIFT                                                8
504     #define PCIEIP_REG_VPD_CAP_UNUSED0                                                               (0x3<<16) //
505     #define PCIEIP_REG_VPD_CAP_UNUSED0_SHIFT                                                         16
506     #define PCIEIP_REG_VPD_CAP_ADDRESS                                                               (0x1fff<<18) // This value is the 32-bit word address of the VPD value being accessed in the vpd_data register. Since the data register is 32-bits wide. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap
507     #define PCIEIP_REG_VPD_CAP_ADDRESS_SHIFT                                                         18
508     #define PCIEIP_REG_VPD_CAP_FLAG                                                                  (0x1<<31) // This bit is used to control passing of data between the vpd_data register and Non-Volatile memory. To read a value, this bit is written as zero when the address is written. When the data is available to read, this bit will read as a one. To write data, this bit must written as a one when the address is written. When the bit reads as a zero the write has completed. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap
509     #define PCIEIP_REG_VPD_CAP_FLAG_SHIFT                                                            31
510 #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_K2                                                            0x000054UL //Access:RW   DataWidth:0x20  MSI Message Lower Address Register.  Chips: K2
511     #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_RSVDP_0                                                   (0x3<<0) // Reserved for future use.
512     #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_RSVDP_0_SHIFT                                             0
513     #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H                                       (0x3fffffff<<2) // MSI Message Lower Address Field.   Note: The access attributes of this field are as follows:  - Dbi: R/W
514     #define PCIEIP_REG_MSI_CAP_OFF_04H_REG_PCI_MSI_CAP_OFF_04H_SHIFT                                 2
515 #define PCIEIP_REG_VPD_DATA_BB_A0                                                                    0x000054UL //Access:RW   DataWidth:0x20  This is the VPD data transfer register. See the instructions for the FLAG bit above for usage of this register. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap  Chips: BB_A0
516 #define PCIEIP_REG_VPD_DATA_BB_B0                                                                    0x000054UL //Access:RW   DataWidth:0x20  This is the VPD data transfer register. See the instructions for the FLAG bit above for usage of this register. Path = i_cfg_func.i_cfg_public.i_cfg_vpd_cap  Chips: BB_B0
517 #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_K2                                                            0x000058UL //Access:RW   DataWidth:0x20  For a 32 bit MSI Message, this register contains Data. For 64 bit it contains the Upper Address.  Chips: K2
518     #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H                                       (0xffff<<0) // For a 32-bit MSI Message, this field contains Data. For 64-bit it contains lower 16 bits of the Upper Address.   Note: The access attributes of this field are as follows:  - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R
519     #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_08H_SHIFT                                 0
520     #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH                                       (0xffff<<16) // For a 32 bit MSI Message, this is reserved. For 64-bit it contains upper 16 bits of the Upper Address.  Note: The access attributes of this field are as follows:  - Dbi: PCI_MSI_64_BIT_ADDR_CAP ? R/W : R
521     #define PCIEIP_REG_MSI_CAP_OFF_08H_REG_PCI_MSI_CAP_OFF_0AH_SHIFT                                 16
522 #define PCIEIP_REG_MSI_CAP_BB_A0                                                                     0x000058UL //Access:RW   DataWidth:0x20  The device driver is prohibited from writing to this register.  Chips: BB_A0
523 #define PCIEIP_REG_MSI_CAP_BB_B0                                                                     0x000058UL //Access:RW   DataWidth:0x20  The device driver is prohibited from writing to this register.  Chips: BB_B0
524     #define PCIEIP_REG_MSI_CAP_MSI_CAP_ID                                                            (0xff<<0) // The 8-bit MSI Capability ID is set to 5 to indicate that the next 8 bytes are a Message Signaled Interrupt capability block. Path = cfg_defs
525     #define PCIEIP_REG_MSI_CAP_MSI_CAP_ID_SHIFT                                                      0
526     #define PCIEIP_REG_MSI_CAP_MSI_NEXT_CAP_PTR                                                      (0xff<<8) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
527     #define PCIEIP_REG_MSI_CAP_MSI_NEXT_CAP_PTR_SHIFT                                                8
528     #define PCIEIP_REG_MSI_CAP_MSI_ENABLE                                                            (0x1<<16) // When this bit is set, the chip will generate MSI cycles to indicate interrupts instead of asserting the INTA# pin. When this bit is zero, the INTA# pin will be used. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
529     #define PCIEIP_REG_MSI_CAP_MSI_ENABLE_SHIFT                                                      16
530     #define PCIEIP_REG_MSI_CAP_MULTI_MSG_CAP                                                         (0x7<<17) // These bits indicate the number of messages that the chip is capable of generating. This value comes from the Path = i_cfg_func.i_cfg_private MULTI_MSG_CAP bit in the register space.
531     #define PCIEIP_REG_MSI_CAP_MULTI_MSG_CAP_SHIFT                                                   17
532     #define PCIEIP_REG_MSI_CAP_MULTI_MSG_EN                                                          (0x7<<20) // These bits indicate the number of message that the chip is configured (allowed) to generate. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
533     #define PCIEIP_REG_MSI_CAP_MULTI_MSG_EN_SHIFT                                                    20
534     #define PCIEIP_REG_MSI_CAP_CAP_64BIT                                                             (0x1<<23) // This bit indicates that the chip is capable of generating 64 bit MSI messages. Path = cfg_defs
535     #define PCIEIP_REG_MSI_CAP_CAP_64BIT_SHIFT                                                       23
536     #define PCIEIP_REG_MSI_CAP_MSI_PVMASK_CAPABLE                                                    (0x1<<24) // This bit indicates if the function supports per vector masking. This value comes from the MSI_PV_MASK_CAP bit in the register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
537     #define PCIEIP_REG_MSI_CAP_MSI_PVMASK_CAPABLE_SHIFT                                              24
538 #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_K2                                                            0x00005cUL //Access:RW   DataWidth:0x20  For a 64 bit MSI Message, this register contains Data. For 32 bit, it contains Mask Bits if PVM enabled.  Chips: K2
539     #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH                                       (0xffff<<0) // For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the lower Mask Bits if PVM is enabled.  Note: The access attributes of this field are as follows:  - Dbi: PCI_MSI_64_BIT_ADDR_CAP || MSI_PVM_EN ? R/W : R
540     #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0CH_SHIFT                                 0
541     #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH                                       (0xffff<<16) // For a 64-bit MSI Message, this field contains Data. For 32-bit, it contains the upper Mask Bits if PVM is enabled.  Note: The access attributes of this field are as follows:  - Dbi: !PCI_MSI_64_BIT_ADDR_CAP && MSI_PVM_EN ? R/W : R
542     #define PCIEIP_REG_MSI_CAP_OFF_0CH_REG_PCI_MSI_CAP_OFF_0EH_SHIFT                                 16
543 #define PCIEIP_REG_MSI_ADDR_L_BB_A0                                                                  0x00005cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
544 #define PCIEIP_REG_MSI_ADDR_L_BB_B0                                                                  0x00005cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
545     #define PCIEIP_REG_MSI_ADDR_L_UNUSED0                                                            (0x3<<0) //
546     #define PCIEIP_REG_MSI_ADDR_L_UNUSED0_SHIFT                                                      0
547     #define PCIEIP_REG_MSI_ADDR_L_VAL                                                                (0x3fffffff<<2) // This register controls the lower half of the address of the MSI message that are generated. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
548     #define PCIEIP_REG_MSI_ADDR_L_VAL_SHIFT                                                          2
549 #define PCIEIP_REG_MSI_CAP_OFF_10H_REG_K2                                                            0x000060UL //Access:RW   DataWidth:0x20  Used for MSI when Vector Masking Capable. For 32 bit contains Pending Bits. For 64 bit, contains Mask Bits.  Chips: K2
550 #define PCIEIP_REG_MSI_ADDR_H_BB_A0                                                                  0x000060UL //Access:RW   DataWidth:0x20  This register controls the upper half of the address of the MSI message that are generated. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap  Chips: BB_A0
551 #define PCIEIP_REG_MSI_ADDR_H_BB_B0                                                                  0x000060UL //Access:RW   DataWidth:0x20  This register controls the upper half of the address of the MSI message that are generated. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap  Chips: BB_B0
552 #define PCIEIP_REG_MSI_CAP_OFF_14H_REG_K2                                                            0x000064UL //Access:R    DataWidth:0x20  Used for MSI 64 bit messaging when Vector Masking Capable. Contains Pending Bits.  Chips: K2
553 #define PCIEIP_REG_MSI_DATA_BB_A0                                                                    0x000064UL //Access:RW   DataWidth:0x20  This register controls the data value that will be presented on the lower 16 bits of the data bus during MSI messages. The MENA value from the MSI Control register allows a specific number of the lower bits (up to 6) to be modified to indicate different interrupt conditions. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap  Chips: BB_A0
554 #define PCIEIP_REG_MSI_DATA_BB_B0                                                                    0x000064UL //Access:RW   DataWidth:0x20  This register controls the data value that will be presented on the lower 16 bits of the data bus during MSI messages. The MENA value from the MSI Control register allows a specific number of the lower bits (up to 6) to be modified to indicate different interrupt conditions. This register is readable in the pci register space. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap  Chips: BB_B0
555     #define PCIEIP_REG_MSI_DATA_MSI_DATA                                                             (0xffff<<0) //
556     #define PCIEIP_REG_MSI_DATA_MSI_DATA_SHIFT                                                       0
557 #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG                                        0x000070UL //Access:RW   DataWidth:0x20  PCI Express Capabilities, ID, Next Pointer Register.  Chips: K2
558     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID                        (0xff<<0) // PCIE Capability ID.
559     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT                  0
560     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR                  (0xff<<8) // PCIE Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
561     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT            8
562     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG                       (0xf<<16) // PCIE Capability Version Number.
563     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT                 16
564     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE                 (0xf<<20) // PCIE Device/PortType.
565     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT           20
566     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP                      (0x1<<24) // PCIe Slot Implemented Valid.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
567     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT                24
568     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM                   (0x1f<<25) // PCIE Interrupt Message Number.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
569     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT             25
570     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD                               (0x1<<30) // Reserved.
571     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT                         30
572     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31                           (0x1<<31) // Reserved for future use.
573     #define PCIEIP_REG_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SHIFT                     31
574 #define PCIEIP_REG_DEVICE_CAPABILITIES_REG                                                           0x000074UL //Access:RW   DataWidth:0x20  Device Capabilities Register.  Chips: K2
575     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE                             (0x7<<0) // Max Payload Size Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
576     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT                       0
577     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT                         (0x3<<3) // Phantom Functions Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
578     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT                   3
579     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP                                 (0x1<<5) // Extended Tag Field Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
580     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT                           5
581     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY                         (0x7<<6) // Applies to endpoints only L0s acceptable latency.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
582     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_SHIFT                   6
583     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY                          (0x7<<9) // Applies to endpoints only L1 acceptable latency.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
584     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_SHIFT                    9
585     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_RSVDP_12                                              (0x7<<12) // Reserved for future use.
586     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_RSVDP_12_SHIFT                                        12
587     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT                        (0x1<<15) // Role-based Error Reporting Implemented.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
588     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT                  15
589     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_RSVDP_16                                              (0x3<<16) // Reserved for future use.
590     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_RSVDP_16_SHIFT                                        16
591     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE                       (0xff<<18) // Captured Slot Power Limit Value.
592     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_SHIFT                 18
593     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE                       (0x3<<26) // Captured Slot Power Limit Scale.
594     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_SHIFT                 26
595     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP                                      (0x1<<28) // Function Level Reset Capability (endpoints only).   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
596     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_SHIFT                                28
597     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_RSVDP_29                                              (0x7<<29) // Reserved for future use.
598     #define PCIEIP_REG_DEVICE_CAPABILITIES_REG_RSVDP_29_SHIFT                                        29
599 #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS                                                      0x000078UL //Access:RW   DataWidth:0x20  Device Control and Status Register.  Chips: K2
600     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN                      (0x1<<0) // Correctable Error Reporting Enable.
601     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT                0
602     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN                 (0x1<<1) // Non-fatal Error Reporting Enable.
603     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT           1
604     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN                     (0x1<<2) // Fatal Error Reporting Enable.
605     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT               2
606     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN                    (0x1<<3) // Unsupported Request Reporting Enable.
607     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT              3
608     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER                            (0x1<<4) // Enable Relaxed Ordering.
609     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT                      4
610     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS                     (0x7<<5) // Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG).
611     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT               5
612     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN                              (0x1<<8) // Extended Tag Field Enable.   The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
613     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT                        8
614     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN                         (0x1<<9) // Phantom Functions Enable.   The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
615     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SHIFT                   9
616     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN                         (0x1<<10) // Aux Power PM Enable.   This bit is derived by sampling the sys_aux_pwr_det input.  Note: This register field is sticky.
617     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT                   10
618     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP                             (0x1<<11) // Enable No Snoop.   Note: The access attributes of this field are as follows:  - Dbi: R
619     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT                       11
620     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE                       (0x7<<12) // Max Read Request Size.
621     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT                 12
622     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR                            (0x1<<15) // Initiate Function Level Reset (for endpoints).
623     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT                      15
624     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED                       (0x1<<16) // Correctable Error Detected Status.
625     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT                 16
626     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED                  (0x1<<17) // Non-Fatal Error Detected Status.
627     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT            17
628     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED                      (0x1<<18) // Fatal Error Detected Status.
629     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT                18
630     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED                (0x1<<19) // Unsupported Request Detected Status.
631     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT          19
632     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED                      (0x1<<20) // Aux Power Detected Status.   This bit is derived by sampling the sys_aux_pwr_det input.
633     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT                20
634     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING                           (0x1<<21) // Transactions Pending Status.
635     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT                     21
636     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22                                         (0x3ff<<22) // Reserved for future use.
637     #define PCIEIP_REG_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SHIFT                                   22
638 #define PCIEIP_REG_LINK_CAPABILITIES_REG                                                             0x00007cUL //Access:RW   DataWidth:0x20  Link Capabilities Register.  Chips: K2
639     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED                                 (0xf<<0) // Maximum Link Speed.   In M-PCIe mode, the reset and dynamic values of this field are calculated by the core.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
640     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT                           0
641     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH                                 (0x3f<<4) // Maximum Link Width.   In M-PCIe mode, the reset and dynamic values of this field are calculated by the core.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
642     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT                           4
643     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT                   (0x3<<10) // Level of ASPM (Active State Power Management) Support.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
644     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT             10
645     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY                               (0x7<<12) // LOs Exit Latency.  There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
646     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT                         12
647     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY                                (0x7<<15) // L1 Exit Latency.  There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
648     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT                          15
649     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN                                (0x1<<18) // Clock Power Management.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
650     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT                          18
651     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP                      (0x1<<19) // Surprise Down Error Reporting Capable.
652     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT                19
653     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP                             (0x1<<20) // Data Link Layer Link Active Reporting Capable.
654     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT                       20
655     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP                                (0x1<<21) // Link Bandwidth Notification Capable.
656     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT                          21
657     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE                            (0x1<<22) // ASPM Optionality Compliance.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
658     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT                      22
659     #define PCIEIP_REG_LINK_CAPABILITIES_REG_RSVDP_23                                                (0x1<<23) // Reserved for future use.
660     #define PCIEIP_REG_LINK_CAPABILITIES_REG_RSVDP_23_SHIFT                                          23
661     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM                                       (0xff<<24) // Port Number.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
662     #define PCIEIP_REG_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT                                 24
663 #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG                                                      0x000080UL //Access:RW   DataWidth:0x20  Link Control and Status Register.  Chips: K2
664     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL            (0x3<<0) // Active State Power Management (ASPM) Control.
665     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT      0
666     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2                                          (0x1<<2) // Reserved for future use.
667     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SHIFT                                    2
668     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB                                     (0x1<<3) // Read Completion Boundary (RCB).  Note: The access attributes of this field are as follows:  - Dbi: R/W
669     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT                               3
670     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE                            (0x1<<4) // Initiate Link Disable.   In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.  Note: The access attributes of this field are as follows:  - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
671     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT                      4
672     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK                            (0x1<<5) // Initiate Link Retrain.   Note: The access attributes of this field are as follows:  - Dbi: see description
673     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT                      5
674     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG                       (0x1<<6) // Common Clock Configuration.
675     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT                 6
676     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH                          (0x1<<7) // Extended Synch.
677     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT                    7
678     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN                        (0x1<<8) // Enable Clock Power Management.   The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS  Note: This register field is sticky.
679     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT                  8
680     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE                   (0x1<<9) // Hardware Autonomous Width Disable.   Note: The access attributes of this field are as follows:  - Dbi: R/W
681     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT             9
682     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN                      (0x1<<10) // Link Bandwidth Management Interrupt Enable.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
683     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT                10
684     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN                     (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
685     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT               11
686     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12                                         (0x3<<12) // Reserved for future use.
687     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SHIFT                                   12
688     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL                   (0x3<<14) // DRS Signaling Control.
689     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT             14
690     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED                              (0xf<<16) // Current Link Speed.
691     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT                        16
692     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH                         (0x3f<<20) // Negotiated Link Width.
693     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT                   20
694     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26                                         (0x1<<26) // Reserved for future use.
695     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SHIFT                                   26
696     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING                           (0x1<<27) // LTSSM is in Configuration or Recovery State.   Note: The access attributes of this field are as follows:  - Dbi: R
697     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT                     27
698     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG                         (0x1<<28) // Slot Clock Configuration.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
699     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT                   28
700     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE                              (0x1<<29) // Data Link Layer Active.
701     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT                        29
702     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS                      (0x1<<30) // Link Bandwidth Management Status.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
703     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT                30
704     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS                     (0x1<<31) // Link Autonomous Bandwidth Status.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
705     #define PCIEIP_REG_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT               31
706 #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG                                                          0x000094UL //Access:R    DataWidth:0x20  Device Capabilities 2 Register.  Chips: K2
707     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE                           (0xf<<0) // Completion Timeout Ranges Supported.
708     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT                     0
709     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT                 (0x1<<4) // Completion Timeout Disable Supported.
710     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT           4
711     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT                         (0x1<<5) // ARI Forwarding Supported.
712     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT                   5
713     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP                         (0x1<<6) // Atomic Operation Routing Supported.
714     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT                   6
715     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP                          (0x1<<7) // 32 Bit AtomicOp Completer Supported.
716     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT                    7
717     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP                          (0x1<<8) // 64 Bit AtomicOp Completer Supported.
718     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT                    8
719     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP                            (0x1<<9) // 128 Bit CAS Completer Supported.
720     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT                      9
721     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR                          (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
722     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT                    10
723     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP                                    (0x1<<11) // LTR Mechanism Supported.
724     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT                              11
725     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0                         (0x1<<12) // TPH Completer Supported Bit 0.
726     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT                   12
727     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1                         (0x1<<13) // TPH Completer Supported Bit 1.
728     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT                   13
729     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_RSVDP_14                                             (0xf<<14) // Reserved for future use.
730     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_RSVDP_14_SHIFT                                       14
731     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT                                (0x3<<18) // (OBFF) Optimized Buffer Flush/fill Supported.
732     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_SHIFT                          18
733     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_UNUSED_0                                             (0xf<<20) // reserved
734     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_UNUSED_0_SHIFT                                       20
735     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_RSVDP_24                                             (0x7f<<24) // Reserved for future use.
736     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_RSVDP_24_SHIFT                                       24
737     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_UNUSED_1                                             (0x1<<31) // reserved
738     #define PCIEIP_REG_DEVICE_CAPABILITIES2_REG_UNUSED_1_SHIFT                                       31
739 #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG                                                0x000098UL //Access:RW   DataWidth:0x20  Device Control 2 and Status 2 Register.  Chips: K2
740     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE                 (0xf<<0) // Completion Timeout Value.   Note: The access attributes of this field are as follows:  - Dbi: R/W
741     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT           0
742     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE               (0x1<<4) // Completion Timeout Disable.
743     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT         4
744     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS            (0x1<<5) // ARI Forwarding Enable.
745     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT      5
746     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN                     (0x1<<6) // AtomicOp Requester Enable. Reflected on the cfg_atomic_req_en output.
747     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_SHIFT               6
748     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK                 (0x1<<7) // AtomicOp Egress Blocking. Reflected on the cfg_atomic_egress_block output.
749     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_SHIFT           7
750     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN                        (0x1<<8) // IDO Request Enable.
751     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_SHIFT                  8
752     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN                        (0x1<<9) // IDO Completion Enable.
753     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_SHIFT                  9
754     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN                            (0x1<<10) // LTR Mechanism Enable.   The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.  Note: RW for function #0 and RsdvP for all other functions
755     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SHIFT                      10
756     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_UNUSED_0                                   (0x3<<11) // reserved
757     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_UNUSED_0_SHIFT                             11
758     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN                           (0x3<<13) // OBFF Enable.   Note: RW for function #0 and RsdvP for all other functions  Note: The access attributes of this field are as follows:  - Dbi: R/W
759     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_SHIFT                     13
760     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_UNUSED_1                                   (0x1ffff<<15) // reserved
761     #define PCIEIP_REG_DEVICE_CONTROL2_DEVICE_STATUS2_REG_UNUSED_1_SHIFT                             15
762 #define PCIEIP_REG_LINK_CAPABILITIES2_REG                                                            0x00009cUL //Access:RW   DataWidth:0x20  Link Capabilities 2 Register.  Chips: K2
763     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_RSVDP_0                                                (0x1<<0) // Reserved for future use.
764     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_RSVDP_0_SHIFT                                          0
765     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR                     (0x7f<<1) // Supported Link Speeds Vector.   This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.
766     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT               1
767     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT                            (0x1<<8) // Cross Link Supported.
768     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT                      8
769     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_RSVDP_9                                                (0x3fff<<9) // Reserved for future use.
770     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_RSVDP_9_SHIFT                                          9
771     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_UNUSED_0                                               (0x1<<23) // reserved
772     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_UNUSED_0_SHIFT                                         23
773     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_RSVDP_24                                               (0x7f<<24) // Reserved for future use.
774     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_RSVDP_24_SHIFT                                         24
775     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED                                          (0x1<<31) // DRS Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
776     #define PCIEIP_REG_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_SHIFT                                    31
777 #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_K2                                                 0x0000a0UL //Access:R    DataWidth:0x20  Link Control 2 and Status 2 Register.  Chips: K2
778     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_UNUSED_0                                       (0xffff<<0) // reserved
779     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_UNUSED_0_SHIFT                                 0
780     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS                       (0x1<<16) // Current De-emphasis Level.    In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE
781     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT                 16
782     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_UNUSED_1                                       (0x7ff<<17) // reserved
783     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_UNUSED_1_SHIFT                                 17
784     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE                      (0x7<<28) // Downstream Component Presence. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
785     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SHIFT                28
786     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED                           (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
787     #define PCIEIP_REG_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SHIFT                     31
788 #define PCIEIP_REG_MSIX_CAP_BB_A0                                                                    0x0000a0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
789 #define PCIEIP_REG_MSIX_CAP_BB_B0                                                                    0x0000a0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
790     #define PCIEIP_REG_MSIX_CAP_MSIX_CAP_ID                                                          (0xff<<0) // Capability ID for MSIX Path = cfg_defs
791     #define PCIEIP_REG_MSIX_CAP_MSIX_CAP_ID_SHIFT                                                    0
792     #define PCIEIP_REG_MSIX_CAP_MSIX_NEXT_CAP_PTR                                                    (0xff<<8) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
793     #define PCIEIP_REG_MSIX_CAP_MSIX_NEXT_CAP_PTR_SHIFT                                              8
794     #define PCIEIP_REG_MSIX_CAP_TABLE_SIZE                                                           (0x7ff<<16) // System sw reads this field to determine the MSI-X table size N, which is encoded as N-1 Path = i_cfg_func.i_cfg_private
795     #define PCIEIP_REG_MSIX_CAP_TABLE_SIZE_SHIFT                                                     16
796     #define PCIEIP_REG_MSIX_CAP_RESERVED                                                             (0x7<<27) // Reserved
797     #define PCIEIP_REG_MSIX_CAP_RESERVED_SHIFT                                                       27
798     #define PCIEIP_REG_MSIX_CAP_FUNC_MASK                                                            (0x1<<30) // If 1, all of the vectors associated with the function are masked regardless of their per vector Mask bit. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
799     #define PCIEIP_REG_MSIX_CAP_FUNC_MASK_SHIFT                                                      30
800     #define PCIEIP_REG_MSIX_CAP_MSIX_ENABLE                                                          (0x1<<31) // If 1, and the MSI enable bit in the MSI message control register is 0, the function is permitted to use MSIX request service and profited from using INTx# messages. Path = i_cfg_func.i_cfg_public.i_cfg_msi_cap
801     #define PCIEIP_REG_MSIX_CAP_MSIX_ENABLE_SHIFT                                                    31
802 #define PCIEIP_REG_MSIX_TBL_OFF_BIR                                                                  0x0000a4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
803     #define PCIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_BIR                                                    (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X table into memory space. Path = i_cfg_func.i_cfg_private
804     #define PCIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_BIR_SHIFT                                              0
805     #define PCIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_OFFSET                                                 (0x1fffffff<<3) // Path = i_cfg_func.i_cfg_private
806     #define PCIEIP_REG_MSIX_TBL_OFF_BIR_TABLE_OFFSET_SHIFT                                           3
807 #define PCIEIP_REG_MSIX_PBA_BIR_OFF                                                                  0x0000a8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
808     #define PCIEIP_REG_MSIX_PBA_BIR_OFF_PBA_BIR                                                      (0x7<<0) // Indicates which one of functions BAR is used to map MSI-X PBA into memory space. Path = i_cfg_func.i_cfg_private
809     #define PCIEIP_REG_MSIX_PBA_BIR_OFF_PBA_BIR_SHIFT                                                0
810     #define PCIEIP_REG_MSIX_PBA_BIR_OFF_PBA_OFFSET                                                   (0x1fffffff<<3) // Path = i_cfg_func.i_cfg_private
811     #define PCIEIP_REG_MSIX_PBA_BIR_OFF_PBA_OFFSET_SHIFT                                             3
812 #define PCIEIP_REG_PCIE_CAPABILITY                                                                   0x0000acUL //Access:R    DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap  Chips: BB_A0 BB_B0
813     #define PCIEIP_REG_PCIE_CAPABILITY_PCIE_CAP_ID                                                   (0xff<<0) // This register contains the PCIExpress Capability ID. Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
814     #define PCIEIP_REG_PCIE_CAPABILITY_PCIE_CAP_ID_SHIFT                                             0
815     #define PCIEIP_REG_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR                                             (0xff<<8) // This registers contains the pointer to the next PCI capability structure. Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
816     #define PCIEIP_REG_PCIE_CAPABILITY_PCIE_NEXT_CAP_PTR_SHIFT                                       8
817     #define PCIEIP_REG_PCIE_CAPABILITY_VER                                                           (0xf<<16) // Capability Version. PCI Express Capability structure version number. These bits are hardwired to 2h. Path= cfg_defs
818     #define PCIEIP_REG_PCIE_CAPABILITY_VER_SHIFT                                                     16
819     #define PCIEIP_REG_PCIE_CAPABILITY_TYPE                                                          (0xf<<20) // Device/Port Type. Device is an End Point. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
820     #define PCIEIP_REG_PCIE_CAPABILITY_TYPE_SHIFT                                                    20
821     #define PCIEIP_REG_PCIE_CAPABILITY_SLOT_IMPLEMENTED                                              (0x1<<24) // Slot Implemented. This register is not supported. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
822     #define PCIEIP_REG_PCIE_CAPABILITY_SLOT_IMPLEMENTED_SHIFT                                        24
823     #define PCIEIP_REG_PCIE_CAPABILITY_MSG_NUM                                                       (0x1f<<25) // Interrupt Message Number:indicate which MSI/MSI-X vector is used for the interrupt message generated in association with any of the status bits of this capability structure. For MSI, the value in this register indicates the offset between the base Message Data and the interrupt message that is generated. For MSI-X, the value in this register indicates which MSI-X Table entry is used to generate the interrupt message. The entry must be one of the first 32 entries even if the function implements more than 32 entries. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
824     #define PCIEIP_REG_PCIE_CAPABILITY_MSG_NUM_SHIFT                                                 25
825 #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_K2                                                  0x0000b0UL //Access:RW   DataWidth:0x20  MSI-X Capability ID, Next Pointer, Control Registers.  Chips: K2
826     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID                                 (0xff<<0) // MSI-X Capability ID.
827     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_SHIFT                           0
828     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET                        (0xff<<8) // MSI-X Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
829     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_SHIFT                  8
830     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE                             (0x7ff<<16) // MSI-X Table Size.   SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
831     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SHIFT                       16
832     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27                                        (0x7<<27) // Reserved for future use.
833     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SHIFT                                  27
834     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK                          (0x1<<30) // Function Mask.   Note: The access attributes of this field are as follows:  - Dbi: R/W
835     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_SHIFT                    30
836     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE                                 (0x1<<31) // MSI-X Enable.   Note: The access attributes of this field are as follows:  - Dbi: R/W
837     #define PCIEIP_REG_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_SHIFT                           31
838 #define PCIEIP_REG_DEVICE_CAPABILITY_BB_A0                                                           0x0000b0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
839 #define PCIEIP_REG_DEVICE_CAPABILITY_BB_B0                                                           0x0000b0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
840     #define PCIEIP_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED                                       (0x7<<0) // Max Payload Size Supported. These bits are programmable from the register space and default value is based on define in version.v file. Path= i_cfg_func.i_cfg_private
841     #define PCIEIP_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_SHIFT                                 0
842     #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED0                                                     (0x3<<3) //
843     #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED0_SHIFT                                               3
844     #define PCIEIP_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT                                        (0x1<<5) // Extended Tag Field Support. This bit is programmable through register space. Path= i_cfg_func.i_cfg_private
845     #define PCIEIP_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_SHIFT                                  5
846     #define PCIEIP_REG_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY                                      (0x7<<6) // Endpoint L0s Acceptable Latency. These bits are programmable through register space. The value should be 0 for root ports. Path= i_cfg_func.i_cfg_private
847     #define PCIEIP_REG_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_SHIFT                                6
848     #define PCIEIP_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY                                       (0x7<<9) // Endpoint L1 Acceptable Latency. These bits are programmable through register space. The bits should be 0 for Root ports Path= i_cfg_func.i_cfg_private
849     #define PCIEIP_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_SHIFT                                 9
850     #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED1                                                     (0x7<<12) //
851     #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED1_SHIFT                                               12
852     #define PCIEIP_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT                                          (0x1<<15) // Indicate device is conforming to the ECN, PCI Express Base Specification, Revision 1.1., or subsequent PCI Express Base Specification revisions Path= i_cfg_func.i_cfg_private
853     #define PCIEIP_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_SHIFT                                    15
854     #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED2                                                     (0x3<<16) //
855     #define PCIEIP_REG_DEVICE_CAPABILITY_UNUSED2_SHIFT                                               16
856     #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL                                       (0xff<<18) // Specifies the upper limit on power supplied by slot. It is set by the Set_Slot_Power_Limit Message. This field is not set for Root ports. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
857     #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_VAL_SHIFT                                 18
858     #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE                                     (0x3<<26) // Specifies the scale used for the Slot Power Limit Value. It is set by the Set_Slot_Power_Limit Message. This field is not set for Root ports Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
859     #define PCIEIP_REG_DEVICE_CAPABILITY_CAPTURED_SLOT_PWR_SCALE_SHIFT                               26
860     #define PCIEIP_REG_DEVICE_CAPABILITY_FLR_CAP_SUPPORTED                                           (0x1<<28) // FLR capability is advertized when flr_supported bit in private device_capability register space is set.
861     #define PCIEIP_REG_DEVICE_CAPABILITY_FLR_CAP_SUPPORTED_SHIFT                                     28
862 #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_K2                                                          0x0000b4UL //Access:RW   DataWidth:0x20  MSI-X Table Offset and BIR Register.  Chips: K2
863     #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR                                            (0x7<<0) // MSI-X Table Bar Indicator Register Field.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
864     #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SHIFT                                      0
865     #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET                                   (0x1fffffff<<3) // MSI-X Table Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
866     #define PCIEIP_REG_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SHIFT                             3
867 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_BB_A0                                                       0x0000b4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
868 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_BB_B0                                                       0x0000b4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
869     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN                                      (0x1<<0) // Correctable Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
870     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_REPORT_EN_SHIFT                                0
871     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN                                    (0x1<<1) // Non-Fatal Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
872     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NFATAL_ERR_REPORT_EN_SHIFT                              1
873     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN                                     (0x1<<2) // Fatal Error Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
874     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_REPORT_EN_SHIFT                               2
875     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN                                         (0x1<<3) // Unsupported Request Reporting Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
876     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_U_REQ_REPORT_EN_SHIFT                                   3
877     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE                                   (0x1<<4) // Relax Ordering Enable. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
878     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_RELAX_ORDERING_ENABLE_SHIFT                             4
879     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE                                        (0x7<<5) // Max Payload Size. Depending on the spec, internal logic uses either the min or the max of the value of the two functions. For ARI devices max payload size is determined solely by setting in Function 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
880     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT                                  5
881     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN                                         (0x1<<8) // Extended Tag Field Enable. This capability when set allows DUT to generate more than 32 tags. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
882     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_EN_SHIFT                                   8
883     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNUSED0                                                 (0x1<<9) //
884     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNUSED0_SHIFT                                           9
885     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA                                          (0x1<<10) // This bit when set enables device to draw aux power independent of PME AUX power Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
886     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_PM_ENA_SHIFT                                    10
887     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE                                         (0x1<<11) // Enable No Snoop. When this bit is set to 1, PCIE initiates a read request with the No Snoop bit in the attribute field set for the transactions that request the No Snoop attribute. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
888     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NO_SNOOP_ENABLE_SHIFT                                   11
889     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ                                        (0x7<<12) // Maximum Read Request Size. Depending on the spec, internal logic uses either the min or the max of the value of the two functions. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
890     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_MAX_READ_REQ_SIZ_SHIFT                                  12
891     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FLR_INITIATED                                           (0x1<<15) // Initiate Function Level reset. This bit is writeable only if flr_supported bit in private device_capability register is set. A write of 1 to this bit initiates Function Level Reset. The value read by s/w from this bit is always 0.
892     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FLR_INITIATED_SHIFT                                     15
893     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_DET                                            (0x1<<16) // Correctable Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
894     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_CORR_ERR_DET_SHIFT                                      16
895     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET                                       (0x1<<17) // Non-Fatal Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
896     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NON_FATAL_ERR_DET_SHIFT                                 17
897     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_DET                                           (0x1<<18) // Fatal Error Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
898     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_FATAL_ERR_DET_SHIFT                                     18
899     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET                                           (0x1<<19) // UnSupported Request Detected. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap.
900     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_UNSUP_REQ_DET_SHIFT                                     19
901     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_DET                                             (0x1<<20) // This bit is the current state of the VAUX_PRSNT pin of the device. When it is '1', it is indicating that part needs VAUX and detects the VAUX is present. Path= input to pcie_vaux_pipe
902     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_AUX_PWR_DET_SHIFT                                       20
903     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND                                     (0x1<<21) // This is bit is read back a 1, whenever a non-posted request initiated by PCIE core is pending to be completed. Path= i_tl_top
904     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_NP_TRANSACTION_PEND_SHIFT                               21
905 #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_K2                                                            0x0000b8UL //Access:RW   DataWidth:0x20  MSI-X PBA Offset and BIR Register.  Chips: K2
906     #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA                                              (0x7<<0) // MSI-X PBA BIR.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
907     #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_SHIFT                                        0
908     #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET                                       (0x1fffffff<<3) // MSI-X PBA Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
909     #define PCIEIP_REG_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SHIFT                                 3
910 #define PCIEIP_REG_LINK_CAPABILITY_BB_A0                                                             0x0000b8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
911 #define PCIEIP_REG_LINK_CAPABILITY_BB_B0                                                             0x0000b8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
912     #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_SPEED                                                (0xf<<0) // Path= i_cfg_func.i_cfg_private Value used by internal logic is the smaller of the value programmed for each function
913     #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT                                          0
914     #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_WIDTH                                                (0x3f<<4) // Maximum Link Width. These are programmable through reg space.Bit 9 is always 0 and is not programmable. Default value is based on numLanes field in version.v Path= i_cfg_func.i_cfg_private
915     #define PCIEIP_REG_LINK_CAPABILITY_MAX_LINK_WIDTH_SHIFT                                          4
916     #define PCIEIP_REG_LINK_CAPABILITY_ASPM_SUPT                                                     (0x3<<10) // ASPM Support. These bits are programmable through reg space. Path= i_cfg_func.i_cfg_private
917     #define PCIEIP_REG_LINK_CAPABILITY_ASPM_SUPT_SHIFT                                               10
918     #define PCIEIP_REG_LINK_CAPABILITY_L0S_EXIT_LAT                                                  (0x7<<12) // L0s Exit Latency. These bits are programmable through register space. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Depending on whether device is in common clock mode or not, the value reflected by these bits is one of the following.
919     #define PCIEIP_REG_LINK_CAPABILITY_L0S_EXIT_LAT_SHIFT                                            12
920     #define PCIEIP_REG_LINK_CAPABILITY_L1_EXIT_LAT                                                   (0x7<<15) // L1 Exit Latency. These bits are programmable through register space. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Depending on whether device is in common clock mode or not, the value reflected by these bits is one of the following.
921     #define PCIEIP_REG_LINK_CAPABILITY_L1_EXIT_LAT_SHIFT                                             15
922     #define PCIEIP_REG_LINK_CAPABILITY_CLK_PWR_MGMT                                                  (0x1<<18) // Clock Power Management. These bits are programmable through register. The feature itself has to be enabled in version.v Path= i_cfg_func.i_cfg_private
923     #define PCIEIP_REG_LINK_CAPABILITY_CLK_PWR_MGMT_SHIFT                                            18
924     #define PCIEIP_REG_LINK_CAPABILITY_SUR_DWN_ERR_REP                                               (0x1<<19) // Surprise Down Error Reporting Capable: RC: this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. RC: Not supported and hardwired to 0. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
925     #define PCIEIP_REG_LINK_CAPABILITY_SUR_DWN_ERR_REP_SHIFT                                         19
926     #define PCIEIP_REG_LINK_CAPABILITY_DL_ACTIVE_REP                                                 (0x1<<20) // Data Link Layer Link Active Reporting Capable: RC: this bit must be hardwired to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and Management State Machine. RC: Implemented (RW) for RC. Default to 0. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_private
927     #define PCIEIP_REG_LINK_CAPABILITY_DL_ACTIVE_REP_SHIFT                                           20
928     #define PCIEIP_REG_LINK_CAPABILITY_LINK_BW_NOTIFY                                                (0x1<<21) // Link Bandwidth Notification Capability: RC: A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting Links wider than x1 and/or multiple Link speeds. RC: Field is implemented. EP: Not supported and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
929     #define PCIEIP_REG_LINK_CAPABILITY_LINK_BW_NOTIFY_SHIFT                                          21
930     #define PCIEIP_REG_LINK_CAPABILITY_UNUSED0                                                       (0x3<<22) //
931     #define PCIEIP_REG_LINK_CAPABILITY_UNUSED0_SHIFT                                                 22
932     #define PCIEIP_REG_LINK_CAPABILITY_PORT_NUMBER                                                   (0xff<<24) // PCIE Port Number. These bits are programmable through register. Path= i_cfg_func.i_cfg_private
933     #define PCIEIP_REG_LINK_CAPABILITY_PORT_NUMBER_SHIFT                                             24
934 #define PCIEIP_REG_LINK_STATUS_CONTROL                                                               0x0000bcUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
935     #define PCIEIP_REG_LINK_STATUS_CONTROL_ASPM_CTRL                                                 (0x3<<0) // ASPM Control. Value used by logic is dependent on the value of this bit for each enabled function and also on the programmed powerstate of each function. For ARI devices, ASPM setting is determined solely by the setting in Function 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
936     #define PCIEIP_REG_LINK_STATUS_CONTROL_ASPM_CTRL_SHIFT                                           0
937     #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED0                                                   (0x1<<2) //
938     #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED0_SHIFT                                             2
939     #define PCIEIP_REG_LINK_STATUS_CONTROL_RCB                                                       (0x1<<3) // Read Completion Boundary. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
940     #define PCIEIP_REG_LINK_STATUS_CONTROL_RCB_SHIFT                                                 3
941     #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE                                      (0x1<<4) // Requesting PHY to disable the link. This bit is only applicable to RC. So for EP it is read only bit. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
942     #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_LINK_DISABLE_SHIFT                                4
943     #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK                                      (0x1<<5) // Requesting PHY to retrain the link. This bit is only applicable to RC. So for EP it is read only bit. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
944     #define PCIEIP_REG_LINK_STATUS_CONTROL_CFG_PSM_RETRAIN_LINK_SHIFT                                5
945     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK                                        (0x1<<6) // Common Clock Configuration. Value used by logic is resolved to 1 only if all functions (when enabled) have this bit set. For ARI devices, only Function 0 determines the value used. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
946     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_COMMON_CLK_SHIFT                                  6
947     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC                                          (0x1<<7) // Extended Synch. This bit when set forces the transmission of 4096 FTS ordered sets in the L0s state followed by a single SKP ordered set prior to entering the L0 state, and the transmission of 1024 TS1 ordered sets in the L1 state prior to entering the Recovery state. Value used by logic is resolved to 1 if either function has this bit set. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
948     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_CR_EXT_SYNC_SHIFT                                    7
949     #define PCIEIP_REG_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT                                            (0x1<<8) // Enable Clock Power Management: RC: N/A and hardwired to 0. EP: When this bit is set, the device is permitted to use CLKREQ# signal to power management. Feature is enabled through version.v define Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
950     #define PCIEIP_REG_LINK_STATUS_CONTROL_EN_CLK_PW_MGMT_SHIFT                                      8
951     #define PCIEIP_REG_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS                                         (0x1<<9) // Hardware Autonomous Width Disable: When Set, this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. Other functions are reserved. RC: Not applicable and hardwire to 0 EP: If supported, only apply to function0. Not implemented and hardwire to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
952     #define PCIEIP_REG_LINK_STATUS_CONTROL_HW_AUTO_WIDTH_DIS_SHIFT                                   9
953     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN                                       (0x1<<10) // Link Bandwidth Management Interrupt Enable: when Set, this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been Set. RC: N/A and hardwired to 0. EP: Not implemented and hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
954     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_MGMT_INT_EN_SHIFT                                 10
955     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_INT_EN                                            (0x1<<11) // Link Autonomous Bandwidth Interrupt Enable: When Set, this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been Set. RC: Not implemented and hardwired to 0. EP: N/A and hardwired to 0 Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
956     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_BW_INT_EN_SHIFT                                      11
957     #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED1                                                   (0xf<<12) //
958     #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED1_SHIFT                                             12
959     #define PCIEIP_REG_LINK_STATUS_CONTROL_NEG_LINK_SPEED                                            (0xf<<16) // Link Speed. These bits indicate the negotiated link speed of the PCI Express link. These bits are undefined if the link is not up (L0, L0s, L1). Path= i_pl_top.i_pl_ltssm
960     #define PCIEIP_REG_LINK_STATUS_CONTROL_NEG_LINK_SPEED_SHIFT                                      16
961     #define PCIEIP_REG_LINK_STATUS_CONTROL_NEG_LINK_WIDTH                                            (0x3f<<20) // Negotiated Link Width. These bits indicate the negotiated link width of the PCI Express link. Path= i_pl_top.i_pl_ltssm
962     #define PCIEIP_REG_LINK_STATUS_CONTROL_NEG_LINK_WIDTH_SHIFT                                      20
963     #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED2                                                   (0x1<<26) //
964     #define PCIEIP_REG_LINK_STATUS_CONTROL_UNUSED2_SHIFT                                             26
965     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_TRAINING                                             (0x1<<27) // EP: This bit is N/A and is hardwired to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
966     #define PCIEIP_REG_LINK_STATUS_CONTROL_LINK_TRAINING_SHIFT                                       27
967     #define PCIEIP_REG_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG                                           (0x1<<28) // Slot Clock configuration. This bit is read-only by host, but read/write via backdoor CS bus. Path= i_cfg_func.i_cfg_private
968     #define PCIEIP_REG_LINK_STATUS_CONTROL_SLOT_CLK_CONFIG_SHIFT                                     28
969     #define PCIEIP_REG_LINK_STATUS_CONTROL_DL_ACTIVE                                                 (0x1<<29) // Data Link Layer Link Active: returns a 1b to indicate the DL_Active state, 0b otherwise. Not implemented and hardwire to 0. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
970     #define PCIEIP_REG_LINK_STATUS_CONTROL_DL_ACTIVE_SHIFT                                           29
971 #define PCIEIP_REG_SLOT_CAPABILITY                                                                   0x0000c0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
972     #define PCIEIP_REG_SLOT_CAPABILITY_UNUSED_2                                                      (0x7f<<0) // Not implemented
973     #define PCIEIP_REG_SLOT_CAPABILITY_UNUSED_2_SHIFT                                                0
974     #define PCIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE                                        (0xff<<7) // Not implemented
975     #define PCIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_VALUE_SHIFT                                  7
976     #define PCIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE                                        (0x3<<15) // Not implemented
977     #define PCIEIP_REG_SLOT_CAPABILITY_SLOT_POWER_LIMIT_SCALE_SHIFT                                  15
978     #define PCIEIP_REG_SLOT_CAPABILITY_UNUSED                                                        (0x3<<17) // Not implemented
979     #define PCIEIP_REG_SLOT_CAPABILITY_UNUSED_SHIFT                                                  17
980     #define PCIEIP_REG_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER                                          (0x1fff<<19) // Not implemented
981     #define PCIEIP_REG_SLOT_CAPABILITY_PHYSICAL_SLOT_NUMBER_SHIFT                                    19
982 #define PCIEIP_REG_SLOT_CONTROL_STATUS                                                               0x0000c4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
983     #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_CONTROL                                              (0xffff<<0) // Not implemented
984     #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_CONTROL_SHIFT                                        0
985     #define PCIEIP_REG_SLOT_CONTROL_STATUS_UNUSED_1                                                  (0x3f<<16) // Not implemented
986     #define PCIEIP_REG_SLOT_CONTROL_STATUS_UNUSED_1_SHIFT                                            16
987     #define PCIEIP_REG_SLOT_CONTROL_STATUS_PRESENCE_DETECT                                           (0x1<<22) // Not implemented
988     #define PCIEIP_REG_SLOT_CONTROL_STATUS_PRESENCE_DETECT_SHIFT                                     22
989     #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_STATUS                                               (0x1ff<<23) // Not implemented
990     #define PCIEIP_REG_SLOT_CONTROL_STATUS_SLOT_STATUS_SHIFT                                         23
991 #define PCIEIP_REG_ROOT_CAP_CONTROL                                                                  0x0000c8UL //Access:R    DataWidth:0x20  For EP this register is not applicable and hardwired to 0.  Chips: BB_A0 BB_B0
992 #define PCIEIP_REG_ROOT_STATUS                                                                       0x0000ccUL //Access:R    DataWidth:0x20  For EP this register is not applicable and hardwired to 0.  Chips: BB_A0 BB_B0
993 #define PCIEIP_REG_VPD_BASE_K2                                                                       0x0000d0UL //Access:RW   DataWidth:0x20  VPD Control and Capabilities Register.  Chips: K2
994     #define PCIEIP_REG_VPD_BASE_VPD_PCIE_EXTENDED_CAP_ID                                             (0xff<<0) // VPD Extended Capability ID.
995     #define PCIEIP_REG_VPD_BASE_VPD_PCIE_EXTENDED_CAP_ID_SHIFT                                       0
996     #define PCIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET                                                      (0xff<<8) // VPD Pointer to Next Capability.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
997     #define PCIEIP_REG_VPD_BASE_VPD_NEXT_OFFSET_SHIFT                                                8
998     #define PCIEIP_REG_VPD_BASE_VPD_ADDRESS                                                          (0x7fff<<16) // VPD Address.   Note: The access attributes of this field are as follows:  - Dbi: R/W
999     #define PCIEIP_REG_VPD_BASE_VPD_ADDRESS_SHIFT                                                    16
1000     #define PCIEIP_REG_VPD_BASE_VPD_FLAG                                                             (0x1<<31) // VPD Flag.   Note: The access attributes of this field are as follows:  - Dbi: R/W
1001     #define PCIEIP_REG_VPD_BASE_VPD_FLAG_SHIFT                                                       31
1002 #define PCIEIP_REG_DEVICE_CAPABILITY_2_BB_A0                                                         0x0000d0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1003 #define PCIEIP_REG_DEVICE_CAPABILITY_2_BB_B0                                                         0x0000d0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1004     #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED                             (0xf<<0) // Completion Timeout Ranges Supported. Programmable through register space Path= i_cfg_func.i_cfg_private
1005     #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_RANGES_SUPPORTED_SHIFT                       0
1006     #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED                             (0x1<<4) // Completion Timeout Disable Supported, Programmable through register space Path= i_cfg_func.i_cfg_private
1007     #define PCIEIP_REG_DEVICE_CAPABILITY_2_CMPL_TIMEOUT_DISABL_SUPPORTED_SHIFT                       4
1008     #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED0                                                   (0x3f<<5) //
1009     #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED0_SHIFT                                             5
1010     #define PCIEIP_REG_DEVICE_CAPABILITY_2_LTR_MECHANISM_SUPPORTED                                   (0x1<<11) // Latency Tolerance Reporting Mechanism Supported, Programmable through register space. This field will read 1, when bit 5 of ext_cap_ena field in private register space is set.
1011     #define PCIEIP_REG_DEVICE_CAPABILITY_2_LTR_MECHANISM_SUPPORTED_SHIFT                             11
1012     #define PCIEIP_REG_DEVICE_CAPABILITY_2_TPH_COMPLETER_SUPPORTED                                   (0x3<<12) // TPH and Extended TPH completer not supported.
1013     #define PCIEIP_REG_DEVICE_CAPABILITY_2_TPH_COMPLETER_SUPPORTED_SHIFT                             12
1014     #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED1                                                   (0xf<<14) //
1015     #define PCIEIP_REG_DEVICE_CAPABILITY_2_UNUSED1_SHIFT                                             14
1016     #define PCIEIP_REG_DEVICE_CAPABILITY_2_OBFF_SUPORTED                                             (0x3<<18) // OBFF Supported using WAKE# signaling only. Value is programmable through private register space in Device_cap2.
1017     #define PCIEIP_REG_DEVICE_CAPABILITY_2_OBFF_SUPORTED_SHIFT                                       18
1018 #define PCIEIP_REG_DATA_REG_K2                                                                       0x0000d4UL //Access:RW   DataWidth:0x20  VPD Data Register.  Chips: K2
1019 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_BB_A0                                                     0x0000d4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1020 #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_BB_B0                                                     0x0000d4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1021     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE                                    (0xf<<0) // Completion timeout value. The spec specifies a range, the device uses the max value in the range. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1022     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_VALUE_SHIFT                              0
1023     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE                                  (0x1<<4) // Completion Timeout Disable Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1024     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_CMPL_TIMEOUT_DISABLE_SHIFT                            4
1025     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED0                                               (0x1<<5) //
1026     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED0_SHIFT                                         5
1027     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE                                     (0x1<<6) // Atomic requester Enable. When this bit is set, function and associated VF's are enabled to make Atomic Op requests.
1028     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_ATOMIC_REQ_ENABLE_SHIFT                               6
1029     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED1                                               (0x1<<7) //
1030     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED1_SHIFT                                         7
1031     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_REQ_ENABLE                                        (0x1<<8) // IDO Request Enable, This field is writeable, when bit ido_supported bit of private device_capability_2 register is set. When this bit is set, function is permitted to set ID based Ordering Attribute of Requests it initiates.
1032     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_REQ_ENABLE_SHIFT                                  8
1033     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_CPL_ENABLE                                        (0x1<<9) // IDO Completion Enable, This field is writeable, when bit ido_supported bit of private device_capability_2 register is set. When this bit is set, function is permitted to set ID based Ordering Attribute of Completions it returns.
1034     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_IDO_CPL_ENABLE_SHIFT                                  9
1035     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_LTR_MECHANISM_ENABLE                                  (0x1<<10) // Latency Tolerance Reporting Mechanism Enable, This field is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW only in function 0 and is RsvdP for all other functions.
1036     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_LTR_MECHANISM_ENABLE_SHIFT                            10
1037     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED2                                               (0x3<<11) //
1038     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED2_SHIFT                                         11
1039     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_OBFF_ENABLE                                           (0x3<<13) // Enable OBFF mechanism and select signaling method. This field is writeable, when bit 5 of ext_cap_ena field in private register space is set. This bit is RW only in function 0 and is RsvdP for all other functions.
1040     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_OBFF_ENABLE_SHIFT                                     13
1041     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED3                                               (0x1<<15) //
1042     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_UNUSED3_SHIFT                                         15
1043     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2                                       (0xffff<<16) // Placeholder for Gen2 Path= i_cfg_func.i_cfg_public.i_cfg_rd_mux
1044     #define PCIEIP_REG_DEVICE_STATUS_CONTROL_2_DEVICE_STATUS_2_SHIFT                                 16
1045 #define PCIEIP_REG_LINK_CAPABILITY_2                                                                 0x0000d8UL //Access:R    DataWidth:0x20  Placeholder for Gen2 Path= i_cfg_func.i_cfg_private  Chips: BB_A0 BB_B0
1046 #define PCIEIP_REG_LINK_STATUS_CONTROL_2                                                             0x0000dcUL //Access:RW   DataWidth:0x20  This register will be Read only by default, and will read all 0's to allow compliance with PCIE spec 1.1. To enable this register, reset comply_pcie_1_1 bit in the register space to 0.  Chips: BB_A0 BB_B0
1047     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED                                       (0xf<<0) // Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1048     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_TARGET_LINK_SPEED_SHIFT                                 0
1049     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE                                        (0x1<<4) //
1050     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_ENTER_COMPLIANCE_SHIFT                                  4
1051     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE                                   (0x1<<5) //
1052     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_HW_AUTO_SPEED_DISABLE_SHIFT                             5
1053     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS                                          (0x1<<6) // When link is operating at Gen2 rates, this bit selects the level of de-emphasis. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap Value used by logic is resolved to 1 if either function has this bit set.
1054     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_SEL_DEEMPHASIS_SHIFT                                    6
1055     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN                                           (0x7<<7) // Value used by logic is resolved to the smaller binary value, if two functions have different values.
1056     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_TX_MARGIN_SHIFT                                     7
1057     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE                                (0x1<<10) //
1058     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_ENTER_MOD_COMPLIANCE_SHIFT                          10
1059     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS                                      (0x1<<11) //
1060     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_SOS_SHIFT                                11
1061     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH                                   (0x1<<12) //
1062     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_COMPLIANCE_DEEMPH_SHIFT                             12
1063     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_UNUSED0                                                 (0x7<<13) //
1064     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_UNUSED0_SHIFT                                           13
1065     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL                                       (0x1<<16) // curr_deemph_level Path = pl_top
1066     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CURR_DEEMPH_LEVEL_SHIFT                                 16
1067     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_COMPLETE                                         (0x1<<17) // Equalization Complete - when set, this indicates that the Transmitter equalization procedure has completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1068     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_COMPLETE_SHIFT                                   17
1069     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE1_SUCCESS                                   (0x1<<18) // Equalization Phase 1 Successful - when set, this indicates that Phase 1 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1070     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE1_SUCCESS_SHIFT                             18
1071     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE2_SUCCESS                                   (0x1<<19) // Equalization Phase 2 Successful - when set, this indicates that Phase 2 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1072     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE2_SUCCESS_SHIFT                             19
1073     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE3_SUCCESS                                   (0x1<<20) // Equalization Phase 3 Successful - when set, this indicates that Phase 3 of the Transmitter equalization procedure has successfully completed. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1074     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_EQ_PHASE3_SUCCESS_SHIFT                             20
1075     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_LINK_EQ_REQUEST                                     (0x1<<21) // This bit is set by hardware to request the link equalization process to be performed on the link. Path= i_cfg_func.i_cfg_public.i_cfg_exp_cap
1076     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_CFG_LINK_EQ_REQUEST_SHIFT                               21
1077     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_LINK_STATUS_2_UNUSED                                    (0x3ff<<22) // Placeholder
1078     #define PCIEIP_REG_LINK_STATUS_CONTROL_2_LINK_STATUS_2_UNUSED_SHIFT                              22
1079 #define PCIEIP_REG_SLOT_CAPABILITY_2                                                                 0x0000e0UL //Access:R    DataWidth:0x20  Not implemented  Chips: BB_A0 BB_B0
1080 #define PCIEIP_REG_SLOT_STATUS_CONTROL_2                                                             0x0000e4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
1081     #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2                                          (0xffff<<0) // Not implemented
1082     #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_CONTROL_2_SHIFT                                    0
1083     #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2                                           (0xffff<<16) // Not implemented
1084     #define PCIEIP_REG_SLOT_STATUS_CONTROL_2_SLOT_STATUS_2_SHIFT                                     16
1085 #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_K2                                                            0x000100UL //Access:RW   DataWidth:0x20  Advanced Error Reporting Extended Capability Header.  Chips: K2
1086     #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_ID                                                    (0xffff<<0) // AER Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1087     #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_ID_SHIFT                                              0
1088     #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_VERSION                                               (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1089     #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_CAP_VERSION_SHIFT                                         16
1090     #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET                                               (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1091     #define PCIEIP_REG_AER_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT                                         20
1092 #define PCIEIP_REG_ADV_ERR_CAP_BB_A0                                                                 0x000100UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1093 #define PCIEIP_REG_ADV_ERR_CAP_BB_B0                                                                 0x000100UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1094     #define PCIEIP_REG_ADV_ERR_CAP_ADV_ERR_CAP_ID                                                    (0xffff<<0) // PCI Express Extended Capability ID. These bits are hardwired to 0001h indicating the presence of PCI Express Advanced Error Capability. Path= cfg_defs
1095     #define PCIEIP_REG_ADV_ERR_CAP_ADV_ERR_CAP_ID_SHIFT                                              0
1096     #define PCIEIP_REG_ADV_ERR_CAP_VER                                                               (0xf<<16) // Capability ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Path= cfg_defs.v
1097     #define PCIEIP_REG_ADV_ERR_CAP_VER_SHIFT                                                         16
1098     #define PCIEIP_REG_ADV_ERR_CAP_NEXT                                                              (0xfff<<20) // Next Capabilities Pointer is 0x13C which is Power Budget. Path= i_cfg_func.i_cfg_public.i_cfg_ep_reg
1099     #define PCIEIP_REG_ADV_ERR_CAP_NEXT_SHIFT                                                        20
1100 #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_K2                                                          0x000104UL //Access:RW   DataWidth:0x20  Uncorrectable Error Status Register.  Chips: K2
1101     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_0                                                 (0xf<<0) // Reserved for future use.
1102     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_0_SHIFT                                           0
1103     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS                                  (0x1<<4) // Data Link Protocol Error Status.
1104     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_DL_PROTOCOL_ERR_STATUS_SHIFT                            4
1105     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS                                      (0x1<<5) // Surprise Down Error Status (Optional).   Note: Not supported.
1106     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_SUR_DWN_ERR_STATUS_SHIFT                                5
1107     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_6                                                 (0x3f<<6) // Reserved for future use.
1108     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_6_SHIFT                                           6
1109     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS                                     (0x1<<12) // Poisoned TLP Status.
1110     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_POIS_TLP_ERR_STATUS_SHIFT                               12
1111     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS                                  (0x1<<13) // Flow Control Protocol Error Status.
1112     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_FC_PROTOCOL_ERR_STATUS_SHIFT                            13
1113     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS                                (0x1<<14) // Completion Timeout Status.
1114     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_TIMEOUT_ERR_STATUS_SHIFT                          14
1115     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS                                  (0x1<<15) // Completer Abort Status.
1116     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_CMPLT_ABORT_ERR_STATUS_SHIFT                            15
1117     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS                                  (0x1<<16) // Unexpected Completion Status.
1118     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNEXP_CMPLT_ERR_STATUS_SHIFT                            16
1119     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS                                 (0x1<<17) // Receiver Overflow Status.
1120     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_REC_OVERFLOW_ERR_STATUS_SHIFT                           17
1121     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS                                     (0x1<<18) // Malformed TLP Status.
1122     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_MALF_TLP_ERR_STATUS_SHIFT                               18
1123     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS                                         (0x1<<19) // ECRC Error Status.
1124     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_ECRC_ERR_STATUS_SHIFT                                   19
1125     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS                              (0x1<<20) // Unsupported Request Error Status.
1126     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_UNSUPPORTED_REQ_ERR_STATUS_SHIFT                        20
1127     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_21                                                (0x1<<21) // Reserved for future use.
1128     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_21_SHIFT                                          21
1129     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS                                     (0x1<<22) // Uncorrectable Internal Error Status.    The core sets this bit when your application asserts app_err_bus[9]. It does not set this bit when it detects internal uncorrectable internal errors such as parity and ECC failures. You should use the outputs from these errors to drive the app_err_bus[9] input. For more details, see the "Data Integrity (Wire, Datapath, and RAM Protection)" section in the Databook.
1130     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_INTERNAL_ERR_STATUS_SHIFT                               22
1131     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_23                                                (0x3<<23) // Reserved for future use.
1132     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_23_SHIFT                                          23
1133     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS                             (0x1<<25) // TLP Prefix Blocked Error Status.   Note: Not supported.
1134     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_TLP_PRFX_BLOCKED_ERR_STATUS_SHIFT                       25
1135     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_26                                                (0x3f<<26) // Reserved for future use.
1136     #define PCIEIP_REG_UNCORR_ERR_STATUS_OFF_RSVDP_26_SHIFT                                          26
1137 #define PCIEIP_REG_UC_ERR_STATUS_BB_A0                                                               0x000104UL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1138 #define PCIEIP_REG_UC_ERR_STATUS_BB_B0                                                               0x000104UL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1139     #define PCIEIP_REG_UC_ERR_STATUS_UNUSED0                                                         (0xf<<0) //
1140     #define PCIEIP_REG_UC_ERR_STATUS_UNUSED0_SHIFT                                                   0
1141     #define PCIEIP_REG_UC_ERR_STATUS_DLPES                                                           (0x1<<4) // Data Link Protocol Error Status
1142     #define PCIEIP_REG_UC_ERR_STATUS_DLPES_SHIFT                                                     4
1143     #define PCIEIP_REG_UC_ERR_STATUS_UNUSED1                                                         (0x7f<<5) //
1144     #define PCIEIP_REG_UC_ERR_STATUS_UNUSED1_SHIFT                                                   5
1145     #define PCIEIP_REG_UC_ERR_STATUS_PTLPS                                                           (0x1<<12) // Poisoned TLP Status.
1146     #define PCIEIP_REG_UC_ERR_STATUS_PTLPS_SHIFT                                                     12
1147     #define PCIEIP_REG_UC_ERR_STATUS_FCPES                                                           (0x1<<13) // Flow Control Protocol Error Status.
1148     #define PCIEIP_REG_UC_ERR_STATUS_FCPES_SHIFT                                                     13
1149     #define PCIEIP_REG_UC_ERR_STATUS_CTS                                                             (0x1<<14) // Completer Timeout Status.
1150     #define PCIEIP_REG_UC_ERR_STATUS_CTS_SHIFT                                                       14
1151     #define PCIEIP_REG_UC_ERR_STATUS_CAS                                                             (0x1<<15) // Completer Abort Status.
1152     #define PCIEIP_REG_UC_ERR_STATUS_CAS_SHIFT                                                       15
1153     #define PCIEIP_REG_UC_ERR_STATUS_UCS                                                             (0x1<<16) // Unexpected Completion Status.
1154     #define PCIEIP_REG_UC_ERR_STATUS_UCS_SHIFT                                                       16
1155     #define PCIEIP_REG_UC_ERR_STATUS_ROS                                                             (0x1<<17) // Receiver Overflow Status.
1156     #define PCIEIP_REG_UC_ERR_STATUS_ROS_SHIFT                                                       17
1157     #define PCIEIP_REG_UC_ERR_STATUS_MTLPS                                                           (0x1<<18) // Malformed TLP Status.
1158     #define PCIEIP_REG_UC_ERR_STATUS_MTLPS_SHIFT                                                     18
1159     #define PCIEIP_REG_UC_ERR_STATUS_ECRCS                                                           (0x1<<19) // ECRC Error Status
1160     #define PCIEIP_REG_UC_ERR_STATUS_ECRCS_SHIFT                                                     19
1161     #define PCIEIP_REG_UC_ERR_STATUS_URES                                                            (0x1<<20) // Unsupported Request Error Status.
1162     #define PCIEIP_REG_UC_ERR_STATUS_URES_SHIFT                                                      20
1163 #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_K2                                                            0x000108UL //Access:RW   DataWidth:0x20  Uncorrectable Error Mask Register.  Chips: K2
1164     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_0                                                   (0xf<<0) // Reserved for future use.
1165     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_0_SHIFT                                             0
1166     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK                                      (0x1<<4) // Data Link Protocol Error Mask.   Note: This register field is sticky.
1167     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_DL_PROTOCOL_ERR_MASK_SHIFT                                4
1168     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK                                          (0x1<<5) // Surprise Down Error Mask.   Note: Not supported.  Note: This register field is sticky.
1169     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_SUR_DWN_ERR_MASK_SHIFT                                    5
1170     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_6                                                   (0x3f<<6) // Reserved for future use.
1171     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_6_SHIFT                                             6
1172     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK                                         (0x1<<12) // Poisoned TLP Error Mask.   Note: This register field is sticky.
1173     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_POIS_TLP_ERR_MASK_SHIFT                                   12
1174     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK                                      (0x1<<13) // Flow Control Protocol Error Mask.   Note: This register field is sticky.
1175     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_FC_PROTOCOL_ERR_MASK_SHIFT                                13
1176     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK                                    (0x1<<14) // Completion Timeout Error Mask.   Note: This register field is sticky.
1177     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_TIMEOUT_ERR_MASK_SHIFT                              14
1178     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK                                      (0x1<<15) // Completer Abort Error Mask (Optional).   Note: This register field is sticky.
1179     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_CMPLT_ABORT_ERR_MASK_SHIFT                                15
1180     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK                                      (0x1<<16) // Unexpected Completion Mask.   Note: This register field is sticky.
1181     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNEXP_CMPLT_ERR_MASK_SHIFT                                16
1182     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK                                     (0x1<<17) // Receiver Overflow Mask (Optional).   Note: This register field is sticky.
1183     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_REC_OVERFLOW_ERR_MASK_SHIFT                               17
1184     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK                                         (0x1<<18) // Malformed TLP Mask.   Note: This register field is sticky.
1185     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_MALF_TLP_ERR_MASK_SHIFT                                   18
1186     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK                                             (0x1<<19) // ECRC Error Mask (Optional).   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
1187     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ECRC_ERR_MASK_SHIFT                                       19
1188     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK                                  (0x1<<20) // Unsupported Request Error Mask.   Note: This register field is sticky.
1189     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_UNSUPPORTED_REQ_ERR_MASK_SHIFT                            20
1190     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_21                                                  (0x1<<21) // Reserved for future use.
1191     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_21_SHIFT                                            21
1192     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK                                         (0x1<<22) // Uncorrectable Internal Error Mask (Optional).   Note: This register field is sticky.
1193     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_INTERNAL_ERR_MASK_SHIFT                                   22
1194     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_23                                                  (0x1<<23) // Reserved for future use.
1195     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_23_SHIFT                                            23
1196     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK                            (0x1<<24) // AtomicOp Egress Block Mask (Optional).   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
1197     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_ATOMIC_EGRESS_BLOCKED_ERR_MASK_SHIFT                      24
1198     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK                                 (0x1<<25) // TLP Prefix Blocked Error Mask.   Note: Not supported.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
1199     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_TLP_PRFX_BLOCKED_ERR_MASK_SHIFT                           25
1200     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_26                                                  (0x3f<<26) // Reserved for future use.
1201     #define PCIEIP_REG_UNCORR_ERR_MASK_OFF_RSVDP_26_SHIFT                                            26
1202 #define PCIEIP_REG_UCORR_ERR_MASK_BB_A0                                                              0x000108UL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1203 #define PCIEIP_REG_UCORR_ERR_MASK_BB_B0                                                              0x000108UL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1204     #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED0                                                        (0xf<<0) //
1205     #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED0_SHIFT                                                  0
1206     #define PCIEIP_REG_UCORR_ERR_MASK_DLPEM                                                          (0x1<<4) // Data Link Protocol Error Mask.
1207     #define PCIEIP_REG_UCORR_ERR_MASK_DLPEM_SHIFT                                                    4
1208     #define PCIEIP_REG_UCORR_ERR_MASK_SDEM                                                           (0x1<<5) // Surprise Down Error Mask
1209     #define PCIEIP_REG_UCORR_ERR_MASK_SDEM_SHIFT                                                     5
1210     #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED1                                                        (0x3f<<6) //
1211     #define PCIEIP_REG_UCORR_ERR_MASK_UNUSED1_SHIFT                                                  6
1212     #define PCIEIP_REG_UCORR_ERR_MASK_PTLPM                                                          (0x1<<12) // Poisoned TLP Mask.
1213     #define PCIEIP_REG_UCORR_ERR_MASK_PTLPM_SHIFT                                                    12
1214     #define PCIEIP_REG_UCORR_ERR_MASK_FCPEM                                                          (0x1<<13) // Flow Control Protocol Error Mask.
1215     #define PCIEIP_REG_UCORR_ERR_MASK_FCPEM_SHIFT                                                    13
1216     #define PCIEIP_REG_UCORR_ERR_MASK_CTM                                                            (0x1<<14) // Completer Timeout Mask.
1217     #define PCIEIP_REG_UCORR_ERR_MASK_CTM_SHIFT                                                      14
1218     #define PCIEIP_REG_UCORR_ERR_MASK_CAM                                                            (0x1<<15) // Completer Abort Mask.
1219     #define PCIEIP_REG_UCORR_ERR_MASK_CAM_SHIFT                                                      15
1220     #define PCIEIP_REG_UCORR_ERR_MASK_UCM                                                            (0x1<<16) // Unexpected Completion Mask.
1221     #define PCIEIP_REG_UCORR_ERR_MASK_UCM_SHIFT                                                      16
1222     #define PCIEIP_REG_UCORR_ERR_MASK_ROM                                                            (0x1<<17) // Receiver Overflow Mask.
1223     #define PCIEIP_REG_UCORR_ERR_MASK_ROM_SHIFT                                                      17
1224     #define PCIEIP_REG_UCORR_ERR_MASK_MTLPM                                                          (0x1<<18) // Malformed TLP Mask.
1225     #define PCIEIP_REG_UCORR_ERR_MASK_MTLPM_SHIFT                                                    18
1226     #define PCIEIP_REG_UCORR_ERR_MASK_ECRCEM                                                         (0x1<<19) // ECRC Error Mask
1227     #define PCIEIP_REG_UCORR_ERR_MASK_ECRCEM_SHIFT                                                   19
1228     #define PCIEIP_REG_UCORR_ERR_MASK_UREM                                                           (0x1<<20) // Unsupported Request Error Mask.
1229     #define PCIEIP_REG_UCORR_ERR_MASK_UREM_SHIFT                                                     20
1230 #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_K2                                                             0x00010cUL //Access:RW   DataWidth:0x20  Uncorrectable Error Severity Register.  Chips: K2
1231     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_0                                                    (0xf<<0) // Reserved for future use.
1232     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_0_SHIFT                                              0
1233     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY                                   (0x1<<4) // Data Link Protocol Error Severity.   Note: This register field is sticky.
1234     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_DL_PROTOCOL_ERR_SEVERITY_SHIFT                             4
1235     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY                                       (0x1<<5) // Surprise Down Error Severity (Optional).   Note: Not supported.  Note: This register field is sticky.
1236     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_SUR_DWN_ERR_SEVERITY_SHIFT                                 5
1237     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_6                                                    (0x3f<<6) // Reserved for future use.
1238     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_6_SHIFT                                              6
1239     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY                                      (0x1<<12) // Poisoned TLP Severity.   Note: This register field is sticky.
1240     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_POIS_TLP_ERR_SEVERITY_SHIFT                                12
1241     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY                                   (0x1<<13) // Flow Control Protocol Error Severity (Optional).   Note: This register field is sticky.
1242     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_FC_PROTOCOL_ERR_SEVERITY_SHIFT                             13
1243     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY                                 (0x1<<14) // Completion Timeout Error Severity.   Note: This register field is sticky.
1244     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_TIMEOUT_ERR_SEVERITY_SHIFT                           14
1245     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY                                   (0x1<<15) // Completer Abort Error Severity (Optional).   Note: This register field is sticky.
1246     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_CMPLT_ABORT_ERR_SEVERITY_SHIFT                             15
1247     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY                                   (0x1<<16) // Unexpected Completion Error Severity.   Note: This register field is sticky.
1248     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNEXP_CMPLT_ERR_SEVERITY_SHIFT                             16
1249     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY                                  (0x1<<17) // Receiver Overflow Error Severity (Optional).   Note: This register field is sticky.
1250     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_REC_OVERFLOW_ERR_SEVERITY_SHIFT                            17
1251     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY                                      (0x1<<18) // Malformed TLP Severity.   Note: This register field is sticky.
1252     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_MALF_TLP_ERR_SEVERITY_SHIFT                                18
1253     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY                                          (0x1<<19) // ECRC Error Severity (Optional).   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
1254     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ECRC_ERR_SEVERITY_SHIFT                                    19
1255     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY                               (0x1<<20) // Unsupported Request Error Severity.   Note: This register field is sticky.
1256     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_UNSUPPORTED_REQ_ERR_SEVERITY_SHIFT                         20
1257     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_21                                                   (0x1<<21) // Reserved for future use.
1258     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_21_SHIFT                                             21
1259     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY                                      (0x1<<22) // Uncorrectable Internal Error Severity (Optional).   Note: This register field is sticky.
1260     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_INTERNAL_ERR_SEVERITY_SHIFT                                22
1261     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_23                                                   (0x1<<23) // Reserved for future use.
1262     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_23_SHIFT                                             23
1263     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY                         (0x1<<24) // AtomicOp Egress Blocked Severity (Optional).   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
1264     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY_SHIFT                   24
1265     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY                              (0x1<<25) // TLP Prefix Blocked Error Severity (Optional).   Note: Not supported.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
1266     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_TLP_PRFX_BLOCKED_ERR_SEVERITY_SHIFT                        25
1267     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_26                                                   (0x3f<<26) // Reserved for future use.
1268     #define PCIEIP_REG_UNCORR_ERR_SEV_OFF_RSVDP_26_SHIFT                                             26
1269 #define PCIEIP_REG_UCORR_ERR_SEVR_BB_A0                                                              0x00010cUL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1270 #define PCIEIP_REG_UCORR_ERR_SEVR_BB_B0                                                              0x00010cUL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1271     #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED0                                                        (0xf<<0) //
1272     #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED0_SHIFT                                                  0
1273     #define PCIEIP_REG_UCORR_ERR_SEVR_DLPES                                                          (0x1<<4) // Data Link Protocol Error Severity.
1274     #define PCIEIP_REG_UCORR_ERR_SEVR_DLPES_SHIFT                                                    4
1275     #define PCIEIP_REG_UCORR_ERR_SEVR_SDES                                                           (0x1<<5) // Surprise Down Error Severity. Hardwire to 1'b1.
1276     #define PCIEIP_REG_UCORR_ERR_SEVR_SDES_SHIFT                                                     5
1277     #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED1                                                        (0x3f<<6) //
1278     #define PCIEIP_REG_UCORR_ERR_SEVR_UNUSED1_SHIFT                                                  6
1279     #define PCIEIP_REG_UCORR_ERR_SEVR_PTLPS                                                          (0x1<<12) // Poisoned TLP Severity.
1280     #define PCIEIP_REG_UCORR_ERR_SEVR_PTLPS_SHIFT                                                    12
1281     #define PCIEIP_REG_UCORR_ERR_SEVR_FCPES                                                          (0x1<<13) // Flow Control Protocol Error Severity.
1282     #define PCIEIP_REG_UCORR_ERR_SEVR_FCPES_SHIFT                                                    13
1283     #define PCIEIP_REG_UCORR_ERR_SEVR_CTS                                                            (0x1<<14) // Completer Timeout Severity.
1284     #define PCIEIP_REG_UCORR_ERR_SEVR_CTS_SHIFT                                                      14
1285     #define PCIEIP_REG_UCORR_ERR_SEVR_CAS                                                            (0x1<<15) // Completer Abort Severity.
1286     #define PCIEIP_REG_UCORR_ERR_SEVR_CAS_SHIFT                                                      15
1287     #define PCIEIP_REG_UCORR_ERR_SEVR_UCS                                                            (0x1<<16) // Unexpected Completion Severity.
1288     #define PCIEIP_REG_UCORR_ERR_SEVR_UCS_SHIFT                                                      16
1289     #define PCIEIP_REG_UCORR_ERR_SEVR_ROS                                                            (0x1<<17) // Receiver Overflow Severity.
1290     #define PCIEIP_REG_UCORR_ERR_SEVR_ROS_SHIFT                                                      17
1291     #define PCIEIP_REG_UCORR_ERR_SEVR_MTLPS                                                          (0x1<<18) // Malformed TLP Severity.
1292     #define PCIEIP_REG_UCORR_ERR_SEVR_MTLPS_SHIFT                                                    18
1293     #define PCIEIP_REG_UCORR_ERR_SEVR_ECRCES                                                         (0x1<<19) // Ecrc error Severity
1294     #define PCIEIP_REG_UCORR_ERR_SEVR_ECRCES_SHIFT                                                   19
1295     #define PCIEIP_REG_UCORR_ERR_SEVR_URES                                                           (0x1<<20) // Unsupported Request Error Severity.
1296     #define PCIEIP_REG_UCORR_ERR_SEVR_URES_SHIFT                                                     20
1297 #define PCIEIP_REG_CORR_ERR_STATUS_OFF_K2                                                            0x000110UL //Access:RW   DataWidth:0x20  Correctable Error Status Register.  Chips: K2
1298     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS                                             (0x1<<0) // Receiver Error Status (Optional).
1299     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RX_ERR_STATUS_SHIFT                                       0
1300     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RSVDP_1                                                   (0x1f<<1) // Reserved for future use.
1301     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RSVDP_1_SHIFT                                             1
1302     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS                                            (0x1<<6) // Bad TLP Status.
1303     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_TLP_STATUS_SHIFT                                      6
1304     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS                                           (0x1<<7) // Bad DLLP Status.
1305     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_BAD_DLLP_STATUS_SHIFT                                     7
1306     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS                                 (0x1<<8) // REPLAY_NUM Rollover Status.
1307     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_REPLAY_NO_ROLEOVER_STATUS_SHIFT                           8
1308     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RSVDP_9                                                   (0x7<<9) // Reserved for future use.
1309     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RSVDP_9_SHIFT                                             9
1310     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS                                  (0x1<<12) // Replay Timer Timeout Status.
1311     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RPL_TIMER_TIMEOUT_STATUS_SHIFT                            12
1312     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS                             (0x1<<13) // Advisory Non-Fatal Error Status.
1313     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_ADVISORY_NON_FATAL_ERR_STATUS_SHIFT                       13
1314     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS                                  (0x1<<14) // Corrected Internal Error Status (Optional).
1315     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_CORRECTED_INT_ERR_STATUS_SHIFT                            14
1316     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS                                (0x1<<15) // Header Log Overflow Error Status (Optional).
1317     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_HEADER_LOG_OVERFLOW_STATUS_SHIFT                          15
1318     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RSVDP_16                                                  (0xffff<<16) // Reserved for future use.
1319     #define PCIEIP_REG_CORR_ERR_STATUS_OFF_RSVDP_16_SHIFT                                            16
1320 #define PCIEIP_REG_CORR_ERR_STATUS_BB_A0                                                             0x000110UL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1321 #define PCIEIP_REG_CORR_ERR_STATUS_BB_B0                                                             0x000110UL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1322     #define PCIEIP_REG_CORR_ERR_STATUS_RX_ERR_STATUS                                                 (0x1<<0) // Receiver Error Status.
1323     #define PCIEIP_REG_CORR_ERR_STATUS_RX_ERR_STATUS_SHIFT                                           0
1324     #define PCIEIP_REG_CORR_ERR_STATUS_UNUSED0                                                       (0x1f<<1) //
1325     #define PCIEIP_REG_CORR_ERR_STATUS_UNUSED0_SHIFT                                                 1
1326     #define PCIEIP_REG_CORR_ERR_STATUS_BAD_TLP_STATUS                                                (0x1<<6) // Bad TLP Status.
1327     #define PCIEIP_REG_CORR_ERR_STATUS_BAD_TLP_STATUS_SHIFT                                          6
1328     #define PCIEIP_REG_CORR_ERR_STATUS_BAD_DLLP_STATUS                                               (0x1<<7) // Bad DLLP Status.
1329     #define PCIEIP_REG_CORR_ERR_STATUS_BAD_DLLP_STATUS_SHIFT                                         7
1330     #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_NUM_RO_STATUS                                           (0x1<<8) // REPLAY_NUM Rollover Status.
1331     #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_NUM_RO_STATUS_SHIFT                                     8
1332     #define PCIEIP_REG_CORR_ERR_STATUS_UNUSED1                                                       (0x7<<9) //
1333     #define PCIEIP_REG_CORR_ERR_STATUS_UNUSED1_SHIFT                                                 9
1334     #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_TMR_TO_STATUS                                           (0x1<<12) // Replay Timer Timeout Status.
1335     #define PCIEIP_REG_CORR_ERR_STATUS_RPLAY_TMR_TO_STATUS_SHIFT                                     12
1336     #define PCIEIP_REG_CORR_ERR_STATUS_ADVSRY_ERR_STATUS                                             (0x1<<13) // Advisory Non fatal Error Status. Only set if role_based_err_rpt is asserted.
1337     #define PCIEIP_REG_CORR_ERR_STATUS_ADVSRY_ERR_STATUS_SHIFT                                       13
1338 #define PCIEIP_REG_CORR_ERR_MASK_OFF_K2                                                              0x000114UL //Access:RW   DataWidth:0x20  Correctable Error Mask Register.  Chips: K2
1339     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK                                                 (0x1<<0) // Receiver Error Mask (Optional).   Note: This register field is sticky.
1340     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RX_ERR_MASK_SHIFT                                           0
1341     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RSVDP_1                                                     (0x1f<<1) // Reserved for future use.
1342     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RSVDP_1_SHIFT                                               1
1343     #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK                                                (0x1<<6) // Bad TLP Mask.   Note: This register field is sticky.
1344     #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_TLP_MASK_SHIFT                                          6
1345     #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK                                               (0x1<<7) // Bad DLLP Mask.   Note: This register field is sticky.
1346     #define PCIEIP_REG_CORR_ERR_MASK_OFF_BAD_DLLP_MASK_SHIFT                                         7
1347     #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK                                     (0x1<<8) // REPLAY_NUM Rollover Mask.   Note: This register field is sticky.
1348     #define PCIEIP_REG_CORR_ERR_MASK_OFF_REPLAY_NO_ROLEOVER_MASK_SHIFT                               8
1349     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RSVDP_9                                                     (0x7<<9) // Reserved for future use.
1350     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RSVDP_9_SHIFT                                               9
1351     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK                                      (0x1<<12) // Replay Timer Timeout Mask.   Note: This register field is sticky.
1352     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RPL_TIMER_TIMEOUT_MASK_SHIFT                                12
1353     #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK                                 (0x1<<13) // Advisory Non-Fatal Error Mask.   Note: This register field is sticky.
1354     #define PCIEIP_REG_CORR_ERR_MASK_OFF_ADVISORY_NON_FATAL_ERR_MASK_SHIFT                           13
1355     #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK                                      (0x1<<14) // Corrected Internal Error Mask (Optional).   Note: This register field is sticky.
1356     #define PCIEIP_REG_CORR_ERR_MASK_OFF_CORRECTED_INT_ERR_MASK_SHIFT                                14
1357     #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK                                    (0x1<<15) // Header Log Overflow Error Mask (Optional).   Note: This register field is sticky.
1358     #define PCIEIP_REG_CORR_ERR_MASK_OFF_HEADER_LOG_OVERFLOW_MASK_SHIFT                              15
1359     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RSVDP_16                                                    (0xffff<<16) // Reserved for future use.
1360     #define PCIEIP_REG_CORR_ERR_MASK_OFF_RSVDP_16_SHIFT                                              16
1361 #define PCIEIP_REG_CORR_ERR_MASK_BB_A0                                                               0x000114UL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1362 #define PCIEIP_REG_CORR_ERR_MASK_BB_B0                                                               0x000114UL //Access:RW   DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1363     #define PCIEIP_REG_CORR_ERR_MASK_RES                                                             (0x1<<0) // Receiver Error Mask.
1364     #define PCIEIP_REG_CORR_ERR_MASK_RES_SHIFT                                                       0
1365     #define PCIEIP_REG_CORR_ERR_MASK_UNUSED0                                                         (0x1f<<1) //
1366     #define PCIEIP_REG_CORR_ERR_MASK_UNUSED0_SHIFT                                                   1
1367     #define PCIEIP_REG_CORR_ERR_MASK_BTLPS                                                           (0x1<<6) // Bad TLP Mask.
1368     #define PCIEIP_REG_CORR_ERR_MASK_BTLPS_SHIFT                                                     6
1369     #define PCIEIP_REG_CORR_ERR_MASK_BDLLPS                                                          (0x1<<7) // Bad DLLP Mask.
1370     #define PCIEIP_REG_CORR_ERR_MASK_BDLLPS_SHIFT                                                    7
1371     #define PCIEIP_REG_CORR_ERR_MASK_RNRS                                                            (0x1<<8) // REPLAY_NUM Rollover Mask.
1372     #define PCIEIP_REG_CORR_ERR_MASK_RNRS_SHIFT                                                      8
1373     #define PCIEIP_REG_CORR_ERR_MASK_UNUSED1                                                         (0x7<<9) //
1374     #define PCIEIP_REG_CORR_ERR_MASK_UNUSED1_SHIFT                                                   9
1375     #define PCIEIP_REG_CORR_ERR_MASK_RTTS                                                            (0x1<<12) // Replay Timer Timeout Mask.
1376     #define PCIEIP_REG_CORR_ERR_MASK_RTTS_SHIFT                                                      12
1377     #define PCIEIP_REG_CORR_ERR_MASK_ANFM                                                            (0x1<<13) // Advisory Non fatal Error Mask
1378     #define PCIEIP_REG_CORR_ERR_MASK_ANFM_SHIFT                                                      13
1379 #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_K2                                                           0x000118UL //Access:RW   DataWidth:0x20  Advanced Error Capabilities and Control Register.  Chips: K2
1380     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER                                        (0x1f<<0) // First Error Pointer.   Note: This register field is sticky.
1381     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_FIRST_ERR_POINTER_SHIFT                                  0
1382     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP                                             (0x1<<5) // ECRC Generation Capable.   Note: This register field is sticky.
1383     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_CAP_SHIFT                                       5
1384     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN                                              (0x1<<6) // ECRC Generation Enable.   Note: This register field is sticky.
1385     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_GEN_EN_SHIFT                                        6
1386     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP                                           (0x1<<7) // ECRC Check Capable.   Note: This register field is sticky.
1387     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_CAP_SHIFT                                     7
1388     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN                                            (0x1<<8) // ECRC Check Enable.   Note: This register field is sticky.
1389     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_ECRC_CHECK_EN_SHIFT                                      8
1390     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP                                      (0x1<<9) // Multiple Header Recording Capable.   Note: This register field is sticky.
1391     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_CAP_SHIFT                                9
1392     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN                                       (0x1<<10) // Multiple Header Recording Enable.   Note: This register field is sticky.
1393     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_MULTIPLE_HEADER_EN_SHIFT                                 10
1394     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_UNUSED_0                                                 (0x1<<11) // reserved
1395     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_UNUSED_0_SHIFT                                           11
1396     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_RSVDP_12                                                 (0xfffff<<12) // Reserved for future use.
1397     #define PCIEIP_REG_ADV_ERR_CAP_CTRL_OFF_RSVDP_12_SHIFT                                           12
1398 #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_BB_A0                                                         0x000118UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1399 #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_BB_B0                                                         0x000118UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1400     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR                                            (0x1f<<0) // First Error Pointer - These bits correspond to the bit position in which the first error occurred.
1401     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_FIRST_UERR_PTR_SHIFT                                      0
1402     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGCAP                                                  (0x1<<5) // ECRC generation capable, programmable through register space
1403     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGCAP_SHIFT                                            5
1404     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGEN                                                   (0x1<<6) // ECRC generate Enable
1405     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCGEN_SHIFT                                             6
1406     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCCAP                                                   (0x1<<7) // ECRC Check Capable, programmable through register space
1407     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCCAP_SHIFT                                             7
1408     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCEN                                                    (0x1<<8) // ECRC Check Enable
1409     #define PCIEIP_REG_ADV_ERR_CAP_CONTROL_ECRCEN_SHIFT                                              8
1410 #define PCIEIP_REG_HDR_LOG_0_OFF_K2                                                                  0x00011cUL //Access:R    DataWidth:0x20  Header Log Register 0.  Chips: K2
1411     #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE                                          (0xff<<0) // Byte 0 of Header log register of First 32 bit Data Word.   Note: This register field is sticky.
1412     #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FIRST_BYTE_SHIFT                                    0
1413     #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE                                         (0xff<<8) // Byte 1 of Header log register of First 32 bit Data Word.   Note: This register field is sticky.
1414     #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_SECOND_BYTE_SHIFT                                   8
1415     #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE                                          (0xff<<16) // Byte 2 of Header log register of First 32 bit Data Word.   Note: This register field is sticky.
1416     #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_THIRD_BYTE_SHIFT                                    16
1417     #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE                                         (0xff<<24) // Byte 3 of Header log register of First 32 bit Data Word.   Note: This register field is sticky.
1418     #define PCIEIP_REG_HDR_LOG_0_OFF_FIRST_DWORD_FOURTH_BYTE_SHIFT                                   24
1419 #define PCIEIP_REG_HEADER_LOG1_BB_A0                                                                 0x00011cUL //Access:R    DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1420 #define PCIEIP_REG_HEADER_LOG1_BB_B0                                                                 0x00011cUL //Access:R    DataWidth:0x20  Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1421 #define PCIEIP_REG_HDR_LOG_1_OFF_K2                                                                  0x000120UL //Access:R    DataWidth:0x20  Header Log Register 1.  Chips: K2
1422     #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE                                         (0xff<<0) // Byte 0 of Header log register of Second 32 bit Data Word.   Note: This register field is sticky.
1423     #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FIRST_BYTE_SHIFT                                   0
1424     #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE                                        (0xff<<8) // Byte 1 of Header log register of Second 32 bit Data Word.   Note: This register field is sticky.
1425     #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_SECOND_BYTE_SHIFT                                  8
1426     #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE                                         (0xff<<16) // Byte 2 of Header log register of Second 32 bit Data Word.   Note: This register field is sticky.
1427     #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_THIRD_BYTE_SHIFT                                   16
1428     #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE                                        (0xff<<24) // Byte 3 of Header log register of Second 32 bit Data Word.   Note: This register field is sticky.
1429     #define PCIEIP_REG_HDR_LOG_1_OFF_SECOND_DWORD_FOURTH_BYTE_SHIFT                                  24
1430 #define PCIEIP_REG_HEADER_LOG2_BB_A0                                                                 0x000120UL //Access:R    DataWidth:0x20  Second DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1431 #define PCIEIP_REG_HEADER_LOG2_BB_B0                                                                 0x000120UL //Access:R    DataWidth:0x20  Second DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1432 #define PCIEIP_REG_HDR_LOG_2_OFF_K2                                                                  0x000124UL //Access:R    DataWidth:0x20  Header Log Register 2.  Chips: K2
1433     #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE                                          (0xff<<0) // Byte 0 of Header log register of Third 32 bit Data Word.   Note: This register field is sticky.
1434     #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FIRST_BYTE_SHIFT                                    0
1435     #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE                                         (0xff<<8) // Byte 1 of Header log register of Third 32 bit Data Word.   Note: This register field is sticky.
1436     #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_SECOND_BYTE_SHIFT                                   8
1437     #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE                                          (0xff<<16) // Byte 2 of Header log register of Third 32 bit Data Word.   Note: This register field is sticky.
1438     #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_THIRD_BYTE_SHIFT                                    16
1439     #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE                                         (0xff<<24) // Byte 3 of Header log register of Third 32 bit Data Word.   Note: This register field is sticky.
1440     #define PCIEIP_REG_HDR_LOG_2_OFF_THIRD_DWORD_FOURTH_BYTE_SHIFT                                   24
1441 #define PCIEIP_REG_HEADER_LOG3_BB_A0                                                                 0x000124UL //Access:R    DataWidth:0x20  Third DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1442 #define PCIEIP_REG_HEADER_LOG3_BB_B0                                                                 0x000124UL //Access:R    DataWidth:0x20  Third DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1443 #define PCIEIP_REG_HDR_LOG_3_OFF_K2                                                                  0x000128UL //Access:R    DataWidth:0x20  Header Log Register 3.  Chips: K2
1444     #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE                                         (0xff<<0) // Byte 0 of Header log register of Fourth 32 bit Data Word.   Note: This register field is sticky.
1445     #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FIRST_BYTE_SHIFT                                   0
1446     #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE                                        (0xff<<8) // Byte 1 of Header log register of Fourth 32 bit Data Word.   Note: This register field is sticky.
1447     #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_SECOND_BYTE_SHIFT                                  8
1448     #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE                                         (0xff<<16) // Byte 2 of Header log register of Fourth 32 bit Data Word.   Note: This register field is sticky.
1449     #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_THIRD_BYTE_SHIFT                                   16
1450     #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE                                        (0xff<<24) // Byte 3 of Header log register of Fourth 32 bit Data Word.   Note: This register field is sticky.
1451     #define PCIEIP_REG_HDR_LOG_3_OFF_FOURTH_DWORD_FOURTH_BYTE_SHIFT                                  24
1452 #define PCIEIP_REG_HEADER_LOG4_BB_A0                                                                 0x000128UL //Access:R    DataWidth:0x20  Fourth DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_A0
1453 #define PCIEIP_REG_HEADER_LOG4_BB_B0                                                                 0x000128UL //Access:R    DataWidth:0x20  Fourth DW of TLP header associated with Error. Path= i_cfg_func.i_cfg_public.i_cfg_adv_err_cap  Chips: BB_B0
1454 #define PCIEIP_REG_ROOT_ERROR_COMMAND                                                                0x00012cUL //Access:R    DataWidth:0x20  For EP this register is not applicable and hardwired to 0.  Chips: BB_A0 BB_B0
1455 #define PCIEIP_REG_ROOT_ERROR_STATUS                                                                 0x000130UL //Access:R    DataWidth:0x20  For EP this register is not applicable and hardwired to 0.  Chips: BB_A0 BB_B0
1456 #define PCIEIP_REG_ROOT_ERR_ID                                                                       0x000134UL //Access:R    DataWidth:0x20  For EP this register is not applicable and hardwired to 0.  Chips: BB_A0 BB_B0
1457 #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF                                                              0x000138UL //Access:R    DataWidth:0x20  TLP Prefix Log Register 1.  Chips: K2
1458     #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE                             (0xff<<0) // Byte 0 of Error TLP Prefix Log 1.   Note: This register field is sticky.
1459     #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FIRST_BYTE_SHIFT                       0
1460     #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE                            (0xff<<8) // Byte 1 of Error TLP Prefix Log 1.   Note: This register field is sticky.
1461     #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_SECOND_BYTE_SHIFT                      8
1462     #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE                             (0xff<<16) // Byte 2 of Error TLP Prefix Log 1.   Note: This register field is sticky.
1463     #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_THIRD_BYTE_SHIFT                       16
1464     #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE                            (0xff<<24) // Byte 3 of Error TLP Prefix Log 1.   Note: This register field is sticky.
1465     #define PCIEIP_REG_TLP_PREFIX_LOG_1_OFF_CFG_TLP_PFX_LOG_1_FOURTH_BYTE_SHIFT                      24
1466 #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_K2                                                           0x00013cUL //Access:R    DataWidth:0x20  TLP Prefix Log Register 2.  Chips: K2
1467     #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE                             (0xff<<0) // Byte 0 Error TLP Prefix Log 2.   Note: This register field is sticky.
1468     #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FIRST_BYTE_SHIFT                       0
1469     #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE                            (0xff<<8) // Byte 1 Error TLP Prefix Log 2.   Note: This register field is sticky.
1470     #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_SECOND_BYTE_SHIFT                      8
1471     #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE                             (0xff<<16) // Byte 2 Error TLP Prefix Log 2.   Note: This register field is sticky.
1472     #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_THIRD_BYTE_SHIFT                       16
1473     #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE                            (0xff<<24) // Byte 3 Error TLP Prefix Log 2.   Note: This register field is sticky.
1474     #define PCIEIP_REG_TLP_PREFIX_LOG_2_OFF_CFG_TLP_PFX_LOG_2_FOURTH_BYTE_SHIFT                      24
1475 #define PCIEIP_REG_DEVICE_SER_NUM_CAP_BB_A0                                                          0x00013cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1476 #define PCIEIP_REG_DEVICE_SER_NUM_CAP_BB_B0                                                          0x00013cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1477     #define PCIEIP_REG_DEVICE_SER_NUM_CAP_DEVICE_SER_NUM_CAP_ID                                      (0xffff<<0) // Device Serial Number Extended Capability ID. These bits are programmable through register space. Path = i_cfg_func.i_cfg_private
1478     #define PCIEIP_REG_DEVICE_SER_NUM_CAP_DEVICE_SER_NUM_CAP_ID_SHIFT                                0
1479     #define PCIEIP_REG_DEVICE_SER_NUM_CAP_VER                                                        (0xf<<16) // Capability ID Version. These bits are programmable through register space. Path = i_cfg_func.i_cfg_private
1480     #define PCIEIP_REG_DEVICE_SER_NUM_CAP_VER_SHIFT                                                  16
1481     #define PCIEIP_REG_DEVICE_SER_NUM_CAP_NEXT                                                       (0xfff<<20) // Next Capabilities Pointer. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
1482     #define PCIEIP_REG_DEVICE_SER_NUM_CAP_NEXT_SHIFT                                                 20
1483 #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_K2                                                           0x000140UL //Access:R    DataWidth:0x20  TLP Prefix Log Register 3.  Chips: K2
1484     #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE                             (0xff<<0) // Byte 0 Error TLP Prefix Log 3.   Note: This register field is sticky.
1485     #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FIRST_BYTE_SHIFT                       0
1486     #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE                            (0xff<<8) // Byte 1 Error TLP Prefix Log 3.   Note: This register field is sticky.
1487     #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_SECOND_BYTE_SHIFT                      8
1488     #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE                             (0xff<<16) // Byte 2 Error TLP Prefix Log 3.   Note: This register field is sticky.
1489     #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_THIRD_BYTE_SHIFT                       16
1490     #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE                            (0xff<<24) // Byte 3 Error TLP Prefix Log 3.   Note: This register field is sticky.
1491     #define PCIEIP_REG_TLP_PREFIX_LOG_3_OFF_CFG_TLP_PFX_LOG_3_FOURTH_BYTE_SHIFT                      24
1492 #define PCIEIP_REG_LOWER_SER_NUM_BB_A0                                                               0x000140UL //Access:R    DataWidth:0x20  This register has the PCIE Device Serial Number bits [31:0]. This register will contain the data written in the Device Serial Number Access Lower Register (Offset 504h). Path = i_cfg_func.i_cfg_private  Chips: BB_A0
1493 #define PCIEIP_REG_LOWER_SER_NUM_BB_B0                                                               0x000140UL //Access:R    DataWidth:0x20  This register has the PCIE Device Serial Number bits [31:0]. This register will contain the data written in the Device Serial Number Access Lower Register (Offset 504h). Path = i_cfg_func.i_cfg_private  Chips: BB_B0
1494 #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_K2                                                           0x000144UL //Access:R    DataWidth:0x20  TLP Prefix Log Register 4.  Chips: K2
1495     #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE                             (0xff<<0) // Byte 0 Error TLP Prefix Log 4.   Note: This register field is sticky.
1496     #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FIRST_BYTE_SHIFT                       0
1497     #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE                            (0xff<<8) // Byte 1 Error TLP Prefix Log 4.   Note: This register field is sticky.
1498     #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_SECOND_BYTE_SHIFT                      8
1499     #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE                             (0xff<<16) // Byte 2 Error TLP Prefix Log 4.   Note: This register field is sticky.
1500     #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_THIRD_BYTE_SHIFT                       16
1501     #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE                            (0xff<<24) // Byte 3 Error TLP Prefix Log 4.   Note: This register field is sticky.
1502     #define PCIEIP_REG_TLP_PREFIX_LOG_4_OFF_CFG_TLP_PFX_LOG_4_FOURTH_BYTE_SHIFT                      24
1503 #define PCIEIP_REG_UPPER_SER_NUM_BB_A0                                                               0x000144UL //Access:R    DataWidth:0x20  This register has the PCIE Device Serial Number bits [63:32]. This register will contain the data written in the Device Serial Number Access Upper Register (Offset 508h). Path = i_cfg_func.i_cfg_private  Chips: BB_A0
1504 #define PCIEIP_REG_UPPER_SER_NUM_BB_B0                                                               0x000144UL //Access:R    DataWidth:0x20  This register has the PCIE Device Serial Number bits [63:32]. This register will contain the data written in the Device Serial Number Access Upper Register (Offset 508h). Path = i_cfg_func.i_cfg_private  Chips: BB_B0
1505 #define PCIEIP_REG_VC_BASE                                                                           0x000148UL //Access:RW   DataWidth:0x20  VC Extended Capability Header.  Chips: K2
1506     #define PCIEIP_REG_VC_BASE_VC_PCIE_EXTENDED_CAP_ID                                               (0xffff<<0) // VC Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1507     #define PCIEIP_REG_VC_BASE_VC_PCIE_EXTENDED_CAP_ID_SHIFT                                         0
1508     #define PCIEIP_REG_VC_BASE_VC_CAP_VERSION                                                        (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1509     #define PCIEIP_REG_VC_BASE_VC_CAP_VERSION_SHIFT                                                  16
1510     #define PCIEIP_REG_VC_BASE_VC_NEXT_OFFSET                                                        (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1511     #define PCIEIP_REG_VC_BASE_VC_NEXT_OFFSET_SHIFT                                                  20
1512 #define PCIEIP_REG_VC_CAPABILITIES_REG_1                                                             0x00014cUL //Access:RW   DataWidth:0x20  Port VC Capability Register 1.  Chips: K2
1513     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT                                           (0x7<<0) // Extended VC Count.
1514     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_EXT_VC_CNT_SHIFT                                     0
1515     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_RSVDP_3                                                 (0x1<<3) // Reserved for future use.
1516     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_RSVDP_3_SHIFT                                           3
1517     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT                                   (0x7<<4) // Low Priority Extended VC Count.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
1518     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_LOW_PRI_EXT_VC_CNT_SHIFT                             4
1519     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_RSVDP_7                                                 (0x1<<7) // Reserved for future use.
1520     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_RSVDP_7_SHIFT                                           7
1521     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK                                      (0x3<<8) // Reference Clock.
1522     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_REFERENCE_CLOCK_SHIFT                                8
1523     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE                             (0x3<<10) // Port Arbitration Table Entry Size.
1524     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_VC_PORT_ARBI_TBL_ENTRY_SIZE_SHIFT                       10
1525     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_RSVDP_12                                                (0xfffff<<12) // Reserved for future use.
1526     #define PCIEIP_REG_VC_CAPABILITIES_REG_1_RSVDP_12_SHIFT                                          12
1527 #define PCIEIP_REG_VC_CAPABILITIES_REG_2_K2                                                          0x000150UL //Access:RW   DataWidth:0x20  Port VC Capability Register 2.  Chips: K2
1528     #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_CAP                                             (0xf<<0) // VC Arbitration Capability.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
1529     #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_CAP_SHIFT                                       0
1530     #define PCIEIP_REG_VC_CAPABILITIES_REG_2_RSVDP_4                                                 (0xfffff<<4) // Reserved for future use.
1531     #define PCIEIP_REG_VC_CAPABILITIES_REG_2_RSVDP_4_SHIFT                                           4
1532     #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET                                    (0xff<<24) // VC Arbitration Table Offset.
1533     #define PCIEIP_REG_VC_CAPABILITIES_REG_2_VC_ARBI_TABLE_OFFSET_SHIFT                              24
1534 #define PCIEIP_REG_PWR_BDGT_CAP_BB_A0                                                                0x000150UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1535 #define PCIEIP_REG_PWR_BDGT_CAP_BB_B0                                                                0x000150UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1536     #define PCIEIP_REG_PWR_BDGT_CAP_PWR_BDGT_CAP_ID                                                  (0xffff<<0) // Power Budgeting Extended Capability ID. Hardwired to 4. Path = cfg_defs
1537     #define PCIEIP_REG_PWR_BDGT_CAP_PWR_BDGT_CAP_ID_SHIFT                                            0
1538     #define PCIEIP_REG_PWR_BDGT_CAP_VER                                                              (0xf<<16) // Capability ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Hardwire to 1. Path = cfg_defs
1539     #define PCIEIP_REG_PWR_BDGT_CAP_VER_SHIFT                                                        16
1540     #define PCIEIP_REG_PWR_BDGT_CAP_NEXT                                                             (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. The read-only value of this register is controlled by the EXT_CAP_ENA register in the PCI register space. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
1541     #define PCIEIP_REG_PWR_BDGT_CAP_NEXT_SHIFT                                                       20
1542 #define PCIEIP_REG_VC_STATUS_CONTROL_REG_K2                                                          0x000154UL //Access:RW   DataWidth:0x20  Port VC Control and Status Register.  Chips: K2
1543     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE                                   (0x1<<0) // Requests Hardware to Load VC Arbitration Table.
1544     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_LOAD_VC_ARBI_TABLE_SHIFT                             0
1545     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT                                          (0x7<<1) // VC Arbitration Select.
1546     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_SELECT_SHIFT                                    1
1547     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_RSVDP_4                                                 (0xfff<<4) // Reserved for future use.
1548     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_RSVDP_4_SHIFT                                           4
1549     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS                                    (0x1<<16) // VC Arbitration Table Status.
1550     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_VC_ARBI_TABLE_STATUS_SHIFT                              16
1551     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_RSVDP_17                                                (0x7fff<<17) // Reserved for future use.
1552     #define PCIEIP_REG_VC_STATUS_CONTROL_REG_RSVDP_17_SHIFT                                          17
1553 #define PCIEIP_REG_PWR_BDGT_DATA_SEL_BB_A0                                                           0x000154UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1554 #define PCIEIP_REG_PWR_BDGT_DATA_SEL_BB_B0                                                           0x000154UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1555     #define PCIEIP_REG_PWR_BDGT_DATA_SEL_DS_VALUE                                                    (0xff<<0) // This value selects the value visible in the pb_dr. Path = i_cfg_func.i_cfg_public.i_cfg_pw_budget_cap
1556     #define PCIEIP_REG_PWR_BDGT_DATA_SEL_DS_VALUE_SHIFT                                              0
1557 #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_K2                                                           0x000158UL //Access:R    DataWidth:0x20  VC Resource Capability Register (0).  Chips: K2
1558     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0                                     (0xff<<0) // Port Arbitration Capability.
1559     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_CAP_VC0_SHIFT                               0
1560     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_RSVDP_8                                                  (0x7f<<8) // Reserved for future use.
1561     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_RSVDP_8_SHIFT                                            8
1562     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0                                (0x1<<15) // Reject Snoop Transactions.   Note: The access attributes of this field are as follows:  - Dbi: R
1563     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_REJECT_SNOOP_TRANS_VC0_SHIFT                          15
1564     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0                                     (0x3f<<16) // Maximum Time Slots-1 supported.   Note: The access attributes of this field are as follows:  - Dbi: R
1565     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_MAX_TIME_SLOT_VC0_SHIFT                               16
1566     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_RSVDP_22                                                 (0x3<<22) // Reserved for future use.
1567     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_RSVDP_22_SHIFT                                           22
1568     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0                                   (0xff<<24) // Port Arbitration Table Offset.
1569     #define PCIEIP_REG_RESOURCE_CAP_REG_VC0_VC_PORT_ARBI_TABLE_VC0_SHIFT                             24
1570 #define PCIEIP_REG_PWR_BDGT_DATA_BB_A0                                                               0x000158UL //Access:R    DataWidth:0x20  This register provides the power budgeting data for the entry number specified by the pwr_bdgt_data_sel register. The data present in this register is selected from one of the POWER BUDGET DATA ACCESS Registers from offset 510h through 52Ch, based on the value written in Power Budget Data Select register. The field definitions for each selected value are the same. Path = i_cfg_func.i_cfg_public.i_cfg_pw_budget_cap  Chips: BB_A0
1571 #define PCIEIP_REG_PWR_BDGT_DATA_BB_B0                                                               0x000158UL //Access:R    DataWidth:0x20  This register provides the power budgeting data for the entry number specified by the pwr_bdgt_data_sel register. The data present in this register is selected from one of the POWER BUDGET DATA ACCESS Registers from offset 510h through 52Ch, based on the value written in Power Budget Data Select register. The field definitions for each selected value are the same. Path = i_cfg_func.i_cfg_public.i_cfg_pw_budget_cap  Chips: BB_B0
1572     #define PCIEIP_REG_PWR_BDGT_DATA_BASE_PWR                                                        (0xff<<0) // Base Power
1573     #define PCIEIP_REG_PWR_BDGT_DATA_BASE_PWR_SHIFT                                                  0
1574     #define PCIEIP_REG_PWR_BDGT_DATA_DSCALE                                                          (0x3<<8) // Data Scale
1575     #define PCIEIP_REG_PWR_BDGT_DATA_DSCALE_SHIFT                                                    8
1576     #define PCIEIP_REG_PWR_BDGT_DATA_UNUSED0                                                         (0x7<<10) //
1577     #define PCIEIP_REG_PWR_BDGT_DATA_UNUSED0_SHIFT                                                   10
1578     #define PCIEIP_REG_PWR_BDGT_DATA_PM_STATE                                                        (0x3<<13) // PM State
1579     #define PCIEIP_REG_PWR_BDGT_DATA_PM_STATE_SHIFT                                                  13
1580     #define PCIEIP_REG_PWR_BDGT_DATA_TYPE                                                            (0x7<<15) // Type
1581     #define PCIEIP_REG_PWR_BDGT_DATA_TYPE_SHIFT                                                      15
1582     #define PCIEIP_REG_PWR_BDGT_DATA_RAIL                                                            (0x7<<18) // Power rail
1583     #define PCIEIP_REG_PWR_BDGT_DATA_RAIL_SHIFT                                                      18
1584 #define PCIEIP_REG_RESOURCE_CON_REG_VC0_K2                                                           0x00015cUL //Access:RW   DataWidth:0x20  VC Resource Control Register (0).  Chips: K2
1585     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0                                            (0x1<<0) // Bit 0 of TC to VC Mapping.
1586     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_SHIFT                                      0
1587     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1                                       (0x7f<<1) // Bits 7:1 of TC to VC Mapping.
1588     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_TC_MAP_VC0_BIT1_SHIFT                                 1
1589     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_RSVDP_8                                                  (0xff<<8) // Reserved for future use.
1590     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_RSVDP_8_SHIFT                                            8
1591     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0                              (0x1<<16) // Load Port Arbitration Table.
1592     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_LOAD_PORT_ARBI_TABLE_VC0_SHIFT                        16
1593     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0                                  (0x1<<17) // Port Arbitration Select.
1594     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_PORT_ARBI_SELECT_VC0_SHIFT                            17
1595     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_RSVDP_18                                                 (0x3f<<18) // Reserved for future use.
1596     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_RSVDP_18_SHIFT                                           18
1597     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ID_VC                                                 (0x7<<24) // VC ID.
1598     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ID_VC_SHIFT                                           24
1599     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_RSVDP_27                                                 (0xf<<27) // Reserved for future use.
1600     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_RSVDP_27_SHIFT                                           27
1601     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0                                            (0x1<<31) // VC Enable.
1602     #define PCIEIP_REG_RESOURCE_CON_REG_VC0_VC_ENABLE_VC0_SHIFT                                      31
1603 #define PCIEIP_REG_PWR_BDGT_CAPABILITY_BB_A0                                                         0x00015cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1604 #define PCIEIP_REG_PWR_BDGT_CAPABILITY_BB_B0                                                         0x00015cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1605     #define PCIEIP_REG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC                                 (0x1<<0) // The "System Allocated" bit when set indicates that the power budget for the device is included within the system power budget. Reported Power Budgeting Data for this device should be ignored by software for power budgeting decisions if this bit is set. This register is Read Only. The value can be written indirectly by writing into Power Budget Capability Register (0x550[0]) Path = i_cfg_func.i_cfg_private
1606     #define PCIEIP_REG_PWR_BDGT_CAPABILITY_PCIE_CFG_PB_CAP_SYS_ALLOC_SHIFT                           0
1607 #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_K2                                                        0x000160UL //Access:R    DataWidth:0x20  VC Resource Status Register (0).  Chips: K2
1608     #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_RSVDP_0                                               (0xffff<<0) // Reserved for future use.
1609     #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_RSVDP_0_SHIFT                                         0
1610     #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0                         (0x1<<16) // Port Arbitration Table Status.
1611     #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_PORT_ARBI_TABLE_STATUS_VC0_SHIFT                   16
1612     #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0                                   (0x1<<17) // VC Negotiation Pending.
1613     #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_VC_NEGO_PENDING_VC0_SHIFT                             17
1614     #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_RSVDP_18                                              (0x3fff<<18) // Reserved for future use.
1615     #define PCIEIP_REG_RESOURCE_STATUS_REG_VC0_RSVDP_18_SHIFT                                        18
1616 #define PCIEIP_REG_VC_CAP_BB_A0                                                                      0x000160UL //Access:R    DataWidth:0x20  The read-back value of this register is controlled by the EXT_CAP_ENA register in the PCI register space.  Chips: BB_A0
1617 #define PCIEIP_REG_VC_CAP_BB_B0                                                                      0x000160UL //Access:R    DataWidth:0x20  The read-back value of this register is controlled by the EXT_CAP_ENA register in the PCI register space.  Chips: BB_B0
1618     #define PCIEIP_REG_VC_CAP_VC_CAP_ID                                                              (0xffff<<0) // Virtual channel Capability ID. Hardwired to 2. Path = cfg_defs
1619     #define PCIEIP_REG_VC_CAP_VC_CAP_ID_SHIFT                                                        0
1620     #define PCIEIP_REG_VC_CAP_VC_CAP_VER                                                             (0xf<<16) // Capability ID Version. These bits are hardwired to 1h indicating the version of the capability ID. Hardwire to 1. Path = cfg_defs
1621     #define PCIEIP_REG_VC_CAP_VC_CAP_VER_SHIFT                                                       16
1622     #define PCIEIP_REG_VC_CAP_VC_NEXT_CAP_OFF                                                        (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
1623     #define PCIEIP_REG_VC_CAP_VC_NEXT_CAP_OFF_SHIFT                                                  20
1624 #define PCIEIP_REG_PORT_VC_CAPABILITY                                                                0x000164UL //Access:R    DataWidth:0x20  Not implemented.  Chips: BB_A0 BB_B0
1625 #define PCIEIP_REG_SN_BASE_K2                                                                        0x000168UL //Access:RW   DataWidth:0x20  Device Serial Number Extended Capability Header.  Chips: K2
1626     #define PCIEIP_REG_SN_BASE_SN_PCIE_EXTENDED_CAP_ID                                               (0xffff<<0) // Serial Number Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1627     #define PCIEIP_REG_SN_BASE_SN_PCIE_EXTENDED_CAP_ID_SHIFT                                         0
1628     #define PCIEIP_REG_SN_BASE_SN_CAP_VERSION                                                        (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1629     #define PCIEIP_REG_SN_BASE_SN_CAP_VERSION_SHIFT                                                  16
1630     #define PCIEIP_REG_SN_BASE_SN_NEXT_OFFSET                                                        (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1631     #define PCIEIP_REG_SN_BASE_SN_NEXT_OFFSET_SHIFT                                                  20
1632 #define PCIEIP_REG_PORT_VC_CAPABILITY2_BB_A0                                                         0x000168UL //Access:R    DataWidth:0x20  Not implemented.  Chips: BB_A0
1633 #define PCIEIP_REG_PORT_VC_CAPABILITY2_BB_B0                                                         0x000168UL //Access:R    DataWidth:0x20  Not implemented.  Chips: BB_B0
1634 #define PCIEIP_REG_SER_NUM_REG_DW_1_K2                                                               0x00016cUL //Access:RW   DataWidth:0x20  Serial Number 1 Register.  Chips: K2
1635 #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_BB_A0                                                      0x00016cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1636 #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_BB_B0                                                      0x00016cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1637     #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_CONTROL                                        (0xffff<<0) // Not implemented.
1638     #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_CONTROL_SHIFT                                  0
1639     #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_STATUS                                         (0xffff<<16) // Not implemented.
1640     #define PCIEIP_REG_PORT_VC_STATUS_CONTROL_PORT_VC_STATUS_SHIFT                                   16
1641 #define PCIEIP_REG_SER_NUM_REG_DW_2_K2                                                               0x000170UL //Access:RW   DataWidth:0x20  Serial Number 2 Register.  Chips: K2
1642 #define PCIEIP_REG_PORT_ARB_TABLE_BB_A0                                                              0x000170UL //Access:R    DataWidth:0x20  Not implemented.  Chips: BB_A0
1643 #define PCIEIP_REG_PORT_ARB_TABLE_BB_B0                                                              0x000170UL //Access:R    DataWidth:0x20  Not implemented.  Chips: BB_B0
1644 #define PCIEIP_REG_VC_RSRC_CONTROL                                                                   0x000174UL //Access:RW   DataWidth:0x20  The read-back value of this register is controlled by the EXT_CAP_ENA register in the PCI register space.  Chips: BB_A0 BB_B0
1645     #define PCIEIP_REG_VC_RSRC_CONTROL_DEFAULT_VC0                                                   (0x1<<0) // This bit is hardwired to one because DUT is only support VC0. Path = i_cfg_func.i_cfg_public.i_cfg_vc_cap
1646     #define PCIEIP_REG_VC_RSRC_CONTROL_DEFAULT_VC0_SHIFT                                             0
1647     #define PCIEIP_REG_VC_RSRC_CONTROL_TC_VC_MAP                                                     (0x7f<<1) // This field indicates the TCs that are mapped to the VC resource. This field is valid for all devices. Note: Bit 0 of this field is read only. It is set to 1 for the default VC0. Path = i_cfg_func.i_cfg_private
1648     #define PCIEIP_REG_VC_RSRC_CONTROL_TC_VC_MAP_SHIFT                                               1
1649     #define PCIEIP_REG_VC_RSRC_CONTROL_UNUSED0                                                       (0x7fffff<<8) //
1650     #define PCIEIP_REG_VC_RSRC_CONTROL_UNUSED0_SHIFT                                                 8
1651     #define PCIEIP_REG_VC_RSRC_CONTROL_VC_ENABLE                                                     (0x1<<31) // Enables virtual channel. This bit is hardwired to 1 for the default VC0 and writing to this filed has no effect. Path = i_cfg_func.i_cfg_public.i_cfg_vc_cap
1652     #define PCIEIP_REG_VC_RSRC_CONTROL_VC_ENABLE_SHIFT                                               31
1653 #define PCIEIP_REG_PB_BASE_K2                                                                        0x000178UL //Access:RW   DataWidth:0x20  Power Budgeting Extended Capability Header.  Chips: K2
1654     #define PCIEIP_REG_PB_BASE_PB_PCIE_EXTENDED_CAP_ID                                               (0xffff<<0) // PB Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1655     #define PCIEIP_REG_PB_BASE_PB_PCIE_EXTENDED_CAP_ID_SHIFT                                         0
1656     #define PCIEIP_REG_PB_BASE_PB_CAP_VERSION                                                        (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1657     #define PCIEIP_REG_PB_BASE_PB_CAP_VERSION_SHIFT                                                  16
1658     #define PCIEIP_REG_PB_BASE_PB_NEXT_OFFSET                                                        (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1659     #define PCIEIP_REG_PB_BASE_PB_NEXT_OFFSET_SHIFT                                                  20
1660 #define PCIEIP_REG_VC_RSRC_STATUS_BB_A0                                                              0x000178UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1661 #define PCIEIP_REG_VC_RSRC_STATUS_BB_B0                                                              0x000178UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1662     #define PCIEIP_REG_VC_RSRC_STATUS_UNUSED0                                                        (0xffff<<0) //
1663     #define PCIEIP_REG_VC_RSRC_STATUS_UNUSED0_SHIFT                                                  0
1664     #define PCIEIP_REG_VC_RSRC_STATUS_VC_RSRC_STATUS                                                 (0xffff<<16) // Not implemented.
1665     #define PCIEIP_REG_VC_RSRC_STATUS_VC_RSRC_STATUS_SHIFT                                           16
1666 #define PCIEIP_REG_PB_DATA_SELECT                                                                    0x00017cUL //Access:RW   DataWidth:0x20  Data select Register.  Chips: K2
1667     #define PCIEIP_REG_PB_DATA_SELECT_PB_DATA_SEL                                                    (0xff<<0) // Data Select Register.
1668     #define PCIEIP_REG_PB_DATA_SELECT_PB_DATA_SEL_SHIFT                                              0
1669     #define PCIEIP_REG_PB_DATA_SELECT_RSVDP_8                                                        (0xffffff<<8) // Reserved for future use.
1670     #define PCIEIP_REG_PB_DATA_SELECT_RSVDP_8_SHIFT                                                  8
1671 #define PCIEIP_REG_DATA_REG_PB_K2                                                                    0x000180UL //Access:R    DataWidth:0x20  Data Register.  Chips: K2
1672     #define PCIEIP_REG_DATA_REG_PB_PB_BASE_POWER                                                     (0xff<<0) // Base Power.
1673     #define PCIEIP_REG_DATA_REG_PB_PB_BASE_POWER_SHIFT                                               0
1674     #define PCIEIP_REG_DATA_REG_PB_PB_DATA_SCALE                                                     (0x3<<8) // Data Scale.
1675     #define PCIEIP_REG_DATA_REG_PB_PB_DATA_SCALE_SHIFT                                               8
1676     #define PCIEIP_REG_DATA_REG_PB_PB_PM_SUB_STATE                                                   (0x7<<10) // PM Sub State.
1677     #define PCIEIP_REG_DATA_REG_PB_PB_PM_SUB_STATE_SHIFT                                             10
1678     #define PCIEIP_REG_DATA_REG_PB_PB_PM_STATE                                                       (0x3<<13) // PM State.
1679     #define PCIEIP_REG_DATA_REG_PB_PB_PM_STATE_SHIFT                                                 13
1680     #define PCIEIP_REG_DATA_REG_PB_PB_TYPE                                                           (0x7<<15) // Type of Operating Condition.
1681     #define PCIEIP_REG_DATA_REG_PB_PB_TYPE_SHIFT                                                     15
1682     #define PCIEIP_REG_DATA_REG_PB_PB_POWER_RAIL_STATE                                               (0x7<<18) // Power Rail State.
1683     #define PCIEIP_REG_DATA_REG_PB_PB_POWER_RAIL_STATE_SHIFT                                         18
1684     #define PCIEIP_REG_DATA_REG_PB_RSVDP_21                                                          (0x7ff<<21) // Reserved for future use.
1685     #define PCIEIP_REG_DATA_REG_PB_RSVDP_21_SHIFT                                                    21
1686 #define PCIEIP_REG_VENDOR_CAP_BB_A0                                                                  0x000180UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting bit 0 of RC_EXT_CAP_ENA for RC. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn in version.v. When supporting SRIOV, this capability is enabled if PCIE_VF_BAR_STRIDE is defined in version.v  Chips: BB_A0
1687 #define PCIEIP_REG_VENDOR_CAP_BB_B0                                                                  0x000180UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting bit 0 of RC_EXT_CAP_ENA for RC. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn in version.v. When supporting SRIOV, this capability is enabled if PCIE_VF_BAR_STRIDE is defined in version.v  Chips: BB_B0
1688     #define PCIEIP_REG_VENDOR_CAP_VENDOR_SPEC_CAP_ID                                                 (0xffff<<0) // Vendor Specific Extended Capability ID. Hardwired to 0xB. Path = cfg_defs
1689     #define PCIEIP_REG_VENDOR_CAP_VENDOR_SPEC_CAP_ID_SHIFT                                           0
1690     #define PCIEIP_REG_VENDOR_CAP_CAP_VER                                                            (0xf<<16) // Vendor Specific Extended Capability version. Hardwired to 0x1. Path = cfg_defs
1691     #define PCIEIP_REG_VENDOR_CAP_CAP_VER_SHIFT                                                      16
1692     #define PCIEIP_REG_VENDOR_CAP_NEXT                                                               (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability. Path = i_cfg_func.i_cfg_public.i_cfg_ep_reg
1693     #define PCIEIP_REG_VENDOR_CAP_NEXT_SHIFT                                                         20
1694 #define PCIEIP_REG_CAP_REG_PB_K2                                                                     0x000184UL //Access:RW   DataWidth:0x20  Power Budget Capability Register.  Chips: K2
1695     #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC                                                       (0x1<<0) // System Allocated PB.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
1696     #define PCIEIP_REG_CAP_REG_PB_PB_SYS_ALLOC_SHIFT                                                 0
1697     #define PCIEIP_REG_CAP_REG_PB_RSVDP_1                                                            (0x7fffffff<<1) // Reserved for future use.
1698     #define PCIEIP_REG_CAP_REG_PB_RSVDP_1_SHIFT                                                      1
1699 #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_BB_A0                                                      0x000184UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting bit 0 of RC_EXT_CAP_ENA for RC. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn in version.v  Chips: BB_A0
1700 #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_BB_B0                                                      0x000184UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 0 of the EXT_CAP_ENA for EP, or setting bit 0 of RC_EXT_CAP_ENA for RC. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn in version.v  Chips: BB_B0
1701     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_ID                                                (0xffff<<0) // VSEC ID. This field is a vendor-defined ID number that indicates the nature and format of the VSEC structure. Software must qualify the Vendor ID before interpreting this field. Path = i_cfg_func.i_cfg_private
1702     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_ID_SHIFT                                          0
1703     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_REV                                               (0xf<<16) // VSEC Rev. This field is a vendor-defined version number that indicates the version of the VSEC structure. Software must qualify the Vendor ID and VSEC ID before interpreting this field. Path = i_cfg_func.i_cfg_private
1704     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_REV_SHIFT                                         16
1705     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH                                            (0xfff<<20) // VSEC Length. This field indicates the number of bytes in the entire VSEC structure, including the PCI Express Enhanced Capability header, the Vendor-Specific header, and the Vendor-Specific Registers. Path = i_cfg_func.i_cfg_private
1706     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_VSEC_LENGTH_SHIFT                                      20
1707 #define PCIEIP_REG_ARI_BASE_K2                                                                       0x000188UL //Access:RW   DataWidth:0x20  ARI Capability Header.  Chips: K2
1708     #define PCIEIP_REG_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID                                             (0xffff<<0) // ARI Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1709     #define PCIEIP_REG_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_SHIFT                                       0
1710     #define PCIEIP_REG_ARI_BASE_ARI_CAP_VERSION                                                      (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1711     #define PCIEIP_REG_ARI_BASE_ARI_CAP_VERSION_SHIFT                                                16
1712     #define PCIEIP_REG_ARI_BASE_ARI_NEXT_OFFSET                                                      (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1713     #define PCIEIP_REG_ARI_BASE_ARI_NEXT_OFFSET_SHIFT                                                20
1714 #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_BB_A0                                                        0x000188UL //Access:RW   DataWidth:0x20  If bit 0 of the EXT_CAP_ENA for EP or bit 0 of RC_EXT_CAP_ENA for RC is reset to '0', reading this register will return all 0's. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn or PCIE_VF_BAR_STRIDE in version.v  Chips: BB_A0
1715 #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_BB_B0                                                        0x000188UL //Access:RW   DataWidth:0x20  If bit 0 of the EXT_CAP_ENA for EP or bit 0 of RC_EXT_CAP_ENA for RC is reset to '0', reading this register will return all 0's. By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining VendorCapOn or PCIE_VF_BAR_STRIDE in version.v  Chips: BB_B0
1716     #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_BITS                                      (0x7fffffff<<0) // This field defines alignment and stride of VF BAR0 address space. The bits are a power of 2 value that multiplies the PF VF Bar0 value to compute the starting address and alignment of the BAR0 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0.
1717     #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_BITS_SHIFT                                0
1718     #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_EN                                        (0x1<<31) // Enable VF Bar0 Stride. When this bit bit is clear, computation of the VF BAR0 offset from the PF SRIOV capability structure is unchanged.
1719     #define PCIEIP_REG_VENDOR_SPECIFIC_REG1_VF_BAR0_STRIDE_EN_SHIFT                                  31
1720 #define PCIEIP_REG_CAP_REG_K2                                                                        0x00018cUL //Access:R    DataWidth:0x20  ARI Capability and Control Register.  Chips: K2
1721     #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP                                                  (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability.
1722     #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_CAP_SHIFT                                            0
1723     #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP                                                   (0x1<<1) // ACS Function Groups Capability.
1724     #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_CAP_SHIFT                                             1
1725     #define PCIEIP_REG_CAP_REG_RSVDP_2                                                               (0x3f<<2) // Reserved for future use.
1726     #define PCIEIP_REG_CAP_REG_RSVDP_2_SHIFT                                                         2
1727     #define PCIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM                                                      (0xff<<8) // Next Function Number.
1728     #define PCIEIP_REG_CAP_REG_ARI_NEXT_FUN_NUM_SHIFT                                                8
1729     #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN                                                   (0x1<<16) // MFVC Function Groups Enable.
1730     #define PCIEIP_REG_CAP_REG_ARI_MFVC_FUN_GRP_EN_SHIFT                                             16
1731     #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN                                                    (0x1<<17) // ACS Function Groups Enable.
1732     #define PCIEIP_REG_CAP_REG_ARI_ACS_FUN_GRP_EN_SHIFT                                              17
1733     #define PCIEIP_REG_CAP_REG_RSVDP_18                                                              (0x3<<18) // Reserved for future use.
1734     #define PCIEIP_REG_CAP_REG_RSVDP_18_SHIFT                                                        18
1735     #define PCIEIP_REG_CAP_REG_ARI_FUN_GRP                                                           (0x7<<20) // Function Group.
1736     #define PCIEIP_REG_CAP_REG_ARI_FUN_GRP_SHIFT                                                     20
1737     #define PCIEIP_REG_CAP_REG_RSVDP_23                                                              (0x1ff<<23) // Reserved for future use.
1738     #define PCIEIP_REG_CAP_REG_RSVDP_23_SHIFT                                                        23
1739 #define PCIEIP_REG_VENDOR_SPECIFIC_REG2_BB_A0                                                        0x00018cUL //Access:R    DataWidth:0x20    Chips: BB_A0
1740 #define PCIEIP_REG_VENDOR_SPECIFIC_REG2_BB_B0                                                        0x00018cUL //Access:R    DataWidth:0x20    Chips: BB_B0
1741 #define PCIEIP_REG_VENDOR_SPECIFIC_REG3                                                              0x000190UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
1742     #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_BITS                                      (0x7fffffff<<0) // This field defines alignment and stride of VF BAR2 address space. The bits are a power of 2 value that multiplies the PF VF Bar2 value to compute the starting address and alignment of the BAR2 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0.
1743     #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_BITS_SHIFT                                0
1744     #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_EN                                        (0x1<<31) // Enable VF Bar2 Stride. When this bit bit is clear, computation of the VF BAR2 offset from the PF SRIOV capability structure is unchanged.
1745     #define PCIEIP_REG_VENDOR_SPECIFIC_REG3_VF_BAR2_STRIDE_EN_SHIFT                                  31
1746 #define PCIEIP_REG_VENDOR_SPECIFIC_REG4                                                              0x000194UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0
1747 #define PCIEIP_REG_SRIOV_BASE_REG_K2                                                                 0x000198UL //Access:RW   DataWidth:0x20  SR-IOV Capability Header. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Chips: K2
1748     #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_PCIE_EXTENDED_CAP_ID                                     (0xffff<<0) // SRIOV Extended Capability ID. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1749     #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_PCIE_EXTENDED_CAP_ID_SHIFT                               0
1750     #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_CAP_VERSION                                              (0xf<<16) // Capability Version. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1751     #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_CAP_VERSION_SHIFT                                        16
1752     #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_NEXT_OFFSET                                              (0xfff<<20) // Next Capability Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1753     #define PCIEIP_REG_SRIOV_BASE_REG_SRIOV_NEXT_OFFSET_SHIFT                                        20
1754 #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_BB_A0                                                        0x000198UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1755 #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_BB_B0                                                        0x000198UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1756     #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_BITS                                      (0x7fffffff<<0) // This field defines alignment and stride of VF BAR4 address space. The bits are a power of 2 value that multiplies the PF VF Bar4 value to compute the starting address and alignment of the BAR4 for each VF. This field may only have 1 bit set.This field is ignored when bit 31 is 0.
1757     #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_BITS_SHIFT                                0
1758     #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_EN                                        (0x1<<31) // Enable VF Bar4 Stride. When this bit bit is clear, computation of the VF BAR4 offset from the PF SRIOV capability structure is unchanged.
1759     #define PCIEIP_REG_VENDOR_SPECIFIC_REG5_VF_BAR4_STRIDE_EN_SHIFT                                  31
1760 #define PCIEIP_REG_CAPABILITIES_REG                                                                  0x00019cUL //Access:RW   DataWidth:0x20  SR-IOV Capability Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Chips: K2
1761     #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP                                       (0x1<<0) // VF Migration Capable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1762     #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_CAP_SHIFT                                 0
1763     #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED                                 (0x1<<1) // ARI Capable Hierarchy Preserved. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
1764     #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_ARI_CAP_HIER_PRESERVED_SHIFT                           1
1765     #define PCIEIP_REG_CAPABILITIES_REG_RSVDP_2                                                      (0x7ffff<<2) // Reserved for future use.
1766     #define PCIEIP_REG_CAPABILITIES_REG_RSVDP_2_SHIFT                                                2
1767     #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_INT_MSG_NUM                               (0x3ff<<21) // VF Migration Interrupt Message Number. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1768     #define PCIEIP_REG_CAPABILITIES_REG_SRIOV_VF_MIGRATION_INT_MSG_NUM_SHIFT                         21
1769     #define PCIEIP_REG_CAPABILITIES_REG_RSVDP_31                                                     (0x1<<31) // Reserved for future use.
1770     #define PCIEIP_REG_CAPABILITIES_REG_RSVDP_31_SHIFT                                               31
1771 #define PCIEIP_REG_STATUS_CONTROL_REG                                                                0x0001a0UL //Access:RW   DataWidth:0x20  SR-IOV Control and Status Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Chips: K2
1772     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE                                            (0x1<<0) // VF Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1773     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_ENABLE_SHIFT                                      0
1774     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE                                  (0x1<<1) // VF Migration Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1775     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_ENABLE_SHIFT                            1
1776     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE                              (0x1<<2) // VF Migration Interrupt Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1777     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MIGRATION_INT_ENABLE_SHIFT                        2
1778     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE                                               (0x1<<3) // VF Memory Space Enable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1779     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_VF_MSE_SHIFT                                         3
1780     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER                                     (0x1<<4) // ARI Capable Hierarchy (Applies to endpoint only). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W but read-value is not always same as write-value
1781     #define PCIEIP_REG_STATUS_CONTROL_REG_SRIOV_ARI_CAPABLE_HIER_SHIFT                               4
1782     #define PCIEIP_REG_STATUS_CONTROL_REG_RSVDP_5                                                    (0x7ffffff<<5) // Reserved for future use.
1783     #define PCIEIP_REG_STATUS_CONTROL_REG_RSVDP_5_SHIFT                                              5
1784 #define PCIEIP_REG_SRIOV_INITIAL_VFS                                                                 0x0001a4UL //Access:RW   DataWidth:0x20  TotalVFs InitialVFs Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Chips: K2
1785     #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_INITIAL_VFS                                           (0xffff<<0) // InitialVFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two InitialVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1786     #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_INITIAL_VFS_SHIFT                                     0
1787     #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_TOTAL_VFS                                             (0xffff<<16) // Total VFs (Max Number of VFs). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
1788     #define PCIEIP_REG_SRIOV_INITIAL_VFS_SRIOV_TOTAL_VFS_SHIFT                                       16
1789 #define PCIEIP_REG_SRIOV_NUM_VFS                                                                     0x0001a8UL //Access:RW   DataWidth:0x20  NumVFs and Function Dependency Link Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.  Chips: K2
1790     #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_NUM_VFS                                                   (0xffff<<0) // Number of Visible VFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: STATUS_CONTROL_REG.SRIOV_VF_ENABLE ? RW : RO
1791     #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_NUM_VFS_SHIFT                                             0
1792     #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_FDL                                                       (0xff<<16) // Functional Dependency Link. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1793     #define PCIEIP_REG_SRIOV_NUM_VFS_SRIOV_FDL_SHIFT                                                 16
1794     #define PCIEIP_REG_SRIOV_NUM_VFS_RSVDP_24                                                        (0xff<<24) // Reserved for future use.
1795     #define PCIEIP_REG_SRIOV_NUM_VFS_RSVDP_24_SHIFT                                                  24
1796 #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION                                                          0x0001acUL //Access:RW   DataWidth:0x20  VF Stride and Offset Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Chips: K2
1797     #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_OFFSET                                      (0xffff<<0) // First VF Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two First VF Offset registers at this address location; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register" determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1798     #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_OFFSET_SHIFT                                0
1799     #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_STRIDE                                      (0xffff<<16) // VF Stride. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two VF Stride registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit of the PF0 "SR-IOV Control Register". determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1800     #define PCIEIP_REG_SRIOV_VF_OFFSET_POSITION_SRIOV_VF_STRIDE_SHIFT                                16
1801 #define PCIEIP_REG_VF_DEVICE_ID_REG_K2                                                               0x0001b0UL //Access:RW   DataWidth:0x20  VF Device ID For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Chips: K2
1802     #define PCIEIP_REG_VF_DEVICE_ID_REG_RSVDP_0                                                      (0xffff<<0) // Reserved for future use.
1803     #define PCIEIP_REG_VF_DEVICE_ID_REG_RSVDP_0_SHIFT                                                0
1804     #define PCIEIP_REG_VF_DEVICE_ID_REG_SRIOV_VF_DEVICE_ID                                           (0xffff<<16) // VF Device ID. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1805     #define PCIEIP_REG_VF_DEVICE_ID_REG_SRIOV_VF_DEVICE_ID_SHIFT                                     16
1806 #define PCIEIP_REG_LTR_CAP_BB_A0                                                                     0x0001b0UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining LTR_ENABLED in version.v and setting bit 5 of EXT_CAP_ENA. This capability when present , will only exist in function 0 of a multi-function device.  Chips: BB_A0
1807 #define PCIEIP_REG_LTR_CAP_BB_B0                                                                     0x0001b0UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP, By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining LTR_ENABLED in version.v and setting bit 5 of EXT_CAP_ENA. This capability when present , will only exist in function 0 of a multi-function device.  Chips: BB_B0
1808     #define PCIEIP_REG_LTR_CAP_LTR_EXT_CAP_ID                                                        (0xffff<<0) // Vendor Specific Extended Capability ID.
1809     #define PCIEIP_REG_LTR_CAP_LTR_EXT_CAP_ID_SHIFT                                                  0
1810     #define PCIEIP_REG_LTR_CAP_CAP_VER                                                               (0xf<<16) // LTR Capability version. Hardwired to 0x1.
1811     #define PCIEIP_REG_LTR_CAP_CAP_VER_SHIFT                                                         16
1812     #define PCIEIP_REG_LTR_CAP_NEXT                                                                  (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
1813     #define PCIEIP_REG_LTR_CAP_NEXT_SHIFT                                                            20
1814 #define PCIEIP_REG_SUP_PAGE_SIZES_REG_K2                                                             0x0001b4UL //Access:RW   DataWidth:0x20  Supported Page Sizes.  Chips: K2
1815 #define PCIEIP_REG_LATENCY_REGISTER_BB_A0                                                            0x0001b4UL //Access:RW   DataWidth:0x20  The RW value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes).  Chips: BB_A0
1816 #define PCIEIP_REG_LATENCY_REGISTER_BB_B0                                                            0x0001b4UL //Access:RW   DataWidth:0x20  The RW value of this register is controlled by setting bit 5 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes).  Chips: BB_B0
1817     #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_VALUE                                         (0x3ff<<0) // Max Snoop Latency Value. Along with Max snoop latency scale field, this register specifies the maximum no-snoop latency that a device is premitted to request. Software should set this to the platforms max supported latency or less.
1818     #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_VALUE_SHIFT                                   0
1819     #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_SCALE                                         (0x7<<10) // Max Snoop Latency Scale. This register provides a scale for the value contained within the max_snoop_late_value field.
1820     #define PCIEIP_REG_LATENCY_REGISTER_MAX_SNOOP_LATE_SCALE_SHIFT                                   10
1821     #define PCIEIP_REG_LATENCY_REGISTER_UNUSED0                                                      (0x7<<13) //
1822     #define PCIEIP_REG_LATENCY_REGISTER_UNUSED0_SHIFT                                                13
1823     #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_VALUE                                      (0x3ff<<16) // Max No Snoop Latency Value. Along with Max No snoop latency scale field, this register specifies the maximum no-snoop latency that a device is premitted to request. Software should set this to the platforms max supported latency or less.
1824     #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_VALUE_SHIFT                                16
1825     #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_SCALE                                      (0x7<<26) // Max No Snoop Latency Scale. This register provides a scale for the value contained within the max_no_snoop_late_value field.
1826     #define PCIEIP_REG_LATENCY_REGISTER_MAX_NO_SNOOP_LATE_SCALE_SHIFT                                26
1827 #define PCIEIP_REG_SYSTEM_PAGE_SIZE_REG_K2                                                           0x0001b8UL //Access:RW   DataWidth:0x20  System Page Size.  Chips: K2
1828 #define PCIEIP_REG_ARI_CAP_BB_A0                                                                     0x0001b8UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining SRIOV in version.v .  Chips: BB_A0
1829 #define PCIEIP_REG_ARI_CAP_BB_B0                                                                     0x0001b8UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining SRIOV in version.v .  Chips: BB_B0
1830     #define PCIEIP_REG_ARI_CAP_ARI_EXT_CAP_ID                                                        (0xffff<<0) // ARI Extended Capability ID. Hardwired to 0xE.
1831     #define PCIEIP_REG_ARI_CAP_ARI_EXT_CAP_ID_SHIFT                                                  0
1832     #define PCIEIP_REG_ARI_CAP_CAP_VER                                                               (0xf<<16) // ARI Capability version. Hardwired to 0x1.
1833     #define PCIEIP_REG_ARI_CAP_CAP_VER_SHIFT                                                         16
1834     #define PCIEIP_REG_ARI_CAP_NEXT                                                                  (0xfff<<20) //
1835     #define PCIEIP_REG_ARI_CAP_NEXT_SHIFT                                                            20
1836 #define PCIEIP_REG_SRIOV_BAR0_REG_K2                                                                 0x0001bcUL //Access:RW   DataWidth:0x20  VF BAR0. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
1837     #define PCIEIP_REG_SRIOV_BAR0_REG_RSVDP_0                                                        (0x1<<0) // Reserved for future use.
1838     #define PCIEIP_REG_SRIOV_BAR0_REG_RSVDP_0_SHIFT                                                  0
1839     #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE                                             (0x3<<1) // VF BAR0 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1840     #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_TYPE_SHIFT                                       1
1841     #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH                                         (0x1<<3) // VF BAR0 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1842     #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_PREFETCH_SHIFT                                   3
1843     #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_START                                            (0xfffffff<<4) // VF BAR0 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
1844     #define PCIEIP_REG_SRIOV_BAR0_REG_SRIOV_VF_BAR0_START_SHIFT                                      4
1845 #define PCIEIP_REG_ARI_CONTROL_REGISTER_BB_A0                                                        0x0001bcUL //Access:R    DataWidth:0x20  The RW value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes).  Chips: BB_A0
1846 #define PCIEIP_REG_ARI_CONTROL_REGISTER_BB_B0                                                        0x0001bcUL //Access:R    DataWidth:0x20  The RW value of this register is controlled by setting bit 6 of the EXT_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes).  Chips: BB_B0
1847     #define PCIEIP_REG_ARI_CONTROL_REGISTER_MFVC_FUNC_GROUP_CAP                                      (0x1<<0) // Hardwired to 0
1848     #define PCIEIP_REG_ARI_CONTROL_REGISTER_MFVC_FUNC_GROUP_CAP_SHIFT                                0
1849     #define PCIEIP_REG_ARI_CONTROL_REGISTER_ACS_FUNC_GROUP_CAP                                       (0x1<<1) // Hardwired to 0
1850     #define PCIEIP_REG_ARI_CONTROL_REGISTER_ACS_FUNC_GROUP_CAP_SHIFT                                 1
1851     #define PCIEIP_REG_ARI_CONTROL_REGISTER_UNUSED0                                                  (0x3f<<2) //
1852     #define PCIEIP_REG_ARI_CONTROL_REGISTER_UNUSED0_SHIFT                                            2
1853     #define PCIEIP_REG_ARI_CONTROL_REGISTER_NEXT_FUNCTION_NUMBER                                     (0xff<<8) // Next Function Number. This field indicates the function number of the next higher numbered function in device. Value reflects programming in ARI_CAP(0x5FC) private register.
1854     #define PCIEIP_REG_ARI_CONTROL_REGISTER_NEXT_FUNCTION_NUMBER_SHIFT                               8
1855     #define PCIEIP_REG_ARI_CONTROL_REGISTER_ARI_CTRL                                                 (0xffff<<16) // Field is unused and is hardwired to 0.
1856     #define PCIEIP_REG_ARI_CONTROL_REGISTER_ARI_CTRL_SHIFT                                           16
1857 #define PCIEIP_REG_SRIOV_BAR1_REG_K2                                                                 0x0001c0UL //Access:RW   DataWidth:0x20  VF BAR1. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
1858     #define PCIEIP_REG_SRIOV_BAR1_REG_RSVDP_0                                                        (0x1<<0) // Reserved for future use.
1859     #define PCIEIP_REG_SRIOV_BAR1_REG_RSVDP_0_SHIFT                                                  0
1860     #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE                                             (0x3<<1) // VF BAR1 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1861     #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_TYPE_SHIFT                                       1
1862     #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH                                         (0x1<<3) // VF BAR1 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1863     #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_PREFETCH_SHIFT                                   3
1864     #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_START                                            (0xfffffff<<4) // VF BAR1 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
1865     #define PCIEIP_REG_SRIOV_BAR1_REG_SRIOV_VF_BAR1_START_SHIFT                                      4
1866 #define PCIEIP_REG_SRIOV_CAP_BB_A0                                                                   0x0001c0UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 7 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining SRIOV in version.v .  Chips: BB_A0
1867 #define PCIEIP_REG_SRIOV_CAP_BB_B0                                                                   0x0001c0UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 7 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining SRIOV in version.v .  Chips: BB_B0
1868     #define PCIEIP_REG_SRIOV_CAP_SRIOV_EXT_CAP_ID                                                    (0xffff<<0) // SRIOV Extended Capability ID. Hardwired to 0xE.
1869     #define PCIEIP_REG_SRIOV_CAP_SRIOV_EXT_CAP_ID_SHIFT                                              0
1870     #define PCIEIP_REG_SRIOV_CAP_SRCAP_VER                                                           (0xf<<16) // SRIOV Capability version. Hardwired to 0x1.
1871     #define PCIEIP_REG_SRIOV_CAP_SRCAP_VER_SHIFT                                                     16
1872     #define PCIEIP_REG_SRIOV_CAP_NEXT                                                                (0xfff<<20) //
1873     #define PCIEIP_REG_SRIOV_CAP_NEXT_SHIFT                                                          20
1874 #define PCIEIP_REG_SRIOV_BAR2_REG_K2                                                                 0x0001c4UL //Access:RW   DataWidth:0x20  VF BAR2. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
1875     #define PCIEIP_REG_SRIOV_BAR2_REG_RSVDP_0                                                        (0x1<<0) // Reserved for future use.
1876     #define PCIEIP_REG_SRIOV_BAR2_REG_RSVDP_0_SHIFT                                                  0
1877     #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE                                             (0x3<<1) // VF BAR2 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1878     #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_TYPE_SHIFT                                       1
1879     #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH                                         (0x1<<3) // VF BAR2 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1880     #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_PREFETCH_SHIFT                                   3
1881     #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_START                                            (0xfffffff<<4) // VF BAR2 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
1882     #define PCIEIP_REG_SRIOV_BAR2_REG_SRIOV_VF_BAR2_START_SHIFT                                      4
1883 #define PCIEIP_REG_SRIOV_CAPABILITIES_BB_A0                                                          0x0001c4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1884 #define PCIEIP_REG_SRIOV_CAPABILITIES_BB_B0                                                          0x0001c4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1885     #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1A                                                  (0x1<<0) // The capability is hardwired to 0.
1886     #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1A_SHIFT                                            0
1887     #define PCIEIP_REG_SRIOV_CAPABILITIES_ARI_CAP_HIER_PRESERVED                                     (0x1<<1) // This field is only present in PF0. This bet when set indicates that the ARI capable hierarchy is preserved across certain power state transitions.
1888     #define PCIEIP_REG_SRIOV_CAPABILITIES_ARI_CAP_HIER_PRESERVED_SHIFT                               1
1889     #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1                                                   (0x3fffffff<<2) // The capability is hardwired to 0.
1890     #define PCIEIP_REG_SRIOV_CAPABILITIES_UNUSED_1_SHIFT                                             2
1891 #define PCIEIP_REG_SRIOV_BAR3_REG_K2                                                                 0x0001c8UL //Access:RW   DataWidth:0x20  VF BAR3. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
1892     #define PCIEIP_REG_SRIOV_BAR3_REG_RSVDP_0                                                        (0x1<<0) // Reserved for future use.
1893     #define PCIEIP_REG_SRIOV_BAR3_REG_RSVDP_0_SHIFT                                                  0
1894     #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE                                             (0x3<<1) // VF BAR3 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1895     #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_TYPE_SHIFT                                       1
1896     #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH                                         (0x1<<3) // VF BAR3 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1897     #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_PREFETCH_SHIFT                                   3
1898     #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_START                                            (0xfffffff<<4) // VF BAR3 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
1899     #define PCIEIP_REG_SRIOV_BAR3_REG_SRIOV_VF_BAR3_START_SHIFT                                      4
1900 #define PCIEIP_REG_SRIOV_CONTROL_BB_A0                                                               0x0001c8UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1901 #define PCIEIP_REG_SRIOV_CONTROL_BB_B0                                                               0x0001c8UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1902     #define PCIEIP_REG_SRIOV_CONTROL_VF_ENABLE                                                       (0x1<<0) // Enables/Disables VFs.
1903     #define PCIEIP_REG_SRIOV_CONTROL_VF_ENABLE_SHIFT                                                 0
1904     #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_EN                                                       (0x1<<1) //
1905     #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_EN_SHIFT                                                 1
1906     #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_INTERR_EN                                                (0x1<<2) // This bit has no effect in IP. However spec has defined it to be RW.
1907     #define PCIEIP_REG_SRIOV_CONTROL_VF_MIG_INTERR_EN_SHIFT                                          2
1908     #define PCIEIP_REG_SRIOV_CONTROL_VF_MSE                                                          (0x1<<3) // When set, memory space is enabled for VFs.
1909     #define PCIEIP_REG_SRIOV_CONTROL_VF_MSE_SHIFT                                                    3
1910     #define PCIEIP_REG_SRIOV_CONTROL_ARI_CAPABLE_HIER                                                (0x1<<4) // When set, the device is permitted to locate VF in Func Number 8 to 255. This field is RW only in PF0 and is RO in all other PFs.
1911     #define PCIEIP_REG_SRIOV_CONTROL_ARI_CAPABLE_HIER_SHIFT                                          4
1912     #define PCIEIP_REG_SRIOV_CONTROL_UNUSED_2                                                        (0x7ff<<5) // The Status is hardwired to 0.
1913     #define PCIEIP_REG_SRIOV_CONTROL_UNUSED_2_SHIFT                                                  5
1914     #define PCIEIP_REG_SRIOV_CONTROL_SRIOV_STATUS                                                    (0xffff<<16) // The Status is hardwired to 0.
1915     #define PCIEIP_REG_SRIOV_CONTROL_SRIOV_STATUS_SHIFT                                              16
1916 #define PCIEIP_REG_SRIOV_BAR4_REG_K2                                                                 0x0001ccUL //Access:RW   DataWidth:0x20  VF BAR4. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
1917     #define PCIEIP_REG_SRIOV_BAR4_REG_RSVDP_0                                                        (0x1<<0) // Reserved for future use.
1918     #define PCIEIP_REG_SRIOV_BAR4_REG_RSVDP_0_SHIFT                                                  0
1919     #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE                                             (0x3<<1) // VF BAR4 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1920     #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_TYPE_SHIFT                                       1
1921     #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH                                         (0x1<<3) // VF BAR4 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1922     #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_PREFETCH_SHIFT                                   3
1923     #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_START                                            (0xfffff<<4) // VF BAR4 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
1924     #define PCIEIP_REG_SRIOV_BAR4_REG_SRIOV_VF_BAR4_START_SHIFT                                      4
1925     #define PCIEIP_REG_SRIOV_BAR4_REG_RSVDP_24                                                       (0xff<<24) // Reserved for future use.
1926     #define PCIEIP_REG_SRIOV_BAR4_REG_RSVDP_24_SHIFT                                                 24
1927 #define PCIEIP_REG_SRIOV_INITIALVF_BB_A0                                                             0x0001ccUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1928 #define PCIEIP_REG_SRIOV_INITIALVF_BB_B0                                                             0x0001ccUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1929     #define PCIEIP_REG_SRIOV_INITIALVF_INITIALVF                                                     (0xffff<<0) // The Value in this register is based on programming in the private space at 0x600. This field indicates the number of VFs that are initially associated with the PF.
1930     #define PCIEIP_REG_SRIOV_INITIALVF_INITIALVF_SHIFT                                               0
1931     #define PCIEIP_REG_SRIOV_INITIALVF_TOTALVF                                                       (0xffff<<16) // The Value in this register is based on programming in the private space at 0x600. This field indicates the maximum number of VFs that could be associated with PF.
1932     #define PCIEIP_REG_SRIOV_INITIALVF_TOTALVF_SHIFT                                                 16
1933 #define PCIEIP_REG_SRIOV_BAR5_REG_K2                                                                 0x0001d0UL //Access:RW   DataWidth:0x20  VF BAR5. This register is used to define the BAR contents (in VF's Type-1 header) for all VFs in this PF. The actual BARs in the VF's Type-1 header are RO and are derived by the core from the SRIOV_VF_BAR*_START field in this register in conjunction with SRIOV_VF_OFFSET and SRIOV_VF_STRIDE. For a fuller description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
1934     #define PCIEIP_REG_SRIOV_BAR5_REG_RSVDP_0                                                        (0x1<<0) // Reserved for future use.
1935     #define PCIEIP_REG_SRIOV_BAR5_REG_RSVDP_0_SHIFT                                                  0
1936     #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE                                             (0x3<<1) // VF BAR5 32 or 64 bit. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1937     #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_TYPE_SHIFT                                       1
1938     #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH                                         (0x1<<3) // VF BAR5 Prefetchable. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: If enabled and (DBI_RO_WR_EN == 1) then R/W else R
1939     #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_PREFETCH_SHIFT                                   3
1940     #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_START                                            (0xfffffff<<4) // VF BAR5 Base Address. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Note: The access attributes of this field are as follows:  - Dbi: R/W
1941     #define PCIEIP_REG_SRIOV_BAR5_REG_SRIOV_VF_BAR5_START_SHIFT                                      4
1942 #define PCIEIP_REG_SRIOV_NUMVF_BB_A0                                                                 0x0001d0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1943 #define PCIEIP_REG_SRIOV_NUMVF_BB_B0                                                                 0x0001d0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1944     #define PCIEIP_REG_SRIOV_NUMVF_NUMVF                                                             (0xffff<<0) // This field controls the number of VFs that are available. S/W sets this as part of creating VF.
1945     #define PCIEIP_REG_SRIOV_NUMVF_NUMVF_SHIFT                                                       0
1946     #define PCIEIP_REG_SRIOV_NUMVF_FUNC_DEPENDENCY_LINK                                              (0xff<<16) // The Value in this register is based on programming in the private space at 0x608.
1947     #define PCIEIP_REG_SRIOV_NUMVF_FUNC_DEPENDENCY_LINK_SHIFT                                        16
1948     #define PCIEIP_REG_SRIOV_NUMVF_RSVD_1                                                            (0xff<<24) //
1949     #define PCIEIP_REG_SRIOV_NUMVF_RSVD_1_SHIFT                                                      24
1950 #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_K2                                                   0x0001d4UL //Access:R    DataWidth:0x20  VF Migration State Array Offset For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Chips: K2
1951     #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_BIR                     (0x7<<0) // VF Migration State BIR. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1952     #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_BIR_SHIFT               0
1953     #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET                  (0x1fffffff<<3) // VF Migration State Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.
1954     #define PCIEIP_REG_VF_MIGRATION_STATE_ARRAY_REG_SRIOV_VF_MIGRATION_STATE_OFFSET_SHIFT            3
1955 #define PCIEIP_REG_SRIOV_VFOFFSET_BB_A0                                                              0x0001d4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1956 #define PCIEIP_REG_SRIOV_VFOFFSET_BB_B0                                                              0x0001d4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1957     #define PCIEIP_REG_SRIOV_VFOFFSET_VF_OFFSET                                                      (0xffff<<0) // The value in this register is based on programming in private space at 0x604. This field defines the Routing ID offset of the first VF associated with the PF. The First VFs RID is calculated by adding this field to the RID of the PF.
1958     #define PCIEIP_REG_SRIOV_VFOFFSET_VF_OFFSET_SHIFT                                                0
1959     #define PCIEIP_REG_SRIOV_VFOFFSET_VF_STRIDE                                                      (0xffff<<16) // This field is hardwired to 1.
1960     #define PCIEIP_REG_SRIOV_VFOFFSET_VF_STRIDE_SHIFT                                                16
1961 #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_K2                                                            0x0001d8UL //Access:RW   DataWidth:0x20  TPH Extended Capability Header.  Chips: K2
1962     #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID                                           (0xffff<<0) // TPH Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1963     #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_SHIFT                                     0
1964     #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER                                           (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1965     #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_SHIFT                                     16
1966     #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR                                          (0xfff<<20) // Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1967     #define PCIEIP_REG_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_SHIFT                                    20
1968 #define PCIEIP_REG_SRIOV_VF_DEVICEID_BB_A0                                                           0x0001d8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
1969 #define PCIEIP_REG_SRIOV_VF_DEVICEID_BB_B0                                                           0x0001d8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
1970     #define PCIEIP_REG_SRIOV_VF_DEVICEID_RESERVED                                                    (0xffff<<0) //
1971     #define PCIEIP_REG_SRIOV_VF_DEVICEID_RESERVED_SHIFT                                              0
1972     #define PCIEIP_REG_SRIOV_VF_DEVICEID_VF_DEVICEID                                                 (0xffff<<16) // The value in this register is based on programming in private space at 0x604. This field contains Device ID for every VF belonging to this PF.
1973     #define PCIEIP_REG_SRIOV_VF_DEVICEID_VF_DEVICEID_SHIFT                                           16
1974 #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_K2                                                            0x0001dcUL //Access:RW   DataWidth:0x20  TPH Requestor Capability Register.   SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.  Chips: K2
1975     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE                                        (0x1<<0) // No ST Mode Supported.
1976     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SHIFT                                  0
1977     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC                                       (0x1<<1) // Interrupt Vector Mode Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1978     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SHIFT                                 1
1979     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC                                       (0x1<<2) // Device Specific Mode Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1980     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SHIFT                                 2
1981     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_RSVDP_3                                                   (0x1f<<3) // Reserved for future use.
1982     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_RSVDP_3_SHIFT                                             3
1983     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH                                      (0x1<<8) // Extended TPH Requester Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1984     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SHIFT                                8
1985     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0                                (0x1<<9) // ST Table Location Bit 0.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1986     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SHIFT                          9
1987     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1                                (0x1<<10) // ST Table Location Bit 1.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
1988     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SHIFT                          10
1989     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_RSVDP_11                                                  (0x1f<<11) // Reserved for future use.
1990     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_RSVDP_11_SHIFT                                            11
1991     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE                                 (0x7ff<<16) // ST Table Size.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R  Note: This register field is sticky.
1992     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SHIFT                           16
1993     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_RSVDP_27                                                  (0x1f<<27) // Reserved for future use.
1994     #define PCIEIP_REG_TPH_REQ_CAP_REG_REG_RSVDP_27_SHIFT                                            27
1995 #define PCIEIP_REG_SRIOV_SUPPORTEDPAGESIZE_BB_A0                                                     0x0001dcUL //Access:R    DataWidth:0x20  This value in this register is based on programming in private space at 0x60C. Default indicates support from 4K to 4M.  Chips: BB_A0
1996 #define PCIEIP_REG_SRIOV_SUPPORTEDPAGESIZE_BB_B0                                                     0x0001dcUL //Access:R    DataWidth:0x20  This value in this register is based on programming in private space at 0x60C. Default indicates support from 4K to 4M.  Chips: BB_B0
1997 #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_K2                                                        0x0001e0UL //Access:RW   DataWidth:0x20  TPH Requestor Control Register.  Chips: K2
1998     #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT                                (0x7<<0) // ST Mode Select.   Note: The access attributes of this field are as follows:  - Dbi: R/W
1999     #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_SHIFT                          0
2000     #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_RSVDP_3                                               (0x1f<<3) // Reserved for future use.
2001     #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_RSVDP_3_SHIFT                                         3
2002     #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN                                   (0x3<<8) // TPH Requester Enable Bit.
2003     #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_SHIFT                             8
2004     #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_RSVDP_10                                              (0x3fffff<<10) // Reserved for future use.
2005     #define PCIEIP_REG_TPH_REQ_CONTROL_REG_REG_RSVDP_10_SHIFT                                        10
2006 #define PCIEIP_REG_SRIOV_SYSTEMPAGESIZE_BB_A0                                                        0x0001e0UL //Access:RW   DataWidth:0x20  Default value is 4K . This field defines the page size system will use to map VFs mem address.  Chips: BB_A0
2007 #define PCIEIP_REG_SRIOV_SYSTEMPAGESIZE_BB_B0                                                        0x0001e0UL //Access:RW   DataWidth:0x20  Default value is 4K . This field defines the page size system will use to map VFs mem address.  Chips: BB_B0
2008 #define PCIEIP_REG_TPH_ST_TABLE_REG_0_K2                                                             0x0001e4UL //Access:RW   DataWidth:0x20  TPH ST Table Register 0.  Chips: K2
2009     #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0                                   (0xff<<0) // ST Table 0 Lower Byte.   Note: The access attributes of this field are as follows:  - Dbi: this field is RW or Tie to 0 by table size configure
2010     #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_SHIFT                             0
2011     #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0                                  (0xff<<8) // ST Table 0 Upper Byte.   Note: The access attributes of this field are as follows:  - Dbi: this field is RW or Tie to 0 by table size configure
2012     #define PCIEIP_REG_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_SHIFT                            8
2013     #define PCIEIP_REG_TPH_ST_TABLE_REG_0_UNUSED_0                                                   (0xffff<<16) // reserved
2014     #define PCIEIP_REG_TPH_ST_TABLE_REG_0_UNUSED_0_SHIFT                                             16
2015 #define PCIEIP_REG_VF_BAR0_BB_A0                                                                     0x0001e4UL //Access:RW   DataWidth:0x20  The 32-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR2 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_A0
2016 #define PCIEIP_REG_VF_BAR0_BB_B0                                                                     0x0001e4UL //Access:RW   DataWidth:0x20  The 32-bit VF_BAR0 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR2 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_B0
2017     #define PCIEIP_REG_VF_BAR0_MEM_SPACE                                                             (0x1<<0) // This bit indicates that VF_BAR0 maps a memory space and is always read as 0.
2018     #define PCIEIP_REG_VF_BAR0_MEM_SPACE_SHIFT                                                       0
2019     #define PCIEIP_REG_VF_BAR0_SPACE_TYPE                                                            (0x3<<1) // These bits indicate that VF_BAR0 may be programmed to map this adapter to anywhere in the 64-bit address space. Bit can be programmed from shadow register(reg 0x608).
2020     #define PCIEIP_REG_VF_BAR0_SPACE_TYPE_SHIFT                                                      1
2021     #define PCIEIP_REG_VF_BAR0_VF_PREFETCH                                                           (0x1<<3) // This bit indicates that the area mapped by VF_BAR0 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x608).
2022     #define PCIEIP_REG_VF_BAR0_VF_PREFETCH_SHIFT                                                     3
2023     #define PCIEIP_REG_VF_BAR0_UNUSED0                                                               (0xff<<4) //
2024     #define PCIEIP_REG_VF_BAR0_UNUSED0_SHIFT                                                         4
2025     #define PCIEIP_REG_VF_BAR0_ADDRESS                                                               (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR1 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR0_SIZE(reg 0x608) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
2026     #define PCIEIP_REG_VF_BAR0_ADDRESS_SHIFT                                                         12
2027 #define PCIEIP_REG_VF_BAR1                                                                           0x0001e8UL //Access:RW   DataWidth:0x20  The 32-bit VF_BAR1 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus.  Chips: BB_A0 BB_B0
2028 #define PCIEIP_REG_VF_BAR2                                                                           0x0001ecUL //Access:RW   DataWidth:0x20  The 32-bit VF_BAR2 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR3 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_A0 BB_B0
2029     #define PCIEIP_REG_VF_BAR2_MEM_SPACE                                                             (0x1<<0) // This bit indicates that VF_BAR2 maps a memory space and is always read as 0.
2030     #define PCIEIP_REG_VF_BAR2_MEM_SPACE_SHIFT                                                       0
2031     #define PCIEIP_REG_VF_BAR2_SPACE_TYPE                                                            (0x3<<1) // These bits indicate that VF_BAR2 may be programmed to map this adapter to anywhere in the 64-bit address space(reg 0x608).
2032     #define PCIEIP_REG_VF_BAR2_SPACE_TYPE_SHIFT                                                      1
2033     #define PCIEIP_REG_VF_BAR2_VF_PREFETCH                                                           (0x1<<3) // This bit indicates that the area mapped by VF_BAR2 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x608).
2034     #define PCIEIP_REG_VF_BAR2_VF_PREFETCH_SHIFT                                                     3
2035     #define PCIEIP_REG_VF_BAR2_UNUSED0                                                               (0xff<<4) //
2036     #define PCIEIP_REG_VF_BAR2_UNUSED0_SHIFT                                                         4
2037     #define PCIEIP_REG_VF_BAR2_ADDRESS                                                               (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR3 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR2_SIZE(reg 0x608) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
2038     #define PCIEIP_REG_VF_BAR2_ADDRESS_SHIFT                                                         12
2039 #define PCIEIP_REG_VF_BAR3                                                                           0x0001f0UL //Access:RW   DataWidth:0x20  The 32-bit VF_BAR3 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus.  Chips: BB_A0 BB_B0
2040 #define PCIEIP_REG_VF_BAR4                                                                           0x0001f4UL //Access:RW   DataWidth:0x20  The 32-bit VF_BAR4 register programs the base address for the memory space mapped by the VFs belonging to this PF. This register can be combined with VF_BAR5 to make a 64-bit address. Each VF BAR describes the amount of address space consumed by a single VF. Path = i_cfg_func.i_cfg_public.i_cfg_dec  Chips: BB_A0 BB_B0
2041     #define PCIEIP_REG_VF_BAR4_MEM_SPACE                                                             (0x1<<0) // This bit indicates that VF_BAR4 maps a memory space and is always read as 0.
2042     #define PCIEIP_REG_VF_BAR4_MEM_SPACE_SHIFT                                                       0
2043     #define PCIEIP_REG_VF_BAR4_SPACE_TYPE                                                            (0x3<<1) // These bits indicate that VF_BAR4 may be programmed to map this adapter to anywhere in the 64-bit address space(reg 0x620).
2044     #define PCIEIP_REG_VF_BAR4_SPACE_TYPE_SHIFT                                                      1
2045     #define PCIEIP_REG_VF_BAR4_VF_PREFETCH                                                           (0x1<<3) // This bit indicates that the area mapped by VF_BAR4 may be pre-fetched or cached by the system without side effects. Bit can be programmed from shadow register(reg 0x620).
2046     #define PCIEIP_REG_VF_BAR4_VF_PREFETCH_SHIFT                                                     3
2047     #define PCIEIP_REG_VF_BAR4_UNUSED0                                                               (0xff<<4) //
2048     #define PCIEIP_REG_VF_BAR4_UNUSED0_SHIFT                                                         4
2049     #define PCIEIP_REG_VF_BAR4_ADDRESS                                                               (0xfffff<<12) // These bits set the address within a 32-bit address space that device will respond in. These bits may be combined with the bits in VF_BAR5 to create a full 64 bit address decode. Only the bits that addresses blocks bigger than the setting in the VFBAR4_SIZE(reg 0x620) value are RW. All lower bits are RO with a value of zero. This value is sticky and only reset by HARD Reset.
2050     #define PCIEIP_REG_VF_BAR4_ADDRESS_SHIFT                                                         12
2051 #define PCIEIP_REG_VF_BAR5                                                                           0x0001f8UL //Access:RW   DataWidth:0x20  The 32-bit VF_BAR5 register programs the upper half of the base address for the memory space mapped by the card onto the PCI bus.  Chips: BB_A0 BB_B0
2052 #define PCIEIP_REG_PTM_EXTENDED_CAP                                                                  0x000200UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP, The capability can be enabled by default by defining PCIE_PTM_SUPP in version.v and setting bit 0 of EXT3_CAP_ENA.  Chips: BB_A0 BB_B0
2053     #define PCIEIP_REG_PTM_EXTENDED_CAP_PTM_EXT_CAP_ID                                               (0xffff<<0) // Vendor Specific Extended Capability ID.
2054     #define PCIEIP_REG_PTM_EXTENDED_CAP_PTM_EXT_CAP_ID_SHIFT                                         0
2055     #define PCIEIP_REG_PTM_EXTENDED_CAP_CAP_VER                                                      (0xf<<16) // PTM Capability version. Hardwired to 0x1.
2056     #define PCIEIP_REG_PTM_EXTENDED_CAP_CAP_VER_SHIFT                                                16
2057     #define PCIEIP_REG_PTM_EXTENDED_CAP_NEXT                                                         (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
2058     #define PCIEIP_REG_PTM_EXTENDED_CAP_NEXT_SHIFT                                                   20
2059 #define PCIEIP_REG_PTM_CAP_REG                                                                       0x000204UL //Access:R    DataWidth:0x20  The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP.  Chips: BB_A0 BB_B0
2060     #define PCIEIP_REG_PTM_CAP_REG_PTM_REQUESTER_CAPABLE                                             (0x1<<0) // Device implements the PTM Requester role.
2061     #define PCIEIP_REG_PTM_CAP_REG_PTM_REQUESTER_CAPABLE_SHIFT                                       0
2062 #define PCIEIP_REG_PTM_CTRL_REG                                                                      0x000208UL //Access:RW   DataWidth:0x20  The RW value of this register is controlled by setting bit 0 of the EXT3_CAP_ENA for EP.  Chips: BB_A0 BB_B0
2063     #define PCIEIP_REG_PTM_CTRL_REG_PTM_ENABLED                                                      (0x1<<0) // When Set, Function is permitted to participate in PTM mechanism
2064     #define PCIEIP_REG_PTM_CTRL_REG_PTM_ENABLED_SHIFT                                                0
2065     #define PCIEIP_REG_PTM_CTRL_REG_ROOT_SELECT                                                      (0x1<<1) // If Set, device is the PTM Root.
2066     #define PCIEIP_REG_PTM_CTRL_REG_ROOT_SELECT_SHIFT                                                1
2067     #define PCIEIP_REG_PTM_CTRL_REG_UNUSED0                                                          (0x3f<<2) //
2068     #define PCIEIP_REG_PTM_CTRL_REG_UNUSED0_SHIFT                                                    2
2069     #define PCIEIP_REG_PTM_CTRL_REG_PTM_EFFECTIVE_GRANULARITY                                        (0xff<<8) // Field provides information on the expected accuracy of the PTM clock. For endpoints, system software programs this field to the value representing the max Local Clock granularity reported by the PTM Root.
2070     #define PCIEIP_REG_PTM_CTRL_REG_PTM_EFFECTIVE_GRANULARITY_SHIFT                                  8
2071 #define PCIEIP_REG_ATS_CAP                                                                           0x000210UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 9 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining ATS_ON in version.v .  Chips: BB_A0 BB_B0
2072     #define PCIEIP_REG_ATS_CAP_ATS_EXT_CAP_ID                                                        (0xffff<<0) // ATS Extended Capability ID. Hardwired to 0xF.
2073     #define PCIEIP_REG_ATS_CAP_ATS_EXT_CAP_ID_SHIFT                                                  0
2074     #define PCIEIP_REG_ATS_CAP_ATSCAP_VER                                                            (0xf<<16) // ATS Capability version. Hardwired to 0x1.
2075     #define PCIEIP_REG_ATS_CAP_ATSCAP_VER_SHIFT                                                      16
2076     #define PCIEIP_REG_ATS_CAP_ATS_NEXT                                                              (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
2077     #define PCIEIP_REG_ATS_CAP_ATS_NEXT_SHIFT                                                        20
2078 #define PCIEIP_REG_ATS_CONTROL                                                                       0x000214UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2079     #define PCIEIP_REG_ATS_CONTROL_ATS_INVLD_QDEPTH                                                  (0x1f<<0) // The number of Invalidate Requests that the function can accept before putting backpressure on the upstream request. the value in this field is controlled by programming in private register at 0x630
2080     #define PCIEIP_REG_ATS_CONTROL_ATS_INVLD_QDEPTH_SHIFT                                            0
2081     #define PCIEIP_REG_ATS_CONTROL_ATS_PAGE_ALIGNED_REQ                                              (0x1<<5) // This bit when set indicates Untranslated Address is always aligned to 4K boundary. the value in this field is controlled by programming in private register at 0x630
2082     #define PCIEIP_REG_ATS_CONTROL_ATS_PAGE_ALIGNED_REQ_SHIFT                                        5
2083     #define PCIEIP_REG_ATS_CONTROL_RSVD_Z                                                            (0x3ff<<6) //
2084     #define PCIEIP_REG_ATS_CONTROL_RSVD_Z_SHIFT                                                      6
2085     #define PCIEIP_REG_ATS_CONTROL_ATS_STU                                                           (0x1f<<16) // The value indicates to the Function, the minimum of 4K byte blocks that is indicated in a Translation Completion or Invalidate Requests. A value of 0 indicates 1 block and a value of 31 indicates 2^31 blocks.
2086     #define PCIEIP_REG_ATS_CONTROL_ATS_STU_SHIFT                                                     16
2087     #define PCIEIP_REG_ATS_CONTROL_RESERVED_Z                                                        (0x3ff<<21) //
2088     #define PCIEIP_REG_ATS_CONTROL_RESERVED_Z_SHIFT                                                  21
2089     #define PCIEIP_REG_ATS_CONTROL_ATS_ENABLE                                                        (0x1<<31) // When set, function is enabled to cache translations.
2090     #define PCIEIP_REG_ATS_CONTROL_ATS_ENABLE_SHIFT                                                  31
2091 #define PCIEIP_REG_RBAR_EXT_CAP                                                                      0x000220UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 8 of the EXT_CAP_ENA for EP, The capability can be enabled by default by defining RESIZE_BAR in version.v .  Chips: BB_A0 BB_B0
2092     #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_EXT_CAP_ID                                                  (0xffff<<0) // RBAR Extended Capability ID. Hardwired to 0x15.
2093     #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_EXT_CAP_ID_SHIFT                                            0
2094     #define PCIEIP_REG_RBAR_EXT_CAP_RBARCAP_VER                                                      (0xf<<16) // RBAR Capability version. Hardwired to 0x1.
2095     #define PCIEIP_REG_RBAR_EXT_CAP_RBARCAP_VER_SHIFT                                                16
2096     #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_NEXT                                                        (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
2097     #define PCIEIP_REG_RBAR_EXT_CAP_RBAR_NEXT_SHIFT                                                  20
2098 #define PCIEIP_REG_RBAR_CAP                                                                          0x000224UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2099     #define PCIEIP_REG_RBAR_CAP_SIZE_CAPABILITY                                                      (0xf<<0) // unused
2100     #define PCIEIP_REG_RBAR_CAP_SIZE_CAPABILITY_SHIFT                                                0
2101     #define PCIEIP_REG_RBAR_CAP_SIZE_1M_CAPABILITY                                                   (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value reflected here is from corresponding bit in private register.
2102     #define PCIEIP_REG_RBAR_CAP_SIZE_1M_CAPABILITY_SHIFT                                             4
2103     #define PCIEIP_REG_RBAR_CAP_SIZE_2M_CAPABILITY                                                   (0x1<<5) // when Set, it indicates function will operate with Bar sized to 2M. Value reflected here is from corresponding bit in private register.
2104     #define PCIEIP_REG_RBAR_CAP_SIZE_2M_CAPABILITY_SHIFT                                             5
2105     #define PCIEIP_REG_RBAR_CAP_SIZE_4M_CAPABILITY                                                   (0x1<<6) // when Set, it indicates function will operate with Bar sized to 4M. Value reflected here is from corresponding bit in private register.
2106     #define PCIEIP_REG_RBAR_CAP_SIZE_4M_CAPABILITY_SHIFT                                             6
2107     #define PCIEIP_REG_RBAR_CAP_SIZE_8M_CAPABILITY                                                   (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value reflected here is from corresponding bit in private register.
2108     #define PCIEIP_REG_RBAR_CAP_SIZE_8M_CAPABILITY_SHIFT                                             7
2109     #define PCIEIP_REG_RBAR_CAP_SIZE_16M_CAPABILITY                                                  (0x1<<8) // when Set, it indicates function will operate with Bar sized to 16M. Value reflected here is from corresponding bit in private register.
2110     #define PCIEIP_REG_RBAR_CAP_SIZE_16M_CAPABILITY_SHIFT                                            8
2111     #define PCIEIP_REG_RBAR_CAP_SIZE_32M_CAPABILITY                                                  (0x1<<9) // when Set, it indicates function will operate with Bar sized to 32M. Value reflected here is from corresponding bit in private register.
2112     #define PCIEIP_REG_RBAR_CAP_SIZE_32M_CAPABILITY_SHIFT                                            9
2113     #define PCIEIP_REG_RBAR_CAP_SIZE_64M_CAPABILITY                                                  (0x1<<10) // when Set, it indicates function will operate with Bar sized to 64M. Value reflected here is from corresponding bit in private register.
2114     #define PCIEIP_REG_RBAR_CAP_SIZE_64M_CAPABILITY_SHIFT                                            10
2115     #define PCIEIP_REG_RBAR_CAP_SIZE_128M_CAPABILITY                                                 (0x1<<11) // when Set, it indicates function will operate with Bar sized to 128M. Value reflected here is from corresponding bit in private register.
2116     #define PCIEIP_REG_RBAR_CAP_SIZE_128M_CAPABILITY_SHIFT                                           11
2117     #define PCIEIP_REG_RBAR_CAP_SIZE_256M_CAPABILITY                                                 (0x1<<12) // when Set, it indicates function will operate with Bar sized to 256M. Value reflected here is from corresponding bit in private register.
2118     #define PCIEIP_REG_RBAR_CAP_SIZE_256M_CAPABILITY_SHIFT                                           12
2119     #define PCIEIP_REG_RBAR_CAP_SIZE_512M_CAPABILITY                                                 (0x1<<13) // when Set, it indicates function will operate with Bar sized to 512M. Value reflected here is from corresponding bit in private register.
2120     #define PCIEIP_REG_RBAR_CAP_SIZE_512M_CAPABILITY_SHIFT                                           13
2121     #define PCIEIP_REG_RBAR_CAP_SIZE_1G_CAPABILITY                                                   (0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value reflected here is from corresponding bit in private register.
2122     #define PCIEIP_REG_RBAR_CAP_SIZE_1G_CAPABILITY_SHIFT                                             14
2123     #define PCIEIP_REG_RBAR_CAP_SIZE_512G_TO_2G_CAPABILITY                                           (0x1ff<<15) // unsupported.
2124     #define PCIEIP_REG_RBAR_CAP_SIZE_512G_TO_2G_CAPABILITY_SHIFT                                     15
2125 #define PCIEIP_REG_RBAR_CTRL                                                                         0x000228UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2126     #define PCIEIP_REG_RBAR_CTRL_RBAR_INDX                                                           (0x7<<0) // Indicates which BAR supports a negotiable size.
2127     #define PCIEIP_REG_RBAR_CTRL_RBAR_INDX_SHIFT                                                     0
2128     #define PCIEIP_REG_RBAR_CTRL_RSVD                                                                (0x3<<3) // Unused
2129     #define PCIEIP_REG_RBAR_CTRL_RSVD_SHIFT                                                          3
2130     #define PCIEIP_REG_RBAR_CTRL_NUM_RBAR                                                            (0x7<<5) // Indicates number of resizeable BARs in capability.
2131     #define PCIEIP_REG_RBAR_CTRL_NUM_RBAR_SHIFT                                                      5
2132     #define PCIEIP_REG_RBAR_CTRL_BAR_SIZE                                                            (0x1f<<8) // When this reg is programmed, value is immediately reflected in the size of the resource, as encoded in the number of RO bits in BAR.
2133     #define PCIEIP_REG_RBAR_CTRL_BAR_SIZE_SHIFT                                                      8
2134 #define PCIEIP_REG_TPH_EXTENDED_CAP                                                                  0x000230UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP, By default, this capability is enabled The capability can be enabled by default by defining TPH_ON in version.v and setting bit 0 of EXT2_CAP_ENA.  Chips: BB_A0 BB_B0
2135     #define PCIEIP_REG_TPH_EXTENDED_CAP_TPH_EXT_CAP_ID                                               (0xffff<<0) // Vendor Specific Extended Capability ID.
2136     #define PCIEIP_REG_TPH_EXTENDED_CAP_TPH_EXT_CAP_ID_SHIFT                                         0
2137     #define PCIEIP_REG_TPH_EXTENDED_CAP_CAP_VER                                                      (0xf<<16) // LTR Capability version. Hardwired to 0x1.
2138     #define PCIEIP_REG_TPH_EXTENDED_CAP_CAP_VER_SHIFT                                                16
2139     #define PCIEIP_REG_TPH_EXTENDED_CAP_NEXT                                                         (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
2140     #define PCIEIP_REG_TPH_EXTENDED_CAP_NEXT_SHIFT                                                   20
2141 #define PCIEIP_REG_TPH_REQ_CAPABILITY                                                                0x000234UL //Access:R    DataWidth:0x20  The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP. By default, this capability is disabled (i.e. reading this register will return zeroes).  Chips: BB_A0 BB_B0
2142     #define PCIEIP_REG_TPH_REQ_CAPABILITY_NO_ST_MODE_SUPPORTED                                       (0x1<<0) // Function supports NO ST mode of operation. This mode is required to be supported.
2143     #define PCIEIP_REG_TPH_REQ_CAPABILITY_NO_ST_MODE_SUPPORTED_SHIFT                                 0
2144     #define PCIEIP_REG_TPH_REQ_CAPABILITY_INT_VECTOR_MODE_SUPPORTED                                  (0x1<<1) // If Set function supports Interrupt Vector mode of operation. Value in this field can be programmed through TPH_CAP register in private space.
2145     #define PCIEIP_REG_TPH_REQ_CAPABILITY_INT_VECTOR_MODE_SUPPORTED_SHIFT                            1
2146     #define PCIEIP_REG_TPH_REQ_CAPABILITY_DEVICE_MODE_SUPPORTED                                      (0x1<<2) // If Set function supports device mode of operation.
2147     #define PCIEIP_REG_TPH_REQ_CAPABILITY_DEVICE_MODE_SUPPORTED_SHIFT                                2
2148     #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED0                                                    (0x1f<<3) //
2149     #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED0_SHIFT                                              3
2150     #define PCIEIP_REG_TPH_REQ_CAPABILITY_EXTENDED_TPH_REQ_SUPP                                      (0x1<<8) // If Set function is capable of generating Req's with TPH TLP prefix.
2151     #define PCIEIP_REG_TPH_REQ_CAPABILITY_EXTENDED_TPH_REQ_SUPP_SHIFT                                8
2152     #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_LOCATION                                          (0x3<<9) // Value indicates if and where the ST table is located. Value in this field can be programmed through TPH_CAP register in private space.
2153     #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_LOCATION_SHIFT                                    9
2154     #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED1                                                    (0x1f<<11) //
2155     #define PCIEIP_REG_TPH_REQ_CAPABILITY_UNUSED1_SHIFT                                              11
2156     #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_SIZE                                              (0x7ff<<16) // Software reads this field to determine the STTable Size N, whihc is encoded as N-1. So a returned value of 16, indicates a table size of 17. The value in this field can be programmed by programming the TPH_CAP register in the private space.
2157     #define PCIEIP_REG_TPH_REQ_CAPABILITY_ST_TABLE_SIZE_SHIFT                                        16
2158 #define PCIEIP_REG_TPH_REQ_CONTROL                                                                   0x000238UL //Access:RW   DataWidth:0x20  The RW value of this register is controlled by setting bit 0 of the EXT2_CAP_ENA for EP.  Chips: BB_A0 BB_B0
2159     #define PCIEIP_REG_TPH_REQ_CONTROL_ST_MODE_SELECT                                                (0x7<<0) // Value indicates ST mode of operation
2160     #define PCIEIP_REG_TPH_REQ_CONTROL_ST_MODE_SELECT_SHIFT                                          0
2161     #define PCIEIP_REG_TPH_REQ_CONTROL_UNUSED0                                                       (0x1f<<3) //
2162     #define PCIEIP_REG_TPH_REQ_CONTROL_UNUSED0_SHIFT                                                 3
2163     #define PCIEIP_REG_TPH_REQ_CONTROL_TPH_REQUESTER_ENABLE                                          (0x3<<8) // Value indicates if and how TPH is enabled
2164     #define PCIEIP_REG_TPH_REQ_CONTROL_TPH_REQUESTER_ENABLE_SHIFT                                    8
2165 #define PCIEIP_REG_PML1SUB_CAPID                                                                     0x000240UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 2 of the EXT2_CAP_ENA for EP, By default, this capability is disabled (i.e. reading this register will return zeroes). The capability can be enabled by default by defining PMCR_L1_SUBSTATES_ENA in version.v and setting bit 2 of EXT2_CAP_ENA. This capability when present , will only exist in function 0 of a multi-function device.  Chips: BB_A0 BB_B0
2166     #define PCIEIP_REG_PML1SUB_CAPID_L1SUB_EXT_CAP_ID                                                (0xffff<<0) // Vendor Specific Extended Capability ID. Value is from corresponding field in private register.
2167     #define PCIEIP_REG_PML1SUB_CAPID_L1SUB_EXT_CAP_ID_SHIFT                                          0
2168     #define PCIEIP_REG_PML1SUB_CAPID_CAP_VER                                                         (0xf<<16) // PM L1 substates Capability version. Value is from corresponding field in private register.
2169     #define PCIEIP_REG_PML1SUB_CAPID_CAP_VER_SHIFT                                                   16
2170     #define PCIEIP_REG_PML1SUB_CAPID_NEXT                                                            (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
2171     #define PCIEIP_REG_PML1SUB_CAPID_NEXT_SHIFT                                                      20
2172 #define PCIEIP_REG_PML1_SUB_CAP_REG                                                                  0x000244UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2173     #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_2_SUPP                                                 (0x1<<0) // Advertize L1_2 capability support for PM
2174     #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_2_SUPP_SHIFT                                           0
2175     #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_1_SUPP                                                 (0x1<<1) // Advertize L1_1 capability support for PM
2176     #define PCIEIP_REG_PML1_SUB_CAP_REG_PM_L1_1_SUPP_SHIFT                                           1
2177     #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_2_SUPP                                               (0x1<<2) // Advertize L1_2 capability support for ASPM
2178     #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_2_SUPP_SHIFT                                         2
2179     #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_1_SUPP                                               (0x1<<3) // Advertize L1_1 capability support for ASPM
2180     #define PCIEIP_REG_PML1_SUB_CAP_REG_ASPM_L1_1_SUPP_SHIFT                                         3
2181     #define PCIEIP_REG_PML1_SUB_CAP_REG_CLKREQ_L1SUB_SUPP                                            (0x1<<4) // Clkreq based L1 substates is supported.
2182     #define PCIEIP_REG_PML1_SUB_CAP_REG_CLKREQ_L1SUB_SUPP_SHIFT                                      4
2183     #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_1                                                   (0x7<<5) //
2184     #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_1_SHIFT                                             5
2185     #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_CMN_MODE_UP_TIME                                       (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
2186     #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_CMN_MODE_UP_TIME_SHIFT                                 8
2187     #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_SCALE                                           (0x3<<16) // Along with the value field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface.
2188     #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_SCALE_SHIFT                                     16
2189     #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_0                                                   (0x1<<18) //
2190     #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_0_SHIFT                                             18
2191     #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_VALUE                                           (0x1f<<19) // Along with the scale field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface.
2192     #define PCIEIP_REG_PML1_SUB_CAP_REG_L1SUB_PWR_ON_VALUE_SHIFT                                     19
2193     #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED                                                     (0xff<<24) //
2194     #define PCIEIP_REG_PML1_SUB_CAP_REG_RESERVED_SHIFT                                               24
2195 #define PCIEIP_REG_PML1_SUB_CONTROL1                                                                 0x000248UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2196     #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_2_ENABLE                                              (0x1<<0) // When set, PM L1.2 is enabled.
2197     #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_2_ENABLE_SHIFT                                        0
2198     #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_1_ENABLE                                              (0x1<<1) // When set, PM L1.1 is enabled.
2199     #define PCIEIP_REG_PML1_SUB_CONTROL1_PM_L1_1_ENABLE_SHIFT                                        1
2200     #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_2_ENABLE                                            (0x1<<2) // When set, ASPM L1.2 is enabled.
2201     #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_2_ENABLE_SHIFT                                      2
2202     #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_1_ENABLE                                            (0x1<<3) // When set, ASPM L1.1 is enabled.
2203     #define PCIEIP_REG_PML1_SUB_CONTROL1_ASPM_L1_1_ENABLE_SHIFT                                      3
2204     #define PCIEIP_REG_PML1_SUB_CONTROL1_L1PM_SUB_MECH                                               (0x1<<4) // Value of 0 is hardwired indicating support for only CLKREQ based PM mechanism.
2205     #define PCIEIP_REG_PML1_SUB_CONTROL1_L1PM_SUB_MECH_SHIFT                                         4
2206     #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED_1                                                  (0x7<<5) //
2207     #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED_1_SHIFT                                            5
2208     #define PCIEIP_REG_PML1_SUB_CONTROL1_COMMON_MODE_RESTORE_TIME                                    (0xff<<8) // For downstream port only.
2209     #define PCIEIP_REG_PML1_SUB_CONTROL1_COMMON_MODE_RESTORE_TIME_SHIFT                              8
2210     #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_VALUE                                    (0x3ff<<16) // Provides a value for the L1_2 LTR threshold
2211     #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_VALUE_SHIFT                              16
2212     #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED                                                    (0x7<<26) // Reserved
2213     #define PCIEIP_REG_PML1_SUB_CONTROL1_RESERVED_SHIFT                                              26
2214     #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_SCALE                                    (0x7<<29) // Provides a scale for the L1_2 LTR threshold value
2215     #define PCIEIP_REG_PML1_SUB_CONTROL1_LTR_L1_2_THRESHOLD_SCALE_SHIFT                              29
2216 #define PCIEIP_REG_PML1_SUB_CONTROL2                                                                 0x00024cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2217     #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_SCALE                                            (0x3<<0) // This field along with value sets the min amount of time that the Port must wait in L1.2 exit after sampling CLKREQ# asserted before actively driving the interface. This field specifies the scale used
2218     #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_SCALE_SHIFT                                      0
2219     #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_A                                                      (0x1<<2) //
2220     #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_A_SHIFT                                                2
2221     #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_VALUE                                            (0x1f<<3) // This field along with scale sets the min amount of time that the Port must wait in L1.2 exit after sampling CLKREQ# asserted before actively driving the interface.
2222     #define PCIEIP_REG_PML1_SUB_CONTROL2_T_POWER_ON_VALUE_SHIFT                                      3
2223     #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD                                                        (0xffffff<<8) //
2224     #define PCIEIP_REG_PML1_SUB_CONTROL2_RSVD_SHIFT                                                  8
2225 #define PCIEIP_REG_LTR_CAP_HDR_REG                                                                   0x000264UL //Access:RW   DataWidth:0x20  LTR Extended Capability Header.  Chips: K2
2226     #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_ID                                                        (0xffff<<0) // LTR Extended Capacity ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2227     #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_ID_SHIFT                                                  0
2228     #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_VERSION                                                   (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2229     #define PCIEIP_REG_LTR_CAP_HDR_REG_CAP_VERSION_SHIFT                                             16
2230     #define PCIEIP_REG_LTR_CAP_HDR_REG_NEXT_OFFSET                                                   (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2231     #define PCIEIP_REG_LTR_CAP_HDR_REG_NEXT_OFFSET_SHIFT                                             20
2232 #define PCIEIP_REG_LTR_LATENCY_REG                                                                   0x000268UL //Access:RW   DataWidth:0x20  LTR Max Snoop and No-Snoop Latency Register.  Chips: K2
2233     #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT                                                 (0x3ff<<0) // Max Snoop Latency Value.
2234     #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SHIFT                                           0
2235     #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE                                           (0x7<<10) // Max Snoop Latency Scale.
2236     #define PCIEIP_REG_LTR_LATENCY_REG_MAX_SNOOP_LAT_SCALE_SHIFT                                     10
2237     #define PCIEIP_REG_LTR_LATENCY_REG_RSVDP_13                                                      (0x7<<13) // Reserved for future use.
2238     #define PCIEIP_REG_LTR_LATENCY_REG_RSVDP_13_SHIFT                                                13
2239     #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT                                              (0x3ff<<16) // Max No-Snoop Latency Value.
2240     #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SHIFT                                        16
2241     #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE                                        (0x7<<26) // Max No-Snoop Latency Scale.
2242     #define PCIEIP_REG_LTR_LATENCY_REG_MAX_NO_SNOOP_LAT_SCALE_SHIFT                                  26
2243     #define PCIEIP_REG_LTR_LATENCY_REG_RSVDP_29                                                      (0x7<<29) // Reserved for future use.
2244     #define PCIEIP_REG_LTR_LATENCY_REG_RSVDP_29_SHIFT                                                29
2245 #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG                                                            0x00026cUL //Access:RW   DataWidth:0x20  Vendor-Specific Extended Capability Header.  Chips: K2
2246     #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID                                        (0xffff<<0) // PCI Express Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2247     #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_EXTENDED_CAP_ID_SHIFT                                  0
2248     #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_CAP_VERSION                                            (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2249     #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_CAP_VERSION_SHIFT                                      16
2250     #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET                                            (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2251     #define PCIEIP_REG_RAS_DES_CAP_HEADER_REG_NEXT_OFFSET_SHIFT                                      20
2252 #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG                                                        0x000270UL //Access:R    DataWidth:0x20  Vendor-Specific Header.  Chips: K2
2253     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID                                            (0xffff<<0) // VSEC ID.
2254     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_ID_SHIFT                                      0
2255     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV                                           (0xf<<16) // VSEC Rev.
2256     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_REV_SHIFT                                     16
2257     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH                                        (0xfff<<20) // VSEC Length.
2258     #define PCIEIP_REG_VENDOR_SPECIFIC_HEADER_REG_VSEC_LENGTH_SHIFT                                  20
2259 #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG                                                         0x000274UL //Access:RW   DataWidth:0x20  Event Counter Control. This is a viewport control register.  - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG viewport register.  - Setting the EVENT_COUNTER_ENABLE field in this register enables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.  - Setting the EVENT_COUNTER_CLEAR field in this register clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.  - Reading the EVENT_COUNTER_STATUS field in this register returns the Enable status of the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register.  Chips: K2
2260     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR                                 (0x3<<0) // Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and you can clear all event counters at once by writing the 'all clear' code. The read value is always '0'.  - 00: no change  - 01: per clear  - 10: no change  - 11: all clear  - Other: reserved
2261     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_CLEAR_SHIFT                           0
2262     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE                                (0x7<<2) // Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default, all event counters are disabled. You can enable/disable a specific Event Counter by writing the 'per event off' or 'per event on' codes. You can enable/disable all event counters by writing the 'all on' or 'all off' codes. The read value is always '0'.  - 000: no change  - 001: per event off  - 010: no change  - 011: per event on  - 100: no change  - 101: all off  - 110: no change  - 111: all on
2263     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_ENABLE_SHIFT                          2
2264     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_RSVDP_5                                             (0x3<<5) // Reserved for future use.
2265     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_RSVDP_5_SHIFT                                       5
2266     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS                                (0x1<<7) // Event Counter Status. This register returns the current value of the Event Counter selected by the following fields:  - EVENT_COUNTER_EVENT_SELECT  - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky.
2267     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_STATUS_SHIFT                          7
2268     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT                           (0xf<<8) // Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register.  - 0x0: Lane0  - 0x1: Lane1  - 0x2: Lane2  - ..  - 0xF: Lane15 Note: This register field is sticky.
2269     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_LANE_SELECT_SHIFT                     8
2270     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_RSVDP_12                                            (0xf<<12) // Reserved for future use.
2271     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_RSVDP_12_SHIFT                                      12
2272     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT                          (0xfff<<16) // Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register.  - 27-24: Group number(4-bit: 0..0x7)  - 23-16: Event number(8-bit: 0..0x13) within the Group For example:  - 0x000: Ebuf Overflow  - 0x001: Ebuf Underrun  - ..  - 0x700: Tx Memory Write  - 0x713: Rx Message TLP For detailed definitions of Group number and Event number, see the RAS DES chapter in the Databook.  Note: This register field is sticky.
2273     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_EVENT_COUNTER_EVENT_SELECT_SHIFT                    16
2274     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_RSVDP_28                                            (0xf<<28) // Reserved for future use.
2275     #define PCIEIP_REG_EVENT_COUNTER_CONTROL_REG_RSVDP_28_SHIFT                                      28
2276 #define PCIEIP_REG_EVENT_COUNTER_DATA_REG                                                            0x000278UL //Access:R    DataWidth:0x20  Event Counter Data. This viewport register returns the data selected by the following fields:  - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG  - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2277 #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG                                                   0x00027cUL //Access:RW   DataWidth:0x20  Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2278     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START                                   (0x1<<0) // Timer Start.  - 0: Start/Restart  - 1: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop.  Note: This register field is sticky.
2279     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIMER_START_SHIFT                             0
2280     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1                                       (0x7f<<1) // Reserved for future use.
2281     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_1_SHIFT                                 1
2282     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT                    (0xff<<8) // Time-based Duration Select. Selects the duration of time-based analysis. When "manual control" is selected and TIMER_START is set to '1', this analysis never stops until TIMER_STOP is set to '0'.  - 0x0: Manual control  - 0x1: 1ms  - 0x2: 10ms  - 0x3: 100ms  - 0x4: 1s  - 0x5: 2s  - 0x6: 4s  - Else: Reserved Note: This register field is sticky.
2283     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_DURATION_SELECT_SHIFT              8
2284     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16                                      (0xff<<16) // Reserved for future use.
2285     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_RSVDP_16_SHIFT                                16
2286     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT                      (0xff<<24) // Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT), and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units:  - Core_clk Cycles. Total time in ps is [Value of TIME_BASED_ANALYSIS_DATA returned when TIME_BASED_REPORT_SELECT=0x00] * TIME_BASED_ANALYSIS_DATA  - Aux_clk Cycles. Total time in ps is [Period of platform specific clock] * TIME_BASED_ANALYSIS_DATA  - Data Bytes. Actual amount of bytes is 16 * TIME_BASED_ANALYSIS_DATA Core_clk Cycles  - 0x00: Duration of 1 cycle  - 0x01: TxL0s  - 0x02: RxL0s  - 0x03: L0  - 0x04: L1 (Rsvd when aux_clk is supplied from the platform specific clock during L1, L1.1 or L1.2)  - 0x07: Configuration/Recovery Aux_clk Cycles  - 0x05: L1.1  - 0x06: L1.2 Data Bytes  - 0x20: Tx TLP Bytes  - 0x21: Rx TLP Bytes  - Else: Rsvd Note: This register field is sticky.
2287     #define PCIEIP_REG_TIME_BASED_ANALYSIS_CONTROL_REG_TIME_BASED_REPORT_SELECT_SHIFT                24
2288 #define PCIEIP_REG_TIME_BASED_ANALYSIS_DATA_REG                                                      0x000280UL //Access:R    DataWidth:0x20  Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2289 #define PCIEIP_REG_EINJ_ENABLE_REG                                                                   0x00029cUL //Access:RW   DataWidth:0x20  Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers:  - 0: CRC Error: EINJ0_CRC_REG  - 1: Sequence Number Error: EINJ1_SEQNUM_REG  - 2: DLLP Error: EINJ2_DLLP_REG   - 3: Symbol DataK Mask Error or Sync Header Error: EINJ3_SYMBOL_REG  - 4: FC Credit Update Error: EINJ4_FC_REG  - 5: TLP Duplicate/Nullify Error: EINJ5_SP_TLP_REG  - 6: Specific TLP Error: EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG After the errors have been inserted by core, it will clear each bit here. For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2290     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE                                       (0x1<<0) // Error Injection0 Enable (CRC Error).  Enables insertion of errors into various CRC.  For more details, see the EINJ0_CRC_REG register.  Note: This register field is sticky.
2291     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION0_ENABLE_SHIFT                                 0
2292     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE                                       (0x1<<1) // Error Injection1 Enable (Sequence Number Error).  Enables insertion of errors into sequence numbers.  For more details, see the EINJ1_SEQNUM_REG register.  Note: This register field is sticky.
2293     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION1_ENABLE_SHIFT                                 1
2294     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE                                       (0x1<<2) // Error Injection2 Enable (DLLP Error).  Enables insertion of DLLP errors.  For more details, see the EINJ2_DLLP_REG register.  Note: This register field is sticky.
2295     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION2_ENABLE_SHIFT                                 2
2296     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE                                       (0x1<<3) // Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error).  Enables DataK masking of special symbols or the breaking of the sync header.  For more details, see the EINJ3_SYMBOL_REG register.  Note: This register field is sticky.
2297     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION3_ENABLE_SHIFT                                 3
2298     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE                                       (0x1<<4) // Error Injection4 Enable (FC Credit Update Error).  Enables insertion of errors into UpdateFCs.  For more details, see the EINJ4_FC_REG register.  Note: This register field is sticky.
2299     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION4_ENABLE_SHIFT                                 4
2300     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE                                       (0x1<<5) // Error Injection5 Enable (TLP Duplicate/Nullify Error).  Enables insertion of duplicate/nullified TLPs.  For more details, see the EINJ5_SP_TLP_REG register.  Note: This register field is sticky.
2301     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION5_ENABLE_SHIFT                                 5
2302     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE                                       (0x1<<6) // Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select.  You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT =0.  You can set this bit to '1' when you have disabled the address translation by setting ADDR_TRANSLATION_SUPPORT_EN=0. For more details, see the EINJ6_COMPARE_*_REG/EINJ6_CHANGE_*_REG/EINJ6_TLP_REG registers.  Note: This register field is sticky.
2303     #define PCIEIP_REG_EINJ_ENABLE_REG_ERROR_INJECTION6_ENABLE_SHIFT                                 6
2304     #define PCIEIP_REG_EINJ_ENABLE_REG_RSVDP_7                                                       (0x1ffffff<<7) // Reserved for future use.
2305     #define PCIEIP_REG_EINJ_ENABLE_REG_RSVDP_7_SHIFT                                                 7
2306 #define PCIEIP_REG_EINJ0_CRC_REG                                                                     0x0002a0UL //Access:RW   DataWidth:0x20  Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC, and parity of ordered sets for the selected type of the packets as follows:  - LCRC. Bad TLP will be detected at the receiver side; receiver responds with NAK DLLP; Data Link Retry starts.  - 16-bit CRC of ACK/NAK DLLPs. Bad DLLP occurs at the receiver side; Replay NUM Rollover occurs.  - 16-bit CRC of UpdateFC DLLPs. Error insertion continues for the specific time; LTSSM transitions to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs).  - ECRC. If ECRC check is enabled, ECRC error is detected at the receiver side.  - FCRC. Framing error will be detected, TLP is discarded, and the LTSSM transitions to Recovery state.  - Parity of TSOS. Error insertion continues for the specific time; LTSSM Recovery/Configuration timeout will occur.  - Parity of SKPOS. Lane error will be detected at the receiver side.  Chips: K2
2307     #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_COUNT                                                     (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b.  - If the counter value is 0x00 and ERROR_INJECTION0_ENABLE=1, the errors are inserted until ERROR_INJECTION0_ENABLE is set to '0'.  Note: This register field is sticky.
2308     #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_COUNT_SHIFT                                               0
2309     #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE                                                  (0xf<<8) // Error injection type. Selects the type of CRC error to be inserted.  Tx Path  - 0000b: New TLP's LCRC error injection  - 0001b: 16bCRC error injection of ACK/NAK DLLP  - 0010b: 16bCRC error injection of Update-FC DLLP  - 0011b: New TLP's ECRC error injection  - 0100b: TLP's FCRC error injection (128b/130b)  - 0101b: Parity error of TSOS (128b/130b)  - 0110b: Parity error of SKPOS (128b/130b) Rx Path  - 1000b: LCRC error injection  - 1011b: ECRC error injection  - Others: Reserved Note: This register field is sticky.
2310     #define PCIEIP_REG_EINJ0_CRC_REG_EINJ0_CRC_TYPE_SHIFT                                            8
2311     #define PCIEIP_REG_EINJ0_CRC_REG_RSVDP_12                                                        (0xfffff<<12) // Reserved for future use.
2312     #define PCIEIP_REG_EINJ0_CRC_REG_RSVDP_12_SHIFT                                                  12
2313 #define PCIEIP_REG_EINJ1_SEQNUM_REG                                                                  0x0002a4UL //Access:RW   DataWidth:0x20  Error Injection Control 1 (Sequence Number Error).  Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true:  - ((NEXT_TRANSMIT_SEQ -1) - AckNak_Seq_Num) mod 4096 > 2048  - (AckNak_Seq_Num - ACKD_SEQ) mod 4096 >= 2048 TLP is treated as Duplicate TLP at the Rx side when all these conditions are true:  - Sequence Number != NEXT_RCV_SEQ  - (NEXT_RCV_SEQ - Sequence Number) mod 4096 <= 2048 TLP is treated as Bad TLP at the Rx side when all these conditions are true:  - Sequence Number != NEXT_RCV_SEQ and  - (NEXT_RCV_SEQ - Sequence Number) mod 4096 > 2048  Chips: K2
2314     #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_COUNT                                                  (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION1_ENABLE=1, the errors are inserted until ERROR_INJECTION1_ENABLE is set to '0'.  Note: This register field is sticky.
2315     #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_COUNT_SHIFT                                            0
2316     #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE                                            (0x1<<8) // Sequence number type. Selects the type of sequence number.  - 0b: Insertion of New TLP's SEQ# error  - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky.
2317     #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_SEQNUM_TYPE_SHIFT                                      8
2318     #define PCIEIP_REG_EINJ1_SEQNUM_REG_RSVDP_9                                                      (0x7f<<9) // Reserved for future use.
2319     #define PCIEIP_REG_EINJ1_SEQNUM_REG_RSVDP_9_SHIFT                                                9
2320     #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM                                             (0x1fff<<16) // Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement.  - 0x0FFF: +4095  - ..  - 0x0002: +2  - 0x0001: +1  - 0x0000: 0  - 0x1FFF: -1  - 0x1FFE: -2  - ..  - 0x1001: -4095 For example:  - Set Type, SEQ# and Count  -- EINJ1_SEQNUM_TYPE =0 (Insert errors into new TLPs)  -- EINJ1_BAD_SEQNUM =0x1FFD (represents -3)  -- EINJ1_COUNT =1  - Enable Error Injection  -- ERROR_INJECTION1_ENABLE =1  - Send a TLP From the Core's Application Interface  -- Assume SEQ#5 is given to the TLP.  - The SEQ# is Changed to #2 by the Error Injection Function in Layer2.  -- 5 + (-3) = 2  - The TLP with SEQ#2 is Transmitted to PCIe Link. Note: This register field is sticky.
2321     #define PCIEIP_REG_EINJ1_SEQNUM_REG_EINJ1_BAD_SEQNUM_SHIFT                                       16
2322     #define PCIEIP_REG_EINJ1_SEQNUM_REG_RSVDP_29                                                     (0x7<<29) // Reserved for future use.
2323     #define PCIEIP_REG_EINJ1_SEQNUM_REG_RSVDP_29_SHIFT                                               29
2324 #define PCIEIP_REG_EINJ2_DLLP_REG                                                                    0x0002a8UL //Access:RW   DataWidth:0x20  Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors:  - If "ACK/NAK DLLP's transmission block" is selected, replay timeout error will occur at the transmitter of the TLPs and then Data Link Retry will occur.  - If "Update FC DLLP's transmission block" is selected, LTSSM will transition to the Recovery state because of the UpdateFC timeout (if the timeout is implemented at the receiver of the UpdateFCs).  - If "Always Transmission for NAK DLLP" is selected, Data Link Retry will occur at the transmitter of the TLPs. Furthermore, Replay NUM Rollover will occur when the transmitter has been requested four times to send the TLP with the same sequence number.  Chips: K2
2325     #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_COUNT                                                    (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and the error is inserted, ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION2_ENABLE =1, the errors are inserted until ERROR_INJECTION2_ENABLE is set to '0'. This register is affected only when EINJ2_DLLP_TYPE =2'10b.  Note: This register field is sticky.
2326     #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_COUNT_SHIFT                                              0
2327     #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE                                                (0x3<<8) // DLLP Type. Selects the type of DLLP errors to be inserted.  - 00b: ACK/NAK DLLP's transmission block  - 01b: Update FC DLLP's transmission block  - 10b: Always Transmission for NAK DLLP  - 11b: Reserved Note: This register field is sticky.
2328     #define PCIEIP_REG_EINJ2_DLLP_REG_EINJ2_DLLP_TYPE_SHIFT                                          8
2329     #define PCIEIP_REG_EINJ2_DLLP_REG_RSVDP_10                                                       (0x3fffff<<10) // Reserved for future use.
2330     #define PCIEIP_REG_EINJ2_DLLP_REG_RSVDP_10_SHIFT                                                 10
2331 #define PCIEIP_REG_EINJ3_SYMBOL_REG                                                                  0x0002acUL //Access:RW   DataWidth:0x20  Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used, this register controls error insertion into the special (K code) symbols.  - If TS1/TS2/FTS/E-Idle/SKP is selected, it affects whole of the ordered set. It might cause timeout of the LTSSM.  - If END/EDB/STP/SDP is selected, TLP/DLLP will be discarded at the receiver side. When 128b/130b encoding is used, this register controls error insertion into the sync-header.  Chips: K2
2332     #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_COUNT                                                  (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION3_ENABLE =1, the errors are inserted until ERROR_INJECTION3_ENABLE is set to '0'.  Note: This register field is sticky.
2333     #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_COUNT_SHIFT                                            0
2334     #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE                                            (0x7<<8) // Error Type. 8b/10b encoding - Mask K symbol.  - 000b: Reserved  - 001b: COM/PAD(TS1 Order set)  - 010b: COM/PAD(TS2 Order set)  - 011b: COM/FTS(FTS Order set)  - 100b: COM/IDL(E-Idle Order set)  - 101b: END/EDB Symbol  - 110b: STP/SDP Symbol  - 111b: COM/SKP(SKP Order set) 128b/130b encoding - Change sync header.  - 000b: Invert sync header  - Others: Reserved Note: This register field is sticky.
2335     #define PCIEIP_REG_EINJ3_SYMBOL_REG_EINJ3_SYMBOL_TYPE_SHIFT                                      8
2336     #define PCIEIP_REG_EINJ3_SYMBOL_REG_RSVDP_11                                                     (0x1fffff<<11) // Reserved for future use.
2337     #define PCIEIP_REG_EINJ3_SYMBOL_REG_RSVDP_11_SHIFT                                               11
2338 #define PCIEIP_REG_EINJ4_FC_REG                                                                      0x0002b0UL //Access:RW   DataWidth:0x20  Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types:  - Posted TLP Header credit  - Non-Posted TLP Header credit  - Completion TLP Header credit  - Posted TLP Data credit  - Non-Posted TLP Data credit  - Completion TLP Data credit These errors are not correctable while error insertion is enabled. Receiver buffer overflow error might occur.  Chips: K2
2339     #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_COUNT                                                      (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION4_ENABLE =1, the errors are inserted until ERROR_INJECTION4_ENABLE is set to '0'.  Note: This register field is sticky.
2340     #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_COUNT_SHIFT                                                0
2341     #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE                                                 (0x7<<8) // Update-FC type. Selects the credit type.  - 000b: Posted TLP Header Credit value control  - 001b: Non-Posted TLP Header Credit value control  - 010b: Completion TLP Header Credit value control  - 011b: Reserved  - 100b: Posted TLP Data Credit value control  - 101b: Non-Posted TLP Data Credit value control  - 110b: Completion TLP Data Credit value control  - 111b: Reserved Note: This register field is sticky.
2342     #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_UPDFC_TYPE_SHIFT                                           8
2343     #define PCIEIP_REG_EINJ4_FC_REG_RSVDP_11                                                         (0x1<<11) // Reserved for future use.
2344     #define PCIEIP_REG_EINJ4_FC_REG_RSVDP_11_SHIFT                                                   11
2345     #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_VC_NUMBER                                                  (0x7<<12) // VC Number. Indicates target VC Number.  Note: This register field is sticky.
2346     #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_VC_NUMBER_SHIFT                                            12
2347     #define PCIEIP_REG_EINJ4_FC_REG_RSVDP_15                                                         (0x1<<15) // Reserved for future use.
2348     #define PCIEIP_REG_EINJ4_FC_REG_RSVDP_15_SHIFT                                                   15
2349     #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE                                            (0x1fff<<16) // Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement.  - 0x0FFF: +4095  - ..  - 0x0002: +2  - 0x0001: +1  - 0x0000: 0  - 0x1FFF: -1  - 0x1FFE: -2  - ..  - 0x1001: -4095 Note: This register field is sticky.
2350     #define PCIEIP_REG_EINJ4_FC_REG_EINJ4_BAD_UPDFC_VALUE_SHIFT                                      16
2351     #define PCIEIP_REG_EINJ4_FC_REG_RSVDP_29                                                         (0x7<<29) // Reserved for future use.
2352     #define PCIEIP_REG_EINJ4_FC_REG_RSVDP_29_SHIFT                                                   29
2353 #define PCIEIP_REG_EINJ5_SP_TLP_REG                                                                  0x0002b4UL //Access:RW   DataWidth:0x20  Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol.  - For Duplicate TLP, the core initiates Data Link Retry by handling ACK DLLP as NAK DLLP. These TLPs will be duplicate TLPs at the receiver side.  - For Nullified TLP, the TLPs that the core transmits are changed into nullified TLPs and the original TLPs are stored in the retry buffer. The receiver of these TLPs will detect the lack of seq# and send NAK DLLP at the next TLP. Then the original TLPs are sent from retry buffer and the data controls are recovered. For 128 bit core or more than 128 bit, the core inserts errors the number of times of EINJ5_COUNT but doesn't ensure that the errors are continuously inserted into TLPs.  Chips: K2
2354     #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_COUNT                                                  (0xff<<0) // Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION5_ENABLE =1, the errors are inserted until ERROR_INJECTION5_ENABLE is set to '0'.  Note: This register field is sticky.
2355     #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_COUNT_SHIFT                                            0
2356     #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP                                          (0x1<<8) // Specified TLP. Selects the specified TLP to be inserted.  - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP.  - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky.
2357     #define PCIEIP_REG_EINJ5_SP_TLP_REG_EINJ5_SPECIFIED_TLP_SHIFT                                    8
2358     #define PCIEIP_REG_EINJ5_SP_TLP_REG_RSVDP_9                                                      (0x7fffff<<9) // Reserved for future use.
2359     #define PCIEIP_REG_EINJ5_SP_TLP_REG_RSVDP_9_SHIFT                                                9
2360 #define PCIEIP_REG_EINJ6_COMPARE_POINT_H0_REG                                                        0x0002b8UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.  Chips: K2
2361 #define PCIEIP_REG_EINJ6_COMPARE_POINT_H1_REG                                                        0x0002bcUL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.  Chips: K2
2362 #define PCIEIP_REG_EINJ6_COMPARE_POINT_H2_REG                                                        0x0002c0UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.  Chips: K2
2363 #define PCIEIP_REG_EINJ6_COMPARE_POINT_H3_REG                                                        0x0002c4UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.  Chips: K2
2364 #define PCIEIP_REG_EINJ6_COMPARE_VALUE_H0_REG                                                        0x0002c8UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.  Chips: K2
2365 #define PCIEIP_REG_EINJ6_COMPARE_VALUE_H1_REG                                                        0x0002ccUL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.  Chips: K2
2366 #define PCIEIP_REG_EINJ6_COMPARE_VALUE_H2_REG                                                        0x0002d0UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.  Chips: K2
2367 #define PCIEIP_REG_EINJ6_COMPARE_VALUE_H3_REG                                                        0x0002d4UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the EINJ6_TLP_REG register.  Chips: K2
2368 #define PCIEIP_REG_EINJ6_CHANGE_POINT_H0_REG                                                         0x0002d8UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.  Chips: K2
2369 #define PCIEIP_REG_EINJ6_CHANGE_POINT_H1_REG                                                         0x0002dcUL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.  Chips: K2
2370 #define PCIEIP_REG_EINJ6_CHANGE_POINT_H2_REG                                                         0x0002e0UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.  Chips: K2
2371 #define PCIEIP_REG_EINJ6_CHANGE_POINT_H3_REG                                                         0x0002e4UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.  Chips: K2
2372 #define PCIEIP_REG_EINJ6_CHANGE_VALUE_H0_REG                                                         0x0002e8UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW0[7:0], TLP_DW0[15:8], TLP_DW0[23:16], TLP_DW0[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.  Chips: K2
2373 #define PCIEIP_REG_EINJ6_CHANGE_VALUE_H1_REG                                                         0x0002ecUL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW1[7:0], TLP_DW1[15:8], TLP_DW1[23:16], TLP_DW1[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.  Chips: K2
2374 #define PCIEIP_REG_EINJ6_CHANGE_VALUE_H2_REG                                                         0x0002f0UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW2[7:0], TLP_DW2[15:8], TLP_DW2[23:16], TLP_DW2[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.  Chips: K2
2375 #define PCIEIP_REG_EINJ6_CHANGE_VALUE_H3_REG                                                         0x0002f4UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register.  Bits [31:0] = TLP_DW3[7:0], TLP_DW3[15:8], TLP_DW3[23:16], TLP_DW3[31:24]  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the EINJ6_TLP_REG register. Only applies when EINJ6_INVERTED_CONTROL in EINJ6_TLP_REG =0.  Chips: K2
2376 #define PCIEIP_REG_EINJ6_TLP_REG                                                                     0x0002f8UL //Access:RW   DataWidth:0x20  Error Injection Control 6 (Packet Error).  The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*).  When all specified bits (in the Tx TLP header and EINJ6_COMPARE_VALUE*) match, the core inserts errors into the TLP. The type and number of errors are specified by the this register.  The Packet Change Point registers (EINJ6_CHANGE_POINT*) specify which Tx TLP header bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*).  The type and number of errors are specified by the this register. Only applies when EINJ6_INVERTED_CONTROL in this register =0. The TLP into that errors are injected will not arrive at the transaction layer of the remote device when all of the following conditions are true.  - Using 128b/130b encoding  - Injecting errors into TLP Length field / TLP digest bit  Chips: K2
2377     #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_COUNT                                                     (0xff<<0) // Error Injection Count.  Indicates the number of errors to insert. This counter is decremented while errors are been inserted.  - If the counter value is 0x01 and error is inserted, ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'.  - If the counter value is 0x00 and ERROR_INJECTION6_ENABLE=1, errors are inserted until ERROR_INJECTION6_ENABLE is set to '0'.  Note: This register field is sticky.
2378     #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_COUNT_SHIFT                                               0
2379     #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL                                          (0x1<<8) // Inverted Error Injection Control.  - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3].  - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. Note: This register field is sticky.
2380     #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_INVERTED_CONTROL_SHIFT                                    8
2381     #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_PACKET_TYPE                                               (0x7<<9) // Packet type.  Selects the TLP packets to inject errors into.  - 0: TLP Header  - 1: TLP Prefix 1st 4-DWORDs  - 2: TLP Prefix 2nd -DWORDs  - Else: Reserved Note: This register field is sticky.
2382     #define PCIEIP_REG_EINJ6_TLP_REG_EINJ6_PACKET_TYPE_SHIFT                                         9
2383     #define PCIEIP_REG_EINJ6_TLP_REG_RSVDP_12                                                        (0xfffff<<12) // Reserved for future use.
2384     #define PCIEIP_REG_EINJ6_TLP_REG_RSVDP_12_SHIFT                                                  12
2385 #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP                                                       0x000300UL //Access:R    DataWidth:0x20  The read-only value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP, The capability can be enabled by default by defining pcieGen3Rate in version.v and setting bit 1 of EXT2_CAP_ENA.  Chips: BB_A0 BB_B0
2386     #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_SECPCIE_EXT_CAP_ID                                (0xffff<<0) // Secondary PCIE Extended Capability ID.
2387     #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_SECPCIE_EXT_CAP_ID_SHIFT                          0
2388     #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_CAP_VER                                           (0xf<<16) // Capability version. Hardwired to 0x1.
2389     #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_CAP_VER_SHIFT                                     16
2390     #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_NEXT                                              (0xfff<<20) // This value continues the PCI capability chain. It's value specified an offset in the PCI address space of the next capability.
2391     #define PCIEIP_REG_SECONDARY_PCIE_EXTENDED_CAP_NEXT_SHIFT                                        20
2392 #define PCIEIP_REG_LINK_CONTROL3                                                                     0x000304UL //Access:R    DataWidth:0x20  The RW value of this register is controlled by setting bit 1 of the EXT2_CAP_ENA for EP.  Chips: BB_A0 BB_B0
2393     #define PCIEIP_REG_LINK_CONTROL3_PERFORM_EQ                                                      (0x1<<0) // N/A to endpoints
2394     #define PCIEIP_REG_LINK_CONTROL3_PERFORM_EQ_SHIFT                                                0
2395     #define PCIEIP_REG_LINK_CONTROL3_LINK_EQ_REQ_INT_EN                                              (0x1<<1) // N/A to endpoints
2396     #define PCIEIP_REG_LINK_CONTROL3_LINK_EQ_REQ_INT_EN_SHIFT                                        1
2397 #define PCIEIP_REG_LANE_ERROR_STATUS                                                                 0x000308UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2398     #define PCIEIP_REG_LANE_ERROR_STATUS_LANE_ERR_STATUS_BITS                                        (0xffff<<0) // Each bit indicates if corresponding PCIE lane detected a lane based error.
2399     #define PCIEIP_REG_LANE_ERROR_STATUS_LANE_ERR_STATUS_BITS_SHIFT                                  0
2400 #define PCIEIP_REG_SD_CONTROL1_REG_K2                                                                0x00030cUL //Access:RW   DataWidth:0x20  Silicon Debug Control 1. For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2401     #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE                                             (0xffff<<0) // Force Detect Lane.  When the FORCE_DETECT_LANE_EN field is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses this value instead.  - 0: Lane0  - 1: Lane1  - 2: Lane2  - ..  - 15: Lane15 Note: This register field is sticky.
2402     #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_SHIFT                                       0
2403     #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN                                          (0x1<<16) // Force Detect Lane Enable.  When this bit is set, the core ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE.  Note: This register field is sticky.
2404     #define PCIEIP_REG_SD_CONTROL1_REG_FORCE_DETECT_LANE_EN_SHIFT                                    16
2405     #define PCIEIP_REG_SD_CONTROL1_REG_RSVDP_17                                                      (0x7<<17) // Reserved for future use.
2406     #define PCIEIP_REG_SD_CONTROL1_REG_RSVDP_17_SHIFT                                                17
2407     #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM                                                   (0x3<<20) // Number of Tx EIOS.  This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The core selects the greater value between this register and the value defined by the PCI-SIG specification.  2.5GT/s, 8.0GT/s or higher:  - 0x0: 1  - 0x1: 4  - 0x2: 8  - 0x3: 16 5.0GT/s:  - 0x0: 2  - 0x1: 8  - 0x2: 16  - 0x3: 32 Note: This register field is sticky.
2408     #define PCIEIP_REG_SD_CONTROL1_REG_TX_EIOS_NUM_SHIFT                                             20
2409     #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL                                            (0x3<<22) // Low Power Entry Interval Time.  Interval Time that the core starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to, RXELECIDLE assertion at the PHY.  - 0x0: 40ns  - 0x1: 160ns  - 0x2: 320ns  - 0x3: 640ns Note: This register field is sticky.
2410     #define PCIEIP_REG_SD_CONTROL1_REG_LOW_POWER_INTERVAL_SHIFT                                      22
2411     #define PCIEIP_REG_SD_CONTROL1_REG_RSVDP_24                                                      (0xff<<24) // Reserved for future use.
2412     #define PCIEIP_REG_SD_CONTROL1_REG_RSVDP_24_SHIFT                                                24
2413 #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_BB_A0                                                   0x00030cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
2414 #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_BB_B0                                                   0x00030cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
2415     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS0                              (0xff<<0) // Applicable only to Upstream component.
2416     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS0_SHIFT                        0
2417     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS0                           (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane0
2418     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS0_SHIFT                     8
2419     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS0                           (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane0
2420     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS0_SHIFT                     12
2421     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED0                                           (0x1<<15) // Reserved
2422     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED0_SHIFT                                     15
2423     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS1                              (0xff<<16) // Applicable only to Upstream component.
2424     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS1_SHIFT                        16
2425     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS1                           (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane1
2426     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS1_SHIFT                     24
2427     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS1                           (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane1
2428     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS1_SHIFT                     28
2429     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED1                                           (0x1<<31) // Reserved
2430     #define PCIEIP_REG_LANE0_1_EQUALIZATION_CTRL_RESERVED1_SHIFT                                     31
2431 #define PCIEIP_REG_SD_CONTROL2_REG_K2                                                                0x000310UL //Access:RW   DataWidth:0x20  Silicon Debug Control 2. For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2432     #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM                                                    (0x1<<0) // Hold and Release LTSSM.  For as long as this register is '1', the core stays in the current LTSSM.  Note: This register field is sticky.
2433     #define PCIEIP_REG_SD_CONTROL2_REG_HOLD_LTSSM_SHIFT                                              0
2434     #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST                                              (0x1<<1) // Recovery Request.  When this bit is set to '1' in L0 or L0s, the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization.
2435     #define PCIEIP_REG_SD_CONTROL2_REG_RECOVERY_REQUEST_SHIFT                                        1
2436     #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN                                          (0x1<<2) // Force LinkDown.  When this bit is set and the core detects REPLY_NUM rolling over 4 times, the LTSSM transitions to Detect State.  Note: This register field is sticky.
2437     #define PCIEIP_REG_SD_CONTROL2_REG_NOACK_FORCE_LINKDOWN_SHIFT                                    2
2438     #define PCIEIP_REG_SD_CONTROL2_REG_RSVDP_3                                                       (0x1f<<3) // Reserved for future use.
2439     #define PCIEIP_REG_SD_CONTROL2_REG_RSVDP_3_SHIFT                                                 3
2440     #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG                                      (0x1<<8) // Direct Recovery.Idle to Configuration.  When this bit is set and the LTSSM is in Recovery Idle State, the LTSSM transitions to Configuration state.  Note: This register field is sticky.
2441     #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_RECIDLE_TO_CONFIG_SHIFT                                8
2442     #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT                                      (0x1<<9) // Direct Polling.Compliance to Detect.  When this bit is set and the LTSSM is in Polling Compliance State, the LTSSM transitions to Detect state.  Note: This register field is sticky.
2443     #define PCIEIP_REG_SD_CONTROL2_REG_DIRECT_POLCOMP_TO_DETECT_SHIFT                                9
2444     #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT                                        (0x1<<10) // Detect Loopback Slave To Exit.  When this bit is set and the LTSSM is in Loopback Slave Active State, the LTSSM transitions to Loopback Slave Exit state.  Note: This register field is sticky.
2445     #define PCIEIP_REG_SD_CONTROL2_REG_DETECT_LPBKSLV_TO_EXIT_SHIFT                                  10
2446     #define PCIEIP_REG_SD_CONTROL2_REG_RSVDP_11                                                      (0x1f<<11) // Reserved for future use.
2447     #define PCIEIP_REG_SD_CONTROL2_REG_RSVDP_11_SHIFT                                                11
2448     #define PCIEIP_REG_SD_CONTROL2_REG_UNUSED_0                                                      (0x1<<16) // reserved
2449     #define PCIEIP_REG_SD_CONTROL2_REG_UNUSED_0_SHIFT                                                16
2450     #define PCIEIP_REG_SD_CONTROL2_REG_RSVDP_17                                                      (0x7fff<<17) // Reserved for future use.
2451     #define PCIEIP_REG_SD_CONTROL2_REG_RSVDP_17_SHIFT                                                17
2452 #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_BB_A0                                                   0x000310UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
2453 #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_BB_B0                                                   0x000310UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
2454     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS2                              (0xff<<0) // Applicable only to Upstream component.
2455     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS2_SHIFT                        0
2456     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS2                           (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane2
2457     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS2_SHIFT                     8
2458     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS2                           (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane2
2459     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS2_SHIFT                     12
2460     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED2                                           (0x1<<15) // Reserved
2461     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED2_SHIFT                                     15
2462     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS3                              (0xff<<16) // Applicable only to Upstream component.
2463     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS3_SHIFT                        16
2464     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS3                           (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane3
2465     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS3_SHIFT                     24
2466     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS3                           (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane3
2467     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS3_SHIFT                     28
2468     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED3                                           (0x1<<31) // Reserved
2469     #define PCIEIP_REG_LANE2_3_EQUALIZATION_CTRL_RESERVED3_SHIFT                                     31
2470 #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL                                                         0x000314UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2471     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS4                              (0xff<<0) // Applicable only to Upstream component.
2472     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS4_SHIFT                        0
2473     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS4                           (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane4
2474     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS4_SHIFT                     8
2475     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS4                           (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane4
2476     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS4_SHIFT                     12
2477     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED4                                           (0x1<<15) // Reserved
2478     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED4_SHIFT                                     15
2479     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS5                              (0xff<<16) // Applicable only to Upstream component.
2480     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS5_SHIFT                        16
2481     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS5                           (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane5
2482     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS5_SHIFT                     24
2483     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS5                           (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane5
2484     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS5_SHIFT                     28
2485     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED5                                           (0x1<<31) // Reserved
2486     #define PCIEIP_REG_LANE4_5_EQUALIZATION_CTRL_RESERVED5_SHIFT                                     31
2487 #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL                                                         0x000318UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
2488     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS6                              (0xff<<0) // Applicable only to Upstream component.
2489     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS6_SHIFT                        0
2490     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS6                           (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane6
2491     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS6_SHIFT                     8
2492     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS6                           (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane6
2493     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS6_SHIFT                     12
2494     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED6                                           (0x1<<15) // Reserved
2495     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED6_SHIFT                                     15
2496     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS7                              (0xff<<16) // Applicable only to Upstream component.
2497     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS7_SHIFT                        16
2498     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS7                           (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane7
2499     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS7_SHIFT                     24
2500     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS7                           (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane7
2501     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS7_SHIFT                     28
2502     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED7                                           (0x1<<31) // Reserved
2503     #define PCIEIP_REG_LANE6_7_EQUALIZATION_CTRL_RESERVED7_SHIFT                                     31
2504 #define PCIEIP_REG_SD_STATUS_L1LANE_REG_K2                                                           0x00031cUL //Access:RW   DataWidth:0x20  Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field:  - LANE_SELECT in SD_CONTROL1_REG For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2505     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT                                              (0xf<<0) // Lane Select.  Lane Select register for Silicon Debug Status Register of Layer1-PerLane.  - 0x0: Lane0  - 0x1: Lane1  - 0x2: Lane2  - ..  - 0xF: Lane15 Note: This register field is sticky.
2506     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_LANE_SELECT_SHIFT                                        0
2507     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_RSVDP_4                                                  (0xfff<<4) // Reserved for future use.
2508     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_RSVDP_4_SHIFT                                            4
2509     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY                                          (0x1<<16) // PIPE:RxPolarity.  Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT).  Note: This register field is sticky.
2510     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXPOLARITY_SHIFT                                    16
2511     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE                                         (0x1<<17) // PIPE:Detect Lane.  Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT).  Note: This register field is sticky.
2512     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_DETECT_LANE_SHIFT                                   17
2513     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID                                             (0x1<<18) // PIPE:RxValid.  Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT).  Note: This register field is sticky.
2514     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXVALID_SHIFT                                       18
2515     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE                                          (0x1<<19) // PIPE:RxElecIdle.  Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT).  Note: This register field is sticky.
2516     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_RXELECIDLE_SHIFT                                    19
2517     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE                                          (0x1<<20) // PIPE:TxElecIdle.  Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT).  Note: This register field is sticky.
2518     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_PIPE_TXELECIDLE_SHIFT                                    20
2519     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_RSVDP_21                                                 (0x7<<21) // Reserved for future use.
2520     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_RSVDP_21_SHIFT                                           21
2521     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_DESKEW_POINTER                                           (0xff<<24) // Deskew Pointer.  Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT).  Note: This register field is sticky.
2522     #define PCIEIP_REG_SD_STATUS_L1LANE_REG_DESKEW_POINTER_SHIFT                                     24
2523 #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_BB_A0                                                   0x00031cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
2524 #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_BB_B0                                                   0x00031cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
2525     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS8                              (0xff<<0) // Applicable only to Upstream component.
2526     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS8_SHIFT                        0
2527     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS8                           (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane8
2528     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS8_SHIFT                     8
2529     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS8                           (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane8
2530     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS8_SHIFT                     12
2531     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED6                                           (0x1<<15) // Reserved
2532     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED6_SHIFT                                     15
2533     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS9                              (0xff<<16) // Applicable only to Upstream component.
2534     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS9_SHIFT                        16
2535     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS9                           (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane9
2536     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS9_SHIFT                     24
2537     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS9                           (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane9
2538     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS9_SHIFT                     28
2539     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED7                                           (0x1<<31) // Reserved
2540     #define PCIEIP_REG_LANE8_9_EQUALIZATION_CTRL_RESERVED7_SHIFT                                     31
2541 #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_K2                                                          0x000320UL //Access:R    DataWidth:0x20  Silicon Debug Status(Layer1 LTSSM). For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2542     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_UNUSED_0                                                (0xff<<0) // reserved
2543     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_UNUSED_0_SHIFT                                          0
2544     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN                                         (0x7<<8) // PIPE:PowerDown.  Indicates PIPE PowerDown signal.  Note: This register field is sticky.
2545     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_PIPE_POWER_DOWN_SHIFT                                   8
2546     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_UNUSED_1                                                (0xf<<11) // reserved
2547     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_UNUSED_1_SHIFT                                          11
2548     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL                                           (0x1<<15) // Lane Reversal Operation.  Receiver detected lane reversal.  This field is only valid in the L0 LTSSM state.  Note: This register field is sticky.
2549     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LANE_REVERSAL_SHIFT                                     15
2550     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE                                          (0xffff<<16) // LTSSM Variable.  Indicates internal LTSSM variables defined in the PCI Express base specification.  C-PCIe Mode:  - 0: directed_speed_change  - 1: changed_speed_recovery  - 2: successful_speed_negotiation  - 3: upconfigure_capable; Set to '1' if both ports advertised the UpConfigure capability in the last Config.Complete.  - 4: select_deemphasis  - 5: start_equalization_w_preset  - 6: equalization_done_8GT_data_rate  - 7: equalization_done_16GT_data_rate  - 15:8: idle_to_rlock_transitioned M-PCIe Mode:  - 0: idle_to_recovery  - 1: recovery_to_configuration Note: This register field is sticky.
2551     #define PCIEIP_REG_SD_STATUS_L1LTSSM_REG_LTSSM_VARIABLE_SHIFT                                    16
2552 #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_BB_A0                                                 0x000320UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
2553 #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_BB_B0                                                 0x000320UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
2554     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS10                           (0xff<<0) // Applicable only to Upstream component.
2555     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS10_SHIFT                     0
2556     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS10                        (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane10
2557     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS10_SHIFT                  8
2558     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS10                        (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane10
2559     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS10_SHIFT                  12
2560     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED10                                        (0x1<<15) // Reserved
2561     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED10_SHIFT                                  15
2562     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS11                           (0xff<<16) // Applicable only to Upstream component.
2563     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS11_SHIFT                     16
2564     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS11                        (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane11
2565     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS11_SHIFT                  24
2566     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS11                        (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane11
2567     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS11_SHIFT                  28
2568     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED11                                        (0x1<<31) // Reserved
2569     #define PCIEIP_REG_LANE10_11_EQUALIZATION_CTRL_RESERVED11_SHIFT                                  31
2570 #define PCIEIP_REG_SD_STATUS_PM_REG_K2                                                               0x000324UL //Access:RW   DataWidth:0x20  Silicon Debug Status(PM). For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2571     #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE                                           (0x1f<<0) // Internal PM State(Master).  Indicates internal state machine of Power Management Master controller.  - 0h: S_IDLE  - 1h: S_RESPOND_NAK  - 2h: S_BLOCK_TLP  - 3h: S_WAIT_LAST_TLP_ACK  - 4h: S_WAIT_EIDLE  - 5h: S_LINK_ENTR_L1  - 6h: S_L1  - 7h: S_L1_EXIT  - 8h: S_L23RDY  - 9h: S_LINK_ENTR_L23  - Ah: S_L23RDY_WAIT4ALIVE  - Bh: S_ACK_WAIT4IDLE Note: This register field is sticky.
2572     #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_MSTATE_SHIFT                                     0
2573     #define PCIEIP_REG_SD_STATUS_PM_REG_RSVDP_5                                                      (0x7<<5) // Reserved for future use.
2574     #define PCIEIP_REG_SD_STATUS_PM_REG_RSVDP_5_SHIFT                                                5
2575     #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE                                           (0xf<<8) // Internal PM State(Slave).  Indicates internal state machine of Power Management Slave controller.  - 00h: IDLE  - 01h: L0  - 02h: L0S  - 03h: ENTER_L0S  - 04h: L0S_EXIT  - 08h: L1  - 09h: L1_BLOCK_TLP  - 0Ah: L1_WAIT_LAST_TLP_ACK  - 0Bh: L1_WAIT_PMDLLP_ACK  - 0Ch: L1_LINK_ENTR_L1  - 0Dh: L1_EXIT  - 0Fh: PREP_4L1  - 10h: L23_BLOCK_TLP  - 11h: L23_WAIT_LAST_TLP_ACK  - 12h: L23_WAIT_PMDLLP_ACK  - 13h: L23_ENTR_L23  - 14h: L23RDY  - 15h: PREP_4L23  - 16h: L23RDY_WAIT4ALIVE  - 17h: L0S_BLOCK_TLP Note: This register field is sticky.
2576     #define PCIEIP_REG_SD_STATUS_PM_REG_INTERNAL_PM_SSTATE_SHIFT                                     8
2577     #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG                                              (0x1<<12) // PME Re-send flag.  When the DUT sends a PM_PME message TLP, the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%), the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent.
2578     #define PCIEIP_REG_SD_STATUS_PM_REG_PME_RESEND_FLAG_SHIFT                                        12
2579     #define PCIEIP_REG_SD_STATUS_PM_REG_UNUSED_0                                                     (0x7<<13) // reserved
2580     #define PCIEIP_REG_SD_STATUS_PM_REG_UNUSED_0_SHIFT                                               13
2581     #define PCIEIP_REG_SD_STATUS_PM_REG_LATCHED_NFTS                                                 (0xff<<16) // Latched N_FTS.  Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner  Note: This register field is sticky.
2582     #define PCIEIP_REG_SD_STATUS_PM_REG_LATCHED_NFTS_SHIFT                                           16
2583     #define PCIEIP_REG_SD_STATUS_PM_REG_RSVDP_24                                                     (0xff<<24) // Reserved for future use.
2584     #define PCIEIP_REG_SD_STATUS_PM_REG_RSVDP_24_SHIFT                                               24
2585 #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_BB_A0                                                 0x000324UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
2586 #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_BB_B0                                                 0x000324UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
2587     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS12                           (0xff<<0) // Applicable only to Upstream component.
2588     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS12_SHIFT                     0
2589     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS12                        (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane12
2590     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS12_SHIFT                  8
2591     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS12                        (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane12
2592     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS12_SHIFT                  12
2593     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED12                                        (0x1<<15) // Reserved
2594     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED12_SHIFT                                  15
2595     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS13                           (0xff<<16) // Applicable only to Upstream component.
2596     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS13_SHIFT                     16
2597     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS13                        (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane13
2598     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS13_SHIFT                  24
2599     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS13                        (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane13
2600     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS13_SHIFT                  28
2601     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED13                                        (0x1<<31) // Reserved
2602     #define PCIEIP_REG_LANE12_13_EQUALIZATION_CTRL_RESERVED13_SHIFT                                  31
2603 #define PCIEIP_REG_SD_STATUS_L2_REG_K2                                                               0x000328UL //Access:R    DataWidth:0x20  Silicon Debug Status(Layer2). For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2604     #define PCIEIP_REG_SD_STATUS_L2_REG_TX_TLP_SEQ_NO                                                (0xfff<<0) // Tx Tlp Sequence Number.  Indicates next transmit sequence number for transmit TLP.  Note: This register field is sticky.
2605     #define PCIEIP_REG_SD_STATUS_L2_REG_TX_TLP_SEQ_NO_SHIFT                                          0
2606     #define PCIEIP_REG_SD_STATUS_L2_REG_RX_ACK_SEQ_NO                                                (0xfff<<12) // Tx Ack Sequence Number.  Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP.  Note: This register field is sticky.
2607     #define PCIEIP_REG_SD_STATUS_L2_REG_RX_ACK_SEQ_NO_SHIFT                                          12
2608     #define PCIEIP_REG_SD_STATUS_L2_REG_DLCMSM                                                       (0x3<<24) // DLCMSM.  Indicates the current DLCMSM.  - 00b: DL_INACTIVE  - 01b: DL_FC_INIT  - 11b: DL_ACTIVE Note: This register field is sticky.
2609     #define PCIEIP_REG_SD_STATUS_L2_REG_DLCMSM_SHIFT                                                 24
2610     #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1                                                     (0x1<<26) // FC_INIT1.  Indicates the core is in FC_INIT1(VC0) state.  Note: This register field is sticky.
2611     #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT1_SHIFT                                               26
2612     #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2                                                     (0x1<<27) // FC_INIT2. Indicates the core is in FC_INIT2(VC0) state.  Note: This register field is sticky.
2613     #define PCIEIP_REG_SD_STATUS_L2_REG_FC_INIT2_SHIFT                                               27
2614     #define PCIEIP_REG_SD_STATUS_L2_REG_RSVDP_28                                                     (0xf<<28) // Reserved for future use.
2615     #define PCIEIP_REG_SD_STATUS_L2_REG_RSVDP_28_SHIFT                                               28
2616 #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_BB_A0                                                 0x000328UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0
2617 #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_BB_B0                                                 0x000328UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_B0
2618     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS14                           (0xff<<0) // Applicable only to Upstream component.
2619     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS14_SHIFT                     0
2620     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS14                        (0xf<<8) // Latest Transmitter Preset Requested from Upstream Component on Lane14
2621     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS14_SHIFT                  8
2622     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS14                        (0x7<<12) // Latest Receiver Preset Requested from Upstream Component on Lane14
2623     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS14_SHIFT                  12
2624     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED14                                        (0x1<<15) // Reserved
2625     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED14_SHIFT                                  15
2626     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS15                           (0xff<<16) // Applicable only to Upstream component.
2627     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_UPSTREAM_COMP_PRESETS15_SHIFT                     16
2628     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS15                        (0xf<<24) // Latest Transmitter Preset Requested from Upstream Component on Lane15
2629     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_TX_PRESETS15_SHIFT                  24
2630     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS15                        (0x7<<28) // Latest Receiver Preset Requested from Upstream Component on Lane15
2631     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_DNSTREAM_COMP_RX_PRESETS15_SHIFT                  28
2632     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED15                                        (0x1<<31) // Reserved
2633     #define PCIEIP_REG_LANE14_15_EQUALIZATION_CTRL_RESERVED15_SHIFT                                  31
2634 #define PCIEIP_REG_SD_STATUS_L3FC_REG                                                                0x00032cUL //Access:RW   DataWidth:0x20  Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields:  - CREDIT_SEL_VC  - CREDIT_SEL_CREDIT_TYPE  - CREDIT_SEL_TLP_TYPE  - CREDIT_SEL_HD For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2635     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC                                              (0x7<<0) // Credit Select(VC).  This field in conjunction with the CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.  - 0x0: VC0  - 0x1: VC1  - 0x2: VC2  - ..  - 0x7: VC7 Note: This register field is sticky.
2636     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_VC_SHIFT                                        0
2637     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE                                     (0x1<<3) // Credit Select(Credit Type).  This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.  - 0x0: Rx  - 0x1: Tx Note: This register field is sticky.
2638     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_CREDIT_TYPE_SHIFT                               3
2639     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE                                        (0x3<<4) // Credit Select(TLP Type).  This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.  - 0x0: Posted  - 0x1: Non-Posted  - 0x2: Completion Note: This register field is sticky.
2640     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_TLP_TYPE_SHIFT                                  4
2641     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD                                              (0x1<<6) // Credit Select(HeaderData).  This field in conjunction with the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields.  - 0x0: Header Credit  - 0x1: Data Credit Note: This register field is sticky.
2642     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_SEL_HD_SHIFT                                        6
2643     #define PCIEIP_REG_SD_STATUS_L3FC_REG_RSVDP_7                                                    (0x1<<7) // Reserved for future use.
2644     #define PCIEIP_REG_SD_STATUS_L3FC_REG_RSVDP_7_SHIFT                                              7
2645     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0                                               (0xfff<<8) // Credit Data0.  Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields.  - Rx: Credit Received Value  - Tx: Credit Consumed Value Note: This register field is sticky.
2646     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA0_SHIFT                                         8
2647     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA1                                               (0xfff<<20) // Credit Data1.  Current FC credit data selected by the CREDIT_SEL_VC, CREDIT_SEL_CREDIT_TYPE, CREDIT_SEL_TLP_TYPE, and CREDIT_SEL_HD viewport-select fields.  - Rx: Credit Allocated Value  - Tx: Credit Limit Value. This value is valid when DLCMSM=0x3(DL_ACTIVE). Note: This register field is sticky.
2648     #define PCIEIP_REG_SD_STATUS_L3FC_REG_CREDIT_DATA1_SHIFT                                         20
2649 #define PCIEIP_REG_SD_STATUS_L3_REG                                                                  0x000330UL //Access:RW   DataWidth:0x20  Silicon Debug Status(Layer3). For more details, see the RAS DES section in the Core Operations chapter of the Databook.  Chips: K2
2650     #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_POINTER                                                (0x7f<<0) // First Malformed TLP Error Pointer.  Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS.  - 01h: AtomicOp address alignment  - 02h: AtomicOp operand  - 03h: AtomicOp  byte enable  - 04h: TLP length miss match  - 05h: Max payload size  - 06h: Message TLP without TC0  - 07h: Invalid TC  - 08h: Unexpected route bit in Message TLP  - 09h: Unexpected CRS status in Completion TLP  - 0Ah: Byte enable  - 0Bh: Memory Address 4KB boundary  - 0Ch: TLP prefix rules  - 0Dh: Translation request rules  - 0Eh: Invalid TLP type  - 0Fh: Completion rules  - 7Fh: Application  - Else: Reserved Note: This register field is sticky.
2651     #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_POINTER_SHIFT                                          0
2652     #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS                                                 (0x1<<7) // Malformed TLP Status.  Indicates malformed TLP has occurred.
2653     #define PCIEIP_REG_SD_STATUS_L3_REG_MFTLP_STATUS_SHIFT                                           7
2654     #define PCIEIP_REG_SD_STATUS_L3_REG_RSVDP_8                                                      (0xffffff<<8) // Reserved for future use.
2655     #define PCIEIP_REG_SD_STATUS_L3_REG_RSVDP_8_SHIFT                                                8
2656 #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF                                                             0x00036cUL //Access:RW   DataWidth:0x20  PCIe Extended capability ID, Capability version and Next capability offset.  Chips: K2
2657     #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_ID                                                      (0xffff<<0) // PCI Express Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2658     #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_ID_SHIFT                                                0
2659     #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_CAP                                                     (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2660     #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_CAP_SHIFT                                               16
2661     #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET                                             (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2662     #define PCIEIP_REG_RASDP_EXT_CAP_HDR_OFF_NEXT_OFFSET_SHIFT                                       20
2663 #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF                                                     0x000370UL //Access:R    DataWidth:0x20  Vendor Specific Header.  Chips: K2
2664     #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID                                         (0xffff<<0) // VSEC ID.   Note: This register field is sticky.
2665     #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_ID_SHIFT                                   0
2666     #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV                                        (0xf<<16) // VSEC Rev.   Note: This register field is sticky.
2667     #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_REV_SHIFT                                  16
2668     #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH                                     (0xfff<<20) // VSEC Length.   Note: This register field is sticky.
2669     #define PCIEIP_REG_RASDP_VENDOR_SPECIFIC_HDR_OFF_VSEC_LENGTH_SHIFT                               20
2670 #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF                                                         0x000374UL //Access:RW   DataWidth:0x20  ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath.  When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native core clock (core_clk), you must not write this register while operations are in progress in the AXI master / slave interface.  Chips: K2
2671     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX                               (0x1<<0) // Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.  Note: This register field is sticky.
2672     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_TX_SHIFT                         0
2673     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER                (0x1<<1) // Error correction disable for AXI bridge master completion buffer.  Note: This register field is sticky.
2674     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER_SHIFT          1
2675     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND              (0x1<<2) // Error correction disable for AXI bridge outbound request path.  Note: This register field is sticky.
2676     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND_SHIFT        2
2677     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE                        (0x1<<3) // Error correction disable for DMA write engine.  Note: This register field is sticky.
2678     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_WRITE_SHIFT                  3
2679     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX                        (0x1<<4) // Error correction disable for layer 2 Tx path.  Note: This register field is sticky.
2680     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_TX_SHIFT                  4
2681     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX                        (0x1<<5) // Error correction disable for layer 3 Tx path.  Note: This register field is sticky.
2682     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_TX_SHIFT                  5
2683     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX                           (0x1<<6) // Error correction disable for Adm Tx path.  Note: This register field is sticky.
2684     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_TX_SHIFT                     6
2685     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_7                                             (0x1ff<<7) // Reserved for future use.
2686     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_7_SHIFT                                       7
2687     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX                               (0x1<<16) // Global error correction disable for all Rx layers.  Note: This register field is sticky.
2688     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_RX_SHIFT                         16
2689     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION    (0x1<<17) // Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors.  Note: This register field is sticky.
2690     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION_SHIFT 17
2691     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST       (0x1<<18) // Error correction disable for AXI bridge inbound request path.  Note: This register field is sticky.
2692     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST_SHIFT 18
2693     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ                         (0x1<<19) // Error correction disable for DMA read engine.  Note: This register field is sticky.
2694     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_DMA_READ_SHIFT                   19
2695     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX                        (0x1<<20) // Error correction disable for layer 2 Rx path.  Note: This register field is sticky.
2696     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER2_RX_SHIFT                  20
2697     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX                        (0x1<<21) // Error correction disable for layer 3 Rx path.  Note: This register field is sticky.
2698     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_LAYER3_RX_SHIFT                  21
2699     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX                           (0x1<<22) // Error correction disable for ADM Rx path.  Note: This register field is sticky.
2700     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_ERROR_PROT_DISABLE_ADM_RX_SHIFT                     22
2701     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_23                                            (0x1ff<<23) // Reserved for future use.
2702     #define PCIEIP_REG_RASDP_ERROR_PROT_CTRL_OFF_RSVDP_23_SHIFT                                      23
2703 #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF                                                       0x000378UL //Access:RW   DataWidth:0x20  Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_CORR_COUNT_REPORT_OFF viewport data register.  Chips: K2
2704     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS                               (0x1<<0) // Clear all correctable error counters.
2705     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_CLEAR_COUNTERS_SHIFT                         0
2706     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1                                           (0x7<<1) // Reserved for future use.
2707     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_1_SHIFT                                     1
2708     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS                                  (0x1<<4) // Enable correctable errors counters.  - 1: counters increment when the core detects a correctable error  - 0: counters are frozen The counters are enabled by default.
2709     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_EN_COUNTERS_SHIFT                            4
2710     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5                                           (0x7fff<<5) // Reserved for future use.
2711     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_RSVDP_5_SHIFT                                     5
2712     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION                     (0xf<<20) // Select correctable counter region:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
2713     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_REGION_SHIFT               20
2714     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION                            (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
2715     #define PCIEIP_REG_RASDP_CORR_COUNTER_CTRL_OFF_CORR_COUNTER_SELECTION_SHIFT                      24
2716 #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF                                                       0x00037cUL //Access:R    DataWidth:0x20  Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register.  Chips: K2
2717     #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER                                      (0xff<<0) // Current corrected error count for the selected counter.
2718     #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SHIFT                                0
2719     #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8                                           (0xfff<<8) // Reserved for future use.
2720     #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_RSVDP_8_SHIFT                                     8
2721     #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION                      (0xf<<20) // Selected correctable counter region:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
2722     #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_REGION_SHIFT                20
2723     #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED                             (0xff<<24) // Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register.
2724     #define PCIEIP_REG_RASDP_CORR_COUNT_REPORT_OFF_CORR_COUNTER_SELECTED_SHIFT                       24
2725 #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF                                                     0x000380UL //Access:RW   DataWidth:0x20  Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the counter data returned by the RASDP_UNCORR_COUNT_REPORT_OFF viewport data register.  Chips: K2
2726     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS                           (0x1<<0) // Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared.
2727     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_CLEAR_COUNTERS_SHIFT                     0
2728     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1                                         (0x7<<1) // Reserved for future use.
2729     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_1_SHIFT                                   1
2730     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS                              (0x1<<4) // Enable uncorrectable errors counters.  - 1: enables the counters to increment on detected correctable errors  - 0: counters are frozen The counters are enabled by default.
2731     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_EN_COUNTERS_SHIFT                        4
2732     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5                                         (0x7fff<<5) // Reserved for future use.
2733     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_RSVDP_5_SHIFT                                   5
2734     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION                 (0xf<<20) // Select uncorrectable counter region:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
2735     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_REGION_SHIFT           20
2736     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION                        (0xff<<24) // Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
2737     #define PCIEIP_REG_RASDP_UNCORR_COUNTER_CTRL_OFF_UNCORR_COUNTER_SELECTION_SHIFT                  24
2738 #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF                                                     0x000384UL //Access:R    DataWidth:0x20  Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF register.  Chips: K2
2739     #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER                                  (0xff<<0) // Current uncorrected error count for the selected counter
2740     #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SHIFT                            0
2741     #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8                                         (0xfff<<8) // Reserved for future use.
2742     #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_RSVDP_8_SHIFT                                   8
2743     #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION                  (0xf<<20) // Selected uncorrectable counter region:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
2744     #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_REGION_SHIFT            20
2745     #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED                         (0xff<<24) // Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register.
2746     #define PCIEIP_REG_RASDP_UNCORR_COUNT_REPORT_OFF_UNCORR_COUNTER_SELECTED_SHIFT                   24
2747 #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF                                                          0x000388UL //Access:RW   DataWidth:0x20  Error injection control for the following features:  - 1-bit or 2-bit injection  - Continuous or fixed-number (n) injection modes  - Global enable/disable  - Selectable location where injection occurs  Chips: K2
2748     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN                                         (0x1<<0) // Error injection global enable. When set enables the error insertion logic.
2749     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_EN_SHIFT                                   0
2750     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1                                              (0x7<<1) // Reserved for future use.
2751     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_1_SHIFT                                        1
2752     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE                                       (0x3<<4) // Error injection type:  - 0: none  - 1: 1-bit  - 2: 2-bit
2753     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_TYPE_SHIFT                                 4
2754     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6                                              (0x3<<6) // Reserved for future use.
2755     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_6_SHIFT                                        6
2756     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT                                      (0xff<<8) // Error injection count.  - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN.  - 1: one errors injected
2757     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_COUNT_SHIFT                                8
2758     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC                                        (0xff<<16) // Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
2759     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_ERROR_INJ_LOC_SHIFT                                  16
2760     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24                                             (0xff<<24) // Reserved for future use.
2761     #define PCIEIP_REG_RASDP_ERROR_INJ_CTRL_OFF_RSVDP_24_SHIFT                                       24
2762 #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF                                                     0x00038cUL //Access:R    DataWidth:0x20  Corrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.  Chips: K2
2763     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0                                         (0xf<<0) // Reserved for future use.
2764     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_0_SHIFT                                   0
2765     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR                            (0xf<<4) // Region of the first corrected error:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
2766     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_FIRST_CORR_ERROR_SHIFT                      4
2767     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR                            (0xff<<8) // Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR.  You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
2768     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_FIRST_CORR_ERROR_SHIFT                      8
2769     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16                                        (0xf<<16) // Reserved for future use.
2770     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_RSVDP_16_SHIFT                                  16
2771     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR                             (0xf<<20) // Region of the last corrected error:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
2772     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_REG_LAST_CORR_ERROR_SHIFT                       20
2773     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR                             (0xff<<24) // Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR.  You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
2774     #define PCIEIP_REG_RASDP_CORR_ERROR_LOCATION_OFF_LOC_LAST_CORR_ERROR_SHIFT                       24
2775 #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF                                                   0x000390UL //Access:R    DataWidth:0x20  Uncorrected errors locations. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.  Chips: K2
2776     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0                                       (0xf<<0) // Reserved for future use.
2777     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_0_SHIFT                                 0
2778     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR                        (0xf<<4) // Region of the first uncorrected error:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
2779     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_FIRST_UNCORR_ERROR_SHIFT                  4
2780     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR                        (0xff<<8) // Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR.  You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
2781     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_FIRST_UNCORR_ERROR_SHIFT                  8
2782     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16                                      (0xf<<16) // Reserved for future use.
2783     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_RSVDP_16_SHIFT                                16
2784     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR                         (0xf<<20) // Region of the last uncorrected error:  - 0x0: Region select for Adm Rx path  - 0x1: Region select for layer 3 Rx path  - 0x2: Region select for layer 2 Rx path  - 0x3: Region select for DMA inbound path  - 0x4: Region select for AXI bridge inbound request path  - 0x5: Region select for AXI bridge inbound completion composer path  - 0x6: Region select for Adm Tx path  - 0x7: Region select for layer 3 Tx path  - 0x8: Region select for layer 2 Tx path  - 0x9: Region select for DMA outbound path  - 0xa: Region select for AXI bridge outbound request path  - 0xb: Region select for AXI bridge outbound master completion buffer path  - 0xc: Reserved  - 0xf: Reserved
2785     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_REG_LAST_UNCORR_ERROR_SHIFT                   20
2786     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR                         (0xff<<24) // Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR.  You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at http://www.synopsys.com/dw/doc.php/iip/DWC_pcie/latest/doc/RASDP_CheckPoints.pdf
2787     #define PCIEIP_REG_RASDP_UNCORR_ERROR_LOCATION_OFF_LOC_LAST_UNCORR_ERROR_SHIFT                   24
2788 #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF                                                           0x000394UL //Access:RW   DataWidth:0x20  RASDP error mode enable. The core enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode:  - Rx TLPs that are forwarded to your application are not guaranteed to be correct; you must discard them. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.  Chips: K2
2789     #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN                                         (0x1<<0) // Write '1' to enable the core enter RASDP error mode when it detects an uncorrectable error.  Note: This register field is sticky.
2790     #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_ERROR_MODE_EN_SHIFT                                   0
2791     #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN                                     (0x1<<1) // Write '1' to enable the core to bring the link down when the core enters RASDP error mode.  Note: This register field is sticky.
2792     #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_AUTO_LINK_DOWN_EN_SHIFT                               1
2793     #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_RSVDP_2                                               (0x3fffffff<<2) // Reserved for future use.
2794     #define PCIEIP_REG_RASDP_ERROR_MODE_EN_OFF_RSVDP_2_SHIFT                                         2
2795 #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF                                                        0x000398UL //Access:RW   DataWidth:0x20  Exit RASDP error mode. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.  Chips: K2
2796     #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR                                   (0x1<<0) // Write '1' to take the core out of RASDP error mode. The core will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs.
2797     #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_ERROR_MODE_CLEAR_SHIFT                             0
2798     #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1                                            (0x7fffffff<<1) // Reserved for future use.
2799     #define PCIEIP_REG_RASDP_ERROR_MODE_CLEAR_OFF_RSVDP_1_SHIFT                                      1
2800 #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF                                                     0x00039cUL //Access:R    DataWidth:0x20  RAM Address where a corrected error (1-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.  Chips: K2
2801     #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR                             (0x7ffffff<<0) // RAM Address where a corrected error (1-bit ECC) has been detected.
2802     #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_ADDR_CORR_ERROR_SHIFT                       0
2803     #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27                                        (0x1<<27) // Reserved for future use.
2804     #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RSVDP_27_SHIFT                                  27
2805     #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR                            (0xf<<28) // RAM index where a corrected error (1-bit ECC) has been detected.
2806     #define PCIEIP_REG_RASDP_RAM_ADDR_CORR_ERROR_OFF_RAM_INDEX_CORR_ERROR_SHIFT                      28
2807 #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF                                                   0x0003a0UL //Access:R    DataWidth:0x20  RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details, see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook.  Chips: K2
2808     #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR                         (0x7ffffff<<0) // RAM Address where an uncorrected error (2-bit ECC) has been detected.
2809     #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_ADDR_UNCORR_ERROR_SHIFT                   0
2810     #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27                                      (0x1<<27) // Reserved for future use.
2811     #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RSVDP_27_SHIFT                                27
2812     #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR                        (0xf<<28) // RAM index where an uncorrected error (2-bit ECC) has been detected.
2813     #define PCIEIP_REG_RASDP_RAM_ADDR_UNCORR_ERROR_OFF_RAM_INDEX_UNCORR_ERROR_SHIFT                  28
2814 #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF                                                               0x0003a4UL //Access:RW   DataWidth:0x20  Precision Time Measurement Capability Header. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Chips: K2
2815     #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_ID                                                (0xffff<<0) // Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2816     #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_ID_SHIFT                                          0
2817     #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_VERSION                                           (0xf<<16) // Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2818     #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_CAP_VERSION_SHIFT                                     16
2819     #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_NEXT_OFFSET                                           (0xfff<<20) // Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2820     #define PCIEIP_REG_PTM_EXT_CAP_HDR_OFF_PTM_NEXT_OFFSET_SHIFT                                     20
2821 #define PCIEIP_REG_PTM_CAP_OFF                                                                       0x0003a8UL //Access:RW   DataWidth:0x20  PTM Capability Register. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Chips: K2
2822     #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE                                                   (0x1<<0) // PTM Requester Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2823     #define PCIEIP_REG_PTM_CAP_OFF_PTM_REQ_CAPABLE_SHIFT                                             0
2824     #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE                                                   (0x1<<1) // PTM Responder Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2825     #define PCIEIP_REG_PTM_CAP_OFF_PTM_RES_CAPABLE_SHIFT                                             1
2826     #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE                                                  (0x1<<2) // PTM Root Capable. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2827     #define PCIEIP_REG_PTM_CAP_OFF_PTM_ROOT_CAPABLE_SHIFT                                            2
2828     #define PCIEIP_REG_PTM_CAP_OFF_RSVDP_3                                                           (0x1f<<3) // Reserved for future use.
2829     #define PCIEIP_REG_PTM_CAP_OFF_RSVDP_3_SHIFT                                                     3
2830     #define PCIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN                                                      (0xff<<8) // PTM Local Clock Granularity. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
2831     #define PCIEIP_REG_PTM_CAP_OFF_PTM_CLK_GRAN_SHIFT                                                8
2832     #define PCIEIP_REG_PTM_CAP_OFF_RSVDP_16                                                          (0xffff<<16) // Reserved for future use.
2833     #define PCIEIP_REG_PTM_CAP_OFF_RSVDP_16_SHIFT                                                    16
2834 #define PCIEIP_REG_PTM_CONTROL_OFF                                                                   0x0003acUL //Access:RW   DataWidth:0x20  PTM Control Register. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Chips: K2
2835     #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE                                                    (0x1<<0) // PTM Enable. When set, this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.
2836     #define PCIEIP_REG_PTM_CONTROL_OFF_PTM_ENABLE_SHIFT                                              0
2837     #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT                                                   (0x1<<1) // PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: HWINIT
2838     #define PCIEIP_REG_PTM_CONTROL_OFF_ROOT_SELECT_SHIFT                                             1
2839     #define PCIEIP_REG_PTM_CONTROL_OFF_RSVDP_2                                                       (0x3f<<2) // Reserved for future use.
2840     #define PCIEIP_REG_PTM_CONTROL_OFF_RSVDP_2_SHIFT                                                 2
2841     #define PCIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN                                                      (0xff<<8) // PTM Effective Granularity. For a description of this standard PCIe register, see the PCI Express Base Specification 3.0.  Note: The access attributes of this field are as follows:  - Dbi: HWINIT
2842     #define PCIEIP_REG_PTM_CONTROL_OFF_EFF_GRAN_SHIFT                                                8
2843     #define PCIEIP_REG_PTM_CONTROL_OFF_RSVDP_16                                                      (0xffff<<16) // Reserved for future use.
2844     #define PCIEIP_REG_PTM_CONTROL_OFF_RSVDP_16_SHIFT                                                16
2845 #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF                                                               0x0003b0UL //Access:RW   DataWidth:0x20  Precision Time Measurement Requester Capability Header (VSEC). For more details, see the PTM section in the Databook.  Chips: K2
2846     #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_ID                                        (0xffff<<0) // Precision Time Measurement Requester VSEC ID. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2847     #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_ID_SHIFT                                  0
2848     #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_VER                                       (0xf<<16) // Precision Time Measurement Requester VSEC Version. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2849     #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_VER_SHIFT                                 16
2850     #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_NEXT_OFFS                                 (0xfff<<20) // Precision Time Measurement Requester VSEC Next Pointer. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2851     #define PCIEIP_REG_PTM_REQ_CAP_HDR_OFF_PTM_REQ_EXT_CAP_NEXT_OFFS_SHIFT                           20
2852 #define PCIEIP_REG_PTM_REQ_HDR_OFF                                                                   0x0003b4UL //Access:RW   DataWidth:0x20  Precision Time Measurement Requester Vendor Specific Header. For more details, see the PTM section in the Databook.  Chips: K2
2853     #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_ID                                               (0xffff<<0) // PTM Requester VSEC ID. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2854     #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_ID_SHIFT                                         0
2855     #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_REV                                              (0xf<<16) // PTM Requester VSEC Revision. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2856     #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_REV_SHIFT                                        16
2857     #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_LENGTH                                           (0xfff<<20) // PTM Requester VSEC Length. For more details, see the PTM section in the Databook.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2858     #define PCIEIP_REG_PTM_REQ_HDR_OFF_PTM_REQ_VSEC_LENGTH_SHIFT                                     20
2859 #define PCIEIP_REG_PTM_REQ_CONTROL_OFF                                                               0x0003b8UL //Access:RW   DataWidth:0x20  PTM Requester Vendor Specific Control Register. For more details, see the PTM section in the Databook.  Chips: K2
2860     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED                               (0x1<<0) // PTM Requester Auto Update Enabled - When enabled PTM Requester will automatically atempt to update it's context every 10ms. For more details, see the PTM section in the Databook.  Note: This register field is sticky.
2861     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_AUTO_UPDATE_ENABLED_SHIFT                         0
2862     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE                                      (0x1<<1) // PTM Requester Start Update - When set the PTM Requester will attempt a PTM Dialogue to update it's context; This bit is self clearing. For more details, see the PTM section in the Databook.
2863     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_START_UPDATE_SHIFT                                1
2864     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS                                       (0x1<<2) // PTM Fast Timers - Debug mode for PTM Timers. The 100us timer output will go high at 30us and the 10ms timer output will go high at 100us (The Long Timer Value is ignored). There is no change to the 1us timer. The requester operation will otherwise remain the same. For more details, see the PTM section in the Databook.  Note: This register field is sticky.
2865     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_FAST_TIMERS_SHIFT                                 2
2866     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_RSVDP_3                                                   (0x1f<<3) // Reserved for future use.
2867     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_RSVDP_3_SHIFT                                             3
2868     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER                                        (0xff<<8) // PTM Requester Long Timer - Determines the period between each auto update PTM Dialogue in miliseconds. Update period is the register value +1 milisecond. For the Switch product this value must not be set larger than 0x9 for spec compliance. For more details, see the PTM section in the Databook.  Note: This register field is sticky.
2869     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_PTM_REQ_LONG_TIMER_SHIFT                                  8
2870     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_RSVDP_16                                                  (0xffff<<16) // Reserved for future use.
2871     #define PCIEIP_REG_PTM_REQ_CONTROL_OFF_RSVDP_16_SHIFT                                            16
2872 #define PCIEIP_REG_PTM_REQ_STATUS_OFF                                                                0x0003bcUL //Access:R    DataWidth:0x20  PTM Requester Vendor Specific Status Register. For more details, see the PTM section in the Databook.  Chips: K2
2873     #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID                                      (0x1<<0) // PTM Requester Context Valid - Indicate that the Timing Context is valid. For more details, see the PTM section in the Databook.
2874     #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_CONTEXT_VALID_SHIFT                                0
2875     #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED                              (0x1<<1) // PTM Requester Manual Update Allowed - Indicates whether or not a Manual Update can be signalled. For more details, see the PTM section in the Databook.
2876     #define PCIEIP_REG_PTM_REQ_STATUS_OFF_PTM_REQ_MANUAL_UPDATE_ALLOWED_SHIFT                        1
2877     #define PCIEIP_REG_PTM_REQ_STATUS_OFF_RSVDP_2                                                    (0x3fffffff<<2) // Reserved for future use.
2878     #define PCIEIP_REG_PTM_REQ_STATUS_OFF_RSVDP_2_SHIFT                                              2
2879 #define PCIEIP_REG_PTM_REQ_LOCAL_LSB_OFF                                                             0x0003c0UL //Access:RW   DataWidth:0x20  PTM Requester Local Clock LSB  For more details, see the PTM section in the Databook.  Chips: K2
2880 #define PCIEIP_REG_PTM_REQ_LOCAL_MSB_OFF                                                             0x0003c4UL //Access:RW   DataWidth:0x20  PTM Requester Local Clock MSB. For more details, see the PTM section in the Databook.  Chips: K2
2881 #define PCIEIP_REG_PTM_REQ_T1_LSB_OFF                                                                0x0003c8UL //Access:R    DataWidth:0x20  PTM Requester T1 Timestamp LSB. For more details, see the PTM section in the Databook.  Chips: K2
2882 #define PCIEIP_REG_PTM_REQ_T1_MSB_OFF                                                                0x0003ccUL //Access:R    DataWidth:0x20  PTM Requester T1 Timestamp MSB. For more details, see the PTM section in the Databook.  Chips: K2
2883 #define PCIEIP_REG_PTM_REQ_T1P_LSB_OFF                                                               0x0003d0UL //Access:R    DataWidth:0x20  PTM Requester T1 Previous Timestamp LSB. For more details, see the PTM section in the Databook.  Chips: K2
2884 #define PCIEIP_REG_PTM_REQ_T1P_MSB_OFF                                                               0x0003d4UL //Access:R    DataWidth:0x20  PTM Requester T1 Previous Timestamp MSB. For more details, see the PTM section in the Databook.  Chips: K2
2885 #define PCIEIP_REG_PTM_REQ_T4_LSB_OFF                                                                0x0003d8UL //Access:R    DataWidth:0x20  PTM Requester T4 Timestamp LSB. For more details, see the PTM section in the Databook.  Chips: K2
2886 #define PCIEIP_REG_PTM_REQ_T4_MSB_OFF                                                                0x0003dcUL //Access:R    DataWidth:0x20  PTM Requester T4 Timestamp MSB. For more details, see the PTM section in the Databook.  Chips: K2
2887 #define PCIEIP_REG_PTM_REQ_T4P_LSB_OFF                                                               0x0003e0UL //Access:R    DataWidth:0x20  PTM Requester T4 Previous Timestamp LSB. For more details, see the PTM section in the Databook.  Chips: K2
2888 #define PCIEIP_REG_PTM_REQ_T4P_MSB_OFF                                                               0x0003e4UL //Access:R    DataWidth:0x20  PTM Requester T4 Previous Timestamp MSB. For more details, see the PTM section in the Databook.  Chips: K2
2889 #define PCIEIP_REG_PTM_REQ_MASTER_LSB_OFF                                                            0x0003e8UL //Access:R    DataWidth:0x20  PTM Requester Master Time LSB. For more details, see the PTM section in the Databook.  Chips: K2
2890 #define PCIEIP_REG_PTM_REQ_MASTER_MSB_OFF                                                            0x0003ecUL //Access:R    DataWidth:0x20  PTM Requester Master Time MSB. For more details, see the PTM section in the Databook.  Chips: K2
2891 #define PCIEIP_REG_PTM_REQ_PROP_DELAY_OFF                                                            0x0003f0UL //Access:R    DataWidth:0x20  PTM Requester Propagation Delay. For more details, see the PTM section in the Databook.  Chips: K2
2892 #define PCIEIP_REG_PTM_REQ_MASTERT1_LSB_OFF                                                          0x0003f4UL //Access:R    DataWidth:0x20  PTM Requester Master Time at T1 LSB. For more details, see the PTM section in the Databook.  Chips: K2
2893 #define PCIEIP_REG_PTM_REQ_MASTERT1_MSB_OFF                                                          0x0003f8UL //Access:R    DataWidth:0x20  PTM Requester Master Time at T1 MSB. For more details, see the PTM section in the Databook.  Chips: K2
2894 #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF                                                            0x0003fcUL //Access:RW   DataWidth:0x20  PTM Requester TX Latency. For more details, see the PTM section in the Databook.  Chips: K2
2895     #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_PTM_REQ_TX_LATENCY                                     (0xfff<<0) // PTM Requester TX Latency - Requester Transmit path latency (12 bit wide). For more details, see the PTM section in the Databook.  Note: This register field is sticky.
2896     #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_PTM_REQ_TX_LATENCY_SHIFT                               0
2897     #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_RSVDP_12                                               (0xfffff<<12) // Reserved for future use.
2898     #define PCIEIP_REG_PTM_REQ_TX_LATENCY_OFF_RSVDP_12_SHIFT                                         12
2899 #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF                                                            0x000400UL //Access:RW   DataWidth:0x20  PTM Requester RX Latency. For more details, see the PTM section in the Databook.  Chips: K2
2900     #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_PTM_REQ_RX_LATENCY                                     (0xfff<<0) // PTM Requester RX Latency - Requester Receive path latency (12 bit wide). For more details, see the PTM section in the Databook.  Note: This register field is sticky.
2901     #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_PTM_REQ_RX_LATENCY_SHIFT                               0
2902     #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_RSVDP_12                                               (0xfffff<<12) // Reserved for future use.
2903     #define PCIEIP_REG_PTM_REQ_RX_LATENCY_OFF_RSVDP_12_SHIFT                                         12
2904 #define PCIEIP_REG_RESBAR_CAP_HDR_REG                                                                0x000404UL //Access:RW   DataWidth:0x20  Resizable BAR Capability Header.  Chips: K2
2905     #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID                                          (0xffff<<0) // Resizable BAR Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2906     #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_EXT_CAP_ID_SHIFT                                    0
2907     #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION                                         (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2908     #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_VERSION_SHIFT                                   16
2909     #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET                                     (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
2910     #define PCIEIP_REG_RESBAR_CAP_HDR_REG_RESBAR_CAP_NEXT_OFFSET_SHIFT                               20
2911 #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_K2                                                           0x000408UL //Access:RW   DataWidth:0x20  Resizable BAR0 Capability Register.  Chips: K2
2912     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RSVDP_0                                                  (0xf<<0) // Reserved for future use.
2913     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RSVDP_0_SHIFT                                            0
2914     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB                                     (0x1<<4) // Up to 1MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2915     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1MB_SHIFT                               4
2916     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB                                     (0x1<<5) // Up to 2MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2917     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2MB_SHIFT                               5
2918     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB                                     (0x1<<6) // Up to 4MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2919     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4MB_SHIFT                               6
2920     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB                                     (0x1<<7) // Up to 8MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2921     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8MB_SHIFT                               7
2922     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB                                    (0x1<<8) // Up to 16MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2923     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16MB_SHIFT                              8
2924     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB                                    (0x1<<9) // Up to 32MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2925     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32MB_SHIFT                              9
2926     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB                                    (0x1<<10) // Up to 64MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2927     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64MB_SHIFT                              10
2928     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB                                   (0x1<<11) // Up to 128MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2929     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128MB_SHIFT                             11
2930     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB                                   (0x1<<12) // Up to 256MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2931     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256MB_SHIFT                             12
2932     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB                                   (0x1<<13) // Up to 512MB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2933     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512MB_SHIFT                             13
2934     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB                                     (0x1<<14) // Up to 1GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2935     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_1GB_SHIFT                               14
2936     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB                                     (0x1<<15) // Up to 2GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2937     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_2GB_SHIFT                               15
2938     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB                                     (0x1<<16) // Up to 4GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2939     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_4GB_SHIFT                               16
2940     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB                                     (0x1<<17) // Up to 8GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2941     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_8GB_SHIFT                               17
2942     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB                                    (0x1<<18) // Up to 16GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2943     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_16GB_SHIFT                              18
2944     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB                                    (0x1<<19) // Up to 32GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2945     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_32GB_SHIFT                              19
2946     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB                                    (0x1<<20) // Up to 64GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2947     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_64GB_SHIFT                              20
2948     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB                                   (0x1<<21) // Up to 128GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2949     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_128GB_SHIFT                             21
2950     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB                                   (0x1<<22) // Up to 256GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2951     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_256GB_SHIFT                             22
2952     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB                                   (0x1<<23) // Up to 512GB BAR Supported.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2953     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RESBAR_CAP_REG_0_512GB_SHIFT                             23
2954     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RSVDP_24                                                 (0xff<<24) // Reserved for future use.
2955     #define PCIEIP_REG_RESBAR_CAP_REG_0_REG_RSVDP_24_SHIFT                                           24
2956 #define PCIEIP_REG_CONFIG_2_BB_A0                                                                    0x000408UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
2957 #define PCIEIP_REG_CONFIG_2_BB_B0                                                                    0x000408UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
2958     #define PCIEIP_REG_CONFIG_2_BAR1_SIZE                                                            (0xf<<0) // These bits control the size of the BAR1 area advertised in the bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. Default is 64K
2959     #define PCIEIP_REG_CONFIG_2_BAR1_SIZE_SHIFT                                                      0
2960     #define PCIEIP_REG_CONFIG_2_BAR1_64ENA                                                           (0x1<<4) // This bit enables the advertisement of bar_1 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_1. This value is sticky and only reset by HARD Reset. If set it is 64bit addressing.
2961     #define PCIEIP_REG_CONFIG_2_BAR1_64ENA_SHIFT                                                     4
2962     #define PCIEIP_REG_CONFIG_2_EXP_ROM_RETRY                                                        (0x1<<5) // This bit will force the PCI bus to re-try all cycles to the current Expansion ROM BAR area. When this bit is set, then no Expansion ROM interrupt will be generated. This bit must be cleared to allow the interrupt to be generated.
2963     #define PCIEIP_REG_CONFIG_2_EXP_ROM_RETRY_SHIFT                                                  5
2964     #define PCIEIP_REG_CONFIG_2_CFG_CYCLE_RETRY                                                      (0x1<<6) // This bit will force the PCI bus to re-try all cycles to the configuration space until it is cleared. This is used to block the host from accessing context if needed to prevent reading of false data. This bit may be used in combination with the FIRST_CFG_DONE bit below to prevent changing of the configuration space values after they have be read by the system. Normally this bit will be set by the firmware while the configuration space is programmed. This bit also exists in each VF and can be used to control individual VF.
2965     #define PCIEIP_REG_CONFIG_2_CFG_CYCLE_RETRY_SHIFT                                                6
2966     #define PCIEIP_REG_CONFIG_2_FIRST_CFG_DONE                                                       (0x1<<7) // This bit will be set the first time since PCI reset that a configuration cycle hass been done by the PCI block. This may be used by firmware to detect if the host already has the reset values of the configuration space. this may happen if the NVM system is much slower than expected. Tn this case, the firmware can choose to not exist or show an error on LEDs, etc. instead of changing the configuratio space values that the host ahas already read.
2967     #define PCIEIP_REG_CONFIG_2_FIRST_CFG_DONE_SHIFT                                                 7
2968     #define PCIEIP_REG_CONFIG_2_ROM_BAR_SIZE                                                         (0xff<<8) // These bits control the size of the Expansion ROM area advertised in the Exp_ROM_BAR register of the PCI configuration space. When this value is non-zero, the Expansion ROM attention must be handled by an internal processor to move data between the Serial Non-Volatile Memory and the Expansion ROM interface. When the value is zero, the expansion ROM BAR will not advertize the presence of an expansion ROM.
2969     #define PCIEIP_REG_CONFIG_2_ROM_BAR_SIZE_SHIFT                                                   8
2970     #define PCIEIP_REG_CONFIG_2_BAR_PREFETCH                                                         (0x1<<16) // This bit when set is reflected in bit 3 of bar_1 and indicates that the BAR is pre-fetchable
2971     #define PCIEIP_REG_CONFIG_2_BAR_PREFETCH_SHIFT                                                   16
2972     #define PCIEIP_REG_CONFIG_2_RESERVED0                                                            (0x7fff<<17) //
2973     #define PCIEIP_REG_CONFIG_2_RESERVED0_SHIFT                                                      17
2974 #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_K2                                                          0x00040cUL //Access:RW   DataWidth:0x20  Resizable BAR0 Control Register.  Chips: K2
2975     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0                                   (0x7<<0) // BAR Index.   Note: This register field is sticky.
2976     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_IDX_0_SHIFT                             0
2977     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RSVDP_3                                                 (0x3<<3) // Reserved for future use.
2978     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RSVDP_3_SHIFT                                           3
2979     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS                                (0x7<<5) // Number of Resizeable BARs.   Note: This register field is sticky.
2980     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_NUM_BARS_SHIFT                          5
2981     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE                                (0x1f<<8) // BAR Size.   Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
2982     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RESBAR_CTRL_REG_BAR_SIZE_SHIFT                          8
2983     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RSVDP_13                                                (0x7ffff<<13) // Reserved for future use.
2984     #define PCIEIP_REG_RESBAR_CTRL_REG_0_REG_RSVDP_13_SHIFT                                          13
2985 #define PCIEIP_REG_CONFIG_3_BB_A0                                                                    0x00040cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
2986 #define PCIEIP_REG_CONFIG_3_BB_B0                                                                    0x00040cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
2987     #define PCIEIP_REG_CONFIG_3_STICKY_BYTE                                                          (0xff<<0) // This value is reset only reset by HARD Reset such that it can be used to detect initial power up if a non-zero value is written by the firmware after initialization. It has not hardware function other than reset type detection. This value is sticky and only reset by HARD Reset.
2988     #define PCIEIP_REG_CONFIG_3_STICKY_BYTE_SHIFT                                                    0
2989     #define PCIEIP_REG_CONFIG_3_REG_STICKY_BYTE                                                      (0xff<<8) // This value is reset only by REG_HARD_RST.
2990     #define PCIEIP_REG_CONFIG_3_REG_STICKY_BYTE_SHIFT                                                8
2991     #define PCIEIP_REG_CONFIG_3_VF_MEM_DSICARD                                                       (0x1<<16) // This bits exists in VF only Setting this bit to '1' forces the VF to drop any mem request that it receives. UR completion will be returned for mem read requests. This bit along with the CRS bit can be used by software to control when VF is up.
2992     #define PCIEIP_REG_CONFIG_3_VF_MEM_DSICARD_SHIFT                                                 16
2993     #define PCIEIP_REG_CONFIG_3_UNUSED0                                                              (0x7f<<17) //
2994     #define PCIEIP_REG_CONFIG_3_UNUSED0_SHIFT                                                        17
2995     #define PCIEIP_REG_CONFIG_3_FORCE_PME                                                            (0x1<<24) // Setting this bit to '1' forces the PME message to be send This simulates the PME event. The PME control bits in the configuration space still control the output normally. This value is sticky and only reset by HARD Reset.
2996     #define PCIEIP_REG_CONFIG_3_FORCE_PME_SHIFT                                                      24
2997     #define PCIEIP_REG_CONFIG_3_PME_STATUS                                                           (0x1<<25) // This bit indicates the current state of the PME_STATUS bit in configuration space. This value is sticky and only reset by HARD Reset.
2998     #define PCIEIP_REG_CONFIG_3_PME_STATUS_SHIFT                                                     25
2999     #define PCIEIP_REG_CONFIG_3_PME_ENABLE                                                           (0x1<<26) // This is the current state of the PME_ENABLE bit in configuration space. This value is sticky and only reset by HARD Reset.
3000     #define PCIEIP_REG_CONFIG_3_PME_ENABLE_SHIFT                                                     26
3001     #define PCIEIP_REG_CONFIG_3_PM_STATE                                                             (0x3<<27) // This value interfaces to the PM_STATE value in the Power Management configuration space. Reads of this register return the last value written to the PM_STATE value in configuration space.
3002     #define PCIEIP_REG_CONFIG_3_PM_STATE_SHIFT                                                       27
3003     #define PCIEIP_REG_CONFIG_3_UNUSED1                                                              (0x1<<29) //
3004     #define PCIEIP_REG_CONFIG_3_UNUSED1_SHIFT                                                        29
3005     #define PCIEIP_REG_CONFIG_3_VAUX_PRESENT                                                         (0x1<<30) // This bit indicates the input level on the VAUX_PRESENT pin. This indicates if the VAUX supply is available in the current configuration. The value also controls the value of the Power Management PME_SUPPORT register in configuration space. Field is local in each PF
3006     #define PCIEIP_REG_CONFIG_3_VAUX_PRESENT_SHIFT                                                   30
3007     #define PCIEIP_REG_CONFIG_3_PCI_POWER                                                            (0x1<<31) // PCI_POWER This bit indicates the current state of power on the PCI bus. If this bit is '1', it indicates that the PCI padring has power. If this bit is '0', it indicates that the PCI padring does not have power (D3 Cold).
3008     #define PCIEIP_REG_CONFIG_3_PCI_POWER_SHIFT                                                      31
3009 #define PCIEIP_REG_PM_DATA_A                                                                         0x000410UL //Access:RW   DataWidth:0x20  This register controls the first 4 power management PM_Data read values  Chips: BB_A0 BB_B0
3010     #define PCIEIP_REG_PM_DATA_A_PM_DATA_0_PRG                                                       (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 0. This is the power consumed in D0 state. This value is sticky and only reset by HARD Reset.
3011     #define PCIEIP_REG_PM_DATA_A_PM_DATA_0_PRG_SHIFT                                                 0
3012     #define PCIEIP_REG_PM_DATA_A_PM_DATA_1_PRG                                                       (0xff<<8) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 1. This is the power consumed in D1 state. This value is sticky and only reset by HARD Reset.
3013     #define PCIEIP_REG_PM_DATA_A_PM_DATA_1_PRG_SHIFT                                                 8
3014     #define PCIEIP_REG_PM_DATA_A_PM_DATA_2_PRG                                                       (0xff<<16) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 2. This is the power consumed in D2 state. This value is sticky and only reset by HARD Reset.
3015     #define PCIEIP_REG_PM_DATA_A_PM_DATA_2_PRG_SHIFT                                                 16
3016     #define PCIEIP_REG_PM_DATA_A_PM_DATA_3_PRG                                                       (0xff<<24) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 3. This is the power consumed in D3 state. This value is sticky and only reset by HARD Reset.
3017     #define PCIEIP_REG_PM_DATA_A_PM_DATA_3_PRG_SHIFT                                                 24
3018 #define PCIEIP_REG_PM_DATA_B                                                                         0x000414UL //Access:RW   DataWidth:0x20  This register controls the second 4 power management PM_Data read values  Chips: BB_A0 BB_B0
3019     #define PCIEIP_REG_PM_DATA_B_PM_DATA_4_PRG                                                       (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 4. This is the power dissipated in D0 state. This value is sticky and only reset by HARD Reset.
3020     #define PCIEIP_REG_PM_DATA_B_PM_DATA_4_PRG_SHIFT                                                 0
3021     #define PCIEIP_REG_PM_DATA_B_PM_DATA_5_PRG                                                       (0xff<<8) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 5. This is the power dissipated in D1 state. This value is sticky and only reset by HARD Reset.
3022     #define PCIEIP_REG_PM_DATA_B_PM_DATA_5_PRG_SHIFT                                                 8
3023     #define PCIEIP_REG_PM_DATA_B_PM_DATA_6_PRG                                                       (0xff<<16) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 6. This is the power dissipated in D2 state. This value is sticky and only reset by HARD Reset.
3024     #define PCIEIP_REG_PM_DATA_B_PM_DATA_6_PRG_SHIFT                                                 16
3025     #define PCIEIP_REG_PM_DATA_B_PM_DATA_7_PRG                                                       (0xff<<24) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 7. This is the power dissipated in D3 state. This value is sticky and only reset by HARD Reset.
3026     #define PCIEIP_REG_PM_DATA_B_PM_DATA_7_PRG_SHIFT                                                 24
3027 #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ                                                              0x000418UL //Access:RW   DataWidth:0x20  This register controls the higher bar size advertizements, when a bar size greater than 1G is desired.  Chips: BB_A0 BB_B0
3028     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_HIEXT                                          (0xf<<0) // These bits control the size of the BAR1 area advertised in the bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is desired. When requiring a BAR size greater than 1 GB, the corresponding bar1_size bits should be programmed to 0xF.
3029     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_HIEXT_SHIFT                                    0
3030     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_HIEXT                                          (0xf<<4) // These bits control the size of the BAR2 area advertised in the bar_3 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is desired. When requiring a BAR size greater than 1 GB, the corresponding bar2_size bits should be programmed to 0xF.
3031     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_HIEXT_SHIFT                                    4
3032     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_HIEXT                                          (0xf<<8) // These bits control the size of the BAR3 area advertised in the bar_5 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size greater than 1GB is desired. When requiring a BAR size greater than 1 GB, the corresponding bar3_size bits should be programmed to 0xF.
3033     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_HIEXT_SHIFT                                    8
3034     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_LOEXT                                          (0x7<<12) // These bits control the size of the BAR1 area advertised in the bar_1 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size lower than 64K is desired. When requiring a BAR size smaller than 64K , the corresponding bar_size bits should be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K, then the bar1_size_loext bits need to be 0.
3035     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR1_SIZE_LOEXT_SHIFT                                    12
3036     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_UNUSED0                                                  (0x1<<15) //
3037     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_UNUSED0_SHIFT                                            15
3038     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_LOEXT                                          (0x7<<16) // These bits control the size of the BAR2 area advertised in the bar_3 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size lower than 64K is desired. When requiring a BAR size smaller than 64K , the corresponding bar2_size bits should be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K, then the bar1_size_loext bits need to be 0.
3039     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR2_SIZE_LOEXT_SHIFT                                    16
3040     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_LOEXT                                          (0x7<<19) // These bits control the size of the BAR3 area advertised in the bar_5 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. These bits are programmed when a BAR size lower than 64K is desired. When requiring a BAR size smaller than 64K , the corresponding bar3_size bits should be programmed to 0x0, as also the bar1_size_hiext bits. If desiring a bar size greater than 32K, then the bar1_size_loext bits need to be 0.
3041     #define PCIEIP_REG_PCI_EXTENDED_BAR_SIZ_BAR3_SIZE_LOEXT_SHIFT                                    19
3042 #define PCIEIP_REG_REG_VPD_INTF                                                                      0x000428UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3043     #define PCIEIP_REG_REG_VPD_INTF_INTF_REQ                                                         (0x1<<0) // This bit will be set if there is a pending request for action by the firmware to handle a Vital Product Data interface. This bit is set when the vpd_flag_addr register in configuation space is written. This bit is cleared when the vpd_data register below is written.
3044     #define PCIEIP_REG_REG_VPD_INTF_INTF_REQ_SHIFT                                                   0
3045 #define PCIEIP_REG_REG_VPD_ADDR_FLAG                                                                 0x00042cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3046     #define PCIEIP_REG_REG_VPD_ADDR_FLAG_UNUSED0                                                     (0x3ffff<<0) //
3047     #define PCIEIP_REG_REG_VPD_ADDR_FLAG_UNUSED0_SHIFT                                               0
3048     #define PCIEIP_REG_REG_VPD_ADDR_FLAG_ADDRESS                                                     (0x1fff<<18) // This value is the byte address of the VPD value being requested by the host in the vpd_flag_addr register of the configuration space.
3049     #define PCIEIP_REG_REG_VPD_ADDR_FLAG_ADDRESS_SHIFT                                               18
3050     #define PCIEIP_REG_REG_VPD_ADDR_FLAG_WR                                                          (0x1<<31) // This bit indicates if the host is requesting a read or a write cycle. If this bit is set, then the host has requested the data in the vpd_data register to be passed to the NVM interface. If the value is clear, then the host has requested the data to be passed from the NVM interface to the vpd_data register. The value of this bit is only valid if the INTF_REQ bit is set. This bit is a RO copy of the flag bit in the vpd_flag_addr register in configuration space.
3051     #define PCIEIP_REG_REG_VPD_ADDR_FLAG_WR_SHIFT                                                    31
3052 #define PCIEIP_REG_REG_VPD_DATA                                                                      0x000430UL //Access:RW   DataWidth:0x20  This is the data register for passing values between the NVM interface and the vpd_data register in the configuration space. When INTF_REQ is '1' and the WR bit is clear, this word should be written with the NVM data requested in the ADDRESS value to clear the INTF_REQ bit. When INTF_REQ is '1' and the WR bit is set, this word should be read and written to the NVM interface. After the NVM interface write is complete, this value should be written with the same value to clear the INTF_REQ bit. When this value is written and the INTF_REQ bit is set, the FLAG bit in the vpd_flag_addr register in configurationspace will be complemented.  Chips: BB_A0 BB_B0
3053 #define PCIEIP_REG_REG_ID_VAL1                                                                       0x000434UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3054     #define PCIEIP_REG_REG_ID_VAL1_DEVICE_ID                                                         (0xffff<<0) // This register programs the read value of the device_id register of the configuration space. The hardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset. The default value reflects the value of DEVICE_ID in version.v defined by user or the strap pins user_device_id if user relies on straps.
3055     #define PCIEIP_REG_REG_ID_VAL1_DEVICE_ID_SHIFT                                                   0
3056     #define PCIEIP_REG_REG_ID_VAL1_VENDOR_ID                                                         (0xffff<<16) // This register programs the read value of the vendor_id register of the configuration space. The hardware default value is the Broadcom vendor ID. This value is sticky and only reset by HARD Reset.
3057     #define PCIEIP_REG_REG_ID_VAL1_VENDOR_ID_SHIFT                                                   16
3058 #define PCIEIP_REG_REG_ID_VAL2                                                                       0x000438UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3059     #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_VENDOR_ID                                               (0xffff<<0) // This value controls the read value of the subsystem_vendor_id value in the configuration space. This value is sticky and only reset by HARD Reset.
3060     #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_VENDOR_ID_SHIFT                                         0
3061     #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_ID                                                      (0xffff<<16) // This value controls the read value of the subsystem_id value in the configuration space. This value is sticky and only reset by HARD Reset. The default value reflects the value of DEVICE_ID in version.v defined by user or the strap pins user_device_id if user relies on straps.
3062     #define PCIEIP_REG_REG_ID_VAL2_SUBSYSTEM_ID_SHIFT                                                16
3063 #define PCIEIP_REG_REG_ID_VAL3                                                                       0x00043cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3064     #define PCIEIP_REG_REG_ID_VAL3_CLASS_CODE                                                        (0xffffff<<0) // This register programs the read value of the class_code register of the configuration space. The 24-bit Class Code register identifies the generic function of the device. All of the legal values are specific in the PCI specification. The default value for this register is the class code for an Ethernet interface (0x020000). This value is sticky and only reset by HARD Reset. The default value reflects the value of CLASS_CODE in version.v defined by user.
3065     #define PCIEIP_REG_REG_ID_VAL3_CLASS_CODE_SHIFT                                                  0
3066     #define PCIEIP_REG_REG_ID_VAL3_REVISION_ID                                                       (0xff<<24) // This register programs the read value of the revision_id register of the configuration space. The default value is provided by user_revision_id strap pins. This field also exists in VF register space
3067     #define PCIEIP_REG_REG_ID_VAL3_REVISION_ID_SHIFT                                                 24
3068 #define PCIEIP_REG_REG_ID_VAL4                                                                       0x000440UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3069     #define PCIEIP_REG_REG_ID_VAL4_CAP_ENA                                                           (0xf<<0) // This value controls the read value of the next capability pointers in the PCIE configuration space and allows each extra capability to be independently disabled by manipulation of the next pointer values. The read values for each enable combination is shown below. PCIE capability is always enabled. Bit 0 enables the Power Management capability. Bit 1 enables the VPD capability, and Bit 2 enables the MSI capability and Bit3 is MSIX capability This value is sticky and only reset by HARD Reset.
3070     #define PCIEIP_REG_REG_ID_VAL4_CAP_ENA_SHIFT                                                     0
3071     #define PCIEIP_REG_REG_ID_VAL4_UNUSED0                                                           (0x3<<4) //
3072     #define PCIEIP_REG_REG_ID_VAL4_UNUSED0_SHIFT                                                     4
3073     #define PCIEIP_REG_REG_ID_VAL4_PM_DATA_SCALE                                                     (0x3<<6) // This value is read as the DATA_SCALE value in the Power Management CSR register in the PCI Configuration address space. This value is sticky and only reset by HARD Reset.
3074     #define PCIEIP_REG_REG_ID_VAL4_PM_DATA_SCALE_SHIFT                                               6
3075     #define PCIEIP_REG_REG_ID_VAL4_MSI_PV_MASK_CAPABLE                                               (0x1<<8) // This value controls the per vector masking capability in the MSI control field
3076     #define PCIEIP_REG_REG_ID_VAL4_MSI_PV_MASK_CAPABLE_SHIFT                                         8
3077     #define PCIEIP_REG_REG_ID_VAL4_MSI_LIMIT                                                         (0x7<<9) // This value reports the MSI value that is programmed in the PCI configuration space. This value will always be equal or less than what was advertised. This value is sticky and only reset by HARD Reset.
3078     #define PCIEIP_REG_REG_ID_VAL4_MSI_LIMIT_SHIFT                                                   9
3079     #define PCIEIP_REG_REG_ID_VAL4_MULTI_MSG_CAP                                                     (0x7<<12) // This value controls the read value of the MSI_CTRL_MCAP value in the PCI configuration space. The default is 0, which is one MSI. This value is sticky and only reset by HARD Reset.
3080     #define PCIEIP_REG_REG_ID_VAL4_MULTI_MSG_CAP_SHIFT                                               12
3081     #define PCIEIP_REG_REG_ID_VAL4_MSI_ENABLE                                                        (0x1<<15) // This bit indicates the programming of the MSI Enable bit in PCI configuration space. If this bit is set, it means that the interrupt output is masked and all interrupts must be indicated with MSI cycles.
3082     #define PCIEIP_REG_REG_ID_VAL4_MSI_ENABLE_SHIFT                                                  15
3083     #define PCIEIP_REG_REG_ID_VAL4_RESERVED3                                                         (0xffff<<16) //
3084     #define PCIEIP_REG_REG_ID_VAL4_RESERVED3_SHIFT                                                   16
3085 #define PCIEIP_REG_REG_ID_VAL5                                                                       0x000444UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3086     #define PCIEIP_REG_REG_ID_VAL5_D1_SUPPORT                                                        (0x1<<0) // This bit indicates whether the device supports the D1 power management state. It is reflected in the D1_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset.
3087     #define PCIEIP_REG_REG_ID_VAL5_D1_SUPPORT_SHIFT                                                  0
3088     #define PCIEIP_REG_REG_ID_VAL5_D2_SUPPORT                                                        (0x1<<1) // This bit indicates whether the device supports the D2 power management state. It is reflected in the D2_SUPPORT bit in the configuration space. This value is sticky and only reset by HARD Reset.
3089     #define PCIEIP_REG_REG_ID_VAL5_D2_SUPPORT_SHIFT                                                  1
3090     #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D0                                                         (0x1<<2) // This bit indicates whether the device supports transmiting PME message from the D0 power state. It is reflected in the PME_IN_D0 bit in the configuration space. This value is sticky and only reset by HARD Reset.
3091     #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D0_SHIFT                                                   2
3092     #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D1                                                         (0x1<<3) // This bit indicates whether the device supports transmiting PME message from the D1 power state. It is reflected in the PME_IN_D1 bit in the configuration space. This value is sticky and only reset by HARD Reset.
3093     #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D1_SHIFT                                                   3
3094     #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D2                                                         (0x1<<4) // This bit indicates whether the device supports transmiting PME message from the D2 power state. It is reflected in the PME_IN_D2 bit in the configuration space. This value is sticky and only reset by HARD Reset.
3095     #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D2_SHIFT                                                   4
3096     #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D3_HOT                                                     (0x1<<5) // This bit indicates whether the device supports transmiting PME message from the D3hot power state. It is reflected in the PME_IN_D3_HOT bit in the configuration space. This value is sticky and only reset by HARD Reset.
3097     #define PCIEIP_REG_REG_ID_VAL5_PME_IN_D3_HOT_SHIFT                                               5
3098     #define PCIEIP_REG_REG_ID_VAL5_PM_VERSION                                                        (0x7<<6) // The value indicates the function complies with which revision of PCI PM spec. This value is reflected in corresponding field in PM capabilities register
3099     #define PCIEIP_REG_REG_ID_VAL5_PM_VERSION_SHIFT                                                  6
3100     #define PCIEIP_REG_REG_ID_VAL5_NO_SOFT_RESET                                                     (0x1<<9) // This indicates function does not perform an internal reset when transitioning from D3 to D0. the value is reflected in corresponding field in PM CSR.
3101     #define PCIEIP_REG_REG_ID_VAL5_NO_SOFT_RESET_SHIFT                                               9
3102     #define PCIEIP_REG_REG_ID_VAL5_RESERVED0                                                         (0x3fffff<<10) //
3103     #define PCIEIP_REG_REG_ID_VAL5_RESERVED0_SHIFT                                                   10
3104 #define PCIEIP_REG_REG_ID_VAL6                                                                       0x00044cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3105     #define PCIEIP_REG_REG_ID_VAL6_UNUSED0                                                           (0xffff<<0) //
3106     #define PCIEIP_REG_REG_ID_VAL6_UNUSED0_SHIFT                                                     0
3107     #define PCIEIP_REG_REG_ID_VAL6_BIST                                                              (0xff<<16) // This register controls the read value of the bist register in the configuration space. This value is sticky and only reset by HARD Reset.
3108     #define PCIEIP_REG_REG_ID_VAL6_BIST_SHIFT                                                        16
3109 #define PCIEIP_REG_REG_MSI_DATA                                                                      0x000450UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3110     #define PCIEIP_REG_REG_MSI_DATA_MSI_DATA                                                         (0xffff<<0) // This register reflects the MSI data register value in the configuration space. This value may be used by the completion processor to determine the data value it will use for vectored MSI cycles.
3111     #define PCIEIP_REG_REG_MSI_DATA_MSI_DATA_SHIFT                                                   0
3112 #define PCIEIP_REG_REG_MSI_ADDR_H                                                                    0x000454UL //Access:R    DataWidth:0x20  This register reflects the upper half of the MSI address register value in the configuration space. This value may be used by the completion processor to determine the address value it will use for vectored MSI cycles.  Chips: BB_A0 BB_B0
3113 #define PCIEIP_REG_REG_MSI_ADDR_L                                                                    0x000458UL //Access:R    DataWidth:0x20  This register reflects the lower half of the MSI address bit[31:2] value in the configuration space. The lower two bits [1:0] are hard wired to zero. This value may be used by the completion processor to determine the address value it will use for vectored MSI cycles.  Chips: BB_A0 BB_B0
3114 #define PCIEIP_REG_REG_MSI_MASK                                                                      0x000464UL //Access:R    DataWidth:0x20  This register reflects the MSI mask register value in the configuration space  Chips: BB_A0 BB_B0
3115 #define PCIEIP_REG_REG_MSI_PEND                                                                      0x000468UL //Access:RW   DataWidth:0x20  Each pending bit that is set , the function has a pending associated message. This register gets reflected in the configuration space.  Chips: BB_A0 BB_B0
3116 #define PCIEIP_REG_REG_PM_DATA_C                                                                     0x00046cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3117     #define PCIEIP_REG_REG_PM_DATA_C_PM_DATA_8_PRG                                                   (0xff<<0) // This is the value read from the pm_data register when the DATA_SEL value in the PM_CSR register is 8. This is the power dissipated by common logic in case of multi function devices. This value is sticky and only reset by HARD Reset.
3118     #define PCIEIP_REG_REG_PM_DATA_C_PM_DATA_8_PRG_SHIFT                                             0
3119     #define PCIEIP_REG_REG_PM_DATA_C_RESERVED0                                                       (0xffffff<<8) //
3120     #define PCIEIP_REG_REG_PM_DATA_C_RESERVED0_SHIFT                                                 8
3121 #define PCIEIP_REG_REG_MSIX_CONTROL                                                                  0x0004c0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3122     #define PCIEIP_REG_REG_MSIX_CONTROL_MSIX_TBL_SIZ                                                 (0x7ff<<0) // This register controls the read value of the MSIX_CONTROL[10:0] register in the configuration space. A value of "00000000011" indicates a table size of 4 Lower 6 bits of this field also exists in VF register space
3123     #define PCIEIP_REG_REG_MSIX_CONTROL_MSIX_TBL_SIZ_SHIFT                                           0
3124     #define PCIEIP_REG_REG_MSIX_CONTROL_RESERVED0                                                    (0x1fffff<<11) //
3125     #define PCIEIP_REG_REG_MSIX_CONTROL_RESERVED0_SHIFT                                              11
3126 #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR                                                              0x0004c4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3127     #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR                                             (0x7<<0) // This register controls the read value of the MSIX_TBL_OFF_BIR[2:0] register. This indicates which one of the function's Base address registers located at 10h in configuration space is used to map the function's MSI-X table into memory space. Value is controlled by PCIE_MSIX_TBL_OFF field in version.v
3128     #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR_SHIFT                                       0
3129     #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF                                             (0x1fffffff<<3) // This register controls the read value of the MSIX_TBL_OFF_BIR[31:3] register. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X table. Value is controlled by PCIE_MSIX_TBL_OFF field in version.v
3130     #define PCIEIP_REG_REG_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF_SHIFT                                       3
3131 #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR                                                              0x0004c8UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3132     #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_BIR                                             (0x7<<0) // This register controls the read value of the MSIX_PBA_OFF_BIR[2:0] register. This indicates which one of the function's Base address registers located at 10h in configuration space is used to map the function's MSI-X PBA into memory space. Value is controlled by PCIE_MSIX_PBA_OFF field in version.v
3133     #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_BIR_SHIFT                                       0
3134     #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_OFF                                             (0x1fffffff<<3) // This register controls the read value of the MSIX_PBA_OFF_BIR[31:3] register. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X PBA Value is controlled by PCIE_MSIX_PBA_OFF field in version.v
3135     #define PCIEIP_REG_REG_MSIX_PBA_OFF_BIR_MSIX_PBA_OFF_SHIFT                                       3
3136 #define PCIEIP_REG_REG_PCIE_CAPABILITY                                                               0x0004d0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3137     #define PCIEIP_REG_REG_PCIE_CAPABILITY_INTERRUPT_MSG_NUM                                         (0x1f<<0) // This controls the value in configuration space
3138     #define PCIEIP_REG_REG_PCIE_CAPABILITY_INTERRUPT_MSG_NUM_SHIFT                                   0
3139     #define PCIEIP_REG_REG_PCIE_CAPABILITY_COMPLY_PCIE_1_1                                           (0x1<<5) // This bit when set, hides any PCIE spec 2.0 defined registers (bits) and enables design to be 1.1 compliant
3140     #define PCIEIP_REG_REG_PCIE_CAPABILITY_COMPLY_PCIE_1_1_SHIFT                                     5
3141     #define PCIEIP_REG_REG_PCIE_CAPABILITY_ASPM_OPTIONALITY                                          (0x1<<6) // This bit when set, sets the ASPM optionality bit in the Link cap register. This bit is recommended to be set for newer PCIe devices and required for 3.0 compliant devices
3142     #define PCIEIP_REG_REG_PCIE_CAPABILITY_ASPM_OPTIONALITY_SHIFT                                    6
3143 #define PCIEIP_REG_REG_DEVICE_CAPABILITY                                                             0x0004d4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3144     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED                                   (0x7<<0) // This controls the value of this field in the DEVICE_CAP register in the configuration space
3145     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_MAX_PL_SIZE_SUPPORTED_SHIFT                             0
3146     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED0                                                 (0x3<<3) //
3147     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED0_SHIFT                                           3
3148     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT                                    (0x1<<5) // This controls the value of this field in the DEVICE_CAP register in the configuration field
3149     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT_SHIFT                              5
3150     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY                                  (0x7<<6) // This controls the value of this field in the configuration space
3151     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY_SHIFT                            6
3152     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY                                   (0x7<<9) // This controls the value in the configuration space
3153     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY_SHIFT                             9
3154     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED1                                                 (0x7<<12) //
3155     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED1_SHIFT                                           12
3156     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT                                      (0x1<<15) // This controls value in configuration space
3157     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT_SHIFT                                15
3158     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED2                                                 (0xfff<<16) //
3159     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_UNUSED2_SHIFT                                           16
3160     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_FLR_SUPPORTED                                           (0x1<<28) // This controls value in configuration space and allows FLR capability to be advertized by DUT.
3161     #define PCIEIP_REG_REG_DEVICE_CAPABILITY_FLR_SUPPORTED_SHIFT                                     28
3162 #define PCIEIP_REG_REG_DEVICE_CONTROL                                                                0x0004d8UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3163     #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED0                                                    (0x7ffffff<<0) //
3164     #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED0_SHIFT                                              0
3165     #define PCIEIP_REG_REG_DEVICE_CONTROL_FLR_IN_PROGRESS                                            (0x1<<27) // When FLR is initiated, this register will read a value of 1 indicating that the Function is in FLR state. Func can be brought out of FLR state either by writing 1 to this register (at least 50 ms after FLR was initiated), or it can also be cleared automatically after 55 ms if auto_clear bit in private reg space is set. This bit also exists in VF register space
3166     #define PCIEIP_REG_REG_DEVICE_CONTROL_FLR_IN_PROGRESS_SHIFT                                      27
3167     #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED1                                                    (0x1<<28) //
3168     #define PCIEIP_REG_REG_DEVICE_CONTROL_UNUSED1_SHIFT                                              28
3169     #define PCIEIP_REG_REG_DEVICE_CONTROL_SRIOV_DISABLE_IN_PROGRESS                                  (0x1<<29) // When VF Enable is cleared(after it was previously set), this register will read a value of 1, indicating that all the VFs that belong to this PF should be flushed. Software should clear this bit within 1 second of VF Enable being set by writing a 1 to it, so that VFs are visible to the system again.
3170     #define PCIEIP_REG_REG_DEVICE_CONTROL_SRIOV_DISABLE_IN_PROGRESS_SHIFT                            29
3171 #define PCIEIP_REG_REG_LINK_CAPABILITY                                                               0x0004dcUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3172     #define PCIEIP_REG_REG_LINK_CAPABILITY_MAX_LINK_SPEED                                            (0xf<<0) // This controls the value of the same field in the link_capability register in configuration space.This also controls the variables advertised by the PHY such as FTS ordered sets etc.
3173     #define PCIEIP_REG_REG_LINK_CAPABILITY_MAX_LINK_SPEED_SHIFT                                      0
3174     #define PCIEIP_REG_REG_LINK_CAPABILITY_MAX_LINK_WIDTH                                            (0x1f<<4) // This controls the value of the same field in the link_capability register in configuration space
3175     #define PCIEIP_REG_REG_LINK_CAPABILITY_MAX_LINK_WIDTH_SHIFT                                      4
3176     #define PCIEIP_REG_REG_LINK_CAPABILITY_CLK_POWER_MGMT                                            (0x1<<9) // This controls the value of the same field in the link_capability register in configuration space
3177     #define PCIEIP_REG_REG_LINK_CAPABILITY_CLK_POWER_MGMT_SHIFT                                      9
3178     #define PCIEIP_REG_REG_LINK_CAPABILITY_ASPM_SUPPORT                                              (0x3<<10) // This controls the value of the same field in the link_capability register in configuration space
3179     #define PCIEIP_REG_REG_LINK_CAPABILITY_ASPM_SUPPORT_SHIFT                                        10
3180     #define PCIEIP_REG_REG_LINK_CAPABILITY_L0S_EXIT_LAT                                              (0x7<<12) // This controls the value of the same field in the link_capability register in configuration space
3181     #define PCIEIP_REG_REG_LINK_CAPABILITY_L0S_EXIT_LAT_SHIFT                                        12
3182     #define PCIEIP_REG_REG_LINK_CAPABILITY_L1_EXIT_LAT                                               (0x7<<15) // This controls the value of the same field in the link_capability register in configuration space
3183     #define PCIEIP_REG_REG_LINK_CAPABILITY_L1_EXIT_LAT_SHIFT                                         15
3184     #define PCIEIP_REG_REG_LINK_CAPABILITY_L0S_EXIT_COMM_LAT                                         (0x7<<18) // This controls the value of the same field in the link_capability register in configuration space
3185     #define PCIEIP_REG_REG_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_SHIFT                                   18
3186     #define PCIEIP_REG_REG_LINK_CAPABILITY_L1_EXIT_COMM_LAT                                          (0x7<<21) // This controls the value of the same field in the link_capability register in configuration space
3187     #define PCIEIP_REG_REG_LINK_CAPABILITY_L1_EXIT_COMM_LAT_SHIFT                                    21
3188     #define PCIEIP_REG_REG_LINK_CAPABILITY_PORT_NUM                                                  (0xff<<24) // This controls the value of the same field in the link_capability register in configuration space
3189     #define PCIEIP_REG_REG_LINK_CAPABILITY_PORT_NUM_SHIFT                                            24
3190 #define PCIEIP_REG_REG_BAR2_CONFIG                                                                   0x0004e0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3191     #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_SIZE                                                     (0xf<<0) // These bits control the size of the BAR2 area advertised in the bar_3 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. Default is 64K bytes.
3192     #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_SIZE_SHIFT                                               0
3193     #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_64ENA                                                    (0x1<<4) // This bit enables the advertisement of bar_3 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_3. This value is sticky and only reset by HARD Reset. Default is 64bit addressing.
3194     #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_64ENA_SHIFT                                              4
3195     #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_PREFETCH                                                 (0x1<<5) // This bit when set is reflected in bit 3 of bar_3 and indicates that the BAR is pre-fetchable
3196     #define PCIEIP_REG_REG_BAR2_CONFIG_BAR2_PREFETCH_SHIFT                                           5
3197     #define PCIEIP_REG_REG_BAR2_CONFIG_RESERVED                                                      (0x3ffffff<<6) //
3198     #define PCIEIP_REG_REG_BAR2_CONFIG_RESERVED_SHIFT                                                6
3199 #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2                                                      0x0004e4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3200     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP                               (0xf<<0) // Completion Timeout Ranges Supported. Controls value in same field in the config space 0xF- Ranges A,B,C and D
3201     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP_SHIFT                         0
3202     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP                              (0x1<<4) // Completion Timeout Disable Supported, Controls value in same field in the config space
3203     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP_SHIFT                        4
3204     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_RESERVED1                                        (0x1f<<5) // unused
3205     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_RESERVED1_SHIFT                                  5
3206     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_IDO_SUPPORTED                                    (0x1<<10) // This bit is valid only if IDO_Enabled is defined in version.v. When this bit is set, IDO feature is made visible to external config access.
3207     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_IDO_SUPPORTED_SHIFT                              10
3208     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_UNUSED0                                          (0x7f<<11) //
3209     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_UNUSED0_SHIFT                                    11
3210     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_OBFF_SUPPORTED                                   (0x3<<18) // This indicates that OBFF is supported using WAKE# signalling only. It is recommended to set this value to 2 or 3(also supported using Messages) This bit is valid only if PCIE_OBFF_SUPP is defined in version.v. When this bit is set, OBFF feature is made visible to external config access.
3211     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_OBFF_SUPPORTED_SHIFT                             18
3212     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_RESERVED                                         (0xfff<<20) // unused
3213     #define PCIEIP_REG_REG_PCIE_DEVICE_CAPABILITY_2_RESERVED_SHIFT                                   20
3214 #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_2                                                        0x0004e8UL //Access:RW   DataWidth:0x20  Place holder for now  Chips: BB_A0 BB_B0
3215 #define PCIEIP_REG_REG_PCIE_LINK_CONTROL                                                             0x0004ecUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3216     #define PCIEIP_REG_REG_PCIE_LINK_CONTROL_RC_RCB                                                  (0x1<<0) // Not supported for EP
3217     #define PCIEIP_REG_REG_PCIE_LINK_CONTROL_RC_RCB_SHIFT                                            0
3218 #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC                                                       0x0004f0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3219     #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_RC_DL_ACTIVE_CAP                                  (0x1<<0) // RC only. If set, indicates dl_active capability at bit 20 of link_capability register. For EP, this field will not has any effect in link_capability register.
3220     #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_RC_DL_ACTIVE_CAP_SHIFT                            0
3221     #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_SLOT_CLK_CONFIG                                   (0x1<<1) // If set, indicates device use the same reference clock that the platform provides on the connector.
3222     #define PCIEIP_REG_REG_PCIE_LINK_CAPABILITY_RC_SLOT_CLK_CONFIG_SHIFT                             1
3223 #define PCIEIP_REG_REG_BAR3_CONFIG                                                                   0x0004f4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3224     #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_SIZE                                                     (0xf<<0) // These bits control the size of the BAR3 area advertised in the bar_5 register of the PCI configuration space. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3225     #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_SIZE_SHIFT                                               0
3226     #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_64ENA                                                    (0x1<<4) // This bit enables the advertisement of bar_5 as a 32-bit address. The value of this bit maps directly to bit 2 of bar_5. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3227     #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_64ENA_SHIFT                                              4
3228     #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_PREFETCH                                                 (0x1<<5) // This bit when set is reflected in bit 3 of bar_5 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
3229     #define PCIEIP_REG_REG_BAR3_CONFIG_BAR3_PREFETCH_SHIFT                                           5
3230     #define PCIEIP_REG_REG_BAR3_CONFIG_RESERVED                                                      (0x3ffffff<<6) //
3231     #define PCIEIP_REG_REG_BAR3_CONFIG_RESERVED_SHIFT                                                6
3232 #define PCIEIP_REG_REG_ROOT_CAP                                                                      0x0004f8UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3233     #define PCIEIP_REG_REG_ROOT_CAP_RC_CRS_CAP                                                       (0x1<<0) // This register is reserved for RC only. It is not applicable for EP.
3234     #define PCIEIP_REG_REG_ROOT_CAP_RC_CRS_CAP_SHIFT                                                 0
3235     #define PCIEIP_REG_REG_ROOT_CAP_RC_LTR_SUPPORTED                                                 (0x1<<1) // This register is reserved for RC only. It is not applicable for EP.
3236     #define PCIEIP_REG_REG_ROOT_CAP_RC_LTR_SUPPORTED_SHIFT                                           1
3237     #define PCIEIP_REG_REG_ROOT_CAP_RC_CLKREQ_SUPPORTED                                              (0x1<<2) // This register is reserved for RC only. It is not applicable for EP.
3238     #define PCIEIP_REG_REG_ROOT_CAP_RC_CLKREQ_SUPPORTED_SHIFT                                        2
3239     #define PCIEIP_REG_REG_ROOT_CAP_RC_EXT2_CAP_ENA                                                  (0x1f<<3) // If it is set, indicates RC supports CLKREQ Enable for the RC extended capability structures. Basic extended capability structure is defined in bits 31:30 of RC_EXT_CAP_ENA field . AER in bits 31:30 is always enabled, so that extended capability structure will follow the requirement of starting at 0x100. L1Sub capability will be present only if PMCR_RC_L1_SUBSTATES_ENA is defined in version.v Secondary PCIE extended capability will be present only if pcieGen3Rate is defined in version.v
3240     #define PCIEIP_REG_REG_ROOT_CAP_RC_EXT2_CAP_ENA_SHIFT                                            3
3241 #define PCIEIP_REG_REG_ROOT_CONTROL                                                                  0x0004fcUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3242     #define PCIEIP_REG_REG_ROOT_CONTROL_RC_CLKREQ_ENABLED                                            (0x1<<0) // This register is reserved for RC only. It is not applicable for EP.
3243     #define PCIEIP_REG_REG_ROOT_CONTROL_RC_CLKREQ_ENABLED_SHIFT                                      0
3244 #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID                                                            0x000500UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3245     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_DEV_SER_NUM_CAP_ID                                     (0xffff<<0) // This register controls the value of CAP_ID in the DEV_SER_NUM_CAP_ID (0x13C) register in the configuration space.
3246     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_DEV_SER_NUM_CAP_ID_SHIFT                               0
3247     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_DEV_SER_NUM_CAP_VER                                    (0xf<<16) // This register controls the value of CAP_VER in the DEV_SER_NUM_CAP_ID (0x13C) register in the configuration space.
3248     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_DEV_SER_NUM_CAP_VER_SHIFT                              16
3249     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA                                            (0x3f<<20) // Enable for the EP extended capability structures. Default the link list is adv err, dev serial, pwr budget, virtual channel LTR capability will be present only if LTR_ENABLED is defined in version.v
3250     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_EXT_CAP_ENA_SHIFT                                      20
3251     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_EXT_REG_CAP_ENA                                        (0xf<<26) // Reserved Enable for the EP extended capability structures. Basic extended capability structure is defined in bits 25:20. AER in bits 25:20 should always be enabled, so that extended capability structure will follow the requirement of starting at 0x100. ARI, SRIOV capability will be present only if SRIOV is defined in version.v SRIOV capability should not be enabled without enabling ARI capability. ATS capability will be present only if ATS_ON is defined in version.v
3252     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_EXT_REG_CAP_ENA_SHIFT                                  26
3253     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_RC_EXT_CAP_ENA                                         (0x3<<30) // Enable for the RC extended capability structures
3254     #define PCIEIP_REG_REG_DEV_SER_NUM_CAP_ID_RC_EXT_CAP_ENA_SHIFT                                   30
3255 #define PCIEIP_REG_REG_LOWER_SER_NUM                                                                 0x000504UL //Access:RW   DataWidth:0x20  This register controls the value in the LOWER_SER_NUM (0x104) in the configuration space.  Chips: BB_A0 BB_B0
3256 #define PCIEIP_REG_REG_UPPER_SER_NUM                                                                 0x000508UL //Access:RW   DataWidth:0x20  This register controls the value in the UPPER_SER_NUM (0x108) in the configuration space.  Chips: BB_A0 BB_B0
3257 #define PCIEIP_REG_REG_ADV_ERR_CAP                                                                   0x00050cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3258     #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_CHK_CAP                                                  (0x1<<0) // This value controls the corresponding bit in the ADV_ERR_CAP _CONTROL (0x128)
3259     #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_CHK_CAP_SHIFT                                            0
3260     #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_GEN_CAP                                                  (0x1<<1) // This value controls the corresponding bit in the ADV_ERR_CAP _CONTROL (0x128)
3261     #define PCIEIP_REG_REG_ADV_ERR_CAP_ECRC_GEN_CAP_SHIFT                                            1
3262 #define PCIEIP_REG_REG_PWR_BDGT_DATA_0                                                               0x000510UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3263     #define PCIEIP_REG_REG_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 0. This value is sticky and only reset by HARD Reset.
3264     #define PCIEIP_REG_REG_PWR_BDGT_DATA_0_PWR_BDGT_DATA_0_SHIFT                                     0
3265     #define PCIEIP_REG_REG_PWR_BDGT_DATA_0_RESERVED                                                  (0x7ff<<21) //
3266     #define PCIEIP_REG_REG_PWR_BDGT_DATA_0_RESERVED_SHIFT                                            21
3267 #define PCIEIP_REG_REG_PWR_BDGT_DATA_1                                                               0x000514UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3268     #define PCIEIP_REG_REG_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 1. This value is sticky and only reset by HARD Reset.
3269     #define PCIEIP_REG_REG_PWR_BDGT_DATA_1_PWR_BDGT_DATA_1_SHIFT                                     0
3270     #define PCIEIP_REG_REG_PWR_BDGT_DATA_1_RW                                                        (0x7ff<<21) //
3271     #define PCIEIP_REG_REG_PWR_BDGT_DATA_1_RW_SHIFT                                                  21
3272 #define PCIEIP_REG_REG_PWR_BDGT_DATA_2                                                               0x000518UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3273     #define PCIEIP_REG_REG_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 2. This value is sticky and only reset by HARD Reset.
3274     #define PCIEIP_REG_REG_PWR_BDGT_DATA_2_PWR_BDGT_DATA_2_SHIFT                                     0
3275     #define PCIEIP_REG_REG_PWR_BDGT_DATA_2_RW                                                        (0x7ff<<21) //
3276     #define PCIEIP_REG_REG_PWR_BDGT_DATA_2_RW_SHIFT                                                  21
3277 #define PCIEIP_REG_REG_PWD_BDGT_DATA_3                                                               0x00051cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3278     #define PCIEIP_REG_REG_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 3. This value is sticky and only reset by HARD Reset.
3279     #define PCIEIP_REG_REG_PWD_BDGT_DATA_3_PWR_BDGT_DATA_3_SHIFT                                     0
3280     #define PCIEIP_REG_REG_PWD_BDGT_DATA_3_RW                                                        (0x7ff<<21) //
3281     #define PCIEIP_REG_REG_PWD_BDGT_DATA_3_RW_SHIFT                                                  21
3282 #define PCIEIP_REG_REG_PWR_BDGT_DATA_4                                                               0x000520UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3283     #define PCIEIP_REG_REG_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 4. This value is sticky and only reset by HARD Reset.
3284     #define PCIEIP_REG_REG_PWR_BDGT_DATA_4_PWR_BDGT_DATA_4_SHIFT                                     0
3285     #define PCIEIP_REG_REG_PWR_BDGT_DATA_4_RW                                                        (0x7ff<<21) //
3286     #define PCIEIP_REG_REG_PWR_BDGT_DATA_4_RW_SHIFT                                                  21
3287 #define PCIEIP_REG_REG_PWR_BDGT_DATA_5                                                               0x000524UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3288     #define PCIEIP_REG_REG_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 5. This value is sticky and only reset by HARD Reset.
3289     #define PCIEIP_REG_REG_PWR_BDGT_DATA_5_PWR_BDGT_DATA_5_SHIFT                                     0
3290     #define PCIEIP_REG_REG_PWR_BDGT_DATA_5_RW                                                        (0x7ff<<21) //
3291     #define PCIEIP_REG_REG_PWR_BDGT_DATA_5_RW_SHIFT                                                  21
3292 #define PCIEIP_REG_REG_PWR_BDGT_DATA_6                                                               0x000528UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3293     #define PCIEIP_REG_REG_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 6. This value is sticky and only reset by HARD Reset.
3294     #define PCIEIP_REG_REG_PWR_BDGT_DATA_6_PWR_BDGT_DATA_6_SHIFT                                     0
3295     #define PCIEIP_REG_REG_PWR_BDGT_DATA_6_RW                                                        (0x7ff<<21) //
3296     #define PCIEIP_REG_REG_PWR_BDGT_DATA_6_RW_SHIFT                                                  21
3297 #define PCIEIP_REG_REG_PWR_BDGT_DATA_7                                                               0x00052cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3298     #define PCIEIP_REG_REG_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 7. This value is sticky and only reset by HARD Reset.
3299     #define PCIEIP_REG_REG_PWR_BDGT_DATA_7_PWR_BDGT_DATA_7_SHIFT                                     0
3300     #define PCIEIP_REG_REG_PWR_BDGT_DATA_7_RW                                                        (0x7ff<<21) //
3301     #define PCIEIP_REG_REG_PWR_BDGT_DATA_7_RW_SHIFT                                                  21
3302 #define PCIEIP_REG_REG_EXT2_CAP_ADDR                                                                 0x000530UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3303     #define PCIEIP_REG_REG_EXT2_CAP_ADDR_EXT2_CAP_ENA                                                (0xf<<0) // Enable for the EP extended capability structures. Basic extended capability structure is defined in bits 25:20 and additional extended capability is in 29:26 in dev_ser_num_cap_id register. AER in bits 25:20 should always be enabled, so that extended capability structure will follow the requirement of starting at 0x100. TPH capability will be present only if TPH_ON is defined in version.v SRIOV capability should not be enabled without enabling ARI capability. Secondary PCIE extended capability will be present only if pcieGen3Rate is defined in version.v
3304     #define PCIEIP_REG_REG_EXT2_CAP_ADDR_EXT2_CAP_ENA_SHIFT                                          0
3305     #define PCIEIP_REG_REG_EXT2_CAP_ADDR_EXT3_CAP_ENA                                                (0xf<<4) // Enable for the EP extended capability structures. Basic extended capability structure is defined in bits 25:20 and additional extended capability is in 29:26 in dev_ser_num_cap_id register. The next set of capabilities are defined in etx2_cap_ena in bits 3:0 of this register. This register enables the PTM capability which will be present PCIE_PTM_SUPP is defined in version.v
3306     #define PCIEIP_REG_REG_EXT2_CAP_ADDR_EXT3_CAP_ENA_SHIFT                                          4
3307     #define PCIEIP_REG_REG_EXT2_CAP_ADDR_RW                                                          (0xffffff<<8) //
3308     #define PCIEIP_REG_REG_EXT2_CAP_ADDR_RW_SHIFT                                                    8
3309 #define PCIEIP_REG_REG_PWR_BDGT_DATA_8                                                               0x000534UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3310     #define PCIEIP_REG_REG_PWR_BDGT_DATA_8_PWR_BDGT_DATA_8                                           (0x1fffff<<0) // This is the value read from the pwr_bdgt_data register (0x158) when the pwr_bdgt_data_sel register (0x154) value is 7. This value is sticky and only reset by HARD Reset.
3311     #define PCIEIP_REG_REG_PWR_BDGT_DATA_8_PWR_BDGT_DATA_8_SHIFT                                     0
3312     #define PCIEIP_REG_REG_PWR_BDGT_DATA_8_RESERVED                                                  (0x7ff<<21) //
3313     #define PCIEIP_REG_REG_PWR_BDGT_DATA_8_RESERVED_SHIFT                                            21
3314 #define PCIEIP_REG_REG_L1SUB_CAP                                                                     0x000540UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3315     #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_2_SUPP                                                    (0x1<<0) // Advertize L1_2 capability support for PM
3316     #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_2_SUPP_SHIFT                                              0
3317     #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_1_SUPP                                                    (0x1<<1) // Advertize L1_1 capability support for PM
3318     #define PCIEIP_REG_REG_L1SUB_CAP_PM_L1_1_SUPP_SHIFT                                              1
3319     #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_2_SUPP                                                  (0x1<<2) // Advertize L1_2 capability support for ASPM
3320     #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_2_SUPP_SHIFT                                            2
3321     #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_1_SUPP                                                  (0x1<<3) // Advertize L1_1 capability support for ASPM
3322     #define PCIEIP_REG_REG_L1SUB_CAP_ASPM_L1_1_SUPP_SHIFT                                            3
3323     #define PCIEIP_REG_REG_L1SUB_CAP_CLKREQ_L1SUB_SUPP                                               (0x1<<4) // Clkreq based L1 substates is supported.
3324     #define PCIEIP_REG_REG_L1SUB_CAP_CLKREQ_L1SUB_SUPP_SHIFT                                         4
3325     #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_1                                                      (0x7<<5) //
3326     #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_1_SHIFT                                                5
3327     #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_CMN_MODE_UP_TIME                                          (0xff<<8) // Time in us that device advertizes that it requires to re-establish common mode.
3328     #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_CMN_MODE_UP_TIME_SHIFT                                    8
3329     #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_PWR_ON_SCALE                                              (0x3<<16) // Along with the value field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface.
3330     #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_PWR_ON_SCALE_SHIFT                                        16
3331     #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_0                                                      (0x1<<18) //
3332     #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_0_SHIFT                                                18
3333     #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_PWR_ON_VALUE                                              (0x1f<<19) // Along with the scale field, this field advertizes the tpower_on time in us, that the link partner must wait when exiting from L1_2 state due to driving CLKREQ#, before actively driving the interface.
3334     #define PCIEIP_REG_REG_L1SUB_CAP_L1SUB_PWR_ON_VALUE_SHIFT                                        19
3335     #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED                                                        (0xff<<24) //
3336     #define PCIEIP_REG_REG_L1SUB_CAP_RESERVED_SHIFT                                                  24
3337 #define PCIEIP_REG_REG_L1SUB_EXT_CAP                                                                 0x000544UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3338     #define PCIEIP_REG_REG_L1SUB_EXT_CAP_L1SUB_VERSION_CAPID                                         (0xfffff<<0) // This field is provided to program the cap ID and version number for L1 substates capability structure. The field was not finalized as of time of implementation and so is programmable.
3339     #define PCIEIP_REG_REG_L1SUB_EXT_CAP_L1SUB_VERSION_CAPID_SHIFT                                   0
3340     #define PCIEIP_REG_REG_L1SUB_EXT_CAP_RESERVED                                                    (0xfff<<20) //
3341     #define PCIEIP_REG_REG_L1SUB_EXT_CAP_RESERVED_SHIFT                                              20
3342 #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY                                                           0x000550UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3343     #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_PWR_SYSTEM_ALLOC                                      (0x1<<0) // This bit controls the system alloc bit in the PWR_BDGT_CAP (0x15c) in the configuration space
3344     #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_PWR_SYSTEM_ALLOC_SHIFT                                0
3345     #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_RESERVED                                              (0x7fffffff<<1) //
3346     #define PCIEIP_REG_REG_PWR_BDGT_CAPABILITY_RESERVED_SHIFT                                        1
3347 #define PCIEIP_REG_REG_VSEC_HDR                                                                      0x000554UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3348     #define PCIEIP_REG_REG_VSEC_HDR_VSEC_ID                                                          (0xffff<<0) // Vendor defined ID of VSEC structure. Software must qualify the Vendor ID and VSEC ID before interpreting this field.
3349     #define PCIEIP_REG_REG_VSEC_HDR_VSEC_ID_SHIFT                                                    0
3350     #define PCIEIP_REG_REG_VSEC_HDR_VSEC_REV                                                         (0xf<<16) // Vendor defined version number of VSEC structure.
3351     #define PCIEIP_REG_REG_VSEC_HDR_VSEC_REV_SHIFT                                                   16
3352     #define PCIEIP_REG_REG_VSEC_HDR_VSEC_LENGTH                                                      (0xfff<<20) // VSEC Length: Indicates the number of bytes in the entire VSEC structure, including the PCI Express Enhanced Capacbility Header, Vendor Specific Header, and the Vendor Specific Registers.
3353     #define PCIEIP_REG_REG_VSEC_HDR_VSEC_LENGTH_SHIFT                                                20
3354 #define PCIEIP_REG_REG_RC_USER_MEM_LO1                                                               0x000558UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3355     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_SIZE1                                             (0xf<<0) // These bits control the size of the user BAR1 area. This value is sticky and only reset by HARD Reset. This register is only applicable for RC.
3356     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_SIZE1_SHIFT                                       0
3357     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_2                                                  (0x7<<4) //
3358     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_2_SHIFT                                            4
3359     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_EN1                                           (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory transactions received in Rx direction are compared against the user defined address range before it is forwarded to user. If requests do not fall in this USer BAR area, the request is target aborted.
3360     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_EN1_SHIFT                                     7
3361     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_1                                                  (0xff<<8) //
3362     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_UNUSED_1_SHIFT                                            8
3363     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_ADDR_LO1                                      (0xffff<<16) // USER_BAR_LOWER_ADDRESS: Lower 16 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.
3364     #define PCIEIP_REG_REG_RC_USER_MEM_LO1_RC_USER_MEM_ADDR_LO1_SHIFT                                16
3365 #define PCIEIP_REG_REG_RC_USER_MEM_HI1                                                               0x00055cUL //Access:R    DataWidth:0x20  USER_BAR_HIGHER_ADDRESS: Higher 32 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.  Chips: BB_A0 BB_B0
3366 #define PCIEIP_REG_REG_RC_USER_MEM_LO2                                                               0x000560UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3367     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_SIZE2                                             (0xf<<0) // These bits control the size of the user BAR1 area. This value is sticky and only reset by HARD Reset. This register is only applicable for RC.
3368     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_SIZE2_SHIFT                                       0
3369     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_2                                                  (0x7<<4) //
3370     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_2_SHIFT                                            4
3371     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_EN2                                           (0x1<<7) // Enable User Defined Mem area in RC mode. If this bit is set, then memory transactions received in Rx direction are compared against the user defined address range before it is forwarded to user. If requests do not fall in this USer BAR area, the request is target aborted.
3372     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_EN2_SHIFT                                     7
3373     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_1                                                  (0xff<<8) //
3374     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_UNUSED_1_SHIFT                                            8
3375     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_ADDR_LO2                                      (0xffff<<16) // USER_BAR_LOWER_ADDRESS: Lower 16 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.
3376     #define PCIEIP_REG_REG_RC_USER_MEM_LO2_RC_USER_MEM_ADDR_LO2_SHIFT                                16
3377 #define PCIEIP_REG_REG_RC_USER_MEM_HI2                                                               0x000564UL //Access:R    DataWidth:0x20  USER_BAR_HIGHER_ADDRESS: Higher 32 bits of BAR for user in RC mode. This is not the PCI standard compliant BAR, but is instead a mechanism for user to provide a mem range restriction over and above that specified by the PCI Base and Limit registers.  Chips: BB_A0 BB_B0
3378 #define PCIEIP_REG_REG_PCIER_MC_WINDOW_SIZE_REQ                                                      0x0005ecUL //Access:RW   DataWidth:0x20  This register is visible only if PCIE_EP_MC_SUPP is defined in version.v  Chips: BB_A0 BB_B0
3379     #define PCIEIP_REG_REG_PCIER_MC_WINDOW_SIZE_REQ_MC_WINDOW_SIZE_REQ                               (0x3f<<0) // Default value of this field is 64KB. This field will be reflected in the MC Capability register.
3380     #define PCIEIP_REG_REG_PCIER_MC_WINDOW_SIZE_REQ_MC_WINDOW_SIZE_REQ_SHIFT                         0
3381 #define PCIEIP_REG_REG_PTM_CAP                                                                       0x0005f0UL //Access:RW   DataWidth:0x20  This register is visible only if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
3382     #define PCIEIP_REG_REG_PTM_CAP_PTM_REQ_CAPABLE                                                   (0x1<<0) // This field will be reflected in the PTM capability register.
3383     #define PCIEIP_REG_REG_PTM_CAP_PTM_REQ_CAPABLE_SHIFT                                             0
3384     #define PCIEIP_REG_REG_PTM_CAP_PTM_CAP_SUPP                                                      (0x1<<1) // This field will be reflected in the PTM capability register. Field indicates device is capable of generating PTM requests.
3385     #define PCIEIP_REG_REG_PTM_CAP_PTM_CAP_SUPP_SHIFT                                                1
3386 #define PCIEIP_REG_REG_TPH_CAP                                                                       0x0005f4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3387     #define PCIEIP_REG_REG_TPH_CAP_TPH_INT_VEC_MODE_SUPP                                             (0x1<<0) // when Set, it indicates function supports Interrupt vector mode of op. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
3388     #define PCIEIP_REG_REG_TPH_CAP_TPH_INT_VEC_MODE_SUPP_SHIFT                                       0
3389     #define PCIEIP_REG_REG_TPH_CAP_TPH_DEV_SPEC_MODE                                                 (0x1<<1) // When Set, it indicates function suports device specific mode of operation. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
3390     #define PCIEIP_REG_REG_TPH_CAP_TPH_DEV_SPEC_MODE_SHIFT                                           1
3391     #define PCIEIP_REG_REG_TPH_CAP_TPH_ST_TABLE_LOCATION                                             (0x3<<2) // The IP supports only a value of 0, which would indicate ST Table is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. All other values should not be programmed. The value programmed here is reflected in the corresponding field of the PCIE defined TPH Capability register.
3392     #define PCIEIP_REG_REG_TPH_CAP_TPH_ST_TABLE_LOCATION_SHIFT                                       2
3393     #define PCIEIP_REG_REG_TPH_CAP_TPH_ST_TABLE_SIZE                                                 (0x7ff<<4) // This field will be reflected in the ST Table Size field of the PCIE defined TPH capability register. The value programmed here indicates a table size of value + 1.
3394     #define PCIEIP_REG_REG_TPH_CAP_TPH_ST_TABLE_SIZE_SHIFT                                           4
3395 #define PCIEIP_REG_REG_RESIZEBAR_CAP                                                                 0x0005f8UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3396     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_CAPABILITY                                             (0xf<<0) // unused
3397     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_CAPABILITY_SHIFT                                       0
3398     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1M_CAPABILITY                                          (0x1<<4) // when Set, it indicates function will operate with Bar sized to 1M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3399     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1M_CAPABILITY_SHIFT                                    4
3400     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_2M_CAPABILITY                                          (0x1<<5) // when Set, it indicates function will operate with Bar sized to 2M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3401     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_2M_CAPABILITY_SHIFT                                    5
3402     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_4M_CAPABILITY                                          (0x1<<6) // when Set, it indicates function will operate with Bar sized to 4M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3403     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_4M_CAPABILITY_SHIFT                                    6
3404     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_8M_CAPABILITY                                          (0x1<<7) // when Set, it indicates function will operate with Bar sized to 8M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3405     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_8M_CAPABILITY_SHIFT                                    7
3406     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_16M_CAPABILITY                                         (0x1<<8) // when Set, it indicates function will operate with Bar sized to 16M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3407     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_16M_CAPABILITY_SHIFT                                   8
3408     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_32M_CAPABILITY                                         (0x1<<9) // when Set, it indicates function will operate with Bar sized to 32M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3409     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_32M_CAPABILITY_SHIFT                                   9
3410     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_64M_CAPABILITY                                         (0x1<<10) // when Set, it indicates function will operate with Bar sized to 64M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3411     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_64M_CAPABILITY_SHIFT                                   10
3412     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_128M_CAPABILITY                                        (0x1<<11) // when Set, it indicates function will operate with Bar sized to 128M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3413     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_128M_CAPABILITY_SHIFT                                  11
3414     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_256M_CAPABILITY                                        (0x1<<12) // when Set, it indicates function will operate with Bar sized to 256M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3415     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_256M_CAPABILITY_SHIFT                                  12
3416     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512M_CAPABILITY                                        (0x1<<13) // when Set, it indicates function will operate with Bar sized to 512M. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3417     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512M_CAPABILITY_SHIFT                                  13
3418     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1G_CAPABILITY                                          (0x1<<14) // when Set, it indicates function will operate with Bar sized to 1G. Value programmed here is reflected in the corresponding bits in the RBAR_CAP register.
3419     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_1G_CAPABILITY_SHIFT                                    14
3420     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512G_TO_2G_CAPABILITY                                  (0x1ff<<15) // unsupported.
3421     #define PCIEIP_REG_REG_RESIZEBAR_CAP_SIZE_512G_TO_2G_CAPABILITY_SHIFT                            15
3422 #define PCIEIP_REG_REG_ARI_CAP                                                                       0x0005fcUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3423     #define PCIEIP_REG_REG_ARI_CAP_NEXT_FUNCTION_NUMBER                                              (0xff<<0) // Value programmed here is reflected in the corresponding bits in the ari_control_register. This field should be programmed to indicate the next function number of the next higher numbered function in the device or 00h, if there are no higher numbered functions.
3424     #define PCIEIP_REG_REG_ARI_CAP_NEXT_FUNCTION_NUMBER_SHIFT                                        0
3425 #define PCIEIP_REG_REG_INITVF                                                                        0x000600UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3426     #define PCIEIP_REG_REG_INITVF_INITIALVF                                                          (0xffff<<0) // Value programmed here is reflected in the corresponding bits in the SRIOV_InitialVF register. This field indicates maximum number of VFs initially associated with the PF. This value should be the same as TotalVF field.
3427     #define PCIEIP_REG_REG_INITVF_INITIALVF_SHIFT                                                    0
3428     #define PCIEIP_REG_REG_INITVF_TOTALVF                                                            (0xffff<<16) // Value programmed here is reflected in the corresponding bits in the SRIOV_TotalVF Cfg register. This field indicates maximum number of VFs associated with the PF.
3429     #define PCIEIP_REG_REG_INITVF_TOTALVF_SHIFT                                                      16
3430 #define PCIEIP_REG_REG_VF_OFFSET                                                                     0x000604UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3431     #define PCIEIP_REG_REG_VF_OFFSET_VF_OFFSET                                                       (0xffff<<0) // Value programmed here is reflected in the corresponding bits in the SRIOV_VFOffset cfg register. This field defines the Routing ID of the first VF that is associated with the PF. The first VF's routing ID is calculated by adding the RID of the PF with the contents of this field. This field should be programmed based on the programming in the FIRST_VF_NUM register in the tl_reg private register space. Each PF is expected to have a multiple of 8 VFs and so this field should be programmed accordingly.
3432     #define PCIEIP_REG_REG_VF_OFFSET_VF_OFFSET_SHIFT                                                 0
3433     #define PCIEIP_REG_REG_VF_OFFSET_DEVICEID                                                        (0xffff<<16) // Value programmed here is reflected in the corresponding bits in the SRIOV_VFOffset Cfg register. This field indicates device ID for all VFs associated with this PF. Reset value is based on VFDEVICE_ID field in version.v
3434     #define PCIEIP_REG_REG_VF_OFFSET_DEVICEID_SHIFT                                                  16
3435 #define PCIEIP_REG_REG_VF_BAR_REG                                                                    0x000608UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3436     #define PCIEIP_REG_REG_VF_BAR_REG_BAR0_SIZE_OF_VF                                                (0xf<<0) // This field influences the size of the VFs BAR register, advertized in the VF BAR0 register in the PCIE config space. This register is only applicable for EP.
3437     #define PCIEIP_REG_REG_VF_BAR_REG_BAR0_SIZE_OF_VF_SHIFT                                          0
3438     #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_64ENA                                                   (0x1<<4) // This bit enables the advertisement of VF BAR0 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR0. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3439     #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_64ENA_SHIFT                                             4
3440     #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_PREFETCH                                                (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR0 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
3441     #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR0_PREFETCH_SHIFT                                          5
3442     #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED0                                                        (0x3<<6) //
3443     #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED0_SHIFT                                                  6
3444     #define PCIEIP_REG_REG_VF_BAR_REG_BAR2_SIZE_OF_VF                                                (0xf<<8) // This field influences the size of the VFs BAR register, advertized in the VF BAR2 register in the PCIE config space. This register is only applicable for EP.
3445     #define PCIEIP_REG_REG_VF_BAR_REG_BAR2_SIZE_OF_VF_SHIFT                                          8
3446     #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_64ENA                                                   (0x1<<12) // This bit enables the advertisement of VF BAR2 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR2. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3447     #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_64ENA_SHIFT                                             12
3448     #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_PREFETCH                                                (0x1<<13) // This bit when set is reflected in bit 3 of VF BAR2 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
3449     #define PCIEIP_REG_REG_VF_BAR_REG_VFBAR2_PREFETCH_SHIFT                                          13
3450     #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED1                                                        (0x3<<14) //
3451     #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED1_SHIFT                                                  14
3452     #define PCIEIP_REG_REG_VF_BAR_REG_SRIOV_CAP_VERSION                                              (0xf<<16) // Value programmed here is reflected in the corresponding bits in the SRIOV Capability Cfg register. This field is PCI_SIG defined version number that indicates version of capability structure present .
3453     #define PCIEIP_REG_REG_VF_BAR_REG_SRIOV_CAP_VERSION_SHIFT                                        16
3454     #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED2                                                        (0xf<<20) //
3455     #define PCIEIP_REG_REG_VF_BAR_REG_UNUSED2_SHIFT                                                  20
3456     #define PCIEIP_REG_REG_VF_BAR_REG_FUNC_DEPENDENCY_LINK                                           (0xff<<24) // Value programmed here is reflected in the corresponding bits in the SRIOV Extended Capability Cfg register. This field is used to describe vendor specific dependencies between sets of functions.
3457     #define PCIEIP_REG_REG_VF_BAR_REG_FUNC_DEPENDENCY_LINK_SHIFT                                     24
3458 #define PCIEIP_REG_REG_VF_SUPP_PAGE_SIZE                                                             0x00060cUL //Access:RW   DataWidth:0x20  Value programmed here is reflected in the corresponding bits in the SRIOV_SupportedPageSize Cfg register. This field indicates page sizes supported by the PF. PFs are required to support 4k, 8K, 64K, 256K, 1MB and 4MB page sizes. This PF supports a page size of 2^n+12 if bit n is set. For eg, if bit 0 is set, PF supports 4K page sizes.  Chips: BB_A0 BB_B0
3459 #define PCIEIP_REG_REG_VF_CAP_EN                                                                     0x000610UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3460     #define PCIEIP_REG_REG_VF_CAP_EN_VF_CAP_EN                                                       (0x1<<0) // This value controls the read value of the next capability pointers in the VF configuration space and allows each extra capability to be independently disabled by manipulation of the next pointer values. The read values for each enable combination is shown below. PCIE capability is always enabled. Bit 0 enables the MSIX capability. This value is sticky and only reset by HARD Reset. Value affects only the VF's that belong to the PF.
3461     #define PCIEIP_REG_REG_VF_CAP_EN_VF_CAP_EN_SHIFT                                                 0
3462     #define PCIEIP_REG_REG_VF_CAP_EN_UNUSED0                                                         (0x7f<<1) //
3463     #define PCIEIP_REG_REG_VF_CAP_EN_UNUSED0_SHIFT                                                   1
3464     #define PCIEIP_REG_REG_VF_CAP_EN_VF_EXT_CAP_EN                                                   (0x3f<<8) // Enable for the VF extended capability structures in the VF config space. Value programmed here only affects the VF cfg space belonging to the PF Default value of the link list is adv err, which has to be present always to allow extended config space to start at 0x100. Also ARI cap needs to always be present.
3465     #define PCIEIP_REG_REG_VF_CAP_EN_VF_EXT_CAP_EN_SHIFT                                             8
3466 #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF                                                           0x000614UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3467     #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR                                       (0x7<<0) // This register controls the read value of the MSIX_TBL_OFF_BIR[2:0] register in the VF Cfg space. This indicates which one of the function's Base address registers located in SRIOV capability structure of PF configuration space is used to map the function's MSI-X table into memory space. All the VFs that belong to this PF use the same BIR value.
3468     #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR_SHIFT                                 0
3469     #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR_OFF                                   (0x1fffffff<<3) // This register controls the read value of the MSIX_TBL_OFF_BIR[31:3] register in the VF cfg space. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X table . All the VF's that belong to this PF use the same offset value.
3470     #define PCIEIP_REG_REG_VF_MSIX_TBL_BIR_OFF_VF_MSIX_TBL_BIR_OFF_SHIFT                             3
3471 #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT                                                           0x000618UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3472     #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_BIR                                       (0x7<<0) // This register controls the read value of the MSIX_PBA_OFF_BIR[2:0] register in the VF Cfg space. This indicates which one of the function's Base address registers located in SRIOV capability structure in PF configuration space is used to map the VF's's MSI-X PBA into memory space. All the VF's that belong to the PF use the same BIT value. The value is controlled by IOV_MSIX_PBA_OFF define in version.v
3473     #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_BIR_SHIFT                                 0
3474     #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_OFF                                       (0x1fffffff<<3) // This register controls the read value of the MSIX_PBA_OFF_BIR[31:3] registern the VF Cfg space. This is used as an offset from the address contained by one of the functions Base address registers to point to the base of the MSI-X PBA
3475     #define PCIEIP_REG_REG_VF_MSIX_PBA_OFF_BIT_VF_MSIX_PBA_OFF_SHIFT                                 3
3476 #define PCIEIP_REG_REG_VF_MSIX_CONTROL                                                               0x00061cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3477     #define PCIEIP_REG_REG_VF_MSIX_CONTROL_VF_MSIX_TBL_SIZ                                           (0x3f<<0) // This field resides in VF only and does not exist in PF. This register controls the read value of the MSIX_CONTROL[10:0] register in the VF configuration space. A value of "00000000011" indicates a table size of 4. The value is controlled by IOV_MSIX_TBL_SIZ define in version.v
3478     #define PCIEIP_REG_REG_VF_MSIX_CONTROL_VF_MSIX_TBL_SIZ_SHIFT                                     0
3479     #define PCIEIP_REG_REG_VF_MSIX_CONTROL_RESERVEDVF_0                                              (0x3ffffff<<6) //
3480     #define PCIEIP_REG_REG_VF_MSIX_CONTROL_RESERVEDVF_0_SHIFT                                        6
3481 #define PCIEIP_REG_REG_VF_BAR4_REG                                                                   0x000620UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3482     #define PCIEIP_REG_REG_VF_BAR4_REG_BAR4_SIZE_OF_VF                                               (0xf<<0) // This field influences the size of the VFs BAR register, advertized in the VF BAR4 register in the PCIE config space. This register is only applicable for EP.
3483     #define PCIEIP_REG_REG_VF_BAR4_REG_BAR4_SIZE_OF_VF_SHIFT                                         0
3484     #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_64ENA                                                  (0x1<<4) // This bit enables the advertisement of VF BAR4 as a 64-bit address. The value of this bit maps directly to bit 2 of VF BAR4. This value is sticky and only reset by HARD Reset. This register is only applicable for EP.
3485     #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_64ENA_SHIFT                                            4
3486     #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_PREFETCH                                               (0x1<<5) // This bit when set is reflected in bit 3 of VF BAR4 and indicates that the BAR is pre-fetchable. This register is only applicable for EP.
3487     #define PCIEIP_REG_REG_VF_BAR4_REG_VFBAR4_PREFETCH_SHIFT                                         5
3488 #define PCIEIP_REG_REG_PF_INITVF                                                                     0x000624UL //Access:RW   DataWidth:0x20  Register programs the first VF allocation for a PF. All the VFs within IP are assumed to reside in a contiguous space starting at VFNUM =0. This register identifies the first VFNUM location for a PF. This register exists only in a PF  Chips: BB_A0 BB_B0
3489     #define PCIEIP_REG_REG_PF_INITVF_PF_FIRST_VF_NUM                                                 (0x1f<<0) // First VF_NUM for PF is encoded in this register. The number of VFs assigned to a PF is assumed to be a multiple of 8. Software should program these bits based on Total Number of VFs programmed for each PF.
3490     #define PCIEIP_REG_REG_PF_INITVF_PF_FIRST_VF_NUM_SHIFT                                           0
3491 #define PCIEIP_REG_REG_VF_NSP                                                                        0x000628UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3492     #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR0_NSP                                                      (0xf<<0) // This field describes the number of System pages needed by VF BAR0 belonging to PF. User Page Size(UPS) is determined by UABS &gt;&gt; NSP, where UABS is the User Advertized Bar Size and NSP is this field. BAR Size advertized is changed if SPS &gt; UPS, where SPS is System Page Size. Programming should ensure that resulting BAR size will not be bigger than 2G, so value of this field should be kept small if SPS is large.
3493     #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR0_NSP_SHIFT                                                0
3494     #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR2_NSP                                                      (0xf<<4) // This field describes the number of System pages needed by VF BAR2 belonging to PF. User Page Size(UPS) is determined by UABS &gt;&gt; NSP, where UABS is the User Advertized Bar Size and NSP is this field. BAR Size advertized is changed if SPS &gt; UPS, where SPS is System Page Size. Programming should ensure that resulting BAR size will not be bigger than 2G, so value of this field should be kept small if SPS is large.
3495     #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR2_NSP_SHIFT                                                4
3496     #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR4_NSP                                                      (0xf<<8) // This field describes the number of System pages needed by VF BAR4 belonging to PF. User Page Size(UPS) is determined by UABS &gt;&gt; NSP, where UABS is the User Advertized Bar Size and NSP is this field. BAR Size advertized is changed if SPS &gt; UPS, where SPS is System Page Size. Programming should ensure that resulting BAR size will not be bigger than 2G, so value of this field should be kept small if SPS is large.
3497     #define PCIEIP_REG_REG_VF_NSP_PF_VFBAR4_NSP_SHIFT                                                8
3498 #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH                                                          0x000630UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3499     #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_INVLD_QDEPTH                                     (0x1f<<0) // This register controls the corresponding value in the ATS capability register. This field advertizes the number of Invalidate requests the Function can accept before putting backpressure on the upstream connection.
3500     #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_INVLD_QDEPTH_SHIFT                               0
3501     #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_PAGE_ALIGNED_REQ                                 (0x1<<5) // This register controls the corresponding value in the ATS capability register. This field qhen Set, indicates the Untranslated Address always aligns to a 4K byte boundary. Setting this bit is recommended.
3502     #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_ATS_PAGE_ALIGNED_REQ_SHIFT                           5
3503     #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_RESERVEDVF_0                                         (0x3ffffff<<6) //
3504     #define PCIEIP_REG_REG_ATS_INLD_QUEUE_DEPTH_RESERVEDVF_0_SHIFT                                   6
3505 #define PCIEIP_REG_REG_VFTPH_CAP                                                                     0x000634UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3506     #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_INT_VEC_MODE_SUPP                                         (0x1<<0) // when Set, it indicates function supports Interrupt vector mode of op. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
3507     #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_INT_VEC_MODE_SUPP_SHIFT                                   0
3508     #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_DEV_SPEC_MODE                                             (0x1<<1) // When Set, it indicates function suports device specific mode of operation. Value programmed here is reflected in the corresponding bits in the TPH CAP register.
3509     #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_DEV_SPEC_MODE_SHIFT                                       1
3510     #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_ST_TABLE_LOCATION                                         (0x3<<2) // The IP supports only a value of 0, which would indicate ST Table is not present, or a value of 2, which indicates ST table is located in MSI-X Table structure. All other values should not be programmed. The value programmed here is reflected in the corresponding field of the PCIE defined TPH Capability register in VF.
3511     #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_ST_TABLE_LOCATION_SHIFT                                   2
3512     #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_ST_TABLE_SIZE                                             (0x7ff<<4) // This field will be reflected in the ST Table Size field of the PCIE defined TPH capability register in the VF. The value programmed here indicates a table size of value + 1.
3513     #define PCIEIP_REG_REG_VFTPH_CAP_VFTPH_ST_TABLE_SIZE_SHIFT                                       4
3514     #define PCIEIP_REG_REG_VFTPH_CAP_UNUSED0                                                         (0xffff<<15) //
3515     #define PCIEIP_REG_REG_VFTPH_CAP_UNUSED0_SHIFT                                                   15
3516     #define PCIEIP_REG_REG_VFTPH_CAP_TPH_SUPP_INVF                                                   (0x1<<31) // This field when set enables TPH capability in all the VF's.
3517     #define PCIEIP_REG_REG_VFTPH_CAP_TPH_SUPP_INVF_SHIFT                                             31
3518 #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF                                                             0x000700UL //Access:RW   DataWidth:0x20  Ack Latency Timer and Replay Timer Register.  Chips: K2
3519     #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT                           (0xffff<<0) // Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details, see "Ack Scheduling". You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-7, 3-8, and 3-9 of the PCIe 3.0 specification. The limit must reflect the round trip latency from requester to completer. If there is a change in the payload size or link width, the core will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_ACK_NAK field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.
3520     #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_ROUND_TRIP_LATENCY_TIME_LIMIT_SHIFT                     0
3521     #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT                                       (0xffff<<16) // Replay Timer Limit. The replay timer expires when it reaches this limit. The core initiates a replay upon reception of a NAK or when the replay timer expires. For more details, see "Transmit Replay". You can modify the effective timer limit with the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register. After reset, the core updates the default according to the Negotiated Link Width, Max_Payload_Size, and speed. The value is determined from Tables 3-4, 3-5, and 3-6 of the PCIe 3.0 specification. If there is a change in the payload size or link speed, the core will override any value that you have written to this register field, and reset the field back to the specification-defined value. It will not change the value in the TIMER_MOD_REPLAY_TIMER field of the TIMER_CTRL_MAX_FUNC_NUM_OFF register.
3522     #define PCIEIP_REG_ACK_LATENCY_TIMER_OFF_REPLAY_TIME_LIMIT_SHIFT                                 16
3523 #define PCIEIP_REG_VENDOR_SPEC_DLLP_OFF                                                              0x000704UL //Access:RW   DataWidth:0x20  Vendor Specific DLLP Register.  Chips: K2
3524 #define PCIEIP_REG_PORT_FORCE_OFF                                                                    0x000708UL //Access:RW   DataWidth:0x20  Port Force Link Register.  Chips: K2
3525     #define PCIEIP_REG_PORT_FORCE_OFF_LINK_NUM                                                       (0xff<<0) // Link Number. Not used for endpoint. Not used for M-PCIe.  Note: This register field is sticky.
3526     #define PCIEIP_REG_PORT_FORCE_OFF_LINK_NUM_SHIFT                                                 0
3527     #define PCIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM                                                   (0xf<<8) // Forced Link Command. The link command that the core is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v.  Note: This register field is sticky.
3528     #define PCIEIP_REG_PORT_FORCE_OFF_FORCED_LTSSM_SHIFT                                             8
3529     #define PCIEIP_REG_PORT_FORCE_OFF_RSVDP_12                                                       (0x7<<12) // Reserved for future use.
3530     #define PCIEIP_REG_PORT_FORCE_OFF_RSVDP_12_SHIFT                                                 12
3531     #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN                                                       (0x1<<15) // Force Link. The core supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state, and to force the core to transmit a specific Link Command. Asserting this bit triggers the following actions:  - Forces the LTSSM to the state specified by the Forced LTSSM State field.  - Forces the core to transmit the command specified by the Forced Link Command field. This is a self-clearing register field. Reading from this register field always returns a "0".
3532     #define PCIEIP_REG_PORT_FORCE_OFF_FORCE_EN_SHIFT                                                 15
3533     #define PCIEIP_REG_PORT_FORCE_OFF_LINK_STATE                                                     (0x3f<<16) // Forced LTSSM State. The LTSSM state that the core is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v.  Note: This register field is sticky.
3534     #define PCIEIP_REG_PORT_FORCE_OFF_LINK_STATE_SHIFT                                               16
3535     #define PCIEIP_REG_PORT_FORCE_OFF_RSVDP_22                                                       (0x3<<22) // Reserved for future use.
3536     #define PCIEIP_REG_PORT_FORCE_OFF_RSVDP_22_SHIFT                                                 22
3537     #define PCIEIP_REG_PORT_FORCE_OFF_CPL_SENT_COUNT                                                 (0xff<<24) // Low Power Entrance Count. The Power Management state waits for this many clock cycles for the associated completion of a CfgWr to D-state register to go low-power. This register is intended for applications that do not let the core handle a completion for configuration request to the PMCSCR register. Not used in downstream ports.  Note: This register field is sticky.
3538     #define PCIEIP_REG_PORT_FORCE_OFF_CPL_SENT_COUNT_SHIFT                                           24
3539 #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF                                                               0x00070cUL //Access:RW   DataWidth:0x20  Ack Frequency and L0-L1 ASPM Control Register.  Chips: K2
3540     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_FREQ                                                  (0xff<<0) // Ack Frequency. The core accumulates the number of pending ACKs specified here (up to 255) before sending an ACK DLLP.  - 0: Indicates that this Ack frequency control feature is turned off. The core schedules a low-priority ACK DLLP for every TLP that it receives.  - 1-255: Indicates that the core will schedule a high-priority ACK after receiving this number of TLPs. It might schedule the ACK before receiving this number of TLPs, but never later. For a typical system, you do not have to modify the default setting. For more details, see "ACK/NAK Scheduling".  Note: This register field is sticky.
3541     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_FREQ_SHIFT                                            0
3542     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS                                                 (0xff<<8) // N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The core does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe.  Note: This register field is sticky.
3543     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ACK_N_FTS_SHIFT                                           8
3544     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS                                          (0xff<<16) // Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. This field is only writable (sticky) when all of the following configuration parameter equations are true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY The core does not support a value of zero; a value of zero can cause the LTSSM to go into the recovery state when exiting from L0s. This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R
3545     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_COMMON_CLK_N_FTS_SHIFT                                    16
3546     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY                                      (0x7<<24) // L0s Entrance Latency. Values correspond to:  - 000: 1 us  - 001: 2 us  - 010: 3 us  - 011: 4 us  - 100: 5 us  - 101: 6 us  - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe.  Note: This register field is sticky.
3547     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L0S_ENTRANCE_LATENCY_SHIFT                                24
3548     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY                                       (0x7<<27) // L1 Entrance Latency. Value range is:  - 000: 1 us  - 001: 2 us  - 010: 4 us  - 011: 8 us  - 100: 16 us  - 101: 32 us  - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used, or all of the credits are infinite.  Note: This register field is sticky.
3549     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_L1_ENTRANCE_LATENCY_SHIFT                                 27
3550     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM                                                (0x1<<30) // ASPM L1 Entry Control.  - 1: Core enters ASPM L1 after a period in which it has been idle.  - 0: Core enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky.
3551     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_ENTER_ASPM_SHIFT                                          30
3552     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_RSVDP_31                                                  (0x1<<31) // Reserved for future use.
3553     #define PCIEIP_REG_ACK_F_ASPM_CTRL_OFF_RSVDP_31_SHIFT                                            31
3554 #define PCIEIP_REG_PORT_LINK_CTRL_OFF                                                                0x000710UL //Access:RW   DataWidth:0x20  Port Link Control Register.  Chips: K2
3555     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ                                   (0x1<<0) // Vendor Specific DLLP Request. When software writes a '1' to this bit, the core transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF.  Reading from this self-clearing register field always returns a '0'.
3556     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_VENDOR_SPECIFIC_DLLP_REQ_SHIFT                             0
3557     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE                                           (0x1<<1) // Scramble Disable. Turns off data scrambling.  Note: This register field is sticky.
3558     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_SCRAMBLE_DISABLE_SHIFT                                     1
3559     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE                                            (0x1<<2) // Loopback Enable. Turns on loopback. For more details, see "Loopback". For M-PCIe, to force the master to enter Digital Loopback mode, you must set this field to "1" during Configuration.start state(initial discovery/configuration). M-PCIe doesn't support loopback mode from L0 state - only from Configuration.start.  Note: This register field is sticky.
3560     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LOOPBACK_ENABLE_SHIFT                                      2
3561     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT                                               (0x1<<3) // Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only).  Note: This register field is sticky.
3562     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RESET_ASSERT_SHIFT                                         3
3563     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RSVDP_4                                                    (0x1<<4) // Reserved for future use.
3564     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RSVDP_4_SHIFT                                              4
3565     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN                                                (0x1<<5) // DLL Link Enable. Enables link initialization. When DLL Link Enable =0, the core does not transmit InitFC DLLPs and does not establish a link.  Note: This register field is sticky.
3566     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_DLL_LINK_EN_SHIFT                                          5
3567     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE                                               (0x1<<6) // LINK_DISABLE is an internally reserved field. Do not use.  Note: This register field is sticky.
3568     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_DISABLE_SHIFT                                         6
3569     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE                                             (0x1<<7) // Fast Link Mode. Sets all internal timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The scaling factor is selected in FAST_LINK_SCALING_FACTOR(default : 1024) for all internal timers. Fast Link Mode can also be activated by setting the diag_ctrl_bus[2] pin to "1". For more details, see "SII Signals: Diagnostic Control". For M-PCIe, this field also affects Remain Hibern8 Time, Minimum Activate Time, and RRAP timeout. If this bit is set to '1', tRRAPInitiatorResponse is set to 1.88 ms(60 ms/32).  Note: This register field is sticky.
3570     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_FAST_LINK_MODE_SHIFT                                       7
3571     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE                                                  (0xf<<8) // LINK_RATE is an internally reserved field. Do not use.  Note: This register field is sticky.
3572     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_RATE_SHIFT                                            8
3573     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RSVDP_12                                                   (0xf<<12) // Reserved for future use.
3574     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RSVDP_12_SHIFT                                             12
3575     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE                                               (0x3f<<16) // Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Predetermined Number of Lanes" field of the "Link Width and Speed Change Control Register". For more information, see "How to Tie Off Unused Lanes". For information on upsizing and downsizing the link width, see "Link Establishment".  - 000001: x1  - 000011: x2  - 000111: x4  - 001111: x8  - 011111: x16  - 111111: x32 (not supported) This field is reserved (fixed to '0') for M-PCIe.  Note: This register field is sticky.
3576     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_LINK_CAPABLE_SHIFT                                         16
3577     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_UNUSED_0                                                   (0x3<<22) // reserved
3578     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_UNUSED_0_SHIFT                                             22
3579     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE                                              (0x1<<24) // BEACON_ENABLE is an internally reserved field. Do not use.  Note: This register field is sticky.
3580     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_BEACON_ENABLE_SHIFT                                        24
3581     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE                                        (0x1<<25) // CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use.  Note: This register field is sticky.
3582     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_CORRUPT_LCRC_ENABLE_SHIFT                                  25
3583     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH                                             (0x1<<26) // EXTENDED_SYNCH is an internally reserved field. Do not use.  Note: This register field is sticky.
3584     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_EXTENDED_SYNCH_SHIFT                                       26
3585     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE                             (0x1<<27) // TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use.  Note: This register field is sticky.
3586     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_TRANSMIT_LANE_REVERSALE_ENABLE_SHIFT                       27
3587     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RSVDP_28                                                   (0xf<<28) // Reserved for future use.
3588     #define PCIEIP_REG_PORT_LINK_CTRL_OFF_RSVDP_28_SHIFT                                             28
3589 #define PCIEIP_REG_LANE_SKEW_OFF                                                                     0x000714UL //Access:RW   DataWidth:0x20  Lane Skew Register.  Chips: K2
3590     #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW                                                (0xffffff<<0) // Insert Lane Skew for Transmit (not supported for x16). Optional feature that causes the core to insert skew between Lanes for test purposes. There are three bits per Lane. The value is in units of one symbol time. For example, the value 010b for a Lane forces a skew of two symbol times for that Lane. The maximum skew value for any Lane is 5 symbol times.  Note: This register field is sticky.
3591     #define PCIEIP_REG_LANE_SKEW_OFF_INSERT_LANE_SKEW_SHIFT                                          0
3592     #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE                                               (0x1<<24) // Flow Control Disable. Prevents the core from sending FC DLLPs.  Note: This register field is sticky.
3593     #define PCIEIP_REG_LANE_SKEW_OFF_FLOW_CTRL_DISABLE_SHIFT                                         24
3594     #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE                                                 (0x1<<25) // Ack/Nak Disable. Prevents the core from sending ACK and NAK DLLPs.  Note: This register field is sticky.
3595     #define PCIEIP_REG_LANE_SKEW_OFF_ACK_NAK_DISABLE_SHIFT                                           25
3596     #define PCIEIP_REG_LANE_SKEW_OFF_RSVDP_26                                                        (0x1f<<26) // Reserved for future use.
3597     #define PCIEIP_REG_LANE_SKEW_OFF_RSVDP_26_SHIFT                                                  26
3598     #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW                                     (0x1<<31) // Disable Lane-to-Lane Deskew. Causes the core to disable the internal Lane-to-Lane deskew logic.  Note: This register field is sticky.
3599     #define PCIEIP_REG_LANE_SKEW_OFF_DISABLE_LANE_TO_LANE_DESKEW_SHIFT                               31
3600 #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF                                                       0x000718UL //Access:RW   DataWidth:0x20  Timer Control and Max Function Number Register.  Chips: K2
3601     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM                                      (0xff<<0) // Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request).  Note: This register field is sticky.
3602     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_MAX_FUNC_NUM_SHIFT                                0
3603     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8                                           (0x3f<<8) // Reserved for future use.
3604     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_8_SHIFT                                     8
3605     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER                            (0x1f<<14) // Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed, and in increments of 256 clock cycles at Gen3 speed. A value of "0" represents no modification to the timer limit. For more details, see the REPLAY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register. At Gen3 speed, the core automatically changes the value of this field to DEFAULT_GEN3_REPLAY_ADJ. For M-PCIe, this field increases the time-out value for the replay timer in increments of 64 clock cycles at HS-Gear1, HS-Gear2, or HS-Gear3 speed.  Note: This register field is sticky.
3606     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_REPLAY_TIMER_SHIFT                      14
3607     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK                                 (0x1f<<19) // Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of "0" represents no modification to the timer value. For more details, see the ROUND_TRIP_LATENCY_TIME_LIMIT field of the ACK_LATENCY_TIMER_OFF register.  Note: This register field is sticky.
3608     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_TIMER_MOD_ACK_NAK_SHIFT                           19
3609     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER                                 (0x1f<<24) // UPDATE_FREQ_TIMER is an internally reserved field. Do not use.  Note: This register field is sticky.
3610     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_UPDATE_FREQ_TIMER_SHIFT                           24
3611     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR                          (0x3<<29) // Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE is set to 1b.  - 0: Scaling Factor is 1024 (1ms is 1us)  - 1: Scaling Factor is 256 (1ms is 4us)  - 2: Scaling Factor is 64 (1ms is 16us)  - 3: Scaling Factor is 16 (1ms is 64us) Not used for M-PCIe.  Note: This register field is sticky.
3612     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_FAST_LINK_SCALING_FACTOR_SHIFT                    29
3613     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31                                          (0x1<<31) // Reserved for future use.
3614     #define PCIEIP_REG_TIMER_CTRL_MAX_FUNC_NUM_OFF_RSVDP_31_SHIFT                                    31
3615 #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF                                                         0x00071cUL //Access:RW   DataWidth:0x20  Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.  Chips: K2
3616     #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL                                         (0x7ff<<0) // SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the core actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application must program this register accordingly. For example, if 1536 were programmed into this register (in a 250 MHz core), then the core actually transmits SKP ordered sets once every 1537 symbol times. The value programmed to this register is actually clock ticks and not symbol times. In a 125 MHz core, programming the value programmed to this register should be scaled down by a factor of 2 (because one clock tick = two symbol times in this case).  Note: This value is not used at Gen3 speed; the skip interval is hardcoded to 370 blocks.  Note: This register field is sticky.
3617     #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_SKP_INT_VAL_SHIFT                                   0
3618     #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER                                         (0xf<<11) // EIDLE_TIMER is an internally reserved field. Do not use.  Note: This register field is sticky.
3619     #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_EIDLE_TIMER_SHIFT                                   11
3620     #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER                                 (0x1<<15) // Disable FC Watchdog Timer.  Note: This register field is sticky.
3621     #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_DISABLE_FC_WD_TIMER_SHIFT                           15
3622     #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1                                         (0xffff<<16) // Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.  [31]: CX_FLT_MASK_RC_CFG_DISCARD  - 0: For RADM RC filter to not allow CFG transaction being received  - 1: For RADM RC filter to allow CFG transaction being received [30]: CX_FLT_MASK_RC_IO_DISCARD  - 0: For RADM RC filter to not allow IO transaction being received  - 1: For RADM RC filter to allow IO transaction being received [29]: CX_FLT_MASK_MSG_DROP  - 0: Drop MSG TLP (except for Vendor MSG). Send decoded message on the SII.  - 1: Do not Drop MSG (except for Vendor MSG). Send message TLPs to your application on TRGT1 and send decoded message on the SII.  - The default for this bit is the inverse of FLT_DROP_MSG. That is, if FLT_DROP_MSG =1, then the default of this bit is "0" (drop message TLPs). This bit only controls message TLPs other than Vendor MSGs. Vendor MSGs are controlled by Filter Mask Register 2, bits [1:0].  The core never passes ATS Invalidate messages to the SII interface regardless of this filter rule setting. The core passes all ATS Invalidate messages to TRGT1 (or AXI bridge master), as they are too big for the SII. [28]: CX_FLT_MASK_CPL_ECRC_DISCARD  - Only used when completion queue is advertised with infinite credits and is in store-and-forward mode.  - 0: Discard completions with ECRC errors  - 1: Allow completions with ECRC errors to be passed up  - Reserved field for SW. [27]: CX_FLT_MASK_ECRC_DISCARD  - 0: Discard TLPs with ECRC errors  - 1: Allow TLPs with ECRC errors to be passed up [26]: CX_FLT_MASK_CPL_LEN_MATCH  - 0: Enforce length match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err  - 1: MASK length match for completions [25]: CX_FLT_MASK_CPL_ATTR_MATCH  - 0: Enforce attribute match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask attribute match for completions [24]: CX_FLT_MASK_CPL_TC_MATCH  - 0: Enforce Traffic Class match for completions; a violation results in a malformed TLP error, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask Traffic Class match for completions [23]: CX_FLT_MASK_CPL_FUNC_MATCH  - 0: Enforce function match for completions; a violation results in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask function match for completions [22]: CX_FLT_MASK_CPL_REQID_MATCH  - 0: Enforce Req. Id match for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask Req. Id match for completions [21]: CX_FLT_MASK_CPL_TAGERR_MATCH  - 0: Enforce Tag Error Rules for completions; a violation result in cpl_abort, and possibly AER of unexp_cpl_err, cpl_rcvd_ur, cpl_rcvd_ca  - 1: Mask Tag Error Rules for completions [20]: CX_FLT_MASK_LOCKED_RD_AS_UR  - 0: Treat locked Read TLPs as UR for EP; Supported for RC  - 1: Treat locked Read TLPs as Supported for EP; UR for RC [19]: CX_FLT_MASK_CFG_TYPE1_RE_AS_UR  - 0: Treat CFG type1 TLPs as UR for EP; Supported for RC  - 1: Treat CFG type1 TLPs as Supported for EP; UR for RC  - When CX_SRIOV_ENABLE is set then this bit is set to allow the filter to process Type 1 Config requests if the EP consumes more than one bus number. [18]: CX_FLT_MASK_UR_OUTSIDE_BAR  - 0: Treat out-of-bar TLPs as UR  - 1: Do not treat out-of-bar TLPs as UR [17]: CX_FLT_MASK_UR_POIS  - 0: Treat poisoned request TLPs as UR  - 1: Do not treat poisoned request TLPs as UR  - The native core always passes poisoned completions to your application except when you are using the DMA read channel. [16]: CX_FLT_MASK_UR_FUNC_MISMATCH  - 0: Treat Function MisMatched TLPs as UR  - 1: Do not treat Function MisMatched TLPs as UR Note: This register field is sticky.
3623     #define PCIEIP_REG_SYMBOL_TIMER_FILTER_1_OFF_MASK_RADM_1_SHIFT                                   16
3624 #define PCIEIP_REG_FILTER_MASK_2_OFF                                                                 0x000720UL //Access:RW   DataWidth:0x20  Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details, see the "Receive Filtering" section. In each case, '0' applies the associated filtering rule and '1' masks the associated filtering rule.  Chips: K2
3625 #define PCIEIP_REG_PL_DEBUG0_OFF                                                                     0x000728UL //Access:R    DataWidth:0x20  Debug Register 0  Chips: K2
3626 #define PCIEIP_REG_PL_DEBUG1_OFF                                                                     0x00072cUL //Access:R    DataWidth:0x20  Debug Register 1  Chips: K2
3627 #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF                                                         0x000730UL //Access:R    DataWidth:0x20  Transmit Posted FC Credit Status  Chips: K2
3628     #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT                                 (0xfff<<0) // Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
3629     #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_DATA_FC_CREDIT_SHIFT                           0
3630     #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT                               (0xff<<12) // Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_ph_cdts, xtlh_xadm_pd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
3631     #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_TX_P_HEADER_FC_CREDIT_SHIFT                         12
3632     #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20                                            (0xfff<<20) // Reserved for future use.
3633     #define PCIEIP_REG_TX_P_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT                                      20
3634 #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF                                                        0x000734UL //Access:R    DataWidth:0x20  Transmit Non-Posted FC Credit Status  Chips: K2
3635     #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT                               (0xfff<<0) // Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
3636     #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_DATA_FC_CREDIT_SHIFT                         0
3637     #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT                             (0xff<<12) // Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_nph_cdts, xtlh_xadm_npd_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
3638     #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_TX_NP_HEADER_FC_CREDIT_SHIFT                       12
3639     #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20                                           (0xfff<<20) // Reserved for future use.
3640     #define PCIEIP_REG_TX_NP_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT                                     20
3641 #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF                                                       0x000738UL //Access:R    DataWidth:0x20  Transmit Completion FC Credit Status  Chips: K2
3642     #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT                             (0xfff<<0) // Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
3643     #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_DATA_FC_CREDIT_SHIFT                       0
3644     #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT                           (0xff<<12) // Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link, updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data [12'b0, xtlh_xadm_cplh_cdts, xtlh_xadm_cpld_cdts]; When the number of advertised completion credits (both header and data) are infinite, then the default would be [12'b0, 8'hFF, 12'hFFF].
3645     #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_TX_CPL_HEADER_FC_CREDIT_SHIFT                     12
3646     #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20                                          (0xfff<<20) // Reserved for future use.
3647     #define PCIEIP_REG_TX_CPL_FC_CREDIT_STATUS_OFF_RSVDP_20_SHIFT                                    20
3648 #define PCIEIP_REG_QUEUE_STATUS_OFF                                                                  0x00073cUL //Access:RW   DataWidth:0x20  Queue Status  Chips: K2
3649     #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN                                  (0x1<<0) // Received TLP FC Credits Not Returned. Indicates that the core has sent a TLP but has not yet received an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the link.
3650     #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_TLP_FC_CREDIT_NON_RETURN_SHIFT                            0
3651     #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE                                           (0x1<<1) // Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer.
3652     #define PCIEIP_REG_QUEUE_STATUS_OFF_TX_RETRY_BUFFER_NE_SHIFT                                     1
3653     #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY                                           (0x1<<2) // Received Queue Not Empty. Indicates there is data in one or more of the receive buffers.
3654     #define PCIEIP_REG_QUEUE_STATUS_OFF_RX_QUEUE_NON_EMPTY_SHIFT                                     2
3655     #define PCIEIP_REG_QUEUE_STATUS_OFF_RSVDP_3                                                      (0x1fff<<3) // Reserved for future use.
3656     #define PCIEIP_REG_QUEUE_STATUS_OFF_RSVDP_3_SHIFT                                                3
3657     #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL                                       (0x1fff<<16) // FC Latency Timer Override Value. When you set the "FC Latency Timer Override Enable" in this register, the value in this field will override the FC latency timer value that the core calculates according to the PCIe specification. For more details, see "Flow Control".  Note: This register field is sticky.
3658     #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_SHIFT                                 16
3659     #define PCIEIP_REG_QUEUE_STATUS_OFF_RSVDP_29                                                     (0x3<<29) // Reserved for future use.
3660     #define PCIEIP_REG_QUEUE_STATUS_OFF_RSVDP_29_SHIFT                                               29
3661     #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN                                    (0x1<<31) // FC Latency Timer Override Enable. When this bit is set, the value from the "FC Latency Timer Override Value" field in this register will override the FC latency timer value that the core calculates according to the PCIe specification.  Note: This register field is sticky.
3662     #define PCIEIP_REG_QUEUE_STATUS_OFF_TIMER_MOD_FLOW_CONTROL_EN_SHIFT                              31
3663 #define PCIEIP_REG_VC_TX_ARBI_1_OFF                                                                  0x000740UL //Access:R    DataWidth:0x20  VC Transmit Arbitration Register 1  Chips: K2
3664     #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0                                              (0xff<<0) // WRR Weight for VC0.  Note: The access attributes of this field are as follows:  - Dbi: R
3665     #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_0_SHIFT                                        0
3666     #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1                                              (0xff<<8) // WRR Weight for VC1.  Note: The access attributes of this field are as follows:  - Dbi: R
3667     #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_1_SHIFT                                        8
3668     #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2                                              (0xff<<16) // WRR Weight for VC2.  Note: The access attributes of this field are as follows:  - Dbi: R
3669     #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_2_SHIFT                                        16
3670     #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3                                              (0xff<<24) // WRR Weight for VC3.  Note: The access attributes of this field are as follows:  - Dbi: R
3671     #define PCIEIP_REG_VC_TX_ARBI_1_OFF_WRR_WEIGHT_VC_3_SHIFT                                        24
3672 #define PCIEIP_REG_VC_TX_ARBI_2_OFF                                                                  0x000744UL //Access:R    DataWidth:0x20  VC Transmit Arbitration Register 2  Chips: K2
3673     #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4                                              (0xff<<0) // WRR Weight for VC4.  Note: The access attributes of this field are as follows:  - Dbi: R
3674     #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_4_SHIFT                                        0
3675     #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5                                              (0xff<<8) // WRR Weight for VC5.  Note: The access attributes of this field are as follows:  - Dbi: R
3676     #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_5_SHIFT                                        8
3677     #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6                                              (0xff<<16) // WRR Weight for VC6.  Note: The access attributes of this field are as follows:  - Dbi: R
3678     #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_6_SHIFT                                        16
3679     #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7                                              (0xff<<24) // WRR Weight for VC7.  Note: The access attributes of this field are as follows:  - Dbi: R
3680     #define PCIEIP_REG_VC_TX_ARBI_2_OFF_WRR_WEIGHT_VC_7_SHIFT                                        24
3681 #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF                                                               0x000748UL //Access:RW   DataWidth:0x20  Segmented-Buffer VC0 Posted Receive Queue Control.  Chips: K2
3682     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT                                         (0xfff<<0) // VC0 Posted Data Credits. The number of initial posted data credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
3683     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_DATA_CREDIT_SHIFT                                   0
3684     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT                                       (0xff<<12) // VC0 Posted Header Credits. The number of initial posted header credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
3685     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_HEADER_CREDIT_SHIFT                                 12
3686     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4                                                 (0x1<<20) // Reserved.  Note: This register field is sticky.
3687     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED4_SHIFT                                           20
3688     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE                                          (0x7<<21) // Reserved.  Note: This register field is sticky.
3689     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC0_P_TLP_Q_MODE_SHIFT                                    21
3690     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED5                                                 (0x3f<<24) // Reserved.  Note: This register field is sticky.
3691     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_RESERVED5_SHIFT                                           24
3692     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0                                     (0x1<<30) // TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues, used only in the segmented-buffer configuration:  - 1: PCIe ordering rules (recommended)  - 0: Strict ordering: posted, completion, then non-posted Note: This register field is sticky.
3693     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_TLP_TYPE_ORDERING_VC0_SHIFT                               30
3694     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q                                          (0x1<<31) // VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues, used only in the segmented-buffer configuration:  - 1: Strict ordering, higher numbered VCs have higher priority  - 0: Round robin Note: This register field is sticky.
3695     #define PCIEIP_REG_VC0_P_RX_Q_CTRL_OFF_VC_ORDERING_RX_Q_SHIFT                                    31
3696 #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF                                                              0x00074cUL //Access:RW   DataWidth:0x20  Segmented-Buffer VC0 Non-Posted Receive Queue Control.  Chips: K2
3697     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT                                       (0xfff<<0) // VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
3698     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_DATA_CREDIT_SHIFT                                 0
3699     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT                                     (0xff<<12) // VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
3700     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_HEADER_CREDIT_SHIFT                               12
3701     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6                                                (0x1<<20) // Reserved.  Note: This register field is sticky.
3702     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED6_SHIFT                                          20
3703     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE                                        (0x7<<21) // Reserved.  Note: This register field is sticky.
3704     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_VC0_NP_TLP_Q_MODE_SHIFT                                  21
3705     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED7                                                (0xff<<24) // Reserved.  Note: This register field is sticky.
3706     #define PCIEIP_REG_VC0_NP_RX_Q_CTRL_OFF_RESERVED7_SHIFT                                          24
3707 #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF                                                             0x000750UL //Access:RW   DataWidth:0x20  Segmented-Buffer VC0 Completion Receive Queue Control.  Chips: K2
3708     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT                                     (0xfff<<0) // VC0 Completion Data Credits. The number of initial Completion data credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
3709     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_DATA_CREDIT_SHIFT                               0
3710     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT                                   (0xff<<12) // VC0 Completion Header Credits. The number of initial Completion header credits for VC0, used only in the segmented-buffer configuration.  Note: The access attributes of this field are as follows:  - Dbi: R (sticky)  Note: This register field is sticky.
3711     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_HEADER_CREDIT_SHIFT                             12
3712     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8                                               (0x1<<20) // Reserved.  Note: This register field is sticky.
3713     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED8_SHIFT                                         20
3714     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE                                      (0x7<<21) // Reserved.  Note: This register field is sticky.
3715     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_VC0_CPL_TLP_Q_MODE_SHIFT                                21
3716     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9                                               (0xff<<24) // Reserved.  Note: This register field is sticky.
3717     #define PCIEIP_REG_VC0_CPL_RX_Q_CTRL_OFF_RESERVED9_SHIFT                                         24
3718 #define PCIEIP_REG_TL_CONTROL_0                                                                      0x000800UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3719     #define PCIEIP_REG_TL_CONTROL_0_PM_TL_IGNORE_REQS                                                (0x1<<0) // When set the TL TX does not send out pending requests if PM requests to block TLPS. By default TL will send all pending dma requests and completions when PM requests it to prepare for leaving L0 before asserting tlp blocked. When this bit is set , if min credits are available, TL indicates to PM that TLP is blocked and does not send out any pending dma requests or completions.
3720     #define PCIEIP_REG_TL_CONTROL_0_PM_TL_IGNORE_REQS_SHIFT                                          0
3721     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_1DW_CHK                                                    (0x1<<1) // Target mem Rd should not be greater than 1 DW if set.
3722     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_1DW_CHK_SHIFT                                              1
3723     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_3DW_CHK                                                    (0x1<<2) // Target mem Rd should not be greater than 3 DW if set.
3724     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_3DW_CHK_SHIFT                                              2
3725     #define PCIEIP_REG_TL_CONTROL_0_MEMWR_1DW_CHK                                                    (0x1<<3) // Target mem Wr should not be greater than 1 DW if set.
3726     #define PCIEIP_REG_TL_CONTROL_0_MEMWR_1DW_CHK_SHIFT                                              3
3727     #define PCIEIP_REG_TL_CONTROL_0_EXPROM_3DW_CHK                                                   (0x1<<4) // Target Expansion ROM should not be greater than 3 DW if set.
3728     #define PCIEIP_REG_TL_CONTROL_0_EXPROM_3DW_CHK_SHIFT                                             4
3729     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_16DW_CHK                                                   (0x1<<5) // Target mem Rd should not be greater than 16 DW if set .
3730     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_16DW_CHK_SHIFT                                             5
3731     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_4DW_CHK                                                    (0x1<<6) // Target mem Rd should not be greater than 4 DW if set .
3732     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_4DW_CHK_SHIFT                                              6
3733     #define PCIEIP_REG_TL_CONTROL_0_MEMWR_4DW_CHK                                                    (0x1<<7) // Target mem Wr should not be greater than 4 DW if set .
3734     #define PCIEIP_REG_TL_CONTROL_0_MEMWR_4DW_CHK_SHIFT                                              7
3735     #define PCIEIP_REG_TL_CONTROL_0_MEMWR_32DW_CHK                                                   (0x1<<8) // Target mem Wr should not be greater than 32 DW if set .
3736     #define PCIEIP_REG_TL_CONTROL_0_MEMWR_32DW_CHK_SHIFT                                             8
3737     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_32DW_CHK                                                   (0x1<<9) // Target mem Rd should not be greater than 32 DW if set .
3738     #define PCIEIP_REG_TL_CONTROL_0_MEMRD_32DW_CHK_SHIFT                                             9
3739     #define PCIEIP_REG_TL_CONTROL_0_UNUSED_3                                                         (0x3<<10) //
3740     #define PCIEIP_REG_TL_CONTROL_0_UNUSED_3_SHIFT                                                   10
3741     #define PCIEIP_REG_TL_CONTROL_0_RETAIN_RID                                                       (0x1<<12) // This bit if set will force DUT to not reset its RID after an FLR.
3742     #define PCIEIP_REG_TL_CONTROL_0_RETAIN_RID_SHIFT                                                 12
3743     #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_FLR_AFTER_55MS                                          (0x1<<13) // If set, DUT will automatically exit FLR state after a 55ms timer expires.
3744     #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_FLR_AFTER_55MS_SHIFT                                    13
3745     #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_CRS_POST_FLR                                            (0x1<<14) // If set, DUT will automatically return Successful completion when it has completed FLR.
3746     #define PCIEIP_REG_TL_CONTROL_0_AUTO_CLR_CRS_POST_FLR_SHIFT                                      14
3747     #define PCIEIP_REG_TL_CONTROL_0_NO_CMPL_IN_FLR                                                   (0x1<<15) // If set, completions received for a function which is in FLR will not be directed to user.
3748     #define PCIEIP_REG_TL_CONTROL_0_NO_CMPL_IN_FLR_SHIFT                                             15
3749     #define PCIEIP_REG_TL_CONTROL_0_CFG_FUNC_EN0                                                     (0x1<<16) // If set, this causes func0 to be hidden
3750     #define PCIEIP_REG_TL_CONTROL_0_CFG_FUNC_EN0_SHIFT                                               16
3751     #define PCIEIP_REG_TL_CONTROL_0_UNUSED_2                                                         (0x1<<17) //
3752     #define PCIEIP_REG_TL_CONTROL_0_UNUSED_2_SHIFT                                                   17
3753     #define PCIEIP_REG_TL_CONTROL_0_CFG_MSI_LOW_MODE                                                 (0x1<<18) // when set, forces MSI_En to low.
3754     #define PCIEIP_REG_TL_CONTROL_0_CFG_MSI_LOW_MODE_SHIFT                                           18
3755     #define PCIEIP_REG_TL_CONTROL_0_BEACON_MULTI_EN                                                  (0x1<<19) // When set Beacon is enabled for all lanes
3756     #define PCIEIP_REG_TL_CONTROL_0_BEACON_MULTI_EN_SHIFT                                            19
3757     #define PCIEIP_REG_TL_CONTROL_0_BEACON_DIS                                                       (0x1<<20) // When set, Beacon generation is disabled
3758     #define PCIEIP_REG_TL_CONTROL_0_BEACON_DIS_SHIFT                                                 20
3759     #define PCIEIP_REG_TL_CONTROL_0_WAKE_L0_L1_EN                                                    (0x1<<21) // When set, it enables WAKE generation in any L-state, when PME_EN bit is set and corresponding status is enabled
3760     #define PCIEIP_REG_TL_CONTROL_0_WAKE_L0_L1_EN_SHIFT                                              21
3761     #define PCIEIP_REG_TL_CONTROL_0_UNUSED_4                                                         (0x1<<22) //
3762     #define PCIEIP_REG_TL_CONTROL_0_UNUSED_4_SHIFT                                                   22
3763     #define PCIEIP_REG_TL_CONTROL_0_RST_IGNORE_DLPDOWN                                               (0x1<<23) // When set, TL does not get reset on DLPDOWN and Pcie_rst_b does not get asserted on DLPDOWN
3764     #define PCIEIP_REG_TL_CONTROL_0_RST_IGNORE_DLPDOWN_SHIFT                                         23
3765     #define PCIEIP_REG_TL_CONTROL_0_PM_DIS_L1_REENTRY                                                (0x1<<24) // When set, it prevents PM from re-entering L1 when programmed to non-D0 power state
3766     #define PCIEIP_REG_TL_CONTROL_0_PM_DIS_L1_REENTRY_SHIFT                                          24
3767     #define PCIEIP_REG_TL_CONTROL_0_PCIE_PHY_TX_SWING                                                (0x1<<25) // This bit is used by PCIE SERDES to determine source of tx margin signals
3768     #define PCIEIP_REG_TL_CONTROL_0_PCIE_PHY_TX_SWING_SHIFT                                          25
3769     #define PCIEIP_REG_TL_CONTROL_0_PERST_B_80USSEL                                                  (0x1<<26) // Select the 150us delayed perst_b instead of the raw perst_b
3770     #define PCIEIP_REG_TL_CONTROL_0_PERST_B_80USSEL_SHIFT                                            26
3771     #define PCIEIP_REG_TL_CONTROL_0_REG_PERST_B_10MSSEL                                              (0x1<<27) // Select the 10ms delayed perst_b instead of the raw perst_b
3772     #define PCIEIP_REG_TL_CONTROL_0_REG_PERST_B_10MSSEL_SHIFT                                        27
3773     #define PCIEIP_REG_TL_CONTROL_0_REG_SCND_RST_ON_HOT                                              (0x1<<28) // In RC mode, when set, it enables pcie_scnd_rst_b to be asserted when Secondary reset bit in BridgeControl register is set.
3774     #define PCIEIP_REG_TL_CONTROL_0_REG_SCND_RST_ON_HOT_SHIFT                                        28
3775     #define PCIEIP_REG_TL_CONTROL_0_REG_FORCE_SCND_RST                                               (0x1<<29) // In RC mode, when set, it forces pcie_scnd_rst_b to be asserted
3776     #define PCIEIP_REG_TL_CONTROL_0_REG_FORCE_SCND_RST_SHIFT                                         29
3777     #define PCIEIP_REG_TL_CONTROL_0_UNUSED_1                                                         (0x3<<30) //
3778     #define PCIEIP_REG_TL_CONTROL_0_UNUSED_1_SHIFT                                                   30
3779 #define PCIEIP_REG_TL_CONTROL_1                                                                      0x000804UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
3780     #define PCIEIP_REG_TL_CONTROL_1_EN_4G_CHK                                                        (0x1<<0) // Enable check to determine if mem requests do not have upper 32 bits of address to be all 0
3781     #define PCIEIP_REG_TL_CONTROL_1_EN_4G_CHK_SHIFT                                                  0
3782     #define PCIEIP_REG_TL_CONTROL_1_EN_4K_CHK                                                        (0x1<<1) // Enable checks to determine TLP doesn not cross 4k boundary
3783     #define PCIEIP_REG_TL_CONTROL_1_EN_4K_CHK_SHIFT                                                  1
3784     #define PCIEIP_REG_TL_CONTROL_1_EN_BC_CHK                                                        (0x1<<2) // Enable check to determine if the length field and bytecount field are in sync
3785     #define PCIEIP_REG_TL_CONTROL_1_EN_BC_CHK_SHIFT                                                  2
3786     #define PCIEIP_REG_TL_CONTROL_1_EN_BE_CHK                                                        (0x1<<3) // Enable check to determine if received TLP follows all the Byte enable rules
3787     #define PCIEIP_REG_TL_CONTROL_1_EN_BE_CHK_SHIFT                                                  3
3788     #define PCIEIP_REG_TL_CONTROL_1_EN_EP_CHK                                                        (0x1<<4) // Enable check for Poisoned TLP
3789     #define PCIEIP_REG_TL_CONTROL_1_EN_EP_CHK_SHIFT                                                  4
3790     #define PCIEIP_REG_TL_CONTROL_1_EN_MPS_CHECK                                                     (0x1<<5) // Enable Check for max payload size Violation
3791     #define PCIEIP_REG_TL_CONTROL_1_EN_MPS_CHECK_SHIFT                                               5
3792     #define PCIEIP_REG_TL_CONTROL_1_EN_RCB_CHK                                                       (0x1<<6) // Enable checks to determine completion TLPs do not violate RCB
3793     #define PCIEIP_REG_TL_CONTROL_1_EN_RCB_CHK_SHIFT                                                 6
3794     #define PCIEIP_REG_TL_CONTROL_1_EN_RTE_CHK                                                       (0x1<<7) // Enable Check to determine if the routing type is correct when receiving message TLP
3795     #define PCIEIP_REG_TL_CONTROL_1_EN_RTE_CHK_SHIFT                                                 7
3796     #define PCIEIP_REG_TL_CONTROL_1_EN_TAC_CHK                                                       (0x1<<8) // Enable Configuration attribute and class check
3797     #define PCIEIP_REG_TL_CONTROL_1_EN_TAC_CHK_SHIFT                                                 8
3798     #define PCIEIP_REG_TL_CONTROL_1_EN_FC_CHK                                                        (0x1<<9) // Enable Flow Control Check
3799     #define PCIEIP_REG_TL_CONTROL_1_EN_FC_CHK_SHIFT                                                  9
3800     #define PCIEIP_REG_TL_CONTROL_1_EN_TO_CHK                                                        (0x1<<10) // Enable Completion Timeout Check( This bit is no longer used, instead bit defined by ECN 1.1 is used)
3801     #define PCIEIP_REG_TL_CONTROL_1_EN_TO_CHK_SHIFT                                                  10
3802     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_1                                                      (0x1<<11) // This bit is used to disable function 1. Bit 17 of 800 can also be used. That bit is retained for software compatibility purpose.
3803     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_1_SHIFT                                                11
3804     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_2                                                      (0x1<<12) // This bit is used to disable function 2.
3805     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_2_SHIFT                                                12
3806     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_3                                                      (0x1<<13) // This bit is used to disable function 3.
3807     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_3_SHIFT                                                13
3808     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_4                                                      (0x1<<14) // This bit is used to disable function 4.
3809     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_4_SHIFT                                                14
3810     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_5                                                      (0x1<<15) // This bit is used to disable function 5.
3811     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_5_SHIFT                                                15
3812     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_6                                                      (0x1<<16) // This bit is used to disable function 6.
3813     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_6_SHIFT                                                16
3814     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_7                                                      (0x1<<17) // This bit is used to disable function 7.
3815     #define PCIEIP_REG_TL_CONTROL_1_HIDE_FUNC_7_SHIFT                                                17
3816     #define PCIEIP_REG_TL_CONTROL_1_RESERVED                                                         (0x1<<18) //
3817     #define PCIEIP_REG_TL_CONTROL_1_RESERVED_SHIFT                                                   18
3818     #define PCIEIP_REG_TL_CONTROL_1_REG_IGNORE_LTRWT_REQMT                                           (0x1<<19) // When set, hardware will return completions and not wait for LTR message to be sent first even though device state may have changed to non-D0.
3819     #define PCIEIP_REG_TL_CONTROL_1_REG_IGNORE_LTRWT_REQMT_SHIFT                                     19
3820     #define PCIEIP_REG_TL_CONTROL_1_REG_REL_NPHCRDT_ECRCERR                                          (0x1<<20) // Release NPH credit even if ECRC error is detected on NPH TLP.
3821     #define PCIEIP_REG_TL_CONTROL_1_REG_REL_NPHCRDT_ECRCERR_SHIFT                                    20
3822     #define PCIEIP_REG_TL_CONTROL_1_REG_UCOR_INT_ERR_EN                                              (0x1<<21) // Enables uncorrectable Internal Error Reporting if feature is implemented in h/w
3823     #define PCIEIP_REG_TL_CONTROL_1_REG_UCOR_INT_ERR_EN_SHIFT                                        21
3824     #define PCIEIP_REG_TL_CONTROL_1_REG_EN_BYTCNT_CHK                                                (0x1<<22) // When enabled, hardware checks the bytecount field in completion headers.
3825     #define PCIEIP_REG_TL_CONTROL_1_REG_EN_BYTCNT_CHK_SHIFT                                          22
3826     #define PCIEIP_REG_TL_CONTROL_1_REG_EN_LTR1                                                      (0x1<<23) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h848 whenever the h/w asserts the user_send_ltr1 port. This bit is used only if LTR_ENABLED is defined in version.v and if h/w supports 3 LTR states.
3827     #define PCIEIP_REG_TL_CONTROL_1_REG_EN_LTR1_SHIFT                                                23
3828     #define PCIEIP_REG_TL_CONTROL_1_EN_AUTOCRSCLR                                                    (0x1<<24) // This bit enables CRS status to be automatically cleared when internal timer is equal to either 1 second or a programmable value(which ever is smaller). This bit is used only if AutoCRSClrOn is defined in version.v
3829     #define PCIEIP_REG_TL_CONTROL_1_EN_AUTOCRSCLR_SHIFT                                              24
3830     #define PCIEIP_REG_TL_CONTROL_1_EN_LTR2                                                          (0x1<<25) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h84c whenever the h/w asserts the user_send_ltr2 port. This bit is used only if LTR_ENABLED is defined in version.v
3831     #define PCIEIP_REG_TL_CONTROL_1_EN_LTR2_SHIFT                                                    25
3832     #define PCIEIP_REG_TL_CONTROL_1_WT_LTR_ASPM_VAL                                                  (0xf<<26) // This programs a timer which indicates the amount of time DUT will wait before requesting entry to ASPM L1 when ASPM LTR is enabled. The unit of this timer is us. This time is in addition to the time that DL waits for bus to be idle. This timer is required to allow DUT to send ASPM LTR message and wait for FC to be returned before entering L1. This bit is used only if LTR_ENABLED is defined in version.v
3833     #define PCIEIP_REG_TL_CONTROL_1_WT_LTR_ASPM_VAL_SHIFT                                            26
3834     #define PCIEIP_REG_TL_CONTROL_1_EN_ASPM_LTR                                                      (0x1<<30) // This bit instructs h/w to send an LTR message with LTR values programmed in 'h844 and 'h848 whenever the DUT enters or leaves ASPM L1. This bit is used only if LTR_ENABLED is defined in version.v
3835     #define PCIEIP_REG_TL_CONTROL_1_EN_ASPM_LTR_SHIFT                                                30
3836     #define PCIEIP_REG_TL_CONTROL_1_SEND_IMMED_LTR                                                   (0x1<<31) // This bit instructs h/w to immediately send an LTR message with LTR values programmed in 'h840. This state has highest priority and when this bit is set, no other LTR message (other than those required by PCIE spec) will be sent. This bit is used only if LTR_ENABLED is defined in version.v
3837     #define PCIEIP_REG_TL_CONTROL_1_SEND_IMMED_LTR_SHIFT                                             31
3838 #define PCIEIP_REG_TL_CONTROL_2                                                                      0x000808UL //Access:RW   DataWidth:0x20  This register masks the generation of pcie_err_attn signal when errors are detected by hardware.  Chips: BB_A0 BB_B0
3839     #define PCIEIP_REG_TL_CONTROL_2_PES0_MASK                                                        (0x1<<0) // Poisoned Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3840     #define PCIEIP_REG_TL_CONTROL_2_PES0_MASK_SHIFT                                                  0
3841     #define PCIEIP_REG_TL_CONTROL_2_FCPES0_MASK                                                      (0x1<<1) // Flow Control Protocol Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3842     #define PCIEIP_REG_TL_CONTROL_2_FCPES0_MASK_SHIFT                                                1
3843     #define PCIEIP_REG_TL_CONTROL_2_CTS0_MASK                                                        (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3844     #define PCIEIP_REG_TL_CONTROL_2_CTS0_MASK_SHIFT                                                  2
3845     #define PCIEIP_REG_TL_CONTROL_2_RX_UR0_MASK                                                      (0x1<<3) // Received UR Status, Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3846     #define PCIEIP_REG_TL_CONTROL_2_RX_UR0_MASK_SHIFT                                                3
3847     #define PCIEIP_REG_TL_CONTROL_2_UCS0_MASK                                                        (0x1<<4) // Unexpected Completion Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3848     #define PCIEIP_REG_TL_CONTROL_2_UCS0_MASK_SHIFT                                                  4
3849     #define PCIEIP_REG_TL_CONTROL_2_ROS0_MASK                                                        (0x1<<5) // Receiver Overflow Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3850     #define PCIEIP_REG_TL_CONTROL_2_ROS0_MASK_SHIFT                                                  5
3851     #define PCIEIP_REG_TL_CONTROL_2_MTLPS0_MASK                                                      (0x1<<6) // Malformed TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3852     #define PCIEIP_REG_TL_CONTROL_2_MTLPS0_MASK_SHIFT                                                6
3853     #define PCIEIP_REG_TL_CONTROL_2_ECRCS0_MASK                                                      (0x1<<7) // ECRC Error TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
3854     #define PCIEIP_REG_TL_CONTROL_2_ECRCS0_MASK_SHIFT                                                7
3855     #define PCIEIP_REG_TL_CONTROL_2_URES0_MASK                                                       (0x1<<8) // Unsupported Request Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3856     #define PCIEIP_REG_TL_CONTROL_2_URES0_MASK_SHIFT                                                 8
3857     #define PCIEIP_REG_TL_CONTROL_2_RXTABRT0_MASK                                                    (0x1<<9) // Received target Abort Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
3858     #define PCIEIP_REG_TL_CONTROL_2_RXTABRT0_MASK_SHIFT                                              9
3859     #define PCIEIP_REG_TL_CONTROL_2_PES1_MASK                                                        (0x1<<10) // Poisoned Error Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
3860     #define PCIEIP_REG_TL_CONTROL_2_PES1_MASK_SHIFT                                                  10
3861     #define PCIEIP_REG_TL_CONTROL_2_FCPES1_MASK                                                      (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3862     #define PCIEIP_REG_TL_CONTROL_2_FCPES1_MASK_SHIFT                                                11
3863     #define PCIEIP_REG_TL_CONTROL_2_CTS1_MASK                                                        (0x1<<12) // Completer Timeout Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3864     #define PCIEIP_REG_TL_CONTROL_2_CTS1_MASK_SHIFT                                                  12
3865     #define PCIEIP_REG_TL_CONTROL_2_RX_UR1_MASK                                                      (0x1<<13) // Received UR Status, Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3866     #define PCIEIP_REG_TL_CONTROL_2_RX_UR1_MASK_SHIFT                                                13
3867     #define PCIEIP_REG_TL_CONTROL_2_UCS1_MASK                                                        (0x1<<14) // Unexpected Completion Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3868     #define PCIEIP_REG_TL_CONTROL_2_UCS1_MASK_SHIFT                                                  14
3869     #define PCIEIP_REG_TL_CONTROL_2_ROS1_MASK                                                        (0x1<<15) // Receiver Overflow Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
3870     #define PCIEIP_REG_TL_CONTROL_2_ROS1_MASK_SHIFT                                                  15
3871     #define PCIEIP_REG_TL_CONTROL_2_MTLPS1_MASK                                                      (0x1<<16) // Malformed TLP Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
3872     #define PCIEIP_REG_TL_CONTROL_2_MTLPS1_MASK_SHIFT                                                16
3873     #define PCIEIP_REG_TL_CONTROL_2_ECRCS1_MASK                                                      (0x1<<17) // ECRC Error TLP Status Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen..
3874     #define PCIEIP_REG_TL_CONTROL_2_ECRCS1_MASK_SHIFT                                                17
3875     #define PCIEIP_REG_TL_CONTROL_2_URES1_MASK                                                       (0x1<<18) // Unsupported Request Error Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3876     #define PCIEIP_REG_TL_CONTROL_2_URES1_MASK_SHIFT                                                 18
3877     #define PCIEIP_REG_TL_CONTROL_2_RXTABRT1_MASK                                                    (0x1<<19) // Received target Abort Error Status Mask for Function1, if set, does not generate pcie_err_attn output when this error is seen.
3878     #define PCIEIP_REG_TL_CONTROL_2_RXTABRT1_MASK_SHIFT                                              19
3879     #define PCIEIP_REG_TL_CONTROL_2_RTAG_VAL_UNEXP_ATTN_MASK                                         (0x1<<20) // rtag_val_unexp_attn Mask. If set, does not generate pcie_err_attn output when this error is seen.
3880     #define PCIEIP_REG_TL_CONTROL_2_RTAG_VAL_UNEXP_ATTN_MASK_SHIFT                                   20
3881     #define PCIEIP_REG_TL_CONTROL_2_TX_TAG_IN_USE_ATTN_MASK                                          (0x1<<21) // tx_tag_in_use_attn Mask. If set, does not generate pcie_err_attn output when this error is seen.
3882     #define PCIEIP_REG_TL_CONTROL_2_TX_TAG_IN_USE_ATTN_MASK_SHIFT                                    21
3883     #define PCIEIP_REG_TL_CONTROL_2_DL_ERR_ATTN_MASK                                                 (0x1<<22) // DL Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
3884     #define PCIEIP_REG_TL_CONTROL_2_DL_ERR_ATTN_MASK_SHIFT                                           22
3885     #define PCIEIP_REG_TL_CONTROL_2_PHY_ERR_ATTN_MASK                                                (0x1<<23) // PHY Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
3886     #define PCIEIP_REG_TL_CONTROL_2_PHY_ERR_ATTN_MASK_SHIFT                                          23
3887     #define PCIEIP_REG_TL_CONTROL_2_TXINTF_OVERFLOW_ATTN_MASK                                        (0x1<<24) //
3888     #define PCIEIP_REG_TL_CONTROL_2_TXINTF_OVERFLOW_ATTN_MASK_SHIFT                                  24
3889     #define PCIEIP_REG_TL_CONTROL_2_BRIDGE_FORWARD_ERR_ATTN_MASK                                     (0x1<<25) // If set, TX reports user interface violation
3890     #define PCIEIP_REG_TL_CONTROL_2_BRIDGE_FORWARD_ERR_ATTN_MASK_SHIFT                               25
3891     #define PCIEIP_REG_TL_CONTROL_2_TTX_MPS_ERR_MASK                                                 (0x1<<26) //
3892     #define PCIEIP_REG_TL_CONTROL_2_TTX_MPS_ERR_MASK_SHIFT                                           26
3893     #define PCIEIP_REG_TL_CONTROL_2_TTX_MRRS_ERR_MASK                                                (0x1<<27) //
3894     #define PCIEIP_REG_TL_CONTROL_2_TTX_MRRS_ERR_MASK_SHIFT                                          27
3895     #define PCIEIP_REG_TL_CONTROL_2_TTX_4KBOUND_ERR_MASK                                             (0x1<<28) //
3896     #define PCIEIP_REG_TL_CONTROL_2_TTX_4KBOUND_ERR_MASK_SHIFT                                       28
3897     #define PCIEIP_REG_TL_CONTROL_2_TTX_UNKNOWNTYPE_ERR_MASK                                         (0x1<<29) //
3898     #define PCIEIP_REG_TL_CONTROL_2_TTX_UNKNOWNTYPE_ERR_MASK_SHIFT                                   29
3899     #define PCIEIP_REG_TL_CONTROL_2_UNUSED_1                                                         (0x3<<30) //
3900     #define PCIEIP_REG_TL_CONTROL_2_UNUSED_1_SHIFT                                                   30
3901 #define PCIEIP_REG_GEN2_CTRL_OFF_K2                                                                  0x00080cUL //Access:RW   DataWidth:0x20  Link Width and Speed Change Control Register.  Chips: K2
3902     #define PCIEIP_REG_GEN2_CTRL_OFF_UNUSED_0                                                        (0xff<<0) // reserved
3903     #define PCIEIP_REG_GEN2_CTRL_OFF_UNUSED_0_SHIFT                                                  0
3904     #define PCIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES                                                    (0x1f<<8) // Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken" or "unused" lanes that detect a receiver. Indicates the number of lanes to check for exit from Electrical Idle in Polling.Active and L2.Idle. It is possible that the LTSSM might detect a receiver on a bad or broken lane during the Detect Substate. However, it is also possible that such a lane might also fail to exit Electrical Idle and therefore prevent a valid link from being configured. This value is referred to as the "Predetermined Number of Lanes" in section 4.2.6.2.1 of the PCI Express Base 3.0 Specification, revision 1.0. Encoding is as follows:  - 0x01: 1 lane  - 0x02: 2 lanes  - 0x03: 3 lanes  - .. When you have unused lanes in your system, then you must change the value in this register to reflect the number of lanes. You must also change the value in the "Link Mode Enable" field of PORT_LINK_CTRL_OFF. The value in this register is normally the same as the encoded value in PORT_LINK_CTRL_OFF. If you find that one of your used lanes is bad then you must reduce the value in this register. For more information, see "How to Tie Off Unused Lanes." For information on upsizing and downsizing the link width, see "Link Establishment." This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
3905     #define PCIEIP_REG_GEN2_CTRL_OFF_NUM_OF_LANES_SHIFT                                              8
3906     #define PCIEIP_REG_GEN2_CTRL_OFF_PRE_DET_LANE                                                    (0x7<<13) // Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. Allowed values are:  - 3'b000: Connect logical Lane0 to physical lane 0 or CX_NL-1 or CX_NL/2-1 or CX_NL/4-1 or CX_NL/8-1, depending on which lane is detected  - 3'b001: Connect logical Lane0 to physical lane 1  - 3'b010: Connect logical Lane0 to physical lane 3  - 3'b011: Connect logical Lane0 to physical lane 7  - 3'b100: Connect logical Lane0 to physical lane 15 This field is used to restrict the receiver detect procedure to a particular lane when the default detect and polling procedure performed on all lanes cannot be successful. A notable example of when it is useful to program this field to a value different from the default, is when a lane is asymmetrically broken, that is, it is detected in Detect LTSSM state but it cannot exit Electrical Idle in Polling LTSSM state.  Note: This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
3907     #define PCIEIP_REG_GEN2_CTRL_OFF_PRE_DET_LANE_SHIFT                                              13
3908     #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN                                          (0x1<<16) // Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the core. For more details, see the 'Lane Reversal' appendix in the Databook. This field is reserved (fixed to '0') for M-PCIe.  Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
3909     #define PCIEIP_REG_GEN2_CTRL_OFF_AUTO_LANE_FLIP_CTRL_EN_SHIFT                                    16
3910     #define PCIEIP_REG_GEN2_CTRL_OFF_UNUSED_1                                                        (0xf<<17) // reserved
3911     #define PCIEIP_REG_GEN2_CTRL_OFF_UNUSED_1_SHIFT                                                  17
3912     #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE                                               (0x1<<21) // Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a "1" value on RxElecIdle instead of looking for a "0" on RxValid. If the PHY fails to deassert the RxValid signal in Recovery.Speed or Loopback.Active (because of corrupted EIOS for example), then EI cannot be inferred successfully in the core by just detecting the condition RxValid=0.  - 0: Use RxElecIdle signal to infer Electrical Idle  - 1: Use RxValid signal to infer Electrical Idle Note: This register field is sticky.
3913     #define PCIEIP_REG_GEN2_CTRL_OFF_GEN1_EI_INFERENCE_SHIFT                                         21
3914     #define PCIEIP_REG_GEN2_CTRL_OFF_UNUSED_2                                                        (0x3ff<<22) // reserved
3915     #define PCIEIP_REG_GEN2_CTRL_OFF_UNUSED_2_SHIFT                                                  22
3916 #define PCIEIP_REG_TL_CONTROL_3_BB_A0                                                                0x00080cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
3917 #define PCIEIP_REG_TL_CONTROL_3_BB_B0                                                                0x00080cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
3918     #define PCIEIP_REG_TL_CONTROL_3_EN_CMPL_RETRY                                                    (0x1<<0) // Enable Completion retry upon completion timeout. (feature is not supported, but bit is defined for posterity.)
3919     #define PCIEIP_REG_TL_CONTROL_3_EN_CMPL_RETRY_SHIFT                                              0
3920     #define PCIEIP_REG_TL_CONTROL_3_EN_PSND_RETRY                                                    (0x1<<1) // Enable Poisoned completions retry. (feature is not supported but bit is defined for posterity.)
3921     #define PCIEIP_REG_TL_CONTROL_3_EN_PSND_RETRY_SHIFT                                              1
3922     #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_PHCRDT                                                   (0x1<<2) // Hold releasing of Posted header credit. When this bit is set, PH credits are not released by IP if FIFO at the DL-TL boundary reaches a critical threshold. This feature allows the FIFO to unload without overflowing
3923     #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_PHCRDT_SHIFT                                             2
3924     #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_DMACRDT                                                  (0x1<<3) // Indicates no non-posted credit is available to user when bit is set. The credits to user are artificially reduced to 0, when FIFO at DL_TL boundary has reached a critical threshold and is in danger of overflowing. This feature allows the FIFO to unload without overflowing
3925     #define PCIEIP_REG_TL_CONTROL_3_EN_HOLD_DMACRDT_SHIFT                                            3
3926     #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ADVERR_RX_ERR                                             (0x1<<4) // Enable the reporting of receiver errors in the advanced error reporting structure.
3927     #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ADVERR_RX_ERR_SHIFT                                       4
3928     #define PCIEIP_REG_TL_CONTROL_3_REG_DIS_D0STATE_L1                                               (0x1<<5) // When set , disables entry into L1, due to function being in D0unint state. When set, it would require all enabled functions to be in D3hot to request L1 entry.
3929     #define PCIEIP_REG_TL_CONTROL_3_REG_DIS_D0STATE_L1_SHIFT                                         5
3930     #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ASPM_L0L1                                                 (0x3<<6) // When clear, field overrides the values in the ASPm Control field and disables it.
3931     #define PCIEIP_REG_TL_CONTROL_3_REG_EN_ASPM_L0L1_SHIFT                                           6
3932     #define PCIEIP_REG_TL_CONTROL_3_TL_REG_TXCTRL                                                    (0xff<<8) //
3933     #define PCIEIP_REG_TL_CONTROL_3_TL_REG_TXCTRL_SHIFT                                              8
3934     #define PCIEIP_REG_TL_CONTROL_3_OVERRIDE_L1_ENTRY                                                (0x1<<16) // This bit when set prevents DUT from entering L1 due to being in non-d0 state.
3935     #define PCIEIP_REG_TL_CONTROL_3_OVERRIDE_L1_ENTRY_SHIFT                                          16
3936     #define PCIEIP_REG_TL_CONTROL_3_MAX_INTER_L1_GAP                                                 (0x7fff<<17) // Programmable delay to prevent link from re-entering L1, when link comes out of L1 into L0 due to PM_PME. The default value corresponds to 8 us and uses pulse_1us signal to count this value
3937     #define PCIEIP_REG_TL_CONTROL_3_MAX_INTER_L1_GAP_SHIFT                                           17
3938 #define PCIEIP_REG_PHY_STATUS_OFF_K2                                                                 0x000810UL //Access:R    DataWidth:0x20  PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins.  Chips: K2
3939 #define PCIEIP_REG_TL_CONTROL_4_BB_A0                                                                0x000810UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0
3940 #define PCIEIP_REG_TL_CONTROL_4_BB_B0                                                                0x000810UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_B0
3941     #define PCIEIP_REG_TL_CONTROL_4_RESERVED2                                                        (0xffff<<0) // For ECO/CTRL bits are reset o hard_reset
3942     #define PCIEIP_REG_TL_CONTROL_4_RESERVED2_SHIFT                                                  0
3943     #define PCIEIP_REG_TL_CONTROL_4_RESERVED1                                                        (0xffff<<16) // For ECO/Control bits are reset on perst_b
3944     #define PCIEIP_REG_TL_CONTROL_4_RESERVED1_SHIFT                                                  16
3945 #define PCIEIP_REG_PHY_CONTROL_OFF_K2                                                                0x000814UL //Access:RW   DataWidth:0x20  PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins.  Chips: K2
3946 #define PCIEIP_REG_TL_CTRLSTAT_5_BB_A0                                                               0x000814UL //Access:RW   DataWidth:0x20  This register stores the status of errors to generate pcie_err_attn.  Chips: BB_A0
3947 #define PCIEIP_REG_TL_CTRLSTAT_5_BB_B0                                                               0x000814UL //Access:RW   DataWidth:0x20  This register stores the status of errors to generate pcie_err_attn.  Chips: BB_B0
3948     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP                                                    (0x1<<0) // This bit is set when h/w detects Poisoned Error Status . If set, h/w generates pcie_err_attn output .
3949     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP_SHIFT                                              0
3950     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL                                                     (0x1<<1) // This bit is set when h/w detects Flow Control Protocol Error Status . If set, h/w generates pcie_err_attn output .
3951     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL_SHIFT                                               1
3952     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT                                                 (0x1<<2) // This bit is set when h/w detects Completer Timeout Status . If set, h/w generates pcie_err_attn output .
3953     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT_SHIFT                                           2
3954     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT                                                 (0x1<<3) // This bit is set when h/w detects Receive UR Status. If set, h/w generates pcie_err_attn output .
3955     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT_SHIFT                                           3
3956     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL                                                   (0x1<<4) // This bit is set when h/w detects Unexpected Completion Status . If set, h/w generates pcie_err_attn output .
3957     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL_SHIFT                                             4
3958     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW                                                    (0x1<<5) // This bit is set when h/w detects Receiver Overflow Status . If set, h/w generates pcie_err_attn output .
3959     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW_SHIFT                                              5
3960     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP                                                    (0x1<<6) // This bit is set when h/w detects Malformed TLP Status . If set, h/w generates pcie_err_attn output .
3961     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP_SHIFT                                              6
3962     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC                                                        (0x1<<7) // This bit is set when h/w detects ECRC Error TLP Status , If set, h/w generates pcie_err_attn output .
3963     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC_SHIFT                                                  7
3964     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT                                                    (0x1<<8) // This bit is set when h/w detects Unsupported Request Error Status . If set, h/w generates pcie_err_attn output .
3965     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT_SHIFT                                              8
3966     #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT                                            (0x1<<9) //
3967     #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT_SHIFT                                      9
3968     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP1                                                   (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function 1. If set, h/w generates pcie_err_attn output.
3969     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_PSND_TLP1_SHIFT                                             10
3970     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL1                                                    (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Status in function 1. If set, h/w generates pcie_err_attn output .
3971     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_FC_PRTL1_SHIFT                                              11
3972     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT1                                                (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in function 1. If set, h/w generates pcie_err_attn output .
3973     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_CPL_TIMEOUT1_SHIFT                                          12
3974     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT1                                                (0x1<<13) // This bits is set when h/w detects Receive UR Status in function 1. If set, h/w generates pcie_err_attn output .
3975     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MASTER_ABRT1_SHIFT                                          13
3976     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL1                                                  (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in function 1. If set, h/w generates pcie_err_attn output when this error is seen.
3977     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNEXP_CPL1_SHIFT                                            14
3978     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW1                                                   (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in function 1. If set, h/w generates pcie_err_attn output .
3979     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_RX_OFLOW1_SHIFT                                             15
3980     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP1                                                   (0x1<<16) // This bit is set when h/w detects Malformed TLP Status in function 1. If set, h/w generates pcie_err_attn output .
3981     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_MALF_TLP1_SHIFT                                             16
3982     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC1                                                       (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function 1. If set, h/w generates pcie_err_attn output .
3983     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_ECRC1_SHIFT                                                 17
3984     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT1                                                   (0x1<<18) // This bit is set when h/w detects Unsupported Request Error Status in function1. If set, h/w generates pcie_err_attn output .
3985     #define PCIEIP_REG_TL_CTRLSTAT_5_ERR_UNSPPORT1_SHIFT                                             18
3986     #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT1                                           (0x1<<19) //
3987     #define PCIEIP_REG_TL_CTRLSTAT_5_PRI_SIG_TARGET_ABORT1_SHIFT                                     19
3988     #define PCIEIP_REG_TL_CTRLSTAT_5_TRX_ERR_UNEXP_RTAG                                              (0x1<<20) //
3989     #define PCIEIP_REG_TL_CTRLSTAT_5_TRX_ERR_UNEXP_RTAG_SHIFT                                        20
3990     #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_ERR_NP_TAG_IN_USE                                           (0x1<<21) //
3991     #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_ERR_NP_TAG_IN_USE_SHIFT                                     21
3992     #define PCIEIP_REG_TL_CTRLSTAT_5_DL_ERR_ATTN                                                     (0x1<<22) //
3993     #define PCIEIP_REG_TL_CTRLSTAT_5_DL_ERR_ATTN_SHIFT                                               22
3994     #define PCIEIP_REG_TL_CTRLSTAT_5_PHY_ERR_ATTN                                                    (0x1<<23) //
3995     #define PCIEIP_REG_TL_CTRLSTAT_5_PHY_ERR_ATTN_SHIFT                                              23
3996     #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_TXINTF_OVERFLOW                                             (0x1<<24) //
3997     #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_TXINTF_OVERFLOW_SHIFT                                       24
3998     #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_BRIDGE_FORWARD_ERR                                          (0x1<<25) //
3999     #define PCIEIP_REG_TL_CTRLSTAT_5_TTX_BRIDGE_FORWARD_ERR_SHIFT                                    25
4000     #define PCIEIP_REG_TL_CTRLSTAT_5_MPS_ERR_ATTN                                                    (0x1<<26) //
4001     #define PCIEIP_REG_TL_CTRLSTAT_5_MPS_ERR_ATTN_SHIFT                                              26
4002     #define PCIEIP_REG_TL_CTRLSTAT_5_MRRS_ERR_ATTN                                                   (0x1<<27) //
4003     #define PCIEIP_REG_TL_CTRLSTAT_5_MRRS_ERR_ATTN_SHIFT                                             27
4004     #define PCIEIP_REG_TL_CTRLSTAT_5_BOUNDARY4K_ERR_ATTN                                             (0x1<<28) //
4005     #define PCIEIP_REG_TL_CTRLSTAT_5_BOUNDARY4K_ERR_ATTN_SHIFT                                       28
4006     #define PCIEIP_REG_TL_CTRLSTAT_5_UNKNOWNTYPE_ERR_ATTN                                            (0x1<<29) //
4007     #define PCIEIP_REG_TL_CTRLSTAT_5_UNKNOWNTYPE_ERR_ATTN_SHIFT                                      29
4008     #define PCIEIP_REG_TL_CTRLSTAT_5_UNUSED_1                                                        (0x3<<30) //
4009     #define PCIEIP_REG_TL_CTRLSTAT_5_UNUSED_1_SHIFT                                                  30
4010 #define PCIEIP_REG_USER_CONTROL_1                                                                    0x000818UL //Access:RW   DataWidth:0x20  This register is for use by the user. User can snoop these registers and use it for their own control.  Chips: BB_A0 BB_B0
4011 #define PCIEIP_REG_USER_CONTROL_2                                                                    0x00081cUL //Access:RW   DataWidth:0x20  This register is for use by the user. User can snoop these registers and use it for their own control.  Chips: BB_A0 BB_B0
4012 #define PCIEIP_REG_USER_CONTROL_3                                                                    0x000820UL //Access:RW   DataWidth:0x20  This register is for use by the user. User can snoop these registers and use it for their own control.  Chips: BB_A0 BB_B0
4013 #define PCIEIP_REG_USER_CONTROL_4                                                                    0x000824UL //Access:RW   DataWidth:0x20  This register is for use by the user. User can snoop these registers and use it for their own control.  Chips: BB_A0 BB_B0
4014 #define PCIEIP_REG_USER_CONTROL_5                                                                    0x000828UL //Access:RW   DataWidth:0x20  This register is for use by the user. User can snoop these registers and use it for their own control.  Chips: BB_A0 BB_B0
4015 #define PCIEIP_REG_USER_CONTROL_6                                                                    0x00082cUL //Access:RW   DataWidth:0x20  This register is for use by the user. User can snoop these registers and use it for their own control.  Chips: BB_A0 BB_B0
4016 #define PCIEIP_REG_USER_CONTROL_7                                                                    0x000830UL //Access:RW   DataWidth:0x20  This register is for use by the user. User can snoop these registers and use it for their own control.  Chips: BB_A0 BB_B0
4017 #define PCIEIP_REG_USER_CONTROL_8                                                                    0x000834UL //Access:RW   DataWidth:0x20  This register is for use by the user. User can snoop these registers and use it for their own control.  Chips: BB_A0 BB_B0
4018 #define PCIEIP_REG_TL_CONTROL_6                                                                      0x00083cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4019     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_8                                                      (0x1<<0) // This bit is used to disable function 8.
4020     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_8_SHIFT                                                0
4021     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_9                                                      (0x1<<1) // This bit is used to disable function 9.
4022     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_9_SHIFT                                                1
4023     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_10                                                     (0x1<<2) // This bit is used to disable function 10.
4024     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_10_SHIFT                                               2
4025     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_11                                                     (0x1<<3) // This bit is used to disable function 11.
4026     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_11_SHIFT                                               3
4027     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_12                                                     (0x1<<4) // This bit is used to disable function 12.
4028     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_12_SHIFT                                               4
4029     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_13                                                     (0x1<<5) // This bit is used to disable function 13.
4030     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_13_SHIFT                                               5
4031     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_14                                                     (0x1<<6) // This bit is used to disable function 14.
4032     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_14_SHIFT                                               6
4033     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_15                                                     (0x1<<7) // This bit is used to disable function 15.
4034     #define PCIEIP_REG_TL_CONTROL_6_HIDE_FUNC_15_SHIFT                                               7
4035     #define PCIEIP_REG_TL_CONTROL_6_UNUSED                                                           (0xffffff<<8) //
4036     #define PCIEIP_REG_TL_CONTROL_6_UNUSED_SHIFT                                                     8
4037 #define PCIEIP_REG_SW_LTR_VAL                                                                        0x000840UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4038     #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_LAT_VALUE                                                 (0x3ff<<0) // Snoop latency Value.
4039     #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_LAT_VALUE_SHIFT                                           0
4040     #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_LAT_SCALE                                                 (0x7<<10) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
4041     #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_LAT_SCALE_SHIFT                                           10
4042     #define PCIEIP_REG_SW_LTR_VAL_RESERVED_0                                                         (0x3<<13) //
4043     #define PCIEIP_REG_SW_LTR_VAL_RESERVED_0_SHIFT                                                   13
4044     #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_REQ                                                       (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
4045     #define PCIEIP_REG_SW_LTR_VAL_SW_SNOOP_REQ_SHIFT                                                 15
4046     #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_LAT_VALUE                                              (0x3ff<<16) // No_Snoop latency Value.
4047     #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_LAT_VALUE_SHIFT                                        16
4048     #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_LAT_SCALE                                              (0x7<<26) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
4049     #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_LAT_SCALE_SHIFT                                        26
4050     #define PCIEIP_REG_SW_LTR_VAL_RESERVED                                                           (0x3<<29) //
4051     #define PCIEIP_REG_SW_LTR_VAL_RESERVED_SHIFT                                                     29
4052     #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_REQ                                                    (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
4053     #define PCIEIP_REG_SW_LTR_VAL_SW_NO_SNOOP_REQ_SHIFT                                              31
4054 #define PCIEIP_REG_LTR0_REG                                                                          0x000844UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4055     #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_LAT_VALUE                                                 (0x3ff<<0) // Snoop latency Value.
4056     #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_LAT_VALUE_SHIFT                                           0
4057     #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_LAT_SCALE                                                 (0x7<<10) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
4058     #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_LAT_SCALE_SHIFT                                           10
4059     #define PCIEIP_REG_LTR0_REG_RESERVED_1                                                           (0x3<<13) //
4060     #define PCIEIP_REG_LTR0_REG_RESERVED_1_SHIFT                                                     13
4061     #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_REQ                                                       (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
4062     #define PCIEIP_REG_LTR0_REG_LTR0_SNOOP_REQ_SHIFT                                                 15
4063     #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_LAT_VALUE                                              (0x3ff<<16) // No_Snoop latency Value.
4064     #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_LAT_VALUE_SHIFT                                        16
4065     #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_LAT_SCALE                                              (0x7<<26) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
4066     #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_LAT_SCALE_SHIFT                                        26
4067     #define PCIEIP_REG_LTR0_REG_RESERVED                                                             (0x3<<29) //
4068     #define PCIEIP_REG_LTR0_REG_RESERVED_SHIFT                                                       29
4069     #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_REQ                                                    (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
4070     #define PCIEIP_REG_LTR0_REG_LTR0_NO_SNOOP_REQ_SHIFT                                              31
4071 #define PCIEIP_REG_LTR1_REG                                                                          0x000848UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4072     #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_LAT_VALUE                                                 (0x3ff<<0) // Snoop latency Value.
4073     #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_LAT_VALUE_SHIFT                                           0
4074     #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_LAT_SCALE                                                 (0x7<<10) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
4075     #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_LAT_SCALE_SHIFT                                           10
4076     #define PCIEIP_REG_LTR1_REG_RESERVED_2                                                           (0x3<<13) //
4077     #define PCIEIP_REG_LTR1_REG_RESERVED_2_SHIFT                                                     13
4078     #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_REQ                                                       (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
4079     #define PCIEIP_REG_LTR1_REG_LTR1_SNOOP_REQ_SHIFT                                                 15
4080     #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_LAT_VALUE                                              (0x3ff<<16) // No_Snoop latency Value.
4081     #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_LAT_VALUE_SHIFT                                        16
4082     #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_LAT_SCALE                                              (0x7<<26) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
4083     #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_LAT_SCALE_SHIFT                                        26
4084     #define PCIEIP_REG_LTR1_REG_RESERVED                                                             (0x3<<29) //
4085     #define PCIEIP_REG_LTR1_REG_RESERVED_SHIFT                                                       29
4086     #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_REQ                                                    (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
4087     #define PCIEIP_REG_LTR1_REG_LTR1_NO_SNOOP_REQ_SHIFT                                              31
4088 #define PCIEIP_REG_LTR2_REG                                                                          0x00084cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4089     #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_LAT_VALUE                                                 (0x3ff<<0) // Snoop latency Value.
4090     #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_LAT_VALUE_SHIFT                                           0
4091     #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_LAT_SCALE                                                 (0x7<<10) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
4092     #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_LAT_SCALE_SHIFT                                           10
4093     #define PCIEIP_REG_LTR2_REG_RESERVED_3                                                           (0x3<<13) //
4094     #define PCIEIP_REG_LTR2_REG_RESERVED_3_SHIFT                                                     13
4095     #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_REQ                                                       (0x1<<15) // Requirement bit indicates if device has a latency requirement for a snoop request.
4096     #define PCIEIP_REG_LTR2_REG_LTR2_SNOOP_REQ_SHIFT                                                 15
4097     #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_LAT_VALUE                                              (0x3ff<<16) // No_Snoop latency Value.
4098     #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_LAT_VALUE_SHIFT                                        16
4099     #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_LAT_SCALE                                              (0x7<<26) // Each LTR message has a value and scale field. Values are multiplied by this scale field to yield an absolute time value expressable in a range from 1ns to 34,326,183,936ns
4100     #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_LAT_SCALE_SHIFT                                        26
4101     #define PCIEIP_REG_LTR2_REG_RESERVED                                                             (0x3<<29) //
4102     #define PCIEIP_REG_LTR2_REG_RESERVED_SHIFT                                                       29
4103     #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_REQ                                                    (0x1<<31) // Requirement bit indicates if device has a latency requirement for a no snoop request.
4104     #define PCIEIP_REG_LTR2_REG_LTR2_NO_SNOOP_REQ_SHIFT                                              31
4105 #define PCIEIP_REG_TL_FUNC345_MASK                                                                   0x000850UL //Access:RW   DataWidth:0x20  This register masks specific errors from setting pcie_err_attn.  Chips: BB_A0 BB_B0
4106     #define PCIEIP_REG_TL_FUNC345_MASK_PES2_MASK                                                     (0x1<<0) // Poisoned Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
4107     #define PCIEIP_REG_TL_FUNC345_MASK_PES2_MASK_SHIFT                                               0
4108     #define PCIEIP_REG_TL_FUNC345_MASK_FCPES2_MASK                                                   (0x1<<1) // Flow Control Protocol Error Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
4109     #define PCIEIP_REG_TL_FUNC345_MASK_FCPES2_MASK_SHIFT                                             1
4110     #define PCIEIP_REG_TL_FUNC345_MASK_CTS2_MASK                                                     (0x1<<2) // Completer Timeout Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
4111     #define PCIEIP_REG_TL_FUNC345_MASK_CTS2_MASK_SHIFT                                               2
4112     #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR2_MASK                                                   (0x1<<3) // Received UR Status, Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
4113     #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR2_MASK_SHIFT                                             3
4114     #define PCIEIP_REG_TL_FUNC345_MASK_UCS2_MASK                                                     (0x1<<4) // Unexpected Completion Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
4115     #define PCIEIP_REG_TL_FUNC345_MASK_UCS2_MASK_SHIFT                                               4
4116     #define PCIEIP_REG_TL_FUNC345_MASK_ROS2_MASK                                                     (0x1<<5) // Receiver Overflow Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
4117     #define PCIEIP_REG_TL_FUNC345_MASK_ROS2_MASK_SHIFT                                               5
4118     #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS2_MASK                                                   (0x1<<6) // Malformed TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
4119     #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS2_MASK_SHIFT                                             6
4120     #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS2_MASK                                                   (0x1<<7) // ECRC Error TLP Status Status Mask, if set, does not generate pcie_err_attn output when this error is seen..
4121     #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS2_MASK_SHIFT                                             7
4122     #define PCIEIP_REG_TL_FUNC345_MASK_URES2_MASK                                                    (0x1<<8) // Unsupported Request Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
4123     #define PCIEIP_REG_TL_FUNC345_MASK_URES2_MASK_SHIFT                                              8
4124     #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT2_MASK                                                 (0x1<<9) // Received target Abort Error Status Mask, if set, does not generate pcie_err_attn output when this error is seen.
4125     #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT2_MASK_SHIFT                                           9
4126     #define PCIEIP_REG_TL_FUNC345_MASK_PES3_MASK                                                     (0x1<<10) // Poisoned Error Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
4127     #define PCIEIP_REG_TL_FUNC345_MASK_PES3_MASK_SHIFT                                               10
4128     #define PCIEIP_REG_TL_FUNC345_MASK_FCPES3_MASK                                                   (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
4129     #define PCIEIP_REG_TL_FUNC345_MASK_FCPES3_MASK_SHIFT                                             11
4130     #define PCIEIP_REG_TL_FUNC345_MASK_CTS3_MASK                                                     (0x1<<12) // Completer Timeout Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
4131     #define PCIEIP_REG_TL_FUNC345_MASK_CTS3_MASK_SHIFT                                               12
4132     #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR3_MASK                                                   (0x1<<13) // Received UR Status, Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
4133     #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR3_MASK_SHIFT                                             13
4134     #define PCIEIP_REG_TL_FUNC345_MASK_UCS3_MASK                                                     (0x1<<14) // Unexpected Completion Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
4135     #define PCIEIP_REG_TL_FUNC345_MASK_UCS3_MASK_SHIFT                                               14
4136     #define PCIEIP_REG_TL_FUNC345_MASK_ROS3_MASK                                                     (0x1<<15) // Receiver Overflow Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
4137     #define PCIEIP_REG_TL_FUNC345_MASK_ROS3_MASK_SHIFT                                               15
4138     #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS3_MASK                                                   (0x1<<16) // Malformed TLP Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
4139     #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS3_MASK_SHIFT                                             16
4140     #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS3_MASK                                                   (0x1<<17) // ECRC Error TLP Status Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen..
4141     #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS3_MASK_SHIFT                                             17
4142     #define PCIEIP_REG_TL_FUNC345_MASK_URES3_MASK                                                    (0x1<<18) // Unsupported Request Error Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
4143     #define PCIEIP_REG_TL_FUNC345_MASK_URES3_MASK_SHIFT                                              18
4144     #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT3_MASK                                                 (0x1<<19) // Received target Abort Error Status Mask for Function3, if set, does not generate pcie_err_attn output when this error is seen.
4145     #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT3_MASK_SHIFT                                           19
4146     #define PCIEIP_REG_TL_FUNC345_MASK_PES4_MASK                                                     (0x1<<20) // Poisoned Error Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
4147     #define PCIEIP_REG_TL_FUNC345_MASK_PES4_MASK_SHIFT                                               20
4148     #define PCIEIP_REG_TL_FUNC345_MASK_FCPES4_MASK                                                   (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
4149     #define PCIEIP_REG_TL_FUNC345_MASK_FCPES4_MASK_SHIFT                                             21
4150     #define PCIEIP_REG_TL_FUNC345_MASK_CTS4_MASK                                                     (0x1<<22) // Completer Timeout Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
4151     #define PCIEIP_REG_TL_FUNC345_MASK_CTS4_MASK_SHIFT                                               22
4152     #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR4_MASK                                                   (0x1<<23) // Received UR Status, Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
4153     #define PCIEIP_REG_TL_FUNC345_MASK_RX_UR4_MASK_SHIFT                                             23
4154     #define PCIEIP_REG_TL_FUNC345_MASK_UCS4_MASK                                                     (0x1<<24) // Unexpected Completion Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
4155     #define PCIEIP_REG_TL_FUNC345_MASK_UCS4_MASK_SHIFT                                               24
4156     #define PCIEIP_REG_TL_FUNC345_MASK_ROS4_MASK                                                     (0x1<<25) // Receiver Overflow Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
4157     #define PCIEIP_REG_TL_FUNC345_MASK_ROS4_MASK_SHIFT                                               25
4158     #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS4_MASK                                                   (0x1<<26) // Malformed TLP Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
4159     #define PCIEIP_REG_TL_FUNC345_MASK_MTLPS4_MASK_SHIFT                                             26
4160     #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS4_MASK                                                   (0x1<<27) // ECRC Error TLP Status Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen..
4161     #define PCIEIP_REG_TL_FUNC345_MASK_ECRCS4_MASK_SHIFT                                             27
4162     #define PCIEIP_REG_TL_FUNC345_MASK_URES4_MASK                                                    (0x1<<28) // Unsupported Request Error Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
4163     #define PCIEIP_REG_TL_FUNC345_MASK_URES4_MASK_SHIFT                                              28
4164     #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT4_MASK                                                 (0x1<<29) // Received target Abort Error Status Mask for Function4, if set, does not generate pcie_err_attn output when this error is seen.
4165     #define PCIEIP_REG_TL_FUNC345_MASK_RXTABRT4_MASK_SHIFT                                           29
4166     #define PCIEIP_REG_TL_FUNC345_MASK_UNUSED_1                                                      (0x3<<30) //
4167     #define PCIEIP_REG_TL_FUNC345_MASK_UNUSED_1_SHIFT                                                30
4168 #define PCIEIP_REG_TL_FUNC345_STAT                                                                   0x000854UL //Access:RW   DataWidth:0x20  This register stores the status of errors to generate pcie_err_attn.  Chips: BB_A0 BB_B0
4169     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP2                                                 (0x1<<0) // This bit is set when h/w detects Poisoned Error Status for Function 2. If set, h/w generates pcie_err_attn output .
4170     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP2_SHIFT                                           0
4171     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL2                                                  (0x1<<1) // This bit is set when h/w detects Flow Control Protocol Error Status for Function 2. If set, h/w generates pcie_err_attn output .
4172     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL2_SHIFT                                            1
4173     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2                                              (0x1<<2) // This bit is set when h/w detects Completer Timeout Status for Function 2. If set, h/w generates pcie_err_attn output .
4174     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT2_SHIFT                                        2
4175     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT2                                              (0x1<<3) // This bit is set when h/w detects Receive UR Status in Function 2. If set, h/w generates pcie_err_attn output .
4176     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT2_SHIFT                                        3
4177     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL2                                                (0x1<<4) // This bit is set when h/w detects Unexpected Completion Status for Function 2. If set, h/w generates pcie_err_attn output .
4178     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL2_SHIFT                                          4
4179     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW2                                                 (0x1<<5) // This bit is set when h/w detects Receiver Overflow Status for Function 2. If set, h/w generates pcie_err_attn output .
4180     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW2_SHIFT                                           5
4181     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP2                                                 (0x1<<6) // This bit is set when h/w detects Malformed TLP Status for Function 2. If set, h/w generates pcie_err_attn output
4182     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP2_SHIFT                                           6
4183     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC2                                                     (0x1<<7) // This bit is set when h/w detects ECRC Error TLP Status for Function 2. If set, h/w generates pcie_err_attn output
4184     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC2_SHIFT                                               7
4185     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT2                                                 (0x1<<8) // This bit is set when h/w detects Unsupported Request Error Status for Function 2. If set, h/w generates pcie_err_attn output .
4186     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT2_SHIFT                                           8
4187     #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2                                         (0x1<<9) //
4188     #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT2_SHIFT                                   9
4189     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP3                                                 (0x1<<10) // This bit is set when h/w detects Poisoned Error Status in function 3. If set, h/w generates pcie_err_attn output
4190     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP3_SHIFT                                           10
4191     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL3                                                  (0x1<<11) // This bit is set when h/w detects Flow Control Protocol Error Status in function 3. If set, h/w generates pcie_err_attn output when this error is seen.
4192     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL3_SHIFT                                            11
4193     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3                                              (0x1<<12) // This bit is set when h/w detects Completer Timeout Status in function 3. If set, h/w generates pcie_err_attn output .
4194     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT3_SHIFT                                        12
4195     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT3                                              (0x1<<13) // This bit is set when h/w detects Receive UR Status in function 3. If set, h/w generates pcie_err_attn output .
4196     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT3_SHIFT                                        13
4197     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL3                                                (0x1<<14) // This bit is set when h/w detects Unexpected Completion Status in function 3. If set, h/w generates pcie_err_attn output .
4198     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL3_SHIFT                                          14
4199     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW3                                                 (0x1<<15) // This bit is set when h/w detects Receiver Overflow Status in function 3. If set, h/w generates pcie_err_attn output .
4200     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW3_SHIFT                                           15
4201     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP3                                                 (0x1<<16) // s bit is set when h/w detects Malformed TLP Status Status in function 3. If set, h/w generates pcie_err_attn output .
4202     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP3_SHIFT                                           16
4203     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC3                                                     (0x1<<17) // This bit is set when h/w detects ECRC Error TLP Status in function 3. If set, h/w generates pcie_err_attn output .
4204     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC3_SHIFT                                               17
4205     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT3                                                 (0x1<<18) // This bit is set when h/w detects Unsupported Request Error Status in function3. If set, h/w generates pcie_err_attn output when this error is seen.
4206     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT3_SHIFT                                           18
4207     #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3                                         (0x1<<19) //
4208     #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT3_SHIFT                                   19
4209     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP4                                                 (0x1<<20) // This bit is set when h/w detects Poisoned Error Status Status in function 4. If set, h/w generates pcie_err_attn output .
4210     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_PSND_TLP4_SHIFT                                           20
4211     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL4                                                  (0x1<<21) // This bit is set when h/w detects Flow Control Protocol Error Status in function 4. If set, h/w generates pcie_err_attn output .
4212     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_FC_PRTL4_SHIFT                                            21
4213     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4                                              (0x1<<22) // This bit is set when h/w detects Completer Timeout Status in function 4. If set, h/w generates pcie_err_attn output .
4214     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_CPL_TIMEOUT4_SHIFT                                        22
4215     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT4                                              (0x1<<23) // This bit is set when h/w detects Receive UR Statusin function 4. If set, h/w generates pcie_err_attn output .
4216     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MASTER_ABRT4_SHIFT                                        23
4217     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL4                                                (0x1<<24) // This bit is set when h/w detects Unexpected Completion Status in function 4. If set, h/w generates pcie_err_attn output .
4218     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNEXP_CPL4_SHIFT                                          24
4219     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW4                                                 (0x1<<25) // This bit is set when h/w detects Receiver Overflow Status in function 4. If set, h/w generates pcie_err_attn output .
4220     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_RX_OFLOW4_SHIFT                                           25
4221     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP4                                                 (0x1<<26) // This bit is set when h/w detects Malformed TLP Status in function 4. If set, h/w generates pcie_err_attn output .
4222     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_MALF_TLP4_SHIFT                                           26
4223     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC4                                                     (0x1<<27) // This bit is set when h/w detects ECRC Error TLP Status in function 4. If set, h/w generates pcie_err_attn output .
4224     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_ECRC4_SHIFT                                               27
4225     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT4                                                 (0x1<<28) // This bit is set when h/w detects Unsupported Request Error Status in function4. If set, h/w generates pcie_err_attn output .
4226     #define PCIEIP_REG_TL_FUNC345_STAT_ERR_UNSPPORT4_SHIFT                                           28
4227     #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4                                         (0x1<<29) //
4228     #define PCIEIP_REG_TL_FUNC345_STAT_PRI_SIG_TARGET_ABORT4_SHIFT                                   29
4229     #define PCIEIP_REG_TL_FUNC345_STAT_UNUSED_1                                                      (0x3<<30) //
4230     #define PCIEIP_REG_TL_FUNC345_STAT_UNUSED_1_SHIFT                                                30
4231 #define PCIEIP_REG_TL_FUNC678_MASK                                                                   0x000858UL //Access:RW   DataWidth:0x20  This register masks specific errors from setting pcie_err_attn.  Chips: BB_A0 BB_B0
4232     #define PCIEIP_REG_TL_FUNC678_MASK_PES5_MASK                                                     (0x1<<0) // Poisoned Error Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
4233     #define PCIEIP_REG_TL_FUNC678_MASK_PES5_MASK_SHIFT                                               0
4234     #define PCIEIP_REG_TL_FUNC678_MASK_FCPES5_MASK                                                   (0x1<<1) // Flow Control Protocol Error Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4235     #define PCIEIP_REG_TL_FUNC678_MASK_FCPES5_MASK_SHIFT                                             1
4236     #define PCIEIP_REG_TL_FUNC678_MASK_CTS5_MASK                                                     (0x1<<2) // Completer Timeout Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4237     #define PCIEIP_REG_TL_FUNC678_MASK_CTS5_MASK_SHIFT                                               2
4238     #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR5_MASK                                                   (0x1<<3) // Received UR Status, Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4239     #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR5_MASK_SHIFT                                             3
4240     #define PCIEIP_REG_TL_FUNC678_MASK_UCS5_MASK                                                     (0x1<<4) // Unexpected Completion Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4241     #define PCIEIP_REG_TL_FUNC678_MASK_UCS5_MASK_SHIFT                                               4
4242     #define PCIEIP_REG_TL_FUNC678_MASK_ROS5_MASK                                                     (0x1<<5) // Receiver Overflow Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
4243     #define PCIEIP_REG_TL_FUNC678_MASK_ROS5_MASK_SHIFT                                               5
4244     #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS5_MASK                                                   (0x1<<6) // Malformed TLP Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
4245     #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS5_MASK_SHIFT                                             6
4246     #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS5_MASK                                                   (0x1<<7) // ECRC Error TLP Status Status Mask. If set, does not generate pcie_err_attn output when this error is seen..
4247     #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS5_MASK_SHIFT                                             7
4248     #define PCIEIP_REG_TL_FUNC678_MASK_URES5_MASK                                                    (0x1<<8) // Unsupported Request Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4249     #define PCIEIP_REG_TL_FUNC678_MASK_URES5_MASK_SHIFT                                              8
4250     #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT5_MASK                                                 (0x1<<9) // Received target Abort Error Status Mask. If set, does not generate pcie_err_attn output when this error is seen.
4251     #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT5_MASK_SHIFT                                           9
4252     #define PCIEIP_REG_TL_FUNC678_MASK_PES6_MASK                                                     (0x1<<10) // Poisoned Error Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
4253     #define PCIEIP_REG_TL_FUNC678_MASK_PES6_MASK_SHIFT                                               10
4254     #define PCIEIP_REG_TL_FUNC678_MASK_FCPES6_MASK                                                   (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4255     #define PCIEIP_REG_TL_FUNC678_MASK_FCPES6_MASK_SHIFT                                             11
4256     #define PCIEIP_REG_TL_FUNC678_MASK_CTS6_MASK                                                     (0x1<<12) // Completer Timeout Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4257     #define PCIEIP_REG_TL_FUNC678_MASK_CTS6_MASK_SHIFT                                               12
4258     #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR6_MASK                                                   (0x1<<13) // Received UR Status, Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4259     #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR6_MASK_SHIFT                                             13
4260     #define PCIEIP_REG_TL_FUNC678_MASK_UCS6_MASK                                                     (0x1<<14) // Unexpected Completion Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4261     #define PCIEIP_REG_TL_FUNC678_MASK_UCS6_MASK_SHIFT                                               14
4262     #define PCIEIP_REG_TL_FUNC678_MASK_ROS6_MASK                                                     (0x1<<15) // Receiver Overflow Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
4263     #define PCIEIP_REG_TL_FUNC678_MASK_ROS6_MASK_SHIFT                                               15
4264     #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS6_MASK                                                   (0x1<<16) // Malformed TLP Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
4265     #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS6_MASK_SHIFT                                             16
4266     #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS6_MASK                                                   (0x1<<17) // ECRC Error TLP Status Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen..
4267     #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS6_MASK_SHIFT                                             17
4268     #define PCIEIP_REG_TL_FUNC678_MASK_URES6_MASK                                                    (0x1<<18) // Unsupported Request Error Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4269     #define PCIEIP_REG_TL_FUNC678_MASK_URES6_MASK_SHIFT                                              18
4270     #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT6_MASK                                                 (0x1<<19) // Received target Abort Error Status Mask for Function6. if set, does not generate pcie_err_attn output when this error is seen.
4271     #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT6_MASK_SHIFT                                           19
4272     #define PCIEIP_REG_TL_FUNC678_MASK_PES7_MASK                                                     (0x1<<20) // Poisoned Error Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
4273     #define PCIEIP_REG_TL_FUNC678_MASK_PES7_MASK_SHIFT                                               20
4274     #define PCIEIP_REG_TL_FUNC678_MASK_FCPES7_MASK                                                   (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4275     #define PCIEIP_REG_TL_FUNC678_MASK_FCPES7_MASK_SHIFT                                             21
4276     #define PCIEIP_REG_TL_FUNC678_MASK_CTS7_MASK                                                     (0x1<<22) // Completer Timeout Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4277     #define PCIEIP_REG_TL_FUNC678_MASK_CTS7_MASK_SHIFT                                               22
4278     #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR7_MASK                                                   (0x1<<23) // Received UR Status, Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4279     #define PCIEIP_REG_TL_FUNC678_MASK_RX_UR7_MASK_SHIFT                                             23
4280     #define PCIEIP_REG_TL_FUNC678_MASK_UCS7_MASK                                                     (0x1<<24) // Unexpected Completion Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4281     #define PCIEIP_REG_TL_FUNC678_MASK_UCS7_MASK_SHIFT                                               24
4282     #define PCIEIP_REG_TL_FUNC678_MASK_ROS7_MASK                                                     (0x1<<25) // Receiver Overflow Status Status Mask for Function7, if set, does not generate pcie_err_attn output when this error is seen..
4283     #define PCIEIP_REG_TL_FUNC678_MASK_ROS7_MASK_SHIFT                                               25
4284     #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS7_MASK                                                   (0x1<<26) // Malformed TLP Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
4285     #define PCIEIP_REG_TL_FUNC678_MASK_MTLPS7_MASK_SHIFT                                             26
4286     #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS7_MASK                                                   (0x1<<27) // ECRC Error TLP Status Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen..
4287     #define PCIEIP_REG_TL_FUNC678_MASK_ECRCS7_MASK_SHIFT                                             27
4288     #define PCIEIP_REG_TL_FUNC678_MASK_URES7_MASK                                                    (0x1<<28) // Unsupported Request Error Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4289     #define PCIEIP_REG_TL_FUNC678_MASK_URES7_MASK_SHIFT                                              28
4290     #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT7_MASK                                                 (0x1<<29) // Received target Abort Error Status Mask for Function7. if set, does not generate pcie_err_attn output when this error is seen.
4291     #define PCIEIP_REG_TL_FUNC678_MASK_RXTABRT7_MASK_SHIFT                                           29
4292     #define PCIEIP_REG_TL_FUNC678_MASK_UNUSED_1                                                      (0x3<<30) //
4293     #define PCIEIP_REG_TL_FUNC678_MASK_UNUSED_1_SHIFT                                                30
4294 #define PCIEIP_REG_TL_FUNC678_STAT                                                                   0x00085cUL //Access:RW   DataWidth:0x20  This register stores the status of errors to generate pcie_err_attn.  Chips: BB_A0 BB_B0
4295     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP5                                                 (0x1<<0) // Poisoned Error Status detected for Function 5. If set, hw generates pcie_err_attn output.
4296     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP5_SHIFT                                           0
4297     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL5                                                  (0x1<<1) // Flow Control Protocol Error Status detected for Function 5, if set, generate pcie_err_attn output.
4298     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL5_SHIFT                                            1
4299     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5                                              (0x1<<2) // Completer Timeout Status detected for Function 5. If set, hw generates pcie_err_attn output.
4300     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT5_SHIFT                                        2
4301     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT5                                              (0x1<<3) // Receive UR Status detectedfor Function 5. If set, generate pcie_err_attn output.
4302     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT5_SHIFT                                        3
4303     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL5                                                (0x1<<4) // Unexpected Completion Status detected for Function 5, if set, generate pcie_err_attn output.
4304     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL5_SHIFT                                          4
4305     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW5                                                 (0x1<<5) // Receiver Overflow Status detected for Function 5. If set, hw generates pcie_err_attn output.
4306     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW5_SHIFT                                           5
4307     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP5                                                 (0x1<<6) // Malformed TLP Status detected for Function 5. If set, hw generates pcie_err_attn output.
4308     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP5_SHIFT                                           6
4309     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC5                                                     (0x1<<7) // ECRC Error TLP Status detected for Function 5. If set, hw generates pcie_err_attn output.
4310     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC5_SHIFT                                               7
4311     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT5                                                 (0x1<<8) // Unsupported Request Error Status detected for Function 5. If set, hw generates pcie_err_attn output.
4312     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT5_SHIFT                                           8
4313     #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5                                         (0x1<<9) //
4314     #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT5_SHIFT                                   9
4315     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP6                                                 (0x1<<10) // Poisoned Error Status detected in function 6. If set, hw generates pcie_err_attn output.
4316     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP6_SHIFT                                           10
4317     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL6                                                  (0x1<<11) // Flow Control Protocol Error Status detected in function 6, if set, generate pcie_err_attn output.
4318     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL6_SHIFT                                            11
4319     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6                                              (0x1<<12) // Completer Timeout Status detected in function 6. If set, hw generates pcie_err_attn output.
4320     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT6_SHIFT                                        12
4321     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT6                                              (0x1<<13) // Receive UR Status detectedin function 6. If set, generate pcie_err_attn output.
4322     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT6_SHIFT                                        13
4323     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL6                                                (0x1<<14) // Unexpected Completion Status detected in function 6, if set, generate pcie_err_attn output.
4324     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL6_SHIFT                                          14
4325     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW6                                                 (0x1<<15) // Receiver Overflow Status detected in function 6. If set, hw generates pcie_err_attn output.
4326     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW6_SHIFT                                           15
4327     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP6                                                 (0x1<<16) // Malformed TLP Status detected in function 6. If set, hw generates pcie_err_attn output.
4328     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP6_SHIFT                                           16
4329     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC6                                                     (0x1<<17) // ECRC Error TLP Status detected in function 6. If set, hw generates pcie_err_attn output.
4330     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC6_SHIFT                                               17
4331     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT6                                                 (0x1<<18) // Unsupported Request Error Status detected in function6. If set, hw generates pcie_err_attn output.
4332     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT6_SHIFT                                           18
4333     #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6                                         (0x1<<19) //
4334     #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT6_SHIFT                                   19
4335     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP7                                                 (0x1<<20) // Poisoned Error Status detected in function 7. If set, hw generates pcie_err_attn output.
4336     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_PSND_TLP7_SHIFT                                           20
4337     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL7                                                  (0x1<<21) // Flow Control Protocol Error Status detected in function 7, if set, generate pcie_err_attn output.
4338     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_FC_PRTL7_SHIFT                                            21
4339     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7                                              (0x1<<22) // Completer Timeout Status detected in function 7. If set, hw generates pcie_err_attn output.
4340     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_CPL_TIMEOUT7_SHIFT                                        22
4341     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT7                                              (0x1<<23) // Receive UR Status detectedin function 7. If set, generate pcie_err_attn output.
4342     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MASTER_ABRT7_SHIFT                                        23
4343     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL7                                                (0x1<<24) // Unexpected Completion Status detected in function 7, if set, generate pcie_err_attn output.
4344     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNEXP_CPL7_SHIFT                                          24
4345     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW7                                                 (0x1<<25) // Receiver Overflow Status detected in function 7. If set, hw generates pcie_err_attn output.
4346     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_RX_OFLOW7_SHIFT                                           25
4347     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP7                                                 (0x1<<26) // Malformed TLP Status detected in function 7. If set, hw generates pcie_err_attn output.
4348     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_MALF_TLP7_SHIFT                                           26
4349     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC7                                                     (0x1<<27) // ECRC Error TLP Status detected in function 7. If set, hw generates pcie_err_attn output.
4350     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_ECRC7_SHIFT                                               27
4351     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT7                                                 (0x1<<28) // Unsupported Request Error Status detected in function7. If set, hw generates pcie_err_attn output.
4352     #define PCIEIP_REG_TL_FUNC678_STAT_ERR_UNSPPORT7_SHIFT                                           28
4353     #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7                                         (0x1<<29) //
4354     #define PCIEIP_REG_TL_FUNC678_STAT_PRI_SIG_TARGET_ABORT7_SHIFT                                   29
4355     #define PCIEIP_REG_TL_FUNC678_STAT_UNUSED_1                                                      (0x3<<30) //
4356     #define PCIEIP_REG_TL_FUNC678_STAT_UNUSED_1_SHIFT                                                30
4357 #define PCIEIP_REG_FUNC_INT_SEL                                                                      0x000860UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4358     #define PCIEIP_REG_FUNC_INT_SEL_FUNC0_INT_SEL                                                    (0x7<<0) // Route the interrupt pin for Function 0 to any of INTA to INTD or no interrupt.
4359     #define PCIEIP_REG_FUNC_INT_SEL_FUNC0_INT_SEL_SHIFT                                              0
4360     #define PCIEIP_REG_FUNC_INT_SEL_FUNC1_INT_SEL                                                    (0x7<<3) // Route the interrupt pin for Function 1 to any of INTA to INTD or no interrupt.
4361     #define PCIEIP_REG_FUNC_INT_SEL_FUNC1_INT_SEL_SHIFT                                              3
4362     #define PCIEIP_REG_FUNC_INT_SEL_FUNC2_INT_SEL                                                    (0x7<<6) // Route the interrupt pin for Function 2 to any of INTA to INTD or no interrupt.
4363     #define PCIEIP_REG_FUNC_INT_SEL_FUNC2_INT_SEL_SHIFT                                              6
4364     #define PCIEIP_REG_FUNC_INT_SEL_FUNC3_INT_SEL                                                    (0x7<<9) // Route the interrupt pin for Function 3 to any of INTA to INTD or no interrupt.
4365     #define PCIEIP_REG_FUNC_INT_SEL_FUNC3_INT_SEL_SHIFT                                              9
4366     #define PCIEIP_REG_FUNC_INT_SEL_FUNC4_INT_SEL                                                    (0x7<<12) // Route the interrupt pin for Function 4 to any of INTA to INTD or no interrupt.
4367     #define PCIEIP_REG_FUNC_INT_SEL_FUNC4_INT_SEL_SHIFT                                              12
4368     #define PCIEIP_REG_FUNC_INT_SEL_FUNC5_INT_SEL                                                    (0x7<<15) // Route the interrupt pin for Function 5 to any of INTA to INTD or no interrupt.
4369     #define PCIEIP_REG_FUNC_INT_SEL_FUNC5_INT_SEL_SHIFT                                              15
4370     #define PCIEIP_REG_FUNC_INT_SEL_FUNC6_INT_SEL                                                    (0x7<<18) // Route the interrupt pin for Function 6 to any of INTA to INTD or no interrupt.
4371     #define PCIEIP_REG_FUNC_INT_SEL_FUNC6_INT_SEL_SHIFT                                              18
4372     #define PCIEIP_REG_FUNC_INT_SEL_FUNC7_INT_SEL                                                    (0x7<<21) // Route the interrupt pin for Function 7 to any of INTA to INTD or no interrupt.
4373     #define PCIEIP_REG_FUNC_INT_SEL_FUNC7_INT_SEL_SHIFT                                              21
4374     #define PCIEIP_REG_FUNC_INT_SEL_UNUSED0                                                          (0xff<<24) //
4375     #define PCIEIP_REG_FUNC_INT_SEL_UNUSED0_SHIFT                                                    24
4376 #define PCIEIP_REG_FUNC_INT_SEL2                                                                     0x000864UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4377     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC8_INT_SEL                                                   (0x7<<0) // Route the interrupt pin for Function 0 8o any of INTA to INTD or no interrupt.
4378     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC8_INT_SEL_SHIFT                                             0
4379     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC9_INT_SEL                                                   (0x7<<3) // Route the interrupt pin for Function 9 to any of INTA to INTD or no interrupt.
4380     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC9_INT_SEL_SHIFT                                             3
4381     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC10_INT_SEL                                                  (0x7<<6) // Route the interrupt pin for Function 10 to any of INTA to INTD or no interrupt.
4382     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC10_INT_SEL_SHIFT                                            6
4383     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC11_INT_SEL                                                  (0x7<<9) // Route the interrupt pin for Function 11 to any of INTA to INTD or no interrupt.
4384     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC11_INT_SEL_SHIFT                                            9
4385     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC12_INT_SEL                                                  (0x7<<12) // Route the interrupt pin for Function 12 to any of INTA to INTD or no interrupt.
4386     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC12_INT_SEL_SHIFT                                            12
4387     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC13_INT_SEL                                                  (0x7<<15) // Route the interrupt pin for Function 13 to any of INTA to INTD or no interrupt.
4388     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC13_INT_SEL_SHIFT                                            15
4389     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC14_INT_SEL                                                  (0x7<<18) // Route the interrupt pin for Function 14 to any of INTA to INTD or no interrupt.
4390     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC14_INT_SEL_SHIFT                                            18
4391     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC15_INT_SEL                                                  (0x7<<21) // Route the interrupt pin for Function 15 to any of INTA to INTD or no interrupt.
4392     #define PCIEIP_REG_FUNC_INT_SEL2_FUNC15_INT_SEL_SHIFT                                            21
4393     #define PCIEIP_REG_FUNC_INT_SEL2_UNUSED0                                                         (0xff<<24) //
4394     #define PCIEIP_REG_FUNC_INT_SEL2_UNUSED0_SHIFT                                                   24
4395 #define PCIEIP_REG_TL_RST_CTRL                                                                       0x000868UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4396     #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_MDIO_PERST                                                (0x1<<0) // This bit when cleared will keep the Serdes MDIO regs in reset till PERST_N is released. Default behavior is to release Serdes MDIO from reset on Vaux power being present.
4397     #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_MDIO_PERST_SHIFT                                          0
4398     #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_UC_PERST                                                  (0x1<<1) // This bit when cleared will keep the micro in reset till PERST_N is released. Default behavior is to release micro from reset on Vaux power being present.
4399     #define PCIEIP_REG_TL_RST_CTRL_SEL_DIS_UC_PERST_SHIFT                                            1
4400     #define PCIEIP_REG_TL_RST_CTRL_SOFT_MDIO_RST                                                     (0x1<<2) // This bit when set will reset the Serdes register space, provided bit 3 is also set.
4401     #define PCIEIP_REG_TL_RST_CTRL_SOFT_MDIO_RST_SHIFT                                               2
4402     #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_MDIO_RST                                                 (0x1<<3) // Tthis bit when set will allow bit 2 value to propogate to Serdes. This bit acts as the mux sel for a soft MDIO reset.
4403     #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_MDIO_RST_SHIFT                                           3
4404     #define PCIEIP_REG_TL_RST_CTRL_SOFT_UC_RST                                                       (0x1<<4) // This bit when set will reset the micro, provided bit 5 is also set.
4405     #define PCIEIP_REG_TL_RST_CTRL_SOFT_UC_RST_SHIFT                                                 4
4406     #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_UC_RST                                                   (0x1<<5) // For gen3 serdes, this bit when set will allow bit 4 value to propogate to uc reset. This bit acts as the mux sel for a soft micro reset.
4407     #define PCIEIP_REG_TL_RST_CTRL_SEL_SOFT_UC_RST_SHIFT                                             5
4408     #define PCIEIP_REG_TL_RST_CTRL_UNUSED0                                                           (0x3<<6) //
4409     #define PCIEIP_REG_TL_RST_CTRL_UNUSED0_SHIFT                                                     6
4410     #define PCIEIP_REG_TL_RST_CTRL_ENABLE_ALT_MSG_ERROR                                              (0x1<<8) // Based on 3.0 errata, allows interpreting Rx messages with routing errors or hdr type errors to be UR instead of malformed.
4411     #define PCIEIP_REG_TL_RST_CTRL_ENABLE_ALT_MSG_ERROR_SHIFT                                        8
4412     #define PCIEIP_REG_TL_RST_CTRL_RESERVED                                                          (0x7fffff<<9) //
4413     #define PCIEIP_REG_TL_RST_CTRL_RESERVED_SHIFT                                                    9
4414 #define PCIEIP_REG_TL_OBFF_CTRL                                                                      0x000870UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4415     #define PCIEIP_REG_TL_OBFF_CTRL_MIN_OBFF_PULSE                                                   (0x7f<<0) // Min number of PM clocks to wait after WAKE# signal transition, so that it is throughly debounced.
4416     #define PCIEIP_REG_TL_OBFF_CTRL_MIN_OBFF_PULSE_SHIFT                                             0
4417     #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED0                                                          (0x1<<7) //
4418     #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED0_SHIFT                                                    7
4419     #define PCIEIP_REG_TL_OBFF_CTRL_MAX_OBFF_PULSE                                                   (0x7f<<8) // Max number of PM clocks to wait after WAKE# signal transition to declare OBFF state
4420     #define PCIEIP_REG_TL_OBFF_CTRL_MAX_OBFF_PULSE_SHIFT                                             8
4421     #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED1                                                          (0x1<<15) //
4422     #define PCIEIP_REG_TL_OBFF_CTRL_UNUSED1_SHIFT                                                    15
4423     #define PCIEIP_REG_TL_OBFF_CTRL_RESERVED                                                         (0xffff<<16) //
4424     #define PCIEIP_REG_TL_OBFF_CTRL_RESERVED_SHIFT                                                   16
4425 #define PCIEIP_REG_TL_CTLSTAT_0                                                                      0x000874UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4426     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_1_HIDDEN                                               (0x1<<0) // Set if func1 is hidden either due to hide_func_1 pad being driven high or due to programming bit in TL reg This bit is tied to 0, if IP does not support multiple functions.
4427     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_1_HIDDEN_SHIFT                                         0
4428     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_2_HIDDEN                                               (0x1<<1) // Set if func2 is hidden either due to hide_func_2 pad being driven high or due to programming bit in TL reg
4429     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_2_HIDDEN_SHIFT                                         1
4430     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_3_HIDDEN                                               (0x1<<2) // Set if func3 is hidden either due to hide_func_3 pad being driven high or due to programming bit in TL reg
4431     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_3_HIDDEN_SHIFT                                         2
4432     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_4_HIDDEN                                               (0x1<<3) // Set if func4 is hidden either due to hide_func_4 pad being driven high or due to programming bit in TL reg
4433     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_4_HIDDEN_SHIFT                                         3
4434     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_5_HIDDEN                                               (0x1<<4) // Set if func5 is hidden either due to hide_func_5 pad being driven high or due to programming bit in TL reg
4435     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_5_HIDDEN_SHIFT                                         4
4436     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_6_HIDDEN                                               (0x1<<5) // Set if func6 is hidden either due to hide_func_6 pad being driven high or due to programming bit in TL reg
4437     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_6_HIDDEN_SHIFT                                         5
4438     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_7_HIDDEN                                               (0x1<<6) // Set if func7 is hidden either due to hide_func_7 pad being driven high or due to programming bit in TL reg
4439     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_7_HIDDEN_SHIFT                                         6
4440     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_8_HIDDEN                                               (0x1<<7) // Set if func8 is hidden either due to hide_func_8 pad being driven high or due to programming bit in TL reg
4441     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_8_HIDDEN_SHIFT                                         7
4442     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_9_HIDDEN                                               (0x1<<8) // Set if func9 is hidden either due to hide_func_9 pad being driven high or due to programming bit in TL reg
4443     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_9_HIDDEN_SHIFT                                         8
4444     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_10_HIDDEN                                              (0x1<<9) // Set if func10 is hidden either due to hide_func_10 pad being driven high or due to programming bit in TL reg
4445     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_10_HIDDEN_SHIFT                                        9
4446     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_11_HIDDEN                                              (0x1<<10) // Set if func11 is hidden either due to hide_func_11 pad being driven high or due to programming bit in TL reg
4447     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_11_HIDDEN_SHIFT                                        10
4448     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_12_HIDDEN                                              (0x1<<11) // Set if func12 is hidden either due to hide_func_12 pad being driven high or due to programming bit in TL reg
4449     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_12_HIDDEN_SHIFT                                        11
4450     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_13_HIDDEN                                              (0x1<<12) // Set if func13 is hidden either due to hide_func_13 pad being driven high or due to programming bit in TL reg
4451     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_13_HIDDEN_SHIFT                                        12
4452     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_14_HIDDEN                                              (0x1<<13) // Set if func14 is hidden either due to hide_func_14 pad being driven high or due to programming bit in TL reg
4453     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_14_HIDDEN_SHIFT                                        13
4454     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_15_HIDDEN                                              (0x1<<14) // Set if func15 is hidden either due to hide_func_15 pad being driven high or due to programming bit in TL reg
4455     #define PCIEIP_REG_TL_CTLSTAT_0_PCIE_FUNC_15_HIDDEN_SHIFT                                        14
4456     #define PCIEIP_REG_TL_CTLSTAT_0_UNUSED0                                                          (0x7<<15) //
4457     #define PCIEIP_REG_TL_CTLSTAT_0_UNUSED0_SHIFT                                                    15
4458     #define PCIEIP_REG_TL_CTLSTAT_0_TL_DBG_MALF_ERR                                                  (0x3fff<<18) // debug status for sources of malformed TLP error.
4459     #define PCIEIP_REG_TL_CTLSTAT_0_TL_DBG_MALF_ERR_SHIFT                                            18
4460 #define PCIEIP_REG_PM_STATUS_0                                                                       0x000878UL //Access:R    DataWidth:0x20  For Debug.  Chips: BB_A0 BB_B0
4461     #define PCIEIP_REG_PM_STATUS_0_PME_SENT_SM0                                                      (0x1f<<0) // State machine that handles PME for Function
4462     #define PCIEIP_REG_PM_STATUS_0_PME_SENT_SM0_SHIFT                                                0
4463     #define PCIEIP_REG_PM_STATUS_0_UNUSED0                                                           (0x7ff<<5) //
4464     #define PCIEIP_REG_PM_STATUS_0_UNUSED0_SHIFT                                                     5
4465     #define PCIEIP_REG_PM_STATUS_0_OBFF_CURR_STATE                                                   (0xf<<16) // State machine that handles OBFF for Function
4466     #define PCIEIP_REG_PM_STATUS_0_OBFF_CURR_STATE_SHIFT                                             16
4467     #define PCIEIP_REG_PM_STATUS_0_PCIE_OBFF_STATE                                                   (0xf<<20) // Current OBFF state Indication from DUT.
4468     #define PCIEIP_REG_PM_STATUS_0_PCIE_OBFF_STATE_SHIFT                                             20
4469     #define PCIEIP_REG_PM_STATUS_0_PM_LINK_STATE_SM                                                  (0xff<<24) // State machine that controls current PM Link state.
4470     #define PCIEIP_REG_PM_STATUS_0_PM_LINK_STATE_SM_SHIFT                                            24
4471 #define PCIEIP_REG_PM_STATUS_1                                                                       0x00087cUL //Access:R    DataWidth:0x20  For Debug.  Chips: BB_A0 BB_B0
4472     #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE0                                                   (0x1<<0) // Direct reflection of Config PM PME enable bit for function 0.
4473     #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE0_SHIFT                                             0
4474     #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS0                                                   (0x1<<1) // Direct reflection of config PM PME status bit for function 0.
4475     #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS0_SHIFT                                             1
4476     #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN0                                                (0x1<<2) // Direct reflection of CFG link control, Aux power PM enabled.
4477     #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN0_SHIFT                                          2
4478     #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE1                                                   (0x1<<3) // Direct reflection of Config PM PME enable bit for function 1.
4479     #define PCIEIP_REG_PM_STATUS_1_CFG_PME_ENABLE1_SHIFT                                             3
4480     #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS1                                                   (0x1<<4) // Direct reflection of config PM PME status bit for function 1.
4481     #define PCIEIP_REG_PM_STATUS_1_CFG_PME_STATUS1_SHIFT                                             4
4482     #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN1                                                (0x1<<5) // Direct reflection of CFG link control, Aux power PM enabled.
4483     #define PCIEIP_REG_PM_STATUS_1_CFG_AUX_PWR_PM_EN1_SHIFT                                          5
4484     #define PCIEIP_REG_PM_STATUS_1_UNUSED0                                                           (0x3ffff<<6) //
4485     #define PCIEIP_REG_PM_STATUS_1_UNUSED0_SHIFT                                                     6
4486     #define PCIEIP_REG_PM_STATUS_1_REG_BUS_NUM                                                       (0xff<<24) // Current Bus Number Latched by device.
4487     #define PCIEIP_REG_PM_STATUS_1_REG_BUS_NUM_SHIFT                                                 24
4488 #define PCIEIP_REG_TL_FUNC8TO10_MASK                                                                 0x000880UL //Access:RW   DataWidth:0x20  This register masks specific errors from setting pcie_err_attn for functions 8, 9, and 10.  Chips: BB_A0 BB_B0
4489     #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES8_MASK                                                   (0x1<<0) // Poisoned Error Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4490     #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES8_MASK_SHIFT                                             0
4491     #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES8_MASK                                                 (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4492     #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES8_MASK_SHIFT                                           1
4493     #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS8_MASK                                                   (0x1<<2) // Completer Timeout Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4494     #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS8_MASK_SHIFT                                             2
4495     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR8_MASK                                                 (0x1<<3) // Received UR Status, Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4496     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR8_MASK_SHIFT                                           3
4497     #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS8_MASK                                                   (0x1<<4) // Unexpected Completion Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4498     #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS8_MASK_SHIFT                                             4
4499     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS8_MASK                                                   (0x1<<5) // Receiver Overflow Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4500     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS8_MASK_SHIFT                                             5
4501     #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS8_MASK                                                 (0x1<<6) // Malformed TLP Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4502     #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS8_MASK_SHIFT                                           6
4503     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS8_MASK                                                 (0x1<<7) // ECRC Error TLP Status Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4504     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS8_MASK_SHIFT                                           7
4505     #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES8_MASK                                                  (0x1<<8) // Unsupported Request Error Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4506     #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES8_MASK_SHIFT                                            8
4507     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT8_MASK                                               (0x1<<9) // Received target Abort Error Status Mask for Function8. If set, does not generate pcie_err_attn output when this error is seen.
4508     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT8_MASK_SHIFT                                         9
4509     #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES9_MASK                                                   (0x1<<10) // Poisoned Error Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4510     #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES9_MASK_SHIFT                                             10
4511     #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES9_MASK                                                 (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4512     #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES9_MASK_SHIFT                                           11
4513     #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS9_MASK                                                   (0x1<<12) // Completer Timeout Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4514     #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS9_MASK_SHIFT                                             12
4515     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR9_MASK                                                 (0x1<<13) // Received UR Status, Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4516     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR9_MASK_SHIFT                                           13
4517     #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS9_MASK                                                   (0x1<<14) // Unexpected Completion Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4518     #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS9_MASK_SHIFT                                             14
4519     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS9_MASK                                                   (0x1<<15) // Receiver Overflow Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4520     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS9_MASK_SHIFT                                             15
4521     #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS9_MASK                                                 (0x1<<16) // Malformed TLP Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4522     #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS9_MASK_SHIFT                                           16
4523     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS9_MASK                                                 (0x1<<17) // ECRC Error TLP Status Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4524     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS9_MASK_SHIFT                                           17
4525     #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES9_MASK                                                  (0x1<<18) // Unsupported Request Error Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4526     #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES9_MASK_SHIFT                                            18
4527     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT9_MASK                                               (0x1<<19) // Received target Abort Error Status Mask for Function9. If set, does not generate pcie_err_attn output when this error is seen.
4528     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT9_MASK_SHIFT                                         19
4529     #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES10_MASK                                                  (0x1<<20) // Poisoned Error Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4530     #define PCIEIP_REG_TL_FUNC8TO10_MASK_PES10_MASK_SHIFT                                            20
4531     #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES10_MASK                                                (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4532     #define PCIEIP_REG_TL_FUNC8TO10_MASK_FCPES10_MASK_SHIFT                                          21
4533     #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS10_MASK                                                  (0x1<<22) // Completer Timeout Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4534     #define PCIEIP_REG_TL_FUNC8TO10_MASK_CTS10_MASK_SHIFT                                            22
4535     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR10_MASK                                                (0x1<<23) // Received UR Status, Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4536     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RX_UR10_MASK_SHIFT                                          23
4537     #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS10_MASK                                                  (0x1<<24) // Unexpected Completion Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4538     #define PCIEIP_REG_TL_FUNC8TO10_MASK_UCS10_MASK_SHIFT                                            24
4539     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS10_MASK                                                  (0x1<<25) // Receiver Overflow Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4540     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ROS10_MASK_SHIFT                                            25
4541     #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS10_MASK                                                (0x1<<26) // Malformed TLP Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4542     #define PCIEIP_REG_TL_FUNC8TO10_MASK_MTLPS10_MASK_SHIFT                                          26
4543     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS10_MASK                                                (0x1<<27) // ECRC Error TLP Status Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4544     #define PCIEIP_REG_TL_FUNC8TO10_MASK_ECRCS10_MASK_SHIFT                                          27
4545     #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES10_MASK                                                 (0x1<<28) // Unsupported Request Error Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4546     #define PCIEIP_REG_TL_FUNC8TO10_MASK_URES10_MASK_SHIFT                                           28
4547     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT10_MASK                                              (0x1<<29) // Received target Abort Error Status Mask for Function10. If set, does not generate pcie_err_attn output when this error is seen.
4548     #define PCIEIP_REG_TL_FUNC8TO10_MASK_RXTABRT10_MASK_SHIFT                                        29
4549     #define PCIEIP_REG_TL_FUNC8TO10_MASK_UNUSED_1                                                    (0x3<<30) //
4550     #define PCIEIP_REG_TL_FUNC8TO10_MASK_UNUSED_1_SHIFT                                              30
4551 #define PCIEIP_REG_TL_FUNC8TO10_STAT                                                                 0x000884UL //Access:RW   DataWidth:0x20  This register stores the status of errors to generate pcie_err_attn for functions 8, 9, and 10.  Chips: BB_A0 BB_B0
4552     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP8                                               (0x1<<0) // Poisoned Error Status detected for Function 8. If set, hw generates pcie_err_attn output.
4553     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP8_SHIFT                                         0
4554     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL8                                                (0x1<<1) // Flow Control Protocol Error Status detected for Function 8, if set, generate pcie_err_attn output.
4555     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL8_SHIFT                                          1
4556     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT8                                            (0x1<<2) // Completer Timeout Status detected for Function 8. If set, hw generates pcie_err_attn output.
4557     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT8_SHIFT                                      2
4558     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT8                                            (0x1<<3) // Receive UR Status detectedfor Function 8. If set, generate pcie_err_attn output.
4559     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT8_SHIFT                                      3
4560     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL8                                              (0x1<<4) // Unexpected Completion Status detected for Function 8, if set, generate pcie_err_attn output.
4561     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL8_SHIFT                                        4
4562     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW8                                               (0x1<<5) // Receiver Overflow Status detected for Function 8. If set, hw generates pcie_err_attn output.
4563     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW8_SHIFT                                         5
4564     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP8                                               (0x1<<6) // Malformed TLP Status detected for Function 8. If set, hw generates pcie_err_attn output.
4565     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP8_SHIFT                                         6
4566     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC8                                                   (0x1<<7) // ECRC Error TLP Status detected for Function 8. If set, hw generates pcie_err_attn output.
4567     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC8_SHIFT                                             7
4568     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT8                                               (0x1<<8) // Unsupported Request Error Status detected for Function 8. If set, hw generates pcie_err_attn output.
4569     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT8_SHIFT                                         8
4570     #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT8                                       (0x1<<9) //
4571     #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT8_SHIFT                                 9
4572     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP9                                               (0x1<<10) // Poisoned Error Status detected in function 9. If set, hw generates pcie_err_attn output.
4573     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP9_SHIFT                                         10
4574     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL9                                                (0x1<<11) // Flow Control Protocol Error Status detected in function 9, if set, generate pcie_err_attn output.
4575     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL9_SHIFT                                          11
4576     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT9                                            (0x1<<12) // Completer Timeout Status detected in function 9. If set, hw generates pcie_err_attn output.
4577     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT9_SHIFT                                      12
4578     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT9                                            (0x1<<13) // Receive UR Status detectedin function 9. If set, generate pcie_err_attn output.
4579     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT9_SHIFT                                      13
4580     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL9                                              (0x1<<14) // Unexpected Completion Status detected in function 9, if set, generate pcie_err_attn output.
4581     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL9_SHIFT                                        14
4582     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW9                                               (0x1<<15) // Receiver Overflow Status detected in function 9. If set, hw generates pcie_err_attn output.
4583     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW9_SHIFT                                         15
4584     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP9                                               (0x1<<16) // Malformed TLP Status detected in function 9. If set, hw generates pcie_err_attn output.
4585     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP9_SHIFT                                         16
4586     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC9                                                   (0x1<<17) // ECRC Error TLP Status detected in function 9. If set, hw generates pcie_err_attn output.
4587     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC9_SHIFT                                             17
4588     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT9                                               (0x1<<18) // Unsupported Request Error Status detected in function9. If set, hw generates pcie_err_attn output.
4589     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT9_SHIFT                                         18
4590     #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT9                                       (0x1<<19) //
4591     #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT9_SHIFT                                 19
4592     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP10                                              (0x1<<20) // Poisoned Error Status detected in function 10. If set, hw generates pcie_err_attn output.
4593     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_PSND_TLP10_SHIFT                                        20
4594     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL10                                               (0x1<<21) // Flow Control Protocol Error Status detected in function 10, if set, generate pcie_err_attn output.
4595     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_FC_PRTL10_SHIFT                                         21
4596     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT10                                           (0x1<<22) // Completer Timeout Status detected in function 10. If set, hw generates pcie_err_attn output.
4597     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_CPL_TIMEOUT10_SHIFT                                     22
4598     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT10                                           (0x1<<23) // Receive UR Status detectedin function 10. If set, generate pcie_err_attn output.
4599     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MASTER_ABRT10_SHIFT                                     23
4600     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL10                                             (0x1<<24) // Unexpected Completion Status detected in function 10, if set, generate pcie_err_attn output.
4601     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNEXP_CPL10_SHIFT                                       24
4602     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW10                                              (0x1<<25) // Receiver Overflow Status detected in function 10. If set, hw generates pcie_err_attn output.
4603     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_RX_OFLOW10_SHIFT                                        25
4604     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP10                                              (0x1<<26) // Malformed TLP Status detected in function 10. If set, hw generates pcie_err_attn output.
4605     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_MALF_TLP10_SHIFT                                        26
4606     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC10                                                  (0x1<<27) // ECRC Error TLP Status detected in function 10. If set, hw generates pcie_err_attn output.
4607     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_ECRC10_SHIFT                                            27
4608     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT10                                              (0x1<<28) // Unsupported Request Error Status detected in function10. If set, hw generates pcie_err_attn output.
4609     #define PCIEIP_REG_TL_FUNC8TO10_STAT_ERR_UNSPPORT10_SHIFT                                        28
4610     #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT10                                      (0x1<<29) //
4611     #define PCIEIP_REG_TL_FUNC8TO10_STAT_PRI_SIG_TARGET_ABORT10_SHIFT                                29
4612     #define PCIEIP_REG_TL_FUNC8TO10_STAT_UNUSED_1                                                    (0x3<<30) //
4613     #define PCIEIP_REG_TL_FUNC8TO10_STAT_UNUSED_1_SHIFT                                              30
4614 #define PCIEIP_REG_TL_FUNC11TO13_MASK                                                                0x000888UL //Access:RW   DataWidth:0x20  This register masks specific errors from setting pcie_err_attn for functions 11, 12, and 13.  Chips: BB_A0 BB_B0
4615     #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES11_MASK                                                 (0x1<<0) // Poisoned Error Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4616     #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES11_MASK_SHIFT                                           0
4617     #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES11_MASK                                               (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4618     #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES11_MASK_SHIFT                                         1
4619     #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS11_MASK                                                 (0x1<<2) // Completer Timeout Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4620     #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS11_MASK_SHIFT                                           2
4621     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR11_MASK                                               (0x1<<3) // Received UR Status, Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4622     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR11_MASK_SHIFT                                         3
4623     #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS11_MASK                                                 (0x1<<4) // Unexpected Completion Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4624     #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS11_MASK_SHIFT                                           4
4625     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS11_MASK                                                 (0x1<<5) // Receiver Overflow Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4626     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS11_MASK_SHIFT                                           5
4627     #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS11_MASK                                               (0x1<<6) // Malformed TLP Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4628     #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS11_MASK_SHIFT                                         6
4629     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS11_MASK                                               (0x1<<7) // ECRC Error TLP Status Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4630     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS11_MASK_SHIFT                                         7
4631     #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES11_MASK                                                (0x1<<8) // Unsupported Request Error Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4632     #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES11_MASK_SHIFT                                          8
4633     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT11_MASK                                             (0x1<<9) // Received target Abort Error Status Mask for Function11. If set, hw does not generate pcie_err_attn output when this error is seen.
4634     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT11_MASK_SHIFT                                       9
4635     #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES12_MASK                                                 (0x1<<10) // Poisoned Error Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4636     #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES12_MASK_SHIFT                                           10
4637     #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES12_MASK                                               (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4638     #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES12_MASK_SHIFT                                         11
4639     #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS12_MASK                                                 (0x1<<12) // Completer Timeout Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4640     #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS12_MASK_SHIFT                                           12
4641     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR12_MASK                                               (0x1<<13) // Received UR Status, Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4642     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR12_MASK_SHIFT                                         13
4643     #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS12_MASK                                                 (0x1<<14) // Unexpected Completion Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4644     #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS12_MASK_SHIFT                                           14
4645     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS12_MASK                                                 (0x1<<15) // Receiver Overflow Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4646     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS12_MASK_SHIFT                                           15
4647     #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS12_MASK                                               (0x1<<16) // Malformed TLP Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4648     #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS12_MASK_SHIFT                                         16
4649     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS12_MASK                                               (0x1<<17) // ECRC Error TLP Status Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4650     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS12_MASK_SHIFT                                         17
4651     #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES12_MASK                                                (0x1<<18) // Unsupported Request Error Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4652     #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES12_MASK_SHIFT                                          18
4653     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT12_MASK                                             (0x1<<19) // Received target Abort Error Status Mask for Function12. If set, hw does not generate pcie_err_attn output when this error is seen.
4654     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT12_MASK_SHIFT                                       19
4655     #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES13_MASK                                                 (0x1<<20) // Poisoned Error Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4656     #define PCIEIP_REG_TL_FUNC11TO13_MASK_PES13_MASK_SHIFT                                           20
4657     #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES13_MASK                                               (0x1<<21) // Flow Control Protocol Error Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4658     #define PCIEIP_REG_TL_FUNC11TO13_MASK_FCPES13_MASK_SHIFT                                         21
4659     #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS13_MASK                                                 (0x1<<22) // Completer Timeout Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4660     #define PCIEIP_REG_TL_FUNC11TO13_MASK_CTS13_MASK_SHIFT                                           22
4661     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR13_MASK                                               (0x1<<23) // Received UR Status, Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4662     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RX_UR13_MASK_SHIFT                                         23
4663     #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS13_MASK                                                 (0x1<<24) // Unexpected Completion Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4664     #define PCIEIP_REG_TL_FUNC11TO13_MASK_UCS13_MASK_SHIFT                                           24
4665     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS13_MASK                                                 (0x1<<25) // Receiver Overflow Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4666     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ROS13_MASK_SHIFT                                           25
4667     #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS13_MASK                                               (0x1<<26) // Malformed TLP Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4668     #define PCIEIP_REG_TL_FUNC11TO13_MASK_MTLPS13_MASK_SHIFT                                         26
4669     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS13_MASK                                               (0x1<<27) // ECRC Error TLP Status Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4670     #define PCIEIP_REG_TL_FUNC11TO13_MASK_ECRCS13_MASK_SHIFT                                         27
4671     #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES13_MASK                                                (0x1<<28) // Unsupported Request Error Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4672     #define PCIEIP_REG_TL_FUNC11TO13_MASK_URES13_MASK_SHIFT                                          28
4673     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT13_MASK                                             (0x1<<29) // Received target Abort Error Status Mask for Function13. If set, hw does not generate pcie_err_attn output when this error is seen.
4674     #define PCIEIP_REG_TL_FUNC11TO13_MASK_RXTABRT13_MASK_SHIFT                                       29
4675     #define PCIEIP_REG_TL_FUNC11TO13_MASK_UNUSED_1                                                   (0x3<<30) //
4676     #define PCIEIP_REG_TL_FUNC11TO13_MASK_UNUSED_1_SHIFT                                             30
4677 #define PCIEIP_REG_TL_FUNC11TO13_STAT                                                                0x00088cUL //Access:RW   DataWidth:0x20  This register stores the status of errors to generate pcie_err_attn for functions 11, 12, and 13.  Chips: BB_A0 BB_B0
4678     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP11                                             (0x1<<0) // Poisoned Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
4679     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP11_SHIFT                                       0
4680     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL11                                              (0x1<<1) // Flow Control Protocol Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
4681     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL11_SHIFT                                        1
4682     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT11                                          (0x1<<2) // Completer Timeout Status detected for Function 11. If set, hw generates pcie_err_attn output.
4683     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT11_SHIFT                                    2
4684     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT11                                          (0x1<<3) // Receive UR Status detectedfor Function 11. If set, hw generates pcie_err_attn output.
4685     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT11_SHIFT                                    3
4686     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL11                                            (0x1<<4) // Unexpected Completion Status detected for Function 11. If set, hw generates, generate pcie_err_attn output.
4687     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL11_SHIFT                                      4
4688     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW11                                             (0x1<<5) // Receiver Overflow Status detected for Function 11. If set, hw generates pcie_err_attn output.
4689     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW11_SHIFT                                       5
4690     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP11                                             (0x1<<6) // Malformed TLP Status detected for Function 11. If set, hw generates pcie_err_attn output.
4691     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP11_SHIFT                                       6
4692     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC11                                                 (0x1<<7) // ECRC Error TLP Status detected for Function 11. If set, hw generates pcie_err_attn output.
4693     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC11_SHIFT                                           7
4694     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT11                                             (0x1<<8) // Unsupported Request Error Status detected for Function 11. If set, hw generates pcie_err_attn output.
4695     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT11_SHIFT                                       8
4696     #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT11                                     (0x1<<9) //
4697     #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT11_SHIFT                               9
4698     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP12                                             (0x1<<10) // Poisoned Error Status detected in function 12. If set, hw generates pcie_err_attn output.
4699     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP12_SHIFT                                       10
4700     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL12                                              (0x1<<11) // Flow Control Protocol Error Status detected in function 12. If set, hw generates pcie_err_attn output.
4701     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL12_SHIFT                                        11
4702     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT12                                          (0x1<<12) // Completer Timeout Status detected in function 12. If set, hw generates pcie_err_attn output.
4703     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT12_SHIFT                                    12
4704     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT12                                          (0x1<<13) // Receive UR Status detectedin function 12. If set, hw generates pcie_err_attn output.
4705     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT12_SHIFT                                    13
4706     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL12                                            (0x1<<14) // Unexpected Completion Status detected in function 12. If set, hw generates pcie_err_attn output.
4707     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL12_SHIFT                                      14
4708     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW12                                             (0x1<<15) // Receiver Overflow Status detected in function 12. If set, hw generates pcie_err_attn output.
4709     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW12_SHIFT                                       15
4710     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP12                                             (0x1<<16) // Malformed TLP Status detected in function 12. If set, hw generates pcie_err_attn output.
4711     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP12_SHIFT                                       16
4712     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC12                                                 (0x1<<17) // ECRC Error TLP Status detected in function 12. If set, hw generates pcie_err_attn output.
4713     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC12_SHIFT                                           17
4714     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT12                                             (0x1<<18) // Unsupported Request Error Status detected in function12. If set, hw generates pcie_err_attn output.
4715     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT12_SHIFT                                       18
4716     #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT12                                     (0x1<<19) //
4717     #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT12_SHIFT                               19
4718     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP13                                             (0x1<<20) // Poisoned Error Status detected in function 13. If set, hw generates pcie_err_attn output.
4719     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_PSND_TLP13_SHIFT                                       20
4720     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL13                                              (0x1<<21) // Flow Control Protocol Error Status detected in function 13. If set, hw generates pcie_err_attn output.
4721     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_FC_PRTL13_SHIFT                                        21
4722     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT13                                          (0x1<<22) // Completer Timeout Status detected in function 13. If set, hw generates pcie_err_attn output.
4723     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_CPL_TIMEOUT13_SHIFT                                    22
4724     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT13                                          (0x1<<23) // Receive UR Status detectedin function 13. If set, hw generates pcie_err_attn output.
4725     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MASTER_ABRT13_SHIFT                                    23
4726     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL13                                            (0x1<<24) // Unexpected Completion Status detected in function 13. If set, hw generates pcie_err_attn output.
4727     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNEXP_CPL13_SHIFT                                      24
4728     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW13                                             (0x1<<25) // Receiver Overflow Status detected in function 13. If set, hw generates pcie_err_attn output.
4729     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_RX_OFLOW13_SHIFT                                       25
4730     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP13                                             (0x1<<26) // Malformed TLP Status detected in function 13. If set, hw generates pcie_err_attn output.
4731     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_MALF_TLP13_SHIFT                                       26
4732     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC13                                                 (0x1<<27) // ECRC Error TLP Status detected in function 13. If set, hw generates pcie_err_attn output.
4733     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_ECRC13_SHIFT                                           27
4734     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT13                                             (0x1<<28) // Unsupported Request Error Status detected in function13. If set, hw generates pcie_err_attn output.
4735     #define PCIEIP_REG_TL_FUNC11TO13_STAT_ERR_UNSPPORT13_SHIFT                                       28
4736     #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT13                                     (0x1<<29) //
4737     #define PCIEIP_REG_TL_FUNC11TO13_STAT_PRI_SIG_TARGET_ABORT13_SHIFT                               29
4738     #define PCIEIP_REG_TL_FUNC11TO13_STAT_UNUSED_1                                                   (0x3<<30) //
4739     #define PCIEIP_REG_TL_FUNC11TO13_STAT_UNUSED_1_SHIFT                                             30
4740 #define PCIEIP_REG_TL_FUNC14TO15_MASK                                                                0x000890UL //Access:RW   DataWidth:0x20  This register masks specific errors from setting pcie_err_attn for functions 14 and 15.  Chips: BB_A0 BB_B0
4741     #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES14_MASK                                                 (0x1<<0) // Poisoned Error Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4742     #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES14_MASK_SHIFT                                           0
4743     #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES14_MASK                                               (0x1<<1) // Flow Control Protocol Error Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4744     #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES14_MASK_SHIFT                                         1
4745     #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS14_MASK                                                 (0x1<<2) // Completer Timeout Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4746     #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS14_MASK_SHIFT                                           2
4747     #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR14_MASK                                               (0x1<<3) // Received UR Status, Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4748     #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR14_MASK_SHIFT                                         3
4749     #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS14_MASK                                                 (0x1<<4) // Unexpected Completion Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4750     #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS14_MASK_SHIFT                                           4
4751     #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS14_MASK                                                 (0x1<<5) // Receiver Overflow Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4752     #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS14_MASK_SHIFT                                           5
4753     #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS14_MASK                                               (0x1<<6) // Malformed TLP Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4754     #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS14_MASK_SHIFT                                         6
4755     #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS14_MASK                                               (0x1<<7) // ECRC Error TLP Status Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4756     #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS14_MASK_SHIFT                                         7
4757     #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES14_MASK                                                (0x1<<8) // Unsupported Request Error Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4758     #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES14_MASK_SHIFT                                          8
4759     #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT14_MASK                                             (0x1<<9) // Received target Abort Error Status Mask for Function14. If set, does not generate pcie_err_attn output when this error is seen.
4760     #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT14_MASK_SHIFT                                       9
4761     #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES15_MASK                                                 (0x1<<10) // Poisoned Error Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4762     #define PCIEIP_REG_TL_FUNC14TO15_MASK_PES15_MASK_SHIFT                                           10
4763     #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES15_MASK                                               (0x1<<11) // Flow Control Protocol Error Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4764     #define PCIEIP_REG_TL_FUNC14TO15_MASK_FCPES15_MASK_SHIFT                                         11
4765     #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS15_MASK                                                 (0x1<<12) // Completer Timeout Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4766     #define PCIEIP_REG_TL_FUNC14TO15_MASK_CTS15_MASK_SHIFT                                           12
4767     #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR15_MASK                                               (0x1<<13) // Received UR Status, Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4768     #define PCIEIP_REG_TL_FUNC14TO15_MASK_RX_UR15_MASK_SHIFT                                         13
4769     #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS15_MASK                                                 (0x1<<14) // Unexpected Completion Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4770     #define PCIEIP_REG_TL_FUNC14TO15_MASK_UCS15_MASK_SHIFT                                           14
4771     #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS15_MASK                                                 (0x1<<15) // Receiver Overflow Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4772     #define PCIEIP_REG_TL_FUNC14TO15_MASK_ROS15_MASK_SHIFT                                           15
4773     #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS15_MASK                                               (0x1<<16) // Malformed TLP Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4774     #define PCIEIP_REG_TL_FUNC14TO15_MASK_MTLPS15_MASK_SHIFT                                         16
4775     #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS15_MASK                                               (0x1<<17) // ECRC Error TLP Status Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4776     #define PCIEIP_REG_TL_FUNC14TO15_MASK_ECRCS15_MASK_SHIFT                                         17
4777     #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES15_MASK                                                (0x1<<18) // Unsupported Request Error Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4778     #define PCIEIP_REG_TL_FUNC14TO15_MASK_URES15_MASK_SHIFT                                          18
4779     #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT15_MASK                                             (0x1<<19) // Received target Abort Error Status Mask for Function15. If set, does not generate pcie_err_attn output when this error is seen.
4780     #define PCIEIP_REG_TL_FUNC14TO15_MASK_RXTABRT15_MASK_SHIFT                                       19
4781     #define PCIEIP_REG_TL_FUNC14TO15_MASK_UNUSED_1                                                   (0xfff<<20) //
4782     #define PCIEIP_REG_TL_FUNC14TO15_MASK_UNUSED_1_SHIFT                                             20
4783 #define PCIEIP_REG_TL_FUNC14TO15_STAT                                                                0x000894UL //Access:RW   DataWidth:0x20  This register stores the status of errors to generate pcie_err_attn for functions 14 and 15.  Chips: BB_A0 BB_B0
4784     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP14                                             (0x1<<0) // Poisoned Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
4785     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP14_SHIFT                                       0
4786     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL14                                              (0x1<<1) // Flow Control Protocol Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
4787     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL14_SHIFT                                        1
4788     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT14                                          (0x1<<2) // Completer Timeout Status detected for Function 14. If set, hw generates pcie_err_attn output.
4789     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT14_SHIFT                                    2
4790     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT14                                          (0x1<<3) // Receive UR Status detectedfor Function 14. If set, hw generates pcie_err_attn output.
4791     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT14_SHIFT                                    3
4792     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL14                                            (0x1<<4) // Unexpected Completion Status detected for Function 14. If set, hw generates pcie_err_attn output.
4793     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL14_SHIFT                                      4
4794     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW14                                             (0x1<<5) // Receiver Overflow Status detected for Function 14. If set, hw generates pcie_err_attn output.
4795     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW14_SHIFT                                       5
4796     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP14                                             (0x1<<6) // Malformed TLP Status detected for Function 14. If set, hw generates pcie_err_attn output.
4797     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP14_SHIFT                                       6
4798     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC14                                                 (0x1<<7) // ECRC Error TLP Status detected for Function 14. If set, hw generates pcie_err_attn output.
4799     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC14_SHIFT                                           7
4800     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT14                                             (0x1<<8) // Unsupported Request Error Status detected for Function 14. If set, hw generates pcie_err_attn output.
4801     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT14_SHIFT                                       8
4802     #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT14                                     (0x1<<9) //
4803     #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT14_SHIFT                               9
4804     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP15                                             (0x1<<10) // Poisoned Error Status detected in function 15. If set, hw generates pcie_err_attn output.
4805     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_PSND_TLP15_SHIFT                                       10
4806     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL15                                              (0x1<<11) // Flow Control Protocol Error Status detected in function 15. If set, hw generates pcie_err_attn output.
4807     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_FC_PRTL15_SHIFT                                        11
4808     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT15                                          (0x1<<12) // Completer Timeout Status detected in function 15. If set, hw generates pcie_err_attn output.
4809     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_CPL_TIMEOUT15_SHIFT                                    12
4810     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT15                                          (0x1<<13) // Receive UR Status detectedin function 15. If set, hw generates pcie_err_attn output.
4811     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MASTER_ABRT15_SHIFT                                    13
4812     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL15                                            (0x1<<14) // Unexpected Completion Status detected in function 15. If set, hw geneartes pcie_err_attn output.
4813     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNEXP_CPL15_SHIFT                                      14
4814     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW15                                             (0x1<<15) // Receiver Overflow Status detected in function 15. If set, hw generates pcie_err_attn output.
4815     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_RX_OFLOW15_SHIFT                                       15
4816     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP15                                             (0x1<<16) // Malformed TLP Status detected in function 15. If set, hw generates pcie_err_attn output.
4817     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_MALF_TLP15_SHIFT                                       16
4818     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC15                                                 (0x1<<17) // ECRC Error TLP Status detected in function 15. If set, hw generates pcie_err_attn output.
4819     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_ECRC15_SHIFT                                           17
4820     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT15                                             (0x1<<18) // Unsupported Request Error Status detected in function15. If set, hw generates pcie_err_attn output.
4821     #define PCIEIP_REG_TL_FUNC14TO15_STAT_ERR_UNSPPORT15_SHIFT                                       18
4822     #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT15                                     (0x1<<19) //
4823     #define PCIEIP_REG_TL_FUNC14TO15_STAT_PRI_SIG_TARGET_ABORT15_SHIFT                               19
4824     #define PCIEIP_REG_TL_FUNC14TO15_STAT_UNUSED_1                                                   (0xfff<<20) //
4825     #define PCIEIP_REG_TL_FUNC14TO15_STAT_UNUSED_1_SHIFT                                             20
4826 #define PCIEIP_REG_ORDER_RULE_CTRL_OFF                                                               0x0008b4UL //Access:RW   DataWidth:0x20  Order Rule Control Register.  Chips: K2
4827     #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_NP_PASS_P                                                 (0xff<<0) // Non-Posted Passing Posted Ordering Rule Control.   Determines if NP can pass halted P queue.  - 0 : NP can not pass P (recommended).  - 1 : NP can pass P
4828     #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_NP_PASS_P_SHIFT                                           0
4829     #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P                                                (0xff<<8) // Completion Passing Posted Ordering Rule Control.   Determines if CPL can pass halted P queue.  - 0: CPL can not pass P (recommended)  - 1: CPL can pass P
4830     #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_CPL_PASS_P_SHIFT                                          8
4831     #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_RSVDP_16                                                  (0xffff<<16) // Reserved for future use.
4832     #define PCIEIP_REG_ORDER_RULE_CTRL_OFF_RSVDP_16_SHIFT                                            16
4833 #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF                                                         0x0008b8UL //Access:RW   DataWidth:0x20  PIPE Loopback Control Register.  Chips: K2
4834     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID                                        (0xffff<<0) // LPBK_RXVALID is an internally reserved field. Do not use.  Note: This register field is sticky.
4835     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_LPBK_RXVALID_SHIFT                                  0
4836     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE                                       (0x3f<<16) // RXSTATUS_LANE is an internally reserved field. Do not use.  Note: This register field is sticky.
4837     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_LANE_SHIFT                                 16
4838     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22                                            (0x3<<22) // Reserved for future use.
4839     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_22_SHIFT                                      22
4840     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE                                      (0x7<<24) // RXSTATUS_VALUE is an internally reserved field. Do not use.
4841     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RXSTATUS_VALUE_SHIFT                                24
4842     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27                                            (0xf<<27) // Reserved for future use.
4843     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_RSVDP_27_SHIFT                                      27
4844     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK                                       (0x1<<31) // PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe.  Note: This register field is sticky.
4845     #define PCIEIP_REG_PIPE_LOOPBACK_CONTROL_OFF_PIPE_LOOPBACK_SHIFT                                 31
4846 #define PCIEIP_REG_MISC_CONTROL_1_OFF                                                                0x0008bcUL //Access:RW   DataWidth:0x20  DBI Read-Only Write Enable Register.  Chips: K2
4847     #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN                                               (0x1<<0) // Write to RO Registers Using DBI. When you set this field to "1", then some RO and HwInit bits are writable from the local application through the DBI. For more details, see "Writing to Read-Only Registers."  Note: This register field is sticky.
4848     #define PCIEIP_REG_MISC_CONTROL_1_OFF_DBI_RO_WR_EN_SHIFT                                         0
4849     #define PCIEIP_REG_MISC_CONTROL_1_OFF_DEFAULT_TARGET                                             (0x1<<1) // Default target a received UR/CA TLP is sent to. When you set this field to "1", a core received UR/CA TLP will be forwarded to target 1; when you set this field to "0", a core received UR/CA TLP will be forwarded to target 0.  Note: This register field is sticky.
4850     #define PCIEIP_REG_MISC_CONTROL_1_OFF_DEFAULT_TARGET_SHIFT                                       1
4851     #define PCIEIP_REG_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1                                         (0x1<<2) // Mask the UR/CA error reporting when the default target for UR/CA TLP is target1. When you set this field to "1", the error reporting for received UR/CA TLP will be masked.  Note: This register field is sticky.
4852     #define PCIEIP_REG_MISC_CONTROL_1_OFF_UR_CA_MASK_4_TRGT1_SHIFT                                   2
4853     #define PCIEIP_REG_MISC_CONTROL_1_OFF_RSVDP_3                                                    (0x1fffffff<<3) // Reserved for future use.
4854     #define PCIEIP_REG_MISC_CONTROL_1_OFF_RSVDP_3_SHIFT                                              3
4855 #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF                                                            0x0008c0UL //Access:RW   DataWidth:0x20  UpConfigure Multi-lane Control Register.  Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details, see the "Link Establishment" section in the Core Operations chapter of the Databook.  Chips: K2
4856     #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH                                      (0x3f<<0) // Target Link Width.  Values correspond to:  - 6'b000000: Core does not start upconfigure or autonomous width downsizing in the Configuration state.  - 6'b000001: x1  - 6'b000010: x2  - 6'b000100: x4  - 6'b001000: x8  - 6'b010000: x16  - 6'b100000: x32 This field is reserved (fixed to '0') for M-PCIe.
4857     #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_TARGET_LINK_WIDTH_SHIFT                                0
4858     #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE                               (0x1<<6) // Directed Link Width Change.  The core always moves to Configuration state through Recovery state when this bit is set to '1'.  - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in LINK_CONTROL_LINK_STATUS_REG is '0', the core starts upconfigure or autonomous width downsizing (to the TARGET_LINK_WIDTH value) in the Configuration state.  - If TARGET_LINK_WIDTH value is 0x0, the core does not start upconfigure or autonomous width downsizing in the Configuration state. The core self-clears this field when the core accepts this request.  This field is reserved (fixed to '0') for M-PCIe.
4859     #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_DIRECT_LINK_WIDTH_CHANGE_SHIFT                         6
4860     #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT                                    (0x1<<7) // Upconfigure Support.  The core sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state.  This field is reserved (fixed to '0') for M-PCIe.  Note: This register field is sticky.
4861     #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_UPCONFIGURE_SUPPORT_SHIFT                              7
4862     #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_RSVDP_8                                                (0xffffff<<8) // Reserved for future use.
4863     #define PCIEIP_REG_MULTI_LANE_CONTROL_OFF_RSVDP_8_SHIFT                                          8
4864 #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF                                                              0x0008c4UL //Access:RW   DataWidth:0x20  PHY Interoperability Control Register.   This register is reserved for internal use.  You should not write to this register and change the default unless specifically instructed by Synopsys support.  Chips: K2
4865     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL                                        (0x7f<<0) // Rxstandby Control. Bits 0..5 determine if the core asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake.  - [0]: Rx EIOS and subsequent T TX-IDLE-MIN  - [1]: Rate Change  - [2]: Inactive lane for upconfigure/downconfigure  - [3]: PowerDown=P1orP2  - [4]: RxL0s.Idle  - [5]: EI Infer in L0  - [6]: Execute RxStandby/RxStandbyStatus Handshake This field is reserved (fixed to '0') for M-PCIe.  Note: This register field is sticky.
4866     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RXSTANDBY_CONTROL_SHIFT                                  0
4867     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RSVDP_7                                                  (0x1<<7) // Reserved for future use.
4868     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RSVDP_7_SHIFT                                            7
4869     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_UNUSED_0                                                 (0x1<<8) // reserved
4870     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_UNUSED_0_SHIFT                                           8
4871     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1                                             (0x1<<9) // L1 entry control bit.  - 1: Core does not wait for PHY to acknowledge transition to P1 before entering L1.  - 0: Core waits for the PHY to acknowledge transition to P1 before entering L1. Note: The access attributes of this field are as follows:  - Dbi: R/W (sticky)  Note: This register field is sticky.
4872     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_L1_NOWAIT_P1_SHIFT                                       9
4873     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RSVDP_10                                                 (0x3fffff<<10) // Reserved for future use.
4874     #define PCIEIP_REG_PHY_INTEROP_CTRL_OFF_RSVDP_10_SHIFT                                           10
4875 #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF                                                     0x0008c8UL //Access:RW   DataWidth:0x20  TRGT_CPL_LUT Delete Entry Control register.   Using this register you can delete one entry in the target completion LUT.  Note:: The target completion LUT (and associated target completion timeout event) is watching for received application completions (on XALI0/1/2) corresponding to previously received non-posted requests from the PCIe wire.  Chips: K2
4876     #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID                                      (0x7fffffff<<0) // This number selects one entry to delete of the TRGT_CPL_LUT.
4877     #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_LOOK_UP_ID_SHIFT                                0
4878     #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN                                       (0x1<<31) // This is a one shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'.
4879     #define PCIEIP_REG_TRGT_CPL_LUT_DELETE_ENTRY_OFF_DELETE_EN_SHIFT                                 31
4880 #define PCIEIP_REG_PCIE_VERSION_NUMBER_OFF                                                           0x0008f8UL //Access:R    DataWidth:0x20  PCIe IIP release version nubmer.  Chips: K2
4881 #define PCIEIP_REG_PCIE_VERSION_TYPE_OFF                                                             0x0008fcUL //Access:R    DataWidth:0x20  PCIe IIP release version type.  Chips: K2
4882 #define PCIEIP_REG_TL_STATUS_0                                                                       0x000900UL //Access:R    DataWidth:0x20  Split completion table entry. For Debug.  Chips: BB_A0 BB_B0
4883     #define PCIEIP_REG_TL_STATUS_0_DEVICE_NO                                                         (0xf<<0) // Split table contents for tag0. this corresponds to Device_no[4:1] of PCIE header.
4884     #define PCIEIP_REG_TL_STATUS_0_DEVICE_NO_SHIFT                                                   0
4885     #define PCIEIP_REG_TL_STATUS_0_FUNC_NO                                                           (0x7<<4) // Split table contents for tag0. This is the Function number of the request made.
4886     #define PCIEIP_REG_TL_STATUS_0_FUNC_NO_SHIFT                                                     4
4887     #define PCIEIP_REG_TL_STATUS_0_TC                                                                (0x7<<7) // Split table contents for tag0. This is the Traffic class field.
4888     #define PCIEIP_REG_TL_STATUS_0_TC_SHIFT                                                          7
4889     #define PCIEIP_REG_TL_STATUS_0_ATTR                                                              (0x3<<10) // Split table Contents for tag0. This corresponds to attr field in PCIE header.
4890     #define PCIEIP_REG_TL_STATUS_0_ATTR_SHIFT                                                        10
4891     #define PCIEIP_REG_TL_STATUS_0_BYTE_COUNT                                                        (0x1fff<<12) // Split table contents for tag0. This corresponds to the Byte count field.
4892     #define PCIEIP_REG_TL_STATUS_0_BYTE_COUNT_SHIFT                                                  12
4893     #define PCIEIP_REG_TL_STATUS_0_LWR_ADDR                                                          (0x7f<<25) // Split table contents for tag0. This corresponds to the Lower address field.
4894     #define PCIEIP_REG_TL_STATUS_0_LWR_ADDR_SHIFT                                                    25
4895 #define PCIEIP_REG_TL_STATUS_1                                                                       0x000904UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 01.  Chips: BB_A0 BB_B0
4896 #define PCIEIP_REG_TL_STATUS_2                                                                       0x000908UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 02.  Chips: BB_A0 BB_B0
4897 #define PCIEIP_REG_TL_STATUS_3                                                                       0x00090cUL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 03.  Chips: BB_A0 BB_B0
4898 #define PCIEIP_REG_TL_STATUS_4                                                                       0x000910UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 04.  Chips: BB_A0 BB_B0
4899 #define PCIEIP_REG_TL_STATUS_5                                                                       0x000914UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 05.  Chips: BB_A0 BB_B0
4900 #define PCIEIP_REG_TL_STATUS_6                                                                       0x000918UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 06.  Chips: BB_A0 BB_B0
4901 #define PCIEIP_REG_TL_STATUS_7                                                                       0x00091cUL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 07.  Chips: BB_A0 BB_B0
4902 #define PCIEIP_REG_TL_STATUS_8                                                                       0x000920UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 08.  Chips: BB_A0 BB_B0
4903 #define PCIEIP_REG_TL_STATUS_9                                                                       0x000924UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 09.  Chips: BB_A0 BB_B0
4904 #define PCIEIP_REG_TL_STATUS_10                                                                      0x000928UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 10.  Chips: BB_A0 BB_B0
4905 #define PCIEIP_REG_TL_STATUS_11                                                                      0x00092cUL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 11.  Chips: BB_A0 BB_B0
4906 #define PCIEIP_REG_TL_STATUS_12                                                                      0x000930UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 12.  Chips: BB_A0 BB_B0
4907 #define PCIEIP_REG_TL_STATUS_13                                                                      0x000934UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 13.  Chips: BB_A0 BB_B0
4908 #define PCIEIP_REG_TL_STATUS_14                                                                      0x000938UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 14.  Chips: BB_A0 BB_B0
4909 #define PCIEIP_REG_TL_STATUS_15                                                                      0x00093cUL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 15.  Chips: BB_A0 BB_B0
4910 #define PCIEIP_REG_TL_STATUS_16                                                                      0x000940UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 16.  Chips: BB_A0 BB_B0
4911 #define PCIEIP_REG_TL_STATUS_17                                                                      0x000944UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 17.  Chips: BB_A0 BB_B0
4912 #define PCIEIP_REG_TL_STATUS_18                                                                      0x000948UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 18.  Chips: BB_A0 BB_B0
4913 #define PCIEIP_REG_TL_STATUS_19                                                                      0x00094cUL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 19.  Chips: BB_A0 BB_B0
4914 #define PCIEIP_REG_TL_STATUS_20                                                                      0x000950UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 20.  Chips: BB_A0 BB_B0
4915 #define PCIEIP_REG_TL_STATUS_21                                                                      0x000954UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 21.  Chips: BB_A0 BB_B0
4916 #define PCIEIP_REG_TL_STATUS_22                                                                      0x000958UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 22.  Chips: BB_A0 BB_B0
4917 #define PCIEIP_REG_TL_STATUS_23                                                                      0x00095cUL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 23.  Chips: BB_A0 BB_B0
4918 #define PCIEIP_REG_TL_STATUS_24                                                                      0x000960UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 24.  Chips: BB_A0 BB_B0
4919 #define PCIEIP_REG_TL_STATUS_25                                                                      0x000964UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 25.  Chips: BB_A0 BB_B0
4920 #define PCIEIP_REG_TL_STATUS_26                                                                      0x000968UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 26.  Chips: BB_A0 BB_B0
4921 #define PCIEIP_REG_TL_STATUS_27                                                                      0x00096cUL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 27.  Chips: BB_A0 BB_B0
4922 #define PCIEIP_REG_TL_STATUS_28                                                                      0x000970UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 28.  Chips: BB_A0 BB_B0
4923 #define PCIEIP_REG_TL_STATUS_29                                                                      0x000974UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 29.  Chips: BB_A0 BB_B0
4924 #define PCIEIP_REG_TL_STATUS_30                                                                      0x000978UL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 30.  Chips: BB_A0 BB_B0
4925 #define PCIEIP_REG_TL_STATUS_31                                                                      0x00097cUL //Access:R    DataWidth:0x20  This register is same as tl_status_0, except that it corresponds to split completion table entry for tag 31.  Chips: BB_A0 BB_B0
4926 #define PCIEIP_REG_TL_HDR_FC_ST                                                                      0x000980UL //Access:R    DataWidth:0x20  Header Flow Control. For Debug.  Chips: BB_A0 BB_B0
4927     #define PCIEIP_REG_TL_HDR_FC_ST_NPH_AVAIL                                                        (0xff<<0) // Non Posted Header credits available.
4928     #define PCIEIP_REG_TL_HDR_FC_ST_NPH_AVAIL_SHIFT                                                  0
4929     #define PCIEIP_REG_TL_HDR_FC_ST_PH_AVAIL                                                         (0xff<<8) // Posted Header Credits Available.
4930     #define PCIEIP_REG_TL_HDR_FC_ST_PH_AVAIL_SHIFT                                                   8
4931     #define PCIEIP_REG_TL_HDR_FC_ST_CPLH_AVAIL                                                       (0xff<<16) // Completion Header credits available.
4932     #define PCIEIP_REG_TL_HDR_FC_ST_CPLH_AVAIL_SHIFT                                                 16
4933     #define PCIEIP_REG_TL_HDR_FC_ST_NPD_AVAIL_7_0                                                    (0xff<<24) // Non-Posted Data credits available: bit[7:0].
4934     #define PCIEIP_REG_TL_HDR_FC_ST_NPD_AVAIL_7_0_SHIFT                                              24
4935 #define PCIEIP_REG_TL_DAT_FC_ST                                                                      0x000984UL //Access:R    DataWidth:0x20  Data Flow Control. For Debug.  Chips: BB_A0 BB_B0
4936     #define PCIEIP_REG_TL_DAT_FC_ST_PD_AVAIL                                                         (0xfff<<0) // Posted Data credits available.
4937     #define PCIEIP_REG_TL_DAT_FC_ST_PD_AVAIL_SHIFT                                                   0
4938     #define PCIEIP_REG_TL_DAT_FC_ST_UNUSED0                                                          (0xf<<12) //
4939     #define PCIEIP_REG_TL_DAT_FC_ST_UNUSED0_SHIFT                                                    12
4940     #define PCIEIP_REG_TL_DAT_FC_ST_CPLD_AVAIL                                                       (0xfff<<16) // Completion Data credits available.
4941     #define PCIEIP_REG_TL_DAT_FC_ST_CPLD_AVAIL_SHIFT                                                 16
4942     #define PCIEIP_REG_TL_DAT_FC_ST_NPD_AVAIL_11_8                                                   (0xf<<28) // Non-Posted Data credits available: bit[11:8].
4943     #define PCIEIP_REG_TL_DAT_FC_ST_NPD_AVAIL_11_8_SHIFT                                             28
4944 #define PCIEIP_REG_TL_HDR_FCCON_ST                                                                   0x000988UL //Access:R    DataWidth:0x20  Header Flow Control. For Debug.  Chips: BB_A0 BB_B0
4945     #define PCIEIP_REG_TL_HDR_FCCON_ST_NPH_CC                                                        (0xff<<0) // Non Posted Header credits consumed.
4946     #define PCIEIP_REG_TL_HDR_FCCON_ST_NPH_CC_SHIFT                                                  0
4947     #define PCIEIP_REG_TL_HDR_FCCON_ST_PH_CC                                                         (0xff<<8) // Posted Header Credits consumed.
4948     #define PCIEIP_REG_TL_HDR_FCCON_ST_PH_CC_SHIFT                                                   8
4949     #define PCIEIP_REG_TL_HDR_FCCON_ST_CPLH_CC                                                       (0xff<<16) // Completion Header credits consumed.
4950     #define PCIEIP_REG_TL_HDR_FCCON_ST_CPLH_CC_SHIFT                                                 16
4951     #define PCIEIP_REG_TL_HDR_FCCON_ST_NPD_CC_7_0                                                    (0xff<<24) // Non-Posted Data credits consumed: bit[7:0].
4952     #define PCIEIP_REG_TL_HDR_FCCON_ST_NPD_CC_7_0_SHIFT                                              24
4953 #define PCIEIP_REG_TL_DAT_FCCON_ST                                                                   0x00098cUL //Access:R    DataWidth:0x20  Data Flow Control. For Debug.  Chips: BB_A0 BB_B0
4954     #define PCIEIP_REG_TL_DAT_FCCON_ST_PD_CC                                                         (0xfff<<0) // Posted Data credits consumed.
4955     #define PCIEIP_REG_TL_DAT_FCCON_ST_PD_CC_SHIFT                                                   0
4956     #define PCIEIP_REG_TL_DAT_FCCON_ST_UNUSED0                                                       (0xf<<12) //
4957     #define PCIEIP_REG_TL_DAT_FCCON_ST_UNUSED0_SHIFT                                                 12
4958     #define PCIEIP_REG_TL_DAT_FCCON_ST_CPLD_CC                                                       (0xfff<<16) // Completion Data credits consumed.
4959     #define PCIEIP_REG_TL_DAT_FCCON_ST_CPLD_CC_SHIFT                                                 16
4960     #define PCIEIP_REG_TL_DAT_FCCON_ST_NPD_CC_11_8                                                   (0xf<<28) // Non-Posted Data credits consumed: bit[11:8].
4961     #define PCIEIP_REG_TL_DAT_FCCON_ST_NPD_CC_11_8_SHIFT                                             28
4962 #define PCIEIP_REG_TL_TGT_CRDT_ST                                                                    0x000990UL //Access:R    DataWidth:0x20  Target Flow Control. For Debug.  Chips: BB_A0 BB_B0
4963     #define PCIEIP_REG_TL_TGT_CRDT_ST_PH_CRDT_CNTR                                                   (0x7f<<0) // Available Posted header credits for target writes.
4964     #define PCIEIP_REG_TL_TGT_CRDT_ST_PH_CRDT_CNTR_SHIFT                                             0
4965     #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED0                                                        (0x1<<7) //
4966     #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED0_SHIFT                                                  7
4967     #define PCIEIP_REG_TL_TGT_CRDT_ST_PD_CRDT_CNTR                                                   (0x7f<<8) // Available Posted data credits for target writes.
4968     #define PCIEIP_REG_TL_TGT_CRDT_ST_PD_CRDT_CNTR_SHIFT                                             8
4969     #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED1                                                        (0x1<<15) //
4970     #define PCIEIP_REG_TL_TGT_CRDT_ST_UNUSED1_SHIFT                                                  15
4971     #define PCIEIP_REG_TL_TGT_CRDT_ST_NP_CRDT_CNTR                                                   (0x1<<16) // Available Non-posted credit for target reads or config.
4972     #define PCIEIP_REG_TL_TGT_CRDT_ST_NP_CRDT_CNTR_SHIFT                                             16
4973 #define PCIEIP_REG_TL_CRDT_ALLOC_ST                                                                  0x000994UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
4974     #define PCIEIP_REG_TL_CRDT_ALLOC_ST_NPH_ALLOC                                                    (0xff<<0) // Non-Posted header credits allocated.
4975     #define PCIEIP_REG_TL_CRDT_ALLOC_ST_NPH_ALLOC_SHIFT                                              0
4976     #define PCIEIP_REG_TL_CRDT_ALLOC_ST_NPD_ALLOC                                                    (0xff<<8) // Non-Posted data credits allocated.
4977     #define PCIEIP_REG_TL_CRDT_ALLOC_ST_NPD_ALLOC_SHIFT                                              8
4978     #define PCIEIP_REG_TL_CRDT_ALLOC_ST_PH_ALLOC                                                     (0xff<<16) // Posted header credits allocated.
4979     #define PCIEIP_REG_TL_CRDT_ALLOC_ST_PH_ALLOC_SHIFT                                               16
4980     #define PCIEIP_REG_TL_CRDT_ALLOC_ST_PD_ALLOC                                                     (0xff<<24) // Posted Data credits allocated.
4981     #define PCIEIP_REG_TL_CRDT_ALLOC_ST_PD_ALLOC_SHIFT                                               24
4982 #define PCIEIP_REG_TL_SMLOGIC_ST                                                                     0x000998UL //Access:R    DataWidth:0x20  State machines in TL status for debug.  Chips: BB_A0 BB_B0
4983     #define PCIEIP_REG_TL_SMLOGIC_ST_NP_CURR_STATE                                                   (0xf<<0) // Target Non-Posted request State machine.
4984     #define PCIEIP_REG_TL_SMLOGIC_ST_NP_CURR_STATE_SHIFT                                             0
4985     #define PCIEIP_REG_TL_SMLOGIC_ST_PH_CURR_STATE                                                   (0xf<<4) // Target posted request state machine.
4986     #define PCIEIP_REG_TL_SMLOGIC_ST_PH_CURR_STATE_SHIFT                                             4
4987     #define PCIEIP_REG_TL_SMLOGIC_ST_CPL_CURR_STATE                                                  (0x3<<8) // CPL_CURR_STATE Read Completions State machine.
4988     #define PCIEIP_REG_TL_SMLOGIC_ST_CPL_CURR_STATE_SHIFT                                            8
4989     #define PCIEIP_REG_TL_SMLOGIC_ST_UNUSED0                                                         (0x3f<<10) //
4990     #define PCIEIP_REG_TL_SMLOGIC_ST_UNUSED0_SHIFT                                                   10
4991     #define PCIEIP_REG_TL_SMLOGIC_ST_TX_SM                                                           (0x7<<16) // Transmit State machine.
4992     #define PCIEIP_REG_TL_SMLOGIC_ST_TX_SM_SHIFT                                                     16
4993 #define PCIEIP_REG_TL_PM_DEBUG                                                                       0x00099cUL //Access:R    DataWidth:0x20  Different OBFF Related Debug Signals.  Chips: BB_A0 BB_B0
4994 #define PCIEIP_REG_TL_RST_DEBUG                                                                      0x0009a0UL //Access:R    DataWidth:0x20  Different Reset Related Debug Signals.  Chips: BB_A0 BB_B0
4995     #define PCIEIP_REG_TL_RST_DEBUG_AUX_DBG_SIGS_0                                                   (0x7ff<<0) //
4996     #define PCIEIP_REG_TL_RST_DEBUG_AUX_DBG_SIGS_0_SHIFT                                             0
4997     #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_MDIO_N                                        (0x1<<11) //
4998     #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_MDIO_N_SHIFT                                  11
4999     #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_UC_N                                          (0x1<<12) //
5000     #define PCIEIP_REG_TL_RST_DEBUG_PCIE_LNK_PHY_RESET_UC_N_SHIFT                                    12
5001     #define PCIEIP_REG_TL_RST_DEBUG_HARD_RST_CFG_B                                                   (0x1<<13) //
5002     #define PCIEIP_REG_TL_RST_DEBUG_HARD_RST_CFG_B_SHIFT                                             13
5003     #define PCIEIP_REG_TL_RST_DEBUG_PERST_CFG_B                                                      (0x1<<14) //
5004     #define PCIEIP_REG_TL_RST_DEBUG_PERST_CFG_B_SHIFT                                                14
5005     #define PCIEIP_REG_TL_RST_DEBUG_RESERVED                                                         (0x1<<15) //
5006     #define PCIEIP_REG_TL_RST_DEBUG_RESERVED_SHIFT                                                   15
5007     #define PCIEIP_REG_TL_RST_DEBUG_AUX_DBG_SIGS_1                                                   (0x7ff<<16) //
5008     #define PCIEIP_REG_TL_RST_DEBUG_AUX_DBG_SIGS_1_SHIFT                                             16
5009     #define PCIEIP_REG_TL_RST_DEBUG_RESERVED_1                                                       (0x1f<<27) //
5010     #define PCIEIP_REG_TL_RST_DEBUG_RESERVED_1_SHIFT                                                 27
5011 #define PCIEIP_REG_TL_IOV_VFCTL_0                                                                    0x000a04UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5012     #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_NEXTBUS                                                     (0x1<<0) // This bit when set enables the DUT to assume that VFs are residing on a bus number that is different than the one on which the PFs reside. When this bit is enabled, VF_offset is automatically set to be greater than 256. So VFs reside on the next bus number and PCIE IP will consume multiple bus numbers. In this case VFs are accessed using Cfg Type 1 Transactions. This bit should be set if ARI is not supported in the hierarchy.
5013     #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_NEXTBUS_SHIFT                                               0
5014     #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_OFFSET_VETO                                                 (0x1<<1) // This bit when set, prevents DUT from automatically setting VF offset to be greater than 256(when vf_nextbus, bit 0 is set). User would have to set the offset bit on their own in this case.
5015     #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_OFFSET_VETO_SHIFT                                           1
5016     #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_EN_BAR_ADJUST                                               (0x1<<2) // This bit when set, enables DUT to automatically adjust the VF BAR size based on the System Page Size programming. When system Page size is programmed to be greater than User Page Size, DUT will change the VF BAR size advertized to be the new Effective system Page Size.
5017     #define PCIEIP_REG_TL_IOV_VFCTL_0_VF_EN_BAR_ADJUST_SHIFT                                         2
5018 #define PCIEIP_REG_TL_FCIMM_NP_LIMIT                                                                 0x000a10UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5019     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NPD_IMM_LIMIT                                        (0xfff<<0) // The number of accumulated non-posted data credits since the last request for immediate update that are needed to force an immediate update. The default is 0 since infinite non-posted data credits are advertised.
5020     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NPD_IMM_LIMIT_SHIFT                                  0
5021     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NPH_IMM_LIMIT                                        (0xff<<12) // The number of accumulated non-posted header credits since the last request for immediate update that are needed to force an immediate update. The default is (NPH_INIT_CREDIT &gt;&gt; 1). A value of 0 means always force an update (if infinite credits are not advertised).
5022     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NPH_IMM_LIMIT_SHIFT                                  12
5023     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_IMMEDIATE                                     (0x1<<20) // When set, released non-posted credits are flagged for immediate update. When clear, the credits may or not be updated until one or more of the accumulated credit thresholds for non-posted header or non-posted data is reached. (If clear and infinite credits are advertised, the thresholds are not used to force immediate updates.)
5024     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_IMMEDIATE_SHIFT                               20
5025     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NP_USCNT                                             (0xf<<21) // The number of microseconds between the last update and the forced update if there are outstanding non-posted credits to update. The resolution on the timer is +/- 1 us.
5026     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_FC_NP_USCNT_SHIFT                                       21
5027     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_UPD_10US                                      (0x1<<25) // When set, outstanding non-posted credit updates are forwarded to the DLL as immediate updates after a given number of microseconds (see below) elapses since the last update. This is typically used with non-immediate (threshold-based) updates.
5028     #define PCIEIP_REG_TL_FCIMM_NP_LIMIT_REG_ENA_FC_NP_UPD_10US_SHIFT                                25
5029 #define PCIEIP_REG_TL_FCIMM_P_LIMIT                                                                  0x000a14UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5030     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_PD_IMM_LIMIT                                          (0xfff<<0) // The number of accumulated posted data credits since the last request for immediate update that are needed to force an immediate update. The default is (PD_INIT_CREDIT &gt;&gt; 1). A value of 0 means always force an update (if infinite credits are not advertised).
5031     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_PD_IMM_LIMIT_SHIFT                                    0
5032     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_PH_IMM_LIMIT                                          (0xff<<12) // The number of accumulated posted header credits since the last request for immediate update that are needed to force an immediate update. The default is (PH_INIT_CREDIT &gt;&gt; 1). A value of 0 means always force an update (if infinite credits are not advertised).
5033     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_PH_IMM_LIMIT_SHIFT                                    12
5034     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_IMMEDIATE                                       (0x1<<20) // When set, released posted credits are flagged for immediate update. When clear, the credits may or not be updated until one or more of the accumulated credit thresholds for posted header or posted data is reached. (If clear and infinite credits are advertised, the thresholds are not used to force immediate updates.)
5035     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_IMMEDIATE_SHIFT                                 20
5036     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_P_USCNT                                               (0xf<<21) // The number of microseconds between the last update and the forced update if there are outstanding posted credits to update. The resolution on the timer is +/- 1 us.
5037     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_FC_P_USCNT_SHIFT                                         21
5038     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_UPD_10US                                        (0x1<<25) // When set, outstanding posted credit updates are forwarded to the DLL as immediate updates after a given number of microseconds (see below) elapses since the last update. This is typically used with non-immediate (threshold-based) updates.
5039     #define PCIEIP_REG_TL_FCIMM_P_LIMIT_REG_ENA_FC_P_UPD_10US_SHIFT                                  25
5040 #define PCIEIP_REG_REG_CAPENA_FN0_MASK                                                               0x000a1cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5041     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_CAP_ENA_FN0_MASK                                          (0xf<<0) // Each bit, when set, indicates that the corresponding capability available in cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
5042     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_CAP_ENA_FN0_MASK_SHIFT                                    0
5043     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT_CAP_ENA_FN0_MASK                                      (0x3ff<<4) // Each bit, when set, indicates that the corresponding capability available in ext_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
5044     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT_CAP_ENA_FN0_MASK_SHIFT                                4
5045     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_RC_EXT_CAP_ENA_FN0_MASK                                   (0x3<<14) // Each bit, when set, indicates that the corresponding capability available in rc_ext_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
5046     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_RC_EXT_CAP_ENA_FN0_MASK_SHIFT                             14
5047     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT2_CAP_ENA_FN0_MASK                                     (0xf<<16) // Each bit, when set, indicates that the corresponding capability available in ext2_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
5048     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT2_CAP_ENA_FN0_MASK_SHIFT                               16
5049     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT3_CAP_ENA_FN0_MASK                                     (0xf<<20) // Each bit, when set, indicates that the corresponding capability available in ext3_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
5050     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_EXT3_CAP_ENA_FN0_MASK_SHIFT                               20
5051     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_UNUSED0                                                   (0x3<<24) //
5052     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_UNUSED0_SHIFT                                             24
5053     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_RC_EXT2_CAP_ENA_FN0_MASK                                  (0x1f<<26) // Each bit, when set, indicates that the corresponding capability available in rc_ext2_cap_ena is valid only for function 0 and the the corresponding capability for other physical functions are disabled.
5054     #define PCIEIP_REG_REG_CAPENA_FN0_MASK_RC_EXT2_CAP_ENA_FN0_MASK_SHIFT                            26
5055 #define PCIEIP_REG_VDM_CTL0                                                                          0x000a20UL //Access:RW   DataWidth:0x20  This register is present if PCIE_VDM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5056     #define PCIEIP_REG_VDM_CTL0_REG_VDM_LENGTH                                                       (0x3ff<<0) // Length in bytes to which VDM messages are restricted to
5057     #define PCIEIP_REG_VDM_CTL0_REG_VDM_LENGTH_SHIFT                                                 0
5058     #define PCIEIP_REG_VDM_CTL0_UNUSED0                                                              (0x3f<<10) //
5059     #define PCIEIP_REG_VDM_CTL0_UNUSED0_SHIFT                                                        10
5060     #define PCIEIP_REG_VDM_CTL0_REG_VDM_ENABLED                                                      (0x1<<16) // VDM is enabled when this bit is set. PCIe will pass VDM messgaes to user interface when this bit is enabled, else it will be silently dropped.
5061     #define PCIEIP_REG_VDM_CTL0_REG_VDM_ENABLED_SHIFT                                                16
5062 #define PCIEIP_REG_PTM_CTL0                                                                          0x000a24UL //Access:RW   DataWidth:0x20  This register is present if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5063     #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_START                                                    (0x1<<0) // This bit when set, forces hardware to generate a PTM Request message. Hardware automatically clears this bit, when the PTM response is received.
5064     #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_START_SHIFT                                              0
5065     #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_MASK                                                    (0x1<<1) // This field when set will prevent hardware from generating attention when PTM req- response handshake has completed.
5066     #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_MASK_SHIFT                                              1
5067     #define PCIEIP_REG_PTM_CTL0_UNUSED0                                                              (0xfffffff<<2) //
5068     #define PCIEIP_REG_PTM_CTL0_UNUSED0_SHIFT                                                        2
5069     #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_STAT                                                    (0x1<<30) // This field when set inidcates that the PTM req-response handshake initiated by software has completed. This bit is cleared by writing to it.
5070     #define PCIEIP_REG_PTM_CTL0_REG_PTM_ATTN_STAT_SHIFT                                              30
5071     #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_STATUS                                                   (0x1<<31) // This field when set inidcates that the PTM req-response handshake completed successfully. This field is valid only when bit 30 is set.
5072     #define PCIEIP_REG_PTM_CTL0_REG_PTM_REQ_STATUS_SHIFT                                             31
5073 #define PCIEIP_REG_PTM_PMSTR_HI                                                                      0x000a28UL //Access:R    DataWidth:0x20  This register is present if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5074 #define PCIEIP_REG_PTM_PMSTR_LO                                                                      0x000a2cUL //Access:R    DataWidth:0x20  This register is present if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5075 #define PCIEIP_REG_PTM_LOCAL_HI                                                                      0x000a30UL //Access:R    DataWidth:0x20  This register is present if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5076 #define PCIEIP_REG_PTM_LOCAL_LO                                                                      0x000a34UL //Access:R    DataWidth:0x20  This register is present if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5077 #define PCIEIP_REG_PTM_RES_LOCAL_HI                                                                  0x000a38UL //Access:R    DataWidth:0x20  This register is present if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5078 #define PCIEIP_REG_PTM_RES_LOCAL_LO                                                                  0x000a3cUL //Access:R    DataWidth:0x20  This register is present if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5079 #define PCIEIP_REG_PTM_MSTR_PROP_DLY                                                                 0x000a40UL //Access:R    DataWidth:0x20  This register is present if PCIE_PTM_SUPP is defined in version.v  Chips: BB_A0 BB_B0
5080 #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL                                                              0x000a50UL //Access:RW   DataWidth:0x20  Control register for tx tlp statistics  Chips: BB_A0 BB_B0
5081     #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_EN                                      (0x1<<0) // TLP Statistics Enable. Setting this bit to '1' enables the tx TLP statistics collection. Hardware will count various types of TLPs in the TX direction, as programmed in the reg_ttx_det_tlp_type register. When this bit is reset to '0', the counting stops and software can read the results. This bit is automatically cleared after the specified time if reg_ttx_tlp_stat_len is non-zero. All statistic read-back registers are cleared when this transitions from '0' to '1'.
5082     #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_EN_SHIFT                                0
5083     #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_UNUSED0                                                  (0x7f<<1) //
5084     #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_UNUSED0_SHIFT                                            1
5085     #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_LEN                                     (0xffffff<<8) // TLP Statistics Length. This field specifies the TLP statistics collection time in microseconds. When it is set to '0', software has to clear the reg_ttx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware automatically clears the enable bit after the specified time.
5086     #define PCIEIP_REG_PCIER_TL_STAT_TX_CTL_REG_TTX_TLP_STAT_LEN_SHIFT                               8
5087 #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE                                                             0x000a54UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5088     #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_0                                  (0xff<<0) // This register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[6:0] Bits[6:0] indicate TLP type. TLP type can be masked using reg_ttx_det_tlp_type_mask[6:0].
5089     #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_0_SHIFT                            0
5090     #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_1                                  (0xff<<8) // This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[14:8] Bits[14:8] indicate TLP type. TLP type can be masked using reg_ttx_det_tlp_type_mask[14:8].
5091     #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_1_SHIFT                            8
5092     #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_2                                  (0xff<<16) // This register contains Enable bit and the TLP type that hardware can detect. Bit[23] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[22:16] Bits[22:16] indicate TLP type. TLP type can be masked using reg_ttx_det_tlp_type_mask[22:16].
5093     #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_2_SHIFT                            16
5094     #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_3                                  (0xff<<24) // This register contains Enable bit and the TLP type that hardware can detect. Bit[31] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[30:24] Bits[30:24] indicate TLP type. TLP type can be masked using reg_ttx_det_tlp_type_mask[30:24].
5095     #define PCIEIP_REG_PCIER_TL_STAT_TX_TYPE_REG_TTX_DET_TLP_TYPE_3_SHIFT                            24
5096 #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK                                                             0x000a58UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5097     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_0                             (0x7f<<0) // This register contains the mask bits for reg_ttx_det_tlp_type_0. Bits[7:0] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_0 will be masked. Masking works only if Enable bit (bit [7] of reg_ttx_det_tlp_type_0) is true.
5098     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_0_SHIFT                       0
5099     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED0                                                 (0x1<<7) //
5100     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED0_SHIFT                                           7
5101     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_1                             (0x7f<<8) // This register contains the mask bits for reg_ttx_det_tlp_type_1. Bits[14:8] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_1 will be masked. Masking works only if Enable bit (bit [15] of reg_ttx_det_tlp_type_1) is true.
5102     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_1_SHIFT                       8
5103     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED1                                                 (0x1<<15) //
5104     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED1_SHIFT                                           15
5105     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_2                             (0x7f<<16) // This register contains the mask bits for reg_ttx_det_tlp_type_2. Bits[22:16] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_2 will be masked. Masking works only if Enable bit (bit [7] of reg_ttx_det_tlp_type_2) is true.
5106     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_2_SHIFT                       16
5107     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED2                                                 (0x1<<23) //
5108     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_UNUSED2_SHIFT                                           23
5109     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_3                             (0x7f<<24) // This register contains the mask bits for reg_ttx_det_tlp_type_3. Bits[30:24] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_ttx_det_tlp_type_3 will be masked. Masking works only if Enable bit (bit [7] of reg_ttx_det_tlp_type_3) is true.
5110     #define PCIEIP_REG_PCIER_TL_STAT_TX_MASK_REG_TTX_DET_TLP_TYPE_MASK_3_SHIFT                       24
5111 #define PCIEIP_REG_PCIER_TL_STAT_TX_CTR_LO                                                           0x000a5cUL //Access:R    DataWidth:0x20  TX TLP Statistics Low 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_ttx_tlp_stat_en goes from '0' to '1'.  Chips: BB_A0 BB_B0
5112 #define PCIEIP_REG_PCIER_TL_STAT_TX_CTR_HI                                                           0x000a60UL //Access:R    DataWidth:0x20  TX TLP Statistics High 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_ttx_tlp_stat_en goes from '0' to '1'.  Chips: BB_A0 BB_B0
5113 #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL                                                              0x000a64UL //Access:RW   DataWidth:0x20  Control register for rx tlp statistics  Chips: BB_A0 BB_B0
5114     #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_EN                                      (0x1<<0) // TLP Statistics Enable. Setting this bit to '1' enables the rx TLP statistics collection. Hardware will count various types of TLPs programmed in the reg_trx_det_tlp_type register in RX direction. When this bit is reset to '0', the counting stops and software can read the results. This bit is automatically cleared after the specified time if reg_trx_tlp_stat_len is non-zero. All statistic read-back registers are cleared when this transitions from '0' to '1'.
5115     #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_EN_SHIFT                                0
5116     #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_UNUSED0                                                  (0x7f<<1) //
5117     #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_UNUSED0_SHIFT                                            1
5118     #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_LEN                                     (0xffffff<<8) // TLP Statistics Length. This field specifies the TLP statistics collection time in microseconds. When it is set to '0', software has to clear the reg_trx_tlp_stat_en bit to stop the operation. When it is set to a non-zero value, hardware automatically clears the enable bit after the specified time.
5119     #define PCIEIP_REG_PCIER_TL_STAT_RX_CTL_REG_TRX_TLP_STAT_LEN_SHIFT                               8
5120 #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE                                                             0x000a68UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5121     #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_0                                  (0xff<<0) // This register contains Enable bit and the TLP type that hardware can detect. Bit[7] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[6:0] Bits[6:0] indicate TLP type. TLP type can be masked using reg_trx_det_tlp_type_mask[6:0].
5122     #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_0_SHIFT                            0
5123     #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_1                                  (0xff<<8) // This register contains Enable bit and the TLP type that hardware can detect. Bit[15] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[14:8] Bits[14:8] indicate TLP type. TLP type can be masked using reg_trx_det_tlp_type_mask[14:8].
5124     #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_1_SHIFT                            8
5125     #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_2                                  (0xff<<16) // This register contains Enable bit and the TLP type that hardware can detect. Bit[23] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[22:16] Bits[22:16] indicate TLP type. TLP type can be masked using reg_trx_det_tlp_type_mask[22:16].
5126     #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_2_SHIFT                            16
5127     #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_3                                  (0xff<<24) // This register contains Enable bit and the TLP type that hardware can detect. Bit[31] is enable bit. If this bit is set to 1, then hardware will detect the TLP type indicated by bits[30:24] Bits[30:24] indicate TLP type. TLP type can be masked using reg_trx_det_tlp_type_mask[30:24].
5128     #define PCIEIP_REG_PCIER_TL_STAT_RX_TYPE_REG_TRX_DET_TLP_TYPE_3_SHIFT                            24
5129 #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK                                                             0x000a6cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5130     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_0                             (0x7f<<0) // This register contains the mask bits for reg_trx_det_tlp_type_0. Bits[7:0] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_0 will be masked. Masking works only if Enable bit (bit [7] of reg_trx_det_tlp_type_0) is true.
5131     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_0_SHIFT                       0
5132     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED0                                                 (0x1<<7) //
5133     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED0_SHIFT                                           7
5134     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_1                             (0x7f<<8) // This register contains the mask bits for reg_trx_det_tlp_type_1. Bits[14:8] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_1 will be masked. Masking works only if Enable bit (bit [15] of reg_trx_det_tlp_type_1) is true.
5135     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_1_SHIFT                       8
5136     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED1                                                 (0x1<<15) //
5137     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED1_SHIFT                                           15
5138     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_2                             (0x7f<<16) // This register contains the mask bits for reg_trx_det_tlp_type_2. Bits[22:16] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_2 will be masked. Masking works only if Enable bit (bit [7] of reg_trx_det_tlp_type_2) is true.
5139     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_2_SHIFT                       16
5140     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED2                                                 (0x1<<23) //
5141     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_UNUSED2_SHIFT                                           23
5142     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_3                             (0x7f<<24) // This register contains the mask bits for reg_trx_det_tlp_type_3. Bits[30:24] are the mask bits. Default value is 0. If a bit is set to 1 then corresponding bit of reg_trx_det_tlp_type_3 will be masked. Masking works only if Enable bit (bit [7] of reg_trx_det_tlp_type_3) is true.
5143     #define PCIEIP_REG_PCIER_TL_STAT_RX_MASK_REG_TRX_DET_TLP_TYPE_MASK_3_SHIFT                       24
5144 #define PCIEIP_REG_PCIER_TL_STAT_RX_CTR_LO                                                           0x000a70UL //Access:R    DataWidth:0x20  RX TLP Statistics Low 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'.  Chips: BB_A0 BB_B0
5145 #define PCIEIP_REG_PCIER_TL_STAT_RX_CTR_HI                                                           0x000a74UL //Access:R    DataWidth:0x20  RX TLP Statistics High 32 bits. This register indicates the number of TLPs that have been trasmitted. It is cleared when reg_trx_tlp_stat_en goes from '0' to '1'.  Chips: BB_A0 BB_B0
5146 #define PCIEIP_REG_PL_LTR_LATENCY_OFF                                                                0x000b30UL //Access:RW   DataWidth:0x20  LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port, the register fields capture the corresponding fields in the LTR messages that are transmitted by the port. For a downstream port, the register fields capture the corresponding fields in the LTR messages that are received by the port. The full content of the register is reflected on the app_ltr_latency[31:0] output.  Chips: K2
5147     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE                                        (0x3ff<<0) // Snoop Latency Value.  Note: The access attributes of this field are as follows:  - Dbi: R/W
5148     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_VALUE_SHIFT                                  0
5149     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE                                        (0x7<<10) // Snoop Latency Scale.  Note: The access attributes of this field are as follows:  - Dbi: R/W
5150     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_SCALE_SHIFT                                  10
5151     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_RSVDP_13                                                   (0x3<<13) // Reserved for future use.
5152     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_RSVDP_13_SHIFT                                             13
5153     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE                                      (0x1<<15) // Snoop Latency Requirement.  Note: The access attributes of this field are as follows:  - Dbi: R/W
5154     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_SNOOP_LATENCY_REQUIRE_SHIFT                                15
5155     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE                                     (0x3ff<<16) // No Snoop Latency Value.  Note: The access attributes of this field are as follows:  - Dbi: R/W
5156     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_VALUE_SHIFT                               16
5157     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE                                     (0x7<<26) // No Snoop Latency Scale.  Note: The access attributes of this field are as follows:  - Dbi: R/W
5158     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_SCALE_SHIFT                               26
5159     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_RSVDP_29                                                   (0x3<<29) // Reserved for future use.
5160     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_RSVDP_29_SHIFT                                             29
5161     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE                                   (0x1<<31) // No Snoop Latency Requirement.  Note: The access attributes of this field are as follows:  - Dbi: R/W
5162     #define PCIEIP_REG_PL_LTR_LATENCY_OFF_NO_SNOOP_LATENCY_REQUIRE_SHIFT                             31
5163 #define PCIEIP_REG_AUX_CLK_FREQ_OFF                                                                  0x000b40UL //Access:RW   DataWidth:0x20  Auxiliary Clock Frequency Control Register.  Chips: K2
5164     #define PCIEIP_REG_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ                                                 (0x3ff<<0) // The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy in the time counted. If the actual frequency (f) of aux_clk does not exactly match the programmed frequency (f_prog), then there is an error in the time counted by the core that can be expressed in percentage as: err% = (f_prog/f-1)*100. For example if f=2.5 MHz and f_prog=3 MHz, then err% =(3/2.5-1)*100 =20%, meaning that the time counted by the core on aux_clk will be 20% greater than the time in us programmed in the corresponding time register (for example T_POWER_ON).  Note: This register field is sticky.
5165     #define PCIEIP_REG_AUX_CLK_FREQ_OFF_AUX_CLK_FREQ_SHIFT                                           0
5166     #define PCIEIP_REG_AUX_CLK_FREQ_OFF_RSVDP_10                                                     (0x3fffff<<10) // Reserved for future use.
5167     #define PCIEIP_REG_AUX_CLK_FREQ_OFF_RSVDP_10_SHIFT                                               10
5168 #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT                                                            0x000c00UL //Access:RW   DataWidth:0x20  Main status and control register for the PL DL Debug FIFO. Trigger and status shown in this register. For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the DBG FIFO has collected all needed data.  Chips: BB_A0 BB_B0
5169     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_PRETRIG_CNT                                   (0xff<<0) // When non-zero, indicates the maximum number of entries collected and saved prior to the trigger.
5170     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_PRETRIG_CNT_SHIFT                             0
5171     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_RD_CTRL_CSRD_USER_B                               (0x1<<8) // When cleared, indicates that the DBG FIFO is read by user interface. When set, indicates that the DBG FIFO is read by CS registers only.
5172     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_RD_CTRL_CSRD_USER_B_SHIFT                         8
5173     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIG_ADDR                                     (0x1ff<<9) // When DBG FIFO is triggered, this indicates the FIFO address of the trigger location (where data corresponding to the trigger cycle is collected). Bit 17 is a wrap condition in the FIFO
5174     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIG_ADDR_SHIFT                               9
5175     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_RADDR                                         (0xff<<18) // Current dbg fifo read pointer on write side.
5176     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_RADDR_SHIFT                                   18
5177     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN_ST                                       (0x1<<26) // Asserted when attn signal is generated and active. Write 1 to clear the attn.
5178     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN_ST_SHIFT                                 26
5179     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN                                          (0x1<<27) // Enables to generate attention to trigger external logic analyzers.
5180     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ATTN_SHIFT                                    27
5181     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_RESERVED_28                                            (0x1<<28) //
5182     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_RESERVED_28_SHIFT                                      28
5183     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_PRETRIG_FULL                                      (0x1<<29) // Indicates that DBG FIFO has filled the pretrigger buffer before the trigger occurred. If the trigger occurs before the pretrigger buffer is filled, the trig_addr field is used to determine the amount of pre-trigger data collected
5184     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_FIFO_PRETRIG_FULL_SHIFT                                29
5185     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIGGERED                                     (0x1<<30) // Indicates that the DBG FIFO is triggered.
5186     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_TRIGGERED_SHIFT                               30
5187     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ACTIVE                                        (0x1<<31) // When set by write, activates the DBG FIFO logic. To retrigger, this must be cleared then set again.  When read, this indicates that the DBG FIFO is active (waiting for a trigger).
5188     #define PCIEIP_REG_PCIER_DBG_FIFO_CTLSTAT_DBG_FIFO_ACTIVE_SHIFT                                  31
5189 #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT                                                        0x000c04UL //Access:RW   DataWidth:0x20  Control and Status for accesses to DBG FIFO indirect registers.  Chips: BB_A0 BB_B0
5190     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_REG                                      (0x1ff<<0) // The indirect write address register.
5191     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_REG_SHIFT                                0
5192     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_AUTOINC                                  (0x1<<9) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
5193     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_WADDR_AUTOINC_SHIFT                            9
5194     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_REG                                      (0x1ff<<10) // The indirect read address register.
5195     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_REG_SHIFT                                10
5196     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_AUTOINC                                  (0x1<<19) // When set, the indirect read address register is incremented on reads.
5197     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_RADDR_AUTOINC_SHIFT                            19
5198     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_NO_RADDR                                       (0x1<<20) // When set, the indirect write address register is used for indirect reads as well.
5199     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_IND_NO_RADDR_SHIFT                                 20
5200     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_RESERVED_22                                        (0x3<<21) //
5201     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_RESERVED_22_SHIFT                                  21
5202     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_DBG_FIFO_WADDR                                     (0x1ff<<23) // Current write address to the external FIFO. Bit 31 is a wrap condition in the FIFO
5203     #define PCIEIP_REG_PCIER_DBG_FIFO_IND_CTLSTAT_DBG_FIFO_WADDR_SHIFT                               23
5204 #define PCIEIP_REG_PCIER_DBG_FIFO_IND_DATA                                                           0x000c08UL //Access:RW   DataWidth:0x20  Access to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. The registers are:  Register 0 :: IND_PCIE_DBG_TRIG0_0TO1_MASK - mask bits [319:0] for 0to1 trigger0 Register 10 :: IND_PCIE_DBG_TRIG0_1TO0_MASK - mask bits [319:0] for 1to0 trigger0 Register 20 :: IND_PCIE_DBG_TRIG0_MATCH_MASK - mask bits [319:0] for match trigger0 Register 30 :: IND_PCIE_DBG_TRIG0_MATCH_VALUE - match value bits[319:0] for trigger0  Register 40 :: IND_PCIE_DBG_TRIG0_DATA_SELECT - [127:0] Trigger0 signals each group is selected with 8 bits among the 256 32 bit signals Register 50 :: IND_PCIE_DBG_TRIG1_0TO1_MASK - mask bits [319:0] for 0to1 trigger1 Register 60 :: IND_PCIE_DBG_TRIG1_1TO0_MASK - mask bits [319:0] for 1to0 trigger1 Register 70 :: IND_PCIE_DBG_TRIG1_MATCH_MASK - mask bits [319:0] for match trigger1 Register 80 :: IND_PCIE_DBG_TRIG1_MATCH_VALUE - match value bits[319:0] for trigger1  Register 90 :: IND_PCIE_DBG_TRIG1_DATA_SELECT - [127:0] Trigger1 signals each group is selected with 8 bits among the 256 32 bit signals Register 100 :: IND_PCIE_DBG_TRIG2_0TO1_MASK - mask bits [319:0] for 0to1 trigger2 Register 110 :: IND_PCIE_DBG_TRIG2_1TO0_MASK - mask bits [319:0] for 1to0 trigger2 Register 120 :: IND_PCIE_DBG_TRIG2_MATCH_MASK - mask bits [319:0] for match trigger2 Register 130 :: IND_PCIE_DBG_TRIG2_MATCH_VALUE - match value bits[319:0] for trigger2  Register 140 :: IND_PCIE_DBG_TRIG2_DATA_SELECT - [127:0] Trigger2 signals each group is selected with 8 bits among the 256 32 bit signals Register 150 :: IND_PCIE_DBG_TRIG_SELECT - Trigger condition selecta Register 151 :: IND_PCIE_DBG_TRIG_TIMEOUT - Timeout select for Trigger sm Register 160 :: IND_PCIE_DBG_FILTER_0TO1_MASK - mask bits [319:0] for 0to1 data filtering Register 170 :: IND_PCIE_DBG_FILTER_1TO0_MASK - mask bits [319:0] for 1to0 data filtering Register 180 :: IND_PCIE_DBG_FILTER_MATCH0_MASK - mask bits [319:0] for match0 data filtering Register 190 :: IND_PCIE_DBG_FILTER_MATCH0_VALUE - match0 value bits[319:0] for data filtering Register 200 :: IND_PCIE_DBG_FILTER_MATCH1_MASK - mask bits [319:0] for match1 data filtering Register 210 :: IND_PCIE_DBG_FILTER_MATCH1_VALUE - match1 value bits[319:0] for data filtering Register 220 :: IND_PCIE_DBG_FILTER_SELECT - select the advanced filtering mechanism Register 228 :: IND_PCIE_DBG_ATTN_CTRL - Controls the attention generating state machine Register 229 :: IND_PCIE_DBG_ATTN_SELECT - Select which attention to go out Register 230 :: IND_PCIE_DBG_ATTN_0TO1_MASK - mask bits [319:0] for 0to1 attention signal group Register 240 :: IND_PCIE_DBG_ATTN_1TO0_MASK - mask bits [319:0] for 1to0 attention signal group Register 250 :: IND_PCIE_DBG_ATTN_MATCH_MASK - mask bits [319:0] for match attention signal group Register 260 :: IND_PCIE_DBG_ATTN_MATCH_VALUE - match value bits [319:0] for attention signal group Register 270 :: IND_PCIE_DBG_FIFO_DATA_SELECT - bits [127:0] selects the group of signals to store in the fifo each group is selected with 8 bits among the 256 32 bit signals Register 274 :: IND_PCIE_DBG_FIFO_TIME_SELECT - not used in debug fifo mode  Register 275 :: IND_DBG_FIFO_EVENT_SELECT - select which events to count for each of the two event counters. In addition, either level or rising edge sensitivity is selectable Register 276 :: IND_DBG_FIFO_EVENT_CFG0 - event config0 Register 277 :: IND_DBG_FIFO_EVENT_CFG1 - event config1  If accessing an unimplemented register, the value 0xbadaddee will be returned.  Chips: BB_A0 BB_B0
5205 #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL                                                            0x000c0cUL //Access:RW   DataWidth:0x20  Debug Control for PL DL DEBUG FIFO  Chips: BB_A0 BB_B0
5206     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_TRIGSM                                                 (0xf<<0) // Debug fifo trigger state machine status
5207     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_TRIGSM_SHIFT                                           0
5208     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_TRIGGER_OUT                                            (0x7<<4) // Trigger_out[2:0] status
5209     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_TRIGGER_OUT_SHIFT                                      4
5210     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_7                                             (0x1<<7) //
5211     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_7_SHIFT                                       7
5212     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_ATTNSM                                                 (0x3<<8) // Debug fifo attn state machine status
5213     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_ATTNSM_SHIFT                                           8
5214     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_DBG_FIFO_ATTN                                          (0x1<<10) // Debug fifo attn signal status
5215     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_DBG_FIFO_ATTN_SHIFT                                    10
5216     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_23                                            (0x1fff<<11) //
5217     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RESERVED_23_SHIFT                                      11
5218     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_CTRL_ATTN                                      (0x1<<24) // When set, asserts attn signal irrespective of attnsm state
5219     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_CTRL_ATTN_SHIFT                                24
5220     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_25                                    (0x1<<25) // When set, resets user side interface for tlda2 fifo
5221     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_25_SHIFT                              25
5222     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_26                                    (0x1<<26) // When set, resets user side interface for tlda fifo
5223     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_26_SHIFT                              26
5224     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_27                                    (0x1<<27) // When set, resets user side interface for dbg fifo
5225     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_RD_SIDE_SOFT_RST_27_SHIFT                              27
5226     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_28                                    (0x1<<28) // When set, clears the debug fifo active also enables user side flush for debug fifo
5227     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_28_SHIFT                              28
5228     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_29                                    (0x1<<29) // When set, activates debug fifo
5229     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_29_SHIFT                              29
5230     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_30                                    (0x1<<30) // When set, resets notrig_cnt and trigsm
5231     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_30_SHIFT                              30
5232     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_31                                    (0x1<<31) // When set, dbg_fifo_triggered will get asserted irrespective of trigsm state
5233     #define PCIEIP_REG_PCIER_DBG_FIFO_DBG_CTL_REG_DBG_FIFO_CTL_31_SHIFT                              31
5234 #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL                                                           0x000c10UL //Access:RW   DataWidth:0x20  Control for TL PL/DL debug FIFO's  Chips: BB_A0 BB_B0
5235     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_USER_RD_FIFO_SEL                                      (0x7<<0) // 000 - no FIFO selected to read by user if  001 - PL/DL FIFO is selected to read by user if  010 - TLDA-0 FIFO is selected to read by user if  100 - TLDA-1 FIFO is selected to read by user if  All other encodings are reserved and un-expected results would come if selected.
5236     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_USER_RD_FIFO_SEL_SHIFT                                0
5237     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_UNUSED0                                               (0x1ff<<3) //
5238     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_UNUSED0_SHIFT                                         3
5239     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_DBG_FIFO_SEL                                          (0x7<<12) // 000 - generic lane is selected  001 - predefined lane 1  010 - predefined lane 2  .  .  .  111 - Serdes data seleted
5240     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_DBG_FIFO_SEL_SHIFT                                    12
5241     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_15                                           (0x1<<15) //
5242     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_15_SHIFT                                     15
5243     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_TLDA_FIFO_MUX_SEL                                     (0xf<<16) // TLDA mux will be selected
5244     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_TLDA_FIFO_MUX_SEL_SHIFT                               16
5245     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_TLDA_FIFO2_MUX_SEL                                    (0xf<<20) // TLDA2 mux will be selected
5246     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_TLDA_FIFO2_MUX_SEL_SHIFT                              20
5247     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_31                                           (0xff<<24) //
5248     #define PCIEIP_REG_PCIER_TLPL_DBG_FIFO_CTL_RESERVED_31_SHIFT                                     24
5249 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_9                                                               0x000c18UL //Access:R    DataWidth:0x20  The ten read registers give a total of 320 bits of data from the DBG FIFO. The DBG FIFO is read when PCIER_DBG_FIFO_RD_0 is read every time.  If the DBG FIFO location is not used, each register will read 0xFFFFFFFF.  Chips: BB_A0 BB_B0
5250 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_8                                                               0x000c1cUL //Access:R    DataWidth:0x20  Bits [287:256] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5251 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_7                                                               0x000c20UL //Access:R    DataWidth:0x20  Bits [255:224] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5252 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_6                                                               0x000c24UL //Access:R    DataWidth:0x20  Bits [223:192] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5253 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_5                                                               0x000c28UL //Access:R    DataWidth:0x20  Bits [191:160] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5254 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_4                                                               0x000c2cUL //Access:R    DataWidth:0x20  Bits [159:128] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5255 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_3                                                               0x000c30UL //Access:R    DataWidth:0x20  Bits [127:96] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5256 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_2                                                               0x000c34UL //Access:R    DataWidth:0x20  Bits [95:64] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5257 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_1                                                               0x000c38UL //Access:R    DataWidth:0x20  Bits [63:32] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5258 #define PCIEIP_REG_PCIER_DBG_FIFO_RD_0                                                               0x000c3cUL //Access:R    DataWidth:0x20  Bits [31:0] of the current DBG FIFO location  Chips: BB_A0 BB_B0
5259 #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT                                                               0x000c40UL //Access:RW   DataWidth:0x20  Main status and control register for the Transaction Layer Data Analyzer. Trigger and status shown in this register. If both of the above two bits are set, the results are undefined.  Chips: BB_A0 BB_B0
5260     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_TL_TLDAFIFO_RADDR                                         (0x7f<<0) // The current read address for the external FIFO
5261     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_TL_TLDAFIFO_RADDR_SHIFT                                   0
5262     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RADDR_DWSEL                                          (0x1<<7) // When set, indicates that the lower 160 bits from the current FIFO read address are in the RDFIFO registers.
5263     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RADDR_DWSEL_SHIFT                                    7
5264     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RDAUTOINC                                            (0x1<<8) // When set and in local mode, reads to PCIER_TLDA_RDFIFO_4 will automatically increment the read address.
5265     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_FIFO_RDAUTOINC_SHIFT                                      8
5266     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_SERIES                                               (0x1<<9) // When set, the FIFOs are linked in series to increase the depth of the FIFO.
5267     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_SERIES_SHIFT                                         9
5268     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_PARA                                                 (0x1<<10) // When set, the FIFOs are linked in parallel to increase the width of the FIFO.
5269     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LINK_PARA_SHIFT                                           10
5270     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UI_PRETRIG_ALL                                            (0x1<<11) // Valid only when reading FIFOs from the user interface. When set, all pretrigger data is considered valid and will be present on the interface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
5271     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UI_PRETRIG_ALL_SHIFT                                      11
5272     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UNUSED0                                                   (0x1<<12) //
5273     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_UNUSED0_SHIFT                                             12
5274     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_DATA_AT_TRIG                                              (0x1<<13) // When set after FIFO has triggered, indicates that data at the trigger has been collected (as opposed to filtered out based on indirect register settings).
5275     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_DATA_AT_TRIG_SHIFT                                        13
5276     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_MODE                                                (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read from the registers. When cleared, indicates that the FIFO is operating through reads from the user interface.
5277     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_MODE_SHIFT                                          14
5278     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_CNT                                               (0x7f<<15) // The number of pre-trigger samples to keep. pretrig_cnt[6] is only valid when if there are two TLDA blocks and they are linked serially (extending the FIFO depth).
5279     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_CNT_SHIFT                                         15
5280     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_TRIG_ADDR                                                 (0x7f<<22) // The FIFO write address at the time of the trigger. Use bit 13 of this register to determine if there was data collected at the time of the trigger.
5281     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_TRIG_ADDR_SHIFT                                           22
5282     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_FULL                                              (0x1<<29) // Set if pretrigger data was expected and enough data samples were collected prior to the trigger
5283     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_PRETRIG_FULL_SHIFT                                        29
5284     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_TRIGGERED                                      (0x1<<30) // Indicates that the TLDA is triggered.   For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the TLDA has collected all needed data.
5285     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_TRIGGERED_SHIFT                                30
5286     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_ACTIVE                                         (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must be cleared then set again.  When read, this indicates that the TLDA is active (waiting for a trigger).
5287     #define PCIEIP_REG_PCIER_TLDA0_CTLSTAT_LOCAL_TLDA_ACTIVE_SHIFT                                   31
5288 #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT                                                           0x000c44UL //Access:RW   DataWidth:0x20  Control and status register for indirect accesses.  Chips: BB_A0 BB_B0
5289     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_REG                                         (0xff<<0) // The indirect write address register.
5290     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_REG_SHIFT                                   0
5291     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_AUTOINC                                     (0x1<<8) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
5292     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_WADDR_AUTOINC_SHIFT                               8
5293     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_REG                                         (0xff<<9) // The indirect read address register.
5294     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_REG_SHIFT                                   9
5295     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_AUTOINC                                     (0x1<<17) // When set, the indirect read address register is incremented on reads.
5296     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_RADDR_AUTOINC_SHIFT                               17
5297     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_NO_RD_ADDR                                        (0x1<<18) // When set, the indirect write address register (below) is used for indirect reads as well.
5298     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_IND_NO_RD_ADDR_SHIFT                                  18
5299     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_UNUSED0                                               (0x1f<<19) //
5300     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_UNUSED0_SHIFT                                         19
5301     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_TL_TLDAFIFO_WADDR                                     (0x7f<<24) // Current write address to the external FIFO.
5302     #define PCIEIP_REG_PCIER_TLDA0_IND_CTLSTAT_TL_TLDAFIFO_WADDR_SHIFT                               24
5303 #define PCIEIP_REG_PCIER_TLDA0_IND_DATA                                                              0x000c48UL //Access:RW   DataWidth:0x20  Access to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. Registers are more fully described in the TLDA docs. The registers are:  -- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 rising edge mask bits [31:0]  Register 1 :: IND_TLDA_TRIG0_0TO1_MASK1 -- Trigger 0 rising edge mask bits [63:32]  Register 2 :: IND_TLDA_TRIG0_0TO1_MASK2 -- Trigger 0 rising edge mask bits [95:64]  Register 3 :: IND_TLDA_TRIG0_0TO1_MASK3 -- Trigger 0 rising edge mask bits [127:96]  Register 4 :: IND_TLDA_TRIG0_0TO1_MASK4 -- Trigger 0 rising edge mask bits [159:128]  Register 5 :: IND_TLDA_TRIG0_0TO1_MASK5 -- Trigger 0 rising edge mask bits [191:160]  Register 6 :: IND_TLDA_TRIG0_1TO0_MASK0 -- Trigger 0 falling edge mask bits [31:0]  Register 7 :: IND_TLDA_TRIG0_1TO0_MASK1 -- Trigger 0 falling edge mask bits [63:32]  Register 8 :: IND_TLDA_TRIG0_1TO0_MASK2 -- Trigger 0 falling edge mask bits [95:64]  Register 9 :: IND_TLDA_TRIG0_1TO0_MASK3 -- Trigger 0 falling edge mask bits [127:96]  Register 10 :: IND_TLDA_TRIG0_1TO0_MASK4 -- Trigger 0 falling edge mask bits [159:128]  Register 11 :: IND_TLDA_TRIG0_1TO0_MASK5 -- Trigger 0 falling edge mask bits [191:160]  Register 12 :: IND_TLDA_TRIG0_MATCH_MASK0 -- Trigger 0 bit match mask bits [31:0]  Register 13 :: IND_TLDA_TRIG0_MATCH_MASK1 -- Trigger 0 bit match mask bits [63:32]  Register 14 :: IND_TLDA_TRIG0_MATCH_MASK2 -- Trigger 0 bit match mask bits [95:64]  Register 15 :: IND_TLDA_TRIG0_MATCH_MASK3 -- Trigger 0 bit match mask bits [127:96]  Register 16 :: IND_TLDA_TRIG0_MATCH_MASK4 -- Trigger 0 bit match mask bits [159:128]  Register 17 :: IND_TLDA_TRIG0_MATCH_MASK5 -- Trigger 0 bit match mask bits [191:160]  Register 18 :: IND_TLDA_TRIG0_MATCH_VALUE0 -- Trigger 0 bit match value bits [31:0]  Register 19 :: IND_TLDA_TRIG0_MATCH_VALUE1 -- Trigger 0 bit match value bits [63:32]  Register 20 :: IND_TLDA_TRIG0_MATCH_VALUE2 -- Trigger 0 bit match value bits [95:64]  Register 21 :: IND_TLDA_TRIG0_MATCH_VALUE3 -- Trigger 0 bit match value bits [127:96]  Register 22 :: IND_TLDA_TRIG0_MATCH_VALUE4 -- Trigger 0 bit match value bits [159:128]  Register 23 :: IND_TLDA_TRIG0_MATCH_VALUE5 -- Trigger 0 bit match value bits [191:160]  Register 24 :: IND_TLDA_TRIG0_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 0  Register 25 :: IND_TLDA_TRIG0_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 0  Register 26 :: IND_TLDA_TRIG0_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 0  Register 27 :: IND_TLDA_TRIG0_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 0  Register 28 :: IND_TLDA_TRIG0_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 0  Register 29 :: IND_TLDA_TRIG0_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 0   -- Second trigger configuration registers Register 32 :: IND_TLDA_TRIG1_0TO1_MASK0 -- Trigger 1 rising edge mask bits [31:0]  Register 33 :: IND_TLDA_TRIG1_0TO1_MASK1 -- Trigger 1 rising edge mask bits [63:32]  Register 34 :: IND_TLDA_TRIG1_0TO1_MASK2 -- Trigger 1 rising edge mask bits [95:64]  Register 35 :: IND_TLDA_TRIG1_0TO1_MASK3 -- Trigger 1 rising edge mask bits [127:96]  Register 36 :: IND_TLDA_TRIG1_0TO1_MASK4 -- Trigger 1 rising edge mask bits [159:128]  Register 37 :: IND_TLDA_TRIG1_0TO1_MASK5 -- Trigger 1 rising edge mask bits [191:160]  Register 38 :: IND_TLDA_TRIG1_1TO0_MASK0 -- Trigger 1 falling edge mask bits [31:0]  Register 39 :: IND_TLDA_TRIG1_1TO0_MASK1 -- Trigger 1 falling edge mask bits [63:32]  Register 40 :: IND_TLDA_TRIG1_1TO0_MASK2 -- Trigger 1 falling edge mask bits [95:64]  Register 41 :: IND_TLDA_TRIG1_1TO0_MASK3 -- Trigger 1 falling edge mask bits [127:96]  Register 42 :: IND_TLDA_TRIG1_1TO0_MASK4 -- Trigger 1 falling edge mask bits [159:128]  Register 43 :: IND_TLDA_TRIG1_1TO0_MASK5 -- Trigger 1 falling edge mask bits [191:160]  Register 44 :: IND_TLDA_TRIG1_MATCH_MASK0 -- Trigger 1 bit match mask bits [31:0]  Register 45 :: IND_TLDA_TRIG1_MATCH_MASK1 -- Trigger 1 bit match mask bits [63:32]  Register 46 :: IND_TLDA_TRIG1_MATCH_MASK2 -- Trigger 1 bit match mask bits [95:64]  Register 47 :: IND_TLDA_TRIG1_MATCH_MASK3 -- Trigger 1 bit match mask bits [127:96]  Register 48 :: IND_TLDA_TRIG1_MATCH_MASK4 -- Trigger 1 bit match mask bits [159:128]  Register 49 :: IND_TLDA_TRIG1_MATCH_MASK5 -- Trigger 1 bit match mask bits [191:160]  Register 50 :: IND_TLDA_TRIG1_MATCH_VALUE0 -- Trigger 1 bit match value bits [31:0]  Register 51 :: IND_TLDA_TRIG1_MATCH_VALUE1 -- Trigger 1 bit match value bits [63:32]  Register 52 :: IND_TLDA_TRIG1_MATCH_VALUE2 -- Trigger 1 bit match value bits [95:64]  Register 53 :: IND_TLDA_TRIG1_MATCH_VALUE3 -- Trigger 1 bit match value bits [127:96]  Register 54 :: IND_TLDA_TRIG1_MATCH_VALUE4 -- Trigger 1 bit match value bits [159:128]  Register 55 :: IND_TLDA_TRIG1_MATCH_VALUE5 -- Trigger 1 bit match value bits [191:160]  Register 56 :: IND_TLDA_TRIG1_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 1  Register 57 :: IND_TLDA_TRIG1_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 1  Register 58 :: IND_TLDA_TRIG1_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 1  Register 59 :: IND_TLDA_TRIG1_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 1  Register 60 :: IND_TLDA_TRIG1_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 1  Register 61 :: IND_TLDA_TRIG1_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 1   -- Third trigger configuration registers Register 64 :: IND_TLDA_TRIG2_0TO1_MASK0 -- Trigger 2 rising edge mask bits [31:0]  Register 65 :: IND_TLDA_TRIG2_0TO1_MASK1 -- Trigger 2 rising edge mask bits [63:32]  Register 66 :: IND_TLDA_TRIG2_0TO1_MASK2 -- Trigger 2 rising edge mask bits [95:64]  Register 67 :: IND_TLDA_TRIG2_0TO1_MASK3 -- Trigger 2 rising edge mask bits [127:96]  Register 68 :: IND_TLDA_TRIG2_0TO1_MASK4 -- Trigger 2 rising edge mask bits [159:128]  Register 69 :: IND_TLDA_TRIG2_0TO1_MASK5 -- Trigger 2 rising edge mask bits [191:160]  Register 70 :: IND_TLDA_TRIG2_1TO0_MASK0 -- Trigger 2 falling edge mask bits [31:0]  Register 71 :: IND_TLDA_TRIG2_1TO0_MASK1 -- Trigger 2 falling edge mask bits [63:32]  Register 72 :: IND_TLDA_TRIG2_1TO0_MASK2 -- Trigger 2 falling edge mask bits [95:64]  Register 73 :: IND_TLDA_TRIG2_1TO0_MASK3 -- Trigger 2 falling edge mask bits [127:96]  Register 74 :: IND_TLDA_TRIG2_1TO0_MASK4 -- Trigger 2 falling edge mask bits [159:128]  Register 75 :: IND_TLDA_TRIG2_1TO0_MASK5 -- Trigger 2 falling edge mask bits [191:160]  Register 76 :: IND_TLDA_TRIG2_MATCH_MASK0 -- Trigger 2 bit match mask bits [31:0]  Register 77 :: IND_TLDA_TRIG2_MATCH_MASK1 -- Trigger 2 bit match mask bits [63:32]  Register 78 :: IND_TLDA_TRIG2_MATCH_MASK2 -- Trigger 2 bit match mask bits [95:64]  Register 79 :: IND_TLDA_TRIG2_MATCH_MASK3 -- Trigger 2 bit match mask bits [127:96]  Register 80 :: IND_TLDA_TRIG2_MATCH_MASK4 -- Trigger 2 bit match mask bits [159:128]  Register 81 :: IND_TLDA_TRIG2_MATCH_MASK5 -- Trigger 2 bit match mask bits [191:160]  Register 82 :: IND_TLDA_TRIG2_MATCH_VALUE0 -- Trigger 2 bit match value bits [31:0]  Register 83 :: IND_TLDA_TRIG2_MATCH_VALUE1 -- Trigger 2 bit match value bits [63:32]  Register 84 :: IND_TLDA_TRIG2_MATCH_VALUE2 -- Trigger 2 bit match value bits [95:64]  Register 85 :: IND_TLDA_TRIG2_MATCH_VALUE3 -- Trigger 2 bit match value bits [127:96]  Register 86 :: IND_TLDA_TRIG2_MATCH_VALUE4 -- Trigger 2 bit match value bits [159:128]  Register 87 :: IND_TLDA_TRIG2_MATCH_VALUE5 -- Trigger 2 bit match value bits [191:160]  Register 88 :: IND_TLDA_TRIG2_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 2  Register 89 :: IND_TLDA_TRIG2_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 2  Register 90 :: IND_TLDA_TRIG2_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 2  Register 91 :: IND_TLDA_TRIG2_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 2  Register 92 :: IND_TLDA_TRIG2_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 2  Register 93 :: IND_TLDA_TRIG2_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 2   -- Trigger selection and timeout configuration registers Register 96 :: IND_TLDA_TRIG_SELECT -- Selects which triggers or combination of triggers to use  Register 97 :: IND_TLDA_TRIG_TIMEOUT -- Configures timeouts for trigger actions  Register 98 :: IND_TLDA_TRIG_COMBINED_TRIG -- Selects how triggers from two TLDAs are combined   -- Data filtering based on rising edge in the data Register 100 :: IND_TLDA_FILTER_0TO1_MASK0 -- Data path filter rising edge mask bits [31:0]  Register 101 :: IND_TLDA_FILTER_0TO1_MASK1 -- Data path filter rising edga mask bits [63:32]  Register 102 :: IND_TLDA_FILTER_0TO1_MASK2 -- Data path filter rising edge mask bits [95:64]  Register 103 :: IND_TLDA_FILTER_0TO1_MASK3 -- Data path filter rising edge mask bits [127:96]  Register 104 :: IND_TLDA_FILTER_0TO1_MASK4 -- Data path filter rising edge mask bits [159:128]  Register 105 :: IND_TLDA_FILTER_0TO1_MASK5 -- Data path filter rising edge mask bits [191:160]  Register 106 :: IND_TLDA_FILTER_0TO1_MASK6 -- Data path filter rising edge mask bits [223:192]  Register 107 :: IND_TLDA_FILTER_0TO1_MASK7 -- Data path filter rising edge mask bits [255:224]  Register 108 :: IND_TLDA_FILTER_0TO1_MASK8 -- Data path filter rising edge mask bits [287:256]  Register 109 :: IND_TLDA_FILTER_0TO1_MASK9 -- Data path filter rising edge mask bits [319:288]   -- Data filtering based on faling edge in the data Register 110 :: IND_TLDA_FILTER_1TO0_MASK0 -- Data path filter falling edge mask bits [31:0]  Register 111 :: IND_TLDA_FILTER_1TO0_MASK1 -- Data path filter falling edga mask bits [63:32]  Register 112 :: IND_TLDA_FILTER_1TO0_MASK2 -- Data path filter falling edge mask bits [95:64]  Register 113 :: IND_TLDA_FILTER_1TO0_MASK3 -- Data path filter falling edge mask bits [127:96]  Register 114 :: IND_TLDA_FILTER_1TO0_MASK4 -- Data path filter falling edge mask bits [159:128]  Register 115 :: IND_TLDA_FILTER_1TO0_MASK5 -- Data path filter falling edge mask bits [191:160]  Register 116 :: IND_TLDA_FILTER_1TO0_MASK6 -- Data path filter falling edge mask bits [223:192]  Register 117 :: IND_TLDA_FILTER_1TO0_MASK7 -- Data path filter falling edge mask bits [255:224]  Register 118 :: IND_TLDA_FILTER_1TO0_MASK8 -- Data path filter falling edge mask bits [287:256]  Register 119 :: IND_TLDA_FILTER_1TO0_MASK9 -- Data path filter falling edge mask bits [319:288]   -- Data filtering based on matching (masked) value in the data Register 120 :: IND_TLDA_FILTER_MATCH0_MASK0 -- Data path filter match-0 mask bits [31:0]  Register 121 :: IND_TLDA_FILTER_MATCH0_MASK1 -- Data path filter match-0 mask bits [63:32]  Register 122 :: IND_TLDA_FILTER_MATCH0_MASK2 -- Data path filter match-0 mask bits [95:64]  Register 123 :: IND_TLDA_FILTER_MATCH0_MASK3 -- Data path filter match-0 mask bits [127:96]  Register 124 :: IND_TLDA_FILTER_MATCH0_MASK4 -- Data path filter match-0 mask bits [159:128]  Register 125 :: IND_TLDA_FILTER_MATCH0_MASK5 -- Data path filter match-0 mask bits [191:160]  Register 126 :: IND_TLDA_FILTER_MATCH0_MASK6 -- Data path filter match-0 mask bits [223:192]  Register 127 :: IND_TLDA_FILTER_MATCH0_MASK7 -- Data path filter match-0 mask bits [255:224]  Register 128 :: IND_TLDA_FILTER_MATCH0_MASK8 -- Data path filter match-0 mask bits [287:256]  Register 129 :: IND_TLDA_FILTER_MATCH0_MASK9 -- Data path filter match-0 mask bits [319:288]  Register 130 :: IND_TLDA_FILTER_MATCH0_VALUE0 -- Data path filter match-0 value bits [31:0]  Register 131 :: IND_TLDA_FILTER_MATCH0_VALUE1 -- Data path filter match-0 value bits [63:32]  Register 132 :: IND_TLDA_FILTER_MATCH0_VALUE2 -- Data path filter match-0 value bits [95:64]  Register 133 :: IND_TLDA_FILTER_MATCH0_VALUE3 -- Data path filter match-0 value bits [127:96]  Register 134 :: IND_TLDA_FILTER_MATCH0_VALUE4 -- Data path filter match-0 value bits [159:128]  Register 135 :: IND_TLDA_FILTER_MATCH0_VALUE5 -- Data path filter match-0 value bits [191:160]  Register 136 :: IND_TLDA_FILTER_MATCH0_VALUE6 -- Data path filter match-0 value bits [223:192]  Register 137 :: IND_TLDA_FILTER_MATCH0_VALUE7 -- Data path filter match-0 value bits [255:224]  Register 138 :: IND_TLDA_FILTER_MATCH0_VALUE8 -- Data path filter match-0 value bits [287:256]  Register 139 :: IND_TLDA_FILTER_MATCH0_VALUE9 -- Data path filter match-0 value bits [319:288]  Register 140 :: IND_TLDA_FILTER_MATCH1_MASK0 -- Data path filter match-1 mask bits [31:0]  Register 141 :: IND_TLDA_FILTER_MATCH1_MASK1 -- Data path filter match-1 mask bits [63:32]  Register 142 :: IND_TLDA_FILTER_MATCH1_MASK2 -- Data path filter match-1 mask bits [95:64]  Register 143 :: IND_TLDA_FILTER_MATCH1_MASK3 -- Data path filter match-1 mask bits [127:96]  Register 144 :: IND_TLDA_FILTER_MATCH1_MASK4 -- Data path filter match-1 mask bits [159:128]  Register 145 :: IND_TLDA_FILTER_MATCH1_MASK5 -- Data path filter match-1 mask bits [191:160]  Register 146 :: IND_TLDA_FILTER_MATCH1_MASK6 -- Data path filter match-1 mask bits [223:192]  Register 147 :: IND_TLDA_FILTER_MATCH1_MASK7 -- Data path filter match-1 mask bits [255:224]  Register 148 :: IND_TLDA_FILTER_MATCH1_MASK8 -- Data path filter match-1 mask bits [287:256]  Register 149 :: IND_TLDA_FILTER_MATCH1_MASK9 -- Data path filter match-1 mask bits [319:288]  Register 150 :: IND_TLDA_FILTER_MATCH1_VALUE0 -- Data path filter match-1 value bits [31:0]  Register 151 :: IND_TLDA_FILTER_MATCH1_VALUE1 -- Data path filter match-1 value bits [63:32]  Register 152 :: IND_TLDA_FILTER_MATCH1_VALUE2 -- Data path filter match-1 value bits [95:64]  Register 153 :: IND_TLDA_FILTER_MATCH1_VALUE3 -- Data path filter match-1 value bits [127:96]  Register 154 :: IND_TLDA_FILTER_MATCH1_VALUE4 -- Data path filter match-1 value bits [159:128]  Register 155 :: IND_TLDA_FILTER_MATCH1_VALUE5 -- Data path filter match-1 value bits [191:160]  Register 156 :: IND_TLDA_FILTER_MATCH1_VALUE6 -- Data path filter match-1 value bits [223:192]  Register 157 :: IND_TLDA_FILTER_MATCH1_VALUE7 -- Data path filter match-1 value bits [255:224]  Register 158 :: IND_TLDA_FILTER_MATCH1_VALUE8 -- Data path filter match-1 value bits [287:256]  Register 159 :: IND_TLDA_FILTER_MATCH1_VALUE9 -- Data path filter match-1 value bits [319:288]   Register 160 :: IND_TLDA_FILTER_SELECT -- Select the combinations of data filtering to use  Register 161 :: IND_TLDA_DATA_SELECT0 -- Bits [31:0] to select the data source  Register 162 :: IND_TLDA_DATA_SELECT1 -- Bits [63:32] to select the data source  Register 163 :: IND_TLDA_DATA_SELECT2 -- Bits [95:64] to select the data source  Register 164 :: IND_TLDA_DATA_SELECT3 -- Bits [127:96] to select the data source  Register 165 :: IND_TLDA_DATA_SELECT4 -- Bits [159:128] to select the data source  Register 166 :: IND_TLDA_DATA_SELECT5 -- Bits [191:160] to select the data source   Register 169 :: IND_TLDA_TIME_SELECT -- Select the time stamp to include in the data   Register 170 :: IND_TLDA_PREDEF_DATASEL -- Configure on of the preselected data source combinations   Register 171 :: IND_TLDA_EVENT_SEL -- Select the events to watch  Register 172 :: IND_TLDA_EVENT_CFG0 -- Configure the first set of event actions (counting, thresholds, etc)  Register 173 :: IND_TLDA_EVENT_CFG1 -- Configure the second set of event actions (counting, thresholds, etc)   Register 192 :: IND_TLDA_SPARE_DBG0 -- Spare debug register  Register 193 :: IND_TLDA_SPARE_DBG1 -- Spare debug register   If accessing an unimplemented register, the value 0xbadaddee will be returned.  Chips: BB_A0 BB_B0
5304 #define PCIEIP_REG_PCIER_TLDA0_RDFIFO_4                                                              0x000c4cUL //Access:R    DataWidth:0x20  The five read registers give a total of 160 bits of data from the FIFO. The FIFO is read when PCIER_TLDA0_RDFIFO_4 is read every other time. Also, on the opposite reads of PCIER_TLDA0_RDFIFO_4, the data in these registers is advanced to the next half of the FIFO data. So when the first PCIER_TLDA0_RDFIFO_4 read occurs, data is read from the FIFO and bits [159:0] are in these registers. Next read of PCIER_TLDA0_RDFIFO_4, bits [319:160] are in these registers. If the FIFO location is not used, each register will read 0xbaddf1f0.  Chips: BB_A0 BB_B0
5305 #define PCIEIP_REG_PCIER_TLDA0_RDFIFO_3                                                              0x000c50UL //Access:R    DataWidth:0x20  Bits [127:96] of the current half-data from the FIFO  Chips: BB_A0 BB_B0
5306 #define PCIEIP_REG_PCIER_TLDA0_RDFIFO_2                                                              0x000c54UL //Access:R    DataWidth:0x20  Bits [95:64] of the current half-data from the FIFO  Chips: BB_A0 BB_B0
5307 #define PCIEIP_REG_PCIER_TLDA0_RDFIFO_1                                                              0x000c58UL //Access:R    DataWidth:0x20  Bits [63:32] of the current half-data from the FIFO  Chips: BB_A0 BB_B0
5308 #define PCIEIP_REG_PCIER_TLDA0_RDFIFO_0                                                              0x000c5cUL //Access:R    DataWidth:0x20  Bits [31:0] of the current half-data from the FIFO  Chips: BB_A0 BB_B0
5309 #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT                                                               0x000c60UL //Access:RW   DataWidth:0x20  Main status and control register for the second Transaction Layer Data Analyzer. Trigger and status shown in this register.  Chips: BB_A0 BB_B0
5310     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_TL_TLDAFIFO_RADDR                                         (0x7f<<0) // The current read address for the external FIFO
5311     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_TL_TLDAFIFO_RADDR_SHIFT                                   0
5312     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RADDR_DWSEL                                          (0x1<<7) // When set, indicates that the lower 160 bits from the current FIFO read address are in the RDFIFO registers.
5313     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RADDR_DWSEL_SHIFT                                    7
5314     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RDAUTOINC                                            (0x1<<8) // When set and in local mode, reads to PCIER_TLDA_RDFIFO_4 will automatically increment the read address.
5315     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_FIFO_RDAUTOINC_SHIFT                                      8
5316     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_SERIES                                               (0x1<<9) // When set, this indicates the FIFOs are linked in series to increase the depth of the FIFO.
5317     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_SERIES_SHIFT                                         9
5318     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_PARA                                                 (0x1<<10) // When set, this indicates the FIFOs are linked in parallel to increase the width of the FIFO.
5319     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LINK_PARA_SHIFT                                           10
5320     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UI_PRETRIG_ALL                                            (0x1<<11) // Valid only when reading FIFOs from the user interface. When set, all pretrigger data is considered valid and will be present on the interface. Note that there is a bug in earlier versions of the TLDA that make this a write-only bit.
5321     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UI_PRETRIG_ALL_SHIFT                                      11
5322     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UNUSED0                                                   (0x1<<12) //
5323     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_UNUSED0_SHIFT                                             12
5324     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_DATA_AT_TRIG                                              (0x1<<13) // When set after FIFO has triggered, indicates that data at the trigger has been collected (as opposed to filtered out based on indirect register settings).
5325     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_DATA_AT_TRIG_SHIFT                                        13
5326     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_MODE                                                (0x1<<14) // When set, indicates that the FIFO is operating in local mode - FIFO will be read from the registers. When cleared, indicates that the FIFO is operating through reads from the user interface.
5327     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_MODE_SHIFT                                          14
5328     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_CNT                                               (0x7f<<15) // The number of pre-trigger samples to keep. pretrig_cnt[6] is only valid when if there are two TLDA blocks and they are linked serially (extending the FIFO depth).
5329     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_CNT_SHIFT                                         15
5330     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_TRIG_ADDR                                                 (0x7f<<22) // The FIFO write address at the time of the trigger. Use bit 13 of this register to determine if there was data collected at the time of the trigger.
5331     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_TRIG_ADDR_SHIFT                                           22
5332     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_FULL                                              (0x1<<29) // Set if pretrigger data was expected and enough data samples were collected prior to the trigger
5333     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_PRETRIG_FULL_SHIFT                                        29
5334     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_TRIGGERED                                      (0x1<<30) // Indicates that the TLDA is triggered.  For the above two bits, 0b10 is ready but not triggered, 0b11 is actively collecting and triggered, and 0b01 is that the TLDA has collected all needed data.
5335     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_TRIGGERED_SHIFT                                30
5336     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_ACTIVE                                         (0x1<<31) // When set by write, activates the TLDA logic. To retrigger, this must be cleared then set again.  When read, this indicates that the TLDA is active (waiting for a trigger).
5337     #define PCIEIP_REG_PCIER_TLDA1_CTLSTAT_LOCAL_TLDA_ACTIVE_SHIFT                                   31
5338 #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT                                                           0x000c64UL //Access:RW   DataWidth:0x20  Control and status register for indirect accesses.  Chips: BB_A0 BB_B0
5339     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_REG                                         (0xff<<0) // The indirect write address register.
5340     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_REG_SHIFT                                   0
5341     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_AUTOINC                                     (0x1<<8) // When set, the indirect write address register is incremented on writes and, if ind_no_rd_addr is set, it is also incremented on reads.
5342     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_WADDR_AUTOINC_SHIFT                               8
5343     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_REG                                         (0xff<<9) // The indirect read address register.
5344     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_REG_SHIFT                                   9
5345     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_AUTOINC                                     (0x1<<17) // When set, the indirect read address register is incremented on reads.
5346     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_RADDR_AUTOINC_SHIFT                               17
5347     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_NO_RD_ADDR                                        (0x1<<18) // When set, the indirect write address register (below) is used for indirect reads as well.
5348     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_IND_NO_RD_ADDR_SHIFT                                  18
5349     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_UNUSED0                                               (0x1f<<19) //
5350     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_UNUSED0_SHIFT                                         19
5351     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_TL_TLDAFIFO_WADDR                                     (0x3f<<24) // Current write address to the external FIFO.
5352     #define PCIEIP_REG_PCIER_TLDA1_IND_CTLSTAT_TL_TLDAFIFO_WADDR_SHIFT                               24
5353 #define PCIEIP_REG_PCIER_TLDA1_IND_DATA                                                              0x000c68UL //Access:RW   DataWidth:0x20  Access to the currently referenced indirect register via ind_raddr_reg or ind_waddr_reg. Registers are more fully described in the TLDA docs. The registers are:  -- First trigger configuration registers Register 0 :: IND_TLDA_TRIG0_0TO1_MASK0 -- Trigger 0 rising edge mask bits [31:0]  Register 1 :: IND_TLDA_TRIG0_0TO1_MASK1 -- Trigger 0 rising edge mask bits [63:32]  Register 2 :: IND_TLDA_TRIG0_0TO1_MASK2 -- Trigger 0 rising edge mask bits [95:64]  Register 3 :: IND_TLDA_TRIG0_0TO1_MASK3 -- Trigger 0 rising edge mask bits [127:96]  Register 4 :: IND_TLDA_TRIG0_0TO1_MASK4 -- Trigger 0 rising edge mask bits [159:128]  Register 5 :: IND_TLDA_TRIG0_0TO1_MASK5 -- Trigger 0 rising edge mask bits [191:160]  Register 6 :: IND_TLDA_TRIG0_1TO0_MASK0 -- Trigger 0 falling edge mask bits [31:0]  Register 7 :: IND_TLDA_TRIG0_1TO0_MASK1 -- Trigger 0 falling edge mask bits [63:32]  Register 8 :: IND_TLDA_TRIG0_1TO0_MASK2 -- Trigger 0 falling edge mask bits [95:64]  Register 9 :: IND_TLDA_TRIG0_1TO0_MASK3 -- Trigger 0 falling edge mask bits [127:96]  Register 10 :: IND_TLDA_TRIG0_1TO0_MASK4 -- Trigger 0 falling edge mask bits [159:128]  Register 11 :: IND_TLDA_TRIG0_1TO0_MASK5 -- Trigger 0 falling edge mask bits [191:160]  Register 12 :: IND_TLDA_TRIG0_MATCH_MASK0 -- Trigger 0 bit match mask bits [31:0]  Register 13 :: IND_TLDA_TRIG0_MATCH_MASK1 -- Trigger 0 bit match mask bits [63:32]  Register 14 :: IND_TLDA_TRIG0_MATCH_MASK2 -- Trigger 0 bit match mask bits [95:64]  Register 15 :: IND_TLDA_TRIG0_MATCH_MASK3 -- Trigger 0 bit match mask bits [127:96]  Register 16 :: IND_TLDA_TRIG0_MATCH_MASK4 -- Trigger 0 bit match mask bits [159:128]  Register 17 :: IND_TLDA_TRIG0_MATCH_MASK5 -- Trigger 0 bit match mask bits [191:160]  Register 18 :: IND_TLDA_TRIG0_MATCH_VALUE0 -- Trigger 0 bit match value bits [31:0]  Register 19 :: IND_TLDA_TRIG0_MATCH_VALUE1 -- Trigger 0 bit match value bits [63:32]  Register 20 :: IND_TLDA_TRIG0_MATCH_VALUE2 -- Trigger 0 bit match value bits [95:64]  Register 21 :: IND_TLDA_TRIG0_MATCH_VALUE3 -- Trigger 0 bit match value bits [127:96]  Register 22 :: IND_TLDA_TRIG0_MATCH_VALUE4 -- Trigger 0 bit match value bits [159:128]  Register 23 :: IND_TLDA_TRIG0_MATCH_VALUE5 -- Trigger 0 bit match value bits [191:160]  Register 24 :: IND_TLDA_TRIG0_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 0  Register 25 :: IND_TLDA_TRIG0_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 0  Register 26 :: IND_TLDA_TRIG0_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 0  Register 27 :: IND_TLDA_TRIG0_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 0  Register 28 :: IND_TLDA_TRIG0_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 0  Register 29 :: IND_TLDA_TRIG0_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 0   -- Second trigger configuration registers Register 32 :: IND_TLDA_TRIG1_0TO1_MASK0 -- Trigger 1 rising edge mask bits [31:0]  Register 33 :: IND_TLDA_TRIG1_0TO1_MASK1 -- Trigger 1 rising edge mask bits [63:32]  Register 34 :: IND_TLDA_TRIG1_0TO1_MASK2 -- Trigger 1 rising edge mask bits [95:64]  Register 35 :: IND_TLDA_TRIG1_0TO1_MASK3 -- Trigger 1 rising edge mask bits [127:96]  Register 36 :: IND_TLDA_TRIG1_0TO1_MASK4 -- Trigger 1 rising edge mask bits [159:128]  Register 37 :: IND_TLDA_TRIG1_0TO1_MASK5 -- Trigger 1 rising edge mask bits [191:160]  Register 38 :: IND_TLDA_TRIG1_1TO0_MASK0 -- Trigger 1 falling edge mask bits [31:0]  Register 39 :: IND_TLDA_TRIG1_1TO0_MASK1 -- Trigger 1 falling edge mask bits [63:32]  Register 40 :: IND_TLDA_TRIG1_1TO0_MASK2 -- Trigger 1 falling edge mask bits [95:64]  Register 41 :: IND_TLDA_TRIG1_1TO0_MASK3 -- Trigger 1 falling edge mask bits [127:96]  Register 42 :: IND_TLDA_TRIG1_1TO0_MASK4 -- Trigger 1 falling edge mask bits [159:128]  Register 43 :: IND_TLDA_TRIG1_1TO0_MASK5 -- Trigger 1 falling edge mask bits [191:160]  Register 44 :: IND_TLDA_TRIG1_MATCH_MASK0 -- Trigger 1 bit match mask bits [31:0]  Register 45 :: IND_TLDA_TRIG1_MATCH_MASK1 -- Trigger 1 bit match mask bits [63:32]  Register 46 :: IND_TLDA_TRIG1_MATCH_MASK2 -- Trigger 1 bit match mask bits [95:64]  Register 47 :: IND_TLDA_TRIG1_MATCH_MASK3 -- Trigger 1 bit match mask bits [127:96]  Register 48 :: IND_TLDA_TRIG1_MATCH_MASK4 -- Trigger 1 bit match mask bits [159:128]  Register 49 :: IND_TLDA_TRIG1_MATCH_MASK5 -- Trigger 1 bit match mask bits [191:160]  Register 50 :: IND_TLDA_TRIG1_MATCH_VALUE0 -- Trigger 1 bit match value bits [31:0]  Register 51 :: IND_TLDA_TRIG1_MATCH_VALUE1 -- Trigger 1 bit match value bits [63:32]  Register 52 :: IND_TLDA_TRIG1_MATCH_VALUE2 -- Trigger 1 bit match value bits [95:64]  Register 53 :: IND_TLDA_TRIG1_MATCH_VALUE3 -- Trigger 1 bit match value bits [127:96]  Register 54 :: IND_TLDA_TRIG1_MATCH_VALUE4 -- Trigger 1 bit match value bits [159:128]  Register 55 :: IND_TLDA_TRIG1_MATCH_VALUE5 -- Trigger 1 bit match value bits [191:160]  Register 56 :: IND_TLDA_TRIG1_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 1  Register 57 :: IND_TLDA_TRIG1_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 1  Register 58 :: IND_TLDA_TRIG1_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 1  Register 59 :: IND_TLDA_TRIG1_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 1  Register 60 :: IND_TLDA_TRIG1_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 1  Register 61 :: IND_TLDA_TRIG1_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 1   -- Third trigger configuration registers Register 64 :: IND_TLDA_TRIG2_0TO1_MASK0 -- Trigger 2 rising edge mask bits [31:0]  Register 65 :: IND_TLDA_TRIG2_0TO1_MASK1 -- Trigger 2 rising edge mask bits [63:32]  Register 66 :: IND_TLDA_TRIG2_0TO1_MASK2 -- Trigger 2 rising edge mask bits [95:64]  Register 67 :: IND_TLDA_TRIG2_0TO1_MASK3 -- Trigger 2 rising edge mask bits [127:96]  Register 68 :: IND_TLDA_TRIG2_0TO1_MASK4 -- Trigger 2 rising edge mask bits [159:128]  Register 69 :: IND_TLDA_TRIG2_0TO1_MASK5 -- Trigger 2 rising edge mask bits [191:160]  Register 70 :: IND_TLDA_TRIG2_1TO0_MASK0 -- Trigger 2 falling edge mask bits [31:0]  Register 71 :: IND_TLDA_TRIG2_1TO0_MASK1 -- Trigger 2 falling edge mask bits [63:32]  Register 72 :: IND_TLDA_TRIG2_1TO0_MASK2 -- Trigger 2 falling edge mask bits [95:64]  Register 73 :: IND_TLDA_TRIG2_1TO0_MASK3 -- Trigger 2 falling edge mask bits [127:96]  Register 74 :: IND_TLDA_TRIG2_1TO0_MASK4 -- Trigger 2 falling edge mask bits [159:128]  Register 75 :: IND_TLDA_TRIG2_1TO0_MASK5 -- Trigger 2 falling edge mask bits [191:160]  Register 76 :: IND_TLDA_TRIG2_MATCH_MASK0 -- Trigger 2 bit match mask bits [31:0]  Register 77 :: IND_TLDA_TRIG2_MATCH_MASK1 -- Trigger 2 bit match mask bits [63:32]  Register 78 :: IND_TLDA_TRIG2_MATCH_MASK2 -- Trigger 2 bit match mask bits [95:64]  Register 79 :: IND_TLDA_TRIG2_MATCH_MASK3 -- Trigger 2 bit match mask bits [127:96]  Register 80 :: IND_TLDA_TRIG2_MATCH_MASK4 -- Trigger 2 bit match mask bits [159:128]  Register 81 :: IND_TLDA_TRIG2_MATCH_MASK5 -- Trigger 2 bit match mask bits [191:160]  Register 82 :: IND_TLDA_TRIG2_MATCH_VALUE0 -- Trigger 2 bit match value bits [31:0]  Register 83 :: IND_TLDA_TRIG2_MATCH_VALUE1 -- Trigger 2 bit match value bits [63:32]  Register 84 :: IND_TLDA_TRIG2_MATCH_VALUE2 -- Trigger 2 bit match value bits [95:64]  Register 85 :: IND_TLDA_TRIG2_MATCH_VALUE3 -- Trigger 2 bit match value bits [127:96]  Register 86 :: IND_TLDA_TRIG2_MATCH_VALUE4 -- Trigger 2 bit match value bits [159:128]  Register 87 :: IND_TLDA_TRIG2_MATCH_VALUE5 -- Trigger 2 bit match value bits [191:160]  Register 88 :: IND_TLDA_TRIG2_DATA_SELECT0 -- Bits [31:0] to select the data source for trigger 2  Register 89 :: IND_TLDA_TRIG2_DATA_SELECT1 -- Bits [63:32] to select the data source for trigger 2  Register 90 :: IND_TLDA_TRIG2_DATA_SELECT2 -- Bits [95:64] to select the data source for trigger 2  Register 91 :: IND_TLDA_TRIG2_DATA_SELECT3 -- Bits [127:96] to select the data source for trigger 2  Register 92 :: IND_TLDA_TRIG2_DATA_SELECT4 -- Bits [159:128] to select the data source for trigger 2  Register 93 :: IND_TLDA_TRIG2_DATA_SELECT5 -- Bits [191:160] to select the data source for trigger 2   -- Trigger selection and timeout configuration registers Register 96 :: IND_TLDA_TRIG_SELECT -- Selects which triggers or combination of triggers to use  Register 97 :: IND_TLDA_TRIG_TIMEOUT -- Configures timeouts for trigger actions   -- Data filtering based on rising edge in the data Register 100 :: IND_TLDA_FILTER_0TO1_MASK0 -- Data path filter rising edge mask bits [31:0]  Register 101 :: IND_TLDA_FILTER_0TO1_MASK1 -- Data path filter rising edga mask bits [63:32]  Register 102 :: IND_TLDA_FILTER_0TO1_MASK2 -- Data path filter rising edge mask bits [95:64]  Register 103 :: IND_TLDA_FILTER_0TO1_MASK3 -- Data path filter rising edge mask bits [127:96]  Register 104 :: IND_TLDA_FILTER_0TO1_MASK4 -- Data path filter rising edge mask bits [159:128]  Register 105 :: IND_TLDA_FILTER_0TO1_MASK5 -- Data path filter rising edge mask bits [191:160]  Register 106 :: IND_TLDA_FILTER_0TO1_MASK6 -- Data path filter rising edge mask bits [223:192]  Register 107 :: IND_TLDA_FILTER_0TO1_MASK7 -- Data path filter rising edge mask bits [255:224]  Register 108 :: IND_TLDA_FILTER_0TO1_MASK8 -- Data path filter rising edge mask bits [287:256]  Register 109 :: IND_TLDA_FILTER_0TO1_MASK9 -- Data path filter rising edge mask bits [319:288]   -- Data filtering based on faling edge in the data Register 110 :: IND_TLDA_FILTER_1TO0_MASK0 -- Data path filter falling edge mask bits [31:0]  Register 111 :: IND_TLDA_FILTER_1TO0_MASK1 -- Data path filter falling edga mask bits [63:32]  Register 112 :: IND_TLDA_FILTER_1TO0_MASK2 -- Data path filter falling edge mask bits [95:64]  Register 113 :: IND_TLDA_FILTER_1TO0_MASK3 -- Data path filter falling edge mask bits [127:96]  Register 114 :: IND_TLDA_FILTER_1TO0_MASK4 -- Data path filter falling edge mask bits [159:128]  Register 115 :: IND_TLDA_FILTER_1TO0_MASK5 -- Data path filter falling edge mask bits [191:160]  Register 116 :: IND_TLDA_FILTER_1TO0_MASK6 -- Data path filter falling edge mask bits [223:192]  Register 117 :: IND_TLDA_FILTER_1TO0_MASK7 -- Data path filter falling edge mask bits [255:224]  Register 118 :: IND_TLDA_FILTER_1TO0_MASK8 -- Data path filter falling edge mask bits [287:256]  Register 119 :: IND_TLDA_FILTER_1TO0_MASK9 -- Data path filter falling edge mask bits [319:288]   -- Data filtering based on matching (masked) value in the data Register 120 :: IND_TLDA_FILTER_MATCH0_MASK0 -- Data path filter match-0 mask bits [31:0]  Register 121 :: IND_TLDA_FILTER_MATCH0_MASK1 -- Data path filter match-0 mask bits [63:32]  Register 122 :: IND_TLDA_FILTER_MATCH0_MASK2 -- Data path filter match-0 mask bits [95:64]  Register 123 :: IND_TLDA_FILTER_MATCH0_MASK3 -- Data path filter match-0 mask bits [127:96]  Register 124 :: IND_TLDA_FILTER_MATCH0_MASK4 -- Data path filter match-0 mask bits [159:128]  Register 125 :: IND_TLDA_FILTER_MATCH0_MASK5 -- Data path filter match-0 mask bits [191:160]  Register 126 :: IND_TLDA_FILTER_MATCH0_MASK6 -- Data path filter match-0 mask bits [223:192]  Register 127 :: IND_TLDA_FILTER_MATCH0_MASK7 -- Data path filter match-0 mask bits [255:224]  Register 128 :: IND_TLDA_FILTER_MATCH0_MASK8 -- Data path filter match-0 mask bits [287:256]  Register 129 :: IND_TLDA_FILTER_MATCH0_MASK9 -- Data path filter match-0 mask bits [319:288]  Register 130 :: IND_TLDA_FILTER_MATCH0_VALUE0 -- Data path filter match-0 value bits [31:0]  Register 131 :: IND_TLDA_FILTER_MATCH0_VALUE1 -- Data path filter match-0 value bits [63:32]  Register 132 :: IND_TLDA_FILTER_MATCH0_VALUE2 -- Data path filter match-0 value bits [95:64]  Register 133 :: IND_TLDA_FILTER_MATCH0_VALUE3 -- Data path filter match-0 value bits [127:96]  Register 134 :: IND_TLDA_FILTER_MATCH0_VALUE4 -- Data path filter match-0 value bits [159:128]  Register 135 :: IND_TLDA_FILTER_MATCH0_VALUE5 -- Data path filter match-0 value bits [191:160]  Register 136 :: IND_TLDA_FILTER_MATCH0_VALUE6 -- Data path filter match-0 value bits [223:192]  Register 137 :: IND_TLDA_FILTER_MATCH0_VALUE7 -- Data path filter match-0 value bits [255:224]  Register 138 :: IND_TLDA_FILTER_MATCH0_VALUE8 -- Data path filter match-0 value bits [287:256]  Register 139 :: IND_TLDA_FILTER_MATCH0_VALUE9 -- Data path filter match-0 value bits [319:288]  Register 140 :: IND_TLDA_FILTER_MATCH1_MASK0 -- Data path filter match-1 mask bits [31:0]  Register 141 :: IND_TLDA_FILTER_MATCH1_MASK1 -- Data path filter match-1 mask bits [63:32]  Register 142 :: IND_TLDA_FILTER_MATCH1_MASK2 -- Data path filter match-1 mask bits [95:64]  Register 143 :: IND_TLDA_FILTER_MATCH1_MASK3 -- Data path filter match-1 mask bits [127:96]  Register 144 :: IND_TLDA_FILTER_MATCH1_MASK4 -- Data path filter match-1 mask bits [159:128]  Register 145 :: IND_TLDA_FILTER_MATCH1_MASK5 -- Data path filter match-1 mask bits [191:160]  Register 146 :: IND_TLDA_FILTER_MATCH1_MASK6 -- Data path filter match-1 mask bits [223:192]  Register 147 :: IND_TLDA_FILTER_MATCH1_MASK7 -- Data path filter match-1 mask bits [255:224]  Register 148 :: IND_TLDA_FILTER_MATCH1_MASK8 -- Data path filter match-1 mask bits [287:256]  Register 149 :: IND_TLDA_FILTER_MATCH1_MASK9 -- Data path filter match-1 mask bits [319:288]  Register 150 :: IND_TLDA_FILTER_MATCH1_VALUE0 -- Data path filter match-1 value bits [31:0]  Register 151 :: IND_TLDA_FILTER_MATCH1_VALUE1 -- Data path filter match-1 value bits [63:32]  Register 152 :: IND_TLDA_FILTER_MATCH1_VALUE2 -- Data path filter match-1 value bits [95:64]  Register 153 :: IND_TLDA_FILTER_MATCH1_VALUE3 -- Data path filter match-1 value bits [127:96]  Register 154 :: IND_TLDA_FILTER_MATCH1_VALUE4 -- Data path filter match-1 value bits [159:128]  Register 155 :: IND_TLDA_FILTER_MATCH1_VALUE5 -- Data path filter match-1 value bits [191:160]  Register 156 :: IND_TLDA_FILTER_MATCH1_VALUE6 -- Data path filter match-1 value bits [223:192]  Register 157 :: IND_TLDA_FILTER_MATCH1_VALUE7 -- Data path filter match-1 value bits [255:224]  Register 158 :: IND_TLDA_FILTER_MATCH1_VALUE8 -- Data path filter match-1 value bits [287:256]  Register 159 :: IND_TLDA_FILTER_MATCH1_VALUE9 -- Data path filter match-1 value bits [319:288]   Register 160 :: IND_TLDA_FILTER_SELECT -- Select the combinations of data filtering to use  Register 161 :: IND_TLDA_DATA_SELECT0 -- Bits [31:0] to select the data source  Register 162 :: IND_TLDA_DATA_SELECT1 -- Bits [63:32] to select the data source  Register 163 :: IND_TLDA_DATA_SELECT2 -- Bits [95:64] to select the data source  Register 164 :: IND_TLDA_DATA_SELECT3 -- Bits [127:96] to select the data source  Register 165 :: IND_TLDA_DATA_SELECT4 -- Bits [159:128] to select the data source  Register 166 :: IND_TLDA_DATA_SELECT5 -- Bits [191:160] to select the data source   Register 169 :: IND_TLDA_TIME_SELECT -- Select the time stamp to include in the data   Register 170 :: IND_TLDA_PREDEF_DATASEL -- Configure on of the preselected data source combinations   Register 171 :: IND_TLDA_EVENT_SEL -- Select the events to watch  Register 172 :: IND_TLDA_EVENT_CFG0 -- Configure the first set of event actions (counting, thresholds, etc)  Register 173 :: IND_TLDA_EVENT_CFG1 -- Configure the second set of event actions (counting, thresholds, etc)   Register 192 :: IND_TLDA_SPARE_DBG0 -- Spare debug register  Register 193 :: IND_TLDA_SPARE_DBG1 -- Spare debug register   If accessing an unimplemented register, the value 0xbadaddee will be returned.  Chips: BB_A0 BB_B0
5354 #define PCIEIP_REG_PCIER_TLDA1_RDFIFO_4                                                              0x000c6cUL //Access:R    DataWidth:0x20  The five read registers give a total of 160 bits of data from the FIFO. The FIFO is read when PCIER_TLDA1_RDFIFO_4 is read every other time. Also, on the opposite reads of PCIER_TLDA1_RDFIFO_4, the data in these registers is advanced to the next half of the FIFO data. So when the first PCIER_TLDA1_RDFIFO_4 read occurs, data is read from the FIFO and bits [159:0] are in these registers. Next read of PCIER_TLDA1_RDFIFO_4, bits [319:160] are in these registers. If the FIFO location is not used, each register will read 0xbaddf1f0.  Chips: BB_A0 BB_B0
5355 #define PCIEIP_REG_PCIER_TLDA1_RDFIFO_3                                                              0x000c70UL //Access:R    DataWidth:0x20  Bits [127:96] of the current half-data from the second FIFO  Chips: BB_A0 BB_B0
5356 #define PCIEIP_REG_PCIER_TLDA1_RDFIFO_2                                                              0x000c74UL //Access:R    DataWidth:0x20  Bits [95:64] of the current half-data from the second FIFO  Chips: BB_A0 BB_B0
5357 #define PCIEIP_REG_PCIER_TLDA1_RDFIFO_1                                                              0x000c78UL //Access:R    DataWidth:0x20  Bits [63:32] of the current half-data from the second FIFO  Chips: BB_A0 BB_B0
5358 #define PCIEIP_REG_PCIER_TLDA1_RDFIFO_0                                                              0x000c7cUL //Access:R    DataWidth:0x20  Bits [31:0] of the current half-data from the second FIFO  Chips: BB_A0 BB_B0
5359 #define PCIEIP_REG_PDL_CONTROL_0                                                                     0x001000UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5360     #define PCIEIP_REG_PDL_CONTROL_0_ENA_SCRAM                                                       (0x1<<0) // PHY: Enable Scrambler. Default for FPGA is 0
5361     #define PCIEIP_REG_PDL_CONTROL_0_ENA_SCRAM_SHIFT                                                 0
5362     #define PCIEIP_REG_PDL_CONTROL_0_DIS_INV_POLARITY                                                (0x1<<1) // PHY: Disable Inverse Polarity. Setting this bit to '1' disables the polarity inversion regardless of what hardware detects during the training.
5363     #define PCIEIP_REG_PDL_CONTROL_0_DIS_INV_POLARITY_SHIFT                                          1
5364     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_TIMER                                            (0x1<<2) // DL: Disable Replay Timer. In effect, REPLAY only occurs when NACK DLLP is received.
5365     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_TIMER_SHIFT                                      2
5366     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_3                                                      (0x1<<3) //
5367     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_3_SHIFT                                                3
5368     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLL                                                 (0x1<<4) // DL: Disable CRC check for incoming DLLP packets
5369     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLL_SHIFT                                           4
5370     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLP                                                 (0x1<<5) // DL: Disable CRC check for incoming TLP packets
5371     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_CRC_DLP_SHIFT                                           5
5372     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_BUFF                                             (0x1<<6) // DL: If set, REPLAY EMPTY will be asserted.
5373     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_REPLAY_BUFF_SHIFT                                       6
5374     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_9_7                                                    (0x7<<7) //
5375     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_9_7_SHIFT                                              7
5376     #define PCIEIP_REG_PDL_CONTROL_0_DIS_ELECIDLE_RETRAIN                                            (0x1<<10) // PHY: Disable Electrical Idle Retrain. Setting this bit to '1' prevents link from doing retrain if either inferred electrical idle occurs or signal is not detected on all lanes while in L0 or RxL0s.
5377     #define PCIEIP_REG_PDL_CONTROL_0_DIS_ELECIDLE_RETRAIN_SHIFT                                      10
5378     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_AUTO_CRDUPD                                             (0x1<<11) // DL: Disable Auto Credit Update. If this bit is set to '1', DL will not automatically generate UpdateFC every 30us (or 120 us if Ext Sync is set)
5379     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_AUTO_CRDUPD_SHIFT                                       11
5380     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_RETRAIN_REQ                                             (0x1<<12) // DL:Disable hardware from triggering link retraining due to Replay timer roll over, Replay timeout, or detecting maximum number of correctable errors.
5381     #define PCIEIP_REG_PDL_CONTROL_0_DISABLE_RETRAIN_REQ_SHIFT                                       12
5382     #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL1                                                    (0x1<<13) // DL: Force L0 to L1. When this bit is set to '1', DL will send PM_Enter_L1 DLLP to link partner.
5383     #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL1_SHIFT                                              13
5384     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_22_14                                                  (0x1ff<<14) //
5385     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_22_14_SHIFT                                            14
5386     #define PCIEIP_REG_PDL_CONTROL_0_FORCE_RCVR_DETECT_ALL                                           (0x1<<23) // PHY: Force Receiver Detect All. When this bit is set to '1', internal Receiver Detected signals are forced to '1' as if link partner receiver has been detected for all lanes.
5387     #define PCIEIP_REG_PDL_CONTROL_0_FORCE_RCVR_DETECT_ALL_SHIFT                                     23
5388     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_26_24                                                  (0x7<<24) //
5389     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_26_24_SHIFT                                            24
5390     #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL2                                                    (0x1<<27) // DL: Force L0 to L2. When this bit is set to '1', DL will send PM_Enter_L23 DLLP to link partner.
5391     #define PCIEIP_REG_PDL_CONTROL_0_FORCE_L0TOL2_SHIFT                                              27
5392     #define PCIEIP_REG_PDL_CONTROL_0_DIS_HOT_RESET                                                   (0x1<<28) // PHY: Disable Hot Reset.
5393     #define PCIEIP_REG_PDL_CONTROL_0_DIS_HOT_RESET_SHIFT                                             28
5394     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_30_29                                                  (0x3<<29) //
5395     #define PCIEIP_REG_PDL_CONTROL_0_RESERVED_30_29_SHIFT                                            29
5396     #define PCIEIP_REG_PDL_CONTROL_0_DIRECT_RECOV_TO_CONFIG                                          (0x1<<31) // PHY: Direct Recovery to Configuration State. When this bit is set to '1', LTSSM is directed to transition from Recovery.Idle to Configuration state.
5397     #define PCIEIP_REG_PDL_CONTROL_0_DIRECT_RECOV_TO_CONFIG_SHIFT                                    31
5398 #define PCIEIP_REG_PDL_CONTROL_1                                                                     0x001004UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5399     #define PCIEIP_REG_PDL_CONTROL_1_MAX_DLP_IDLE_CNT                                                (0x7f<<0) // DL: This field specifies the time that DL doesn't have any TLP/DLLP to transmit before DL requests PL to enter L0s. The actual time is equal to (MAX_DLP_IDLE_CNT * 128ns).
5400     #define PCIEIP_REG_PDL_CONTROL_1_MAX_DLP_IDLE_CNT_SHIFT                                          0
5401     #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_P_LAT_SEL                                              (0x1<<7) // When this bit is set, the software value will be used for UpdateFC Latency of Posted credit.
5402     #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_P_LAT_SEL_SHIFT                                        7
5403     #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_3                                                        (0x1<<8) // Reserved
5404     #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_3_SHIFT                                                  8
5405     #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_NP_LAT_SEL                                             (0x1<<9) // When this bit is set, the software value will be used for UpdateFC Latency of Non-Posted credit.
5406     #define PCIEIP_REG_PDL_CONTROL_1_SW_UPDFC_NP_LAT_SEL_SHIFT                                       9
5407     #define PCIEIP_REG_PDL_CONTROL_1_DIS_NAK_RST_TMR                                                 (0x1<<10) // DL: When this bit is set to '1', Replay Timer will not be reset if a NAK is received during a Replay operation. While not in Replay, a NAK always resets the timer regardless of the setting of this bit.
5408     #define PCIEIP_REG_PDL_CONTROL_1_DIS_NAK_RST_TMR_SHIFT                                           10
5409     #define PCIEIP_REG_PDL_CONTROL_1_FORCE_TX_L0S                                                    (0x1<<11) // PHY: Force to TX L0s. Setting this bit to '1' forces LTSSM to enter TX L0s state.
5410     #define PCIEIP_REG_PDL_CONTROL_1_FORCE_TX_L0S_SHIFT                                              11
5411     #define PCIEIP_REG_PDL_CONTROL_1_MAX_REPLAY_NUM                                                  (0x3<<12) // DL: Maximum times Replay must be repeated before DL triggers link retrains
5412     #define PCIEIP_REG_PDL_CONTROL_1_MAX_REPLAY_NUM_SHIFT                                            12
5413     #define PCIEIP_REG_PDL_CONTROL_1_RETRAIN_REQ                                                     (0x1<<14) // This initiates Link re-training by directing PHY LTSSM to recovery state. It is a pulse, so reading this bit always returns '0'.
5414     #define PCIEIP_REG_PDL_CONTROL_1_RETRAIN_REQ_SHIFT                                               14
5415     #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_1                                                        (0x1<<15) // Reserved
5416     #define PCIEIP_REG_PDL_CONTROL_1_UNUSED_1_SHIFT                                                  15
5417     #define PCIEIP_REG_PDL_CONTROL_1_MAX_DLP_L1_ENTRANCE                                             (0x7f<<16) // DL: This field specifies the time DL must wait before initiating ASPM L1 request. If L0s is enabled, it is the time link is in L0s. If L0s is not enabled, it is the time link doesn't have any activity. The actual time is equal to (MAX_DLP_L1_ENTRANCE * 256ns).
5418     #define PCIEIP_REG_PDL_CONTROL_1_MAX_DLP_L1_ENTRANCE_SHIFT                                       16
5419     #define PCIEIP_REG_PDL_CONTROL_1_ASPM_L1_GAP                                                     (0x7f<<23) // DL: After an ASPM L1 request is rejected by RC, if EP doesn't enter L0s, this field specifies the gap time before EP can initiate the next ASPM L1 request. The actual time is equal to (ASPM_L1_GAP * 256ns).
5420     #define PCIEIP_REG_PDL_CONTROL_1_ASPM_L1_GAP_SHIFT                                               23
5421     #define PCIEIP_REG_PDL_CONTROL_1_INT_ASPM_L1_ENA                                                 (0x1<<30) // Internal ASPM L1 Enable. When this bit is set to '1', hardware autonomously control ASPM L1 by monitoring link activities. Signal user_early_l1_exit also works in this mode.
5422     #define PCIEIP_REG_PDL_CONTROL_1_INT_ASPM_L1_ENA_SHIFT                                           30
5423     #define PCIEIP_REG_PDL_CONTROL_1_EXT_ASPM_L1_ENA                                                 (0x1<<31) // External ASPM L1 Enable. When this bit is set to '1', user can directly control when to enter ASPM L1 using signal user_l1_enter. Actual L1 entering is contingent to link activities. If user_early_l1_exit is also set, it overrides user_l1_enter signal.
5424     #define PCIEIP_REG_PDL_CONTROL_1_EXT_ASPM_L1_ENA_SHIFT                                           31
5425 #define PCIEIP_REG_PDL_CONTROL_2                                                                     0x001008UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5426     #define PCIEIP_REG_PDL_CONTROL_2_SEL_SOS_INTERVAL                                                (0x3<<0) // PHY: Select SKP OS interval. This field selects the interval for SKP ordered set transmitting.
5427     #define PCIEIP_REG_PDL_CONTROL_2_SEL_SOS_INTERVAL_SHIFT                                          0
5428     #define PCIEIP_REG_PDL_CONTROL_2_DIS_SOS_INTERVAL                                                (0x1<<2) // PHY: Disable SKP OS. When this bit is set to '1', periodic SKP OS transmitting is disabled.
5429     #define PCIEIP_REG_PDL_CONTROL_2_DIS_SOS_INTERVAL_SHIFT                                          2
5430     #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_ACK_LAT_TIMER                                            (0x1<<3) // DL: If set, it will enable ACK Latency Timer. In this case, DL ACK or NACK requests are only sent out when timer reaches MAX_ACK_LAT_TIMER. When this timer is disabled, ACK/NACK requests will be sent to PCIE bus as soon as they are asserted.
5431     #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_ACK_LAT_TIMER_SHIFT                                      3
5432     #define PCIEIP_REG_PDL_CONTROL_2_SW_ACK_LAT_SEL                                                  (0x1<<4) // If set, override hardwired value with the programmable ACK Latency timer. HW will select programmable value depending on whether PHY operates in gen 1or gen2. The programmable register for ACK LAT is at address 0x1034
5433     #define PCIEIP_REG_PDL_CONTROL_2_SW_ACK_LAT_SEL_SHIFT                                            4
5434     #define PCIEIP_REG_PDL_CONTROL_2_SW_REPLAY_TIMER_SEL                                             (0x1<<5) // If set, override hardwired value with programmable REPLAY timer. HW will select programmable value depending on whether PHY operates in gen 1or gen2. The programmable REPLAY register is at address 0x102C
5435     #define PCIEIP_REG_PDL_CONTROL_2_SW_REPLAY_TIMER_SEL_SHIFT                                       5
5436     #define PCIEIP_REG_PDL_CONTROL_2_RESERVED_7_6                                                    (0x3<<6) //
5437     #define PCIEIP_REG_PDL_CONTROL_2_RESERVED_7_6_SHIFT                                              6
5438     #define PCIEIP_REG_PDL_CONTROL_2_L0SL1L2_WAIT_FOR_IDLE                                           (0xf<<8) // PHY: RxL0s, L1, L2 Wait For Idle. This field specifies the minimum number of clock cycles that LTSSM will stay in RxL0s, L1, L2 Idle state before exiting because of signal detection.
5439     #define PCIEIP_REG_PDL_CONTROL_2_L0SL1L2_WAIT_FOR_IDLE_SHIFT                                     8
5440     #define PCIEIP_REG_PDL_CONTROL_2_RESERVED_15_12                                                  (0xf<<12) //
5441     #define PCIEIP_REG_PDL_CONTROL_2_RESERVED_15_12_SHIFT                                            12
5442     #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_P                                                (0x1<<16) // DL: Enable Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL will send out FC update for Posted
5443     #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_P_SHIFT                                          16
5444     #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_N                                                (0x1<<17) // DL: Enable Non-Posted Latency Timer. If this timer reaches MAX_ACK_LAT_TIMER value, DL will send out FC update for Non-Posted
5445     #define PCIEIP_REG_PDL_CONTROL_2_ENABLE_CRD_LAT_N_SHIFT                                          17
5446     #define PCIEIP_REG_PDL_CONTROL_2_CORR_ERR_REG_MAX                                                (0x3ff<<18) // DL: Maximum Correctable Errors that DL must detect within an 256us interval before asserting Correctable Error flag in DLATTN_VEC register.
5447     #define PCIEIP_REG_PDL_CONTROL_2_CORR_ERR_REG_MAX_SHIFT                                          18
5448 #define PCIEIP_REG_PDL_CONTROL_3                                                                     0x00100cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5449     #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT                                                (0xff<<0) // PHY
5450     #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_SHIFT                                          0
5451     #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG                                           (0xff<<8) // PHY
5452     #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_SHIFT                                     8
5453     #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_GEN2                                           (0xff<<16) // PHY
5454     #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_GEN2_SHIFT                                     16
5455     #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_GEN2                                      (0xff<<24) // PHY
5456     #define PCIEIP_REG_PDL_CONTROL_3_MAX_TX_FTS_LIMIT_LONG_GEN2_SHIFT                                24
5457 #define PCIEIP_REG_PDL_CONTROL_4                                                                     0x001010UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5458     #define PCIEIP_REG_PDL_CONTROL_4_NPD_FC_INIT                                                     (0xfff<<0) // DL: Non-Posted Data for INITFC
5459     #define PCIEIP_REG_PDL_CONTROL_4_NPD_FC_INIT_SHIFT                                               0
5460     #define PCIEIP_REG_PDL_CONTROL_4_PD_FC_INIT                                                      (0xfff<<12) // DL: Posted Data for INITFC
5461     #define PCIEIP_REG_PDL_CONTROL_4_PD_FC_INIT_SHIFT                                                12
5462     #define PCIEIP_REG_PDL_CONTROL_4_NPH_FC_INIT                                                     (0xff<<24) // DL: Non Posted Header for INITFC
5463     #define PCIEIP_REG_PDL_CONTROL_4_NPH_FC_INIT_SHIFT                                               24
5464 #define PCIEIP_REG_PDL_CONTROL_5                                                                     0x001014UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5465     #define PCIEIP_REG_PDL_CONTROL_5_PH_INIT                                                         (0xff<<0) // DL: Posted Header for INITFC
5466     #define PCIEIP_REG_PDL_CONTROL_5_PH_INIT_SHIFT                                                   0
5467     #define PCIEIP_REG_PDL_CONTROL_5_DOWNSTREAM_PORT                                                 (0x1<<8) // This bit is set to '1' if IP is configured as a Downstream Port.
5468     #define PCIEIP_REG_PDL_CONTROL_5_DOWNSTREAM_PORT_SHIFT                                           8
5469     #define PCIEIP_REG_PDL_CONTROL_5_GLOOPBACK                                                       (0x1<<9) //
5470     #define PCIEIP_REG_PDL_CONTROL_5_GLOOPBACK_SHIFT                                                 9
5471     #define PCIEIP_REG_PDL_CONTROL_5_MIN_INITFC1                                                     (0xf<<10) // DL: Minimum number of InitFC1 sets (i.e. P, NP, CPL) that DL will send before switching to InitFC2.
5472     #define PCIEIP_REG_PDL_CONTROL_5_MIN_INITFC1_SHIFT                                               10
5473     #define PCIEIP_REG_PDL_CONTROL_5_UNUSED_1                                                        (0x3ffff<<14) // Reserved
5474     #define PCIEIP_REG_PDL_CONTROL_5_UNUSED_1_SHIFT                                                  14
5475 #define PCIEIP_REG_PDL_CONTROL_6                                                                     0x001018UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5476     #define PCIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_COMNCLK_GEN3                                       (0xff<<0) // Gen3 N_FTS value advertised when in common clock mode.
5477     #define PCIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_COMNCLK_GEN3_SHIFT                                 0
5478     #define PCIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_DIFFCLK_GEN3                                       (0xff<<8) // Gen3 N_FTS value advertised when not in common clock mode.
5479     #define PCIEIP_REG_PDL_CONTROL_6_REG_ADV_NFTS_DIFFCLK_GEN3_SHIFT                                 8
5480     #define PCIEIP_REG_PDL_CONTROL_6_UNUSED_1                                                        (0xffff<<16) // Reserved - always write 0
5481     #define PCIEIP_REG_PDL_CONTROL_6_UNUSED_1_SHIFT                                                  16
5482 #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3                                                              0x00101cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5483     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_SW_REPLAY_TIMER_GEN3                                     (0xfff<<0) // Software Gen3 value for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is selected.
5484     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_SW_REPLAY_TIMER_GEN3_SHIFT                               0
5485     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_HW_REPLAY_INTDEL_GEN3                                    (0x1ff<<12) // Hardware Gen3 internal delay for the replay timeout in symbol time. This delay is only applied to the hardware-calculated replay timeout.
5486     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_HW_REPLAY_INTDEL_GEN3_SHIFT                              12
5487     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_UNUSED_1                                                 (0x7ff<<21) // Reserved - always write 0
5488     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN3_UNUSED_1_SHIFT                                           21
5489 #define PCIEIP_REG_DL_ACK_LAT_GEN3                                                                   0x001020UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5490     #define PCIEIP_REG_DL_ACK_LAT_GEN3_SW_ACK_LAT_GEN3                                               (0xfff<<0) // Software Gen3 AckNak latency timer value in symbol time.
5491     #define PCIEIP_REG_DL_ACK_LAT_GEN3_SW_ACK_LAT_GEN3_SHIFT                                         0
5492     #define PCIEIP_REG_DL_ACK_LAT_GEN3_HW_ACK_LAT_ADJ_GEN3                                           (0xff<<12) // Hardware Gen3 AckNak latency adjustment in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an ACK latency according to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so that the real Ack latency is close to the value in spec.
5493     #define PCIEIP_REG_DL_ACK_LAT_GEN3_HW_ACK_LAT_ADJ_GEN3_SHIFT                                     12
5494     #define PCIEIP_REG_DL_ACK_LAT_GEN3_SW_UPDFC_LAT_GEN3                                             (0xfff<<20) // Software Gen3 UpdateFC latency value in symbol time.
5495     #define PCIEIP_REG_DL_ACK_LAT_GEN3_SW_UPDFC_LAT_GEN3_SHIFT                                       20
5496 #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1                                                              0x001024UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5497     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_SW_REPLAY_TIMER_GEN1                                     (0xfff<<0) // Software Gen1 value for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is selected.
5498     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_SW_REPLAY_TIMER_GEN1_SHIFT                               0
5499     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_HW_REPLAY_INTDEL_GEN1                                    (0x1ff<<12) // Hardware Gen1 internal delay for the replay timeout in symbol time. This delay is only applied to the hardware-calculated replay timeout.
5500     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN1_HW_REPLAY_INTDEL_GEN1_SHIFT                              12
5501 #define PCIEIP_REG_PDL_CONTROL_10                                                                    0x001028UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5502     #define PCIEIP_REG_PDL_CONTROL_10_UNUSED0                                                        (0xff<<0) //
5503     #define PCIEIP_REG_PDL_CONTROL_10_UNUSED0_SHIFT                                                  0
5504     #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_RXENABLE                                                 (0x1<<8) // Enable checksum feature on receiving side
5505     #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_RXENABLE_SHIFT                                           8
5506     #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_ENABLE                                                   (0x1<<9) // Enable checksum feature on transmit side
5507     #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_ENABLE_SHIFT                                             9
5508     #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_WRITE_NULLIFY                                            (0x1<<10) // DL: If set and DL has detected checksum error earlier, DL will nullify all subsequence memory write request whose pcie_cksum_err bit is not set.
5509     #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_WRITE_NULLIFY_SHIFT                                      10
5510     #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_NULLIFY                                                  (0x1<<11) // If set DL will nullify the first packet with bad checksum. Subsequent MWR packets will get nullified if DL_CS_WRITE_NULLIFY is set, regardless if they have bad or good checksum If this bit is clear and checksum mismatch occurs, Error attention will be set, but no packet will get nullified.
5511     #define PCIEIP_REG_PDL_CONTROL_10_DL_CS_NULLIFY_SHIFT                                            11
5512     #define PCIEIP_REG_PDL_CONTROL_10_DL_LO_WATERMARK                                                (0x3ff<<12) // If DLP2TLP buffer fills up to the high water mark value, DL will send a flag to TL restraining it from sending more Posted FC updates, potentially stall DMA requests, until the buffer falls below the Low watermark level.
5513     #define PCIEIP_REG_PDL_CONTROL_10_DL_LO_WATERMARK_SHIFT                                          12
5514     #define PCIEIP_REG_PDL_CONTROL_10_DL_HI_WATERMARK                                                (0x3ff<<22) // If DLP2TLP buffer fills up to this high water mark value, DL will send a flag to TL restraining it from sending more Posted FC updates , potentially stall DMA requests, until the flag de-asserted.
5515     #define PCIEIP_REG_PDL_CONTROL_10_DL_HI_WATERMARK_SHIFT                                          22
5516 #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2                                                              0x00102cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5517     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_SW_REPLAY_TIMER_GEN2                                     (0xfff<<0) // Software Gen2 value for the replay timeout in symbol time. It is selected if bit sw_replay_timer_sel is set to '1'; otherwise, the hardware-calculated value is selected.
5518     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_SW_REPLAY_TIMER_GEN2_SHIFT                               0
5519     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_HW_REPLAY_INTDEL_GEN2                                    (0x1ff<<12) // Hardware Gen2 internal delay for the replay timeout in symbol time. This delay is only applied to the hardware-calculated replay timeout.
5520     #define PCIEIP_REG_DL_REPLAY_TIMER_GEN2_HW_REPLAY_INTDEL_GEN2_SHIFT                              12
5521 #define PCIEIP_REG_DL_ACK_LAT_GEN1                                                                   0x001030UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5522     #define PCIEIP_REG_DL_ACK_LAT_GEN1_SW_ACK_LAT_GEN1                                               (0xfff<<0) // Software Gen1 AckNak latency timer value in symbol time.
5523     #define PCIEIP_REG_DL_ACK_LAT_GEN1_SW_ACK_LAT_GEN1_SHIFT                                         0
5524     #define PCIEIP_REG_DL_ACK_LAT_GEN1_HW_ACK_LAT_ADJ_GEN1                                           (0xff<<12) // Hardware Gen1 AckNak latency adjustment in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an ACK latency according to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so that the real Ack latency is close to the value in spec.
5525     #define PCIEIP_REG_DL_ACK_LAT_GEN1_HW_ACK_LAT_ADJ_GEN1_SHIFT                                     12
5526     #define PCIEIP_REG_DL_ACK_LAT_GEN1_SW_UPDFC_LAT_GEN1                                             (0xfff<<20) // Software Gen1 UpdateFC latency value in symbol time.
5527     #define PCIEIP_REG_DL_ACK_LAT_GEN1_SW_UPDFC_LAT_GEN1_SHIFT                                       20
5528 #define PCIEIP_REG_DL_ACK_LAT_GEN2                                                                   0x001034UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5529     #define PCIEIP_REG_DL_ACK_LAT_GEN2_SW_ACK_LAT_GEN2                                               (0xfff<<0) // Software Gen2 AckNak latency timer value in symbol time.
5530     #define PCIEIP_REG_DL_ACK_LAT_GEN2_SW_ACK_LAT_GEN2_SHIFT                                         0
5531     #define PCIEIP_REG_DL_ACK_LAT_GEN2_HW_ACK_LAT_ADJ_GEN2                                           (0xff<<12) // Hardware Gen2 AckNak latency adjustment in symbol time. Depending on speed and Max Packet Size (MPS), hardware automatically generates an ACK latency according to the table in PCIE spec. Since the actual internal delay of the design is larger than the spec internal delay, this adjustment is subtracted out from the hardware-calculated value so that the real Ack latency is close to the value in spec.
5532     #define PCIEIP_REG_DL_ACK_LAT_GEN2_HW_ACK_LAT_ADJ_GEN2_SHIFT                                     12
5533     #define PCIEIP_REG_DL_ACK_LAT_GEN2_SW_UPDFC_LAT_GEN2                                             (0xfff<<20) // Software Gen2 UpdateFC latency value in symbol time.
5534     #define PCIEIP_REG_DL_ACK_LAT_GEN2_SW_UPDFC_LAT_GEN2_SHIFT                                       20
5535 #define PCIEIP_REG_PDL_CONTROL_14                                                                    0x001038UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5536     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_EXT_SEL_0                                                (0x1fff<<0) // This maps 8k of addresses that can be used to extend the debug bus0. First 2k belongs to PHY Second 2K belongs to Dl Third 2K belongs to TL The last 2k is left for Vaux
5537     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_EXT_SEL_0_SHIFT                                          0
5538     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_EXT_SEL_1                                                (0x1fff<<13) // This maps 8k of addresses that can be used to extend the debug bus1. First 2k belongs to PHY Second 2K belongs to Dl Third 2K belongs to TL The last 2k is left for Vaux
5539     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_EXT_SEL_1_SHIFT                                          13
5540     #define PCIEIP_REG_PDL_CONTROL_14_UNUSED_1                                                       (0x1<<26) //
5541     #define PCIEIP_REG_PDL_CONTROL_14_UNUSED_1_SHIFT                                                 26
5542     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_SEL_0                                                (0x3<<27) // This selects the source that drives the debug bus 1 when debug access is controlled by grc
5543     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_SEL_0_SHIFT                                          27
5544     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_SEL_1                                                (0x3<<29) // This selects the source that drives the debug bus 1 when debug access is controlled by grc
5545     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_SEL_1_SHIFT                                          29
5546     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_ENA                                                  (0x1<<31) // Enable GRC to control the driving of the debug bus. When this bit is set, it provides the capability to expand the debug bus
5547     #define PCIEIP_REG_PDL_CONTROL_14_DEBUG_GRC_ENA_SHIFT                                            31
5548 #define PCIEIP_REG_DLATTN_VEC                                                                        0x001040UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5549     #define PCIEIP_REG_DLATTN_VEC_DL_CHKSUM_ERR                                                      (0x1<<0) // DL: Assert when DL detects checksum error while transmitting a TLP. Generates pcie_err_att status to chip. This status is not cleared till a 1 is written to it.
5550     #define PCIEIP_REG_DLATTN_VEC_DL_CHKSUM_ERR_SHIFT                                                0
5551     #define PCIEIP_REG_DLATTN_VEC_DL_D2TBUF_OFLOW_ERR                                                (0x1<<1) // Signal DLP2TLP buffer on receive side is overflow.
5552     #define PCIEIP_REG_DLATTN_VEC_DL_D2TBUF_OFLOW_ERR_SHIFT                                          1
5553     #define PCIEIP_REG_DLATTN_VEC_DLP2TLP_PARITY_ERROR                                               (0x1<<2) // Set if DLP2TLP buffer detects parity error
5554     #define PCIEIP_REG_DLATTN_VEC_DLP2TLP_PARITY_ERROR_SHIFT                                         2
5555     #define PCIEIP_REG_DLATTN_VEC_REPLAY_ADDRESS_PARITY_ERROR                                        (0x1<<3) // Set if Replay Address buffer detects parity error
5556     #define PCIEIP_REG_DLATTN_VEC_REPLAY_ADDRESS_PARITY_ERROR_SHIFT                                  3
5557     #define PCIEIP_REG_DLATTN_VEC_REPLAY_WRAPPER_PARITY_ERROR                                        (0x1<<4) // Set if Replay Wrapper has parity error
5558     #define PCIEIP_REG_DLATTN_VEC_REPLAY_WRAPPER_PARITY_ERROR_SHIFT                                  4
5559     #define PCIEIP_REG_DLATTN_VEC_DL_CORRECTABLE_ERROR                                               (0x1<<5) // Assert when Correctable Error counter reach max CORR_ERR_REG_MAX value defined at bit [27:18] of reg 0x1008. The counter is incremented if there is any error associate with LCRC mismatch in DLP, DLL, PHY on receiving side.
5560     #define PCIEIP_REG_DLATTN_VEC_DL_CORRECTABLE_ERROR_SHIFT                                         5
5561     #define PCIEIP_REG_DLATTN_VEC_DE_FRAMING_ERROR                                                   (0x1<<6) // Indicate un-decoded condition in de-framing logic
5562     #define PCIEIP_REG_DLATTN_VEC_DE_FRAMING_ERROR_SHIFT                                             6
5563     #define PCIEIP_REG_DLATTN_VEC_DLP_ERROR_STATUS                                                   (0x1<<7) // Assert when LCRC mismatch and sequence number is correct
5564     #define PCIEIP_REG_DLATTN_VEC_DLP_ERROR_STATUS_SHIFT                                             7
5565     #define PCIEIP_REG_DLATTN_VEC_DLP_INCORRECT                                                      (0x1<<8) // RX: Indicate DLP is too long or TLP dataphases is more than max payload.
5566     #define PCIEIP_REG_DLATTN_VEC_DLP_INCORRECT_SHIFT                                                8
5567     #define PCIEIP_REG_DLATTN_VEC_TLPBUFRDERR                                                        (0x1<<9) // RX: Asserted when one or more TLP does have either incorrect LCRC, sequence number, or ending with EDB
5568     #define PCIEIP_REG_DLATTN_VEC_TLPBUFRDERR_SHIFT                                                  9
5569     #define PCIEIP_REG_DLATTN_VEC_REPLAY_SEQUENCE_OVERRUN                                            (0x1<<10) // REPLAY SEQUENCE is overrun
5570     #define PCIEIP_REG_DLATTN_VEC_REPLAY_SEQUENCE_OVERRUN_SHIFT                                      10
5571     #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_ACK                                                      (0x1<<11) // Set if DL detects impossible condition to de-allocate entries in Replay Buffer.
5572     #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_ACK_SHIFT                                                11
5573     #define PCIEIP_REG_DLATTN_VEC_REPLAY_BUFFER_OVERRUN                                              (0x1<<12) // Set if Replay buffer is overwritten
5574     #define PCIEIP_REG_DLATTN_VEC_REPLAY_BUFFER_OVERRUN_SHIFT                                        12
5575     #define PCIEIP_REG_DLATTN_VEC_REPLAY_NUMBER_ROLL_OVER                                            (0x1<<13) // Set if number of Replay reaches max value. Default of this value is 4 times.
5576     #define PCIEIP_REG_DLATTN_VEC_REPLAY_NUMBER_ROLL_OVER_SHIFT                                      13
5577     #define PCIEIP_REG_DLATTN_VEC_REPLAY_TIMEOUT                                                     (0x1<<14) // Set if Replay Timer expired without receiving any ACK or NACK from RC
5578     #define PCIEIP_REG_DLATTN_VEC_REPLAY_TIMEOUT_SHIFT                                               14
5579     #define PCIEIP_REG_DLATTN_VEC_DL_TX_UNDRUN                                                       (0x1<<15) // DL TX Underrun. This bit is set to '1' if underrun occurs at the DL/PL TX interface.
5580     #define PCIEIP_REG_DLATTN_VEC_DL_TX_UNDRUN_SHIFT                                                 15
5581     #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_STATUS                                                   (0x1<<16) // Detect DLLP with mismatched CRC-16 on receiving side.
5582     #define PCIEIP_REG_DLATTN_VEC_DLL_ERROR_STATUS_SHIFT                                             16
5583     #define PCIEIP_REG_DLATTN_VEC_DLL_PE_INIT_STATUS                                                 (0x1<<17) // Receive UPDATEFC DLLP when DL has not completed FC_INIT1 state, or receive INITFC1 DLLP when DL has already finished the FC initialization.
5584     #define PCIEIP_REG_DLATTN_VEC_DLL_PE_INIT_STATUS_SHIFT                                           17
5585     #define PCIEIP_REG_DLATTN_VEC_UNUSED_3                                                           (0x1<<18) //
5586     #define PCIEIP_REG_DLATTN_VEC_UNUSED_3_SHIFT                                                     18
5587     #define PCIEIP_REG_DLATTN_VEC_TLP_INCORRECT                                                      (0x1<<19) // This signal is set to '1' when the TLP length that TL indicates to DL does not match to the actual length of the TLP transmitted across the TL/DL TX interface.
5588     #define PCIEIP_REG_DLATTN_VEC_TLP_INCORRECT_SHIFT                                                19
5589     #define PCIEIP_REG_DLATTN_VEC_TLP_2_DLPBUF_PARITY_ERROR                                          (0x1<<20) // Set if TLP2DLP Buf has parity error
5590     #define PCIEIP_REG_DLATTN_VEC_TLP_2_DLPBUF_PARITY_ERROR_SHIFT                                    20
5591 #define PCIEIP_REG_DL_ATTN_MASK                                                                      0x001044UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5592     #define PCIEIP_REG_DL_ATTN_MASK_MASK_FOR_DL_ATTENTIONS                                           (0x1fffff<<0) // If set mask out DL attentions specified in register 0x1040
5593     #define PCIEIP_REG_DL_ATTN_MASK_MASK_FOR_DL_ATTENTIONS_SHIFT                                     0
5594     #define PCIEIP_REG_DL_ATTN_MASK_UNUSED_1                                                         (0x7ff<<21) //
5595     #define PCIEIP_REG_DL_ATTN_MASK_UNUSED_1_SHIFT                                                   21
5596 #define PCIEIP_REG_DL_STATUS                                                                         0x001048UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5597     #define PCIEIP_REG_DL_STATUS_CORR_ERR_REG                                                        (0x3ff<<0) // Total number of errors within 256us due to CRC16, LCRC, sequence number, or PL RX error.
5598     #define PCIEIP_REG_DL_STATUS_CORR_ERR_REG_SHIFT                                                  0
5599     #define PCIEIP_REG_DL_STATUS_REPLAY_ALM_FULL                                                     (0x1<<10) // If set, indicates Replay buffer is almost full. Replay available entries are two or less than two
5600     #define PCIEIP_REG_DL_STATUS_REPLAY_ALM_FULL_SHIFT                                               10
5601     #define PCIEIP_REG_DL_STATUS_UNUSED0                                                             (0x3<<11) //
5602     #define PCIEIP_REG_DL_STATUS_UNUSED0_SHIFT                                                       11
5603     #define PCIEIP_REG_DL_STATUS_PHYLINKUP                                                           (0x1<<13) // If set, indicates link is trained
5604     #define PCIEIP_REG_DL_STATUS_PHYLINKUP_SHIFT                                                     13
5605     #define PCIEIP_REG_DL_STATUS_DL_ACTIVE                                                           (0x1<<14) // If set, signal DL finishes both INITFC1 and INITFC2
5606     #define PCIEIP_REG_DL_STATUS_DL_ACTIVE_SHIFT                                                     14
5607     #define PCIEIP_REG_DL_STATUS_DL_INIT                                                             (0x1<<15) // If set, DL is doing VC0 FC initialization
5608     #define PCIEIP_REG_DL_STATUS_DL_INIT_SHIFT                                                       15
5609     #define PCIEIP_REG_DL_STATUS_RESERVED                                                            (0xffff<<16) //
5610     #define PCIEIP_REG_DL_STATUS_RESERVED_SHIFT                                                      16
5611 #define PCIEIP_REG_DL_TX_CHECKSUM                                                                    0x00104cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5612     #define PCIEIP_REG_DL_TX_CHECKSUM_EXPECTED_TX_CHECKSUM                                           (0xffff<<0) // This field holds the checksum calculated by hardware when checksum error is detected.
5613     #define PCIEIP_REG_DL_TX_CHECKSUM_EXPECTED_TX_CHECKSUM_SHIFT                                     0
5614     #define PCIEIP_REG_DL_TX_CHECKSUM_ACTUAL_TX_CHECKSUM                                             (0xffff<<16) // This field holds the checksum received from User Interface when checksum error is detected.
5615     #define PCIEIP_REG_DL_TX_CHECKSUM_ACTUAL_TX_CHECKSUM_SHIFT                                       16
5616 #define PCIEIP_REG_DL_MAX_UPDFC                                                                      0x001050UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5617     #define PCIEIP_REG_DL_MAX_UPDFC_MAX_UPDFC_NORMAL                                                 (0x3f<<0) // DL: Maximum time in microseconds that DL has to send at least one UpdateFC DLLP for each FC credit type when Extended Sync bit is '0'.
5618     #define PCIEIP_REG_DL_MAX_UPDFC_MAX_UPDFC_NORMAL_SHIFT                                           0
5619     #define PCIEIP_REG_DL_MAX_UPDFC_MAX_UPDFC_EXT                                                    (0xff<<6) // DL: Maximum time in microseconds that DL has to send at least one UpdateFC DLLP for each FC credit type when Extended Sync bit is '1'.
5620     #define PCIEIP_REG_DL_MAX_UPDFC_MAX_UPDFC_EXT_SHIFT                                              6
5621     #define PCIEIP_REG_DL_MAX_UPDFC_RESERVED                                                         (0x3ffff<<14) //
5622     #define PCIEIP_REG_DL_MAX_UPDFC_RESERVED_SHIFT                                                   14
5623 #define PCIEIP_REG_DL_T2D_THRS                                                                       0x001054UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5624     #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_THRS_ENA                                                   (0x1<<0) // T2D FIFO Threshold Enable. This bit is set to '1' to enable the T2D FIFO threshold feature. Depending on TL, DL bus width and clock relationship, after the first data in T2D FIFO becomes available, next data may not be available as fast as DL can retrieve. This can cause data underrun at the DL/PL TX interface. To prevent this underrun issue, when this bit is set, DL will start reading data out of T2D FIFO when one of below conditions occurs: - TLP ends in one entry. - The number of valid entries in T2D FIFO is greater than or equal to dl_t2d_count_thrs. - DL has waited at least dl_t2d_time_thrs clock cycles. This is neccessary in case the TLP size is smaller than the count threshold.
5625     #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_THRS_ENA_SHIFT                                             0
5626     #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_COUNT_THRS                                                 (0x7<<1) // T2D FIFO Count Threshold. This is the number of valid data in T2D FIFO before DL state machine starts TLP transfer.
5627     #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_COUNT_THRS_SHIFT                                           1
5628     #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_TIME_THRS                                                  (0xf<<4) // T2D FIFO Time Threshold. When T2D FIFO data becomes available, this is the number of clock cycles that DL state machine will wait before starting TLP transfer.
5629     #define PCIEIP_REG_DL_T2D_THRS_DL_T2D_TIME_THRS_SHIFT                                            4
5630     #define PCIEIP_REG_DL_T2D_THRS_RESERVED                                                          (0xffffff<<8) //
5631     #define PCIEIP_REG_DL_T2D_THRS_RESERVED_SHIFT                                                    8
5632 #define PCIEIP_REG_DL_FIFO_TEST                                                                      0x001058UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5633     #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE                                              (0x3ff<<0) // Replay FIFO Test Size. When bit replayfifo_testsize_sel is set to '1', this value is used as the Replay FIFO size. This value must be set to less than or equal to the actual FIFO size. It is for simulation purpose only.
5634     #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_SHIFT                                        0
5635     #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE                                                 (0x3ff<<10) // D2T FIFO Test Size. When bit d2tfifo_testsize_sel is set to '1', this value is used as the D2T FIFO size. This value must be set to less than or equal to the actual FIFO size. Furthermore, if DL and TL are asynchronous, this value must be a power of 2. It is for simulation purpose only.
5636     #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE_SHIFT                                           10
5637     #define PCIEIP_REG_DL_FIFO_TEST_RESERVED                                                         (0x3ff<<20) //
5638     #define PCIEIP_REG_DL_FIFO_TEST_RESERVED_SHIFT                                                   20
5639     #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_SEL                                          (0x1<<30) // Replay FIFO Test Size Select. When this bit is set to '1', the value in replayfifo_testsize will be used as Replay FIFO size. This is for simulation purpose only.
5640     #define PCIEIP_REG_DL_FIFO_TEST_REPLAYFIFO_TESTSIZE_SEL_SHIFT                                    30
5641     #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE_SEL                                             (0x1<<31) // D2T FIFO Test Size Select. When this bit is set to '1', the value in d2tfifo_testsize will be used as D2T FIFO size. This is for simulation purpose only.
5642     #define PCIEIP_REG_DL_FIFO_TEST_D2TFIFO_TESTSIZE_SEL_SHIFT                                       31
5643 #define PCIEIP_REG_DL_SPARE0                                                                         0x00105cUL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0
5644 #define PCIEIP_REG_MDIO_ADDR                                                                         0x001100UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5645     #define PCIEIP_REG_MDIO_ADDR_ADR                                                                 (0xffff<<0) // This value controls the register index sent to on the MDIO bus connected to the PCIE Serdes block.
5646     #define PCIEIP_REG_MDIO_ADDR_ADR_SHIFT                                                           0
5647     #define PCIEIP_REG_MDIO_ADDR_PORT                                                                (0xf<<16) // This value controls port address sent to on the MDIO bus connected to the PCIE Serdes block.
5648     #define PCIEIP_REG_MDIO_ADDR_PORT_SHIFT                                                          16
5649     #define PCIEIP_REG_MDIO_ADDR_CMD                                                                 (0xfff<<20) // A write of '0' to these bits causes no action and allows the address to be programmed in preparation for a write. A write of '1' on these bits initiates a read at the address and port specified.
5650     #define PCIEIP_REG_MDIO_ADDR_CMD_SHIFT                                                           20
5651 #define PCIEIP_REG_MDIO_WR_DATA                                                                      0x001104UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5652     #define PCIEIP_REG_MDIO_WR_DATA_WDATA_REG                                                        (0x7fffffff<<0) // This value will be the register data for write cycles.
5653     #define PCIEIP_REG_MDIO_WR_DATA_WDATA_REG_SHIFT                                                  0
5654     #define PCIEIP_REG_MDIO_WR_DATA_CMD                                                              (0x1<<31) // This bit must be written as a '1' to initiate write cycle based ont the data in bits [15:0] and the mdio_addr value. When the write has completed, this bit will read as '0'.
5655     #define PCIEIP_REG_MDIO_WR_DATA_CMD_SHIFT                                                        31
5656 #define PCIEIP_REG_MDIO_RD_DATA                                                                      0x001108UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5657     #define PCIEIP_REG_MDIO_RD_DATA_RDATA_REG                                                        (0x7fffffff<<0) // After a read has been requested in the mdio_addr register, this area will return the MDIO data. This field is only valid if the CMD field is '1'.
5658     #define PCIEIP_REG_MDIO_RD_DATA_RDATA_REG_SHIFT                                                  0
5659     #define PCIEIP_REG_MDIO_RD_DATA_CMD                                                              (0x1<<31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which case, this bit will read as '1'. This bit is automatically cleared by a write to the mdio_addr register.
5660     #define PCIEIP_REG_MDIO_RD_DATA_CMD_SHIFT                                                        31
5661 #define PCIEIP_REG_ATE_TLP_HDR_0                                                                     0x00110cUL //Access:RW   DataWidth:0x20  In ATE test mode this register together with ate_tlp_hdr_1, ate_tlp_hdr_2, and ate_tlp_hdr_3 form the 128-bit header information that is sent to TL logic to build a TLP. The header information is passed to TL as is except the TAG (i.e. bits 47:40 in a non-posted request) and RTAG (i.e. bits 79:72 in a Completion request), which are incremented by one after each packet transfer.  Chips: BB_A0 BB_B0
5662 #define PCIEIP_REG_ATE_TLP_HDR_1                                                                     0x001110UL //Access:RW   DataWidth:0x20  When a TLP is generated in ATE test mode, this register holds bits [63:32] of the header bus.  Chips: BB_A0 BB_B0
5663 #define PCIEIP_REG_ATE_TLP_HDR_2                                                                     0x001114UL //Access:RW   DataWidth:0x20  When a TLP is generated in ATE test mode, this register holds bits [95:64] of the header bus.  Chips: BB_A0 BB_B0
5664 #define PCIEIP_REG_ATE_TLP_HDR_3                                                                     0x001118UL //Access:RW   DataWidth:0x20  When a TLP is generated in ATE test mode, this register holds bits [127:96] of the header bus.  Chips: BB_A0 BB_B0
5665 #define PCIEIP_REG_ATE_TLP_CFG                                                                       0x00111cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5666     #define PCIEIP_REG_ATE_TLP_CFG_ATE_TLP_CNT                                                       (0xff<<0) // ATE TLP Count. Specify the number of TLP's to be transferred. When ate_tlp_go is set to '1', the value in this field is loaded into an internal counter that is decremented by one as each TLP is completed. Reading this register always returns the internal counter.
5667     #define PCIEIP_REG_ATE_TLP_CFG_ATE_TLP_CNT_SHIFT                                                 0
5668     #define PCIEIP_REG_ATE_TLP_CFG_ATE_NULLIFY                                                       (0x1<<8) // ATE TLP Nullify. When this bit is set to '1', an internal signal is asserted together with the last data word to nullify the transaction (i.e. emulate user_tx_nullify).
5669     #define PCIEIP_REG_ATE_TLP_CFG_ATE_NULLIFY_SHIFT                                                 8
5670     #define PCIEIP_REG_ATE_TLP_CFG_ATE_PAT_SEL                                                       (0x7<<9) // ATE Pattern Select.
5671     #define PCIEIP_REG_ATE_TLP_CFG_ATE_PAT_SEL_SHIFT                                                 9
5672     #define PCIEIP_REG_ATE_TLP_CFG_UNUSED0                                                           (0xf<<12) //
5673     #define PCIEIP_REG_ATE_TLP_CFG_UNUSED0_SHIFT                                                     12
5674     #define PCIEIP_REG_ATE_TLP_CFG_ATE_PAT_SEED                                                      (0xff<<16) // ATE Pattern Seed. This field holds the first data byte of the first TLP payload generated in ATE test mode. The remaining data bytes are generated based on the setting of ate_pat_sel.
5675     #define PCIEIP_REG_ATE_TLP_CFG_ATE_PAT_SEED_SHIFT                                                16
5676 #define PCIEIP_REG_ATE_TLP_CTL                                                                       0x001120UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5677     #define PCIEIP_REG_ATE_TLP_CTL_ATE_TLP_GO                                                        (0x1<<0) // ATE TLP Go bit. When this bit is set to '1', the TX User Interface is bypassed and internal logic generates packets to TL logic. After all packets are transferred, this bit is reset to '0' by hardware.
5678     #define PCIEIP_REG_ATE_TLP_CTL_ATE_TLP_GO_SHIFT                                                  0
5679     #define PCIEIP_REG_ATE_TLP_CTL_UNUSED0                                                           (0x7<<1) //
5680     #define PCIEIP_REG_ATE_TLP_CTL_UNUSED0_SHIFT                                                     1
5681     #define PCIEIP_REG_ATE_TLP_CTL_REG_TRX_CLR_RX_TLP_SB                                             (0x1<<4) // Clear RX TLP scoreboard logic bit. SW needs to read trx_reg_sb_op_done (bit[31]). If trx_reg_sb_op_done register value is 1, it indicates that HW is done comparing RX TLPs. SW needs to write reg_trx_clr_rx_tlp_sb to '1' which will clear trx_reg_sb_op_done (bit[31]), trx_reg_err_tlp_num(bits[27:20]), trx_reg_data_mismatch (bit[17]) and trx_reg_hdr_mismatch (bit[16]) registers. It is a self clearing bit.
5682     #define PCIEIP_REG_ATE_TLP_CTL_REG_TRX_CLR_RX_TLP_SB_SHIFT                                       4
5683     #define PCIEIP_REG_ATE_TLP_CTL_UNUSED1                                                           (0x7ff<<5) //
5684     #define PCIEIP_REG_ATE_TLP_CTL_UNUSED1_SHIFT                                                     5
5685     #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_HDR_MISMATCH                                              (0x1<<16) // Header Mismatch. A value of '1' indicates that transmitted TLP header does not match with received TLP header. This bit can be cleared by writing '1' to reg_trx_clr_rx_tlp_sb (bit[4]).
5686     #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_HDR_MISMATCH_SHIFT                                        16
5687     #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_DATA_MISMATCH                                             (0x1<<17) // Data Mismatch. A value of '1' indicates that transmitted TLP data do not match with received TLP data. This bit can be cleared by writing '1' to reg_trx_clr_rx_tlp_sb (bit[4]).
5688     #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_DATA_MISMATCH_SHIFT                                       17
5689     #define PCIEIP_REG_ATE_TLP_CTL_UNUSED2                                                           (0x3<<18) //
5690     #define PCIEIP_REG_ATE_TLP_CTL_UNUSED2_SHIFT                                                     18
5691     #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_ERR_TLP_NUM                                               (0xff<<20) // Indicates erroneous (header/ data mismatch) TLP number. If more than one TLP has an error, value will be 0xF. When an ATE TLP packet transmission is initiated, HW transmits number of TLPs equal to ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). trx_reg_err_tlp_num indicates the number of TLP that has error. This register is cleared by writing '1' to reg_trx_clr_rx_tlp_sb (bit[4]).
5692     #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_ERR_TLP_NUM_SHIFT                                         20
5693     #define PCIEIP_REG_ATE_TLP_CTL_UNUSED3                                                           (0x7<<28) //
5694     #define PCIEIP_REG_ATE_TLP_CTL_UNUSED3_SHIFT                                                     28
5695     #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_SB_OP_DONE                                                (0x1<<31) // Value of '1' indicates that number of TLPs received is equal to number of TLPs transmitted (ATE_TLP_CNT (bits[7:0] of ate_tlp_cfg - offset 0x111c). This register value needs to be ignored until user writes '1' to ATE_TLP_GO (bit[0] of ate_tlp_ctl - offset 0x1120) register.
5696     #define PCIEIP_REG_ATE_TLP_CTL_TRX_REG_SB_OP_DONE_SHIFT                                          31
5697 #define PCIEIP_REG_SERDES_PMI_ADDR                                                                   0x001130UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5698     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_REG_ADDR                                               (0xf<<0) // Register Addr
5699     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_REG_ADDR_SHIFT                                         0
5700     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_BLOCK_ADDR                                             (0xfff<<4) // Block Addr
5701     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_BLOCK_ADDR_SHIFT                                       4
5702     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_LANE_NUM                                               (0x3<<16) // Lane Number
5703     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_LANE_NUM_SHIFT                                         16
5704     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_LANE_OFFSET                                            (0x7<<18) // Offset into each set of 4 lanes
5705     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_LANE_OFFSET_SHIFT                                      18
5706     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_UNICAST_BCAST                                          (0x3f<<21) // Value of 0 indicates unicast and write is per lane. Value 0xF indicates broadcast.
5707     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_UNICAST_BCAST_SHIFT                                    21
5708     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_DEV_ID                                                 (0x1f<<27) // Device ID. Value of 1 for this device.
5709     #define PCIEIP_REG_SERDES_PMI_ADDR_SERDES_DEV_ID_SHIFT                                           27
5710 #define PCIEIP_REG_SERDES_PMI_WDATA                                                                  0x001134UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5711     #define PCIEIP_REG_SERDES_PMI_WDATA_PMI_WDATA_REG                                                (0xffff<<0) // This value will be the register data for write cycles.
5712     #define PCIEIP_REG_SERDES_PMI_WDATA_PMI_WDATA_REG_SHIFT                                          0
5713     #define PCIEIP_REG_SERDES_PMI_WDATA_RESERVED                                                     (0x3fff<<16) // This value will be ignored.
5714     #define PCIEIP_REG_SERDES_PMI_WDATA_RESERVED_SHIFT                                               16
5715     #define PCIEIP_REG_SERDES_PMI_WDATA_RCMD                                                         (0x1<<30) // This bit must be written as a '1' to initiate read cycle to the pmi_addr value. When the read has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time this operation is unpredictable.
5716     #define PCIEIP_REG_SERDES_PMI_WDATA_RCMD_SHIFT                                                   30
5717     #define PCIEIP_REG_SERDES_PMI_WDATA_WCMD                                                         (0x1<<31) // This bit must be written as a '1' to initiate write cycle based on the data in bits [15:0] and the pmi_addr value. When the write has completed, this bit will read as '0'. If both bit 31 and 30 set at the same time this operation is unpredictable.
5718     #define PCIEIP_REG_SERDES_PMI_WDATA_WCMD_SHIFT                                                   31
5719 #define PCIEIP_REG_SERDES_PMI_RDATA                                                                  0x001138UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5720     #define PCIEIP_REG_SERDES_PMI_RDATA_PMI_RDATA_REG                                                (0xffff<<0) // After a read has been requested in the pmi_addr register, this area will return the MDIO data. This field is only valid if the CMD field is '1'.
5721     #define PCIEIP_REG_SERDES_PMI_RDATA_PMI_RDATA_REG_SHIFT                                          0
5722     #define PCIEIP_REG_SERDES_PMI_RDATA_RESERVED                                                     (0x7fff<<16) // Not used.
5723     #define PCIEIP_REG_SERDES_PMI_RDATA_RESERVED_SHIFT                                               16
5724     #define PCIEIP_REG_SERDES_PMI_RDATA_VALID                                                        (0x1<<31) // This bit will read as '0' until a requested read of the PCIE serdes has completed, in which case, this bit will read as '1'. This bit is automatically cleared by a write to the serdes_pmi_wdata register.
5725     #define PCIEIP_REG_SERDES_PMI_RDATA_VALID_SHIFT                                                  31
5726 #define PCIEIP_REG_DL_DBG_0                                                                          0x001400UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5727 #define PCIEIP_REG_DL_DBG_1                                                                          0x001404UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5728 #define PCIEIP_REG_DL_DBG_2                                                                          0x001408UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5729 #define PCIEIP_REG_DL_DBG_3                                                                          0x00140cUL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5730 #define PCIEIP_REG_DL_DBG_4                                                                          0x001410UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5731 #define PCIEIP_REG_DL_DBG_5                                                                          0x001414UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5732 #define PCIEIP_REG_DL_DBG_6                                                                          0x001418UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5733 #define PCIEIP_REG_DL_DBG_7                                                                          0x00141cUL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5734 #define PCIEIP_REG_DL_DBG_8                                                                          0x001420UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5735 #define PCIEIP_REG_DL_DBG_9                                                                          0x001424UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5736 #define PCIEIP_REG_DL_DBG_10                                                                         0x001428UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5737 #define PCIEIP_REG_DL_DBG_11                                                                         0x00142cUL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5738 #define PCIEIP_REG_DL_DBG_12                                                                         0x001430UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5739 #define PCIEIP_REG_DL_DBG_13                                                                         0x001434UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5740 #define PCIEIP_REG_DL_DBG_14                                                                         0x001438UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5741 #define PCIEIP_REG_DL_DBG_15                                                                         0x00143cUL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5742 #define PCIEIP_REG_DL_DBG_16                                                                         0x001440UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5743 #define PCIEIP_REG_DL_DBG_17                                                                         0x001444UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5744 #define PCIEIP_REG_DL_DBG_18                                                                         0x001448UL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5745 #define PCIEIP_REG_DL_DBG_19                                                                         0x00144cUL //Access:R    DataWidth:0x20  DL debug signals.  Chips: BB_A0 BB_B0
5746 #define PCIEIP_REG_REG_PHY_CTL_0                                                                     0x001800UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5747     #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_WIDTH_CHANGE_REQ                                       (0x1<<0) // Request a width change (ie -make the link wider, if possible). Do not assert if the "other side" is not capable of upconfiguration.
5748     #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_WIDTH_CHANGE_REQ_SHIFT                                 0
5749     #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_SPEED_CHANGE_REQ                                       (0x1<<1) // Request a speed change (ie -make the link fast or slower, depending on the advertised speeds).
5750     #define PCIEIP_REG_REG_PHY_CTL_0_DIRECTED_SPEED_CHANGE_REQ_SHIFT                                 1
5751     #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_3                                                        (0x7<<2) // Some of these bits have obsolete uses and should always be written as 0
5752     #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_3_SHIFT                                                  2
5753     #define PCIEIP_REG_REG_PHY_CTL_0_REG_IDLE_TO_RLOCK_ENA                                           (0x1<<5) // Enable the shortcut transition from Config.Complete to Recovery.RcvrLock Software should not change this field while the PCIE link is active.
5754     #define PCIEIP_REG_REG_PHY_CTL_0_REG_IDLE_TO_RLOCK_ENA_SHIFT                                     5
5755     #define PCIEIP_REG_REG_PHY_CTL_0_REG_UPCONFIG_ENA                                                (0x1<<6) // For multi-lane links on a 2.0 compliant core, enable advertisement of the capability to upconfigure the number of lanes in the link.
5756     #define PCIEIP_REG_REG_PHY_CTL_0_REG_UPCONFIG_ENA_SHIFT                                          6
5757     #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_2                                                        (0x1<<7) //
5758     #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_2_SHIFT                                                  7
5759     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_FRAMERR                                            (0x1<<8) // Consider DLLP and TLP framing errors as errors when reporting physical layer errors
5760     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_FRAMERR_SHIFT                                      8
5761     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_NOLOCK                                             (0x1<<9) // Consider loss of bit and symbol lock from the PCIe Serdes as errors reporting physical layer errors
5762     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_NOLOCK_SHIFT                                       9
5763     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_SKEW                                               (0x1<<10) // Consider link skew errors as errors when reporting physical layer errors
5764     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_SKEW_SHIFT                                         10
5765     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFOVER                                            (0x1<<11) // Consider buffer overrun errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
5766     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFOVER_SHIFT                                      11
5767     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFUNDER                                           (0x1<<12) // Consider buffer underrun errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
5768     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_BUFUNDER_SHIFT                                     12
5769     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_DECODE                                             (0x1<<13) // Consider decode errors from the PCIe Serdes as errors when processing ordered sets, DLLPs, and TLPs BUG: do not use in EP/RC Ax cores
5770     #define PCIEIP_REG_REG_PHY_CTL_0_REG_RXERR_IS_DECODE_SHIFT                                       13
5771     #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_1                                                        (0x3<<14) //
5772     #define PCIEIP_REG_REG_PHY_CTL_0_UNUSED_1_SHIFT                                                  14
5773     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_POL                                               (0x1<<16) // If set, all symbols of the Modified Compliance Pattern must be of the same polarity (no mixed polarity) for the receiver to lock
5774     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_POL_SHIFT                                         16
5775     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_ERR                                               (0x1<<17) // If set, both error symbols must match in the received Modified Compliance Pattern before the value is reported
5776     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_MATCH_ERR_SHIFT                                         17
5777     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_EXIT                                                    (0x1<<18) // Directed exit from generating the Modified Compliance Pattern in Polling.Compliance if the Enter Compliance bit of the Link Control 2 register is not set
5778     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_EXIT_SHIFT                                              18
5779     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_SIGDET_EXIT                                             (0x1<<19) // Allows exit from Polling.Compliance when generating the Modified Compliance pattern and at least one lane goes to electrical idle
5780     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_SIGDET_EXIT_SHIFT                                       19
5781     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_FORCE_ENTRY                                             (0x1<<20) // Forces entry to Polling.Compliance from Polling.Active. This also causes the Compliance Receive bit in the outgoing TS1s to be set in Polling.Active. After entry to Polling.Compliance, the Modified Compliance Pattern is generated instead of the legacy compliance pattern
5782     #define PCIEIP_REG_REG_PHY_CTL_0_REG_MCP_FORCE_ENTRY_SHIFT                                       20
5783     #define PCIEIP_REG_REG_PHY_CTL_0_REG_TX_DEEMPH                                                   (0x1<<21) // The value for the Selectable Deemphasis bit set in TS1s in Polling.Active, Loopback, Recovery, and some Configuration states and set in TS2s in Polling.Configuration
5784     #define PCIEIP_REG_REG_PHY_CTL_0_REG_TX_DEEMPH_SHIFT                                             21
5785     #define PCIEIP_REG_REG_PHY_CTL_0_REG_LOCAL_DEEMPH_LO                                             (0x1<<22) // The initial value of the local deemphasis set in the Detect state (this propagates to the PCIe Serdes via the TxDeemph signal. 0 == -6 dB, 1 == -3.5 dB (For Gen3, this is the low bit of the local Tx preset if none received in EQ TS2s.)
5786     #define PCIEIP_REG_REG_PHY_CTL_0_REG_LOCAL_DEEMPH_LO_SHIFT                                       22
5787     #define PCIEIP_REG_REG_PHY_CTL_0_REG_AUTONOMOUS_CHANGE                                           (0x1<<23) // The value for the Autonomous Change bit set in TS1s in the Configuration state when PhyLinkUp is set and set in TS2s in the Recovery state
5788     #define PCIEIP_REG_REG_PHY_CTL_0_REG_AUTONOMOUS_CHANGE_SHIFT                                     23
5789     #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_DETECT                                            (0x1<<24) // Directed transition from Loopback or Polling.Compliance states to Detect state
5790     #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_DETECT_SHIFT                                      24
5791     #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_L0                                                (0x1<<25) // Directed transition from L1 state to Recovery or L2 state to Detect.
5792     #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIRECT_TO_L0_SHIFT                                          25
5793     #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_ELECIDLE                                       (0x1<<26) // Optionally enable the use of electrical idle or inferred electrical ide as a condition for exiting loopback in 2.0 compliant cores.
5794     #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_ELECIDLE_SHIFT                                 26
5795     #define PCIEIP_REG_REG_PHY_CTL_0_REG_DISABLE_SPEED_EI                                            (0x1<<27) // Disable use of electrical idle in Recovery.Speed - only use inferred electrical idle
5796     #define PCIEIP_REG_REG_PHY_CTL_0_REG_DISABLE_SPEED_EI_SHIFT                                      27
5797     #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_IEI                                            (0x1<<28) // For 2.0 compliant systems, default to the optional behavior of exiting Loopback on inferred electrical idle at 2.5 GT/s.
5798     #define PCIEIP_REG_REG_PHY_CTL_0_REG_LPBK_EXIT_ON_IEI_SHIFT                                      28
5799     #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIS_LANE_REVERSAL                                           (0x1<<29) // Disable the ability to compensate for lane reversal in multi-lane links.
5800     #define PCIEIP_REG_REG_PHY_CTL_0_REG_DIS_LANE_REVERSAL_SHIFT                                     29
5801     #define PCIEIP_REG_REG_PHY_CTL_0_REG_ENABLE_RIDLE_SPD_CLR                                        (0x1<<30) // Enable the clearing of directed_speed_change on the transition to Recovery.Idle. This is newly specified for the 2.1 spec in cases where no speed change occurs even though it is directed.
5802     #define PCIEIP_REG_REG_PHY_CTL_0_REG_ENABLE_RIDLE_SPD_CLR_SHIFT                                  30
5803     #define PCIEIP_REG_REG_PHY_CTL_0_GEN2_FEATURES_ENA                                               (0x1<<31) // Enable gen2 features when in 1.1 compliance mode (register 0x4d0, bit 5 is set)
5804     #define PCIEIP_REG_REG_PHY_CTL_0_GEN2_FEATURES_ENA_SHIFT                                         31
5805 #define PCIEIP_REG_REG_PHY_CTL_1                                                                     0x001804UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5806     #define PCIEIP_REG_REG_PHY_CTL_1_REG_FORCE_GEN2_16BIT                                            (0x1<<0) // Force the PIPE interface to be 16-bit, even in Gen 1 Software should not change this field while the PCIE link is active.
5807     #define PCIEIP_REG_REG_PHY_CTL_1_REG_FORCE_GEN2_16BIT_SHIFT                                      0
5808     #define PCIEIP_REG_REG_PHY_CTL_1_REG_DISABLE_COMPLIANCE                                          (0x1<<1) // Disable entry to Polling.Compliance
5809     #define PCIEIP_REG_REG_PHY_CTL_1_REG_DISABLE_COMPLIANCE_SHIFT                                    1
5810     #define PCIEIP_REG_REG_PHY_CTL_1_REG_LANE_POWERDOWN_ENA                                          (0x1<<2) // Enable the PIPE-style powerdown of unused lanes in a multi-lane link.
5811     #define PCIEIP_REG_REG_PHY_CTL_1_REG_LANE_POWERDOWN_ENA_SHIFT                                    2
5812     #define PCIEIP_REG_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC                                     (0x1<<3) // Enable the auxilliary powerdown of unused lanes in a multi-lane link.
5813     #define PCIEIP_REG_REG_PHY_CTL_1_REG_P2_POWERDOWN_ENA_NOSYNC_SHIFT                               3
5814     #define PCIEIP_REG_REG_PHY_CTL_1_REG_FAREND_LPBK_REQ                                             (0x1<<4) // Initiate PL changes required for a far-end loopback
5815     #define PCIEIP_REG_REG_PHY_CTL_1_REG_FAREND_LPBK_REQ_SHIFT                                       4
5816     #define PCIEIP_REG_REG_PHY_CTL_1_REG_COMPL_CFG_DETECT_RST                                        (0x1<<5) // If set, when Detect is entered the compliance configuration that cycles through the rates, deemphasis, and presets is reset back to the first configuration (Gen1).
5817     #define PCIEIP_REG_REG_PHY_CTL_1_REG_COMPL_CFG_DETECT_RST_SHIFT                                  5
5818     #define PCIEIP_REG_REG_PHY_CTL_1_REG_LATE_CLR_DESKEW_BUFS                                        (0x1<<6) // When set, clear the statis deskew buffers on assertion of the internal deskew enable signal rather than clearing the buffers on the deassertion. This prevents the transient misalignment of data at the end of L0 (when transitioning to L0s or L1). When clear, the legacy behaviour is enabled where the static deskew buffers are cleared on deassertion of the internal deskew enable signal.
5819     #define PCIEIP_REG_REG_PHY_CTL_1_REG_LATE_CLR_DESKEW_BUFS_SHIFT                                  6
5820     #define PCIEIP_REG_REG_PHY_CTL_1_REG_EIDL_DLY                                                    (0x1f<<7) // Tuning field to set the delay in clocks for the electrical idle signal (on the PIPE interface) so that EIDL OS appears first if present (0 = 24 clocks, 1 = 1 clock, 2 = 2 clocks, etc up to 23 clocks) Software should not change this field while the PCIE link is active For Ev3 A0 and B0, this field must be written to a value greater than 16.
5821     #define PCIEIP_REG_REG_PHY_CTL_1_REG_EIDL_DLY_SHIFT                                              7
5822     #define PCIEIP_REG_REG_PHY_CTL_1_REG_POWERDOWN_P1PLL_ENA                                         (0x1<<12) // This signal goes to the PCIe Serdes to enable the PLL to power down when all lanes are in L1 If ClkReq is active, this signal is ignored.
5823     #define PCIEIP_REG_REG_PHY_CTL_1_REG_POWERDOWN_P1PLL_ENA_SHIFT                                   12
5824     #define PCIEIP_REG_REG_PHY_CTL_1_REG_COM_FOR_INF_EIDL                                            (0x1<<13) // Enable using lack of received COM instead of lack of received TS2 in Recovery.RcvrCfg for inferred electrical idle. This is to mimic the "Gen2 0.7 spec" functionality
5825     #define PCIEIP_REG_REG_PHY_CTL_1_REG_COM_FOR_INF_EIDL_SHIFT                                      13
5826     #define PCIEIP_REG_REG_PHY_CTL_1_EIE_FTS_MAX                                                     (0x3<<14) // This field programs the number of EIE symbols to send before the first FTS when exiting Tx_L0s in Gen2  b00 : Four EIE symbols are sent b01 : Six EIE symbols are sent (default) b10 : Eight EIE symbols are sent b11 : Eight EIE symbols are sent
5827     #define PCIEIP_REG_REG_PHY_CTL_1_EIE_FTS_MAX_SHIFT                                               14
5828     #define PCIEIP_REG_REG_PHY_CTL_1_REG_RXVALID_FOR_EIE                                             (0x1<<16) // Use valid data as "exit from electrical idle" in the Loopback states
5829     #define PCIEIP_REG_REG_PHY_CTL_1_REG_RXVALID_FOR_EIE_SHIFT                                       16
5830     #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ANY_LANES                                               (0x1<<17) // Declare EIE if any lane has TSx/EIEOS (or IEI if no lane has TSx/EIEOS)
5831     #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ANY_LANES_SHIFT                                         17
5832     #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_SOS                                                 (0x1<<18) // Declare an inferred electrical idel in L0 if no Skip Ordered Set (SOS) is received in any 128 us interval. See comments for bit 19 of this register
5833     #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_SOS_SHIFT                                           18
5834     #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_UPDFC                                               (0x1<<19) // Declare an inferred electrical idle in L0 if no UpdateFC is received in any 128 us interval. Can be combined with bit 18 of this register. In that case, not receiving both an UpdateFC or a Skip Ordered Set within the 128 us interval is considered an inferred electrical idle
5835     #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_ENA_UPDFC_SHIFT                                         19
5836     #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_FILTER_MAX                                              (0xf<<20) // The depth of the inferred electrical idle filter used to "deskew" the detection of ordered sets.
5837     #define PCIEIP_REG_REG_PHY_CTL_1_REG_IEI_FILTER_MAX_SHIFT                                        20
5838     #define PCIEIP_REG_REG_PHY_CTL_1_UNUSED_1                                                        (0x1<<24) //
5839     #define PCIEIP_REG_REG_PHY_CTL_1_UNUSED_1_SHIFT                                                  24
5840     #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_1KX                                             (0x1<<25) // Speed up training by 1000x (1 ms = 1 us)
5841     #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_1KX_SHIFT                                       25
5842     #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_2KX                                             (0x1<<26) // Speed up training by 2000x (1 ms = 500 ns). Do not use with Denali
5843     #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TIMER_2KX_SHIFT                                       26
5844     #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_POLL                                                  (0x1<<27) // When training is sped up using bits 25 or 26, extend the timeout for Polling.Active to 72 us
5845     #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_POLL_SHIFT                                            27
5846     #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TS1                                                   (0x1<<28) // Speed up Polling.Active by restricting the number of TS1s to transmit to 32 (instead of 1024)
5847     #define PCIEIP_REG_REG_PHY_CTL_1_REG_SPDUP_TS1_SHIFT                                             28
5848     #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_LTSSM_HIST                                              (0x1<<29) // Clear the LTSSM histogram. Not self-clearing
5849     #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_LTSSM_HIST_SHIFT                                        29
5850     #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_GEN2_HIST                                               (0x1<<30) // Clear the Gen2 debug histogram. Not self-clearing
5851     #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_GEN2_HIST_SHIFT                                         30
5852     #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_RECOV_HIST                                              (0x1<<31) // Clear the recovery histogram. Not self-clearing
5853     #define PCIEIP_REG_REG_PHY_CTL_1_REG_CLR_RECOV_HIST_SHIFT                                        31
5854 #define PCIEIP_REG_REG_PHY_CTL_2                                                                     0x001808UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5855     #define PCIEIP_REG_REG_PHY_CTL_2_PRESCALE_CNT_MAX                                                (0x7f<<0) // Prescaler (using 4 ns clocks) for the inferred electrical idle counters
5856     #define PCIEIP_REG_REG_PHY_CTL_2_PRESCALE_CNT_MAX_SHIFT                                          0
5857     #define PCIEIP_REG_REG_PHY_CTL_2_EIDL_TX_GOOD_CNT_MAX                                            (0x1ff<<7) // Minimum time (in 4 ns clocks) to hold the transmitter in electrical idle when initially changing line rate during Recovery
5858     #define PCIEIP_REG_REG_PHY_CTL_2_EIDL_TX_GOOD_CNT_MAX_SHIFT                                      7
5859     #define PCIEIP_REG_REG_PHY_CTL_2_EIDL_TX_BAD_CNT_MAX                                             (0xfff<<16) // Minimum time (in 4 ns clocks) to hold the transmitter in electrical idle when changing line rate after a previous unsuccessful speed change in this retrain
5860     #define PCIEIP_REG_REG_PHY_CTL_2_EIDL_TX_BAD_CNT_MAX_SHIFT                                       16
5861     #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_10                                                  (0x3<<28) // Reserved - only write 0. Spare flops for the PL - train_ctl_in[1:0]. [29] (PL_FIX_19) Enable Phase 3 local echo delay to allow Serdes time to react  - signal is reg_gen3_ena_ph3_echo_delay.
5862     #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_10_SHIFT                                            28
5863     #define PCIEIP_REG_REG_PHY_CTL_2_REG_DIS_SERDES_CLKCOMP                                          (0x1<<30) // When set, the Serdes elastic buffers will be prevented from adjusting - generating dynamic clock compensation events - prior to the MAC performing static deskew. This is controlled via the pcie_lnk_phy_gpin_0 signal. (Also, this is pl_spare_in[2] or train_ctl_in[2].)
5864     #define PCIEIP_REG_REG_PHY_CTL_2_REG_DIS_SERDES_CLKCOMP_SHIFT                                    30
5865     #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_3                                                   (0x1<<31) // Reserved - only write 0. Spare flop for the PL - train_ctl_in[3]. Connected to Serdes via pipe_GPin_1.
5866     #define PCIEIP_REG_REG_PHY_CTL_2_PL_SPARE_IN_3_SHIFT                                             31
5867 #define PCIEIP_REG_REG_PHY_CTL_3                                                                     0x00180cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5868     #define PCIEIP_REG_REG_PHY_CTL_3_EIDL_INF_COM_CNT_MAX                                            (0x1ff<<0) // The maximum time to wait (using prescaled increments) before declaring an inferred electrical idle in Recovery.RcvrCfg based on no receipt of TS1s/TS2s (or optionally just COM symbols)
5869     #define PCIEIP_REG_REG_PHY_CTL_3_EIDL_INF_COM_CNT_MAX_SHIFT                                      0
5870     #define PCIEIP_REG_REG_PHY_CTL_3_EIDL_INF_EIE_CNT_MAX                                            (0x1f<<9) // The maximum time to wait (using prescaled increments) before declaring an inferred electrical idle in Recovery.Speed or Loopback based on no exit from electrical idle. The value is divided by four for Gen1 speeds
5871     #define PCIEIP_REG_REG_PHY_CTL_3_EIDL_INF_EIE_CNT_MAX_SHIFT                                      9
5872     #define PCIEIP_REG_REG_PHY_CTL_3_REG_GLOOPBACK                                                   (0x1<<14) // Enable the "pins" gloopback - assumes an external loopback method
5873     #define PCIEIP_REG_REG_PHY_CTL_3_REG_GLOOPBACK_SHIFT                                             14
5874     #define PCIEIP_REG_REG_PHY_CTL_3_REG_SPEED_CHANGE_WAIT                                           (0x1<<15) // Wait for the Serdes to indicate speed change using the PhyStatus (otherwise it assumes the rate change was successful).
5875     #define PCIEIP_REG_REG_PHY_CTL_3_REG_SPEED_CHANGE_WAIT_SHIFT                                     15
5876     #define PCIEIP_REG_REG_PHY_CTL_3_UNUSED_2                                                        (0x1<<16) //
5877     #define PCIEIP_REG_REG_PHY_CTL_3_UNUSED_2_SHIFT                                                  16
5878     #define PCIEIP_REG_REG_PHY_CTL_3_REG_LOSE_DESKEW_ON_SKP                                          (0x1<<17) // Enable a stronger check at the end of lane deskew and clock compensation to look for aligned SKP symbols and COM symbols rather than just COM symbols.
5879     #define PCIEIP_REG_REG_PHY_CTL_3_REG_LOSE_DESKEW_ON_SKP_SHIFT                                    17
5880     #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DLLRX_IN_IDLE                                           (0x1<<18) // Enable received data to be presented to the DLL in Configuration.Idle or Recovery.Idle if the lane to lane deskew is corrected even if logical idle data symbols have not been received. This is not according to spec but is according to the previous implmentation.
5881     #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DLLRX_IN_IDLE_SHIFT                                     18
5882     #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_PWRDN_ACK                                      (0x1<<19) // Ignore powerdown change ACk for R.Lock timeouts
5883     #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_PWRDN_ACK_SHIFT                                19
5884     #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_SPD_ACK                                        (0x1<<20) // Ignore rate change ACk for R.Lock timeouts
5885     #define PCIEIP_REG_REG_PHY_CTL_3_REG_IGNORE_RLOCK_SPD_ACK_SHIFT                                  20
5886     #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_RXEI_IN_SPEED                                           (0x1<<21) // Enable requiring Rx EI before speed change
5887     #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_RXEI_IN_SPEED_SHIFT                                     21
5888     #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P1_RXEI_REQ                                             (0x1<<22) // Disable requirement for all lanes in EI on transition to P1
5889     #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P1_RXEI_REQ_SHIFT                                       22
5890     #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DETECT_P1                                               (0x1<<23) // Enable requirement for Serdes to be in P1 before receiver detect
5891     #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_DETECT_P1_SHIFT                                         23
5892     #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P0S_IN_EXIT_L0S                                         (0x1<<24) // Do not wait for P0s before exiting Tx_L0s
5893     #define PCIEIP_REG_REG_PHY_CTL_3_REG_DIS_P0S_IN_EXIT_L0S_SHIFT                                   24
5894     #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_GEN1_IN_DISABLED                                        (0x1<<25) // Change the rate to the Serdes to Gen1 in the Disabled state rather than waiting until the LTSSM moves to Detect (per PIPE spec) to mask a Serdes bug.
5895     #define PCIEIP_REG_REG_PHY_CTL_3_REG_ENA_GEN1_IN_DISABLED_SHIFT                                  25
5896     #define PCIEIP_REG_REG_PHY_CTL_3_REG_SEL_GEN12_CLEAR_DLP                                         (0x7<<26) // Select the delay to gate off data from the PL to the DLL in Gen1 and Gen2 rates.
5897     #define PCIEIP_REG_REG_PHY_CTL_3_REG_SEL_GEN12_CLEAR_DLP_SHIFT                                   26
5898     #define PCIEIP_REG_REG_PHY_CTL_3_REG_SEL_GEN3_CLEAR_DLP                                          (0x7<<29) // Select the delay to gate off data from the PL to the DLL in Gen3 rate.
5899     #define PCIEIP_REG_REG_PHY_CTL_3_REG_SEL_GEN3_CLEAR_DLP_SHIFT                                    29
5900 #define PCIEIP_REG_REG_PHY_CTL_4                                                                     0x001810UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5901     #define PCIEIP_REG_REG_PHY_CTL_4_REG_SEL_RCVD_DEEMPH                                             (0x1<<0) // For RC only. Select the value to use for the deemphasis set during Recovery from the downstream component instead of from the Link Control 2 register.
5902     #define PCIEIP_REG_REG_PHY_CTL_4_REG_SEL_RCVD_DEEMPH_SHIFT                                       0
5903     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_UP                                          (0x1<<1) // For RC only. Enale automatic speed match when the link must change to Gen1 (slow down).
5904     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_UP_SHIFT                                    1
5905     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_DOWN                                        (0x1<<2) // For RC only. Enale automatic speed match when the link must change to Gen2 (speed up).
5906     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ENA_SPEED_MATCH_DOWN_SHIFT                                  2
5907     #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_50MS                                            (0x1<<3) // For RC only. For testing/simulation purposes, speed up the timer used to wait after a failed automatic speed up/slow down to 50 ms instead of 200 ms.
5908     #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_50MS_SHIFT                                      3
5909     #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_25MS                                            (0x1<<4) // For RC only. For testing/simulation purposes, speed up the timer used to wait after a failed automatic speed up/slow down to 25 ms instead of 200 ms.
5910     #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPDUP_200MS_25MS_SHIFT                                      4
5911     #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPEED_MATCH_ADV_DETECT                                      (0x1<<5) // For RC only. When the RC is automatically speeding up/slowing down the link to match advertised rates, use the rates from the link partner advertised since Detect rather than those immediately advertised.
5912     #define PCIEIP_REG_REG_PHY_CTL_4_REG_SPEED_MATCH_ADV_DETECT_SHIFT                                5
5913     #define PCIEIP_REG_REG_PHY_CTL_4_REG_REPORT_SPEED_MATCH                                          (0x1<<6) // For RC only. Report automatic speed up/slow down by the RC in the Autonomous Bandwidth Status bits.
5914     #define PCIEIP_REG_REG_PHY_CTL_4_REG_REPORT_SPEED_MATCH_SHIFT                                    6
5915     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_LOCAL_SPD_CHG                                         (0x1<<7) // Allow locally initiated speed change (directed_speed_change) even if the link partner has only advertised Gen1 rate since Detect.
5916     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_LOCAL_SPD_CHG_SHIFT                                   7
5917     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_REMOTE_SPD_CHG                                        (0x1<<8) // Allow link partner to initiate speed change (directed_speed_change) even if only Gen1 rate has been advertised since Detect.
5918     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ALLOW_REMOTE_SPD_CHG_SHIFT                                  8
5919     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ADV_LINKCAP_RATES                                           (0x1<<9) // For RC only. Advertise the supported rates from the Link Capabilities register instead of the Link Control 2 register.
5920     #define PCIEIP_REG_REG_PHY_CTL_4_REG_ADV_LINKCAP_RATES_SHIFT                                     9
5921     #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY                                                 (0x7<<10) // Sets the delay between the assertion of electrical idle to the power state change to P2. The delay is the in clocks and is 4 + the value of this field.
5922     #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY_SHIFT                                           10
5923     #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY_DIS                                             (0x1<<13) // If set, disables the delay between the assertion of electrical idle to the power state change to P2. This is needed in Gen2 when entering L2. The minimum time to wait in Detect.Quiet (in 32 ns increments) if the state is entered at non-Gen1 speeds
5924     #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_EI_DELAY_DIS_SHIFT                                       13
5925     #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_IN_RESET_ENA                                             (0x1<<14) // Allow lanes to be put into P2 state during reset to save power.
5926     #define PCIEIP_REG_REG_PHY_CTL_4_REG_P2_IN_RESET_ENA_SHIFT                                       14
5927     #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_2                                                        (0x1<<15) //
5928     #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_2_SHIFT                                                  15
5929     #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_EXIT_ON_ANY                                           (0x1<<16) // Enable exit from Compliance on 1.1-compliant systems on signal detect on any lane (spec says all lanes must have signal detect to exit).
5930     #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_EXIT_ON_ANY_SHIFT                                     16
5931     #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_MIN_LANE_DETECT                                       (0x1<<17) // The minimum number of lanes for signal detect to avoid entry to Compliance. 0 means only 1 is needed, 1 means all are needed.
5932     #define PCIEIP_REG_REG_PHY_CTL_4_REG_COMPL_MIN_LANE_DETECT_SHIFT                                 17
5933     #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_1                                                        (0x1<<18) //
5934     #define PCIEIP_REG_REG_PHY_CTL_4_UNUSED_1_SHIFT                                                  18
5935     #define PCIEIP_REG_REG_PHY_CTL_4_UPCFG_LANES                                                     (0x1f<<19) // Mask for indicating lanes to upconfigure (1, 2, 4, 8, or 16)
5936     #define PCIEIP_REG_REG_PHY_CTL_4_UPCFG_LANES_SHIFT                                               19
5937     #define PCIEIP_REG_REG_PHY_CTL_4_REG_TX_LINKNO                                                   (0xff<<24) // For root complex cores, this indicates the link number for the link
5938     #define PCIEIP_REG_REG_PHY_CTL_4_REG_TX_LINKNO_SHIFT                                             24
5939 #define PCIEIP_REG_REG_PHY_CTL_5                                                                     0x001814UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5940     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TCRPW_MAX                                              (0x1f<<0) // Counter of 25 MHz clks for the mininum time to spend with external CLKREQ deasserted.
5941     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TCRPW_MAX_SHIFT                                        0
5942     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TREFUP_MAX_HI                                          (0xf<<5) // High 4 bits of the 10 bit-counter of 25 MHz clks for the minimum time to spend waiting for the reference clock buffers in the Serdes to power up after P2. For Ev3 A0, this field should be set to 4'h2
5943     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TREFUP_MAX_HI_SHIFT                                    5
5944     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TCRLON_MAX                                             (0x1f<<9) // Counter of 25 MHz clks for the maximum time to wait after assertion of external CLKREQ until the reference clock is active.
5945     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TCRLON_MAX_SHIFT                                       9
5946     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TEXCR_MAX                                              (0x7f<<14) // Counter of 25 MHz clks for the minimum time to wait between assertion of clkreq/auxclk to the Serdes and deassertion of external CLKREQ.
5947     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TEXCR_MAX_SHIFT                                        14
5948     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_DIS_FASTL1EXIT                                         (0x1<<21) // When set, disables the control of the Serdes device type to minimize the PLL lock time (when set, don't reuse the old value - start over).
5949     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_DIS_FASTL1EXIT_SHIFT                                   21
5950     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_L0S_LFCLK_SEL                                          (0x3<<22) // Selects the low-frequency clock used to advance the L0s exit state machine. Default is from the version.v  b00 : lfclk = 25 MHz (default and compatible with older cores) b01 : lfclk = 50 MHz  b1x : lfclk = 100 MHz (refclk)
5951     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_L0S_LFCLK_SEL_SHIFT                                    22
5952     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TREFUP_MAX_LO                                          (0x3f<<24) // Low 6 bits of the 10 bit-counter of 25 MHz clks for the minimum time to spend waiting for the reference clock buffers in the Serdes to power up after P2. For Ev3 A0, this field should be set to 6'h16
5953     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_TREFUP_MAX_LO_SHIFT                                    24
5954     #define PCIEIP_REG_REG_PHY_CTL_5_UNUSED_1                                                        (0x1<<30) // Reserved - only write 0
5955     #define PCIEIP_REG_REG_PHY_CTL_5_UNUSED_1_SHIFT                                                  30
5956     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_NO_L2_CLKREQ                                           (0x1<<31) // When set, disables entry to CLKREQ when L2/L23 is requested (ie, only PM L1 and ASPM L1 etner CLKREQ)
5957     #define PCIEIP_REG_REG_PHY_CTL_5_REG_PMCR_NO_L2_CLKREQ_SHIFT                                     31
5958 #define PCIEIP_REG_REG_PHY_CTL_6                                                                     0x001818UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5959     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_TP0TOREFCLK_MAX                                        (0x3f<<0) // Number of clocks at 25 MHz to delay between the start of active clkreq (not in the standby state) and the switchover from RefClk to AuxClk. This timer includes waiting for the Serdes response to the P0 to P2 powerdown state change and will eventually advance even if it is not seen.
5960     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_TP0TOREFCLK_MAX_SHIFT                                  0
5961     #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_3                                                        (0x3<<6) // Reserved - only write 0
5962     #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_3_SHIFT                                                  6
5963     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_SERDES_RESET_MAX                                       (0x3f<<8) // Number of clocks at 25 MHz to delay between assertion of reset to the Serdes before deassertion of the Serdes clk switcher reset
5964     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_SERDES_RESET_MAX_SHIFT                                 8
5965     #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_2                                                        (0x3<<14) // Reserved - only write 0
5966     #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_2_SHIFT                                                  14
5967     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_CLR_HIST                                               (0x1<<16) // Clear the clkreq state history
5968     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_CLR_HIST_SHIFT                                         16
5969     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_ANY_PHYSTATUS                                      (0x1<<17) // Use any PhyStatus to indicate the P0-&gt;P2 transition. Default is that all active lanes must respond.
5970     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_ANY_PHYSTATUS_SHIFT                                17
5971     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKREQB_ON                                         (0x1<<18) // CLKREQB is always asserted regardless of the clock PM state.
5972     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKREQB_ON_SHIFT                                   18
5973     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKRST_PERST                                       (0x1<<19) // Always reset the Serdes clk mux during perstb and keep it asserted while perstb is asserted. Default is to briefly reset on perstb assertion, then deassert the clk mux reset.
5974     #define PCIEIP_REG_REG_PHY_CTL_6_REG_PMCR_ENA_CLKRST_PERST_SHIFT                                 19
5975     #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_1                                                        (0xfff<<20) // Reserved - only write 0
5976     #define PCIEIP_REG_REG_PHY_CTL_6_UNUSED_1_SHIFT                                                  20
5977 #define PCIEIP_REG_REG_PHY_CTL_7                                                                     0x00181cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5978     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_INTV                                                (0xf<<0) // b0000: select pseudo-random value between 1 to 15 b0001 to b1111 : specify a fixed value
5979     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_INTV_SHIFT                                          0
5980     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_PRESCALE                                            (0x7<<4) // b000 : prescale = 2**2 of clock periods (~16ns) b001 : prescale = 2**3 of clock periods b010 : prescale = 2**8 of clock periods b011 : prescale = 2**12 of clock periods b100 : prescale = 2**15 of clock periods b101 : prescale = 2**18 of clock periods (~1.0ms) b110 : prescale = 2**20 of clock periods b111 : prescale = 2**21 of clock periods (~8.4ms)
5981     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_PRESCALE_SHIFT                                      4
5982     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LANE                                                (0x1f<<7) // This field selects the lanes where error is injected to. b1xxxx : random lane is chosen b01111 : lane 15 b01110 : lane 14 .... b00010 : lane 2 b00001 : lane 1 b00000 : lane 0
5983     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LANE_SHIFT                                          7
5984     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LOC                                                 (0x3<<12) // This field has different actions based on the reg_err_inj_type field.  If reg_err_inj_type != b00 (a TLP or DLLP error): b11 : corrupt framing (start of frame or end of frame, whichever is first) b10 : corrupt start of frame (STP or SDP. b01 : corrupt end of frame b00 : corrupt data in frame (second symbol)  If reg_err_inj_type == b00 for transmit errors (ordered sets): b11 : corrupt next logical idle data on the lane rom below b10 : corrupt the last symbol of the ordered set on the lane from below b01 : corrupt the first symbol other than com on the lane from below b00 : corrupt the COM symbol on the lane from below  If reg_err_inj_type == b00 for receive errors (serdes errors): b11 : inject disparity error on the lane from below b10 : inject decode error on the lane from below b01 : inject buffer error on the lane from below b00 : inject data invalid error on the lane from below
5985     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_LOC_SHIFT                                           12
5986     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TYPE                                                (0x3<<14) // b11 : Reserved b10 : DLLP error b01 : TLP error b00 : Ordered set error for TX or Serdes error for RX
5987     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TYPE_SHIFT                                          14
5988     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TX_ENA                                              (0x1<<16) // Inject transmit DLLP/TLP error or ordered set error.
5989     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_TX_ENA_SHIFT                                        16
5990     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_RX_ENA                                              (0x1<<17) // Inject receive DLLP/TLP error or serdes error.
5991     #define PCIEIP_REG_REG_PHY_CTL_7_REG_ERR_INJ_RX_ENA_SHIFT                                        17
5992     #define PCIEIP_REG_REG_PHY_CTL_7_UNUSED_1                                                        (0x1fff<<18) // Reserved - always write 0
5993     #define PCIEIP_REG_REG_PHY_CTL_7_UNUSED_1_SHIFT                                                  18
5994     #define PCIEIP_REG_REG_PHY_CTL_7_REG_DIS_DESKEW_AFTER_ALIGN_ERR                                  (0x1<<31) // When cleared (the default), Gen3 block alignment errors and invalid data result in the link being declared unusable since data alignment is lost. When set, the legacy behavior is maintained and no retrain will occur, with the possiblity of incorrect training and fall back to lower speeds.
5995     #define PCIEIP_REG_REG_PHY_CTL_7_REG_DIS_DESKEW_AFTER_ALIGN_ERR_SHIFT                            31
5996 #define PCIEIP_REG_PHY_ERR_ATTN_VEC                                                                  0x001820UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
5997     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_ELASTIC_ERR                                                  (0x1<<0) // If set, either an elastic buffer overflow or underflow (in the Serdes)
5998     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_ELASTIC_ERR_SHIFT                                            0
5999     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DISPARITY_ERR                                                (0x1<<1) // If set, a disparity error occurred in the Serdes WC 0
6000     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DISPARITY_ERR_SHIFT                                          1
6001     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DECODE_ERR                                                   (0x1<<2) // If set, an 8b10b decode error occurred in the Serdes
6002     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_DECODE_ERR_SHIFT                                             2
6003     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_LINK_IS_SKEW                                                 (0x1<<3) // If set, the link needed to be deskewed
6004     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_LINK_IS_SKEW_SHIFT                                           3
6005     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_TRAIN_ERR                                                    (0x1<<4) // If set, the link needed to be retrained
6006     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_TRAIN_ERR_SHIFT                                              4
6007     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_L0S_MAIN_ERR                                                 (0x1<<5) // Receiver training error in L0S
6008     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_L0S_MAIN_ERR_SHIFT                                           5
6009     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_RETRAIN_REQ                                                  (0x1<<6) // Request to retrain received from a higher layer
6010     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_RETRAIN_REQ_SHIFT                                            6
6011     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_CC_ERR_STATUS                                                (0x1<<7) // Clock Compensation deskew error.
6012     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_CC_ERR_STATUS_SHIFT                                          7
6013     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_1                                                     (0xf<<8) // Reserved - only write 0
6014     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_1_SHIFT                                               8
6015     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_2                                                     (0xfffff<<12) //
6016     #define PCIEIP_REG_PHY_ERR_ATTN_VEC_UNUSED_2_SHIFT                                               12
6017 #define PCIEIP_REG_PHY_ERR_ATTN_MASK                                                                 0x001824UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6018     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_ELASTIC_ERR                                            (0x1<<0) // If set, masks ELASTIC_ERR from generating attention. If clear, ELASTIC_ERR generates attention
6019     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_ELASTIC_ERR_SHIFT                                      0
6020     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DISPARITY_ERR                                          (0x1<<1) // If set, masks DISPARITY_ERR from generating attention. If clear, DISPARITY_ERR generates attention
6021     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DISPARITY_ERR_SHIFT                                    1
6022     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DECODE_ERR                                             (0x1<<2) // If set, masks DECODE_ERR from generating attention. If clear, DECODE_ERR generates attention
6023     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_DECODE_ERR_SHIFT                                       2
6024     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_LINK_IS_SKEW                                           (0x1<<3) // If set, masks LINK_IS_SKEW from generating attention. If clear, LINK_IS_SKEW generates attention
6025     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_LINK_IS_SKEW_SHIFT                                     3
6026     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_TRAIN_ERR                                              (0x1<<4) // If set, masks TRAIN_ERR from generating attention. If clear, TRAIN_ERR generates attention RW 1
6027     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_TRAIN_ERR_SHIFT                                        4
6028     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_L0S_MAIN_ERROR                                         (0x1<<5) // If set, masks L0S_MAIN_ERR from generating attention. If clear, L0S_MAIN_ERR generates attention
6029     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_L0S_MAIN_ERROR_SHIFT                                   5
6030     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_RETRAIN_REQ                                            (0x1<<6) // If set, masks RETRAIN_REQ from generating attention. If clear, RETRAIN_REQ generates attention
6031     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_RETRAIN_REQ_SHIFT                                      6
6032     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_CC_ERR_STATUS                                          (0x1<<7) // If set, masks Clock Compensation deskew error from generating attn. If clear, Clock Compensation deskew error generates attn.
6033     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_MASK_CC_ERR_STATUS_SHIFT                                    7
6034     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_1                                                    (0xf<<8) // Reserved - only write 0
6035     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_1_SHIFT                                              8
6036     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_2                                                    (0xfffff<<12) //
6037     #define PCIEIP_REG_PHY_ERR_ATTN_MASK_UNUSED_2_SHIFT                                              12
6038 #define PCIEIP_REG_REG_PHY_CTL_8                                                                     0x001830UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6039     #define PCIEIP_REG_REG_PHY_CTL_8_REG_LOSE_DESKEW_ON_FIFO                                         (0x1<<0) // Enable loss of lane alignment on deskew/clkcomp FIFO errors.
6040     #define PCIEIP_REG_REG_PHY_CTL_8_REG_LOSE_DESKEW_ON_FIFO_SHIFT                                   0
6041     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_BLOCK_REALIGN                                      (0x1<<1) // Enable request to the Serdes to realign blocks.
6042     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_BLOCK_REALIGN_SHIFT                                1
6043     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_FRAMERR_RETRAIN                                    (0x1<<2) // Enable retraining on any Gen3 framing error.
6044     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_FRAMERR_RETRAIN_SHIFT                              2
6045     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_BLOCK_ALIGN_ERR                                    (0x1<<3) // Disable error and retrain for block alignment error from Serdes.
6046     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_BLOCK_ALIGN_ERR_SHIFT                              3
6047     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_BLOCK_ALIGN_ERR_DLY                                    (0xf<<4) // Delay value for block alignment error (deassertion of RxValid from the Serdes indicating loss of block alignment) before the link is retrained. This is to allow any EIOS to be seen since EIOS first is not an error.
6048     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_BLOCK_ALIGN_ERR_DLY_SHIFT                              4
6049     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FIXED_DATA_WIDTH                                       (0x1<<8) // *** Do not modify!! Enable 16-bit data for all rates.
6050     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FIXED_DATA_WIDTH_SHIFT                                 8
6051     #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_EIOS_DET_ELECIDLE                                       (0x1<<9) // Enable the EIOS detector to mask out data.
6052     #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_EIOS_DET_ELECIDLE_SHIFT                                 9
6053     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SCRAM                                              (0x1<<10) // Disable scrambling in Gen3.
6054     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SCRAM_SHIFT                                        10
6055     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_TX_STALL                                           (0x1<<11) // *** Do not modify!! Enable transmitting Gen3 stalls (null data or deassertion of the TxDataValid signals periodically).
6056     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_TX_STALL_SHIFT                                     11
6057     #define PCIEIP_REG_REG_PHY_CTL_8_REG_MCP_G3_ALLOW_DATA_LOCK                                      (0x1<<12) // Allow locking to the data blocks in Gen3 Modified Compliance Pattern
6058     #define PCIEIP_REG_REG_PHY_CTL_8_REG_MCP_G3_ALLOW_DATA_LOCK_SHIFT                                12
6059     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_RESTORE_REVERSAL                                   (0x1<<13) // When retraining to enter compliance, the lane assignments, polarity reversal, and lane reversal information is saved, then restored. This bit disables the restoration of the lane reversal since it wasn't explicitly stated.
6060     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_RESTORE_REVERSAL_SHIFT                             13
6061     #define PCIEIP_REG_REG_PHY_CTL_8_REG_CLR_FREEZE_DESKEW                                           (0x1<<14) // Clear the block aligner debug information frozen on an aligner error. Set, then clear immediately.
6062     #define PCIEIP_REG_REG_PHY_CTL_8_REG_CLR_FREEZE_DESKEW_SHIFT                                     14
6063     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SKIP_FIX                                           (0x1<<15) // Disable the logic that corrects for misaligned deassertions of RxDataValid (in other words, null data is inserted on different relative blocks and the logic fixes that to a limited extent).
6064     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_DIS_SKIP_FIX_SHIFT                                     15
6065     #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_RECOV_TSX                                               (0x1<<16) // Enable mixed consecutive TS1s and TS2s for Recovery.RcvrLock transitions
6066     #define PCIEIP_REG_REG_PHY_CTL_8_REG_ENA_RECOV_TSX_SHIFT                                         16
6067     #define PCIEIP_REG_REG_PHY_CTL_8_UNUSED_1                                                        (0x3<<17) // Reserved - only write 0
6068     #define PCIEIP_REG_REG_PHY_CTL_8_UNUSED_1_SHIFT                                                  17
6069     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_EQ_TIMEOUTS                                    (0x1<<19) // Enable updated timeouts for Recovery.Equalization phases (now 12 ms for 0 and 1, 32 ms for 3).
6070     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_EQ_TIMEOUTS_SHIFT                              19
6071     #define PCIEIP_REG_REG_PHY_CTL_8_REG_EIOS_DET_MIN_TIME                                           (0xf<<20) // Minimum time (in PCLKs) to wait for EI exit using the EIOS detector
6072     #define PCIEIP_REG_REG_PHY_CTL_8_REG_EIOS_DET_MIN_TIME_SHIFT                                     20
6073     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_071_LOADBOARD                                          (0x1<<24) // Enable TX preset encoding for value b1010 in CLB/CBB environments
6074     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_071_LOADBOARD_SHIFT                                    24
6075     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFG_IEI_4MS                                        (0x1<<25) // Enable 4 ms inferred electrical idle in Recovery.RcvrCfg at 8 GT/s
6076     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFG_IEI_4MS_SHIFT                                  25
6077     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFGSPEED_128X_TS2                                  (0x1<<26) // Enable transmission of 128 TS2s in Recovery.RcvrCfg prior to transition to Recovery.Speed (instead of 32 TS2s in 0.70 revision).
6078     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_CFGSPEED_128X_TS2_SHIFT                            26
6079     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_COMPLPAT                                       (0x1<<27) // Enable the updated version fo the Gen3 Compliance pattern generation rather than the 0.70 version.
6080     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_071_COMPLPAT_SHIFT                                 27
6081     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_INSERT                                       (0x1<<28) // Enable insertion of DC balance symbols on the transmitted training sequences.
6082     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_INSERT_SHIFT                                 28
6083     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_RESTORE                                      (0x1<<29) // Enable correction of DC balance symbols on the received training sequences.
6084     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_ENA_DCBAL_RESTORE_SHIFT                                29
6085     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_INGORE_USER_ALLOW_GEN3                                 (0x1<<30) // Ignore the "strap" setting for user_allow_gen3.
6086     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_INGORE_USER_ALLOW_GEN3_SHIFT                           30
6087     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FORCE_G3_ADV                                           (0x1<<31) // Force initial setting of Gen3 advertisement.
6088     #define PCIEIP_REG_REG_PHY_CTL_8_REG_GEN3_FORCE_G3_ADV_SHIFT                                     31
6089 #define PCIEIP_REG_REG_PHY_CTL_9                                                                     0x001834UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6090     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_CLR_STICKY_ERRS                                        (0xfffff<<0) // Clear the corresponding bits indicating Gen3 errors reported in offset 0x1d34, bits [19:0].
6091     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_CLR_STICKY_ERRS_SHIFT                                  0
6092     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_EDS                                            (0x1<<20) // Enable a bad/misplaced End-of-Data-Stream token as a framing/receiver error
6093     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_EDS_SHIFT                                      20
6094     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_SYM_CNT_ERR                                    (0x1<<21) // Enable bad block count as a framing/receiver error
6095     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_SYM_CNT_ERR_SHIFT                              21
6096     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SYNCHEADER_ERR                                     (0x1<<22) // Enable invalid sync header as a framing/receiver error
6097     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SYNCHEADER_ERR_SHIFT                               22
6098     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_LEN_ERR                                        (0x1<<23) // Enable the auxilliary bad TLP length to be reported as a framing/receiver error.
6099     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BAD_LEN_ERR_SHIFT                                  23
6100     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_BADSYNC_ALWAYS                                         (0x1<<24) // Enable the auxilliary bad sync header to be reported as an error in all cases.
6101     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_BADSYNC_ALWAYS_SHIFT                                   24
6102     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_L0_ALIGN_ERR                                           (0x1<<25) // Enable the auxilliary alignment error to be reported as a framing/receiver error in L0.
6103     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_L0_ALIGN_ERR_SHIFT                                     25
6104     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ALL_ALIGN_ERR                                          (0x1<<26) // Enable the auxilliary alignment error to be reported as a framing/receiver error in Configuration and Recovery as well as L0.
6105     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ALL_ALIGN_ERR_SHIFT                                    26
6106     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BLOCK_LANE_ERR                                     (0x1<<27) // Enable bad sync header errors as lane status errors in the Secondary PCIE structure.
6107     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_BLOCK_LANE_ERR_SHIFT                               27
6108     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_AUX_FRAMERR_RETRAIN                                    (0x1<<28) // Enable auxilliary framing errors to cause a retrain (if framing errors are enabled for retraining).
6109     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_AUX_FRAMERR_RETRAIN_SHIFT                              28
6110     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SKIPDATA_ERR                                       (0x1<<29) // Enable generation of an error if the skipped/null data misaligns.
6111     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_SKIPDATA_ERR_SHIFT                                 29
6112     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_DIS_PARITY_ERR                                         (0x1<<30) // Disable reporting Gen3 data parity errors in the Secondary PCIE structure.
6113     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_DIS_PARITY_ERR_SHIFT                                   30
6114     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_IDLE_START_ERR                                     (0x1<<31) // Eanble error when idle symbols appear in the DW before a TLP or DLLP
6115     #define PCIEIP_REG_REG_PHY_CTL_9_REG_GEN3_ENA_IDLE_START_ERR_SHIFT                               31
6116 #define PCIEIP_REG_REG_PHY_CTL_10                                                                    0x001838UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6117     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_GEN3_EQ_TSX                                       (0x1<<0) // Disable transmission of the equalization TS1s and TS2s.
6118     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_GEN3_EQ_TSX_SHIFT                                 0
6119     #define PCIEIP_REG_REG_PHY_CTL_10_REG_LOCAL_DEEMPH_HI                                            (0x7<<1) // Upper three bits of the local deephasis setting in cases where no presets are received from the link partner.
6120     #define PCIEIP_REG_REG_PHY_CTL_10_REG_LOCAL_DEEMPH_HI_SHIFT                                      1
6121     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_5                                                       (0x1<<4) //
6122     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_5_SHIFT                                                 4
6123     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_QUIESCE_GUARANTEE                                  (0x1<<5) // Software sets if it can disable data traffic during re-equalization.
6124     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_QUIESCE_GUARANTEE_SHIFT                            5
6125     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_NO_REDO                                            (0x1<<6) // Disable redo
6126     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_EQ_NO_REDO_SHIFT                                      6
6127     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DEFAULT_PRESET                                        (0xf<<7) // Default preset for advertisement.
6128     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DEFAULT_PRESET_SHIFT                                  7
6129     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_ON_REDO                                (0x1<<11) // Disable equalization request on redo.
6130     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_ON_REDO_SHIFT                          11
6131     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_REQUEST_EQUALIZATION                                  (0x1<<12) // Software can request that the link partner initiates equalization.
6132     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_REQUEST_EQUALIZATION_SHIFT                            12
6133     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_FROM_PHY                               (0x1<<13) // Disable requests from the Serdes to request equalization.
6134     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_REQUEST_FROM_PHY_SHIFT                         13
6135     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_SYM6                                            (0x1<<14) // Enable symbol 6 (TS1 or TS2) matching requirements for consecutive TS1s or TS2s.
6136     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_SYM6_SHIFT                                      14
6137     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_PARITY                                          (0x1<<15) // Enable parity matching for Gen3 TS1s, symbols 6 through 9
6138     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_MATCH_PARITY_SHIFT                                    15
6139     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQUALIZATION                                      (0x1<<16) // Disable Gen3 equalization.
6140     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQUALIZATION_SHIFT                                16
6141     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_TIMERS                                         (0x1<<17) // For debug purposes, disable timeouts from Recovery.Equalization phases.
6142     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_EQ_TIMERS_SHIFT                                   17
6143     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_DLP_HOLD_CLEAR                                    (0x1<<18) // Clear indication that a DLP was received on change to Gen3.
6144     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_DLP_HOLD_CLEAR_SHIFT                              18
6145     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_TX_DLP_HOLDOFF                                    (0x1<<19) // Hold off sending DLPs until equalization is complete
6146     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_TX_DLP_HOLDOFF_SHIFT                              19
6147     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_4                                                       (0x1<<20) //
6148     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_4_SHIFT                                                 20
6149     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_2                                                       (0x1<<21) //
6150     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_2_SHIFT                                                 21
6151     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC3_ECHO_PRESET                                   (0x1<<22) // enable echo preset bit in Phase 3
6152     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC3_ECHO_PRESET_SHIFT                             22
6153     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_CLR_RCFG_PRESETS                                      (0x1<<23) // Clear previously received presets on entry to Recovery.RcvrCfg
6154     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_CLR_RCFG_PRESETS_SHIFT                                23
6155     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_LPBK_EC23_ENA                                         (0x1<<24) // In Gen3 Loopback Slave shall take the transmitter setting specified by the received TS1 if the EC field is set to 2'b10 or 2'b11 depending on whether Slave is an RC or EP respectively. When this bit is set to '1', Slave takes the settings when EC is either 2'10 or 2'11.
6156     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_LPBK_EC23_ENA_SHIFT                                   24
6157     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED                                                         (0x1<<25) //
6158     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_SHIFT                                                   25
6159     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_PH2_PRESETS                                       (0x1<<26) // Disable presets in Phase 2 (raw data to Serdes)
6160     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_PH2_PRESETS_SHIFT                                 26
6161     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EQ_TS1                                            (0x1<<27) // Enable transmisssion of EQ TS1s (mainly for RC functionality)
6162     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EQ_TS1_SHIFT                                      27
6163     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_1                                                       (0x1<<28) // Reserved - only write 0
6164     #define PCIEIP_REG_REG_PHY_CTL_10_UNUSED_1_SHIFT                                                 28
6165     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_TXEC_DELAY                                        (0x1<<29) // Disable timeout counter delay waiting for EC bits to change in equalization
6166     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_DIS_TXEC_DELAY_SHIFT                                  29
6167     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC2_EXIT_ON_TXEC3                                 (0x1<<30) // Enable exiting Phase 2 only on Tx of EC=2'b11 regardless of what is received
6168     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_EC2_EXIT_ON_TXEC3_SHIFT                           30
6169     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_PH2_MATCH_PRESETS                                 (0x1<<31) // Enable preset vs ceofficient matching during Phase 2 based on Serdes request
6170     #define PCIEIP_REG_REG_PHY_CTL_10_REG_GEN3_ENA_PH2_MATCH_PRESETS_SHIFT                           31
6171 #define PCIEIP_REG_REG_PHY_CTL_11                                                                    0x00183cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6172     #define PCIEIP_REG_REG_PHY_CTL_11_REG_EIDL_DELAY_G3                                              (0x1f<<0) // Delay value for raw electrical idle to sig detect in Gen3 mode
6173     #define PCIEIP_REG_REG_PHY_CTL_11_REG_EIDL_DELAY_G3_SHIFT                                        0
6174     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_20X                                       (0x1<<5) // 20x timer speedup for use with Gen3 uC equalization
6175     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_20X_SHIFT                                 5
6176     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_50X                                       (0x1<<6) // 50x timer speedup for use with Gen3 uC equalization
6177     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_SPDUP_TIMER_50X_SHIFT                                 6
6178     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_MATCH_EQ_SYM1TO5                                      (0x1<<7) // For Gen3 TS1s in Equalization, match symbols 1 to 5 as well
6179     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_MATCH_EQ_SYM1TO5_SHIFT                                7
6180     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_DCBAL_SOS                                         (0x1<<8) // Enable SOS data DC balance accumulation
6181     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_DCBAL_SOS_SHIFT                                   8
6182     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_SERDES                                   (0x1<<9) // Enable Gen3 redo deskew on request from Serdes
6183     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_SERDES_SHIFT                             9
6184     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_PIPE                                     (0x1<<10) // Enable Gen3 redo deskew on PIPE misalignment issues
6185     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_PIPE_SHIFT                               10
6186     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_FRAME                                    (0x1<<11) // Enable Gen3 redo deskew on framing/post-deskew alignment issues
6187     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ALIGN_DESKEW_FRAME_SHIFT                              11
6188     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RLOCK                                  (0x1<<12) // Assert signal to PHY when idle_to_rlock transition is taken.
6189     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RLOCK_SHIFT                            12
6190     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RXL0S                                  (0x1<<13) // Assert signal to PHY when Rx_L0s times out
6191     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_RXL0S_SHIFT                            13
6192     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_TMOUT                                  (0x1<<14) // Enable the L1 failure on 24 ms timeout in R.Lock
6193     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_L0SL1_FAIL_TMOUT_SHIFT                            14
6194     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_L0SL1_FAIL                                       (0x1<<15) // Use the l0s/l1 failure signal only for Gen3
6195     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_L0SL1_FAIL_SHIFT                                 15
6196     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_PHY_L1_ACTIVE                                    (0x1<<16) // Use the phy l1 active signal only for Gen3
6197     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ONLY_PHY_L1_ACTIVE_SHIFT                              16
6198     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_ANY_EQTS2                                         (0x1<<17) // Select between requiring all EQ TS2s or any EQ TS2 to set start_eq_w_preset
6199     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_ANY_EQTS2_SHIFT                                   17
6200     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_BLOCK_ALIGN_RCFG_RESET                                (0x1<<18) // Reset needed flops on block align during Recovery.RcvrCfg
6201     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_BLOCK_ALIGN_RCFG_RESET_SHIFT                          18
6202     #define PCIEIP_REG_REG_PHY_CTL_11_UNUSED                                                         (0x1<<19) //
6203     #define PCIEIP_REG_REG_PHY_CTL_11_UNUSED_SHIFT                                                   19
6204     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PRESET_MISMATCH                                   (0x1<<20) // Enable check for mismatch of presets in R.Lock after equalization
6205     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PRESET_MISMATCH_SHIFT                             20
6206     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYLINKUP_HOLDOFF                                 (0x1<<21) // Enable PhyLinkUp holdoff in Gen3 (for InitFC vs UpdateFC issue)
6207     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYLINKUP_HOLDOFF_SHIFT                           21
6208     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH3_PRESET_COEFF                                  (0x1<<22) // (PL_FIX_05) Enable preset-coefficient lookup for EQ Phase 3
6209     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH3_PRESET_COEFF_SHIFT                            22
6210     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH2_TXRX_PRESET_MATCH                             (0x1<<23) // (PL_FIX_05) Tx/Rx presets in phase 2 must match before preset signal to Serdes asserted
6211     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PH2_TXRX_PRESET_MATCH_SHIFT                       23
6212     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_DEFAULT_RX_PRESET                                     (0x7<<24) // (PL_FIX_14) Default Rx preset to send to the Serdes if no EQ TS2s
6213     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_DEFAULT_RX_PRESET_SHIFT                               24
6214     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2                                            (0x1<<27) // (PL_FIX_15) For a possible ECN, send EQ TS2s
6215     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2_SHIFT                                      27
6216     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2_REDO                                       (0x1<<28) // (PL_FIX_15) For a possible ECN, send EQ TS2s as an endpoint when redoing equalization
6217     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_EPTX_EQTS2_REDO_SHIFT                                 28
6218     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EIOS                                       (0x1<<29) // Enable Serdes IEI signal on internal EIOS detect
6219     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EIOS_SHIFT                                 29
6220     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EI                                         (0x1<<30) // Enable Serdes IEI signal on internal EI detect
6221     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_EI_SHIFT                                   30
6222     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_IEI                                        (0x1<<31) // Enable Serdes IEI signal on internal IEI
6223     #define PCIEIP_REG_REG_PHY_CTL_11_REG_GEN3_ENA_PHYIEI_IEI_SHIFT                                  31
6224 #define PCIEIP_REG_REG_PHY_CTL_12                                                                    0x001840UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6225     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_ADDR                                                (0x3f<<0) // SED read address start
6226     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_ADDR_SHIFT                                          0
6227     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_AUTOINC                                             (0x1<<6) // SED read address auto-increment
6228     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_AUTOINC_SHIFT                                       6
6229     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_ADDR                                            (0x1<<7) // SED clear read address to 0
6230     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_ADDR_SHIFT                                      7
6231     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL                                                 (0xf<<8) // SED fill/write select (Default for LTSSM)
6232     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_SHIFT                                           8
6233     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR                                                 (0x1<<12) // Clear SED memory and write address
6234     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_CLR_SHIFT                                           12
6235     #define PCIEIP_REG_REG_PHY_CTL_12_UNUSED_2                                                       (0x7<<13) //
6236     #define PCIEIP_REG_REG_PHY_CTL_12_UNUSED_2_SHIFT                                                 13
6237     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_CONFIG                                          (0xff<<16) // SED configuration
6238     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_CONFIG_SHIFT                                    16
6239     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_CONFIG_ADDR                                     (0xf<<24) // SED address selection for multiple options for field [23:16]
6240     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_SEL_CONFIG_ADDR_SHIFT                               24
6241     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_TRIG_HOLD                                           (0x1<<28) // Hold off SED triggering
6242     #define PCIEIP_REG_REG_PHY_CTL_12_REG_SEDCFG_TRIG_HOLD_SHIFT                                     28
6243     #define PCIEIP_REG_REG_PHY_CTL_12_REG_GEN3_ENA_PH1_FS_LF                                         (0x1<<29) // [DEBUG_BIT}: Captures internal defined FS and LF values when receive use preset = 1 in EQ Phase 1
6244     #define PCIEIP_REG_REG_PHY_CTL_12_REG_GEN3_ENA_PH1_FS_LF_SHIFT                                   29
6245     #define PCIEIP_REG_REG_PHY_CTL_12_UNUSED_1                                                       (0x3<<30) //
6246     #define PCIEIP_REG_REG_PHY_CTL_12_UNUSED_1_SHIFT                                                 30
6247 #define PCIEIP_REG_REG_PHY_CTL_13                                                                    0x001844UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6248     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_5_TO_0                               (0x3f<<0) // Pre-cursor for the coefficient set
6249     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_5_TO_0_SHIFT                         0
6250     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_11_TO_6                              (0x3f<<6) // Main cursor for the coefficient set
6251     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_11_TO_6_SHIFT                        6
6252     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_17_TO_12                             (0x3f<<12) // Post-cursor for the coefficient set
6253     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_ENTRY_17_TO_12_SHIFT                       12
6254     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_INDEX                                      (0xf<<18) // Index for reading/writing the Preset LUT (number of the preset)
6255     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_INDEX_SHIFT                                18
6256     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_WRSTB                                      (0x1<<22) // Write strobe for Preset LUT
6257     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_LUT_WRSTB_SHIFT                                22
6258     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_SERDES_PRESET_SEL                                     (0x1<<23) // Conbtrol bit to select the default preset to use in phase2 advertizement provided on pcie_rx_linkevalfm signal from Serdes to MAC
6259     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_SERDES_PRESET_SEL_SHIFT                               23
6260     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_EQ_REQ_VAL                                     (0xf<<24) // programmable preset value advertized by the EP to the Link partner-RC Transmitter in Phase2 EQ programmable preset value advertized by the RC to the Link partner-EP Transmitter in Phase3 EQ
6261     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_PRESET_EQ_REQ_VAL_SHIFT                               24
6262     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_PRESET_EQ2_REQ                                    (0x1<<28) // Use programmable preset Phase2 EQ in EP mode
6263     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_PRESET_EQ2_REQ_SHIFT                              28
6264     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_COEFF_EQ2_REQ                                     (0x1<<29) // [DEBUG_BIT]: use programmable coefficients in Phase2 EQ
6265     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_USE_COEFF_EQ2_REQ_SHIFT                               29
6266     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_EN_LP_COEFF_MATCH                                     (0x1<<30) // enable LP coeffcient match checking in default/noraml Phase2 EQ
6267     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_EN_LP_COEFF_MATCH_SHIFT                               30
6268     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_ENA_PH2_PRESET_COEFF                                  (0x1<<31) // [DEBUG_BIT]: enable conversion of preset to coefficients to serdes when LP is always a preset use Phase2 EQ
6269     #define PCIEIP_REG_REG_PHY_CTL_13_REG_GEN3_ENA_PH2_PRESET_COEFF_SHIFT                            31
6270 #define PCIEIP_REG_REG_PHY_CTL_14                                                                    0x001848UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6271     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EQTS2_PRESET                                          (0xf<<0) // (PL_FIX_15) Transmitter preset to transmit in EP EQ TS2s
6272     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EQTS2_PRESET_SHIFT                                    0
6273     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EQTS2_RXHINT                                          (0x7<<4) // (PL_FIX_15) Receiver preset hint to transmit in EP EQ TS2s
6274     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EQTS2_RXHINT_SHIFT                                    4
6275     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ0_TO                                      (0x1<<7) // [SEMI_FUNCTIONAL]: Extend EQ until Phase0 timeout for Normal EQ handshaking
6276     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ0_TO_SHIFT                                7
6277     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ1_TO                                      (0x1<<8) // [SEMI_FUNCTIONAL]: Extend EQ until Phase1 timeout for Normal EQ handshaking
6278     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ1_TO_SHIFT                                8
6279     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ2_TO                                      (0x1<<9) // [SEMI_FUNCTIONAL]: Extend EQ until Phase2 timeout for Normal EQ handshaking
6280     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ2_TO_SHIFT                                9
6281     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ3_TO                                      (0x1<<10) // [SEMI_FUNCTIONAL]: Extend EQ until Phase3 timeout for Normal EQ handshaking
6282     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_EQ3_TO_SHIFT                                10
6283     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH0_TIMEOUT                                    (0x1<<11) // Disable timeout for Equalization Phase0
6284     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH0_TIMEOUT_SHIFT                              11
6285     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH1_TIMEOUT                                    (0x1<<12) // Disable timeout for Equalization Phase1
6286     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH1_TIMEOUT_SHIFT                              12
6287     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH2_TIMEOUT                                    (0x1<<13) // Disable timeout for Equalization Phase2
6288     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH2_TIMEOUT_SHIFT                              13
6289     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH3_TIMEOUT                                    (0x1<<14) // Disable timeout for Equalization Phase3
6290     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_DIS_EQ_PH3_TIMEOUT_SHIFT                              14
6291     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_L1ONLY_RECOVLOCK_TO                         (0x1<<15) // [SEMI_FUNCTIONAL]: Extend timeout in RecovRecvrLock State through L1 exit recovery
6292     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_L1ONLY_RECOVLOCK_TO_SHIFT                   15
6293     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_RECOVLOCK_TO                                (0x1<<16) // [SEMI_FUNCTIONAL]: Extend timeout in RecovRecvrLock State through any exit recovery
6294     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_RECOVLOCK_TO_SHIFT                          16
6295     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_SEL                       (0x1<<17) // [SEMI_FUNCTIONAL]: Extend programmable timeout select control in RecovRecvrLock State
6296     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_SEL_SHIFT                 17
6297     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_VALUE                     (0x1f<<18) // [SEMI_FUNCTIONAL]: Extend programmable timeout value in RecovRecvrLock State
6298     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_EN_EXTEND_PRGM_RECOVLOCK_TO_VALUE_SHIFT               18
6299     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_PH2_EVAL_WAIT_DELAY                                   (0x1ff<<23) // programmable wait delay in Phase2 of equalization
6300     #define PCIEIP_REG_REG_PHY_CTL_14_REG_GEN3_PH2_EVAL_WAIT_DELAY_SHIFT                             23
6301 #define PCIEIP_REG_REG_PHY_CTL_15                                                                    0x00184cUL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0
6302 #define PCIEIP_REG_REG_PHY_CTL_16                                                                    0x001854UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6303     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_ENTRY                                         (0x3ffff<<0) // Gen1/Gen2 deemphasis register control programming of coefficients for preset-0(-6dB) and preset-1(-3.5dB) in the format {C+1[5:0],C0[5:0],C_1[5:0]}
6304     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_ENTRY_SHIFT                                   0
6305     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_INDEX                                         (0x1<<18) // Gen1/Gen2 deemphasis register control programming index for preset 0 and 1 0: points to the preset 0 coefficients(-6dB) 1: points to the preset 1 coefficients(-3.5dB)
6306     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_INDEX_SHIFT                                   18
6307     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_WRSTB                                         (0x1<<19) // Gen1/Gen2 deemphasis register control programming write strobe for Preset 0 and 1
6308     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_WRSTB_SHIFT                                   19
6309     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_SEL                                           (0x1<<20) // Gen2 deemphasis register select control bit to change from Preset-1(-3.5dB) to preset-0(-6dB)
6310     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN12_DEEMPH_SEL_SHIFT                                     20
6311     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN123_DEEMPH_PRESET_SEL                                   (0x1<<21) // Select control bit for the read status of the gen1/2 and gen2 lut entry 18-bit value poining to the corresponding index. 0: Selects Gen3 read preset lut pointing to the reg_gen3_preset_lut_index value 1: Selects Gen1/2 read preset lut pointing to the reg_gen12_deemph_index value
6312     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN123_DEEMPH_PRESET_SEL_SHIFT                             21
6313     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_IGNORE_SERDES_EVALDC                                  (0x1<<22) // [DEBUG_BIT]: Ignore serdes direction change and controls from the MAC register
6314     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_IGNORE_SERDES_EVALDC_SHIFT                            22
6315     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_OVERRIDE_SERDES_EVALDC_VAL                            (0x3f<<23) // [DEBUG_BITS]: Direction change value for coeff evaluation from the MAC control register
6316     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_OVERRIDE_SERDES_EVALDC_VAL_SHIFT                      23
6317     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC2_EN_COEFFPR_MATCHREJ_TWOTS1                        (0x1<<29) // [DEBUG_BIT]: Phase2: Controls enabling of the two consecutive EQ TS1's for checking preset and coefficient matches
6318     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC2_EN_COEFFPR_MATCHREJ_TWOTS1_SHIFT                  29
6319     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC3_EN_COEFFPR_MATCHREJ_TWOTS1                        (0x1<<30) // [DEBUG_BIT]: Phase3: Controls enabling of the two consecutive EQ TS1's for checking preset and coefficient matches
6320     #define PCIEIP_REG_REG_PHY_CTL_16_REG_GEN3_EC3_EN_COEFFPR_MATCHREJ_TWOTS1_SHIFT                  30
6321     #define PCIEIP_REG_REG_PHY_CTL_16_REG_CLR_RECOV_EQ_SM_HIST                                       (0x1<<31) // [DEBUG_BIT]: clears the previous statate transitions captured for recovery eq statemachine in ph2(EP) and ph3(RC)
6322     #define PCIEIP_REG_REG_PHY_CTL_16_REG_CLR_RECOV_EQ_SM_HIST_SHIFT                                 31
6323 #define PCIEIP_REG_REG_PHY_CTL_17                                                                    0x001858UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6324     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRECTRL_LSB_EN                            (0x1<<0) // AFE TX deemphasis register override enable control bit for prectrl[1:0] LSB two bits
6325     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRECTRL_LSB_EN_SHIFT                      0
6326     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRE_CTRL_LSB_VAL                          (0x3<<1) // AFE TX deemphasis register control two LSB bit value for prectrl[1:0]
6327     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_PRE_CTRL_LSB_VAL_SHIFT                    1
6328     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_EN                               (0x1<<3) // AFE TX deemphasis register override enable control bit for main[1:0] LSB two bits
6329     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_EN_SHIFT                         3
6330     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_VAL                              (0x3<<4) // AFE TX deemphasis register control two LSB bit value for main[1:0]
6331     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_MAIN_LSB_VAL_SHIFT                        4
6332     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_EN                           (0x1<<6) // AFE TX deemphasis register override enable control bit for postctrl[1:0] LSB two bits
6333     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_EN_SHIFT                     6
6334     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_VAL                          (0x3<<7) // AFE TX deemphasis register control two LSB bit value for postctrl[1:0]
6335     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POSTCTRL_LSB_VAL_SHIFT                    7
6336     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_EN                                   (0x1<<9) // AFE TX deemphasis register override enable control bit for prectrl[4:2] upper three bits
6337     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_EN_SHIFT                             9
6338     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_VAL                                  (0x7<<10) // AFE TX deemphasis register control upper three bit value for prectrl[4:2]
6339     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_PRE_CTRL_UPPER_VAL_SHIFT                            10
6340     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_EN                                  (0x1<<13) // AFE TX deemphasis register override enable control bit for main[4:2] upper five bits
6341     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_EN_SHIFT                            13
6342     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_VAL                                 (0x1f<<14) // AFE TX deemphasis register control upper five bit value for main[6:2]
6343     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_MAIN_CTRL_UPPER_VAL_SHIFT                           14
6344     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_EN                                  (0x1<<19) // AFE TX deemphasis register override enable control bit for postctrl[5:2] upper four bits
6345     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_EN_SHIFT                            19
6346     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_VAL                                 (0xf<<20) // AFE TX deemphasis register control upper four bit value for postctrl[5:2]
6347     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_POST_CTRL_UPPER_VAL_SHIFT                           20
6348     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_EN                                  (0x1<<24) // AFE TX deemphasis register override enable control bit for post2[3:0] four bits
6349     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_EN_SHIFT                            24
6350     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_VAL                                 (0xf<<25) // AFE TX deemphasis register control for four bit value for post2[3:0]
6351     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN123_TX_DEEMPH_POST2_VAL_SHIFT                           25
6352     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH2_RXEVAL_TO_SERDES                             (0x1<<29) // Phase2: Skips Rx EQ evaluation to Serdes and wait for 22msec extended timeout to occur.
6353     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH2_RXEVAL_TO_SERDES_SHIFT                       29
6354     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH3_RXEVAL_TO_SERDES                             (0x1<<30) // Phase3: Skips Rx EQ evaluation to Serdes and wait for 22msec extended timeout to occur.
6355     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_SKIP_PH3_RXEVAL_TO_SERDES_SHIFT                       30
6356     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_RX_RESET_EIEOS                                        (0x1<<31) // RX reset EIEOS control bit for TS1(SYM6-Bit2) in Recovery.Equalizations. Default zero value
6357     #define PCIEIP_REG_REG_PHY_CTL_17_REG_GEN3_RX_RESET_EIEOS_SHIFT                                  31
6358 #define PCIEIP_REG_REG_PHY_CTL_18                                                                    0x00185cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6359     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_EN                                              (0x1<<0) // Enable bit to control the registered programmed FULL SWING value in Phase 1 of eualization
6360     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_EN_SHIFT                                        0
6361     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_VAL                                             (0x3f<<1) // Registered programmed 6-bit FULL SWING value in Phase 1 of eualization. The hardware default value 6'h28(FS=40).
6362     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_FS_VAL_SHIFT                                       1
6363     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_EN                                              (0x1<<7) // Enable bit to control the registered programmed LOW FREQUENCY value in Phase 1 of eualization
6364     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_EN_SHIFT                                        7
6365     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_VAL                                             (0x3f<<8) // Registered programmed 6-bit LOW FREQUENCY value in Phase 1 of eualization. The hardware default value 6'hC(LF=12).
6366     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EQ_LF_VAL_SHIFT                                       8
6367     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_RX_COEFF_SEL                                      (0x1<<14) // Selects to the received coefficients in the phase 2 of equalization. The default coefficientis a defined value.
6368     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_RX_COEFF_SEL_SHIFT                                14
6369     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DISABLE_REQ_WAIT_1USEC                            (0x1<<15) // [DEBUG_BIT]: Disables the 1usec wait time for LP to response for preset or coeff req in phase2(EP and phase3(RC) modes..
6370     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DISABLE_REQ_WAIT_1USEC_SHIFT                      15
6371     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_ENA_EC0_ECHO_PRESET                                   (0x1<<16) // Enables EC0 echo use preset bit in EP mode
6372     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_ENA_EC0_ECHO_PRESET_SHIFT                             16
6373     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_ENA_EC2_ECHO_PRESET                                (0x1<<17) // Enables EC2 echo use preset bit in RC mode
6374     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_ENA_EC2_ECHO_PRESET_SHIFT                          17
6375     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_USE_PRESET_EQ3_REQ                                 (0x1<<18) // Use programmable preset Phase3 EQ in RC mode
6376     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_USE_PRESET_EQ3_REQ_SHIFT                           18
6377     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_IGNORE_USE_PRESET_CHECK                           (0x1<<19) // [DEBUG_BIT]: Ignore the receive ec2 use preset check in phase2 of equalization for the eq eval state machine
6378     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_IGNORE_USE_PRESET_CHECK_SHIFT                     19
6379     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH3_DIS_RULE_CHECK                                    (0x1<<20) // [DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 3 of equalization in EP mode
6380     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH3_DIS_RULE_CHECK_SHIFT                              20
6381     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH2_DIS_RULE_CHECK                                    (0x1<<21) // [DEBUG_BIT]: Disables Preset and coefficient rule check error in phase 2 of equalization in RC mode
6382     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_PH2_DIS_RULE_CHECK_SHIFT                              21
6383     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_IGNORE_USE_PRESET_REDO_CHECK                          (0x1<<22) // [DEBUG_BIT]: Ignores the phase 2 received usepreset bit when checking for preset mismatch at the end of equalization
6384     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_IGNORE_USE_PRESET_REDO_CHECK_SHIFT                    22
6385     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_SKIP_EQ_PHASE23                                    (0x1<<23) // RC Mode: Skips equalizationphas 2 and Phase 3.
6386     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_SKIP_EQ_PHASE23_SHIFT                              23
6387     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DIS_EVAL_COEFF_MATCH                              (0x1<<24) // [DEBUG_BIT]: EP mode Phase2: Disables the coefficient match reject status in EVAL and Adjust eval states
6388     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC2_DIS_EVAL_COEFF_MATCH_SHIFT                        24
6389     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC3_DIS_EVAL_COEFF_MATCH                              (0x1<<25) // [DEBUG_BIT]: RC mode Phase3: Disables the coefficient match reject status in EVAL and Adjust eval states
6390     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_EC3_DIS_EVAL_COEFF_MATCH_SHIFT                        25
6391     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_FORCE_EQ_EVERY_SPDCHG                              (0x1<<26) // [DEBUG_BIT]: RC mode : Forces Gen3 equalization for every Speed change over from Gen1-Gen3
6392     #define PCIEIP_REG_REG_PHY_CTL_18_REG_GEN3_RC_FORCE_EQ_EVERY_SPDCHG_SHIFT                        26
6393     #define PCIEIP_REG_REG_PHY_CTL_18_REG_EQ_STATIC_DEBUG_ADDR                                       (0x1f<<27) // [DEBUG_BITS]: Equalization static debug 5-bit address control for reading pl_eq_static_debug data at address 0x1d94
6394     #define PCIEIP_REG_REG_PHY_CTL_18_REG_EQ_STATIC_DEBUG_ADDR_SHIFT                                 27
6395 #define PCIEIP_REG_PL_GEN3_ENA_FRMERR                                                                0x001860UL //Access:RW   DataWidth:0x20  Notes: There are more Gen3 framing error enable bits in reg_phy_ctl_9 register.  Chips: BB_A0 BB_B0
6396     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_ILLEGAL_OS_AFTER_EDS_ERR                          (0x1<<0) // Enable Illegal Ordered Set After EDS Error. When this bit is set to '1', report Gen3 framing error if an OS other than EIOS, EIEOS, or SKPOS is detected after an EDS token.
6397     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_ILLEGAL_OS_AFTER_EDS_ERR_SHIFT                    0
6398     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_AFTER_SDS_ERR                                  (0x1<<1) // Enable Ordered Set After SDS Error. When this bit is set to '1', report Gen3 framing error if an OS is detected right after an SDS token.
6399     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_AFTER_SDS_ERR_SHIFT                            1
6400     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_NO_EDS_ERR                                     (0x1<<2) // Enable Ordered Set with No EDS Error. When this bit is set to '1', report Gen3 framing error if an OS is detected without a preceding EDS token while in middle of a data stream.
6401     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_OS_NO_EDS_ERR_SHIFT                               2
6402     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FCRC_ERR                                      (0x1<<3) // Enable Bad Framing CRC Error. When this bit is set to '1', report Gen3 framing error if bad framing CRC is detected in a STP token.
6403     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FCRC_ERR_SHIFT                                3
6404     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FP_ERR                                        (0x1<<4) // Enable Bad Framing Parity Error. When this bit is set to '1', report Gen3 framing error if bad framing parity is detected in a STP token.
6405     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FP_ERR_SHIFT                                  4
6406     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_EDB_ERR                                       (0x1<<5) // Enable Bad EDB Error. When this bit is set to '1', report Gen3 framing error if a bad EDB token is detected.
6407     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_EDB_ERR_SHIFT                                 5
6408     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FRAMING_SYM_ERR                               (0x1<<6) // Enable Bad Framing Symbol Error. When this bit is set to '1', report Gen3 framing error if a framing token is not detected at the expection position.
6409     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_BAD_FRAMING_SYM_ERR_SHIFT                         6
6410     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_DATA_AFTER_EDS_ERR                                (0x1<<7) // Enable Data After EDS Error. When this bit is set to '1', report Gen3 framing error if a data block is detected after an EDS token.
6411     #define PCIEIP_REG_PL_GEN3_ENA_FRMERR_GEN3_ENA_DATA_AFTER_EDS_ERR_SHIFT                          7
6412 #define PCIEIP_REG_PL_LPBK_MASTER_CTL0                                                               0x001900UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6413     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENA                                           (0x1<<0) // Loopback Master Enable. Setting this bit to '1' enables the master loopback operation. Normally, if lpbk_master_len is set to '0', software has to clear this bit to stop the operation. Otherwise, hardware automatically clears this bit when the operation is done. In case the loopback operation is timeout during Loopback.Entry state, hardware clears this bit before returning to Detect state regardless of the setting of lpbk_master_len.
6414     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENA_SHIFT                                     0
6415     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENTRY                                         (0x1<<1) // Loopback Master Entry State. If this bit is set to '1', loopback is entered from Recovery.Idle state; otherwise, loopback is entered from Configuration.Linkwidth.Start state.
6416     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ENTRY_SHIFT                                   1
6417     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SET_COMPL_RECV                                (0x1<<2) // Loopback Master Set Compliance Receive. If this bit is set to '1', the Compliance Receive bit in TS1 is set to '1' when loopback master initiates the loopback operation. This feature allows Loopback Slave to enter Loopback.Active state without achieving symbol lock or block alignment.
6418     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SET_COMPL_RECV_SHIFT                          2
6419     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_AUTO_COMPL_RECV                               (0x1<<3) // Loopback Master Automatically Set Compliance Receive. If this bit is set to '1', hardware automatically sets the Compliance Receive bit in TS1 to '1' during Loopback.Entry state when loopback is entered from Configuration.Linkwidth.Start state and Gen3 is the highest common speed.
6420     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_AUTO_COMPL_RECV_SHIFT                         3
6421     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_FRC_SETTING                                   (0x1<<4) // Loopback Master Force Setting. When loopback is entered from Recov.Idle state and this bit is set to '1', hardware applies the settings specified in lpbk_master_slave_setting and lpbak_master_tx_setting registers.
6422     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_FRC_SETTING_SHIFT                             4
6423     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SKPOS                                         (0x1<<5) // Loopback Master Skip Ordered Set. When this bit is set, SKP OS are periodically inserted to loopback data. If data is generated by PHY, MAC provides SKP OS to PHY using a req/ack handshake. If it is Gen3 and data is generated by PHY without framing, this bit is ignored.
6424     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_SKPOS_SHIFT                                   5
6425     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ONE_SKPOS                                     (0x1<<6) // Loopback Master One Skip Ordered Set. PCIE Spec requires that in Gen3 loopback master inserts two SKIP ordered sets for each SKIP OS interval. For testing purpose, when this bit is set to '1', hardware inserts only one SKP OS for each interval.
6426     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_ONE_SKPOS_SHIFT                               6
6427     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_2                                                  (0x1<<7) //
6428     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_2_SHIFT                                            7
6429     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_PATTERN                                       (0x1f<<8) // Loopback Master Pattern. This field specifies the data pattern to be transmitted during Loopback.Active state. 5'b00000: reserved  5'b00001: Serdes PRBS7 pattern  5'b00010: Serdes PRBS15 pattern  5'b00011: Serdes PRBS23 pattern  5'b00100: Serdes PRBS31 pattern  5'b00101: Serdes 1010 pattern  5'b00110: Serdes 1100 pattern  5'b00111: Serdes low frequency pattern  5'b01000: reserved  5'b01001: Serdes PRBS7 pattern (with framing for Gen3)  5'b01010: Serdes PRBS15 pattern (with framing for Gen3)  5'b01011: Serdes PRBS23 pattern (with framing for Gen3)  5'b01100: Serdes PRBS31 pattern (with framing for Gen3)  5'b01101: Serdes 1010 pattern (with framing for Gen3)  5'b01110: Serdes 1100 pattern (with framing for Gen3)  5'b01111: Serdes low frequency pattern (with framing for Gen3)  5'b10000: MAC Compliance pattern  5'b10001: MAC Modified Compliance pattern  Others : reserved
6430     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_PATTERN_SHIFT                                 8
6431     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_1                                                  (0x7<<13) //
6432     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_UNUSED_1_SHIFT                                            13
6433     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_LEN                                           (0xffff<<16) // Loopback Master Length. This field specifies the length of the loopback operation in milliseconds. When it is set to '0', software has to clear the lpbk_master_ena bit to stop the operation. When it is set to a non-zero value, hardware automatically clears the lpbk_master_ena bit after the specified time.
6434     #define PCIEIP_REG_PL_LPBK_MASTER_CTL0_LPBK_MASTER_LEN_SHIFT                                     16
6435 #define PCIEIP_REG_PL_LPBK_MASTER_CTL1                                                               0x001904UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6436     #define PCIEIP_REG_PL_LPBK_MASTER_CTL1_LPBK_MASTER_ENTRY_TMOUT                                   (0x7f<<0) // Loopback Master Entry Timeout. While in Loopback.Entry state, if Compliance Receive bit was not set in transmitting TS1 and Loopback Master doesn't receive the feedback from Loopback Slave, it will transition to Detect state after a specified time. This field specifies the timeout in milliseconds. The timeout value must be less than 100ms.
6437     #define PCIEIP_REG_PL_LPBK_MASTER_CTL1_LPBK_MASTER_ENTRY_TMOUT_SHIFT                             0
6438 #define PCIEIP_REG_PL_LPBK_MASTER_STAT                                                               0x001908UL //Access:R    DataWidth:0x20  The loopback status register is cleared when lpbk_master_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6439     #define PCIEIP_REG_PL_LPBK_MASTER_STAT_LPBK_MASTER_STAT                                          (0x1<<0) // Loopback Master Status. This is the status of the last loopback operation. 1'b0: completed normally 1'b1: exited because of timeout during Loopback.Entry state
6440     #define PCIEIP_REG_PL_LPBK_MASTER_STAT_LPBK_MASTER_STAT_SHIFT                                    0
6441 #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING                                                      0x00190cUL //Access:RW   DataWidth:0x20  This register specifies the Slave's TX settings that Loopback Master will transmit in TS1 during Loopback.Entry state in following cases: 1. Entered from Configuration.Linkwidth.Start and changed to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master_frc_setting is set to '1'. If data rate is Gen3, Loopback Master will automatically set EC field (i.e. TS1, byte6[1:0]) to 2'b10 or 2'b11 depending on whether it is EP or RC respectively.  Chips: BB_A0 BB_B0
6442     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_RXPRESET                         (0x7<<0) // Loopback Master TS1 Receiver Preset Hint. This value is sent in TS1, byte6[2:0] if current rate is Gen1/Gen2 and EQ TS1's are sent.
6443     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_RXPRESET_SHIFT                   0
6444     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_TXPRESET                         (0xf<<3) // Loopback Master TS1 Transmitter Preset. This value is sent in TS1, byte6[6:3] if the current rate is Gen3 or current rate is Gen1/2 and EQ TS1's are sent.
6445     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_TXPRESET_SHIFT                   3
6446     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_USEPRESET                        (0x1<<7) // Loopback Master TS1 Use Preset. This value is sent in TS1, byte6[7] if the current rate is Gen3.
6447     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_USEPRESET_SHIFT                  7
6448     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_PRECURSOR                        (0x3f<<8) // Loopback Master TS1 Pre-Cursor Coefficient. This value is sent in TS1, byte7[5:0] if the current rate is Gen3.
6449     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_PRECURSOR_SHIFT                  8
6450     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_CURSOR                           (0x3f<<14) // Loopback Master TS1 Cursor Coefficient. This value is sent in TS1, byte8[5:0] if the current rate is Gen3.
6451     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_CURSOR_SHIFT                     14
6452     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_POSTCURSOR                       (0x3f<<20) // Loopback Master TS1 Post-cursor Coefficient. This value is sent in TS1, byte9[5:0] if the current rate is Gen3.
6453     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_POSTCURSOR_SHIFT                 20
6454     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_G2_DEEMPH                        (0x1<<26) // Loopback Master TS1 Selectable De-emphasis. This value is sent in TS1, byte4[6] if the highest common rate is Gen2.
6455     #define PCIEIP_REG_PL_LPBK_MASTER_SLAVE_SETTING_LPBK_MASTER_TS1_G2_DEEMPH_SHIFT                  26
6456 #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING                                                         0x001910UL //Access:RW   DataWidth:0x20  This register specifies the Loopback Master TX settings in following cases: 1. Entered from Configuration.Linkwidth.Start and changed to a new speed. 2. Entered from Recovery.Idle and bit lpbk_master_frc_setting is set to '1'.  Chips: BB_A0 BB_B0
6457     #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_LPBK_MASTER_G3_TXDEEMPH                             (0x3ffff<<0) // Loopback Master Gen3 TX Deemphasis. This TX setting is used when loopback is in Gen3 rate.
6458     #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_LPBK_MASTER_G3_TXDEEMPH_SHIFT                       0
6459     #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_LPBK_MASTER_G2_TXDEEMPH                             (0x3<<18) // Loopback Master Gen2 Deemphasis. This TX setting is used when loopback is in Gen2 rate. Notes that for Gen1 the TX deemphasis is always set to -3.5db.
6460     #define PCIEIP_REG_PL_LPBK_MASTER_TX_SETTING_LPBK_MASTER_G2_TXDEEMPH_SHIFT                       18
6461 #define PCIEIP_REG_PL_SW_LTSSM_CTL                                                                   0x001930UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6462     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_ENA                                                  (0x1<<0) // Software LTSSM Enable. Setting this bit to '1' allows software to take control of the LTSSM.
6463     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_ENA_SHIFT                                            0
6464     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_DLYSTART                                             (0x1<<1) // Software LTSSM Delay Start. When this bit is set together with sw_ltssm_ena, hardware continues to operate as normal until LTSSM reaches to the state specified by sw_ltssm_topst and sw_ltssm_subst. Once software starts controlling LTSSM, it continues to do so until sw_ltssm_ena is reset to '0'. This feature allows software to control LTSSM in some certain states but not all.
6465     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_DLYSTART_SHIFT                                       1
6466     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_UPDT                                                 (0x1<<2) // Software LTSSM Update. Writing a '1' to this bit updates the internal software LTSSM state with the state specified by sw_ltssm_topst and sw_ltssm_subst. If software is in control, the new state will be applied to LTSSM. This bit is self-cleared, so reading always retuns '0'.
6467     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_UPDT_SHIFT                                           2
6468     #define PCIEIP_REG_PL_SW_LTSSM_CTL_LTSSM_TMOUT_DIS                                               (0x1<<3) // LTSSM Timeout Disable. When this bit is set to '1', all LTSSM timeouts are disabled.
6469     #define PCIEIP_REG_PL_SW_LTSSM_CTL_LTSSM_TMOUT_DIS_SHIFT                                         3
6470     #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED0                                                       (0xf<<4) //
6471     #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED0_SHIFT                                                 4
6472     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_SUBST                                                (0x1ff<<8) // Software LTSSM Sub-level State. This field specifies the state of the sub-level state machine that software wants LTSSM to enter. The updating sub-level SM is selected based on the top-level state.
6473     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_SUBST_SHIFT                                          8
6474     #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED1                                                       (0x7<<17) //
6475     #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED1_SHIFT                                                 17
6476     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_TOPST                                                (0x1ff<<20) // Software LTSSM Top-level State. This field specifies the state of the top-level state machine that software wants LTSSM to enter.
6477     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_TOPST_SHIFT                                          20
6478     #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED2                                                       (0x3<<29) //
6479     #define PCIEIP_REG_PL_SW_LTSSM_CTL_UNUSED2_SHIFT                                                 29
6480     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_INT_ENA                                              (0x1<<31) // Software LTSSM Internal Enable. This bit reflects the internal software LTSSM enable that is set to '1' only when S/W is actually in control of the LTSSM. If sw_ltssm_dlystart is '1', the internal enable is not set until LTSSM reaches the desired state.
6481     #define PCIEIP_REG_PL_SW_LTSSM_CTL_SW_LTSSM_INT_ENA_SHIFT                                        31
6482 #define PCIEIP_REG_PCIE_STATIS_CTL                                                                   0x001940UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6483     #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_ENA                                               (0x1<<0) // PCIE Statistic Enable. Setting this bit to '1' enables the PCIE statistic collection. Hardware will count various things such as the number of TLP, DLLP, OS bytes transferred in both RX and TX direction, the number of detected errors etc. When this bit is reset to '0', the counting stops and software can read the results. This bit can be automatically cleared after the specified time if pcie_statis_len is non-zero. All statistic read-back registers are cleared when this bit transitions from '0' to '1'.
6484     #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_ENA_SHIFT                                         0
6485     #define PCIEIP_REG_PCIE_STATIS_CTL_UNUSED0                                                       (0x7f<<1) //
6486     #define PCIEIP_REG_PCIE_STATIS_CTL_UNUSED0_SHIFT                                                 1
6487     #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_LEN                                               (0xffffff<<8) // PCIE Statistic Length. This field specifies the PCIE statistic collection time in microseconds. When it is set to '0', software has to clear the pcie_statis_ena bit to stop the operation. When it is set to a non-zero value, hardware automatically clears the enable bit after the specified time.
6488     #define PCIEIP_REG_PCIE_STATIS_CTL_PCIE_STATIS_LEN_SHIFT                                         8
6489 #define PCIEIP_REG_PCIE_TXTLP_STATIS_LO                                                              0x001944UL //Access:R    DataWidth:0x20  PCIE TX TLP Statistic Low 32 bits. This is the number of TLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6490 #define PCIEIP_REG_PCIE_TXTLP_STATIS_HI                                                              0x001948UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6491     #define PCIEIP_REG_PCIE_TXTLP_STATIS_HI_PCIE_TXTLP_STATIS_HI                                     (0xff<<0) // PCIE TX TLP Statistic High 8 bits. This is the number of TLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
6492     #define PCIEIP_REG_PCIE_TXTLP_STATIS_HI_PCIE_TXTLP_STATIS_HI_SHIFT                               0
6493 #define PCIEIP_REG_PCIE_TXDLLP_STATIS_LO                                                             0x00194cUL //Access:R    DataWidth:0x20  PCIE TX DLLP Statistic Low 32 bits. This is the number of DLLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6494 #define PCIEIP_REG_PCIE_TXDLLP_STATIS_HI                                                             0x001950UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6495     #define PCIEIP_REG_PCIE_TXDLLP_STATIS_HI_PCIE_TXDLLP_STATIS_HI                                   (0xff<<0) // PCIE TX DLLP Statistic High 8 bits. This is the number of DLLP bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
6496     #define PCIEIP_REG_PCIE_TXDLLP_STATIS_HI_PCIE_TXDLLP_STATIS_HI_SHIFT                             0
6497 #define PCIEIP_REG_PCIE_TXOS_STATIS_LO                                                               0x001954UL //Access:R    DataWidth:0x20  PCIE TX Ordered Set Statistic Low 32 bits. This is the number of ordered set bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6498 #define PCIEIP_REG_PCIE_TXOS_STATIS_HI                                                               0x001958UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6499     #define PCIEIP_REG_PCIE_TXOS_STATIS_HI_PCIE_TXOS_STATIS_HI                                       (0xff<<0) // PCIE TX Ordered Set Statistic High 8 bits. This is the number of ordered set bytes that have been trasmitted. It is cleared when pcie_statis_ena goes from '0' to '1'.
6500     #define PCIEIP_REG_PCIE_TXOS_STATIS_HI_PCIE_TXOS_STATIS_HI_SHIFT                                 0
6501 #define PCIEIP_REG_PCIE_RXTLP_STATIS_LO                                                              0x00195cUL //Access:R    DataWidth:0x20  PCIE RX TLP Statistic Low 32 bits. This is the number of TLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6502 #define PCIEIP_REG_PCIE_RXTLP_STATIS_HI                                                              0x001960UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6503     #define PCIEIP_REG_PCIE_RXTLP_STATIS_HI_PCIE_RXTLP_STATIS_HI                                     (0xff<<0) // PCIE RX TLP Statistic High 8 bits. This is the number of TLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
6504     #define PCIEIP_REG_PCIE_RXTLP_STATIS_HI_PCIE_RXTLP_STATIS_HI_SHIFT                               0
6505 #define PCIEIP_REG_PCIE_RXDLLP_STATIS_LO                                                             0x001964UL //Access:R    DataWidth:0x20  PCIE RX DLLP Statistic Low 32 bits. This is the number of DLLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6506 #define PCIEIP_REG_PCIE_RXDLLP_STATIS_HI                                                             0x001968UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6507     #define PCIEIP_REG_PCIE_RXDLLP_STATIS_HI_PCIE_RXDLLP_STATIS_HI                                   (0xff<<0) // PCIE RX DLLP Statistic High 8 bits. This is the number of DLLP bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
6508     #define PCIEIP_REG_PCIE_RXDLLP_STATIS_HI_PCIE_RXDLLP_STATIS_HI_SHIFT                             0
6509 #define PCIEIP_REG_PCIE_RXOS_STATIS_LO                                                               0x00196cUL //Access:R    DataWidth:0x20  PCIE RX Ordered Set Statistic Low 32 bits. This is the number of ordered set bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6510 #define PCIEIP_REG_PCIE_RXOS_STATIS_HI                                                               0x001970UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6511     #define PCIEIP_REG_PCIE_RXOS_STATIS_HI_PCIE_RXOS_STATIS_HI                                       (0xff<<0) // PCIE RX Ordered Set Statistic High 8 bits. This is the number of ordered set bytes that have been received. It is cleared when pcie_statis_ena goes from '0' to '1'.
6512     #define PCIEIP_REG_PCIE_RXOS_STATIS_HI_PCIE_RXOS_STATIS_HI_SHIFT                                 0
6513 #define PCIEIP_REG_PCIE_PLRXERR_STATIS                                                               0x001974UL //Access:R    DataWidth:0x20  PL Receiver Error Statistic. Number of errors detected by Physical Layer Receiver. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6514 #define PCIEIP_REG_PCIE_RXDLLPERR_STATIS                                                             0x001978UL //Access:R    DataWidth:0x20  RX DLLP Error Statistic. Number of DLLP CRC errors detected by Data Link Layer. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6515 #define PCIEIP_REG_PCIE_RXTLPERR_STATIS                                                              0x00197cUL //Access:R    DataWidth:0x20  RX TLP Error Statistic. Number of TLP LCRC and sequence number errors detected by Data Link Layer. It is cleared when pcie_statis_ena goes from '0' to '1'.  Chips: BB_A0 BB_B0
6516 #define PCIEIP_REG_LTSSM_STATIS_CTL                                                                  0x0019a0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6517     #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_ENA                                             (0x1<<0) // LTSSM Statistic Enable. Setting this bit to '1' enables the LTSSM statisic collection. When this bit is reset to '0', information is frozen so S/W can read the results. All statistic registers are reset when this bit transitions from '0' to '1'.
6518     #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_ENA_SHIFT                                       0
6519     #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_AUTOINC                                         (0x1<<1) // LTSSM Statistic Auto Increment. When this bit is set to '1', hardware automatically increases the ltssm_statis_rdaddr by 1 after register ltssm_statis_N is read.
6520     #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_AUTOINC_SHIFT                                   1
6521     #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_RDADDR                                          (0x1<<2) // LTSSM Statistic Readback Address. ltssm_statis_0 to ltssm_statis_N are stored in FIFOs. This field indicates the current readback address of the LTSSM Statistic FIFO. Reading ltssm_statis_0 to ltssm_statis_N registers return the values stored at current address. Software writes to this field to specify the starting FIFO offset where it wants to read back LTSSM statistic data.
6522     #define PCIEIP_REG_LTSSM_STATIS_CTL_LTSSM_STATIS_RDADDR_SHIFT                                    2
6523 #define PCIEIP_REG_LTSSM_STATIS_0                                                                    0x0019a4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6524     #define PCIEIP_REG_LTSSM_STATIS_0_EQ_PH1_TIME                                                    (0xffff<<0) // Equalization Phase 1 Time. This field contains the time that LTSSM spent in Equalization Phase 1 state. The unit is microsecond.
6525     #define PCIEIP_REG_LTSSM_STATIS_0_EQ_PH1_TIME_SHIFT                                              0
6526     #define PCIEIP_REG_LTSSM_STATIS_0_EQ_PH0_TIME                                                    (0xffff<<16) // Equalization Phase 0 Time. This field contains the time that LTSSM spent in Equalization Phase 0 state. The unit is microsecond.
6527     #define PCIEIP_REG_LTSSM_STATIS_0_EQ_PH0_TIME_SHIFT                                              16
6528 #define PCIEIP_REG_LTSSM_STATIS_1                                                                    0x0019a8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6529     #define PCIEIP_REG_LTSSM_STATIS_1_EQ_PH3_TIME                                                    (0xffff<<0) // Equalization Phase 3 Time. This field contains the time that LTSSM spent in Equalization Phase 3 state. The unit is microsecond.
6530     #define PCIEIP_REG_LTSSM_STATIS_1_EQ_PH3_TIME_SHIFT                                              0
6531     #define PCIEIP_REG_LTSSM_STATIS_1_EQ_PH2_TIME                                                    (0xffff<<16) // Equalization Phase 2 Time. This field contains the time that LTSSM spent in Equalization Phase 2 state. The unit is microsecond.
6532     #define PCIEIP_REG_LTSSM_STATIS_1_EQ_PH2_TIME_SHIFT                                              16
6533 #define PCIEIP_REG_LTSSM_STATIS_2                                                                    0x0019acUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6534     #define PCIEIP_REG_LTSSM_STATIS_2_PWR_ACK_TIME                                                   (0xff<<0) // Power State Acknowledge Time. This field contains the time since power state changed to when Serdes acknowledged. The unit is microsecond.
6535     #define PCIEIP_REG_LTSSM_STATIS_2_PWR_ACK_TIME_SHIFT                                             0
6536     #define PCIEIP_REG_LTSSM_STATIS_2_SYM_LOCK_TIME                                                  (0xff<<8) // Symbol Lock Time. This field contains the time it took Serdes to achieve symbol lock after PLL locked. The unit is microsecond.
6537     #define PCIEIP_REG_LTSSM_STATIS_2_SYM_LOCK_TIME_SHIFT                                            8
6538     #define PCIEIP_REG_LTSSM_STATIS_2_ELECIDLE_TIME                                                  (0xffff<<16) // Electrical Idle Time. This field contains the time that LTSSM spent in Electrical Idle state. The unit is microsecond.
6539     #define PCIEIP_REG_LTSSM_STATIS_2_ELECIDLE_TIME_SHIFT                                            16
6540 #define PCIEIP_REG_LTSSM_STATIS_3                                                                    0x0019b0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6541     #define PCIEIP_REG_LTSSM_STATIS_3_RECOV_TIME                                                     (0xffff<<0) // Recovery Time. This field contains the time that LTSSM spent in Recovery state. The unit is microsecond.
6542     #define PCIEIP_REG_LTSSM_STATIS_3_RECOV_TIME_SHIFT                                               0
6543     #define PCIEIP_REG_LTSSM_STATIS_3_L0S_EXIT_TIME                                                  (0xff<<16) // L0s Exit Time. This field contains the time that LTSSM spent to exit L0s state. The unit is microsecond.
6544     #define PCIEIP_REG_LTSSM_STATIS_3_L0S_EXIT_TIME_SHIFT                                            16
6545 #define PCIEIP_REG_LTSSM_STATIS_CNT                                                                  0x0019b4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6546     #define PCIEIP_REG_LTSSM_STATIS_CNT_RECOV_CNT                                                    (0xffff<<0) // Recovery Entered Count. This field contains the number of times LTSSM entered Recovery state.
6547     #define PCIEIP_REG_LTSSM_STATIS_CNT_RECOV_CNT_SHIFT                                              0
6548     #define PCIEIP_REG_LTSSM_STATIS_CNT_L0S_FAIL_CNT                                                 (0xff<<16) // L0s Exit Failure Count. This field contains the number of L0s exit failures (i.e. LTSSM has to transition from L0s to Recovery).
6549     #define PCIEIP_REG_LTSSM_STATIS_CNT_L0S_FAIL_CNT_SHIFT                                           16
6550 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512                                                          0x001c00UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6551     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_12                                          (0x7f<<0) // For lane 12: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6552     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_12_SHIFT                                    0
6553     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_12                                          (0x1<<7) // For lane 12: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6554     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_12_SHIFT                                    7
6555     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_13                                          (0x7f<<8) // For lane 13 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6556     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_13_SHIFT                                    8
6557     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_13                                          (0x1<<15) // For lane 13 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6558     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_13_SHIFT                                    15
6559     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_14                                          (0x7f<<16) // For lane 14: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6560     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_14_SHIFT                                    16
6561     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_14                                          (0x1<<23) // For lane 14: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6562     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_14_SHIFT                                    23
6563     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_15                                          (0x7f<<24) // For lane 15 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6564     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_ERRS_15_SHIFT                                    24
6565     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_15                                          (0x1<<31) // For lane 15 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6566     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_1512_MCP_LOCK_15_SHIFT                                    31
6567 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118                                                           0x001c04UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6568     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_8                                            (0x7f<<0) // For lane 8: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6569     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_8_SHIFT                                      0
6570     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_8                                            (0x1<<7) // For lane 8: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6571     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_8_SHIFT                                      7
6572     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_9                                            (0x7f<<8) // For lane 9 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6573     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_9_SHIFT                                      8
6574     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_9                                            (0x1<<15) // For lane 9 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6575     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_9_SHIFT                                      15
6576     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_10                                           (0x7f<<16) // For lane 10: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6577     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_10_SHIFT                                     16
6578     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_10                                           (0x1<<23) // For lane 10: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6579     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_10_SHIFT                                     23
6580     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_11                                           (0x7f<<24) // For lane 11 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6581     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_ERRS_11_SHIFT                                     24
6582     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_11                                           (0x1<<31) // For lane 11 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6583     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_118_MCP_LOCK_11_SHIFT                                     31
6584 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74                                                            0x001c08UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6585     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_4                                             (0x7f<<0) // For lane 4: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6586     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_4_SHIFT                                       0
6587     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_4                                             (0x1<<7) // For lane 4: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6588     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_4_SHIFT                                       7
6589     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_5                                             (0x7f<<8) // For lane 5 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6590     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_5_SHIFT                                       8
6591     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_5                                             (0x1<<15) // For lane 5 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6592     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_5_SHIFT                                       15
6593     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_6                                             (0x7f<<16) // For lane 6: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6594     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_6_SHIFT                                       16
6595     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_6                                             (0x1<<23) // For lane 6: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6596     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_6_SHIFT                                       23
6597     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_7                                             (0x7f<<24) // For lane 7 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6598     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_ERRS_7_SHIFT                                       24
6599     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_7                                             (0x1<<31) // For lane 7 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6600     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_74_MCP_LOCK_7_SHIFT                                       31
6601 #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30                                                            0x001c0cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6602     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_0                                             (0x7f<<0) // For lane 0: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6603     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_0_SHIFT                                       0
6604     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_0                                             (0x1<<7) // For lane 0: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6605     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_0_SHIFT                                       7
6606     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_1                                             (0x7f<<8) // For lane 1 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6607     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_1_SHIFT                                       8
6608     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_1                                             (0x1<<15) // For lane 1 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6609     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_1_SHIFT                                       15
6610     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_2                                             (0x7f<<16) // For lane 2: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6611     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_2_SHIFT                                       16
6612     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_2                                             (0x1<<23) // For lane 2: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6613     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_2_SHIFT                                       23
6614     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_3                                             (0x7f<<24) // For lane 3 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the link partner after locking to the Modified Compliance Pattern
6615     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_ERRS_3_SHIFT                                       24
6616     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_3                                             (0x1<<31) // For lane 3 in a multi-lane system: Set by the link partner when it locks to the Modified Compliance Pattern (only reported if this receiver has also locked)
6617     #define PCIEIP_REG_RECEIVED_MCP_ERRORS_30_MCP_LOCK_3_SHIFT                                       31
6618 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512                                                       0x001c10UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6619     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_12                                    (0x7f<<0) // For lane 12: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6620     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_12_SHIFT                              0
6621     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_12                                    (0x1<<7) // For lane 12: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6622     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_12_SHIFT                              7
6623     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_13                                    (0x7f<<8) // For lane 13 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6624     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_13_SHIFT                              8
6625     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_13                                    (0x1<<15) // For lane 13 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6626     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_13_SHIFT                              15
6627     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_14                                    (0x7f<<16) // For lane 14: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6628     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_14_SHIFT                              16
6629     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_14                                    (0x1<<23) // For lane 14: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6630     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_14_SHIFT                              23
6631     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_15                                    (0x7f<<24) // For lane 15 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6632     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_ERRS_15_SHIFT                              24
6633     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_15                                    (0x1<<31) // For lane 15 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6634     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_1512_TX_MCP_LOCK_15_SHIFT                              31
6635 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118                                                        0x001c14UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6636     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_8                                      (0x7f<<0) // For lane 8: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6637     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_8_SHIFT                                0
6638     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_8                                      (0x1<<7) // For lane 8: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6639     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_8_SHIFT                                7
6640     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_9                                      (0x7f<<8) // For lane 9 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6641     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_9_SHIFT                                8
6642     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_9                                      (0x1<<15) // For lane 9 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6643     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_9_SHIFT                                15
6644     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_10                                     (0x7f<<16) // For lane 10: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6645     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_10_SHIFT                               16
6646     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_10                                     (0x1<<23) // For lane 10: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6647     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_10_SHIFT                               23
6648     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_11                                     (0x7f<<24) // For lane 11 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6649     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_ERRS_11_SHIFT                               24
6650     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_11                                     (0x1<<31) // For lane 11 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6651     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_118_TX_MCP_LOCK_11_SHIFT                               31
6652 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74                                                         0x001c18UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6653     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_4                                       (0x7f<<0) // For lane 4: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6654     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_4_SHIFT                                 0
6655     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_4                                       (0x1<<7) // For lane 4: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6656     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_4_SHIFT                                 7
6657     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_5                                       (0x7f<<8) // For lane 5 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6658     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_5_SHIFT                                 8
6659     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_5                                       (0x1<<15) // For lane 5 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6660     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_5_SHIFT                                 15
6661     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_6                                       (0x7f<<16) // For lane 6: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6662     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_6_SHIFT                                 16
6663     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_6                                       (0x1<<23) // For lane 6: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6664     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_6_SHIFT                                 23
6665     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_7                                       (0x7f<<24) // For lane 7 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6666     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_ERRS_7_SHIFT                                 24
6667     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_7                                       (0x1<<31) // For lane 7 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6668     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_74_TX_MCP_LOCK_7_SHIFT                                 31
6669 #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30                                                         0x001c1cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6670     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_0                                       (0x7f<<0) // For lane 0: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6671     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_0_SHIFT                                 0
6672     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_0                                       (0x1<<7) // For lane 0: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6673     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_0_SHIFT                                 7
6674     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_1                                       (0x7f<<8) // For lane 1 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6675     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_1_SHIFT                                 8
6676     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_1                                       (0x1<<15) // For lane 1 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6677     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_1_SHIFT                                 15
6678     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_2                                       (0x7f<<16) // For lane 2: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6679     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_2_SHIFT                                 16
6680     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_2                                       (0x1<<23) // For lane 2: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6681     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_2_SHIFT                                 23
6682     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_3                                       (0x7f<<24) // For lane 3 in a multi-lane system: The number of decode and disparity errors (and optionally buffer overflow/underflow errors) recorded by the local receiver after locking to the Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6683     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_ERRS_3_SHIFT                                 24
6684     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_3                                       (0x1<<31) // For lane 3 in a multi-lane system: Set by the local receiver when it locks to the received Modified Compliance Pattern. This is sent to the link partner in the Modified Compliance Pattern
6685     #define PCIEIP_REG_TRANSMITTED_MCP_ERRORS_30_TX_MCP_LOCK_3_SHIFT                                 31
6686 #define PCIEIP_REG_RX_FTS_LIMIT                                                                      0x001c20UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6687     #define PCIEIP_REG_RX_FTS_LIMIT_RX_FTS_LIMIT                                                     (0xff<<0) // The N_FTS value advertised by the link partner
6688     #define PCIEIP_REG_RX_FTS_LIMIT_RX_FTS_LIMIT_SHIFT                                               0
6689     #define PCIEIP_REG_RX_FTS_LIMIT_UNUSED_1                                                         (0xffffff<<8) // Reserved
6690     #define PCIEIP_REG_RX_FTS_LIMIT_UNUSED_1_SHIFT                                                   8
6691 #define PCIEIP_REG_FTS_HIST                                                                          0x001cd0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6692     #define PCIEIP_REG_FTS_HIST_FTS_HIST_0                                                           (0xff<<0) // Last count of recognized FTSOS
6693     #define PCIEIP_REG_FTS_HIST_FTS_HIST_0_SHIFT                                                     0
6694     #define PCIEIP_REG_FTS_HIST_FTS_HIST_1                                                           (0xff<<8) // Count of recognized FTSOS 1 Rx_L0s ago
6695     #define PCIEIP_REG_FTS_HIST_FTS_HIST_1_SHIFT                                                     8
6696     #define PCIEIP_REG_FTS_HIST_FTS_HIST_2                                                           (0xff<<16) // Count of recognized FTSOS 2 Rx_L0s ago
6697     #define PCIEIP_REG_FTS_HIST_FTS_HIST_2_SHIFT                                                     16
6698     #define PCIEIP_REG_FTS_HIST_FTS_HIST_3                                                           (0xff<<24) // Count of recognized FTSOS 3 Rx_L0s ago
6699     #define PCIEIP_REG_FTS_HIST_FTS_HIST_3_SHIFT                                                     24
6700 #define PCIEIP_REG_GEN2_DEBUG_0                                                                      0x001cd4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6701     #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_8                                                     (0xff<<0) // Gen2 Debug History 8 transitions ago (see below for encoding)
6702     #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_8_SHIFT                                               0
6703     #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_9                                                     (0xff<<8) // Gen2 Debug History 9 transitions ago (see below for encoding)
6704     #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_9_SHIFT                                               8
6705     #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_10                                                    (0xff<<16) // Gen2 Debug History 10 transitions ago (see below for encoding)
6706     #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_10_SHIFT                                              16
6707     #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_11                                                    (0xff<<24) // Gen2 Debug History 11 transitions ago (see below for encoding)
6708     #define PCIEIP_REG_GEN2_DEBUG_0_GEN2_DEBUG_11_SHIFT                                              24
6709 #define PCIEIP_REG_GEN2_DEBUG_1                                                                      0x001cd8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6710     #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_4                                                     (0xff<<0) // Gen2 Debug History 4 transitions ago (see below for encoding)
6711     #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_4_SHIFT                                               0
6712     #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_5                                                     (0xff<<8) // Gen2 Debug History 5 transitions ago (see below for encoding)
6713     #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_5_SHIFT                                               8
6714     #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_6                                                     (0xff<<16) // Gen2 Debug History 6 transitions ago (see below for encoding)
6715     #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_6_SHIFT                                               16
6716     #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_7                                                     (0xff<<24) // Gen2 Debug History 7 transitions ago (see below for encoding)
6717     #define PCIEIP_REG_GEN2_DEBUG_1_GEN2_DEBUG_7_SHIFT                                               24
6718 #define PCIEIP_REG_GEN2_DEBUG_2                                                                      0x001cdcUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6719     #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_0                                                     (0xff<<0) // Gen2 Debug History - current. Changes are recorded when any of bits [5:0] differ.
6720     #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_0_SHIFT                                               0
6721     #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_1                                                     (0xff<<8) // Gen2 Debug History 1 transitions ago (see below for encoding)
6722     #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_1_SHIFT                                               8
6723     #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_2                                                     (0xff<<16) // Gen2 Debug History 2 transitions ago (see below for encoding)
6724     #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_2_SHIFT                                               16
6725     #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_3                                                     (0xff<<24) // Gen2 Debug History 3 transitions ago (see below for encoding)
6726     #define PCIEIP_REG_GEN2_DEBUG_2_GEN2_DEBUG_3_SHIFT                                               24
6727 #define PCIEIP_REG_RECOVERY_HIST_0                                                                   0x001ce0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6728     #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_4                                                  (0xff<<0) // Recovery History 4 transitions ago (see below for encoding)
6729     #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_4_SHIFT                                            0
6730     #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_5                                                  (0xff<<8) // Recovery History 5 transitions ago (see below for encoding)
6731     #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_5_SHIFT                                            8
6732     #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_6                                                  (0xff<<16) // Recovery History 6 transitions ago (see below for encoding)
6733     #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_6_SHIFT                                            16
6734     #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_7                                                  (0xff<<24) // Recovery History 7 transitions ago (see below for encoding)
6735     #define PCIEIP_REG_RECOVERY_HIST_0_RECOV_HIST_7_SHIFT                                            24
6736 #define PCIEIP_REG_RECOVERY_HIST_1                                                                   0x001ce4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6737     #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_0                                                  (0xff<<0) // Recovery History - current. Changes are recorded when any of bits [5:0] differ.
6738     #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_0_SHIFT                                            0
6739     #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_1                                                  (0xff<<8) // Recovery History 1 transitions ago (see below for encoding)
6740     #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_1_SHIFT                                            8
6741     #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_2                                                  (0xff<<16) // Recovery History 2 transitions ago (see below for encoding)
6742     #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_2_SHIFT                                            16
6743     #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_3                                                  (0xff<<24) // Recovery History 3 transitions ago (see below for encoding)
6744     #define PCIEIP_REG_RECOVERY_HIST_1_RECOV_HIST_3_SHIFT                                            24
6745 #define PCIEIP_REG_PHY_LTSSM_HIST_0                                                                  0x001cecUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6746     #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_12                                                (0xff<<0) // LTSSM state 12 transitions in the past
6747     #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_12_SHIFT                                          0
6748     #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_13                                                (0xff<<8) // LTSSM state 13 transitions in the past (see encoding below)
6749     #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_13_SHIFT                                          8
6750     #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_14                                                (0xff<<16) // LTSSM state 14 transitions in the past (see encoding below)
6751     #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_14_SHIFT                                          16
6752     #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_15                                                (0xff<<24) // LTSSM state 15 transitions in the past (see encoding below)
6753     #define PCIEIP_REG_PHY_LTSSM_HIST_0_LTSSM_HIST_15_SHIFT                                          24
6754 #define PCIEIP_REG_PHY_LTSSM_HIST_1                                                                  0x001cf0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6755     #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_8                                                 (0xff<<0) // LTSSM state 8 transitions in the past (see encoding above)
6756     #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_8_SHIFT                                           0
6757     #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_9                                                 (0xff<<8) // LTSSM state 9 transitions in the past (see encoding above)
6758     #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_9_SHIFT                                           8
6759     #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_10                                                (0xff<<16) // LTSSM state 10 transitions in the past (see encoding above)
6760     #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_10_SHIFT                                          16
6761     #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_11                                                (0xff<<24) // LTSSM state 11 transitions in the past (see encoding above)
6762     #define PCIEIP_REG_PHY_LTSSM_HIST_1_LTSSM_HIST_11_SHIFT                                          24
6763 #define PCIEIP_REG_PHY_LTSSM_HIST_2                                                                  0x001cf4UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6764     #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_4                                                 (0xff<<0) // LTSSM state 4 transitions in the past (see encoding above)
6765     #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_4_SHIFT                                           0
6766     #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_5                                                 (0xff<<8) // LTSSM state 5 transitions in the past (see encoding above)
6767     #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_5_SHIFT                                           8
6768     #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_6                                                 (0xff<<16) // LTSSM state 6 transitions in the past (see encoding above)
6769     #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_6_SHIFT                                           16
6770     #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_7                                                 (0xff<<24) // LTSSM state 7 transitions in the past (see encoding above)
6771     #define PCIEIP_REG_PHY_LTSSM_HIST_2_LTSSM_HIST_7_SHIFT                                           24
6772 #define PCIEIP_REG_PHY_LTSSM_HIST_3                                                                  0x001cf8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6773     #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_0                                                 (0xff<<0) // Current LTSSM state (see encoding above)
6774     #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_0_SHIFT                                           0
6775     #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_1                                                 (0xff<<8) // LTSSM state last transition/last LTSSM state (see encoding above)
6776     #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_1_SHIFT                                           8
6777     #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_2                                                 (0xff<<16) // LTSSM state 6 transitions in the past (see encoding above)
6778     #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_2_SHIFT                                           16
6779     #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_3                                                 (0xff<<24) // LTSSM state 3 transitions in the past (see encoding above)
6780     #define PCIEIP_REG_PHY_LTSSM_HIST_3_LTSSM_HIST_3_SHIFT                                           24
6781 #define PCIEIP_REG_PHY_LTSSM_HIST_2_DUP                                                              0x001cfcUL //Access:R    DataWidth:0x20  Duplicate of ltssm histogram entries 11, 10, 9, and 8 for compatibility  Chips: BB_A0 BB_B0
6782 #define PCIEIP_REG_PHY_DBG_0                                                                         0x001d00UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6783 #define PCIEIP_REG_PHY_DBG_1                                                                         0x001d04UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6784 #define PCIEIP_REG_PHY_DBG_2                                                                         0x001d08UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6785 #define PCIEIP_REG_PHY_DBG_3                                                                         0x001d0cUL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6786 #define PCIEIP_REG_PHY_DBG_4                                                                         0x001d10UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6787 #define PCIEIP_REG_PHY_DBG_5                                                                         0x001d14UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6788 #define PCIEIP_REG_PHY_DBG_6                                                                         0x001d18UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6789 #define PCIEIP_REG_PHY_DBG_7                                                                         0x001d1cUL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6790 #define PCIEIP_REG_PHY_DBG_8                                                                         0x001d20UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6791 #define PCIEIP_REG_PHY_DBG_9                                                                         0x001d24UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6792 #define PCIEIP_REG_PHY_DBG_10                                                                        0x001d28UL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6793 #define PCIEIP_REG_PHY_DBG_11                                                                        0x001d2cUL //Access:R    DataWidth:0x20  PHY Debug Signals  Chips: BB_A0 BB_B0
6794 #define PCIEIP_REG_ATE_LOOPBACK_INFO                                                                 0x001d30UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6795     #define PCIEIP_REG_ATE_LOOPBACK_INFO_UNUSED_1                                                    (0x1f<<0) // The current state of the ATE loopback SM tracker:  b00011 : IDLE state - not active b00101 : Waiting for L0 state b00110 : In L0, waiting for L0 at Gen2 b01001 : In L0 at Gen2, waiting for L0s at Gen2 b01010 : In L0s at Gen2, waiting for L0s exit b01100 : Finished without error b10110 : Error while in L0, waiting for L0 at Gen2 b11001 : Error while in L0 at Gen2, waiting for L0s at Gen2 b11010 : Error while in L0s at Gen2, waiting for L0s exit
6796     #define PCIEIP_REG_ATE_LOOPBACK_INFO_UNUSED_1_SHIFT                                              0
6797     #define PCIEIP_REG_ATE_LOOPBACK_INFO_PCIE_PHY_GLOOPBACK                                          (0x1<<5) // Current state of the gloopback signal to the Serdes
6798     #define PCIEIP_REG_ATE_LOOPBACK_INFO_PCIE_PHY_GLOOPBACK_SHIFT                                    5
6799     #define PCIEIP_REG_ATE_LOOPBACK_INFO_REG_GLOOPBACK                                               (0x1<<6) // Current state of the "pins" gloopback request
6800     #define PCIEIP_REG_ATE_LOOPBACK_INFO_REG_GLOOPBACK_SHIFT                                         6
6801     #define PCIEIP_REG_ATE_LOOPBACK_INFO_UNUSED                                                      (0x1ffffff<<7) //
6802     #define PCIEIP_REG_ATE_LOOPBACK_INFO_UNUSED_SHIFT                                                7
6803 #define PCIEIP_REG_GEN3_STICKY_ERRORS                                                                0x001d34UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6804     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_FRAMING_ERR                                       (0x1<<0) // A framing error occurred
6805     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_FRAMING_ERR_SHIFT                                 0
6806     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FCRC                                      (0x1<<1) // FCRC error in the STP token
6807     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FCRC_SHIFT                                1
6808     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FP                                        (0x1<<2) // Parity error in the STP token
6809     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FP_SHIFT                                  2
6810     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_EDB                                       (0x1<<3) // Badly formed or misplaced EDB token
6811     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_EDB_SHIFT                                 3
6812     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FRAMING_SYM                               (0x1<<4) // No valid framing symbol in the data stream
6813     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_FRAMING_SYM_SHIFT                         4
6814     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_BLOCK_TYPE                                (0x1<<5) // Serdes indicated a bad block type (sync header of 00b or 11b)
6815     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_BAD_BLOCK_TYPE_SHIFT                          5
6816     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_AFTER_SDS                          (0x1<<6) // An ordered set occurred after an SDS without an EDS first
6817     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_AFTER_SDS_SHIFT                    6
6818     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_DATA_AFTER_EDS                                (0x1<<7) // Data block occurred immediately after an EDS token
6819     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_DATA_AFTER_EDS_SHIFT                          7
6820     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_NO_EDS                             (0x1<<8) // An ordered set occurred in the data stream without a prior EDS
6821     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ORDEREDSET_NO_EDS_SHIFT                       8
6822     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_MULT_ORDEREDSETS                              (0x1<<9) // Ordered set follows SKP ordered set after EDS
6823     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_MULT_ORDEREDSETS_SHIFT                        9
6824     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_RETRAIN_ON_GEN3_BLOCKALIGN                        (0x1<<10) // Retraining occurred due to block misalignment
6825     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_RETRAIN_ON_GEN3_BLOCKALIGN_SHIFT                  10
6826     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BLOCK_ALIGN_ERR                                   (0x1<<11) // Block alignment error from the Serdes
6827     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BLOCK_ALIGN_ERR_SHIFT                             11
6828     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_EDS                                    (0x1<<12) // Misplaced or badly formed EDS token
6829     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_EDS_SHIFT                              12
6830     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_SYM_CNT                                (0x1<<13) // Incorrect length for a data block
6831     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_SYM_CNT_SHIFT                          13
6832     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SYNCHEADER                                 (0x1<<14) // Mismatch or misalignment in the sync headers
6833     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SYNCHEADER_SHIFT                           14
6834     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_LEN                                    (0x1<<15) // Bad Gen3 TLP length
6835     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_BAD_LEN_SHIFT                              15
6836     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SKIPDATA                                   (0x1<<16) // Misalignment in the null/skipped data
6837     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_AUXERR_SKIPDATA_SHIFT                             16
6838     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BAD_SKIP_DATA_RATE                                (0x1<<17) // Too many or too few RxDataValid deassertions in 65 clocks at Gen3.
6839     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_BAD_SKIP_DATA_RATE_SHIFT                          17
6840     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_IDLE_START                                    (0x1<<18) // Error when in the same symbol time Idle symbols appear in the DW before a TLP or a DLLP.
6841     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_IDLE_START_SHIFT                              18
6842     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ILLEGAL_EDSOS                                 (0x1<<19) // This bit is set to '1' when the ordered set following an EDS token is other than SKP OS, EIEOS, or EIOS.
6843     #define PCIEIP_REG_GEN3_STICKY_ERRORS_SET_GEN3_ERR_ILLEGAL_EDSOS_SHIFT                           19
6844     #define PCIEIP_REG_GEN3_STICKY_ERRORS_UNUSED                                                     (0xfff<<20) //
6845     #define PCIEIP_REG_GEN3_STICKY_ERRORS_UNUSED_SHIFT                                               20
6846 #define PCIEIP_REG_PHY_DBG_POLLING_COMPL                                                             0x001d38UL //Access:R    DataWidth:0x20  PHY Debug - Polling Compliance signals  Chips: BB_A0 BB_B0
6847 #define PCIEIP_REG_PHY_DBG_EQUALIZE                                                                  0x001d3cUL //Access:R    DataWidth:0x20  PHY Debug - Equalization signals  Chips: BB_A0 BB_B0
6848 #define PCIEIP_REG_DEBUG_DESKEW_0                                                                    0x001d40UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6849     #define PCIEIP_REG_DEBUG_DESKEW_0_DEBUG_DESKEW_LANE_14                                           (0xffff<<0) //
6850     #define PCIEIP_REG_DEBUG_DESKEW_0_DEBUG_DESKEW_LANE_14_SHIFT                                     0
6851     #define PCIEIP_REG_DEBUG_DESKEW_0_DEBUG_DESKEW_LANE_15                                           (0xffff<<16) //
6852     #define PCIEIP_REG_DEBUG_DESKEW_0_DEBUG_DESKEW_LANE_15_SHIFT                                     16
6853 #define PCIEIP_REG_DEBUG_DESKEW_1                                                                    0x001d44UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6854     #define PCIEIP_REG_DEBUG_DESKEW_1_DEBUG_DESKEW_LANE_12                                           (0xffff<<0) //
6855     #define PCIEIP_REG_DEBUG_DESKEW_1_DEBUG_DESKEW_LANE_12_SHIFT                                     0
6856     #define PCIEIP_REG_DEBUG_DESKEW_1_DEBUG_DESKEW_LANE_13                                           (0xffff<<16) //
6857     #define PCIEIP_REG_DEBUG_DESKEW_1_DEBUG_DESKEW_LANE_13_SHIFT                                     16
6858 #define PCIEIP_REG_DEBUG_DESKEW_2                                                                    0x001d48UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6859     #define PCIEIP_REG_DEBUG_DESKEW_2_DEBUG_DESKEW_LANE_10                                           (0xffff<<0) //
6860     #define PCIEIP_REG_DEBUG_DESKEW_2_DEBUG_DESKEW_LANE_10_SHIFT                                     0
6861     #define PCIEIP_REG_DEBUG_DESKEW_2_DEBUG_DESKEW_LANE_11                                           (0xffff<<16) //
6862     #define PCIEIP_REG_DEBUG_DESKEW_2_DEBUG_DESKEW_LANE_11_SHIFT                                     16
6863 #define PCIEIP_REG_DEBUG_DESKEW_3                                                                    0x001d4cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6864     #define PCIEIP_REG_DEBUG_DESKEW_3_DEBUG_DESKEW_LANE_8                                            (0xffff<<0) //
6865     #define PCIEIP_REG_DEBUG_DESKEW_3_DEBUG_DESKEW_LANE_8_SHIFT                                      0
6866     #define PCIEIP_REG_DEBUG_DESKEW_3_DEBUG_DESKEW_LANE_9                                            (0xffff<<16) //
6867     #define PCIEIP_REG_DEBUG_DESKEW_3_DEBUG_DESKEW_LANE_9_SHIFT                                      16
6868 #define PCIEIP_REG_DEBUG_DESKEW_4                                                                    0x001d50UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6869     #define PCIEIP_REG_DEBUG_DESKEW_4_DEBUG_DESKEW_LANE_6                                            (0xffff<<0) //
6870     #define PCIEIP_REG_DEBUG_DESKEW_4_DEBUG_DESKEW_LANE_6_SHIFT                                      0
6871     #define PCIEIP_REG_DEBUG_DESKEW_4_DEBUG_DESKEW_LANE_7                                            (0xffff<<16) //
6872     #define PCIEIP_REG_DEBUG_DESKEW_4_DEBUG_DESKEW_LANE_7_SHIFT                                      16
6873 #define PCIEIP_REG_DEBUG_DESKEW_5                                                                    0x001d54UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6874     #define PCIEIP_REG_DEBUG_DESKEW_5_DEBUG_DESKEW_LANE_4                                            (0xffff<<0) //
6875     #define PCIEIP_REG_DEBUG_DESKEW_5_DEBUG_DESKEW_LANE_4_SHIFT                                      0
6876     #define PCIEIP_REG_DEBUG_DESKEW_5_DEBUG_DESKEW_LANE_5                                            (0xffff<<16) //
6877     #define PCIEIP_REG_DEBUG_DESKEW_5_DEBUG_DESKEW_LANE_5_SHIFT                                      16
6878 #define PCIEIP_REG_DEBUG_DESKEW_6                                                                    0x001d58UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6879     #define PCIEIP_REG_DEBUG_DESKEW_6_DEBUG_DESKEW_LANE_2                                            (0xffff<<0) //
6880     #define PCIEIP_REG_DEBUG_DESKEW_6_DEBUG_DESKEW_LANE_2_SHIFT                                      0
6881     #define PCIEIP_REG_DEBUG_DESKEW_6_DEBUG_DESKEW_LANE_3                                            (0xffff<<16) //
6882     #define PCIEIP_REG_DEBUG_DESKEW_6_DEBUG_DESKEW_LANE_3_SHIFT                                      16
6883 #define PCIEIP_REG_DEBUG_DESKEW_7                                                                    0x001d5cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6884     #define PCIEIP_REG_DEBUG_DESKEW_7_DEBUG_DESKEW_LANE_0                                            (0xffff<<0) //
6885     #define PCIEIP_REG_DEBUG_DESKEW_7_DEBUG_DESKEW_LANE_0_SHIFT                                      0
6886     #define PCIEIP_REG_DEBUG_DESKEW_7_DEBUG_DESKEW_LANE_1                                            (0xffff<<16) //
6887     #define PCIEIP_REG_DEBUG_DESKEW_7_DEBUG_DESKEW_LANE_1_SHIFT                                      16
6888 #define PCIEIP_REG_FREEZE_DESKEW_0                                                                   0x001d60UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6889     #define PCIEIP_REG_FREEZE_DESKEW_0_FREEZE_DESKEW_LANE_14                                         (0xffff<<0) //
6890     #define PCIEIP_REG_FREEZE_DESKEW_0_FREEZE_DESKEW_LANE_14_SHIFT                                   0
6891     #define PCIEIP_REG_FREEZE_DESKEW_0_FREEZE_DESKEW_LANE_15                                         (0xffff<<16) //
6892     #define PCIEIP_REG_FREEZE_DESKEW_0_FREEZE_DESKEW_LANE_15_SHIFT                                   16
6893 #define PCIEIP_REG_FREEZE_DESKEW_1                                                                   0x001d64UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6894     #define PCIEIP_REG_FREEZE_DESKEW_1_FREEZE_DESKEW_LANE_12                                         (0xffff<<0) //
6895     #define PCIEIP_REG_FREEZE_DESKEW_1_FREEZE_DESKEW_LANE_12_SHIFT                                   0
6896     #define PCIEIP_REG_FREEZE_DESKEW_1_FREEZE_DESKEW_LANE_13                                         (0xffff<<16) //
6897     #define PCIEIP_REG_FREEZE_DESKEW_1_FREEZE_DESKEW_LANE_13_SHIFT                                   16
6898 #define PCIEIP_REG_FREEZE_DESKEW_2                                                                   0x001d68UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6899     #define PCIEIP_REG_FREEZE_DESKEW_2_FREEZE_DESKEW_LANE_10                                         (0xffff<<0) //
6900     #define PCIEIP_REG_FREEZE_DESKEW_2_FREEZE_DESKEW_LANE_10_SHIFT                                   0
6901     #define PCIEIP_REG_FREEZE_DESKEW_2_FREEZE_DESKEW_LANE_11                                         (0xffff<<16) //
6902     #define PCIEIP_REG_FREEZE_DESKEW_2_FREEZE_DESKEW_LANE_11_SHIFT                                   16
6903 #define PCIEIP_REG_FREEZE_DESKEW_3                                                                   0x001d6cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6904     #define PCIEIP_REG_FREEZE_DESKEW_3_FREEZE_DESKEW_LANE_8                                          (0xffff<<0) //
6905     #define PCIEIP_REG_FREEZE_DESKEW_3_FREEZE_DESKEW_LANE_8_SHIFT                                    0
6906     #define PCIEIP_REG_FREEZE_DESKEW_3_FREEZE_DESKEW_LANE_9                                          (0xffff<<16) //
6907     #define PCIEIP_REG_FREEZE_DESKEW_3_FREEZE_DESKEW_LANE_9_SHIFT                                    16
6908 #define PCIEIP_REG_FREEZE_DESKEW_4                                                                   0x001d70UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6909     #define PCIEIP_REG_FREEZE_DESKEW_4_FREEZE_DESKEW_LANE_6                                          (0xffff<<0) //
6910     #define PCIEIP_REG_FREEZE_DESKEW_4_FREEZE_DESKEW_LANE_6_SHIFT                                    0
6911     #define PCIEIP_REG_FREEZE_DESKEW_4_FREEZE_DESKEW_LANE_7                                          (0xffff<<16) //
6912     #define PCIEIP_REG_FREEZE_DESKEW_4_FREEZE_DESKEW_LANE_7_SHIFT                                    16
6913 #define PCIEIP_REG_FREEZE_DESKEW_5                                                                   0x001d74UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6914     #define PCIEIP_REG_FREEZE_DESKEW_5_FREEZE_DESKEW_LANE_4                                          (0xffff<<0) //
6915     #define PCIEIP_REG_FREEZE_DESKEW_5_FREEZE_DESKEW_LANE_4_SHIFT                                    0
6916     #define PCIEIP_REG_FREEZE_DESKEW_5_FREEZE_DESKEW_LANE_5                                          (0xffff<<16) //
6917     #define PCIEIP_REG_FREEZE_DESKEW_5_FREEZE_DESKEW_LANE_5_SHIFT                                    16
6918 #define PCIEIP_REG_FREEZE_DESKEW_6                                                                   0x001d78UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6919     #define PCIEIP_REG_FREEZE_DESKEW_6_FREEZE_DESKEW_LANE_2                                          (0xffff<<0) //
6920     #define PCIEIP_REG_FREEZE_DESKEW_6_FREEZE_DESKEW_LANE_2_SHIFT                                    0
6921     #define PCIEIP_REG_FREEZE_DESKEW_6_FREEZE_DESKEW_LANE_3                                          (0xffff<<16) //
6922     #define PCIEIP_REG_FREEZE_DESKEW_6_FREEZE_DESKEW_LANE_3_SHIFT                                    16
6923 #define PCIEIP_REG_FREEZE_DESKEW_7                                                                   0x001d7cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6924     #define PCIEIP_REG_FREEZE_DESKEW_7_FREEZE_DESKEW_LANE_0                                          (0xffff<<0) //
6925     #define PCIEIP_REG_FREEZE_DESKEW_7_FREEZE_DESKEW_LANE_0_SHIFT                                    0
6926     #define PCIEIP_REG_FREEZE_DESKEW_7_FREEZE_DESKEW_LANE_1                                          (0xffff<<16) //
6927     #define PCIEIP_REG_FREEZE_DESKEW_7_FREEZE_DESKEW_LANE_1_SHIFT                                    16
6928 #define PCIEIP_REG_PHY_DBG_SED_RDDATA                                                                0x001d80UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6929     #define PCIEIP_REG_PHY_DBG_SED_RDDATA_SED_READ_DATA                                              (0x7ffffff<<0) // SED Read Data. Reading this register returns the contents of SED FIFO at the current read address.
6930     #define PCIEIP_REG_PHY_DBG_SED_RDDATA_SED_READ_DATA_SHIFT                                        0
6931 #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30                                                             0x001d84UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6932     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_0                                           (0xff<<0) // SED Extended Configuration 0.
6933     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_0_SHIFT                                     0
6934     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_1                                           (0xff<<8) // SED Extended Configuration 1.
6935     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_1_SHIFT                                     8
6936     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_2                                           (0xff<<16) // SED Extended Configuration 2.
6937     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_2_SHIFT                                     16
6938     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_3                                           (0xff<<24) // SED Extended Configuration 3.
6939     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_30_SED_EXT_CFG_3_SHIFT                                     24
6940 #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74                                                             0x001d88UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6941     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_4                                           (0xff<<0) // SED Extended Configuration 4.
6942     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_4_SHIFT                                     0
6943     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_5                                           (0xff<<8) // SED Extended Configuration 5.
6944     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_5_SHIFT                                     8
6945     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_6                                           (0xff<<16) // SED Extended Configuration 6.
6946     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_6_SHIFT                                     16
6947     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_7                                           (0xff<<24) // SED Extended Configuration 7.
6948     #define PCIEIP_REG_PHY_DBG_SED_EXTCFG_74_SED_EXT_CFG_7_SHIFT                                     24
6949 #define PCIEIP_REG_PHY_DBG_PRESET_LUT                                                                0x001d90UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6950     #define PCIEIP_REG_PHY_DBG_PRESET_LUT_PRESET_LUT_ENTRY_VAL                                       (0x1ffff<<0) // Preset LUT Read Data.
6951     #define PCIEIP_REG_PHY_DBG_PRESET_LUT_PRESET_LUT_ENTRY_VAL_SHIFT                                 0
6952 #define PCIEIP_REG_PHY_DBG_MUXED_SIGS                                                                0x001e00UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6953     #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_PHY_DBG_SIGS_0                                             (0x7ff<<0) // Debug signals that are muxed to the debug port 0.
6954     #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_PHY_DBG_SIGS_0_SHIFT                                       0
6955     #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_UNUSED                                                     (0x1f<<11) //
6956     #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_UNUSED_SHIFT                                               11
6957     #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_PHY_DBG_SIGS_1                                             (0x7ff<<16) // Debug signals that are muxed to the debug port 1.
6958     #define PCIEIP_REG_PHY_DBG_MUXED_SIGS_PHY_DBG_SIGS_1_SHIFT                                       16
6959 #define PCIEIP_REG_PHY_DBG_CLKREQ_0                                                                  0x001e10UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6960     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_7                                                (0xf<<0) // The state of the clock PM state machine and perstb 7 transitions in the past. See encoding above.
6961     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_7_SHIFT                                          0
6962     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_6                                                (0xf<<4) // The state of the clock PM state machine and perstb 6 transitions in the past. See encoding above.
6963     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_6_SHIFT                                          4
6964     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_5                                                (0xf<<8) // The state of the clock PM state machine and perstb 5 transitions in the past. See encoding above.
6965     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_5_SHIFT                                          8
6966     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_4                                                (0xf<<12) // The state of the clock PM state machine and perstb 4 transitions in the past. See encoding above.
6967     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_4_SHIFT                                          12
6968     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_3                                                (0xf<<16) // The state of the clock PM state machine and perstb 3 transitions in the past. See encoding above.
6969     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_3_SHIFT                                          16
6970     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_2                                                (0xf<<20) // The state of the clock PM state machine and perstb 2 transitions in the past. See encoding above.
6971     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_2_SHIFT                                          20
6972     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_1                                                (0xf<<24) // The state of the clock PM state machine and perstb 1 transition in the past. See encoding above.
6973     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_1_SHIFT                                          24
6974     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_0                                                (0xf<<28) // The current state of the clock PM state machine and perstb. The encoding is:  b0000 : Unused entry b0001 : State waiting for activation b0010 : State waiting for Serdes to complete P0 to P2 change b0011 : State waiting for Tp0torefclk timer expiry b0100 : State waiting for Texcr timer expiry b0101 : State waiting for Tcrpw timer expiry b0110 : State waiting for reactivation b0111 : State waiting for Tcrlon timer expiry b1000 : State waiting for Trefup timer expiry b1001 : State waiting Serdes to complete PLL lock b1010 : State waiting for clock PM exit conditions to settle b1110 : Unknown state (failure) b1111 : Fundamental reset (perstb) occurred
6975     #define PCIEIP_REG_PHY_DBG_CLKREQ_0_CLKREQ_HIST_0_SHIFT                                          28
6976 #define PCIEIP_REG_PHY_DBG_CLKREQ_1                                                                  0x001e14UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6977     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_15                                               (0xf<<0) // The state of the clock PM state machine and perstb 15 transitions in the past. See encoding above.
6978     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_15_SHIFT                                         0
6979     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_14                                               (0xf<<4) // The state of the clock PM state machine and perstb 14 transitions in the past. See encoding above.
6980     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_14_SHIFT                                         4
6981     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_13                                               (0xf<<8) // The state of the clock PM state machine and perstb 13 transitions in the past. See encoding above.
6982     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_13_SHIFT                                         8
6983     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_12                                               (0xf<<12) // The state of the clock PM state machine and perstb 12 transitions in the past. See encoding above.
6984     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_12_SHIFT                                         12
6985     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_11                                               (0xf<<16) // The state of the clock PM state machine and perstb 11 transitions in the past. See encoding above.
6986     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_11_SHIFT                                         16
6987     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_10                                               (0xf<<20) // The state of the clock PM state machine and perstb 10 transitions in the past. See encoding above.
6988     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_10_SHIFT                                         20
6989     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_9                                                (0xf<<24) // The state of the clock PM state machine and perstb 9 transitions in the past. See encoding above.
6990     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_9_SHIFT                                          24
6991     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_8                                                (0xf<<28) // The state of the clock PM state machine and perstb 8 transitions in the past. See encoding above.
6992     #define PCIEIP_REG_PHY_DBG_CLKREQ_1_CLKREQ_HIST_8_SHIFT                                          28
6993 #define PCIEIP_REG_PHY_DBG_CLKREQ_2                                                                  0x001e18UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
6994     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_23                                               (0xf<<0) // The state of the clock PM state machine and perstb 23 transitions in the past. See encoding above.
6995     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_23_SHIFT                                         0
6996     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_22                                               (0xf<<4) // The state of the clock PM state machine and perstb 22 transitions in the past. See encoding above.
6997     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_22_SHIFT                                         4
6998     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_21                                               (0xf<<8) // The state of the clock PM state machine and perstb 21 transitions in the past. See encoding above.
6999     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_21_SHIFT                                         8
7000     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_20                                               (0xf<<12) // The state of the clock PM state machine and perstb 20 transitions in the past. See encoding above.
7001     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_20_SHIFT                                         12
7002     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_19                                               (0xf<<16) // The state of the clock PM state machine and perstb 19 transitions in the past. See encoding above.
7003     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_19_SHIFT                                         16
7004     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_18                                               (0xf<<20) // The state of the clock PM state machine and perstb 18 transitions in the past. See encoding above.
7005     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_18_SHIFT                                         20
7006     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_17                                               (0xf<<24) // The state of the clock PM state machine and perstb 17 transitions in the past. See encoding above.
7007     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_17_SHIFT                                         24
7008     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_16                                               (0xf<<28) // The state of the clock PM state machine and perstb 16 transitions in the past. See encoding above.
7009     #define PCIEIP_REG_PHY_DBG_CLKREQ_2_CLKREQ_HIST_16_SHIFT                                         28
7010 #define PCIEIP_REG_PHY_DBG_CLKREQ_3                                                                  0x001e1cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
7011     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_31                                               (0xf<<0) // The state of the clock PM state machine and perstb 31 transitions in the past. See encoding above.
7012     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_31_SHIFT                                         0
7013     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_30                                               (0xf<<4) // The state of the clock PM state machine and perstb 30 transitions in the past. See encoding above.
7014     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_30_SHIFT                                         4
7015     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_29                                               (0xf<<8) // The state of the clock PM state machine and perstb 29 transitions in the past. See encoding above.
7016     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_29_SHIFT                                         8
7017     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_28                                               (0xf<<12) // The state of the clock PM state machine and perstb 28 transitions in the past. See encoding above.
7018     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_28_SHIFT                                         12
7019     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_27                                               (0xf<<16) // The state of the clock PM state machine and perstb 27 transitions in the past. See encoding above.
7020     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_27_SHIFT                                         16
7021     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_26                                               (0xf<<20) // The state of the clock PM state machine and perstb 26 transitions in the past. See encoding above.
7022     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_26_SHIFT                                         20
7023     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_25                                               (0xf<<24) // The state of the clock PM state machine and perstb 25 transitions in the past. See encoding above.
7024     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_25_SHIFT                                         24
7025     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_24                                               (0xf<<28) // The state of the clock PM state machine and perstb 24 transitions in the past. See encoding above.
7026     #define PCIEIP_REG_PHY_DBG_CLKREQ_3_CLKREQ_HIST_24_SHIFT                                         28
7027 #define PCIEIP_REG_MISC_DBG_STATUS                                                                   0x001e20UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
7028     #define PCIEIP_REG_MISC_DBG_STATUS_USER_ALLOW_GEN3_SYNC                                          (0x1<<0) // Instantaneous value of the top-level user_allow_gen3 signal (sync'd to the cfg_clk domain). The reset value will depend on the environment.
7029     #define PCIEIP_REG_MISC_DBG_STATUS_USER_ALLOW_GEN3_SYNC_SHIFT                                    0
7030     #define PCIEIP_REG_MISC_DBG_STATUS_UNUSED                                                        (0x7fffffff<<1) //
7031     #define PCIEIP_REG_MISC_DBG_STATUS_UNUSED_SHIFT                                                  1
7032 #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG                                                     0x000000UL //Access:R    DataWidth:0x20  Device ID and Vendor ID Register.  Chips: K2
7033     #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID                             (0xffff<<0) // Vendor ID. PCI-SIG assigned Manufacturer Identifier.
7034     #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_VENDOR_ID_SHIFT                       0
7035     #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID                             (0xffff<<16) // Device ID. Vendor Assigned Device Identifier.
7036     #define PCIEIP_VF_REG_VF_DEVICE_ID_VENDOR_ID_REG_PCI_TYPE0_DEVICE_ID_SHIFT                       16
7037 #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG                                                          0x000004UL //Access:RW   DataWidth:0x20  Command and Status Register.  Chips: K2
7038     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN                                      (0x1<<0) // Enables IO Access Response.   You cannot write to this register if your configuration has no IO bars; that is, the internal signal has_io_bar=0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
7039     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_IO_EN_SHIFT                                0
7040     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN                               (0x1<<1) // Enables Memory Access Response.   You cannot write to this register if your configuration has no MEM bars; that is, the internal signal has_mem_bar=0.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)
7041     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_MEM_SPACE_EN_SHIFT                         1
7042     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN                              (0x1<<2) // Bus Master Enable. Controls Issuing of Memory and I/O Requests.
7043     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_BUS_MASTER_EN_SHIFT                        2
7044     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION                    (0x1<<3) // Special Cycle Enable.
7045     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SPECIAL_CYCLE_OPERATION_SHIFT              3
7046     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE                                  (0x1<<4) // Memory Write and Invalidate.
7047     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_MWI_ENABLE_SHIFT                            4
7048     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP                           (0x1<<5) // VGA Palette Snoop.
7049     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_VGA_PALETTE_SNOOP_SHIFT                     5
7050     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN                              (0x1<<6) // Controls Logging of Poisoned TLPs.
7051     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_PARITY_ERR_EN_SHIFT                        6
7052     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING                              (0x1<<7) // IDSEL Stepping.
7053     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_IDSEL_STEPPING_SHIFT                        7
7054     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN                                     (0x1<<8) // Enables Error Reporting.
7055     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_SERREN_SHIFT                               8
7056     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RSVDP_9                                              (0x1<<9) // Reserved for future use.
7057     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RSVDP_9_SHIFT                                        9
7058     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN                                     (0x1<<10) // Controls generation of interrupts by a function.
7059     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE0_INT_EN_SHIFT                               10
7060     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_RESERV                                      (0x1f<<11) // Reserved.
7061     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_PCI_TYPE_RESERV_SHIFT                                11
7062     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_UNUSED_0                                             (0x1<<16) // reserved
7063     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_UNUSED_0_SHIFT                                       16
7064     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RSVDP_17                                             (0x3<<17) // Reserved for future use.
7065     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RSVDP_17_SHIFT                                       17
7066     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS                                           (0x1<<19) // Emulation interrupt pending.
7067     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_INT_STATUS_SHIFT                                     19
7068     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST                                             (0x1<<20) // Extended Capability.
7069     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_CAP_LIST_SHIFT                                       20
7070     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP                                       (0x1<<21) // PCI 66MHz Capability.
7071     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_66MHZ_CAP_SHIFT                                 21
7072     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RSVDP_22                                             (0x1<<22) // Reserved for future use.
7073     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RSVDP_22_SHIFT                                       22
7074     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP                                         (0x1<<23) // Fast Back to Back Transaction Capable and Enable.
7075     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_FAST_B2B_CAP_SHIFT                                   23
7076     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE                                           (0x1<<24) // Controls poisoned Completion and Request error reporting.
7077     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_MASTER_DPE_SHIFT                                     24
7078     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DEV_SEL_TIMING                                       (0x3<<25) // Device Select Timing.
7079     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DEV_SEL_TIMING_SHIFT                                 25
7080     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT                                (0x1<<27) // Completer Abort Error.
7081     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_TARGET_ABORT_SHIFT                          27
7082     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT                                    (0x1<<28) // Completer Abort received.
7083     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_TARGET_ABORT_SHIFT                              28
7084     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT                                    (0x1<<29) // Unsupported request completion status received.
7085     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_RCVD_MASTER_ABORT_SHIFT                              29
7086     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR                                     (0x1<<30) // Fatal or Non-Fatal Error Message sent by function.
7087     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_SIGNALED_SYS_ERR_SHIFT                               30
7088     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR                                  (0x1<<31) // Poisoned TLP received by function.
7089     #define PCIEIP_VF_REG_VF_STATUS_COMMAND_REG_DETECTED_PARITY_ERR_SHIFT                            31
7090 #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID                                                      0x000008UL //Access:R    DataWidth:0x20  Class Code and Revision ID Register.  Chips: K2
7091     #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_REVISION_ID                                      (0xff<<0) // Vendor chosen Revision ID.   Note: This register field is sticky.
7092     #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_REVISION_ID_SHIFT                                0
7093     #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE                                (0xff<<8) // Class Code Programming Interface.   Note: This register field is sticky.
7094     #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_PROGRAM_INTERFACE_SHIFT                          8
7095     #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_SUBCLASS_CODE                                    (0xff<<16) // Subclass Code to represent Device Type.   Note: This register field is sticky.
7096     #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_SUBCLASS_CODE_SHIFT                              16
7097     #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE                                  (0xff<<24) // Base Class Code to represent Device Type.   Note: This register field is sticky.
7098     #define PCIEIP_VF_REG_VF_CLASS_CODE_REVISION_ID_BASE_CLASS_CODE_SHIFT                            24
7099 #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG                                0x00000cUL //Access:R    DataWidth:0x20  BIST, Header Type, Cache Line Size, and Latency Timer Registers.  Chips: K2
7100     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE            (0xff<<0) // Cache Line Size. Has no effect on PCIe device behavior.
7101     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_CACHE_LINE_SIZE_SHIFT      0
7102     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER       (0xff<<8) // Does not apply to PCI Express.
7103     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_LATENCY_MASTER_TIMER_SHIFT 8
7104     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE                (0x7f<<16) // Specifies Header Type.
7105     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_HEADER_TYPE_SHIFT          16
7106     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC                 (0x1<<23) // Specifies whether device is multifunction.   Note: This register field is sticky.
7107     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_MULTI_FUNC_SHIFT           23
7108     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST                       (0xff<<24) // Optional for BIST support.
7109     #define PCIEIP_VF_REG_VF_BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG_BIST_SHIFT                 24
7110 #define PCIEIP_VF_REG_VF_BAR0_REG                                                                    0x000010UL //Access:R    DataWidth:0x20  BAR0 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7111     #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO                                                    (0x1<<0) // BAR0 Memory Space Indicator.
7112     #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_MEM_IO_SHIFT                                              0
7113     #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE                                                      (0x3<<1) // BAR0 32-bit or 64-bit.
7114     #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_TYPE_SHIFT                                                1
7115     #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH                                                  (0x1<<3) // BAR0 Prefetchable.
7116     #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_PREFETCH_SHIFT                                            3
7117     #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_START                                                     (0xfffffff<<4) // BAR0 Base Address.
7118     #define PCIEIP_VF_REG_VF_BAR0_REG_BAR0_START_SHIFT                                               4
7119 #define PCIEIP_VF_REG_VF_BAR1_REG                                                                    0x000014UL //Access:R    DataWidth:0x20  BAR1 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7120     #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO                                                    (0x1<<0) // BAR1 Memory Space Indicator.
7121     #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_MEM_IO_SHIFT                                              0
7122     #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE                                                      (0x3<<1) // BAR1 32-bit or 64-bit.
7123     #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_TYPE_SHIFT                                                1
7124     #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH                                                  (0x1<<3) // BAR1 Prefetchable.
7125     #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_PREFETCH_SHIFT                                            3
7126     #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_START                                                     (0xfffffff<<4) // BAR1 Base Address.
7127     #define PCIEIP_VF_REG_VF_BAR1_REG_BAR1_START_SHIFT                                               4
7128 #define PCIEIP_VF_REG_VF_BAR2_REG                                                                    0x000018UL //Access:R    DataWidth:0x20  BAR2 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7129     #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO                                                    (0x1<<0) // BAR2 Memory Space Indicator.
7130     #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_MEM_IO_SHIFT                                              0
7131     #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE                                                      (0x3<<1) // BAR2 32-bit or 64-bit.
7132     #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_TYPE_SHIFT                                                1
7133     #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH                                                  (0x1<<3) // BAR2 Prefetchable.
7134     #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_PREFETCH_SHIFT                                            3
7135     #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_START                                                     (0xfffffff<<4) // BAR2 Base Address.
7136     #define PCIEIP_VF_REG_VF_BAR2_REG_BAR2_START_SHIFT                                               4
7137 #define PCIEIP_VF_REG_VF_BAR3_REG                                                                    0x00001cUL //Access:R    DataWidth:0x20  BAR3 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7138     #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO                                                    (0x1<<0) // BAR3 Memory Space Indicator.
7139     #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_MEM_IO_SHIFT                                              0
7140     #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE                                                      (0x3<<1) // BAR3 32-bit or 64-bit.
7141     #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_TYPE_SHIFT                                                1
7142     #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH                                                  (0x1<<3) // BAR3 Prefetchable.
7143     #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_PREFETCH_SHIFT                                            3
7144     #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_START                                                     (0xfffffff<<4) // BAR3 Base Address.
7145     #define PCIEIP_VF_REG_VF_BAR3_REG_BAR3_START_SHIFT                                               4
7146 #define PCIEIP_VF_REG_VF_BAR4_REG                                                                    0x000020UL //Access:R    DataWidth:0x20  BAR4 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7147     #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO                                                    (0x1<<0) // BAR4 Memory Space Indicator.
7148     #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_MEM_IO_SHIFT                                              0
7149     #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE                                                      (0x3<<1) // BAR4 32-bit or 64-bit.
7150     #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_TYPE_SHIFT                                                1
7151     #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH                                                  (0x1<<3) // BAR4 Prefetchable.
7152     #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_PREFETCH_SHIFT                                            3
7153     #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_START                                                     (0xfffffff<<4) // BAR4 Base Address.
7154     #define PCIEIP_VF_REG_VF_BAR4_REG_BAR4_START_SHIFT                                               4
7155 #define PCIEIP_VF_REG_VF_BAR5_REG                                                                    0x000024UL //Access:R    DataWidth:0x20  BAR5 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7156     #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO                                                    (0x1<<0) // BAR5 Memory Space Indicator.
7157     #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_MEM_IO_SHIFT                                              0
7158     #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE                                                      (0x3<<1) // BAR5 32-bit or 64-bit.
7159     #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_TYPE_SHIFT                                                1
7160     #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH                                                  (0x1<<3) // BAR5 Prefetchable.
7161     #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_PREFETCH_SHIFT                                            3
7162     #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_START                                                     (0xfffffff<<4) // BAR5 Base Address.
7163     #define PCIEIP_VF_REG_VF_BAR5_REG_BAR5_START_SHIFT                                               4
7164 #define PCIEIP_VF_REG_VF_CARDBUS_CIS_PTR_REG                                                         0x000028UL //Access:R    DataWidth:0x20  CardBus CIS Pointer Register.  Chips: K2
7165 #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG                                        0x00002cUL //Access:RW   DataWidth:0x20  Subsystem ID and Subsystem Vendor ID Register.  Chips: K2
7166     #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID                   (0xffff<<0) // Subsystem Vendor ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7167     #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_VENDOR_ID_SHIFT             0
7168     #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID                      (0xffff<<16) // Subsystem Device ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7169     #define PCIEIP_VF_REG_VF_SUBSYSTEM_ID_SUBSYSTEM_VENDOR_ID_REG_SUBSYS_DEV_ID_SHIFT                16
7170 #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG                                                             0x000034UL //Access:R    DataWidth:0x20  Capability Pointer Register.  Chips: K2
7171     #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_CAP_POINTER                                             (0xff<<0) // Pointer to first item in the PCI Capability Structure.   Note: This register field is sticky.
7172     #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_CAP_POINTER_SHIFT                                       0
7173     #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_RSVDP_8                                                 (0xffffff<<8) // Reserved for future use.
7174     #define PCIEIP_VF_REG_VF_PCI_CAP_PTR_REG_RSVDP_8_SHIFT                                           8
7175 #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG                      0x00003cUL //Access:R    DataWidth:0x20  Interrupt Line and Pin Register.  Chips: K2
7176     #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE         (0xff<<0) // PCI Compatible Interrupt Line Routing Register Field.
7177     #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_LINE_SHIFT   0
7178     #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN          (0xff<<8) // PCI Compatible Interrupt Pin Register Field.
7179     #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_INT_PIN_SHIFT    8
7180     #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16         (0xffff<<16) // Reserved for future use.
7181     #define PCIEIP_VF_REG_VF_MAX_LATENCY_MIN_GRANT_INTERRUPT_PIN_INTERRUPT_LINE_REG_RSVDP_16_SHIFT   16
7182 #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG                                  0x000070UL //Access:RW   DataWidth:0x20  PCI Express Capabilities, ID, Next Pointer Register.  Chips: K2
7183     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID                  (0xff<<0) // PCIE Capability ID.
7184     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_ID_SHIFT            0
7185     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR            (0xff<<8) // PCIE Next Capability Pointer.
7186     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_NEXT_PTR_SHIFT      8
7187     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG                 (0xf<<16) // PCIE Capability Version Number.
7188     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_CAP_REG_SHIFT           16
7189     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE           (0xf<<20) // PCIE Device/PortType.
7190     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_DEV_PORT_TYPE_SHIFT     20
7191     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP                (0x1<<24) // PCIe Slot Implemented Valid.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7192     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_SLOT_IMP_SHIFT          24
7193     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM             (0x1f<<25) // PCIE Interrupt Message Number.
7194     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_PCIE_INT_MSG_NUM_SHIFT       25
7195     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD                         (0x1<<30) // Reserved.
7196     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVD_SHIFT                   30
7197     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31                     (0x1<<31) // Reserved for future use.
7198     #define PCIEIP_VF_REG_VF_PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG_RSVDP_31_SHIFT               31
7199 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG                                                     0x000074UL //Access:RW   DataWidth:0x20  Device Capabilities Register.  Chips: K2
7200     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE                       (0x7<<0) // Max Payload Size Supported.
7201     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_MAX_PAYLOAD_SIZE_SHIFT                 0
7202     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT                   (0x3<<3) // Phantom Functions Supported.
7203     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_PHANTOM_FUNC_SUPPORT_SHIFT             3
7204     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP                           (0x1<<5) // Extended Tag Field Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7205     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EXT_TAG_SUPP_SHIFT                     5
7206     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY                   (0x7<<6) // Applies to endpoints only L0s acceptable latency.
7207     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L0S_ACCPT_LATENCY_SHIFT             6
7208     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY                    (0x7<<9) // Applies to endpoints only L1 acceptable latency.
7209     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_EP_L1_ACCPT_LATENCY_SHIFT              9
7210     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_RSVDP_12                                        (0x7<<12) // Reserved for future use.
7211     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_RSVDP_12_SHIFT                                  12
7212     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT                  (0x1<<15) // Role-based Error Reporting Implemented.
7213     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_ROLE_BASED_ERR_REPORT_SHIFT            15
7214     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_RSVDP_16                                        (0x3<<16) // Reserved for future use.
7215     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_RSVDP_16_SHIFT                                  16
7216     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE                 (0xff<<18) // Captured Slot Power Limit Value.
7217     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_VALUE_SHIFT           18
7218     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE                 (0x3<<26) // Captured Slot Power Limit Scale.
7219     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_CAP_SLOT_PWR_LMT_SCALE_SHIFT           26
7220     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP                                (0x1<<28) // Function Level Reset Capability (endpoints only).
7221     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_PCIE_CAP_FLR_CAP_SHIFT                          28
7222     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_RSVDP_29                                        (0x7<<29) // Reserved for future use.
7223     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES_REG_RSVDP_29_SHIFT                                  29
7224 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS                                                0x000078UL //Access:RW   DataWidth:0x20  Device Control and Status Register.  Chips: K2
7225     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN                (0x1<<0) // Correctable Error Reporting Enable.
7226     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_REPORT_EN_SHIFT          0
7227     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN           (0x1<<1) // Non-fatal Error Reporting Enable.
7228     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_REPORT_EN_SHIFT     1
7229     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN               (0x1<<2) // Fatal Error Reporting Enable.
7230     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_REPORT_EN_SHIFT         2
7231     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN              (0x1<<3) // Unsupported Request Reporting Enable.
7232     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORT_REQ_REP_EN_SHIFT        3
7233     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER                      (0x1<<4) // Enable Relaxed Ordering.
7234     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_REL_ORDER_SHIFT                4
7235     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS               (0x7<<5) // Max Payload Size. Max_Payload_Size . This field sets maximum TLP payload size for the Function. Permissible values that can be programmed are indicated by the Max_Payload_Size Supported field (PCIE_CAP_MAX_PAYLOAD_SIZE) in the Device Capabilities register (DEVICE_CAPABILITIES_REG).
7236     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_PAYLOAD_SIZE_CS_SHIFT         5
7237     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN                        (0x1<<8) // Extended Tag Field Enable.   The write value is gated with the PCIE_CAP_EXT_TAG_SUPP field of DEVICE_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_EXT_TAG_SUPP ? RW : RO
7238     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EXT_TAG_EN_SHIFT                  8
7239     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN                   (0x1<<9) // Phantom Functions Enable.   The write value is gated with the PCIE_CAP_PHANTOM_FUNC_SUPPORT field of DEVICE_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: DEVICE_CAPABILITIES_REG.PCIE_CAP_PHANTOM_FUNC_SUPPORT ? RW : RO
7240     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_PHANTOM_FUNC_EN_SHIFT             9
7241     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN                   (0x1<<10) // Aux Power PM Enable.   This bit is derived by sampling the sys_aux_pwr_det input.
7242     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_PM_EN_SHIFT             10
7243     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP                       (0x1<<11) // Enable No Snoop.   Note: The access attributes of this field are as follows:  - Dbi: R
7244     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_EN_NO_SNOOP_SHIFT                 11
7245     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE                 (0x7<<12) // Max Read Request Size.
7246     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_MAX_READ_REQ_SIZE_SHIFT           12
7247     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR                      (0x1<<15) // Initiate Function Level Reset (for endpoints).
7248     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_INITIATE_FLR_SHIFT                15
7249     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED                 (0x1<<16) // Correctable Error Detected Status.
7250     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_CORR_ERR_DETECTED_SHIFT           16
7251     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED            (0x1<<17) // Non-Fatal Error Detected Status.
7252     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_NON_FATAL_ERR_DETECTED_SHIFT      17
7253     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED                (0x1<<18) // Fatal Error Detected Status.
7254     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_FATAL_ERR_DETECTED_SHIFT          18
7255     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED          (0x1<<19) // Unsupported Request Detected Status.
7256     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_UNSUPPORTED_REQ_DETECTED_SHIFT    19
7257     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED                (0x1<<20) // Aux Power Detected Status.   This bit is derived by sampling the sys_aux_pwr_det input.
7258     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_AUX_POWER_DETECTED_SHIFT          20
7259     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING                     (0x1<<21) // Transactions Pending Status.
7260     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_PCIE_CAP_TRANS_PENDING_SHIFT               21
7261     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22                                   (0x3ff<<22) // Reserved for future use.
7262     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL_DEVICE_STATUS_RSVDP_22_SHIFT                             22
7263 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG                                                       0x00007cUL //Access:RW   DataWidth:0x20  Link Capabilities Register.  Chips: K2
7264     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED                           (0xf<<0) // Maximum Link Speed.   In M-PCIe mode, the reset and dynamic values of this field are calculated by the core.
7265     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_SPEED_SHIFT                     0
7266     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH                           (0x3f<<4) // Maximum Link Width.   In M-PCIe mode, the reset and dynamic values of this field are calculated by the core.
7267     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_MAX_LINK_WIDTH_SHIFT                     4
7268     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT             (0x3<<10) // Level of ASPM (Active State Power Management) Support.
7269     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT_SHIFT       10
7270     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY                         (0x7<<12) // LOs Exit Latency.  There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.
7271     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L0S_EXIT_LATENCY_SHIFT                   12
7272     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY                          (0x7<<15) // L1 Exit Latency.  There are two each of these register fields, this one and a shadow one at the same address. The Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG) determines which one is used by the core and which one is accessed by a read request. Common Clock operation is supported (possible) in the core when one or more of the following expressions is true:  - CX_NFTS !=CX_COMM_NFTS  - DEFAULT_L0S_EXIT_LATENCY !=DEFAULT_COMM_L0S_EXIT_LATENCY  - DEFAULT_L1_EXIT_LATENCY !=DEFAULT_COMM_L1_EXIT_LATENCY Common Clock operation is enabled in the core when you set the Common Clock bit (PCIE_CAP_COMMON_CLK_CONFIG) of the Link Control Register (LINK_CONTROL_LINK_STATUS_REG). The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the shadow field at this location.
7273     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_L1_EXIT_LATENCY_SHIFT                    15
7274     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN                          (0x1<<18) // Clock Power Management.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7275     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_CLOCK_POWER_MAN_SHIFT                    18
7276     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP                (0x1<<19) // Surprise Down Error Reporting Capable.
7277     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP_SHIFT          19
7278     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP                       (0x1<<20) // Data Link Layer Link Active Reporting Capable.
7279     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_DLL_ACTIVE_REP_CAP_SHIFT                 20
7280     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP                          (0x1<<21) // Link Bandwidth Notification Capable.
7281     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_LINK_BW_NOT_CAP_SHIFT                    21
7282     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE                      (0x1<<22) // ASPM Optionality Compliance.   Note: The access attributes of this field are as follows:  - Dbi: R
7283     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_ASPM_OPT_COMPLIANCE_SHIFT                22
7284     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_RSVDP_23                                          (0x1<<23) // Reserved for future use.
7285     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_RSVDP_23_SHIFT                                    23
7286     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM                                 (0xff<<24) // Port Number.
7287     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES_REG_PCIE_CAP_PORT_NUM_SHIFT                           24
7288 #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG                                                0x000080UL //Access:RW   DataWidth:0x20  Link Control and Status Register.  Chips: K2
7289     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL      (0x3<<0) // Active State Power Management (ASPM) Control.
7290     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL_SHIFT 0
7291     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2                                    (0x1<<2) // Reserved for future use.
7292     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_RSVDP_2_SHIFT                              2
7293     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB                               (0x1<<3) // Read Completion Boundary (RCB).
7294     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RCB_SHIFT                         3
7295     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE                      (0x1<<4) // Initiate Link Disable.   In a DSP that supports crosslink, the core gates the write value with the CROSS_LINK_EN field in PORT_LINK_CTRL_OFF.  Note: The access attributes of this field are as follows:  - Dbi: CX_CROSSLINK_ENABLE=1 && PORT_LINK_CTRL_OFF.CROSS_LINK_EN=1||CX_CROSSLINK_ENABLE=0 && dsp=1? RW : RO
7296     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_DISABLE_SHIFT                4
7297     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK                      (0x1<<5) // Initiate Link Retrain.   Note: The access attributes of this field are as follows:  - Dbi: see description
7298     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_RETRAIN_LINK_SHIFT                5
7299     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG                 (0x1<<6) // Common Clock Configuration.
7300     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_COMMON_CLK_CONFIG_SHIFT           6
7301     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH                    (0x1<<7) // Extended Synch.
7302     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EXTENDED_SYNCH_SHIFT              7
7303     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN                  (0x1<<8) // Enable Clock Power Management.   The write value is gated with the PCIE_CAP_CLOCK_POWER_MAN field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_CLOCK_POWER_MAN ? RWS : ROS
7304     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_EN_CLK_POWER_MAN_SHIFT            8
7305     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE             (0x1<<9) // Hardware Autonomous Width Disable.
7306     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_HW_AUTO_WIDTH_DISABLE_SHIFT       9
7307     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN                (0x1<<10) // Link Bandwidth Management Interrupt Enable.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
7308     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_INT_EN_SHIFT          10
7309     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN               (0x1<<11) // Link Autonomous Bandwidth Management Interrupt Enable.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW : RO
7310     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_INT_EN_SHIFT         11
7311     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12                                   (0x3<<12) // Reserved for future use.
7312     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_RSVDP_12_SHIFT                             12
7313     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL             (0x3<<14) // DRS Signaling Control.
7314     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DRS_SIGNALING_CONTROL_SHIFT       14
7315     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED                        (0xf<<16) // Current Link Speed.
7316     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_SPEED_SHIFT                  16
7317     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH                   (0x3f<<20) // Negotiated Link Width.
7318     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_NEGO_LINK_WIDTH_SHIFT             20
7319     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26                                   (0x1<<26) // Reserved for future use.
7320     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_RSVDP_26_SHIFT                             26
7321     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING                     (0x1<<27) // LTSSM is in Configuration or Recovery State.   Note: The access attributes of this field are as follows:  - Dbi: R
7322     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_TRAINING_SHIFT               27
7323     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG                   (0x1<<28) // Slot Clock Configuration.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7324     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_SLOT_CLK_CONFIG_SHIFT             28
7325     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE                        (0x1<<29) // Data Link Layer Active.
7326     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_DLL_ACTIVE_SHIFT                  29
7327     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS                (0x1<<30) // Link Bandwidth Management Status.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
7328     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_BW_MAN_STATUS_SHIFT          30
7329     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS               (0x1<<31) // Link Autonomous Bandwidth Status.   The write value is gated with the PCIE_CAP_LINK_BW_NOT_CAP field in LINK_CAPABILITIES_REG.  Note: The access attributes of this field are as follows:  - Dbi: LINK_CAPABILITIES_REG.PCIE_CAP_LINK_BW_NOT_CAP ? RW1C : RO
7330     #define PCIEIP_VF_REG_VF_LINK_CONTROL_LINK_STATUS_REG_PCIE_CAP_LINK_AUTO_BW_STATUS_SHIFT         31
7331 #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG                                                    0x000094UL //Access:R    DataWidth:0x20  Device Capabilities 2 Register.  Chips: K2
7332     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE                     (0xf<<0) // Completion Timeout Ranges Supported.
7333     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_RANGE_SHIFT               0
7334     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT           (0x1<<4) // Completion Timeout Disable Supported.
7335     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT_SHIFT     4
7336     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT                   (0x1<<5) // ARI Forwarding Supported.
7337     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_SHIFT             5
7338     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP                   (0x1<<6) // Atomic Operation Routing Supported.
7339     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_ATOMIC_ROUTING_SUPP_SHIFT             6
7340     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP                    (0x1<<7) // 32 Bit AtomicOp Completer Supported.
7341     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_32_ATOMIC_CPL_SUPP_SHIFT              7
7342     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP                    (0x1<<8) // 64 Bit AtomicOp Completer Supported.
7343     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_64_ATOMIC_CPL_SUPP_SHIFT              8
7344     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP                      (0x1<<9) // 128 Bit CAS Completer Supported.
7345     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_128_CAS_CPL_SUPP_SHIFT                9
7346     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR                    (0x1<<10) // No Relaxed Ordering Enabled PR-PR Passing.
7347     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_NO_RO_EN_PR2PR_PAR_SHIFT              10
7348     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP                              (0x1<<11) // LTR Mechanism Supported.
7349     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_LTR_SUPP_SHIFT                        11
7350     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0                   (0x1<<12) // TPH Completer Supported Bit 0.
7351     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_0_SHIFT             12
7352     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1                   (0x1<<13) // TPH Completer Supported Bit 1.
7353     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_TPH_CMPLT_SUPPORT_1_SHIFT             13
7354     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_RSVDP_14                                       (0xf<<14) // Reserved for future use.
7355     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_RSVDP_14_SHIFT                                 14
7356     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT                          (0x3<<18) // (OBFF) Optimized Buffer Flush/fill Supported.
7357     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_PCIE_CAP_OBFF_SUPPORT_SHIFT                    18
7358     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_UNUSED_0                                       (0xf<<20) // reserved
7359     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_UNUSED_0_SHIFT                                 20
7360     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_RSVDP_24                                       (0x7f<<24) // Reserved for future use.
7361     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_RSVDP_24_SHIFT                                 24
7362     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_UNUSED_1                                       (0x1<<31) // reserved
7363     #define PCIEIP_VF_REG_VF_DEVICE_CAPABILITIES2_REG_UNUSED_1_SHIFT                                 31
7364 #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG                                          0x000098UL //Access:R    DataWidth:0x20  Device Control 2 and Status 2 Register.  Chips: K2
7365     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE           (0xf<<0) // Completion Timeout Value.
7366     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_VALUE_SHIFT     0
7367     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE         (0x1<<4) // Completion Timeout Disable.
7368     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_CPL_TIMEOUT_DISABLE_SHIFT   4
7369     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS      (0x1<<5) // ARI Forwarding Enable.
7370     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ARI_FORWARD_SUPPORT_CS_SHIFT 5
7371     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN               (0x1<<6) // AtomicOp Requester Enable. Reflected on the cfg_atomic_req_en output.
7372     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_REQ_EN_SHIFT         6
7373     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK           (0x1<<7) // AtomicOp Egress Blocking. Reflected on the cfg_atomic_egress_block output.
7374     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_ATOMIC_EGRESS_BLK_SHIFT     7
7375     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN                  (0x1<<8) // IDO Request Enable.
7376     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_REQ_EN_SHIFT            8
7377     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN                  (0x1<<9) // IDO Completion Enable.
7378     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_IDO_CPL_EN_SHIFT            9
7379     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN                      (0x1<<10) // LTR Mechanism Enable.   The write value is gated with the PCIE_CAP_LTR_SUPP field of DEVICE_CAPABILITIES2_REG.  Note: RW for function #0 and RsdvP for all other functions
7380     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_LTR_EN_SHIFT                10
7381     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_UNUSED_0                             (0x3<<11) // reserved
7382     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_UNUSED_0_SHIFT                       11
7383     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN                     (0x3<<13) // OBFF Enable.   Note: RW for function #0 and RsdvP for all other functions
7384     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_PCIE_CAP_OBFF_EN_SHIFT               13
7385     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_UNUSED_1                             (0x1ffff<<15) // reserved
7386     #define PCIEIP_VF_REG_VF_DEVICE_CONTROL2_DEVICE_STATUS2_REG_UNUSED_1_SHIFT                       15
7387 #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG                                                      0x00009cUL //Access:RW   DataWidth:0x20  Link Capabilities 2 Register.  Chips: K2
7388     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_RSVDP_0                                          (0x1<<0) // Reserved for future use.
7389     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_RSVDP_0_SHIFT                                    0
7390     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR               (0x7f<<1) // Supported Link Speeds Vector.   This field has a default of (PCIE_CAP_MAX_LINK_SPEED == 0100) ? 0001111 : (PCIE_CAP_MAX_LINK_SPEED == 0011) ? 0000111 : (PCIE_CAP_MAX_LINK_SPEED == 0010) ? 0000011 : 0000001 where PCIE_CAP_MAX_LINK_SPEED is a field in the LINK_CAPABILITIES_REG register.
7391     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR_SHIFT         1
7392     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT                      (0x1<<8) // Cross Link Supported.
7393     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_PCIE_CAP_CROSS_LINK_SUPPORT_SHIFT                8
7394     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_RSVDP_9                                          (0x3fff<<9) // Reserved for future use.
7395     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_RSVDP_9_SHIFT                                    9
7396     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_UNUSED_0                                         (0x1<<23) // reserved
7397     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_UNUSED_0_SHIFT                                   23
7398     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_RSVDP_24                                         (0x7f<<24) // Reserved for future use.
7399     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_RSVDP_24_SHIFT                                   24
7400     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED                                    (0x1<<31) // DRS Supported.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R
7401     #define PCIEIP_VF_REG_VF_LINK_CAPABILITIES2_REG_DRS_SUPPORTED_SHIFT                              31
7402 #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG                                              0x0000a0UL //Access:R    DataWidth:0x20  Link Control 2 and Status 2 Register.  Chips: K2
7403     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_UNUSED_0                                 (0xffff<<0) // reserved
7404     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_UNUSED_0_SHIFT                           0
7405     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS                 (0x1<<16) // Current De-emphasis Level.    In M-PCIe mode this register is always 0x0. In C-PCIe mode, its contents are derived by sampling the PIPE
7406     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_PCIE_CAP_CURR_DEEMPHASIS_SHIFT           16
7407     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_UNUSED_1                                 (0x7ff<<17) // reserved
7408     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_UNUSED_1_SHIFT                           17
7409     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE                (0x7<<28) // Downstream Component Presence. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
7410     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DOWNSTREAM_COMPO_PRESENCE_SHIFT          28
7411     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED                     (0x1<<31) // DRS Message Received. For a description of this standard PCIe register field, see the PCI Express Base Specification 4.0.
7412     #define PCIEIP_VF_REG_VF_LINK_CONTROL2_LINK_STATUS2_REG_DRS_MESSAGE_RECEIVED_SHIFT               31
7413 #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG                                               0x0000b0UL //Access:RW   DataWidth:0x20  MSI-X Capability ID, Next Pointer, Control Registers.  Chips: K2
7414     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID                           (0xff<<0) // MSI-X Capability ID.
7415     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_ID_SHIFT                     0
7416     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET                  (0xff<<8) // MSI-X Next Capability Pointer.
7417     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_CAP_NEXT_OFFSET_SHIFT            8
7418     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE                       (0x7ff<<16) // MSI-X Table Size.   SRIOV Note: All VFs in a single PF have the same value for "MSI-X Table Size" (PCI_MSIX_TABLE_SIZE field in VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG). To write this common value, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PCI_MSIX_TABLE_SIZE field in the PF PCI_MSIX_CAP_ID_NEXT_CTRL_REG register.  Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R   - Dbi2: R
7419     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_TABLE_SIZE_SHIFT                 16
7420     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27                                  (0x7<<27) // Reserved for future use.
7421     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_RSVDP_27_SHIFT                            27
7422     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK                    (0x1<<30) // Function Mask.   Note: The access attributes of this field are as follows:  - Dbi: R/W
7423     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_FUNCTION_MASK_SHIFT              30
7424     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE                           (0x1<<31) // MSI-X Enable.   Note: The access attributes of this field are as follows:  - Dbi: R/W
7425     #define PCIEIP_VF_REG_VF_PCI_MSIX_CAP_ID_NEXT_CTRL_REG_PCI_MSIX_ENABLE_SHIFT                     31
7426 #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG                                                       0x0000b4UL //Access:R    DataWidth:0x20  MSI-X Table Offset and BIR Register.  Chips: K2
7427     #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR                                      (0x7<<0) // MSI-X Table Bar Indicator Register Field.
7428     #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_BIR_SHIFT                                0
7429     #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET                             (0x1fffffff<<3) // MSI-X Table Offset.
7430     #define PCIEIP_VF_REG_VF_MSIX_TABLE_OFFSET_REG_PCI_MSIX_TABLE_OFFSET_SHIFT                       3
7431 #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG                                                         0x0000b8UL //Access:R    DataWidth:0x20  MSI-X PBA Offset and BIR Register.  Chips: K2
7432     #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA                                        (0x7<<0) // MSI-X PBA BIR.
7433     #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_SHIFT                                  0
7434     #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET                                 (0x1fffffff<<3) // MSI-X PBA Offset.
7435     #define PCIEIP_VF_REG_VF_MSIX_PBA_OFFSET_REG_PCI_MSIX_PBA_OFFSET_SHIFT                           3
7436 #define PCIEIP_VF_REG_VF_ARI_BASE                                                                    0x000100UL //Access:RW   DataWidth:0x20  ARI Capability Header.  Chips: K2
7437     #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID                                       (0xffff<<0) // ARI Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7438     #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_PCIE_EXTENDED_CAP_ID_SHIFT                                 0
7439     #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_CAP_VERSION                                                (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7440     #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_CAP_VERSION_SHIFT                                          16
7441     #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_NEXT_OFFSET                                                (0xfff<<20) // Next Capability Offset.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7442     #define PCIEIP_VF_REG_VF_ARI_BASE_ARI_NEXT_OFFSET_SHIFT                                          20
7443 #define PCIEIP_VF_REG_VF_CAP_REG                                                                     0x000104UL //Access:R    DataWidth:0x20  ARI Capability and Control Register.  Chips: K2
7444     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP                                            (0x1<<0) // Multi Functional Virtual Channel (MFVC) Function Groups Capability.
7445     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_CAP_SHIFT                                      0
7446     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP                                             (0x1<<1) // ACS Function Groups Capability.
7447     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_CAP_SHIFT                                       1
7448     #define PCIEIP_VF_REG_VF_CAP_REG_RSVDP_2                                                         (0x3f<<2) // Reserved for future use.
7449     #define PCIEIP_VF_REG_VF_CAP_REG_RSVDP_2_SHIFT                                                   2
7450     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM                                                (0xff<<8) // Next Function Number.
7451     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_NEXT_FUN_NUM_SHIFT                                          8
7452     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN                                             (0x1<<16) // MFVC Function Groups Enable.
7453     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_MFVC_FUN_GRP_EN_SHIFT                                       16
7454     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN                                              (0x1<<17) // ACS Function Groups Enable.
7455     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_ACS_FUN_GRP_EN_SHIFT                                        17
7456     #define PCIEIP_VF_REG_VF_CAP_REG_RSVDP_18                                                        (0x3<<18) // Reserved for future use.
7457     #define PCIEIP_VF_REG_VF_CAP_REG_RSVDP_18_SHIFT                                                  18
7458     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_FUN_GRP                                                     (0x7<<20) // Function Group.
7459     #define PCIEIP_VF_REG_VF_CAP_REG_ARI_FUN_GRP_SHIFT                                               20
7460     #define PCIEIP_VF_REG_VF_CAP_REG_RSVDP_23                                                        (0x1ff<<23) // Reserved for future use.
7461     #define PCIEIP_VF_REG_VF_CAP_REG_RSVDP_23_SHIFT                                                  23
7462 #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG                                                         0x000110UL //Access:RW   DataWidth:0x20  TPH Extended Capability Header.  Chips: K2
7463     #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID                                     (0xffff<<0) // TPH Extended Capability ID.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7464     #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_PCIE_EXT_CAP_ID_SHIFT                               0
7465     #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER                                     (0xf<<16) // Capability Version.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7466     #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_CAP_VER_SHIFT                               16
7467     #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR                                    (0xfff<<20) // Next Capability Pointer.   Note: The access attributes of this field are as follows:  - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)  Note: This register field is sticky.
7468     #define PCIEIP_VF_REG_VF_TPH_EXT_CAP_HDR_REG_TPH_REQ_NEXT_PTR_SHIFT                              20
7469 #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG                                                         0x000114UL //Access:R    DataWidth:0x20  TPH Requestor Capability Register.   SRIOV Note: All VFs in a single PF have the same values for VF_TPH_REQ_CAP_REG_REG. To write this common register, you must perform a DBI_CS2 write (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) while accessing the PF TPH_REQ_CAP_REG_REG register.  Chips: K2
7470     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE                                  (0x1<<0) // No ST Mode Supported.
7471     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_NO_ST_MODE_SHIFT                            0
7472     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC                                 (0x1<<1) // Interrupt Vector Mode Supported.   Note: This register field is sticky.
7473     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_INT_VEC_SHIFT                           1
7474     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC                                 (0x1<<2) // Device Specific Mode Supported.   Note: This register field is sticky.
7475     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_DEVICE_SPEC_SHIFT                           2
7476     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_RSVDP_3                                             (0x1f<<3) // Reserved for future use.
7477     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_RSVDP_3_SHIFT                                       3
7478     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH                                (0x1<<8) // Extended TPH Requester Supported.   Note: This register field is sticky.
7479     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_EXTENDED_TPH_SHIFT                          8
7480     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0                          (0x1<<9) // ST Table Location Bit 0.   Note: This register field is sticky.
7481     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_0_SHIFT                    9
7482     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1                          (0x1<<10) // ST Table Location Bit 1.   Note: This register field is sticky.
7483     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_LOC_1_SHIFT                    10
7484     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_RSVDP_11                                            (0x1f<<11) // Reserved for future use.
7485     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_RSVDP_11_SHIFT                                      11
7486     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE                           (0x7ff<<16) // ST Table Size.   Note: This register field is sticky.
7487     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_TPH_REQ_CAP_ST_TABLE_SIZE_SHIFT                     16
7488     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_RSVDP_27                                            (0x1f<<27) // Reserved for future use.
7489     #define PCIEIP_VF_REG_VF_TPH_REQ_CAP_REG_REG_RSVDP_27_SHIFT                                      27
7490 #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG                                                     0x000118UL //Access:RW   DataWidth:0x20  TPH Requestor Control Register.  Chips: K2
7491     #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT                          (0x7<<0) // ST Mode Select.   Note: The access attributes of this field are as follows:  - Dbi: R/W
7492     #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_ST_MODE_SELECT_SHIFT                    0
7493     #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_RSVDP_3                                         (0x1f<<3) // Reserved for future use.
7494     #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_RSVDP_3_SHIFT                                   3
7495     #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN                             (0x3<<8) // TPH Requester Enable Bit.
7496     #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_TPH_REQ_CTRL_REQ_EN_SHIFT                       8
7497     #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_RSVDP_10                                        (0x3fffff<<10) // Reserved for future use.
7498     #define PCIEIP_VF_REG_VF_TPH_REQ_CONTROL_REG_REG_RSVDP_10_SHIFT                                  10
7499 #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0                                                          0x00011cUL //Access:RW   DataWidth:0x20  TPH ST Table Register 0.  Chips: K2
7500     #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0                             (0xff<<0) // ST Table 0 Lower Byte.   Note: The access attributes of this field are as follows:  - Dbi: this field is RW or Tie to 0 by table size configure
7501     #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_LOWER_0_SHIFT                       0
7502     #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0                            (0xff<<8) // ST Table 0 Upper Byte.   Note: The access attributes of this field are as follows:  - Dbi: this field is RW or Tie to 0 by table size configure
7503     #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_TPH_REQ_ST_TABLE_HIGHER_0_SHIFT                      8
7504     #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_UNUSED_0                                             (0xffff<<16) // reserved
7505     #define PCIEIP_VF_REG_VF_TPH_ST_TABLE_REG_0_UNUSED_0_SHIFT                                       16
7506 #define PCIEIP_SHADOW_REG_BAR0_MASK_REG                                                              0x000010UL //Access:W    DataWidth:0x20  BAR0 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7507     #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED                                   (0x1<<0) // BAR0 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7508     #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_ENABLED_SHIFT                             0
7509     #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK                                      (0x7fffffff<<1) // BAR0 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7510     #define PCIEIP_SHADOW_REG_BAR0_MASK_REG_PCI_TYPE0_BAR0_MASK_SHIFT                                1
7511 #define PCIEIP_SHADOW_REG_BAR1_MASK_REG                                                              0x000014UL //Access:RW   DataWidth:0x20  BAR1 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7512     #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED                                   (0x1<<0) // BAR1 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7513     #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_ENABLED_SHIFT                             0
7514     #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK                                      (0x7fffffff<<1) // BAR1 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7515     #define PCIEIP_SHADOW_REG_BAR1_MASK_REG_PCI_TYPE0_BAR1_MASK_SHIFT                                1
7516 #define PCIEIP_SHADOW_REG_BAR4_MASK_REG                                                              0x000020UL //Access:W    DataWidth:0x20  BAR4 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7517     #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED                                   (0x1<<0) // BAR4 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7518     #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_ENABLED_SHIFT                             0
7519     #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK                                      (0x7fffffff<<1) // BAR4 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7520     #define PCIEIP_SHADOW_REG_BAR4_MASK_REG_PCI_TYPE0_BAR4_MASK_SHIFT                                1
7521 #define PCIEIP_SHADOW_REG_BAR5_MASK_REG                                                              0x000024UL //Access:W    DataWidth:0x20  BAR5 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7522     #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED                                   (0x1<<0) // BAR5 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7523     #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_ENABLED_SHIFT                             0
7524     #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK                                      (0x7fffffff<<1) // BAR5 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7525     #define PCIEIP_SHADOW_REG_BAR5_MASK_REG_PCI_TYPE0_BAR5_MASK_SHIFT                                1
7526 #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG                                                       0x000030UL //Access:R    DataWidth:0x20  Expansion ROM BAR and Mask Register.  The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7527     #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED                                   (0x1<<0) // Expansion ROM Bar Mask Register Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: if ROM_BAR_ENABLED then W else R
7528     #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_BAR_ENABLED_SHIFT                             0
7529     #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK                                          (0x7fffffff<<1) // Expansion ROM Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: if ROM_BAR_ENABLED then W else R
7530     #define PCIEIP_SHADOW_REG_EXP_ROM_BAR_MASK_REG_ROM_MASK_SHIFT                                    1
7531 #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS                                                   0x0001a4UL //Access:R    DataWidth:0x20  TotalVFs InitialVFs Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two of these registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address.  Chips: K2
7532     #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_INITIAL_VFS                      (0xffff<<0) // InitialVFs. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two InitialVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W
7533     #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_INITIAL_VFS_SHIFT                0
7534     #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_TOTAL_VFS                        (0xffff<<16) // Total VFs (Max Number of VFs). For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two TotalVFs registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W
7535     #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_INITIAL_VFS_SHADOW_SRIOV_TOTAL_VFS_SHIFT                  16
7536 #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION                                            0x0001acUL //Access:R    DataWidth:0x20  VF Stride and Offset Register. For a description of this standard PCIe register, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1.  Chips: K2
7537     #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_STRIDE                 (0xffff<<0) // VF Stride. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two VF Stride registers; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W
7538     #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_STRIDE_SHIFT           0
7539     #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_OFFSET                 (0xffff<<16) // First VF Offset. For a description of this standard PCIe register field, see the Single Root I/O Virtualization and Sharing Specification Revision 1.1. There are two First VF Offset registers at this address location; one each for ARI Capable and non-ARI Capable Hierarchies. The "ARI Capable Hierarchy" bit (SRIOV_ARI_CAPABLE_HIER) of the PF0 "SR-IOV Control Register" (STATUS_CONTROL_REG) determines which one is used by the core when SR-IOV is being used, and which one is accessed by a read request. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W
7540     #define PCIEIP_SHADOW_REG_SHADOW_SRIOV_VF_OFFSET_POSITION_SHADOW_SRIOV_VF_OFFSET_SHIFT           16
7541 #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG                                                        0x0001bcUL //Access:W    DataWidth:0x20  BAR0 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7542     #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED                             (0x1<<0) // BAR0 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7543     #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_ENABLED_SHIFT                       0
7544     #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK                                (0x7fffffff<<1) // BAR0 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7545     #define PCIEIP_SHADOW_REG_SRIOV_BAR0_MASK_REG_PCI_SRIOV_BAR0_MASK_SHIFT                          1
7546 #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG                                                        0x0001c0UL //Access:RW   DataWidth:0x20  BAR1 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7547     #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED                             (0x1<<0) // BAR1 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7548     #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_ENABLED_SHIFT                       0
7549     #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK                                (0x7fffffff<<1) // BAR1 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7550     #define PCIEIP_SHADOW_REG_SRIOV_BAR1_MASK_REG_PCI_SRIOV_BAR1_MASK_SHIFT                          1
7551 #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG                                                        0x0001c4UL //Access:W    DataWidth:0x20  BAR2 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7552     #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED                             (0x1<<0) // BAR2 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7553     #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_ENABLED_SHIFT                       0
7554     #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK                                (0x7fffffff<<1) // BAR2 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7555     #define PCIEIP_SHADOW_REG_SRIOV_BAR2_MASK_REG_PCI_SRIOV_BAR2_MASK_SHIFT                          1
7556 #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG                                                        0x0001c8UL //Access:RW   DataWidth:0x20  BAR3 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7557     #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED                             (0x1<<0) // BAR3 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7558     #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_ENABLED_SHIFT                       0
7559     #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK                                (0x7fffffff<<1) // BAR3 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7560     #define PCIEIP_SHADOW_REG_SRIOV_BAR3_MASK_REG_PCI_SRIOV_BAR3_MASK_SHIFT                          1
7561 #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG                                                        0x0001ccUL //Access:W    DataWidth:0x20  BAR4 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7562     #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED                             (0x1<<0) // BAR4 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7563     #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_ENABLED_SHIFT                       0
7564     #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK                                (0x7fffffff<<1) // BAR4 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7565     #define PCIEIP_SHADOW_REG_SRIOV_BAR4_MASK_REG_PCI_SRIOV_BAR4_MASK_SHIFT                          1
7566 #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG                                                        0x0001d0UL //Access:RW   DataWidth:0x20  BAR5 and BAR Mask.  The mask for this BAR exists (if implemented) as a shadow register at this address. The assertion of CS2 (that is, assert the dbi_cs2 input, or the CS2 address bit for the AXI bridge) is required to write to the second register at this address. For more details, see "Accessing Configuration Registers".  Chips: K2
7567     #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED                             (0x1<<0) // BAR5 Mask Enabled.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7568     #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_ENABLED_SHIFT                       0
7569     #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK                                (0x7fffffff<<1) // BAR5 Mask.   Note: The access attributes of this field are as follows:  - Dbi: No access   - Dbi2: W (sticky) Note: This register field is sticky.
7570     #define PCIEIP_SHADOW_REG_SRIOV_BAR5_MASK_REG_PCI_SRIOV_BAR5_MASK_SHIFT                          1
7571 #define SEM_FAST_REG_RAM_EXT_DISABLE                                                                 0x000004UL //Access:RW   DataWidth:0x1   Disable for SDM write to int_ram.  Chips: BB_A0 BB_B0 K2
7572 #define SEM_FAST_REG_INT_STS                                                                         0x000040UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7573     #define SEM_FAST_REG_INT_STS_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
7574     #define SEM_FAST_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                 0
7575 #define SEM_FAST_REG_INT_MASK                                                                        0x000044UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7576     #define SEM_FAST_REG_INT_MASK_ADDRESS_ERROR                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: SEM_FAST_REG_INT_STS.ADDRESS_ERROR .
7577     #define SEM_FAST_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                0
7578 #define SEM_FAST_REG_INT_STS_WR                                                                      0x000048UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7579     #define SEM_FAST_REG_INT_STS_WR_ADDRESS_ERROR                                                    (0x1<<0) // Signals an unknown address to the rf module.
7580     #define SEM_FAST_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                              0
7581 #define SEM_FAST_REG_INT_STS_CLR                                                                     0x00004cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7582     #define SEM_FAST_REG_INT_STS_CLR_ADDRESS_ERROR                                                   (0x1<<0) // Signals an unknown address to the rf module.
7583     #define SEM_FAST_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                             0
7584 #define SEM_FAST_REG_ERROR_RST                                                                       0x000050UL //Access:W    DataWidth:0x1   Reset to error interrupt.  Chips: BB_A0 BB_B0 K2
7585 #define SEM_FAST_REG_PARITY_RST                                                                      0x000054UL //Access:W    DataWidth:0x1   Reset to parity interrupt.  Chips: BB_A0 BB_B0 K2
7586 #define SEM_FAST_REG_PRTY_MASK_H_0                                                                   0x000204UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: K2
7587     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                             (0x1<<0) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
7588     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                       0
7589     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY                                             (0x1<<1) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
7590     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_SHIFT                                       1
7591     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY                                             (0x1<<2) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
7592     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_SHIFT                                       2
7593     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                             (0x1<<3) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
7594     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                       3
7595     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY                                             (0x1<<4) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
7596     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_SHIFT                                       4
7597     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY                                             (0x1<<5) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
7598     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_SHIFT                                       5
7599     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY                                             (0x1<<6) // This bit masks, when set, the Parity bit: SEM_FAST_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
7600     #define SEM_FAST_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_SHIFT                                       6
7601 #define SEM_FAST_REG_MEM_ECC_EVENTS                                                                  0x000210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
7602 #define SEM_FAST_REG_MEM024_I_MEM_DFT                                                                0x000218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.i_sem_sync.i_sem_sync_ls.i_sem_fast_iram_wsync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
7603 #define SEM_FAST_REG_RESERVED_21C                                                                    0x00021cUL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7604 #define SEM_FAST_REG_MEM023_I_MEM_DFT                                                                0x000220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.i_sem_sync.i_sem_sync_ls.i_sem_fast_iram_rsync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
7605 #define SEM_FAST_REG_MEM022_I_MEM_DFT                                                                0x000224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.i_sem_sync.i_sem_sync_ls.i_sem_fast_ext_store_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
7606 #define SEM_FAST_REG_RESERVED_228                                                                    0x000228UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7607 #define SEM_FAST_REG_MEM021_I_MEM_DFT                                                                0x00022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.i_sem_sync.i_sem_sync_ls.i_sem_fast_ext_load_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
7608 #define SEM_FAST_REG_MEM020_I_MEM_DFT                                                                0x000230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.i_sem_sync.i_sem_sync_ls.i_sem_fast_dbg_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
7609 #define SEM_FAST_REG_RESERVED_234                                                                    0x000234UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7610 #define SEM_FAST_REG_MEM019_I_MEM_DFT                                                                0x000238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.i_sem_sync.i_sem_sync_dra.i_sem_fast_dra_wsync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
7611 #define SEM_FAST_REG_RESERVED_23C                                                                    0x00023cUL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7612 #define SEM_FAST_REG_MEM018_I_MEM_DFT                                                                0x000240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.i_sem_sync.i_sem_sync_dra.i_sem_fast_dra_rsync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
7613 #define SEM_FAST_REG_RESERVED_244                                                                    0x000244UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7614 #define SEM_FAST_REG_MEM017_I_ESILICON_TCAM_DFT                                                      0x000248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.i_sem_cam.i_sem_cam_wrapper.i_esilicon_tcam of module ts_28hpc_tcam_111_hs_e_t_shlas_128x69_pbn_bist_wr. [2]=rme, [1:0]=t_strw.  Chips: K2
7615 #define SEM_FAST_REG_MEM001_I_MEM_DFT                                                                0x00024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.PRAM_MEM_GEN_FOR[0].PRAM_INST_A_GEN_IF.i_stormp_h.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
7616 #define SEM_FAST_REG_RESERVED_250                                                                    0x000250UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7617 #define SEM_FAST_REG_MEM002_I_MEM_DFT                                                                0x000254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.PRAM_MEM_GEN_FOR[0].PRAM_INST_A_GEN_IF.i_stormp_l.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
7618 #define SEM_FAST_REG_RESERVED_258                                                                    0x000258UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7619 #define SEM_FAST_REG_MEM003_I_MEM_DFT                                                                0x00025cUL //Access:R    DataWidth:0x20  Reserved for PRAM DFT that are shared for all logical memory replications  Chips: K2
7620 #define SEM_FAST_REG_RESERVED_260                                                                    0x000260UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7621 #define SEM_FAST_REG_MEM004_I_MEM_DFT                                                                0x000264UL //Access:R    DataWidth:0x20  Reserved for PRAM DFT that are shared for all logical memory replications  Chips: K2
7622 #define SEM_FAST_REG_RESERVED_268                                                                    0x000268UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7623 #define SEM_FAST_REG_MEM005_I_MEM_DFT                                                                0x00026cUL //Access:R    DataWidth:0x20  Reserved for PRAM DFT that are shared for all logical memory replications  Chips: K2
7624 #define SEM_FAST_REG_RESERVED_270                                                                    0x000270UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7625 #define SEM_FAST_REG_MEM006_I_MEM_DFT                                                                0x000274UL //Access:R    DataWidth:0x20  Reserved for PRAM DFT that are shared for all logical memory replications  Chips: K2
7626 #define SEM_FAST_REG_RESERVED_278                                                                    0x000278UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7627 #define SEM_FAST_REG_MEM007_I_MEM_DFT                                                                0x00027cUL //Access:R    DataWidth:0x20  Reserved for PRAM DFT that are shared for all logical memory replications  Chips: K2
7628 #define SEM_FAST_REG_RESERVED_280                                                                    0x000280UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7629 #define SEM_FAST_REG_MEM008_I_MEM_DFT                                                                0x000284UL //Access:R    DataWidth:0x20  Reserved for PRAM DFT that are shared for all logical memory replications  Chips: K2
7630 #define SEM_FAST_REG_RESERVED_288                                                                    0x000288UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7631 #define SEM_FAST_REG_RESERVED_28C                                                                    0x00028cUL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7632 #define SEM_FAST_REG_RESERVED_290                                                                    0x000290UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7633 #define SEM_FAST_REG_RESERVED_294                                                                    0x000294UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7634 #define SEM_FAST_REG_RESERVED_298                                                                    0x000298UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7635 #define SEM_FAST_REG_RESERVED_29C                                                                    0x00029cUL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7636 #define SEM_FAST_REG_RESERVED_2A0                                                                    0x0002a0UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7637 #define SEM_FAST_REG_RESERVED_2A4                                                                    0x0002a4UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7638 #define SEM_FAST_REG_RESERVED_2A8                                                                    0x0002a8UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7639 #define SEM_FAST_REG_RESERVED_2AC                                                                    0x0002acUL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7640 #define SEM_FAST_REG_RESERVED_2B0                                                                    0x0002b0UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7641 #define SEM_FAST_REG_RESERVED_2B4                                                                    0x0002b4UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7642 #define SEM_FAST_REG_RESERVED_2B8                                                                    0x0002b8UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7643 #define SEM_FAST_REG_RESERVED_2BC                                                                    0x0002bcUL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7644 #define SEM_FAST_REG_RESERVED_2C0                                                                    0x0002c0UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7645 #define SEM_FAST_REG_MEM013_I_MEM_0_DFT                                                              0x0002c4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.REG_FILE_INST_GEN_FOR[0].i_rf.i_mem1.i_mem_0 of module es_gmem_2r2w. [2]=rme, [1:0]=t_strw.  Chips: K2
7646 #define SEM_FAST_REG_MEM014_I_MEM_0_DFT                                                              0x0002c8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.REG_FILE_INST_GEN_FOR[0].i_rf.i_mem2.i_mem_0 of module es_gmem_2r2w. [2]=rme, [1:0]=t_strw.  Chips: K2
7647 #define SEM_FAST_REG_RESERVED_2CC                                                                    0x0002ccUL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7648 #define SEM_FAST_REG_RESERVED_2D0                                                                    0x0002d0UL //Access:R    DataWidth:0x20  Reserved  Chips: K2
7649 #define SEM_FAST_REG_MEM015_I_MEM_0_DFT                                                              0x0002d4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.REG_FILE_INST_GEN_FOR[1].i_rf.i_mem1.i_mem_0 of module es_gmem_2r2w. [2]=rme, [1:0]=t_strw.  Chips: K2
7650 #define SEM_FAST_REG_MEM016_I_MEM_0_DFT                                                              0x0002d8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.REG_FILE_INST_GEN_FOR[1].i_rf.i_mem2.i_mem_0 of module es_gmem_2r2w. [2]=rme, [1:0]=t_strw.  Chips: K2
7651 #define SEM_FAST_REG_MEM009_I_MEM_DFT                                                                0x0002dcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance sem_pd.i_sem_pd_core.RAM_INST_GEN_FOR[0].i_int_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
7652 #define SEM_FAST_REG_MEM010_I_MEM_DFT                                                                0x0002e0UL //Access:R    DataWidth:0x20  Reserved for IRAM DFT that are shared for all logical memory replications  Chips: K2
7653 #define SEM_FAST_REG_MEM011_I_MEM_DFT                                                                0x0002e4UL //Access:R    DataWidth:0x20  Reserved for IRAM DFT that are shared for all logical memory replications  Chips: K2
7654 #define SEM_FAST_REG_MEM012_I_MEM_DFT                                                                0x0002e8UL //Access:R    DataWidth:0x20  Reserved for IRAM DFT that are shared for all logical memory replications  Chips: K2
7655 #define SEM_FAST_REG_GPRE                                                                            0x000400UL //Access:R    DataWidth:0x20  This (indirect) register array of 32 registers provides read-only access of the GPRE registers. Register can be accessed only when storm is stalled.  Chips: BB_A0 BB_B0 K2
7656 #define SEM_FAST_REG_GPRE_SIZE                                                                       32
7657 #define SEM_FAST_REG_GPRE0                                                                           0x000480UL //Access:R    DataWidth:0x10  GPRE0 bits {2'b0; message is ready in passive register file; dra_wr path is not empty; vfc ready;ext_load_rdy; cam ready; dra-empty; thread_err}.  Chips: BB_A0 BB_B0 K2
7658 #define SEM_FAST_REG_STALL_MASK                                                                      0x000484UL //Access:RW   DataWidth:0x13  Provides a vector for enabling/masking the various stall sources from asserting stall.  Chips: BB_A0 BB_B0 K2
7659 #define SEM_FAST_REG_STALL_0                                                                         0x000488UL //Access:RW   DataWidth:0x1   This register is used to define the state of an independent stall source. This is the first of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.  Chips: BB_A0 BB_B0 K2
7660 #define SEM_FAST_REG_STALL_1                                                                         0x00048cUL //Access:RW   DataWidth:0x1   This register is used to define the state of an independent stall source. This is the second of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.  Chips: BB_A0 BB_B0 K2
7661 #define SEM_FAST_REG_STALL_2                                                                         0x000490UL //Access:RW   DataWidth:0x1   This register is used to define the state of an independent stall source. This is the last of three provided via the RBC. The value written to the lsb if this register will define the value it is given. This stall source can be masked independently from the other stall sources.  Chips: BB_A0 BB_B0 K2
7662 #define SEM_FAST_REG_STALLED                                                                         0x000494UL //Access:R    DataWidth:0x1   This register provides a status to indicate whether or not the Storm is currently stalled.  Chips: BB_A0 BB_B0 K2
7663 #define SEM_FAST_REG_STALL_RST                                                                       0x000498UL //Access:W    DataWidth:0x1   Writing this register with any value causes all the internal and external stall sources to be reset, resulting in the negation of the stall signal.  Chips: BB_A0 BB_B0 K2
7664 #define SEM_FAST_REG_STORM_ATTN_STALL_CLR                                                            0x00049cUL //Access:W    DataWidth:0x1   Used to clear the latched storm attention stall signal.  Chips: BB_A0 BB_B0 K2
7665 #define SEM_FAST_REG_STORM_STACK_SIZE                                                                0x0004a0UL //Access:RW   DataWidth:0x4   Defines the size of the Storm stack.  Chips: BB_A0 BB_B0 K2
7666 #define SEM_FAST_REG_PC_BREAKPOINT                                                                   0x0004a4UL //Access:RW   DataWidth:0x10  This register defines the PC breakpoint PRAM address. Anytime the Storm reads from this address while it is executing, it will be stalled.  Chips: BB_A0 BB_B0 K2
7667 #define SEM_FAST_REG_PRAM_PRTY_ADDR_LOW                                                              0x0004a8UL //Access:R    DataWidth:0xf   This register delivers the PRAM address for the low-word instruction that was being read when the most recent PRAM parity error occurred.  Chips: BB_A0 BB_B0 K2
7668 #define SEM_FAST_REG_PRAM_PRTY_ADDR_HIGH                                                             0x0004acUL //Access:R    DataWidth:0xf   This register delivers the PRAM address for the high-word instruction that was being read when the most recent PRAM parity error occurred.  Chips: BB_A0 BB_B0 K2
7669 #define SEM_FAST_REG_PRAM_PRTY_RELEASE                                                               0x0004b0UL //Access:W    DataWidth:0x1   Writing this register with any value causes the PRAM ECC replay logic to be executed and the PRAM parity stall to be released following the reload of the PRAM data path.  Chips: BB_A0 BB_B0 K2
7670 #define SEM_FAST_REG_PRAM_PRTY_INT_CLR                                                               0x0004b4UL //Access:W    DataWidth:0x1   Writing this register with any value causes the PRAM parity error to be cleared.  Chips: BB_A0 BB_B0 K2
7671 #define SEM_FAST_REG_PORT_ID_WIDTH                                                                   0x0004b8UL //Access:RW   DataWidth:0x2   Defines the width of the PortID field as it is extracted from the Opaque FID and presented to the Storm on GPRE8[31:24]. A value of 1 means that the PortID will be taken as a single bit (Intended for BB), a value of 2 means that the PortID will be taken as a 2-bit field (Intended for K2). A value of zero means that the PortID is not extracted and is always assumed to be zero.  Chips: BB_A0 BB_B0 K2
7672 #define SEM_FAST_REG_PORT_ID_OFFSET                                                                  0x0004bcUL //Access:RW   DataWidth:0x5   Defines the offset (in bits) from the lsb of the CID in which to assign to bit-0 of the port ID. I.e. if port_id_wdth is set to 0x1 and port_id_ofset is set to 0x8, then the port ID is assigned from bits [9:8] of the CID.  Chips: BB_A0 BB_B0 K2
7673 #define SEM_FAST_REG_ACTIVE_REG_SET                                                                  0x0004c0UL //Access:R    DataWidth:0x1   Defines the Storm register file set that is currently active.  Chips: BB_A0 BB_B0 K2
7674 #define SEM_FAST_REG_STATE_MACHINE                                                                   0x0004c4UL //Access:R    DataWidth:0x14  State machine bus spelling [vfc_ou_fifo_counter[11:8]; 2'b0; int_state[5:4]; 1'b0; wr_state[2:0}].  Chips: BB_A0 BB_B0 K2
7675 #define SEM_FAST_REG_PRAM_LAST_ADDR                                                                  0x0004c8UL //Access:R    DataWidth:0x20  Last read address from STORM to pram {add_p_out_high; 1'b0; add_p_out_low}.  Chips: BB_A0 BB_B0 K2
7676 #define SEM_FAST_REG_IRAM_ECC_ERROR_INJ                                                              0x0004ccUL //Access:RW   DataWidth:0x7   Writing this register results in internal RAM ECC error injection the next time there is a write to the internal RAM by RBC. For this, any set bit in the data field will result in a corresponding bit inversion in the written data while ECC is calculated according to original data. bit 6 - when set, invert bit on complementary index 4:0. bit 5 - when set, invert bit on index 4:0.                          bits 4:0 - bit inversion index (0-31), Note - When setting only a single bit inversion (only bit 5 or 6 set ), ECC mechanism is expected to fix error. When setting both bit inversion (bits 5 and 6 set), ECC mechanism is expected to only detect error without fix and parity interrupt is expected to be asserted.  Chips: BB_A0 BB_B0 K2
7677 #define SEM_FAST_REG_ECO_RESERVED                                                                    0x0004d0UL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
7678 #define SEM_FAST_REG_STORM_PC                                                                        0x0004d4UL //Access:R    DataWidth:0x10  This register delivers the Storm PC for read-only debug access.  Chips: BB_B0 K2
7679 #define SEM_FAST_REG_RT_CLK_TICK_VALUE                                                               0x000500UL //Access:RW   DataWidth:0x20  This array of indirect registers defines the modulus (roll-over) values for the corresponding real time clocks. The sub-address for this indirect register is the RTC index.  Chips: BB_A0 BB_B0 K2
7680 #define SEM_FAST_REG_RT_CLK_TICK_VALUE_SIZE                                                          10
7681 #define SEM_FAST_REG_RT_CLK_TICK_SRC                                                                 0x000540UL //Access:RW   DataWidth:0x3   Array of ten registers. These are used to select the Storm which is allowed to update the corresponding real-time clock with regard to the associated RTClkTickValue. The Storm decode assignments used for this register are as follows; T-Storm=0; M-Storm=1; U-Storm=2; X-Storm=3; Y-Storm=4; P-Storm=5. The sub-address for this indirect register is the RTC index.  Chips: BB_A0 BB_B0 K2
7682 #define SEM_FAST_REG_RT_CLK_TICK_SRC_SIZE                                                            10
7683 #define SEM_FAST_REG_RT_CLK_INIT_VALUE                                                               0x000580UL //Access:RW   DataWidth:0x20  Array of ten registers. These are used to define the initialization value for each of the real-time clocks. This value is assigned to the corresponding real-time clock only when the Storm corresponding to the value stored in the RTClkInitSrc register makes an RTC update assertion. The sub-address for this indirect register is the RTC index.  Chips: BB_A0 BB_B0 K2
7684 #define SEM_FAST_REG_RT_CLK_INIT_VALUE_SIZE                                                          10
7685 #define SEM_FAST_REG_RT_CLK_INIT_SRC                                                                 0x0005c0UL //Access:RW   DataWidth:0x3   Array of ten registers. These are used to select the Storm which is allowed to initialize the corresponding real-time clock with the value provided by the associated RTClkInitValue register. The Storm decode assignments used for this register are as follows; T-Storm=0; M-Storm=1; U-Storm=2; X-Storm=3; Y-Storm=4; P-Storm=5. The sub-address for this indirect register is the RTC index.  Chips: BB_A0 BB_B0 K2
7686 #define SEM_FAST_REG_RT_CLK_INIT_SRC_SIZE                                                            10
7687 #define SEM_FAST_REG_REAL_TIME_CNT                                                                   0x000600UL //Access:R    DataWidth:0x20  This array of indirect registers provides read/write access to the real time clock values. The sub-address for this indirect register is the RTC index.  Chips: BB_A0 BB_B0 K2
7688 #define SEM_FAST_REG_REAL_TIME_CNT_SIZE                                                              10
7689 #define SEM_FAST_REG_RT_CLK_ENABLE                                                                   0x000628UL //Access:RW   DataWidth:0xa   This register is a vector containing a bit per RTC used to enable each of the ten real-time clocks. The bit index corresponds with the ID of the real-time clock.  Chips: BB_A0 BB_B0 K2
7690 #define SEM_FAST_REG_CAM_MASK_LSB                                                                    0x00062cUL //Access:RW   DataWidth:0x20  The following register assigns bits 31:0 of the CAM mask in preparation for upcoming RBC requested SEARCH and/or ADD commands.  Chips: BB_A0 BB_B0 K2
7691 #define SEM_FAST_REG_CAM_MASK_MIDDLE                                                                 0x000630UL //Access:RW   DataWidth:0x20  The following register assigns bits 63:31 of the CAM mask in preparation for upcoming RBC requested SEARCH and/or ADD commands.  Chips: BB_A0 BB_B0 K2
7692 #define SEM_FAST_REG_CAM_MASK_MSB                                                                    0x000634UL //Access:RW   DataWidth:0x4   The following register assigns bits 67:64 of the CAM mask in preparation for upcoming RBC requested SEARCH and/or ADD commands.  Chips: BB_A0 BB_B0 K2
7693 #define SEM_FAST_REG_CAM_VALUE_LSB                                                                   0x000638UL //Access:RW   DataWidth:0x20  The following register assigns bits 31:0 of the CAM value in preparation for upcoming RBC requested SEARCH, ADD and/or INVALIDATE commands.  Chips: BB_A0 BB_B0 K2
7694 #define SEM_FAST_REG_CAM_VALUE_MIDDLE                                                                0x00063cUL //Access:RW   DataWidth:0x20  The following register assigns bits 63:32 of the CAM value in preparation for upcoming RBC requested SEARCH, ADD and/or INVALIDATE commands.  Chips: BB_A0 BB_B0 K2
7695 #define SEM_FAST_REG_CAM_VALUE_MSB                                                                   0x000640UL //Access:RW   DataWidth:0x4   The following register assigns bits 67:64 of the CAM value in preparation for upcoming RBC requested SEARCH, ADD and/or INVALIDATE commands.  Chips: BB_A0 BB_B0 K2
7696 #define SEM_FAST_REG_CAM_RD_DATA_LSB                                                                 0x000644UL //Access:R    DataWidth:0x20  This register delivers the LSB read data from the CAM for the most recent RBC read request issued. The data returned is defined as follows: cam_rd_data_lsb = cam_rd_data[31:0].  Chips: BB_A0 BB_B0 K2
7697 #define SEM_FAST_REG_CAM_RD_DATA_MIDDLE                                                              0x000648UL //Access:R    DataWidth:0x20  This register delivers middle read data from the CAM for the most recent RBC read request issued. The data returned is defined as follows: cam_rd_data_middle = cam_read_data[63:32].  Chips: BB_A0 BB_B0 K2
7698 #define SEM_FAST_REG_CAM_RD_DATA_MSB                                                                 0x00064cUL //Access:R    DataWidth:0x4   This register delivers the MSB read data from the CAM for the most recent RBC read request issued. The data returned is defined as follows: cam_rd_data_msb[3:0] = cam_read_data[67:64].  Chips: BB_A0 BB_B0 K2
7699 #define SEM_FAST_REG_CAM_VALID                                                                       0x000650UL //Access:R    DataWidth:0x1   This register delivers the valid bit from CAM for the most recent RBC read request issued. The valid bit is returned on bit-0 of the data. All other bits will be zero.  Chips: BB_A0 BB_B0 K2
7700 #define SEM_FAST_REG_CAM_SEARCH                                                                      0x000654UL //Access:R    DataWidth:0x9   This register delivers CAM search response data from CAM for the most recent RBC search request issued. The data returned is defined as follows: cam_search[8] = match, cam_rd_data_msb[6:0] = search_index.  Chips: BB_A0 BB_B0 K2
7701 #define SEM_FAST_REG_CAM_CONTROL                                                                     0x000658UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7702     #define SEM_FAST_REG_CAM_CONTROL_CAM_INIT_EN                                                     (0x1<<0) // Writing a one to this register bit (transition from 0 to 1) causes the entire CAM to be zeroed and all entries to be invalidated.
7703     #define SEM_FAST_REG_CAM_CONTROL_CAM_INIT_EN_SHIFT                                               0
7704     #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_HIT_EN                                                (0x1<<1) // When set, this bit enables hit parity scrubbing on the CAM.
7705     #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_HIT_EN_SHIFT                                          1
7706     #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_MISS_EN                                               (0x1<<2) // When set, this bit enables miss parity scrubbing on the CAM.
7707     #define SEM_FAST_REG_CAM_CONTROL_CAM_SCRUB_MISS_EN_SHIFT                                         2
7708 #define SEM_FAST_REG_CAM_INIT_IN_PROCESS                                                             0x00065cUL //Access:R    DataWidth:0x1   This register is set after the CAM initialization is started (by writing to cam_init) and remains set until the entire CAM initialization is complete.  Chips: BB_A0 BB_B0 K2
7709 #define SEM_FAST_REG_CAM_MATCH_VECTOR                                                                0x000730UL //Access:R    DataWidth:0x20  This array of registers returns the 128-bit CAM match vector returned in the most recent RBC-initiaged search request. For this, cam_match_vector[0] returns bits 31:0 of the vector, cam_match_vector[1] returns bits 63:32, and so on.  Chips: BB_A0 BB_B0 K2
7710 #define SEM_FAST_REG_CAM_MATCH_VECTOR_SIZE                                                           4
7711 #define SEM_FAST_REG_DEBUG_ACTIVE                                                                    0x000740UL //Access:RW   DataWidth:0x1   Used to activate/deactivate the SEMI fast debug, based on the mode defined by the DebugMode register; 0=inactive, 1=active.  Chips: BB_A0 BB_B0 K2
7712 #define SEM_FAST_REG_DEBUG_MODE                                                                      0x000744UL //Access:RW   DataWidth:0x3   Defines the use of the fast debug channel, based on the following enumerations: 0x0-PRINTF; 0x1-PRAM address; 0x2-Reserved; 0x3-DRA read + DRA write; 0x4-load/store address; 0x5-fast DRA state machines; 0x6-recording handler debug; 0x7-Reserved. Note: this register is not applicable when DebugActive=0.  Chips: BB_A0 BB_B0 K2
7713 #define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE                                                          0x000748UL //Access:RW   DataWidth:0x3   Vector used to disable any of the following debug sources for modes 2 and 3 on the fast debug channel: b0-DRA write disable; b1-DRA read disable; b2-interrupt disable.  Chips: BB_A0 BB_B0 K2
7714 #define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE                                                           0x00074cUL //Access:RW   DataWidth:0x2   Vector used to disable any of the following debug sources for mode-4 on the fast debug channel: b0-store data disable; b1-load data disable.  Chips: BB_A0 BB_B0 K2
7715 #define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE                                                           0x000750UL //Access:RW   DataWidth:0x6   Vector used to disable any of the following debug sources for mode-6 on the fast debug channel: b0-dra_in disable; b1-fin disable; b2-load disable; b3-thread start disable; b4-store disable; b5-GPRE read data disable.  Chips: BB_A0 BB_B0 K2
7716 #define SEM_FAST_REG_FILTER_CID                                                                      0x000754UL //Access:RW   DataWidth:0x20  Connection id that should compared with cid field of the data (in Dra-In message); Note: applicable only when FILTER_EN.FILTER_CID_USE_RCVD =0.  Chips: BB_A0 BB_B0 K2
7717 #define SEM_FAST_REG_FILTER_EVENT_ID                                                                 0x000758UL //Access:RW   DataWidth:0x8   Event id that should compared with event id field of the data (in Dra-In message).  Chips: BB_A0 BB_B0 K2
7718 #define SEM_FAST_REG_EVENT_ID_MASK                                                                   0x00075cUL //Access:RW   DataWidth:0x8   Mask for event id. 1- specified bit is ignored; 0 - specified bit is checked.  Chips: BB_A0 BB_B0 K2
7719 #define SEM_FAST_REG_EVENT_ID_RANGE_STRT                                                             0x000760UL //Access:RW   DataWidth:0x8   Used to provide a starting range for the event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active statistics will start with this value.  Chips: BB_A0 BB_B0 K2
7720 #define SEM_FAST_REG_EVENT_ID_RANGE_END                                                              0x000764UL //Access:RW   DataWidth:0x8   Used to provide a ending range for the event ID range filter. A range of event IDs to capture for fast debug mode-6 and for active statistics will end with this value.  Chips: BB_A0 BB_B0 K2
7721 #define SEM_FAST_REG_RECORD_FILTER_ENABLE                                                            0x000768UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7722     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EN                                          (0x3<<0) // (a) 00 - Filter off; in that case all data should be transmitted to the DBG block without any filtering implemented (data should bypass filtering machine).; (b) 01 - Filter on prior to trigger event (asserted by the DBG block) only; When off - data should be transmitted to the DBG block without any filtering. ; (c) 10 - Filter on upon trigger event (asserted by the DBG block) only. When off - data should be transmitted to the DBG block without any filtering.; (d) 11 - Filter on - constant filtering; in this case the triggering event (asserted by the DBG block) is irrelevant.
7723     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EN_SHIFT                                    0
7724     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_RCRD                                    (0x1<<2) // (a) 1 - use the recorded connection id field which arrives from the DBG block (dbg_sem_cid interface) for compariso; NOTE: NA if need to filter connection id prior to trigger event (filter_en=01 OR filter_en=11) as the connection id field which arrives from the DBG block (dbg_sem_cid interface) is valid upon triggering event only; (b) 0 - use the configuration connection id field (filter_cid) for comparison.
7725     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_RCRD_SHIFT                              2
7726     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_EN                                      (0x1<<3) // Used to enable CID/TID filter for recording handlers, when set.
7727     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_CID_EN_SHIFT                                3
7728     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVNT_ID_EN                                  (0x1<<4) // Used to enable Event ID filter for recording handlers, when set.
7729     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVNT_ID_EN_SHIFT                            4
7730     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC                                     (0x3<<5) // Used to define the DRA-In source that should be compared for recording handlers. A value of 0 indicates FIC0; a value of 1 indicates FIC1; a value of 2 indicates passive buffer.
7731     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC_SHIFT                               5
7732     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC_EN                                  (0x1<<7) // Used to enable DRA source filter for recording handlers, when set.
7733     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_DRA_SRC_EN_SHIFT                            7
7734     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVENT_ID_RANGE_EN                           (0x1<<8) // Used to enable filtering based on a range of event IDs rather than "match" filtering. When set, the event ID range is defined by the EventIDRangeStrt and EventIDRangeEnd registers.
7735     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_EVENT_ID_RANGE_EN_SHIFT                     8
7736     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_STORE_EN                                    (0x1<<9) // Used to enable the debug store address filter for fast debug, when set.
7737     #define SEM_FAST_REG_RECORD_FILTER_ENABLE_REC_FILTER_STORE_EN_SHIFT                              9
7738 #define SEM_FAST_REG_DBG_STORE_ADDR_MASK                                                             0x00076cUL //Access:RW   DataWidth:0x10  Used in conjunction with dbg_store_addr_value to filter the store data that is sent through the fast debug channel for all debug modes that transmit store transactions. For all the bits of the mask that are set, then only if the corresponding bits of the store address match dbg_store_addr_value, the transaction will be delivered on the debug mux.  Chips: BB_A0 BB_B0 K2
7739 #define SEM_FAST_REG_DBG_STORE_ADDR_VALUE                                                            0x000770UL //Access:RW   DataWidth:0x10  Used in conjunction with dbg_store_addr_mask to filter the store data that is sent through the fast debug channel for all debug modes that transmit store transactions. For all the bits of dbg_store_addr_mask that are set, then only if the corresponding bits of the store address match the value of this register, the transaction will be delivered on the debug mux.  Chips: BB_A0 BB_B0 K2
7740 #define SEM_FAST_REG_SYNC_DRA_RD_ALM_FULL                                                            0x000840UL //Access:RW   DataWidth:0x6   Almost full for DRA_RD SYNC FIFO.  Chips: BB_A0 BB_B0 K2
7741 #define SEM_FAST_REG_SYNC_RAM_RD_ALM_FULL                                                            0x000844UL //Access:RW   DataWidth:0x5   Almost full for RAM_RD SYNC FIFO.  Chips: BB_A0 BB_B0 K2
7742 #define SEM_FAST_REG_SYNC_EXT_STORE_ALM_FULL                                                         0x000848UL //Access:RW   DataWidth:0x6   Almost full for EXT_STORE SYNC FIFO.  Chips: BB_A0 BB_B0 K2
7743 #define SEM_FAST_REG_DBG_ALM_FULL                                                                    0x00084cUL //Access:RW   DataWidth:0x7   Almost full for DBG SYNC FIFO.  Chips: BB_A0 BB_B0 K2
7744 #define SEM_FAST_REG_FULL                                                                            0x000940UL //Access:R    DataWidth:0xe   Full data spelling : {vfc_out_fifo_full; cam_inp_msb_full; ext_load_rdy; sync_dbg_full; rd_fin_full; sync_wr_pop_full; sync_rd_push_full; sync_fin_full; cam_inp_lsb_full ; cam_inp_msb_full; cam_out_full; sync_ram_rd_full; sync_ram_wr_full; sync_ext_store_full}.  Chips: BB_A0 BB_B0 K2
7745 #define SEM_FAST_REG_EMPTY                                                                           0x000944UL //Access:R    DataWidth:0xd   Empty data spelling;{vfc_out_fifo_empty; cam_inp_msb2_empty; sync_dbg_empty; rd_fin_empty; sync_wr_pop_empty; sync_rd_push_empty; sync_fin_empty; cam_inp_lsb_empty; cam_inp_msb_empty; cam_out_empty; sync_ram_rd_empty; sync_ram_wr_empty; sync_ext_store_empty}.  Chips: BB_A0 BB_B0 K2
7746 #define SEM_FAST_REG_ALM_FULL                                                                        0x000948UL //Access:R    DataWidth:0x2   Alm_full data spelling; {ram_alm_full; ext_alm_full}.  Chips: BB_A0 BB_B0 K2
7747 #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE                                                            0x000a40UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7748     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_CID_EN                                      (0x1<<0) // Used to enable CID/TID filter for Storm active statistics counter, when set.
7749     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_CID_EN_SHIFT                                0
7750     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVNT_ID_EN                                  (0x1<<1) // Used to enable Event ID filter for Storm active statistics counter, when set.
7751     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVNT_ID_EN_SHIFT                            1
7752     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC                                     (0x3<<2) // Used to define the DRA-In source that should be compared for active statistics counter. A value of 0 indicates FIC0; a value of 1 indicates FIC1; a value of 2 indicates passive buffer.
7753     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC_SHIFT                               2
7754     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC_EN                                  (0x1<<4) // Used to enable DRA source filter for Storm active statistics counter, when set.
7755     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_DRA_SRC_EN_SHIFT                            4
7756     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVENT_ID_RANGE_EN                           (0x1<<5) // Used to enable active statistics filtering based on a range of event IDs rather than "match" filtering. When set, the event ID range is defined by the EventIDRangeStrt and EventIDRangeEnd registers.
7757     #define SEM_FAST_REG_ACTIVE_FILTER_ENABLE_ACT_FILTER_EVENT_ID_RANGE_EN_SHIFT                     5
7758 #define SEM_FAST_REG_STORM_ACTIVE_CYCLES                                                             0x000a44UL //Access:R    DataWidth:0x20  Statistics - The accumulated number of Storm cycles in which the Storm has been active (not idle).  Chips: BB_A0 BB_B0 K2
7759 #define SEM_FAST_REG_STALL_CYCLES_MASK                                                               0x000a48UL //Access:RW   DataWidth:0x13  Provides a vector for enabling/masking the various stall sources from contributing to the storm_stall_cycles statistics count.  Chips: BB_A0 BB_B0 K2
7760 #define SEM_FAST_REG_STORM_STALL_CYCLES                                                              0x000a4cUL //Access:R    DataWidth:0x20  Statistics - The accumulated number of Storm cycles in which the Storm has been stalled by the "stall" signal on the load/store bus.  Chips: BB_A0 BB_B0 K2
7761 #define SEM_FAST_REG_IDLE_SLEEPING_CYCLES                                                            0x000a50UL //Access:R    DataWidth:0x20  Statistics - The accumulated number of Storm cycles in which the Storm has been idle due to having no threads to run and one or more threads are allocated in the free-threads list, but are sleeping.  Chips: BB_A0 BB_B0 K2
7762 #define SEM_FAST_REG_IDLE_INACTIVE_CYCLES                                                            0x000a54UL //Access:R    DataWidth:0x20  Statistics - The accumulated number of Storm cycles in which the Storm has been idle due to having no threads to run and no threads are allocated.  Chips: BB_A0 BB_B0 K2
7763 #define SEM_FAST_REG_VFC_DATA_WR                                                                     0x000b40UL //Access:RW   DataWidth:0x20  Command data for VFC. VFC will accumulate all writing to this register till will be done write to vfc_wr_addr.  Chips: BB_A0 BB_B0 K2
7764 #define SEM_FAST_REG_VFC_ADDR                                                                        0x000b44UL //Access:RW   DataWidth:0xc   Command address for VFC. Write to it should be done when all command data was already written to vfc_data_wr register.  Chips: BB_A0 BB_B0 K2
7765 #define SEM_FAST_REG_VFC_DATA_RD                                                                     0x000b48UL //Access:R    DataWidth:0x20  Read data from VFC.  Chips: BB_A0 BB_B0 K2
7766 #define SEM_FAST_REG_VFC_STATUS                                                                      0x000b4cUL //Access:R    DataWidth:0x3   B0 - response is ready. It is set when response cycle of 32 bit is ready from VFC block. It is reset when read is done from vfc_data_rd register; B1 - vfc is busy. It is set when was done write to vfc_addr register. It is reset when last from VFC was received. B2 - sending command is on going. It will be set when was done write to vfc_data_wr register. It will be reset when it was done write to vfc_addr register. New command may be sent from RBC when all 3 bits of this register is reset.  Chips: BB_A0 BB_B0 K2
7767 #define SEM_FAST_REG_CAM_BIST_EN                                                                     0x000c40UL //Access:RW   DataWidth:0x1   Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.  Chips: BB_A0 BB_B0 K2
7768 #define SEM_FAST_REG_CAM_BIST_SKIP_ERROR_CNT                                                         0x000c44UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0 K2
7769 #define SEM_FAST_REG_CAM_BIST_STATUS_SEL                                                             0x000c48UL //Access:RW   DataWidth:0x8   Used to select the BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.  Chips: BB_A0 BB_B0 K2
7770 #define SEM_FAST_REG_CAM_BIST_STATUS                                                                 0x000c4cUL //Access:R    DataWidth:0x20  Provides read-only access to the BIST status word selected by cam_bist_status_sel.  Chips: BB_A0 BB_B0 K2
7771 #define SEM_FAST_REG_MEMCTRL_WR_RD_N                                                                 0x000cc0UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
7772 #define SEM_FAST_REG_MEMCTRL_CMD                                                                     0x000cc4UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
7773 #define SEM_FAST_REG_MEMCTRL_ADDRESS                                                                 0x000cc8UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
7774 #define SEM_FAST_REG_MEMCTRL_STATUS                                                                  0x000cccUL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0
7775 #define SEM_FAST_REG_STORM_REG_FILE                                                                  0x008000UL //Access:R    DataWidth:0x20  Register file memories. If address lsb=0=>read from bits 31:0; otherway from bits 63:32. Upper bit selects the RF. Used only for debugging.  Chips: BB_A0 BB_B0 K2
7776 #define SEM_FAST_REG_STORM_REG_FILE_SIZE                                                             512
7777 #define SEM_FAST_REG_CAM_REQUEST                                                                     0x009000UL //Access:RW   DataWidth:0x4   Writing this indirect register will cause a CAM command to be executed with the CAM offset specified by the indirect register sub-address. Bits [3:0] of the data bus provide the OpCode for the request where the following numerations apply: 0x0=ADD, 0x1=SRCH, 0x2=INVALIDATE, 0x3=READ. Reading this register returns the OpCode of the most recent RBC-initiated CAM request.  Chips: BB_A0 BB_B0 K2
7778 #define SEM_FAST_REG_CAM_REQUEST_SIZE                                                                256
7779 #define SEM_FAST_REG_VFC_CONFIG                                                                      0x00a000UL //Access:RW   DataWidth:0x20  Provides a memory-mapped region for VFC configurations; up to 256 registers.  Chips: BB_A0 BB_B0 K2
7780 #define SEM_FAST_REG_VFC_CONFIG_SIZE                                                                 256
7781 #define SEM_FAST_REG_INT_RAM                                                                         0x020000UL //Access:RW   DataWidth:0x20  Internal RAM (if bit lsb of addr =0 => write to bits[31:0; otherwise to [63:32).  Chips: BB_A0 BB_B0 K2
7782 #define SEM_FAST_REG_INT_RAM_SIZE                                                                    20480
7783 #define VFC_REG_MASK_LSB_0_LOW                                                                       0x000000UL //Access:RW   DataWidth:0x20  Bits [31:0] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.  Chips: BB_A0 BB_B0 K2
7784 #define VFC_REG_MASK_LSB_0_HIGH                                                                      0x000004UL //Access:RW   DataWidth:0x20  Bits [63:32] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.  Chips: BB_A0 BB_B0 K2
7785 #define VFC_REG_MASK_LSB_1_LOW                                                                       0x000008UL //Access:RW   DataWidth:0x20  Bits [31:0] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.  Chips: BB_A0 BB_B0 K2
7786 #define VFC_REG_MASK_LSB_1_HIGH                                                                      0x00000cUL //Access:RW   DataWidth:0x20  Bits [63:32] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.  Chips: BB_A0 BB_B0 K2
7787 #define VFC_REG_MASK_LSB_2_LOW                                                                       0x000010UL //Access:RW   DataWidth:0x20  Bits [31:0] for vector CAM mask that are used for search and add commands.1 means the corresponding data bit should be compared and 0 means it should be ignored.  Chips: BB_A0 BB_B0 K2
7788 #define VFC_REG_MASK_LSB_2_HIGH                                                                      0x000014UL //Access:RW   DataWidth:0x20  Bits [31:0] for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.  Chips: BB_A0 BB_B0 K2
7789 #define VFC_REG_MASK_LSB_3_LOW                                                                       0x000018UL //Access:RW   DataWidth:0x20  Bits [111:96] bits for vector CAM mask that are used for search and add commands.1 means the corresponding data bit should be compared and 0 means it should be ignored.  Chips: BB_A0 BB_B0 K2
7790 #define VFC_REG_MASK_LSB_3_HIGH                                                                      0x00001cUL //Access:RW   DataWidth:0x20  Bits [63:32]  for vector CAM mask that are used for search and add commands. 1 means the corresponding data bit should be compared and 0 means it should be ignored.  Chips: BB_A0 BB_B0 K2
7791 #define VFC_REG_ALU_RST_EN                                                                           0x000020UL //Access:RW   DataWidth:0x8   This register includes bit per ALU vector: 0-4 long vectors; 5-11 short vectors. When it is set then appropriate vector will be reset when RST bit is set in request.  Chips: BB_A0 BB_B0 K2
7792 #define VFC_REG_TT_RESULT_EN                                                                         0x000024UL //Access:RW   DataWidth:0x1   This register defines value that will be written to DSt vector for analyze operation. If it is set to 1, then row from target table will be rwitten. If it is set to 0, then row from target table OR previous value of DST vector will be written.  Chips: BB_A0 BB_B0 K2
7793 #define VFC_REG_INTERRUPT_IND                                                                        0x000028UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7794     #define VFC_REG_INTERRUPT_IND_ADDRESS_INTERRUPT                                                  (0x1<<0) // This is error interrupt. It may be asserted when it was access to not existing address in VFC. Also it will be asserted when there is attempt to write to read only register. It will be de-asserted aftre write 1 to it.
7795     #define VFC_REG_INTERRUPT_IND_ADDRESS_INTERRUPT_SHIFT                                            0
7796     #define VFC_REG_INTERRUPT_IND_INP_FIFO_ITERRUPT                                                  (0x1<<1) // This is error interrupt. It may be asserted when it was input FIFO overflow.
7797     #define VFC_REG_INTERRUPT_IND_INP_FIFO_ITERRUPT_SHIFT                                            1
7798     #define VFC_REG_INTERRUPT_IND_LEN_FIFO_INTERRUPT                                                 (0x1<<2) // This is error interrupt. It may be asserted when it was length FIFO overflow.
7799     #define VFC_REG_INTERRUPT_IND_LEN_FIFO_INTERRUPT_SHIFT                                           2
7800     #define VFC_REG_INTERRUPT_IND_INP_BUF_INTERRUPT                                                  (0x1<<3) // This is error interrupt. It may be asserted when it was input buffers overflow.
7801     #define VFC_REG_INTERRUPT_IND_INP_BUF_INTERRUPT_SHIFT                                            3
7802     #define VFC_REG_INTERRUPT_IND_OUT_BUF_INTERRUPT                                                  (0x1<<4) // This is error interrupt. It may be asserted when it was output buffer overflow.
7803     #define VFC_REG_INTERRUPT_IND_OUT_BUF_INTERRUPT_SHIFT                                            4
7804     #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT                                                 (0x1<<5) // This is error interrupt. It may be asserted when it was address overflow of INFO part of RSS RAM. It will be de-asserted aftre write 1 to it.
7805     #define VFC_REG_INTERRUPT_IND_RSS_INFO_INTERRUPT_SHIFT                                           5
7806     #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT                                              (0x1<<6) // This is error interrupt. It may be asserted when it was address overflow of KEY LSB part of RSS RAM.   It will be de-asserted aftre write 1 to it.
7807     #define VFC_REG_INTERRUPT_IND_RSS_KEY_LSB_INTERRUPT_SHIFT                                        6
7808     #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT                                              (0x1<<7) // This is error interrupt. It may be asserted when it was address overflow of KEY MSB part of RSS RAM. It will be de-asserted aftre write 1 to it.
7809     #define VFC_REG_INTERRUPT_IND_RSS_KEY_MSB_INTERRUPT_SHIFT                                        7
7810     #define VFC_REG_INTERRUPT_IND_RBC_WRITE_INTERRUPT                                                (0x1<<8) // This is error interrupt. It may be asserted when it was RBC command with address not equal to 12 bit or data cycle not equal 64 bit or number of data cycles bigger than 6.  It will be de-asserted aftre write 1 to it.
7811     #define VFC_REG_INTERRUPT_IND_RBC_WRITE_INTERRUPT_SHIFT                                          8
7812     #define VFC_REG_INTERRUPT_IND_DEADLOCK_INTERRUPT                                                 (0x1<<9) // This is error interrupt. It may be asserted when waitp is asserted and output FIFO is also full.  It will be de-asserted aftre write 1 to it.
7813     #define VFC_REG_INTERRUPT_IND_DEADLOCK_INTERRUPT_SHIFT                                           9
7814 #define VFC_REG_PARITY_IND                                                                           0x00002cUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7815     #define VFC_REG_PARITY_IND_RSS_RAM_PARITY                                                        (0x1<<0) // This is parity interrupt. It may be asserted when it was RSS RAM parity error.  It will be de-asserted aftre write 1 to it.
7816     #define VFC_REG_PARITY_IND_RSS_RAM_PARITY_SHIFT                                                  0
7817     #define VFC_REG_PARITY_IND_CAM_PARITY                                                            (0x1<<1) // This is parity interrupt. It may be asserted when it was CAM parity error. It will be de-asserted aftre write 1 to it.
7818     #define VFC_REG_PARITY_IND_CAM_PARITY_SHIFT                                                      1
7819     #define VFC_REG_PARITY_IND_TT_RAM_PARITY                                                         (0x1<<2) // This is parity interrupt. It may be asserted when it was parity error inside TT RAM. It will be de-asserted aftre write 1 to it.
7820     #define VFC_REG_PARITY_IND_TT_RAM_PARITY_SHIFT                                                   2
7821 #define VFC_REG_INDICATIONS1                                                                         0x000030UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
7822     #define VFC_REG_INDICATIONS1_INP_FIFO_EMPTY                                                      (0x1<<0) // Empty indication from input FIFO.
7823     #define VFC_REG_INDICATIONS1_INP_FIFO_EMPTY_SHIFT                                                0
7824     #define VFC_REG_INDICATIONS1_LEN_FIFO_EMPTY                                                      (0x1<<1) // Empty indication from length command FIFO.
7825     #define VFC_REG_INDICATIONS1_LEN_FIFO_EMPTY_SHIFT                                                1
7826     #define VFC_REG_INDICATIONS1_INP_BUF_EMPTY                                                       (0x1<<2) // Empty indication from input buffers.
7827     #define VFC_REG_INDICATIONS1_INP_BUF_EMPTY_SHIFT                                                 2
7828     #define VFC_REG_INDICATIONS1_OUT_FIFO_EMPTY                                                      (0x1<<3) // Empty indication from output FIFO.
7829     #define VFC_REG_INDICATIONS1_OUT_FIFO_EMPTY_SHIFT                                                3
7830     #define VFC_REG_INDICATIONS1_SEM_FIFO_EMPTY                                                      (0x1<<4) // Empty indication from SEM output FIFO inside VFC.
7831     #define VFC_REG_INDICATIONS1_SEM_FIFO_EMPTY_SHIFT                                                4
7832     #define VFC_REG_INDICATIONS1_RESERVED1_1                                                         (0x7<<5) // Reserved bits.
7833     #define VFC_REG_INDICATIONS1_RESERVED1_1_SHIFT                                                   5
7834     #define VFC_REG_INDICATIONS1_INP_FIFO_FULL                                                       (0x1<<8) // Full indication from input FIFO.
7835     #define VFC_REG_INDICATIONS1_INP_FIFO_FULL_SHIFT                                                 8
7836     #define VFC_REG_INDICATIONS1_LEN_FIFO_FULL                                                       (0x1<<9) // Full indication from length command FIFO.
7837     #define VFC_REG_INDICATIONS1_LEN_FIFO_FULL_SHIFT                                                 9
7838     #define VFC_REG_INDICATIONS1_INP_BUF_FULL                                                        (0x1<<10) // Full indication from input buffers.
7839     #define VFC_REG_INDICATIONS1_INP_BUF_FULL_SHIFT                                                  10
7840     #define VFC_REG_INDICATIONS1_OUT_FIFO_FULL                                                       (0x1<<11) // Full indication from output FIFO.
7841     #define VFC_REG_INDICATIONS1_OUT_FIFO_FULL_SHIFT                                                 11
7842     #define VFC_REG_INDICATIONS1_SEM_FIFO_FULL                                                       (0x1<<12) // Full indication from SEM output FIFO inside VFC.
7843     #define VFC_REG_INDICATIONS1_SEM_FIFO_FULL_SHIFT                                                 12
7844     #define VFC_REG_INDICATIONS1_RESERVED1_2                                                         (0x7<<13) // Reserved bits.
7845     #define VFC_REG_INDICATIONS1_RESERVED1_2_SHIFT                                                   13
7846     #define VFC_REG_INDICATIONS1_RBC_RSP_RDY                                                         (0x1<<16) // Indicates if RBC response is ready.
7847     #define VFC_REG_INDICATIONS1_RBC_RSP_RDY_SHIFT                                                   16
7848     #define VFC_REG_INDICATIONS1_VFC_WAITP                                                           (0x1<<17) // Indicates if waitp from VFC to STORM is asserted.
7849     #define VFC_REG_INDICATIONS1_VFC_WAITP_SHIFT                                                     17
7850 #define VFC_REG_INDICATIONS2                                                                         0x000034UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
7851     #define VFC_REG_INDICATIONS2_INP_FIFO_CNT                                                        (0x1f<<0) // Number of entries inside input memory FIFO.
7852     #define VFC_REG_INDICATIONS2_INP_FIFO_CNT_SHIFT                                                  0
7853     #define VFC_REG_INDICATIONS2_RESERVED2_1                                                         (0x7<<5) // Reserved bits.
7854     #define VFC_REG_INDICATIONS2_RESERVED2_1_SHIFT                                                   5
7855     #define VFC_REG_INDICATIONS2_LEN_FIFO_CNT                                                        (0x1f<<8) // Number of entries inside length command FIFO.
7856     #define VFC_REG_INDICATIONS2_LEN_FIFO_CNT_SHIFT                                                  8
7857     #define VFC_REG_INDICATIONS2_RESERVED2_2                                                         (0x7<<13) // Reserved bits.
7858     #define VFC_REG_INDICATIONS2_RESERVED2_2_SHIFT                                                   13
7859     #define VFC_REG_INDICATIONS2_INP_BUF_CNT                                                         (0xf<<16) // Number of entries inside buffers of input FIFO.
7860     #define VFC_REG_INDICATIONS2_INP_BUF_CNT_SHIFT                                                   16
7861     #define VFC_REG_INDICATIONS2_OUT_BUF_CNT                                                         (0xf<<20) // Number of entries inside output FIFO.
7862     #define VFC_REG_INDICATIONS2_OUT_BUF_CNT_SHIFT                                                   20
7863     #define VFC_REG_INDICATIONS2_SEM_FIFO_CNT                                                        (0xf<<24) // Number of entries inside SEMI output FIFO inside VFC.
7864     #define VFC_REG_INDICATIONS2_SEM_FIFO_CNT_SHIFT                                                  24
7865 #define VFC_REG_SW_RST                                                                               0x000038UL //Access:W    DataWidth:0x1   Write to this bit will cause to block reset.  Chips: BB_A0 BB_B0 K2
7866 #define VFC_REG_MEMORIES_RST                                                                         0x00003cUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7867     #define VFC_REG_MEMORIES_RST_CAM_RST                                                             (0x1<<0) // Write 1 to this bit will cause reset of all CAM rows including valid bit and all bits in a row. Write 0 to it will have no effect. Read 1 from this bit means that CAM reset was finished. Read 0 from this bit means that CAM reset was never done or not finished.
7868     #define VFC_REG_MEMORIES_RST_CAM_RST_SHIFT                                                       0
7869     #define VFC_REG_MEMORIES_RST_RAM_RST                                                             (0x1<<1) // Write 1 to this bit will cause reset of all RSS RAM rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset is in progress. Read 0 from this bit means that RAM reset was finished.
7870     #define VFC_REG_MEMORIES_RST_RAM_RST_SHIFT                                                       1
7871     #define VFC_REG_MEMORIES_RST_TT_RST                                                              (0x1<<2) // Write 1 to this bit will cause reset of all Target tables rows. Write 0 to it will have no effect. Read 1 from this bit means that RAM reset was finished. Read 1 from this bit means that TT RAM reset is in progress. Read 0 from this bit means that TT RAM reset was finished.
7872     #define VFC_REG_MEMORIES_RST_TT_RST_SHIFT                                                        2
7873 #define VFC_REG_CAM_PARITY_EN                                                                        0x000040UL //Access:RW   DataWidth:0x1   REQUIRED -If this bit is set then background mechanism for parity check will be enabled; 0 - disabled. This bit must be disabled in palladium and FPGA. Init value of 1 must be done in a chip mode  Chips: BB_A0 BB_B0 K2
7874 #define VFC_REG_CAM_CLK_DIVIDER                                                                      0x000044UL //Access:RW   DataWidth:0x4   Cam clock divider : may be equal to 2 only.  Chips: BB_A0 BB_B0 K2
7875 #define VFC_REG_PARITY_MASK                                                                          0x000048UL //Access:RW   DataWidth:0x3   REQUIRED - 0 - parity is enabled;1 parity check is disabled.  Chips: BB_A0 BB_B0 K2
7876 #define VFC_REG_INTERRUPT_MASK                                                                       0x00004cUL //Access:RW   DataWidth:0xa   REQUIRED - 0 - interrupt is enabled;1- interrupt check is disabled.  Chips: BB_A0 BB_B0 K2
7877 #define VFC_REG_RSS_RAM_TM_0                                                                         0x000050UL //Access:RW   DataWidth:0x5   TM indication for RSS RAM instance 0.  Chips: BB_A0 BB_B0 K2
7878 #define VFC_REG_RSS_RAM_TM_1                                                                         0x000054UL //Access:RW   DataWidth:0x5   TM indication for RSS RAM instance 1.  Chips: BB_A0 BB_B0 K2
7879 #define VFC_REG_INP_FIFO_TM                                                                          0x000058UL //Access:RW   DataWidth:0x2   TM indication for Input fifo.  Chips: BB_A0 BB_B0 K2
7880 #define VFC_REG_CAM_TM                                                                               0x00005cUL //Access:RW   DataWidth:0x14  TM indication for CAM.  Chips: BB_A0 BB_B0 K2
7881 #define VFC_REG_VFC_CAM_BIST_EN                                                                      0x000060UL //Access:RW   DataWidth:0x1   Bist enable bit for Cam.  Chips: BB_A0 BB_B0 K2
7882 #define VFC_REG_VFC_CAM_BIST_DBG_SEL                                                                 0x000064UL //Access:RW   DataWidth:0x8   This select the type of data present on bist_status bus (slixe or status select).  Chips: BB_A0 BB_B0 K2
7883 #define VFC_REG_VFC_CAM_BIST_STATUS                                                                  0x000068UL //Access:R    DataWidth:0x20  This returns the bist_status which can be done/go/sX_status.  Chips: BB_A0 BB_B0 K2
7884 #define VFC_REG_KEY_RSS_EXT5                                                                         0x00006cUL //Access:RW   DataWidth:0x8   Key extension for 5th tuple.  Chips: BB_A0 BB_B0 K2
7885 #define VFC_REG_INP_FIFO_ALM_FULL                                                                    0x000070UL //Access:RW   DataWidth:0x5   Almost full for input FIFO. When number of entries inside input FIFO is bigger or equal to this number then waitp to STORM will be asserted.  Chips: BB_A0 BB_B0 K2
7886 #define VFC_REG_STORM_CMD_DISABLE                                                                    0x000074UL //Access:RW   DataWidth:0x1   When set then it disables selecting of commands from STORM. It will allow for RBC to configurate block. STORM command may be executed when this bit will be deasserted.  Chips: BB_A0 BB_B0 K2
7887 #define VFC_REG_WAITP_STAT                                                                           0x000078UL //Access:RC   DataWidth:0x20  Statistics for number of cycles when waitp was raised to STORM as a result of full input FIFO. This vector will be reset after reading from it. It is also possible to write to it.  Chips: BB_A0 BB_B0 K2
7888 #define VFC_REG_ECO_RESERVED                                                                         0x00007cUL //Access:RW   DataWidth:0x20  Unused bits for future eco.  Chips: BB_A0 BB_B0 K2
7889 #define VFC_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD                                                        0x000080UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0 K2
7890 #define VFC_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD                                                        0x000084UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0 K2
7891 #define VFC_REG_DEBUG_DATA                                                                           0x000090UL //Access:R    DataWidth:0x1e  Multi Field Register.  Chips: BB_A0 BB_B0 K2
7892     #define VFC_REG_DEBUG_DATA_CURRENT_MSG_LEN                                                       (0x7<<0) // Length of VFC command from STORM that is waitinf for arbitration.
7893     #define VFC_REG_DEBUG_DATA_CURRENT_MSG_LEN_SHIFT                                                 0
7894     #define VFC_REG_DEBUG_DATA_CUR_MSG_EMPTY                                                         (0x1<<3) // Empty indication for current message that has first cycle from STORM.
7895     #define VFC_REG_DEBUG_DATA_CUR_MSG_EMPTY_SHIFT                                                   3
7896     #define VFC_REG_DEBUG_DATA_MEXT_MSG_LEN                                                          (0x7<<4) // Length of next VFC command from STORM that will be selected after current message.
7897     #define VFC_REG_DEBUG_DATA_MEXT_MSG_LEN_SHIFT                                                    4
7898     #define VFC_REG_DEBUG_DATA_NEXT_MSG_EMPTY                                                        (0x1<<7) // Next message ready indication that has first cycle fro mSTORM.
7899     #define VFC_REG_DEBUG_DATA_NEXT_MSG_EMPTY_SHIFT                                                  7
7900     #define VFC_REG_DEBUG_DATA_RBC_CNT                                                               (0xff<<8) // Number of transactions from SEM_PD for last RBC command.
7901     #define VFC_REG_DEBUG_DATA_RBC_CNT_SHIFT                                                         8
7902     #define VFC_REG_DEBUG_DATA_STORM_READY                                                           (0x1<<16) // Ready indication from STORM to input arbiter.
7903     #define VFC_REG_DEBUG_DATA_STORM_READY_SHIFT                                                     16
7904     #define VFC_REG_DEBUG_DATA_RBC_READY                                                             (0x1<<17) // Ready indication from RBC to input arbiter.
7905     #define VFC_REG_DEBUG_DATA_RBC_READY_SHIFT                                                       17
7906     #define VFC_REG_DEBUG_DATA_RESERVED2                                                             (0x3<<18) // This field is set to 0.
7907     #define VFC_REG_DEBUG_DATA_RESERVED2_SHIFT                                                       18
7908     #define VFC_REG_DEBUG_DATA_LAST_MATCH_ADDR                                                       (0x3ff<<20) // Last match address that will be used for analyze operation.
7909     #define VFC_REG_DEBUG_DATA_LAST_MATCH_ADDR_SHIFT                                                 20
7910 #define VFC_REG_STORM_CMD_ADDR                                                                       0x000094UL //Access:R    DataWidth:0xc   Address of command from STORM that is waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7911 #define VFC_REG_STORM_CMD_DATA_0                                                                     0x000098UL //Access:R    DataWidth:0x20  Data bits[31:0] of VFC command from STORM that are waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7912 #define VFC_REG_STORM_CMD_DATA_1                                                                     0x00009cUL //Access:R    DataWidth:0x20  Data bits[63:32] of VFC command from STORM that are waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7913 #define VFC_REG_STORM_CMD_DATA_2                                                                     0x0000a0UL //Access:R    DataWidth:0x20  Data bits[95:64] of VFC command from STORM that are waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7914 #define VFC_REG_STORM_CMD_DATA_3                                                                     0x0000a4UL //Access:R    DataWidth:0x20  Data bits[127:96] of VFC command from STORM that are waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7915 #define VFC_REG_STORM_CMD_DATA_4                                                                     0x0000a8UL //Access:R    DataWidth:0x20  Data bits[159:128] of VFC command from STORM that are waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7916 #define VFC_REG_STORM_CMD_DATA_5                                                                     0x0000acUL //Access:R    DataWidth:0x20  Data bits[191:160] of VFC command from STORM that are waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7917 #define VFC_REG_STORM_CMD_DATA_6                                                                     0x0000b0UL //Access:R    DataWidth:0x20  Data bits[223:192] of VFC command from STORM that are waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7918 #define VFC_REG_STORM_CMD_DATA_7                                                                     0x0000b4UL //Access:R    DataWidth:0x20  Data bits[255:224] of VFC command from STORM that are waiting for arbitration.  Chips: BB_A0 BB_B0 K2
7919 #define VFC_REG_MASK_LSB_4_LOW                                                                       0x0000b8UL //Access:RW   DataWidth:0x20  Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.  Chips: BB_A0 BB_B0 K2
7920 #define VFC_REG_MASK_LSB_4_HIGH                                                                      0x0000bcUL //Access:RW   DataWidth:0x20  Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.  Chips: BB_A0 BB_B0 K2
7921 #define VFC_REG_MASK_LSB_5_LOW                                                                       0x0000c0UL //Access:RW   DataWidth:0x20  Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.  Chips: BB_A0 BB_B0 K2
7922 #define VFC_REG_MASK_LSB_5_HIGH                                                                      0x0000c4UL //Access:RW   DataWidth:0x20  Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.  Chips: BB_A0 BB_B0 K2
7923 #define VFC_REG_MASK_LSB_6_LOW                                                                       0x0000c8UL //Access:RW   DataWidth:0x20  Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.  Chips: BB_A0 BB_B0 K2
7924 #define VFC_REG_MASK_LSB_6_HIGH                                                                      0x0000ccUL //Access:RW   DataWidth:0x20  Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.  Chips: BB_A0 BB_B0 K2
7925 #define VFC_REG_MASK_LSB_7_LOW                                                                       0x0000d0UL //Access:RW   DataWidth:0x20  Bits [31:0] of data for search optimized operation that will be used when M field equals to 0.  Chips: BB_A0 BB_B0 K2
7926 #define VFC_REG_MASK_LSB_7_HIGH                                                                      0x0000d4UL //Access:RW   DataWidth:0x20  Bits [63:32] of data for search optimized operation that will be used when M field equals to 0.  Chips: BB_A0 BB_B0 K2
7927 #define VFC_REG_OFFSET_ALU_VECTOR_0                                                                  0x0000f8UL //Access:R    DataWidth:0x9   Last analyze offset for ALU vector 0.  Chips: BB_A0 BB_B0 K2
7928 #define VFC_REG_OFFSET_ALU_VECTOR_1                                                                  0x0000fcUL //Access:R    DataWidth:0x9   Last analyze offset for ALU vector 1.  Chips: BB_A0 BB_B0 K2
7929 #define VFC_REG_OFFSET_ALU_VECTOR_2                                                                  0x000100UL //Access:R    DataWidth:0x9   Last analyze offset for ALU vector 2.  Chips: BB_A0 BB_B0 K2
7930 #define VFC_REG_OFFSET_ALU_VECTOR_3                                                                  0x000104UL //Access:R    DataWidth:0x9   Last analyze offset for ALU vector 3.  Chips: BB_A0 BB_B0 K2
7931 #define VFC_REG_OFFSET_ALU_VECTOR_4                                                                  0x000108UL //Access:R    DataWidth:0x9   Last analyze offset for ALU vector 4.  Chips: BB_A0 BB_B0 K2
7932 #define VFC_REG_OFFSET_ALU_VECTOR_5                                                                  0x00010cUL //Access:R    DataWidth:0x9   Last analyze offset for ALU vector 5.  Chips: BB_A0 BB_B0 K2
7933 #define VFC_REG_OFFSET_ALU_VECTOR_6                                                                  0x000110UL //Access:R    DataWidth:0x9   Last analyze offset for ALU vector 6.  Chips: BB_A0 BB_B0 K2
7934 #define VFC_REG_OFFSET_ALU_VECTOR_7                                                                  0x000114UL //Access:R    DataWidth:0x9   Last analyze offset for ALU vector 7.  Chips: BB_A0 BB_B0 K2
7935 #define VFC_REG_PORT4_MODE_EN                                                                        0x000118UL //Access:RW   DataWidth:0x1   If this bit set to 0 then allows to work with 160 clients. If set to 1 then with 208.  Chips: BB_A0 BB_B0 K2
7936 #define VFC_REG_INP_FIFO_DBG_RD_EN                                                                   0x00011cUL //Access:RW   DataWidth:0x1   Input FIFO debug enable.  Chips: BB_A0 BB_B0 K2
7937 #define VFC_REG_INP_FIFO_DBG_RD_ADD                                                                  0x000120UL //Access:RW   DataWidth:0x4   Input FIFO debug address.  Chips: BB_A0 BB_B0 K2
7938 #define VFC_REG_CAM_BIST_SKIP_ERROR_CNT                                                              0x000124UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0 K2
7939 #define VFC_REG_PRTY_MASK_H_0                                                                        0x000204UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7940     #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
7941     #define VFC_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT                                          0
7942     #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
7943     #define VFC_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT                                          1
7944     #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
7945     #define VFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                            2
7946     #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
7947     #define VFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            3
7948     #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
7949     #define VFC_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            4
7950     #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
7951     #define VFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            5
7952     #define VFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: VFC_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
7953     #define VFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                            2
7954 #define VFC_REG_MEM_ECC_EVENTS                                                                       0x00021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
7955 #define VFC_REG_MEM006_I_MEM_DFT_K2                                                                  0x000224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance vfc.i_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
7956 #define VFC_REG_MEM001_I_MEM_DFT_K2                                                                  0x000228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance vfc.VFC_RSS_RAM_K2_GEN_IF.i_rss_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
7957 #define VFC_REG_MEM005_I_MEM_DFT_K2                                                                  0x00022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_tt1_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
7958 #define VFC_REG_MEM002_I_MEM_DFT_K2                                                                  0x000230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_mtt2_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
7959 #define VFC_REG_MEM004_I_MEM_DFT_K2                                                                  0x000234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_stt2_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
7960 #define VFC_REG_MEM003_I_MEM_DFT_K2                                                                  0x000238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance vfc.VFC_TT_RAMS_K2_GEN_IF.i_ro_vec.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
7961 #define PB_REG_INT_STS                                                                               0x000040UL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7962     #define PB_REG_INT_STS_ADDRESS_ERROR                                                             (0x1<<0) // Signals an unknown address to the rf module.
7963     #define PB_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                       0
7964     #define PB_REG_INT_STS_EOP_ERROR                                                                 (0x1<<1) // EOP check error.
7965     #define PB_REG_INT_STS_EOP_ERROR_SHIFT                                                           1
7966     #define PB_REG_INT_STS_IFIFO_ERROR                                                               (0x1<<2) // Instruction FIFO error.
7967     #define PB_REG_INT_STS_IFIFO_ERROR_SHIFT                                                         2
7968     #define PB_REG_INT_STS_PFIFO_ERROR                                                               (0x1<<3) // Parameter FIFO error.
7969     #define PB_REG_INT_STS_PFIFO_ERROR_SHIFT                                                         3
7970     #define PB_REG_INT_STS_DB_BUF_ERROR                                                              (0x1<<4) // DB FIFO error.
7971     #define PB_REG_INT_STS_DB_BUF_ERROR_SHIFT                                                        4
7972     #define PB_REG_INT_STS_TH_EXEC_ERROR                                                             (0x1<<5) //
7973     #define PB_REG_INT_STS_TH_EXEC_ERROR_SHIFT                                                       5
7974     #define PB_REG_INT_STS_TQ_ERROR_WR                                                               (0x1<<6) // TQ write overflow.
7975     #define PB_REG_INT_STS_TQ_ERROR_WR_SHIFT                                                         6
7976     #define PB_REG_INT_STS_TQ_ERROR_RD_TH                                                            (0x1<<7) // TQ read underflow by task handler.
7977     #define PB_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT                                                      7
7978     #define PB_REG_INT_STS_TQ_ERROR_RD_IH                                                            (0x1<<8) // TQ read underflow by instruction handler.
7979     #define PB_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT                                                      8
7980 #define PB_REG_INT_MASK                                                                              0x000044UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
7981     #define PB_REG_INT_MASK_ADDRESS_ERROR                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
7982     #define PB_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                      0
7983     #define PB_REG_INT_MASK_EOP_ERROR                                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
7984     #define PB_REG_INT_MASK_EOP_ERROR_SHIFT                                                          1
7985     #define PB_REG_INT_MASK_IFIFO_ERROR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
7986     #define PB_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                        2
7987     #define PB_REG_INT_MASK_PFIFO_ERROR                                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
7988     #define PB_REG_INT_MASK_PFIFO_ERROR_SHIFT                                                        3
7989     #define PB_REG_INT_MASK_DB_BUF_ERROR                                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
7990     #define PB_REG_INT_MASK_DB_BUF_ERROR_SHIFT                                                       4
7991     #define PB_REG_INT_MASK_TH_EXEC_ERROR                                                            (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
7992     #define PB_REG_INT_MASK_TH_EXEC_ERROR_SHIFT                                                      5
7993     #define PB_REG_INT_MASK_TQ_ERROR_WR                                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
7994     #define PB_REG_INT_MASK_TQ_ERROR_WR_SHIFT                                                        6
7995     #define PB_REG_INT_MASK_TQ_ERROR_RD_TH                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
7996     #define PB_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT                                                     7
7997     #define PB_REG_INT_MASK_TQ_ERROR_RD_IH                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
7998     #define PB_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT                                                     8
7999 #define PB_REG_INT_STS_WR                                                                            0x000048UL //Access:WR   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
8000     #define PB_REG_INT_STS_WR_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
8001     #define PB_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                    0
8002     #define PB_REG_INT_STS_WR_EOP_ERROR                                                              (0x1<<1) // EOP check error.
8003     #define PB_REG_INT_STS_WR_EOP_ERROR_SHIFT                                                        1
8004     #define PB_REG_INT_STS_WR_IFIFO_ERROR                                                            (0x1<<2) // Instruction FIFO error.
8005     #define PB_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                      2
8006     #define PB_REG_INT_STS_WR_PFIFO_ERROR                                                            (0x1<<3) // Parameter FIFO error.
8007     #define PB_REG_INT_STS_WR_PFIFO_ERROR_SHIFT                                                      3
8008     #define PB_REG_INT_STS_WR_DB_BUF_ERROR                                                           (0x1<<4) // DB FIFO error.
8009     #define PB_REG_INT_STS_WR_DB_BUF_ERROR_SHIFT                                                     4
8010     #define PB_REG_INT_STS_WR_TH_EXEC_ERROR                                                          (0x1<<5) //
8011     #define PB_REG_INT_STS_WR_TH_EXEC_ERROR_SHIFT                                                    5
8012     #define PB_REG_INT_STS_WR_TQ_ERROR_WR                                                            (0x1<<6) // TQ write overflow.
8013     #define PB_REG_INT_STS_WR_TQ_ERROR_WR_SHIFT                                                      6
8014     #define PB_REG_INT_STS_WR_TQ_ERROR_RD_TH                                                         (0x1<<7) // TQ read underflow by task handler.
8015     #define PB_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT                                                   7
8016     #define PB_REG_INT_STS_WR_TQ_ERROR_RD_IH                                                         (0x1<<8) // TQ read underflow by instruction handler.
8017     #define PB_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT                                                   8
8018 #define PB_REG_INT_STS_CLR                                                                           0x00004cUL //Access:RC   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
8019     #define PB_REG_INT_STS_CLR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
8020     #define PB_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                   0
8021     #define PB_REG_INT_STS_CLR_EOP_ERROR                                                             (0x1<<1) // EOP check error.
8022     #define PB_REG_INT_STS_CLR_EOP_ERROR_SHIFT                                                       1
8023     #define PB_REG_INT_STS_CLR_IFIFO_ERROR                                                           (0x1<<2) // Instruction FIFO error.
8024     #define PB_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                     2
8025     #define PB_REG_INT_STS_CLR_PFIFO_ERROR                                                           (0x1<<3) // Parameter FIFO error.
8026     #define PB_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT                                                     3
8027     #define PB_REG_INT_STS_CLR_DB_BUF_ERROR                                                          (0x1<<4) // DB FIFO error.
8028     #define PB_REG_INT_STS_CLR_DB_BUF_ERROR_SHIFT                                                    4
8029     #define PB_REG_INT_STS_CLR_TH_EXEC_ERROR                                                         (0x1<<5) //
8030     #define PB_REG_INT_STS_CLR_TH_EXEC_ERROR_SHIFT                                                   5
8031     #define PB_REG_INT_STS_CLR_TQ_ERROR_WR                                                           (0x1<<6) // TQ write overflow.
8032     #define PB_REG_INT_STS_CLR_TQ_ERROR_WR_SHIFT                                                     6
8033     #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_TH                                                        (0x1<<7) // TQ read underflow by task handler.
8034     #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT                                                  7
8035     #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_IH                                                        (0x1<<8) // TQ read underflow by instruction handler.
8036     #define PB_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT                                                  8
8037 #define PB_REG_PRTY_MASK                                                                             0x000054UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
8038     #define PB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                      (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
8039     #define PB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                                0
8040 #define PB_REG_CONTROL                                                                               0x000400UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
8041     #define PB_REG_CONTROL_BYTE_ORDER_SWITCH                                                         (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
8042     #define PB_REG_CONTROL_BYTE_ORDER_SWITCH_SHIFT                                                   0
8043     #define PB_REG_CONTROL_DB_IGNORE_ERROR                                                           (0x1<<1) // Indicates if to ignore the input error indication.
8044     #define PB_REG_CONTROL_DB_IGNORE_ERROR_SHIFT                                                     1
8045     #define PB_REG_CONTROL_DONT_PASS_ERROR                                                           (0x1<<2) // Masks error on output of pb.
8046     #define PB_REG_CONTROL_DONT_PASS_ERROR_SHIFT                                                     2
8047     #define PB_REG_CONTROL_EOP_CHECK_DISABLE                                                         (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
8048     #define PB_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT                                                   3
8049     #define PB_REG_CONTROL_CRC_COMPARE_DISABLE                                                       (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
8050     #define PB_REG_CONTROL_CRC_COMPARE_DISABLE_SHIFT                                                 4
8051     #define PB_REG_CONTROL_EN_INPUTS                                                                 (0x1<<5) // Enable inputs.
8052     #define PB_REG_CONTROL_EN_INPUTS_SHIFT                                                           5
8053     #define PB_REG_CONTROL_DISABLE_PB                                                                (0x1<<6) // Debug only: Disable PB.
8054     #define PB_REG_CONTROL_DISABLE_PB_SHIFT                                                          6
8055     #define PB_REG_CONTROL_DEBUG_SELECT                                                              (0xf<<7) // Obsolete.
8056     #define PB_REG_CONTROL_DEBUG_SELECT_SHIFT                                                        7
8057     #define PB_REG_CONTROL_RELAX_TH                                                                  (0x1<<11) // Dbug only.
8058     #define PB_REG_CONTROL_RELAX_TH_SHIFT                                                            11
8059     #define PB_REG_CONTROL_DUMMY_ERR_ALLOW                                                           (0x1<<12) // Dummy ingress error allow.  When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
8060     #define PB_REG_CONTROL_DUMMY_ERR_ALLOW_SHIFT                                                     12
8061 #define PB_REG_CRC_MASK_1_0                                                                          0x000404UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8062 #define PB_REG_CRC_MASK_1_1                                                                          0x000408UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8063 #define PB_REG_CRC_MASK_1_2                                                                          0x00040cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8064 #define PB_REG_CRC_MASK_1_3                                                                          0x000410UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8065 #define PB_REG_CRC_MASK_2_0                                                                          0x000414UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8066 #define PB_REG_CRC_MASK_2_1                                                                          0x000418UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8067 #define PB_REG_CRC_MASK_2_2                                                                          0x00041cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8068 #define PB_REG_CRC_MASK_2_3                                                                          0x000420UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8069 #define PB_REG_CRC_MASK_3_0                                                                          0x000424UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8070 #define PB_REG_CRC_MASK_3_1                                                                          0x000428UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8071 #define PB_REG_CRC_MASK_3_2                                                                          0x00042cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8072 #define PB_REG_CRC_MASK_3_3                                                                          0x000430UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
8073 #define PB_REG_DB_EMPTY                                                                              0x000500UL //Access:R    DataWidth:0x1   Data Buffer empty status.  Chips: BB_A0 BB_B0 K2
8074 #define PB_REG_DB_FULL                                                                               0x000504UL //Access:R    DataWidth:0x1   Data Buffer full status.  Chips: BB_A0 BB_B0 K2
8075 #define PB_REG_TQ_EMPTY                                                                              0x000508UL //Access:R    DataWidth:0x1   Task Queue empty status.  Chips: BB_A0 BB_B0 K2
8076 #define PB_REG_TQ_FULL                                                                               0x00050cUL //Access:R    DataWidth:0x1   Task Queue full status.  Chips: BB_A0 BB_B0 K2
8077 #define PB_REG_IFIFO_EMPTY                                                                           0x000510UL //Access:R    DataWidth:0x1   Instruction FIFO empty status.  Chips: BB_A0 BB_B0 K2
8078 #define PB_REG_IFIFO_FULL                                                                            0x000514UL //Access:R    DataWidth:0x1   Instruction FIFO full status.  Chips: BB_A0 BB_B0 K2
8079 #define PB_REG_PFIFO_EMPTY                                                                           0x000518UL //Access:R    DataWidth:0x1   Parameter FIFO empty status.  Chips: BB_A0 BB_B0 K2
8080 #define PB_REG_PFIFO_FULL                                                                            0x00051cUL //Access:R    DataWidth:0x1   Parameter FIFO full status.  Chips: BB_A0 BB_B0 K2
8081 #define PB_REG_TQ_TH_EMPTY                                                                           0x000520UL //Access:R    DataWidth:0x1   Task Queue empty status for task handler.  Chips: BB_A0 BB_B0 K2
8082 #define PB_REG_ERRORED_CRC                                                                           0x000600UL //Access:R    DataWidth:0x20  CRC mismatch debug register.  This register stores the calculated CRC value that resulted in the most recent CRC error event.  Chips: BB_A0 BB_B0 K2
8083 #define PB_REG_ERRORED_INSTR                                                                         0x000604UL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the instruction being executed at the time EOP error is detected. The instruction is aligned with the least significant bit of this register.  Bits 31:29 provide additional information about the instruction.  Bit 31 indicates whether the instruction is valid.  Bit 30 indicates if the instruction is the first instruction in the task.  Bit 29 indicates whether the instruction is the last instruction in the task.  Chips: BB_A0 BB_B0 K2
8084 #define PB_REG_ERRORED_HDR_LOW                                                                       0x000608UL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the lower 32 bits of the task header being executed at the time EOP error is detected.  The instruction length is not kept and is read as 0.  Chips: BB_A0 BB_B0 K2
8085 #define PB_REG_ERRORED_HDR_HIGH                                                                      0x00060cUL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the upper 32 bits of the task header being executed at the time EOP error is detected.  The task passthrough bit is not kept and is read as 0.  Chips: BB_A0 BB_B0 K2
8086 #define PB_REG_ERRORED_LENGTH                                                                        0x000610UL //Access:R    DataWidth:0x10  EOP mismatch debug register.  This register provides the number of data bytes remaining to be read from DB at the time of EOP error detection.  Chips: BB_A0 BB_B0 K2
8087 #define PB_REG_ECO_RESERVED                                                                          0x000614UL //Access:RW   DataWidth:0x8   For future eco.  Chips: BB_A0 BB_B0 K2
8088 #define PB_REG_DBG_OUT_DATA                                                                          0x000700UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
8089 #define PB_REG_DBG_OUT_DATA_SIZE                                                                     8
8090 #define PB_REG_DBG_OUT_VALID                                                                         0x000720UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
8091 #define PB_REG_DBG_OUT_FRAME                                                                         0x000724UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
8092 #define PB_REG_DBG_SELECT                                                                            0x000728UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
8093 #define PB_REG_DBG_DWORD_ENABLE                                                                      0x00072cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
8094 #define PB_REG_DBG_SHIFT                                                                             0x000730UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
8095 #define PB_REG_DBG_FORCE_VALID                                                                       0x000734UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
8096 #define PB_REG_DBG_FORCE_FRAME                                                                       0x000738UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
8097 #define PB_REG_DB_FIFO                                                                               0x002000UL //Access:WB_R DataWidth:0x108 Provides read-only access of the data buffer FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
8098 #define PB_REG_DB_FIFO_SIZE                                                                          512
8099 #define PB_REG_L1                                                                                    0x003000UL //Access:WB   DataWidth:0x40  L1 CRC memory access.  Chips: BB_A0 BB_B0 K2
8100 #define PB_REG_L1_SIZE                                                                               640
8101 #define ETH_MAC_REG_REVISION                                                                         0x000000UL //Access:R    DataWidth:0x20  Package defined constants  Chips: K2
8102     #define ETH_MAC_REG_REVISION_CORE_REVISION                                                       (0xff<<0) // 8-bit value from package parameter CORE_REVISION
8103     #define ETH_MAC_REG_REVISION_CORE_REVISION_SHIFT                                                 0
8104     #define ETH_MAC_REG_REVISION_CORE_VERSION                                                        (0xff<<8) // 8-bit value from package parameter CORE_VERSION
8105     #define ETH_MAC_REG_REVISION_CORE_VERSION_SHIFT                                                  8
8106     #define ETH_MAC_REG_REVISION_CUSTOMER_REVISION                                                   (0xffff<<16) // Programmable Customer Revision from package parameter CUST_REVISION
8107     #define ETH_MAC_REG_REVISION_CUSTOMER_REVISION_SHIFT                                             16
8108 #define ETH_MAC_REG_SCRATCH                                                                          0x000004UL //Access:RW   DataWidth:0x20  General Purpose  Chips: K2
8109 #define ETH_MAC_REG_COMMAND_CONFIG                                                                   0x000008UL //Access:RW   DataWidth:0x20  Control and Configuration  Chips: K2
8110     #define ETH_MAC_REG_COMMAND_CONFIG_TX_ENA                                                        (0x1<<0) // MAC Transmit Path Enable. Should be set to '1' to enable the MAC transmit path, should be set to '0' (Reset value) to disable the MAC transmit path.
8111     #define ETH_MAC_REG_COMMAND_CONFIG_TX_ENA_SHIFT                                                  0
8112     #define ETH_MAC_REG_COMMAND_CONFIG_RX_ENA                                                        (0x1<<1) // MAC Receive Path Enable. Should be set to '1' to enable the MAC receive path, should be set to '0' (Reset value) to disable the MAC receive path.
8113     #define ETH_MAC_REG_COMMAND_CONFIG_RX_ENA_SHIFT                                                  1
8114     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV2                                                    (0x1<<2) // reserved
8115     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV2_SHIFT                                              2
8116     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV3                                                    (0x1<<3) // reserved
8117     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV3_SHIFT                                              3
8118     #define ETH_MAC_REG_COMMAND_CONFIG_PROMIS_EN                                                     (0x1<<4) // Enable MAC Promiscuous Operation. If set to '1', all frames are received without any MAC address filtering. If set to '0' (Reset value), Unicast frames with a destination address not matching the Core MAC address (programmed in registers MAC_ADDR_0 and MAC_ADDR_1) are rejected.
8119     #define ETH_MAC_REG_COMMAND_CONFIG_PROMIS_EN_SHIFT                                               4
8120     #define ETH_MAC_REG_COMMAND_CONFIG_PAD_EN                                                        (0x1<<5) // reserved, write 0 always. (MAC never removes padding)
8121     #define ETH_MAC_REG_COMMAND_CONFIG_PAD_EN_SHIFT                                                  5
8122     #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD                                                       (0x1<<6) // Terminate / Forward Received CRC. If set to '1', the CRC field of received frames is forwarded with the frame to the user application. If set to '0' (Reset value), the CRC field is stripped from the frame. Note - If padding (Bit PAD_EN set to ?1?) is enabled, CRC_FWD is ignored.
8123     #define ETH_MAC_REG_COMMAND_CONFIG_CRC_FWD_SHIFT                                                 6
8124     #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_FWD                                                     (0x1<<7) // Terminate / Forward Pause Frames. If set to '1', pause frames are forwarded to the user application. If set to '0' (Reset value), pause frames are terminated and discarded within the MAC.
8125     #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_FWD_SHIFT                                               7
8126     #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_IGNORE                                                  (0x1<<8) // Ignore received Pause frame quanta. If set to '1', received pause frames are ignored by the MAC. If set to '0' (Reset value), the transmit process is stopped for the amount of time specified in the pause quanta received within a pause frame.
8127     #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_IGNORE_SHIFT                                            8
8128     #define ETH_MAC_REG_COMMAND_CONFIG_TX_ADDR_INS                                                   (0x1<<9) // Set Source MAC Address on Transmit. If set to '1', the MAC overwrites the source MAC address received from the client interface with the MAC address programmed in registers MAC_ADDR_0 and MAC_ADDR_1 . If set to '0' (Reset value), the source MAC address from the client interface is transmitted unmodified to the line.
8129     #define ETH_MAC_REG_COMMAND_CONFIG_TX_ADDR_INS_SHIFT                                             9
8130     #define ETH_MAC_REG_COMMAND_CONFIG_LOOPBACK_EN                                                   (0x1<<10) // Enable PHY Interface loopback. If set to '1', the signal loop_ena is set to '1'. If set to '0' (Reset value), the signal loop_ena is set to '0'.
8131     #define ETH_MAC_REG_COMMAND_CONFIG_LOOPBACK_EN_SHIFT                                             10
8132     #define ETH_MAC_REG_COMMAND_CONFIG_TX_PAD_EN                                                     (0x1<<11) // reserved, writable but has no effect. The MAC never appends padding octets; the user application must provide frames of correct minimum size.
8133     #define ETH_MAC_REG_COMMAND_CONFIG_TX_PAD_EN_SHIFT                                               11
8134     #define ETH_MAC_REG_COMMAND_CONFIG_SW_RESET                                                      (0x1<<12) // Self-Clearing Software Reset. When written with '1', all Statistics Counters are reset to 0.
8135     #define ETH_MAC_REG_COMMAND_CONFIG_SW_RESET_SHIFT                                                12
8136     #define ETH_MAC_REG_COMMAND_CONFIG_CNTL_FRAME_ENA                                                (0x1<<13) // Enable Reception of all Control Frames. If set to '1', all control frames are accepted. If set to '0', only Pause frames are accepted and all other command frames are rejected.
8137     #define ETH_MAC_REG_COMMAND_CONFIG_CNTL_FRAME_ENA_SHIFT                                          13
8138     #define ETH_MAC_REG_COMMAND_CONFIG_RX_ERR_DISC                                                   (0x1<<14) // Enable Receive Errored Frame Discard. Use only with RX FIFO Store and Forward. May not be supported by all Core variants.
8139     #define ETH_MAC_REG_COMMAND_CONFIG_RX_ERR_DISC_SHIFT                                             14
8140     #define ETH_MAC_REG_COMMAND_CONFIG_PHY_TXENA                                                     (0x1<<15) // Controls toplevel pin phy_txena. No internal function
8141     #define ETH_MAC_REG_COMMAND_CONFIG_PHY_TXENA_SHIFT                                               15
8142     #define ETH_MAC_REG_COMMAND_CONFIG_SEND_IDLE                                                     (0x1<<16) // Force Idle Generation. If set to '1', the MAC permanently sends XLGMII Idle sequences even when faults are received.
8143     #define ETH_MAC_REG_COMMAND_CONFIG_SEND_IDLE_SHIFT                                               16
8144     #define ETH_MAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK                                                 (0x1<<17) // Disable Payload Length Check. Not supported; write 0 always.
8145     #define ETH_MAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK_SHIFT                                           17
8146     #define ETH_MAC_REG_COMMAND_CONFIG_RS_COL_CNT_EXT                                                (0x1<<18) // reserved
8147     #define ETH_MAC_REG_COMMAND_CONFIG_RS_COL_CNT_EXT_SHIFT                                          18
8148     #define ETH_MAC_REG_COMMAND_CONFIG_PFC_MODE                                                      (0x1<<19) // Priority Flow Control Mode enable. If set to 1, the Core generates and processes PFC control frames according to the Priority Flow Control Interface signals. If set to 0 (Reset Value), the Core operates in legacy Pause Frame mode and generates and processes standard Pause Frames.
8149     #define ETH_MAC_REG_COMMAND_CONFIG_PFC_MODE_SHIFT                                                19
8150     #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_PFC_COMP                                                (0x1<<20) // Link Pause compatible with PFC mode. Pause is only indicated but does not stop TX.
8151     #define ETH_MAC_REG_COMMAND_CONFIG_PAUSE_PFC_COMP_SHIFT                                          20
8152     #define ETH_MAC_REG_COMMAND_CONFIG_RX_SFD_ANY                                                    (0x1<<21) // Disable check for SFD (0xd5) and accept frame with any character.
8153     #define ETH_MAC_REG_COMMAND_CONFIG_RX_SFD_ANY_SHIFT                                              21
8154     #define ETH_MAC_REG_COMMAND_CONFIG_TX_FLUSH                                                      (0x1<<22) // Egress flush enable.
8155     #define ETH_MAC_REG_COMMAND_CONFIG_TX_FLUSH_SHIFT                                                22
8156     #define ETH_MAC_REG_COMMAND_CONFIG_TX_LOWP_ENA                                                   (0x1<<23) // Instruct RS Layer to transmit LPI.
8157     #define ETH_MAC_REG_COMMAND_CONFIG_TX_LOWP_ENA_SHIFT                                             23
8158     #define ETH_MAC_REG_COMMAND_CONFIG_LOWP_RXEMPTY                                                  (0x1<<24) // Mask toplevel pin reg_lowp with RX FIFO empty.
8159     #define ETH_MAC_REG_COMMAND_CONFIG_LOWP_RXEMPTY_SHIFT                                            24
8160     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV25                                                   (0x1<<25) // reserved
8161     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV25_SHIFT                                             25
8162     #define ETH_MAC_REG_COMMAND_CONFIG_TX_FIFO_RESET                                                 (0x1<<26) // Self-Clearing TX FIFO reset command. May not be supported in all Core variants
8163     #define ETH_MAC_REG_COMMAND_CONFIG_TX_FIFO_RESET_SHIFT                                           26
8164     #define ETH_MAC_REG_COMMAND_CONFIG_FLT_HDL_DIS                                                   (0x1<<27) // Disable RS fault handling. When set to '0' (default), the MAC automatically inserts remote faults and idles in egress direction on detection of local faults and remote faults, respectively, on ingress direction. When set to '1', this feature is disabled.
8165     #define ETH_MAC_REG_COMMAND_CONFIG_FLT_HDL_DIS_SHIFT                                             27
8166     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV28                                                   (0x1<<28) // reserved
8167     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV28_SHIFT                                             28
8168     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV29                                                   (0x1<<29) // reserved
8169     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV29_SHIFT                                             29
8170     #define ETH_MAC_REG_COMMAND_CONFIG_SHORT_PREAMBLE                                                (0x1<<30) // reserved; write 0 always
8171     #define ETH_MAC_REG_COMMAND_CONFIG_SHORT_PREAMBLE_SHIFT                                          30
8172     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV31                                                   (0x1<<31) // reserved
8173     #define ETH_MAC_REG_COMMAND_CONFIG_MACCC_RSV31_SHIFT                                             31
8174 #define ETH_MAC_REG_MAC_ADDR_0                                                                       0x00000cUL //Access:RW   DataWidth:0x20  First 4 bytes of MAC address  Chips: K2
8175 #define ETH_MAC_REG_MAC_ADDR_1                                                                       0x000010UL //Access:RW   DataWidth:0x20  Last 2 bytes of MAC address  Chips: K2
8176     #define ETH_MAC_REG_MAC_ADDR_1_MAC_ADDRESS_1                                                     (0xffff<<0) // Last 2 bytes: 5th is 7:0, 6th is 15:8
8177     #define ETH_MAC_REG_MAC_ADDR_1_MAC_ADDRESS_1_SHIFT                                               0
8178     #define ETH_MAC_REG_MAC_ADDR_1_UNUSED_0                                                          (0xffff<<16) // reserved
8179     #define ETH_MAC_REG_MAC_ADDR_1_UNUSED_0_SHIFT                                                    16
8180 #define ETH_MAC_REG_FRM_LENGTH                                                                       0x000014UL //Access:RW   DataWidth:0x20  Maximum Frame Size  Chips: K2
8181     #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH                                                        (0xffff<<0) // Maximum Frame Size
8182     #define ETH_MAC_REG_FRM_LENGTH_FRM_LENGTH_SHIFT                                                  0
8183     #define ETH_MAC_REG_FRM_LENGTH_TX_MTU                                                            (0xffff<<16) // Optional maximum frame size setting for transmit statistics use if it should be different from receive statistics. When set to 0 the FRM_LENGTH value is used (i.e. statistics symmetric for TX and RX).
8184     #define ETH_MAC_REG_FRM_LENGTH_TX_MTU_SHIFT                                                      16
8185 #define ETH_MAC_REG_RX_FIFO_SECTIONS                                                                 0x00001cUL //Access:RW   DataWidth:0x20  RX FIFO thresholds  Chips: K2
8186     #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL                                             (0xffff<<0) // RX section full threshold
8187     #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_FULL_SHIFT                                       0
8188     #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_EMPTY                                            (0xffff<<16) // RX section empty threshold
8189     #define ETH_MAC_REG_RX_FIFO_SECTIONS_RX_SECTION_EMPTY_SHIFT                                      16
8190 #define ETH_MAC_REG_TX_FIFO_SECTIONS                                                                 0x000020UL //Access:RW   DataWidth:0x20  TX FIFO thresholds  Chips: K2
8191     #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL                                             (0xffff<<0) // TX section full threshold
8192     #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_FULL_SHIFT                                       0
8193     #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY                                            (0xffff<<16) // TX section empty threshold
8194     #define ETH_MAC_REG_TX_FIFO_SECTIONS_TX_SECTION_EMPTY_SHIFT                                      16
8195 #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E                                                               0x000024UL //Access:R    DataWidth:0x20  Not configurable  Chips: K2
8196     #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_EMPTY                                      (0xffff<<0) // RX FIFO almost empty threshold
8197     #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_EMPTY_SHIFT                                0
8198     #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_FULL                                       (0xffff<<16) // RX FIFO almost full threshold
8199     #define ETH_MAC_REG_RX_FIFO_ALMOST_F_E_RX_FIFO_ALMOST_FULL_SHIFT                                 16
8200 #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E                                                               0x000028UL //Access:R    DataWidth:0x20  Not configurable  Chips: K2
8201     #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_EMPTY                                      (0xffff<<0) // TX FIFO almost empty threshold
8202     #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_EMPTY_SHIFT                                0
8203     #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_FULL                                       (0xffff<<16) // TX FIFO almost full threshold
8204     #define ETH_MAC_REG_TX_FIFO_ALMOST_F_E_TX_FIFO_ALMOST_FULL_SHIFT                                 16
8205 #define ETH_MAC_REG_HASHTABLE_LOAD                                                                   0x00002cUL //Access:RW   DataWidth:0x20  reserved; register is writeable bits 8,4:0 but have no effect.  Chips: K2
8206     #define ETH_MAC_REG_HASHTABLE_LOAD_HASH_TABLE_ADDRESS                                            (0x1f<<0) // 0 specify the hash table address (code)
8207     #define ETH_MAC_REG_HASHTABLE_LOAD_HASH_TABLE_ADDRESS_SHIFT                                      0
8208     #define ETH_MAC_REG_HASHTABLE_LOAD_UNUSED_0                                                      (0x7<<5) // reserved
8209     #define ETH_MAC_REG_HASHTABLE_LOAD_UNUSED_0_SHIFT                                                5
8210     #define ETH_MAC_REG_HASHTABLE_LOAD_ENABLE_MULTICAST_FRAME                                        (0x1<<8) // enables (1) or disables (0) multicast frame reception for the entry.
8211     #define ETH_MAC_REG_HASHTABLE_LOAD_ENABLE_MULTICAST_FRAME_SHIFT                                  8
8212     #define ETH_MAC_REG_HASHTABLE_LOAD_UNUSED_1                                                      (0x7fffff<<9) // reserved
8213     #define ETH_MAC_REG_HASHTABLE_LOAD_UNUSED_1_SHIFT                                                9
8214 #define ETH_MAC_REG_MDIO_CFG_STATUS                                                                  0x000030UL //Access:RW   DataWidth:0x20  MDIO Configuration and Status  Chips: K2
8215     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_BUSY                                                    (0x1<<0) // MDIO busy. If set, a MDIO transaction is currently ongoing. If cleared, the application can access the other registers.
8216     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_BUSY_SHIFT                                              0
8217     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_READ_ERROR                                              (0x1<<1) // MDIO read error. If set, the last read transaction had no response from a PHY and the data read could be invalid. This can happen, if the PHY address does not match any PHY that is available on the MDIO bus.
8218     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_READ_ERROR_SHIFT                                        1
8219     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_HOLD_TIME_SETTING                                       (0x7<<2) // MDIO hold time setting (reg_clk cycles).
8220     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_HOLD_TIME_SETTING_SHIFT                                 2
8221     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_DISABLE_PREAMBLE                                        (0x1<<5) // MDIO transaction preamble disable. Shortens transaction but is non-standard.
8222     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_DISABLE_PREAMBLE_SHIFT                                  5
8223     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLAUSE45                                                (0x1<<6) // MDIO transaction use Clause 45 format (1) or Clause 22 format (0).
8224     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLAUSE45_SHIFT                                          6
8225     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLOCK_DIVISOR                                           (0x1ff<<7) // MDIO clock divisor; A value of 5 to 511. The frequency is reg_clk/(2*divisor+1). The reset default is defined by the synthesis package setting MDIO_CLK_DIV. Setting the divisor to 0 disables MDC.
8226     #define ETH_MAC_REG_MDIO_CFG_STATUS_MDIO_CLOCK_DIVISOR_SHIFT                                     7
8227     #define ETH_MAC_REG_MDIO_CFG_STATUS_UNUSED_0                                                     (0xffff<<16) // reserved
8228     #define ETH_MAC_REG_MDIO_CFG_STATUS_UNUSED_0_SHIFT                                               16
8229 #define ETH_MAC_REG_MDIO_COMMAND                                                                     0x000034UL //Access:RW   DataWidth:0x20  MDIO Command (PHY and Port Address)  Chips: K2
8230     #define ETH_MAC_REG_MDIO_COMMAND_DEVICE_ADDRESS                                                  (0x1f<<0) // Device Address
8231     #define ETH_MAC_REG_MDIO_COMMAND_DEVICE_ADDRESS_SHIFT                                            0
8232     #define ETH_MAC_REG_MDIO_COMMAND_PORT_ADDRESS                                                    (0x1f<<5) // Port Address
8233     #define ETH_MAC_REG_MDIO_COMMAND_PORT_ADDRESS_SHIFT                                              5
8234     #define ETH_MAC_REG_MDIO_COMMAND_UNUSED_0                                                        (0xf<<10) // reserved
8235     #define ETH_MAC_REG_MDIO_COMMAND_UNUSED_0_SHIFT                                                  10
8236     #define ETH_MAC_REG_MDIO_COMMAND_READ_ADDRESS_POST_INCREMENT                                     (0x1<<14) // If written with 1, a read with address post-increment will be performed. Post-increment will be performed in the PHY internal address register.
8237     #define ETH_MAC_REG_MDIO_COMMAND_READ_ADDRESS_POST_INCREMENT_SHIFT                               14
8238     #define ETH_MAC_REG_MDIO_COMMAND_NORMAL_READ_TRANSACTION                                         (0x1<<15) // If written with 1, a normal read transaction is initiated.
8239     #define ETH_MAC_REG_MDIO_COMMAND_NORMAL_READ_TRANSACTION_SHIFT                                   15
8240     #define ETH_MAC_REG_MDIO_COMMAND_UNUSED_1                                                        (0xffff<<16) // reserved
8241     #define ETH_MAC_REG_MDIO_COMMAND_UNUSED_1_SHIFT                                                  16
8242 #define ETH_MAC_REG_MDIO_DATA                                                                        0x000038UL //Access:RW   DataWidth:0x20  MDIO Data to write and last Data read  Chips: K2
8243     #define ETH_MAC_REG_MDIO_DATA_MDIO_DATA                                                          (0xffff<<0) // 16-bit data word. When written- Initiates a write transaction to the PHY. The MDIO_COMMAND register must have been initialized. The busy status bit will be set immediately and cleared when the write transaction has finished. When read - Returns the data read from the PHY register after a read transaction has been completed (initiated by writing a 1 to Bit 15 or Bit 14 of the MDIO_COMMAND register).
8244     #define ETH_MAC_REG_MDIO_DATA_MDIO_DATA_SHIFT                                                    0
8245     #define ETH_MAC_REG_MDIO_DATA_UNUSED_0                                                           (0xffff<<16) // reserved
8246     #define ETH_MAC_REG_MDIO_DATA_UNUSED_0_SHIFT                                                     16
8247 #define ETH_MAC_REG_MDIO_REGADDR                                                                     0x00003cUL //Access:W    DataWidth:0x20  MDIO Register Address. Address of register within the PHY device to read from or write to. After writing this register, an address-write transaction will be initiated to set the PHY internal address register to the value given.  Chips: K2
8248     #define ETH_MAC_REG_MDIO_REGADDR_MDIO_REGADDR                                                    (0xffff<<0) // The MDIO_COMMAND register must have been initialized before the first write to this register.
8249     #define ETH_MAC_REG_MDIO_REGADDR_MDIO_REGADDR_SHIFT                                              0
8250     #define ETH_MAC_REG_MDIO_REGADDR_UNUSED_0                                                        (0xffff<<16) // reserved
8251     #define ETH_MAC_REG_MDIO_REGADDR_UNUSED_0_SHIFT                                                  16
8252 #define ETH_MAC_REG_STATUS                                                                           0x000040UL //Access:RW   DataWidth:0x20  General Purpose Status  Chips: K2
8253     #define ETH_MAC_REG_STATUS_RX_LOC_FAULT                                                          (0x1<<0) // Local Fault Status. Set to '1' when the MAC detects Rx Local Fault Sequences on the CGMII receive interface.
8254     #define ETH_MAC_REG_STATUS_RX_LOC_FAULT_SHIFT                                                    0
8255     #define ETH_MAC_REG_STATUS_RX_REM_FAULT                                                          (0x1<<1) // Remote Fault Status. Set to '1' when the MAC detects Rx Remote Fault Sequences on the CGMII receive interface
8256     #define ETH_MAC_REG_STATUS_RX_REM_FAULT_SHIFT                                                    1
8257     #define ETH_MAC_REG_STATUS_PHY_LOS                                                               (0x1<<2) // PHY indicates loss-of-signal. Represents value of pin "phy_los".
8258     #define ETH_MAC_REG_STATUS_PHY_LOS_SHIFT                                                         2
8259     #define ETH_MAC_REG_STATUS_TS_AVAIL                                                              (0x1<<3) // Transmit Timestamp Available. Indicates that the timestamp of the last transmitted 1588 event frame is available in the register TS_TIMESTAMP.  To clear TS_AVAIL, the bit must be written with a '1'.
8260     #define ETH_MAC_REG_STATUS_TS_AVAIL_SHIFT                                                        3
8261     #define ETH_MAC_REG_STATUS_RX_LOWP                                                               (0x1<<4) // Receiving Low Power Idle (LPI)
8262     #define ETH_MAC_REG_STATUS_RX_LOWP_SHIFT                                                         4
8263     #define ETH_MAC_REG_STATUS_TX_EMPTY                                                              (0x1<<5) // TX FIFO is empty
8264     #define ETH_MAC_REG_STATUS_TX_EMPTY_SHIFT                                                        5
8265     #define ETH_MAC_REG_STATUS_RX_EMPTY                                                              (0x1<<6) // RX FIFO is empty
8266     #define ETH_MAC_REG_STATUS_RX_EMPTY_SHIFT                                                        6
8267     #define ETH_MAC_REG_STATUS_RX_LINT_FAULT                                                         (0x1<<7) // Special Link Interruption Fault Sequence detected in receive
8268     #define ETH_MAC_REG_STATUS_RX_LINT_FAULT_SHIFT                                                   7
8269     #define ETH_MAC_REG_STATUS_TX_IS_IDLE                                                            (0x1<<8) // TX MAC datapath (statemachine) is idle
8270     #define ETH_MAC_REG_STATUS_TX_IS_IDLE_SHIFT                                                      8
8271     #define ETH_MAC_REG_STATUS_UNUSED_0                                                              (0x7fffff<<9) // reserved
8272     #define ETH_MAC_REG_STATUS_UNUSED_0_SHIFT                                                        9
8273 #define ETH_MAC_REG_TX_IPG_LENGTH                                                                    0x000044UL //Access:RW   DataWidth:0x20  TX InterPacketGap configuration  Chips: K2
8274     #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG                                                          (0x7f<<0) // Number of octets in steps of 4 (XGMII) or 8 (XLGMII). Minimum 8. Value 12 should be set for compliant operation.
8275     #define ETH_MAC_REG_TX_IPG_LENGTH_TXIPG_SHIFT                                                    0
8276     #define ETH_MAC_REG_TX_IPG_LENGTH_UNUSED_0                                                       (0x1ff<<7) // reserved
8277     #define ETH_MAC_REG_TX_IPG_LENGTH_UNUSED_0_SHIFT                                                 7
8278     #define ETH_MAC_REG_TX_IPG_LENGTH_COMPENSATION                                                   (0xffff<<16) // Compensation for PCS inserted markers. Depending on PCS type a value of 16383 (40G) or 20479 (25/50G) must be set.
8279     #define ETH_MAC_REG_TX_IPG_LENGTH_COMPENSATION_SHIFT                                             16
8280 #define ETH_MAC_REG_CREDIT_TRIGGER                                                                   0x000048UL //Access:RW   DataWidth:0x20  reserved  Chips: K2
8281     #define ETH_MAC_REG_CREDIT_TRIGGER_LOADCREDIT                                                    (0x1<<0) // Credit-based FIFO only: When written with a 1, RX FIFO reset occurs and credit counter loaded from the INIT_CREDIT value.
8282     #define ETH_MAC_REG_CREDIT_TRIGGER_LOADCREDIT_SHIFT                                              0
8283     #define ETH_MAC_REG_CREDIT_TRIGGER_UNUSED_0                                                      (0x7fffffff<<1) // reserved
8284     #define ETH_MAC_REG_CREDIT_TRIGGER_UNUSED_0_SHIFT                                                1
8285 #define ETH_MAC_REG_INIT_CREDIT                                                                      0x00004cUL //Access:RW   DataWidth:0x20  reserved  Chips: K2
8286     #define ETH_MAC_REG_INIT_CREDIT_INITIALCREDIT                                                    (0xff<<0) // Credit-based FIFO only: Specifies the initial credit value to be loaded.
8287     #define ETH_MAC_REG_INIT_CREDIT_INITIALCREDIT_SHIFT                                              0
8288     #define ETH_MAC_REG_INIT_CREDIT_UNUSED_0                                                         (0xffffff<<8) // reserved
8289     #define ETH_MAC_REG_INIT_CREDIT_UNUSED_0_SHIFT                                                   8
8290 #define ETH_MAC_REG_CREDIT_REG                                                                       0x000050UL //Access:R    DataWidth:0x20  reserved  Chips: K2
8291     #define ETH_MAC_REG_CREDIT_REG_CREDITS                                                           (0xff<<0) // Current credit register value (for debug purpose only).
8292     #define ETH_MAC_REG_CREDIT_REG_CREDITS_SHIFT                                                     0
8293     #define ETH_MAC_REG_CREDIT_REG_UNUSED_0                                                          (0xffffff<<8) // reserved
8294     #define ETH_MAC_REG_CREDIT_REG_UNUSED_0_SHIFT                                                    8
8295 #define ETH_MAC_REG_CL01_PAUSE_QUANTA                                                                0x000054UL //Access:RW   DataWidth:0x20  Class 0 and 1 pause quanta. When link pause mode is enabled, CL0_PAUSE_QUANTA is used.  Chips: K2
8296     #define ETH_MAC_REG_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA                                           (0xffff<<0) // CL0_PAUSE_QUANTA
8297     #define ETH_MAC_REG_CL01_PAUSE_QUANTA_CL0_PAUSE_QUANTA_SHIFT                                     0
8298     #define ETH_MAC_REG_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA                                           (0xffff<<16) // Value to be sent for the PFC quanta value for that class when a class XOFF is triggered. Each Quanta specifies a 512 bit-time.
8299     #define ETH_MAC_REG_CL01_PAUSE_QUANTA_CL1_PAUSE_QUANTA_SHIFT                                     16
8300 #define ETH_MAC_REG_CL23_PAUSE_QUANTA                                                                0x000058UL //Access:RW   DataWidth:0x20  Class 2 and 3 pause quanta  Chips: K2
8301     #define ETH_MAC_REG_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA                                           (0xffff<<0) // CL2_PAUSE_QUANTA
8302     #define ETH_MAC_REG_CL23_PAUSE_QUANTA_CL2_PAUSE_QUANTA_SHIFT                                     0
8303     #define ETH_MAC_REG_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA                                           (0xffff<<16) // CL3_PAUSE_QUANTA; Value to be sent for the PFC quanta value for that class when a class XOFF is triggered.
8304     #define ETH_MAC_REG_CL23_PAUSE_QUANTA_CL3_PAUSE_QUANTA_SHIFT                                     16
8305 #define ETH_MAC_REG_CL45_PAUSE_QUANTA                                                                0x00005cUL //Access:RW   DataWidth:0x20  Class 4 and 5 pause quanta  Chips: K2
8306     #define ETH_MAC_REG_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA                                           (0xffff<<0) // CL4_PAUSE_QUANTA
8307     #define ETH_MAC_REG_CL45_PAUSE_QUANTA_CL4_PAUSE_QUANTA_SHIFT                                     0
8308     #define ETH_MAC_REG_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA                                           (0xffff<<16) // CL5_PAUSE_QUANTA; Value to be sent for the PFC quanta value for that class when a class XOFF is triggered.
8309     #define ETH_MAC_REG_CL45_PAUSE_QUANTA_CL5_PAUSE_QUANTA_SHIFT                                     16
8310 #define ETH_MAC_REG_CL67_PAUSE_QUANTA                                                                0x000060UL //Access:RW   DataWidth:0x20  Class 6 and 7 pause quanta  Chips: K2
8311     #define ETH_MAC_REG_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA                                           (0xffff<<0) // CL6_PAUSE_QUANTA
8312     #define ETH_MAC_REG_CL67_PAUSE_QUANTA_CL6_PAUSE_QUANTA_SHIFT                                     0
8313     #define ETH_MAC_REG_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA                                           (0xffff<<16) // CL7_PAUSE_QUANTA; Value to be sent for the PFC quanta value for that class when a class XOFF is triggered.
8314     #define ETH_MAC_REG_CL67_PAUSE_QUANTA_CL7_PAUSE_QUANTA_SHIFT                                     16
8315 #define ETH_MAC_REG_CL01_QUANTA_THRESH                                                               0x000064UL //Access:RW   DataWidth:0x20  Class 0 and 1 refresh threshold. When link pause mode is enabled, CL0_QUANTA_THRESH is used for refreshing pause frames.  Chips: K2
8316     #define ETH_MAC_REG_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH                                         (0xffff<<0) // CL0_QUANTA_THRESH
8317     #define ETH_MAC_REG_CL01_QUANTA_THRESH_CL0_QUANTA_THRESH_SHIFT                                   0
8318     #define ETH_MAC_REG_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH                                         (0xffff<<16) // CL1_QUANTA_THRESH;When a PFC quanta timer counts down and reaches this value, a refresh pause frame should be sent with the programmed full quanta value if the input level indicates that a pause condition still exists.
8319     #define ETH_MAC_REG_CL01_QUANTA_THRESH_CL1_QUANTA_THRESH_SHIFT                                   16
8320 #define ETH_MAC_REG_CL23_QUANTA_THRESH                                                               0x000068UL //Access:RW   DataWidth:0x20  Class 2 and 3 refresh threshold  Chips: K2
8321     #define ETH_MAC_REG_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH                                         (0xffff<<0) // CL2_QUANTA_THRESH
8322     #define ETH_MAC_REG_CL23_QUANTA_THRESH_CL2_QUANTA_THRESH_SHIFT                                   0
8323     #define ETH_MAC_REG_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH                                         (0xffff<<16) // CL3_QUANTA_THRESH; When a PFC quanta timer counts down and reaches this value, a refresh pause frame should be sent with the programmed full quanta value if the input level indicates that a pause condition still exists.
8324     #define ETH_MAC_REG_CL23_QUANTA_THRESH_CL3_QUANTA_THRESH_SHIFT                                   16
8325 #define ETH_MAC_REG_CL45_QUANTA_THRESH                                                               0x00006cUL //Access:RW   DataWidth:0x20  Class 2 and 3 refresh threshold  Chips: K2
8326     #define ETH_MAC_REG_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH                                         (0xffff<<0) // CL4_QUANTA_THRESH
8327     #define ETH_MAC_REG_CL45_QUANTA_THRESH_CL4_QUANTA_THRESH_SHIFT                                   0
8328     #define ETH_MAC_REG_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH                                         (0xffff<<16) // CL5_QUANTA_THRESH
8329     #define ETH_MAC_REG_CL45_QUANTA_THRESH_CL5_QUANTA_THRESH_SHIFT                                   16
8330 #define ETH_MAC_REG_CL67_QUANTA_THRESH                                                               0x000070UL //Access:RW   DataWidth:0x20  Class 6 and 7 refresh threshold  Chips: K2
8331     #define ETH_MAC_REG_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH                                         (0xffff<<0) // CL6_QUANTA_THRESH
8332     #define ETH_MAC_REG_CL67_QUANTA_THRESH_CL6_QUANTA_THRESH_SHIFT                                   0
8333     #define ETH_MAC_REG_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH                                         (0xffff<<16) // CL7_QUANTA_THRESH
8334     #define ETH_MAC_REG_CL67_QUANTA_THRESH_CL7_QUANTA_THRESH_SHIFT                                   16
8335 #define ETH_MAC_REG_RX_PAUSE_STATUS                                                                  0x000074UL //Access:R    DataWidth:0x20  Current per class received pause status. 0 is used for link pause also.  Chips: K2
8336     #define ETH_MAC_REG_RX_PAUSE_STATUS_PAUSESTATUS                                                  (0xff<<0) // Status bit for software to read the current received pause status. One bit for each of the 8 classes.
8337     #define ETH_MAC_REG_RX_PAUSE_STATUS_PAUSESTATUS_SHIFT                                            0
8338     #define ETH_MAC_REG_RX_PAUSE_STATUS_UNUSED_0                                                     (0xffffff<<8) // reserved
8339     #define ETH_MAC_REG_RX_PAUSE_STATUS_UNUSED_0_SHIFT                                               8
8340 #define ETH_MAC_REG_TS_TIMESTAMP                                                                     0x00007cUL //Access:R    DataWidth:0x20  Transmit Timestamp  Chips: K2
8341 #define ETH_MAC_REG_XIF_MODE                                                                         0x000080UL //Access:RW   DataWidth:0x20  Interface Mode Configuration  Chips: K2
8342     #define ETH_MAC_REG_XIF_MODE_XGMII                                                               (0x1<<0) // Enable XGMII-64 (4byte alignment)
8343     #define ETH_MAC_REG_XIF_MODE_XGMII_SHIFT                                                         0
8344     #define ETH_MAC_REG_XIF_MODE_UNUSED_0                                                            (0x7<<1) // reserved
8345     #define ETH_MAC_REG_XIF_MODE_UNUSED_0_SHIFT                                                      1
8346     #define ETH_MAC_REG_XIF_MODE_PAUSETIMERX8                                                        (0x1<<4) // Enable Pause Timer Compensation when using external XLGMII/GMII Converter
8347     #define ETH_MAC_REG_XIF_MODE_PAUSETIMERX8_SHIFT                                                  4
8348     #define ETH_MAC_REG_XIF_MODE_ONESTEPENA                                                          (0x1<<5) // Enable 1-step capable datapath (if available)
8349     #define ETH_MAC_REG_XIF_MODE_ONESTEPENA_SHIFT                                                    5
8350     #define ETH_MAC_REG_XIF_MODE_UNUSED_1                                                            (0x3ffffff<<6) // reserved
8351     #define ETH_MAC_REG_XIF_MODE_UNUSED_1_SHIFT                                                      6
8352 #define ETH_MAC_REG_STATN_CONFIG                                                                     0x0000e0UL //Access:RW   DataWidth:0x20  statistics configuration options  Chips: K2
8353     #define ETH_MAC_REG_STATN_CONFIG_SATURATE                                                        (0x1<<0) // Configure saturation behavior. When set to 1, the counters saturate at all-1. Otherwise counters wrap around.
8354     #define ETH_MAC_REG_STATN_CONFIG_SATURATE_SHIFT                                                  0
8355     #define ETH_MAC_REG_STATN_CONFIG_CLEAR_ON_READ                                                   (0x1<<1) // Configure clear-on-read behavior. When set to 1, the counters are cleared (set to STATN_CLEARVALUE) after having been transferred into the read registers (snapshot captured). When set 0 (default) the counters are not modified when read/captured.
8356     #define ETH_MAC_REG_STATN_CONFIG_CLEAR_ON_READ_SHIFT                                             1
8357     #define ETH_MAC_REG_STATN_CONFIG_CLEAR                                                           (0x1<<2) // Clear all counters command (self-clearing). When written with 1 all counters (tx and rx) are cleared (set to STATN_CLEARVALUE).
8358     #define ETH_MAC_REG_STATN_CONFIG_CLEAR_SHIFT                                                     2
8359     #define ETH_MAC_REG_STATN_CONFIG_UNUSED_0                                                        (0x1fffffff<<3) // reserved
8360     #define ETH_MAC_REG_STATN_CONFIG_UNUSED_0_SHIFT                                                  3
8361 #define ETH_MAC_REG_STATN_CLEARVALUE_LO                                                              0x0000e4UL //Access:RW   DataWidth:0x20  Lower 32bit of 64bit value written into statistics memory when a counter is cleared (testing only, should be 0 normally)  Chips: K2
8362 #define ETH_MAC_REG_STATN_CLEARVALUE_HI                                                              0x0000e8UL //Access:RW   DataWidth:0x20  Upper 32bit of 64bit value written into statistics memory when a counter is cleared (testing only, should be 0 normally)  Chips: K2
8363 #define ETH_MAC_REG_ETHERSTATSOCTETS                                                                 0x000100UL //Access:R    DataWidth:0x20  total, good and bad  Chips: K2
8364 #define ETH_MAC_REG_ETHERSTATSOCTETS_H                                                               0x000104UL //Access:R    DataWidth:0x20  total, good and bad  Chips: K2
8365 #define ETH_MAC_REG_OCTETSOK                                                                         0x000108UL //Access:R    DataWidth:0x20  total, good  Chips: K2
8366 #define ETH_MAC_REG_OCTETSOK_H                                                                       0x00010cUL //Access:R    DataWidth:0x20  total, good  Chips: K2
8367 #define ETH_MAC_REG_AALIGNMENTERRORS                                                                 0x000110UL //Access:R    DataWidth:0x20  Wrong SFD detected  Chips: K2
8368 #define ETH_MAC_REG_AALIGNMENTERRORS_H                                                               0x000114UL //Access:R    DataWidth:0x20  Wrong SFD detected  Chips: K2
8369 #define ETH_MAC_REG_APAUSEMACCTRLFRAMES                                                              0x000118UL //Access:R    DataWidth:0x20  Good Pause frames received  Chips: K2
8370 #define ETH_MAC_REG_APAUSEMACCTRLFRAMES_H                                                            0x00011cUL //Access:R    DataWidth:0x20  Good Pause frames received  Chips: K2
8371 #define ETH_MAC_REG_FRAMESOK                                                                         0x000120UL //Access:R    DataWidth:0x20  Good frames received  Chips: K2
8372 #define ETH_MAC_REG_FRAMESOK_H                                                                       0x000124UL //Access:R    DataWidth:0x20  Good frames received  Chips: K2
8373 #define ETH_MAC_REG_CRCERRORS                                                                        0x000128UL //Access:R    DataWidth:0x20  wrong CRC and good length received  Chips: K2
8374 #define ETH_MAC_REG_CRCERRORS_H                                                                      0x00012cUL //Access:R    DataWidth:0x20  wrong CRC and good length received  Chips: K2
8375 #define ETH_MAC_REG_VLANOK                                                                           0x000130UL //Access:R    DataWidth:0x20  Good Frames with VLAN tag received  Chips: K2
8376 #define ETH_MAC_REG_VLANOK_H                                                                         0x000134UL //Access:R    DataWidth:0x20  Good Frames with VLAN tag received  Chips: K2
8377 #define ETH_MAC_REG_IFINERRORS                                                                       0x000138UL //Access:R    DataWidth:0x20  Errored frames received  Chips: K2
8378 #define ETH_MAC_REG_IFINERRORS_H                                                                     0x00013cUL //Access:R    DataWidth:0x20  Errored frames received  Chips: K2
8379 #define ETH_MAC_REG_IFINUCASTPKTS                                                                    0x000140UL //Access:R    DataWidth:0x20  Good Unicast received  Chips: K2
8380 #define ETH_MAC_REG_IFINUCASTPKTS_H                                                                  0x000144UL //Access:R    DataWidth:0x20  Good Unicast received  Chips: K2
8381 #define ETH_MAC_REG_IFINMCASTPKTS                                                                    0x000148UL //Access:R    DataWidth:0x20  Good Multicast received  Chips: K2
8382 #define ETH_MAC_REG_IFINMCASTPKTS_H                                                                  0x00014cUL //Access:R    DataWidth:0x20  Good Multicast received  Chips: K2
8383 #define ETH_MAC_REG_IFINBCASTPKTS                                                                    0x000150UL //Access:R    DataWidth:0x20  Good Broadcast received  Chips: K2
8384 #define ETH_MAC_REG_IFINBCASTPKTS_H                                                                  0x000154UL //Access:R    DataWidth:0x20  Good Broadcast received  Chips: K2
8385 #define ETH_MAC_REG_ETHERSTATSDROPEVENTS                                                             0x000158UL //Access:R    DataWidth:0x20  Dropped frames  Chips: K2
8386 #define ETH_MAC_REG_ETHERSTATSDROPEVENTS_H                                                           0x00015cUL //Access:R    DataWidth:0x20  Dropped frames  Chips: K2
8387 #define ETH_MAC_REG_ETHERSTATSPKTS                                                                   0x000160UL //Access:R    DataWidth:0x20  Frames received, good and bad  Chips: K2
8388 #define ETH_MAC_REG_ETHERSTATSPKTS_H                                                                 0x000164UL //Access:R    DataWidth:0x20  Frames received, good and bad  Chips: K2
8389 #define ETH_MAC_REG_ETHERSTATSUNDERSIZEPKTS                                                          0x000168UL //Access:R    DataWidth:0x20  Frames received less 64 with good crc  Chips: K2
8390 #define ETH_MAC_REG_ETHERSTATSUNDERSIZEPKTS_H                                                        0x00016cUL //Access:R    DataWidth:0x20  Frames received less 64 with good crc  Chips: K2
8391 #define ETH_MAC_REG_ETHERSTATSPKTS64                                                                 0x000170UL //Access:R    DataWidth:0x20  Frames of 64 octets received  Chips: K2
8392 #define ETH_MAC_REG_ETHERSTATSPKTS64_H                                                               0x000174UL //Access:R    DataWidth:0x20  Frames of 64 octets received  Chips: K2
8393 #define ETH_MAC_REG_ETHERSTATSPKTS65TO127                                                            0x000178UL //Access:R    DataWidth:0x20  Frames of 65 to 127 octets received  Chips: K2
8394 #define ETH_MAC_REG_ETHERSTATSPKTS65TO127_H                                                          0x00017cUL //Access:R    DataWidth:0x20  Frames of 65 to 127 octets received  Chips: K2
8395 #define ETH_MAC_REG_ETHERSTATSPKTS128TO255                                                           0x000180UL //Access:R    DataWidth:0x20  Frames of 128 to 255 octets received  Chips: K2
8396 #define ETH_MAC_REG_ETHERSTATSPKTS128TO255_H                                                         0x000184UL //Access:R    DataWidth:0x20  Frames of 128 to 255 octets received  Chips: K2
8397 #define ETH_MAC_REG_ETHERSTATSPKTS256TO511                                                           0x000188UL //Access:R    DataWidth:0x20  Frames of 256 to 511 octets received  Chips: K2
8398 #define ETH_MAC_REG_ETHERSTATSPKTS256TO511_H                                                         0x00018cUL //Access:R    DataWidth:0x20  Frames of 256 to 511 octets received  Chips: K2
8399 #define ETH_MAC_REG_ETHERSTATSPKTS512TO1023                                                          0x000190UL //Access:R    DataWidth:0x20  Frames of 512 to 1023 octets received  Chips: K2
8400 #define ETH_MAC_REG_ETHERSTATSPKTS512TO1023_H                                                        0x000194UL //Access:R    DataWidth:0x20  Frames of 512 to 1023 octets received  Chips: K2
8401 #define ETH_MAC_REG_ETHERSTATSPKTS1024TO1518                                                         0x000198UL //Access:R    DataWidth:0x20  Frames of 1024 to 1518 octets received  Chips: K2
8402 #define ETH_MAC_REG_ETHERSTATSPKTS1024TO1518_H                                                       0x00019cUL //Access:R    DataWidth:0x20  Frames of 1024 to 1518 octets received  Chips: K2
8403 #define ETH_MAC_REG_ETHERSTATSPKTS1519TOMAX                                                          0x0001a0UL //Access:R    DataWidth:0x20  Frames of 1519 to FRM_LENGTH octets received  Chips: K2
8404 #define ETH_MAC_REG_ETHERSTATSPKTS1519TOMAX_H                                                        0x0001a4UL //Access:R    DataWidth:0x20  Frames of 1519 to FRM_LENGTH octets received  Chips: K2
8405 #define ETH_MAC_REG_ETHERSTATSPKTSOVERSIZE                                                           0x0001a8UL //Access:R    DataWidth:0x20  Frames greater FRM_LENGTH and good CRC received  Chips: K2
8406 #define ETH_MAC_REG_ETHERSTATSPKTSOVERSIZE_H                                                         0x0001acUL //Access:R    DataWidth:0x20  Frames greater FRM_LENGTH and good CRC received  Chips: K2
8407 #define ETH_MAC_REG_ETHERSTATSJABBERS                                                                0x0001b0UL //Access:R    DataWidth:0x20  Frames greater FRM_LENGTH and bad CRC received  Chips: K2
8408 #define ETH_MAC_REG_ETHERSTATSJABBERS_H                                                              0x0001b4UL //Access:R    DataWidth:0x20  Frames greater FRM_LENGTH and bad CRC received  Chips: K2
8409 #define ETH_MAC_REG_ETHERSTATSFRAGMENTS                                                              0x0001b8UL //Access:R    DataWidth:0x20  Frames less 64 and bad CRC received  Chips: K2
8410 #define ETH_MAC_REG_ETHERSTATSFRAGMENTS_H                                                            0x0001bcUL //Access:R    DataWidth:0x20  Frames less 64 and bad CRC received  Chips: K2
8411 #define ETH_MAC_REG_AMACCONTROLFRAMES                                                                0x0001c0UL //Access:R    DataWidth:0x20  Good frames received of type 0x8808 but not Pause  Chips: K2
8412 #define ETH_MAC_REG_AMACCONTROLFRAMES_H                                                              0x0001c4UL //Access:R    DataWidth:0x20  Good frames received of type 0x8808 but not Pause  Chips: K2
8413 #define ETH_MAC_REG_AFRAMETOOLONG                                                                    0x0001c8UL //Access:R    DataWidth:0x20  Good and bad frames exceeding FRM_LENGTH received  Chips: K2
8414 #define ETH_MAC_REG_AFRAMETOOLONG_H                                                                  0x0001ccUL //Access:R    DataWidth:0x20  Good and bad frames exceeding FRM_LENGTH received  Chips: K2
8415 #define ETH_MAC_REG_AINRANGELENGTHERROR                                                              0x0001d0UL //Access:R    DataWidth:0x20  Good frames with invalid length field (not supported)  Chips: K2
8416 #define ETH_MAC_REG_AINRANGELENGTHERROR_H                                                            0x0001d4UL //Access:R    DataWidth:0x20  Good frames with invalid length field (not supported)  Chips: K2
8417 #define ETH_MAC_REG_TXETHERSTATSOCTETS                                                               0x000200UL //Access:R    DataWidth:0x20  total, good and bad  Chips: K2
8418 #define ETH_MAC_REG_TXETHERSTATSOCTETS_H                                                             0x000204UL //Access:R    DataWidth:0x20  total, good and bad  Chips: K2
8419 #define ETH_MAC_REG_TXOCTETSOK                                                                       0x000208UL //Access:R    DataWidth:0x20  total, good  Chips: K2
8420 #define ETH_MAC_REG_TXOCTETSOK_H                                                                     0x00020cUL //Access:R    DataWidth:0x20  total, good  Chips: K2
8421 #define ETH_MAC_REG_TXAPAUSEMACCTRLFRAMES                                                            0x000218UL //Access:R    DataWidth:0x20  Good Pause frames transmitted  Chips: K2
8422 #define ETH_MAC_REG_TXAPAUSEMACCTRLFRAMES_H                                                          0x00021cUL //Access:R    DataWidth:0x20  Good Pause frames transmitted  Chips: K2
8423 #define ETH_MAC_REG_TXFRAMESOK                                                                       0x000220UL //Access:R    DataWidth:0x20  Good frames transmitted  Chips: K2
8424 #define ETH_MAC_REG_TXFRAMESOK_H                                                                     0x000224UL //Access:R    DataWidth:0x20  Good frames transmitted  Chips: K2
8425 #define ETH_MAC_REG_TXCRCERRORS                                                                      0x000228UL //Access:R    DataWidth:0x20  wrong CRC transmitted  Chips: K2
8426 #define ETH_MAC_REG_TXCRCERRORS_H                                                                    0x00022cUL //Access:R    DataWidth:0x20  wrong CRC transmitted  Chips: K2
8427 #define ETH_MAC_REG_TXVLANOK                                                                         0x000230UL //Access:R    DataWidth:0x20  Good Frames with VLAN tag transmitted  Chips: K2
8428 #define ETH_MAC_REG_TXVLANOK_H                                                                       0x000234UL //Access:R    DataWidth:0x20  Good Frames with VLAN tag transmitted  Chips: K2
8429 #define ETH_MAC_REG_IFOUTERRORS                                                                      0x000238UL //Access:R    DataWidth:0x20  Errored frames transmitted  Chips: K2
8430 #define ETH_MAC_REG_IFOUTERRORS_H                                                                    0x00023cUL //Access:R    DataWidth:0x20  Errored frames transmitted  Chips: K2
8431 #define ETH_MAC_REG_IFOUTUCASTPKTS                                                                   0x000240UL //Access:R    DataWidth:0x20  Good Unicast transmitted  Chips: K2
8432 #define ETH_MAC_REG_IFOUTUCASTPKTS_H                                                                 0x000244UL //Access:R    DataWidth:0x20  Good Unicast transmitted  Chips: K2
8433 #define ETH_MAC_REG_IFOUTMCASTPKTS                                                                   0x000248UL //Access:R    DataWidth:0x20  Good Multicast transmitted  Chips: K2
8434 #define ETH_MAC_REG_IFOUTMCASTPKTS_H                                                                 0x00024cUL //Access:R    DataWidth:0x20  Good Multicast transmitted  Chips: K2
8435 #define ETH_MAC_REG_IFOUTBCASTPKTS                                                                   0x000250UL //Access:R    DataWidth:0x20  Good Broadcast transmitted  Chips: K2
8436 #define ETH_MAC_REG_IFOUTBCASTPKTS_H                                                                 0x000254UL //Access:R    DataWidth:0x20  Good Broadcast transmitted  Chips: K2
8437 #define ETH_MAC_REG_TXETHERSTATSDROPEVENTS                                                           0x000258UL //Access:R    DataWidth:0x20  Dropped frames (unused, reserved)  Chips: K2
8438 #define ETH_MAC_REG_TXETHERSTATSDROPEVENTS_H                                                         0x00025cUL //Access:R    DataWidth:0x20  Dropped frames (unused, reserved)  Chips: K2
8439 #define ETH_MAC_REG_TXETHERSTATSPKTS                                                                 0x000260UL //Access:R    DataWidth:0x20  Frames transmitted, good and bad  Chips: K2
8440 #define ETH_MAC_REG_TXETHERSTATSPKTS_H                                                               0x000264UL //Access:R    DataWidth:0x20  Frames transmitted, good and bad  Chips: K2
8441 #define ETH_MAC_REG_TXETHERSTATSUNDERSIZEPKTS                                                        0x000268UL //Access:R    DataWidth:0x20  Frames transmitted less 64  Chips: K2
8442 #define ETH_MAC_REG_TXETHERSTATSUNDERSIZEPKTS_H                                                      0x00026cUL //Access:R    DataWidth:0x20  Frames transmitted less 64  Chips: K2
8443 #define ETH_MAC_REG_TXETHERSTATSPKTS64                                                               0x000270UL //Access:R    DataWidth:0x20  Frames of 64 octets transmitted  Chips: K2
8444 #define ETH_MAC_REG_TXETHERSTATSPKTS64_H                                                             0x000274UL //Access:R    DataWidth:0x20  Frames of 64 octets transmitted  Chips: K2
8445 #define ETH_MAC_REG_TXETHERSTATSPKTS65TO127                                                          0x000278UL //Access:R    DataWidth:0x20  Frames of 65 to 127 octets transmitted  Chips: K2
8446 #define ETH_MAC_REG_TXETHERSTATSPKTS65TO127_H                                                        0x00027cUL //Access:R    DataWidth:0x20  Frames of 65 to 127 octets transmitted  Chips: K2
8447 #define ETH_MAC_REG_TXETHERSTATSPKTS128TO255                                                         0x000280UL //Access:R    DataWidth:0x20  Frames of 128 to 255 octets transmitted  Chips: K2
8448 #define ETH_MAC_REG_TXETHERSTATSPKTS128TO255_H                                                       0x000284UL //Access:R    DataWidth:0x20  Frames of 128 to 255 octets transmitted  Chips: K2
8449 #define ETH_MAC_REG_TXETHERSTATSPKTS256TO511                                                         0x000288UL //Access:R    DataWidth:0x20  Frames of 256 to 511 octets transmitted  Chips: K2
8450 #define ETH_MAC_REG_TXETHERSTATSPKTS256TO511_H                                                       0x00028cUL //Access:R    DataWidth:0x20  Frames of 256 to 511 octets transmitted  Chips: K2
8451 #define ETH_MAC_REG_TXETHERSTATSPKTS512TO1023                                                        0x000290UL //Access:R    DataWidth:0x20  Frames of 512 to 1023 octets transmitted  Chips: K2
8452 #define ETH_MAC_REG_TXETHERSTATSPKTS512TO1023_H                                                      0x000294UL //Access:R    DataWidth:0x20  Frames of 512 to 1023 octets transmitted  Chips: K2
8453 #define ETH_MAC_REG_TXETHERSTATSPKTS1024TO1518                                                       0x000298UL //Access:R    DataWidth:0x20  Frames of 1024 to 1518 octets transmitted  Chips: K2
8454 #define ETH_MAC_REG_TXETHERSTATSPKTS1024TO1518_H                                                     0x00029cUL //Access:R    DataWidth:0x20  Frames of 1024 to 1518 octets transmitted  Chips: K2
8455 #define ETH_MAC_REG_TXETHERSTATSPKTS1519TOTX_MTU                                                     0x0002a0UL //Access:R    DataWidth:0x20  Frames of 1519 to FRM_LENGTH.TX_MTU octets transmitted  Chips: K2
8456 #define ETH_MAC_REG_TXETHERSTATSPKTS1519TOTX_MTU_H                                                   0x0002a4UL //Access:R    DataWidth:0x20  Frames of 1519 to FRM_LENGTH.TX_MTU octets transmitted  Chips: K2
8457 #define ETH_MAC_REG_TXAMACCONTROLFRAMES                                                              0x0002c0UL //Access:R    DataWidth:0x20  Good frames transmitted of type 0x8808 but not Pause  Chips: K2
8458 #define ETH_MAC_REG_TXAMACCONTROLFRAMES_H                                                            0x0002c4UL //Access:R    DataWidth:0x20  Good frames transmitted of type 0x8808 but not Pause  Chips: K2
8459 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_0                                                       0x000380UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.  Chips: K2
8460 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_0_H                                                     0x000384UL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8461 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_1                                                       0x000388UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.  Chips: K2
8462 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_1_H                                                     0x00038cUL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8463 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_2                                                       0x000390UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.  Chips: K2
8464 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_2_H                                                     0x000394UL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8465 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_3                                                       0x000398UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.  Chips: K2
8466 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_3_H                                                     0x00039cUL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8467 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_4                                                       0x0003a0UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.  Chips: K2
8468 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_4_H                                                     0x0003a4UL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8469 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_5                                                       0x0003a8UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.  Chips: K2
8470 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_5_H                                                     0x0003acUL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8471 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_6                                                       0x0003b0UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.  Chips: K2
8472 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_6_H                                                     0x0003b4UL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8473 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_7                                                       0x0003b8UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames received for each class.  Chips: K2
8474 #define ETH_MAC_REG_ACBFCPAUSEFRAMESRECEIVED_7_H                                                     0x0003bcUL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8475 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_0                                                    0x0003c0UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.  Chips: K2
8476 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_0_H                                                  0x0003c4UL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8477 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_1                                                    0x0003c8UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.  Chips: K2
8478 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_1_H                                                  0x0003ccUL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8479 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_2                                                    0x0003d0UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.  Chips: K2
8480 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_2_H                                                  0x0003d4UL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8481 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_3                                                    0x0003d8UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.  Chips: K2
8482 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_3_H                                                  0x0003dcUL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8483 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_4                                                    0x0003e0UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.  Chips: K2
8484 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_4_H                                                  0x0003e4UL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8485 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_5                                                    0x0003e8UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.  Chips: K2
8486 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_5_H                                                  0x0003ecUL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8487 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_6                                                    0x0003f0UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.  Chips: K2
8488 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_6_H                                                  0x0003f4UL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8489 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_7                                                    0x0003f8UL //Access:R    DataWidth:0x20  Set of 8 objects recording the number of CBFC (Class Based Flow Control) pause frames transmitted for each class.  Chips: K2
8490 #define ETH_MAC_REG_ACBFCPAUSEFRAMESTRANSMITTED_7_H                                                  0x0003fcUL //Access:R    DataWidth:0x20  Upper 32bit of 64bit counter.  Chips: K2
8491 #define ETH_RSFEC_REG_RS_FEC_CONTROL                                                                 0x000000UL //Access:RW   DataWidth:0x20  Control register for enabling FEC functions.  Chips: K2
8492     #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_CORRECTION                                           (0x1<<0) // When 1, bypass the decoder's correction function for reduced latency; When  0, normal FEC operation.
8493     #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_CORRECTION_SHIFT                                     0
8494     #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_ERROR_INDICATION                                     (0x1<<1) // When 1, configure the FEC decoder to not indicate errors to the PCS layer; When  0, the FEC decoder indicates errors to the PCS layer.
8495     #define ETH_RSFEC_REG_RS_FEC_CONTROL_BYPASS_ERROR_INDICATION_SHIFT                               1
8496     #define ETH_RSFEC_REG_RS_FEC_CONTROL_UNUSED_0                                                    (0x3fffffff<<2) // reserved
8497     #define ETH_RSFEC_REG_RS_FEC_CONTROL_UNUSED_0_SHIFT                                              2
8498 #define ETH_RSFEC_REG_RS_FEC_STATUS                                                                  0x000004UL //Access:R    DataWidth:0x20  RS FEC Status register.  Chips: K2
8499     #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_CORRECTION                                            (0x1<<0) // Indicates existence of the receive correction bypass option; The bypass function allows a reduced latency operation.
8500     #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_CORRECTION_SHIFT                                      0
8501     #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_INDICATION                                            (0x1<<1) // Indicates the ability to disable error propagation to the PCS layer.
8502     #define ETH_RSFEC_REG_RS_FEC_STATUS_BYPASS_INDICATION_SHIFT                                      1
8503     #define ETH_RSFEC_REG_RS_FEC_STATUS_HIGH_SER                                                     (0x1<<2) // Asserts when error indication bypass is enabled and high symbol error rate is found;  Clear on read.
8504     #define ETH_RSFEC_REG_RS_FEC_STATUS_HIGH_SER_SHIFT                                               2
8505     #define ETH_RSFEC_REG_RS_FEC_STATUS_UNUSED_0                                                     (0x1f<<3) // reserved
8506     #define ETH_RSFEC_REG_RS_FEC_STATUS_UNUSED_0_SHIFT                                               3
8507     #define ETH_RSFEC_REG_RS_FEC_STATUS_AMPS_LOCK                                                    (0xf<<8) // RS-FEC receive lane locked and aligned; One bit per lane: Bit 8 = lane 0, Bit 9 = lane 1, Bit 10= lane 2, Bit 11 = lane 3.
8508     #define ETH_RSFEC_REG_RS_FEC_STATUS_AMPS_LOCK_SHIFT                                              8
8509     #define ETH_RSFEC_REG_RS_FEC_STATUS_UNUSED_1                                                     (0x3<<12) // reserved
8510     #define ETH_RSFEC_REG_RS_FEC_STATUS_UNUSED_1_SHIFT                                               12
8511     #define ETH_RSFEC_REG_RS_FEC_STATUS_FEC_ALIGN_STATUS                                             (0x1<<14) // Indicates, when 1 that the RS-FEC receiver has locked on incoming data and deskew completed.
8512     #define ETH_RSFEC_REG_RS_FEC_STATUS_FEC_ALIGN_STATUS_SHIFT                                       14
8513     #define ETH_RSFEC_REG_RS_FEC_STATUS_PCS_ALIGN_STATUS                                             (0x1<<15) // Always 1.
8514     #define ETH_RSFEC_REG_RS_FEC_STATUS_PCS_ALIGN_STATUS_SHIFT                                       15
8515     #define ETH_RSFEC_REG_RS_FEC_STATUS_UNUSED_2                                                     (0xffff<<16) // reserved
8516     #define ETH_RSFEC_REG_RS_FEC_STATUS_UNUSED_2_SHIFT                                               16
8517 #define ETH_RSFEC_REG_RS_FEC_CCW_LO                                                                  0x000008UL //Access:R    DataWidth:0x20  Counts number of corrected FEC codewords lower 16-bits; None roll-over when upper 16-bits are 0xffff.  Chips: K2
8518     #define ETH_RSFEC_REG_RS_FEC_CCW_LO_COUNTER                                                      (0xffff<<0) // Counts number of corrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over when upper 16-bits are 0xffff
8519     #define ETH_RSFEC_REG_RS_FEC_CCW_LO_COUNTER_SHIFT                                                0
8520     #define ETH_RSFEC_REG_RS_FEC_CCW_LO_UNUSED_0                                                     (0xffff<<16) // reserved
8521     #define ETH_RSFEC_REG_RS_FEC_CCW_LO_UNUSED_0_SHIFT                                               16
8522 #define ETH_RSFEC_REG_RS_FEC_CCW_HI                                                                  0x00000cUL //Access:R    DataWidth:0x20  Counts number of corrected FEC codewords upper 16-bits; Clears on read; None roll-over.  Chips: K2
8523     #define ETH_RSFEC_REG_RS_FEC_CCW_HI_COUNTER_HI                                                   (0xffff<<0) // Counts number of corrected FEC codewords upper 16-bits; None roll-over; Clears when read.
8524     #define ETH_RSFEC_REG_RS_FEC_CCW_HI_COUNTER_HI_SHIFT                                             0
8525     #define ETH_RSFEC_REG_RS_FEC_CCW_HI_UNUSED_0                                                     (0xffff<<16) // reserved
8526     #define ETH_RSFEC_REG_RS_FEC_CCW_HI_UNUSED_0_SHIFT                                               16
8527 #define ETH_RSFEC_REG_RS_FEC_NCCW_LO                                                                 0x000010UL //Access:R    DataWidth:0x20  Counts number of uncorrected FEC codewords lower 16-bits; None roll-over when upper 16-bits are 0xffff.  Chips: K2
8528     #define ETH_RSFEC_REG_RS_FEC_NCCW_LO_COUNTER                                                     (0xffff<<0) // Counts number of uncorrected FEC codewords lower 16-bits; Must be read before upper 16-bits; None roll-over when upper 16-bits are 0xffff
8529     #define ETH_RSFEC_REG_RS_FEC_NCCW_LO_COUNTER_SHIFT                                               0
8530     #define ETH_RSFEC_REG_RS_FEC_NCCW_LO_UNUSED_0                                                    (0xffff<<16) // reserved
8531     #define ETH_RSFEC_REG_RS_FEC_NCCW_LO_UNUSED_0_SHIFT                                              16
8532 #define ETH_RSFEC_REG_RS_FEC_NCCW_HI                                                                 0x000014UL //Access:R    DataWidth:0x20  Counts number of uncorrected FEC codewords upper 16-bits; Clears on read; None roll-over.  Chips: K2
8533     #define ETH_RSFEC_REG_RS_FEC_NCCW_HI_COUNTER_HI                                                  (0xffff<<0) // Counts number of uncorrected FEC codewords upper 16-bits; None roll-over; Clears when read.
8534     #define ETH_RSFEC_REG_RS_FEC_NCCW_HI_COUNTER_HI_SHIFT                                            0
8535     #define ETH_RSFEC_REG_RS_FEC_NCCW_HI_UNUSED_0                                                    (0xffff<<16) // reserved
8536     #define ETH_RSFEC_REG_RS_FEC_NCCW_HI_UNUSED_0_SHIFT                                              16
8537 #define ETH_RSFEC_REG_RS_FEC_LANEMAP                                                                 0x000018UL //Access:R    DataWidth:0x20  FEC alignment status and lane mappings.  Chips: K2
8538     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_0                                                  (0x3<<0) // FEC lane mapped to PMA lane 0.
8539     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_0_SHIFT                                            0
8540     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_1                                                  (0x3<<2) // FEC lane mapped to PMA lane 1.
8541     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_1_SHIFT                                            2
8542     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_2                                                  (0x3<<4) // FEC lane mapped to PMA lane 2.
8543     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_2_SHIFT                                            4
8544     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_3                                                  (0x3<<6) // FEC lane mapped to PMA lane 3.
8545     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_PMA_LANE_3_SHIFT                                            6
8546     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_UNUSED_0                                                    (0xffffff<<8) // reserved
8547     #define ETH_RSFEC_REG_RS_FEC_LANEMAP_UNUSED_0_SHIFT                                              8
8548 #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_LO                                                            0x000028UL //Access:R    DataWidth:0x20  Counts number of (corrected) 10-bit symbol errors found in lane 0; None roll-over when upper 16-bits are 0xffff.  Chips: K2
8549     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_LO_SYMBOL_ERRORS                                          (0xffff<<0) // Counts number of (corrected) 10-bit symbol errors found in lane 0 for correctable codewords only; Lower 16-bit of counter; Must be read first; None roll-over when upper word is 0xffff.
8550     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_LO_SYMBOL_ERRORS_SHIFT                                    0
8551     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_LO_UNUSED_0                                               (0xffff<<16) // reserved
8552     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_LO_UNUSED_0_SHIFT                                         16
8553 #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_HI                                                            0x00002cUL //Access:R    DataWidth:0x20  Upper 16-bit of counter (with above register); Clears on read; None roll-over.  Chips: K2
8554     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_HI_SYMBOL_ERROR_HI                                        (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 0; Clears on read; None roll-over.
8555     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_HI_SYMBOL_ERROR_HI_SHIFT                                  0
8556     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_HI_UNUSED_0                                               (0xffff<<16) // reserved
8557     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR0_HI_UNUSED_0_SHIFT                                         16
8558 #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_LO                                                            0x000030UL //Access:R    DataWidth:0x20  Counts number of (corrected) 10-bit symbol errors found in lane 1; None roll-over when upper 16-bits are 0xffff.  Chips: K2
8559     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_LO_SYMBOL_ERRORS                                          (0xffff<<0) // Counts number of (corrected) 10-bit symbol errors found in lane 1 for correctable codewords only; Lower 16-bit of counter; Must be read first; None roll-over when upper word is 0xffff.
8560     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_LO_SYMBOL_ERRORS_SHIFT                                    0
8561     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_LO_UNUSED_0                                               (0xffff<<16) // reserved
8562     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_LO_UNUSED_0_SHIFT                                         16
8563 #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_HI                                                            0x000034UL //Access:R    DataWidth:0x20  Upper 16-bit of counter (with above register); Clears on read; None roll-over.  Chips: K2
8564     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_HI_SYMBOL_ERROR_HI                                        (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 1; Clears on read; None roll-over.
8565     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_HI_SYMBOL_ERROR_HI_SHIFT                                  0
8566     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_HI_UNUSED_0                                               (0xffff<<16) // reserved
8567     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR1_HI_UNUSED_0_SHIFT                                         16
8568 #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_LO                                                            0x000038UL //Access:R    DataWidth:0x20  Counts number of (corrected) 10-bit symbol errors found in lane 2; None roll-over when upper 16-bits are 0xffff.  Chips: K2
8569     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_LO_SYMBOL_ERRORS                                          (0xffff<<0) // Counts number of (corrected) 10-bit symbol errors found in lane 2 for correctable codewords only; Lower 16-bit of counter; Must be read first; None roll-over when upper word is 0xffff.
8570     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_LO_SYMBOL_ERRORS_SHIFT                                    0
8571     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_LO_UNUSED_0                                               (0xffff<<16) // reserved
8572     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_LO_UNUSED_0_SHIFT                                         16
8573 #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_HI                                                            0x00003cUL //Access:R    DataWidth:0x20  Upper 16-bit of counter (with above register); Clears on read; None roll-over.  Chips: K2
8574     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_HI_SYMBOL_ERROR_HI                                        (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 2; Clears on read; None roll-over.
8575     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_HI_SYMBOL_ERROR_HI_SHIFT                                  0
8576     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_HI_UNUSED_0                                               (0xffff<<16) // reserved
8577     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR2_HI_UNUSED_0_SHIFT                                         16
8578 #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_LO                                                            0x000040UL //Access:R    DataWidth:0x20  Counts number of (corrected) 10-bit symbol errors found in lane 3; None roll-over when upper 16-bits are 0xffff.  Chips: K2
8579     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_LO_SYMBOL_ERRORS                                          (0xffff<<0) // Counts number of (corrected) 10-bit symbol errors found in lane 3 for correctable codewords only; Lower 16-bit of counter; Must be read first; None roll-over when upper word is 0xffff.
8580     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_LO_SYMBOL_ERRORS_SHIFT                                    0
8581     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_LO_UNUSED_0                                               (0xffff<<16) // reserved
8582     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_LO_UNUSED_0_SHIFT                                         16
8583 #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_HI                                                            0x000044UL //Access:R    DataWidth:0x20  Upper 16 bit of counter (with above register); Clears on read; None roll-over.  Chips: K2
8584     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_HI_SYMBOL_ERROR_HI                                        (0xffff<<0) // Upper 16-bits of the 32-bit Symbol error counter for lane 3; Clears on read; None roll-over.
8585     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_HI_SYMBOL_ERROR_HI_SHIFT                                  0
8586     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_HI_UNUSED_0                                               (0xffff<<16) // reserved
8587     #define ETH_RSFEC_REG_RS_FEC_SYMBLERR3_HI_UNUSED_0_SHIFT                                         16
8588 #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL                                                          0x000200UL //Access:RW   DataWidth:0x20  Additional control to enable RS-FEC operation.  Chips: K2
8589     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_UNUSED_0                                             (0x3<<0) // reserved
8590     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_UNUSED_0_SHIFT                                       0
8591     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_ENABLE                                        (0x1<<2) // When 1, enable RSFEC datapath instead PCS MLD;  When 0, use normal PCS MLD datapath (default).
8592     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_ENABLE_SHIFT                                  2
8593     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_UNUSED_1                                             (0xfff<<3) // reserved
8594     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_UNUSED_1_SHIFT                                       3
8595     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_STATUS                                        (0x1<<15) // Indicates the operatyional outcome of the (above) enable bit control; When 1 = FEC enabled and 0 = disabled.
8596     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_RS_FEC_STATUS_SHIFT                                  15
8597     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_UNUSED_2                                             (0xffff<<16) // reserved
8598     #define ETH_RSFEC_REG_RS_FEC_VENDOR_CONTROL_UNUSED_2_SHIFT                                       16
8599 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1                                                            0x000204UL //Access:R    DataWidth:0x20  Implementation specific information that may be useful for debugging link problems; Clears on read.  Chips: K2
8600     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_AMPS_LOCK                                              (0xf<<0) // Per PMA lane FEC synchronization status; Bit 0=lane 0 up to Bit 3 = lane 3; Latched high; Clear on read.
8601     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_AMPS_LOCK_SHIFT                                        0
8602     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LH                                    (0x1<<4) // FEC alignment status; Latched high; Clear on read.
8603     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LH_SHIFT                              4
8604     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_MARKER_CHECK_RESTART                                   (0x1<<5) // The marker_check function (PCS sublayer) caused an alignment restart to the FEC; Latched high; Clear on read.
8605     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_MARKER_CHECK_RESTART_SHIFT                             5
8606     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DATAPATH_RESTART                                    (0x1<<6) // RX datapath (sync) reset occured; Latched high; Clear on read.
8607     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DATAPATH_RESTART_SHIFT                              6
8608     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DATAPATH_RESTART                                    (0x1<<7) // TX datapath (sync) reset occured; Latched high; Clear on read.
8609     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DATAPATH_RESTART_SHIFT                              7
8610     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DP_OVERFLOW                                         (0x1<<8) // RX datapath 4x66 pacing fifo overflow fatal error; Latched high; Clear on read.
8611     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_RX_DP_OVERFLOW_SHIFT                                   8
8612     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DP_OVERFLOW                                         (0x1<<9) // TX datapath 4x66 input fifo overflow fatal error; Latched high; Clear on read.
8613     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_TX_DP_OVERFLOW_SHIFT                                   9
8614     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LL                                    (0x1<<10) // FEC alignment status; Latched high; Sets on read.
8615     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_FEC_ALIGN_STATUS_LL_SHIFT                              10
8616     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_UNUSED_0                                               (0x1<<11) // reserved
8617     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_UNUSED_0_SHIFT                                         11
8618     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_DESKEW_EMPTY                                           (0xf<<12) // Real-time indication from FEC deskew FIFO per lane; bit 12 = lane 0 upto bit 15 = lane3.
8619     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_DESKEW_EMPTY_SHIFT                                     12
8620     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_UNUSED_1                                               (0xffff<<16) // reserved
8621     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO1_UNUSED_1_SHIFT                                         16
8622 #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO2                                                            0x000208UL //Access:R    DataWidth:0x20  Implementation specific status information; Clears on read.  Chips: K2
8623     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO2_AMPS_LOCK                                              (0xf<<0) // Per PMA lane FEC synchronization status; Realtime updates;  Bit  0 = lane 0 upto bit 3 = lane 3; Clears on read;
8624     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO2_AMPS_LOCK_SHIFT                                        0
8625     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO2_UNUSED_0                                               (0xfffffff<<4) // reserved
8626     #define ETH_RSFEC_REG_RS_FEC_VENDOR_INFO2_UNUSED_0_SHIFT                                         4
8627 #define ETH_RSFEC_REG_RS_FEC_VENDOR_REVISION                                                         0x00020cUL //Access:R    DataWidth:0x20  A version information taken from package file parameter FEC91_DEV_VERSION.  Chips: K2
8628     #define ETH_RSFEC_REG_RS_FEC_VENDOR_REVISION_REVISION                                            (0xffff<<0) // A version information taken from package file parameter FEC91_DEV_VERSION.
8629     #define ETH_RSFEC_REG_RS_FEC_VENDOR_REVISION_REVISION_SHIFT                                      0
8630     #define ETH_RSFEC_REG_RS_FEC_VENDOR_REVISION_UNUSED_0                                            (0xffff<<16) // reserved
8631     #define ETH_RSFEC_REG_RS_FEC_VENDOR_REVISION_UNUSED_0_SHIFT                                      16
8632 #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTKEY                                                       0x000210UL //Access:RW   DataWidth:0x20  Bits 7:0; Must be written with the 8-bit value of 0x57 to enable RS-FEC transmit test error injection capability.  Chips: K2
8633     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTKEY_TEST_KEY                                          (0xff<<0) // Bits 7:0; Must be written with 8-bit value 0x57 to enable RS-FEC transmit test error injection capability.
8634     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTKEY_TEST_KEY_SHIFT                                    0
8635     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTKEY_UNUSED_0                                          (0xffffff<<8) // reserved
8636     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTKEY_UNUSED_0_SHIFT                                    8
8637 #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTSYMBOLS                                                   0x000214UL //Access:RW   DataWidth:0x20  Bits 15:0. One bit per 10-bit Symbol; Each bit is applied to corresponding 10B symbol after FEC encoding.  Chips: K2
8638     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTSYMBOLS_TEST_SYMBOLS                                  (0xffff<<0) // Bits 15:0. One bit per 10-bit Symbol; When a bit is 1 the test pattern is applied to the corresponding 10B symbol after the FEC encoding.
8639     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTSYMBOLS_TEST_SYMBOLS_SHIFT                            0
8640     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTSYMBOLS_UNUSED_0                                      (0xffff<<16) // reserved
8641     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTSYMBOLS_UNUSED_0_SHIFT                                16
8642 #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN                                                   0x000218UL //Access:RW   DataWidth:0x20  Bits 9:0; A 10-bit value which XORed with a 10B symbol FEC encoder to manipulate transmitted datastream.  Chips: K2
8643     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_TEST_PATTERN                                  (0x3ff<<0) // A 10-bit value which will be XORed with a 10B symbol after the FEC encoder to manipulate the transmitted datastream.
8644     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_TEST_PATTERN_SHIFT                            0
8645     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_OVERWRITE                                     (0x1<<10) // If the bit is set the 10B symbol is replaced by the pattern instead using XOR.
8646     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_OVERWRITE_SHIFT                               10
8647     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_UNUSED_0                                      (0x1fffff<<11) // reserved
8648     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTPATTERN_UNUSED_0_SHIFT                                11
8649 #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER                                                   0x00021cUL //Access:RW   DataWidth:0x20  Enable register to control the triggers with the error insertion; Bit 0 clears on operation complete.  Chips: K2
8650     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER_TEST_TRIGGER                                  (0x1<<0) // For bit 0 only, when written with 1 triggers the error insertion (on one word of 16 symbols); This bit clears automatically.
8651     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER_TEST_TRIGGER_SHIFT                            0
8652     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER_UNUSED_0                                      (0x7fffffff<<1) // reserved
8653     #define ETH_RSFEC_REG_RS_FEC_VENDOR_TX_TESTTRIGGER_UNUSED_0_SHIFT                                1
8654 #define ETH_PCS1G_REG_CONTROL                                                                        0x000000UL //Access:RW   DataWidth:0x20  Control register  Chips: K2
8655     #define ETH_PCS1G_REG_CONTROL_UNUSED_0                                                           (0x3f<<0) // reserved
8656     #define ETH_PCS1G_REG_CONTROL_UNUSED_0_SHIFT                                                     0
8657     #define ETH_PCS1G_REG_CONTROL_SPEED_6                                                            (0x1<<6) // Speed Selection Indication; always 1
8658     #define ETH_PCS1G_REG_CONTROL_SPEED_6_SHIFT                                                      6
8659     #define ETH_PCS1G_REG_CONTROL_UNUSED_1                                                           (0x1<<7) // reserved
8660     #define ETH_PCS1G_REG_CONTROL_UNUSED_1_SHIFT                                                     7
8661     #define ETH_PCS1G_REG_CONTROL_DUPLEX                                                             (0x1<<8) // Indicate full-duplex operation; always 1
8662     #define ETH_PCS1G_REG_CONTROL_DUPLEX_SHIFT                                                       8
8663     #define ETH_PCS1G_REG_CONTROL_ANRESTART                                                          (0x1<<9) // Restart Autonegotiation
8664     #define ETH_PCS1G_REG_CONTROL_ANRESTART_SHIFT                                                    9
8665     #define ETH_PCS1G_REG_CONTROL_ISOLATE                                                            (0x1<<10) // Set PCS isolate mode; Controls toplevel pin only, no internal function.
8666     #define ETH_PCS1G_REG_CONTROL_ISOLATE_SHIFT                                                      10
8667     #define ETH_PCS1G_REG_CONTROL_POWERDOWN                                                          (0x1<<11) // Enable powerdown state, if supported.
8668     #define ETH_PCS1G_REG_CONTROL_POWERDOWN_SHIFT                                                    11
8669     #define ETH_PCS1G_REG_CONTROL_ANENABLE                                                           (0x1<<12) // Autonegotiation enable
8670     #define ETH_PCS1G_REG_CONTROL_ANENABLE_SHIFT                                                     12
8671     #define ETH_PCS1G_REG_CONTROL_SPEED_13                                                           (0x1<<13) // Speed Selection Indication; always 0
8672     #define ETH_PCS1G_REG_CONTROL_SPEED_13_SHIFT                                                     13
8673     #define ETH_PCS1G_REG_CONTROL_LOOPBACK                                                           (0x1<<14) // Enable loopback
8674     #define ETH_PCS1G_REG_CONTROL_LOOPBACK_SHIFT                                                     14
8675     #define ETH_PCS1G_REG_CONTROL_RESET                                                              (0x1<<15) // PCS soft-reset command; self-clearing
8676     #define ETH_PCS1G_REG_CONTROL_RESET_SHIFT                                                        15
8677     #define ETH_PCS1G_REG_CONTROL_UNUSED_2                                                           (0xffff<<16) // reserved
8678     #define ETH_PCS1G_REG_CONTROL_UNUSED_2_SHIFT                                                     16
8679 #define ETH_PCS1G_REG_STATUS                                                                         0x000004UL //Access:R    DataWidth:0x20  Status indications  Chips: K2
8680     #define ETH_PCS1G_REG_STATUS_EXTDCAPABILITY                                                      (0x1<<0) // Indicate extended register support; always 1
8681     #define ETH_PCS1G_REG_STATUS_EXTDCAPABILITY_SHIFT                                                0
8682     #define ETH_PCS1G_REG_STATUS_UNUSED_0                                                            (0x1<<1) // reserved
8683     #define ETH_PCS1G_REG_STATUS_UNUSED_0_SHIFT                                                      1
8684     #define ETH_PCS1G_REG_STATUS_LINKSTATUS                                                          (0x1<<2) // Indicate link status; latch-low
8685     #define ETH_PCS1G_REG_STATUS_LINKSTATUS_SHIFT                                                    2
8686     #define ETH_PCS1G_REG_STATUS_ANEGABILITY                                                         (0x1<<3) // Autonegotiation ability; always 1
8687     #define ETH_PCS1G_REG_STATUS_ANEGABILITY_SHIFT                                                   3
8688     #define ETH_PCS1G_REG_STATUS_UNUSED_1                                                            (0x1<<4) // reserved
8689     #define ETH_PCS1G_REG_STATUS_UNUSED_1_SHIFT                                                      4
8690     #define ETH_PCS1G_REG_STATUS_ANEGCOMPLETE                                                        (0x1<<5) // Autonegotiation completed indication
8691     #define ETH_PCS1G_REG_STATUS_ANEGCOMPLETE_SHIFT                                                  5
8692     #define ETH_PCS1G_REG_STATUS_UNUSED_2                                                            (0x3ffffff<<6) // reserved
8693     #define ETH_PCS1G_REG_STATUS_UNUSED_2_SHIFT                                                      6
8694 #define ETH_PCS1G_REG_PHY_ID_0                                                                       0x000008UL //Access:R    DataWidth:0x20  PHY Identifier lower 16 bits  Chips: K2
8695     #define ETH_PCS1G_REG_PHY_ID_0_PHYID                                                             (0xffff<<0) // PHY Identifier from package file parameter PHY_IDENTIFIER lower 16 bits.
8696     #define ETH_PCS1G_REG_PHY_ID_0_PHYID_SHIFT                                                       0
8697     #define ETH_PCS1G_REG_PHY_ID_0_UNUSED_0                                                          (0xffff<<16) // reserved
8698     #define ETH_PCS1G_REG_PHY_ID_0_UNUSED_0_SHIFT                                                    16
8699 #define ETH_PCS1G_REG_PHY_ID_1                                                                       0x00000cUL //Access:R    DataWidth:0x20  PHY Identifier upper 16 bits  Chips: K2
8700     #define ETH_PCS1G_REG_PHY_ID_1_PHYID                                                             (0xffff<<0) // PHY Identifier from package file parameter PHY_IDENTIFIER upper 16 bits.
8701     #define ETH_PCS1G_REG_PHY_ID_1_PHYID_SHIFT                                                       0
8702     #define ETH_PCS1G_REG_PHY_ID_1_UNUSED_0                                                          (0xffff<<16) // reserved
8703     #define ETH_PCS1G_REG_PHY_ID_1_UNUSED_0_SHIFT                                                    16
8704 #define ETH_PCS1G_REG_DEV_ABILITY                                                                    0x000010UL //Access:RW   DataWidth:0x20  Local Device Abilities for Autonegotiation. Contents differs for 1000Base-X or SGMII mode.  Chips: K2
8705     #define ETH_PCS1G_REG_DEV_ABILITY_ABILITY_RSV05                                                  (0x1f<<0) // reserved; SGMII:=set to 1 to indicate SGMII to PHY
8706     #define ETH_PCS1G_REG_DEV_ABILITY_ABILITY_RSV05_SHIFT                                            0
8707     #define ETH_PCS1G_REG_DEV_ABILITY_FD                                                             (0x1<<5) // Indicate full-duplex support; SGMII:=reserved
8708     #define ETH_PCS1G_REG_DEV_ABILITY_FD_SHIFT                                                       5
8709     #define ETH_PCS1G_REG_DEV_ABILITY_HD                                                             (0x1<<6) // Indicate half-duplex support; SGMII:=reserved
8710     #define ETH_PCS1G_REG_DEV_ABILITY_HD_SHIFT                                                       6
8711     #define ETH_PCS1G_REG_DEV_ABILITY_PS1                                                            (0x1<<7) // Pause Support 1; SGMII:=reserved
8712     #define ETH_PCS1G_REG_DEV_ABILITY_PS1_SHIFT                                                      7
8713     #define ETH_PCS1G_REG_DEV_ABILITY_PS2                                                            (0x1<<8) // Pause Support 2; SGMII:=EEE clock stop enable to PHY
8714     #define ETH_PCS1G_REG_DEV_ABILITY_PS2_SHIFT                                                      8
8715     #define ETH_PCS1G_REG_DEV_ABILITY_ABILITY_RSV9                                                   (0x7<<9) // reserved; SGMII:=reserved
8716     #define ETH_PCS1G_REG_DEV_ABILITY_ABILITY_RSV9_SHIFT                                             9
8717     #define ETH_PCS1G_REG_DEV_ABILITY_RF1                                                            (0x1<<12) // Remote fault 1; SGMII:=reserved
8718     #define ETH_PCS1G_REG_DEV_ABILITY_RF1_SHIFT                                                      12
8719     #define ETH_PCS1G_REG_DEV_ABILITY_RF2                                                            (0x1<<13) // Remote fault 2; SGMII:=reserved
8720     #define ETH_PCS1G_REG_DEV_ABILITY_RF2_SHIFT                                                      13
8721     #define ETH_PCS1G_REG_DEV_ABILITY_ACK                                                            (0x1<<14) // Acknowledge during autonegotiation
8722     #define ETH_PCS1G_REG_DEV_ABILITY_ACK_SHIFT                                                      14
8723     #define ETH_PCS1G_REG_DEV_ABILITY_NP                                                             (0x1<<15) // Next Page support; SGMII:=reserved
8724     #define ETH_PCS1G_REG_DEV_ABILITY_NP_SHIFT                                                       15
8725     #define ETH_PCS1G_REG_DEV_ABILITY_UNUSED_0                                                       (0xffff<<16) // reserved
8726     #define ETH_PCS1G_REG_DEV_ABILITY_UNUSED_0_SHIFT                                                 16
8727 #define ETH_PCS1G_REG_PARTNER_ABILITY                                                                0x000014UL //Access:R    DataWidth:0x20  Received Abilities during Autonegotiation. Contents differ depending on 1000Base-X or SGMII mode.  Chips: K2
8728     #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV05                                             (0x1f<<0) // reserved; SGMII:=1
8729     #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV05_SHIFT                                       0
8730     #define ETH_PCS1G_REG_PARTNER_ABILITY_FD                                                         (0x1<<5) // Indicate full-duplex support; SGMII:=reserved
8731     #define ETH_PCS1G_REG_PARTNER_ABILITY_FD_SHIFT                                                   5
8732     #define ETH_PCS1G_REG_PARTNER_ABILITY_HD                                                         (0x1<<6) // Indicate half-duplex support; SGMII:=reserved
8733     #define ETH_PCS1G_REG_PARTNER_ABILITY_HD_SHIFT                                                   6
8734     #define ETH_PCS1G_REG_PARTNER_ABILITY_PS1                                                        (0x1<<7) // Pause Support 1; SGMII:=reserved
8735     #define ETH_PCS1G_REG_PARTNER_ABILITY_PS1_SHIFT                                                  7
8736     #define ETH_PCS1G_REG_PARTNER_ABILITY_PS2                                                        (0x1<<8) // Pause Support 2; SGMII:=EEE clock stop capability from PHY
8737     #define ETH_PCS1G_REG_PARTNER_ABILITY_PS2_SHIFT                                                  8
8738     #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV9                                              (0x1<<9) // reserved; SGMII:=EEE capability from PHY
8739     #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV9_SHIFT                                        9
8740     #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV10                                             (0x3<<10) // reserved; SGMII:=Copper Speed indication from PHY
8741     #define ETH_PCS1G_REG_PARTNER_ABILITY_PABILITY_RSV10_SHIFT                                       10
8742     #define ETH_PCS1G_REG_PARTNER_ABILITY_RF1                                                        (0x1<<12) // Remote fault 1; SGMII:=Copper Duplex status from PHY
8743     #define ETH_PCS1G_REG_PARTNER_ABILITY_RF1_SHIFT                                                  12
8744     #define ETH_PCS1G_REG_PARTNER_ABILITY_RF2                                                        (0x1<<13) // Remote fault 2; SGMII:=reserved
8745     #define ETH_PCS1G_REG_PARTNER_ABILITY_RF2_SHIFT                                                  13
8746     #define ETH_PCS1G_REG_PARTNER_ABILITY_ACK                                                        (0x1<<14) // Acknowledge during autonegotiation
8747     #define ETH_PCS1G_REG_PARTNER_ABILITY_ACK_SHIFT                                                  14
8748     #define ETH_PCS1G_REG_PARTNER_ABILITY_NP                                                         (0x1<<15) // Next Page support; SGMII:=Copper Link Status from PHY
8749     #define ETH_PCS1G_REG_PARTNER_ABILITY_NP_SHIFT                                                   15
8750     #define ETH_PCS1G_REG_PARTNER_ABILITY_UNUSED_0                                                   (0xffff<<16) // reserved
8751     #define ETH_PCS1G_REG_PARTNER_ABILITY_UNUSED_0_SHIFT                                             16
8752 #define ETH_PCS1G_REG_AN_EXPANSION                                                                   0x000018UL //Access:R    DataWidth:0x20  Autonegotiation Expansion Register  Chips: K2
8753     #define ETH_PCS1G_REG_AN_EXPANSION_UNUSED_0                                                      (0x1<<0) // reserved
8754     #define ETH_PCS1G_REG_AN_EXPANSION_UNUSED_0_SHIFT                                                0
8755     #define ETH_PCS1G_REG_AN_EXPANSION_PAGERECEIVED                                                  (0x1<<1) // Autoneg page received indication; latch-high
8756     #define ETH_PCS1G_REG_AN_EXPANSION_PAGERECEIVED_SHIFT                                            1
8757     #define ETH_PCS1G_REG_AN_EXPANSION_NEXTPAGEABLE                                                  (0x1<<2) // Indicate PCS supports next page exchange for autonegotiation
8758     #define ETH_PCS1G_REG_AN_EXPANSION_NEXTPAGEABLE_SHIFT                                            2
8759     #define ETH_PCS1G_REG_AN_EXPANSION_UNUSED_1                                                      (0x1fffffff<<3) // reserved
8760     #define ETH_PCS1G_REG_AN_EXPANSION_UNUSED_1_SHIFT                                                3
8761 #define ETH_PCS1G_REG_NP_TX                                                                          0x00001cUL //Access:RW   DataWidth:0x20  Next Page data to transmit  Chips: K2
8762     #define ETH_PCS1G_REG_NP_TX_DATA                                                                 (0x7ff<<0) // Next Page data
8763     #define ETH_PCS1G_REG_NP_TX_DATA_SHIFT                                                           0
8764     #define ETH_PCS1G_REG_NP_TX_TOGGLE                                                               (0x1<<11) // Next Page toggle handshaking bit
8765     #define ETH_PCS1G_REG_NP_TX_TOGGLE_SHIFT                                                         11
8766     #define ETH_PCS1G_REG_NP_TX_ACK2                                                                 (0x1<<12) // Next Page data acknowledge indication
8767     #define ETH_PCS1G_REG_NP_TX_ACK2_SHIFT                                                           12
8768     #define ETH_PCS1G_REG_NP_TX_MP                                                                   (0x1<<13) // Message Next Page type identification
8769     #define ETH_PCS1G_REG_NP_TX_MP_SHIFT                                                             13
8770     #define ETH_PCS1G_REG_NP_TX_ACK                                                                  (0x1<<14) // Acknowledge during page exchange
8771     #define ETH_PCS1G_REG_NP_TX_ACK_SHIFT                                                            14
8772     #define ETH_PCS1G_REG_NP_TX_NP                                                                   (0x1<<15) // Next Pages to follow indication
8773     #define ETH_PCS1G_REG_NP_TX_NP_SHIFT                                                             15
8774     #define ETH_PCS1G_REG_NP_TX_UNUSED_0                                                             (0xffff<<16) // reserved
8775     #define ETH_PCS1G_REG_NP_TX_UNUSED_0_SHIFT                                                       16
8776 #define ETH_PCS1G_REG_LP_NP_RX                                                                       0x000020UL //Access:R    DataWidth:0x20  Received Next Page data from link partner  Chips: K2
8777     #define ETH_PCS1G_REG_LP_NP_RX_DATA                                                              (0x7ff<<0) // Next Page data
8778     #define ETH_PCS1G_REG_LP_NP_RX_DATA_SHIFT                                                        0
8779     #define ETH_PCS1G_REG_LP_NP_RX_TOGGLE                                                            (0x1<<11) // Next Page toggle handshaking bit
8780     #define ETH_PCS1G_REG_LP_NP_RX_TOGGLE_SHIFT                                                      11
8781     #define ETH_PCS1G_REG_LP_NP_RX_ACK2                                                              (0x1<<12) // Next Page data acknowledge indication
8782     #define ETH_PCS1G_REG_LP_NP_RX_ACK2_SHIFT                                                        12
8783     #define ETH_PCS1G_REG_LP_NP_RX_MP                                                                (0x1<<13) // Message Next Page type identification
8784     #define ETH_PCS1G_REG_LP_NP_RX_MP_SHIFT                                                          13
8785     #define ETH_PCS1G_REG_LP_NP_RX_ACK                                                               (0x1<<14) // Acknowledge during page exchange
8786     #define ETH_PCS1G_REG_LP_NP_RX_ACK_SHIFT                                                         14
8787     #define ETH_PCS1G_REG_LP_NP_RX_NP                                                                (0x1<<15) // Next Pages to follow indication
8788     #define ETH_PCS1G_REG_LP_NP_RX_NP_SHIFT                                                          15
8789     #define ETH_PCS1G_REG_LP_NP_RX_UNUSED_0                                                          (0xffff<<16) // reserved
8790     #define ETH_PCS1G_REG_LP_NP_RX_UNUSED_0_SHIFT                                                    16
8791 #define ETH_PCS1G_REG_SCRATCH                                                                        0x000040UL //Access:RW   DataWidth:0x20  General Purpose Test register  Chips: K2
8792     #define ETH_PCS1G_REG_SCRATCH_SCRATCH                                                            (0xffff<<0) // Arbitrary value for read/write test
8793     #define ETH_PCS1G_REG_SCRATCH_SCRATCH_SHIFT                                                      0
8794     #define ETH_PCS1G_REG_SCRATCH_UNUSED_0                                                           (0xffff<<16) // reserved
8795     #define ETH_PCS1G_REG_SCRATCH_UNUSED_0_SHIFT                                                     16
8796 #define ETH_PCS1G_REG_REV                                                                            0x000044UL //Access:R    DataWidth:0x20  Core Revision  Chips: K2
8797     #define ETH_PCS1G_REG_REV_REVISION                                                               (0xffff<<0) // from package parameter DEV_VERSION
8798     #define ETH_PCS1G_REG_REV_REVISION_SHIFT                                                         0
8799     #define ETH_PCS1G_REG_REV_UNUSED_0                                                               (0xffff<<16) // reserved
8800     #define ETH_PCS1G_REG_REV_UNUSED_0_SHIFT                                                         16
8801 #define ETH_PCS1G_REG_LINK_TIMER_0                                                                   0x000048UL //Access:RW   DataWidth:0x20  Autonegotiation link timer lower 16 bits  Chips: K2
8802     #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER0                                                        (0x1<<0) // Bit 0 of link timer value; not writeable and always 0
8803     #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER0_SHIFT                                                  0
8804     #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER15_1                                                     (0x7fff<<1) // Bits 15:1 of link timer value
8805     #define ETH_PCS1G_REG_LINK_TIMER_0_TIMER15_1_SHIFT                                               1
8806     #define ETH_PCS1G_REG_LINK_TIMER_0_UNUSED_0                                                      (0xffff<<16) // reserved
8807     #define ETH_PCS1G_REG_LINK_TIMER_0_UNUSED_0_SHIFT                                                16
8808 #define ETH_PCS1G_REG_LINK_TIMER_1                                                                   0x00004cUL //Access:RW   DataWidth:0x20  Autonegotiation link timer uppest 5 bits  Chips: K2
8809     #define ETH_PCS1G_REG_LINK_TIMER_1_TIMER20_16                                                    (0x1f<<0) // Link timer uppest 5 bits of 21bit timer
8810     #define ETH_PCS1G_REG_LINK_TIMER_1_TIMER20_16_SHIFT                                              0
8811     #define ETH_PCS1G_REG_LINK_TIMER_1_UNUSED_0                                                      (0x7ffffff<<5) // reserved
8812     #define ETH_PCS1G_REG_LINK_TIMER_1_UNUSED_0_SHIFT                                                5
8813 #define ETH_PCS1G_REG_IF_MODE                                                                        0x000050UL //Access:RW   DataWidth:0x20  SGMII Mode Control  Chips: K2
8814     #define ETH_PCS1G_REG_IF_MODE_SGMII_ENA                                                          (0x1<<0) // Enable SGMII mode
8815     #define ETH_PCS1G_REG_IF_MODE_SGMII_ENA_SHIFT                                                    0
8816     #define ETH_PCS1G_REG_IF_MODE_USE_SGMII_AN                                                       (0x1<<1) // Use the SGMII autonegotiation results to set SGMII speed
8817     #define ETH_PCS1G_REG_IF_MODE_USE_SGMII_AN_SHIFT                                                 1
8818     #define ETH_PCS1G_REG_IF_MODE_SGMII_SPEED                                                        (0x3<<2) // Set SGMII speed when not using autonegotiation
8819     #define ETH_PCS1G_REG_IF_MODE_SGMII_SPEED_SHIFT                                                  2
8820     #define ETH_PCS1G_REG_IF_MODE_SGMII_DUPLEX                                                       (0x1<<4) // Set SGMII half-duplex mode when not using autonegotiation
8821     #define ETH_PCS1G_REG_IF_MODE_SGMII_DUPLEX_SHIFT                                                 4
8822     #define ETH_PCS1G_REG_IF_MODE_IFMODE_RSV5                                                        (0x1<<5) // reserved; writeable for backward compatibility; write 0 always
8823     #define ETH_PCS1G_REG_IF_MODE_IFMODE_RSV5_SHIFT                                                  5
8824     #define ETH_PCS1G_REG_IF_MODE_UNUSED_0                                                           (0x3ffffff<<6) // reserved
8825     #define ETH_PCS1G_REG_IF_MODE_UNUSED_0_SHIFT                                                     6
8826 #define ETH_PCS1G_REG_DECODE_ERRORS                                                                  0x000054UL //Access:RW   DataWidth:0x20  10B decoder error counter for test/debug; May not exist in all Core Variants;  Chips: K2
8827     #define ETH_PCS1G_REG_DECODE_ERRORS_ERRORS                                                       (0xffff<<0) // RX 10B/8B code errors; May not be supported in all Core variants; Counter is not accurate and intended only to be of help during test/debug; Clears when writing CONTROL.15 or CONTROL.10 with 1.
8828     #define ETH_PCS1G_REG_DECODE_ERRORS_ERRORS_SHIFT                                                 0
8829     #define ETH_PCS1G_REG_DECODE_ERRORS_UNUSED_0                                                     (0xffff<<16) // reserved
8830     #define ETH_PCS1G_REG_DECODE_ERRORS_UNUSED_0_SHIFT                                               16
8831 #define ETH_PCS10_50G_REG_CONTROL1                                                                   0x000000UL //Access:RW   DataWidth:0x20  PCS Control.  Chips: K2
8832     #define ETH_PCS10_50G_REG_CONTROL1_UNUSED_0                                                      (0x3<<0) // reserved
8833     #define ETH_PCS10_50G_REG_CONTROL1_UNUSED_0_SHIFT                                                0
8834     #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECTION                                               (0xf<<2) // 0011 = 40 Gb/s; 0000 = 10Gb/s.
8835     #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECTION_SHIFT                                         2
8836     #define ETH_PCS10_50G_REG_CONTROL1_SPEED_ALWAYS1                                                 (0x1<<6) // Always 1.
8837     #define ETH_PCS10_50G_REG_CONTROL1_SPEED_ALWAYS1_SHIFT                                           6
8838     #define ETH_PCS10_50G_REG_CONTROL1_UNUSED_1                                                      (0xf<<7) // reserved
8839     #define ETH_PCS10_50G_REG_CONTROL1_UNUSED_1_SHIFT                                                7
8840     #define ETH_PCS10_50G_REG_CONTROL1_LOW_POWER                                                     (0x1<<11) // 0=normal operation (Always 0).
8841     #define ETH_PCS10_50G_REG_CONTROL1_LOW_POWER_SHIFT                                               11
8842     #define ETH_PCS10_50G_REG_CONTROL1_UNUSED_2                                                      (0x1<<12) // reserved
8843     #define ETH_PCS10_50G_REG_CONTROL1_UNUSED_2_SHIFT                                                12
8844     #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECT_ALWAYS1                                          (0x1<<13) // Always 1.
8845     #define ETH_PCS10_50G_REG_CONTROL1_SPEED_SELECT_ALWAYS1_SHIFT                                    13
8846     #define ETH_PCS10_50G_REG_CONTROL1_LOOPBACK                                                      (0x1<<14) // 1=Enable loopback, 0=disable loopback.
8847     #define ETH_PCS10_50G_REG_CONTROL1_LOOPBACK_SHIFT                                                14
8848     #define ETH_PCS10_50G_REG_CONTROL1_RESET                                                         (0x1<<15) // 1=PCS reset, 0=normal; Self clearing.
8849     #define ETH_PCS10_50G_REG_CONTROL1_RESET_SHIFT                                                   15
8850     #define ETH_PCS10_50G_REG_CONTROL1_UNUSED_3                                                      (0xffff<<16) // reserved
8851     #define ETH_PCS10_50G_REG_CONTROL1_UNUSED_3_SHIFT                                                16
8852 #define ETH_PCS10_50G_REG_STATUS1                                                                    0x000004UL //Access:R    DataWidth:0x20  PCS Status.  Chips: K2
8853     #define ETH_PCS10_50G_REG_STATUS1_UNUSED_0                                                       (0x1<<0) // reserved
8854     #define ETH_PCS10_50G_REG_STATUS1_UNUSED_0_SHIFT                                                 0
8855     #define ETH_PCS10_50G_REG_STATUS1_LOW_POWER_ABILITY                                              (0x1<<1) // Set to 1 to indicate that the PCS implements a low power mode.
8856     #define ETH_PCS10_50G_REG_STATUS1_LOW_POWER_ABILITY_SHIFT                                        1
8857     #define ETH_PCS10_50G_REG_STATUS1_PCS_RECEIVE_LINK                                               (0x1<<2) // When 1, indicates PCS receive link up; When ?0?, indicates PCS receive link is or was down (latching low).
8858     #define ETH_PCS10_50G_REG_STATUS1_PCS_RECEIVE_LINK_SHIFT                                         2
8859     #define ETH_PCS10_50G_REG_STATUS1_UNUSED_1                                                       (0xf<<3) // reserved
8860     #define ETH_PCS10_50G_REG_STATUS1_UNUSED_1_SHIFT                                                 3
8861     #define ETH_PCS10_50G_REG_STATUS1_FAULT                                                          (0x1<<7) // When 1, indicates a fault condition idetected; When ?0?, indicates that no fault condition is detected.
8862     #define ETH_PCS10_50G_REG_STATUS1_FAULT_SHIFT                                                    7
8863     #define ETH_PCS10_50G_REG_STATUS1_RX_LPI_ACTIVE                                                  (0x1<<8) // 1: receive is currently in LPI state;  0: normal operation.
8864     #define ETH_PCS10_50G_REG_STATUS1_RX_LPI_ACTIVE_SHIFT                                            8
8865     #define ETH_PCS10_50G_REG_STATUS1_TX_LPI_ACTIVE                                                  (0x1<<9) // 1: transmit is currently in LPI state;  0: normal operation.
8866     #define ETH_PCS10_50G_REG_STATUS1_TX_LPI_ACTIVE_SHIFT                                            9
8867     #define ETH_PCS10_50G_REG_STATUS1_RX_LPI                                                         (0x1<<10) // 1: receive is or was in LPI state;  0: normal operation; Latching high.
8868     #define ETH_PCS10_50G_REG_STATUS1_RX_LPI_SHIFT                                                   10
8869     #define ETH_PCS10_50G_REG_STATUS1_TX_LPI                                                         (0x1<<11) // 1: transmit is or was in LPI state;  0: normal operation; Latching high.
8870     #define ETH_PCS10_50G_REG_STATUS1_TX_LPI_SHIFT                                                   11
8871     #define ETH_PCS10_50G_REG_STATUS1_UNUSED_2                                                       (0xfffff<<12) // reserved
8872     #define ETH_PCS10_50G_REG_STATUS1_UNUSED_2_SHIFT                                                 12
8873 #define ETH_PCS10_50G_REG_DEVICE_ID0                                                                 0x000008UL //Access:R    DataWidth:0x20  PHY Identifier constant from package parameter PHY_IDENTIFIER bits 15:4. Bits 3:0 always 0.  Chips: K2
8874     #define ETH_PCS10_50G_REG_DEVICE_ID0_IDENTIFIER                                                  (0xffff<<0) // Bits 15:0 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
8875     #define ETH_PCS10_50G_REG_DEVICE_ID0_IDENTIFIER_SHIFT                                            0
8876     #define ETH_PCS10_50G_REG_DEVICE_ID0_UNUSED_0                                                    (0xffff<<16) // reserved
8877     #define ETH_PCS10_50G_REG_DEVICE_ID0_UNUSED_0_SHIFT                                              16
8878 #define ETH_PCS10_50G_REG_DEVICE_ID1                                                                 0x00000cUL //Access:R    DataWidth:0x20  PHY Identifier constant from package parameter PHY_IDENTIFIER bits 31:16.  Chips: K2
8879     #define ETH_PCS10_50G_REG_DEVICE_ID1_IDENTIFIER                                                  (0xffff<<0) // Bits 31:16 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
8880     #define ETH_PCS10_50G_REG_DEVICE_ID1_IDENTIFIER_SHIFT                                            0
8881     #define ETH_PCS10_50G_REG_DEVICE_ID1_UNUSED_0                                                    (0xffff<<16) // reserved
8882     #define ETH_PCS10_50G_REG_DEVICE_ID1_UNUSED_0_SHIFT                                              16
8883 #define ETH_PCS10_50G_REG_SPEED_ABILITY                                                              0x000010UL //Access:R    DataWidth:0x20  PCS supported speeds (values as defined by standard only, no proprietary speeds).  Chips: K2
8884     #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10GETH                                                  (0x1<<0) // When 1, this PCS is 10Geth capable.
8885     #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10GETH_SHIFT                                            0
8886     #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10PASS_TS                                               (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
8887     #define ETH_PCS10_50G_REG_SPEED_ABILITY_C10PASS_TS_SHIFT                                         1
8888     #define ETH_PCS10_50G_REG_SPEED_ABILITY_C40G                                                     (0x1<<2) // When 1, this PCS is 40G capable.
8889     #define ETH_PCS10_50G_REG_SPEED_ABILITY_C40G_SHIFT                                               2
8890     #define ETH_PCS10_50G_REG_SPEED_ABILITY_C100G                                                    (0x1<<3) // When 1, this PCS is 100G capable.
8891     #define ETH_PCS10_50G_REG_SPEED_ABILITY_C100G_SHIFT                                              3
8892     #define ETH_PCS10_50G_REG_SPEED_ABILITY_UNUSED_0                                                 (0xfffffff<<4) // reserved
8893     #define ETH_PCS10_50G_REG_SPEED_ABILITY_UNUSED_0_SHIFT                                           4
8894 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1                                                            0x000014UL //Access:R    DataWidth:0x20  Constant indicating PCS presence.  Chips: K2
8895     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_CLAUSE22                                               (0x1<<0) // Clause 22 registers present when 1.
8896     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_CLAUSE22_SHIFT                                         0
8897     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PMD_PMA                                                (0x1<<1) // PMD/PMA present when 1.
8898     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PMD_PMA_SHIFT                                          1
8899     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_WIS_PRES                                               (0x1<<2) // WIS present when 1.
8900     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_WIS_PRES_SHIFT                                         2
8901     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PCS_PRES                                               (0x1<<3) // PCS present when 1.
8902     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PCS_PRES_SHIFT                                         3
8903     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PHY_XS                                                 (0x1<<4) // PHY XS present when 1.
8904     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_PHY_XS_SHIFT                                           4
8905     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_DTE_XS                                                 (0x1<<5) // DTE XS present when 1.
8906     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_DTE_XS_SHIFT                                           5
8907     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_TC_PRES                                                (0x1<<6) // TC present when 1.
8908     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_TC_PRES_SHIFT                                          6
8909     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_UNUSED_0                                               (0x1ffffff<<7) // reserved
8910     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG1_UNUSED_0_SHIFT                                         7
8911 #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2                                                            0x000018UL //Access:R    DataWidth:0x20  Vendor specific presence.  Chips: K2
8912     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_UNUSED_0                                               (0x1fff<<0) // reserved
8913     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_UNUSED_0_SHIFT                                         0
8914     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_CLAUSE22                                               (0x1<<13) // Clause 22 extension present
8915     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_CLAUSE22_SHIFT                                         13
8916     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE1                                                (0x1<<14) // Vendor specific device 1 present
8917     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE1_SHIFT                                          14
8918     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE2                                                (0x1<<15) // Vendor specific device 2 present
8919     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_DEVICE2_SHIFT                                          15
8920     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_UNUSED_1                                               (0xffff<<16) // reserved
8921     #define ETH_PCS10_50G_REG_DEVICES_IN_PKG2_UNUSED_1_SHIFT                                         16
8922 #define ETH_PCS10_50G_REG_CONTROL2                                                                   0x00001cUL //Access:RW   DataWidth:0x20  Operating speed indication/control.  Chips: K2
8923     #define ETH_PCS10_50G_REG_CONTROL2_PCS_TYPE                                                      (0x7<<0) // PCS type selection; Writing 0 sets PCS_MODE to 0x03 setting Clause 49 mode and disabling MLD.
8924     #define ETH_PCS10_50G_REG_CONTROL2_PCS_TYPE_SHIFT                                                0
8925     #define ETH_PCS10_50G_REG_CONTROL2_UNUSED_0                                                      (0x1fffffff<<3) // reserved
8926     #define ETH_PCS10_50G_REG_CONTROL2_UNUSED_0_SHIFT                                                3
8927 #define ETH_PCS10_50G_REG_STATUS2                                                                    0x000020UL //Access:R    DataWidth:0x20  Fault status; Device capabilities  Chips: K2
8928     #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_R                                                     (0x1<<0) // When 1, this PCS is 10GBase-R capable.
8929     #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_R_SHIFT                                               0
8930     #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_X                                                     (0x1<<1) // When 1, this PCS is 10GBase-X capable.
8931     #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_X_SHIFT                                               1
8932     #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_W                                                     (0x1<<2) // When 1, this PCS is 10GBase-W capable.
8933     #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_W_SHIFT                                               2
8934     #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_T                                                     (0x1<<3) // When 1, this PCS is 10GBase-T capable.
8935     #define ETH_PCS10_50G_REG_STATUS2_C10GBASE_T_SHIFT                                               3
8936     #define ETH_PCS10_50G_REG_STATUS2_C40GBASE_R                                                     (0x1<<4) // When 1, this PCS is 40GBase-R capable.
8937     #define ETH_PCS10_50G_REG_STATUS2_C40GBASE_R_SHIFT                                               4
8938     #define ETH_PCS10_50G_REG_STATUS2_C100GBASE_R                                                    (0x1<<5) // When 1, this PCS is 100GBase-R capable.
8939     #define ETH_PCS10_50G_REG_STATUS2_C100GBASE_R_SHIFT                                              5
8940     #define ETH_PCS10_50G_REG_STATUS2_UNUSED_0                                                       (0xf<<6) // reserved
8941     #define ETH_PCS10_50G_REG_STATUS2_UNUSED_0_SHIFT                                                 6
8942     #define ETH_PCS10_50G_REG_STATUS2_RECEIVE_FAULT                                                  (0x1<<10) // Receive fault. 1=Fault condition on receive path. Latched high
8943     #define ETH_PCS10_50G_REG_STATUS2_RECEIVE_FAULT_SHIFT                                            10
8944     #define ETH_PCS10_50G_REG_STATUS2_TRANSMIT_FAULT                                                 (0x1<<11) // Transmit fault. 1=Fault condition on transmit path. Latched high
8945     #define ETH_PCS10_50G_REG_STATUS2_TRANSMIT_FAULT_SHIFT                                           11
8946     #define ETH_PCS10_50G_REG_STATUS2_UNUSED_1                                                       (0x3<<12) // reserved
8947     #define ETH_PCS10_50G_REG_STATUS2_UNUSED_1_SHIFT                                                 12
8948     #define ETH_PCS10_50G_REG_STATUS2_DEVICE_PRESENT                                                 (0x3<<14) // Device present. When bits are 10 = device responding at this address.
8949     #define ETH_PCS10_50G_REG_STATUS2_DEVICE_PRESENT_SHIFT                                           14
8950     #define ETH_PCS10_50G_REG_STATUS2_UNUSED_2                                                       (0xffff<<16) // reserved
8951     #define ETH_PCS10_50G_REG_STATUS2_UNUSED_2_SHIFT                                                 16
8952 #define ETH_PCS10_50G_REG_PKG_ID0                                                                    0x000038UL //Access:R    DataWidth:0x20  Constant from package parameter PACK_IDENTIFIER bits 15:0.  Chips: K2
8953     #define ETH_PCS10_50G_REG_PKG_ID0_IDENTIFIER                                                     (0xffff<<0) // Constant from package parameter PACK_IDENTIFIER bits 15:0.
8954     #define ETH_PCS10_50G_REG_PKG_ID0_IDENTIFIER_SHIFT                                               0
8955     #define ETH_PCS10_50G_REG_PKG_ID0_UNUSED_0                                                       (0xffff<<16) // reserved
8956     #define ETH_PCS10_50G_REG_PKG_ID0_UNUSED_0_SHIFT                                                 16
8957 #define ETH_PCS10_50G_REG_PKG_ID1                                                                    0x00003cUL //Access:R    DataWidth:0x20  Constant from package parameter PACK_IDENTIFIER bits 31:16.  Chips: K2
8958     #define ETH_PCS10_50G_REG_PKG_ID1_IDENTIFIER                                                     (0xffff<<0) // Constant from package parameter PACK_IDENTIFIER bits 31:16.
8959     #define ETH_PCS10_50G_REG_PKG_ID1_IDENTIFIER_SHIFT                                               0
8960     #define ETH_PCS10_50G_REG_PKG_ID1_UNUSED_0                                                       (0xffff<<16) // reserved
8961     #define ETH_PCS10_50G_REG_PKG_ID1_UNUSED_0_SHIFT                                                 16
8962 #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY                                                        0x000050UL //Access:RW   DataWidth:0x20  EEE Control and Capabilities (exists only if EEE is available).  Chips: K2
8963     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_LPI_FW                                             (0x1<<0) // Mode for selecting select 40G EEE mode; 1 = Fast wake mode; 0 = Deep sleep for LPI function.
8964     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_LPI_FW_SHIFT                                       0
8965     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_UNUSED_0                                           (0x1f<<1) // reserved
8966     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_UNUSED_0_SHIFT                                     1
8967     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR                                     (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
8968     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR_SHIFT                               6
8969     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_UNUSED_1                                           (0x1<<7) // reserved
8970     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_UNUSED_1_SHIFT                                     7
8971     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE                                 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
8972     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_SHIFT                           8
8973     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP                                 (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
8974     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP_SHIFT                           9
8975     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_UNUSED_2                                           (0x3fffff<<10) // reserved
8976     #define ETH_PCS10_50G_REG_EEE_CTRL_CAPABILITY_UNUSED_2_SHIFT                                     10
8977 #define ETH_PCS10_50G_REG_WAKE_ERR_COUNTER                                                           0x000058UL //Access:R    DataWidth:0x20  EEE Wake error counter (exists only if EEE is available); Clears on read.  Chips: K2
8978     #define ETH_PCS10_50G_REG_WAKE_ERR_COUNTER_COUNTER                                               (0xffff<<0) // Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
8979     #define ETH_PCS10_50G_REG_WAKE_ERR_COUNTER_COUNTER_SHIFT                                         0
8980     #define ETH_PCS10_50G_REG_WAKE_ERR_COUNTER_UNUSED_0                                              (0xffff<<16) // reserved
8981     #define ETH_PCS10_50G_REG_WAKE_ERR_COUNTER_UNUSED_0_SHIFT                                        16
8982 #define ETH_PCS10_50G_REG_BASER_STATUS1                                                              0x000080UL //Access:R    DataWidth:0x20  Link Status Information.  Chips: K2
8983     #define ETH_PCS10_50G_REG_BASER_STATUS1_BLOCK_LOCK                                               (0x1<<0) // 1=PCS locked to received blocks.
8984     #define ETH_PCS10_50G_REG_BASER_STATUS1_BLOCK_LOCK_SHIFT                                         0
8985     #define ETH_PCS10_50G_REG_BASER_STATUS1_HIGH_BER                                                 (0x1<<1) // 1=PCS reporting a high BER.
8986     #define ETH_PCS10_50G_REG_BASER_STATUS1_HIGH_BER_SHIFT                                           1
8987     #define ETH_PCS10_50G_REG_BASER_STATUS1_UNUSED_0                                                 (0x3ff<<2) // reserved
8988     #define ETH_PCS10_50G_REG_BASER_STATUS1_UNUSED_0_SHIFT                                           2
8989     #define ETH_PCS10_50G_REG_BASER_STATUS1_RECEIVE_LINK                                             (0x1<<12) // Receive link status. 1=Link up; 0=link down.
8990     #define ETH_PCS10_50G_REG_BASER_STATUS1_RECEIVE_LINK_SHIFT                                       12
8991     #define ETH_PCS10_50G_REG_BASER_STATUS1_UNUSED_1                                                 (0x7ffff<<13) // reserved
8992     #define ETH_PCS10_50G_REG_BASER_STATUS1_UNUSED_1_SHIFT                                           13
8993 #define ETH_PCS10_50G_REG_BASER_STATUS2                                                              0x000084UL //Access:R    DataWidth:0x20  Link Status latches and error counters.  Chips: K2
8994     #define ETH_PCS10_50G_REG_BASER_STATUS2_ERRORED_CNT                                              (0xff<<0) // Errored blocks counter; None roll-over.
8995     #define ETH_PCS10_50G_REG_BASER_STATUS2_ERRORED_CNT_SHIFT                                        0
8996     #define ETH_PCS10_50G_REG_BASER_STATUS2_BER_COUNTER                                              (0x3f<<8) // BER counter; None roll-over.
8997     #define ETH_PCS10_50G_REG_BASER_STATUS2_BER_COUNTER_SHIFT                                        8
8998     #define ETH_PCS10_50G_REG_BASER_STATUS2_HIGH_BER                                                 (0x1<<14) // BER flag; Latched high.
8999     #define ETH_PCS10_50G_REG_BASER_STATUS2_HIGH_BER_SHIFT                                           14
9000     #define ETH_PCS10_50G_REG_BASER_STATUS2_BLOCK_LOCK                                               (0x1<<15) // Block Lock; Latched low.
9001     #define ETH_PCS10_50G_REG_BASER_STATUS2_BLOCK_LOCK_SHIFT                                         15
9002     #define ETH_PCS10_50G_REG_BASER_STATUS2_UNUSED_0                                                 (0xffff<<16) // reserved
9003     #define ETH_PCS10_50G_REG_BASER_STATUS2_UNUSED_0_SHIFT                                           16
9004 #define ETH_PCS10_50G_REG_SEED_A0                                                                    0x000088UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed A bits 15:0.  Chips: K2
9005     #define ETH_PCS10_50G_REG_SEED_A0_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 15:0.
9006     #define ETH_PCS10_50G_REG_SEED_A0_SEED_SHIFT                                                     0
9007     #define ETH_PCS10_50G_REG_SEED_A0_UNUSED_0                                                       (0xffff<<16) // reserved
9008     #define ETH_PCS10_50G_REG_SEED_A0_UNUSED_0_SHIFT                                                 16
9009 #define ETH_PCS10_50G_REG_SEED_A1                                                                    0x00008cUL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed A bits 31:16.  Chips: K2
9010     #define ETH_PCS10_50G_REG_SEED_A1_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 31:16.
9011     #define ETH_PCS10_50G_REG_SEED_A1_SEED_SHIFT                                                     0
9012     #define ETH_PCS10_50G_REG_SEED_A1_UNUSED_0                                                       (0xffff<<16) // reserved
9013     #define ETH_PCS10_50G_REG_SEED_A1_UNUSED_0_SHIFT                                                 16
9014 #define ETH_PCS10_50G_REG_SEED_A2                                                                    0x000090UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed A bits 47:32.  Chips: K2
9015     #define ETH_PCS10_50G_REG_SEED_A2_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 47:32.
9016     #define ETH_PCS10_50G_REG_SEED_A2_SEED_SHIFT                                                     0
9017     #define ETH_PCS10_50G_REG_SEED_A2_UNUSED_0                                                       (0xffff<<16) // reserved
9018     #define ETH_PCS10_50G_REG_SEED_A2_UNUSED_0_SHIFT                                                 16
9019 #define ETH_PCS10_50G_REG_SEED_A3                                                                    0x000094UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed A bits 57:48.  Chips: K2
9020     #define ETH_PCS10_50G_REG_SEED_A3_SEED                                                           (0x3ff<<0) // 10GBase-R Test Pattern Seed A: Bits 57:48.
9021     #define ETH_PCS10_50G_REG_SEED_A3_SEED_SHIFT                                                     0
9022     #define ETH_PCS10_50G_REG_SEED_A3_UNUSED_0                                                       (0x3fffff<<10) // reserved
9023     #define ETH_PCS10_50G_REG_SEED_A3_UNUSED_0_SHIFT                                                 10
9024 #define ETH_PCS10_50G_REG_SEED_B0                                                                    0x000098UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed B bits 15:0.  Chips: K2
9025     #define ETH_PCS10_50G_REG_SEED_B0_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 15:0.
9026     #define ETH_PCS10_50G_REG_SEED_B0_SEED_SHIFT                                                     0
9027     #define ETH_PCS10_50G_REG_SEED_B0_UNUSED_0                                                       (0xffff<<16) // reserved
9028     #define ETH_PCS10_50G_REG_SEED_B0_UNUSED_0_SHIFT                                                 16
9029 #define ETH_PCS10_50G_REG_SEED_B1                                                                    0x00009cUL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed B bits 31:16.  Chips: K2
9030     #define ETH_PCS10_50G_REG_SEED_B1_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 31:16.
9031     #define ETH_PCS10_50G_REG_SEED_B1_SEED_SHIFT                                                     0
9032     #define ETH_PCS10_50G_REG_SEED_B1_UNUSED_0                                                       (0xffff<<16) // reserved
9033     #define ETH_PCS10_50G_REG_SEED_B1_UNUSED_0_SHIFT                                                 16
9034 #define ETH_PCS10_50G_REG_SEED_B2                                                                    0x0000a0UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed B bits 47:32.  Chips: K2
9035     #define ETH_PCS10_50G_REG_SEED_B2_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 47:32.
9036     #define ETH_PCS10_50G_REG_SEED_B2_SEED_SHIFT                                                     0
9037     #define ETH_PCS10_50G_REG_SEED_B2_UNUSED_0                                                       (0xffff<<16) // reserved
9038     #define ETH_PCS10_50G_REG_SEED_B2_UNUSED_0_SHIFT                                                 16
9039 #define ETH_PCS10_50G_REG_SEED_B3                                                                    0x0000a4UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed B bits 57:48.  Chips: K2
9040     #define ETH_PCS10_50G_REG_SEED_B3_SEED                                                           (0x3ff<<0) // 10GBase-R Test Pattern Seed B: Bits 57:48.
9041     #define ETH_PCS10_50G_REG_SEED_B3_SEED_SHIFT                                                     0
9042     #define ETH_PCS10_50G_REG_SEED_B3_UNUSED_0                                                       (0x3fffff<<10) // reserved
9043     #define ETH_PCS10_50G_REG_SEED_B3_UNUSED_0_SHIFT                                                 10
9044 #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL                                                         0x0000a8UL //Access:RW   DataWidth:0x20  Test Pattern Generator and Checker controls.  Chips: K2
9045     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL                                    (0x1<<0) // Data Pattern Select: 1=all Zero, 0=2x Local Fault; 10G only.
9046     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL_SHIFT                              0
9047     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_SQUARE                                       (0x1<<1) // Select Square Wave (1) or Pseudo Random (0) test pattern; 10G only.
9048     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_SQUARE_SHIFT                                 1
9049     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN                                      (0x1<<2) // Receive test-pattern enable.
9050     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN_SHIFT                                2
9051     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN                                      (0x1<<3) // Transmit test-pattern enable.
9052     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN_SHIFT                                3
9053     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_UNUSED_0                                            (0x7<<4) // reserved
9054     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_UNUSED_0_SHIFT                                      4
9055     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_RANDOM                                       (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
9056     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_SELECT_RANDOM_SHIFT                                 7
9057     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_UNUSED_1                                            (0xffffff<<8) // reserved
9058     #define ETH_PCS10_50G_REG_BASER_TEST_CONTROL_UNUSED_1_SHIFT                                      8
9059 #define ETH_PCS10_50G_REG_BASER_TEST_ERR_CNT                                                         0x0000acUL //Access:R    DataWidth:0x20  Test Pattern Error Counter; Clears on read; None roll-over.  Chips: K2
9060     #define ETH_PCS10_50G_REG_BASER_TEST_ERR_CNT_COUNTER                                             (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
9061     #define ETH_PCS10_50G_REG_BASER_TEST_ERR_CNT_COUNTER_SHIFT                                       0
9062     #define ETH_PCS10_50G_REG_BASER_TEST_ERR_CNT_UNUSED_0                                            (0xffff<<16) // reserved
9063     #define ETH_PCS10_50G_REG_BASER_TEST_ERR_CNT_UNUSED_0_SHIFT                                      16
9064 #define ETH_PCS10_50G_REG_BER_HIGH_ORDER_CNT                                                         0x0000b0UL //Access:R    DataWidth:0x20  BER High Order Counter of BER bits 21:6; None roll-over.  Chips: K2
9065     #define ETH_PCS10_50G_REG_BER_HIGH_ORDER_CNT_BER_COUNTER                                         (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
9066     #define ETH_PCS10_50G_REG_BER_HIGH_ORDER_CNT_BER_COUNTER_SHIFT                                   0
9067     #define ETH_PCS10_50G_REG_BER_HIGH_ORDER_CNT_UNUSED_0                                            (0xffff<<16) // reserved
9068     #define ETH_PCS10_50G_REG_BER_HIGH_ORDER_CNT_UNUSED_0_SHIFT                                      16
9069 #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT                                                     0x0000b4UL //Access:R    DataWidth:0x20  Error Blocks High Order Counter bits 21:8; None roll-over.  Chips: K2
9070     #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER                          (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
9071     #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER_SHIFT                    0
9072     #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_UNUSED_0                                        (0x1<<14) // reserved
9073     #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_UNUSED_0_SHIFT                                  14
9074     #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT                              (0x1<<15) // High order counter present; Always 1.
9075     #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT_SHIFT                        15
9076     #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_UNUSED_1                                        (0xffff<<16) // reserved
9077     #define ETH_PCS10_50G_REG_ERR_BLK_HIGH_ORDER_CNT_UNUSED_1_SHIFT                                  16
9078 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1                                                      0x0000c8UL //Access:R    DataWidth:0x20  Lane Alignment Status Bits and Block Lock.  Chips: K2
9079     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE0_BLOCK_LOCK                                 (0x1<<0) // Lane 0 block lock.
9080     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE0_BLOCK_LOCK_SHIFT                           0
9081     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE1_BLOCK_LOCK                                 (0x1<<1) // Lane 1 block lock.
9082     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE1_BLOCK_LOCK_SHIFT                           1
9083     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE2_BLOCK_LOCK                                 (0x1<<2) // Lane 2 block lock.
9084     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE2_BLOCK_LOCK_SHIFT                           2
9085     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE3_BLOCK_LOCK                                 (0x1<<3) // Lane 3 block lock.
9086     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE3_BLOCK_LOCK_SHIFT                           3
9087     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_UNUSED_0                                         (0xff<<4) // reserved
9088     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_UNUSED_0_SHIFT                                   4
9089     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS                                (0x1<<12) // Lane alignment status; 1=All Receive lanes locked and aligned.
9090     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS_SHIFT                          12
9091     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_UNUSED_1                                         (0x7ffff<<13) // reserved
9092     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT1_UNUSED_1_SHIFT                                   13
9093 #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3                                                      0x0000d0UL //Access:R    DataWidth:0x20  Lane Alignment Marker Lock Status bits.  Chips: K2
9094     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK                                (0x1<<0) // Lane 0 alignment marker lock
9095     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK_SHIFT                          0
9096     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK                                (0x1<<1) // Lane 1 alignment marker lock
9097     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK_SHIFT                          1
9098     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK                                (0x1<<2) // Lane 2 alignment marker lock
9099     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK_SHIFT                          2
9100     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK                                (0x1<<3) // Lane 3 alignment marker lock
9101     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK_SHIFT                          3
9102     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_UNUSED_0                                         (0xfffffff<<4) // reserved
9103     #define ETH_PCS10_50G_REG_MULTILANE_ALIGN_STAT3_UNUSED_0_SHIFT                                   4
9104 #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE0                                                          0x000320UL //Access:R    DataWidth:0x20  BIP Error Counter Lane 0; Clears on read; None roll-over.  Chips: K2
9105     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE0_BIP_ERROR_COUNTER                                    (0xffff<<0) // BIP error counter lane 0; None roll-over.
9106     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE0_BIP_ERROR_COUNTER_SHIFT                              0
9107     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE0_UNUSED_0                                             (0xffff<<16) // reserved
9108     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE0_UNUSED_0_SHIFT                                       16
9109 #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE1                                                          0x000324UL //Access:R    DataWidth:0x20  BIP Error Counter Lane 1; Clears on read; None roll-over.  Chips: K2
9110     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE1_BIP_ERROR_COUNTER                                    (0xffff<<0) // BIP error counter lane 1; None roll-over.
9111     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE1_BIP_ERROR_COUNTER_SHIFT                              0
9112     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE1_UNUSED_0                                             (0xffff<<16) // reserved
9113     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE1_UNUSED_0_SHIFT                                       16
9114 #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE2                                                          0x000328UL //Access:R    DataWidth:0x20  BIP Error Counter Lane 2; Clears on read; None roll-over.  Chips: K2
9115     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE2_BIP_ERROR_COUNTER                                    (0xffff<<0) // BIP error counter lane 2; None roll-over.
9116     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE2_BIP_ERROR_COUNTER_SHIFT                              0
9117     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE2_UNUSED_0                                             (0xffff<<16) // reserved
9118     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE2_UNUSED_0_SHIFT                                       16
9119 #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE3                                                          0x00032cUL //Access:R    DataWidth:0x20  BIP Error Counter Lane 3; Clears on read; None roll-over.  Chips: K2
9120     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE3_BIP_ERROR_COUNTER                                    (0xffff<<0) // BIP error counter lane 3; None roll-over.
9121     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE3_BIP_ERROR_COUNTER_SHIFT                              0
9122     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE3_UNUSED_0                                             (0xffff<<16) // reserved
9123     #define ETH_PCS10_50G_REG_BIP_ERR_CNT_LANE3_UNUSED_0_SHIFT                                       16
9124 #define ETH_PCS10_50G_REG_LANE0_MAPPING                                                              0x000640UL //Access:R    DataWidth:0x20  Lane Channel 0 mapping bits 1:0.  Chips: K2
9125     #define ETH_PCS10_50G_REG_LANE0_MAPPING_LANE_MAPPING                                             (0x3<<0) // Lane 0 mapping bits 1:0.
9126     #define ETH_PCS10_50G_REG_LANE0_MAPPING_LANE_MAPPING_SHIFT                                       0
9127     #define ETH_PCS10_50G_REG_LANE0_MAPPING_UNUSED_0                                                 (0x3fffffff<<2) // reserved
9128     #define ETH_PCS10_50G_REG_LANE0_MAPPING_UNUSED_0_SHIFT                                           2
9129 #define ETH_PCS10_50G_REG_LANE1_MAPPING                                                              0x000644UL //Access:R    DataWidth:0x20  Lane Channel 1 mapping bits 1:0.  Chips: K2
9130     #define ETH_PCS10_50G_REG_LANE1_MAPPING_LANE_MAPPING                                             (0x3<<0) // Lane 1 mapping bits 1:0.
9131     #define ETH_PCS10_50G_REG_LANE1_MAPPING_LANE_MAPPING_SHIFT                                       0
9132     #define ETH_PCS10_50G_REG_LANE1_MAPPING_UNUSED_0                                                 (0x3fffffff<<2) // reserved
9133     #define ETH_PCS10_50G_REG_LANE1_MAPPING_UNUSED_0_SHIFT                                           2
9134 #define ETH_PCS10_50G_REG_LANE2_MAPPING                                                              0x000648UL //Access:R    DataWidth:0x20  Lane Channel 2 mapping bits 1:0.  Chips: K2
9135     #define ETH_PCS10_50G_REG_LANE2_MAPPING_LANE_MAPPING                                             (0x3<<0) // Lane 2 mapping bits 1:0.
9136     #define ETH_PCS10_50G_REG_LANE2_MAPPING_LANE_MAPPING_SHIFT                                       0
9137     #define ETH_PCS10_50G_REG_LANE2_MAPPING_UNUSED_0                                                 (0x3fffffff<<2) // reserved
9138     #define ETH_PCS10_50G_REG_LANE2_MAPPING_UNUSED_0_SHIFT                                           2
9139 #define ETH_PCS10_50G_REG_LANE3_MAPPING                                                              0x00064cUL //Access:R    DataWidth:0x20  Lane Channel 3 mapping bits 1:0.  Chips: K2
9140     #define ETH_PCS10_50G_REG_LANE3_MAPPING_LANE_MAPPING                                             (0x3<<0) // Lane 3 mapping bits 1:0.
9141     #define ETH_PCS10_50G_REG_LANE3_MAPPING_LANE_MAPPING_SHIFT                                       0
9142     #define ETH_PCS10_50G_REG_LANE3_MAPPING_UNUSED_0                                                 (0x3fffffff<<2) // reserved
9143     #define ETH_PCS10_50G_REG_LANE3_MAPPING_UNUSED_0_SHIFT                                           2
9144 #define ETH_PCS10_50G_REG_VENDOR_SCRATCH                                                             0x020000UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Scratch Register.  Chips: K2
9145     #define ETH_PCS10_50G_REG_VENDOR_SCRATCH_SCRATCH                                                 (0xffff<<0) // Scratch Register; Register address to test read and write operation.
9146     #define ETH_PCS10_50G_REG_VENDOR_SCRATCH_SCRATCH_SHIFT                                           0
9147     #define ETH_PCS10_50G_REG_VENDOR_SCRATCH_UNUSED_0                                                (0xffff<<16) // reserved
9148     #define ETH_PCS10_50G_REG_VENDOR_SCRATCH_UNUSED_0_SHIFT                                          16
9149 #define ETH_PCS10_50G_REG_VENDOR_CORE_REV                                                            0x020004UL //Access:R    DataWidth:0x20  Vendor Specific Reg; Core Revision derived from DEV_VERSION package parameter.  Chips: K2
9150     #define ETH_PCS10_50G_REG_VENDOR_CORE_REV_REVISION                                               (0xffff<<0) // Core Design version as defined by DEV_VERSION parameter in PCS package file.
9151     #define ETH_PCS10_50G_REG_VENDOR_CORE_REV_REVISION_SHIFT                                         0
9152     #define ETH_PCS10_50G_REG_VENDOR_CORE_REV_UNUSED_0                                               (0xffff<<16) // reserved
9153     #define ETH_PCS10_50G_REG_VENDOR_CORE_REV_UNUSED_0_SHIFT                                         16
9154 #define ETH_PCS10_50G_REG_VENDOR_VL_INTVL                                                            0x020008UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).  Chips: K2
9155     #define ETH_PCS10_50G_REG_VENDOR_VL_INTVL_MARKER_COUNTER                                         (0xffff<<0) // A 16-bit value defining the amount of data between markers; (distance of markers-1).
9156     #define ETH_PCS10_50G_REG_VENDOR_VL_INTVL_MARKER_COUNTER_SHIFT                                   0
9157     #define ETH_PCS10_50G_REG_VENDOR_VL_INTVL_UNUSED_0                                               (0xffff<<16) // reserved
9158     #define ETH_PCS10_50G_REG_VENDOR_VL_INTVL_UNUSED_0_SHIFT                                         16
9159 #define ETH_PCS10_50G_REG_VENDOR_TXLANE_THRESH                                                       0x02000cUL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Defines the transmit line decoupling FIFOs almost full threshold.  Chips: K2
9160     #define ETH_PCS10_50G_REG_VENDOR_TXLANE_THRESH_THRESHOLD                                         (0xf<<0) // A 4-bit value to define the transmit line decoupling FIFOs almost full threshold; Valid values are 4..9.
9161     #define ETH_PCS10_50G_REG_VENDOR_TXLANE_THRESH_THRESHOLD_SHIFT                                   0
9162     #define ETH_PCS10_50G_REG_VENDOR_TXLANE_THRESH_UNUSED_0                                          (0xfffffff<<4) // reserved
9163     #define ETH_PCS10_50G_REG_VENDOR_TXLANE_THRESH_UNUSED_0_SHIFT                                    4
9164 #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG                                                       0x020010UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Define Reduced-XLAUI PMA mode using 2 lanes.  Chips: K2
9165     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RXLAUI_ENA                                        (0x1<<0) // Enable Reduced-XLAUI PMA mode using 2 lanes.
9166     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RXLAUI_ENA_SHIFT                                  0
9167     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RESERVED_WRITEABLE_BITS                           (0x7<<1) // These bits are writeable but have no effect.
9168     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_RESERVED_WRITEABLE_BITS_SHIFT                     1
9169     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE0                                      (0xf<<4) // Set VL (0..3) to transmit to RXLAUI lane 0.
9170     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE0_SHIFT                                4
9171     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE1                                      (0xf<<8) // Set VL (0..3) to transmit to RXLAUI lane 1.
9172     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_TX_MAP_LANE1_SHIFT                                8
9173     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_UNUSED_0                                          (0x7<<12) // reserved
9174     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_UNUSED_0_SHIFT                                    12
9175     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_ENA_STATUS                                        (0x1<<15) // Indicates if currently the RXLAUI mode is enabled.
9176     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_ENA_STATUS_SHIFT                                  15
9177     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_UNUSED_1                                          (0xffff<<16) // reserved
9178     #define ETH_PCS10_50G_REG_VENDOR_RXLAUI_CONFIG_UNUSED_1_SHIFT                                    16
9179 #define ETH_PCS10_50G_REG_VENDOR_VL0_0                                                               0x020020UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Marker pattern for PCS Virtual Lane 0.  Chips: K2
9180     #define ETH_PCS10_50G_REG_VENDOR_VL0_0_M0                                                        (0xff<<0) // Lane 0 Marker pattern for m0.
9181     #define ETH_PCS10_50G_REG_VENDOR_VL0_0_M0_SHIFT                                                  0
9182     #define ETH_PCS10_50G_REG_VENDOR_VL0_0_M1                                                        (0xff<<8) // Lane 0 Marker pattern for m1.
9183     #define ETH_PCS10_50G_REG_VENDOR_VL0_0_M1_SHIFT                                                  8
9184     #define ETH_PCS10_50G_REG_VENDOR_VL0_0_UNUSED_0                                                  (0xffff<<16) // reserved
9185     #define ETH_PCS10_50G_REG_VENDOR_VL0_0_UNUSED_0_SHIFT                                            16
9186 #define ETH_PCS10_50G_REG_VENDOR_VL0_1                                                               0x020024UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Last byte of PCS Virtual Lane 0 marker pattern.  Chips: K2
9187     #define ETH_PCS10_50G_REG_VENDOR_VL0_1_M2                                                        (0xff<<0) // Lane 0 last btye of Marker pattern for m2.
9188     #define ETH_PCS10_50G_REG_VENDOR_VL0_1_M2_SHIFT                                                  0
9189     #define ETH_PCS10_50G_REG_VENDOR_VL0_1_UNUSED_0                                                  (0xffffff<<8) // reserved
9190     #define ETH_PCS10_50G_REG_VENDOR_VL0_1_UNUSED_0_SHIFT                                            8
9191 #define ETH_PCS10_50G_REG_VENDOR_VL1_0                                                               0x020028UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Marker pattern for PCS Virtual Lane 1.  Chips: K2
9192     #define ETH_PCS10_50G_REG_VENDOR_VL1_0_M0                                                        (0xff<<0) // Lane 1 Marker pattern for m0.
9193     #define ETH_PCS10_50G_REG_VENDOR_VL1_0_M0_SHIFT                                                  0
9194     #define ETH_PCS10_50G_REG_VENDOR_VL1_0_M1                                                        (0xff<<8) // Lane 1 Marker pattern for m1.
9195     #define ETH_PCS10_50G_REG_VENDOR_VL1_0_M1_SHIFT                                                  8
9196     #define ETH_PCS10_50G_REG_VENDOR_VL1_0_UNUSED_0                                                  (0xffff<<16) // reserved
9197     #define ETH_PCS10_50G_REG_VENDOR_VL1_0_UNUSED_0_SHIFT                                            16
9198 #define ETH_PCS10_50G_REG_VENDOR_VL1_1                                                               0x02002cUL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Last byte of PCS Virtual Lane 1 marker pattern.  Chips: K2
9199     #define ETH_PCS10_50G_REG_VENDOR_VL1_1_M2                                                        (0xff<<0) // Lane 1 last btye of Marker pattern for m2.
9200     #define ETH_PCS10_50G_REG_VENDOR_VL1_1_M2_SHIFT                                                  0
9201     #define ETH_PCS10_50G_REG_VENDOR_VL1_1_UNUSED_0                                                  (0xffffff<<8) // reserved
9202     #define ETH_PCS10_50G_REG_VENDOR_VL1_1_UNUSED_0_SHIFT                                            8
9203 #define ETH_PCS10_50G_REG_VENDOR_VL2_0                                                               0x020030UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Marker pattern for PCS Virtual Lane 2.  Chips: K2
9204     #define ETH_PCS10_50G_REG_VENDOR_VL2_0_M0                                                        (0xff<<0) // Lane 2 Marker pattern for m0.
9205     #define ETH_PCS10_50G_REG_VENDOR_VL2_0_M0_SHIFT                                                  0
9206     #define ETH_PCS10_50G_REG_VENDOR_VL2_0_M1                                                        (0xff<<8) // Lane 2 Marker pattern for m1.
9207     #define ETH_PCS10_50G_REG_VENDOR_VL2_0_M1_SHIFT                                                  8
9208     #define ETH_PCS10_50G_REG_VENDOR_VL2_0_UNUSED_0                                                  (0xffff<<16) // reserved
9209     #define ETH_PCS10_50G_REG_VENDOR_VL2_0_UNUSED_0_SHIFT                                            16
9210 #define ETH_PCS10_50G_REG_VENDOR_VL2_1                                                               0x020034UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Last byte of PCS Virtual Lane 2 marker pattern.  Chips: K2
9211     #define ETH_PCS10_50G_REG_VENDOR_VL2_1_M2                                                        (0xff<<0) // Lane 2 last btye of Marker pattern for m2.
9212     #define ETH_PCS10_50G_REG_VENDOR_VL2_1_M2_SHIFT                                                  0
9213     #define ETH_PCS10_50G_REG_VENDOR_VL2_1_UNUSED_0                                                  (0xffffff<<8) // reserved
9214     #define ETH_PCS10_50G_REG_VENDOR_VL2_1_UNUSED_0_SHIFT                                            8
9215 #define ETH_PCS10_50G_REG_VENDOR_VL3_0                                                               0x020038UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Marker pattern for PCS Virtual Lane 3.  Chips: K2
9216     #define ETH_PCS10_50G_REG_VENDOR_VL3_0_M0                                                        (0xff<<0) // Lane 3 Marker pattern for m0.
9217     #define ETH_PCS10_50G_REG_VENDOR_VL3_0_M0_SHIFT                                                  0
9218     #define ETH_PCS10_50G_REG_VENDOR_VL3_0_M1                                                        (0xff<<8) // Lane 3 Marker pattern for m1.
9219     #define ETH_PCS10_50G_REG_VENDOR_VL3_0_M1_SHIFT                                                  8
9220     #define ETH_PCS10_50G_REG_VENDOR_VL3_0_UNUSED_0                                                  (0xffff<<16) // reserved
9221     #define ETH_PCS10_50G_REG_VENDOR_VL3_0_UNUSED_0_SHIFT                                            16
9222 #define ETH_PCS10_50G_REG_VENDOR_VL3_1                                                               0x02003cUL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Last byte of PCS Virtual Lane 3 marker pattern.  Chips: K2
9223     #define ETH_PCS10_50G_REG_VENDOR_VL3_1_M2                                                        (0xff<<0) // Lane 3 last btye of Marker pattern for m2.
9224     #define ETH_PCS10_50G_REG_VENDOR_VL3_1_M2_SHIFT                                                  0
9225     #define ETH_PCS10_50G_REG_VENDOR_VL3_1_UNUSED_0                                                  (0xffffff<<8) // reserved
9226     #define ETH_PCS10_50G_REG_VENDOR_VL3_1_UNUSED_0_SHIFT                                            8
9227 #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE                                                            0x020040UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Configure PCS supporting Clause 49 or 82 Encoder/Decoder, MLD.  Chips: K2
9228     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49                                           (0x1<<0) // When 0 PCS uses Clause 82 encoder/decoder functions; When 1 PCS uses Clause 49 encoder/decoder functions.
9229     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49_SHIFT                                     0
9230     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_DISABLE_MLD                                            (0x1<<1) // When 0 PCS 4-lane MLD function is active; When 1 the MLD function is disabled.
9231     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_DISABLE_MLD_SHIFT                                      1
9232     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_UNUSED_0                                               (0x3f<<2) // reserved
9233     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_UNUSED_0_SHIFT                                         2
9234     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49                                        (0x1<<8) // Current status of Clause 49 setting.
9235     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_SHIFT                                  8
9236     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD                                         (0x1<<9) // Current status of MLD setting.
9237     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD_SHIFT                                   9
9238     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_UNUSED_1                                               (0x3fffff<<10) // reserved
9239     #define ETH_PCS10_50G_REG_VENDOR_PCS_MODE_UNUSED_1_SHIFT                                         10
9240 #define ETH_PCS10_25G_REG_CONTROL1                                                                   0x000000UL //Access:RW   DataWidth:0x20  PCS Control.  Chips: K2
9241     #define ETH_PCS10_25G_REG_CONTROL1_UNUSED_0                                                      (0x3<<0) // reserved
9242     #define ETH_PCS10_25G_REG_CONTROL1_UNUSED_0_SHIFT                                                0
9243     #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECTION                                               (0xf<<2) // 0011 = 40 Gb/s; 0000 = 10Gb/s.
9244     #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECTION_SHIFT                                         2
9245     #define ETH_PCS10_25G_REG_CONTROL1_SPEED_ALWAYS1                                                 (0x1<<6) // Always 1.
9246     #define ETH_PCS10_25G_REG_CONTROL1_SPEED_ALWAYS1_SHIFT                                           6
9247     #define ETH_PCS10_25G_REG_CONTROL1_UNUSED_1                                                      (0xf<<7) // reserved
9248     #define ETH_PCS10_25G_REG_CONTROL1_UNUSED_1_SHIFT                                                7
9249     #define ETH_PCS10_25G_REG_CONTROL1_LOW_POWER                                                     (0x1<<11) // 0=normal operation (Always 0).
9250     #define ETH_PCS10_25G_REG_CONTROL1_LOW_POWER_SHIFT                                               11
9251     #define ETH_PCS10_25G_REG_CONTROL1_UNUSED_2                                                      (0x1<<12) // reserved
9252     #define ETH_PCS10_25G_REG_CONTROL1_UNUSED_2_SHIFT                                                12
9253     #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECT_ALWAYS1                                          (0x1<<13) // Always 1.
9254     #define ETH_PCS10_25G_REG_CONTROL1_SPEED_SELECT_ALWAYS1_SHIFT                                    13
9255     #define ETH_PCS10_25G_REG_CONTROL1_LOOPBACK                                                      (0x1<<14) // 1=Enable loopback, 0=disable loopback.
9256     #define ETH_PCS10_25G_REG_CONTROL1_LOOPBACK_SHIFT                                                14
9257     #define ETH_PCS10_25G_REG_CONTROL1_RESET                                                         (0x1<<15) // 1=PCS reset, 0=normal; Self clearing.
9258     #define ETH_PCS10_25G_REG_CONTROL1_RESET_SHIFT                                                   15
9259     #define ETH_PCS10_25G_REG_CONTROL1_UNUSED_3                                                      (0xffff<<16) // reserved
9260     #define ETH_PCS10_25G_REG_CONTROL1_UNUSED_3_SHIFT                                                16
9261 #define ETH_PCS10_25G_REG_STATUS1                                                                    0x000004UL //Access:R    DataWidth:0x20  PCS Status.  Chips: K2
9262     #define ETH_PCS10_25G_REG_STATUS1_UNUSED_0                                                       (0x1<<0) // reserved
9263     #define ETH_PCS10_25G_REG_STATUS1_UNUSED_0_SHIFT                                                 0
9264     #define ETH_PCS10_25G_REG_STATUS1_LOW_POWER_ABILITY                                              (0x1<<1) // Set to 1 to indicate that the PCS implements a low power mode.
9265     #define ETH_PCS10_25G_REG_STATUS1_LOW_POWER_ABILITY_SHIFT                                        1
9266     #define ETH_PCS10_25G_REG_STATUS1_PCS_RECEIVE_LINK                                               (0x1<<2) // When 1, indicates PCS receive link up; When ?0?, indicates PCS receive link is or was down (latching low).
9267     #define ETH_PCS10_25G_REG_STATUS1_PCS_RECEIVE_LINK_SHIFT                                         2
9268     #define ETH_PCS10_25G_REG_STATUS1_UNUSED_1                                                       (0xf<<3) // reserved
9269     #define ETH_PCS10_25G_REG_STATUS1_UNUSED_1_SHIFT                                                 3
9270     #define ETH_PCS10_25G_REG_STATUS1_FAULT                                                          (0x1<<7) // When 1, indicates a fault condition idetected; When ?0?, indicates that no fault condition is detected.
9271     #define ETH_PCS10_25G_REG_STATUS1_FAULT_SHIFT                                                    7
9272     #define ETH_PCS10_25G_REG_STATUS1_RX_LPI_ACTIVE                                                  (0x1<<8) // 1: receive is currently in LPI state; 0: normal operation.
9273     #define ETH_PCS10_25G_REG_STATUS1_RX_LPI_ACTIVE_SHIFT                                            8
9274     #define ETH_PCS10_25G_REG_STATUS1_TX_LPI_ACTIVE                                                  (0x1<<9) // 1: transmit is currently in LPI state; 0: normal operation.
9275     #define ETH_PCS10_25G_REG_STATUS1_TX_LPI_ACTIVE_SHIFT                                            9
9276     #define ETH_PCS10_25G_REG_STATUS1_RX_LPI                                                         (0x1<<10) // 1: receive is or was in LPI state; 0: normal operation; Latching high.
9277     #define ETH_PCS10_25G_REG_STATUS1_RX_LPI_SHIFT                                                   10
9278     #define ETH_PCS10_25G_REG_STATUS1_TX_LPI                                                         (0x1<<11) // 1: transmit is or was in LPI state; 0: normal operation; Latching high.
9279     #define ETH_PCS10_25G_REG_STATUS1_TX_LPI_SHIFT                                                   11
9280     #define ETH_PCS10_25G_REG_STATUS1_UNUSED_2                                                       (0xfffff<<12) // reserved
9281     #define ETH_PCS10_25G_REG_STATUS1_UNUSED_2_SHIFT                                                 12
9282 #define ETH_PCS10_25G_REG_DEVICE_ID0                                                                 0x000008UL //Access:R    DataWidth:0x20  PHY Identifier constant from package parameter PHY_IDENTIFIER bits 15:4. Bits 3:0 always 0.  Chips: K2
9283     #define ETH_PCS10_25G_REG_DEVICE_ID0_IDENTIFIER                                                  (0xffff<<0) // Bits 15:0 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
9284     #define ETH_PCS10_25G_REG_DEVICE_ID0_IDENTIFIER_SHIFT                                            0
9285     #define ETH_PCS10_25G_REG_DEVICE_ID0_UNUSED_0                                                    (0xffff<<16) // reserved
9286     #define ETH_PCS10_25G_REG_DEVICE_ID0_UNUSED_0_SHIFT                                              16
9287 #define ETH_PCS10_25G_REG_DEVICE_ID1                                                                 0x00000cUL //Access:R    DataWidth:0x20  PHY Identifier constant from package parameter PHY_IDENTIFIER bits 31:16.  Chips: K2
9288     #define ETH_PCS10_25G_REG_DEVICE_ID1_IDENTIFIER                                                  (0xffff<<0) // Bits 31:16 of Device Identifier defined by parameter PHY_IDENTIFIER in PCS package file.
9289     #define ETH_PCS10_25G_REG_DEVICE_ID1_IDENTIFIER_SHIFT                                            0
9290     #define ETH_PCS10_25G_REG_DEVICE_ID1_UNUSED_0                                                    (0xffff<<16) // reserved
9291     #define ETH_PCS10_25G_REG_DEVICE_ID1_UNUSED_0_SHIFT                                              16
9292 #define ETH_PCS10_25G_REG_SPEED_ABILITY                                                              0x000010UL //Access:R    DataWidth:0x20  PCS supported speeds (values as defined by standard only, no proprietary speeds).  Chips: K2
9293     #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10GETH                                                  (0x1<<0) // When 1, this PCS is 10Geth capable.
9294     #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10GETH_SHIFT                                            0
9295     #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10PASS_TS                                               (0x1<<1) // When 1, this PCS is 10PASS-TS/2Base-TL capable.
9296     #define ETH_PCS10_25G_REG_SPEED_ABILITY_C10PASS_TS_SHIFT                                         1
9297     #define ETH_PCS10_25G_REG_SPEED_ABILITY_C40G                                                     (0x1<<2) // When 1, this PCS is 40G capable.
9298     #define ETH_PCS10_25G_REG_SPEED_ABILITY_C40G_SHIFT                                               2
9299     #define ETH_PCS10_25G_REG_SPEED_ABILITY_C100G                                                    (0x1<<3) // When 1, this PCS is 100G capable.
9300     #define ETH_PCS10_25G_REG_SPEED_ABILITY_C100G_SHIFT                                              3
9301     #define ETH_PCS10_25G_REG_SPEED_ABILITY_UNUSED_0                                                 (0xfffffff<<4) // reserved
9302     #define ETH_PCS10_25G_REG_SPEED_ABILITY_UNUSED_0_SHIFT                                           4
9303 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1                                                            0x000014UL //Access:R    DataWidth:0x20  Constant indicating PCS presence.  Chips: K2
9304     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_CLAUSE22                                               (0x1<<0) // Clause 22 registers present when 1.
9305     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_CLAUSE22_SHIFT                                         0
9306     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PMD_PMA                                                (0x1<<1) // PMD/PMA present when 1.
9307     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PMD_PMA_SHIFT                                          1
9308     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_WIS_PRES                                               (0x1<<2) // WIS present when 1.
9309     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_WIS_PRES_SHIFT                                         2
9310     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PCS_PRES                                               (0x1<<3) // PCS present when 1.
9311     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PCS_PRES_SHIFT                                         3
9312     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PHY_XS                                                 (0x1<<4) // PHY XS present when 1.
9313     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_PHY_XS_SHIFT                                           4
9314     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_DTE_XS                                                 (0x1<<5) // DTE XS present when 1.
9315     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_DTE_XS_SHIFT                                           5
9316     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_TC_PRES                                                (0x1<<6) // TC present when 1.
9317     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_TC_PRES_SHIFT                                          6
9318     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_UNUSED_0                                               (0x1ffffff<<7) // reserved
9319     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG1_UNUSED_0_SHIFT                                         7
9320 #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2                                                            0x000018UL //Access:R    DataWidth:0x20  Vendor specific presence.  Chips: K2
9321     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_UNUSED_0                                               (0x1fff<<0) // reserved
9322     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_UNUSED_0_SHIFT                                         0
9323     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_CLAUSE22                                               (0x1<<13) // Clause 22 extension present
9324     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_CLAUSE22_SHIFT                                         13
9325     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE1                                                (0x1<<14) // Vendor specific device 1 present
9326     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE1_SHIFT                                          14
9327     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE2                                                (0x1<<15) // Vendor specific device 2 present
9328     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_DEVICE2_SHIFT                                          15
9329     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_UNUSED_1                                               (0xffff<<16) // reserved
9330     #define ETH_PCS10_25G_REG_DEVICES_IN_PKG2_UNUSED_1_SHIFT                                         16
9331 #define ETH_PCS10_25G_REG_CONTROL2                                                                   0x00001cUL //Access:RW   DataWidth:0x20  Operating speed indication/control.  Chips: K2
9332     #define ETH_PCS10_25G_REG_CONTROL2_PCS_TYPE                                                      (0x7<<0) // PCS type selection; Writing 0 sets PCS_MODE to 0x03 setting Clause 49 mode and disabling MLD.
9333     #define ETH_PCS10_25G_REG_CONTROL2_PCS_TYPE_SHIFT                                                0
9334     #define ETH_PCS10_25G_REG_CONTROL2_UNUSED_0                                                      (0x1fffffff<<3) // reserved
9335     #define ETH_PCS10_25G_REG_CONTROL2_UNUSED_0_SHIFT                                                3
9336 #define ETH_PCS10_25G_REG_STATUS2                                                                    0x000020UL //Access:R    DataWidth:0x20  Fault status; Device capabilities  Chips: K2
9337     #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_R                                                     (0x1<<0) // When 1, this PCS is 10GBase-R capable.
9338     #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_R_SHIFT                                               0
9339     #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_X                                                     (0x1<<1) // When 1, this PCS is 10GBase-X capable.
9340     #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_X_SHIFT                                               1
9341     #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_W                                                     (0x1<<2) // When 1, this PCS is 10GBase-W capable.
9342     #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_W_SHIFT                                               2
9343     #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_T                                                     (0x1<<3) // When 1, this PCS is 10GBase-T capable.
9344     #define ETH_PCS10_25G_REG_STATUS2_C10GBASE_T_SHIFT                                               3
9345     #define ETH_PCS10_25G_REG_STATUS2_C40GBASE_R                                                     (0x1<<4) // When 1, this PCS is 40GBase-R capable.
9346     #define ETH_PCS10_25G_REG_STATUS2_C40GBASE_R_SHIFT                                               4
9347     #define ETH_PCS10_25G_REG_STATUS2_C100GBASE_R                                                    (0x1<<5) // When 1, this PCS is 100GBase-R capable.
9348     #define ETH_PCS10_25G_REG_STATUS2_C100GBASE_R_SHIFT                                              5
9349     #define ETH_PCS10_25G_REG_STATUS2_UNUSED_0                                                       (0xf<<6) // reserved
9350     #define ETH_PCS10_25G_REG_STATUS2_UNUSED_0_SHIFT                                                 6
9351     #define ETH_PCS10_25G_REG_STATUS2_RECEIVE_FAULT                                                  (0x1<<10) // Receive fault. 1=Fault condition on receive path. Latched high
9352     #define ETH_PCS10_25G_REG_STATUS2_RECEIVE_FAULT_SHIFT                                            10
9353     #define ETH_PCS10_25G_REG_STATUS2_TRANSMIT_FAULT                                                 (0x1<<11) // Transmit fault. 1=Fault condition on transmit path. Latched high
9354     #define ETH_PCS10_25G_REG_STATUS2_TRANSMIT_FAULT_SHIFT                                           11
9355     #define ETH_PCS10_25G_REG_STATUS2_UNUSED_1                                                       (0x3<<12) // reserved
9356     #define ETH_PCS10_25G_REG_STATUS2_UNUSED_1_SHIFT                                                 12
9357     #define ETH_PCS10_25G_REG_STATUS2_DEVICE_PRESENT                                                 (0x3<<14) // Device present. When bits are 10 = device responding at this address.
9358     #define ETH_PCS10_25G_REG_STATUS2_DEVICE_PRESENT_SHIFT                                           14
9359     #define ETH_PCS10_25G_REG_STATUS2_UNUSED_2                                                       (0xffff<<16) // reserved
9360     #define ETH_PCS10_25G_REG_STATUS2_UNUSED_2_SHIFT                                                 16
9361 #define ETH_PCS10_25G_REG_PKG_ID0                                                                    0x000038UL //Access:R    DataWidth:0x20  Constant from package parameter PACK_IDENTIFIER bits 15:0.  Chips: K2
9362     #define ETH_PCS10_25G_REG_PKG_ID0_IDENTIFIER                                                     (0xffff<<0) // Constant from package parameter PACK_IDENTIFIER bits 15:0.
9363     #define ETH_PCS10_25G_REG_PKG_ID0_IDENTIFIER_SHIFT                                               0
9364     #define ETH_PCS10_25G_REG_PKG_ID0_UNUSED_0                                                       (0xffff<<16) // reserved
9365     #define ETH_PCS10_25G_REG_PKG_ID0_UNUSED_0_SHIFT                                                 16
9366 #define ETH_PCS10_25G_REG_PKG_ID1                                                                    0x00003cUL //Access:R    DataWidth:0x20  Constant from package parameter PACK_IDENTIFIER bits 31:16.  Chips: K2
9367     #define ETH_PCS10_25G_REG_PKG_ID1_IDENTIFIER                                                     (0xffff<<0) // Constant from package parameter PACK_IDENTIFIER bits 31:16.
9368     #define ETH_PCS10_25G_REG_PKG_ID1_IDENTIFIER_SHIFT                                               0
9369     #define ETH_PCS10_25G_REG_PKG_ID1_UNUSED_0                                                       (0xffff<<16) // reserved
9370     #define ETH_PCS10_25G_REG_PKG_ID1_UNUSED_0_SHIFT                                                 16
9371 #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY                                                        0x000050UL //Access:RW   DataWidth:0x20  EEE Control and Capabilities (exists only if EEE is available).  Chips: K2
9372     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_LPI_FW                                             (0x1<<0) // Mode for selecting select 40G EEE mode; 1 = Fast wake mode; 0 = Deep sleep for LPI function.
9373     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_LPI_FW_SHIFT                                       0
9374     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_UNUSED_0                                           (0x1f<<1) // reserved
9375     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_UNUSED_0_SHIFT                                     1
9376     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR                                     (0x1<<6) // When 1, EEE is supported for 10GBASE-KR.
9377     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_10GBASE_KR_SHIFT                               6
9378     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_UNUSED_1                                           (0x1<<7) // reserved
9379     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_UNUSED_1_SHIFT                                     7
9380     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE                                 (0x1<<8) // When 1, EEE fast wake is supported for 40GBASE-R.
9381     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RAWAKE_SHIFT                           8
9382     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP                                 (0x1<<9) // When 1, EEE deep sleep is supported for 40GBASE-R.
9383     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_EEE_40GBASE_RSLEEP_SHIFT                           9
9384     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_UNUSED_2                                           (0x3fffff<<10) // reserved
9385     #define ETH_PCS10_25G_REG_EEE_CTRL_CAPABILITY_UNUSED_2_SHIFT                                     10
9386 #define ETH_PCS10_25G_REG_WAKE_ERR_COUNTER                                                           0x000058UL //Access:R    DataWidth:0x20  EEE Wake error counter (exists only if EEE is available); Clears on read.  Chips: K2
9387     #define ETH_PCS10_25G_REG_WAKE_ERR_COUNTER_COUNTER                                               (0xffff<<0) // Increments each time the LPI enters the RX_WTF state indicating a wake time fault; None roll-over.
9388     #define ETH_PCS10_25G_REG_WAKE_ERR_COUNTER_COUNTER_SHIFT                                         0
9389     #define ETH_PCS10_25G_REG_WAKE_ERR_COUNTER_UNUSED_0                                              (0xffff<<16) // reserved
9390     #define ETH_PCS10_25G_REG_WAKE_ERR_COUNTER_UNUSED_0_SHIFT                                        16
9391 #define ETH_PCS10_25G_REG_BASER_STATUS1                                                              0x000080UL //Access:R    DataWidth:0x20  Link Status Information.  Chips: K2
9392     #define ETH_PCS10_25G_REG_BASER_STATUS1_BLOCK_LOCK                                               (0x1<<0) // 1=PCS locked to received blocks.
9393     #define ETH_PCS10_25G_REG_BASER_STATUS1_BLOCK_LOCK_SHIFT                                         0
9394     #define ETH_PCS10_25G_REG_BASER_STATUS1_HIGH_BER                                                 (0x1<<1) // 1=PCS reporting a high BER.
9395     #define ETH_PCS10_25G_REG_BASER_STATUS1_HIGH_BER_SHIFT                                           1
9396     #define ETH_PCS10_25G_REG_BASER_STATUS1_UNUSED_0                                                 (0x3ff<<2) // reserved
9397     #define ETH_PCS10_25G_REG_BASER_STATUS1_UNUSED_0_SHIFT                                           2
9398     #define ETH_PCS10_25G_REG_BASER_STATUS1_RECEIVE_LINK                                             (0x1<<12) // Receive link status. 1=Link up; 0=link down.
9399     #define ETH_PCS10_25G_REG_BASER_STATUS1_RECEIVE_LINK_SHIFT                                       12
9400     #define ETH_PCS10_25G_REG_BASER_STATUS1_UNUSED_1                                                 (0x7ffff<<13) // reserved
9401     #define ETH_PCS10_25G_REG_BASER_STATUS1_UNUSED_1_SHIFT                                           13
9402 #define ETH_PCS10_25G_REG_BASER_STATUS2                                                              0x000084UL //Access:R    DataWidth:0x20  Link Status latches and error counters.  Chips: K2
9403     #define ETH_PCS10_25G_REG_BASER_STATUS2_ERRORED_CNT                                              (0xff<<0) // Errored blocks counter; None roll-over.
9404     #define ETH_PCS10_25G_REG_BASER_STATUS2_ERRORED_CNT_SHIFT                                        0
9405     #define ETH_PCS10_25G_REG_BASER_STATUS2_BER_COUNTER                                              (0x3f<<8) // BER counter; None roll-over.
9406     #define ETH_PCS10_25G_REG_BASER_STATUS2_BER_COUNTER_SHIFT                                        8
9407     #define ETH_PCS10_25G_REG_BASER_STATUS2_HIGH_BER                                                 (0x1<<14) // BER flag; Latched high.
9408     #define ETH_PCS10_25G_REG_BASER_STATUS2_HIGH_BER_SHIFT                                           14
9409     #define ETH_PCS10_25G_REG_BASER_STATUS2_BLOCK_LOCK                                               (0x1<<15) // Block Lock; Latched low.
9410     #define ETH_PCS10_25G_REG_BASER_STATUS2_BLOCK_LOCK_SHIFT                                         15
9411     #define ETH_PCS10_25G_REG_BASER_STATUS2_UNUSED_0                                                 (0xffff<<16) // reserved
9412     #define ETH_PCS10_25G_REG_BASER_STATUS2_UNUSED_0_SHIFT                                           16
9413 #define ETH_PCS10_25G_REG_SEED_A0                                                                    0x000088UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed A bits 15:0.  Chips: K2
9414     #define ETH_PCS10_25G_REG_SEED_A0_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 15:0.
9415     #define ETH_PCS10_25G_REG_SEED_A0_SEED_SHIFT                                                     0
9416     #define ETH_PCS10_25G_REG_SEED_A0_UNUSED_0                                                       (0xffff<<16) // reserved
9417     #define ETH_PCS10_25G_REG_SEED_A0_UNUSED_0_SHIFT                                                 16
9418 #define ETH_PCS10_25G_REG_SEED_A1                                                                    0x00008cUL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed A bits 31:16.  Chips: K2
9419     #define ETH_PCS10_25G_REG_SEED_A1_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 31:16.
9420     #define ETH_PCS10_25G_REG_SEED_A1_SEED_SHIFT                                                     0
9421     #define ETH_PCS10_25G_REG_SEED_A1_UNUSED_0                                                       (0xffff<<16) // reserved
9422     #define ETH_PCS10_25G_REG_SEED_A1_UNUSED_0_SHIFT                                                 16
9423 #define ETH_PCS10_25G_REG_SEED_A2                                                                    0x000090UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed A bits 47:32.  Chips: K2
9424     #define ETH_PCS10_25G_REG_SEED_A2_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed A: Bits 47:32.
9425     #define ETH_PCS10_25G_REG_SEED_A2_SEED_SHIFT                                                     0
9426     #define ETH_PCS10_25G_REG_SEED_A2_UNUSED_0                                                       (0xffff<<16) // reserved
9427     #define ETH_PCS10_25G_REG_SEED_A2_UNUSED_0_SHIFT                                                 16
9428 #define ETH_PCS10_25G_REG_SEED_A3                                                                    0x000094UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed A bits 57:48.  Chips: K2
9429     #define ETH_PCS10_25G_REG_SEED_A3_SEED                                                           (0x3ff<<0) // 10GBase-R Test Pattern Seed A: Bits 57:48.
9430     #define ETH_PCS10_25G_REG_SEED_A3_SEED_SHIFT                                                     0
9431     #define ETH_PCS10_25G_REG_SEED_A3_UNUSED_0                                                       (0x3fffff<<10) // reserved
9432     #define ETH_PCS10_25G_REG_SEED_A3_UNUSED_0_SHIFT                                                 10
9433 #define ETH_PCS10_25G_REG_SEED_B0                                                                    0x000098UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed B bits 15:0.  Chips: K2
9434     #define ETH_PCS10_25G_REG_SEED_B0_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 15:0.
9435     #define ETH_PCS10_25G_REG_SEED_B0_SEED_SHIFT                                                     0
9436     #define ETH_PCS10_25G_REG_SEED_B0_UNUSED_0                                                       (0xffff<<16) // reserved
9437     #define ETH_PCS10_25G_REG_SEED_B0_UNUSED_0_SHIFT                                                 16
9438 #define ETH_PCS10_25G_REG_SEED_B1                                                                    0x00009cUL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed B bits 31:16.  Chips: K2
9439     #define ETH_PCS10_25G_REG_SEED_B1_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 31:16.
9440     #define ETH_PCS10_25G_REG_SEED_B1_SEED_SHIFT                                                     0
9441     #define ETH_PCS10_25G_REG_SEED_B1_UNUSED_0                                                       (0xffff<<16) // reserved
9442     #define ETH_PCS10_25G_REG_SEED_B1_UNUSED_0_SHIFT                                                 16
9443 #define ETH_PCS10_25G_REG_SEED_B2                                                                    0x0000a0UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed B bits 47:32.  Chips: K2
9444     #define ETH_PCS10_25G_REG_SEED_B2_SEED                                                           (0xffff<<0) // 10GBase-R Test Pattern Seed B: Bits 47:32.
9445     #define ETH_PCS10_25G_REG_SEED_B2_SEED_SHIFT                                                     0
9446     #define ETH_PCS10_25G_REG_SEED_B2_UNUSED_0                                                       (0xffff<<16) // reserved
9447     #define ETH_PCS10_25G_REG_SEED_B2_UNUSED_0_SHIFT                                                 16
9448 #define ETH_PCS10_25G_REG_SEED_B3                                                                    0x0000a4UL //Access:RW   DataWidth:0x20  10G Base-R Test Pattern Seed B bits 57:48.  Chips: K2
9449     #define ETH_PCS10_25G_REG_SEED_B3_SEED                                                           (0x3ff<<0) // 10GBase-R Test Pattern Seed B: Bits 57:48.
9450     #define ETH_PCS10_25G_REG_SEED_B3_SEED_SHIFT                                                     0
9451     #define ETH_PCS10_25G_REG_SEED_B3_UNUSED_0                                                       (0x3fffff<<10) // reserved
9452     #define ETH_PCS10_25G_REG_SEED_B3_UNUSED_0_SHIFT                                                 10
9453 #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL                                                         0x0000a8UL //Access:RW   DataWidth:0x20  Test Pattern Generator and Checker controls.  Chips: K2
9454     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL                                    (0x1<<0) // Data Pattern Select: 1=all Zero, 0=2x Local Fault; 10G only.
9455     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_DATA_PATTERN_SEL_SHIFT                              0
9456     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_SQUARE                                       (0x1<<1) // Select Square Wave (1) or Pseudo Random (0) test pattern; 10G only.
9457     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_SQUARE_SHIFT                                 1
9458     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN                                      (0x1<<2) // Receive test-pattern enable.
9459     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_RX_TESTPATTERN_SHIFT                                2
9460     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN                                      (0x1<<3) // Transmit test-pattern enable.
9461     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_TX_TESTPATTERN_SHIFT                                3
9462     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_UNUSED_0                                            (0x7<<4) // reserved
9463     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_UNUSED_0_SHIFT                                      4
9464     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_RANDOM                                       (0x1<<7) // Select Random Idle test pattern (40G); Overrides bits 1:0 when set.
9465     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_SELECT_RANDOM_SHIFT                                 7
9466     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_UNUSED_1                                            (0xffffff<<8) // reserved
9467     #define ETH_PCS10_25G_REG_BASER_TEST_CONTROL_UNUSED_1_SHIFT                                      8
9468 #define ETH_PCS10_25G_REG_BASER_TEST_ERR_CNT                                                         0x0000acUL //Access:R    DataWidth:0x20  Test Pattern Error Counter; Clears on read; None roll-over.  Chips: K2
9469     #define ETH_PCS10_25G_REG_BASER_TEST_ERR_CNT_COUNTER                                             (0xffff<<0) // Test pattern error counter; Clears on read; None roll-over.
9470     #define ETH_PCS10_25G_REG_BASER_TEST_ERR_CNT_COUNTER_SHIFT                                       0
9471     #define ETH_PCS10_25G_REG_BASER_TEST_ERR_CNT_UNUSED_0                                            (0xffff<<16) // reserved
9472     #define ETH_PCS10_25G_REG_BASER_TEST_ERR_CNT_UNUSED_0_SHIFT                                      16
9473 #define ETH_PCS10_25G_REG_BER_HIGH_ORDER_CNT                                                         0x0000b0UL //Access:R    DataWidth:0x20  BER High Order Counter of BER bits 21:6; None roll-over.  Chips: K2
9474     #define ETH_PCS10_25G_REG_BER_HIGH_ORDER_CNT_BER_COUNTER                                         (0xffff<<0) // Bits 21:6 of BER counter; None roll-over.
9475     #define ETH_PCS10_25G_REG_BER_HIGH_ORDER_CNT_BER_COUNTER_SHIFT                                   0
9476     #define ETH_PCS10_25G_REG_BER_HIGH_ORDER_CNT_UNUSED_0                                            (0xffff<<16) // reserved
9477     #define ETH_PCS10_25G_REG_BER_HIGH_ORDER_CNT_UNUSED_0_SHIFT                                      16
9478 #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT                                                     0x0000b4UL //Access:R    DataWidth:0x20  Error Blocks High Order Counter bits 21:8; None roll-over.  Chips: K2
9479     #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER                          (0x3fff<<0) // Bits 21:8 of Error Blocks counter; None roll-over.
9480     #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_ERRORED_BLOCKS_COUNTER_SHIFT                    0
9481     #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_UNUSED_0                                        (0x1<<14) // reserved
9482     #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_UNUSED_0_SHIFT                                  14
9483     #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT                              (0x1<<15) // High order counter present; Always 1.
9484     #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_HIGH_ORDER_PRESENT_SHIFT                        15
9485     #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_UNUSED_1                                        (0xffff<<16) // reserved
9486     #define ETH_PCS10_25G_REG_ERR_BLK_HIGH_ORDER_CNT_UNUSED_1_SHIFT                                  16
9487 #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1                                                      0x0000c8UL //Access:R    DataWidth:0x20  Lane Alignment Status Bits and Block Lock.  Chips: K2
9488     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_UNUSED_0                                         (0xfff<<0) // reserved
9489     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_UNUSED_0_SHIFT                                   0
9490     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS                                (0x1<<12) // Lane alignment status; 1=All Receive lanes locked and aligned.
9491     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_LANE_ALIGN_STATUS_SHIFT                          12
9492     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_UNUSED_1                                         (0x7ffff<<13) // reserved
9493     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT1_UNUSED_1_SHIFT                                   13
9494 #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3                                                      0x0000d0UL //Access:R    DataWidth:0x20  Lane Alignment Marker Lock Status bits.  Chips: K2
9495     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK                                (0x1<<0) // Lane 0 alignment marker lock.
9496     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE0_MARKER_LOCK_SHIFT                          0
9497     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK                                (0x1<<1) // Lane 1 alignment marker lock.
9498     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE1_MARKER_LOCK_SHIFT                          1
9499     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK                                (0x1<<2) // Lane 2 alignment marker lock.
9500     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE2_MARKER_LOCK_SHIFT                          2
9501     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK                                (0x1<<3) // Lane 3 alignment marker lock.
9502     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_LANE3_MARKER_LOCK_SHIFT                          3
9503     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_UNUSED_0                                         (0xfffffff<<4) // reserved
9504     #define ETH_PCS10_25G_REG_MULTILANE_ALIGN_STAT3_UNUSED_0_SHIFT                                   4
9505 #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE0                                                          0x000320UL //Access:R    DataWidth:0x20  BIP Error Counter Lane 0; Clears on read; None roll-over.  Chips: K2
9506     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE0_BIP_ERROR_COUNTER                                    (0xffff<<0) // BIP error counter lane 0; None roll-over.
9507     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE0_BIP_ERROR_COUNTER_SHIFT                              0
9508     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE0_UNUSED_0                                             (0xffff<<16) // reserved
9509     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE0_UNUSED_0_SHIFT                                       16
9510 #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE1                                                          0x000324UL //Access:R    DataWidth:0x20  BIP Error Counter Lane 1; Clears on read; None roll-over.  Chips: K2
9511     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE1_BIP_ERROR_COUNTER                                    (0xffff<<0) // BIP error counter lane 1; None roll-over.
9512     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE1_BIP_ERROR_COUNTER_SHIFT                              0
9513     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE1_UNUSED_0                                             (0xffff<<16) // reserved
9514     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE1_UNUSED_0_SHIFT                                       16
9515 #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE2                                                          0x000328UL //Access:R    DataWidth:0x20  BIP Error Counter Lane 2; Clears on read; None roll-over.  Chips: K2
9516     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE2_BIP_ERROR_COUNTER                                    (0xffff<<0) // BIP error counter lane 2; None roll-over.
9517     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE2_BIP_ERROR_COUNTER_SHIFT                              0
9518     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE2_UNUSED_0                                             (0xffff<<16) // reserved
9519     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE2_UNUSED_0_SHIFT                                       16
9520 #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE3                                                          0x00032cUL //Access:R    DataWidth:0x20  BIP Error Counter Lane 3; Clears on read; None roll-over.  Chips: K2
9521     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE3_BIP_ERROR_COUNTER                                    (0xffff<<0) // BIP error counter lane 3; None roll-over.
9522     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE3_BIP_ERROR_COUNTER_SHIFT                              0
9523     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE3_UNUSED_0                                             (0xffff<<16) // reserved
9524     #define ETH_PCS10_25G_REG_BIP_ERR_CNT_LANE3_UNUSED_0_SHIFT                                       16
9525 #define ETH_PCS10_25G_REG_VENDOR_SCRATCH                                                             0x020000UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Scratch Register.  Chips: K2
9526     #define ETH_PCS10_25G_REG_VENDOR_SCRATCH_SCRATCH                                                 (0xffff<<0) // Scratch Register; Register address to test read and write operation.
9527     #define ETH_PCS10_25G_REG_VENDOR_SCRATCH_SCRATCH_SHIFT                                           0
9528     #define ETH_PCS10_25G_REG_VENDOR_SCRATCH_UNUSED_0                                                (0xffff<<16) // reserved
9529     #define ETH_PCS10_25G_REG_VENDOR_SCRATCH_UNUSED_0_SHIFT                                          16
9530 #define ETH_PCS10_25G_REG_VENDOR_CORE_REV                                                            0x020004UL //Access:R    DataWidth:0x20  Vendor Specific Reg; Core Revision derived from DEV_VERSION package parameter.  Chips: K2
9531     #define ETH_PCS10_25G_REG_VENDOR_CORE_REV_REVISION                                               (0xffff<<0) // Core Design version as defined by DEV_VERSION parameter in PCS package file.
9532     #define ETH_PCS10_25G_REG_VENDOR_CORE_REV_REVISION_SHIFT                                         0
9533     #define ETH_PCS10_25G_REG_VENDOR_CORE_REV_UNUSED_0                                               (0xffff<<16) // reserved
9534     #define ETH_PCS10_25G_REG_VENDOR_CORE_REV_UNUSED_0_SHIFT                                         16
9535 #define ETH_PCS10_25G_REG_VENDOR_VL_INTVL                                                            0x020008UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Set the amount of data between markers. (I.e. distance of markers-1).  Chips: K2
9536     #define ETH_PCS10_25G_REG_VENDOR_VL_INTVL_MARKER_COUNTER                                         (0xffff<<0) // A 16-bit value defining the amount of data between markers; (distance of markers-1).
9537     #define ETH_PCS10_25G_REG_VENDOR_VL_INTVL_MARKER_COUNTER_SHIFT                                   0
9538     #define ETH_PCS10_25G_REG_VENDOR_VL_INTVL_UNUSED_0                                               (0xffff<<16) // reserved
9539     #define ETH_PCS10_25G_REG_VENDOR_VL_INTVL_UNUSED_0_SHIFT                                         16
9540 #define ETH_PCS10_25G_REG_VENDOR_TXLANE_THRESH                                                       0x02000cUL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Defines the transmit line decoupling FIFOs almost full threshold.  Chips: K2
9541     #define ETH_PCS10_25G_REG_VENDOR_TXLANE_THRESH_THRESHOLD                                         (0xf<<0) // A 4-bit value to define the transmit line decoupling FIFOs almost full threshold; Valid values are 4..9.
9542     #define ETH_PCS10_25G_REG_VENDOR_TXLANE_THRESH_THRESHOLD_SHIFT                                   0
9543     #define ETH_PCS10_25G_REG_VENDOR_TXLANE_THRESH_UNUSED_0                                          (0xfffffff<<4) // reserved
9544     #define ETH_PCS10_25G_REG_VENDOR_TXLANE_THRESH_UNUSED_0_SHIFT                                    4
9545 #define ETH_PCS10_25G_REG_VENDOR_VL0_0                                                               0x020020UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Marker pattern for PCS Virtual Lane 0.  Chips: K2
9546     #define ETH_PCS10_25G_REG_VENDOR_VL0_0_M0                                                        (0xff<<0) // Lane 0 Marker pattern for m0.
9547     #define ETH_PCS10_25G_REG_VENDOR_VL0_0_M0_SHIFT                                                  0
9548     #define ETH_PCS10_25G_REG_VENDOR_VL0_0_M1                                                        (0xff<<8) // Lane 0 Marker pattern for m1.
9549     #define ETH_PCS10_25G_REG_VENDOR_VL0_0_M1_SHIFT                                                  8
9550     #define ETH_PCS10_25G_REG_VENDOR_VL0_0_UNUSED_0                                                  (0xffff<<16) // reserved
9551     #define ETH_PCS10_25G_REG_VENDOR_VL0_0_UNUSED_0_SHIFT                                            16
9552 #define ETH_PCS10_25G_REG_VENDOR_VL0_1                                                               0x020024UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Last byte of PCS Virtual Lane 0 marker pattern.  Chips: K2
9553     #define ETH_PCS10_25G_REG_VENDOR_VL0_1_M2                                                        (0xff<<0) // Lane 0 last btye of Marker pattern for m2.
9554     #define ETH_PCS10_25G_REG_VENDOR_VL0_1_M2_SHIFT                                                  0
9555     #define ETH_PCS10_25G_REG_VENDOR_VL0_1_UNUSED_0                                                  (0xffffff<<8) // reserved
9556     #define ETH_PCS10_25G_REG_VENDOR_VL0_1_UNUSED_0_SHIFT                                            8
9557 #define ETH_PCS10_25G_REG_VENDOR_VL1_0                                                               0x020028UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Marker pattern for PCS Virtual Lane 1.  Chips: K2
9558     #define ETH_PCS10_25G_REG_VENDOR_VL1_0_M0                                                        (0xff<<0) // Lane 1 Marker pattern for m0.
9559     #define ETH_PCS10_25G_REG_VENDOR_VL1_0_M0_SHIFT                                                  0
9560     #define ETH_PCS10_25G_REG_VENDOR_VL1_0_M1                                                        (0xff<<8) // Lane 1 Marker pattern for m1.
9561     #define ETH_PCS10_25G_REG_VENDOR_VL1_0_M1_SHIFT                                                  8
9562     #define ETH_PCS10_25G_REG_VENDOR_VL1_0_UNUSED_0                                                  (0xffff<<16) // reserved
9563     #define ETH_PCS10_25G_REG_VENDOR_VL1_0_UNUSED_0_SHIFT                                            16
9564 #define ETH_PCS10_25G_REG_VENDOR_VL1_1                                                               0x02002cUL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Last byte of PCS Virtual Lane 1 marker pattern.  Chips: K2
9565     #define ETH_PCS10_25G_REG_VENDOR_VL1_1_M2                                                        (0xff<<0) // Lane 1 last btye of Marker pattern for m2.
9566     #define ETH_PCS10_25G_REG_VENDOR_VL1_1_M2_SHIFT                                                  0
9567     #define ETH_PCS10_25G_REG_VENDOR_VL1_1_UNUSED_0                                                  (0xffffff<<8) // reserved
9568     #define ETH_PCS10_25G_REG_VENDOR_VL1_1_UNUSED_0_SHIFT                                            8
9569 #define ETH_PCS10_25G_REG_VENDOR_VL2_0                                                               0x020030UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Marker pattern for PCS Virtual Lane 2.  Chips: K2
9570     #define ETH_PCS10_25G_REG_VENDOR_VL2_0_M0                                                        (0xff<<0) // Lane 2 Marker pattern for m0.
9571     #define ETH_PCS10_25G_REG_VENDOR_VL2_0_M0_SHIFT                                                  0
9572     #define ETH_PCS10_25G_REG_VENDOR_VL2_0_M1                                                        (0xff<<8) // Lane 2 Marker pattern for m1.
9573     #define ETH_PCS10_25G_REG_VENDOR_VL2_0_M1_SHIFT                                                  8
9574     #define ETH_PCS10_25G_REG_VENDOR_VL2_0_UNUSED_0                                                  (0xffff<<16) // reserved
9575     #define ETH_PCS10_25G_REG_VENDOR_VL2_0_UNUSED_0_SHIFT                                            16
9576 #define ETH_PCS10_25G_REG_VENDOR_VL2_1                                                               0x020034UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Last byte of PCS Virtual Lane 2 marker pattern.  Chips: K2
9577     #define ETH_PCS10_25G_REG_VENDOR_VL2_1_M2                                                        (0xff<<0) // Lane 2 last btye of Marker pattern for m2.
9578     #define ETH_PCS10_25G_REG_VENDOR_VL2_1_M2_SHIFT                                                  0
9579     #define ETH_PCS10_25G_REG_VENDOR_VL2_1_UNUSED_0                                                  (0xffffff<<8) // reserved
9580     #define ETH_PCS10_25G_REG_VENDOR_VL2_1_UNUSED_0_SHIFT                                            8
9581 #define ETH_PCS10_25G_REG_VENDOR_VL3_0                                                               0x020038UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Marker pattern for PCS Virtual Lane 3.  Chips: K2
9582     #define ETH_PCS10_25G_REG_VENDOR_VL3_0_M0                                                        (0xff<<0) // Lane 3 Marker pattern for m0.
9583     #define ETH_PCS10_25G_REG_VENDOR_VL3_0_M0_SHIFT                                                  0
9584     #define ETH_PCS10_25G_REG_VENDOR_VL3_0_M1                                                        (0xff<<8) // Lane 3 Marker pattern for m1.
9585     #define ETH_PCS10_25G_REG_VENDOR_VL3_0_M1_SHIFT                                                  8
9586     #define ETH_PCS10_25G_REG_VENDOR_VL3_0_UNUSED_0                                                  (0xffff<<16) // reserved
9587     #define ETH_PCS10_25G_REG_VENDOR_VL3_0_UNUSED_0_SHIFT                                            16
9588 #define ETH_PCS10_25G_REG_VENDOR_VL3_1                                                               0x02003cUL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Last byte of PCS Virtual Lane 3 marker pattern.  Chips: K2
9589     #define ETH_PCS10_25G_REG_VENDOR_VL3_1_M2                                                        (0xff<<0) // Lane 3 last btye of Marker pattern for m2.
9590     #define ETH_PCS10_25G_REG_VENDOR_VL3_1_M2_SHIFT                                                  0
9591     #define ETH_PCS10_25G_REG_VENDOR_VL3_1_UNUSED_0                                                  (0xffffff<<8) // reserved
9592     #define ETH_PCS10_25G_REG_VENDOR_VL3_1_UNUSED_0_SHIFT                                            8
9593 #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE                                                            0x020040UL //Access:RW   DataWidth:0x20  Vendor Specific Reg; Configure PCS supporting Clause 49 or 82 Encoder/Decoder, MLD.  Chips: K2
9594     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49                                           (0x1<<0) // When 0 PCS uses Clause 82 encoder/decoder functions; When 1 PCS uses Clause 49 encoder/decoder functions.
9595     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ENA_CLAUSE49_SHIFT                                     0
9596     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_DISABLE_MLD                                            (0x1<<1) // When 0 PCS 4-lane MLD function is active; When 1 the MLD function is disabled.
9597     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_DISABLE_MLD_SHIFT                                      1
9598     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_UNUSED_0                                               (0x3f<<2) // reserved
9599     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_UNUSED_0_SHIFT                                         2
9600     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49                                        (0x1<<8) // Current status of Clause 49 setting.
9601     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_ENA_CLAUSE49_SHIFT                                  8
9602     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD                                         (0x1<<9) // Current status of MLD setting.
9603     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_ST_DISABLE_MLD_SHIFT                                   9
9604     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_UNUSED_1                                               (0x3fffff<<10) // reserved
9605     #define ETH_PCS10_25G_REG_VENDOR_PCS_MODE_UNUSED_1_SHIFT                                         10
9606 #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0                                                       0x0000e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9607     #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0_ATEST_EN                                          (0xf<<0) // Analog test mode enable. Controls the macro that drives the atest1_o/atest2_o bumps located over the CMU macro.  0x0 - off high-impedance 0x1 - CMU 0 0x3 - Lane 0 0x4 - Lane 1 0x5 - Lane 2 0x6 - Lane 3 0x15 - SoC circuitry. PHY input pins soc_atest1_i and soc_atest2_i are shorted to atest1_o and atest2_o respectively. rest - reserved
9608     #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0_ATEST_EN_SHIFT                                    0
9609     #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0_UNUSED_0                                          (0xf<<4) // reserved
9610     #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL0_UNUSED_0_SHIFT                                    4
9611 #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL1                                                       0x0000e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9612     #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL1_ATEST_SEL                                         (0x3f<<0) // Analog test mode select. Controls the internal analog voltage or current from the respective macro sent to the atest1_o/atest2_o bumps located over the CMU macro.  Decoding table is provided in separate documentation.
9613     #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL1_ATEST_SEL_SHIFT                                   0
9614     #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL1_UNUSED_0                                          (0x3<<6) // reserved
9615     #define PHY_NW_IP_REG_PHY0_TOP_AFE_ATEST_CTRL1_UNUSED_0_SHIFT                                    6
9616 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1                                            0x0003e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9617     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_UNUSED_0                               (0x7f<<0) // reserved
9618     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_UNUSED_0_SHIFT                         0
9619     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN                         (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_lc0_clk_cmu.
9620     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMU_CTRL1_TBUS_OUT_CG_EN_SHIFT                   7
9621 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1                                         0x0003e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9622     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_UNUSED_0                            (0x7f<<0) // reserved
9623     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_UNUSED_0_SHIFT                      0
9624     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN                      (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_lc0_clk_cmudiv.
9625     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_LC0_CLK_CMUDIV_CTRL1_TBUS_OUT_CG_EN_SHIFT                7
9626 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1                                            0x00040cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9627     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_UNUSED_0                               (0x7f<<0) // reserved
9628     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_UNUSED_0_SHIFT                         0
9629     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_TBUS_OUT_CG_EN                         (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll2.
9630     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2_CTRL1_TBUS_OUT_CG_EN_SHIFT                   7
9631 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1                                         0x000414UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9632     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_UNUSED_0                            (0x7f<<0) // reserved
9633     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_UNUSED_0_SHIFT                      0
9634     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_TBUS_OUT_CG_EN                      (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll2div.
9635     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL2DIV_CTRL1_TBUS_OUT_CG_EN_SHIFT                7
9636 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1                                            0x00041cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9637     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_UNUSED_0                               (0x7f<<0) // reserved
9638     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_UNUSED_0_SHIFT                         0
9639     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_TBUS_OUT_CG_EN                         (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll3.
9640     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3_CTRL1_TBUS_OUT_CG_EN_SHIFT                   7
9641 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1                                         0x000424UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9642     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_UNUSED_0                            (0x7f<<0) // reserved
9643     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_UNUSED_0_SHIFT                      0
9644     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_TBUS_OUT_CG_EN                      (0x1<<7) // Clock gate enable for the TBUS debug output branch of cm_r0_clk_pll3div.
9645     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_CM_R0_CLK_PLL3DIV_CTRL1_TBUS_OUT_CG_EN_SHIFT                7
9646 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX                                                      0x000440UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9647     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL                                     (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln0_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
9648     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_SRC_SEL_SHIFT                               0
9649     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_UNUSED_0                                         (0x3<<2) // reserved
9650     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_UNUSED_0_SHIFT                                   2
9651     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN                                  (0x1<<4) // Clock gate enable for TX bist clock branch
9652     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_CTRL_BIST_CG_EN_SHIFT                            4
9653     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_UNUSED_1                                         (0x7<<5) // reserved
9654     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_TX_UNUSED_1_SHIFT                                   5
9655 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX                                                      0x000448UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9656     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_UNUSED_0                                         (0xf<<0) // reserved
9657     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_UNUSED_0_SHIFT                                   0
9658     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN                                       (0x1<<4) // Clock gate enable for RX clock output to customer logics
9659     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_CG_EN_SHIFT                                 4
9660     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN                                  (0x1<<5) // Clock gate enable for RX bist clock branch
9661     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_CTRL_BIST_CG_EN_SHIFT                            5
9662     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_UNUSED_1                                         (0x3<<6) // reserved
9663     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN0_CLK_RX_UNUSED_1_SHIFT                                   6
9664 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX                                                      0x000460UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9665     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL                                     (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln1_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
9666     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_SRC_SEL_SHIFT                               0
9667     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_UNUSED_0                                         (0x3<<2) // reserved
9668     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_UNUSED_0_SHIFT                                   2
9669     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN                                  (0x1<<4) // Clock gate enable for TX bist clock branch
9670     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_CTRL_BIST_CG_EN_SHIFT                            4
9671     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_UNUSED_1                                         (0x7<<5) // reserved
9672     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_TX_UNUSED_1_SHIFT                                   5
9673 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX                                                      0x000468UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9674     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_UNUSED_0                                         (0xf<<0) // reserved
9675     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_UNUSED_0_SHIFT                                   0
9676     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN                                       (0x1<<4) // Clock gate enable for RX clock output to customer logics
9677     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_CG_EN_SHIFT                                 4
9678     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN                                  (0x1<<5) // Clock gate enable for RX bist clock branch
9679     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_CTRL_BIST_CG_EN_SHIFT                            5
9680     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_UNUSED_1                                         (0x3<<6) // reserved
9681     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN1_CLK_RX_UNUSED_1_SHIFT                                   6
9682 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX                                                      0x000480UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9683     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL                                     (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln2_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
9684     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_SRC_SEL_SHIFT                               0
9685     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_UNUSED_0                                         (0x3<<2) // reserved
9686     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_UNUSED_0_SHIFT                                   2
9687     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN                                  (0x1<<4) // Clock gate enable for TX bist clock branch
9688     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_CTRL_BIST_CG_EN_SHIFT                            4
9689     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_UNUSED_1                                         (0x7<<5) // reserved
9690     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_TX_UNUSED_1_SHIFT                                   5
9691 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX                                                      0x000488UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9692     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_UNUSED_0                                         (0xf<<0) // reserved
9693     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_UNUSED_0_SHIFT                                   0
9694     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN                                       (0x1<<4) // Clock gate enable for RX clock output to customer logics
9695     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_CG_EN_SHIFT                                 4
9696     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN                                  (0x1<<5) // Clock gate enable for RX bist clock branch
9697     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_CTRL_BIST_CG_EN_SHIFT                            5
9698     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_UNUSED_1                                         (0x3<<6) // reserved
9699     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN2_CLK_RX_UNUSED_1_SHIFT                                   6
9700 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX                                                      0x0004a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9701     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL                                     (0x3<<0) // Clock source select for lane 0 TX clock. 0x0: ln3_txclk_i PHY input clock 0x1: rx clock 0x2: cmu clock 0x3: test clock
9702     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_SRC_SEL_SHIFT                               0
9703     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_UNUSED_0                                         (0x3<<2) // reserved
9704     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_UNUSED_0_SHIFT                                   2
9705     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN                                  (0x1<<4) // Clock gate enable for TX bist clock branch
9706     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_CTRL_BIST_CG_EN_SHIFT                            4
9707     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_UNUSED_1                                         (0x7<<5) // reserved
9708     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_TX_UNUSED_1_SHIFT                                   5
9709 #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX                                                      0x0004a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9710     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_UNUSED_0                                         (0xf<<0) // reserved
9711     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_UNUSED_0_SHIFT                                   0
9712     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN                                       (0x1<<4) // Clock gate enable for RX clock output to customer logics
9713     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_CG_EN_SHIFT                                 4
9714     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN                                  (0x1<<5) // Clock gate enable for RX bist clock branch
9715     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_CTRL_BIST_CG_EN_SHIFT                            5
9716     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_UNUSED_1                                         (0x3<<6) // reserved
9717     #define PHY_NW_IP_REG_PHY0_TOP_CLOCK_LN3_CLK_RX_UNUSED_1_SHIFT                                   6
9718 #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0                                                             0x000600UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9719     #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0_ERR                                                     (0x1<<0) // PHY error status. 0x0 - no error 0x1 - PHY has an internal error detected by firmware. PHY error code can be used to isolate error event.  Decoding table is provided in separate documentation.
9720     #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0_ERR_SHIFT                                               0
9721     #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0_UNUSED_0                                                (0x7f<<1) // reserved
9722     #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL0_UNUSED_0_SHIFT                                          1
9723 #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL1                                                             0x000604UL //Access:RW   DataWidth:0x8   lower 8-bits of 16-bit PHY error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
9724 #define PHY_NW_IP_REG_PHY0_TOP_ERR_CTRL2                                                             0x000608UL //Access:RW   DataWidth:0x8   higher 8-bits of 16-bit PHY error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
9725 #define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0                                                           0x000614UL //Access:W    DataWidth:0x8   Multi Field Register.  Chips: K2
9726     #define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0_REGBUS_ERR                                            (0x1<<0) // Rebug error status.  Write 1 to clear.
9727     #define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0_REGBUS_ERR_SHIFT                                      0
9728     #define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0_UNUSED_0                                              (0x7f<<1) // reserved
9729     #define PHY_NW_IP_REG_PHY0_TOP_ERR_STATUS0_UNUSED_0_SHIFT                                        1
9730 #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL                                                  0x00061cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9731     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL_CLR                                          (0x1<<0) // Clear the debug info presented in REGBUS_ERR_INFO_STATUS* registers.
9732     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL_CLR_SHIFT                                    0
9733     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL_UNUSED_0                                     (0x7f<<1) // reserved
9734     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_CTRL_UNUSED_0_SHIFT                               1
9735 #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0                                               0x000620UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
9736     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE                                  (0x3<<0) // Type of error: 1 = err ack 2 = timeout
9737     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_ERR_TYPE_SHIFT                            0
9738     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW                               (0x1<<2) // Errored register transfer type: 0 = read transfer 1 = write transfer
9739     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_TRANSFER_RW_SHIFT                         2
9740     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_UNUSED_0                                  (0x1f<<3) // reserved
9741     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS0_UNUSED_0_SHIFT                            3
9742 #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS1                                               0x000624UL //Access:R    DataWidth:0x8   Errored register transfer address low 8 bits  Chips: K2
9743 #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS2                                               0x000628UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
9744     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB                         (0x7f<<0) // Errored register transfer address upper bits
9745     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS2_TRANSFER_ADDR_MSB_SHIFT                   0
9746     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS2_UNUSED_0                                  (0x1<<7) // reserved
9747     #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS2_UNUSED_0_SHIFT                            7
9748 #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS3                                               0x00062cUL //Access:R    DataWidth:0x8   Errored register transfer write data  Chips: K2
9749 #define PHY_NW_IP_REG_PHY0_TOP_REGBUS_ERR_INFO_STATUS4                                               0x000630UL //Access:R    DataWidth:0x8   Errored register transfer write data bit enable  Chips: K2
9750 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0                                                         0x000680UL //Access:RW   DataWidth:0x8   lower 8-bits of the 16-bit digital test bus tbus address. Decoding table is provided in separate documentation.  Chips: K2
9751 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8                                                        0x000684UL //Access:RW   DataWidth:0x8   higher 8-bits of the 16-bit digital test bus tbus address. Decoding table is provided in separate documentation.  Chips: K2
9752 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0                                                         0x0006c0UL //Access:R    DataWidth:0x8   Digital test bus tbus output bits [7:0]  Chips: K2
9753 #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8                                                        0x0006c4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
9754     #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_F3                                                 (0xf<<0) // Digital test bus tbus output bits [11:8]
9755     #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_F3_SHIFT                                           0
9756     #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_UNUSED_0                                           (0xf<<4) // reserved
9757     #define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_UNUSED_0_SHIFT                                     4
9758 #define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL                                                              0x000700UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9759     #define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL_SIM_1B_MODEL                                             (0x1<<0) // Set if running a 1b simulation.  Firmware may check this field to discover its runtime context.  Do not set on actual silicon.
9760     #define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL_SIM_1B_MODEL_SHIFT                                       0
9761     #define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL_UNUSED_0                                                 (0x7f<<1) // reserved
9762     #define PHY_NW_IP_REG_PHY0_TOP_SIM_CTRL_UNUSED_0_SHIFT                                           1
9763 #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL                                                               0x000704UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9764     #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_UNUSED_0                                                  (0x1<<0) // reserved
9765     #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_UNUSED_0_SHIFT                                            0
9766     #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_CRC_DISABLE                                               (0x1<<1) // Prevents firmware from running program memory CRC integrity check at boot up. Must be written before releasing cpu_reset_i
9767     #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_CRC_DISABLE_SHIFT                                         1
9768     #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_UNUSED_1                                                  (0x3f<<2) // reserved
9769     #define PHY_NW_IP_REG_PHY0_TOP_FW_CTRL_UNUSED_1_SHIFT                                            2
9770 #define PHY_NW_IP_REG_PHY0_MB_CMD                                                                    0x000800UL //Access:RW   DataWidth:0x8   Command to the PHY firmware. It is expected that only the APB master writes to the command register.  Upon a write to this register, CMD_FLAG is set automatically.  Chips: K2
9771 #define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG                                                               0x000808UL //Access:W    DataWidth:0x8   Multi Field Register.  Chips: K2
9772     #define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG_F5                                                        (0x1<<0) // Indicates the presence of a new command to the PHY firmware. It is set automatically when CMD is written. It is expected to be cleared by the PHY firmware by writing 1 to it.
9773     #define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG_F5_SHIFT                                                  0
9774     #define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG_UNUSED_0                                                  (0x7f<<1) // reserved
9775     #define PHY_NW_IP_REG_PHY0_MB_CMD_FLAG_UNUSED_0_SHIFT                                            1
9776 #define PHY_NW_IP_REG_PHY0_MB_CMD_DATA0                                                              0x00080cUL //Access:RW   DataWidth:0x8   Command auxiliary data or argument 0  Chips: K2
9777 #define PHY_NW_IP_REG_PHY0_MB_CMD_DATA1                                                              0x000810UL //Access:RW   DataWidth:0x8   Command auxiliary data or argument 1  Chips: K2
9778 #define PHY_NW_IP_REG_PHY0_MB_CMD_DATA2                                                              0x000814UL //Access:RW   DataWidth:0x8   Command auxiliary data or argument 2  Chips: K2
9779 #define PHY_NW_IP_REG_PHY0_MB_CMD_DATA3                                                              0x000818UL //Access:RW   DataWidth:0x8   Command auxiliary data or argument 3  Chips: K2
9780 #define PHY_NW_IP_REG_PHY0_MB_CMD_DATA4                                                              0x00081cUL //Access:RW   DataWidth:0x8   Command auxiliary data or argument 4  Chips: K2
9781 #define PHY_NW_IP_REG_PHY0_MB_CMD_DATA5                                                              0x000820UL //Access:RW   DataWidth:0x8   Command auxiliary data or argument 5  Chips: K2
9782 #define PHY_NW_IP_REG_PHY0_MB_CMD_DATA6                                                              0x000824UL //Access:RW   DataWidth:0x8   Command auxiliary data or argument 6  Chips: K2
9783 #define PHY_NW_IP_REG_PHY0_MB_CMD_DATA7                                                              0x000828UL //Access:RW   DataWidth:0x8   Command auxiliary data or argument 7  Chips: K2
9784 #define PHY_NW_IP_REG_PHY0_MB_RSP                                                                    0x000840UL //Access:RW   DataWidth:0x8   Response to the PHY firmware. It is expected that only the APB master writes to the Response register.  Upon a write to this register, RSP_FLAG is set automatically.  Chips: K2
9785 #define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG                                                               0x000848UL //Access:W    DataWidth:0x8   Multi Field Register.  Chips: K2
9786     #define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG_F15                                                       (0x1<<0) // Indicates the presence of a new Response to the PHY firmware. It is set automatically when RSP is written. It is expected to be cleared by the PHY firmware by writing 1 to it.
9787     #define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG_F15_SHIFT                                                 0
9788     #define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG_UNUSED_0                                                  (0x7f<<1) // reserved
9789     #define PHY_NW_IP_REG_PHY0_MB_RSP_FLAG_UNUSED_0_SHIFT                                            1
9790 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA0                                                              0x00084cUL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 0  Chips: K2
9791 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA1                                                              0x000850UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 1  Chips: K2
9792 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA2                                                              0x000854UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 2  Chips: K2
9793 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA3                                                              0x000858UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 3  Chips: K2
9794 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA4                                                              0x00085cUL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 4  Chips: K2
9795 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA5                                                              0x000860UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 5  Chips: K2
9796 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA6                                                              0x000864UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 6  Chips: K2
9797 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA7                                                              0x000868UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 7  Chips: K2
9798 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA8                                                              0x00086cUL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 8  Chips: K2
9799 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA9                                                              0x000870UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 9  Chips: K2
9800 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA10                                                             0x000874UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 10  Chips: K2
9801 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA11                                                             0x000878UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 11  Chips: K2
9802 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA12                                                             0x00087cUL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 12  Chips: K2
9803 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA13                                                             0x000880UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 13  Chips: K2
9804 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA14                                                             0x000884UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 14  Chips: K2
9805 #define PHY_NW_IP_REG_PHY0_MB_RSP_DATA15                                                             0x000888UL //Access:RW   DataWidth:0x8   Response auxiliary data or argument 15  Chips: K2
9806 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_EN                                          0x000c00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9807     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_EN_F32                                  (0x1<<0) // Override enable for afe_calcomp_offset AFE ovr_signal.
9808     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_EN_F32_SHIFT                            0
9809     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_EN_UNUSED_0                             (0x7f<<1) // reserved
9810     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_EN_UNUSED_0_SHIFT                       1
9811 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_VAL                                         0x000c04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9812     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_VAL_F33                                 (0x3f<<0) // Override value for afe_calcomp_offset AFE input.
9813     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_VAL_F33_SHIFT                           0
9814     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_VAL_UNUSED_0                            (0x3<<6) // reserved
9815     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OFFSET_OVR_VAL_UNUSED_0_SHIFT                      6
9816 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_EN                                             0x000c08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9817     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_EN_F34                                     (0x1<<0) // Override enable for afe_calcomp_out AFE ovr_signal.
9818     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_EN_F34_SHIFT                               0
9819     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
9820     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_EN_UNUSED_0_SHIFT                          1
9821 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_VAL                                            0x000c0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9822     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_VAL_F35                                    (0x1<<0) // Override value for afe_calcomp_out AFE input.
9823     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_VAL_F35_SHIFT                              0
9824     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_VAL_UNUSED_0                               (0x7f<<1) // reserved
9825     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CALCOMP_OUT_OVR_VAL_UNUSED_0_SHIFT                         1
9826 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_EN                                      0x000c10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9827     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_EN_F36                              (0x1<<0) // Override enable for afe_cmcp_clki_dcd_trim AFE ovr_signal.
9828     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_EN_F36_SHIFT                        0
9829     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_EN_UNUSED_0                         (0x7f<<1) // reserved
9830     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_EN_UNUSED_0_SHIFT                   1
9831 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_VAL                                     0x000c14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9832     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_VAL_F37                             (0x1f<<0) // Override value for afe_cmcp_clki_dcd_trim AFE input.
9833     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_VAL_F37_SHIFT                       0
9834     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_VAL_UNUSED_0                        (0x7<<5) // reserved
9835     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKI_DCD_TRIM_OVR_VAL_UNUSED_0_SHIFT                  5
9836 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_EN                                      0x000c18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9837     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_EN_F38                              (0x1<<0) // Override enable for afe_cmcp_clkq_dcd_trim AFE ovr_signal.
9838     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_EN_F38_SHIFT                        0
9839     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_EN_UNUSED_0                         (0x7f<<1) // reserved
9840     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_EN_UNUSED_0_SHIFT                   1
9841 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_VAL                                     0x000c1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9842     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_VAL_F39                             (0x1f<<0) // Override value for afe_cmcp_clkq_dcd_trim AFE input.
9843     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_VAL_F39_SHIFT                       0
9844     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_VAL_UNUSED_0                        (0x7<<5) // reserved
9845     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_CLKQ_DCD_TRIM_OVR_VAL_UNUSED_0_SHIFT                  5
9846 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_EN                                     0x000c20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9847     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_EN_F40                             (0x1<<0) // Override enable for afe_cmcp_div1p5_qsample AFE ovr_signal.
9848     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_EN_F40_SHIFT                       0
9849     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_EN_UNUSED_0                        (0x7f<<1) // reserved
9850     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                  1
9851 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_VAL                                    0x000c24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9852     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_VAL_F41                            (0xf<<0) // Override value for afe_cmcp_div1p5_qsample AFE input.
9853     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_VAL_F41_SHIFT                      0
9854     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_VAL_UNUSED_0                       (0xf<<4) // reserved
9855     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_DIV1P5_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                 4
9856 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_EN                                            0x000c28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9857     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_EN_F42                                    (0x1<<0) // Override enable for afe_cmcp_iq_trim AFE ovr_signal.
9858     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_EN_F42_SHIFT                              0
9859     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
9860     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_EN_UNUSED_0_SHIFT                         1
9861 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_VAL                                           0x000c2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9862     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_VAL_F43                                   (0x1f<<0) // Override value for afe_cmcp_iq_trim AFE input.
9863     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_VAL_F43_SHIFT                             0
9864     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
9865     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMCP_IQ_TRIM_OVR_VAL_UNUSED_0_SHIFT                        5
9866 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_EN                                    0x000c30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9867     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_EN_F44                            (0x1<<0) // Override enable for afe_cmpll_clkdiv_qsample AFE ovr_signal.
9868     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_EN_F44_SHIFT                      0
9869     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0                       (0x7f<<1) // reserved
9870     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                 1
9871 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_VAL                                   0x000c34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9872     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_VAL_F45                           (0x1<<0) // Override value for afe_cmpll_clkdiv_qsample AFE input.
9873     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_VAL_F45_SHIFT                     0
9874     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0                      (0x7f<<1) // reserved
9875     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                1
9876 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_EN                                             0x000c38UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9877     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_EN_F46                                     (0x1<<0) // Override enable for afe_cmpll_degen AFE ovr_signal.
9878     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_EN_F46_SHIFT                               0
9879     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
9880     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_EN_UNUSED_0_SHIFT                          1
9881 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_VAL                                            0x000c3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9882     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_VAL_F47                                    (0xf<<0) // Override value for afe_cmpll_degen AFE input.
9883     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_VAL_F47_SHIFT                              0
9884     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_VAL_UNUSED_0                               (0xf<<4) // reserved
9885     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DEGEN_OVR_VAL_UNUSED_0_SHIFT                         4
9886 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DOSC_OVR_EN                                              0x000c40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9887     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DOSC_OVR_EN_F48                                      (0x1<<0) // Override enable for afe_cmpll_dosc AFE ovr_signal.
9888     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DOSC_OVR_EN_F48_SHIFT                                0
9889     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DOSC_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
9890     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DOSC_OVR_EN_UNUSED_0_SHIFT                           1
9891 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_DOSC_OVR_VAL                                             0x000c44UL //Access:RW   DataWidth:0x8   Override value for afe_cmpll_dosc AFE input.  Chips: K2
9892 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_EN                                              0x000c48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9893     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_EN_F50                                      (0x1<<0) // Override enable for afe_cmpll_ndiv AFE ovr_signal.
9894     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_EN_F50_SHIFT                                0
9895     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
9896     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_EN_UNUSED_0_SHIFT                           1
9897 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_VAL                                             0x000c4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9898     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_VAL_F51                                     (0x7f<<0) // Override value for afe_cmpll_ndiv AFE input.
9899     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_VAL_F51_SHIFT                               0
9900     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_VAL_UNUSED_0                                (0x1<<7) // reserved
9901     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_NDIV_OVR_VAL_UNUSED_0_SHIFT                          7
9902 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_EN                                              0x000c50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9903     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_EN_F52                                      (0x1<<0) // Override enable for afe_cmpll_psel AFE ovr_signal.
9904     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_EN_F52_SHIFT                                0
9905     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
9906     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_EN_UNUSED_0_SHIFT                           1
9907 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_VAL                                             0x000c54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9908     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_VAL_F53                                     (0x7<<0) // Override value for afe_cmpll_psel AFE input.
9909     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_VAL_F53_SHIFT                               0
9910     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_VAL_UNUSED_0                                (0x1f<<3) // reserved
9911     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_PSEL_OVR_VAL_UNUSED_0_SHIFT                          3
9912 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_EN                                           0x000c58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9913     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_EN_F54                                   (0x1<<0) // Override enable for afe_cmpll_qsample AFE ovr_signal.
9914     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_EN_F54_SHIFT                             0
9915     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
9916     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                        1
9917 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_VAL                                          0x000c5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9918     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_VAL_F55                                  (0x1<<0) // Override value for afe_cmpll_qsample AFE input.
9919     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_VAL_F55_SHIFT                            0
9920     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_VAL_UNUSED_0                             (0x7f<<1) // reserved
9921     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                       1
9922 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_EN                                         0x000c60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9923     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_EN_F56                                 (0x1<<0) // Override enable for afe_cmpll_vco_swing AFE ovr_signal.
9924     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_EN_F56_SHIFT                           0
9925     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_EN_UNUSED_0                            (0x7f<<1) // reserved
9926     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_EN_UNUSED_0_SHIFT                      1
9927 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_VAL                                        0x000c64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9928     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_VAL_F57                                (0xf<<0) // Override value for afe_cmpll_vco_swing AFE input.
9929     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_VAL_F57_SHIFT                          0
9930     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_VAL_UNUSED_0                           (0xf<<4) // reserved
9931     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_CMPLL_VCO_SWING_OVR_VAL_UNUSED_0_SHIFT                     4
9932 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_EN                                        0x000c68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9933     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_EN_F58                                (0x1<<0) // Override enable for afe_refclk_input_sel AFE ovr_signal.
9934     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_EN_F58_SHIFT                          0
9935     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
9936     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_EN_UNUSED_0_SHIFT                     1
9937 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_VAL                                       0x000c6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9938     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_VAL_F59                               (0x3<<0) // Override value for afe_refclk_input_sel AFE input.
9939     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_VAL_F59_SHIFT                         0
9940     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_VAL_UNUSED_0                          (0x3f<<2) // reserved
9941     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_INPUT_SEL_OVR_VAL_UNUSED_0_SHIFT                    2
9942 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_EN                                         0x000c70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9943     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_EN_F60                                 (0x1<<0) // Override enable for afe_refclk_left_sel AFE ovr_signal.
9944     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_EN_F60_SHIFT                           0
9945     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_EN_UNUSED_0                            (0x7f<<1) // reserved
9946     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_EN_UNUSED_0_SHIFT                      1
9947 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_VAL                                        0x000c74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9948     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_VAL_F61                                (0x3<<0) // Override value for afe_refclk_left_sel AFE input.
9949     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_VAL_F61_SHIFT                          0
9950     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_VAL_UNUSED_0                           (0x3f<<2) // reserved
9951     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_LEFT_SEL_OVR_VAL_UNUSED_0_SHIFT                     2
9952 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_EN                                        0x000c78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9953     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_EN_F62                                (0x1<<0) // Override enable for afe_refclk_right_sel AFE ovr_signal.
9954     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_EN_F62_SHIFT                          0
9955     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
9956     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_EN_UNUSED_0_SHIFT                     1
9957 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_VAL                                       0x000c7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9958     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_VAL_F63                               (0x3<<0) // Override value for afe_refclk_right_sel AFE input.
9959     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_VAL_F63_SHIFT                         0
9960     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_VAL_UNUSED_0                          (0x3f<<2) // reserved
9961     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_REFCLK_RIGHT_SEL_OVR_VAL_UNUSED_0_SHIFT                    2
9962 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_EN                                              0x000c80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9963     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_EN_F64                                      (0x1<<0) // Override enable for afe_rxterm_val AFE ovr_signal.
9964     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_EN_F64_SHIFT                                0
9965     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
9966     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_EN_UNUSED_0_SHIFT                           1
9967 #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_VAL                                             0x000c84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9968     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_VAL_F65                                     (0x1f<<0) // Override value for afe_rxterm_val AFE input.
9969     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_VAL_F65_SHIFT                               0
9970     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_VAL_UNUSED_0                                (0x7<<5) // reserved
9971     #define PHY_NW_IP_REG_PHY0_OVR_CMU_LC_RXTERM_VAL_OVR_VAL_UNUSED_0_SHIFT                          5
9972 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_DOSC_OVR_EN                                              0x000e00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9973     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_DOSC_OVR_EN_F66                                      (0x1<<0) // Override enable for afe_cmpll2_dosc AFE ovr_signal.
9974     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_DOSC_OVR_EN_F66_SHIFT                                0
9975     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_DOSC_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
9976     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_DOSC_OVR_EN_UNUSED_0_SHIFT                           1
9977 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_DOSC_OVR_VAL                                             0x000e04UL //Access:RW   DataWidth:0x8   Override value for afe_cmpll2_dosc AFE input.  Chips: K2
9978 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_EN                                              0x000e08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9979     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_EN_F68                                      (0x1<<0) // Override enable for afe_cmpll2_ndiv AFE ovr_signal.
9980     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_EN_F68_SHIFT                                0
9981     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
9982     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_EN_UNUSED_0_SHIFT                           1
9983 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_VAL                                             0x000e0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9984     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_VAL_F69                                     (0x7f<<0) // Override value for afe_cmpll2_ndiv AFE input.
9985     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_VAL_F69_SHIFT                               0
9986     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_VAL_UNUSED_0                                (0x1<<7) // reserved
9987     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_NDIV_OVR_VAL_UNUSED_0_SHIFT                          7
9988 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_EN                                              0x000e10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9989     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_EN_F70                                      (0x1<<0) // Override enable for afe_cmpll2_psel AFE ovr_signal.
9990     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_EN_F70_SHIFT                                0
9991     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
9992     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_EN_UNUSED_0_SHIFT                           1
9993 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_VAL                                             0x000e14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9994     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_VAL_F71                                     (0x7<<0) // Override value for afe_cmpll2_psel AFE input.
9995     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_VAL_F71_SHIFT                               0
9996     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_VAL_UNUSED_0                                (0x1f<<3) // reserved
9997     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_PSEL_OVR_VAL_UNUSED_0_SHIFT                          3
9998 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_EN                                           0x000e18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
9999     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_EN_F72                                   (0x1<<0) // Override enable for afe_cmpll2_qsample AFE ovr_signal.
10000     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_EN_F72_SHIFT                             0
10001     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10002     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                        1
10003 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_VAL                                          0x000e1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10004     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_VAL_F73                                  (0x1<<0) // Override value for afe_cmpll2_qsample AFE input.
10005     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_VAL_F73_SHIFT                            0
10006     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_VAL_UNUSED_0                             (0x7f<<1) // reserved
10007     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                       1
10008 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_EN                                             0x000e20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10009     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_EN_F74                                     (0x1<<0) // Override enable for afe_cmpll2_vcofr AFE ovr_signal.
10010     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_EN_F74_SHIFT                               0
10011     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
10012     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_EN_UNUSED_0_SHIFT                          1
10013 #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_VAL                                            0x000e24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10014     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_VAL_F75                                    (0x7<<0) // Override value for afe_cmpll2_vcofr AFE input.
10015     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_VAL_F75_SHIFT                              0
10016     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_VAL_UNUSED_0                               (0x1f<<3) // reserved
10017     #define PHY_NW_IP_REG_PHY0_OVR_CMU_R_CMPLL2_VCOFR_OVR_VAL_UNUSED_0_SHIFT                         3
10018 #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_EN                                                0x001000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10019     #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_EN_F76                                        (0x1<<0) // Override enable for afe_calcomp_out AFE ovr_signal.
10020     #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_EN_F76_SHIFT                                  0
10021     #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
10022     #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_EN_UNUSED_0_SHIFT                             1
10023 #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_VAL                                               0x001004UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10024     #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_VAL_F77                                       (0x1<<0) // Override value for afe_calcomp_out AFE input.
10025     #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_VAL_F77_SHIFT                                 0
10026     #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_VAL_UNUSED_0                                  (0x7f<<1) // reserved
10027     #define PHY_NW_IP_REG_PHY0_OVR_LN0_CALCOMP_OUT_OVR_VAL_UNUSED_0_SHIFT                            1
10028 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_EN                                                 0x001008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10029     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_EN_F78                                         (0x1<<0) // Override enable for afe_rxcdr_dlpf AFE ovr_signal.
10030     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_EN_F78_SHIFT                                   0
10031     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
10032     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_EN_UNUSED_0_SHIFT                              1
10033 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_VAL_7_0                                            0x00100cUL //Access:RW   DataWidth:0x8   Override value for afe_rxcdr_dlpf AFE input.  Chips: K2
10034 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_VAL_8_8                                            0x001010UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10035     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_VAL_8_8_F80                                    (0x1<<0) // Override value for afe_rxcdr_dlpf AFE input.
10036     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_VAL_8_8_F80_SHIFT                              0
10037     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_VAL_8_8_UNUSED_0                               (0x7f<<1) // reserved
10038     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_DLPF_OVR_VAL_8_8_UNUSED_0_SHIFT                         1
10039 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_EN                                       0x001014UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10040     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_EN_F81                               (0x1<<0) // Override enable for afe_rxcdr_hscan_clki_lsb AFE ovr_signal.
10041     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_EN_F81_SHIFT                         0
10042     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10043     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_EN_UNUSED_0_SHIFT                    1
10044 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_VAL                                      0x001018UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10045     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_F82                              (0x3<<0) // Override value for afe_rxcdr_hscan_clki_lsb AFE input.
10046     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_F82_SHIFT                        0
10047     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_UNUSED_0                         (0x3f<<2) // reserved
10048     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_UNUSED_0_SHIFT                   2
10049 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_EN                                       0x00101cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10050     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_EN_F83                               (0x1<<0) // Override enable for afe_rxcdr_hscan_clki_msb AFE ovr_signal.
10051     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_EN_F83_SHIFT                         0
10052     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10053     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_EN_UNUSED_0_SHIFT                    1
10054 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_VAL                                      0x001020UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10055     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_F84                              (0x1f<<0) // Override value for afe_rxcdr_hscan_clki_msb AFE input.
10056     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_F84_SHIFT                        0
10057     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_UNUSED_0                         (0x7<<5) // reserved
10058     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_UNUSED_0_SHIFT                   5
10059 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_EN                                       0x001024UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10060     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_F85                               (0x1<<0) // Override enable for afe_rxcdr_hscan_clkq_lsb AFE ovr_signal.
10061     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_F85_SHIFT                         0
10062     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10063     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_UNUSED_0_SHIFT                    1
10064 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL                                      0x001028UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10065     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_F86                              (0x3<<0) // Override value for afe_rxcdr_hscan_clkq_lsb AFE input.
10066     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_F86_SHIFT                        0
10067     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_UNUSED_0                         (0x3f<<2) // reserved
10068     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_UNUSED_0_SHIFT                   2
10069 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_EN                                       0x00102cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10070     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_F87                               (0x1<<0) // Override enable for afe_rxcdr_hscan_clkq_msb AFE ovr_signal.
10071     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_F87_SHIFT                         0
10072     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10073     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_UNUSED_0_SHIFT                    1
10074 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL                                      0x001030UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10075     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_F88                              (0x1f<<0) // Override value for afe_rxcdr_hscan_clkq_msb AFE input.
10076     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_F88_SHIFT                        0
10077     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_UNUSED_0                         (0x7<<5) // reserved
10078     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_UNUSED_0_SHIFT                   5
10079 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN                                   0x001034UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10080     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_F89                           (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_lsb_fine AFE ovr_signal.
10081     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_F89_SHIFT                     0
10082     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_UNUSED_0                      (0x7f<<1) // reserved
10083     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_UNUSED_0_SHIFT                1
10084 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL                                  0x001038UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10085     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_F90                          (0x1<<0) // Override value for afe_rxcdr_hscan_eye_lsb_fine AFE input.
10086     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_F90_SHIFT                    0
10087     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_UNUSED_0                     (0x7f<<1) // reserved
10088     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_UNUSED_0_SHIFT               1
10089 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_EN                                        0x00103cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10090     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_EN_F91                                (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_lsb AFE ovr_signal.
10091     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_EN_F91_SHIFT                          0
10092     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
10093     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_EN_UNUSED_0_SHIFT                     1
10094 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_VAL                                       0x001040UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10095     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_VAL_F92                               (0xf<<0) // Override value for afe_rxcdr_hscan_eye_lsb AFE input.
10096     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_VAL_F92_SHIFT                         0
10097     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_VAL_UNUSED_0                          (0xf<<4) // reserved
10098     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_LSB_OVR_VAL_UNUSED_0_SHIFT                    4
10099 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_EN                                        0x001044UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10100     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_EN_F93                                (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_msb AFE ovr_signal.
10101     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_EN_F93_SHIFT                          0
10102     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
10103     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_EN_UNUSED_0_SHIFT                     1
10104 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_VAL                                       0x001048UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10105     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_VAL_F94                               (0x3<<0) // Override value for afe_rxcdr_hscan_eye_msb AFE input.
10106     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_VAL_F94_SHIFT                         0
10107     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_VAL_UNUSED_0                          (0x3f<<2) // reserved
10108     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_HSCAN_EYE_MSB_OVR_VAL_UNUSED_0_SHIFT                    2
10109 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_EN                                            0x00104cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10110     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_EN_F95                                    (0x1<<0) // Override enable for afe_rxcdr_vcocal_en AFE ovr_signal.
10111     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_EN_F95_SHIFT                              0
10112     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10113     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_EN_UNUSED_0_SHIFT                         1
10114 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_VAL                                           0x001050UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10115     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_VAL_F96                                   (0x1<<0) // Override value for afe_rxcdr_vcocal_en AFE input.
10116     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_VAL_F96_SHIFT                             0
10117     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10118     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_EN_OVR_VAL_UNUSED_0_SHIFT                        1
10119 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_EN                                            0x001054UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10120     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_EN_F97                                    (0x1<<0) // Override enable for afe_rxcdr_vcocal_go AFE ovr_signal.
10121     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_EN_F97_SHIFT                              0
10122     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10123     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_EN_UNUSED_0_SHIFT                         1
10124 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_VAL                                           0x001058UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10125     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_VAL_F98                                   (0x1<<0) // Override value for afe_rxcdr_vcocal_go AFE input.
10126     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_VAL_F98_SHIFT                             0
10127     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10128     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_GO_OVR_VAL_UNUSED_0_SHIFT                        1
10129 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_EN                                          0x00105cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10130     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_EN_F99                                  (0x1<<0) // Override enable for afe_rxcdr_vcocal_load AFE ovr_signal.
10131     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_EN_F99_SHIFT                            0
10132     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_EN_UNUSED_0                             (0x7f<<1) // reserved
10133     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_EN_UNUSED_0_SHIFT                       1
10134 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_VAL                                         0x001060UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10135     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_VAL_F100                                (0x1<<0) // Override value for afe_rxcdr_vcocal_load AFE input.
10136     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_VAL_F100_SHIFT                          0
10137     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_VAL_UNUSED_0                            (0x7f<<1) // reserved
10138     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_LOAD_OVR_VAL_UNUSED_0_SHIFT                      1
10139 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_EN                                            0x001064UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10140     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_EN_F101                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_up AFE ovr_signal.
10141     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_EN_F101_SHIFT                             0
10142     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10143     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_EN_UNUSED_0_SHIFT                         1
10144 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_VAL                                           0x001068UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10145     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_VAL_F102                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_up AFE input.
10146     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_VAL_F102_SHIFT                            0
10147     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10148     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOCAL_UP_OVR_VAL_UNUSED_0_SHIFT                        1
10149 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_EN                                                0x00106cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10150     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_EN_F103                                       (0x1<<0) // Override enable for afe_rxcdr_vcofr AFE ovr_signal.
10151     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_EN_F103_SHIFT                                 0
10152     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
10153     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_EN_UNUSED_0_SHIFT                             1
10154 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_VAL                                               0x001070UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10155     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_VAL_F104                                      (0x1f<<0) // Override value for afe_rxcdr_vcofr AFE input.
10156     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_VAL_F104_SHIFT                                0
10157     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_VAL_UNUSED_0                                  (0x7<<5) // reserved
10158     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXCDR_VCOFR_OVR_VAL_UNUSED_0_SHIFT                            5
10159 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_EN                                       0x001074UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10160     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_EN_F105                              (0x1<<0) // Override enable for afe_rxdfe_clkdiv_qsample AFE ovr_signal.
10161     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_EN_F105_SHIFT                        0
10162     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10163     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                    1
10164 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_VAL                                      0x001078UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10165     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_F106                             (0x1<<0) // Override value for afe_rxdfe_clkdiv_qsample AFE input.
10166     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_F106_SHIFT                       0
10167     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0                         (0x7f<<1) // reserved
10168     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                   1
10169 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN                                    0x00107cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10170     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_F107                           (0x1<<0) // Override enable for afe_rxdfe_clkdiveye_qsample AFE ovr_signal.
10171     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_F107_SHIFT                     0
10172     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_UNUSED_0                       (0x7f<<1) // reserved
10173     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                 1
10174 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL                                   0x001080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10175     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_F108                          (0xf<<0) // Override value for afe_rxdfe_clkdiveye_qsample AFE input.
10176     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_F108_SHIFT                    0
10177     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_UNUSED_0                      (0xf<<4) // reserved
10178     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                4
10179 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN                               0x001084UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10180     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_F109                      (0x1<<0) // Override enable for afe_rxdfe_dataslicereven0_offset AFE ovr_signal.
10181     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_F109_SHIFT                0
10182     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_UNUSED_0                  (0x7f<<1) // reserved
10183     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_UNUSED_0_SHIFT            1
10184 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL                              0x001088UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10185     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_F110                     (0x3f<<0) // Override value for afe_rxdfe_dataslicereven0_offset AFE input.
10186     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_F110_SHIFT               0
10187     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_UNUSED_0                 (0x3<<6) // reserved
10188     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_UNUSED_0_SHIFT           6
10189 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN                               0x00108cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10190     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_F111                      (0x1<<0) // Override enable for afe_rxdfe_dataslicereven1_offset AFE ovr_signal.
10191     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_F111_SHIFT                0
10192     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_UNUSED_0                  (0x7f<<1) // reserved
10193     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_UNUSED_0_SHIFT            1
10194 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL                              0x001090UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10195     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_F112                     (0x3f<<0) // Override value for afe_rxdfe_dataslicereven1_offset AFE input.
10196     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_F112_SHIFT               0
10197     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_UNUSED_0                 (0x3<<6) // reserved
10198     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_UNUSED_0_SHIFT           6
10199 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_EN                                0x001094UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10200     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_F113                       (0x1<<0) // Override enable for afe_rxdfe_dataslicerodd0_offset AFE ovr_signal.
10201     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_F113_SHIFT                 0
10202     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
10203     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
10204 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL                               0x001098UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10205     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_F114                      (0x3f<<0) // Override value for afe_rxdfe_dataslicerodd0_offset AFE input.
10206     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_F114_SHIFT                0
10207     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
10208     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
10209 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_EN                                0x00109cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10210     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_F115                       (0x1<<0) // Override enable for afe_rxdfe_dataslicerodd1_offset AFE ovr_signal.
10211     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_F115_SHIFT                 0
10212     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
10213     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
10214 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL                               0x0010a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10215     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_F116                      (0x3f<<0) // Override value for afe_rxdfe_dataslicerodd1_offset AFE input.
10216     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_F116_SHIFT                0
10217     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
10218     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
10219 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN                                0x0010a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10220     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_F117                       (0x1<<0) // Override enable for afe_rxdfe_edgeslicereven_offset AFE ovr_signal.
10221     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_F117_SHIFT                 0
10222     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
10223     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
10224 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL                               0x0010a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10225     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_F118                      (0x3f<<0) // Override value for afe_rxdfe_edgeslicereven_offset AFE input.
10226     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_F118_SHIFT                0
10227     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
10228     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
10229 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_EN                                 0x0010acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10230     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_F119                        (0x1<<0) // Override enable for afe_rxdfe_edgeslicerodd_offset AFE ovr_signal.
10231     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_F119_SHIFT                  0
10232     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_UNUSED_0                    (0x7f<<1) // reserved
10233     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_UNUSED_0_SHIFT              1
10234 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL                                0x0010b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10235     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_F120                       (0x3f<<0) // Override value for afe_rxdfe_edgeslicerodd_offset AFE input.
10236     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_F120_SHIFT                 0
10237     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_UNUSED_0                   (0x3<<6) // reserved
10238     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT             6
10239 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_EN                                           0x0010b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10240     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_EN_F121                                  (0x1<<0) // Override enable for afe_rxdfe_even0_tap1 AFE ovr_signal.
10241     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_EN_F121_SHIFT                            0
10242     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10243     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_EN_UNUSED_0_SHIFT                        1
10244 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_VAL                                          0x0010b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10245     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_VAL_F122                                 (0x1f<<0) // Override value for afe_rxdfe_even0_tap1 AFE input.
10246     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_VAL_F122_SHIFT                           0
10247     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_VAL_UNUSED_0                             (0x7<<5) // reserved
10248     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN0_TAP1_OVR_VAL_UNUSED_0_SHIFT                       5
10249 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_EN                                           0x0010bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10250     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_EN_F123                                  (0x1<<0) // Override enable for afe_rxdfe_even1_tap1 AFE ovr_signal.
10251     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_EN_F123_SHIFT                            0
10252     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10253     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_EN_UNUSED_0_SHIFT                        1
10254 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_VAL                                          0x0010c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10255     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_VAL_F124                                 (0x1f<<0) // Override value for afe_rxdfe_even1_tap1 AFE input.
10256     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_VAL_F124_SHIFT                           0
10257     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_VAL_UNUSED_0                             (0x7<<5) // reserved
10258     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EVEN1_TAP1_OVR_VAL_UNUSED_0_SHIFT                       5
10259 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_EN                                             0x0010c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10260     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_EN_F125                                    (0x1<<0) // Override enable for afe_rxdfe_eye_tap1 AFE ovr_signal.
10261     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_EN_F125_SHIFT                              0
10262     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
10263     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_EN_UNUSED_0_SHIFT                          1
10264 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_VAL                                            0x0010c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10265     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_VAL_F126                                   (0x1f<<0) // Override value for afe_rxdfe_eye_tap1 AFE input.
10266     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_VAL_F126_SHIFT                             0
10267     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_VAL_UNUSED_0                               (0x7<<5) // reserved
10268     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_TAP1_OVR_VAL_UNUSED_0_SHIFT                         5
10269 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_EN                                        0x0010ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10270     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_EN_F127                               (0x1<<0) // Override enable for afe_rxdfe_eye_vscan_lsb AFE ovr_signal.
10271     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_EN_F127_SHIFT                         0
10272     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
10273     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_EN_UNUSED_0_SHIFT                     1
10274 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_VAL                                       0x0010d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10275     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_VAL_F128                              (0x1f<<0) // Override value for afe_rxdfe_eye_vscan_lsb AFE input.
10276     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_VAL_F128_SHIFT                        0
10277     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_VAL_UNUSED_0                          (0x7<<5) // reserved
10278     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_LSB_OVR_VAL_UNUSED_0_SHIFT                    5
10279 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_EN                                        0x0010d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10280     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_EN_F129                               (0x1<<0) // Override enable for afe_rxdfe_eye_vscan_msb AFE ovr_signal.
10281     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_EN_F129_SHIFT                         0
10282     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
10283     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_EN_UNUSED_0_SHIFT                     1
10284 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_VAL                                       0x0010d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10285     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_VAL_F130                              (0x7<<0) // Override value for afe_rxdfe_eye_vscan_msb AFE input.
10286     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_VAL_F130_SHIFT                        0
10287     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_VAL_UNUSED_0                          (0x1f<<3) // reserved
10288     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYE_VSCAN_MSB_OVR_VAL_UNUSED_0_SHIFT                    3
10289 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN                                 0x0010dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10290     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_F131                        (0x1<<0) // Override enable for afe_rxdfe_eyeslicereven_offset AFE ovr_signal.
10291     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_F131_SHIFT                  0
10292     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_UNUSED_0                    (0x7f<<1) // reserved
10293     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT              1
10294 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL                                0x0010e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10295     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_F132                       (0x3f<<0) // Override value for afe_rxdfe_eyeslicereven_offset AFE input.
10296     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_F132_SHIFT                 0
10297     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0                   (0x3<<6) // reserved
10298     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT             6
10299 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_EN                                  0x0010e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10300     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_EN_F133                         (0x1<<0) // Override enable for afe_rxdfe_eyeslicerodd_offset AFE ovr_signal.
10301     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_EN_F133_SHIFT                   0
10302     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_EN_UNUSED_0                     (0x7f<<1) // reserved
10303     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_EN_UNUSED_0_SHIFT               1
10304 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_VAL                                 0x0010e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10305     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_F134                        (0x3f<<0) // Override value for afe_rxdfe_eyeslicerodd_offset AFE input.
10306     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_F134_SHIFT                  0
10307     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_UNUSED_0                    (0x3<<6) // reserved
10308     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT              6
10309 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_EN                                            0x0010ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10310     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_EN_F135                                   (0x1<<0) // Override enable for afe_rxdfe_odd0_tap1 AFE ovr_signal.
10311     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_EN_F135_SHIFT                             0
10312     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10313     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_EN_UNUSED_0_SHIFT                         1
10314 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_VAL                                           0x0010f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10315     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_VAL_F136                                  (0x1f<<0) // Override value for afe_rxdfe_odd0_tap1 AFE input.
10316     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_VAL_F136_SHIFT                            0
10317     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
10318     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD0_TAP1_OVR_VAL_UNUSED_0_SHIFT                        5
10319 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_EN                                            0x0010f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10320     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_EN_F137                                   (0x1<<0) // Override enable for afe_rxdfe_odd1_tap1 AFE ovr_signal.
10321     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_EN_F137_SHIFT                             0
10322     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10323     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_EN_UNUSED_0_SHIFT                         1
10324 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_VAL                                           0x0010f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10325     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_VAL_F138                                  (0x1f<<0) // Override value for afe_rxdfe_odd1_tap1 AFE input.
10326     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_VAL_F138_SHIFT                            0
10327     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
10328     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_ODD1_TAP1_OVR_VAL_UNUSED_0_SHIFT                        5
10329 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_EN                                       0x0010fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10330     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_EN_F139                              (0x1<<0) // Override enable for afe_rxdfe_sumeven_offset AFE ovr_signal.
10331     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_EN_F139_SHIFT                        0
10332     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10333     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT                    1
10334 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_VAL                                      0x001100UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10335     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_VAL_F140                             (0x3f<<0) // Override value for afe_rxdfe_sumeven_offset AFE input.
10336     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_VAL_F140_SHIFT                       0
10337     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_VAL_UNUSED_0                         (0x3<<6) // reserved
10338     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMEVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT                   6
10339 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_EN                                        0x001104UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10340     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_EN_F141                               (0x1<<0) // Override enable for afe_rxdfe_sumodd_offset AFE ovr_signal.
10341     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_EN_F141_SHIFT                         0
10342     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
10343     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_EN_UNUSED_0_SHIFT                     1
10344 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_VAL                                       0x001108UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10345     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_VAL_F142                              (0x3f<<0) // Override value for afe_rxdfe_sumodd_offset AFE input.
10346     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_VAL_F142_SHIFT                        0
10347     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_VAL_UNUSED_0                          (0x3<<6) // reserved
10348     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_SUMODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT                    6
10349 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_EN                                                 0x00110cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10350     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_EN_F143                                        (0x1<<0) // Override enable for afe_rxdfe_tap2 AFE ovr_signal.
10351     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_EN_F143_SHIFT                                  0
10352     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
10353     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_EN_UNUSED_0_SHIFT                              1
10354 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_VAL                                                0x001110UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10355     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_VAL_F144                                       (0xf<<0) // Override value for afe_rxdfe_tap2 AFE input.
10356     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_VAL_F144_SHIFT                                 0
10357     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_VAL_UNUSED_0                                   (0xf<<4) // reserved
10358     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP2_OVR_VAL_UNUSED_0_SHIFT                             4
10359 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_EN                                                 0x001114UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10360     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_EN_F145                                        (0x1<<0) // Override enable for afe_rxdfe_tap3 AFE ovr_signal.
10361     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_EN_F145_SHIFT                                  0
10362     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
10363     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_EN_UNUSED_0_SHIFT                              1
10364 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_VAL                                                0x001118UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10365     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_VAL_F146                                       (0x7<<0) // Override value for afe_rxdfe_tap3 AFE input.
10366     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_VAL_F146_SHIFT                                 0
10367     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
10368     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP3_OVR_VAL_UNUSED_0_SHIFT                             3
10369 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_EN                                                 0x00111cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10370     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_EN_F147                                        (0x1<<0) // Override enable for afe_rxdfe_tap4 AFE ovr_signal.
10371     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_EN_F147_SHIFT                                  0
10372     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
10373     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_EN_UNUSED_0_SHIFT                              1
10374 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_VAL                                                0x001120UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10375     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_VAL_F148                                       (0x7<<0) // Override value for afe_rxdfe_tap4 AFE input.
10376     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_VAL_F148_SHIFT                                 0
10377     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
10378     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP4_OVR_VAL_UNUSED_0_SHIFT                             3
10379 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_EN                                                 0x001124UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10380     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_EN_F149                                        (0x1<<0) // Override enable for afe_rxdfe_tap5 AFE ovr_signal.
10381     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_EN_F149_SHIFT                                  0
10382     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
10383     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_EN_UNUSED_0_SHIFT                              1
10384 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_VAL                                                0x001128UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10385     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_VAL_F150                                       (0x7<<0) // Override value for afe_rxdfe_tap5 AFE input.
10386     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_VAL_F150_SHIFT                                 0
10387     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
10388     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_TAP5_OVR_VAL_UNUSED_0_SHIFT                             3
10389 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_EN                                     0x00112cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10390     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_EN_F151                            (0x1<<0) // Override enable for afe_rxdfe_vscaneven_offset AFE ovr_signal.
10391     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_EN_F151_SHIFT                      0
10392     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_EN_UNUSED_0                        (0x7f<<1) // reserved
10393     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT                  1
10394 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_VAL                                    0x001130UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10395     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_F152                           (0x3f<<0) // Override value for afe_rxdfe_vscaneven_offset AFE input.
10396     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_F152_SHIFT                     0
10397     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_UNUSED_0                       (0x3<<6) // reserved
10398     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT                 6
10399 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_EN                                      0x001134UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10400     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_EN_F153                             (0x1<<0) // Override enable for afe_rxdfe_vscanodd_offset AFE ovr_signal.
10401     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_EN_F153_SHIFT                       0
10402     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_EN_UNUSED_0                         (0x7f<<1) // reserved
10403     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_EN_UNUSED_0_SHIFT                   1
10404 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_VAL                                     0x001138UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10405     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_VAL_F154                            (0x3f<<0) // Override value for afe_rxdfe_vscanodd_offset AFE input.
10406     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_VAL_F154_SHIFT                      0
10407     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_VAL_UNUSED_0                        (0x3<<6) // reserved
10408     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDFE_VSCANODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT                  6
10409 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_EN                                            0x00113cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10410     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_EN_F155                                   (0x1<<0) // Override enable for afe_rxdp_data_width AFE ovr_signal.
10411     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_EN_F155_SHIFT                             0
10412     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10413     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_EN_UNUSED_0_SHIFT                         1
10414 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_VAL                                           0x001140UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10415     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_VAL_F156                                  (0x1<<0) // Override value for afe_rxdp_data_width AFE input.
10416     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_VAL_F156_SHIFT                            0
10417     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10418     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXDP_DATA_WIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
10419 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_EN                                           0x001144UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10420     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_EN_F157                                  (0x1<<0) // Override enable for afe_rxleq_eq_biasres AFE ovr_signal.
10421     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_EN_F157_SHIFT                            0
10422     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10423     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_EN_UNUSED_0_SHIFT                        1
10424 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_VAL                                          0x001148UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10425     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_VAL_F158                                 (0x7<<0) // Override value for afe_rxleq_eq_biasres AFE input.
10426     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_VAL_F158_SHIFT                           0
10427     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
10428     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_BIASRES_OVR_VAL_UNUSED_0_SHIFT                       3
10429 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_EN                                               0x00114cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10430     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_EN_F159                                      (0x1<<0) // Override enable for afe_rxleq_eq_hfg AFE ovr_signal.
10431     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_EN_F159_SHIFT                                0
10432     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
10433     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_EN_UNUSED_0_SHIFT                            1
10434 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_VAL                                              0x001150UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10435     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_VAL_F160                                     (0x1f<<0) // Override value for afe_rxleq_eq_hfg AFE input.
10436     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_VAL_F160_SHIFT                               0
10437     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_VAL_UNUSED_0                                 (0x7<<5) // reserved
10438     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_HFG_OVR_VAL_UNUSED_0_SHIFT                           5
10439 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_EN                                               0x001154UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10440     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_EN_F161                                      (0x1<<0) // Override enable for afe_rxleq_eq_lfg AFE ovr_signal.
10441     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_EN_F161_SHIFT                                0
10442     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
10443     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_EN_UNUSED_0_SHIFT                            1
10444 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_VAL                                              0x001158UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10445     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_VAL_F162                                     (0x1f<<0) // Override value for afe_rxleq_eq_lfg AFE input.
10446     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_VAL_F162_SHIFT                               0
10447     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_VAL_UNUSED_0                                 (0x7<<5) // reserved
10448     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LFG_OVR_VAL_UNUSED_0_SHIFT                           5
10449 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_EN                                           0x00115cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10450     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_EN_F163                                  (0x1<<0) // Override enable for afe_rxleq_eq_loadres AFE ovr_signal.
10451     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_EN_F163_SHIFT                            0
10452     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10453     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_EN_UNUSED_0_SHIFT                        1
10454 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_VAL                                          0x001160UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10455     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_VAL_F164                                 (0x7<<0) // Override value for afe_rxleq_eq_loadres AFE input.
10456     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_VAL_F164_SHIFT                           0
10457     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
10458     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_LOADRES_OVR_VAL_UNUSED_0_SHIFT                       3
10459 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_EN                                               0x001164UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10460     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_EN_F165                                      (0x1<<0) // Override enable for afe_rxleq_eq_mbf AFE ovr_signal.
10461     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_EN_F165_SHIFT                                0
10462     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
10463     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_EN_UNUSED_0_SHIFT                            1
10464 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_VAL                                              0x001168UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10465     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_VAL_F166                                     (0xf<<0) // Override value for afe_rxleq_eq_mbf AFE input.
10466     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_VAL_F166_SHIFT                               0
10467     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_VAL_UNUSED_0                                 (0xf<<4) // reserved
10468     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBF_OVR_VAL_UNUSED_0_SHIFT                           4
10469 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_EN                                               0x00116cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10470     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_EN_F167                                      (0x1<<0) // Override enable for afe_rxleq_eq_mbg AFE ovr_signal.
10471     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_EN_F167_SHIFT                                0
10472     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
10473     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_EN_UNUSED_0_SHIFT                            1
10474 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_VAL                                              0x001170UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10475     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_VAL_F168                                     (0xf<<0) // Override value for afe_rxleq_eq_mbg AFE input.
10476     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_VAL_F168_SHIFT                               0
10477     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_VAL_UNUSED_0                                 (0xf<<4) // reserved
10478     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_MBG_OVR_VAL_UNUSED_0_SHIFT                           4
10479 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_EN                                               0x001174UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10480     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_EN_F169                                      (0x1<<0) // Override enable for afe_rxleq_eq_sql AFE ovr_signal.
10481     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_EN_F169_SHIFT                                0
10482     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
10483     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_EN_UNUSED_0_SHIFT                            1
10484 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_VAL                                              0x001178UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10485     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_VAL_F170                                     (0x7<<0) // Override value for afe_rxleq_eq_sql AFE input.
10486     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_VAL_F170_SHIFT                               0
10487     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_VAL_UNUSED_0                                 (0x1f<<3) // reserved
10488     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_EQ_SQL_OVR_VAL_UNUSED_0_SHIFT                           3
10489 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_EN                                               0x00117cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10490     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_EN_F171                                      (0x1<<0) // Override enable for afe_rxleq_gn_apg AFE ovr_signal.
10491     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_EN_F171_SHIFT                                0
10492     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
10493     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_EN_UNUSED_0_SHIFT                            1
10494 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_VAL                                              0x001180UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10495     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_VAL_F172                                     (0x3<<0) // Override value for afe_rxleq_gn_apg AFE input.
10496     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_VAL_F172_SHIFT                               0
10497     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_VAL_UNUSED_0                                 (0x3f<<2) // reserved
10498     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_APG_OVR_VAL_UNUSED_0_SHIFT                           2
10499 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_EN                                             0x001184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10500     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_EN_F173                                    (0x1<<0) // Override enable for afe_rxleq_gn_biasi AFE ovr_signal.
10501     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_EN_F173_SHIFT                              0
10502     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
10503     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_EN_UNUSED_0_SHIFT                          1
10504 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_VAL                                            0x001188UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10505     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_VAL_F174                                   (0x3<<0) // Override value for afe_rxleq_gn_biasi AFE input.
10506     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_VAL_F174_SHIFT                             0
10507     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_VAL_UNUSED_0                               (0x3f<<2) // reserved
10508     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_BIASI_OVR_VAL_UNUSED_0_SHIFT                         2
10509 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_EN                                           0x00118cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10510     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_EN_F175                                  (0x1<<0) // Override enable for afe_rxleq_gn_loadres AFE ovr_signal.
10511     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_EN_F175_SHIFT                            0
10512     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10513     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_EN_UNUSED_0_SHIFT                        1
10514 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_VAL                                          0x001190UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10515     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_VAL_F176                                 (0x7<<0) // Override value for afe_rxleq_gn_loadres AFE input.
10516     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_VAL_F176_SHIFT                           0
10517     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
10518     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_GN_LOADRES_OVR_VAL_UNUSED_0_SHIFT                       3
10519 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_EN                                            0x001194UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10520     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_EN_F177                                   (0x1<<0) // Override enable for afe_rxleq_offset_e1 AFE ovr_signal.
10521     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_EN_F177_SHIFT                             0
10522     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10523     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_EN_UNUSED_0_SHIFT                         1
10524 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_VAL                                           0x001198UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10525     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_VAL_F178                                  (0x3f<<0) // Override value for afe_rxleq_offset_e1 AFE input.
10526     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_VAL_F178_SHIFT                            0
10527     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
10528     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E1_OVR_VAL_UNUSED_0_SHIFT                        6
10529 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_EN                                            0x00119cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10530     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_EN_F179                                   (0x1<<0) // Override enable for afe_rxleq_offset_e2 AFE ovr_signal.
10531     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_EN_F179_SHIFT                             0
10532     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10533     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_EN_UNUSED_0_SHIFT                         1
10534 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_VAL                                           0x0011a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10535     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_VAL_F180                                  (0x3f<<0) // Override value for afe_rxleq_offset_e2 AFE input.
10536     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_VAL_F180_SHIFT                            0
10537     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
10538     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E2_OVR_VAL_UNUSED_0_SHIFT                        6
10539 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_EN                                            0x0011a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10540     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_EN_F181                                   (0x1<<0) // Override enable for afe_rxleq_offset_e3 AFE ovr_signal.
10541     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_EN_F181_SHIFT                             0
10542     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10543     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_EN_UNUSED_0_SHIFT                         1
10544 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_VAL                                           0x0011a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10545     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_VAL_F182                                  (0x3f<<0) // Override value for afe_rxleq_offset_e3 AFE input.
10546     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_VAL_F182_SHIFT                            0
10547     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
10548     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E3_OVR_VAL_UNUSED_0_SHIFT                        6
10549 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_EN                                            0x0011acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10550     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_EN_F183                                   (0x1<<0) // Override enable for afe_rxleq_offset_e4 AFE ovr_signal.
10551     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_EN_F183_SHIFT                             0
10552     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10553     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_EN_UNUSED_0_SHIFT                         1
10554 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_VAL                                           0x0011b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10555     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_VAL_F184                                  (0x3f<<0) // Override value for afe_rxleq_offset_e4 AFE input.
10556     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_VAL_F184_SHIFT                            0
10557     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
10558     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E4_OVR_VAL_UNUSED_0_SHIFT                        6
10559 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_EN                                            0x0011b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10560     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_EN_F185                                   (0x1<<0) // Override enable for afe_rxleq_offset_e5 AFE ovr_signal.
10561     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_EN_F185_SHIFT                             0
10562     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10563     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_EN_UNUSED_0_SHIFT                         1
10564 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_VAL                                           0x0011b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10565     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_VAL_F186                                  (0x3f<<0) // Override value for afe_rxleq_offset_e5 AFE input.
10566     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_VAL_F186_SHIFT                            0
10567     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
10568     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E5_OVR_VAL_UNUSED_0_SHIFT                        6
10569 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_EN                                            0x0011bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10570     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_EN_F187                                   (0x1<<0) // Override enable for afe_rxleq_offset_e6 AFE ovr_signal.
10571     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_EN_F187_SHIFT                             0
10572     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10573     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_EN_UNUSED_0_SHIFT                         1
10574 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_VAL                                           0x0011c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10575     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_VAL_F188                                  (0x3f<<0) // Override value for afe_rxleq_offset_e6 AFE input.
10576     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_VAL_F188_SHIFT                            0
10577     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
10578     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_E6_OVR_VAL_UNUSED_0_SHIFT                        6
10579 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_EN                                            0x0011c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10580     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_EN_F189                                   (0x1<<0) // Override enable for afe_rxleq_offset_g1 AFE ovr_signal.
10581     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_EN_F189_SHIFT                             0
10582     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10583     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_EN_UNUSED_0_SHIFT                         1
10584 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_VAL                                           0x0011c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10585     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_VAL_F190                                  (0x3f<<0) // Override value for afe_rxleq_offset_g1 AFE input.
10586     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_VAL_F190_SHIFT                            0
10587     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
10588     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_OFFSET_G1_OVR_VAL_UNUSED_0_SHIFT                        6
10589 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_EN                                              0x0011ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10590     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_EN_F191                                     (0x1<<0) // Override enable for afe_rxleq_ple_att AFE ovr_signal.
10591     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_EN_F191_SHIFT                               0
10592     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
10593     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_EN_UNUSED_0_SHIFT                           1
10594 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_VAL                                             0x0011d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10595     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_VAL_F192                                    (0x7<<0) // Override value for afe_rxleq_ple_att AFE input.
10596     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_VAL_F192_SHIFT                              0
10597     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_VAL_UNUSED_0                                (0x1f<<3) // reserved
10598     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLEQ_PLE_ATT_OVR_VAL_UNUSED_0_SHIFT                          3
10599 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_EN                                                  0x0011d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10600     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_EN_F193                                         (0x1<<0) // Override enable for afe_rxlos_agc AFE ovr_signal.
10601     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_EN_F193_SHIFT                                   0
10602     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_EN_UNUSED_0                                     (0x7f<<1) // reserved
10603     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_EN_UNUSED_0_SHIFT                               1
10604 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_VAL                                                 0x0011d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10605     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_VAL_F194                                        (0x1<<0) // Override value for afe_rxlos_agc AFE input.
10606     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_VAL_F194_SHIFT                                  0
10607     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_VAL_UNUSED_0                                    (0x7f<<1) // reserved
10608     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_OVR_VAL_UNUSED_0_SHIFT                              1
10609 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_EN                                              0x0011dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10610     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_EN_F195                                     (0x1<<0) // Override enable for afe_rxlos_agc_set AFE ovr_signal.
10611     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_EN_F195_SHIFT                               0
10612     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
10613     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_EN_UNUSED_0_SHIFT                           1
10614 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_VAL                                             0x0011e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10615     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_VAL_F196                                    (0x1<<0) // Override value for afe_rxlos_agc_set AFE input.
10616     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_VAL_F196_SHIFT                              0
10617     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_VAL_UNUSED_0                                (0x7f<<1) // reserved
10618     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_AGC_SET_OVR_VAL_UNUSED_0_SHIFT                          1
10619 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_EN                                            0x0011e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10620     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_EN_F197                                   (0x1<<0) // Override enable for afe_rxlos_bandwidth AFE ovr_signal.
10621     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_EN_F197_SHIFT                             0
10622     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10623     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_EN_UNUSED_0_SHIFT                         1
10624 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_VAL                                           0x0011e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10625     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_VAL_F198                                  (0x1<<0) // Override value for afe_rxlos_bandwidth AFE input.
10626     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_VAL_F198_SHIFT                            0
10627     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10628     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_BANDWIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
10629 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_EN                                             0x0011ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10630     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_EN_F199                                    (0x1<<0) // Override enable for afe_rxlos_comp_sel AFE ovr_signal.
10631     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_EN_F199_SHIFT                              0
10632     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
10633     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_EN_UNUSED_0_SHIFT                          1
10634 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_VAL                                            0x0011f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10635     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_VAL_F200                                   (0x1<<0) // Override value for afe_rxlos_comp_sel AFE input.
10636     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_VAL_F200_SHIFT                             0
10637     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_VAL_UNUSED_0                               (0x7f<<1) // reserved
10638     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_COMP_SEL_OVR_VAL_UNUSED_0_SHIFT                         1
10639 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_EN                                           0x0011f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10640     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_EN_F201                                  (0x1<<0) // Override enable for afe_rxlos_envdet_byp AFE ovr_signal.
10641     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_EN_F201_SHIFT                            0
10642     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10643     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_EN_UNUSED_0_SHIFT                        1
10644 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_VAL                                          0x0011f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10645     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_VAL_F202                                 (0x1<<0) // Override value for afe_rxlos_envdet_byp AFE input.
10646     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_VAL_F202_SHIFT                           0
10647     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_VAL_UNUSED_0                             (0x7f<<1) // reserved
10648     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_ENVDET_BYP_OVR_VAL_UNUSED_0_SHIFT                       1
10649 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_EN                                                 0x0011fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10650     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_EN_F203                                        (0x1<<0) // Override enable for afe_rxlos_gain AFE ovr_signal.
10651     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_EN_F203_SHIFT                                  0
10652     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
10653     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_EN_UNUSED_0_SHIFT                              1
10654 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_VAL                                                0x001200UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10655     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_VAL_F204                                       (0x1<<0) // Override value for afe_rxlos_gain AFE input.
10656     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_VAL_F204_SHIFT                                 0
10657     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_VAL_UNUSED_0                                   (0x7f<<1) // reserved
10658     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_GAIN_OVR_VAL_UNUSED_0_SHIFT                             1
10659 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_EN                                           0x001204UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10660     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_EN_F205                                  (0x1<<0) // Override enable for afe_rxlos_hysteresis AFE ovr_signal.
10661     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_EN_F205_SHIFT                            0
10662     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10663     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_EN_UNUSED_0_SHIFT                        1
10664 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_VAL                                          0x001208UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10665     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_VAL_F206                                 (0x7<<0) // Override value for afe_rxlos_hysteresis AFE input.
10666     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_VAL_F206_SHIFT                           0
10667     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
10668     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_HYSTERESIS_OVR_VAL_UNUSED_0_SHIFT                       3
10669 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_EN                                               0x00120cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10670     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_EN_F207                                      (0x1<<0) // Override enable for afe_rxlos_offset AFE ovr_signal.
10671     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_EN_F207_SHIFT                                0
10672     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
10673     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_EN_UNUSED_0_SHIFT                            1
10674 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_VAL                                              0x001210UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10675     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_VAL_F208                                     (0x3f<<0) // Override value for afe_rxlos_offset AFE input.
10676     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_VAL_F208_SHIFT                               0
10677     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_VAL_UNUSED_0                                 (0x3<<6) // reserved
10678     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_OFFSET_OVR_VAL_UNUSED_0_SHIFT                           6
10679 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_EN                                                  0x001214UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10680     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_EN_F209                                         (0x1<<0) // Override enable for afe_rxlos_raw AFE ovr_signal.
10681     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_EN_F209_SHIFT                                   0
10682     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_EN_UNUSED_0                                     (0x7f<<1) // reserved
10683     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_EN_UNUSED_0_SHIFT                               1
10684 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_VAL                                                 0x001218UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10685     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_VAL_F210                                        (0x1<<0) // Override value for afe_rxlos_raw AFE input.
10686     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_VAL_F210_SHIFT                                  0
10687     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_VAL_UNUSED_0                                    (0x7f<<1) // reserved
10688     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_RAW_OVR_VAL_UNUSED_0_SHIFT                              1
10689 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_EN                                                0x00121cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10690     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_EN_F211                                       (0x1<<0) // Override enable for afe_rxlos_spare AFE ovr_signal.
10691     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_EN_F211_SHIFT                                 0
10692     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
10693     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_EN_UNUSED_0_SHIFT                             1
10694 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_VAL                                               0x001220UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10695     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_VAL_F212                                      (0xf<<0) // Override value for afe_rxlos_spare AFE input.
10696     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_VAL_F212_SHIFT                                0
10697     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_VAL_UNUSED_0                                  (0xf<<4) // reserved
10698     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_SPARE_OVR_VAL_UNUSED_0_SHIFT                            4
10699 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_EN                                            0x001224UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10700     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_EN_F213                                   (0x1<<0) // Override enable for afe_rxlos_threshold AFE ovr_signal.
10701     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_EN_F213_SHIFT                             0
10702     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10703     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_EN_UNUSED_0_SHIFT                         1
10704 #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_VAL                                           0x001228UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10705     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_VAL_F214                                  (0xf<<0) // Override value for afe_rxlos_threshold AFE input.
10706     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_VAL_F214_SHIFT                            0
10707     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_VAL_UNUSED_0                              (0xf<<4) // reserved
10708     #define PHY_NW_IP_REG_PHY0_OVR_LN0_RXLOS_THRESHOLD_OVR_VAL_UNUSED_0_SHIFT                        4
10709 #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_EN                                              0x00122cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10710     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_EN_F215                                     (0x1<<0) // Override enable for afe_txcp_dcd_trim AFE ovr_signal.
10711     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_EN_F215_SHIFT                               0
10712     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
10713     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_EN_UNUSED_0_SHIFT                           1
10714 #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_VAL                                             0x001230UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10715     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_VAL_F216                                    (0x3f<<0) // Override value for afe_txcp_dcd_trim AFE input.
10716     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_VAL_F216_SHIFT                              0
10717     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_VAL_UNUSED_0                                (0x3<<6) // reserved
10718     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXCP_DCD_TRIM_OVR_VAL_UNUSED_0_SHIFT                          6
10719 #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_EN                                               0x001234UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10720     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_EN_F217                                      (0x1<<0) // Override enable for afe_txdp_cal_out AFE ovr_signal.
10721     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_EN_F217_SHIFT                                0
10722     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
10723     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_EN_UNUSED_0_SHIFT                            1
10724 #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_VAL                                              0x001238UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10725     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_VAL_F218                                     (0x1<<0) // Override value for afe_txdp_cal_out AFE input.
10726     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_VAL_F218_SHIFT                               0
10727     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_VAL_UNUSED_0                                 (0x7f<<1) // reserved
10728     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CAL_OUT_OVR_VAL_UNUSED_0_SHIFT                           1
10729 #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_EN                                                0x00123cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10730     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_EN_F219                                       (0x1<<0) // Override enable for afe_txdp_clkdly AFE ovr_signal.
10731     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_EN_F219_SHIFT                                 0
10732     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
10733     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_EN_UNUSED_0_SHIFT                             1
10734 #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_VAL                                               0x001240UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10735     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_VAL_F220                                      (0xf<<0) // Override value for afe_txdp_clkdly AFE input.
10736     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_VAL_F220_SHIFT                                0
10737     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_VAL_UNUSED_0                                  (0xf<<4) // reserved
10738     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_CLKDLY_OVR_VAL_UNUSED_0_SHIFT                            4
10739 #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_EN                                            0x001244UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10740     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_EN_F221                                   (0x1<<0) // Override enable for afe_txdp_data_width AFE ovr_signal.
10741     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_EN_F221_SHIFT                             0
10742     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10743     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_EN_UNUSED_0_SHIFT                         1
10744 #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_VAL                                           0x001248UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10745     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_VAL_F222                                  (0x1<<0) // Override value for afe_txdp_data_width AFE input.
10746     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_VAL_F222_SHIFT                            0
10747     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10748     #define PHY_NW_IP_REG_PHY0_OVR_LN0_TXDP_DATA_WIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
10749 #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_EN                                                0x001400UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10750     #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_EN_F223                                       (0x1<<0) // Override enable for afe_calcomp_out AFE ovr_signal.
10751     #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_EN_F223_SHIFT                                 0
10752     #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
10753     #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_EN_UNUSED_0_SHIFT                             1
10754 #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_VAL                                               0x001404UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10755     #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_VAL_F224                                      (0x1<<0) // Override value for afe_calcomp_out AFE input.
10756     #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_VAL_F224_SHIFT                                0
10757     #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_VAL_UNUSED_0                                  (0x7f<<1) // reserved
10758     #define PHY_NW_IP_REG_PHY0_OVR_LN1_CALCOMP_OUT_OVR_VAL_UNUSED_0_SHIFT                            1
10759 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_EN                                                 0x001408UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10760     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_EN_F225                                        (0x1<<0) // Override enable for afe_rxcdr_dlpf AFE ovr_signal.
10761     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_EN_F225_SHIFT                                  0
10762     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
10763     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_EN_UNUSED_0_SHIFT                              1
10764 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_VAL_7_0                                            0x00140cUL //Access:RW   DataWidth:0x8   Override value for afe_rxcdr_dlpf AFE input.  Chips: K2
10765 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_VAL_8_8                                            0x001410UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10766     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_VAL_8_8_F227                                   (0x1<<0) // Override value for afe_rxcdr_dlpf AFE input.
10767     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_VAL_8_8_F227_SHIFT                             0
10768     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_VAL_8_8_UNUSED_0                               (0x7f<<1) // reserved
10769     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_DLPF_OVR_VAL_8_8_UNUSED_0_SHIFT                         1
10770 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_EN                                       0x001414UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10771     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_EN_F228                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clki_lsb AFE ovr_signal.
10772     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_EN_F228_SHIFT                        0
10773     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10774     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_EN_UNUSED_0_SHIFT                    1
10775 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_VAL                                      0x001418UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10776     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_F229                             (0x3<<0) // Override value for afe_rxcdr_hscan_clki_lsb AFE input.
10777     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_F229_SHIFT                       0
10778     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_UNUSED_0                         (0x3f<<2) // reserved
10779     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_UNUSED_0_SHIFT                   2
10780 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_EN                                       0x00141cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10781     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_EN_F230                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clki_msb AFE ovr_signal.
10782     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_EN_F230_SHIFT                        0
10783     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10784     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_EN_UNUSED_0_SHIFT                    1
10785 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_VAL                                      0x001420UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10786     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_F231                             (0x1f<<0) // Override value for afe_rxcdr_hscan_clki_msb AFE input.
10787     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_F231_SHIFT                       0
10788     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_UNUSED_0                         (0x7<<5) // reserved
10789     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_UNUSED_0_SHIFT                   5
10790 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_EN                                       0x001424UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10791     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_F232                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clkq_lsb AFE ovr_signal.
10792     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_F232_SHIFT                        0
10793     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10794     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_UNUSED_0_SHIFT                    1
10795 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL                                      0x001428UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10796     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_F233                             (0x3<<0) // Override value for afe_rxcdr_hscan_clkq_lsb AFE input.
10797     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_F233_SHIFT                       0
10798     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_UNUSED_0                         (0x3f<<2) // reserved
10799     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_UNUSED_0_SHIFT                   2
10800 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_EN                                       0x00142cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10801     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_F234                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clkq_msb AFE ovr_signal.
10802     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_F234_SHIFT                        0
10803     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10804     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_UNUSED_0_SHIFT                    1
10805 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL                                      0x001430UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10806     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_F235                             (0x1f<<0) // Override value for afe_rxcdr_hscan_clkq_msb AFE input.
10807     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_F235_SHIFT                       0
10808     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_UNUSED_0                         (0x7<<5) // reserved
10809     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_UNUSED_0_SHIFT                   5
10810 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN                                   0x001434UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10811     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_F236                          (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_lsb_fine AFE ovr_signal.
10812     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_F236_SHIFT                    0
10813     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_UNUSED_0                      (0x7f<<1) // reserved
10814     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_UNUSED_0_SHIFT                1
10815 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL                                  0x001438UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10816     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_F237                         (0x1<<0) // Override value for afe_rxcdr_hscan_eye_lsb_fine AFE input.
10817     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_F237_SHIFT                   0
10818     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_UNUSED_0                     (0x7f<<1) // reserved
10819     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_UNUSED_0_SHIFT               1
10820 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_EN                                        0x00143cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10821     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_EN_F238                               (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_lsb AFE ovr_signal.
10822     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_EN_F238_SHIFT                         0
10823     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
10824     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_EN_UNUSED_0_SHIFT                     1
10825 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_VAL                                       0x001440UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10826     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_VAL_F239                              (0xf<<0) // Override value for afe_rxcdr_hscan_eye_lsb AFE input.
10827     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_VAL_F239_SHIFT                        0
10828     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_VAL_UNUSED_0                          (0xf<<4) // reserved
10829     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_LSB_OVR_VAL_UNUSED_0_SHIFT                    4
10830 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_EN                                        0x001444UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10831     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_EN_F240                               (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_msb AFE ovr_signal.
10832     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_EN_F240_SHIFT                         0
10833     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
10834     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_EN_UNUSED_0_SHIFT                     1
10835 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_VAL                                       0x001448UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10836     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_VAL_F241                              (0x3<<0) // Override value for afe_rxcdr_hscan_eye_msb AFE input.
10837     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_VAL_F241_SHIFT                        0
10838     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_VAL_UNUSED_0                          (0x3f<<2) // reserved
10839     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_HSCAN_EYE_MSB_OVR_VAL_UNUSED_0_SHIFT                    2
10840 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_EN                                            0x00144cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10841     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_EN_F242                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_en AFE ovr_signal.
10842     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_EN_F242_SHIFT                             0
10843     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10844     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_EN_UNUSED_0_SHIFT                         1
10845 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_VAL                                           0x001450UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10846     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_VAL_F243                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_en AFE input.
10847     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_VAL_F243_SHIFT                            0
10848     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10849     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_EN_OVR_VAL_UNUSED_0_SHIFT                        1
10850 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_EN                                            0x001454UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10851     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_EN_F244                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_go AFE ovr_signal.
10852     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_EN_F244_SHIFT                             0
10853     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10854     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_EN_UNUSED_0_SHIFT                         1
10855 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_VAL                                           0x001458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10856     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_VAL_F245                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_go AFE input.
10857     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_VAL_F245_SHIFT                            0
10858     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10859     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_GO_OVR_VAL_UNUSED_0_SHIFT                        1
10860 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_EN                                          0x00145cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10861     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_EN_F246                                 (0x1<<0) // Override enable for afe_rxcdr_vcocal_load AFE ovr_signal.
10862     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_EN_F246_SHIFT                           0
10863     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_EN_UNUSED_0                             (0x7f<<1) // reserved
10864     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_EN_UNUSED_0_SHIFT                       1
10865 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_VAL                                         0x001460UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10866     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_VAL_F247                                (0x1<<0) // Override value for afe_rxcdr_vcocal_load AFE input.
10867     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_VAL_F247_SHIFT                          0
10868     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_VAL_UNUSED_0                            (0x7f<<1) // reserved
10869     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_LOAD_OVR_VAL_UNUSED_0_SHIFT                      1
10870 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_EN                                            0x001464UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10871     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_EN_F248                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_up AFE ovr_signal.
10872     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_EN_F248_SHIFT                             0
10873     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
10874     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_EN_UNUSED_0_SHIFT                         1
10875 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_VAL                                           0x001468UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10876     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_VAL_F249                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_up AFE input.
10877     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_VAL_F249_SHIFT                            0
10878     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
10879     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOCAL_UP_OVR_VAL_UNUSED_0_SHIFT                        1
10880 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_EN                                                0x00146cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10881     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_EN_F250                                       (0x1<<0) // Override enable for afe_rxcdr_vcofr AFE ovr_signal.
10882     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_EN_F250_SHIFT                                 0
10883     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
10884     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_EN_UNUSED_0_SHIFT                             1
10885 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_VAL                                               0x001470UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10886     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_VAL_F251                                      (0x1f<<0) // Override value for afe_rxcdr_vcofr AFE input.
10887     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_VAL_F251_SHIFT                                0
10888     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_VAL_UNUSED_0                                  (0x7<<5) // reserved
10889     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXCDR_VCOFR_OVR_VAL_UNUSED_0_SHIFT                            5
10890 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_EN                                       0x001474UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10891     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_EN_F252                              (0x1<<0) // Override enable for afe_rxdfe_clkdiv_qsample AFE ovr_signal.
10892     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_EN_F252_SHIFT                        0
10893     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
10894     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                    1
10895 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_VAL                                      0x001478UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10896     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_F253                             (0x1<<0) // Override value for afe_rxdfe_clkdiv_qsample AFE input.
10897     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_F253_SHIFT                       0
10898     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0                         (0x7f<<1) // reserved
10899     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                   1
10900 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN                                    0x00147cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10901     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_F254                           (0x1<<0) // Override enable for afe_rxdfe_clkdiveye_qsample AFE ovr_signal.
10902     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_F254_SHIFT                     0
10903     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_UNUSED_0                       (0x7f<<1) // reserved
10904     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                 1
10905 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL                                   0x001480UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10906     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_F255                          (0xf<<0) // Override value for afe_rxdfe_clkdiveye_qsample AFE input.
10907     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_F255_SHIFT                    0
10908     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_UNUSED_0                      (0xf<<4) // reserved
10909     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                4
10910 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN                               0x001484UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10911     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_F256                      (0x1<<0) // Override enable for afe_rxdfe_dataslicereven0_offset AFE ovr_signal.
10912     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_F256_SHIFT                0
10913     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_UNUSED_0                  (0x7f<<1) // reserved
10914     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_UNUSED_0_SHIFT            1
10915 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL                              0x001488UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10916     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_F257                     (0x3f<<0) // Override value for afe_rxdfe_dataslicereven0_offset AFE input.
10917     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_F257_SHIFT               0
10918     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_UNUSED_0                 (0x3<<6) // reserved
10919     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_UNUSED_0_SHIFT           6
10920 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN                               0x00148cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10921     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_F258                      (0x1<<0) // Override enable for afe_rxdfe_dataslicereven1_offset AFE ovr_signal.
10922     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_F258_SHIFT                0
10923     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_UNUSED_0                  (0x7f<<1) // reserved
10924     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_UNUSED_0_SHIFT            1
10925 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL                              0x001490UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10926     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_F259                     (0x3f<<0) // Override value for afe_rxdfe_dataslicereven1_offset AFE input.
10927     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_F259_SHIFT               0
10928     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_UNUSED_0                 (0x3<<6) // reserved
10929     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_UNUSED_0_SHIFT           6
10930 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_EN                                0x001494UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10931     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_F260                       (0x1<<0) // Override enable for afe_rxdfe_dataslicerodd0_offset AFE ovr_signal.
10932     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_F260_SHIFT                 0
10933     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
10934     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
10935 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL                               0x001498UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10936     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_F261                      (0x3f<<0) // Override value for afe_rxdfe_dataslicerodd0_offset AFE input.
10937     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_F261_SHIFT                0
10938     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
10939     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
10940 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_EN                                0x00149cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10941     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_F262                       (0x1<<0) // Override enable for afe_rxdfe_dataslicerodd1_offset AFE ovr_signal.
10942     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_F262_SHIFT                 0
10943     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
10944     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
10945 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL                               0x0014a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10946     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_F263                      (0x3f<<0) // Override value for afe_rxdfe_dataslicerodd1_offset AFE input.
10947     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_F263_SHIFT                0
10948     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
10949     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
10950 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN                                0x0014a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10951     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_F264                       (0x1<<0) // Override enable for afe_rxdfe_edgeslicereven_offset AFE ovr_signal.
10952     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_F264_SHIFT                 0
10953     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
10954     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
10955 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL                               0x0014a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10956     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_F265                      (0x3f<<0) // Override value for afe_rxdfe_edgeslicereven_offset AFE input.
10957     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_F265_SHIFT                0
10958     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
10959     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
10960 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_EN                                 0x0014acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10961     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_F266                        (0x1<<0) // Override enable for afe_rxdfe_edgeslicerodd_offset AFE ovr_signal.
10962     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_F266_SHIFT                  0
10963     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_UNUSED_0                    (0x7f<<1) // reserved
10964     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_UNUSED_0_SHIFT              1
10965 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL                                0x0014b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10966     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_F267                       (0x3f<<0) // Override value for afe_rxdfe_edgeslicerodd_offset AFE input.
10967     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_F267_SHIFT                 0
10968     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_UNUSED_0                   (0x3<<6) // reserved
10969     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT             6
10970 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_EN                                           0x0014b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10971     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_EN_F268                                  (0x1<<0) // Override enable for afe_rxdfe_even0_tap1 AFE ovr_signal.
10972     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_EN_F268_SHIFT                            0
10973     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10974     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_EN_UNUSED_0_SHIFT                        1
10975 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_VAL                                          0x0014b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10976     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_VAL_F269                                 (0x1f<<0) // Override value for afe_rxdfe_even0_tap1 AFE input.
10977     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_VAL_F269_SHIFT                           0
10978     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_VAL_UNUSED_0                             (0x7<<5) // reserved
10979     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN0_TAP1_OVR_VAL_UNUSED_0_SHIFT                       5
10980 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_EN                                           0x0014bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10981     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_EN_F270                                  (0x1<<0) // Override enable for afe_rxdfe_even1_tap1 AFE ovr_signal.
10982     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_EN_F270_SHIFT                            0
10983     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
10984     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_EN_UNUSED_0_SHIFT                        1
10985 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_VAL                                          0x0014c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10986     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_VAL_F271                                 (0x1f<<0) // Override value for afe_rxdfe_even1_tap1 AFE input.
10987     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_VAL_F271_SHIFT                           0
10988     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_VAL_UNUSED_0                             (0x7<<5) // reserved
10989     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EVEN1_TAP1_OVR_VAL_UNUSED_0_SHIFT                       5
10990 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_EN                                             0x0014c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10991     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_EN_F272                                    (0x1<<0) // Override enable for afe_rxdfe_eye_tap1 AFE ovr_signal.
10992     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_EN_F272_SHIFT                              0
10993     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
10994     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_EN_UNUSED_0_SHIFT                          1
10995 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_VAL                                            0x0014c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
10996     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_VAL_F273                                   (0x1f<<0) // Override value for afe_rxdfe_eye_tap1 AFE input.
10997     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_VAL_F273_SHIFT                             0
10998     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_VAL_UNUSED_0                               (0x7<<5) // reserved
10999     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_TAP1_OVR_VAL_UNUSED_0_SHIFT                         5
11000 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_EN                                        0x0014ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11001     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_EN_F274                               (0x1<<0) // Override enable for afe_rxdfe_eye_vscan_lsb AFE ovr_signal.
11002     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_EN_F274_SHIFT                         0
11003     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
11004     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_EN_UNUSED_0_SHIFT                     1
11005 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_VAL                                       0x0014d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11006     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_VAL_F275                              (0x1f<<0) // Override value for afe_rxdfe_eye_vscan_lsb AFE input.
11007     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_VAL_F275_SHIFT                        0
11008     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_VAL_UNUSED_0                          (0x7<<5) // reserved
11009     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_LSB_OVR_VAL_UNUSED_0_SHIFT                    5
11010 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_EN                                        0x0014d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11011     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_EN_F276                               (0x1<<0) // Override enable for afe_rxdfe_eye_vscan_msb AFE ovr_signal.
11012     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_EN_F276_SHIFT                         0
11013     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
11014     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_EN_UNUSED_0_SHIFT                     1
11015 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_VAL                                       0x0014d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11016     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_VAL_F277                              (0x7<<0) // Override value for afe_rxdfe_eye_vscan_msb AFE input.
11017     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_VAL_F277_SHIFT                        0
11018     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_VAL_UNUSED_0                          (0x1f<<3) // reserved
11019     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYE_VSCAN_MSB_OVR_VAL_UNUSED_0_SHIFT                    3
11020 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN                                 0x0014dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11021     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_F278                        (0x1<<0) // Override enable for afe_rxdfe_eyeslicereven_offset AFE ovr_signal.
11022     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_F278_SHIFT                  0
11023     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_UNUSED_0                    (0x7f<<1) // reserved
11024     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT              1
11025 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL                                0x0014e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11026     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_F279                       (0x3f<<0) // Override value for afe_rxdfe_eyeslicereven_offset AFE input.
11027     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_F279_SHIFT                 0
11028     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0                   (0x3<<6) // reserved
11029     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT             6
11030 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_EN                                  0x0014e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11031     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_EN_F280                         (0x1<<0) // Override enable for afe_rxdfe_eyeslicerodd_offset AFE ovr_signal.
11032     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_EN_F280_SHIFT                   0
11033     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_EN_UNUSED_0                     (0x7f<<1) // reserved
11034     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_EN_UNUSED_0_SHIFT               1
11035 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_VAL                                 0x0014e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11036     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_F281                        (0x3f<<0) // Override value for afe_rxdfe_eyeslicerodd_offset AFE input.
11037     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_F281_SHIFT                  0
11038     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_UNUSED_0                    (0x3<<6) // reserved
11039     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT              6
11040 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_EN                                            0x0014ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11041     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_EN_F282                                   (0x1<<0) // Override enable for afe_rxdfe_odd0_tap1 AFE ovr_signal.
11042     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_EN_F282_SHIFT                             0
11043     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11044     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_EN_UNUSED_0_SHIFT                         1
11045 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_VAL                                           0x0014f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11046     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_VAL_F283                                  (0x1f<<0) // Override value for afe_rxdfe_odd0_tap1 AFE input.
11047     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_VAL_F283_SHIFT                            0
11048     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
11049     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD0_TAP1_OVR_VAL_UNUSED_0_SHIFT                        5
11050 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_EN                                            0x0014f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11051     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_EN_F284                                   (0x1<<0) // Override enable for afe_rxdfe_odd1_tap1 AFE ovr_signal.
11052     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_EN_F284_SHIFT                             0
11053     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11054     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_EN_UNUSED_0_SHIFT                         1
11055 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_VAL                                           0x0014f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11056     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_VAL_F285                                  (0x1f<<0) // Override value for afe_rxdfe_odd1_tap1 AFE input.
11057     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_VAL_F285_SHIFT                            0
11058     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
11059     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_ODD1_TAP1_OVR_VAL_UNUSED_0_SHIFT                        5
11060 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_EN                                       0x0014fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11061     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_EN_F286                              (0x1<<0) // Override enable for afe_rxdfe_sumeven_offset AFE ovr_signal.
11062     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_EN_F286_SHIFT                        0
11063     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
11064     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT                    1
11065 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_VAL                                      0x001500UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11066     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_VAL_F287                             (0x3f<<0) // Override value for afe_rxdfe_sumeven_offset AFE input.
11067     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_VAL_F287_SHIFT                       0
11068     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_VAL_UNUSED_0                         (0x3<<6) // reserved
11069     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMEVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT                   6
11070 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_EN                                        0x001504UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11071     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_EN_F288                               (0x1<<0) // Override enable for afe_rxdfe_sumodd_offset AFE ovr_signal.
11072     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_EN_F288_SHIFT                         0
11073     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
11074     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_EN_UNUSED_0_SHIFT                     1
11075 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_VAL                                       0x001508UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11076     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_VAL_F289                              (0x3f<<0) // Override value for afe_rxdfe_sumodd_offset AFE input.
11077     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_VAL_F289_SHIFT                        0
11078     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_VAL_UNUSED_0                          (0x3<<6) // reserved
11079     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_SUMODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT                    6
11080 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_EN                                                 0x00150cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11081     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_EN_F290                                        (0x1<<0) // Override enable for afe_rxdfe_tap2 AFE ovr_signal.
11082     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_EN_F290_SHIFT                                  0
11083     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11084     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_EN_UNUSED_0_SHIFT                              1
11085 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_VAL                                                0x001510UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11086     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_VAL_F291                                       (0xf<<0) // Override value for afe_rxdfe_tap2 AFE input.
11087     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_VAL_F291_SHIFT                                 0
11088     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_VAL_UNUSED_0                                   (0xf<<4) // reserved
11089     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP2_OVR_VAL_UNUSED_0_SHIFT                             4
11090 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_EN                                                 0x001514UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11091     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_EN_F292                                        (0x1<<0) // Override enable for afe_rxdfe_tap3 AFE ovr_signal.
11092     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_EN_F292_SHIFT                                  0
11093     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11094     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_EN_UNUSED_0_SHIFT                              1
11095 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_VAL                                                0x001518UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11096     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_VAL_F293                                       (0x7<<0) // Override value for afe_rxdfe_tap3 AFE input.
11097     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_VAL_F293_SHIFT                                 0
11098     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
11099     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP3_OVR_VAL_UNUSED_0_SHIFT                             3
11100 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_EN                                                 0x00151cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11101     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_EN_F294                                        (0x1<<0) // Override enable for afe_rxdfe_tap4 AFE ovr_signal.
11102     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_EN_F294_SHIFT                                  0
11103     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11104     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_EN_UNUSED_0_SHIFT                              1
11105 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_VAL                                                0x001520UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11106     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_VAL_F295                                       (0x7<<0) // Override value for afe_rxdfe_tap4 AFE input.
11107     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_VAL_F295_SHIFT                                 0
11108     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
11109     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP4_OVR_VAL_UNUSED_0_SHIFT                             3
11110 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_EN                                                 0x001524UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11111     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_EN_F296                                        (0x1<<0) // Override enable for afe_rxdfe_tap5 AFE ovr_signal.
11112     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_EN_F296_SHIFT                                  0
11113     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11114     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_EN_UNUSED_0_SHIFT                              1
11115 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_VAL                                                0x001528UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11116     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_VAL_F297                                       (0x7<<0) // Override value for afe_rxdfe_tap5 AFE input.
11117     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_VAL_F297_SHIFT                                 0
11118     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
11119     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_TAP5_OVR_VAL_UNUSED_0_SHIFT                             3
11120 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_EN                                     0x00152cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11121     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_EN_F298                            (0x1<<0) // Override enable for afe_rxdfe_vscaneven_offset AFE ovr_signal.
11122     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_EN_F298_SHIFT                      0
11123     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_EN_UNUSED_0                        (0x7f<<1) // reserved
11124     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT                  1
11125 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_VAL                                    0x001530UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11126     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_F299                           (0x3f<<0) // Override value for afe_rxdfe_vscaneven_offset AFE input.
11127     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_F299_SHIFT                     0
11128     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_UNUSED_0                       (0x3<<6) // reserved
11129     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT                 6
11130 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_EN                                      0x001534UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11131     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_EN_F300                             (0x1<<0) // Override enable for afe_rxdfe_vscanodd_offset AFE ovr_signal.
11132     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_EN_F300_SHIFT                       0
11133     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_EN_UNUSED_0                         (0x7f<<1) // reserved
11134     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_EN_UNUSED_0_SHIFT                   1
11135 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_VAL                                     0x001538UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11136     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_VAL_F301                            (0x3f<<0) // Override value for afe_rxdfe_vscanodd_offset AFE input.
11137     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_VAL_F301_SHIFT                      0
11138     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_VAL_UNUSED_0                        (0x3<<6) // reserved
11139     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDFE_VSCANODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT                  6
11140 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_EN                                            0x00153cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11141     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_EN_F302                                   (0x1<<0) // Override enable for afe_rxdp_data_width AFE ovr_signal.
11142     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_EN_F302_SHIFT                             0
11143     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11144     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_EN_UNUSED_0_SHIFT                         1
11145 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_VAL                                           0x001540UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11146     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_VAL_F303                                  (0x1<<0) // Override value for afe_rxdp_data_width AFE input.
11147     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_VAL_F303_SHIFT                            0
11148     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
11149     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXDP_DATA_WIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
11150 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_EN                                           0x001544UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11151     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_EN_F304                                  (0x1<<0) // Override enable for afe_rxleq_eq_biasres AFE ovr_signal.
11152     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_EN_F304_SHIFT                            0
11153     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11154     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_EN_UNUSED_0_SHIFT                        1
11155 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_VAL                                          0x001548UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11156     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_VAL_F305                                 (0x7<<0) // Override value for afe_rxleq_eq_biasres AFE input.
11157     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_VAL_F305_SHIFT                           0
11158     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
11159     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_BIASRES_OVR_VAL_UNUSED_0_SHIFT                       3
11160 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_EN                                               0x00154cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11161     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_EN_F306                                      (0x1<<0) // Override enable for afe_rxleq_eq_hfg AFE ovr_signal.
11162     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_EN_F306_SHIFT                                0
11163     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11164     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_EN_UNUSED_0_SHIFT                            1
11165 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_VAL                                              0x001550UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11166     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_VAL_F307                                     (0x1f<<0) // Override value for afe_rxleq_eq_hfg AFE input.
11167     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_VAL_F307_SHIFT                               0
11168     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_VAL_UNUSED_0                                 (0x7<<5) // reserved
11169     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_HFG_OVR_VAL_UNUSED_0_SHIFT                           5
11170 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_EN                                               0x001554UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11171     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_EN_F308                                      (0x1<<0) // Override enable for afe_rxleq_eq_lfg AFE ovr_signal.
11172     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_EN_F308_SHIFT                                0
11173     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11174     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_EN_UNUSED_0_SHIFT                            1
11175 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_VAL                                              0x001558UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11176     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_VAL_F309                                     (0x1f<<0) // Override value for afe_rxleq_eq_lfg AFE input.
11177     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_VAL_F309_SHIFT                               0
11178     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_VAL_UNUSED_0                                 (0x7<<5) // reserved
11179     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LFG_OVR_VAL_UNUSED_0_SHIFT                           5
11180 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_EN                                           0x00155cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11181     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_EN_F310                                  (0x1<<0) // Override enable for afe_rxleq_eq_loadres AFE ovr_signal.
11182     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_EN_F310_SHIFT                            0
11183     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11184     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_EN_UNUSED_0_SHIFT                        1
11185 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_VAL                                          0x001560UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11186     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_VAL_F311                                 (0x7<<0) // Override value for afe_rxleq_eq_loadres AFE input.
11187     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_VAL_F311_SHIFT                           0
11188     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
11189     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_LOADRES_OVR_VAL_UNUSED_0_SHIFT                       3
11190 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_EN                                               0x001564UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11191     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_EN_F312                                      (0x1<<0) // Override enable for afe_rxleq_eq_mbf AFE ovr_signal.
11192     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_EN_F312_SHIFT                                0
11193     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11194     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_EN_UNUSED_0_SHIFT                            1
11195 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_VAL                                              0x001568UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11196     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_VAL_F313                                     (0xf<<0) // Override value for afe_rxleq_eq_mbf AFE input.
11197     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_VAL_F313_SHIFT                               0
11198     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_VAL_UNUSED_0                                 (0xf<<4) // reserved
11199     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBF_OVR_VAL_UNUSED_0_SHIFT                           4
11200 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_EN                                               0x00156cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11201     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_EN_F314                                      (0x1<<0) // Override enable for afe_rxleq_eq_mbg AFE ovr_signal.
11202     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_EN_F314_SHIFT                                0
11203     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11204     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_EN_UNUSED_0_SHIFT                            1
11205 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_VAL                                              0x001570UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11206     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_VAL_F315                                     (0xf<<0) // Override value for afe_rxleq_eq_mbg AFE input.
11207     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_VAL_F315_SHIFT                               0
11208     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_VAL_UNUSED_0                                 (0xf<<4) // reserved
11209     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_MBG_OVR_VAL_UNUSED_0_SHIFT                           4
11210 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_EN                                               0x001574UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11211     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_EN_F316                                      (0x1<<0) // Override enable for afe_rxleq_eq_sql AFE ovr_signal.
11212     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_EN_F316_SHIFT                                0
11213     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11214     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_EN_UNUSED_0_SHIFT                            1
11215 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_VAL                                              0x001578UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11216     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_VAL_F317                                     (0x7<<0) // Override value for afe_rxleq_eq_sql AFE input.
11217     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_VAL_F317_SHIFT                               0
11218     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_VAL_UNUSED_0                                 (0x1f<<3) // reserved
11219     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_EQ_SQL_OVR_VAL_UNUSED_0_SHIFT                           3
11220 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_EN                                               0x00157cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11221     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_EN_F318                                      (0x1<<0) // Override enable for afe_rxleq_gn_apg AFE ovr_signal.
11222     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_EN_F318_SHIFT                                0
11223     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11224     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_EN_UNUSED_0_SHIFT                            1
11225 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_VAL                                              0x001580UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11226     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_VAL_F319                                     (0x3<<0) // Override value for afe_rxleq_gn_apg AFE input.
11227     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_VAL_F319_SHIFT                               0
11228     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_VAL_UNUSED_0                                 (0x3f<<2) // reserved
11229     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_APG_OVR_VAL_UNUSED_0_SHIFT                           2
11230 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_EN                                             0x001584UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11231     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_EN_F320                                    (0x1<<0) // Override enable for afe_rxleq_gn_biasi AFE ovr_signal.
11232     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_EN_F320_SHIFT                              0
11233     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
11234     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_EN_UNUSED_0_SHIFT                          1
11235 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_VAL                                            0x001588UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11236     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_VAL_F321                                   (0x3<<0) // Override value for afe_rxleq_gn_biasi AFE input.
11237     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_VAL_F321_SHIFT                             0
11238     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_VAL_UNUSED_0                               (0x3f<<2) // reserved
11239     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_BIASI_OVR_VAL_UNUSED_0_SHIFT                         2
11240 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_EN                                           0x00158cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11241     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_EN_F322                                  (0x1<<0) // Override enable for afe_rxleq_gn_loadres AFE ovr_signal.
11242     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_EN_F322_SHIFT                            0
11243     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11244     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_EN_UNUSED_0_SHIFT                        1
11245 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_VAL                                          0x001590UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11246     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_VAL_F323                                 (0x7<<0) // Override value for afe_rxleq_gn_loadres AFE input.
11247     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_VAL_F323_SHIFT                           0
11248     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
11249     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_GN_LOADRES_OVR_VAL_UNUSED_0_SHIFT                       3
11250 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_EN                                            0x001594UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11251     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_EN_F324                                   (0x1<<0) // Override enable for afe_rxleq_offset_e1 AFE ovr_signal.
11252     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_EN_F324_SHIFT                             0
11253     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11254     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_EN_UNUSED_0_SHIFT                         1
11255 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_VAL                                           0x001598UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11256     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_VAL_F325                                  (0x3f<<0) // Override value for afe_rxleq_offset_e1 AFE input.
11257     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_VAL_F325_SHIFT                            0
11258     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
11259     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E1_OVR_VAL_UNUSED_0_SHIFT                        6
11260 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_EN                                            0x00159cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11261     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_EN_F326                                   (0x1<<0) // Override enable for afe_rxleq_offset_e2 AFE ovr_signal.
11262     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_EN_F326_SHIFT                             0
11263     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11264     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_EN_UNUSED_0_SHIFT                         1
11265 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_VAL                                           0x0015a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11266     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_VAL_F327                                  (0x3f<<0) // Override value for afe_rxleq_offset_e2 AFE input.
11267     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_VAL_F327_SHIFT                            0
11268     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
11269     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E2_OVR_VAL_UNUSED_0_SHIFT                        6
11270 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_EN                                            0x0015a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11271     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_EN_F328                                   (0x1<<0) // Override enable for afe_rxleq_offset_e3 AFE ovr_signal.
11272     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_EN_F328_SHIFT                             0
11273     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11274     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_EN_UNUSED_0_SHIFT                         1
11275 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_VAL                                           0x0015a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11276     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_VAL_F329                                  (0x3f<<0) // Override value for afe_rxleq_offset_e3 AFE input.
11277     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_VAL_F329_SHIFT                            0
11278     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
11279     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E3_OVR_VAL_UNUSED_0_SHIFT                        6
11280 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_EN                                            0x0015acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11281     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_EN_F330                                   (0x1<<0) // Override enable for afe_rxleq_offset_e4 AFE ovr_signal.
11282     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_EN_F330_SHIFT                             0
11283     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11284     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_EN_UNUSED_0_SHIFT                         1
11285 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_VAL                                           0x0015b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11286     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_VAL_F331                                  (0x3f<<0) // Override value for afe_rxleq_offset_e4 AFE input.
11287     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_VAL_F331_SHIFT                            0
11288     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
11289     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E4_OVR_VAL_UNUSED_0_SHIFT                        6
11290 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_EN                                            0x0015b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11291     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_EN_F332                                   (0x1<<0) // Override enable for afe_rxleq_offset_e5 AFE ovr_signal.
11292     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_EN_F332_SHIFT                             0
11293     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11294     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_EN_UNUSED_0_SHIFT                         1
11295 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_VAL                                           0x0015b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11296     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_VAL_F333                                  (0x3f<<0) // Override value for afe_rxleq_offset_e5 AFE input.
11297     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_VAL_F333_SHIFT                            0
11298     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
11299     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E5_OVR_VAL_UNUSED_0_SHIFT                        6
11300 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_EN                                            0x0015bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11301     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_EN_F334                                   (0x1<<0) // Override enable for afe_rxleq_offset_e6 AFE ovr_signal.
11302     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_EN_F334_SHIFT                             0
11303     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11304     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_EN_UNUSED_0_SHIFT                         1
11305 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_VAL                                           0x0015c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11306     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_VAL_F335                                  (0x3f<<0) // Override value for afe_rxleq_offset_e6 AFE input.
11307     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_VAL_F335_SHIFT                            0
11308     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
11309     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_E6_OVR_VAL_UNUSED_0_SHIFT                        6
11310 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_EN                                            0x0015c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11311     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_EN_F336                                   (0x1<<0) // Override enable for afe_rxleq_offset_g1 AFE ovr_signal.
11312     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_EN_F336_SHIFT                             0
11313     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11314     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_EN_UNUSED_0_SHIFT                         1
11315 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_VAL                                           0x0015c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11316     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_VAL_F337                                  (0x3f<<0) // Override value for afe_rxleq_offset_g1 AFE input.
11317     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_VAL_F337_SHIFT                            0
11318     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
11319     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_OFFSET_G1_OVR_VAL_UNUSED_0_SHIFT                        6
11320 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_EN                                              0x0015ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11321     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_EN_F338                                     (0x1<<0) // Override enable for afe_rxleq_ple_att AFE ovr_signal.
11322     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_EN_F338_SHIFT                               0
11323     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
11324     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_EN_UNUSED_0_SHIFT                           1
11325 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_VAL                                             0x0015d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11326     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_VAL_F339                                    (0x7<<0) // Override value for afe_rxleq_ple_att AFE input.
11327     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_VAL_F339_SHIFT                              0
11328     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_VAL_UNUSED_0                                (0x1f<<3) // reserved
11329     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLEQ_PLE_ATT_OVR_VAL_UNUSED_0_SHIFT                          3
11330 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_EN                                                  0x0015d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11331     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_EN_F340                                         (0x1<<0) // Override enable for afe_rxlos_agc AFE ovr_signal.
11332     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_EN_F340_SHIFT                                   0
11333     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_EN_UNUSED_0                                     (0x7f<<1) // reserved
11334     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_EN_UNUSED_0_SHIFT                               1
11335 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_VAL                                                 0x0015d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11336     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_VAL_F341                                        (0x1<<0) // Override value for afe_rxlos_agc AFE input.
11337     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_VAL_F341_SHIFT                                  0
11338     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_VAL_UNUSED_0                                    (0x7f<<1) // reserved
11339     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_OVR_VAL_UNUSED_0_SHIFT                              1
11340 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_EN                                              0x0015dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11341     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_EN_F342                                     (0x1<<0) // Override enable for afe_rxlos_agc_set AFE ovr_signal.
11342     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_EN_F342_SHIFT                               0
11343     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
11344     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_EN_UNUSED_0_SHIFT                           1
11345 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_VAL                                             0x0015e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11346     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_VAL_F343                                    (0x1<<0) // Override value for afe_rxlos_agc_set AFE input.
11347     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_VAL_F343_SHIFT                              0
11348     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_VAL_UNUSED_0                                (0x7f<<1) // reserved
11349     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_AGC_SET_OVR_VAL_UNUSED_0_SHIFT                          1
11350 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_EN                                            0x0015e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11351     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_EN_F344                                   (0x1<<0) // Override enable for afe_rxlos_bandwidth AFE ovr_signal.
11352     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_EN_F344_SHIFT                             0
11353     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11354     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_EN_UNUSED_0_SHIFT                         1
11355 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_VAL                                           0x0015e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11356     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_VAL_F345                                  (0x1<<0) // Override value for afe_rxlos_bandwidth AFE input.
11357     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_VAL_F345_SHIFT                            0
11358     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
11359     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_BANDWIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
11360 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_EN                                             0x0015ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11361     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_EN_F346                                    (0x1<<0) // Override enable for afe_rxlos_comp_sel AFE ovr_signal.
11362     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_EN_F346_SHIFT                              0
11363     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
11364     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_EN_UNUSED_0_SHIFT                          1
11365 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_VAL                                            0x0015f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11366     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_VAL_F347                                   (0x1<<0) // Override value for afe_rxlos_comp_sel AFE input.
11367     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_VAL_F347_SHIFT                             0
11368     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_VAL_UNUSED_0                               (0x7f<<1) // reserved
11369     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_COMP_SEL_OVR_VAL_UNUSED_0_SHIFT                         1
11370 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_EN                                           0x0015f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11371     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_EN_F348                                  (0x1<<0) // Override enable for afe_rxlos_envdet_byp AFE ovr_signal.
11372     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_EN_F348_SHIFT                            0
11373     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11374     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_EN_UNUSED_0_SHIFT                        1
11375 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_VAL                                          0x0015f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11376     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_VAL_F349                                 (0x1<<0) // Override value for afe_rxlos_envdet_byp AFE input.
11377     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_VAL_F349_SHIFT                           0
11378     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_VAL_UNUSED_0                             (0x7f<<1) // reserved
11379     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_ENVDET_BYP_OVR_VAL_UNUSED_0_SHIFT                       1
11380 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_EN                                                 0x0015fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11381     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_EN_F350                                        (0x1<<0) // Override enable for afe_rxlos_gain AFE ovr_signal.
11382     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_EN_F350_SHIFT                                  0
11383     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11384     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_EN_UNUSED_0_SHIFT                              1
11385 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_VAL                                                0x001600UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11386     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_VAL_F351                                       (0x1<<0) // Override value for afe_rxlos_gain AFE input.
11387     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_VAL_F351_SHIFT                                 0
11388     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_VAL_UNUSED_0                                   (0x7f<<1) // reserved
11389     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_GAIN_OVR_VAL_UNUSED_0_SHIFT                             1
11390 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_EN                                           0x001604UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11391     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_EN_F352                                  (0x1<<0) // Override enable for afe_rxlos_hysteresis AFE ovr_signal.
11392     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_EN_F352_SHIFT                            0
11393     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11394     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_EN_UNUSED_0_SHIFT                        1
11395 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_VAL                                          0x001608UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11396     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_VAL_F353                                 (0x7<<0) // Override value for afe_rxlos_hysteresis AFE input.
11397     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_VAL_F353_SHIFT                           0
11398     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
11399     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_HYSTERESIS_OVR_VAL_UNUSED_0_SHIFT                       3
11400 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_EN                                               0x00160cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11401     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_EN_F354                                      (0x1<<0) // Override enable for afe_rxlos_offset AFE ovr_signal.
11402     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_EN_F354_SHIFT                                0
11403     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11404     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_EN_UNUSED_0_SHIFT                            1
11405 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_VAL                                              0x001610UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11406     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_VAL_F355                                     (0x3f<<0) // Override value for afe_rxlos_offset AFE input.
11407     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_VAL_F355_SHIFT                               0
11408     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_VAL_UNUSED_0                                 (0x3<<6) // reserved
11409     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_OFFSET_OVR_VAL_UNUSED_0_SHIFT                           6
11410 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_EN                                                  0x001614UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11411     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_EN_F356                                         (0x1<<0) // Override enable for afe_rxlos_raw AFE ovr_signal.
11412     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_EN_F356_SHIFT                                   0
11413     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_EN_UNUSED_0                                     (0x7f<<1) // reserved
11414     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_EN_UNUSED_0_SHIFT                               1
11415 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_VAL                                                 0x001618UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11416     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_VAL_F357                                        (0x1<<0) // Override value for afe_rxlos_raw AFE input.
11417     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_VAL_F357_SHIFT                                  0
11418     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_VAL_UNUSED_0                                    (0x7f<<1) // reserved
11419     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_RAW_OVR_VAL_UNUSED_0_SHIFT                              1
11420 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_EN                                                0x00161cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11421     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_EN_F358                                       (0x1<<0) // Override enable for afe_rxlos_spare AFE ovr_signal.
11422     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_EN_F358_SHIFT                                 0
11423     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
11424     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_EN_UNUSED_0_SHIFT                             1
11425 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_VAL                                               0x001620UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11426     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_VAL_F359                                      (0xf<<0) // Override value for afe_rxlos_spare AFE input.
11427     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_VAL_F359_SHIFT                                0
11428     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_VAL_UNUSED_0                                  (0xf<<4) // reserved
11429     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_SPARE_OVR_VAL_UNUSED_0_SHIFT                            4
11430 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_EN                                            0x001624UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11431     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_EN_F360                                   (0x1<<0) // Override enable for afe_rxlos_threshold AFE ovr_signal.
11432     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_EN_F360_SHIFT                             0
11433     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11434     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_EN_UNUSED_0_SHIFT                         1
11435 #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_VAL                                           0x001628UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11436     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_VAL_F361                                  (0xf<<0) // Override value for afe_rxlos_threshold AFE input.
11437     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_VAL_F361_SHIFT                            0
11438     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_VAL_UNUSED_0                              (0xf<<4) // reserved
11439     #define PHY_NW_IP_REG_PHY0_OVR_LN1_RXLOS_THRESHOLD_OVR_VAL_UNUSED_0_SHIFT                        4
11440 #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_EN                                              0x00162cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11441     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_EN_F362                                     (0x1<<0) // Override enable for afe_txcp_dcd_trim AFE ovr_signal.
11442     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_EN_F362_SHIFT                               0
11443     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
11444     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_EN_UNUSED_0_SHIFT                           1
11445 #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_VAL                                             0x001630UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11446     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_VAL_F363                                    (0x3f<<0) // Override value for afe_txcp_dcd_trim AFE input.
11447     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_VAL_F363_SHIFT                              0
11448     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_VAL_UNUSED_0                                (0x3<<6) // reserved
11449     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXCP_DCD_TRIM_OVR_VAL_UNUSED_0_SHIFT                          6
11450 #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_EN                                               0x001634UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11451     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_EN_F364                                      (0x1<<0) // Override enable for afe_txdp_cal_out AFE ovr_signal.
11452     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_EN_F364_SHIFT                                0
11453     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11454     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_EN_UNUSED_0_SHIFT                            1
11455 #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_VAL                                              0x001638UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11456     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_VAL_F365                                     (0x1<<0) // Override value for afe_txdp_cal_out AFE input.
11457     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_VAL_F365_SHIFT                               0
11458     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_VAL_UNUSED_0                                 (0x7f<<1) // reserved
11459     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CAL_OUT_OVR_VAL_UNUSED_0_SHIFT                           1
11460 #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_EN                                                0x00163cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11461     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_EN_F366                                       (0x1<<0) // Override enable for afe_txdp_clkdly AFE ovr_signal.
11462     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_EN_F366_SHIFT                                 0
11463     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
11464     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_EN_UNUSED_0_SHIFT                             1
11465 #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_VAL                                               0x001640UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11466     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_VAL_F367                                      (0xf<<0) // Override value for afe_txdp_clkdly AFE input.
11467     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_VAL_F367_SHIFT                                0
11468     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_VAL_UNUSED_0                                  (0xf<<4) // reserved
11469     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_CLKDLY_OVR_VAL_UNUSED_0_SHIFT                            4
11470 #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_EN                                            0x001644UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11471     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_EN_F368                                   (0x1<<0) // Override enable for afe_txdp_data_width AFE ovr_signal.
11472     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_EN_F368_SHIFT                             0
11473     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11474     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_EN_UNUSED_0_SHIFT                         1
11475 #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_VAL                                           0x001648UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11476     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_VAL_F369                                  (0x1<<0) // Override value for afe_txdp_data_width AFE input.
11477     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_VAL_F369_SHIFT                            0
11478     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
11479     #define PHY_NW_IP_REG_PHY0_OVR_LN1_TXDP_DATA_WIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
11480 #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_EN                                                0x001800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11481     #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_EN_F370                                       (0x1<<0) // Override enable for afe_calcomp_out AFE ovr_signal.
11482     #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_EN_F370_SHIFT                                 0
11483     #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
11484     #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_EN_UNUSED_0_SHIFT                             1
11485 #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_VAL                                               0x001804UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11486     #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_VAL_F371                                      (0x1<<0) // Override value for afe_calcomp_out AFE input.
11487     #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_VAL_F371_SHIFT                                0
11488     #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_VAL_UNUSED_0                                  (0x7f<<1) // reserved
11489     #define PHY_NW_IP_REG_PHY0_OVR_LN2_CALCOMP_OUT_OVR_VAL_UNUSED_0_SHIFT                            1
11490 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_EN                                                 0x001808UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11491     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_EN_F372                                        (0x1<<0) // Override enable for afe_rxcdr_dlpf AFE ovr_signal.
11492     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_EN_F372_SHIFT                                  0
11493     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11494     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_EN_UNUSED_0_SHIFT                              1
11495 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_VAL_7_0                                            0x00180cUL //Access:RW   DataWidth:0x8   Override value for afe_rxcdr_dlpf AFE input.  Chips: K2
11496 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_VAL_8_8                                            0x001810UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11497     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_VAL_8_8_F374                                   (0x1<<0) // Override value for afe_rxcdr_dlpf AFE input.
11498     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_VAL_8_8_F374_SHIFT                             0
11499     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_VAL_8_8_UNUSED_0                               (0x7f<<1) // reserved
11500     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_DLPF_OVR_VAL_8_8_UNUSED_0_SHIFT                         1
11501 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_EN                                       0x001814UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11502     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_EN_F375                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clki_lsb AFE ovr_signal.
11503     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_EN_F375_SHIFT                        0
11504     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
11505     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_EN_UNUSED_0_SHIFT                    1
11506 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_VAL                                      0x001818UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11507     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_F376                             (0x3<<0) // Override value for afe_rxcdr_hscan_clki_lsb AFE input.
11508     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_F376_SHIFT                       0
11509     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_UNUSED_0                         (0x3f<<2) // reserved
11510     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_UNUSED_0_SHIFT                   2
11511 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_EN                                       0x00181cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11512     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_EN_F377                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clki_msb AFE ovr_signal.
11513     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_EN_F377_SHIFT                        0
11514     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
11515     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_EN_UNUSED_0_SHIFT                    1
11516 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_VAL                                      0x001820UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11517     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_F378                             (0x1f<<0) // Override value for afe_rxcdr_hscan_clki_msb AFE input.
11518     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_F378_SHIFT                       0
11519     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_UNUSED_0                         (0x7<<5) // reserved
11520     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_UNUSED_0_SHIFT                   5
11521 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_EN                                       0x001824UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11522     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_F379                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clkq_lsb AFE ovr_signal.
11523     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_F379_SHIFT                        0
11524     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
11525     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_UNUSED_0_SHIFT                    1
11526 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL                                      0x001828UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11527     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_F380                             (0x3<<0) // Override value for afe_rxcdr_hscan_clkq_lsb AFE input.
11528     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_F380_SHIFT                       0
11529     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_UNUSED_0                         (0x3f<<2) // reserved
11530     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_UNUSED_0_SHIFT                   2
11531 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_EN                                       0x00182cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11532     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_F381                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clkq_msb AFE ovr_signal.
11533     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_F381_SHIFT                        0
11534     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
11535     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_UNUSED_0_SHIFT                    1
11536 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL                                      0x001830UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11537     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_F382                             (0x1f<<0) // Override value for afe_rxcdr_hscan_clkq_msb AFE input.
11538     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_F382_SHIFT                       0
11539     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_UNUSED_0                         (0x7<<5) // reserved
11540     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_UNUSED_0_SHIFT                   5
11541 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN                                   0x001834UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11542     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_F383                          (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_lsb_fine AFE ovr_signal.
11543     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_F383_SHIFT                    0
11544     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_UNUSED_0                      (0x7f<<1) // reserved
11545     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_UNUSED_0_SHIFT                1
11546 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL                                  0x001838UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11547     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_F384                         (0x1<<0) // Override value for afe_rxcdr_hscan_eye_lsb_fine AFE input.
11548     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_F384_SHIFT                   0
11549     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_UNUSED_0                     (0x7f<<1) // reserved
11550     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_UNUSED_0_SHIFT               1
11551 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_EN                                        0x00183cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11552     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_EN_F385                               (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_lsb AFE ovr_signal.
11553     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_EN_F385_SHIFT                         0
11554     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
11555     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_EN_UNUSED_0_SHIFT                     1
11556 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_VAL                                       0x001840UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11557     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_VAL_F386                              (0xf<<0) // Override value for afe_rxcdr_hscan_eye_lsb AFE input.
11558     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_VAL_F386_SHIFT                        0
11559     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_VAL_UNUSED_0                          (0xf<<4) // reserved
11560     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_LSB_OVR_VAL_UNUSED_0_SHIFT                    4
11561 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_EN                                        0x001844UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11562     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_EN_F387                               (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_msb AFE ovr_signal.
11563     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_EN_F387_SHIFT                         0
11564     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
11565     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_EN_UNUSED_0_SHIFT                     1
11566 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_VAL                                       0x001848UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11567     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_VAL_F388                              (0x3<<0) // Override value for afe_rxcdr_hscan_eye_msb AFE input.
11568     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_VAL_F388_SHIFT                        0
11569     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_VAL_UNUSED_0                          (0x3f<<2) // reserved
11570     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_HSCAN_EYE_MSB_OVR_VAL_UNUSED_0_SHIFT                    2
11571 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_EN                                            0x00184cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11572     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_EN_F389                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_en AFE ovr_signal.
11573     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_EN_F389_SHIFT                             0
11574     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11575     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_EN_UNUSED_0_SHIFT                         1
11576 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_VAL                                           0x001850UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11577     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_VAL_F390                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_en AFE input.
11578     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_VAL_F390_SHIFT                            0
11579     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
11580     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_EN_OVR_VAL_UNUSED_0_SHIFT                        1
11581 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_EN                                            0x001854UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11582     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_EN_F391                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_go AFE ovr_signal.
11583     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_EN_F391_SHIFT                             0
11584     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11585     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_EN_UNUSED_0_SHIFT                         1
11586 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_VAL                                           0x001858UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11587     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_VAL_F392                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_go AFE input.
11588     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_VAL_F392_SHIFT                            0
11589     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
11590     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_GO_OVR_VAL_UNUSED_0_SHIFT                        1
11591 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_EN                                          0x00185cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11592     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_EN_F393                                 (0x1<<0) // Override enable for afe_rxcdr_vcocal_load AFE ovr_signal.
11593     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_EN_F393_SHIFT                           0
11594     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_EN_UNUSED_0                             (0x7f<<1) // reserved
11595     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_EN_UNUSED_0_SHIFT                       1
11596 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_VAL                                         0x001860UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11597     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_VAL_F394                                (0x1<<0) // Override value for afe_rxcdr_vcocal_load AFE input.
11598     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_VAL_F394_SHIFT                          0
11599     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_VAL_UNUSED_0                            (0x7f<<1) // reserved
11600     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_LOAD_OVR_VAL_UNUSED_0_SHIFT                      1
11601 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_EN                                            0x001864UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11602     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_EN_F395                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_up AFE ovr_signal.
11603     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_EN_F395_SHIFT                             0
11604     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11605     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_EN_UNUSED_0_SHIFT                         1
11606 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_VAL                                           0x001868UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11607     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_VAL_F396                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_up AFE input.
11608     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_VAL_F396_SHIFT                            0
11609     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
11610     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOCAL_UP_OVR_VAL_UNUSED_0_SHIFT                        1
11611 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_EN                                                0x00186cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11612     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_EN_F397                                       (0x1<<0) // Override enable for afe_rxcdr_vcofr AFE ovr_signal.
11613     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_EN_F397_SHIFT                                 0
11614     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
11615     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_EN_UNUSED_0_SHIFT                             1
11616 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_VAL                                               0x001870UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11617     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_VAL_F398                                      (0x1f<<0) // Override value for afe_rxcdr_vcofr AFE input.
11618     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_VAL_F398_SHIFT                                0
11619     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_VAL_UNUSED_0                                  (0x7<<5) // reserved
11620     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXCDR_VCOFR_OVR_VAL_UNUSED_0_SHIFT                            5
11621 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_EN                                       0x001874UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11622     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_EN_F399                              (0x1<<0) // Override enable for afe_rxdfe_clkdiv_qsample AFE ovr_signal.
11623     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_EN_F399_SHIFT                        0
11624     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
11625     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                    1
11626 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_VAL                                      0x001878UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11627     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_F400                             (0x1<<0) // Override value for afe_rxdfe_clkdiv_qsample AFE input.
11628     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_F400_SHIFT                       0
11629     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0                         (0x7f<<1) // reserved
11630     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                   1
11631 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN                                    0x00187cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11632     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_F401                           (0x1<<0) // Override enable for afe_rxdfe_clkdiveye_qsample AFE ovr_signal.
11633     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_F401_SHIFT                     0
11634     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_UNUSED_0                       (0x7f<<1) // reserved
11635     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                 1
11636 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL                                   0x001880UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11637     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_F402                          (0xf<<0) // Override value for afe_rxdfe_clkdiveye_qsample AFE input.
11638     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_F402_SHIFT                    0
11639     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_UNUSED_0                      (0xf<<4) // reserved
11640     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                4
11641 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN                               0x001884UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11642     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_F403                      (0x1<<0) // Override enable for afe_rxdfe_dataslicereven0_offset AFE ovr_signal.
11643     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_F403_SHIFT                0
11644     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_UNUSED_0                  (0x7f<<1) // reserved
11645     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_UNUSED_0_SHIFT            1
11646 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL                              0x001888UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11647     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_F404                     (0x3f<<0) // Override value for afe_rxdfe_dataslicereven0_offset AFE input.
11648     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_F404_SHIFT               0
11649     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_UNUSED_0                 (0x3<<6) // reserved
11650     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_UNUSED_0_SHIFT           6
11651 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN                               0x00188cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11652     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_F405                      (0x1<<0) // Override enable for afe_rxdfe_dataslicereven1_offset AFE ovr_signal.
11653     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_F405_SHIFT                0
11654     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_UNUSED_0                  (0x7f<<1) // reserved
11655     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_UNUSED_0_SHIFT            1
11656 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL                              0x001890UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11657     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_F406                     (0x3f<<0) // Override value for afe_rxdfe_dataslicereven1_offset AFE input.
11658     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_F406_SHIFT               0
11659     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_UNUSED_0                 (0x3<<6) // reserved
11660     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_UNUSED_0_SHIFT           6
11661 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_EN                                0x001894UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11662     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_F407                       (0x1<<0) // Override enable for afe_rxdfe_dataslicerodd0_offset AFE ovr_signal.
11663     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_F407_SHIFT                 0
11664     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
11665     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
11666 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL                               0x001898UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11667     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_F408                      (0x3f<<0) // Override value for afe_rxdfe_dataslicerodd0_offset AFE input.
11668     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_F408_SHIFT                0
11669     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
11670     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
11671 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_EN                                0x00189cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11672     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_F409                       (0x1<<0) // Override enable for afe_rxdfe_dataslicerodd1_offset AFE ovr_signal.
11673     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_F409_SHIFT                 0
11674     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
11675     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
11676 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL                               0x0018a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11677     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_F410                      (0x3f<<0) // Override value for afe_rxdfe_dataslicerodd1_offset AFE input.
11678     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_F410_SHIFT                0
11679     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
11680     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
11681 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN                                0x0018a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11682     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_F411                       (0x1<<0) // Override enable for afe_rxdfe_edgeslicereven_offset AFE ovr_signal.
11683     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_F411_SHIFT                 0
11684     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
11685     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
11686 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL                               0x0018a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11687     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_F412                      (0x3f<<0) // Override value for afe_rxdfe_edgeslicereven_offset AFE input.
11688     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_F412_SHIFT                0
11689     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
11690     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
11691 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_EN                                 0x0018acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11692     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_F413                        (0x1<<0) // Override enable for afe_rxdfe_edgeslicerodd_offset AFE ovr_signal.
11693     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_F413_SHIFT                  0
11694     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_UNUSED_0                    (0x7f<<1) // reserved
11695     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_UNUSED_0_SHIFT              1
11696 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL                                0x0018b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11697     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_F414                       (0x3f<<0) // Override value for afe_rxdfe_edgeslicerodd_offset AFE input.
11698     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_F414_SHIFT                 0
11699     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_UNUSED_0                   (0x3<<6) // reserved
11700     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT             6
11701 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_EN                                           0x0018b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11702     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_EN_F415                                  (0x1<<0) // Override enable for afe_rxdfe_even0_tap1 AFE ovr_signal.
11703     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_EN_F415_SHIFT                            0
11704     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11705     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_EN_UNUSED_0_SHIFT                        1
11706 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_VAL                                          0x0018b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11707     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_VAL_F416                                 (0x1f<<0) // Override value for afe_rxdfe_even0_tap1 AFE input.
11708     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_VAL_F416_SHIFT                           0
11709     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_VAL_UNUSED_0                             (0x7<<5) // reserved
11710     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN0_TAP1_OVR_VAL_UNUSED_0_SHIFT                       5
11711 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_EN                                           0x0018bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11712     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_EN_F417                                  (0x1<<0) // Override enable for afe_rxdfe_even1_tap1 AFE ovr_signal.
11713     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_EN_F417_SHIFT                            0
11714     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11715     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_EN_UNUSED_0_SHIFT                        1
11716 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_VAL                                          0x0018c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11717     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_VAL_F418                                 (0x1f<<0) // Override value for afe_rxdfe_even1_tap1 AFE input.
11718     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_VAL_F418_SHIFT                           0
11719     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_VAL_UNUSED_0                             (0x7<<5) // reserved
11720     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EVEN1_TAP1_OVR_VAL_UNUSED_0_SHIFT                       5
11721 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_EN                                             0x0018c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11722     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_EN_F419                                    (0x1<<0) // Override enable for afe_rxdfe_eye_tap1 AFE ovr_signal.
11723     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_EN_F419_SHIFT                              0
11724     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
11725     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_EN_UNUSED_0_SHIFT                          1
11726 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_VAL                                            0x0018c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11727     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_VAL_F420                                   (0x1f<<0) // Override value for afe_rxdfe_eye_tap1 AFE input.
11728     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_VAL_F420_SHIFT                             0
11729     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_VAL_UNUSED_0                               (0x7<<5) // reserved
11730     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_TAP1_OVR_VAL_UNUSED_0_SHIFT                         5
11731 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_EN                                        0x0018ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11732     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_EN_F421                               (0x1<<0) // Override enable for afe_rxdfe_eye_vscan_lsb AFE ovr_signal.
11733     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_EN_F421_SHIFT                         0
11734     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
11735     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_EN_UNUSED_0_SHIFT                     1
11736 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_VAL                                       0x0018d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11737     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_VAL_F422                              (0x1f<<0) // Override value for afe_rxdfe_eye_vscan_lsb AFE input.
11738     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_VAL_F422_SHIFT                        0
11739     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_VAL_UNUSED_0                          (0x7<<5) // reserved
11740     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_LSB_OVR_VAL_UNUSED_0_SHIFT                    5
11741 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_EN                                        0x0018d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11742     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_EN_F423                               (0x1<<0) // Override enable for afe_rxdfe_eye_vscan_msb AFE ovr_signal.
11743     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_EN_F423_SHIFT                         0
11744     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
11745     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_EN_UNUSED_0_SHIFT                     1
11746 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_VAL                                       0x0018d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11747     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_VAL_F424                              (0x7<<0) // Override value for afe_rxdfe_eye_vscan_msb AFE input.
11748     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_VAL_F424_SHIFT                        0
11749     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_VAL_UNUSED_0                          (0x1f<<3) // reserved
11750     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYE_VSCAN_MSB_OVR_VAL_UNUSED_0_SHIFT                    3
11751 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN                                 0x0018dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11752     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_F425                        (0x1<<0) // Override enable for afe_rxdfe_eyeslicereven_offset AFE ovr_signal.
11753     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_F425_SHIFT                  0
11754     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_UNUSED_0                    (0x7f<<1) // reserved
11755     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT              1
11756 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL                                0x0018e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11757     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_F426                       (0x3f<<0) // Override value for afe_rxdfe_eyeslicereven_offset AFE input.
11758     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_F426_SHIFT                 0
11759     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0                   (0x3<<6) // reserved
11760     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT             6
11761 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_EN                                  0x0018e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11762     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_EN_F427                         (0x1<<0) // Override enable for afe_rxdfe_eyeslicerodd_offset AFE ovr_signal.
11763     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_EN_F427_SHIFT                   0
11764     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_EN_UNUSED_0                     (0x7f<<1) // reserved
11765     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_EN_UNUSED_0_SHIFT               1
11766 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_VAL                                 0x0018e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11767     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_F428                        (0x3f<<0) // Override value for afe_rxdfe_eyeslicerodd_offset AFE input.
11768     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_F428_SHIFT                  0
11769     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_UNUSED_0                    (0x3<<6) // reserved
11770     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT              6
11771 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_EN                                            0x0018ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11772     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_EN_F429                                   (0x1<<0) // Override enable for afe_rxdfe_odd0_tap1 AFE ovr_signal.
11773     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_EN_F429_SHIFT                             0
11774     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11775     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_EN_UNUSED_0_SHIFT                         1
11776 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_VAL                                           0x0018f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11777     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_VAL_F430                                  (0x1f<<0) // Override value for afe_rxdfe_odd0_tap1 AFE input.
11778     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_VAL_F430_SHIFT                            0
11779     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
11780     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD0_TAP1_OVR_VAL_UNUSED_0_SHIFT                        5
11781 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_EN                                            0x0018f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11782     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_EN_F431                                   (0x1<<0) // Override enable for afe_rxdfe_odd1_tap1 AFE ovr_signal.
11783     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_EN_F431_SHIFT                             0
11784     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11785     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_EN_UNUSED_0_SHIFT                         1
11786 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_VAL                                           0x0018f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11787     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_VAL_F432                                  (0x1f<<0) // Override value for afe_rxdfe_odd1_tap1 AFE input.
11788     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_VAL_F432_SHIFT                            0
11789     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
11790     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_ODD1_TAP1_OVR_VAL_UNUSED_0_SHIFT                        5
11791 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_EN                                       0x0018fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11792     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_EN_F433                              (0x1<<0) // Override enable for afe_rxdfe_sumeven_offset AFE ovr_signal.
11793     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_EN_F433_SHIFT                        0
11794     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
11795     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT                    1
11796 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_VAL                                      0x001900UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11797     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_VAL_F434                             (0x3f<<0) // Override value for afe_rxdfe_sumeven_offset AFE input.
11798     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_VAL_F434_SHIFT                       0
11799     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_VAL_UNUSED_0                         (0x3<<6) // reserved
11800     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMEVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT                   6
11801 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_EN                                        0x001904UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11802     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_EN_F435                               (0x1<<0) // Override enable for afe_rxdfe_sumodd_offset AFE ovr_signal.
11803     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_EN_F435_SHIFT                         0
11804     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
11805     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_EN_UNUSED_0_SHIFT                     1
11806 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_VAL                                       0x001908UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11807     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_VAL_F436                              (0x3f<<0) // Override value for afe_rxdfe_sumodd_offset AFE input.
11808     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_VAL_F436_SHIFT                        0
11809     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_VAL_UNUSED_0                          (0x3<<6) // reserved
11810     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_SUMODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT                    6
11811 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_EN                                                 0x00190cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11812     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_EN_F437                                        (0x1<<0) // Override enable for afe_rxdfe_tap2 AFE ovr_signal.
11813     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_EN_F437_SHIFT                                  0
11814     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11815     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_EN_UNUSED_0_SHIFT                              1
11816 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_VAL                                                0x001910UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11817     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_VAL_F438                                       (0xf<<0) // Override value for afe_rxdfe_tap2 AFE input.
11818     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_VAL_F438_SHIFT                                 0
11819     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_VAL_UNUSED_0                                   (0xf<<4) // reserved
11820     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP2_OVR_VAL_UNUSED_0_SHIFT                             4
11821 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_EN                                                 0x001914UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11822     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_EN_F439                                        (0x1<<0) // Override enable for afe_rxdfe_tap3 AFE ovr_signal.
11823     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_EN_F439_SHIFT                                  0
11824     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11825     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_EN_UNUSED_0_SHIFT                              1
11826 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_VAL                                                0x001918UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11827     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_VAL_F440                                       (0x7<<0) // Override value for afe_rxdfe_tap3 AFE input.
11828     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_VAL_F440_SHIFT                                 0
11829     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
11830     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP3_OVR_VAL_UNUSED_0_SHIFT                             3
11831 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_EN                                                 0x00191cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11832     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_EN_F441                                        (0x1<<0) // Override enable for afe_rxdfe_tap4 AFE ovr_signal.
11833     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_EN_F441_SHIFT                                  0
11834     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11835     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_EN_UNUSED_0_SHIFT                              1
11836 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_VAL                                                0x001920UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11837     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_VAL_F442                                       (0x7<<0) // Override value for afe_rxdfe_tap4 AFE input.
11838     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_VAL_F442_SHIFT                                 0
11839     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
11840     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP4_OVR_VAL_UNUSED_0_SHIFT                             3
11841 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_EN                                                 0x001924UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11842     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_EN_F443                                        (0x1<<0) // Override enable for afe_rxdfe_tap5 AFE ovr_signal.
11843     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_EN_F443_SHIFT                                  0
11844     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
11845     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_EN_UNUSED_0_SHIFT                              1
11846 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_VAL                                                0x001928UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11847     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_VAL_F444                                       (0x7<<0) // Override value for afe_rxdfe_tap5 AFE input.
11848     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_VAL_F444_SHIFT                                 0
11849     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
11850     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_TAP5_OVR_VAL_UNUSED_0_SHIFT                             3
11851 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_EN                                     0x00192cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11852     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_EN_F445                            (0x1<<0) // Override enable for afe_rxdfe_vscaneven_offset AFE ovr_signal.
11853     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_EN_F445_SHIFT                      0
11854     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_EN_UNUSED_0                        (0x7f<<1) // reserved
11855     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT                  1
11856 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_VAL                                    0x001930UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11857     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_F446                           (0x3f<<0) // Override value for afe_rxdfe_vscaneven_offset AFE input.
11858     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_F446_SHIFT                     0
11859     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_UNUSED_0                       (0x3<<6) // reserved
11860     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT                 6
11861 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_EN                                      0x001934UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11862     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_EN_F447                             (0x1<<0) // Override enable for afe_rxdfe_vscanodd_offset AFE ovr_signal.
11863     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_EN_F447_SHIFT                       0
11864     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_EN_UNUSED_0                         (0x7f<<1) // reserved
11865     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_EN_UNUSED_0_SHIFT                   1
11866 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_VAL                                     0x001938UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11867     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_VAL_F448                            (0x3f<<0) // Override value for afe_rxdfe_vscanodd_offset AFE input.
11868     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_VAL_F448_SHIFT                      0
11869     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_VAL_UNUSED_0                        (0x3<<6) // reserved
11870     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDFE_VSCANODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT                  6
11871 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_EN                                            0x00193cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11872     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_EN_F449                                   (0x1<<0) // Override enable for afe_rxdp_data_width AFE ovr_signal.
11873     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_EN_F449_SHIFT                             0
11874     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11875     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_EN_UNUSED_0_SHIFT                         1
11876 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_VAL                                           0x001940UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11877     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_VAL_F450                                  (0x1<<0) // Override value for afe_rxdp_data_width AFE input.
11878     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_VAL_F450_SHIFT                            0
11879     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
11880     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXDP_DATA_WIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
11881 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_EN                                           0x001944UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11882     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_EN_F451                                  (0x1<<0) // Override enable for afe_rxleq_eq_biasres AFE ovr_signal.
11883     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_EN_F451_SHIFT                            0
11884     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11885     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_EN_UNUSED_0_SHIFT                        1
11886 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_VAL                                          0x001948UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11887     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_VAL_F452                                 (0x7<<0) // Override value for afe_rxleq_eq_biasres AFE input.
11888     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_VAL_F452_SHIFT                           0
11889     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
11890     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_BIASRES_OVR_VAL_UNUSED_0_SHIFT                       3
11891 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_EN                                               0x00194cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11892     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_EN_F453                                      (0x1<<0) // Override enable for afe_rxleq_eq_hfg AFE ovr_signal.
11893     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_EN_F453_SHIFT                                0
11894     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11895     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_EN_UNUSED_0_SHIFT                            1
11896 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_VAL                                              0x001950UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11897     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_VAL_F454                                     (0x1f<<0) // Override value for afe_rxleq_eq_hfg AFE input.
11898     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_VAL_F454_SHIFT                               0
11899     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_VAL_UNUSED_0                                 (0x7<<5) // reserved
11900     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_HFG_OVR_VAL_UNUSED_0_SHIFT                           5
11901 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_EN                                               0x001954UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11902     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_EN_F455                                      (0x1<<0) // Override enable for afe_rxleq_eq_lfg AFE ovr_signal.
11903     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_EN_F455_SHIFT                                0
11904     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11905     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_EN_UNUSED_0_SHIFT                            1
11906 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_VAL                                              0x001958UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11907     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_VAL_F456                                     (0x1f<<0) // Override value for afe_rxleq_eq_lfg AFE input.
11908     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_VAL_F456_SHIFT                               0
11909     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_VAL_UNUSED_0                                 (0x7<<5) // reserved
11910     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LFG_OVR_VAL_UNUSED_0_SHIFT                           5
11911 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_EN                                           0x00195cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11912     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_EN_F457                                  (0x1<<0) // Override enable for afe_rxleq_eq_loadres AFE ovr_signal.
11913     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_EN_F457_SHIFT                            0
11914     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11915     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_EN_UNUSED_0_SHIFT                        1
11916 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_VAL                                          0x001960UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11917     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_VAL_F458                                 (0x7<<0) // Override value for afe_rxleq_eq_loadres AFE input.
11918     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_VAL_F458_SHIFT                           0
11919     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
11920     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_LOADRES_OVR_VAL_UNUSED_0_SHIFT                       3
11921 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_EN                                               0x001964UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11922     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_EN_F459                                      (0x1<<0) // Override enable for afe_rxleq_eq_mbf AFE ovr_signal.
11923     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_EN_F459_SHIFT                                0
11924     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11925     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_EN_UNUSED_0_SHIFT                            1
11926 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_VAL                                              0x001968UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11927     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_VAL_F460                                     (0xf<<0) // Override value for afe_rxleq_eq_mbf AFE input.
11928     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_VAL_F460_SHIFT                               0
11929     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_VAL_UNUSED_0                                 (0xf<<4) // reserved
11930     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBF_OVR_VAL_UNUSED_0_SHIFT                           4
11931 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_EN                                               0x00196cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11932     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_EN_F461                                      (0x1<<0) // Override enable for afe_rxleq_eq_mbg AFE ovr_signal.
11933     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_EN_F461_SHIFT                                0
11934     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11935     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_EN_UNUSED_0_SHIFT                            1
11936 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_VAL                                              0x001970UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11937     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_VAL_F462                                     (0xf<<0) // Override value for afe_rxleq_eq_mbg AFE input.
11938     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_VAL_F462_SHIFT                               0
11939     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_VAL_UNUSED_0                                 (0xf<<4) // reserved
11940     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_MBG_OVR_VAL_UNUSED_0_SHIFT                           4
11941 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_EN                                               0x001974UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11942     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_EN_F463                                      (0x1<<0) // Override enable for afe_rxleq_eq_sql AFE ovr_signal.
11943     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_EN_F463_SHIFT                                0
11944     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11945     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_EN_UNUSED_0_SHIFT                            1
11946 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_VAL                                              0x001978UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11947     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_VAL_F464                                     (0x7<<0) // Override value for afe_rxleq_eq_sql AFE input.
11948     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_VAL_F464_SHIFT                               0
11949     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_VAL_UNUSED_0                                 (0x1f<<3) // reserved
11950     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_EQ_SQL_OVR_VAL_UNUSED_0_SHIFT                           3
11951 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_EN                                               0x00197cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11952     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_EN_F465                                      (0x1<<0) // Override enable for afe_rxleq_gn_apg AFE ovr_signal.
11953     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_EN_F465_SHIFT                                0
11954     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
11955     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_EN_UNUSED_0_SHIFT                            1
11956 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_VAL                                              0x001980UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11957     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_VAL_F466                                     (0x3<<0) // Override value for afe_rxleq_gn_apg AFE input.
11958     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_VAL_F466_SHIFT                               0
11959     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_VAL_UNUSED_0                                 (0x3f<<2) // reserved
11960     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_APG_OVR_VAL_UNUSED_0_SHIFT                           2
11961 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_EN                                             0x001984UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11962     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_EN_F467                                    (0x1<<0) // Override enable for afe_rxleq_gn_biasi AFE ovr_signal.
11963     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_EN_F467_SHIFT                              0
11964     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
11965     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_EN_UNUSED_0_SHIFT                          1
11966 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_VAL                                            0x001988UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11967     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_VAL_F468                                   (0x3<<0) // Override value for afe_rxleq_gn_biasi AFE input.
11968     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_VAL_F468_SHIFT                             0
11969     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_VAL_UNUSED_0                               (0x3f<<2) // reserved
11970     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_BIASI_OVR_VAL_UNUSED_0_SHIFT                         2
11971 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_EN                                           0x00198cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11972     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_EN_F469                                  (0x1<<0) // Override enable for afe_rxleq_gn_loadres AFE ovr_signal.
11973     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_EN_F469_SHIFT                            0
11974     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
11975     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_EN_UNUSED_0_SHIFT                        1
11976 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_VAL                                          0x001990UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11977     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_VAL_F470                                 (0x7<<0) // Override value for afe_rxleq_gn_loadres AFE input.
11978     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_VAL_F470_SHIFT                           0
11979     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
11980     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_GN_LOADRES_OVR_VAL_UNUSED_0_SHIFT                       3
11981 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_EN                                            0x001994UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11982     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_EN_F471                                   (0x1<<0) // Override enable for afe_rxleq_offset_e1 AFE ovr_signal.
11983     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_EN_F471_SHIFT                             0
11984     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11985     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_EN_UNUSED_0_SHIFT                         1
11986 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_VAL                                           0x001998UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11987     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_VAL_F472                                  (0x3f<<0) // Override value for afe_rxleq_offset_e1 AFE input.
11988     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_VAL_F472_SHIFT                            0
11989     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
11990     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E1_OVR_VAL_UNUSED_0_SHIFT                        6
11991 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_EN                                            0x00199cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11992     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_EN_F473                                   (0x1<<0) // Override enable for afe_rxleq_offset_e2 AFE ovr_signal.
11993     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_EN_F473_SHIFT                             0
11994     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
11995     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_EN_UNUSED_0_SHIFT                         1
11996 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_VAL                                           0x0019a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
11997     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_VAL_F474                                  (0x3f<<0) // Override value for afe_rxleq_offset_e2 AFE input.
11998     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_VAL_F474_SHIFT                            0
11999     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12000     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E2_OVR_VAL_UNUSED_0_SHIFT                        6
12001 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_EN                                            0x0019a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12002     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_EN_F475                                   (0x1<<0) // Override enable for afe_rxleq_offset_e3 AFE ovr_signal.
12003     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_EN_F475_SHIFT                             0
12004     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12005     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_EN_UNUSED_0_SHIFT                         1
12006 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_VAL                                           0x0019a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12007     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_VAL_F476                                  (0x3f<<0) // Override value for afe_rxleq_offset_e3 AFE input.
12008     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_VAL_F476_SHIFT                            0
12009     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12010     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E3_OVR_VAL_UNUSED_0_SHIFT                        6
12011 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_EN                                            0x0019acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12012     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_EN_F477                                   (0x1<<0) // Override enable for afe_rxleq_offset_e4 AFE ovr_signal.
12013     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_EN_F477_SHIFT                             0
12014     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12015     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_EN_UNUSED_0_SHIFT                         1
12016 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_VAL                                           0x0019b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12017     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_VAL_F478                                  (0x3f<<0) // Override value for afe_rxleq_offset_e4 AFE input.
12018     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_VAL_F478_SHIFT                            0
12019     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12020     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E4_OVR_VAL_UNUSED_0_SHIFT                        6
12021 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_EN                                            0x0019b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12022     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_EN_F479                                   (0x1<<0) // Override enable for afe_rxleq_offset_e5 AFE ovr_signal.
12023     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_EN_F479_SHIFT                             0
12024     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12025     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_EN_UNUSED_0_SHIFT                         1
12026 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_VAL                                           0x0019b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12027     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_VAL_F480                                  (0x3f<<0) // Override value for afe_rxleq_offset_e5 AFE input.
12028     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_VAL_F480_SHIFT                            0
12029     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12030     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E5_OVR_VAL_UNUSED_0_SHIFT                        6
12031 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_EN                                            0x0019bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12032     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_EN_F481                                   (0x1<<0) // Override enable for afe_rxleq_offset_e6 AFE ovr_signal.
12033     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_EN_F481_SHIFT                             0
12034     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12035     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_EN_UNUSED_0_SHIFT                         1
12036 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_VAL                                           0x0019c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12037     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_VAL_F482                                  (0x3f<<0) // Override value for afe_rxleq_offset_e6 AFE input.
12038     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_VAL_F482_SHIFT                            0
12039     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12040     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_E6_OVR_VAL_UNUSED_0_SHIFT                        6
12041 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_EN                                            0x0019c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12042     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_EN_F483                                   (0x1<<0) // Override enable for afe_rxleq_offset_g1 AFE ovr_signal.
12043     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_EN_F483_SHIFT                             0
12044     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12045     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_EN_UNUSED_0_SHIFT                         1
12046 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_VAL                                           0x0019c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12047     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_VAL_F484                                  (0x3f<<0) // Override value for afe_rxleq_offset_g1 AFE input.
12048     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_VAL_F484_SHIFT                            0
12049     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12050     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_OFFSET_G1_OVR_VAL_UNUSED_0_SHIFT                        6
12051 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_EN                                              0x0019ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12052     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_EN_F485                                     (0x1<<0) // Override enable for afe_rxleq_ple_att AFE ovr_signal.
12053     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_EN_F485_SHIFT                               0
12054     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
12055     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_EN_UNUSED_0_SHIFT                           1
12056 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_VAL                                             0x0019d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12057     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_VAL_F486                                    (0x7<<0) // Override value for afe_rxleq_ple_att AFE input.
12058     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_VAL_F486_SHIFT                              0
12059     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_VAL_UNUSED_0                                (0x1f<<3) // reserved
12060     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLEQ_PLE_ATT_OVR_VAL_UNUSED_0_SHIFT                          3
12061 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_EN                                                  0x0019d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12062     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_EN_F487                                         (0x1<<0) // Override enable for afe_rxlos_agc AFE ovr_signal.
12063     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_EN_F487_SHIFT                                   0
12064     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_EN_UNUSED_0                                     (0x7f<<1) // reserved
12065     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_EN_UNUSED_0_SHIFT                               1
12066 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_VAL                                                 0x0019d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12067     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_VAL_F488                                        (0x1<<0) // Override value for afe_rxlos_agc AFE input.
12068     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_VAL_F488_SHIFT                                  0
12069     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_VAL_UNUSED_0                                    (0x7f<<1) // reserved
12070     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_OVR_VAL_UNUSED_0_SHIFT                              1
12071 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_EN                                              0x0019dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12072     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_EN_F489                                     (0x1<<0) // Override enable for afe_rxlos_agc_set AFE ovr_signal.
12073     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_EN_F489_SHIFT                               0
12074     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
12075     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_EN_UNUSED_0_SHIFT                           1
12076 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_VAL                                             0x0019e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12077     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_VAL_F490                                    (0x1<<0) // Override value for afe_rxlos_agc_set AFE input.
12078     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_VAL_F490_SHIFT                              0
12079     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_VAL_UNUSED_0                                (0x7f<<1) // reserved
12080     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_AGC_SET_OVR_VAL_UNUSED_0_SHIFT                          1
12081 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_EN                                            0x0019e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12082     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_EN_F491                                   (0x1<<0) // Override enable for afe_rxlos_bandwidth AFE ovr_signal.
12083     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_EN_F491_SHIFT                             0
12084     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12085     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_EN_UNUSED_0_SHIFT                         1
12086 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_VAL                                           0x0019e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12087     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_VAL_F492                                  (0x1<<0) // Override value for afe_rxlos_bandwidth AFE input.
12088     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_VAL_F492_SHIFT                            0
12089     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
12090     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_BANDWIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
12091 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_EN                                             0x0019ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12092     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_EN_F493                                    (0x1<<0) // Override enable for afe_rxlos_comp_sel AFE ovr_signal.
12093     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_EN_F493_SHIFT                              0
12094     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
12095     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_EN_UNUSED_0_SHIFT                          1
12096 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_VAL                                            0x0019f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12097     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_VAL_F494                                   (0x1<<0) // Override value for afe_rxlos_comp_sel AFE input.
12098     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_VAL_F494_SHIFT                             0
12099     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_VAL_UNUSED_0                               (0x7f<<1) // reserved
12100     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_COMP_SEL_OVR_VAL_UNUSED_0_SHIFT                         1
12101 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_EN                                           0x0019f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12102     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_EN_F495                                  (0x1<<0) // Override enable for afe_rxlos_envdet_byp AFE ovr_signal.
12103     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_EN_F495_SHIFT                            0
12104     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12105     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_EN_UNUSED_0_SHIFT                        1
12106 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_VAL                                          0x0019f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12107     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_VAL_F496                                 (0x1<<0) // Override value for afe_rxlos_envdet_byp AFE input.
12108     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_VAL_F496_SHIFT                           0
12109     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_VAL_UNUSED_0                             (0x7f<<1) // reserved
12110     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_ENVDET_BYP_OVR_VAL_UNUSED_0_SHIFT                       1
12111 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_EN                                                 0x0019fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12112     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_EN_F497                                        (0x1<<0) // Override enable for afe_rxlos_gain AFE ovr_signal.
12113     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_EN_F497_SHIFT                                  0
12114     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
12115     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_EN_UNUSED_0_SHIFT                              1
12116 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_VAL                                                0x001a00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12117     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_VAL_F498                                       (0x1<<0) // Override value for afe_rxlos_gain AFE input.
12118     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_VAL_F498_SHIFT                                 0
12119     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_VAL_UNUSED_0                                   (0x7f<<1) // reserved
12120     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_GAIN_OVR_VAL_UNUSED_0_SHIFT                             1
12121 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_EN                                           0x001a04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12122     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_EN_F499                                  (0x1<<0) // Override enable for afe_rxlos_hysteresis AFE ovr_signal.
12123     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_EN_F499_SHIFT                            0
12124     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12125     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_EN_UNUSED_0_SHIFT                        1
12126 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_VAL                                          0x001a08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12127     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_VAL_F500                                 (0x7<<0) // Override value for afe_rxlos_hysteresis AFE input.
12128     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_VAL_F500_SHIFT                           0
12129     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
12130     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_HYSTERESIS_OVR_VAL_UNUSED_0_SHIFT                       3
12131 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_EN                                               0x001a0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12132     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_EN_F501                                      (0x1<<0) // Override enable for afe_rxlos_offset AFE ovr_signal.
12133     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_EN_F501_SHIFT                                0
12134     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12135     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_EN_UNUSED_0_SHIFT                            1
12136 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_VAL                                              0x001a10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12137     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_VAL_F502                                     (0x3f<<0) // Override value for afe_rxlos_offset AFE input.
12138     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_VAL_F502_SHIFT                               0
12139     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_VAL_UNUSED_0                                 (0x3<<6) // reserved
12140     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_OFFSET_OVR_VAL_UNUSED_0_SHIFT                           6
12141 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_EN                                                  0x001a14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12142     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_EN_F503                                         (0x1<<0) // Override enable for afe_rxlos_raw AFE ovr_signal.
12143     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_EN_F503_SHIFT                                   0
12144     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_EN_UNUSED_0                                     (0x7f<<1) // reserved
12145     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_EN_UNUSED_0_SHIFT                               1
12146 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_VAL                                                 0x001a18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12147     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_VAL_F504                                        (0x1<<0) // Override value for afe_rxlos_raw AFE input.
12148     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_VAL_F504_SHIFT                                  0
12149     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_VAL_UNUSED_0                                    (0x7f<<1) // reserved
12150     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_RAW_OVR_VAL_UNUSED_0_SHIFT                              1
12151 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_EN                                                0x001a1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12152     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_EN_F505                                       (0x1<<0) // Override enable for afe_rxlos_spare AFE ovr_signal.
12153     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_EN_F505_SHIFT                                 0
12154     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
12155     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_EN_UNUSED_0_SHIFT                             1
12156 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_VAL                                               0x001a20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12157     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_VAL_F506                                      (0xf<<0) // Override value for afe_rxlos_spare AFE input.
12158     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_VAL_F506_SHIFT                                0
12159     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_VAL_UNUSED_0                                  (0xf<<4) // reserved
12160     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_SPARE_OVR_VAL_UNUSED_0_SHIFT                            4
12161 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_EN                                            0x001a24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12162     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_EN_F507                                   (0x1<<0) // Override enable for afe_rxlos_threshold AFE ovr_signal.
12163     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_EN_F507_SHIFT                             0
12164     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12165     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_EN_UNUSED_0_SHIFT                         1
12166 #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_VAL                                           0x001a28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12167     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_VAL_F508                                  (0xf<<0) // Override value for afe_rxlos_threshold AFE input.
12168     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_VAL_F508_SHIFT                            0
12169     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_VAL_UNUSED_0                              (0xf<<4) // reserved
12170     #define PHY_NW_IP_REG_PHY0_OVR_LN2_RXLOS_THRESHOLD_OVR_VAL_UNUSED_0_SHIFT                        4
12171 #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_EN                                              0x001a2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12172     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_EN_F509                                     (0x1<<0) // Override enable for afe_txcp_dcd_trim AFE ovr_signal.
12173     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_EN_F509_SHIFT                               0
12174     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
12175     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_EN_UNUSED_0_SHIFT                           1
12176 #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_VAL                                             0x001a30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12177     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_VAL_F510                                    (0x3f<<0) // Override value for afe_txcp_dcd_trim AFE input.
12178     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_VAL_F510_SHIFT                              0
12179     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_VAL_UNUSED_0                                (0x3<<6) // reserved
12180     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXCP_DCD_TRIM_OVR_VAL_UNUSED_0_SHIFT                          6
12181 #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_EN                                               0x001a34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12182     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_EN_F511                                      (0x1<<0) // Override enable for afe_txdp_cal_out AFE ovr_signal.
12183     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_EN_F511_SHIFT                                0
12184     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12185     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_EN_UNUSED_0_SHIFT                            1
12186 #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_VAL                                              0x001a38UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12187     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_VAL_F512                                     (0x1<<0) // Override value for afe_txdp_cal_out AFE input.
12188     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_VAL_F512_SHIFT                               0
12189     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_VAL_UNUSED_0                                 (0x7f<<1) // reserved
12190     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CAL_OUT_OVR_VAL_UNUSED_0_SHIFT                           1
12191 #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_EN                                                0x001a3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12192     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_EN_F513                                       (0x1<<0) // Override enable for afe_txdp_clkdly AFE ovr_signal.
12193     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_EN_F513_SHIFT                                 0
12194     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
12195     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_EN_UNUSED_0_SHIFT                             1
12196 #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_VAL                                               0x001a40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12197     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_VAL_F514                                      (0xf<<0) // Override value for afe_txdp_clkdly AFE input.
12198     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_VAL_F514_SHIFT                                0
12199     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_VAL_UNUSED_0                                  (0xf<<4) // reserved
12200     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_CLKDLY_OVR_VAL_UNUSED_0_SHIFT                            4
12201 #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_EN                                            0x001a44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12202     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_EN_F515                                   (0x1<<0) // Override enable for afe_txdp_data_width AFE ovr_signal.
12203     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_EN_F515_SHIFT                             0
12204     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12205     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_EN_UNUSED_0_SHIFT                         1
12206 #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_VAL                                           0x001a48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12207     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_VAL_F516                                  (0x1<<0) // Override value for afe_txdp_data_width AFE input.
12208     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_VAL_F516_SHIFT                            0
12209     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
12210     #define PHY_NW_IP_REG_PHY0_OVR_LN2_TXDP_DATA_WIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
12211 #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_EN                                                0x001c00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12212     #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_EN_F517                                       (0x1<<0) // Override enable for afe_calcomp_out AFE ovr_signal.
12213     #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_EN_F517_SHIFT                                 0
12214     #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
12215     #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_EN_UNUSED_0_SHIFT                             1
12216 #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_VAL                                               0x001c04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12217     #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_VAL_F518                                      (0x1<<0) // Override value for afe_calcomp_out AFE input.
12218     #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_VAL_F518_SHIFT                                0
12219     #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_VAL_UNUSED_0                                  (0x7f<<1) // reserved
12220     #define PHY_NW_IP_REG_PHY0_OVR_LN3_CALCOMP_OUT_OVR_VAL_UNUSED_0_SHIFT                            1
12221 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_EN                                                 0x001c08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12222     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_EN_F519                                        (0x1<<0) // Override enable for afe_rxcdr_dlpf AFE ovr_signal.
12223     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_EN_F519_SHIFT                                  0
12224     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
12225     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_EN_UNUSED_0_SHIFT                              1
12226 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_VAL_7_0                                            0x001c0cUL //Access:RW   DataWidth:0x8   Override value for afe_rxcdr_dlpf AFE input.  Chips: K2
12227 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_VAL_8_8                                            0x001c10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12228     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_VAL_8_8_F521                                   (0x1<<0) // Override value for afe_rxcdr_dlpf AFE input.
12229     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_VAL_8_8_F521_SHIFT                             0
12230     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_VAL_8_8_UNUSED_0                               (0x7f<<1) // reserved
12231     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_DLPF_OVR_VAL_8_8_UNUSED_0_SHIFT                         1
12232 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_EN                                       0x001c14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12233     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_EN_F522                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clki_lsb AFE ovr_signal.
12234     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_EN_F522_SHIFT                        0
12235     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
12236     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_EN_UNUSED_0_SHIFT                    1
12237 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_VAL                                      0x001c18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12238     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_F523                             (0x3<<0) // Override value for afe_rxcdr_hscan_clki_lsb AFE input.
12239     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_F523_SHIFT                       0
12240     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_UNUSED_0                         (0x3f<<2) // reserved
12241     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_LSB_OVR_VAL_UNUSED_0_SHIFT                   2
12242 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_EN                                       0x001c1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12243     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_EN_F524                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clki_msb AFE ovr_signal.
12244     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_EN_F524_SHIFT                        0
12245     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
12246     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_EN_UNUSED_0_SHIFT                    1
12247 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_VAL                                      0x001c20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12248     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_F525                             (0x1f<<0) // Override value for afe_rxcdr_hscan_clki_msb AFE input.
12249     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_F525_SHIFT                       0
12250     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_UNUSED_0                         (0x7<<5) // reserved
12251     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKI_MSB_OVR_VAL_UNUSED_0_SHIFT                   5
12252 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_EN                                       0x001c24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12253     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_F526                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clkq_lsb AFE ovr_signal.
12254     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_F526_SHIFT                        0
12255     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
12256     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_EN_UNUSED_0_SHIFT                    1
12257 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL                                      0x001c28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12258     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_F527                             (0x3<<0) // Override value for afe_rxcdr_hscan_clkq_lsb AFE input.
12259     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_F527_SHIFT                       0
12260     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_UNUSED_0                         (0x3f<<2) // reserved
12261     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_LSB_OVR_VAL_UNUSED_0_SHIFT                   2
12262 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_EN                                       0x001c2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12263     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_F528                              (0x1<<0) // Override enable for afe_rxcdr_hscan_clkq_msb AFE ovr_signal.
12264     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_F528_SHIFT                        0
12265     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
12266     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_EN_UNUSED_0_SHIFT                    1
12267 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL                                      0x001c30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12268     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_F529                             (0x1f<<0) // Override value for afe_rxcdr_hscan_clkq_msb AFE input.
12269     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_F529_SHIFT                       0
12270     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_UNUSED_0                         (0x7<<5) // reserved
12271     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_CLKQ_MSB_OVR_VAL_UNUSED_0_SHIFT                   5
12272 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN                                   0x001c34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12273     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_F530                          (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_lsb_fine AFE ovr_signal.
12274     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_F530_SHIFT                    0
12275     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_UNUSED_0                      (0x7f<<1) // reserved
12276     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_EN_UNUSED_0_SHIFT                1
12277 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL                                  0x001c38UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12278     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_F531                         (0x1<<0) // Override value for afe_rxcdr_hscan_eye_lsb_fine AFE input.
12279     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_F531_SHIFT                   0
12280     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_UNUSED_0                     (0x7f<<1) // reserved
12281     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_FINE_OVR_VAL_UNUSED_0_SHIFT               1
12282 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_EN                                        0x001c3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12283     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_EN_F532                               (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_lsb AFE ovr_signal.
12284     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_EN_F532_SHIFT                         0
12285     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
12286     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_EN_UNUSED_0_SHIFT                     1
12287 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_VAL                                       0x001c40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12288     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_VAL_F533                              (0xf<<0) // Override value for afe_rxcdr_hscan_eye_lsb AFE input.
12289     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_VAL_F533_SHIFT                        0
12290     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_VAL_UNUSED_0                          (0xf<<4) // reserved
12291     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_LSB_OVR_VAL_UNUSED_0_SHIFT                    4
12292 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_EN                                        0x001c44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12293     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_EN_F534                               (0x1<<0) // Override enable for afe_rxcdr_hscan_eye_msb AFE ovr_signal.
12294     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_EN_F534_SHIFT                         0
12295     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
12296     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_EN_UNUSED_0_SHIFT                     1
12297 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_VAL                                       0x001c48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12298     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_VAL_F535                              (0x3<<0) // Override value for afe_rxcdr_hscan_eye_msb AFE input.
12299     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_VAL_F535_SHIFT                        0
12300     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_VAL_UNUSED_0                          (0x3f<<2) // reserved
12301     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_HSCAN_EYE_MSB_OVR_VAL_UNUSED_0_SHIFT                    2
12302 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_EN                                            0x001c4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12303     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_EN_F536                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_en AFE ovr_signal.
12304     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_EN_F536_SHIFT                             0
12305     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12306     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_EN_UNUSED_0_SHIFT                         1
12307 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_VAL                                           0x001c50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12308     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_VAL_F537                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_en AFE input.
12309     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_VAL_F537_SHIFT                            0
12310     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
12311     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_EN_OVR_VAL_UNUSED_0_SHIFT                        1
12312 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_EN                                            0x001c54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12313     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_EN_F538                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_go AFE ovr_signal.
12314     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_EN_F538_SHIFT                             0
12315     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12316     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_EN_UNUSED_0_SHIFT                         1
12317 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_VAL                                           0x001c58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12318     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_VAL_F539                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_go AFE input.
12319     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_VAL_F539_SHIFT                            0
12320     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
12321     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_GO_OVR_VAL_UNUSED_0_SHIFT                        1
12322 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_EN                                          0x001c5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12323     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_EN_F540                                 (0x1<<0) // Override enable for afe_rxcdr_vcocal_load AFE ovr_signal.
12324     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_EN_F540_SHIFT                           0
12325     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_EN_UNUSED_0                             (0x7f<<1) // reserved
12326     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_EN_UNUSED_0_SHIFT                       1
12327 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_VAL                                         0x001c60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12328     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_VAL_F541                                (0x1<<0) // Override value for afe_rxcdr_vcocal_load AFE input.
12329     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_VAL_F541_SHIFT                          0
12330     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_VAL_UNUSED_0                            (0x7f<<1) // reserved
12331     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_LOAD_OVR_VAL_UNUSED_0_SHIFT                      1
12332 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_EN                                            0x001c64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12333     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_EN_F542                                   (0x1<<0) // Override enable for afe_rxcdr_vcocal_up AFE ovr_signal.
12334     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_EN_F542_SHIFT                             0
12335     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12336     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_EN_UNUSED_0_SHIFT                         1
12337 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_VAL                                           0x001c68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12338     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_VAL_F543                                  (0x1<<0) // Override value for afe_rxcdr_vcocal_up AFE input.
12339     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_VAL_F543_SHIFT                            0
12340     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
12341     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOCAL_UP_OVR_VAL_UNUSED_0_SHIFT                        1
12342 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_EN                                                0x001c6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12343     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_EN_F544                                       (0x1<<0) // Override enable for afe_rxcdr_vcofr AFE ovr_signal.
12344     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_EN_F544_SHIFT                                 0
12345     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
12346     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_EN_UNUSED_0_SHIFT                             1
12347 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_VAL                                               0x001c70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12348     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_VAL_F545                                      (0x1f<<0) // Override value for afe_rxcdr_vcofr AFE input.
12349     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_VAL_F545_SHIFT                                0
12350     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_VAL_UNUSED_0                                  (0x7<<5) // reserved
12351     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXCDR_VCOFR_OVR_VAL_UNUSED_0_SHIFT                            5
12352 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_EN                                       0x001c74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12353     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_EN_F546                              (0x1<<0) // Override enable for afe_rxdfe_clkdiv_qsample AFE ovr_signal.
12354     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_EN_F546_SHIFT                        0
12355     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
12356     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                    1
12357 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_VAL                                      0x001c78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12358     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_F547                             (0x1<<0) // Override value for afe_rxdfe_clkdiv_qsample AFE input.
12359     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_F547_SHIFT                       0
12360     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0                         (0x7f<<1) // reserved
12361     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIV_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                   1
12362 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN                                    0x001c7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12363     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_F548                           (0x1<<0) // Override enable for afe_rxdfe_clkdiveye_qsample AFE ovr_signal.
12364     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_F548_SHIFT                     0
12365     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_UNUSED_0                       (0x7f<<1) // reserved
12366     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_EN_UNUSED_0_SHIFT                 1
12367 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL                                   0x001c80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12368     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_F549                          (0xf<<0) // Override value for afe_rxdfe_clkdiveye_qsample AFE input.
12369     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_F549_SHIFT                    0
12370     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_UNUSED_0                      (0xf<<4) // reserved
12371     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_CLKDIVEYE_QSAMPLE_OVR_VAL_UNUSED_0_SHIFT                4
12372 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN                               0x001c84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12373     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_F550                      (0x1<<0) // Override enable for afe_rxdfe_dataslicereven0_offset AFE ovr_signal.
12374     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_F550_SHIFT                0
12375     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_UNUSED_0                  (0x7f<<1) // reserved
12376     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_EN_UNUSED_0_SHIFT            1
12377 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL                              0x001c88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12378     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_F551                     (0x3f<<0) // Override value for afe_rxdfe_dataslicereven0_offset AFE input.
12379     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_F551_SHIFT               0
12380     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_UNUSED_0                 (0x3<<6) // reserved
12381     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN0_OFFSET_OVR_VAL_UNUSED_0_SHIFT           6
12382 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN                               0x001c8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12383     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_F552                      (0x1<<0) // Override enable for afe_rxdfe_dataslicereven1_offset AFE ovr_signal.
12384     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_F552_SHIFT                0
12385     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_UNUSED_0                  (0x7f<<1) // reserved
12386     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_EN_UNUSED_0_SHIFT            1
12387 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL                              0x001c90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12388     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_F553                     (0x3f<<0) // Override value for afe_rxdfe_dataslicereven1_offset AFE input.
12389     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_F553_SHIFT               0
12390     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_UNUSED_0                 (0x3<<6) // reserved
12391     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICEREVEN1_OFFSET_OVR_VAL_UNUSED_0_SHIFT           6
12392 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_EN                                0x001c94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12393     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_F554                       (0x1<<0) // Override enable for afe_rxdfe_dataslicerodd0_offset AFE ovr_signal.
12394     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_F554_SHIFT                 0
12395     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
12396     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
12397 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL                               0x001c98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12398     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_F555                      (0x3f<<0) // Override value for afe_rxdfe_dataslicerodd0_offset AFE input.
12399     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_F555_SHIFT                0
12400     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
12401     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD0_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
12402 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_EN                                0x001c9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12403     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_F556                       (0x1<<0) // Override enable for afe_rxdfe_dataslicerodd1_offset AFE ovr_signal.
12404     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_F556_SHIFT                 0
12405     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
12406     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
12407 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL                               0x001ca0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12408     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_F557                      (0x3f<<0) // Override value for afe_rxdfe_dataslicerodd1_offset AFE input.
12409     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_F557_SHIFT                0
12410     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
12411     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_DATASLICERODD1_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
12412 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN                                0x001ca4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12413     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_F558                       (0x1<<0) // Override enable for afe_rxdfe_edgeslicereven_offset AFE ovr_signal.
12414     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_F558_SHIFT                 0
12415     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_UNUSED_0                   (0x7f<<1) // reserved
12416     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT             1
12417 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL                               0x001ca8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12418     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_F559                      (0x3f<<0) // Override value for afe_rxdfe_edgeslicereven_offset AFE input.
12419     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_F559_SHIFT                0
12420     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0                  (0x3<<6) // reserved
12421     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT            6
12422 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_EN                                 0x001cacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12423     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_F560                        (0x1<<0) // Override enable for afe_rxdfe_edgeslicerodd_offset AFE ovr_signal.
12424     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_F560_SHIFT                  0
12425     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_UNUSED_0                    (0x7f<<1) // reserved
12426     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_EN_UNUSED_0_SHIFT              1
12427 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL                                0x001cb0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12428     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_F561                       (0x3f<<0) // Override value for afe_rxdfe_edgeslicerodd_offset AFE input.
12429     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_F561_SHIFT                 0
12430     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_UNUSED_0                   (0x3<<6) // reserved
12431     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EDGESLICERODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT             6
12432 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_EN                                           0x001cb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12433     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_EN_F562                                  (0x1<<0) // Override enable for afe_rxdfe_even0_tap1 AFE ovr_signal.
12434     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_EN_F562_SHIFT                            0
12435     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12436     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_EN_UNUSED_0_SHIFT                        1
12437 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_VAL                                          0x001cb8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12438     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_VAL_F563                                 (0x1f<<0) // Override value for afe_rxdfe_even0_tap1 AFE input.
12439     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_VAL_F563_SHIFT                           0
12440     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_VAL_UNUSED_0                             (0x7<<5) // reserved
12441     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN0_TAP1_OVR_VAL_UNUSED_0_SHIFT                       5
12442 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_EN                                           0x001cbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12443     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_EN_F564                                  (0x1<<0) // Override enable for afe_rxdfe_even1_tap1 AFE ovr_signal.
12444     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_EN_F564_SHIFT                            0
12445     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12446     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_EN_UNUSED_0_SHIFT                        1
12447 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_VAL                                          0x001cc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12448     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_VAL_F565                                 (0x1f<<0) // Override value for afe_rxdfe_even1_tap1 AFE input.
12449     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_VAL_F565_SHIFT                           0
12450     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_VAL_UNUSED_0                             (0x7<<5) // reserved
12451     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EVEN1_TAP1_OVR_VAL_UNUSED_0_SHIFT                       5
12452 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_EN                                             0x001cc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12453     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_EN_F566                                    (0x1<<0) // Override enable for afe_rxdfe_eye_tap1 AFE ovr_signal.
12454     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_EN_F566_SHIFT                              0
12455     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
12456     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_EN_UNUSED_0_SHIFT                          1
12457 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_VAL                                            0x001cc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12458     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_VAL_F567                                   (0x1f<<0) // Override value for afe_rxdfe_eye_tap1 AFE input.
12459     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_VAL_F567_SHIFT                             0
12460     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_VAL_UNUSED_0                               (0x7<<5) // reserved
12461     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_TAP1_OVR_VAL_UNUSED_0_SHIFT                         5
12462 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_EN                                        0x001cccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12463     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_EN_F568                               (0x1<<0) // Override enable for afe_rxdfe_eye_vscan_lsb AFE ovr_signal.
12464     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_EN_F568_SHIFT                         0
12465     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
12466     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_EN_UNUSED_0_SHIFT                     1
12467 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_VAL                                       0x001cd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12468     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_VAL_F569                              (0x1f<<0) // Override value for afe_rxdfe_eye_vscan_lsb AFE input.
12469     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_VAL_F569_SHIFT                        0
12470     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_VAL_UNUSED_0                          (0x7<<5) // reserved
12471     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_LSB_OVR_VAL_UNUSED_0_SHIFT                    5
12472 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_EN                                        0x001cd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12473     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_EN_F570                               (0x1<<0) // Override enable for afe_rxdfe_eye_vscan_msb AFE ovr_signal.
12474     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_EN_F570_SHIFT                         0
12475     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
12476     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_EN_UNUSED_0_SHIFT                     1
12477 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_VAL                                       0x001cd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12478     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_VAL_F571                              (0x7<<0) // Override value for afe_rxdfe_eye_vscan_msb AFE input.
12479     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_VAL_F571_SHIFT                        0
12480     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_VAL_UNUSED_0                          (0x1f<<3) // reserved
12481     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYE_VSCAN_MSB_OVR_VAL_UNUSED_0_SHIFT                    3
12482 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN                                 0x001cdcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12483     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_F572                        (0x1<<0) // Override enable for afe_rxdfe_eyeslicereven_offset AFE ovr_signal.
12484     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_F572_SHIFT                  0
12485     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_UNUSED_0                    (0x7f<<1) // reserved
12486     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT              1
12487 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL                                0x001ce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12488     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_F573                       (0x3f<<0) // Override value for afe_rxdfe_eyeslicereven_offset AFE input.
12489     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_F573_SHIFT                 0
12490     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0                   (0x3<<6) // reserved
12491     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICEREVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT             6
12492 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_EN                                  0x001ce4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12493     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_EN_F574                         (0x1<<0) // Override enable for afe_rxdfe_eyeslicerodd_offset AFE ovr_signal.
12494     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_EN_F574_SHIFT                   0
12495     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_EN_UNUSED_0                     (0x7f<<1) // reserved
12496     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_EN_UNUSED_0_SHIFT               1
12497 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_VAL                                 0x001ce8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12498     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_F575                        (0x3f<<0) // Override value for afe_rxdfe_eyeslicerodd_offset AFE input.
12499     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_F575_SHIFT                  0
12500     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_UNUSED_0                    (0x3<<6) // reserved
12501     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_EYESLICERODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT              6
12502 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_EN                                            0x001cecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12503     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_EN_F576                                   (0x1<<0) // Override enable for afe_rxdfe_odd0_tap1 AFE ovr_signal.
12504     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_EN_F576_SHIFT                             0
12505     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12506     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_EN_UNUSED_0_SHIFT                         1
12507 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_VAL                                           0x001cf0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12508     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_VAL_F577                                  (0x1f<<0) // Override value for afe_rxdfe_odd0_tap1 AFE input.
12509     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_VAL_F577_SHIFT                            0
12510     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
12511     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD0_TAP1_OVR_VAL_UNUSED_0_SHIFT                        5
12512 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_EN                                            0x001cf4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12513     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_EN_F578                                   (0x1<<0) // Override enable for afe_rxdfe_odd1_tap1 AFE ovr_signal.
12514     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_EN_F578_SHIFT                             0
12515     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12516     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_EN_UNUSED_0_SHIFT                         1
12517 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_VAL                                           0x001cf8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12518     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_VAL_F579                                  (0x1f<<0) // Override value for afe_rxdfe_odd1_tap1 AFE input.
12519     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_VAL_F579_SHIFT                            0
12520     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_VAL_UNUSED_0                              (0x7<<5) // reserved
12521     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_ODD1_TAP1_OVR_VAL_UNUSED_0_SHIFT                        5
12522 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_EN                                       0x001cfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12523     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_EN_F580                              (0x1<<0) // Override enable for afe_rxdfe_sumeven_offset AFE ovr_signal.
12524     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_EN_F580_SHIFT                        0
12525     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_EN_UNUSED_0                          (0x7f<<1) // reserved
12526     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT                    1
12527 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_VAL                                      0x001d00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12528     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_VAL_F581                             (0x3f<<0) // Override value for afe_rxdfe_sumeven_offset AFE input.
12529     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_VAL_F581_SHIFT                       0
12530     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_VAL_UNUSED_0                         (0x3<<6) // reserved
12531     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMEVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT                   6
12532 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_EN                                        0x001d04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12533     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_EN_F582                               (0x1<<0) // Override enable for afe_rxdfe_sumodd_offset AFE ovr_signal.
12534     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_EN_F582_SHIFT                         0
12535     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_EN_UNUSED_0                           (0x7f<<1) // reserved
12536     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_EN_UNUSED_0_SHIFT                     1
12537 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_VAL                                       0x001d08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12538     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_VAL_F583                              (0x3f<<0) // Override value for afe_rxdfe_sumodd_offset AFE input.
12539     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_VAL_F583_SHIFT                        0
12540     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_VAL_UNUSED_0                          (0x3<<6) // reserved
12541     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_SUMODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT                    6
12542 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_EN                                                 0x001d0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12543     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_EN_F584                                        (0x1<<0) // Override enable for afe_rxdfe_tap2 AFE ovr_signal.
12544     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_EN_F584_SHIFT                                  0
12545     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
12546     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_EN_UNUSED_0_SHIFT                              1
12547 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_VAL                                                0x001d10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12548     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_VAL_F585                                       (0xf<<0) // Override value for afe_rxdfe_tap2 AFE input.
12549     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_VAL_F585_SHIFT                                 0
12550     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_VAL_UNUSED_0                                   (0xf<<4) // reserved
12551     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP2_OVR_VAL_UNUSED_0_SHIFT                             4
12552 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_EN                                                 0x001d14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12553     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_EN_F586                                        (0x1<<0) // Override enable for afe_rxdfe_tap3 AFE ovr_signal.
12554     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_EN_F586_SHIFT                                  0
12555     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
12556     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_EN_UNUSED_0_SHIFT                              1
12557 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_VAL                                                0x001d18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12558     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_VAL_F587                                       (0x7<<0) // Override value for afe_rxdfe_tap3 AFE input.
12559     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_VAL_F587_SHIFT                                 0
12560     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
12561     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP3_OVR_VAL_UNUSED_0_SHIFT                             3
12562 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_EN                                                 0x001d1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12563     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_EN_F588                                        (0x1<<0) // Override enable for afe_rxdfe_tap4 AFE ovr_signal.
12564     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_EN_F588_SHIFT                                  0
12565     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
12566     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_EN_UNUSED_0_SHIFT                              1
12567 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_VAL                                                0x001d20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12568     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_VAL_F589                                       (0x7<<0) // Override value for afe_rxdfe_tap4 AFE input.
12569     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_VAL_F589_SHIFT                                 0
12570     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
12571     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP4_OVR_VAL_UNUSED_0_SHIFT                             3
12572 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_EN                                                 0x001d24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12573     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_EN_F590                                        (0x1<<0) // Override enable for afe_rxdfe_tap5 AFE ovr_signal.
12574     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_EN_F590_SHIFT                                  0
12575     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
12576     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_EN_UNUSED_0_SHIFT                              1
12577 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_VAL                                                0x001d28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12578     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_VAL_F591                                       (0x7<<0) // Override value for afe_rxdfe_tap5 AFE input.
12579     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_VAL_F591_SHIFT                                 0
12580     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_VAL_UNUSED_0                                   (0x1f<<3) // reserved
12581     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_TAP5_OVR_VAL_UNUSED_0_SHIFT                             3
12582 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_EN                                     0x001d2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12583     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_EN_F592                            (0x1<<0) // Override enable for afe_rxdfe_vscaneven_offset AFE ovr_signal.
12584     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_EN_F592_SHIFT                      0
12585     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_EN_UNUSED_0                        (0x7f<<1) // reserved
12586     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_EN_UNUSED_0_SHIFT                  1
12587 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_VAL                                    0x001d30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12588     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_F593                           (0x3f<<0) // Override value for afe_rxdfe_vscaneven_offset AFE input.
12589     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_F593_SHIFT                     0
12590     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_UNUSED_0                       (0x3<<6) // reserved
12591     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANEVEN_OFFSET_OVR_VAL_UNUSED_0_SHIFT                 6
12592 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_EN                                      0x001d34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12593     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_EN_F594                             (0x1<<0) // Override enable for afe_rxdfe_vscanodd_offset AFE ovr_signal.
12594     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_EN_F594_SHIFT                       0
12595     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_EN_UNUSED_0                         (0x7f<<1) // reserved
12596     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_EN_UNUSED_0_SHIFT                   1
12597 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_VAL                                     0x001d38UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12598     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_VAL_F595                            (0x3f<<0) // Override value for afe_rxdfe_vscanodd_offset AFE input.
12599     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_VAL_F595_SHIFT                      0
12600     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_VAL_UNUSED_0                        (0x3<<6) // reserved
12601     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDFE_VSCANODD_OFFSET_OVR_VAL_UNUSED_0_SHIFT                  6
12602 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_EN                                            0x001d3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12603     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_EN_F596                                   (0x1<<0) // Override enable for afe_rxdp_data_width AFE ovr_signal.
12604     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_EN_F596_SHIFT                             0
12605     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12606     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_EN_UNUSED_0_SHIFT                         1
12607 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_VAL                                           0x001d40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12608     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_VAL_F597                                  (0x1<<0) // Override value for afe_rxdp_data_width AFE input.
12609     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_VAL_F597_SHIFT                            0
12610     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
12611     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXDP_DATA_WIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
12612 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_EN                                           0x001d44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12613     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_EN_F598                                  (0x1<<0) // Override enable for afe_rxleq_eq_biasres AFE ovr_signal.
12614     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_EN_F598_SHIFT                            0
12615     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12616     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_EN_UNUSED_0_SHIFT                        1
12617 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_VAL                                          0x001d48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12618     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_VAL_F599                                 (0x7<<0) // Override value for afe_rxleq_eq_biasres AFE input.
12619     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_VAL_F599_SHIFT                           0
12620     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
12621     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_BIASRES_OVR_VAL_UNUSED_0_SHIFT                       3
12622 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_EN                                               0x001d4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12623     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_EN_F600                                      (0x1<<0) // Override enable for afe_rxleq_eq_hfg AFE ovr_signal.
12624     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_EN_F600_SHIFT                                0
12625     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12626     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_EN_UNUSED_0_SHIFT                            1
12627 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_VAL                                              0x001d50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12628     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_VAL_F601                                     (0x1f<<0) // Override value for afe_rxleq_eq_hfg AFE input.
12629     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_VAL_F601_SHIFT                               0
12630     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_VAL_UNUSED_0                                 (0x7<<5) // reserved
12631     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_HFG_OVR_VAL_UNUSED_0_SHIFT                           5
12632 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_EN                                               0x001d54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12633     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_EN_F602                                      (0x1<<0) // Override enable for afe_rxleq_eq_lfg AFE ovr_signal.
12634     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_EN_F602_SHIFT                                0
12635     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12636     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_EN_UNUSED_0_SHIFT                            1
12637 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_VAL                                              0x001d58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12638     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_VAL_F603                                     (0x1f<<0) // Override value for afe_rxleq_eq_lfg AFE input.
12639     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_VAL_F603_SHIFT                               0
12640     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_VAL_UNUSED_0                                 (0x7<<5) // reserved
12641     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LFG_OVR_VAL_UNUSED_0_SHIFT                           5
12642 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_EN                                           0x001d5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12643     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_EN_F604                                  (0x1<<0) // Override enable for afe_rxleq_eq_loadres AFE ovr_signal.
12644     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_EN_F604_SHIFT                            0
12645     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12646     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_EN_UNUSED_0_SHIFT                        1
12647 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_VAL                                          0x001d60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12648     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_VAL_F605                                 (0x7<<0) // Override value for afe_rxleq_eq_loadres AFE input.
12649     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_VAL_F605_SHIFT                           0
12650     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
12651     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_LOADRES_OVR_VAL_UNUSED_0_SHIFT                       3
12652 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_EN                                               0x001d64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12653     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_EN_F606                                      (0x1<<0) // Override enable for afe_rxleq_eq_mbf AFE ovr_signal.
12654     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_EN_F606_SHIFT                                0
12655     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12656     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_EN_UNUSED_0_SHIFT                            1
12657 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_VAL                                              0x001d68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12658     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_VAL_F607                                     (0xf<<0) // Override value for afe_rxleq_eq_mbf AFE input.
12659     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_VAL_F607_SHIFT                               0
12660     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_VAL_UNUSED_0                                 (0xf<<4) // reserved
12661     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBF_OVR_VAL_UNUSED_0_SHIFT                           4
12662 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_EN                                               0x001d6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12663     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_EN_F608                                      (0x1<<0) // Override enable for afe_rxleq_eq_mbg AFE ovr_signal.
12664     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_EN_F608_SHIFT                                0
12665     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12666     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_EN_UNUSED_0_SHIFT                            1
12667 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_VAL                                              0x001d70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12668     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_VAL_F609                                     (0xf<<0) // Override value for afe_rxleq_eq_mbg AFE input.
12669     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_VAL_F609_SHIFT                               0
12670     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_VAL_UNUSED_0                                 (0xf<<4) // reserved
12671     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_MBG_OVR_VAL_UNUSED_0_SHIFT                           4
12672 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_EN                                               0x001d74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12673     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_EN_F610                                      (0x1<<0) // Override enable for afe_rxleq_eq_sql AFE ovr_signal.
12674     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_EN_F610_SHIFT                                0
12675     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12676     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_EN_UNUSED_0_SHIFT                            1
12677 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_VAL                                              0x001d78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12678     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_VAL_F611                                     (0x7<<0) // Override value for afe_rxleq_eq_sql AFE input.
12679     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_VAL_F611_SHIFT                               0
12680     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_VAL_UNUSED_0                                 (0x1f<<3) // reserved
12681     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_EQ_SQL_OVR_VAL_UNUSED_0_SHIFT                           3
12682 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_EN                                               0x001d7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12683     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_EN_F612                                      (0x1<<0) // Override enable for afe_rxleq_gn_apg AFE ovr_signal.
12684     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_EN_F612_SHIFT                                0
12685     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12686     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_EN_UNUSED_0_SHIFT                            1
12687 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_VAL                                              0x001d80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12688     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_VAL_F613                                     (0x3<<0) // Override value for afe_rxleq_gn_apg AFE input.
12689     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_VAL_F613_SHIFT                               0
12690     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_VAL_UNUSED_0                                 (0x3f<<2) // reserved
12691     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_APG_OVR_VAL_UNUSED_0_SHIFT                           2
12692 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_EN                                             0x001d84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12693     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_EN_F614                                    (0x1<<0) // Override enable for afe_rxleq_gn_biasi AFE ovr_signal.
12694     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_EN_F614_SHIFT                              0
12695     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
12696     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_EN_UNUSED_0_SHIFT                          1
12697 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_VAL                                            0x001d88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12698     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_VAL_F615                                   (0x3<<0) // Override value for afe_rxleq_gn_biasi AFE input.
12699     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_VAL_F615_SHIFT                             0
12700     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_VAL_UNUSED_0                               (0x3f<<2) // reserved
12701     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_BIASI_OVR_VAL_UNUSED_0_SHIFT                         2
12702 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_EN                                           0x001d8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12703     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_EN_F616                                  (0x1<<0) // Override enable for afe_rxleq_gn_loadres AFE ovr_signal.
12704     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_EN_F616_SHIFT                            0
12705     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12706     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_EN_UNUSED_0_SHIFT                        1
12707 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_VAL                                          0x001d90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12708     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_VAL_F617                                 (0x7<<0) // Override value for afe_rxleq_gn_loadres AFE input.
12709     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_VAL_F617_SHIFT                           0
12710     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
12711     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_GN_LOADRES_OVR_VAL_UNUSED_0_SHIFT                       3
12712 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_EN                                            0x001d94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12713     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_EN_F618                                   (0x1<<0) // Override enable for afe_rxleq_offset_e1 AFE ovr_signal.
12714     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_EN_F618_SHIFT                             0
12715     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12716     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_EN_UNUSED_0_SHIFT                         1
12717 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_VAL                                           0x001d98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12718     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_VAL_F619                                  (0x3f<<0) // Override value for afe_rxleq_offset_e1 AFE input.
12719     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_VAL_F619_SHIFT                            0
12720     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12721     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E1_OVR_VAL_UNUSED_0_SHIFT                        6
12722 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_EN                                            0x001d9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12723     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_EN_F620                                   (0x1<<0) // Override enable for afe_rxleq_offset_e2 AFE ovr_signal.
12724     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_EN_F620_SHIFT                             0
12725     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12726     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_EN_UNUSED_0_SHIFT                         1
12727 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_VAL                                           0x001da0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12728     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_VAL_F621                                  (0x3f<<0) // Override value for afe_rxleq_offset_e2 AFE input.
12729     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_VAL_F621_SHIFT                            0
12730     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12731     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E2_OVR_VAL_UNUSED_0_SHIFT                        6
12732 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_EN                                            0x001da4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12733     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_EN_F622                                   (0x1<<0) // Override enable for afe_rxleq_offset_e3 AFE ovr_signal.
12734     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_EN_F622_SHIFT                             0
12735     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12736     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_EN_UNUSED_0_SHIFT                         1
12737 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_VAL                                           0x001da8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12738     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_VAL_F623                                  (0x3f<<0) // Override value for afe_rxleq_offset_e3 AFE input.
12739     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_VAL_F623_SHIFT                            0
12740     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12741     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E3_OVR_VAL_UNUSED_0_SHIFT                        6
12742 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_EN                                            0x001dacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12743     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_EN_F624                                   (0x1<<0) // Override enable for afe_rxleq_offset_e4 AFE ovr_signal.
12744     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_EN_F624_SHIFT                             0
12745     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12746     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_EN_UNUSED_0_SHIFT                         1
12747 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_VAL                                           0x001db0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12748     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_VAL_F625                                  (0x3f<<0) // Override value for afe_rxleq_offset_e4 AFE input.
12749     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_VAL_F625_SHIFT                            0
12750     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12751     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E4_OVR_VAL_UNUSED_0_SHIFT                        6
12752 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_EN                                            0x001db4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12753     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_EN_F626                                   (0x1<<0) // Override enable for afe_rxleq_offset_e5 AFE ovr_signal.
12754     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_EN_F626_SHIFT                             0
12755     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12756     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_EN_UNUSED_0_SHIFT                         1
12757 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_VAL                                           0x001db8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12758     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_VAL_F627                                  (0x3f<<0) // Override value for afe_rxleq_offset_e5 AFE input.
12759     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_VAL_F627_SHIFT                            0
12760     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12761     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E5_OVR_VAL_UNUSED_0_SHIFT                        6
12762 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_EN                                            0x001dbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12763     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_EN_F628                                   (0x1<<0) // Override enable for afe_rxleq_offset_e6 AFE ovr_signal.
12764     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_EN_F628_SHIFT                             0
12765     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12766     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_EN_UNUSED_0_SHIFT                         1
12767 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_VAL                                           0x001dc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12768     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_VAL_F629                                  (0x3f<<0) // Override value for afe_rxleq_offset_e6 AFE input.
12769     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_VAL_F629_SHIFT                            0
12770     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12771     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_E6_OVR_VAL_UNUSED_0_SHIFT                        6
12772 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_EN                                            0x001dc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12773     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_EN_F630                                   (0x1<<0) // Override enable for afe_rxleq_offset_g1 AFE ovr_signal.
12774     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_EN_F630_SHIFT                             0
12775     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12776     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_EN_UNUSED_0_SHIFT                         1
12777 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_VAL                                           0x001dc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12778     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_VAL_F631                                  (0x3f<<0) // Override value for afe_rxleq_offset_g1 AFE input.
12779     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_VAL_F631_SHIFT                            0
12780     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_VAL_UNUSED_0                              (0x3<<6) // reserved
12781     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_OFFSET_G1_OVR_VAL_UNUSED_0_SHIFT                        6
12782 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_EN                                              0x001dccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12783     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_EN_F632                                     (0x1<<0) // Override enable for afe_rxleq_ple_att AFE ovr_signal.
12784     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_EN_F632_SHIFT                               0
12785     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
12786     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_EN_UNUSED_0_SHIFT                           1
12787 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_VAL                                             0x001dd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12788     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_VAL_F633                                    (0x7<<0) // Override value for afe_rxleq_ple_att AFE input.
12789     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_VAL_F633_SHIFT                              0
12790     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_VAL_UNUSED_0                                (0x1f<<3) // reserved
12791     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLEQ_PLE_ATT_OVR_VAL_UNUSED_0_SHIFT                          3
12792 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_EN                                                  0x001dd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12793     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_EN_F634                                         (0x1<<0) // Override enable for afe_rxlos_agc AFE ovr_signal.
12794     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_EN_F634_SHIFT                                   0
12795     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_EN_UNUSED_0                                     (0x7f<<1) // reserved
12796     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_EN_UNUSED_0_SHIFT                               1
12797 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_VAL                                                 0x001dd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12798     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_VAL_F635                                        (0x1<<0) // Override value for afe_rxlos_agc AFE input.
12799     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_VAL_F635_SHIFT                                  0
12800     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_VAL_UNUSED_0                                    (0x7f<<1) // reserved
12801     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_OVR_VAL_UNUSED_0_SHIFT                              1
12802 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_EN                                              0x001ddcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12803     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_EN_F636                                     (0x1<<0) // Override enable for afe_rxlos_agc_set AFE ovr_signal.
12804     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_EN_F636_SHIFT                               0
12805     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
12806     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_EN_UNUSED_0_SHIFT                           1
12807 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_VAL                                             0x001de0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12808     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_VAL_F637                                    (0x1<<0) // Override value for afe_rxlos_agc_set AFE input.
12809     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_VAL_F637_SHIFT                              0
12810     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_VAL_UNUSED_0                                (0x7f<<1) // reserved
12811     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_AGC_SET_OVR_VAL_UNUSED_0_SHIFT                          1
12812 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_EN                                            0x001de4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12813     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_EN_F638                                   (0x1<<0) // Override enable for afe_rxlos_bandwidth AFE ovr_signal.
12814     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_EN_F638_SHIFT                             0
12815     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12816     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_EN_UNUSED_0_SHIFT                         1
12817 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_VAL                                           0x001de8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12818     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_VAL_F639                                  (0x1<<0) // Override value for afe_rxlos_bandwidth AFE input.
12819     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_VAL_F639_SHIFT                            0
12820     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
12821     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_BANDWIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
12822 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_EN                                             0x001decUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12823     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_EN_F640                                    (0x1<<0) // Override enable for afe_rxlos_comp_sel AFE ovr_signal.
12824     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_EN_F640_SHIFT                              0
12825     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_EN_UNUSED_0                                (0x7f<<1) // reserved
12826     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_EN_UNUSED_0_SHIFT                          1
12827 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_VAL                                            0x001df0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12828     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_VAL_F641                                   (0x1<<0) // Override value for afe_rxlos_comp_sel AFE input.
12829     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_VAL_F641_SHIFT                             0
12830     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_VAL_UNUSED_0                               (0x7f<<1) // reserved
12831     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_COMP_SEL_OVR_VAL_UNUSED_0_SHIFT                         1
12832 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_EN                                           0x001df4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12833     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_EN_F642                                  (0x1<<0) // Override enable for afe_rxlos_envdet_byp AFE ovr_signal.
12834     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_EN_F642_SHIFT                            0
12835     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12836     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_EN_UNUSED_0_SHIFT                        1
12837 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_VAL                                          0x001df8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12838     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_VAL_F643                                 (0x1<<0) // Override value for afe_rxlos_envdet_byp AFE input.
12839     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_VAL_F643_SHIFT                           0
12840     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_VAL_UNUSED_0                             (0x7f<<1) // reserved
12841     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_ENVDET_BYP_OVR_VAL_UNUSED_0_SHIFT                       1
12842 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_EN                                                 0x001dfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12843     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_EN_F644                                        (0x1<<0) // Override enable for afe_rxlos_gain AFE ovr_signal.
12844     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_EN_F644_SHIFT                                  0
12845     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_EN_UNUSED_0                                    (0x7f<<1) // reserved
12846     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_EN_UNUSED_0_SHIFT                              1
12847 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_VAL                                                0x001e00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12848     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_VAL_F645                                       (0x1<<0) // Override value for afe_rxlos_gain AFE input.
12849     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_VAL_F645_SHIFT                                 0
12850     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_VAL_UNUSED_0                                   (0x7f<<1) // reserved
12851     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_GAIN_OVR_VAL_UNUSED_0_SHIFT                             1
12852 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_EN                                           0x001e04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12853     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_EN_F646                                  (0x1<<0) // Override enable for afe_rxlos_hysteresis AFE ovr_signal.
12854     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_EN_F646_SHIFT                            0
12855     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_EN_UNUSED_0                              (0x7f<<1) // reserved
12856     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_EN_UNUSED_0_SHIFT                        1
12857 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_VAL                                          0x001e08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12858     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_VAL_F647                                 (0x7<<0) // Override value for afe_rxlos_hysteresis AFE input.
12859     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_VAL_F647_SHIFT                           0
12860     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_VAL_UNUSED_0                             (0x1f<<3) // reserved
12861     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_HYSTERESIS_OVR_VAL_UNUSED_0_SHIFT                       3
12862 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_EN                                               0x001e0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12863     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_EN_F648                                      (0x1<<0) // Override enable for afe_rxlos_offset AFE ovr_signal.
12864     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_EN_F648_SHIFT                                0
12865     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12866     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_EN_UNUSED_0_SHIFT                            1
12867 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_VAL                                              0x001e10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12868     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_VAL_F649                                     (0x3f<<0) // Override value for afe_rxlos_offset AFE input.
12869     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_VAL_F649_SHIFT                               0
12870     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_VAL_UNUSED_0                                 (0x3<<6) // reserved
12871     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_OFFSET_OVR_VAL_UNUSED_0_SHIFT                           6
12872 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_EN                                                  0x001e14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12873     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_EN_F650                                         (0x1<<0) // Override enable for afe_rxlos_raw AFE ovr_signal.
12874     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_EN_F650_SHIFT                                   0
12875     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_EN_UNUSED_0                                     (0x7f<<1) // reserved
12876     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_EN_UNUSED_0_SHIFT                               1
12877 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_VAL                                                 0x001e18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12878     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_VAL_F651                                        (0x1<<0) // Override value for afe_rxlos_raw AFE input.
12879     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_VAL_F651_SHIFT                                  0
12880     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_VAL_UNUSED_0                                    (0x7f<<1) // reserved
12881     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_RAW_OVR_VAL_UNUSED_0_SHIFT                              1
12882 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_EN                                                0x001e1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12883     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_EN_F652                                       (0x1<<0) // Override enable for afe_rxlos_spare AFE ovr_signal.
12884     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_EN_F652_SHIFT                                 0
12885     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
12886     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_EN_UNUSED_0_SHIFT                             1
12887 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_VAL                                               0x001e20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12888     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_VAL_F653                                      (0xf<<0) // Override value for afe_rxlos_spare AFE input.
12889     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_VAL_F653_SHIFT                                0
12890     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_VAL_UNUSED_0                                  (0xf<<4) // reserved
12891     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_SPARE_OVR_VAL_UNUSED_0_SHIFT                            4
12892 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_EN                                            0x001e24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12893     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_EN_F654                                   (0x1<<0) // Override enable for afe_rxlos_threshold AFE ovr_signal.
12894     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_EN_F654_SHIFT                             0
12895     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12896     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_EN_UNUSED_0_SHIFT                         1
12897 #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_VAL                                           0x001e28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12898     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_VAL_F655                                  (0xf<<0) // Override value for afe_rxlos_threshold AFE input.
12899     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_VAL_F655_SHIFT                            0
12900     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_VAL_UNUSED_0                              (0xf<<4) // reserved
12901     #define PHY_NW_IP_REG_PHY0_OVR_LN3_RXLOS_THRESHOLD_OVR_VAL_UNUSED_0_SHIFT                        4
12902 #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_EN                                              0x001e2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12903     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_EN_F656                                     (0x1<<0) // Override enable for afe_txcp_dcd_trim AFE ovr_signal.
12904     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_EN_F656_SHIFT                               0
12905     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_EN_UNUSED_0                                 (0x7f<<1) // reserved
12906     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_EN_UNUSED_0_SHIFT                           1
12907 #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_VAL                                             0x001e30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12908     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_VAL_F657                                    (0x3f<<0) // Override value for afe_txcp_dcd_trim AFE input.
12909     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_VAL_F657_SHIFT                              0
12910     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_VAL_UNUSED_0                                (0x3<<6) // reserved
12911     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXCP_DCD_TRIM_OVR_VAL_UNUSED_0_SHIFT                          6
12912 #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_EN                                               0x001e34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12913     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_EN_F658                                      (0x1<<0) // Override enable for afe_txdp_cal_out AFE ovr_signal.
12914     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_EN_F658_SHIFT                                0
12915     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_EN_UNUSED_0                                  (0x7f<<1) // reserved
12916     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_EN_UNUSED_0_SHIFT                            1
12917 #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_VAL                                              0x001e38UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12918     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_VAL_F659                                     (0x1<<0) // Override value for afe_txdp_cal_out AFE input.
12919     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_VAL_F659_SHIFT                               0
12920     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_VAL_UNUSED_0                                 (0x7f<<1) // reserved
12921     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CAL_OUT_OVR_VAL_UNUSED_0_SHIFT                           1
12922 #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_EN                                                0x001e3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12923     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_EN_F660                                       (0x1<<0) // Override enable for afe_txdp_clkdly AFE ovr_signal.
12924     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_EN_F660_SHIFT                                 0
12925     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_EN_UNUSED_0                                   (0x7f<<1) // reserved
12926     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_EN_UNUSED_0_SHIFT                             1
12927 #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_VAL                                               0x001e40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12928     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_VAL_F661                                      (0xf<<0) // Override value for afe_txdp_clkdly AFE input.
12929     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_VAL_F661_SHIFT                                0
12930     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_VAL_UNUSED_0                                  (0xf<<4) // reserved
12931     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_CLKDLY_OVR_VAL_UNUSED_0_SHIFT                            4
12932 #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_EN                                            0x001e44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12933     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_EN_F662                                   (0x1<<0) // Override enable for afe_txdp_data_width AFE ovr_signal.
12934     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_EN_F662_SHIFT                             0
12935     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_EN_UNUSED_0                               (0x7f<<1) // reserved
12936     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_EN_UNUSED_0_SHIFT                         1
12937 #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_VAL                                           0x001e48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12938     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_VAL_F663                                  (0x1<<0) // Override value for afe_txdp_data_width AFE input.
12939     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_VAL_F663_SHIFT                            0
12940     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_VAL_UNUSED_0                              (0x7f<<1) // reserved
12941     #define PHY_NW_IP_REG_PHY0_OVR_LN3_TXDP_DATA_WIDTH_OVR_VAL_UNUSED_0_SHIFT                        1
12942 #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0                                                     0x002080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12943     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_UNUSED_0                                        (0x1f<<0) // reserved
12944     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_UNUSED_0_SHIFT                                  0
12945     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV                              (0x7<<5) // Divider control for CMU output clock cm0_clkdiv_o. This is the additional divided CMU clock for SoC logic. A different divider is employed to allow a different clock frequency from cm0_clk_o. This clock can be used in gearbox applications.  0x0 - DIV4 0x1 - DIV8 0x2 - DIV16 0x3 - DIV20 0x4 - DIV32 0x5 - DIV40 0x6 - DIV64 0x7 - DIV80  The output clock frequency is the serial data rate divided by the divider setting. For example, the output clock will be 805.66406MHz for the DIV32 setting at 25.78125Gbps.
12946     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_CMCP_CTRL0_CMCP_CMUDIVCLK_DIV_SHIFT                        5
12947 #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0                                                   0x0020a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12948     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX                               (0x3<<0) // Test clock MUX control. This is a test feature that allows certain internal clocks to be muxed into the half-rate TX clock path to provide visibility at the TX driver output.  0x0 - mission mode 0x1 - reference clock 0x2 - life clock 0x3 - CMU PLL word rate clock cm0_clk_o
12949     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_MUX_SHIFT                         0
12950     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV                               (0x7<<2) // Test clock divider control. This register controls a programmable divider on the test clock path before clock distribution from the CMU macro to all lanes macros.  0x0 - DIV1 0x1 - DIV2 0x2 - DIV4 0x3 - DIV5 0x4 - DIV8 0x5 - DIV10 0x6 - DIV16 0x7 - DIV20
12951     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_CMCP_TSTCLK_DIV_SHIFT                         2
12952     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_UNUSED_0                                      (0x7<<5) // reserved
12953     #define PHY_NW_IP_REG_CMU_LC0_TOP_AFE_TSTCLK_CTRL0_UNUSED_0_SHIFT                                5
12954 #define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS                                                      0x002148UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
12955     #define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS_CMU_OK                                           (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indicates that CMU macro has successfully transitioned into the ACTIVE or PARTIAL power state, the PLL has locked to the reference clock, and all output clocks are at the correct frequency
12956     #define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS_CMU_OK_SHIFT                                     0
12957     #define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS_UNUSED_0                                         (0x7f<<1) // reserved
12958     #define PHY_NW_IP_REG_CMU_LC0_TOP_PHY_IF_STATUS_UNUSED_0_SHIFT                                   1
12959 #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL1                                                          0x002200UL //Access:RW   DataWidth:0x8   lower 8-bits of 16-bit CMU error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
12960 #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL2                                                          0x002204UL //Access:RW   DataWidth:0x8   higher 8-bits of 16-bit CMU error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
12961 #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3                                                          0x002208UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12962     #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3_CMU_ERR                                              (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro has an internal error detected by firmware. CMU error code can be used to isolate error event.
12963     #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3_CMU_ERR_SHIFT                                        0
12964     #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3_UNUSED_0                                             (0x7f<<1) // reserved
12965     #define PHY_NW_IP_REG_CMU_LC0_TOP_ERR_CTRL3_UNUSED_0_SHIFT                                       1
12966 #define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1                                                      0x00240cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12967     #define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1_CMPLL_V1P8_EN                                    (0x1<<0) // CMU PLL regulator vddha setting.   0x0 - vddha is 1.5V nominal 0x1 - vddha is 1.8V nominal  note: it is important that this register is maintained at the correct value matching the nominal vddha setting for all time following POR.
12968     #define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1_CMPLL_V1P8_EN_SHIFT                              0
12969     #define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1_UNUSED_0                                         (0x7f<<1) // reserved
12970     #define PHY_NW_IP_REG_CMU_LC0_PLL_AFE_REG_CTRL1_UNUSED_0_SHIFT                                   1
12971 #define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS                                                     0x002518UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
12972     #define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS_LOCKED                                          (0x1<<0) // CMU PLL lock detector status. 0x0 - CMU PLL is not locked 0x1 - CMU PLL has locked to the reference clock, and all output clocks are at the correct frequency
12973     #define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS_LOCKED_SHIFT                                    0
12974     #define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS_UNUSED_0                                        (0x7f<<1) // reserved
12975     #define PHY_NW_IP_REG_CMU_LC0_PLL_LOCKDET_STATUS_UNUSED_0_SHIFT                                  1
12976 #define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS                                                       0x003148UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
12977     #define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS_CMU_OK                                            (0x1<<0) // CMU OK status. 0x0 - CMU PLL is not locked 0x1 - indicates that CMU macro has successfully transitioned into the ACTIVE or PARTIAL power state, the PLL has locked to the reference clock, and all output clocks are at the correct frequency
12978     #define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS_CMU_OK_SHIFT                                      0
12979     #define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS_UNUSED_0                                          (0x7f<<1) // reserved
12980     #define PHY_NW_IP_REG_CMU_R0_TOP_PHY_IF_STATUS_UNUSED_0_SHIFT                                    1
12981 #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL1                                                           0x003200UL //Access:RW   DataWidth:0x8   lower 8-bits of 16-bit CMU error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
12982 #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL2                                                           0x003204UL //Access:RW   DataWidth:0x8   higher 8-bits of 16-bit CMU error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
12983 #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3                                                           0x003208UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12984     #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3_CMU_ERR                                               (0x1<<0) // CMU macro error status. 0x0 - no error 0x1 - PHY CMU macro has an internal error detected by firmware. CMU error code can be used to isolate error event.
12985     #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3_CMU_ERR_SHIFT                                         0
12986     #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3_UNUSED_0                                              (0x7f<<1) // reserved
12987     #define PHY_NW_IP_REG_CMU_R0_TOP_ERR_CTRL3_UNUSED_0_SHIFT                                        1
12988 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0                                                       0x003400UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12989     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_PD_CMPLL2                                         (0x1<<0) // Powerdown for RPLL.
12990     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_PD_CMPLL2_SHIFT                                   0
12991     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_UNUSED_0                                          (0x7f<<1) // reserved
12992     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PD_CTRL0_UNUSED_0_SHIFT                                    1
12993 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0                                                      0x003404UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
12994     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_FRACN_N                               (0x1<<0) // Resets the DivN counter in the FracN
12995     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_FRACN_N_SHIFT                         0
12996     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_DIV4P125_N                            (0x1<<1) // TBD
12997     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_RST_CMPLL2_DIV4P125_N_SHIFT                      1
12998     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_UNUSED_0                                         (0x3f<<2) // reserved
12999     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_RST_CTRL0_UNUSED_0_SHIFT                                   2
13000 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0                                                      0x00340cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13001     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0_CMPLL2_REFCLK_SEL                                (0x1<<0) // Select the reference clock. 0 - clk_ref 1- clk_pllref
13002     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0_CMPLL2_REFCLK_SEL_SHIFT                          0
13003     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0_UNUSED_0                                         (0x7f<<1) // reserved
13004     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLK_CTRL0_UNUSED_0_SHIFT                                   1
13005 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0                                                      0x003410UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13006     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_VCO_KICK                                  (0x1<<0) // TBD
13007     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_VCO_KICK_SHIFT                            0
13008     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_BIAS_TRIM                                 (0x1f<<1) // TBD
13009     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_CMPLL2_BIAS_TRIM_SHIFT                           1
13010     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_UNUSED_0                                         (0x3<<6) // reserved
13011     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_VCO_CTRL0_UNUSED_0_SHIFT                                   6
13012 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLKDIV_CTRL0                                                   0x003418UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13013     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLKDIV_CTRL0_CMPLL2_FBKCLK_DIV                             (0x3<<0) // TBD
13014     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLKDIV_CTRL0_CMPLL2_FBKCLK_DIV_SHIFT                       0
13015     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLKDIV_CTRL0_UNUSED_0                                      (0x3f<<2) // reserved
13016     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_CLKDIV_CTRL0_UNUSED_0_SHIFT                                2
13017 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL0                                                      0x003424UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13018     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL0_CMPLL2_PFD_PW                                    (0x3<<0) // TBD
13019     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL0_CMPLL2_PFD_PW_SHIFT                              0
13020     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL0_UNUSED_0                                         (0x3f<<2) // reserved
13021     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL0_UNUSED_0_SHIFT                                   2
13022 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1                                                      0x003428UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13023     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_MUTE                                      (0x1<<0) // TBD
13024     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_MUTE_SHIFT                                0
13025     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_UP                              (0x1<<1) // TBD
13026     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_UP_SHIFT                        1
13027     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_DN                              (0x1<<2) // TBD
13028     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_CMPLL2_PFD_FORCE_DN_SHIFT                        2
13029     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_UNUSED_0                                         (0x1f<<3) // reserved
13030     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PFD_CTRL1_UNUSED_0_SHIFT                                   3
13031 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0                                                     0x00342cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13032     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_CMPLL2_PFILT                                    (0x7<<0) // TBD
13033     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_CMPLL2_PFILT_SHIFT                              0
13034     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_UNUSED_0                                        (0x1<<3) // reserved
13035     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_UNUSED_0_SHIFT                                  3
13036     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_CMPLL2_PCP_TRIM                                 (0x3<<4) // TBD
13037     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_CMPLL2_PCP_TRIM_SHIFT                           4
13038     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_UNUSED_1                                        (0x3<<6) // reserved
13039     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL0_UNUSED_1_SHIFT                                  6
13040 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL1                                                     0x003430UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13041     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL1_CMPLL2_PKVCO                                    (0x1f<<0) // TBD
13042     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL1_CMPLL2_PKVCO_SHIFT                              0
13043     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL1_UNUSED_0                                        (0x7<<5) // reserved
13044     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_PROP_CTRL1_UNUSED_0_SHIFT                                  5
13045 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0                                                      0x003434UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13046     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IDROPI                                    (0x1<<0) // TBD
13047     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IDROPI_SHIFT                              0
13048     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IHIZ                                      (0x1<<1) // TBD
13049     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IHIZ_SHIFT                                1
13050     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IFILT                                     (0xf<<2) // TBD
13051     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IFILT_SHIFT                               2
13052     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IKVCO                                     (0x3<<6) // TBD
13053     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL0_CMPLL2_IKVCO_SHIFT                               6
13054 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1                                                      0x00343cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13055     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IZERO                                     (0x1<<0) // TBD
13056     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IZERO_SHIFT                               0
13057     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IFORCE                                    (0x3<<1) // TBD
13058     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_CMPLL2_IFORCE_SHIFT                              1
13059     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_UNUSED_0                                         (0x1f<<3) // reserved
13060     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL1_UNUSED_0_SHIFT                                   3
13061 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2                                                      0x003440UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13062     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_CAP                                   (0x7<<0) // TBD
13063     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_CAP_SHIFT                             0
13064     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_LPF                                   (0x1<<3) // TBD
13065     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_LPF_SHIFT                             3
13066     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_GAIN                                  (0x3<<4) // TBD
13067     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_CMPLL2_V2I_GAIN_SHIFT                            4
13068     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_UNUSED_0                                         (0x3<<6) // reserved
13069     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL2_UNUSED_0_SHIFT                                   6
13070 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3                                                      0x003444UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13071     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_EN                                 (0x1<<0) // TBD
13072     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_EN_SHIFT                           0
13073     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_DIV                                (0x7<<1) // TBD
13074     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_CMPLL2_CPCHOP_DIV_SHIFT                          1
13075     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_UNUSED_0                                         (0xf<<4) // reserved
13076     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_INT_CTRL3_UNUSED_0_SHIFT                                   4
13077 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0                                                    0x003448UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13078     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0_CMPLL2_FRACDIV_EN                              (0x1<<0) // Selects between FracN and integer divide modes 0 ? integer mode 1 ? FracN/SSC mode
13079     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0_CMPLL2_FRACDIV_EN_SHIFT                        0
13080     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0_UNUSED_0                                       (0x7f<<1) // reserved
13081     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_FRACN_CTRL0_UNUSED_0_SHIFT                                 1
13082 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0                                                     0x003458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13083     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0_CMPLL2_BIAS_LPF                                 (0x1<<0) // TBD
13084     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0_CMPLL2_BIAS_LPF_SHIFT                           0
13085     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0_UNUSED_0                                        (0x7f<<1) // reserved
13086     #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL0_UNUSED_0_SHIFT                                  1
13087 #define PHY_NW_IP_REG_CMU_R0_RPLL_AFE_MISC_CTRL1                                                     0x00345cUL //Access:RW   DataWidth:0x8   TBD  Chips: K2
13088 #define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS                                                     0x003518UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13089     #define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS_LOCKED                                          (0x1<<0) // For lock detection
13090     #define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS_LOCKED_SHIFT                                    0
13091     #define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS_UNUSED_0                                        (0x7f<<1) // reserved
13092     #define PHY_NW_IP_REG_CMU_R0_RPLL_LOCKDET_STATUS_UNUSED_0_SHIFT                                  1
13093 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL0                                                      0x003524UL //Access:RW   DataWidth:0x8   Sets maximum spreading frequency in SSC mode.  Chips: K2
13094 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL1                                                      0x003528UL //Access:RW   DataWidth:0x8   Sets maximum spreading frequency in SSC mode.  Chips: K2
13095 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL2                                                      0x00352cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13096     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL2_MATCH_VAL_19_16                                  (0xf<<0) // Sets maximum spreading frequency in SSC mode.
13097     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL2_MATCH_VAL_19_16_SHIFT                            0
13098     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL2_UNUSED_0                                         (0xf<<4) // reserved
13099     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL2_UNUSED_0_SHIFT                                   4
13100 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL3                                                      0x003530UL //Access:RW   DataWidth:0x8   Increment value in SSC mode;Enabled when ssc_gen_en=1.Note: this is an unsigned number  Chips: K2
13101 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL4                                                      0x003534UL //Access:RW   DataWidth:0x8   Increment value in SSC mode;Enabled when ssc_gen_en=1.Note: this is an unsigned number  Chips: K2
13102 #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5                                                      0x003538UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13103     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_UPDOWN_EN                                        (0x1<<0) // Enable for both Upspreading and Downspreading in SSC mode
13104     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_UPDOWN_EN_SHIFT                                  0
13105     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_FRACSYN_EN                                       (0x1<<1) // Enable for loading freq_offset sr as the offset to establish nominal frequency Freq_offset to implement SSC on
13106     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_FRACSYN_EN_SHIFT                                 1
13107     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_SSC_EN                                           (0x1<<2) // Enables SSC generation
13108     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_SSC_EN_SHIFT                                     2
13109     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_UNUSED_0                                         (0x1f<<3) // reserved
13110     #define PHY_NW_IP_REG_CMU_R0_RPLL_SSC_GEN_CTRL5_UNUSED_0_SHIFT                                   3
13111 #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL0                                                        0x00353cUL //Access:RW   DataWidth:0x8   Used as frequency offset in SSC when ssc_gen_en=1 or  when fracsyn_en=1  Chips: K2
13112 #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL1                                                        0x003540UL //Access:RW   DataWidth:0x8   Used as frequency offset in SSC when ssc_gen_en=1 or  when fracsyn_en=1  Chips: K2
13113 #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL2                                                        0x003544UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13114     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL2_FDIV_19_16                                         (0xf<<0) // Used as frequency offset in SSC when ssc_gen_en=1 or  when fracsyn_en=1
13115     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL2_FDIV_19_16_SHIFT                                   0
13116     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL2_UNUSED_0                                           (0xf<<4) // reserved
13117     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL2_UNUSED_0_SHIFT                                     4
13118 #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3                                                        0x003550UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13119     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_FMODE_EN                                           (0x1<<0) // enable the fracN div mode of the fracn_mod digital control block
13120     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_FMODE_EN_SHIFT                                     0
13121     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_UNUSED_0                                           (0x7f<<1) // reserved
13122     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL3_UNUSED_0_SHIFT                                     1
13123 #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4                                                        0x003554UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13124     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_NDIV                                               (0x7f<<0) // ndiv
13125     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_NDIV_SHIFT                                         0
13126     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_UNUSED_0                                           (0x1<<7) // reserved
13127     #define PHY_NW_IP_REG_CMU_R0_RPLL_FRACN_CTRL4_UNUSED_0_SHIFT                                     7
13128 #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL                                                      0x006000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13129     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN                                (0x1<<0) // RX clock loopback mode enable.   0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
13130     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT                          0
13131     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN                                (0x1<<1) // TX clock loopback mode enable.  0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
13132     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT                          1
13133     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN                                  (0x1<<2) // Far-End Analog FEA loopback mode enable.  0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
13134     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT                            2
13135     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN                                  (0x1<<3) // Near-End Analog NEA loopback mode enable.  0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
13136     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT                            3
13137     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_UNUSED_0                                         (0xf<<4) // reserved
13138     #define PHY_NW_IP_REG_LN0_TOP_AFE_LOOPBACK_CTRL_UNUSED_0_SHIFT                                   4
13139 #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1                                                         0x006088UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13140     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN                                 (0x1<<0) // Enables register control of TX data path mux in DPL
13141     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_SHIFT                           0
13142     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL                                (0x7<<1) // Select value for TX data path mux in DPL.  The corresponding mux select override enable must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4: LT/802.3 5-7: reserved
13143     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_SHIFT                          1
13144     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_TXPOLARITY                                          (0x1<<4) // TX data polarity control
13145     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT                                    4
13146     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN                               (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode.  In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
13147     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT                         5
13148     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_UNUSED_0                                            (0x3<<6) // reserved
13149     #define PHY_NW_IP_REG_LN0_TOP_DPL_TXDP_CTRL1_UNUSED_0_SHIFT                                      6
13150 #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1                                                         0x006090UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13151     #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL                                         (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
13152     #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT                                   0
13153     #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN                                      (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
13154     #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_SHIFT                                1
13155     #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_UNUSED_0                                            (0x3f<<2) // reserved
13156     #define PHY_NW_IP_REG_LN0_TOP_DPL_RXDP_CTRL1_UNUSED_0_SHIFT                                      2
13157 #define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS                                                          0x00609cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13158     #define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS_LN_OK                                                (0x1<<0) // LANE OK status
13159     #define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS_LN_OK_SHIFT                                          0
13160     #define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS_UNUSED_0                                             (0x7f<<1) // reserved
13161     #define PHY_NW_IP_REG_LN0_TOP_PHY_IF_STATUS_UNUSED_0_SHIFT                                       1
13162 #define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0                                                          0x0060e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13163     #define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0_RXVALID                                              (0x1<<0) // rxvalid status output
13164     #define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0_RXVALID_SHIFT                                        0
13165     #define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0_UNUSED_0                                             (0x7f<<1) // reserved
13166     #define PHY_NW_IP_REG_LN0_TOP_LN_STAT_CTRL0_UNUSED_0_SHIFT                                       1
13167 #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0                                                           0x0060ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13168     #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_OVR_EN                                                (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
13169     #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT                                          0
13170     #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH                                         (0x7<<1) // lnX_data_width_i override value for TX.  It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
13171     #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT                                   1
13172     #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH                                         (0x7<<4) // lnX_data_width_i override value for RX.  It takes effect when ovr_en is 1.
13173     #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT                                   4
13174     #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_UNUSED_0                                              (0x1<<7) // reserved
13175     #define PHY_NW_IP_REG_LN0_TOP_LN_CTRL_OVR0_UNUSED_0_SHIFT                                        7
13176 #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL1                                                              0x006140UL //Access:RW   DataWidth:0x8   lower 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
13177 #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL2                                                              0x006144UL //Access:RW   DataWidth:0x8   higher 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
13178 #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3                                                              0x006148UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13179     #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3_LANE_ERR                                                 (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
13180     #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3_LANE_ERR_SHIFT                                           0
13181     #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3_UNUSED_0                                                 (0x7f<<1) // reserved
13182     #define PHY_NW_IP_REG_LN0_TOP_ERR_CTRL3_UNUSED_0_SHIFT                                           1
13183 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS2                                                     0x0062fcUL //Access:R    DataWidth:0x8   Binary-coded DLPF control input to the CDR  Chips: K2
13184 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3                                                     0x006300UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13185     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8                                    (0x1<<0) // Binary-coded DLPF control input to the CDR
13186     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_SHIFT                              0
13187     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3_UNUSED_0                                        (0x7f<<1) // reserved
13188     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS3_UNUSED_0_SHIFT                                  1
13189 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4                                                     0x006304UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13190     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH                                   (0x1<<0) // Indicates that DLPF control input to CDR is too high
13191     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_SHIFT                             0
13192     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW                                    (0x1<<1) // Indicates that DLPF control input to CDR is too low
13193     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_SHIFT                              1
13194     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST                                       (0x1<<2) // CDR loss of lock indicator.  1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
13195     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_SHIFT                                 2
13196     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_UNUSED_0                                        (0x1f<<3) // reserved
13197     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS4_UNUSED_0_SHIFT                                  3
13198 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5                                                     0x006310UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13199     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5_LOCKED                                          (0x1<<0) // CDR lock indicator.  1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
13200     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT                                    0
13201     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5_UNUSED_0                                        (0x7f<<1) // reserved
13202     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_DLPF_STATUS5_UNUSED_0_SHIFT                                  1
13203 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS0                                                 0x006314UL //Access:R    DataWidth:0x8   Value of the accumulator in the CDR integral path  Chips: K2
13204 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS1                                                 0x006318UL //Access:R    DataWidth:0x8   Value of the accumulator in the CDR integral path  Chips: K2
13205 #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS2                                                 0x006320UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13206     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16                           (0xf<<0) // Value of the accumulator in the CDR integral path
13207     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_SHIFT                     0
13208     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS2_UNUSED_0                                    (0xf<<4) // reserved
13209     #define PHY_NW_IP_REG_LN0_CDR_RXCLK_INTEGRAL_STATUS2_UNUSED_0_SHIFT                              4
13210 #define PHY_NW_IP_REG_LN0_ANEG_CFG10                                                                 0x006628UL //Access:RW   DataWidth:0x8   Seed provided to the transmit nonce generator polynomial  Chips: K2
13211 #define PHY_NW_IP_REG_LN0_ANEG_CFG11                                                                 0x00662cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13212     #define PHY_NW_IP_REG_LN0_ANEG_CFG11_PSEUDO_SEL                                                  (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
13213     #define PHY_NW_IP_REG_LN0_ANEG_CFG11_PSEUDO_SEL_SHIFT                                            0
13214     #define PHY_NW_IP_REG_LN0_ANEG_CFG11_UNUSED_0                                                    (0x7f<<1) // reserved
13215     #define PHY_NW_IP_REG_LN0_ANEG_CFG11_UNUSED_0_SHIFT                                              1
13216 #define PHY_NW_IP_REG_LN0_ANEG_CTRL0                                                                 0x006630UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13217     #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_AUTONEG_RESTART                                             (0x1<<0) // Restarts AN that is already in progress or otherwise completed.  Reset is triggered by rising edge of this signal.  Not self clearing.
13218     #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_AUTONEG_RESTART_SHIFT                                       0
13219     #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_UNUSED_0                                                    (0x7f<<1) // reserved
13220     #define PHY_NW_IP_REG_LN0_ANEG_CTRL0_UNUSED_0_SHIFT                                              1
13221 #define PHY_NW_IP_REG_LN0_ANEG_STATUS0                                                               0x006640UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13222     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LP_AUTONEG_ABLE                                           (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
13223     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LP_AUTONEG_ABLE_SHIFT                                     0
13224     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_UNUSED_0                                                  (0x1<<1) // reserved
13225     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_UNUSED_0_SHIFT                                            1
13226     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LINK_STATUS                                               (0x1<<2) // Local link Status.  When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
13227     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_LINK_STATUS_SHIFT                                         2
13228     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_ABILITY                                           (0x1<<3) // Autoneg ability.  When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation.  When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
13229     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_ABILITY_SHIFT                                     3
13230     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_REMOTE_FAULT                                      (0x1<<4) // Remote Fault
13231     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_SHIFT                                4
13232     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_COMPLETE                                          (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
13233     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_AUTONEG_COMPLETE_SHIFT                                    5
13234     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_UNUSED_1                                                  (0x3<<6) // reserved
13235     #define PHY_NW_IP_REG_LN0_ANEG_STATUS0_UNUSED_1_SHIFT                                            6
13236 #define PHY_NW_IP_REG_LN0_ANEG_STATUS1                                                               0x006644UL //Access:W    DataWidth:0x8   Multi Field Register.  Chips: K2
13237     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PAGE_RX                                                   (0x1<<0) // Page Received.   To clear it, write 1 to it.
13238     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PAGE_RX_SHIFT                                             0
13239     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_AN_LINK_GOOD                                              (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
13240     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_AN_LINK_GOOD_SHIFT                                        1
13241     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PARALLEL_DET_FAULT                                        (0x1<<2) // Autoneg Parallel Detection Fault.  Write 1 to clear it.
13242     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_PARALLEL_DET_FAULT_SHIFT                                  2
13243     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_NP_LOADED                                                 (0x1<<3) // mr_np_loaded status.
13244     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_NP_LOADED_SHIFT                                           3
13245     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_UNUSED_0                                                  (0xf<<4) // reserved
13246     #define PHY_NW_IP_REG_LN0_ANEG_STATUS1_UNUSED_0_SHIFT                                            4
13247 #define PHY_NW_IP_REG_LN0_ANEG_STATUS_DBG0                                                           0x006650UL //Access:R    DataWidth:0x8   One-hot sticky capture of AN FSM states.  Bits 7-0  Chips: K2
13248 #define PHY_NW_IP_REG_LN0_ANEG_STATUS_DBG1                                                           0x006654UL //Access:R    DataWidth:0x8   One-hot sticky capture of AN FSM states.  Bits 15-8  Chips: K2
13249 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0                                                            0x006660UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13250     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_SELECTOR                                               (0x1f<<0) // technology Select Field
13251     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_SELECTOR_SHIFT                                         0
13252     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0                                       (0x7<<5) // Echoed Nonce Field bits 2-0.  AN controller generates it.
13253     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_SHIFT                                 5
13254 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1                                                            0x006664UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13255     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3                                       (0x3<<0) // Echoed Nonce Field bits 4-3.    AN controller generates it.
13256     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_SHIFT                                 0
13257     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_PAUSE                                                  (0x1<<2) // Pause advertised ability
13258     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_PAUSE_SHIFT                                            2
13259     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ASM_DIR                                                (0x1<<3) // Pause ASM_DIR advertised ability
13260     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_ASM_DIR_SHIFT                                          3
13261     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_C2                                                     (0x1<<4) // Reserved always 0
13262     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_C2_SHIFT                                               4
13263     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_REMOTE_FAULT                                           (0x1<<5) // Remote Fault Local Device
13264     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_REMOTE_FAULT_SHIFT                                     5
13265     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_UNUSED_0                                               (0x1<<6) // reserved
13266     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_UNUSED_0_SHIFT                                         6
13267     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_NEXT_PAGE                                              (0x1<<7) // Next Page
13268     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE1_NEXT_PAGE_SHIFT                                        7
13269 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE2                                                            0x006668UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13270     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE2_TX_NONCE                                               (0x1f<<0) // Transmitted Nonce Field.  It is generated in hardware.
13271     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE2_TX_NONCE_SHIFT                                         0
13272     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE2_UNUSED_0                                               (0x7<<5) // reserved
13273     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE2_UNUSED_0_SHIFT                                         5
13274 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0                                                       0x00666cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13275     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX                                     (0x1<<0) // 1000Base-KX technology advertised ability
13276     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_SHIFT                               0
13277     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4                                   (0x1<<1) // 10GBase-KX4 technology advertised ability
13278     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_SHIFT                             1
13279     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR                                    (0x1<<2) // 10GBase-KR technology advertised ability
13280     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_SHIFT                              2
13281     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4                                   (0x1<<3) // 40GBase-KR4 technology advertised ability
13282     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_SHIFT                             3
13283     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4                                   (0x1<<4) // 40GBase-CR4 technology advertised ability
13284     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_SHIFT                             4
13285     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10                                 (0x1<<5) // 100GBase-CR10 technology advertised ability
13286     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_SHIFT                           5
13287     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4                                  (0x1<<6) // 100GBase-KP4 technology advertised ability
13288     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_SHIFT                            6
13289     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4                                  (0x1<<7) // 100GBase-KR4 technology advertised ability
13290     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_SHIFT                            7
13291 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1                                                       0x006670UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13292     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4                                  (0x1<<0) // 100GBase-CR4 technology advertised ability
13293     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_SHIFT                            0
13294     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S                                  (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
13295     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_SHIFT                            1
13296     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR                                    (0x1<<2) // 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
13297     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_SHIFT                              2
13298     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11                                   (0x1f<<3) // technology advertised ability Field A15-A11
13299     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_SHIFT                             3
13300 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH2                                                       0x006674UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13301     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16                                   (0x7f<<0) // technology advertised ability Field A22-A16
13302     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_SHIFT                             0
13303     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH2_UNUSED_0                                          (0x1<<7) // reserved
13304     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_TECH2_UNUSED_0_SHIFT                                    7
13305 #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC                                                         0x006678UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13306     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_ABILITY                                         (0x1<<0) // base page bit F0.  It advertises FEC ability
13307     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_ABILITY_SHIFT                                   0
13308     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_REQ                                             (0x1<<1) // base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
13309     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FEC_REQ_SHIFT                                       1
13310     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G                                      (0x1<<2) // base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
13311     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_SHIFT                                2
13312     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G                                      (0x1<<3) // base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
13313     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_SHIFT                                3
13314     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_UNUSED_0                                            (0xf<<4) // reserved
13315     #define PHY_NW_IP_REG_LN0_ANEG_BASE_PAGE_FEC_UNUSED_0_SHIFT                                      4
13316 #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0                                                             0x00667cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13317     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_KR                                          (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
13318     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_KR_SHIFT                                    0
13319     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_CR                                          (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
13320     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_25G_CR_SHIFT                                    1
13321     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_KR2                                         (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
13322     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_KR2_SHIFT                                   2
13323     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_CR2                                         (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
13324     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_ABILITY_50G_CR2_SHIFT                                   3
13325     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_ABILITY                                          (0x1<<4) // Extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
13326     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_ABILITY_SHIFT                                    4
13327     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_ABILITY                                          (0x1<<5) // Extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
13328     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_ABILITY_SHIFT                                    5
13329     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_REQ                                              (0x1<<6) // Extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
13330     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_RS_FEC_REQ_SHIFT                                        6
13331     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_REQ                                              (0x1<<7) // Extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
13332     #define PHY_NW_IP_REG_LN0_ANEG_EXTENDED0_FC_FEC_REQ_SHIFT                                        7
13333 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0                                                         0x0066a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13334     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_SELECTOR                                            (0x1f<<0) // Link partner technology Select Field
13335     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_SELECTOR_SHIFT                                      0
13336     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0                                    (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
13337     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_SHIFT                              5
13338 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1                                                         0x0066a4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13339     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3                                    (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
13340     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_SHIFT                              0
13341     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_PAUSE                                               (0x1<<2) // Link partner Pause advertised ability
13342     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_PAUSE_SHIFT                                         2
13343     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ASM_DIR                                             (0x1<<3) // Link partner Pause ASM_DIR advertised ability
13344     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ASM_DIR_SHIFT                                       3
13345     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_C2                                                  (0x1<<4) // Link partner C2 field always 0
13346     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_C2_SHIFT                                            4
13347     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_REMOTE_FAULT                                        (0x1<<5) // Link partner Remote Fault
13348     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_SHIFT                                  5
13349     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ACK                                                 (0x1<<6) // Link partner Acknowledge always 0
13350     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_ACK_SHIFT                                           6
13351     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_NEXT_PAGE                                           (0x1<<7) // Link partner Next Page
13352     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE1_NEXT_PAGE_SHIFT                                     7
13353 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE2                                                         0x0066a8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13354     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE2_TX_NONCE                                            (0x1f<<0) // Transmitted Nonce Field from Link partner
13355     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE2_TX_NONCE_SHIFT                                      0
13356     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE2_UNUSED_0                                            (0x7<<5) // reserved
13357     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE2_UNUSED_0_SHIFT                                      5
13358 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0                                                    0x0066acUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13359     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX                                  (0x1<<0) // Link partner 1000Base-KX technology advertised ability
13360     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_SHIFT                            0
13361     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4                                (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
13362     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_SHIFT                          1
13363     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR                                 (0x1<<2) // Link partner 10GBase-KR technology advertised ability
13364     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_SHIFT                           2
13365     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4                                (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
13366     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_SHIFT                          3
13367     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4                                (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
13368     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_SHIFT                          4
13369     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10                              (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
13370     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_SHIFT                        5
13371     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4                               (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
13372     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_SHIFT                         6
13373     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4                               (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
13374     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_SHIFT                         7
13375 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1                                                    0x0066b0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13376     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4                               (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
13377     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_SHIFT                         0
13378     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S                               (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
13379     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_SHIFT                         1
13380     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR                                 (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
13381     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_SHIFT                           2
13382     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11                                (0x1f<<3) // Link partner technology advertised ability Field A15-A11
13383     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_SHIFT                          3
13384 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH2                                                    0x0066b4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13385     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16                                (0x7f<<0) // Link partner technology advertised ability Field A22-A16
13386     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_SHIFT                          0
13387     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH2_UNUSED_0                                       (0x1<<7) // reserved
13388     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_TECH2_UNUSED_0_SHIFT                                 7
13389 #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC                                                      0x0066b8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13390     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY                                      (0x1<<0) // Link partner base page bit F0.  It advertises FEC ability
13391     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_SHIFT                                0
13392     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_REQ                                          (0x1<<1) // Link partner base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
13393     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_SHIFT                                    1
13394     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G                                   (0x1<<2) // Link partner base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
13395     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_SHIFT                             2
13396     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G                                   (0x1<<3) // Link partner base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
13397     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_SHIFT                             3
13398     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_UNUSED_0                                         (0xf<<4) // reserved
13399     #define PHY_NW_IP_REG_LN0_ANEG_LP_BASE_PAGE_FEC_UNUSED_0_SHIFT                                   4
13400 #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0                                                          0x0066bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13401     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_KR                                       (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
13402     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_KR_SHIFT                                 0
13403     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_CR                                       (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
13404     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_25G_CR_SHIFT                                 1
13405     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_KR2                                      (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
13406     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_SHIFT                                2
13407     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_CR2                                      (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
13408     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_SHIFT                                3
13409     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_ABILITY                                       (0x1<<4) // Link partner extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
13410     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_SHIFT                                 4
13411     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_ABILITY                                       (0x1<<5) // Link partner extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
13412     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_SHIFT                                 5
13413     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_REQ                                           (0x1<<6) // Link partner extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
13414     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_RS_FEC_REQ_SHIFT                                     6
13415     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_REQ                                           (0x1<<7) // Link partner extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
13416     #define PHY_NW_IP_REG_LN0_ANEG_LP_EXTENDED0_FC_FEC_REQ_SHIFT                                     7
13417 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0                                                      0x0066e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13418     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX                                    (0x1<<0) // Resolution result for 1000Base-KX.  It is valid when status0.an_link_good is 1.
13419     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_SHIFT                              0
13420     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4                                  (0x1<<1) // Resolution result for 10GBase-KX4.  It is valid when status0.an_link_good is 1.
13421     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_SHIFT                            1
13422     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR                                   (0x1<<2) // Resolution result for 10GBase-KR.  It is valid when status0.an_link_good is 1.
13423     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_SHIFT                             2
13424     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4                                  (0x1<<3) // Resolution result for 40GBase-KR4.  It is valid when status0.an_link_good is 1.
13425     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_SHIFT                            3
13426     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4                                  (0x1<<4) // Resolution result for 40GBase-CR4.  It is valid when status0.an_link_good is 1.
13427     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_SHIFT                            4
13428     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10                                (0x1<<5) // Resolution result for 100GBase-CR10.  It is valid when status0.an_link_good is 1.
13429     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_SHIFT                          5
13430     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4                                 (0x1<<6) // Resolution result for 100GBase-KP4.  It is valid when status0.an_link_good is 1.
13431     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_SHIFT                           6
13432     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4                                 (0x1<<7) // Resolution result for 100GBase-KR4.  It is valid when status0.an_link_good is 1.
13433     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_SHIFT                           7
13434 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1                                                      0x0066e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13435     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4                                 (0x1<<0) // Resolution result for 100GBase-CR4.  It is valid when status0.an_link_good is 1.
13436     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_SHIFT                           0
13437     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S                                 (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR.  It is valid when status0.an_link_good is 1.
13438     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_SHIFT                           1
13439     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR                                   (0x1<<2) // Resolution result for 25GBase-GR KR or CR.  It is valid when status0.an_link_good is 1.
13440     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_SHIFT                             2
13441     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR                                   (0x1<<3) // Resolution result for 25GBase-KR.  It is valid when status0.an_link_good is 1.
13442     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_SHIFT                             3
13443     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR                                   (0x1<<4) // Resolution result for 25GBase-CR4.  It is valid when status0.an_link_good is 1.
13444     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_SHIFT                             4
13445     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2                                  (0x1<<5) // Resolution result for 50GBase-KR2.  It is valid when status0.an_link_good is 1.
13446     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_SHIFT                            5
13447     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2                                  (0x1<<6) // Resolution result for 50GBase-CR2.  It is valid when status0.an_link_good is 1.
13448     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_SHIFT                            6
13449     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_UNUSED_0                                         (0x1<<7) // reserved
13450     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_TECH1_UNUSED_0_SHIFT                                   7
13451 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC                                                        0x0066e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13452     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_RS                                                 (0x1<<0) // Resolution result for Reed-Solomon FEC.  It is valid when status0.an_link_good is 1.
13453     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_RS_SHIFT                                           0
13454     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_FC                                                 (0x1<<1) // Resolution result for Firecode base page FEC.  It is valid when status0.an_link_good is 1.
13455     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_FC_SHIFT                                           1
13456     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_UNUSED_0                                           (0x3f<<2) // reserved
13457     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_FEC_UNUSED_0_SHIFT                                     2
13458 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE                                                      0x0066ecUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13459     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_RX                                               (0x1<<0) // Resolution result for RX PAUSE enable.    It is valid when status0.an_link_good is 1.
13460     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_RX_SHIFT                                         0
13461     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_TX                                               (0x1<<1) // Resolution result for TX PAUSE enable.    It is valid when status0.an_link_good is 1.
13462     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_TX_SHIFT                                         1
13463     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_UNUSED_0                                         (0x3f<<2) // reserved
13464     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_PAUSE_UNUSED_0_SHIFT                                   2
13465 #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE                                                        0x0066f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13466     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE_F664                                               (0x1<<0) // Resolution result for EEE.  It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type.  It is 0 otherwise.  It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
13467     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE_F664_SHIFT                                         0
13468     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE_UNUSED_0                                           (0x7f<<1) // reserved
13469     #define PHY_NW_IP_REG_LN0_ANEG_RESOLUTION_EEE_UNUSED_0_SHIFT                                     1
13470 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0                                                          0x0066f8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13471     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_1G_KX                                        (0x1<<0) // link_status for 1000Base-KX
13472     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_1G_KX_SHIFT                                  0
13473     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KX4                                      (0x1<<1) // link_status for 10GBase-KX4
13474     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KX4_SHIFT                                1
13475     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KR                                       (0x1<<2) // link_status for 10GBase-KR
13476     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_10G_KR_SHIFT                                 2
13477     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_KR4                                      (0x1<<3) // link_status for 40GBase-KR4
13478     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_KR4_SHIFT                                3
13479     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_CR4                                      (0x1<<4) // link_status for 40GBase-CR4
13480     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_40G_CR4_SHIFT                                4
13481     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_CR10                                    (0x1<<5) // link_status for 100GBase-CR10
13482     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_CR10_SHIFT                              5
13483     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KP4                                     (0x1<<6) // link_status for 100GBase-KP4
13484     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KP4_SHIFT                               6
13485     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KR4                                     (0x1<<7) // link_status for 100GBase-KR4
13486     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS0_ABILITY_100G_KR4_SHIFT                               7
13487 #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1                                                          0x0066fcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13488     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_100G_CR4                                     (0x1<<0) // link_status for 100GBase-CR4
13489     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_100G_CR4_SHIFT                               0
13490     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_GR                                       (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
13491     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_GR_SHIFT                                 1
13492     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_UNUSED_0                                             (0x1<<2) // reserved
13493     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_UNUSED_0_SHIFT                                       2
13494     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_KR                                       (0x1<<3) // link_status for 25GBase-KR
13495     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_KR_SHIFT                                 3
13496     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_CR                                       (0x1<<4) // link_status for 25GBase-CR4
13497     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_25G_CR_SHIFT                                 4
13498     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_KR2                                      (0x1<<5) // link_status for 50GBase-KR2
13499     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_KR2_SHIFT                                5
13500     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_CR2                                      (0x1<<6) // link_status for 50GBase-CR2
13501     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_ABILITY_50G_CR2_SHIFT                                6
13502     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_UNUSED_1                                             (0x1<<7) // reserved
13503     #define PHY_NW_IP_REG_LN0_ANEG_LINK_STATUS1_UNUSED_1_SHIFT                                       7
13504 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_AGCLOS_CTRL0                                                    0x0068c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13505     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START                                   (0xf<<0) // AGC LOS Threshold Start Value
13506     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_SHIFT                             0
13507     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_AGCLOS_CTRL0_UNUSED_0                                       (0xf<<4) // reserved
13508     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_AGCLOS_CTRL0_UNUSED_0_SHIFT                                 4
13509 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_PLE_ATT_CTRL1                                                   0x0068f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13510     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START                                 (0x7<<0) // PLE LFG Start Value
13511     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_SHIFT                           0
13512     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_PLE_ATT_CTRL1_UNUSED_0                                      (0x1f<<3) // reserved
13513     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_PLE_ATT_CTRL1_UNUSED_0_SHIFT                                3
13514 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_HFG_SQL_CTRL0                                                0x006900UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13515     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START                           (0x1f<<0) // CTLE HFG Start Value
13516     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_SHIFT                     0
13517     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_UNUSED_0                                   (0x7<<5) // reserved
13518     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_UNUSED_0_SHIFT                             5
13519 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_GN_APG_CTRL0                                                    0x0069c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13520     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START                                   (0x3<<0) // GN APG Start Value
13521     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_SHIFT                             0
13522     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_GN_APG_CTRL0_UNUSED_0                                       (0x3f<<2) // reserved
13523     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_GN_APG_CTRL0_UNUSED_0_SHIFT                                 2
13524 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL0                                                    0x006a00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13525     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START                                   (0x1f<<0) // EQ LFG Start Value
13526     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_SHIFT                             0
13527     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL0_UNUSED_0                                       (0x7<<5) // reserved
13528     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL0_UNUSED_0_SHIFT                                 5
13529 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL1                                                    0x006a04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13530     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX                               (0x1f<<0) // EQ LFG Maximum Value, inclusive
13531     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_SHIFT                         0
13532     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL1_UNUSED_0                                       (0x7<<5) // reserved
13533     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL1_UNUSED_0_SHIFT                                 5
13534 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL2                                                    0x006a08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13535     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN                               (0x1f<<0) // EQ LFG Minimum Value, inclusive
13536     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_SHIFT                         0
13537     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL2_UNUSED_0                                       (0x7<<5) // reserved
13538     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_LFG_CTRL2_UNUSED_0_SHIFT                                 5
13539 #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1                                                     0x006a64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13540     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START                                    (0xf<<0) // EQ MBF Start Value
13541     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT                              0
13542     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START                                    (0xf<<4) // EQ MBG Start Value
13543     #define PHY_NW_IP_REG_LN0_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT                              4
13544 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_PD_CTRL0                                                    0x006e00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13545     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV                                       (0xf<<0) // power down TX driver
13546     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_SHIFT                                 0
13547     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_PD_CTRL0_UNUSED_0                                       (0xf<<4) // reserved
13548     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_PD_CTRL0_UNUSED_0_SHIFT                                 4
13549 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_CTRL0                                                       0x006e08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13550     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE                                     (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
13551     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_SHIFT                               0
13552     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_CTRL0_UNUSED_0                                          (0x3f<<2) // reserved
13553     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_AFE_CTRL0_UNUSED_0_SHIFT                                    2
13554 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0                                                      0x006e40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13555     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0_REQ                                              (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1.  Set to 0 once ack is 1.
13556     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0_REQ_SHIFT                                        0
13557     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0_UNUSED_0                                         (0x7f<<1) // reserved
13558     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL0_UNUSED_0_SHIFT                                   1
13559 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0                                                    0x006e44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13560     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0_ACK                                            (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
13561     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0_ACK_SHIFT                                      0
13562     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0_UNUSED_0                                       (0x7f<<1) // reserved
13563     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_STATUS0_UNUSED_0_SHIFT                                 1
13564 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL1                                                      0x006e48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13565     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1                                          (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
13566     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_SHIFT                                    0
13567     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL1_UNUSED_0                                         (0x7<<5) // reserved
13568     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL1_UNUSED_0_SHIFT                                   5
13569 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL3                                                      0x006e50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13570     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1                                         (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
13571     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_SHIFT                                   0
13572     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL3_UNUSED_0                                         (0xf<<4) // reserved
13573     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL3_UNUSED_0_SHIFT                                   4
13574 #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL5                                                      0x006e58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13575     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING                                        (0xf<<0) // Thermometer coded control to adjust the delay between data and clock for the final 2to1 mux. Setting 00000 min delay of clock path and 11111 max delay of clock path.
13576     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_SHIFT                                  0
13577     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL5_UNUSED_0                                         (0xf<<4) // reserved
13578     #define PHY_NW_IP_REG_LN0_DRV_REFCLK_TXEQ_CTRL5_UNUSED_0_SHIFT                                   4
13579 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0                                                       0x007080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13580     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_REQ                                               (0x1<<0) // Write 1 to request a command CMD execution.  It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
13581     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_REQ_SHIFT                                         0
13582     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_CMD                                               (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
13583     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_CMD_SHIFT                                         1
13584     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_UNUSED_0                                          (0x1<<6) // reserved
13585     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_UNUSED_0_SHIFT                                    6
13586     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL                                 (0x1<<7) // Set it to 1 when changing DFE tap values
13587     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_SHIFT                           7
13588 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0                                                     0x0070a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13589     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_ACK                                             (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
13590     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_ACK_SHIFT                                       0
13591     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_UNUSED_0                                        (0x7f<<1) // reserved
13592     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_FSM_STATUS0_UNUSED_0_SHIFT                                  1
13593 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0                                                       0x0070a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13594     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN                                     (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
13595     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_SHIFT                               0
13596     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN                                     (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
13597     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_SHIFT                               1
13598     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN                                      (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
13599     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_SHIFT                                2
13600     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN                                      (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
13601     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_SHIFT                                3
13602     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP2_EN                                           (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
13603     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP2_EN_SHIFT                                     4
13604     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP3_EN                                           (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
13605     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP3_EN_SHIFT                                     5
13606     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP4_EN                                           (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
13607     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP4_EN_SHIFT                                     6
13608     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP5_EN                                           (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
13609     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_CTRL0_TAP5_EN_SHIFT                                     7
13610 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0                                             0x0070acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13611     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0                              (0x1f<<0) // Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
13612     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_SHIFT                        0
13613     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_UNUSED_0                                (0x3<<5) // reserved
13614     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_UNUSED_0_SHIFT                          5
13615     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY                     (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
13616     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT               7
13617 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1                                             0x0070b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13618     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1                              (0x1f<<0) // Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
13619     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_SHIFT                        0
13620     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_UNUSED_0                                (0x3<<5) // reserved
13621     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_UNUSED_0_SHIFT                          5
13622     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY                     (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
13623     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT               7
13624 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2                                             0x0070b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13625     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0                               (0x1f<<0) // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
13626     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_SHIFT                         0
13627     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_UNUSED_0                                (0x3<<5) // reserved
13628     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_UNUSED_0_SHIFT                          5
13629     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
13630     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT                7
13631 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3                                             0x0070b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13632     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1                               (0x1f<<0) // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
13633     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_SHIFT                         0
13634     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_UNUSED_0                                (0x3<<5) // reserved
13635     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_UNUSED_0_SHIFT                          5
13636     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
13637     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT                7
13638 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4                                             0x0070bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13639     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2                                    (0xf<<0) // Starting value for Tap 2 for Tap Adaptations
13640     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_SHIFT                              0
13641     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_UNUSED_0                                (0x7<<4) // reserved
13642     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_UNUSED_0_SHIFT                          4
13643     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
13644     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_SHIFT                     7
13645 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5                                             0x0070c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13646     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3                                    (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
13647     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_SHIFT                              0
13648     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_UNUSED_0                                (0xf<<3) // reserved
13649     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_UNUSED_0_SHIFT                          3
13650     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
13651     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_SHIFT                     7
13652 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6                                             0x0070c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13653     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4                                    (0x7<<0) // Starting value for Tap 4 for Tap Adaptations
13654     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_SHIFT                              0
13655     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_UNUSED_0                                (0xf<<3) // reserved
13656     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_UNUSED_0_SHIFT                          3
13657     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
13658     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_SHIFT                     7
13659 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7                                             0x0070c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13660     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5                                    (0x7<<0) // Starting value for Tap 5 for Tap Adaptations
13661     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_SHIFT                              0
13662     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_UNUSED_0                                (0xf<<3) // reserved
13663     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_UNUSED_0_SHIFT                          3
13664     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
13665     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_SHIFT                     7
13666 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0                                              0x0070ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13667     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0                               (0x1f<<0) // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
13668     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_SHIFT                         0
13669     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_UNUSED_0                                 (0x3<<5) // reserved
13670     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_UNUSED_0_SHIFT                           5
13671     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
13672     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT                7
13673 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1                                              0x0070d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13674     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1                               (0x1f<<0) // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
13675     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_SHIFT                         0
13676     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_UNUSED_0                                 (0x3<<5) // reserved
13677     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_UNUSED_0_SHIFT                           5
13678     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
13679     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT                7
13680 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2                                              0x0070d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13681     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0                                (0x1f<<0) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
13682     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_SHIFT                          0
13683     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_UNUSED_0                                 (0x3<<5) // reserved
13684     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_UNUSED_0_SHIFT                           5
13685     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY                       (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
13686     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT                 7
13687 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3                                              0x0070d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13688     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1                                (0x1f<<0) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
13689     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_SHIFT                          0
13690     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_UNUSED_0                                 (0x3<<5) // reserved
13691     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_UNUSED_0_SHIFT                           5
13692     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY                       (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
13693     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT                 7
13694 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4                                              0x0070dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13695     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2                                     (0xf<<0) // Loading value for Tap 2 for Tap Adaptations
13696     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_SHIFT                               0
13697     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_UNUSED_0                                 (0x7<<4) // reserved
13698     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_UNUSED_0_SHIFT                           4
13699     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
13700     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_SHIFT                      7
13701 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5                                              0x0070e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13702     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3                                     (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
13703     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_SHIFT                               0
13704     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_UNUSED_0                                 (0xf<<3) // reserved
13705     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_UNUSED_0_SHIFT                           3
13706     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
13707     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_SHIFT                      7
13708 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6                                              0x0070e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13709     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4                                     (0x7<<0) // Loading value for Tap 4 for Tap Adaptations
13710     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_SHIFT                               0
13711     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_UNUSED_0                                 (0xf<<3) // reserved
13712     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_UNUSED_0_SHIFT                           3
13713     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
13714     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_SHIFT                      7
13715 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7                                              0x0070e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13716     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5                                     (0x7<<0) // Loading value for Tap 5 for Tap Adaptations
13717     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_SHIFT                               0
13718     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_UNUSED_0                                 (0xf<<3) // reserved
13719     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_UNUSED_0_SHIFT                           3
13720     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
13721     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_SHIFT                      7
13722 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0                                                 0x0070ecUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13723     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0                                  (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap Adaptations
13724     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_SHIFT                            0
13725     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_UNUSED_0                                    (0x3<<5) // reserved
13726     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_UNUSED_0_SHIFT                              5
13727     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY                         (0x1<<7) // polarity 0 = negative, 1 = positive
13728     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_SHIFT                   7
13729 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1                                                 0x0070f0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13730     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1                                  (0x1f<<0) // binary  value for Tap 1 Even 1 Path for Tap Adaptations
13731     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_SHIFT                            0
13732     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_UNUSED_0                                    (0x3<<5) // reserved
13733     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_UNUSED_0_SHIFT                              5
13734     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY                         (0x1<<7) // polarity 0 = negative, 1 = positive
13735     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_SHIFT                   7
13736 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2                                                 0x0070f4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13737     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0                                   (0x1f<<0) // binary  value for Tap 1 Odd 0 Path for Tap Adaptations
13738     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_SHIFT                             0
13739     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_UNUSED_0                                    (0x3<<5) // reserved
13740     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_UNUSED_0_SHIFT                              5
13741     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY                          (0x1<<7) // polarity 0 = negative, 1 = positive
13742     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_SHIFT                    7
13743 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3                                                 0x0070f8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13744     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1                                   (0x1f<<0) // binary  value for Tap 1 Odd 1 Path for Tap Adaptations
13745     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_SHIFT                             0
13746     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_UNUSED_0                                    (0x3<<5) // reserved
13747     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_UNUSED_0_SHIFT                              5
13748     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY                          (0x1<<7) // polarity 0 = negative, 1 = positive
13749     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_SHIFT                    7
13750 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4                                                 0x0070fcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13751     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2                                        (0xf<<0) // binary  value for Tap 2 for Tap Adaptations
13752     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_SHIFT                                  0
13753     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_UNUSED_0                                    (0x7<<4) // reserved
13754     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_UNUSED_0_SHIFT                              4
13755     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
13756     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_SHIFT                         7
13757 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5                                                 0x007100UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13758     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3                                        (0x7<<0) // binary  value for Tap 3 for Tap Adaptations
13759     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_SHIFT                                  0
13760     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_UNUSED_0                                    (0xf<<3) // reserved
13761     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_UNUSED_0_SHIFT                              3
13762     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
13763     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_SHIFT                         7
13764 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6                                                 0x007104UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13765     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4                                        (0x7<<0) // binary  value for Tap 4 for Tap Adaptations
13766     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_SHIFT                                  0
13767     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_UNUSED_0                                    (0xf<<3) // reserved
13768     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_UNUSED_0_SHIFT                              3
13769     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
13770     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_SHIFT                         7
13771 #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7                                                 0x007108UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13772     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5                                        (0x7<<0) // binary  value for Tap 5 for Tap Adaptations
13773     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_SHIFT                                  0
13774     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_UNUSED_0                                    (0xf<<3) // reserved
13775     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_UNUSED_0_SHIFT                              3
13776     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
13777     #define PHY_NW_IP_REG_LN0_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_SHIFT                         7
13778 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL                                                    0x007400UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13779     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL                                (0x1<<0) // Enables analog LOS offset calibration circuits.
13780     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_SHIFT                          0
13781     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL_UNUSED_0                                       (0x7f<<1) // reserved
13782     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_AFE_CAL_CTRL_UNUSED_0_SHIFT                                 1
13783 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0                                                0x00740cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13784     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0_EN                                         (0x1<<0) // Enables the run-length detection digital LOS filter.
13785     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_SHIFT                                   0
13786     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0_UNUSED_0                                   (0x7f<<1) // reserved
13787     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL0_UNUSED_0_SHIFT                             1
13788 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_CTRL1                                                0x007410UL //Access:RW   DataWidth:0x8   Value of run-length which will trigger an LOS condition.  Chips: K2
13789 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0                                              0x007414UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13790     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED                                   (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
13791     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_SHIFT                             0
13792     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY                            (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
13793     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_SHIFT                      1
13794     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_UNUSED_0                                 (0x3f<<2) // reserved
13795     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_RUN_LENGTH_STATUS0_UNUSED_0_SHIFT                           2
13796 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL0                                                    0x007440UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x00.  Chips: K2
13797 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL1                                                    0x007444UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x0000.  Chips: K2
13798 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL2                                                    0x007448UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the raw analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x000000.  Chips: K2
13799 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL3                                                    0x00744cUL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
13800 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL4                                                    0x007450UL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
13801 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL5                                                    0x007454UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13802     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24                       (0x3<<0) // Same as above.
13803     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_SHIFT                 0
13804     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL5_UNUSED_0                                       (0x3f<<2) // reserved
13805     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL5_UNUSED_0_SHIFT                                 2
13806 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6                                                    0x007458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13807     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6_EN                                             (0x1<<0) // Enables the digital deglitching filter.
13808     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6_EN_SHIFT                                       0
13809     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6_UNUSED_0                                       (0x7f<<1) // reserved
13810     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_FILTER_CTRL6_UNUSED_0_SHIFT                                 1
13811 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0                                                  0x0074c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13812     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN                                     (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
13813     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_SHIFT                               0
13814     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_0                                     (0x7<<1) // reserved
13815     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_0_SHIFT                               1
13816     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE                                  (0x1<<4) // Override value for the LOS output of the digital filtering logic.
13817     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_SHIFT                            4
13818     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_1                                     (0x7<<5) // reserved
13819     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_1_SHIFT                               5
13820 #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0                                                         0x0075c4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13821     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_READY                                           (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
13822     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_READY_SHIFT                                     0
13823     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_UNUSED_0                                            (0x1<<1) // reserved
13824     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_UNUSED_0_SHIFT                                      1
13825     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS                                                 (0x1<<2) // The filtered LOS signal value.
13826     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_SHIFT                                           2
13827     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_RAW                                             (0x1<<3) // The unfiltered LOS signal value.
13828     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_RAW_SHIFT                                       3
13829     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_NO_EII                                          (0x1<<4) // The filtered LOS signal value before EII override logic.
13830     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_LOS_NO_EII_SHIFT                                    4
13831     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_UNUSED_1                                            (0x7<<5) // reserved
13832     #define PHY_NW_IP_REG_LN0_LOS_REFCLK_STATUS0_UNUSED_1_SHIFT                                      5
13833 #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL                                                               0x007800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13834     #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_EN                                                        (0x1<<0) // Enables BIST Tx data generation.
13835     #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_EN_SHIFT                                                  0
13836     #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_PATTERN_SEL                                               (0xf<<1) // Selects the pattern to transmitted: 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP 0x9 ? MAC Tx data
13837     #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_PATTERN_SEL_SHIFT                                         1
13838     #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_UNUSED_0                                                  (0x7<<5) // reserved
13839     #define PHY_NW_IP_REG_LN0_BIST_TX_CTRL_UNUSED_0_SHIFT                                            5
13840 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0                                                          0x007818UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13841     #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0_MODE                                                 (0x3<<0) // Controls what type of error injection is used: 0x0 ? None 0x1 ? Single cycle error 0x2 ? Timer based
13842     #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0_MODE_SHIFT                                           0
13843     #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0_UNUSED_0                                             (0x3f<<2) // reserved
13844     #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL0_UNUSED_0_SHIFT                                       2
13845 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL1                                                          0x00781cUL //Access:RW   DataWidth:0x8   Number of cycles between single bit-error injection  Chips: K2
13846 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL2                                                          0x007820UL //Access:RW   DataWidth:0x8   Number of cycles between single bit-error injection  Chips: K2
13847 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL3                                                          0x007824UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
13848 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL4                                                          0x007828UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
13849 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL5                                                          0x00782cUL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
13850 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL6                                                          0x007830UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
13851 #define PHY_NW_IP_REG_LN0_BIST_TX_BER_CTRL7                                                          0x007834UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
13852 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_SHIFT_AMOUNT                                                   0x007880UL //Access:RW   DataWidth:0x8   Determines the length of the UDP.  Must be set to d160 modulus udp_length.  Chips: K2
13853 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_7_0                                                            0x007890UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13854 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_15_8                                                           0x007894UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13855 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_23_16                                                          0x007898UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13856 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_31_24                                                          0x00789cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13857 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_39_32                                                          0x0078a0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13858 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_47_40                                                          0x0078a4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13859 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_55_48                                                          0x0078a8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13860 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_63_56                                                          0x0078acUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13861 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_71_64                                                          0x0078b0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13862 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_79_72                                                          0x0078b4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13863 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_87_80                                                          0x0078b8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13864 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_95_88                                                          0x0078bcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13865 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_103_96                                                         0x0078c0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13866 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_111_104                                                        0x0078c4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13867 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_119_112                                                        0x0078c8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13868 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_127_120                                                        0x0078ccUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13869 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_135_128                                                        0x0078d0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13870 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_143_136                                                        0x0078d4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13871 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_151_144                                                        0x0078d8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13872 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_159_152                                                        0x0078dcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13873 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_167_160                                                        0x0078e0UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13874 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_175_168                                                        0x0078e4UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13875 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_183_176                                                        0x0078e8UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13876 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_191_184                                                        0x0078ecUL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13877 #define PHY_NW_IP_REG_LN0_BIST_TX_UDP_199_192                                                        0x0078f0UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13878 #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL                                                               0x007a00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13879     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_EN                                                        (0x1<<0) // Enables BIST Rx data checking.
13880     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_EN_SHIFT                                                  0
13881     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_PATTERN_SEL                                               (0xf<<1) // Selects the pattern to search for: 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP 0x8 ? Auto-detect
13882     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_PATTERN_SEL_SHIFT                                         1
13883     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_CLEAR_BER                                                 (0x1<<5) // Clears the bit error counter.
13884     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_CLEAR_BER_SHIFT                                           5
13885     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_STOP_ERROR_COUNT                                          (0x1<<6) // Stops the error count from incrementing.  Can be used to read back the BER data coherently.
13886     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_STOP_ERROR_COUNT_SHIFT                                    6
13887     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA                                    (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle.  This will cause the bit error counter to be inaccurate.
13888     #define PHY_NW_IP_REG_LN0_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_SHIFT                              7
13889 #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS                                                             0x007a10UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
13890     #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_STATE                                                   (0x7<<0) // State of the BIST checker: 0x0 ? Off 0x1 ? Searching for pattern 0x2 ? Waiting for pattern lock conditions 0x3 ? Pattern lock acquired 0x4 ? Pattern lock lost
13891     #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_STATE_SHIFT                                             0
13892     #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_PATTERN_DET                                             (0xf<<3) // Indicates the pattern  detected: 0x0 ? No pattern detected 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP
13893     #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_PATTERN_DET_SHIFT                                       3
13894     #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_UNUSED_0                                                (0x1<<7) // reserved
13895     #define PHY_NW_IP_REG_LN0_BIST_RX_STATUS_UNUSED_0_SHIFT                                          7
13896 #define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS0                                                        0x007a20UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
13897 #define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS1                                                        0x007a24UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
13898 #define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS2                                                        0x007a28UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
13899 #define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS4                                                        0x007a30UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
13900 #define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS5                                                        0x007a34UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
13901 #define PHY_NW_IP_REG_LN0_BIST_RX_BER_STATUS6                                                        0x007a38UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
13902 #define PHY_NW_IP_REG_LN0_BIST_RX_LOCK_CTRL0                                                         0x007a50UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern lock.  Chips: K2
13903 #define PHY_NW_IP_REG_LN0_BIST_RX_LOCK_CTRL1                                                         0x007a54UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern lock.  Chips: K2
13904 #define PHY_NW_IP_REG_LN0_BIST_RX_LOCK_CTRL2                                                         0x007a58UL //Access:RW   DataWidth:0x8   Maximum number of errors allowed to trigger pattern lock.  Chips: K2
13905 #define PHY_NW_IP_REG_LN0_BIST_RX_LOCK_CTRL3                                                         0x007a5cUL //Access:RW   DataWidth:0x8   Maximum number of errors allowed to trigger pattern lock.  Chips: K2
13906 #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL0                                                    0x007a80UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern loss-of-lock.  Chips: K2
13907 #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL1                                                    0x007a84UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern loss-of-lock.  Chips: K2
13908 #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL2                                                    0x007a88UL //Access:RW   DataWidth:0x8   Minimum number of errors allowed to trigger pattern loss-of-lock.  Chips: K2
13909 #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL3                                                    0x007a8cUL //Access:RW   DataWidth:0x8   Minimum number of errors allowed to trigger pattern loss-of-lock.  Chips: K2
13910 #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4                                                    0x007a90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13911     #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK                              (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
13912     #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT                        0
13913     #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4_UNUSED_0                                       (0x7f<<1) // reserved
13914     #define PHY_NW_IP_REG_LN0_BIST_RX_LOSS_LOCK_CTRL4_UNUSED_0_SHIFT                                 1
13915 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_SHIFT_AMOUNT                                                   0x007ac0UL //Access:RW   DataWidth:0x8   Determines the length of the UDP.  Must be set to d160 modulus udp_length.  Chips: K2
13916 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_7_0                                                            0x007ad0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13917 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_15_8                                                           0x007ad4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13918 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_23_16                                                          0x007ad8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13919 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_31_24                                                          0x007adcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13920 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_39_32                                                          0x007ae0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13921 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_47_40                                                          0x007ae4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13922 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_55_48                                                          0x007ae8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13923 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_63_56                                                          0x007aecUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13924 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_71_64                                                          0x007af0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13925 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_79_72                                                          0x007af4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13926 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_87_80                                                          0x007af8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13927 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_95_88                                                          0x007afcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13928 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_103_96                                                         0x007b00UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13929 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_111_104                                                        0x007b04UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13930 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_119_112                                                        0x007b08UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13931 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_127_120                                                        0x007b0cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13932 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_135_128                                                        0x007b10UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13933 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_143_136                                                        0x007b14UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13934 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_151_144                                                        0x007b18UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13935 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_159_152                                                        0x007b1cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
13936 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_167_160                                                        0x007b20UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13937 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_175_168                                                        0x007b24UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13938 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_183_176                                                        0x007b28UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13939 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_191_184                                                        0x007b2cUL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13940 #define PHY_NW_IP_REG_LN0_BIST_RX_UDP_199_192                                                        0x007b30UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
13941 #define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0                                                        0x007c00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13942     #define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0_AC_COUPLED                                         (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
13943     #define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0_AC_COUPLED_SHIFT                                   0
13944     #define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0_UNUSED_0                                           (0x7f<<1) // reserved
13945     #define PHY_NW_IP_REG_LN0_FEATURE_RXTERM_CFG0_UNUSED_0_SHIFT                                     1
13946 #define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0                                                      0x007c04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13947     #define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0_EN                                               (0x1<<0) // Enables turning on the divided rxclk output
13948     #define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0_EN_SHIFT                                         0
13949     #define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0_UNUSED_0                                         (0x7f<<1) // reserved
13950     #define PHY_NW_IP_REG_LN0_FEATURE_RXCLKDIV_CFG0_UNUSED_0_SHIFT                                   1
13951 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG                                                     0x007c84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13952     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0                              (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
13953     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_SHIFT                        0
13954     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1                              (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
13955     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_SHIFT                        2
13956     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_UNUSED_0                                        (0xf<<4) // reserved
13957     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_CFG_UNUSED_0_SHIFT                                  4
13958 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG                                                 0x007c88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13959     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN                                    (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
13960     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_SHIFT                              0
13961     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_UNUSED_0                                    (0x7f<<1) // reserved
13962     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_AGC_CFG_UNUSED_0_SHIFT                              1
13963 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG                                             0x007c8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13964     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN                                (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
13965     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_SHIFT                          0
13966     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_UNUSED_0                                (0x7f<<1) // reserved
13967     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_APG_MAP_CFG_UNUSED_0_SHIFT                          1
13968 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG                                                 0x007c90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13969     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL                                   (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
13970     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_SHIFT                             0
13971     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL                                   (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
13972     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_SHIFT                             2
13973     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_UNUSED_0                                    (0xf<<4) // reserved
13974     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_LFG_CFG_UNUSED_0_SHIFT                              4
13975 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0                                                0x007c94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13976     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN                              (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
13977     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_SHIFT                        0
13978     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN                              (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
13979     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_SHIFT                        1
13980     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN                              (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
13981     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_SHIFT                        2
13982     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN                              (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
13983     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_SHIFT                        3
13984     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_UNUSED_0                                   (0xf<<4) // reserved
13985     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG0_UNUSED_0_SHIFT                             4
13986 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1                                                0x007c98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13987     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL                           (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
13988     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_SHIFT                     0
13989     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL                           (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
13990     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_SHIFT                     2
13991     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_UNUSED_0                                   (0xf<<4) // reserved
13992     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_HFG_CFG1_UNUSED_0_SHIFT                             4
13993 #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG                                                 0x007ca0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
13994     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN                                    (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
13995     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT                              0
13996     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN                                    (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
13997     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_SHIFT                              1
13998     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_UNUSED_0                                    (0x3f<<2) // reserved
13999     #define PHY_NW_IP_REG_LN0_FEATURE_CTLE_ADAPT_MBS_CFG_UNUSED_0_SHIFT                              2
14000 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG                                                            0x007cc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14001     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP1_EN                                                (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
14002     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP1_EN_SHIFT                                          0
14003     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP2_EN                                                (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
14004     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP2_EN_SHIFT                                          1
14005     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP3_EN                                                (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
14006     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP3_EN_SHIFT                                          2
14007     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP4_EN                                                (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
14008     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP4_EN_SHIFT                                          3
14009     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP5_EN                                                (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
14010     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_TAP5_EN_SHIFT                                          4
14011     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_UNUSED_0                                               (0x7<<5) // reserved
14012     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_CFG_UNUSED_0_SHIFT                                         5
14013 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG                                                      0x007cc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14014     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG_METHOD_SEL                                       (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
14015     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_SHIFT                                 0
14016     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG_UNUSED_0                                         (0x7f<<1) // reserved
14017     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_CFG_UNUSED_0_SHIFT                                   1
14018 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG                                                 0x007cc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14019     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 1
14020     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_SHIFT                          0
14021     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_UNUSED_0                                    (0x7f<<1) // reserved
14022     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP1_CFG_UNUSED_0_SHIFT                              1
14023 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG                                                 0x007cccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14024     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 2
14025     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_SHIFT                          0
14026     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_UNUSED_0                                    (0x7f<<1) // reserved
14027     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP2_CFG_UNUSED_0_SHIFT                              1
14028 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG                                                 0x007cd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14029     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 3
14030     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_SHIFT                          0
14031     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_UNUSED_0                                    (0x7f<<1) // reserved
14032     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP3_CFG_UNUSED_0_SHIFT                              1
14033 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG                                                 0x007cd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14034     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 4
14035     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_SHIFT                          0
14036     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_UNUSED_0                                    (0x7f<<1) // reserved
14037     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP4_CFG_UNUSED_0_SHIFT                              1
14038 #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG                                                 0x007cd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14039     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 5
14040     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_SHIFT                          0
14041     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_UNUSED_0                                    (0x7f<<1) // reserved
14042     #define PHY_NW_IP_REG_LN0_FEATURE_DFE_ADAPT_TAP5_CFG_UNUSED_0_SHIFT                              1
14043 #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0                                                    0x007ce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14044     #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_EN                                             (0x1<<0) // Enables continuous background adaptation
14045     #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_EN_SHIFT                                       0
14046     #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_UNUSED_0                                       (0x7f<<1) // reserved
14047     #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG0_UNUSED_0_SHIFT                                 1
14048 #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG1                                                    0x007ce4UL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
14049 #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG2                                                    0x007ce8UL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
14050 #define PHY_NW_IP_REG_LN0_FEATURE_ADAPT_CONT_CFG3                                                    0x007cecUL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
14051 #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0                                                          0x007d40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14052     #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_UNUSED_0                                             (0x1<<0) // reserved
14053     #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_UNUSED_0_SHIFT                                       0
14054     #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RX_CTRL_DIS                                          (0x1<<1) // Disables the firmware rx_ctrl MSM
14055     #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_RX_CTRL_DIS_SHIFT                                    1
14056     #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_UNUSED_1                                             (0x3f<<2) // reserved
14057     #define PHY_NW_IP_REG_LN0_FEATURE_TEST_CFG0_UNUSED_1_SHIFT                                       2
14058 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0                                                            0x007e00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14059     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING                                    (0x1<<0) // Starts link training procedure when asserted.  This is an 802.3 defined variable.
14060     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_SHIFT                              0
14061     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE                                     (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion.  This is an 802.3 defined variable.
14062     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_SHIFT                               1
14063     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_SIGNAL_DETECT                                          (0x1<<2) // Output corresponding to link training signal detect variable.  Should be set when link training has completed successfully.
14064     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_SIGNAL_DETECT_SHIFT                                    2
14065     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_CLEAR                                                  (0x1<<3) // Synchronous reset for LT Tx block.
14066     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_CLEAR_SHIFT                                            3
14067     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_UNUSED_0                                               (0xf<<4) // reserved
14068     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL0_UNUSED_0_SHIFT                                         4
14069 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL1                                                            0x007e04UL //Access:RW   DataWidth:0x8   Maximum time allowed for LT procedure.  If this is exceeded then the training_fail status will assert.  This is an 802.defined variable.  Value is encoded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width  Should be set to 500ns for 802.3 compliant timeout.  Chips: K2
14070 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL2                                                            0x007e08UL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
14071 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL3                                                            0x007e0cUL //Access:RW   DataWidth:0x8   Number of additional frames to send after both receivers have been trained and are ready.  This is an 802.3 defined variable.  Should be set between 100 and 300 for 802.3 compliance.  Chips: K2
14072 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4                                                            0x007e10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14073     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4_WAIT_TIME_8                                            (0x1<<0) // Same as above.
14074     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4_WAIT_TIME_8_SHIFT                                      0
14075     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4_UNUSED_0                                               (0x7f<<1) // reserved
14076     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL4_UNUSED_0_SHIFT                                         1
14077 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5                                                            0x007e14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14078     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_FRAME_LOCK                                             (0x1<<0) // Input to LTSM that receiver has acquired frame lock.  This value should be taken from the corresponding LT Rx register.  This  an 802.3 defined variable.
14079     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_FRAME_LOCK_SHIFT                                       0
14080     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_RX_TRAINED                                             (0x1<<1) // Input to LTSM indicating that the local receiver has completed training.  This is an 802.3 defined variable.
14081     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_RX_TRAINED_SHIFT                                       1
14082     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_REMOTE_RX_READY                                        (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready.  This value should be taken from the corresponding LT Rx registers.  This is an 802.3 defined variable.
14083     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_REMOTE_RX_READY_SHIFT                                  2
14084     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_UNUSED_0                                               (0x1f<<3) // reserved
14085     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_CTRL5_UNUSED_0_SHIFT                                         3
14086 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS                                                           0x007e40UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14087     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_FAIL                                         (0x1<<0) // Output from LTSM indicating that link training has failed.  This is an 802.3 defined variable.
14088     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_FAIL_SHIFT                                   0
14089     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING                                              (0x1<<1) // Output from LTSM indicating that link training is in progress.  This is an 802.3 defined variable.
14090     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_TRAINING_SHIFT                                        1
14091     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_SIGNAL_DETECT                                         (0x1<<2) // Output from LTSM indicating that link training is complete and successful.  This is an 802.3 defined variable.  This value is only visible internally, and is not the signal_det value driven to PHY top-level.
14092     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_SIGNAL_DETECT_SHIFT                                   2
14093     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_UNUSED_0                                              (0x1<<3) // reserved
14094     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_UNUSED_0_SHIFT                                        3
14095     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY                                    (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
14096     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_SHIFT                              4
14097     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_UNUSED_1                                              (0x7<<5) // reserved
14098     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATUS_UNUSED_1_SHIFT                                        5
14099 #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL0                                                           0x007e4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14100     #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL0_POLYNOMIAL                                            (0x7<<0) // Selects between CL72 and CL93 PRBS pattern. 0 ? CL72 1 + x^9 +x^11 1 ? CL93 1 + x^5 + x^6 + x^10 + x^11 2 ? CL93 1 + x^5 + x^6 + x^9 + x^11 3 ? CL93 1 + x^4 + x^6 + x^8 + x^11 4 ? CL93 1 + x^4 + x^6 + x^7 + x^11
14101     #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL0_POLYNOMIAL_SHIFT                                      0
14102     #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL0_UNUSED_0                                              (0x1f<<3) // reserved
14103     #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL0_UNUSED_0_SHIFT                                        3
14104 #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL1                                                           0x007e50UL //Access:RW   DataWidth:0x8   Initial PRBS LFSR seed.  This needs to be set according to the requirements in 802.3 CL72 or CL93 depending on the type of link training and lane bonding being performed.  Chips: K2
14105 #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL2                                                           0x007e54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14106     #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL2_SEED_10_8                                             (0x7<<0) // Same as above.
14107     #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL2_SEED_10_8_SHIFT                                       0
14108     #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL2_UNUSED_0                                              (0x1f<<3) // reserved
14109     #define PHY_NW_IP_REG_LN0_LT_TX_PRBS_CTRL2_UNUSED_0_SHIFT                                        3
14110 #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL                                              0x007e80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14111     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1                                     (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 ? hold 2'b01 ? increment 2'b10 ? decrement 2'b11 ? reserved
14112     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_SHIFT                               0
14113     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0                                      (0x3<<2) // Coefficient update request field for cursor tap.
14114     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_SHIFT                                2
14115     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1                                     (0x3<<4) // Coefficient update request field for pre-cursor tap.
14116     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_SHIFT                               4
14117     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE                               (0x1<<6) // Coefficient update initialize field.
14118     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_SHIFT                         6
14119     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET                                   (0x1<<7) // Coefficient update preset field.
14120     #define PHY_NW_IP_REG_LN0_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_SHIFT                             7
14121 #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL                                                   0x007e88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14122     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_P1                                          (0x3<<0) // Status report field for post-cursor tap. 2'b00 ? not updated 2'b01 ? minimum 2'b10 ? updated 2'b11 ? maximum
14123     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_P1_SHIFT                                    0
14124     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_0                                           (0x3<<2) // Status report field for cursor tap.
14125     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_0_SHIFT                                     2
14126     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_M1                                          (0x3<<4) // Status report field for pre-cursor tap.
14127     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_C_M1_SHIFT                                    4
14128     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY                                (0x1<<6) // Status report field to indicate local receiver is ready.  Should be set based on LTSM output of corresponding variable.
14129     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_SHIFT                          6
14130     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_UNUSED_0                                      (0x1<<7) // reserved
14131     #define PHY_NW_IP_REG_LN0_LT_TX_STATUS_REPORT_CTRL_UNUSED_0_SHIFT                                7
14132 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0                                                    0x007ec0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14133     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_CURRENT                                        (0x7<<0) // Current state of LTSM. 0x0 ? INITIALIZE 0x1 ? SEND_TRAINING 0x2 ? TRAIN_REMOTE 0x3 ? TRAIN_LOCAL 0x4 ? S7 0x5 ? TRAINING_FAILURE 0x6 ? LINK_READY 0x7 ? SEND_DATA
14134     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_CURRENT_SHIFT                                  0
14135     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_UNUSED_0                                       (0x1<<3) // reserved
14136     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_UNUSED_0_SHIFT                                 3
14137     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_PREV1                                          (0x7<<4) // One state previous.
14138     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_PREV1_SHIFT                                    4
14139     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_UNUSED_1                                       (0x1<<7) // reserved
14140     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS0_UNUSED_1_SHIFT                                 7
14141 #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1                                                    0x007ec4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14142     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_PREV2                                          (0x7<<0) // Two states previous.
14143     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_PREV2_SHIFT                                    0
14144     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_UNUSED_0                                       (0x1<<3) // reserved
14145     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_UNUSED_0_SHIFT                                 3
14146     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_PREV3                                          (0x7<<4) // Three states previous.
14147     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_PREV3_SHIFT                                    4
14148     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_UNUSED_1                                       (0x1<<7) // reserved
14149     #define PHY_NW_IP_REG_LN0_LT_TX_FSM_STATE_STATUS1_UNUSED_1_SHIFT                                 7
14150 #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0                                                                0x007f00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14151     #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_CLEAR                                                      (0x1<<0) // Synchronous reset for LT Rx block.
14152     #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_CLEAR_SHIFT                                                0
14153     #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_TRAINING                                                   (0x1<<1) // This is the 802.3 defined training variable.  It should be set according to corresponding LTSM output.
14154     #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_TRAINING_SHIFT                                             1
14155     #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_UNUSED_0                                                   (0x3f<<2) // reserved
14156     #define PHY_NW_IP_REG_LN0_LT_RX_CTRL0_UNUSED_0_SHIFT                                             2
14157 #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL0                                                           0x007f08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14158     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL0_POLYNOMIAL                                            (0x7<<0) // Selects between CL72 and CL93 PRBS patterns. 0 ? CL72 1 + x^9 + x^11 1 ? CL93 1 + x^5 + x^6 + x^10 + x^11 2 ? CL93 1 + x^5 + x^6 + x^9 + x^11 3 ? CL93 1 + x^4 + x^6 + x^8 + x^11 4 ? CL93 1 + x^4 + x^6 + x^7 + x^11
14159     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL0_POLYNOMIAL_SHIFT                                      0
14160     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL0_UNUSED_0                                              (0x1f<<3) // reserved
14161     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL0_UNUSED_0_SHIFT                                        3
14162 #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_CTRL1                                                           0x007f0cUL //Access:RW   DataWidth:0x8   Maximum number  of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.  Chips: K2
14163 #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0                                                         0x007f14UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14164     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_UPDATE                                              (0x1<<0) // Assertion indicates that PRBS status information has been updated.
14165     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_UPDATE_SHIFT                                        0
14166     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_LOCK                                                (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
14167     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_LOCK_SHIFT                                          1
14168     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_UNUSED_0                                            (0x3f<<2) // reserved
14169     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS0_UNUSED_0_SHIFT                                      2
14170 #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS1                                                         0x007f18UL //Access:R    DataWidth:0x8   Number of bit errors in PRBS pattern since last lock assertion event.  Chips: K2
14171 #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS2                                                         0x007f1cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14172     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8                                    (0xf<<0) // Same as above.
14173     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_SHIFT                              0
14174     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS2_UNUSED_0                                            (0xf<<4) // reserved
14175     #define PHY_NW_IP_REG_LN0_LT_RX_PRBS_STATUS2_UNUSED_0_SHIFT                                      4
14176 #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL                                                           0x007f40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14177     #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL_CLEAR_COUNT                                           (0x1<<0) // Clears both the absolute and erroneous frame counters.
14178     #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL_CLEAR_COUNT_SHIFT                                     0
14179     #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL_UNUSED_0                                              (0x7f<<1) // reserved
14180     #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_CTRL_UNUSED_0_SHIFT                                        1
14181 #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0                                                        0x007f4cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14182     #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0_FRAME_LOCK                                         (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
14183     #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0_FRAME_LOCK_SHIFT                                   0
14184     #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0_UNUSED_0                                           (0x7f<<1) // reserved
14185     #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS0_UNUSED_0_SHIFT                                     1
14186 #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS1                                                        0x007f50UL //Access:R    DataWidth:0x8   Total number of received frames since frame lock.  Chips: K2
14187 #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS2                                                        0x007f54UL //Access:R    DataWidth:0x8   Same as above.  Chips: K2
14188 #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS3                                                        0x007f58UL //Access:R    DataWidth:0x8   Total number of received frames  with a PRBS, DME, or framing error since frame lock.  Chips: K2
14189 #define PHY_NW_IP_REG_LN0_LT_RX_FRAME_STATUS4                                                        0x007f5cUL //Access:R    DataWidth:0x8   Same as above.  Chips: K2
14190 #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS                                            0x007f80UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14191     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1                                   (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 ? hold 2'b01 ? increment 2'b10 ? decrement 2'b11 ? reserved
14192     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_SHIFT                             0
14193     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0                                    (0x3<<2) // Received coefficient update request field for cursor tap.
14194     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_SHIFT                              2
14195     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1                                   (0x3<<4) // Received coefficient update request field for pre-cursor tap.
14196     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_SHIFT                             4
14197     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE                             (0x1<<6) // Received coefficient update initialize field.
14198     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_SHIFT                       6
14199     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET                                 (0x1<<7) // Received coefficient update preset field.
14200     #define PHY_NW_IP_REG_LN0_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_SHIFT                           7
14201 #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS                                                        0x007f88UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14202     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_P1                                               (0x3<<0) // Received status report field for post-cursor tap. 2'b00 ? not updated 2'b01 ? minimum 2'b10 ? updated 2'b11 ? maximum
14203     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_P1_SHIFT                                         0
14204     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_0                                                (0x3<<2) // Received status report field for cursor tap.
14205     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_0_SHIFT                                          2
14206     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_M1                                               (0x3<<4) // Received status report field for pre-cursor tap.
14207     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_C_M1_SHIFT                                         4
14208     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_LOCAL_RX_READY                                     (0x1<<6) // Received status report field to indicate local receiver is ready.
14209     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_LOCAL_RX_READY_SHIFT                               6
14210     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_DME_ERROR                                          (0x1<<7) // Indicates differential manchester decoding error.  Not sticky.
14211     #define PHY_NW_IP_REG_LN0_LT_RX_REPORT_STATUS_DME_ERROR_SHIFT                                    7
14212 #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL                                                      0x008000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14213     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN                                (0x1<<0) // RX clock loopback mode enable.   0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
14214     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT                          0
14215     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN                                (0x1<<1) // TX clock loopback mode enable.  0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
14216     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT                          1
14217     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN                                  (0x1<<2) // Far-End Analog FEA loopback mode enable.  0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
14218     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT                            2
14219     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN                                  (0x1<<3) // Near-End Analog NEA loopback mode enable.  0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
14220     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT                            3
14221     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_UNUSED_0                                         (0xf<<4) // reserved
14222     #define PHY_NW_IP_REG_LN1_TOP_AFE_LOOPBACK_CTRL_UNUSED_0_SHIFT                                   4
14223 #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1                                                         0x008088UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14224     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN                                 (0x1<<0) // Enables register control of TX data path mux in DPL
14225     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_SHIFT                           0
14226     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL                                (0x7<<1) // Select value for TX data path mux in DPL.  The corresponding mux select override enable must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4: LT/802.3 5-7: reserved
14227     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_SHIFT                          1
14228     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_TXPOLARITY                                          (0x1<<4) // TX data polarity control
14229     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT                                    4
14230     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN                               (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode.  In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
14231     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT                         5
14232     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_UNUSED_0                                            (0x3<<6) // reserved
14233     #define PHY_NW_IP_REG_LN1_TOP_DPL_TXDP_CTRL1_UNUSED_0_SHIFT                                      6
14234 #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1                                                         0x008090UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14235     #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL                                         (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
14236     #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT                                   0
14237     #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN                                      (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
14238     #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_SHIFT                                1
14239     #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_UNUSED_0                                            (0x3f<<2) // reserved
14240     #define PHY_NW_IP_REG_LN1_TOP_DPL_RXDP_CTRL1_UNUSED_0_SHIFT                                      2
14241 #define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS                                                          0x00809cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14242     #define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS_LN_OK                                                (0x1<<0) // LANE OK status
14243     #define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS_LN_OK_SHIFT                                          0
14244     #define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS_UNUSED_0                                             (0x7f<<1) // reserved
14245     #define PHY_NW_IP_REG_LN1_TOP_PHY_IF_STATUS_UNUSED_0_SHIFT                                       1
14246 #define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0                                                          0x0080e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14247     #define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0_RXVALID                                              (0x1<<0) // rxvalid status output
14248     #define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0_RXVALID_SHIFT                                        0
14249     #define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0_UNUSED_0                                             (0x7f<<1) // reserved
14250     #define PHY_NW_IP_REG_LN1_TOP_LN_STAT_CTRL0_UNUSED_0_SHIFT                                       1
14251 #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0                                                           0x0080ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14252     #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_OVR_EN                                                (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
14253     #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT                                          0
14254     #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH                                         (0x7<<1) // lnX_data_width_i override value for TX.  It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
14255     #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT                                   1
14256     #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH                                         (0x7<<4) // lnX_data_width_i override value for RX.  It takes effect when ovr_en is 1.
14257     #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT                                   4
14258     #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_UNUSED_0                                              (0x1<<7) // reserved
14259     #define PHY_NW_IP_REG_LN1_TOP_LN_CTRL_OVR0_UNUSED_0_SHIFT                                        7
14260 #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL1                                                              0x008140UL //Access:RW   DataWidth:0x8   lower 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
14261 #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL2                                                              0x008144UL //Access:RW   DataWidth:0x8   higher 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
14262 #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3                                                              0x008148UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14263     #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3_LANE_ERR                                                 (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
14264     #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3_LANE_ERR_SHIFT                                           0
14265     #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3_UNUSED_0                                                 (0x7f<<1) // reserved
14266     #define PHY_NW_IP_REG_LN1_TOP_ERR_CTRL3_UNUSED_0_SHIFT                                           1
14267 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS2                                                     0x0082fcUL //Access:R    DataWidth:0x8   Binary-coded DLPF control input to the CDR  Chips: K2
14268 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3                                                     0x008300UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14269     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8                                    (0x1<<0) // Binary-coded DLPF control input to the CDR
14270     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_SHIFT                              0
14271     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3_UNUSED_0                                        (0x7f<<1) // reserved
14272     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS3_UNUSED_0_SHIFT                                  1
14273 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4                                                     0x008304UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14274     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH                                   (0x1<<0) // Indicates that DLPF control input to CDR is too high
14275     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_SHIFT                             0
14276     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW                                    (0x1<<1) // Indicates that DLPF control input to CDR is too low
14277     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_SHIFT                              1
14278     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST                                       (0x1<<2) // CDR loss of lock indicator.  1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
14279     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_SHIFT                                 2
14280     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_UNUSED_0                                        (0x1f<<3) // reserved
14281     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS4_UNUSED_0_SHIFT                                  3
14282 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5                                                     0x008310UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14283     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5_LOCKED                                          (0x1<<0) // CDR lock indicator.  1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
14284     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT                                    0
14285     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5_UNUSED_0                                        (0x7f<<1) // reserved
14286     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_DLPF_STATUS5_UNUSED_0_SHIFT                                  1
14287 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS0                                                 0x008314UL //Access:R    DataWidth:0x8   Value of the accumulator in the CDR integral path  Chips: K2
14288 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS1                                                 0x008318UL //Access:R    DataWidth:0x8   Value of the accumulator in the CDR integral path  Chips: K2
14289 #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS2                                                 0x008320UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14290     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16                           (0xf<<0) // Value of the accumulator in the CDR integral path
14291     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_SHIFT                     0
14292     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS2_UNUSED_0                                    (0xf<<4) // reserved
14293     #define PHY_NW_IP_REG_LN1_CDR_RXCLK_INTEGRAL_STATUS2_UNUSED_0_SHIFT                              4
14294 #define PHY_NW_IP_REG_LN1_ANEG_CFG10                                                                 0x008628UL //Access:RW   DataWidth:0x8   Seed provided to the transmit nonce generator polynomial  Chips: K2
14295 #define PHY_NW_IP_REG_LN1_ANEG_CFG11                                                                 0x00862cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14296     #define PHY_NW_IP_REG_LN1_ANEG_CFG11_PSEUDO_SEL                                                  (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
14297     #define PHY_NW_IP_REG_LN1_ANEG_CFG11_PSEUDO_SEL_SHIFT                                            0
14298     #define PHY_NW_IP_REG_LN1_ANEG_CFG11_UNUSED_0                                                    (0x7f<<1) // reserved
14299     #define PHY_NW_IP_REG_LN1_ANEG_CFG11_UNUSED_0_SHIFT                                              1
14300 #define PHY_NW_IP_REG_LN1_ANEG_CTRL0                                                                 0x008630UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14301     #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_AUTONEG_RESTART                                             (0x1<<0) // Restarts AN that is already in progress or otherwise completed.  Reset is triggered by rising edge of this signal.  Not self clearing.
14302     #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_AUTONEG_RESTART_SHIFT                                       0
14303     #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_UNUSED_0                                                    (0x7f<<1) // reserved
14304     #define PHY_NW_IP_REG_LN1_ANEG_CTRL0_UNUSED_0_SHIFT                                              1
14305 #define PHY_NW_IP_REG_LN1_ANEG_STATUS0                                                               0x008640UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14306     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LP_AUTONEG_ABLE                                           (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
14307     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LP_AUTONEG_ABLE_SHIFT                                     0
14308     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_UNUSED_0                                                  (0x1<<1) // reserved
14309     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_UNUSED_0_SHIFT                                            1
14310     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LINK_STATUS                                               (0x1<<2) // Local link Status.  When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
14311     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_LINK_STATUS_SHIFT                                         2
14312     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_ABILITY                                           (0x1<<3) // Autoneg ability.  When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation.  When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
14313     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_ABILITY_SHIFT                                     3
14314     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_REMOTE_FAULT                                      (0x1<<4) // Remote Fault
14315     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_SHIFT                                4
14316     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_COMPLETE                                          (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
14317     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_AUTONEG_COMPLETE_SHIFT                                    5
14318     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_UNUSED_1                                                  (0x3<<6) // reserved
14319     #define PHY_NW_IP_REG_LN1_ANEG_STATUS0_UNUSED_1_SHIFT                                            6
14320 #define PHY_NW_IP_REG_LN1_ANEG_STATUS1                                                               0x008644UL //Access:W    DataWidth:0x8   Multi Field Register.  Chips: K2
14321     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PAGE_RX                                                   (0x1<<0) // Page Received.   To clear it, write 1 to it.
14322     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PAGE_RX_SHIFT                                             0
14323     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_AN_LINK_GOOD                                              (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
14324     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_AN_LINK_GOOD_SHIFT                                        1
14325     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PARALLEL_DET_FAULT                                        (0x1<<2) // Autoneg Parallel Detection Fault.  Write 1 to clear it.
14326     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_PARALLEL_DET_FAULT_SHIFT                                  2
14327     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_NP_LOADED                                                 (0x1<<3) // mr_np_loaded status.
14328     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_NP_LOADED_SHIFT                                           3
14329     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_UNUSED_0                                                  (0xf<<4) // reserved
14330     #define PHY_NW_IP_REG_LN1_ANEG_STATUS1_UNUSED_0_SHIFT                                            4
14331 #define PHY_NW_IP_REG_LN1_ANEG_STATUS_DBG0                                                           0x008650UL //Access:R    DataWidth:0x8   One-hot sticky capture of AN FSM states.  Bits 7-0  Chips: K2
14332 #define PHY_NW_IP_REG_LN1_ANEG_STATUS_DBG1                                                           0x008654UL //Access:R    DataWidth:0x8   One-hot sticky capture of AN FSM states.  Bits 15-8  Chips: K2
14333 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0                                                            0x008660UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14334     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_SELECTOR                                               (0x1f<<0) // technology Select Field
14335     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_SELECTOR_SHIFT                                         0
14336     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0                                       (0x7<<5) // Echoed Nonce Field bits 2-0.  AN controller generates it.
14337     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_SHIFT                                 5
14338 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1                                                            0x008664UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14339     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3                                       (0x3<<0) // Echoed Nonce Field bits 4-3.    AN controller generates it.
14340     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_SHIFT                                 0
14341     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_PAUSE                                                  (0x1<<2) // Pause advertised ability
14342     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_PAUSE_SHIFT                                            2
14343     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ASM_DIR                                                (0x1<<3) // Pause ASM_DIR advertised ability
14344     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_ASM_DIR_SHIFT                                          3
14345     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_C2                                                     (0x1<<4) // Reserved always 0
14346     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_C2_SHIFT                                               4
14347     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_REMOTE_FAULT                                           (0x1<<5) // Remote Fault Local Device
14348     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_REMOTE_FAULT_SHIFT                                     5
14349     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_UNUSED_0                                               (0x1<<6) // reserved
14350     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_UNUSED_0_SHIFT                                         6
14351     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_NEXT_PAGE                                              (0x1<<7) // Next Page
14352     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE1_NEXT_PAGE_SHIFT                                        7
14353 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE2                                                            0x008668UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14354     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE2_TX_NONCE                                               (0x1f<<0) // Transmitted Nonce Field.  It is generated in hardware.
14355     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE2_TX_NONCE_SHIFT                                         0
14356     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE2_UNUSED_0                                               (0x7<<5) // reserved
14357     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE2_UNUSED_0_SHIFT                                         5
14358 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0                                                       0x00866cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14359     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX                                     (0x1<<0) // 1000Base-KX technology advertised ability
14360     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_SHIFT                               0
14361     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4                                   (0x1<<1) // 10GBase-KX4 technology advertised ability
14362     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_SHIFT                             1
14363     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR                                    (0x1<<2) // 10GBase-KR technology advertised ability
14364     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_SHIFT                              2
14365     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4                                   (0x1<<3) // 40GBase-KR4 technology advertised ability
14366     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_SHIFT                             3
14367     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4                                   (0x1<<4) // 40GBase-CR4 technology advertised ability
14368     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_SHIFT                             4
14369     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10                                 (0x1<<5) // 100GBase-CR10 technology advertised ability
14370     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_SHIFT                           5
14371     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4                                  (0x1<<6) // 100GBase-KP4 technology advertised ability
14372     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_SHIFT                            6
14373     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4                                  (0x1<<7) // 100GBase-KR4 technology advertised ability
14374     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_SHIFT                            7
14375 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1                                                       0x008670UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14376     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4                                  (0x1<<0) // 100GBase-CR4 technology advertised ability
14377     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_SHIFT                            0
14378     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S                                  (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
14379     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_SHIFT                            1
14380     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR                                    (0x1<<2) // 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
14381     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_SHIFT                              2
14382     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11                                   (0x1f<<3) // technology advertised ability Field A15-A11
14383     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_SHIFT                             3
14384 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH2                                                       0x008674UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14385     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16                                   (0x7f<<0) // technology advertised ability Field A22-A16
14386     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_SHIFT                             0
14387     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH2_UNUSED_0                                          (0x1<<7) // reserved
14388     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_TECH2_UNUSED_0_SHIFT                                    7
14389 #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC                                                         0x008678UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14390     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_ABILITY                                         (0x1<<0) // base page bit F0.  It advertises FEC ability
14391     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_ABILITY_SHIFT                                   0
14392     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_REQ                                             (0x1<<1) // base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
14393     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FEC_REQ_SHIFT                                       1
14394     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G                                      (0x1<<2) // base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
14395     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_SHIFT                                2
14396     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G                                      (0x1<<3) // base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
14397     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_SHIFT                                3
14398     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_UNUSED_0                                            (0xf<<4) // reserved
14399     #define PHY_NW_IP_REG_LN1_ANEG_BASE_PAGE_FEC_UNUSED_0_SHIFT                                      4
14400 #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0                                                             0x00867cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14401     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_KR                                          (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
14402     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_KR_SHIFT                                    0
14403     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_CR                                          (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
14404     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_25G_CR_SHIFT                                    1
14405     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_KR2                                         (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
14406     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_KR2_SHIFT                                   2
14407     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_CR2                                         (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
14408     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_ABILITY_50G_CR2_SHIFT                                   3
14409     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_ABILITY                                          (0x1<<4) // Extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
14410     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_ABILITY_SHIFT                                    4
14411     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_ABILITY                                          (0x1<<5) // Extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
14412     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_ABILITY_SHIFT                                    5
14413     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_REQ                                              (0x1<<6) // Extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
14414     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_RS_FEC_REQ_SHIFT                                        6
14415     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_REQ                                              (0x1<<7) // Extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
14416     #define PHY_NW_IP_REG_LN1_ANEG_EXTENDED0_FC_FEC_REQ_SHIFT                                        7
14417 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0                                                         0x0086a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14418     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_SELECTOR                                            (0x1f<<0) // Link partner technology Select Field
14419     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_SELECTOR_SHIFT                                      0
14420     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0                                    (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
14421     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_SHIFT                              5
14422 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1                                                         0x0086a4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14423     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3                                    (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
14424     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_SHIFT                              0
14425     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_PAUSE                                               (0x1<<2) // Link partner Pause advertised ability
14426     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_PAUSE_SHIFT                                         2
14427     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ASM_DIR                                             (0x1<<3) // Link partner Pause ASM_DIR advertised ability
14428     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ASM_DIR_SHIFT                                       3
14429     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_C2                                                  (0x1<<4) // Link partner C2 field always 0
14430     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_C2_SHIFT                                            4
14431     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_REMOTE_FAULT                                        (0x1<<5) // Link partner Remote Fault
14432     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_SHIFT                                  5
14433     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ACK                                                 (0x1<<6) // Link partner Acknowledge always 0
14434     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_ACK_SHIFT                                           6
14435     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_NEXT_PAGE                                           (0x1<<7) // Link partner Next Page
14436     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE1_NEXT_PAGE_SHIFT                                     7
14437 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE2                                                         0x0086a8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14438     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE2_TX_NONCE                                            (0x1f<<0) // Transmitted Nonce Field from Link partner
14439     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE2_TX_NONCE_SHIFT                                      0
14440     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE2_UNUSED_0                                            (0x7<<5) // reserved
14441     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE2_UNUSED_0_SHIFT                                      5
14442 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0                                                    0x0086acUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14443     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX                                  (0x1<<0) // Link partner 1000Base-KX technology advertised ability
14444     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_SHIFT                            0
14445     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4                                (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
14446     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_SHIFT                          1
14447     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR                                 (0x1<<2) // Link partner 10GBase-KR technology advertised ability
14448     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_SHIFT                           2
14449     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4                                (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
14450     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_SHIFT                          3
14451     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4                                (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
14452     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_SHIFT                          4
14453     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10                              (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
14454     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_SHIFT                        5
14455     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4                               (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
14456     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_SHIFT                         6
14457     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4                               (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
14458     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_SHIFT                         7
14459 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1                                                    0x0086b0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14460     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4                               (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
14461     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_SHIFT                         0
14462     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S                               (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
14463     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_SHIFT                         1
14464     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR                                 (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
14465     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_SHIFT                           2
14466     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11                                (0x1f<<3) // Link partner technology advertised ability Field A15-A11
14467     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_SHIFT                          3
14468 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH2                                                    0x0086b4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14469     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16                                (0x7f<<0) // Link partner technology advertised ability Field A22-A16
14470     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_SHIFT                          0
14471     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH2_UNUSED_0                                       (0x1<<7) // reserved
14472     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_TECH2_UNUSED_0_SHIFT                                 7
14473 #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC                                                      0x0086b8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14474     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY                                      (0x1<<0) // Link partner base page bit F0.  It advertises FEC ability
14475     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_SHIFT                                0
14476     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_REQ                                          (0x1<<1) // Link partner base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
14477     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_SHIFT                                    1
14478     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G                                   (0x1<<2) // Link partner base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
14479     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_SHIFT                             2
14480     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G                                   (0x1<<3) // Link partner base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
14481     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_SHIFT                             3
14482     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_UNUSED_0                                         (0xf<<4) // reserved
14483     #define PHY_NW_IP_REG_LN1_ANEG_LP_BASE_PAGE_FEC_UNUSED_0_SHIFT                                   4
14484 #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0                                                          0x0086bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14485     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_KR                                       (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
14486     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_KR_SHIFT                                 0
14487     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_CR                                       (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
14488     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_25G_CR_SHIFT                                 1
14489     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_KR2                                      (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
14490     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_SHIFT                                2
14491     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_CR2                                      (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
14492     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_SHIFT                                3
14493     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_ABILITY                                       (0x1<<4) // Link partner extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
14494     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_SHIFT                                 4
14495     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_ABILITY                                       (0x1<<5) // Link partner extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
14496     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_SHIFT                                 5
14497     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_REQ                                           (0x1<<6) // Link partner extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
14498     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_RS_FEC_REQ_SHIFT                                     6
14499     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_REQ                                           (0x1<<7) // Link partner extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
14500     #define PHY_NW_IP_REG_LN1_ANEG_LP_EXTENDED0_FC_FEC_REQ_SHIFT                                     7
14501 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0                                                      0x0086e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14502     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX                                    (0x1<<0) // Resolution result for 1000Base-KX.  It is valid when status0.an_link_good is 1.
14503     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_SHIFT                              0
14504     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4                                  (0x1<<1) // Resolution result for 10GBase-KX4.  It is valid when status0.an_link_good is 1.
14505     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_SHIFT                            1
14506     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR                                   (0x1<<2) // Resolution result for 10GBase-KR.  It is valid when status0.an_link_good is 1.
14507     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_SHIFT                             2
14508     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4                                  (0x1<<3) // Resolution result for 40GBase-KR4.  It is valid when status0.an_link_good is 1.
14509     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_SHIFT                            3
14510     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4                                  (0x1<<4) // Resolution result for 40GBase-CR4.  It is valid when status0.an_link_good is 1.
14511     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_SHIFT                            4
14512     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10                                (0x1<<5) // Resolution result for 100GBase-CR10.  It is valid when status0.an_link_good is 1.
14513     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_SHIFT                          5
14514     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4                                 (0x1<<6) // Resolution result for 100GBase-KP4.  It is valid when status0.an_link_good is 1.
14515     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_SHIFT                           6
14516     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4                                 (0x1<<7) // Resolution result for 100GBase-KR4.  It is valid when status0.an_link_good is 1.
14517     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_SHIFT                           7
14518 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1                                                      0x0086e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14519     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4                                 (0x1<<0) // Resolution result for 100GBase-CR4.  It is valid when status0.an_link_good is 1.
14520     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_SHIFT                           0
14521     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S                                 (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR.  It is valid when status0.an_link_good is 1.
14522     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_SHIFT                           1
14523     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR                                   (0x1<<2) // Resolution result for 25GBase-GR KR or CR.  It is valid when status0.an_link_good is 1.
14524     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_SHIFT                             2
14525     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR                                   (0x1<<3) // Resolution result for 25GBase-KR.  It is valid when status0.an_link_good is 1.
14526     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_SHIFT                             3
14527     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR                                   (0x1<<4) // Resolution result for 25GBase-CR4.  It is valid when status0.an_link_good is 1.
14528     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_SHIFT                             4
14529     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2                                  (0x1<<5) // Resolution result for 50GBase-KR2.  It is valid when status0.an_link_good is 1.
14530     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_SHIFT                            5
14531     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2                                  (0x1<<6) // Resolution result for 50GBase-CR2.  It is valid when status0.an_link_good is 1.
14532     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_SHIFT                            6
14533     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_UNUSED_0                                         (0x1<<7) // reserved
14534     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_TECH1_UNUSED_0_SHIFT                                   7
14535 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC                                                        0x0086e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14536     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_RS                                                 (0x1<<0) // Resolution result for Reed-Solomon FEC.  It is valid when status0.an_link_good is 1.
14537     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_RS_SHIFT                                           0
14538     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_FC                                                 (0x1<<1) // Resolution result for Firecode base page FEC.  It is valid when status0.an_link_good is 1.
14539     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_FC_SHIFT                                           1
14540     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_UNUSED_0                                           (0x3f<<2) // reserved
14541     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_FEC_UNUSED_0_SHIFT                                     2
14542 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE                                                      0x0086ecUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14543     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_RX                                               (0x1<<0) // Resolution result for RX PAUSE enable.    It is valid when status0.an_link_good is 1.
14544     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_RX_SHIFT                                         0
14545     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_TX                                               (0x1<<1) // Resolution result for TX PAUSE enable.    It is valid when status0.an_link_good is 1.
14546     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_TX_SHIFT                                         1
14547     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_UNUSED_0                                         (0x3f<<2) // reserved
14548     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_PAUSE_UNUSED_0_SHIFT                                   2
14549 #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE                                                        0x0086f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14550     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE_F717                                               (0x1<<0) // Resolution result for EEE.  It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type.  It is 0 otherwise.  It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
14551     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE_F717_SHIFT                                         0
14552     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE_UNUSED_0                                           (0x7f<<1) // reserved
14553     #define PHY_NW_IP_REG_LN1_ANEG_RESOLUTION_EEE_UNUSED_0_SHIFT                                     1
14554 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0                                                          0x0086f8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14555     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_1G_KX                                        (0x1<<0) // link_status for 1000Base-KX
14556     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_1G_KX_SHIFT                                  0
14557     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KX4                                      (0x1<<1) // link_status for 10GBase-KX4
14558     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KX4_SHIFT                                1
14559     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KR                                       (0x1<<2) // link_status for 10GBase-KR
14560     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_10G_KR_SHIFT                                 2
14561     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_KR4                                      (0x1<<3) // link_status for 40GBase-KR4
14562     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_KR4_SHIFT                                3
14563     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_CR4                                      (0x1<<4) // link_status for 40GBase-CR4
14564     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_40G_CR4_SHIFT                                4
14565     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_CR10                                    (0x1<<5) // link_status for 100GBase-CR10
14566     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_CR10_SHIFT                              5
14567     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KP4                                     (0x1<<6) // link_status for 100GBase-KP4
14568     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KP4_SHIFT                               6
14569     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KR4                                     (0x1<<7) // link_status for 100GBase-KR4
14570     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS0_ABILITY_100G_KR4_SHIFT                               7
14571 #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1                                                          0x0086fcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14572     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_100G_CR4                                     (0x1<<0) // link_status for 100GBase-CR4
14573     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_100G_CR4_SHIFT                               0
14574     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_GR                                       (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
14575     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_GR_SHIFT                                 1
14576     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_UNUSED_0                                             (0x1<<2) // reserved
14577     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_UNUSED_0_SHIFT                                       2
14578     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_KR                                       (0x1<<3) // link_status for 25GBase-KR
14579     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_KR_SHIFT                                 3
14580     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_CR                                       (0x1<<4) // link_status for 25GBase-CR4
14581     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_25G_CR_SHIFT                                 4
14582     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_KR2                                      (0x1<<5) // link_status for 50GBase-KR2
14583     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_KR2_SHIFT                                5
14584     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_CR2                                      (0x1<<6) // link_status for 50GBase-CR2
14585     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_ABILITY_50G_CR2_SHIFT                                6
14586     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_UNUSED_1                                             (0x1<<7) // reserved
14587     #define PHY_NW_IP_REG_LN1_ANEG_LINK_STATUS1_UNUSED_1_SHIFT                                       7
14588 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_AGCLOS_CTRL0                                                    0x0088c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14589     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START                                   (0xf<<0) // AGC LOS Threshold Start Value
14590     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_SHIFT                             0
14591     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_AGCLOS_CTRL0_UNUSED_0                                       (0xf<<4) // reserved
14592     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_AGCLOS_CTRL0_UNUSED_0_SHIFT                                 4
14593 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_PLE_ATT_CTRL1                                                   0x0088f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14594     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START                                 (0x7<<0) // PLE LFG Start Value
14595     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_SHIFT                           0
14596     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_PLE_ATT_CTRL1_UNUSED_0                                      (0x1f<<3) // reserved
14597     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_PLE_ATT_CTRL1_UNUSED_0_SHIFT                                3
14598 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_HFG_SQL_CTRL0                                                0x008900UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14599     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START                           (0x1f<<0) // CTLE HFG Start Value
14600     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_SHIFT                     0
14601     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_UNUSED_0                                   (0x7<<5) // reserved
14602     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_UNUSED_0_SHIFT                             5
14603 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_GN_APG_CTRL0                                                    0x0089c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14604     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START                                   (0x3<<0) // GN APG Start Value
14605     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_SHIFT                             0
14606     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_GN_APG_CTRL0_UNUSED_0                                       (0x3f<<2) // reserved
14607     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_GN_APG_CTRL0_UNUSED_0_SHIFT                                 2
14608 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL0                                                    0x008a00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14609     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START                                   (0x1f<<0) // EQ LFG Start Value
14610     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_SHIFT                             0
14611     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL0_UNUSED_0                                       (0x7<<5) // reserved
14612     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL0_UNUSED_0_SHIFT                                 5
14613 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL1                                                    0x008a04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14614     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX                               (0x1f<<0) // EQ LFG Maximum Value, inclusive
14615     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_SHIFT                         0
14616     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL1_UNUSED_0                                       (0x7<<5) // reserved
14617     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL1_UNUSED_0_SHIFT                                 5
14618 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL2                                                    0x008a08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14619     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN                               (0x1f<<0) // EQ LFG Minimum Value, inclusive
14620     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_SHIFT                         0
14621     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL2_UNUSED_0                                       (0x7<<5) // reserved
14622     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_LFG_CTRL2_UNUSED_0_SHIFT                                 5
14623 #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1                                                     0x008a64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14624     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START                                    (0xf<<0) // EQ MBF Start Value
14625     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT                              0
14626     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START                                    (0xf<<4) // EQ MBG Start Value
14627     #define PHY_NW_IP_REG_LN1_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT                              4
14628 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_PD_CTRL0                                                    0x008e00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14629     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV                                       (0xf<<0) // power down TX driver
14630     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_SHIFT                                 0
14631     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_PD_CTRL0_UNUSED_0                                       (0xf<<4) // reserved
14632     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_PD_CTRL0_UNUSED_0_SHIFT                                 4
14633 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_CTRL0                                                       0x008e08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14634     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE                                     (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
14635     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_SHIFT                               0
14636     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_CTRL0_UNUSED_0                                          (0x3f<<2) // reserved
14637     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_AFE_CTRL0_UNUSED_0_SHIFT                                    2
14638 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0                                                      0x008e40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14639     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0_REQ                                              (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1.  Set to 0 once ack is 1.
14640     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0_REQ_SHIFT                                        0
14641     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0_UNUSED_0                                         (0x7f<<1) // reserved
14642     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL0_UNUSED_0_SHIFT                                   1
14643 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0                                                    0x008e44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14644     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0_ACK                                            (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
14645     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0_ACK_SHIFT                                      0
14646     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0_UNUSED_0                                       (0x7f<<1) // reserved
14647     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_STATUS0_UNUSED_0_SHIFT                                 1
14648 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL1                                                      0x008e48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14649     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1                                          (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
14650     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_SHIFT                                    0
14651     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL1_UNUSED_0                                         (0x7<<5) // reserved
14652     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL1_UNUSED_0_SHIFT                                   5
14653 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL3                                                      0x008e50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14654     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1                                         (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
14655     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_SHIFT                                   0
14656     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL3_UNUSED_0                                         (0xf<<4) // reserved
14657     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL3_UNUSED_0_SHIFT                                   4
14658 #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL5                                                      0x008e58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14659     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING                                        (0xf<<0) // Thermometer coded control to adjust the delay between data and clock for the final 2to1 mux. Setting 00000 min delay of clock path and 11111 max delay of clock path.
14660     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_SHIFT                                  0
14661     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL5_UNUSED_0                                         (0xf<<4) // reserved
14662     #define PHY_NW_IP_REG_LN1_DRV_REFCLK_TXEQ_CTRL5_UNUSED_0_SHIFT                                   4
14663 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0                                                       0x009080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14664     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_REQ                                               (0x1<<0) // Write 1 to request a command CMD execution.  It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
14665     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_REQ_SHIFT                                         0
14666     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_CMD                                               (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
14667     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_CMD_SHIFT                                         1
14668     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_UNUSED_0                                          (0x1<<6) // reserved
14669     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_UNUSED_0_SHIFT                                    6
14670     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL                                 (0x1<<7) // Set it to 1 when changing DFE tap values
14671     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_SHIFT                           7
14672 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0                                                     0x0090a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14673     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_ACK                                             (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
14674     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_ACK_SHIFT                                       0
14675     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_UNUSED_0                                        (0x7f<<1) // reserved
14676     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_FSM_STATUS0_UNUSED_0_SHIFT                                  1
14677 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0                                                       0x0090a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14678     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN                                     (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
14679     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_SHIFT                               0
14680     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN                                     (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
14681     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_SHIFT                               1
14682     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN                                      (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
14683     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_SHIFT                                2
14684     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN                                      (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
14685     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_SHIFT                                3
14686     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP2_EN                                           (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
14687     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP2_EN_SHIFT                                     4
14688     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP3_EN                                           (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
14689     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP3_EN_SHIFT                                     5
14690     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP4_EN                                           (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
14691     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP4_EN_SHIFT                                     6
14692     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP5_EN                                           (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
14693     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_CTRL0_TAP5_EN_SHIFT                                     7
14694 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0                                             0x0090acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14695     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0                              (0x1f<<0) // Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
14696     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_SHIFT                        0
14697     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_UNUSED_0                                (0x3<<5) // reserved
14698     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_UNUSED_0_SHIFT                          5
14699     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY                     (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
14700     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT               7
14701 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1                                             0x0090b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14702     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1                              (0x1f<<0) // Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
14703     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_SHIFT                        0
14704     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_UNUSED_0                                (0x3<<5) // reserved
14705     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_UNUSED_0_SHIFT                          5
14706     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY                     (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
14707     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT               7
14708 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2                                             0x0090b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14709     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0                               (0x1f<<0) // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
14710     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_SHIFT                         0
14711     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_UNUSED_0                                (0x3<<5) // reserved
14712     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_UNUSED_0_SHIFT                          5
14713     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
14714     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT                7
14715 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3                                             0x0090b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14716     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1                               (0x1f<<0) // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
14717     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_SHIFT                         0
14718     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_UNUSED_0                                (0x3<<5) // reserved
14719     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_UNUSED_0_SHIFT                          5
14720     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
14721     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT                7
14722 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4                                             0x0090bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14723     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2                                    (0xf<<0) // Starting value for Tap 2 for Tap Adaptations
14724     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_SHIFT                              0
14725     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_UNUSED_0                                (0x7<<4) // reserved
14726     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_UNUSED_0_SHIFT                          4
14727     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
14728     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_SHIFT                     7
14729 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5                                             0x0090c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14730     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3                                    (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
14731     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_SHIFT                              0
14732     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_UNUSED_0                                (0xf<<3) // reserved
14733     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_UNUSED_0_SHIFT                          3
14734     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
14735     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_SHIFT                     7
14736 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6                                             0x0090c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14737     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4                                    (0x7<<0) // Starting value for Tap 4 for Tap Adaptations
14738     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_SHIFT                              0
14739     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_UNUSED_0                                (0xf<<3) // reserved
14740     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_UNUSED_0_SHIFT                          3
14741     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
14742     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_SHIFT                     7
14743 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7                                             0x0090c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14744     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5                                    (0x7<<0) // Starting value for Tap 5 for Tap Adaptations
14745     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_SHIFT                              0
14746     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_UNUSED_0                                (0xf<<3) // reserved
14747     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_UNUSED_0_SHIFT                          3
14748     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
14749     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_SHIFT                     7
14750 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0                                              0x0090ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14751     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0                               (0x1f<<0) // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
14752     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_SHIFT                         0
14753     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_UNUSED_0                                 (0x3<<5) // reserved
14754     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_UNUSED_0_SHIFT                           5
14755     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
14756     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT                7
14757 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1                                              0x0090d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14758     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1                               (0x1f<<0) // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
14759     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_SHIFT                         0
14760     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_UNUSED_0                                 (0x3<<5) // reserved
14761     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_UNUSED_0_SHIFT                           5
14762     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
14763     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT                7
14764 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2                                              0x0090d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14765     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0                                (0x1f<<0) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
14766     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_SHIFT                          0
14767     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_UNUSED_0                                 (0x3<<5) // reserved
14768     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_UNUSED_0_SHIFT                           5
14769     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY                       (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
14770     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT                 7
14771 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3                                              0x0090d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14772     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1                                (0x1f<<0) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
14773     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_SHIFT                          0
14774     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_UNUSED_0                                 (0x3<<5) // reserved
14775     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_UNUSED_0_SHIFT                           5
14776     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY                       (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
14777     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT                 7
14778 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4                                              0x0090dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14779     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2                                     (0xf<<0) // Loading value for Tap 2 for Tap Adaptations
14780     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_SHIFT                               0
14781     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_UNUSED_0                                 (0x7<<4) // reserved
14782     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_UNUSED_0_SHIFT                           4
14783     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
14784     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_SHIFT                      7
14785 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5                                              0x0090e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14786     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3                                     (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
14787     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_SHIFT                               0
14788     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_UNUSED_0                                 (0xf<<3) // reserved
14789     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_UNUSED_0_SHIFT                           3
14790     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
14791     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_SHIFT                      7
14792 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6                                              0x0090e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14793     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4                                     (0x7<<0) // Loading value for Tap 4 for Tap Adaptations
14794     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_SHIFT                               0
14795     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_UNUSED_0                                 (0xf<<3) // reserved
14796     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_UNUSED_0_SHIFT                           3
14797     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
14798     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_SHIFT                      7
14799 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7                                              0x0090e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14800     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5                                     (0x7<<0) // Loading value for Tap 5 for Tap Adaptations
14801     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_SHIFT                               0
14802     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_UNUSED_0                                 (0xf<<3) // reserved
14803     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_UNUSED_0_SHIFT                           3
14804     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
14805     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_SHIFT                      7
14806 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0                                                 0x0090ecUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14807     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0                                  (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap Adaptations
14808     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_SHIFT                            0
14809     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_UNUSED_0                                    (0x3<<5) // reserved
14810     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_UNUSED_0_SHIFT                              5
14811     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY                         (0x1<<7) // polarity 0 = negative, 1 = positive
14812     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_SHIFT                   7
14813 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1                                                 0x0090f0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14814     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1                                  (0x1f<<0) // binary  value for Tap 1 Even 1 Path for Tap Adaptations
14815     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_SHIFT                            0
14816     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_UNUSED_0                                    (0x3<<5) // reserved
14817     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_UNUSED_0_SHIFT                              5
14818     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY                         (0x1<<7) // polarity 0 = negative, 1 = positive
14819     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_SHIFT                   7
14820 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2                                                 0x0090f4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14821     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0                                   (0x1f<<0) // binary  value for Tap 1 Odd 0 Path for Tap Adaptations
14822     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_SHIFT                             0
14823     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_UNUSED_0                                    (0x3<<5) // reserved
14824     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_UNUSED_0_SHIFT                              5
14825     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY                          (0x1<<7) // polarity 0 = negative, 1 = positive
14826     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_SHIFT                    7
14827 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3                                                 0x0090f8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14828     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1                                   (0x1f<<0) // binary  value for Tap 1 Odd 1 Path for Tap Adaptations
14829     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_SHIFT                             0
14830     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_UNUSED_0                                    (0x3<<5) // reserved
14831     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_UNUSED_0_SHIFT                              5
14832     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY                          (0x1<<7) // polarity 0 = negative, 1 = positive
14833     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_SHIFT                    7
14834 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4                                                 0x0090fcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14835     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2                                        (0xf<<0) // binary  value for Tap 2 for Tap Adaptations
14836     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_SHIFT                                  0
14837     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_UNUSED_0                                    (0x7<<4) // reserved
14838     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_UNUSED_0_SHIFT                              4
14839     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
14840     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_SHIFT                         7
14841 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5                                                 0x009100UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14842     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3                                        (0x7<<0) // binary  value for Tap 3 for Tap Adaptations
14843     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_SHIFT                                  0
14844     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_UNUSED_0                                    (0xf<<3) // reserved
14845     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_UNUSED_0_SHIFT                              3
14846     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
14847     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_SHIFT                         7
14848 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6                                                 0x009104UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14849     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4                                        (0x7<<0) // binary  value for Tap 4 for Tap Adaptations
14850     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_SHIFT                                  0
14851     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_UNUSED_0                                    (0xf<<3) // reserved
14852     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_UNUSED_0_SHIFT                              3
14853     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
14854     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_SHIFT                         7
14855 #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7                                                 0x009108UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14856     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5                                        (0x7<<0) // binary  value for Tap 5 for Tap Adaptations
14857     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_SHIFT                                  0
14858     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_UNUSED_0                                    (0xf<<3) // reserved
14859     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_UNUSED_0_SHIFT                              3
14860     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
14861     #define PHY_NW_IP_REG_LN1_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_SHIFT                         7
14862 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL                                                    0x009400UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14863     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL                                (0x1<<0) // Enables analog LOS offset calibration circuits.
14864     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_SHIFT                          0
14865     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL_UNUSED_0                                       (0x7f<<1) // reserved
14866     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_AFE_CAL_CTRL_UNUSED_0_SHIFT                                 1
14867 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0                                                0x00940cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14868     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0_EN                                         (0x1<<0) // Enables the run-length detection digital LOS filter.
14869     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_SHIFT                                   0
14870     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0_UNUSED_0                                   (0x7f<<1) // reserved
14871     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL0_UNUSED_0_SHIFT                             1
14872 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_CTRL1                                                0x009410UL //Access:RW   DataWidth:0x8   Value of run-length which will trigger an LOS condition.  Chips: K2
14873 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0                                              0x009414UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14874     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED                                   (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
14875     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_SHIFT                             0
14876     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY                            (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
14877     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_SHIFT                      1
14878     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_UNUSED_0                                 (0x3f<<2) // reserved
14879     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_RUN_LENGTH_STATUS0_UNUSED_0_SHIFT                           2
14880 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL0                                                    0x009440UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x00.  Chips: K2
14881 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL1                                                    0x009444UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x0000.  Chips: K2
14882 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL2                                                    0x009448UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the raw analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x000000.  Chips: K2
14883 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL3                                                    0x00944cUL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
14884 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL4                                                    0x009450UL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
14885 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL5                                                    0x009454UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14886     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24                       (0x3<<0) // Same as above.
14887     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_SHIFT                 0
14888     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL5_UNUSED_0                                       (0x3f<<2) // reserved
14889     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL5_UNUSED_0_SHIFT                                 2
14890 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6                                                    0x009458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14891     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6_EN                                             (0x1<<0) // Enables the digital deglitching filter.
14892     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6_EN_SHIFT                                       0
14893     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6_UNUSED_0                                       (0x7f<<1) // reserved
14894     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_FILTER_CTRL6_UNUSED_0_SHIFT                                 1
14895 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0                                                  0x0094c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14896     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN                                     (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
14897     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_SHIFT                               0
14898     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_0                                     (0x7<<1) // reserved
14899     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_0_SHIFT                               1
14900     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE                                  (0x1<<4) // Override value for the LOS output of the digital filtering logic.
14901     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_SHIFT                            4
14902     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_1                                     (0x7<<5) // reserved
14903     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_1_SHIFT                               5
14904 #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0                                                         0x0095c4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14905     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_READY                                           (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
14906     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_READY_SHIFT                                     0
14907     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_UNUSED_0                                            (0x1<<1) // reserved
14908     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_UNUSED_0_SHIFT                                      1
14909     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS                                                 (0x1<<2) // The filtered LOS signal value.
14910     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_SHIFT                                           2
14911     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_RAW                                             (0x1<<3) // The unfiltered LOS signal value.
14912     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_RAW_SHIFT                                       3
14913     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_NO_EII                                          (0x1<<4) // The filtered LOS signal value before EII override logic.
14914     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_LOS_NO_EII_SHIFT                                    4
14915     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_UNUSED_1                                            (0x7<<5) // reserved
14916     #define PHY_NW_IP_REG_LN1_LOS_REFCLK_STATUS0_UNUSED_1_SHIFT                                      5
14917 #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL                                                               0x009800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14918     #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_EN                                                        (0x1<<0) // Enables BIST Tx data generation.
14919     #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_EN_SHIFT                                                  0
14920     #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_PATTERN_SEL                                               (0xf<<1) // Selects the pattern to transmitted: 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP 0x9 ? MAC Tx data
14921     #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_PATTERN_SEL_SHIFT                                         1
14922     #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_UNUSED_0                                                  (0x7<<5) // reserved
14923     #define PHY_NW_IP_REG_LN1_BIST_TX_CTRL_UNUSED_0_SHIFT                                            5
14924 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0                                                          0x009818UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14925     #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0_MODE                                                 (0x3<<0) // Controls what type of error injection is used: 0x0 ? None 0x1 ? Single cycle error 0x2 ? Timer based
14926     #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0_MODE_SHIFT                                           0
14927     #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0_UNUSED_0                                             (0x3f<<2) // reserved
14928     #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL0_UNUSED_0_SHIFT                                       2
14929 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL1                                                          0x00981cUL //Access:RW   DataWidth:0x8   Number of cycles between single bit-error injection  Chips: K2
14930 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL2                                                          0x009820UL //Access:RW   DataWidth:0x8   Number of cycles between single bit-error injection  Chips: K2
14931 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL3                                                          0x009824UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
14932 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL4                                                          0x009828UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
14933 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL5                                                          0x00982cUL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
14934 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL6                                                          0x009830UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
14935 #define PHY_NW_IP_REG_LN1_BIST_TX_BER_CTRL7                                                          0x009834UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
14936 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_SHIFT_AMOUNT                                                   0x009880UL //Access:RW   DataWidth:0x8   Determines the length of the UDP.  Must be set to d160 modulus udp_length.  Chips: K2
14937 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_7_0                                                            0x009890UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14938 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_15_8                                                           0x009894UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14939 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_23_16                                                          0x009898UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14940 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_31_24                                                          0x00989cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14941 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_39_32                                                          0x0098a0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14942 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_47_40                                                          0x0098a4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14943 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_55_48                                                          0x0098a8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14944 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_63_56                                                          0x0098acUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14945 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_71_64                                                          0x0098b0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14946 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_79_72                                                          0x0098b4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14947 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_87_80                                                          0x0098b8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14948 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_95_88                                                          0x0098bcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14949 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_103_96                                                         0x0098c0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14950 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_111_104                                                        0x0098c4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14951 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_119_112                                                        0x0098c8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14952 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_127_120                                                        0x0098ccUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14953 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_135_128                                                        0x0098d0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14954 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_143_136                                                        0x0098d4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14955 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_151_144                                                        0x0098d8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14956 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_159_152                                                        0x0098dcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
14957 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_167_160                                                        0x0098e0UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
14958 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_175_168                                                        0x0098e4UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
14959 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_183_176                                                        0x0098e8UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
14960 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_191_184                                                        0x0098ecUL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
14961 #define PHY_NW_IP_REG_LN1_BIST_TX_UDP_199_192                                                        0x0098f0UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
14962 #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL                                                               0x009a00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14963     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_EN                                                        (0x1<<0) // Enables BIST Rx data checking.
14964     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_EN_SHIFT                                                  0
14965     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_PATTERN_SEL                                               (0xf<<1) // Selects the pattern to search for: 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP 0x8 ? Auto-detect
14966     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_PATTERN_SEL_SHIFT                                         1
14967     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_CLEAR_BER                                                 (0x1<<5) // Clears the bit error counter.
14968     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_CLEAR_BER_SHIFT                                           5
14969     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_STOP_ERROR_COUNT                                          (0x1<<6) // Stops the error count from incrementing.  Can be used to read back the BER data coherently.
14970     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_STOP_ERROR_COUNT_SHIFT                                    6
14971     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA                                    (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle.  This will cause the bit error counter to be inaccurate.
14972     #define PHY_NW_IP_REG_LN1_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_SHIFT                              7
14973 #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS                                                             0x009a10UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
14974     #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_STATE                                                   (0x7<<0) // State of the BIST checker: 0x0 ? Off 0x1 ? Searching for pattern 0x2 ? Waiting for pattern lock conditions 0x3 ? Pattern lock acquired 0x4 ? Pattern lock lost
14975     #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_STATE_SHIFT                                             0
14976     #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_PATTERN_DET                                             (0xf<<3) // Indicates the pattern  detected: 0x0 ? No pattern detected 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP
14977     #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_PATTERN_DET_SHIFT                                       3
14978     #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_UNUSED_0                                                (0x1<<7) // reserved
14979     #define PHY_NW_IP_REG_LN1_BIST_RX_STATUS_UNUSED_0_SHIFT                                          7
14980 #define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS0                                                        0x009a20UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
14981 #define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS1                                                        0x009a24UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
14982 #define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS2                                                        0x009a28UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
14983 #define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS4                                                        0x009a30UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
14984 #define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS5                                                        0x009a34UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
14985 #define PHY_NW_IP_REG_LN1_BIST_RX_BER_STATUS6                                                        0x009a38UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
14986 #define PHY_NW_IP_REG_LN1_BIST_RX_LOCK_CTRL0                                                         0x009a50UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern lock.  Chips: K2
14987 #define PHY_NW_IP_REG_LN1_BIST_RX_LOCK_CTRL1                                                         0x009a54UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern lock.  Chips: K2
14988 #define PHY_NW_IP_REG_LN1_BIST_RX_LOCK_CTRL2                                                         0x009a58UL //Access:RW   DataWidth:0x8   Maximum number of errors allowed to trigger pattern lock.  Chips: K2
14989 #define PHY_NW_IP_REG_LN1_BIST_RX_LOCK_CTRL3                                                         0x009a5cUL //Access:RW   DataWidth:0x8   Maximum number of errors allowed to trigger pattern lock.  Chips: K2
14990 #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL0                                                    0x009a80UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern loss-of-lock.  Chips: K2
14991 #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL1                                                    0x009a84UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern loss-of-lock.  Chips: K2
14992 #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL2                                                    0x009a88UL //Access:RW   DataWidth:0x8   Minimum number of errors allowed to trigger pattern loss-of-lock.  Chips: K2
14993 #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL3                                                    0x009a8cUL //Access:RW   DataWidth:0x8   Minimum number of errors allowed to trigger pattern loss-of-lock.  Chips: K2
14994 #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4                                                    0x009a90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
14995     #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK                              (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
14996     #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT                        0
14997     #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4_UNUSED_0                                       (0x7f<<1) // reserved
14998     #define PHY_NW_IP_REG_LN1_BIST_RX_LOSS_LOCK_CTRL4_UNUSED_0_SHIFT                                 1
14999 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_SHIFT_AMOUNT                                                   0x009ac0UL //Access:RW   DataWidth:0x8   Determines the length of the UDP.  Must be set to d160 modulus udp_length.  Chips: K2
15000 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_7_0                                                            0x009ad0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15001 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_15_8                                                           0x009ad4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15002 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_23_16                                                          0x009ad8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15003 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_31_24                                                          0x009adcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15004 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_39_32                                                          0x009ae0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15005 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_47_40                                                          0x009ae4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15006 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_55_48                                                          0x009ae8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15007 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_63_56                                                          0x009aecUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15008 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_71_64                                                          0x009af0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15009 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_79_72                                                          0x009af4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15010 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_87_80                                                          0x009af8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15011 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_95_88                                                          0x009afcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15012 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_103_96                                                         0x009b00UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15013 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_111_104                                                        0x009b04UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15014 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_119_112                                                        0x009b08UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15015 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_127_120                                                        0x009b0cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15016 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_135_128                                                        0x009b10UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15017 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_143_136                                                        0x009b14UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15018 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_151_144                                                        0x009b18UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15019 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_159_152                                                        0x009b1cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
15020 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_167_160                                                        0x009b20UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
15021 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_175_168                                                        0x009b24UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
15022 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_183_176                                                        0x009b28UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
15023 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_191_184                                                        0x009b2cUL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
15024 #define PHY_NW_IP_REG_LN1_BIST_RX_UDP_199_192                                                        0x009b30UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
15025 #define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0                                                        0x009c00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15026     #define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0_AC_COUPLED                                         (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
15027     #define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0_AC_COUPLED_SHIFT                                   0
15028     #define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0_UNUSED_0                                           (0x7f<<1) // reserved
15029     #define PHY_NW_IP_REG_LN1_FEATURE_RXTERM_CFG0_UNUSED_0_SHIFT                                     1
15030 #define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0                                                      0x009c04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15031     #define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0_EN                                               (0x1<<0) // Enables turning on the divided rxclk output
15032     #define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0_EN_SHIFT                                         0
15033     #define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0_UNUSED_0                                         (0x7f<<1) // reserved
15034     #define PHY_NW_IP_REG_LN1_FEATURE_RXCLKDIV_CFG0_UNUSED_0_SHIFT                                   1
15035 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG                                                     0x009c84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15036     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0                              (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
15037     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_SHIFT                        0
15038     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1                              (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
15039     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_SHIFT                        2
15040     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_UNUSED_0                                        (0xf<<4) // reserved
15041     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_CFG_UNUSED_0_SHIFT                                  4
15042 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG                                                 0x009c88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15043     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN                                    (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
15044     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_SHIFT                              0
15045     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_UNUSED_0                                    (0x7f<<1) // reserved
15046     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_AGC_CFG_UNUSED_0_SHIFT                              1
15047 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG                                             0x009c8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15048     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN                                (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
15049     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_SHIFT                          0
15050     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_UNUSED_0                                (0x7f<<1) // reserved
15051     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_APG_MAP_CFG_UNUSED_0_SHIFT                          1
15052 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG                                                 0x009c90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15053     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL                                   (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
15054     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_SHIFT                             0
15055     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL                                   (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
15056     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_SHIFT                             2
15057     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_UNUSED_0                                    (0xf<<4) // reserved
15058     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_LFG_CFG_UNUSED_0_SHIFT                              4
15059 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0                                                0x009c94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15060     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN                              (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
15061     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_SHIFT                        0
15062     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN                              (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
15063     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_SHIFT                        1
15064     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN                              (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
15065     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_SHIFT                        2
15066     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN                              (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
15067     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_SHIFT                        3
15068     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_UNUSED_0                                   (0xf<<4) // reserved
15069     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG0_UNUSED_0_SHIFT                             4
15070 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1                                                0x009c98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15071     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL                           (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
15072     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_SHIFT                     0
15073     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL                           (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
15074     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_SHIFT                     2
15075     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_UNUSED_0                                   (0xf<<4) // reserved
15076     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_HFG_CFG1_UNUSED_0_SHIFT                             4
15077 #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG                                                 0x009ca0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15078     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN                                    (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
15079     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT                              0
15080     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN                                    (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
15081     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_SHIFT                              1
15082     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_UNUSED_0                                    (0x3f<<2) // reserved
15083     #define PHY_NW_IP_REG_LN1_FEATURE_CTLE_ADAPT_MBS_CFG_UNUSED_0_SHIFT                              2
15084 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG                                                            0x009cc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15085     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP1_EN                                                (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
15086     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP1_EN_SHIFT                                          0
15087     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP2_EN                                                (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
15088     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP2_EN_SHIFT                                          1
15089     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP3_EN                                                (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
15090     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP3_EN_SHIFT                                          2
15091     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP4_EN                                                (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
15092     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP4_EN_SHIFT                                          3
15093     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP5_EN                                                (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
15094     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_TAP5_EN_SHIFT                                          4
15095     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_UNUSED_0                                               (0x7<<5) // reserved
15096     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_CFG_UNUSED_0_SHIFT                                         5
15097 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG                                                      0x009cc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15098     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG_METHOD_SEL                                       (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
15099     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_SHIFT                                 0
15100     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG_UNUSED_0                                         (0x7f<<1) // reserved
15101     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_CFG_UNUSED_0_SHIFT                                   1
15102 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG                                                 0x009cc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15103     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 1
15104     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_SHIFT                          0
15105     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_UNUSED_0                                    (0x7f<<1) // reserved
15106     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP1_CFG_UNUSED_0_SHIFT                              1
15107 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG                                                 0x009cccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15108     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 2
15109     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_SHIFT                          0
15110     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_UNUSED_0                                    (0x7f<<1) // reserved
15111     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP2_CFG_UNUSED_0_SHIFT                              1
15112 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG                                                 0x009cd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15113     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 3
15114     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_SHIFT                          0
15115     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_UNUSED_0                                    (0x7f<<1) // reserved
15116     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP3_CFG_UNUSED_0_SHIFT                              1
15117 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG                                                 0x009cd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15118     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 4
15119     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_SHIFT                          0
15120     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_UNUSED_0                                    (0x7f<<1) // reserved
15121     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP4_CFG_UNUSED_0_SHIFT                              1
15122 #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG                                                 0x009cd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15123     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 5
15124     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_SHIFT                          0
15125     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_UNUSED_0                                    (0x7f<<1) // reserved
15126     #define PHY_NW_IP_REG_LN1_FEATURE_DFE_ADAPT_TAP5_CFG_UNUSED_0_SHIFT                              1
15127 #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0                                                    0x009ce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15128     #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_EN                                             (0x1<<0) // Enables continuous background adaptation
15129     #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_EN_SHIFT                                       0
15130     #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_UNUSED_0                                       (0x7f<<1) // reserved
15131     #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG0_UNUSED_0_SHIFT                                 1
15132 #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG1                                                    0x009ce4UL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
15133 #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG2                                                    0x009ce8UL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
15134 #define PHY_NW_IP_REG_LN1_FEATURE_ADAPT_CONT_CFG3                                                    0x009cecUL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
15135 #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0                                                          0x009d40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15136     #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_UNUSED_0                                             (0x1<<0) // reserved
15137     #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_UNUSED_0_SHIFT                                       0
15138     #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RX_CTRL_DIS                                          (0x1<<1) // Disables the firmware rx_ctrl MSM
15139     #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_RX_CTRL_DIS_SHIFT                                    1
15140     #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_UNUSED_1                                             (0x3f<<2) // reserved
15141     #define PHY_NW_IP_REG_LN1_FEATURE_TEST_CFG0_UNUSED_1_SHIFT                                       2
15142 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0                                                            0x009e00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15143     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING                                    (0x1<<0) // Starts link training procedure when asserted.  This is an 802.3 defined variable.
15144     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_SHIFT                              0
15145     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE                                     (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion.  This is an 802.3 defined variable.
15146     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_SHIFT                               1
15147     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_SIGNAL_DETECT                                          (0x1<<2) // Output corresponding to link training signal detect variable.  Should be set when link training has completed successfully.
15148     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_SIGNAL_DETECT_SHIFT                                    2
15149     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_CLEAR                                                  (0x1<<3) // Synchronous reset for LT Tx block.
15150     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_CLEAR_SHIFT                                            3
15151     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_UNUSED_0                                               (0xf<<4) // reserved
15152     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL0_UNUSED_0_SHIFT                                         4
15153 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL1                                                            0x009e04UL //Access:RW   DataWidth:0x8   Maximum time allowed for LT procedure.  If this is exceeded then the training_fail status will assert.  This is an 802.defined variable.  Value is encoded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width  Should be set to 500ns for 802.3 compliant timeout.  Chips: K2
15154 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL2                                                            0x009e08UL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
15155 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL3                                                            0x009e0cUL //Access:RW   DataWidth:0x8   Number of additional frames to send after both receivers have been trained and are ready.  This is an 802.3 defined variable.  Should be set between 100 and 300 for 802.3 compliance.  Chips: K2
15156 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4                                                            0x009e10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15157     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4_WAIT_TIME_8                                            (0x1<<0) // Same as above.
15158     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4_WAIT_TIME_8_SHIFT                                      0
15159     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4_UNUSED_0                                               (0x7f<<1) // reserved
15160     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL4_UNUSED_0_SHIFT                                         1
15161 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5                                                            0x009e14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15162     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_FRAME_LOCK                                             (0x1<<0) // Input to LTSM that receiver has acquired frame lock.  This value should be taken from the corresponding LT Rx register.  This  an 802.3 defined variable.
15163     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_FRAME_LOCK_SHIFT                                       0
15164     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_RX_TRAINED                                             (0x1<<1) // Input to LTSM indicating that the local receiver has completed training.  This is an 802.3 defined variable.
15165     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_RX_TRAINED_SHIFT                                       1
15166     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_REMOTE_RX_READY                                        (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready.  This value should be taken from the corresponding LT Rx registers.  This is an 802.3 defined variable.
15167     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_REMOTE_RX_READY_SHIFT                                  2
15168     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_UNUSED_0                                               (0x1f<<3) // reserved
15169     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_CTRL5_UNUSED_0_SHIFT                                         3
15170 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS                                                           0x009e40UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15171     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_FAIL                                         (0x1<<0) // Output from LTSM indicating that link training has failed.  This is an 802.3 defined variable.
15172     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_FAIL_SHIFT                                   0
15173     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING                                              (0x1<<1) // Output from LTSM indicating that link training is in progress.  This is an 802.3 defined variable.
15174     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_TRAINING_SHIFT                                        1
15175     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_SIGNAL_DETECT                                         (0x1<<2) // Output from LTSM indicating that link training is complete and successful.  This is an 802.3 defined variable.  This value is only visible internally, and is not the signal_det value driven to PHY top-level.
15176     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_SIGNAL_DETECT_SHIFT                                   2
15177     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_UNUSED_0                                              (0x1<<3) // reserved
15178     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_UNUSED_0_SHIFT                                        3
15179     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY                                    (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
15180     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_SHIFT                              4
15181     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_UNUSED_1                                              (0x7<<5) // reserved
15182     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATUS_UNUSED_1_SHIFT                                        5
15183 #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL0                                                           0x009e4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15184     #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL0_POLYNOMIAL                                            (0x7<<0) // Selects between CL72 and CL93 PRBS pattern. 0 ? CL72 1 + x^9 +x^11 1 ? CL93 1 + x^5 + x^6 + x^10 + x^11 2 ? CL93 1 + x^5 + x^6 + x^9 + x^11 3 ? CL93 1 + x^4 + x^6 + x^8 + x^11 4 ? CL93 1 + x^4 + x^6 + x^7 + x^11
15185     #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL0_POLYNOMIAL_SHIFT                                      0
15186     #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL0_UNUSED_0                                              (0x1f<<3) // reserved
15187     #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL0_UNUSED_0_SHIFT                                        3
15188 #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL1                                                           0x009e50UL //Access:RW   DataWidth:0x8   Initial PRBS LFSR seed.  This needs to be set according to the requirements in 802.3 CL72 or CL93 depending on the type of link training and lane bonding being performed.  Chips: K2
15189 #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL2                                                           0x009e54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15190     #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL2_SEED_10_8                                             (0x7<<0) // Same as above.
15191     #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL2_SEED_10_8_SHIFT                                       0
15192     #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL2_UNUSED_0                                              (0x1f<<3) // reserved
15193     #define PHY_NW_IP_REG_LN1_LT_TX_PRBS_CTRL2_UNUSED_0_SHIFT                                        3
15194 #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL                                              0x009e80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15195     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1                                     (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 ? hold 2'b01 ? increment 2'b10 ? decrement 2'b11 ? reserved
15196     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_SHIFT                               0
15197     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0                                      (0x3<<2) // Coefficient update request field for cursor tap.
15198     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_SHIFT                                2
15199     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1                                     (0x3<<4) // Coefficient update request field for pre-cursor tap.
15200     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_SHIFT                               4
15201     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE                               (0x1<<6) // Coefficient update initialize field.
15202     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_SHIFT                         6
15203     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET                                   (0x1<<7) // Coefficient update preset field.
15204     #define PHY_NW_IP_REG_LN1_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_SHIFT                             7
15205 #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL                                                   0x009e88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15206     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_P1                                          (0x3<<0) // Status report field for post-cursor tap. 2'b00 ? not updated 2'b01 ? minimum 2'b10 ? updated 2'b11 ? maximum
15207     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_P1_SHIFT                                    0
15208     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_0                                           (0x3<<2) // Status report field for cursor tap.
15209     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_0_SHIFT                                     2
15210     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_M1                                          (0x3<<4) // Status report field for pre-cursor tap.
15211     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_C_M1_SHIFT                                    4
15212     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY                                (0x1<<6) // Status report field to indicate local receiver is ready.  Should be set based on LTSM output of corresponding variable.
15213     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_SHIFT                          6
15214     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_UNUSED_0                                      (0x1<<7) // reserved
15215     #define PHY_NW_IP_REG_LN1_LT_TX_STATUS_REPORT_CTRL_UNUSED_0_SHIFT                                7
15216 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0                                                    0x009ec0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15217     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_CURRENT                                        (0x7<<0) // Current state of LTSM. 0x0 ? INITIALIZE 0x1 ? SEND_TRAINING 0x2 ? TRAIN_REMOTE 0x3 ? TRAIN_LOCAL 0x4 ? S7 0x5 ? TRAINING_FAILURE 0x6 ? LINK_READY 0x7 ? SEND_DATA
15218     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_CURRENT_SHIFT                                  0
15219     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_UNUSED_0                                       (0x1<<3) // reserved
15220     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_UNUSED_0_SHIFT                                 3
15221     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_PREV1                                          (0x7<<4) // One state previous.
15222     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_PREV1_SHIFT                                    4
15223     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_UNUSED_1                                       (0x1<<7) // reserved
15224     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS0_UNUSED_1_SHIFT                                 7
15225 #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1                                                    0x009ec4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15226     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_PREV2                                          (0x7<<0) // Two states previous.
15227     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_PREV2_SHIFT                                    0
15228     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_UNUSED_0                                       (0x1<<3) // reserved
15229     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_UNUSED_0_SHIFT                                 3
15230     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_PREV3                                          (0x7<<4) // Three states previous.
15231     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_PREV3_SHIFT                                    4
15232     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_UNUSED_1                                       (0x1<<7) // reserved
15233     #define PHY_NW_IP_REG_LN1_LT_TX_FSM_STATE_STATUS1_UNUSED_1_SHIFT                                 7
15234 #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0                                                                0x009f00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15235     #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_CLEAR                                                      (0x1<<0) // Synchronous reset for LT Rx block.
15236     #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_CLEAR_SHIFT                                                0
15237     #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_TRAINING                                                   (0x1<<1) // This is the 802.3 defined training variable.  It should be set according to corresponding LTSM output.
15238     #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_TRAINING_SHIFT                                             1
15239     #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_UNUSED_0                                                   (0x3f<<2) // reserved
15240     #define PHY_NW_IP_REG_LN1_LT_RX_CTRL0_UNUSED_0_SHIFT                                             2
15241 #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL0                                                           0x009f08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15242     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL0_POLYNOMIAL                                            (0x7<<0) // Selects between CL72 and CL93 PRBS patterns. 0 ? CL72 1 + x^9 + x^11 1 ? CL93 1 + x^5 + x^6 + x^10 + x^11 2 ? CL93 1 + x^5 + x^6 + x^9 + x^11 3 ? CL93 1 + x^4 + x^6 + x^8 + x^11 4 ? CL93 1 + x^4 + x^6 + x^7 + x^11
15243     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL0_POLYNOMIAL_SHIFT                                      0
15244     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL0_UNUSED_0                                              (0x1f<<3) // reserved
15245     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL0_UNUSED_0_SHIFT                                        3
15246 #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_CTRL1                                                           0x009f0cUL //Access:RW   DataWidth:0x8   Maximum number  of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.  Chips: K2
15247 #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0                                                         0x009f14UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15248     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_UPDATE                                              (0x1<<0) // Assertion indicates that PRBS status information has been updated.
15249     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_UPDATE_SHIFT                                        0
15250     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_LOCK                                                (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
15251     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_LOCK_SHIFT                                          1
15252     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_UNUSED_0                                            (0x3f<<2) // reserved
15253     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS0_UNUSED_0_SHIFT                                      2
15254 #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS1                                                         0x009f18UL //Access:R    DataWidth:0x8   Number of bit errors in PRBS pattern since last lock assertion event.  Chips: K2
15255 #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS2                                                         0x009f1cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15256     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8                                    (0xf<<0) // Same as above.
15257     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_SHIFT                              0
15258     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS2_UNUSED_0                                            (0xf<<4) // reserved
15259     #define PHY_NW_IP_REG_LN1_LT_RX_PRBS_STATUS2_UNUSED_0_SHIFT                                      4
15260 #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL                                                           0x009f40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15261     #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL_CLEAR_COUNT                                           (0x1<<0) // Clears both the absolute and erroneous frame counters.
15262     #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL_CLEAR_COUNT_SHIFT                                     0
15263     #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL_UNUSED_0                                              (0x7f<<1) // reserved
15264     #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_CTRL_UNUSED_0_SHIFT                                        1
15265 #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0                                                        0x009f4cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15266     #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0_FRAME_LOCK                                         (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
15267     #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0_FRAME_LOCK_SHIFT                                   0
15268     #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0_UNUSED_0                                           (0x7f<<1) // reserved
15269     #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS0_UNUSED_0_SHIFT                                     1
15270 #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS1                                                        0x009f50UL //Access:R    DataWidth:0x8   Total number of received frames since frame lock.  Chips: K2
15271 #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS2                                                        0x009f54UL //Access:R    DataWidth:0x8   Same as above.  Chips: K2
15272 #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS3                                                        0x009f58UL //Access:R    DataWidth:0x8   Total number of received frames  with a PRBS, DME, or framing error since frame lock.  Chips: K2
15273 #define PHY_NW_IP_REG_LN1_LT_RX_FRAME_STATUS4                                                        0x009f5cUL //Access:R    DataWidth:0x8   Same as above.  Chips: K2
15274 #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS                                            0x009f80UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15275     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1                                   (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 ? hold 2'b01 ? increment 2'b10 ? decrement 2'b11 ? reserved
15276     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_SHIFT                             0
15277     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0                                    (0x3<<2) // Received coefficient update request field for cursor tap.
15278     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_SHIFT                              2
15279     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1                                   (0x3<<4) // Received coefficient update request field for pre-cursor tap.
15280     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_SHIFT                             4
15281     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE                             (0x1<<6) // Received coefficient update initialize field.
15282     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_SHIFT                       6
15283     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET                                 (0x1<<7) // Received coefficient update preset field.
15284     #define PHY_NW_IP_REG_LN1_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_SHIFT                           7
15285 #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS                                                        0x009f88UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15286     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_P1                                               (0x3<<0) // Received status report field for post-cursor tap. 2'b00 ? not updated 2'b01 ? minimum 2'b10 ? updated 2'b11 ? maximum
15287     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_P1_SHIFT                                         0
15288     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_0                                                (0x3<<2) // Received status report field for cursor tap.
15289     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_0_SHIFT                                          2
15290     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_M1                                               (0x3<<4) // Received status report field for pre-cursor tap.
15291     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_C_M1_SHIFT                                         4
15292     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_LOCAL_RX_READY                                     (0x1<<6) // Received status report field to indicate local receiver is ready.
15293     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_LOCAL_RX_READY_SHIFT                               6
15294     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_DME_ERROR                                          (0x1<<7) // Indicates differential manchester decoding error.  Not sticky.
15295     #define PHY_NW_IP_REG_LN1_LT_RX_REPORT_STATUS_DME_ERROR_SHIFT                                    7
15296 #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL                                                      0x00a000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15297     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN                                (0x1<<0) // RX clock loopback mode enable.   0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
15298     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT                          0
15299     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN                                (0x1<<1) // TX clock loopback mode enable.  0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
15300     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT                          1
15301     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN                                  (0x1<<2) // Far-End Analog FEA loopback mode enable.  0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
15302     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT                            2
15303     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN                                  (0x1<<3) // Near-End Analog NEA loopback mode enable.  0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
15304     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT                            3
15305     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_UNUSED_0                                         (0xf<<4) // reserved
15306     #define PHY_NW_IP_REG_LN2_TOP_AFE_LOOPBACK_CTRL_UNUSED_0_SHIFT                                   4
15307 #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1                                                         0x00a088UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15308     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN                                 (0x1<<0) // Enables register control of TX data path mux in DPL
15309     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_SHIFT                           0
15310     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL                                (0x7<<1) // Select value for TX data path mux in DPL.  The corresponding mux select override enable must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4: LT/802.3 5-7: reserved
15311     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_SHIFT                          1
15312     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_TXPOLARITY                                          (0x1<<4) // TX data polarity control
15313     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT                                    4
15314     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN                               (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode.  In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
15315     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT                         5
15316     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_UNUSED_0                                            (0x3<<6) // reserved
15317     #define PHY_NW_IP_REG_LN2_TOP_DPL_TXDP_CTRL1_UNUSED_0_SHIFT                                      6
15318 #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1                                                         0x00a090UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15319     #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL                                         (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
15320     #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT                                   0
15321     #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN                                      (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
15322     #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_SHIFT                                1
15323     #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_UNUSED_0                                            (0x3f<<2) // reserved
15324     #define PHY_NW_IP_REG_LN2_TOP_DPL_RXDP_CTRL1_UNUSED_0_SHIFT                                      2
15325 #define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS                                                          0x00a09cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15326     #define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS_LN_OK                                                (0x1<<0) // LANE OK status
15327     #define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS_LN_OK_SHIFT                                          0
15328     #define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS_UNUSED_0                                             (0x7f<<1) // reserved
15329     #define PHY_NW_IP_REG_LN2_TOP_PHY_IF_STATUS_UNUSED_0_SHIFT                                       1
15330 #define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0                                                          0x00a0e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15331     #define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0_RXVALID                                              (0x1<<0) // rxvalid status output
15332     #define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0_RXVALID_SHIFT                                        0
15333     #define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0_UNUSED_0                                             (0x7f<<1) // reserved
15334     #define PHY_NW_IP_REG_LN2_TOP_LN_STAT_CTRL0_UNUSED_0_SHIFT                                       1
15335 #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0                                                           0x00a0ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15336     #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_OVR_EN                                                (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
15337     #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT                                          0
15338     #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH                                         (0x7<<1) // lnX_data_width_i override value for TX.  It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
15339     #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT                                   1
15340     #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH                                         (0x7<<4) // lnX_data_width_i override value for RX.  It takes effect when ovr_en is 1.
15341     #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT                                   4
15342     #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_UNUSED_0                                              (0x1<<7) // reserved
15343     #define PHY_NW_IP_REG_LN2_TOP_LN_CTRL_OVR0_UNUSED_0_SHIFT                                        7
15344 #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL1                                                              0x00a140UL //Access:RW   DataWidth:0x8   lower 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
15345 #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL2                                                              0x00a144UL //Access:RW   DataWidth:0x8   higher 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
15346 #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3                                                              0x00a148UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15347     #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3_LANE_ERR                                                 (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
15348     #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3_LANE_ERR_SHIFT                                           0
15349     #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3_UNUSED_0                                                 (0x7f<<1) // reserved
15350     #define PHY_NW_IP_REG_LN2_TOP_ERR_CTRL3_UNUSED_0_SHIFT                                           1
15351 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS2                                                     0x00a2fcUL //Access:R    DataWidth:0x8   Binary-coded DLPF control input to the CDR  Chips: K2
15352 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3                                                     0x00a300UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15353     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8                                    (0x1<<0) // Binary-coded DLPF control input to the CDR
15354     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_SHIFT                              0
15355     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3_UNUSED_0                                        (0x7f<<1) // reserved
15356     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS3_UNUSED_0_SHIFT                                  1
15357 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4                                                     0x00a304UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15358     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH                                   (0x1<<0) // Indicates that DLPF control input to CDR is too high
15359     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_SHIFT                             0
15360     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW                                    (0x1<<1) // Indicates that DLPF control input to CDR is too low
15361     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_SHIFT                              1
15362     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST                                       (0x1<<2) // CDR loss of lock indicator.  1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
15363     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_SHIFT                                 2
15364     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_UNUSED_0                                        (0x1f<<3) // reserved
15365     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS4_UNUSED_0_SHIFT                                  3
15366 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5                                                     0x00a310UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15367     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5_LOCKED                                          (0x1<<0) // CDR lock indicator.  1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
15368     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT                                    0
15369     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5_UNUSED_0                                        (0x7f<<1) // reserved
15370     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_DLPF_STATUS5_UNUSED_0_SHIFT                                  1
15371 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS0                                                 0x00a314UL //Access:R    DataWidth:0x8   Value of the accumulator in the CDR integral path  Chips: K2
15372 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS1                                                 0x00a318UL //Access:R    DataWidth:0x8   Value of the accumulator in the CDR integral path  Chips: K2
15373 #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS2                                                 0x00a320UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15374     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16                           (0xf<<0) // Value of the accumulator in the CDR integral path
15375     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_SHIFT                     0
15376     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS2_UNUSED_0                                    (0xf<<4) // reserved
15377     #define PHY_NW_IP_REG_LN2_CDR_RXCLK_INTEGRAL_STATUS2_UNUSED_0_SHIFT                              4
15378 #define PHY_NW_IP_REG_LN2_ANEG_CFG10                                                                 0x00a628UL //Access:RW   DataWidth:0x8   Seed provided to the transmit nonce generator polynomial  Chips: K2
15379 #define PHY_NW_IP_REG_LN2_ANEG_CFG11                                                                 0x00a62cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15380     #define PHY_NW_IP_REG_LN2_ANEG_CFG11_PSEUDO_SEL                                                  (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
15381     #define PHY_NW_IP_REG_LN2_ANEG_CFG11_PSEUDO_SEL_SHIFT                                            0
15382     #define PHY_NW_IP_REG_LN2_ANEG_CFG11_UNUSED_0                                                    (0x7f<<1) // reserved
15383     #define PHY_NW_IP_REG_LN2_ANEG_CFG11_UNUSED_0_SHIFT                                              1
15384 #define PHY_NW_IP_REG_LN2_ANEG_CTRL0                                                                 0x00a630UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15385     #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_AUTONEG_RESTART                                             (0x1<<0) // Restarts AN that is already in progress or otherwise completed.  Reset is triggered by rising edge of this signal.  Not self clearing.
15386     #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_AUTONEG_RESTART_SHIFT                                       0
15387     #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_UNUSED_0                                                    (0x7f<<1) // reserved
15388     #define PHY_NW_IP_REG_LN2_ANEG_CTRL0_UNUSED_0_SHIFT                                              1
15389 #define PHY_NW_IP_REG_LN2_ANEG_STATUS0                                                               0x00a640UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15390     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LP_AUTONEG_ABLE                                           (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
15391     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LP_AUTONEG_ABLE_SHIFT                                     0
15392     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_UNUSED_0                                                  (0x1<<1) // reserved
15393     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_UNUSED_0_SHIFT                                            1
15394     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LINK_STATUS                                               (0x1<<2) // Local link Status.  When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
15395     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_LINK_STATUS_SHIFT                                         2
15396     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_ABILITY                                           (0x1<<3) // Autoneg ability.  When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation.  When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
15397     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_ABILITY_SHIFT                                     3
15398     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_REMOTE_FAULT                                      (0x1<<4) // Remote Fault
15399     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_SHIFT                                4
15400     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_COMPLETE                                          (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
15401     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_AUTONEG_COMPLETE_SHIFT                                    5
15402     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_UNUSED_1                                                  (0x3<<6) // reserved
15403     #define PHY_NW_IP_REG_LN2_ANEG_STATUS0_UNUSED_1_SHIFT                                            6
15404 #define PHY_NW_IP_REG_LN2_ANEG_STATUS1                                                               0x00a644UL //Access:W    DataWidth:0x8   Multi Field Register.  Chips: K2
15405     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PAGE_RX                                                   (0x1<<0) // Page Received.   To clear it, write 1 to it.
15406     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PAGE_RX_SHIFT                                             0
15407     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_AN_LINK_GOOD                                              (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
15408     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_AN_LINK_GOOD_SHIFT                                        1
15409     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PARALLEL_DET_FAULT                                        (0x1<<2) // Autoneg Parallel Detection Fault.  Write 1 to clear it.
15410     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_PARALLEL_DET_FAULT_SHIFT                                  2
15411     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_NP_LOADED                                                 (0x1<<3) // mr_np_loaded status.
15412     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_NP_LOADED_SHIFT                                           3
15413     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_UNUSED_0                                                  (0xf<<4) // reserved
15414     #define PHY_NW_IP_REG_LN2_ANEG_STATUS1_UNUSED_0_SHIFT                                            4
15415 #define PHY_NW_IP_REG_LN2_ANEG_STATUS_DBG0                                                           0x00a650UL //Access:R    DataWidth:0x8   One-hot sticky capture of AN FSM states.  Bits 7-0  Chips: K2
15416 #define PHY_NW_IP_REG_LN2_ANEG_STATUS_DBG1                                                           0x00a654UL //Access:R    DataWidth:0x8   One-hot sticky capture of AN FSM states.  Bits 15-8  Chips: K2
15417 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0                                                            0x00a660UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15418     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_SELECTOR                                               (0x1f<<0) // technology Select Field
15419     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_SELECTOR_SHIFT                                         0
15420     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0                                       (0x7<<5) // Echoed Nonce Field bits 2-0.  AN controller generates it.
15421     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_SHIFT                                 5
15422 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1                                                            0x00a664UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15423     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3                                       (0x3<<0) // Echoed Nonce Field bits 4-3.    AN controller generates it.
15424     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_SHIFT                                 0
15425     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_PAUSE                                                  (0x1<<2) // Pause advertised ability
15426     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_PAUSE_SHIFT                                            2
15427     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ASM_DIR                                                (0x1<<3) // Pause ASM_DIR advertised ability
15428     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_ASM_DIR_SHIFT                                          3
15429     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_C2                                                     (0x1<<4) // Reserved always 0
15430     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_C2_SHIFT                                               4
15431     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_REMOTE_FAULT                                           (0x1<<5) // Remote Fault Local Device
15432     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_REMOTE_FAULT_SHIFT                                     5
15433     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_UNUSED_0                                               (0x1<<6) // reserved
15434     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_UNUSED_0_SHIFT                                         6
15435     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_NEXT_PAGE                                              (0x1<<7) // Next Page
15436     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE1_NEXT_PAGE_SHIFT                                        7
15437 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE2                                                            0x00a668UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15438     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE2_TX_NONCE                                               (0x1f<<0) // Transmitted Nonce Field.  It is generated in hardware.
15439     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE2_TX_NONCE_SHIFT                                         0
15440     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE2_UNUSED_0                                               (0x7<<5) // reserved
15441     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE2_UNUSED_0_SHIFT                                         5
15442 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0                                                       0x00a66cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15443     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX                                     (0x1<<0) // 1000Base-KX technology advertised ability
15444     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_SHIFT                               0
15445     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4                                   (0x1<<1) // 10GBase-KX4 technology advertised ability
15446     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_SHIFT                             1
15447     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR                                    (0x1<<2) // 10GBase-KR technology advertised ability
15448     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_SHIFT                              2
15449     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4                                   (0x1<<3) // 40GBase-KR4 technology advertised ability
15450     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_SHIFT                             3
15451     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4                                   (0x1<<4) // 40GBase-CR4 technology advertised ability
15452     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_SHIFT                             4
15453     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10                                 (0x1<<5) // 100GBase-CR10 technology advertised ability
15454     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_SHIFT                           5
15455     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4                                  (0x1<<6) // 100GBase-KP4 technology advertised ability
15456     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_SHIFT                            6
15457     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4                                  (0x1<<7) // 100GBase-KR4 technology advertised ability
15458     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_SHIFT                            7
15459 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1                                                       0x00a670UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15460     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4                                  (0x1<<0) // 100GBase-CR4 technology advertised ability
15461     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_SHIFT                            0
15462     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S                                  (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
15463     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_SHIFT                            1
15464     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR                                    (0x1<<2) // 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
15465     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_SHIFT                              2
15466     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11                                   (0x1f<<3) // technology advertised ability Field A15-A11
15467     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_SHIFT                             3
15468 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH2                                                       0x00a674UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15469     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16                                   (0x7f<<0) // technology advertised ability Field A22-A16
15470     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_SHIFT                             0
15471     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH2_UNUSED_0                                          (0x1<<7) // reserved
15472     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_TECH2_UNUSED_0_SHIFT                                    7
15473 #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC                                                         0x00a678UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15474     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_ABILITY                                         (0x1<<0) // base page bit F0.  It advertises FEC ability
15475     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_ABILITY_SHIFT                                   0
15476     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_REQ                                             (0x1<<1) // base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
15477     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FEC_REQ_SHIFT                                       1
15478     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G                                      (0x1<<2) // base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
15479     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_SHIFT                                2
15480     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G                                      (0x1<<3) // base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
15481     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_SHIFT                                3
15482     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_UNUSED_0                                            (0xf<<4) // reserved
15483     #define PHY_NW_IP_REG_LN2_ANEG_BASE_PAGE_FEC_UNUSED_0_SHIFT                                      4
15484 #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0                                                             0x00a67cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15485     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_KR                                          (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
15486     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_KR_SHIFT                                    0
15487     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_CR                                          (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
15488     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_25G_CR_SHIFT                                    1
15489     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_KR2                                         (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
15490     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_KR2_SHIFT                                   2
15491     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_CR2                                         (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
15492     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_ABILITY_50G_CR2_SHIFT                                   3
15493     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_ABILITY                                          (0x1<<4) // Extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
15494     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_ABILITY_SHIFT                                    4
15495     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_ABILITY                                          (0x1<<5) // Extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15496     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_ABILITY_SHIFT                                    5
15497     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_REQ                                              (0x1<<6) // Extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15498     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_RS_FEC_REQ_SHIFT                                        6
15499     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_REQ                                              (0x1<<7) // Extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15500     #define PHY_NW_IP_REG_LN2_ANEG_EXTENDED0_FC_FEC_REQ_SHIFT                                        7
15501 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0                                                         0x00a6a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15502     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_SELECTOR                                            (0x1f<<0) // Link partner technology Select Field
15503     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_SELECTOR_SHIFT                                      0
15504     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0                                    (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
15505     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_SHIFT                              5
15506 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1                                                         0x00a6a4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15507     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3                                    (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
15508     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_SHIFT                              0
15509     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_PAUSE                                               (0x1<<2) // Link partner Pause advertised ability
15510     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_PAUSE_SHIFT                                         2
15511     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ASM_DIR                                             (0x1<<3) // Link partner Pause ASM_DIR advertised ability
15512     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ASM_DIR_SHIFT                                       3
15513     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_C2                                                  (0x1<<4) // Link partner C2 field always 0
15514     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_C2_SHIFT                                            4
15515     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_REMOTE_FAULT                                        (0x1<<5) // Link partner Remote Fault
15516     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_SHIFT                                  5
15517     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ACK                                                 (0x1<<6) // Link partner Acknowledge always 0
15518     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_ACK_SHIFT                                           6
15519     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_NEXT_PAGE                                           (0x1<<7) // Link partner Next Page
15520     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE1_NEXT_PAGE_SHIFT                                     7
15521 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE2                                                         0x00a6a8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15522     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE2_TX_NONCE                                            (0x1f<<0) // Transmitted Nonce Field from Link partner
15523     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE2_TX_NONCE_SHIFT                                      0
15524     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE2_UNUSED_0                                            (0x7<<5) // reserved
15525     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE2_UNUSED_0_SHIFT                                      5
15526 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0                                                    0x00a6acUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15527     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX                                  (0x1<<0) // Link partner 1000Base-KX technology advertised ability
15528     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_SHIFT                            0
15529     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4                                (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
15530     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_SHIFT                          1
15531     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR                                 (0x1<<2) // Link partner 10GBase-KR technology advertised ability
15532     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_SHIFT                           2
15533     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4                                (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
15534     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_SHIFT                          3
15535     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4                                (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
15536     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_SHIFT                          4
15537     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10                              (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
15538     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_SHIFT                        5
15539     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4                               (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
15540     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_SHIFT                         6
15541     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4                               (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
15542     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_SHIFT                         7
15543 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1                                                    0x00a6b0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15544     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4                               (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
15545     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_SHIFT                         0
15546     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S                               (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
15547     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_SHIFT                         1
15548     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR                                 (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
15549     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_SHIFT                           2
15550     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11                                (0x1f<<3) // Link partner technology advertised ability Field A15-A11
15551     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_SHIFT                          3
15552 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH2                                                    0x00a6b4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15553     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16                                (0x7f<<0) // Link partner technology advertised ability Field A22-A16
15554     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_SHIFT                          0
15555     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH2_UNUSED_0                                       (0x1<<7) // reserved
15556     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_TECH2_UNUSED_0_SHIFT                                 7
15557 #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC                                                      0x00a6b8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15558     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY                                      (0x1<<0) // Link partner base page bit F0.  It advertises FEC ability
15559     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_SHIFT                                0
15560     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_REQ                                          (0x1<<1) // Link partner base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
15561     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_SHIFT                                    1
15562     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G                                   (0x1<<2) // Link partner base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
15563     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_SHIFT                             2
15564     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G                                   (0x1<<3) // Link partner base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
15565     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_SHIFT                             3
15566     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_UNUSED_0                                         (0xf<<4) // reserved
15567     #define PHY_NW_IP_REG_LN2_ANEG_LP_BASE_PAGE_FEC_UNUSED_0_SHIFT                                   4
15568 #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0                                                          0x00a6bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15569     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_KR                                       (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
15570     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_KR_SHIFT                                 0
15571     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_CR                                       (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
15572     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_25G_CR_SHIFT                                 1
15573     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_KR2                                      (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
15574     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_SHIFT                                2
15575     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_CR2                                      (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
15576     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_SHIFT                                3
15577     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_ABILITY                                       (0x1<<4) // Link partner extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
15578     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_SHIFT                                 4
15579     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_ABILITY                                       (0x1<<5) // Link partner extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
15580     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_SHIFT                                 5
15581     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_REQ                                           (0x1<<6) // Link partner extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15582     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_RS_FEC_REQ_SHIFT                                     6
15583     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_REQ                                           (0x1<<7) // Link partner extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
15584     #define PHY_NW_IP_REG_LN2_ANEG_LP_EXTENDED0_FC_FEC_REQ_SHIFT                                     7
15585 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0                                                      0x00a6e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15586     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX                                    (0x1<<0) // Resolution result for 1000Base-KX.  It is valid when status0.an_link_good is 1.
15587     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_SHIFT                              0
15588     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4                                  (0x1<<1) // Resolution result for 10GBase-KX4.  It is valid when status0.an_link_good is 1.
15589     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_SHIFT                            1
15590     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR                                   (0x1<<2) // Resolution result for 10GBase-KR.  It is valid when status0.an_link_good is 1.
15591     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_SHIFT                             2
15592     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4                                  (0x1<<3) // Resolution result for 40GBase-KR4.  It is valid when status0.an_link_good is 1.
15593     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_SHIFT                            3
15594     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4                                  (0x1<<4) // Resolution result for 40GBase-CR4.  It is valid when status0.an_link_good is 1.
15595     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_SHIFT                            4
15596     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10                                (0x1<<5) // Resolution result for 100GBase-CR10.  It is valid when status0.an_link_good is 1.
15597     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_SHIFT                          5
15598     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4                                 (0x1<<6) // Resolution result for 100GBase-KP4.  It is valid when status0.an_link_good is 1.
15599     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_SHIFT                           6
15600     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4                                 (0x1<<7) // Resolution result for 100GBase-KR4.  It is valid when status0.an_link_good is 1.
15601     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_SHIFT                           7
15602 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1                                                      0x00a6e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15603     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4                                 (0x1<<0) // Resolution result for 100GBase-CR4.  It is valid when status0.an_link_good is 1.
15604     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_SHIFT                           0
15605     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S                                 (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR.  It is valid when status0.an_link_good is 1.
15606     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_SHIFT                           1
15607     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR                                   (0x1<<2) // Resolution result for 25GBase-GR KR or CR.  It is valid when status0.an_link_good is 1.
15608     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_SHIFT                             2
15609     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR                                   (0x1<<3) // Resolution result for 25GBase-KR.  It is valid when status0.an_link_good is 1.
15610     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_SHIFT                             3
15611     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR                                   (0x1<<4) // Resolution result for 25GBase-CR4.  It is valid when status0.an_link_good is 1.
15612     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_SHIFT                             4
15613     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2                                  (0x1<<5) // Resolution result for 50GBase-KR2.  It is valid when status0.an_link_good is 1.
15614     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_SHIFT                            5
15615     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2                                  (0x1<<6) // Resolution result for 50GBase-CR2.  It is valid when status0.an_link_good is 1.
15616     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_SHIFT                            6
15617     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_UNUSED_0                                         (0x1<<7) // reserved
15618     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_TECH1_UNUSED_0_SHIFT                                   7
15619 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC                                                        0x00a6e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15620     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_RS                                                 (0x1<<0) // Resolution result for Reed-Solomon FEC.  It is valid when status0.an_link_good is 1.
15621     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_RS_SHIFT                                           0
15622     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_FC                                                 (0x1<<1) // Resolution result for Firecode base page FEC.  It is valid when status0.an_link_good is 1.
15623     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_FC_SHIFT                                           1
15624     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_UNUSED_0                                           (0x3f<<2) // reserved
15625     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_FEC_UNUSED_0_SHIFT                                     2
15626 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE                                                      0x00a6ecUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15627     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_RX                                               (0x1<<0) // Resolution result for RX PAUSE enable.    It is valid when status0.an_link_good is 1.
15628     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_RX_SHIFT                                         0
15629     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_TX                                               (0x1<<1) // Resolution result for TX PAUSE enable.    It is valid when status0.an_link_good is 1.
15630     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_TX_SHIFT                                         1
15631     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_UNUSED_0                                         (0x3f<<2) // reserved
15632     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_PAUSE_UNUSED_0_SHIFT                                   2
15633 #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE                                                        0x00a6f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15634     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE_F770                                               (0x1<<0) // Resolution result for EEE.  It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type.  It is 0 otherwise.  It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
15635     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE_F770_SHIFT                                         0
15636     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE_UNUSED_0                                           (0x7f<<1) // reserved
15637     #define PHY_NW_IP_REG_LN2_ANEG_RESOLUTION_EEE_UNUSED_0_SHIFT                                     1
15638 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0                                                          0x00a6f8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15639     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_1G_KX                                        (0x1<<0) // link_status for 1000Base-KX
15640     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_1G_KX_SHIFT                                  0
15641     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KX4                                      (0x1<<1) // link_status for 10GBase-KX4
15642     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KX4_SHIFT                                1
15643     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KR                                       (0x1<<2) // link_status for 10GBase-KR
15644     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_10G_KR_SHIFT                                 2
15645     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_KR4                                      (0x1<<3) // link_status for 40GBase-KR4
15646     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_KR4_SHIFT                                3
15647     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_CR4                                      (0x1<<4) // link_status for 40GBase-CR4
15648     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_40G_CR4_SHIFT                                4
15649     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_CR10                                    (0x1<<5) // link_status for 100GBase-CR10
15650     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_CR10_SHIFT                              5
15651     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KP4                                     (0x1<<6) // link_status for 100GBase-KP4
15652     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KP4_SHIFT                               6
15653     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KR4                                     (0x1<<7) // link_status for 100GBase-KR4
15654     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS0_ABILITY_100G_KR4_SHIFT                               7
15655 #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1                                                          0x00a6fcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15656     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_100G_CR4                                     (0x1<<0) // link_status for 100GBase-CR4
15657     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_100G_CR4_SHIFT                               0
15658     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_GR                                       (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
15659     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_GR_SHIFT                                 1
15660     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_UNUSED_0                                             (0x1<<2) // reserved
15661     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_UNUSED_0_SHIFT                                       2
15662     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_KR                                       (0x1<<3) // link_status for 25GBase-KR
15663     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_KR_SHIFT                                 3
15664     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_CR                                       (0x1<<4) // link_status for 25GBase-CR4
15665     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_25G_CR_SHIFT                                 4
15666     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_KR2                                      (0x1<<5) // link_status for 50GBase-KR2
15667     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_KR2_SHIFT                                5
15668     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_CR2                                      (0x1<<6) // link_status for 50GBase-CR2
15669     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_ABILITY_50G_CR2_SHIFT                                6
15670     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_UNUSED_1                                             (0x1<<7) // reserved
15671     #define PHY_NW_IP_REG_LN2_ANEG_LINK_STATUS1_UNUSED_1_SHIFT                                       7
15672 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_AGCLOS_CTRL0                                                    0x00a8c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15673     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START                                   (0xf<<0) // AGC LOS Threshold Start Value
15674     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_SHIFT                             0
15675     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_AGCLOS_CTRL0_UNUSED_0                                       (0xf<<4) // reserved
15676     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_AGCLOS_CTRL0_UNUSED_0_SHIFT                                 4
15677 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_PLE_ATT_CTRL1                                                   0x00a8f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15678     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START                                 (0x7<<0) // PLE LFG Start Value
15679     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_SHIFT                           0
15680     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_PLE_ATT_CTRL1_UNUSED_0                                      (0x1f<<3) // reserved
15681     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_PLE_ATT_CTRL1_UNUSED_0_SHIFT                                3
15682 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_HFG_SQL_CTRL0                                                0x00a900UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15683     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START                           (0x1f<<0) // CTLE HFG Start Value
15684     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_SHIFT                     0
15685     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_UNUSED_0                                   (0x7<<5) // reserved
15686     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_UNUSED_0_SHIFT                             5
15687 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_GN_APG_CTRL0                                                    0x00a9c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15688     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START                                   (0x3<<0) // GN APG Start Value
15689     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_SHIFT                             0
15690     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_GN_APG_CTRL0_UNUSED_0                                       (0x3f<<2) // reserved
15691     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_GN_APG_CTRL0_UNUSED_0_SHIFT                                 2
15692 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL0                                                    0x00aa00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15693     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START                                   (0x1f<<0) // EQ LFG Start Value
15694     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_SHIFT                             0
15695     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL0_UNUSED_0                                       (0x7<<5) // reserved
15696     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL0_UNUSED_0_SHIFT                                 5
15697 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL1                                                    0x00aa04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15698     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX                               (0x1f<<0) // EQ LFG Maximum Value, inclusive
15699     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_SHIFT                         0
15700     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL1_UNUSED_0                                       (0x7<<5) // reserved
15701     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL1_UNUSED_0_SHIFT                                 5
15702 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL2                                                    0x00aa08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15703     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN                               (0x1f<<0) // EQ LFG Minimum Value, inclusive
15704     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_SHIFT                         0
15705     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL2_UNUSED_0                                       (0x7<<5) // reserved
15706     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_LFG_CTRL2_UNUSED_0_SHIFT                                 5
15707 #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1                                                     0x00aa64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15708     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START                                    (0xf<<0) // EQ MBF Start Value
15709     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT                              0
15710     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START                                    (0xf<<4) // EQ MBG Start Value
15711     #define PHY_NW_IP_REG_LN2_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT                              4
15712 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_PD_CTRL0                                                    0x00ae00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15713     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV                                       (0xf<<0) // power down TX driver
15714     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_SHIFT                                 0
15715     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_PD_CTRL0_UNUSED_0                                       (0xf<<4) // reserved
15716     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_PD_CTRL0_UNUSED_0_SHIFT                                 4
15717 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_CTRL0                                                       0x00ae08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15718     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE                                     (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
15719     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_SHIFT                               0
15720     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_CTRL0_UNUSED_0                                          (0x3f<<2) // reserved
15721     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_AFE_CTRL0_UNUSED_0_SHIFT                                    2
15722 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0                                                      0x00ae40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15723     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0_REQ                                              (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1.  Set to 0 once ack is 1.
15724     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0_REQ_SHIFT                                        0
15725     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0_UNUSED_0                                         (0x7f<<1) // reserved
15726     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL0_UNUSED_0_SHIFT                                   1
15727 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0                                                    0x00ae44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15728     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0_ACK                                            (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
15729     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0_ACK_SHIFT                                      0
15730     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0_UNUSED_0                                       (0x7f<<1) // reserved
15731     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_STATUS0_UNUSED_0_SHIFT                                 1
15732 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL1                                                      0x00ae48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15733     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1                                          (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
15734     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_SHIFT                                    0
15735     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL1_UNUSED_0                                         (0x7<<5) // reserved
15736     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL1_UNUSED_0_SHIFT                                   5
15737 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL3                                                      0x00ae50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15738     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1                                         (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
15739     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_SHIFT                                   0
15740     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL3_UNUSED_0                                         (0xf<<4) // reserved
15741     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL3_UNUSED_0_SHIFT                                   4
15742 #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL5                                                      0x00ae58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15743     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING                                        (0xf<<0) // Thermometer coded control to adjust the delay between data and clock for the final 2to1 mux. Setting 00000 min delay of clock path and 11111 max delay of clock path.
15744     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_SHIFT                                  0
15745     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL5_UNUSED_0                                         (0xf<<4) // reserved
15746     #define PHY_NW_IP_REG_LN2_DRV_REFCLK_TXEQ_CTRL5_UNUSED_0_SHIFT                                   4
15747 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0                                                       0x00b080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15748     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_REQ                                               (0x1<<0) // Write 1 to request a command CMD execution.  It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
15749     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_REQ_SHIFT                                         0
15750     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_CMD                                               (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
15751     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_CMD_SHIFT                                         1
15752     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_UNUSED_0                                          (0x1<<6) // reserved
15753     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_UNUSED_0_SHIFT                                    6
15754     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL                                 (0x1<<7) // Set it to 1 when changing DFE tap values
15755     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_SHIFT                           7
15756 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0                                                     0x00b0a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15757     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_ACK                                             (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
15758     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_ACK_SHIFT                                       0
15759     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_UNUSED_0                                        (0x7f<<1) // reserved
15760     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_FSM_STATUS0_UNUSED_0_SHIFT                                  1
15761 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0                                                       0x00b0a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15762     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN                                     (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
15763     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_SHIFT                               0
15764     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN                                     (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
15765     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_SHIFT                               1
15766     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN                                      (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
15767     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_SHIFT                                2
15768     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN                                      (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
15769     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_SHIFT                                3
15770     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP2_EN                                           (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
15771     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP2_EN_SHIFT                                     4
15772     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP3_EN                                           (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
15773     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP3_EN_SHIFT                                     5
15774     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP4_EN                                           (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
15775     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP4_EN_SHIFT                                     6
15776     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP5_EN                                           (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
15777     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_CTRL0_TAP5_EN_SHIFT                                     7
15778 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0                                             0x00b0acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15779     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0                              (0x1f<<0) // Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
15780     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_SHIFT                        0
15781     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_UNUSED_0                                (0x3<<5) // reserved
15782     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_UNUSED_0_SHIFT                          5
15783     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY                     (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
15784     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT               7
15785 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1                                             0x00b0b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15786     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1                              (0x1f<<0) // Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
15787     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_SHIFT                        0
15788     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_UNUSED_0                                (0x3<<5) // reserved
15789     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_UNUSED_0_SHIFT                          5
15790     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY                     (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
15791     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT               7
15792 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2                                             0x00b0b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15793     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0                               (0x1f<<0) // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
15794     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_SHIFT                         0
15795     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_UNUSED_0                                (0x3<<5) // reserved
15796     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_UNUSED_0_SHIFT                          5
15797     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
15798     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT                7
15799 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3                                             0x00b0b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15800     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1                               (0x1f<<0) // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
15801     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_SHIFT                         0
15802     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_UNUSED_0                                (0x3<<5) // reserved
15803     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_UNUSED_0_SHIFT                          5
15804     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
15805     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT                7
15806 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4                                             0x00b0bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15807     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2                                    (0xf<<0) // Starting value for Tap 2 for Tap Adaptations
15808     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_SHIFT                              0
15809     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_UNUSED_0                                (0x7<<4) // reserved
15810     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_UNUSED_0_SHIFT                          4
15811     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
15812     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_SHIFT                     7
15813 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5                                             0x00b0c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15814     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3                                    (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
15815     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_SHIFT                              0
15816     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_UNUSED_0                                (0xf<<3) // reserved
15817     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_UNUSED_0_SHIFT                          3
15818     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
15819     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_SHIFT                     7
15820 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6                                             0x00b0c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15821     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4                                    (0x7<<0) // Starting value for Tap 4 for Tap Adaptations
15822     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_SHIFT                              0
15823     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_UNUSED_0                                (0xf<<3) // reserved
15824     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_UNUSED_0_SHIFT                          3
15825     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
15826     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_SHIFT                     7
15827 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7                                             0x00b0c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15828     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5                                    (0x7<<0) // Starting value for Tap 5 for Tap Adaptations
15829     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_SHIFT                              0
15830     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_UNUSED_0                                (0xf<<3) // reserved
15831     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_UNUSED_0_SHIFT                          3
15832     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
15833     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_SHIFT                     7
15834 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0                                              0x00b0ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15835     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0                               (0x1f<<0) // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
15836     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_SHIFT                         0
15837     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_UNUSED_0                                 (0x3<<5) // reserved
15838     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_UNUSED_0_SHIFT                           5
15839     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
15840     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT                7
15841 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1                                              0x00b0d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15842     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1                               (0x1f<<0) // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
15843     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_SHIFT                         0
15844     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_UNUSED_0                                 (0x3<<5) // reserved
15845     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_UNUSED_0_SHIFT                           5
15846     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
15847     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT                7
15848 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2                                              0x00b0d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15849     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0                                (0x1f<<0) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
15850     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_SHIFT                          0
15851     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_UNUSED_0                                 (0x3<<5) // reserved
15852     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_UNUSED_0_SHIFT                           5
15853     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY                       (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
15854     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT                 7
15855 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3                                              0x00b0d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15856     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1                                (0x1f<<0) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
15857     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_SHIFT                          0
15858     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_UNUSED_0                                 (0x3<<5) // reserved
15859     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_UNUSED_0_SHIFT                           5
15860     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY                       (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
15861     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT                 7
15862 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4                                              0x00b0dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15863     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2                                     (0xf<<0) // Loading value for Tap 2 for Tap Adaptations
15864     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_SHIFT                               0
15865     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_UNUSED_0                                 (0x7<<4) // reserved
15866     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_UNUSED_0_SHIFT                           4
15867     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
15868     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_SHIFT                      7
15869 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5                                              0x00b0e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15870     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3                                     (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
15871     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_SHIFT                               0
15872     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_UNUSED_0                                 (0xf<<3) // reserved
15873     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_UNUSED_0_SHIFT                           3
15874     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
15875     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_SHIFT                      7
15876 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6                                              0x00b0e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15877     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4                                     (0x7<<0) // Loading value for Tap 4 for Tap Adaptations
15878     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_SHIFT                               0
15879     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_UNUSED_0                                 (0xf<<3) // reserved
15880     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_UNUSED_0_SHIFT                           3
15881     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
15882     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_SHIFT                      7
15883 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7                                              0x00b0e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15884     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5                                     (0x7<<0) // Loading value for Tap 5 for Tap Adaptations
15885     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_SHIFT                               0
15886     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_UNUSED_0                                 (0xf<<3) // reserved
15887     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_UNUSED_0_SHIFT                           3
15888     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
15889     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_SHIFT                      7
15890 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0                                                 0x00b0ecUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15891     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0                                  (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap Adaptations
15892     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_SHIFT                            0
15893     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_UNUSED_0                                    (0x3<<5) // reserved
15894     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_UNUSED_0_SHIFT                              5
15895     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY                         (0x1<<7) // polarity 0 = negative, 1 = positive
15896     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_SHIFT                   7
15897 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1                                                 0x00b0f0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15898     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1                                  (0x1f<<0) // binary  value for Tap 1 Even 1 Path for Tap Adaptations
15899     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_SHIFT                            0
15900     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_UNUSED_0                                    (0x3<<5) // reserved
15901     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_UNUSED_0_SHIFT                              5
15902     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY                         (0x1<<7) // polarity 0 = negative, 1 = positive
15903     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_SHIFT                   7
15904 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2                                                 0x00b0f4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15905     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0                                   (0x1f<<0) // binary  value for Tap 1 Odd 0 Path for Tap Adaptations
15906     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_SHIFT                             0
15907     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_UNUSED_0                                    (0x3<<5) // reserved
15908     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_UNUSED_0_SHIFT                              5
15909     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY                          (0x1<<7) // polarity 0 = negative, 1 = positive
15910     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_SHIFT                    7
15911 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3                                                 0x00b0f8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15912     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1                                   (0x1f<<0) // binary  value for Tap 1 Odd 1 Path for Tap Adaptations
15913     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_SHIFT                             0
15914     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_UNUSED_0                                    (0x3<<5) // reserved
15915     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_UNUSED_0_SHIFT                              5
15916     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY                          (0x1<<7) // polarity 0 = negative, 1 = positive
15917     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_SHIFT                    7
15918 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4                                                 0x00b0fcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15919     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2                                        (0xf<<0) // binary  value for Tap 2 for Tap Adaptations
15920     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_SHIFT                                  0
15921     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_UNUSED_0                                    (0x7<<4) // reserved
15922     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_UNUSED_0_SHIFT                              4
15923     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
15924     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_SHIFT                         7
15925 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5                                                 0x00b100UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15926     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3                                        (0x7<<0) // binary  value for Tap 3 for Tap Adaptations
15927     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_SHIFT                                  0
15928     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_UNUSED_0                                    (0xf<<3) // reserved
15929     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_UNUSED_0_SHIFT                              3
15930     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
15931     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_SHIFT                         7
15932 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6                                                 0x00b104UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15933     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4                                        (0x7<<0) // binary  value for Tap 4 for Tap Adaptations
15934     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_SHIFT                                  0
15935     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_UNUSED_0                                    (0xf<<3) // reserved
15936     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_UNUSED_0_SHIFT                              3
15937     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
15938     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_SHIFT                         7
15939 #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7                                                 0x00b108UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15940     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5                                        (0x7<<0) // binary  value for Tap 5 for Tap Adaptations
15941     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_SHIFT                                  0
15942     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_UNUSED_0                                    (0xf<<3) // reserved
15943     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_UNUSED_0_SHIFT                              3
15944     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
15945     #define PHY_NW_IP_REG_LN2_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_SHIFT                         7
15946 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL                                                    0x00b400UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15947     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL                                (0x1<<0) // Enables analog LOS offset calibration circuits.
15948     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_SHIFT                          0
15949     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL_UNUSED_0                                       (0x7f<<1) // reserved
15950     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_AFE_CAL_CTRL_UNUSED_0_SHIFT                                 1
15951 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0                                                0x00b40cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15952     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0_EN                                         (0x1<<0) // Enables the run-length detection digital LOS filter.
15953     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_SHIFT                                   0
15954     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0_UNUSED_0                                   (0x7f<<1) // reserved
15955     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL0_UNUSED_0_SHIFT                             1
15956 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_CTRL1                                                0x00b410UL //Access:RW   DataWidth:0x8   Value of run-length which will trigger an LOS condition.  Chips: K2
15957 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0                                              0x00b414UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15958     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED                                   (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
15959     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_SHIFT                             0
15960     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY                            (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
15961     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_SHIFT                      1
15962     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_UNUSED_0                                 (0x3f<<2) // reserved
15963     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_RUN_LENGTH_STATUS0_UNUSED_0_SHIFT                           2
15964 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL0                                                    0x00b440UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x00.  Chips: K2
15965 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL1                                                    0x00b444UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x0000.  Chips: K2
15966 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL2                                                    0x00b448UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the raw analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x000000.  Chips: K2
15967 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL3                                                    0x00b44cUL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
15968 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL4                                                    0x00b450UL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
15969 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL5                                                    0x00b454UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15970     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24                       (0x3<<0) // Same as above.
15971     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_SHIFT                 0
15972     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL5_UNUSED_0                                       (0x3f<<2) // reserved
15973     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL5_UNUSED_0_SHIFT                                 2
15974 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6                                                    0x00b458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15975     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6_EN                                             (0x1<<0) // Enables the digital deglitching filter.
15976     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6_EN_SHIFT                                       0
15977     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6_UNUSED_0                                       (0x7f<<1) // reserved
15978     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_FILTER_CTRL6_UNUSED_0_SHIFT                                 1
15979 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0                                                  0x00b4c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
15980     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN                                     (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
15981     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_SHIFT                               0
15982     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_0                                     (0x7<<1) // reserved
15983     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_0_SHIFT                               1
15984     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE                                  (0x1<<4) // Override value for the LOS output of the digital filtering logic.
15985     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_SHIFT                            4
15986     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_1                                     (0x7<<5) // reserved
15987     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_1_SHIFT                               5
15988 #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0                                                         0x00b5c4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
15989     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_READY                                           (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
15990     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_READY_SHIFT                                     0
15991     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_UNUSED_0                                            (0x1<<1) // reserved
15992     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_UNUSED_0_SHIFT                                      1
15993     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS                                                 (0x1<<2) // The filtered LOS signal value.
15994     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_SHIFT                                           2
15995     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_RAW                                             (0x1<<3) // The unfiltered LOS signal value.
15996     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_RAW_SHIFT                                       3
15997     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_NO_EII                                          (0x1<<4) // The filtered LOS signal value before EII override logic.
15998     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_LOS_NO_EII_SHIFT                                    4
15999     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_UNUSED_1                                            (0x7<<5) // reserved
16000     #define PHY_NW_IP_REG_LN2_LOS_REFCLK_STATUS0_UNUSED_1_SHIFT                                      5
16001 #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL                                                               0x00b800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16002     #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_EN                                                        (0x1<<0) // Enables BIST Tx data generation.
16003     #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_EN_SHIFT                                                  0
16004     #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_PATTERN_SEL                                               (0xf<<1) // Selects the pattern to transmitted: 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP 0x9 ? MAC Tx data
16005     #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_PATTERN_SEL_SHIFT                                         1
16006     #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_UNUSED_0                                                  (0x7<<5) // reserved
16007     #define PHY_NW_IP_REG_LN2_BIST_TX_CTRL_UNUSED_0_SHIFT                                            5
16008 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0                                                          0x00b818UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16009     #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0_MODE                                                 (0x3<<0) // Controls what type of error injection is used: 0x0 ? None 0x1 ? Single cycle error 0x2 ? Timer based
16010     #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0_MODE_SHIFT                                           0
16011     #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0_UNUSED_0                                             (0x3f<<2) // reserved
16012     #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL0_UNUSED_0_SHIFT                                       2
16013 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL1                                                          0x00b81cUL //Access:RW   DataWidth:0x8   Number of cycles between single bit-error injection  Chips: K2
16014 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL2                                                          0x00b820UL //Access:RW   DataWidth:0x8   Number of cycles between single bit-error injection  Chips: K2
16015 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL3                                                          0x00b824UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
16016 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL4                                                          0x00b828UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
16017 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL5                                                          0x00b82cUL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
16018 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL6                                                          0x00b830UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
16019 #define PHY_NW_IP_REG_LN2_BIST_TX_BER_CTRL7                                                          0x00b834UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
16020 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_SHIFT_AMOUNT                                                   0x00b880UL //Access:RW   DataWidth:0x8   Determines the length of the UDP.  Must be set to d160 modulus udp_length.  Chips: K2
16021 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_7_0                                                            0x00b890UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16022 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_15_8                                                           0x00b894UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16023 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_23_16                                                          0x00b898UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16024 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_31_24                                                          0x00b89cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16025 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_39_32                                                          0x00b8a0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16026 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_47_40                                                          0x00b8a4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16027 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_55_48                                                          0x00b8a8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16028 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_63_56                                                          0x00b8acUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16029 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_71_64                                                          0x00b8b0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16030 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_79_72                                                          0x00b8b4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16031 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_87_80                                                          0x00b8b8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16032 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_95_88                                                          0x00b8bcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16033 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_103_96                                                         0x00b8c0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16034 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_111_104                                                        0x00b8c4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16035 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_119_112                                                        0x00b8c8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16036 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_127_120                                                        0x00b8ccUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16037 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_135_128                                                        0x00b8d0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16038 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_143_136                                                        0x00b8d4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16039 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_151_144                                                        0x00b8d8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16040 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_159_152                                                        0x00b8dcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16041 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_167_160                                                        0x00b8e0UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16042 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_175_168                                                        0x00b8e4UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16043 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_183_176                                                        0x00b8e8UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16044 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_191_184                                                        0x00b8ecUL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16045 #define PHY_NW_IP_REG_LN2_BIST_TX_UDP_199_192                                                        0x00b8f0UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16046 #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL                                                               0x00ba00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16047     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_EN                                                        (0x1<<0) // Enables BIST Rx data checking.
16048     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_EN_SHIFT                                                  0
16049     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_PATTERN_SEL                                               (0xf<<1) // Selects the pattern to search for: 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP 0x8 ? Auto-detect
16050     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_PATTERN_SEL_SHIFT                                         1
16051     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_CLEAR_BER                                                 (0x1<<5) // Clears the bit error counter.
16052     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_CLEAR_BER_SHIFT                                           5
16053     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_STOP_ERROR_COUNT                                          (0x1<<6) // Stops the error count from incrementing.  Can be used to read back the BER data coherently.
16054     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_STOP_ERROR_COUNT_SHIFT                                    6
16055     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA                                    (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle.  This will cause the bit error counter to be inaccurate.
16056     #define PHY_NW_IP_REG_LN2_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_SHIFT                              7
16057 #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS                                                             0x00ba10UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16058     #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_STATE                                                   (0x7<<0) // State of the BIST checker: 0x0 ? Off 0x1 ? Searching for pattern 0x2 ? Waiting for pattern lock conditions 0x3 ? Pattern lock acquired 0x4 ? Pattern lock lost
16059     #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_STATE_SHIFT                                             0
16060     #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_PATTERN_DET                                             (0xf<<3) // Indicates the pattern  detected: 0x0 ? No pattern detected 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP
16061     #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_PATTERN_DET_SHIFT                                       3
16062     #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_UNUSED_0                                                (0x1<<7) // reserved
16063     #define PHY_NW_IP_REG_LN2_BIST_RX_STATUS_UNUSED_0_SHIFT                                          7
16064 #define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS0                                                        0x00ba20UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
16065 #define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS1                                                        0x00ba24UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
16066 #define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS2                                                        0x00ba28UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
16067 #define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS4                                                        0x00ba30UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
16068 #define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS5                                                        0x00ba34UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
16069 #define PHY_NW_IP_REG_LN2_BIST_RX_BER_STATUS6                                                        0x00ba38UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
16070 #define PHY_NW_IP_REG_LN2_BIST_RX_LOCK_CTRL0                                                         0x00ba50UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern lock.  Chips: K2
16071 #define PHY_NW_IP_REG_LN2_BIST_RX_LOCK_CTRL1                                                         0x00ba54UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern lock.  Chips: K2
16072 #define PHY_NW_IP_REG_LN2_BIST_RX_LOCK_CTRL2                                                         0x00ba58UL //Access:RW   DataWidth:0x8   Maximum number of errors allowed to trigger pattern lock.  Chips: K2
16073 #define PHY_NW_IP_REG_LN2_BIST_RX_LOCK_CTRL3                                                         0x00ba5cUL //Access:RW   DataWidth:0x8   Maximum number of errors allowed to trigger pattern lock.  Chips: K2
16074 #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL0                                                    0x00ba80UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern loss-of-lock.  Chips: K2
16075 #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL1                                                    0x00ba84UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern loss-of-lock.  Chips: K2
16076 #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL2                                                    0x00ba88UL //Access:RW   DataWidth:0x8   Minimum number of errors allowed to trigger pattern loss-of-lock.  Chips: K2
16077 #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL3                                                    0x00ba8cUL //Access:RW   DataWidth:0x8   Minimum number of errors allowed to trigger pattern loss-of-lock.  Chips: K2
16078 #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4                                                    0x00ba90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16079     #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK                              (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
16080     #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT                        0
16081     #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4_UNUSED_0                                       (0x7f<<1) // reserved
16082     #define PHY_NW_IP_REG_LN2_BIST_RX_LOSS_LOCK_CTRL4_UNUSED_0_SHIFT                                 1
16083 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_SHIFT_AMOUNT                                                   0x00bac0UL //Access:RW   DataWidth:0x8   Determines the length of the UDP.  Must be set to d160 modulus udp_length.  Chips: K2
16084 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_7_0                                                            0x00bad0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16085 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_15_8                                                           0x00bad4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16086 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_23_16                                                          0x00bad8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16087 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_31_24                                                          0x00badcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16088 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_39_32                                                          0x00bae0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16089 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_47_40                                                          0x00bae4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16090 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_55_48                                                          0x00bae8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16091 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_63_56                                                          0x00baecUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16092 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_71_64                                                          0x00baf0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16093 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_79_72                                                          0x00baf4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16094 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_87_80                                                          0x00baf8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16095 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_95_88                                                          0x00bafcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16096 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_103_96                                                         0x00bb00UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16097 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_111_104                                                        0x00bb04UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16098 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_119_112                                                        0x00bb08UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16099 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_127_120                                                        0x00bb0cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16100 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_135_128                                                        0x00bb10UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16101 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_143_136                                                        0x00bb14UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16102 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_151_144                                                        0x00bb18UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16103 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_159_152                                                        0x00bb1cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
16104 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_167_160                                                        0x00bb20UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16105 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_175_168                                                        0x00bb24UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16106 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_183_176                                                        0x00bb28UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16107 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_191_184                                                        0x00bb2cUL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16108 #define PHY_NW_IP_REG_LN2_BIST_RX_UDP_199_192                                                        0x00bb30UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
16109 #define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0                                                        0x00bc00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16110     #define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0_AC_COUPLED                                         (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
16111     #define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0_AC_COUPLED_SHIFT                                   0
16112     #define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0_UNUSED_0                                           (0x7f<<1) // reserved
16113     #define PHY_NW_IP_REG_LN2_FEATURE_RXTERM_CFG0_UNUSED_0_SHIFT                                     1
16114 #define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0                                                      0x00bc04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16115     #define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0_EN                                               (0x1<<0) // Enables turning on the divided rxclk output
16116     #define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0_EN_SHIFT                                         0
16117     #define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0_UNUSED_0                                         (0x7f<<1) // reserved
16118     #define PHY_NW_IP_REG_LN2_FEATURE_RXCLKDIV_CFG0_UNUSED_0_SHIFT                                   1
16119 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG                                                     0x00bc84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16120     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0                              (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
16121     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_SHIFT                        0
16122     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1                              (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
16123     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_SHIFT                        2
16124     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_UNUSED_0                                        (0xf<<4) // reserved
16125     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_CFG_UNUSED_0_SHIFT                                  4
16126 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG                                                 0x00bc88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16127     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN                                    (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
16128     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_SHIFT                              0
16129     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_UNUSED_0                                    (0x7f<<1) // reserved
16130     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_AGC_CFG_UNUSED_0_SHIFT                              1
16131 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG                                             0x00bc8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16132     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN                                (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
16133     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_SHIFT                          0
16134     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_UNUSED_0                                (0x7f<<1) // reserved
16135     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_APG_MAP_CFG_UNUSED_0_SHIFT                          1
16136 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG                                                 0x00bc90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16137     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL                                   (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
16138     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_SHIFT                             0
16139     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL                                   (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
16140     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_SHIFT                             2
16141     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_UNUSED_0                                    (0xf<<4) // reserved
16142     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_LFG_CFG_UNUSED_0_SHIFT                              4
16143 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0                                                0x00bc94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16144     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN                              (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
16145     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_SHIFT                        0
16146     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN                              (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
16147     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_SHIFT                        1
16148     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN                              (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
16149     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_SHIFT                        2
16150     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN                              (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
16151     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_SHIFT                        3
16152     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_UNUSED_0                                   (0xf<<4) // reserved
16153     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG0_UNUSED_0_SHIFT                             4
16154 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1                                                0x00bc98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16155     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL                           (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
16156     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_SHIFT                     0
16157     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL                           (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
16158     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_SHIFT                     2
16159     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_UNUSED_0                                   (0xf<<4) // reserved
16160     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_HFG_CFG1_UNUSED_0_SHIFT                             4
16161 #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG                                                 0x00bca0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16162     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN                                    (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
16163     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT                              0
16164     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN                                    (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
16165     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_SHIFT                              1
16166     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_UNUSED_0                                    (0x3f<<2) // reserved
16167     #define PHY_NW_IP_REG_LN2_FEATURE_CTLE_ADAPT_MBS_CFG_UNUSED_0_SHIFT                              2
16168 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG                                                            0x00bcc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16169     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP1_EN                                                (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
16170     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP1_EN_SHIFT                                          0
16171     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP2_EN                                                (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
16172     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP2_EN_SHIFT                                          1
16173     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP3_EN                                                (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
16174     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP3_EN_SHIFT                                          2
16175     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP4_EN                                                (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
16176     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP4_EN_SHIFT                                          3
16177     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP5_EN                                                (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
16178     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_TAP5_EN_SHIFT                                          4
16179     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_UNUSED_0                                               (0x7<<5) // reserved
16180     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_CFG_UNUSED_0_SHIFT                                         5
16181 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG                                                      0x00bcc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16182     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG_METHOD_SEL                                       (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
16183     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_SHIFT                                 0
16184     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG_UNUSED_0                                         (0x7f<<1) // reserved
16185     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_CFG_UNUSED_0_SHIFT                                   1
16186 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG                                                 0x00bcc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16187     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 1
16188     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_SHIFT                          0
16189     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_UNUSED_0                                    (0x7f<<1) // reserved
16190     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP1_CFG_UNUSED_0_SHIFT                              1
16191 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG                                                 0x00bcccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16192     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 2
16193     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_SHIFT                          0
16194     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_UNUSED_0                                    (0x7f<<1) // reserved
16195     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP2_CFG_UNUSED_0_SHIFT                              1
16196 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG                                                 0x00bcd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16197     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 3
16198     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_SHIFT                          0
16199     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_UNUSED_0                                    (0x7f<<1) // reserved
16200     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP3_CFG_UNUSED_0_SHIFT                              1
16201 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG                                                 0x00bcd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16202     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 4
16203     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_SHIFT                          0
16204     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_UNUSED_0                                    (0x7f<<1) // reserved
16205     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP4_CFG_UNUSED_0_SHIFT                              1
16206 #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG                                                 0x00bcd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16207     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 5
16208     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_SHIFT                          0
16209     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_UNUSED_0                                    (0x7f<<1) // reserved
16210     #define PHY_NW_IP_REG_LN2_FEATURE_DFE_ADAPT_TAP5_CFG_UNUSED_0_SHIFT                              1
16211 #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0                                                    0x00bce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16212     #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_EN                                             (0x1<<0) // Enables continuous background adaptation
16213     #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_EN_SHIFT                                       0
16214     #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_UNUSED_0                                       (0x7f<<1) // reserved
16215     #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG0_UNUSED_0_SHIFT                                 1
16216 #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG1                                                    0x00bce4UL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
16217 #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG2                                                    0x00bce8UL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
16218 #define PHY_NW_IP_REG_LN2_FEATURE_ADAPT_CONT_CFG3                                                    0x00bcecUL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
16219 #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0                                                          0x00bd40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16220     #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_UNUSED_0                                             (0x1<<0) // reserved
16221     #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_UNUSED_0_SHIFT                                       0
16222     #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RX_CTRL_DIS                                          (0x1<<1) // Disables the firmware rx_ctrl MSM
16223     #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_RX_CTRL_DIS_SHIFT                                    1
16224     #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_UNUSED_1                                             (0x3f<<2) // reserved
16225     #define PHY_NW_IP_REG_LN2_FEATURE_TEST_CFG0_UNUSED_1_SHIFT                                       2
16226 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0                                                            0x00be00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16227     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING                                    (0x1<<0) // Starts link training procedure when asserted.  This is an 802.3 defined variable.
16228     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_SHIFT                              0
16229     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE                                     (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion.  This is an 802.3 defined variable.
16230     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_SHIFT                               1
16231     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_SIGNAL_DETECT                                          (0x1<<2) // Output corresponding to link training signal detect variable.  Should be set when link training has completed successfully.
16232     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_SIGNAL_DETECT_SHIFT                                    2
16233     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_CLEAR                                                  (0x1<<3) // Synchronous reset for LT Tx block.
16234     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_CLEAR_SHIFT                                            3
16235     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_UNUSED_0                                               (0xf<<4) // reserved
16236     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL0_UNUSED_0_SHIFT                                         4
16237 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL1                                                            0x00be04UL //Access:RW   DataWidth:0x8   Maximum time allowed for LT procedure.  If this is exceeded then the training_fail status will assert.  This is an 802.defined variable.  Value is encoded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width  Should be set to 500ns for 802.3 compliant timeout.  Chips: K2
16238 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL2                                                            0x00be08UL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
16239 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL3                                                            0x00be0cUL //Access:RW   DataWidth:0x8   Number of additional frames to send after both receivers have been trained and are ready.  This is an 802.3 defined variable.  Should be set between 100 and 300 for 802.3 compliance.  Chips: K2
16240 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4                                                            0x00be10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16241     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4_WAIT_TIME_8                                            (0x1<<0) // Same as above.
16242     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4_WAIT_TIME_8_SHIFT                                      0
16243     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4_UNUSED_0                                               (0x7f<<1) // reserved
16244     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL4_UNUSED_0_SHIFT                                         1
16245 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5                                                            0x00be14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16246     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_FRAME_LOCK                                             (0x1<<0) // Input to LTSM that receiver has acquired frame lock.  This value should be taken from the corresponding LT Rx register.  This  an 802.3 defined variable.
16247     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_FRAME_LOCK_SHIFT                                       0
16248     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_RX_TRAINED                                             (0x1<<1) // Input to LTSM indicating that the local receiver has completed training.  This is an 802.3 defined variable.
16249     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_RX_TRAINED_SHIFT                                       1
16250     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_REMOTE_RX_READY                                        (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready.  This value should be taken from the corresponding LT Rx registers.  This is an 802.3 defined variable.
16251     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_REMOTE_RX_READY_SHIFT                                  2
16252     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_UNUSED_0                                               (0x1f<<3) // reserved
16253     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_CTRL5_UNUSED_0_SHIFT                                         3
16254 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS                                                           0x00be40UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16255     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_FAIL                                         (0x1<<0) // Output from LTSM indicating that link training has failed.  This is an 802.3 defined variable.
16256     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_FAIL_SHIFT                                   0
16257     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING                                              (0x1<<1) // Output from LTSM indicating that link training is in progress.  This is an 802.3 defined variable.
16258     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_TRAINING_SHIFT                                        1
16259     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_SIGNAL_DETECT                                         (0x1<<2) // Output from LTSM indicating that link training is complete and successful.  This is an 802.3 defined variable.  This value is only visible internally, and is not the signal_det value driven to PHY top-level.
16260     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_SIGNAL_DETECT_SHIFT                                   2
16261     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_UNUSED_0                                              (0x1<<3) // reserved
16262     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_UNUSED_0_SHIFT                                        3
16263     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY                                    (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
16264     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_SHIFT                              4
16265     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_UNUSED_1                                              (0x7<<5) // reserved
16266     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATUS_UNUSED_1_SHIFT                                        5
16267 #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL0                                                           0x00be4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16268     #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL0_POLYNOMIAL                                            (0x7<<0) // Selects between CL72 and CL93 PRBS pattern. 0 ? CL72 1 + x^9 +x^11 1 ? CL93 1 + x^5 + x^6 + x^10 + x^11 2 ? CL93 1 + x^5 + x^6 + x^9 + x^11 3 ? CL93 1 + x^4 + x^6 + x^8 + x^11 4 ? CL93 1 + x^4 + x^6 + x^7 + x^11
16269     #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL0_POLYNOMIAL_SHIFT                                      0
16270     #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL0_UNUSED_0                                              (0x1f<<3) // reserved
16271     #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL0_UNUSED_0_SHIFT                                        3
16272 #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL1                                                           0x00be50UL //Access:RW   DataWidth:0x8   Initial PRBS LFSR seed.  This needs to be set according to the requirements in 802.3 CL72 or CL93 depending on the type of link training and lane bonding being performed.  Chips: K2
16273 #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL2                                                           0x00be54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16274     #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL2_SEED_10_8                                             (0x7<<0) // Same as above.
16275     #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL2_SEED_10_8_SHIFT                                       0
16276     #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL2_UNUSED_0                                              (0x1f<<3) // reserved
16277     #define PHY_NW_IP_REG_LN2_LT_TX_PRBS_CTRL2_UNUSED_0_SHIFT                                        3
16278 #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL                                              0x00be80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16279     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1                                     (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 ? hold 2'b01 ? increment 2'b10 ? decrement 2'b11 ? reserved
16280     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_SHIFT                               0
16281     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0                                      (0x3<<2) // Coefficient update request field for cursor tap.
16282     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_SHIFT                                2
16283     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1                                     (0x3<<4) // Coefficient update request field for pre-cursor tap.
16284     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_SHIFT                               4
16285     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE                               (0x1<<6) // Coefficient update initialize field.
16286     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_SHIFT                         6
16287     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET                                   (0x1<<7) // Coefficient update preset field.
16288     #define PHY_NW_IP_REG_LN2_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_SHIFT                             7
16289 #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL                                                   0x00be88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16290     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_P1                                          (0x3<<0) // Status report field for post-cursor tap. 2'b00 ? not updated 2'b01 ? minimum 2'b10 ? updated 2'b11 ? maximum
16291     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_P1_SHIFT                                    0
16292     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_0                                           (0x3<<2) // Status report field for cursor tap.
16293     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_0_SHIFT                                     2
16294     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_M1                                          (0x3<<4) // Status report field for pre-cursor tap.
16295     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_C_M1_SHIFT                                    4
16296     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY                                (0x1<<6) // Status report field to indicate local receiver is ready.  Should be set based on LTSM output of corresponding variable.
16297     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_SHIFT                          6
16298     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_UNUSED_0                                      (0x1<<7) // reserved
16299     #define PHY_NW_IP_REG_LN2_LT_TX_STATUS_REPORT_CTRL_UNUSED_0_SHIFT                                7
16300 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0                                                    0x00bec0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16301     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_CURRENT                                        (0x7<<0) // Current state of LTSM. 0x0 ? INITIALIZE 0x1 ? SEND_TRAINING 0x2 ? TRAIN_REMOTE 0x3 ? TRAIN_LOCAL 0x4 ? S7 0x5 ? TRAINING_FAILURE 0x6 ? LINK_READY 0x7 ? SEND_DATA
16302     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_CURRENT_SHIFT                                  0
16303     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_UNUSED_0                                       (0x1<<3) // reserved
16304     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_UNUSED_0_SHIFT                                 3
16305     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_PREV1                                          (0x7<<4) // One state previous.
16306     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_PREV1_SHIFT                                    4
16307     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_UNUSED_1                                       (0x1<<7) // reserved
16308     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS0_UNUSED_1_SHIFT                                 7
16309 #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1                                                    0x00bec4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16310     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_PREV2                                          (0x7<<0) // Two states previous.
16311     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_PREV2_SHIFT                                    0
16312     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_UNUSED_0                                       (0x1<<3) // reserved
16313     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_UNUSED_0_SHIFT                                 3
16314     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_PREV3                                          (0x7<<4) // Three states previous.
16315     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_PREV3_SHIFT                                    4
16316     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_UNUSED_1                                       (0x1<<7) // reserved
16317     #define PHY_NW_IP_REG_LN2_LT_TX_FSM_STATE_STATUS1_UNUSED_1_SHIFT                                 7
16318 #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0                                                                0x00bf00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16319     #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_CLEAR                                                      (0x1<<0) // Synchronous reset for LT Rx block.
16320     #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_CLEAR_SHIFT                                                0
16321     #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_TRAINING                                                   (0x1<<1) // This is the 802.3 defined training variable.  It should be set according to corresponding LTSM output.
16322     #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_TRAINING_SHIFT                                             1
16323     #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_UNUSED_0                                                   (0x3f<<2) // reserved
16324     #define PHY_NW_IP_REG_LN2_LT_RX_CTRL0_UNUSED_0_SHIFT                                             2
16325 #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL0                                                           0x00bf08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16326     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL0_POLYNOMIAL                                            (0x7<<0) // Selects between CL72 and CL93 PRBS patterns. 0 ? CL72 1 + x^9 + x^11 1 ? CL93 1 + x^5 + x^6 + x^10 + x^11 2 ? CL93 1 + x^5 + x^6 + x^9 + x^11 3 ? CL93 1 + x^4 + x^6 + x^8 + x^11 4 ? CL93 1 + x^4 + x^6 + x^7 + x^11
16327     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL0_POLYNOMIAL_SHIFT                                      0
16328     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL0_UNUSED_0                                              (0x1f<<3) // reserved
16329     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL0_UNUSED_0_SHIFT                                        3
16330 #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_CTRL1                                                           0x00bf0cUL //Access:RW   DataWidth:0x8   Maximum number  of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.  Chips: K2
16331 #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0                                                         0x00bf14UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16332     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_UPDATE                                              (0x1<<0) // Assertion indicates that PRBS status information has been updated.
16333     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_UPDATE_SHIFT                                        0
16334     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_LOCK                                                (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
16335     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_LOCK_SHIFT                                          1
16336     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_UNUSED_0                                            (0x3f<<2) // reserved
16337     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS0_UNUSED_0_SHIFT                                      2
16338 #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS1                                                         0x00bf18UL //Access:R    DataWidth:0x8   Number of bit errors in PRBS pattern since last lock assertion event.  Chips: K2
16339 #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS2                                                         0x00bf1cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16340     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8                                    (0xf<<0) // Same as above.
16341     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_SHIFT                              0
16342     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS2_UNUSED_0                                            (0xf<<4) // reserved
16343     #define PHY_NW_IP_REG_LN2_LT_RX_PRBS_STATUS2_UNUSED_0_SHIFT                                      4
16344 #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL                                                           0x00bf40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16345     #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL_CLEAR_COUNT                                           (0x1<<0) // Clears both the absolute and erroneous frame counters.
16346     #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL_CLEAR_COUNT_SHIFT                                     0
16347     #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL_UNUSED_0                                              (0x7f<<1) // reserved
16348     #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_CTRL_UNUSED_0_SHIFT                                        1
16349 #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0                                                        0x00bf4cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16350     #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0_FRAME_LOCK                                         (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
16351     #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0_FRAME_LOCK_SHIFT                                   0
16352     #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0_UNUSED_0                                           (0x7f<<1) // reserved
16353     #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS0_UNUSED_0_SHIFT                                     1
16354 #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS1                                                        0x00bf50UL //Access:R    DataWidth:0x8   Total number of received frames since frame lock.  Chips: K2
16355 #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS2                                                        0x00bf54UL //Access:R    DataWidth:0x8   Same as above.  Chips: K2
16356 #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS3                                                        0x00bf58UL //Access:R    DataWidth:0x8   Total number of received frames  with a PRBS, DME, or framing error since frame lock.  Chips: K2
16357 #define PHY_NW_IP_REG_LN2_LT_RX_FRAME_STATUS4                                                        0x00bf5cUL //Access:R    DataWidth:0x8   Same as above.  Chips: K2
16358 #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS                                            0x00bf80UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16359     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1                                   (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 ? hold 2'b01 ? increment 2'b10 ? decrement 2'b11 ? reserved
16360     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_SHIFT                             0
16361     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0                                    (0x3<<2) // Received coefficient update request field for cursor tap.
16362     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_SHIFT                              2
16363     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1                                   (0x3<<4) // Received coefficient update request field for pre-cursor tap.
16364     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_SHIFT                             4
16365     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE                             (0x1<<6) // Received coefficient update initialize field.
16366     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_SHIFT                       6
16367     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET                                 (0x1<<7) // Received coefficient update preset field.
16368     #define PHY_NW_IP_REG_LN2_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_SHIFT                           7
16369 #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS                                                        0x00bf88UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16370     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_P1                                               (0x3<<0) // Received status report field for post-cursor tap. 2'b00 ? not updated 2'b01 ? minimum 2'b10 ? updated 2'b11 ? maximum
16371     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_P1_SHIFT                                         0
16372     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_0                                                (0x3<<2) // Received status report field for cursor tap.
16373     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_0_SHIFT                                          2
16374     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_M1                                               (0x3<<4) // Received status report field for pre-cursor tap.
16375     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_C_M1_SHIFT                                         4
16376     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_LOCAL_RX_READY                                     (0x1<<6) // Received status report field to indicate local receiver is ready.
16377     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_LOCAL_RX_READY_SHIFT                               6
16378     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_DME_ERROR                                          (0x1<<7) // Indicates differential manchester decoding error.  Not sticky.
16379     #define PHY_NW_IP_REG_LN2_LT_RX_REPORT_STATUS_DME_ERROR_SHIFT                                    7
16380 #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL                                                      0x00c000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16381     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN                                (0x1<<0) // RX clock loopback mode enable.   0x0 - mission mode 0x1 - select recovered clock from CDR as source of half-rate TX clock path.
16382     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_RXCLK_EN_SHIFT                          0
16383     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN                                (0x1<<1) // TX clock loopback mode enable.  0x0 - mission mode 0x1 - MUX half-rate TX clock into LEQ gain stage.
16384     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_TXCLK_EN_SHIFT                          1
16385     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN                                  (0x1<<2) // Far-End Analog FEA loopback mode enable.  0x0 - mission mode 0x1 - loop back parallel data from RX data path to TX data path internal to AFE
16386     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_FEA_EN_SHIFT                            2
16387     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN                                  (0x1<<3) // Near-End Analog NEA loopback mode enable.  0x0 - mission mode 0x1 - loop back quarter rate data from TX data path to RX data path internal to AFE.
16388     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_LOOPBACK_NEA_EN_SHIFT                            3
16389     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_UNUSED_0                                         (0xf<<4) // reserved
16390     #define PHY_NW_IP_REG_LN3_TOP_AFE_LOOPBACK_CTRL_UNUSED_0_SHIFT                                   4
16391 #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1                                                         0x00c088UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16392     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN                                 (0x1<<0) // Enables register control of TX data path mux in DPL
16393     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_EN_SHIFT                           0
16394     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL                                (0x7<<1) // Select value for TX data path mux in DPL.  The corresponding mux select override enable must also be set. 0 : TX data from customer logics 1: RX data for Far-End-Digital FED loopback 2: BIST generator 3: AN/802.3 4: LT/802.3 5-7: reserved
16395     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_SEL_OVR_VAL_SHIFT                          1
16396     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_TXPOLARITY                                          (0x1<<4) // TX data polarity control
16397     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_TXPOLARITY_SHIFT                                    4
16398     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN                               (0x1<<5) // Controls tx_en for Far-End-Digital FED loopback mode.  In FED loopback mode, tx_en will be set when this field is set to 1 and rxvalid is 1.
16399     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_DMUX_TXA_LB_FED_TX_EN_SHIFT                         5
16400     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_UNUSED_0                                            (0x3<<6) // reserved
16401     #define PHY_NW_IP_REG_LN3_TOP_DPL_TXDP_CTRL1_UNUSED_0_SHIFT                                      6
16402 #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1                                                         0x00c090UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16403     #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL                                         (0x1<<0) // A mux select for RX data path in the DPL 0: AFE rx data 1: TX data for Near-End-Digital NED loopback
16404     #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_DMUX_RX_SEL_SHIFT                                   0
16405     #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN                                      (0x1<<1) // A bit stripping selection for RX data path in the DPL 1: Even bits stripped from RX data 0: Odd bits stripped from Rx data
16406     #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_BIT_STRIP_EVEN_SHIFT                                1
16407     #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_UNUSED_0                                            (0x3f<<2) // reserved
16408     #define PHY_NW_IP_REG_LN3_TOP_DPL_RXDP_CTRL1_UNUSED_0_SHIFT                                      2
16409 #define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS                                                          0x00c09cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16410     #define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS_LN_OK                                                (0x1<<0) // LANE OK status
16411     #define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS_LN_OK_SHIFT                                          0
16412     #define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS_UNUSED_0                                             (0x7f<<1) // reserved
16413     #define PHY_NW_IP_REG_LN3_TOP_PHY_IF_STATUS_UNUSED_0_SHIFT                                       1
16414 #define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0                                                          0x00c0e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16415     #define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0_RXVALID                                              (0x1<<0) // rxvalid status output
16416     #define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0_RXVALID_SHIFT                                        0
16417     #define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0_UNUSED_0                                             (0x7f<<1) // reserved
16418     #define PHY_NW_IP_REG_LN3_TOP_LN_STAT_CTRL0_UNUSED_0_SHIFT                                       1
16419 #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0                                                           0x00c0ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16420     #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_OVR_EN                                                (0x1<<0) // override enable for lnX_ctrl_*_i signals in this register
16421     #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_OVR_EN_SHIFT                                          0
16422     #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH                                         (0x7<<1) // lnX_data_width_i override value for TX.  It takes effect when ovr_en is 1. 0x5- Maximum width 40b 0x3-half width 20b 0x1-quarter width 10b, others, reserved.
16423     #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_TX_DATA_WIDTH_SHIFT                                   1
16424     #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH                                         (0x7<<4) // lnX_data_width_i override value for RX.  It takes effect when ovr_en is 1.
16425     #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_RX_DATA_WIDTH_SHIFT                                   4
16426     #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_UNUSED_0                                              (0x1<<7) // reserved
16427     #define PHY_NW_IP_REG_LN3_TOP_LN_CTRL_OVR0_UNUSED_0_SHIFT                                        7
16428 #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL1                                                              0x00c140UL //Access:RW   DataWidth:0x8   lower 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
16429 #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL2                                                              0x00c144UL //Access:RW   DataWidth:0x8   higher 8-bits of 16-bit lane error code.  0x0 - indicates that there is no error rest - reserved  Chips: K2
16430 #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3                                                              0x00c148UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16431     #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3_LANE_ERR                                                 (0x1<<0) // Lane macro error status. 0x0 - no error 0x1 - PHY lane macro has an internal error detected by firmware. Lane error code can be used to isolate error event.
16432     #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3_LANE_ERR_SHIFT                                           0
16433     #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3_UNUSED_0                                                 (0x7f<<1) // reserved
16434     #define PHY_NW_IP_REG_LN3_TOP_ERR_CTRL3_UNUSED_0_SHIFT                                           1
16435 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS2                                                     0x00c2fcUL //Access:R    DataWidth:0x8   Binary-coded DLPF control input to the CDR  Chips: K2
16436 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3                                                     0x00c300UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16437     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8                                    (0x1<<0) // Binary-coded DLPF control input to the CDR
16438     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3_BINARY_VAL_8_SHIFT                              0
16439     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3_UNUSED_0                                        (0x7f<<1) // reserved
16440     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS3_UNUSED_0_SHIFT                                  1
16441 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4                                                     0x00c304UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16442     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH                                   (0x1<<0) // Indicates that DLPF control input to CDR is too high
16443     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_HIGH_SHIFT                             0
16444     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW                                    (0x1<<1) // Indicates that DLPF control input to CDR is too low
16445     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_DLPF_TOO_LOW_SHIFT                              1
16446     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST                                       (0x1<<2) // CDR loss of lock indicator.  1 means lock has been lost. Once lock is lost, this status is sticky until cleared by disabling the loss-of-lock detector by setting set lock_en_i to 0.
16447     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_LOCK_LOST_SHIFT                                 2
16448     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_UNUSED_0                                        (0x1f<<3) // reserved
16449     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS4_UNUSED_0_SHIFT                                  3
16450 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5                                                     0x00c310UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16451     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5_LOCKED                                          (0x1<<0) // CDR lock indicator.  1 means lock is achieved. It is cleared when lock detector is disabled by setting set lock_en_i to 0.
16452     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5_LOCKED_SHIFT                                    0
16453     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5_UNUSED_0                                        (0x7f<<1) // reserved
16454     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_DLPF_STATUS5_UNUSED_0_SHIFT                                  1
16455 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS0                                                 0x00c314UL //Access:R    DataWidth:0x8   Value of the accumulator in the CDR integral path  Chips: K2
16456 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS1                                                 0x00c318UL //Access:R    DataWidth:0x8   Value of the accumulator in the CDR integral path  Chips: K2
16457 #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS2                                                 0x00c320UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16458     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16                           (0xf<<0) // Value of the accumulator in the CDR integral path
16459     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS2_ACCUMULATOR_19_16_SHIFT                     0
16460     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS2_UNUSED_0                                    (0xf<<4) // reserved
16461     #define PHY_NW_IP_REG_LN3_CDR_RXCLK_INTEGRAL_STATUS2_UNUSED_0_SHIFT                              4
16462 #define PHY_NW_IP_REG_LN3_ANEG_CFG10                                                                 0x00c628UL //Access:RW   DataWidth:0x8   Seed provided to the transmit nonce generator polynomial  Chips: K2
16463 #define PHY_NW_IP_REG_LN3_ANEG_CFG11                                                                 0x00c62cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16464     #define PHY_NW_IP_REG_LN3_ANEG_CFG11_PSEUDO_SEL                                                  (0x1<<0) // Selector for the DME page bit 49 pseudo-random generator
16465     #define PHY_NW_IP_REG_LN3_ANEG_CFG11_PSEUDO_SEL_SHIFT                                            0
16466     #define PHY_NW_IP_REG_LN3_ANEG_CFG11_UNUSED_0                                                    (0x7f<<1) // reserved
16467     #define PHY_NW_IP_REG_LN3_ANEG_CFG11_UNUSED_0_SHIFT                                              1
16468 #define PHY_NW_IP_REG_LN3_ANEG_CTRL0                                                                 0x00c630UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16469     #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_AUTONEG_RESTART                                             (0x1<<0) // Restarts AN that is already in progress or otherwise completed.  Reset is triggered by rising edge of this signal.  Not self clearing.
16470     #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_AUTONEG_RESTART_SHIFT                                       0
16471     #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_UNUSED_0                                                    (0x7f<<1) // reserved
16472     #define PHY_NW_IP_REG_LN3_ANEG_CTRL0_UNUSED_0_SHIFT                                              1
16473 #define PHY_NW_IP_REG_LN3_ANEG_STATUS0                                                               0x00c640UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16474     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LP_AUTONEG_ABLE                                           (0x1<<0) // The link partner Auto-Negotiation ability bit shall be set to one to indicate that the link partner is able to participate in the Auto-Negotiation function. This bit shall be reset to zero if the link partner is not Auto- Negotiation able.
16475     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LP_AUTONEG_ABLE_SHIFT                                     0
16476     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_UNUSED_0                                                  (0x1<<1) // reserved
16477     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_UNUSED_0_SHIFT                                            1
16478     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LINK_STATUS                                               (0x1<<2) // Local link Status.  When read as a one, it indicates that the PMA/PMD has determined that a valid link has been established i.e. link_status[HDC] equals OK. When read as a zero, it indicates that the link is not valid.
16479     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_LINK_STATUS_SHIFT                                         2
16480     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_ABILITY                                           (0x1<<3) // Autoneg ability.  When read as a one, it indicates that the PMA/PMD has the ability to perform Auto-Negotiation.  When read as a zero, it indicates that the PMA/PMD lacks the ability to perform Auto-Negotiation.
16481     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_ABILITY_SHIFT                                     3
16482     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_REMOTE_FAULT                                      (0x1<<4) // Remote Fault
16483     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_REMOTE_FAULT_SHIFT                                4
16484     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_COMPLETE                                          (0x1<<5) // Autoneg has completed and autoneg arbitration FSM is in AN GOOD state.
16485     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_AUTONEG_COMPLETE_SHIFT                                    5
16486     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_UNUSED_1                                                  (0x3<<6) // reserved
16487     #define PHY_NW_IP_REG_LN3_ANEG_STATUS0_UNUSED_1_SHIFT                                            6
16488 #define PHY_NW_IP_REG_LN3_ANEG_STATUS1                                                               0x00c644UL //Access:W    DataWidth:0x8   Multi Field Register.  Chips: K2
16489     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PAGE_RX                                                   (0x1<<0) // Page Received.   To clear it, write 1 to it.
16490     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PAGE_RX_SHIFT                                             0
16491     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_AN_LINK_GOOD                                              (0x1<<1) // Autoneg has completed and autoneg arbitration FSM is in either AN GOOD CHECK or AN GOOD state.
16492     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_AN_LINK_GOOD_SHIFT                                        1
16493     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PARALLEL_DET_FAULT                                        (0x1<<2) // Autoneg Parallel Detection Fault.  Write 1 to clear it.
16494     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_PARALLEL_DET_FAULT_SHIFT                                  2
16495     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_NP_LOADED                                                 (0x1<<3) // mr_np_loaded status.
16496     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_NP_LOADED_SHIFT                                           3
16497     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_UNUSED_0                                                  (0xf<<4) // reserved
16498     #define PHY_NW_IP_REG_LN3_ANEG_STATUS1_UNUSED_0_SHIFT                                            4
16499 #define PHY_NW_IP_REG_LN3_ANEG_STATUS_DBG0                                                           0x00c650UL //Access:R    DataWidth:0x8   One-hot sticky capture of AN FSM states.  Bits 7-0  Chips: K2
16500 #define PHY_NW_IP_REG_LN3_ANEG_STATUS_DBG1                                                           0x00c654UL //Access:R    DataWidth:0x8   One-hot sticky capture of AN FSM states.  Bits 15-8  Chips: K2
16501 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0                                                            0x00c660UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16502     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_SELECTOR                                               (0x1f<<0) // technology Select Field
16503     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_SELECTOR_SHIFT                                         0
16504     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0                                       (0x7<<5) // Echoed Nonce Field bits 2-0.  AN controller generates it.
16505     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE0_ECHOED_NONCE_2_0_SHIFT                                 5
16506 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1                                                            0x00c664UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16507     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3                                       (0x3<<0) // Echoed Nonce Field bits 4-3.    AN controller generates it.
16508     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ECHOED_NONCE_4_3_SHIFT                                 0
16509     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_PAUSE                                                  (0x1<<2) // Pause advertised ability
16510     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_PAUSE_SHIFT                                            2
16511     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ASM_DIR                                                (0x1<<3) // Pause ASM_DIR advertised ability
16512     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_ASM_DIR_SHIFT                                          3
16513     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_C2                                                     (0x1<<4) // Reserved always 0
16514     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_C2_SHIFT                                               4
16515     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_REMOTE_FAULT                                           (0x1<<5) // Remote Fault Local Device
16516     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_REMOTE_FAULT_SHIFT                                     5
16517     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_UNUSED_0                                               (0x1<<6) // reserved
16518     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_UNUSED_0_SHIFT                                         6
16519     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_NEXT_PAGE                                              (0x1<<7) // Next Page
16520     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE1_NEXT_PAGE_SHIFT                                        7
16521 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE2                                                            0x00c668UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16522     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE2_TX_NONCE                                               (0x1f<<0) // Transmitted Nonce Field.  It is generated in hardware.
16523     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE2_TX_NONCE_SHIFT                                         0
16524     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE2_UNUSED_0                                               (0x7<<5) // reserved
16525     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE2_UNUSED_0_SHIFT                                         5
16526 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0                                                       0x00c66cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16527     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX                                     (0x1<<0) // 1000Base-KX technology advertised ability
16528     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_1G_KX_SHIFT                               0
16529     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4                                   (0x1<<1) // 10GBase-KX4 technology advertised ability
16530     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KX4_SHIFT                             1
16531     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR                                    (0x1<<2) // 10GBase-KR technology advertised ability
16532     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_10G_KR_SHIFT                              2
16533     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4                                   (0x1<<3) // 40GBase-KR4 technology advertised ability
16534     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_KR4_SHIFT                             3
16535     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4                                   (0x1<<4) // 40GBase-CR4 technology advertised ability
16536     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_40G_CR4_SHIFT                             4
16537     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10                                 (0x1<<5) // 100GBase-CR10 technology advertised ability
16538     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_CR10_SHIFT                           5
16539     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4                                  (0x1<<6) // 100GBase-KP4 technology advertised ability
16540     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KP4_SHIFT                            6
16541     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4                                  (0x1<<7) // 100GBase-KR4 technology advertised ability
16542     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH0_ABILITY_100G_KR4_SHIFT                            7
16543 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1                                                       0x00c670UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16544     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4                                  (0x1<<0) // 100GBase-CR4 technology advertised ability
16545     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_100G_CR4_SHIFT                            0
16546     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S                                  (0x1<<1) // 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
16547     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_S_SHIFT                            1
16548     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR                                    (0x1<<2) // 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
16549     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_25G_GR_SHIFT                              2
16550     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11                                   (0x1f<<3) // technology advertised ability Field A15-A11
16551     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH1_ABILITY_A15_A11_SHIFT                             3
16552 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH2                                                       0x00c674UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16553     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16                                   (0x7f<<0) // technology advertised ability Field A22-A16
16554     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH2_ABILITY_A22_A16_SHIFT                             0
16555     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH2_UNUSED_0                                          (0x1<<7) // reserved
16556     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_TECH2_UNUSED_0_SHIFT                                    7
16557 #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC                                                         0x00c678UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16558     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_ABILITY                                         (0x1<<0) // base page bit F0.  It advertises FEC ability
16559     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_ABILITY_SHIFT                                   0
16560     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_REQ                                             (0x1<<1) // base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
16561     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FEC_REQ_SHIFT                                       1
16562     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G                                      (0x1<<2) // base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
16563     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_RS_FEC_REQ_25G_SHIFT                                2
16564     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G                                      (0x1<<3) // base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
16565     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_FC_FEC_REQ_25G_SHIFT                                3
16566     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_UNUSED_0                                            (0xf<<4) // reserved
16567     #define PHY_NW_IP_REG_LN3_ANEG_BASE_PAGE_FEC_UNUSED_0_SHIFT                                      4
16568 #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0                                                             0x00c67cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16569     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_KR                                          (0x1<<0) // 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
16570     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_KR_SHIFT                                    0
16571     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_CR                                          (0x1<<1) // 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
16572     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_25G_CR_SHIFT                                    1
16573     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_KR2                                         (0x1<<2) // 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
16574     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_KR2_SHIFT                                   2
16575     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_CR2                                         (0x1<<3) // 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
16576     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_ABILITY_50G_CR2_SHIFT                                   3
16577     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_ABILITY                                          (0x1<<4) // Extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
16578     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_ABILITY_SHIFT                                    4
16579     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_ABILITY                                          (0x1<<5) // Extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
16580     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_ABILITY_SHIFT                                    5
16581     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_REQ                                              (0x1<<6) // Extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
16582     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_RS_FEC_REQ_SHIFT                                        6
16583     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_REQ                                              (0x1<<7) // Extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
16584     #define PHY_NW_IP_REG_LN3_ANEG_EXTENDED0_FC_FEC_REQ_SHIFT                                        7
16585 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0                                                         0x00c6a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16586     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_SELECTOR                                            (0x1f<<0) // Link partner technology Select Field
16587     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_SELECTOR_SHIFT                                      0
16588     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0                                    (0x7<<5) // Link partner Echoed Nonce Field bits 2-0
16589     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE0_ECHOED_NONCE_2_0_SHIFT                              5
16590 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1                                                         0x00c6a4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16591     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3                                    (0x3<<0) // Link partner Echoed Nonce Field bits 4-3
16592     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ECHOED_NONCE_4_3_SHIFT                              0
16593     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_PAUSE                                               (0x1<<2) // Link partner Pause advertised ability
16594     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_PAUSE_SHIFT                                         2
16595     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ASM_DIR                                             (0x1<<3) // Link partner Pause ASM_DIR advertised ability
16596     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ASM_DIR_SHIFT                                       3
16597     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_C2                                                  (0x1<<4) // Link partner C2 field always 0
16598     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_C2_SHIFT                                            4
16599     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_REMOTE_FAULT                                        (0x1<<5) // Link partner Remote Fault
16600     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_REMOTE_FAULT_SHIFT                                  5
16601     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ACK                                                 (0x1<<6) // Link partner Acknowledge always 0
16602     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_ACK_SHIFT                                           6
16603     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_NEXT_PAGE                                           (0x1<<7) // Link partner Next Page
16604     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE1_NEXT_PAGE_SHIFT                                     7
16605 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE2                                                         0x00c6a8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16606     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE2_TX_NONCE                                            (0x1f<<0) // Transmitted Nonce Field from Link partner
16607     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE2_TX_NONCE_SHIFT                                      0
16608     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE2_UNUSED_0                                            (0x7<<5) // reserved
16609     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE2_UNUSED_0_SHIFT                                      5
16610 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0                                                    0x00c6acUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16611     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX                                  (0x1<<0) // Link partner 1000Base-KX technology advertised ability
16612     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_1G_KX_SHIFT                            0
16613     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4                                (0x1<<1) // Link partner 10GBase-KX4 technology advertised ability
16614     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KX4_SHIFT                          1
16615     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR                                 (0x1<<2) // Link partner 10GBase-KR technology advertised ability
16616     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_10G_KR_SHIFT                           2
16617     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4                                (0x1<<3) // Link partner 40GBase-KR4 technology advertised ability
16618     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_KR4_SHIFT                          3
16619     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4                                (0x1<<4) // Link partner 40GBase-CR4 technology advertised ability
16620     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_40G_CR4_SHIFT                          4
16621     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10                              (0x1<<5) // Link partner 100GBase-CR10 technology advertised ability
16622     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_CR10_SHIFT                        5
16623     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4                               (0x1<<6) // Link partner 100GBase-KP4 technology advertised ability
16624     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KP4_SHIFT                         6
16625     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4                               (0x1<<7) // Link partner 100GBase-KR4 technology advertised ability
16626     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH0_ABILITY_100G_KR4_SHIFT                         7
16627 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1                                                    0x00c6b0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16628     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4                               (0x1<<0) // Link partner 100GBase-CR4 technology advertised ability
16629     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_100G_CR4_SHIFT                         0
16630     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S                               (0x1<<1) // Link partner 25GBase-GR-S KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A9 in base page.
16631     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_S_SHIFT                         1
16632     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR                                 (0x1<<2) // Link partner 25GBase-GR KR or CR technology advertised ability.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A10 in base page.
16633     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_25G_GR_SHIFT                           2
16634     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11                                (0x1f<<3) // Link partner technology advertised ability Field A15-A11
16635     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH1_ABILITY_A15_A11_SHIFT                          3
16636 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH2                                                    0x00c6b4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16637     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16                                (0x7f<<0) // Link partner technology advertised ability Field A22-A16
16638     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH2_ABILITY_A22_A16_SHIFT                          0
16639     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH2_UNUSED_0                                       (0x1<<7) // reserved
16640     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_TECH2_UNUSED_0_SHIFT                                 7
16641 #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC                                                      0x00c6b8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16642     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY                                      (0x1<<0) // Link partner base page bit F0.  It advertises FEC ability
16643     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_ABILITY_SHIFT                                0
16644     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_REQ                                          (0x1<<1) // Link partner base page bit F1.  It requests FEC to be turned on when supported at the both ends of link
16645     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FEC_REQ_SHIFT                                    1
16646     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G                                   (0x1<<2) // Link partner base page bit F2.  It requests RS-FEC for 25G-GR 25G-KR/-CR link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A23 in base page.
16647     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_RS_FEC_REQ_25G_SHIFT                             2
16648     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G                                   (0x1<<3) // Link partner base page bit F3.  It requests FC-FEC Base-R FEC for 25G-GR or 25G-GR-S 25G-KR/-CR or 25G-KR-S/-CR-S link.  It is defined in IEEE 802.3by.  For prior versions, it corresponds to A24 in base page.
16649     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_FC_FEC_REQ_25G_SHIFT                             3
16650     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_UNUSED_0                                         (0xf<<4) // reserved
16651     #define PHY_NW_IP_REG_LN3_ANEG_LP_BASE_PAGE_FEC_UNUSED_0_SHIFT                                   4
16652 #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0                                                          0x00c6bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16653     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_KR                                       (0x1<<0) // Link partner 25GBase-KR technology advertised ability for 25G/50G consortium specification non-IEEE
16654     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_KR_SHIFT                                 0
16655     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_CR                                       (0x1<<1) // Link partner 25GBase-CR technology advertised ability for 25G/50G consortium specification non-IEEE
16656     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_25G_CR_SHIFT                                 1
16657     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_KR2                                      (0x1<<2) // Link partner 50GBase-KR2 technology advertised ability for 25G/50G consortium specification non-IEEE
16658     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_KR2_SHIFT                                2
16659     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_CR2                                      (0x1<<3) // Link partner 50GBase-CR2 technology advertised ability for 25G/50G consortium specification non-IEEE
16660     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_ABILITY_50G_CR2_SHIFT                                3
16661     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_ABILITY                                       (0x1<<4) // Link partner extended advertised FEC field 0.  It advertises Reed-Solomon FEC CL91 ability for 25G/50G consortium specification non-IEEE
16662     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_ABILITY_SHIFT                                 4
16663     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_ABILITY                                       (0x1<<5) // Link partner extended advertised FEC field 1.  It advertises Fire code FEC CL74 ability for 25G/50G consortium specification non-IEEE
16664     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_ABILITY_SHIFT                                 5
16665     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_REQ                                           (0x1<<6) // Link partner extended advertised FEC field 2.  It requests Reed-Solomon FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
16666     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_RS_FEC_REQ_SHIFT                                     6
16667     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_REQ                                           (0x1<<7) // Link partner extended advertised FEC field 3.  It requests Fire code FEC to be turned on when supported at the both ends of link for 25G/50G consortium specification non-IEEE
16668     #define PHY_NW_IP_REG_LN3_ANEG_LP_EXTENDED0_FC_FEC_REQ_SHIFT                                     7
16669 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0                                                      0x00c6e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16670     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX                                    (0x1<<0) // Resolution result for 1000Base-KX.  It is valid when status0.an_link_good is 1.
16671     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_1G_KX_SHIFT                              0
16672     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4                                  (0x1<<1) // Resolution result for 10GBase-KX4.  It is valid when status0.an_link_good is 1.
16673     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KX4_SHIFT                            1
16674     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR                                   (0x1<<2) // Resolution result for 10GBase-KR.  It is valid when status0.an_link_good is 1.
16675     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_10G_KR_SHIFT                             2
16676     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4                                  (0x1<<3) // Resolution result for 40GBase-KR4.  It is valid when status0.an_link_good is 1.
16677     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_KR4_SHIFT                            3
16678     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4                                  (0x1<<4) // Resolution result for 40GBase-CR4.  It is valid when status0.an_link_good is 1.
16679     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_40G_CR4_SHIFT                            4
16680     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10                                (0x1<<5) // Resolution result for 100GBase-CR10.  It is valid when status0.an_link_good is 1.
16681     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_CR10_SHIFT                          5
16682     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4                                 (0x1<<6) // Resolution result for 100GBase-KP4.  It is valid when status0.an_link_good is 1.
16683     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KP4_SHIFT                           6
16684     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4                                 (0x1<<7) // Resolution result for 100GBase-KR4.  It is valid when status0.an_link_good is 1.
16685     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH0_ABILITY_100G_KR4_SHIFT                           7
16686 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1                                                      0x00c6e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16687     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4                                 (0x1<<0) // Resolution result for 100GBase-CR4.  It is valid when status0.an_link_good is 1.
16688     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_100G_CR4_SHIFT                           0
16689     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S                                 (0x1<<1) // Resolution result for 25GBase-GR-S KR or CR.  It is valid when status0.an_link_good is 1.
16690     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_S_SHIFT                           1
16691     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR                                   (0x1<<2) // Resolution result for 25GBase-GR KR or CR.  It is valid when status0.an_link_good is 1.
16692     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_GR_SHIFT                             2
16693     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR                                   (0x1<<3) // Resolution result for 25GBase-KR.  It is valid when status0.an_link_good is 1.
16694     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_KR_SHIFT                             3
16695     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR                                   (0x1<<4) // Resolution result for 25GBase-CR4.  It is valid when status0.an_link_good is 1.
16696     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_25G_CR_SHIFT                             4
16697     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2                                  (0x1<<5) // Resolution result for 50GBase-KR2.  It is valid when status0.an_link_good is 1.
16698     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_KR2_SHIFT                            5
16699     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2                                  (0x1<<6) // Resolution result for 50GBase-CR2.  It is valid when status0.an_link_good is 1.
16700     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_ABILITY_50G_CR2_SHIFT                            6
16701     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_UNUSED_0                                         (0x1<<7) // reserved
16702     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_TECH1_UNUSED_0_SHIFT                                   7
16703 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC                                                        0x00c6e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16704     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_RS                                                 (0x1<<0) // Resolution result for Reed-Solomon FEC.  It is valid when status0.an_link_good is 1.
16705     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_RS_SHIFT                                           0
16706     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_FC                                                 (0x1<<1) // Resolution result for Firecode base page FEC.  It is valid when status0.an_link_good is 1.
16707     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_FC_SHIFT                                           1
16708     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_UNUSED_0                                           (0x3f<<2) // reserved
16709     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_FEC_UNUSED_0_SHIFT                                     2
16710 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE                                                      0x00c6ecUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16711     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_RX                                               (0x1<<0) // Resolution result for RX PAUSE enable.    It is valid when status0.an_link_good is 1.
16712     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_RX_SHIFT                                         0
16713     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_TX                                               (0x1<<1) // Resolution result for TX PAUSE enable.    It is valid when status0.an_link_good is 1.
16714     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_TX_SHIFT                                         1
16715     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_UNUSED_0                                         (0x3f<<2) // reserved
16716     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_PAUSE_UNUSED_0_SHIFT                                   2
16717 #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE                                                        0x00c6f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16718     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE_F823                                               (0x1<<0) // Resolution result for EEE.  It is 1 if both the local device and the link partner advertise the EEE capability for the resolved PHY type.  It is 0 otherwise.  It is valid when status0.an_link_good is 1. Note that it indicates EEE deep sleep capability.
16719     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE_F823_SHIFT                                         0
16720     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE_UNUSED_0                                           (0x7f<<1) // reserved
16721     #define PHY_NW_IP_REG_LN3_ANEG_RESOLUTION_EEE_UNUSED_0_SHIFT                                     1
16722 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0                                                          0x00c6f8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16723     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_1G_KX                                        (0x1<<0) // link_status for 1000Base-KX
16724     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_1G_KX_SHIFT                                  0
16725     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KX4                                      (0x1<<1) // link_status for 10GBase-KX4
16726     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KX4_SHIFT                                1
16727     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KR                                       (0x1<<2) // link_status for 10GBase-KR
16728     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_10G_KR_SHIFT                                 2
16729     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_KR4                                      (0x1<<3) // link_status for 40GBase-KR4
16730     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_KR4_SHIFT                                3
16731     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_CR4                                      (0x1<<4) // link_status for 40GBase-CR4
16732     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_40G_CR4_SHIFT                                4
16733     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_CR10                                    (0x1<<5) // link_status for 100GBase-CR10
16734     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_CR10_SHIFT                              5
16735     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KP4                                     (0x1<<6) // link_status for 100GBase-KP4
16736     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KP4_SHIFT                               6
16737     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KR4                                     (0x1<<7) // link_status for 100GBase-KR4
16738     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS0_ABILITY_100G_KR4_SHIFT                               7
16739 #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1                                                          0x00c6fcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16740     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_100G_CR4                                     (0x1<<0) // link_status for 100GBase-CR4
16741     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_100G_CR4_SHIFT                               0
16742     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_GR                                       (0x1<<1) // link_status for 25GBase-GR KR/CR or 25GBase-GR-S KR-S/CR-S
16743     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_GR_SHIFT                                 1
16744     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_UNUSED_0                                             (0x1<<2) // reserved
16745     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_UNUSED_0_SHIFT                                       2
16746     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_KR                                       (0x1<<3) // link_status for 25GBase-KR
16747     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_KR_SHIFT                                 3
16748     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_CR                                       (0x1<<4) // link_status for 25GBase-CR4
16749     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_25G_CR_SHIFT                                 4
16750     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_KR2                                      (0x1<<5) // link_status for 50GBase-KR2
16751     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_KR2_SHIFT                                5
16752     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_CR2                                      (0x1<<6) // link_status for 50GBase-CR2
16753     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_ABILITY_50G_CR2_SHIFT                                6
16754     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_UNUSED_1                                             (0x1<<7) // reserved
16755     #define PHY_NW_IP_REG_LN3_ANEG_LINK_STATUS1_UNUSED_1_SHIFT                                       7
16756 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_AGCLOS_CTRL0                                                    0x00c8c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16757     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START                                   (0xf<<0) // AGC LOS Threshold Start Value
16758     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_AGCLOS_CTRL0_AGCLOS_START_SHIFT                             0
16759     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_AGCLOS_CTRL0_UNUSED_0                                       (0xf<<4) // reserved
16760     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_AGCLOS_CTRL0_UNUSED_0_SHIFT                                 4
16761 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_PLE_ATT_CTRL1                                                   0x00c8f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16762     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START                                 (0x7<<0) // PLE LFG Start Value
16763     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_PLE_ATT_CTRL1_PLE_ATT_START_SHIFT                           0
16764     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_PLE_ATT_CTRL1_UNUSED_0                                      (0x1f<<3) // reserved
16765     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_PLE_ATT_CTRL1_UNUSED_0_SHIFT                                3
16766 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_HFG_SQL_CTRL0                                                0x00c900UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16767     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START                           (0x1f<<0) // CTLE HFG Start Value
16768     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_EQ_HFG_SQL_START_SHIFT                     0
16769     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_UNUSED_0                                   (0x7<<5) // reserved
16770     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_HFG_SQL_CTRL0_UNUSED_0_SHIFT                             5
16771 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_GN_APG_CTRL0                                                    0x00c9c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16772     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START                                   (0x3<<0) // GN APG Start Value
16773     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_GN_APG_CTRL0_GN_APG_START_SHIFT                             0
16774     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_GN_APG_CTRL0_UNUSED_0                                       (0x3f<<2) // reserved
16775     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_GN_APG_CTRL0_UNUSED_0_SHIFT                                 2
16776 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL0                                                    0x00ca00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16777     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START                                   (0x1f<<0) // EQ LFG Start Value
16778     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL0_EQ_LFG_START_SHIFT                             0
16779     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL0_UNUSED_0                                       (0x7<<5) // reserved
16780     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL0_UNUSED_0_SHIFT                                 5
16781 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL1                                                    0x00ca04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16782     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX                               (0x1f<<0) // EQ LFG Maximum Value, inclusive
16783     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL1_EQ_LFG_VALUE_MAX_SHIFT                         0
16784     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL1_UNUSED_0                                       (0x7<<5) // reserved
16785     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL1_UNUSED_0_SHIFT                                 5
16786 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL2                                                    0x00ca08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16787     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN                               (0x1f<<0) // EQ LFG Minimum Value, inclusive
16788     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL2_EQ_LFG_VALUE_MIN_SHIFT                         0
16789     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL2_UNUSED_0                                       (0x7<<5) // reserved
16790     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_LFG_CTRL2_UNUSED_0_SHIFT                                 5
16791 #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1                                                     0x00ca64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16792     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START                                    (0xf<<0) // EQ MBF Start Value
16793     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBF_START_SHIFT                              0
16794     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START                                    (0xf<<4) // EQ MBG Start Value
16795     #define PHY_NW_IP_REG_LN3_LEQ_REFCLK_EQ_MB_CTRL1_EQ_MBG_START_SHIFT                              4
16796 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_PD_CTRL0                                                    0x00ce00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16797     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV                                       (0xf<<0) // power down TX driver
16798     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_PD_CTRL0_PD_TXDRV_SHIFT                                 0
16799     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_PD_CTRL0_UNUSED_0                                       (0xf<<4) // reserved
16800     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_PD_CTRL0_UNUSED_0_SHIFT                                 4
16801 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_CTRL0                                                       0x00ce08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16802     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE                                     (0x3<<0) // When HIGH, TX driver goes into a low power IDLE model. In this mode, the output termination is not guaranteed to be 50 Ohm closer to 200 Ohm
16803     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_CTRL0_TXDRV_LP_IDLE_SHIFT                               0
16804     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_CTRL0_UNUSED_0                                          (0x3f<<2) // reserved
16805     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_AFE_CTRL0_UNUSED_0_SHIFT                                    2
16806 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0                                                      0x00ce40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16807     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0_REQ                                              (0x1<<0) // Set to 1 to apply the coefficient settings, and hold until ack is 1.  Set to 0 once ack is 1.
16808     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0_REQ_SHIFT                                        0
16809     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0_UNUSED_0                                         (0x7f<<1) // reserved
16810     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL0_UNUSED_0_SHIFT                                   1
16811 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0                                                    0x00ce44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16812     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0_ACK                                            (0x1<<0) // Set to 1 by firmware when updates are complete. Cleared when req = 0
16813     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0_ACK_SHIFT                                      0
16814     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0_UNUSED_0                                       (0x7f<<1) // reserved
16815     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_STATUS0_UNUSED_0_SHIFT                                 1
16816 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL1                                                      0x00ce48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16817     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1                                          (0x1f<<0) // Setting for TXEQ first post-cursor tap coefficient
16818     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL1_TXEQ_C1_SHIFT                                    0
16819     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL1_UNUSED_0                                         (0x7<<5) // reserved
16820     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL1_UNUSED_0_SHIFT                                   5
16821 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL3                                                      0x00ce50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16822     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1                                         (0xf<<0) // Setting for TXEQ pre-cursor tap coefficient
16823     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL3_TXEQ_CM1_SHIFT                                   0
16824     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL3_UNUSED_0                                         (0xf<<4) // reserved
16825     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL3_UNUSED_0_SHIFT                                   4
16826 #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL5                                                      0x00ce58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16827     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING                                        (0xf<<0) // Thermometer coded control to adjust the delay between data and clock for the final 2to1 mux. Setting 00000 min delay of clock path and 11111 max delay of clock path.
16828     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL5_DRV_SWING_SHIFT                                  0
16829     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL5_UNUSED_0                                         (0xf<<4) // reserved
16830     #define PHY_NW_IP_REG_LN3_DRV_REFCLK_TXEQ_CTRL5_UNUSED_0_SHIFT                                   4
16831 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0                                                       0x00d080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16832     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_REQ                                               (0x1<<0) // Write 1 to request a command CMD execution.  It should be held at 1 until fsm_status0.ack is 1, and then it should be set back to 0.
16833     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_REQ_SHIFT                                         0
16834     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_CMD                                               (0x1f<<1) // Requested command: 0x00 - LOAD_ONLY Others - Reserved
16835     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_CMD_SHIFT                                         1
16836     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_UNUSED_0                                          (0x1<<6) // reserved
16837     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_UNUSED_0_SHIFT                                    6
16838     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL                                 (0x1<<7) // Set it to 1 when changing DFE tap values
16839     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_CTRL0_DRIVE_BEFORE_EVAL_SHIFT                           7
16840 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0                                                     0x00d0a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16841     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_ACK                                             (0x1<<0) // Acknowledge from DFE after command execution. Will be set to 1 after a command is completed, and will clear to 0 after fsm_status0.req is cleared
16842     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_ACK_SHIFT                                       0
16843     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_UNUSED_0                                        (0x7f<<1) // reserved
16844     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_FSM_STATUS0_UNUSED_0_SHIFT                                  1
16845 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0                                                       0x00d0a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16846     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN                                     (0x1<<0) // Enables updating Tap 1 Even 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
16847     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN0_EN_SHIFT                               0
16848     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN                                     (0x1<<1) // Enables updating Tap 1 Even 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
16849     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_EVEN1_EN_SHIFT                               1
16850     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN                                      (0x1<<2) // Enables updating Tap 1 Odd 0 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
16851     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD0_EN_SHIFT                                2
16852     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN                                      (0x1<<3) // Enables updating Tap 1 Odd 1 Path when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled Note that all four tap1 enable fields tap1_*_en must be set to the same value at the same time i.e. in each write.
16853     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP1_ODD1_EN_SHIFT                                3
16854     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP2_EN                                           (0x1<<4) // Enables updating Tap 2 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16855     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP2_EN_SHIFT                                     4
16856     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP3_EN                                           (0x1<<5) // Enables updating Tap 3 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16857     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP3_EN_SHIFT                                     5
16858     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP4_EN                                           (0x1<<6) // Enables updating Tap 4 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16859     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP4_EN_SHIFT                                     6
16860     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP5_EN                                           (0x1<<7) // Enables updating Tap 5 when FSM LOAD_ONLY command executes 0 - Disabled 1 - Enabled
16861     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_CTRL0_TAP5_EN_SHIFT                                     7
16862 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0                                             0x00d0acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16863     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0                              (0x1f<<0) // Starting value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16864     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_SHIFT                        0
16865     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_UNUSED_0                                (0x3<<5) // reserved
16866     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_UNUSED_0_SHIFT                          5
16867     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY                     (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16868     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT               7
16869 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1                                             0x00d0b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16870     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1                              (0x1f<<0) // Starting value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16871     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_SHIFT                        0
16872     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_UNUSED_0                                (0x3<<5) // reserved
16873     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_UNUSED_0_SHIFT                          5
16874     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY                     (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16875     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT               7
16876 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2                                             0x00d0b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16877     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0                               (0x1f<<0) // Starting value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16878     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_SHIFT                         0
16879     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_UNUSED_0                                (0x3<<5) // reserved
16880     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_UNUSED_0_SHIFT                          5
16881     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16882     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT                7
16883 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3                                             0x00d0b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16884     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1                               (0x1f<<0) // Starting value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_start_val_ctrl* registers must be set to the same value.
16885     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_SHIFT                         0
16886     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_UNUSED_0                                (0x3<<5) // reserved
16887     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_UNUSED_0_SHIFT                          5
16888     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_start_val_ctrl* registers must be set to the same value.
16889     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT                7
16890 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4                                             0x00d0bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16891     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2                                    (0xf<<0) // Starting value for Tap 2 for Tap Adaptations
16892     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_SHIFT                              0
16893     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_UNUSED_0                                (0x7<<4) // reserved
16894     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_UNUSED_0_SHIFT                          4
16895     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
16896     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL4_TAP2_POLARITY_SHIFT                     7
16897 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5                                             0x00d0c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16898     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3                                    (0x7<<0) // Starting value for Tap 3 for Tap Adaptations
16899     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_SHIFT                              0
16900     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_UNUSED_0                                (0xf<<3) // reserved
16901     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_UNUSED_0_SHIFT                          3
16902     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
16903     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL5_TAP3_POLARITY_SHIFT                     7
16904 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6                                             0x00d0c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16905     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4                                    (0x7<<0) // Starting value for Tap 4 for Tap Adaptations
16906     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_SHIFT                              0
16907     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_UNUSED_0                                (0xf<<3) // reserved
16908     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_UNUSED_0_SHIFT                          3
16909     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
16910     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL6_TAP4_POLARITY_SHIFT                     7
16911 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7                                             0x00d0c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16912     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5                                    (0x7<<0) // Starting value for Tap 5 for Tap Adaptations
16913     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_SHIFT                              0
16914     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_UNUSED_0                                (0xf<<3) // reserved
16915     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_UNUSED_0_SHIFT                          3
16916     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY                           (0x1<<7) // polarity 0 = negative, 1 = positive
16917     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_START_VAL_CTRL7_TAP5_POLARITY_SHIFT                     7
16918 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0                                              0x00d0ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16919     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0                               (0x1f<<0) // Loading value for Tap 1 Even 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16920     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_SHIFT                         0
16921     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_UNUSED_0                                 (0x3<<5) // reserved
16922     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_UNUSED_0_SHIFT                           5
16923     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16924     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL0_TAP1_EVEN0_POLARITY_SHIFT                7
16925 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1                                              0x00d0d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16926     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1                               (0x1f<<0) // Loading value for Tap 1 Even 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16927     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_SHIFT                         0
16928     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_UNUSED_0                                 (0x3<<5) // reserved
16929     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_UNUSED_0_SHIFT                           5
16930     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY                      (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16931     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL1_TAP1_EVEN1_POLARITY_SHIFT                7
16932 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2                                              0x00d0d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16933     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0                                (0x1f<<0) // Loading value for Tap 1 Odd 0 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16934     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_SHIFT                          0
16935     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_UNUSED_0                                 (0x3<<5) // reserved
16936     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_UNUSED_0_SHIFT                           5
16937     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY                       (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16938     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL2_TAP1_ODD0_POLARITY_SHIFT                 7
16939 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3                                              0x00d0d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16940     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1                                (0x1f<<0) // Loading value for Tap 1 Odd 1 Path for Tap Adaptations. Note that all four tap1 value fields tap1_even0/1 and tap1_odd0/1 of tap_load_val_ctrl* registers must be set to the same value.
16941     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_SHIFT                          0
16942     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_UNUSED_0                                 (0x3<<5) // reserved
16943     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_UNUSED_0_SHIFT                           5
16944     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY                       (0x1<<7) // polarity 0 = negative, 1 = positive Note that all four tap1 polarity fields tap1_*_polarity of tap_load_val_ctrl* registers must be set to the same value.
16945     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL3_TAP1_ODD1_POLARITY_SHIFT                 7
16946 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4                                              0x00d0dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16947     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2                                     (0xf<<0) // Loading value for Tap 2 for Tap Adaptations
16948     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_SHIFT                               0
16949     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_UNUSED_0                                 (0x7<<4) // reserved
16950     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_UNUSED_0_SHIFT                           4
16951     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
16952     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL4_TAP2_POLARITY_SHIFT                      7
16953 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5                                              0x00d0e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16954     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3                                     (0x7<<0) // Loading value for Tap 3 for Tap Adaptations
16955     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_SHIFT                               0
16956     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_UNUSED_0                                 (0xf<<3) // reserved
16957     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_UNUSED_0_SHIFT                           3
16958     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
16959     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL5_TAP3_POLARITY_SHIFT                      7
16960 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6                                              0x00d0e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16961     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4                                     (0x7<<0) // Loading value for Tap 4 for Tap Adaptations
16962     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_SHIFT                               0
16963     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_UNUSED_0                                 (0xf<<3) // reserved
16964     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_UNUSED_0_SHIFT                           3
16965     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
16966     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL6_TAP4_POLARITY_SHIFT                      7
16967 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7                                              0x00d0e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
16968     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5                                     (0x7<<0) // Loading value for Tap 5 for Tap Adaptations
16969     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_SHIFT                               0
16970     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_UNUSED_0                                 (0xf<<3) // reserved
16971     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_UNUSED_0_SHIFT                           3
16972     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY                            (0x1<<7) // polarity 0 = negative, 1 = positive
16973     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_LOAD_VAL_CTRL7_TAP5_POLARITY_SHIFT                      7
16974 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0                                                 0x00d0ecUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16975     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0                                  (0x1f<<0) // binary value for Tap 1 Even 0 Path for Tap Adaptations
16976     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_SHIFT                            0
16977     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_UNUSED_0                                    (0x3<<5) // reserved
16978     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_UNUSED_0_SHIFT                              5
16979     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY                         (0x1<<7) // polarity 0 = negative, 1 = positive
16980     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS0_TAP1_EVEN0_POLARITY_SHIFT                   7
16981 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1                                                 0x00d0f0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16982     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1                                  (0x1f<<0) // binary  value for Tap 1 Even 1 Path for Tap Adaptations
16983     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_SHIFT                            0
16984     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_UNUSED_0                                    (0x3<<5) // reserved
16985     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_UNUSED_0_SHIFT                              5
16986     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY                         (0x1<<7) // polarity 0 = negative, 1 = positive
16987     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS1_TAP1_EVEN1_POLARITY_SHIFT                   7
16988 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2                                                 0x00d0f4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16989     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0                                   (0x1f<<0) // binary  value for Tap 1 Odd 0 Path for Tap Adaptations
16990     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_SHIFT                             0
16991     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_UNUSED_0                                    (0x3<<5) // reserved
16992     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_UNUSED_0_SHIFT                              5
16993     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY                          (0x1<<7) // polarity 0 = negative, 1 = positive
16994     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS2_TAP1_ODD0_POLARITY_SHIFT                    7
16995 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3                                                 0x00d0f8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
16996     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1                                   (0x1f<<0) // binary  value for Tap 1 Odd 1 Path for Tap Adaptations
16997     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_SHIFT                             0
16998     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_UNUSED_0                                    (0x3<<5) // reserved
16999     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_UNUSED_0_SHIFT                              5
17000     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY                          (0x1<<7) // polarity 0 = negative, 1 = positive
17001     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS3_TAP1_ODD1_POLARITY_SHIFT                    7
17002 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4                                                 0x00d0fcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17003     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2                                        (0xf<<0) // binary  value for Tap 2 for Tap Adaptations
17004     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_SHIFT                                  0
17005     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_UNUSED_0                                    (0x7<<4) // reserved
17006     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_UNUSED_0_SHIFT                              4
17007     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
17008     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS4_TAP2_POLARITY_SHIFT                         7
17009 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5                                                 0x00d100UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17010     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3                                        (0x7<<0) // binary  value for Tap 3 for Tap Adaptations
17011     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_SHIFT                                  0
17012     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_UNUSED_0                                    (0xf<<3) // reserved
17013     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_UNUSED_0_SHIFT                              3
17014     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
17015     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS5_TAP3_POLARITY_SHIFT                         7
17016 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6                                                 0x00d104UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17017     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4                                        (0x7<<0) // binary  value for Tap 4 for Tap Adaptations
17018     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_SHIFT                                  0
17019     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_UNUSED_0                                    (0xf<<3) // reserved
17020     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_UNUSED_0_SHIFT                              3
17021     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
17022     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS6_TAP4_POLARITY_SHIFT                         7
17023 #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7                                                 0x00d108UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17024     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5                                        (0x7<<0) // binary  value for Tap 5 for Tap Adaptations
17025     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_SHIFT                                  0
17026     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_UNUSED_0                                    (0xf<<3) // reserved
17027     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_UNUSED_0_SHIFT                              3
17028     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY                               (0x1<<7) // polarity 0 = negative, 1 = positive
17029     #define PHY_NW_IP_REG_LN3_DFE_REFCLK_TAP_VAL_STATUS7_TAP5_POLARITY_SHIFT                         7
17030 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL                                                    0x00d400UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17031     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL                                (0x1<<0) // Enables analog LOS offset calibration circuits.
17032     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL_RXLOS_OFFSETCAL_SHIFT                          0
17033     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL_UNUSED_0                                       (0x7f<<1) // reserved
17034     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_AFE_CAL_CTRL_UNUSED_0_SHIFT                                 1
17035 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0                                                0x00d40cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17036     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0_EN                                         (0x1<<0) // Enables the run-length detection digital LOS filter.
17037     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0_EN_SHIFT                                   0
17038     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0_UNUSED_0                                   (0x7f<<1) // reserved
17039     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL0_UNUSED_0_SHIFT                             1
17040 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_CTRL1                                                0x00d410UL //Access:RW   DataWidth:0x8   Value of run-length which will trigger an LOS condition.  Chips: K2
17041 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0                                              0x00d414UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17042     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED                                   (0x1<<0) // Indicates that the run-length filter is currently exceeding the specified run-length threshold.
17043     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_SHIFT                             0
17044     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY                            (0x1<<1) // Indicates that the run-length filter has, at some time, exceeded the specified run-length threshold.
17045     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_EXCEED_STICKY_SHIFT                      1
17046     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_UNUSED_0                                 (0x3f<<2) // reserved
17047     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_RUN_LENGTH_STATUS0_UNUSED_0_SHIFT                           2
17048 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL0                                                    0x00d440UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x00.  Chips: K2
17049 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL1                                                    0x00d444UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x0000.  Chips: K2
17050 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL2                                                    0x00d448UL //Access:RW   DataWidth:0x8   Digital Rx LOS glitch filter assertion threshold.  Determines the number of consecutive clk_i clock cycles that the raw analog  LOS must remain a logic ?1? before the output of the filter will assert.  Can be disabled by writing a value of 0x000000.  Chips: K2
17051 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL3                                                    0x00d44cUL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
17052 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL4                                                    0x00d450UL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
17053 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL5                                                    0x00d454UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17054     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24                       (0x3<<0) // Same as above.
17055     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL5_DEASSERT_THRESHOLD_25_24_SHIFT                 0
17056     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL5_UNUSED_0                                       (0x3f<<2) // reserved
17057     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL5_UNUSED_0_SHIFT                                 2
17058 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6                                                    0x00d458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17059     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6_EN                                             (0x1<<0) // Enables the digital deglitching filter.
17060     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6_EN_SHIFT                                       0
17061     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6_UNUSED_0                                       (0x7f<<1) // reserved
17062     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_FILTER_CTRL6_UNUSED_0_SHIFT                                 1
17063 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0                                                  0x00d4c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17064     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN                                     (0x1<<0) // Override enable for the LOS output of the digital filtering logic.
17065     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_EN_SHIFT                               0
17066     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_0                                     (0x7<<1) // reserved
17067     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_0_SHIFT                               1
17068     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE                                  (0x1<<4) // Override value for the LOS output of the digital filtering logic.
17069     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_LOS_O_VALUE_SHIFT                            4
17070     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_1                                     (0x7<<5) // reserved
17071     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_OVERRIDE_CTRL0_UNUSED_1_SHIFT                               5
17072 #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0                                                         0x00d5c4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17073     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_READY                                           (0x1<<0) // Indicates that digital and analog Rx LOS blocks are in LOS mode.
17074     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_READY_SHIFT                                     0
17075     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_UNUSED_0                                            (0x1<<1) // reserved
17076     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_UNUSED_0_SHIFT                                      1
17077     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS                                                 (0x1<<2) // The filtered LOS signal value.
17078     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_SHIFT                                           2
17079     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_RAW                                             (0x1<<3) // The unfiltered LOS signal value.
17080     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_RAW_SHIFT                                       3
17081     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_NO_EII                                          (0x1<<4) // The filtered LOS signal value before EII override logic.
17082     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_LOS_NO_EII_SHIFT                                    4
17083     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_UNUSED_1                                            (0x7<<5) // reserved
17084     #define PHY_NW_IP_REG_LN3_LOS_REFCLK_STATUS0_UNUSED_1_SHIFT                                      5
17085 #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL                                                               0x00d800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17086     #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_EN                                                        (0x1<<0) // Enables BIST Tx data generation.
17087     #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_EN_SHIFT                                                  0
17088     #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_PATTERN_SEL                                               (0xf<<1) // Selects the pattern to transmitted: 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP 0x9 ? MAC Tx data
17089     #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_PATTERN_SEL_SHIFT                                         1
17090     #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_UNUSED_0                                                  (0x7<<5) // reserved
17091     #define PHY_NW_IP_REG_LN3_BIST_TX_CTRL_UNUSED_0_SHIFT                                            5
17092 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0                                                          0x00d818UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17093     #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0_MODE                                                 (0x3<<0) // Controls what type of error injection is used: 0x0 ? None 0x1 ? Single cycle error 0x2 ? Timer based
17094     #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0_MODE_SHIFT                                           0
17095     #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0_UNUSED_0                                             (0x3f<<2) // reserved
17096     #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL0_UNUSED_0_SHIFT                                       2
17097 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL1                                                          0x00d81cUL //Access:RW   DataWidth:0x8   Number of cycles between single bit-error injection  Chips: K2
17098 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL2                                                          0x00d820UL //Access:RW   DataWidth:0x8   Number of cycles between single bit-error injection  Chips: K2
17099 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL3                                                          0x00d824UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
17100 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL4                                                          0x00d828UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
17101 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL5                                                          0x00d82cUL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
17102 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL6                                                          0x00d830UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
17103 #define PHY_NW_IP_REG_LN3_BIST_TX_BER_CTRL7                                                          0x00d834UL //Access:RW   DataWidth:0x8   Sets the Tx data bits to be flipped.  Chips: K2
17104 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_SHIFT_AMOUNT                                                   0x00d880UL //Access:RW   DataWidth:0x8   Determines the length of the UDP.  Must be set to d160 modulus udp_length.  Chips: K2
17105 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_7_0                                                            0x00d890UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17106 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_15_8                                                           0x00d894UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17107 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_23_16                                                          0x00d898UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17108 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_31_24                                                          0x00d89cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17109 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_39_32                                                          0x00d8a0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17110 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_47_40                                                          0x00d8a4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17111 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_55_48                                                          0x00d8a8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17112 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_63_56                                                          0x00d8acUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17113 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_71_64                                                          0x00d8b0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17114 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_79_72                                                          0x00d8b4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17115 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_87_80                                                          0x00d8b8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17116 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_95_88                                                          0x00d8bcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17117 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_103_96                                                         0x00d8c0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17118 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_111_104                                                        0x00d8c4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17119 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_119_112                                                        0x00d8c8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17120 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_127_120                                                        0x00d8ccUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17121 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_135_128                                                        0x00d8d0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17122 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_143_136                                                        0x00d8d4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17123 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_151_144                                                        0x00d8d8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17124 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_159_152                                                        0x00d8dcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17125 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_167_160                                                        0x00d8e0UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17126 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_175_168                                                        0x00d8e4UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17127 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_183_176                                                        0x00d8e8UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17128 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_191_184                                                        0x00d8ecUL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17129 #define PHY_NW_IP_REG_LN3_BIST_TX_UDP_199_192                                                        0x00d8f0UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17130 #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL                                                               0x00da00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17131     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_EN                                                        (0x1<<0) // Enables BIST Rx data checking.
17132     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_EN_SHIFT                                                  0
17133     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_PATTERN_SEL                                               (0xf<<1) // Selects the pattern to search for: 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP 0x8 ? Auto-detect
17134     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_PATTERN_SEL_SHIFT                                         1
17135     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_CLEAR_BER                                                 (0x1<<5) // Clears the bit error counter.
17136     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_CLEAR_BER_SHIFT                                           5
17137     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_STOP_ERROR_COUNT                                          (0x1<<6) // Stops the error count from incrementing.  Can be used to read back the BER data coherently.
17138     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_STOP_ERROR_COUNT_SHIFT                                    6
17139     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA                                    (0x1<<7) // Forces the PRBS LFSR to reseed with Rx data every cycle.  This will cause the bit error counter to be inaccurate.
17140     #define PHY_NW_IP_REG_LN3_BIST_RX_CTRL_FORCE_LFSR_WITH_RXDATA_SHIFT                              7
17141 #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS                                                             0x00da10UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17142     #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_STATE                                                   (0x7<<0) // State of the BIST checker: 0x0 ? Off 0x1 ? Searching for pattern 0x2 ? Waiting for pattern lock conditions 0x3 ? Pattern lock acquired 0x4 ? Pattern lock lost
17143     #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_STATE_SHIFT                                             0
17144     #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_PATTERN_DET                                             (0xf<<3) // Indicates the pattern  detected: 0x0 ? No pattern detected 0x1 ? PRBS 0xC1 0x2 ? PRBS 0x221 0x3 ? PRBS 0xA01 0x4 ? PRBS 0xC001 0x5 ? PRBS 0x840001 0x6 ? PRBS 0x90000001 0x7 ? User defined pattern UDP
17145     #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_PATTERN_DET_SHIFT                                       3
17146     #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_UNUSED_0                                                (0x1<<7) // reserved
17147     #define PHY_NW_IP_REG_LN3_BIST_RX_STATUS_UNUSED_0_SHIFT                                          7
17148 #define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS0                                                        0x00da20UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
17149 #define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS1                                                        0x00da24UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
17150 #define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS2                                                        0x00da28UL //Access:R    DataWidth:0x8   Number of bit errors.  Chips: K2
17151 #define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS4                                                        0x00da30UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
17152 #define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS5                                                        0x00da34UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
17153 #define PHY_NW_IP_REG_LN3_BIST_RX_BER_STATUS6                                                        0x00da38UL //Access:R    DataWidth:0x8   Number of cycles that errors have been counted.  Chips: K2
17154 #define PHY_NW_IP_REG_LN3_BIST_RX_LOCK_CTRL0                                                         0x00da50UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern lock.  Chips: K2
17155 #define PHY_NW_IP_REG_LN3_BIST_RX_LOCK_CTRL1                                                         0x00da54UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern lock.  Chips: K2
17156 #define PHY_NW_IP_REG_LN3_BIST_RX_LOCK_CTRL2                                                         0x00da58UL //Access:RW   DataWidth:0x8   Maximum number of errors allowed to trigger pattern lock.  Chips: K2
17157 #define PHY_NW_IP_REG_LN3_BIST_RX_LOCK_CTRL3                                                         0x00da5cUL //Access:RW   DataWidth:0x8   Maximum number of errors allowed to trigger pattern lock.  Chips: K2
17158 #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL0                                                    0x00da80UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern loss-of-lock.  Chips: K2
17159 #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL1                                                    0x00da84UL //Access:RW   DataWidth:0x8   Size of error sampling window to trigger pattern loss-of-lock.  Chips: K2
17160 #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL2                                                    0x00da88UL //Access:RW   DataWidth:0x8   Minimum number of errors allowed to trigger pattern loss-of-lock.  Chips: K2
17161 #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL3                                                    0x00da8cUL //Access:RW   DataWidth:0x8   Minimum number of errors allowed to trigger pattern loss-of-lock.  Chips: K2
17162 #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4                                                    0x00da90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17163     #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK                              (0x1<<0) // Stops pattern from being re-locked when loss-of-lock occurs.
17164     #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4_STOP_ON_LOSS_LOCK_SHIFT                        0
17165     #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4_UNUSED_0                                       (0x7f<<1) // reserved
17166     #define PHY_NW_IP_REG_LN3_BIST_RX_LOSS_LOCK_CTRL4_UNUSED_0_SHIFT                                 1
17167 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_SHIFT_AMOUNT                                                   0x00dac0UL //Access:RW   DataWidth:0x8   Determines the length of the UDP.  Must be set to d160 modulus udp_length.  Chips: K2
17168 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_7_0                                                            0x00dad0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17169 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_15_8                                                           0x00dad4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17170 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_23_16                                                          0x00dad8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17171 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_31_24                                                          0x00dadcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17172 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_39_32                                                          0x00dae0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17173 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_47_40                                                          0x00dae4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17174 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_55_48                                                          0x00dae8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17175 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_63_56                                                          0x00daecUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17176 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_71_64                                                          0x00daf0UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17177 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_79_72                                                          0x00daf4UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17178 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_87_80                                                          0x00daf8UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17179 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_95_88                                                          0x00dafcUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17180 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_103_96                                                         0x00db00UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17181 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_111_104                                                        0x00db04UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17182 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_119_112                                                        0x00db08UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17183 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_127_120                                                        0x00db0cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17184 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_135_128                                                        0x00db10UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17185 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_143_136                                                        0x00db14UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17186 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_151_144                                                        0x00db18UL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17187 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_159_152                                                        0x00db1cUL //Access:RW   DataWidth:0x8   User defined pattern.  Chips: K2
17188 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_167_160                                                        0x00db20UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17189 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_175_168                                                        0x00db24UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17190 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_183_176                                                        0x00db28UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17191 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_191_184                                                        0x00db2cUL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17192 #define PHY_NW_IP_REG_LN3_BIST_RX_UDP_199_192                                                        0x00db30UL //Access:RW   DataWidth:0x8   User defined pattern extension bits.  Chips: K2
17193 #define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0                                                        0x00dc00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17194     #define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0_AC_COUPLED                                         (0x1<<0) // Configures AC/DC coupling of the lane 0: DC coupled 1: AC coupled
17195     #define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0_AC_COUPLED_SHIFT                                   0
17196     #define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0_UNUSED_0                                           (0x7f<<1) // reserved
17197     #define PHY_NW_IP_REG_LN3_FEATURE_RXTERM_CFG0_UNUSED_0_SHIFT                                     1
17198 #define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0                                                      0x00dc04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17199     #define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0_EN                                               (0x1<<0) // Enables turning on the divided rxclk output
17200     #define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0_EN_SHIFT                                         0
17201     #define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0_UNUSED_0                                         (0x7f<<1) // reserved
17202     #define PHY_NW_IP_REG_LN3_FEATURE_RXCLKDIV_CFG0_UNUSED_0_SHIFT                                   1
17203 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG                                                     0x00dc84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17204     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0                              (0x3<<0) // How many times to repeat CTLE adaptation sequence for initial adaptation set 0
17205     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT0_SHIFT                        0
17206     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1                              (0x3<<2) // How many times to repeat CTLE adaptation sequence for initial adaptation set 1
17207     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_REPEAT_COUNT_INIT1_SHIFT                        2
17208     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_UNUSED_0                                        (0xf<<4) // reserved
17209     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_CFG_UNUSED_0_SHIFT                                  4
17210 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG                                                 0x00dc88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17211     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN                                    (0x1<<0) // Enables AGC threshold adaptation for initial adaptation
17212     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_INIT0_EN_SHIFT                              0
17213     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_UNUSED_0                                    (0x7f<<1) // reserved
17214     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_AGC_CFG_UNUSED_0_SHIFT                              1
17215 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG                                             0x00dc8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17216     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN                                (0x1<<0) // Enables mapping GN_APG setting from AGC threshold for initial adaptation
17217     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_INIT0_EN_SHIFT                          0
17218     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_UNUSED_0                                (0x7f<<1) // reserved
17219     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_APG_MAP_CFG_UNUSED_0_SHIFT                          1
17220 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG                                                 0x00dc90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17221     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL                                   (0x3<<0) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 0 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
17222     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT0_SEL_SHIFT                             0
17223     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL                                   (0x3<<2) // Selects the CTLE EQ LFG adaptation method for initial adaptation set 1 0x0: Disables CTLE EQ LFG Adaptation 0x1: Method 1: GN_APG mapped from LUT, EQ_LFG stand-alone closed-loop 0x2: Method 2: GN_APG stand-alone closed-loop, EQ_LFG stand-alone closed-loop 0x3: Method 3: GN_APG and EQ_LFG combined closed-loop
17224     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_INIT1_SEL_SHIFT                             2
17225     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_UNUSED_0                                    (0xf<<4) // reserved
17226     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_LFG_CFG_UNUSED_0_SHIFT                              4
17227 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0                                                0x00dc94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17228     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN                              (0x1<<0) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 0
17229     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_EDGE_EN_SHIFT                        0
17230     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN                              (0x1<<1) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 0
17231     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT0_DATA_EN_SHIFT                        1
17232     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN                              (0x1<<2) // Enables CTLE EQ HFG edge based adaptation at initial adapation set 1
17233     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_EDGE_EN_SHIFT                        2
17234     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN                              (0x1<<3) // Enables CTLE EQ HFG Data based adaptation for the initial adaptation set 1
17235     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_INIT1_DATA_EN_SHIFT                        3
17236     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_UNUSED_0                                   (0xf<<4) // reserved
17237     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG0_UNUSED_0_SHIFT                             4
17238 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1                                                0x00dc98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17239     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL                           (0x3<<0) // Selects which HFG result to use for the initial adaptation set 0 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
17240     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT0_RESULT_SEL_SHIFT                     0
17241     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL                           (0x3<<2) // Selects which HFG result to use for the initial adaptation set 1 0x0: Edge Based 0x1: Data Based 0x2: Average of Edge & Data result 0x3: Reserved
17242     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_INIT1_RESULT_SEL_SHIFT                     2
17243     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_UNUSED_0                                   (0xf<<4) // reserved
17244     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_HFG_CFG1_UNUSED_0_SHIFT                             4
17245 #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG                                                 0x00dca0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17246     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN                                    (0x1<<0) // Enables CTLE midband shaping adaptation for initial adaptation set 0
17247     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT0_EN_SHIFT                              0
17248     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN                                    (0x1<<1) // Enables CTLE midband shaping adaptation for initial adaptation set 1
17249     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_INIT1_EN_SHIFT                              1
17250     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_UNUSED_0                                    (0x3f<<2) // reserved
17251     #define PHY_NW_IP_REG_LN3_FEATURE_CTLE_ADAPT_MBS_CFG_UNUSED_0_SHIFT                              2
17252 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG                                                            0x00dcc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17253     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP1_EN                                                (0x1<<0) // Enables DFE Tap 1. Tap1 will not be powered up if it is not enabled
17254     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP1_EN_SHIFT                                          0
17255     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP2_EN                                                (0x1<<1) // Enables DFE Tap 2. Tap2 will not be powered up if it is not enabled
17256     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP2_EN_SHIFT                                          1
17257     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP3_EN                                                (0x1<<2) // Enables DFE Tap 3. Tap3 will not be powered up if it is not enabled
17258     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP3_EN_SHIFT                                          2
17259     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP4_EN                                                (0x1<<3) // Enables DFE Tap 4. Tap4 will not be powered up if it is not enabled
17260     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP4_EN_SHIFT                                          3
17261     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP5_EN                                                (0x1<<4) // Enables DFE Tap 5. Tap5 will not be powered up if it is not enabled
17262     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_TAP5_EN_SHIFT                                          4
17263     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_UNUSED_0                                               (0x7<<5) // reserved
17264     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_CFG_UNUSED_0_SHIFT                                         5
17265 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG                                                      0x00dcc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17266     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG_METHOD_SEL                                       (0x1<<0) // Which DFE Adaptation Algorithm to use: 0x0: SS-LMS 0x1: Pattern Based Zero Forcing
17267     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG_METHOD_SEL_SHIFT                                 0
17268     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG_UNUSED_0                                         (0x7f<<1) // reserved
17269     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_CFG_UNUSED_0_SHIFT                                   1
17270 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG                                                 0x00dcc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17271     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 1
17272     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_TAP1_INIT_EN_SHIFT                          0
17273     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_UNUSED_0                                    (0x7f<<1) // reserved
17274     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP1_CFG_UNUSED_0_SHIFT                              1
17275 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG                                                 0x00dcccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17276     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 2
17277     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_TAP2_INIT_EN_SHIFT                          0
17278     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_UNUSED_0                                    (0x7f<<1) // reserved
17279     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP2_CFG_UNUSED_0_SHIFT                              1
17280 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG                                                 0x00dcd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17281     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 3
17282     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_TAP3_INIT_EN_SHIFT                          0
17283     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_UNUSED_0                                    (0x7f<<1) // reserved
17284     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP3_CFG_UNUSED_0_SHIFT                              1
17285 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG                                                 0x00dcd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17286     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 4
17287     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_TAP4_INIT_EN_SHIFT                          0
17288     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_UNUSED_0                                    (0x7f<<1) // reserved
17289     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP4_CFG_UNUSED_0_SHIFT                              1
17290 #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG                                                 0x00dcd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17291     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN                                (0x1<<0) // Enables initial adaptations for Tap 5
17292     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_TAP5_INIT_EN_SHIFT                          0
17293     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_UNUSED_0                                    (0x7f<<1) // reserved
17294     #define PHY_NW_IP_REG_LN3_FEATURE_DFE_ADAPT_TAP5_CFG_UNUSED_0_SHIFT                              1
17295 #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0                                                    0x00dce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17296     #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_EN                                             (0x1<<0) // Enables continuous background adaptation
17297     #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_EN_SHIFT                                       0
17298     #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_UNUSED_0                                       (0x7f<<1) // reserved
17299     #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG0_UNUSED_0_SHIFT                                 1
17300 #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG1                                                    0x00dce4UL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
17301 #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG2                                                    0x00dce8UL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
17302 #define PHY_NW_IP_REG_LN3_FEATURE_ADAPT_CONT_CFG3                                                    0x00dcecUL //Access:RW   DataWidth:0x8   How often in ms to run continuous adaptations 1ms to ~279 mins  Chips: K2
17303 #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0                                                          0x00dd40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17304     #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_UNUSED_0                                             (0x1<<0) // reserved
17305     #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_UNUSED_0_SHIFT                                       0
17306     #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RX_CTRL_DIS                                          (0x1<<1) // Disables the firmware rx_ctrl MSM
17307     #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_RX_CTRL_DIS_SHIFT                                    1
17308     #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_UNUSED_1                                             (0x3f<<2) // reserved
17309     #define PHY_NW_IP_REG_LN3_FEATURE_TEST_CFG0_UNUSED_1_SHIFT                                       2
17310 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0                                                            0x00de00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17311     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING                                    (0x1<<0) // Starts link training procedure when asserted.  This is an 802.3 defined variable.
17312     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_RESTART_TRAINING_SHIFT                              0
17313     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE                                     (0x1<<1) // Indicates to LTSM that link training procedure should be run; otherwise procedures skip directly to signal_det assertion.  This is an 802.3 defined variable.
17314     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_MR_TRAINING_ENABLE_SHIFT                               1
17315     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_SIGNAL_DETECT                                          (0x1<<2) // Output corresponding to link training signal detect variable.  Should be set when link training has completed successfully.
17316     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_SIGNAL_DETECT_SHIFT                                    2
17317     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_CLEAR                                                  (0x1<<3) // Synchronous reset for LT Tx block.
17318     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_CLEAR_SHIFT                                            3
17319     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_UNUSED_0                                               (0xf<<4) // reserved
17320     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL0_UNUSED_0_SHIFT                                         4
17321 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL1                                                            0x00de04UL //Access:RW   DataWidth:0x8   Maximum time allowed for LT procedure.  If this is exceeded then the training_fail status will assert.  This is an 802.defined variable.  Value is encoded as: 39338 * DESIRED_DELAY * 2 ^logdata_width / data_width  Should be set to 500ns for 802.3 compliant timeout.  Chips: K2
17322 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL2                                                            0x00de08UL //Access:RW   DataWidth:0x8   Same as above.  Chips: K2
17323 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL3                                                            0x00de0cUL //Access:RW   DataWidth:0x8   Number of additional frames to send after both receivers have been trained and are ready.  This is an 802.3 defined variable.  Should be set between 100 and 300 for 802.3 compliance.  Chips: K2
17324 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4                                                            0x00de10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17325     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4_WAIT_TIME_8                                            (0x1<<0) // Same as above.
17326     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4_WAIT_TIME_8_SHIFT                                      0
17327     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4_UNUSED_0                                               (0x7f<<1) // reserved
17328     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL4_UNUSED_0_SHIFT                                         1
17329 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5                                                            0x00de14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17330     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_FRAME_LOCK                                             (0x1<<0) // Input to LTSM that receiver has acquired frame lock.  This value should be taken from the corresponding LT Rx register.  This  an 802.3 defined variable.
17331     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_FRAME_LOCK_SHIFT                                       0
17332     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_RX_TRAINED                                             (0x1<<1) // Input to LTSM indicating that the local receiver has completed training.  This is an 802.3 defined variable.
17333     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_RX_TRAINED_SHIFT                                       1
17334     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_REMOTE_RX_READY                                        (0x1<<2) // Input to LTSM indicating that the remote receiver is trained and ready.  This value should be taken from the corresponding LT Rx registers.  This is an 802.3 defined variable.
17335     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_REMOTE_RX_READY_SHIFT                                  2
17336     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_UNUSED_0                                               (0x1f<<3) // reserved
17337     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_CTRL5_UNUSED_0_SHIFT                                         3
17338 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS                                                           0x00de40UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17339     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_FAIL                                         (0x1<<0) // Output from LTSM indicating that link training has failed.  This is an 802.3 defined variable.
17340     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_FAIL_SHIFT                                   0
17341     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING                                              (0x1<<1) // Output from LTSM indicating that link training is in progress.  This is an 802.3 defined variable.
17342     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_TRAINING_SHIFT                                        1
17343     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_SIGNAL_DETECT                                         (0x1<<2) // Output from LTSM indicating that link training is complete and successful.  This is an 802.3 defined variable.  This value is only visible internally, and is not the signal_det value driven to PHY top-level.
17344     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_SIGNAL_DETECT_SHIFT                                   2
17345     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_UNUSED_0                                              (0x1<<3) // reserved
17346     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_UNUSED_0_SHIFT                                        3
17347     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY                                    (0x1<<4) // Output from LSM corresponding to 802.3 defined local_rx_ready variable. After this is asserted the corresponding frame status report field should be set.
17348     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_FSM_LOCAL_RX_READY_SHIFT                              4
17349     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_UNUSED_1                                              (0x7<<5) // reserved
17350     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATUS_UNUSED_1_SHIFT                                        5
17351 #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL0                                                           0x00de4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17352     #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL0_POLYNOMIAL                                            (0x7<<0) // Selects between CL72 and CL93 PRBS pattern. 0 ? CL72 1 + x^9 +x^11 1 ? CL93 1 + x^5 + x^6 + x^10 + x^11 2 ? CL93 1 + x^5 + x^6 + x^9 + x^11 3 ? CL93 1 + x^4 + x^6 + x^8 + x^11 4 ? CL93 1 + x^4 + x^6 + x^7 + x^11
17353     #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL0_POLYNOMIAL_SHIFT                                      0
17354     #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL0_UNUSED_0                                              (0x1f<<3) // reserved
17355     #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL0_UNUSED_0_SHIFT                                        3
17356 #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL1                                                           0x00de50UL //Access:RW   DataWidth:0x8   Initial PRBS LFSR seed.  This needs to be set according to the requirements in 802.3 CL72 or CL93 depending on the type of link training and lane bonding being performed.  Chips: K2
17357 #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL2                                                           0x00de54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17358     #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL2_SEED_10_8                                             (0x7<<0) // Same as above.
17359     #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL2_SEED_10_8_SHIFT                                       0
17360     #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL2_UNUSED_0                                              (0x1f<<3) // reserved
17361     #define PHY_NW_IP_REG_LN3_LT_TX_PRBS_CTRL2_UNUSED_0_SHIFT                                        3
17362 #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL                                              0x00de80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17363     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1                                     (0x3<<0) // Coefficient update request field for post-cursor tap. 2'b00 ? hold 2'b01 ? increment 2'b10 ? decrement 2'b11 ? reserved
17364     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_P1_SHIFT                               0
17365     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0                                      (0x3<<2) // Coefficient update request field for cursor tap.
17366     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_0_SHIFT                                2
17367     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1                                     (0x3<<4) // Coefficient update request field for pre-cursor tap.
17368     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_C_M1_SHIFT                               4
17369     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE                               (0x1<<6) // Coefficient update initialize field.
17370     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_INITIALIZE_SHIFT                         6
17371     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET                                   (0x1<<7) // Coefficient update preset field.
17372     #define PHY_NW_IP_REG_LN3_LT_TX_COEFFICIENT_UPDATE_CTRL_PRESET_SHIFT                             7
17373 #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL                                                   0x00de88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17374     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_P1                                          (0x3<<0) // Status report field for post-cursor tap. 2'b00 ? not updated 2'b01 ? minimum 2'b10 ? updated 2'b11 ? maximum
17375     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_P1_SHIFT                                    0
17376     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_0                                           (0x3<<2) // Status report field for cursor tap.
17377     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_0_SHIFT                                     2
17378     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_M1                                          (0x3<<4) // Status report field for pre-cursor tap.
17379     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_C_M1_SHIFT                                    4
17380     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY                                (0x1<<6) // Status report field to indicate local receiver is ready.  Should be set based on LTSM output of corresponding variable.
17381     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_LOCAL_RX_READY_SHIFT                          6
17382     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_UNUSED_0                                      (0x1<<7) // reserved
17383     #define PHY_NW_IP_REG_LN3_LT_TX_STATUS_REPORT_CTRL_UNUSED_0_SHIFT                                7
17384 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0                                                    0x00dec0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17385     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_CURRENT                                        (0x7<<0) // Current state of LTSM. 0x0 ? INITIALIZE 0x1 ? SEND_TRAINING 0x2 ? TRAIN_REMOTE 0x3 ? TRAIN_LOCAL 0x4 ? S7 0x5 ? TRAINING_FAILURE 0x6 ? LINK_READY 0x7 ? SEND_DATA
17386     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_CURRENT_SHIFT                                  0
17387     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_UNUSED_0                                       (0x1<<3) // reserved
17388     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_UNUSED_0_SHIFT                                 3
17389     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_PREV1                                          (0x7<<4) // One state previous.
17390     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_PREV1_SHIFT                                    4
17391     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_UNUSED_1                                       (0x1<<7) // reserved
17392     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS0_UNUSED_1_SHIFT                                 7
17393 #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1                                                    0x00dec4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17394     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_PREV2                                          (0x7<<0) // Two states previous.
17395     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_PREV2_SHIFT                                    0
17396     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_UNUSED_0                                       (0x1<<3) // reserved
17397     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_UNUSED_0_SHIFT                                 3
17398     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_PREV3                                          (0x7<<4) // Three states previous.
17399     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_PREV3_SHIFT                                    4
17400     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_UNUSED_1                                       (0x1<<7) // reserved
17401     #define PHY_NW_IP_REG_LN3_LT_TX_FSM_STATE_STATUS1_UNUSED_1_SHIFT                                 7
17402 #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0                                                                0x00df00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17403     #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_CLEAR                                                      (0x1<<0) // Synchronous reset for LT Rx block.
17404     #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_CLEAR_SHIFT                                                0
17405     #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_TRAINING                                                   (0x1<<1) // This is the 802.3 defined training variable.  It should be set according to corresponding LTSM output.
17406     #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_TRAINING_SHIFT                                             1
17407     #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_UNUSED_0                                                   (0x3f<<2) // reserved
17408     #define PHY_NW_IP_REG_LN3_LT_RX_CTRL0_UNUSED_0_SHIFT                                             2
17409 #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL0                                                           0x00df08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17410     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL0_POLYNOMIAL                                            (0x7<<0) // Selects between CL72 and CL93 PRBS patterns. 0 ? CL72 1 + x^9 + x^11 1 ? CL93 1 + x^5 + x^6 + x^10 + x^11 2 ? CL93 1 + x^5 + x^6 + x^9 + x^11 3 ? CL93 1 + x^4 + x^6 + x^8 + x^11 4 ? CL93 1 + x^4 + x^6 + x^7 + x^11
17411     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL0_POLYNOMIAL_SHIFT                                      0
17412     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL0_UNUSED_0                                              (0x1f<<3) // reserved
17413     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL0_UNUSED_0_SHIFT                                        3
17414 #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_CTRL1                                                           0x00df0cUL //Access:RW   DataWidth:0x8   Maximum number  of PRBS bit errors allowed in single LT frame for PRBS lock to be achieved.  Chips: K2
17415 #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0                                                         0x00df14UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17416     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_UPDATE                                              (0x1<<0) // Assertion indicates that PRBS status information has been updated.
17417     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_UPDATE_SHIFT                                        0
17418     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_LOCK                                                (0x1<<1) // Indicates that a valid PRBS pattern has been detected in receiver LT frame.
17419     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_LOCK_SHIFT                                          1
17420     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_UNUSED_0                                            (0x3f<<2) // reserved
17421     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS0_UNUSED_0_SHIFT                                      2
17422 #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS1                                                         0x00df18UL //Access:R    DataWidth:0x8   Number of bit errors in PRBS pattern since last lock assertion event.  Chips: K2
17423 #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS2                                                         0x00df1cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17424     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8                                    (0xf<<0) // Same as above.
17425     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS2_ERROR_COUNT_11_8_SHIFT                              0
17426     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS2_UNUSED_0                                            (0xf<<4) // reserved
17427     #define PHY_NW_IP_REG_LN3_LT_RX_PRBS_STATUS2_UNUSED_0_SHIFT                                      4
17428 #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL                                                           0x00df40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17429     #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL_CLEAR_COUNT                                           (0x1<<0) // Clears both the absolute and erroneous frame counters.
17430     #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL_CLEAR_COUNT_SHIFT                                     0
17431     #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL_UNUSED_0                                              (0x7f<<1) // reserved
17432     #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_CTRL_UNUSED_0_SHIFT                                        1
17433 #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0                                                        0x00df4cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17434     #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0_FRAME_LOCK                                         (0x1<<0) // Indicates that the receiver has locked to incoming LT frames.
17435     #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0_FRAME_LOCK_SHIFT                                   0
17436     #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0_UNUSED_0                                           (0x7f<<1) // reserved
17437     #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS0_UNUSED_0_SHIFT                                     1
17438 #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS1                                                        0x00df50UL //Access:R    DataWidth:0x8   Total number of received frames since frame lock.  Chips: K2
17439 #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS2                                                        0x00df54UL //Access:R    DataWidth:0x8   Same as above.  Chips: K2
17440 #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS3                                                        0x00df58UL //Access:R    DataWidth:0x8   Total number of received frames  with a PRBS, DME, or framing error since frame lock.  Chips: K2
17441 #define PHY_NW_IP_REG_LN3_LT_RX_FRAME_STATUS4                                                        0x00df5cUL //Access:R    DataWidth:0x8   Same as above.  Chips: K2
17442 #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS                                            0x00df80UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17443     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1                                   (0x3<<0) // Received coefficient update field for post-cursor tap. 2'b00 ? hold 2'b01 ? increment 2'b10 ? decrement 2'b11 ? reserved
17444     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_P1_SHIFT                             0
17445     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0                                    (0x3<<2) // Received coefficient update request field for cursor tap.
17446     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_0_SHIFT                              2
17447     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1                                   (0x3<<4) // Received coefficient update request field for pre-cursor tap.
17448     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_C_M1_SHIFT                             4
17449     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE                             (0x1<<6) // Received coefficient update initialize field.
17450     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_INITIALIZE_SHIFT                       6
17451     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET                                 (0x1<<7) // Received coefficient update preset field.
17452     #define PHY_NW_IP_REG_LN3_LT_RX_COEFFICIENT_UPDATE_STATUS_PRESET_SHIFT                           7
17453 #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS                                                        0x00df88UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17454     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_P1                                               (0x3<<0) // Received status report field for post-cursor tap. 2'b00 ? not updated 2'b01 ? minimum 2'b10 ? updated 2'b11 ? maximum
17455     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_P1_SHIFT                                         0
17456     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_0                                                (0x3<<2) // Received status report field for cursor tap.
17457     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_0_SHIFT                                          2
17458     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_M1                                               (0x3<<4) // Received status report field for pre-cursor tap.
17459     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_C_M1_SHIFT                                         4
17460     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_LOCAL_RX_READY                                     (0x1<<6) // Received status report field to indicate local receiver is ready.
17461     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_LOCAL_RX_READY_SHIFT                               6
17462     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_DME_ERROR                                          (0x1<<7) // Indicates differential manchester decoding error.  Not sticky.
17463     #define PHY_NW_IP_REG_LN3_LT_RX_REPORT_STATUS_DME_ERROR_SHIFT                                    7
17464 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0                                                            0x000000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17465     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_SOC0_DIV_O                                             (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an override
17466     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_SOC0_DIV_O_SHIFT                                       0
17467     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_SOC1_DIV_O                                             (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an override
17468     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X0_SOC1_DIV_O_SHIFT                                       4
17469 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1                                                            0x000004UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17470     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_CK_SOC_DIV_OVR_O_2_0                                   (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for pins ck_soc_div_i [1:0]
17471     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_CK_SOC_DIV_OVR_O_2_0_SHIFT                             0
17472     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O                                   (0x3<<3) // Divider for pma_cm_ref_clk
17473     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O_SHIFT                             3
17474     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_GCFSM_CLK_DIV_O                                        (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
17475     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_GCFSM_CLK_DIV_O_SHIFT                                  5
17476     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O                              (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
17477     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O_SHIFT                        7
17478 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2                                                            0x000008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17479     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_SSC_CLK_DIV_O                                          (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /4 4?d3:  /8:
17480     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_SSC_CLK_DIV_O_SHIFT                                    0
17481     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0                                   (0x7<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
17482     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0_SHIFT                             3
17483     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFDIV_O_1_0                                       (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by 4
17484     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFDIV_O_1_0_SHIFT                                 6
17485 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X3                                                            0x00000cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17486     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X3_AHB_PMA_CM_DIVNSEL_O_6_0                               (0x7f<<0) // CMU N-divider setting
17487     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X3_AHB_PMA_CM_DIVNSEL_O_6_0_SHIFT                         0
17488     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X3_UNUSED_0                                               (0x1<<7) // reserved
17489     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X3_UNUSED_0_SHIFT                                         7
17490 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X4                                                            0x000010UL //Access:RW   DataWidth:0x8   CMU FL LDHS count value  Chips: K2
17491 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5                                                            0x000014UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17492     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_FL_LDHS_O_9_8                               (0x3<<0) // CMU FL LDHS count value
17493     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_FL_LDHS_O_9_8_SHIFT                         0
17494     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O                           (0x1<<2) // CMU reference div2 enable
17495     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_SHIFT                     2
17496     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O                               (0x1<<3) // CMU FL prediv4 enable
17497     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O_SHIFT                         3
17498     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O                       (0x1<<4) // Reference clock startup deglitch circuit disable
17499     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_SHIFT                 4
17500     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_UNUSED_0                                               (0x7<<5) // reserved
17501     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X5_UNUSED_0_SHIFT                                         5
17502 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X6                                                            0x000018UL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
17503 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X7                                                            0x00001cUL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
17504 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X8                                                            0x000020UL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
17505 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X9                                                            0x000024UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17506     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X9_GCFSM_OVR_O_27_24                                      (0xf<<0) // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
17507     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X9_GCFSM_OVR_O_27_24_SHIFT                                0
17508     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X9_UNUSED_0                                               (0xf<<4) // reserved
17509     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X9_UNUSED_0_SHIFT                                         4
17510 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X10                                                           0x000028UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
17511 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X11                                                           0x00002cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
17512 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X12                                                           0x000030UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
17513 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X13                                                           0x000034UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
17514 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X14                                                           0x000038UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
17515 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X15                                                           0x00003cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
17516 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X16                                                           0x000040UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
17517 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X17                                                           0x000044UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
17518 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X18                                                           0x000048UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
17519 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X19                                                           0x00004cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
17520 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X20                                                           0x000050UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
17521 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X21                                                           0x000054UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
17522 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X22                                                           0x000058UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
17523 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X23                                                           0x00005cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
17524 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X24                                                           0x000060UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
17525 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X25                                                           0x000064UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
17526 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26                                                           0x000068UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17527     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O                                (0x1<<0) // GCFSM output override enable
17528     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O_SHIFT                          0
17529     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0                          (0x7f<<1) // GCFSM pma_data_o override
17530     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_SHIFT                    1
17531 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27                                                           0x00006cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17532     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7                         (0x1f<<0) // GCFSM pma_data_o override
17533     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_SHIFT                   0
17534     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O                             (0x1<<5) // GCFSM pma_latch_o override
17535     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O_SHIFT                       5
17536     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O                                (0x1<<6) // GCFSM pma_go_o override
17537     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O_SHIFT                          6
17538     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O                              (0x1<<7) // GCFSM pma_read_o override
17539     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O_SHIFT                        7
17540 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X28                                                           0x000070UL //Access:RW   DataWidth:0x8   GCFSM pma_cal_o override  Chips: K2
17541 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X29                                                           0x000074UL //Access:RW   DataWidth:0x8   GCFSM pma_cal_o override  Chips: K2
17542 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30                                                           0x000078UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17543     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O                          (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable
17544     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_SHIFT                    0
17545     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O                          (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - REF clock output enable
17546     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_SHIFT                    2
17547     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_LOCK_EN_OUT_OVR_O                             (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LOCK output enable
17548     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_SHIFT                       4
17549     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O                         (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU
17550     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_SHIFT                   6
17551 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31                                                           0x00007cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17552     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O                      (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable - switches to SOC from life clock
17553     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_SHIFT                0
17554     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O                    (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU SYNTH
17555     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_SHIFT              2
17556     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O                      (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU VC0
17557     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_SHIFT                4
17558     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O                       (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - IDDQ BIAS
17559     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_SHIFT                 6
17560 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32                                                           0x000080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17561     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O                         (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD BIAS
17562     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_SHIFT                   0
17563     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O                          (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU
17564     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_SHIFT                    2
17565     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O                       (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REG
17566     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_SHIFT                 4
17567     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O                          (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD REF OUT
17568     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_SHIFT                    6
17569 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33                                                           0x000084UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17570     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O                 (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PCS CLK ENA
17571     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_SHIFT           0
17572     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O                      (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU FL
17573     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_SHIFT                2
17574     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O                    (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU GCRX
17575     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_SHIFT              4
17576     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O                      (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LF EXTZERO ENA
17577     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_SHIFT                6
17578 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34                                                           0x000088UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17579     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O                     (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LFI EXTZERO ENA
17580     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_SHIFT               0
17581     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O                    (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REGREF
17582     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_SHIFT              2
17583     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O                     (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU REGREF
17584     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_SHIFT               4
17585     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_TXCLK_OVR_O                             (0x3<<6) // Override register for reset_txclk
17586     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_TXCLK_OVR_O_SHIFT                       6
17587 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35                                                           0x00008cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17588     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_RESET_CLKDIV_OVR_O                            (0x3<<0) // Override register for reset_clkdiv_ovr
17589     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_RESET_CLKDIV_OVR_O_SHIFT                      0
17590     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_OVR_O                               (0x3<<2) // Override register for pd_clkdiv_ovr
17591     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_OVR_O_SHIFT                         2
17592     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_REFCLK_LEFT_OVR_O                   (0x3<<4) // Override register for pd_clkdiv_refclk_left_ovr
17593     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_REFCLK_LEFT_OVR_O_SHIFT             4
17594     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_REFCLK_RIGHT_OVR_O                  (0x3<<6) // Override register for pd_clkdiv_refclk_right_ovr
17595     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X35_MSM_PMA_PD_CLKDIV_REFCLK_RIGHT_OVR_O_SHIFT            6
17596 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X56                                                           0x0000e0UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17597 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X57                                                           0x0000e4UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17598 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X58                                                           0x0000e8UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17599 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X59                                                           0x0000ecUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17600 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X60                                                           0x0000f0UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17601 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X61                                                           0x0000f4UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17602 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X62                                                           0x0000f8UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17603 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X63                                                           0x0000fcUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17604 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X64                                                           0x000100UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17605 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X65                                                           0x000104UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17606 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X66                                                           0x000108UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17607 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X67                                                           0x00010cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17608 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X68                                                           0x000110UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17609 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X69                                                           0x000114UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17610 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X70                                                           0x000118UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17611 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X71                                                           0x00011cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17612 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X72                                                           0x000120UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17613 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X73                                                           0x000124UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17614 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X74                                                           0x000128UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17615 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X75                                                           0x00012cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17616 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X76                                                           0x000130UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17617 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X77                                                           0x000134UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17618 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X78                                                           0x000138UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17619 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X79                                                           0x00013cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17620 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X80                                                           0x000140UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17621 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X81                                                           0x000144UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17622 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X82                                                           0x000148UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17623 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X83                                                           0x00014cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17624 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X84                                                           0x000150UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17625 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X85                                                           0x000154UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17626 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X86                                                           0x000158UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17627 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X87                                                           0x00015cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17628 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X88                                                           0x000160UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17629 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X89                                                           0x000164UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17630 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X90                                                           0x000168UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17631 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X91                                                           0x00016cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
17632 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92                                                           0x000170UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17633     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_MSM_FUNC_DATA_O_289_288                               (0x3<<0) // MSM Function Data Bus slice
17634     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_MSM_FUNC_DATA_O_289_288_SHIFT                         0
17635     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_MSM_IN_OVR_O_5_0                                      (0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag override [3:0] - MFSM function override
17636     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X92_MSM_IN_OVR_O_5_0_SHIFT                                2
17637 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X93                                                           0x000174UL //Access:RW   DataWidth:0x8   Number of reference clock cycles to count after qsample is ok, before PLL is declared locked  Chips: K2
17638 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94                                                           0x000178UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17639     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_NUM_CYCLES_O_9_8                             (0x3<<0) // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
17640     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_NUM_CYCLES_O_9_8_SHIFT                       0
17641     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O                                 (0x1<<2) // State of qsample for PLL to be considered locked
17642     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O_SHIFT                           2
17643     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O                                        (0x7<<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycle count after qsample is ok [0] - Qsample override
17644     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O_SHIFT                                  3
17645     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_UNUSED_0                                              (0x3<<6) // reserved
17646     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X94_UNUSED_0_SHIFT                                        6
17647 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95                                                           0x00017cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17648     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_KVCO_SEL_O                               (0x3<<0) // CMU VCO integral path gain
17649     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_KVCO_SEL_O_SHIFT                         0
17650     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_FORCE_ILF_O                                (0x3<<2) // CMU loop filter force to common mode
17651     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_FORCE_ILF_O_SHIFT                          2
17652     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_CP_SEL_O                                 (0x3<<4) // Charge pump current gain select.
17653     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_CP_SEL_O_SHIFT                           4
17654     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O                                    (0x1<<6) // CMU PLL HIZ setting
17655     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O_SHIFT                              6
17656     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O                                   (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
17657     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O_SHIFT                             7
17658 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96                                                           0x000180UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17659     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_P_CAP_SEL_O                                (0x7<<0) // CMU VCO proportional path cap select
17660     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_P_CAP_SEL_O_SHIFT                          0
17661     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O                          (0x1<<3) // Charge pump chop enable
17662     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_SHIFT                    3
17663     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_I_CAP_SEL_O                                (0x7<<4) // CMU VCO integral path cap select
17664     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_I_CAP_SEL_O_SHIFT                          4
17665     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O                              (0x1<<7) // Bandgap startup circuit bypass
17666     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O_SHIFT                        7
17667 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97                                                           0x000184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17668     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VCO_BIAS_O                                 (0xf<<0) // CMU VCO bias current setting.
17669     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VCO_BIAS_O_SHIFT                           0
17670     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREG_O                                     (0x3<<4) // CMU VREG setting
17671     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREG_O_SHIFT                               4
17672     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREGH_O                                    (0x3<<6) // CMU VREGH setting
17673     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREGH_O_SHIFT                              6
17674 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98                                                           0x000188UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17675     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O                             (0x1<<0) // Force PFD to output down
17676     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O_SHIFT                       0
17677     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O                             (0x1<<1) // Force PFD to output up
17678     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_SHIFT                       1
17679     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O                                     (0x1<<2) // Override enable for overriding N-div value
17680     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O_SHIFT                               2
17681     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O                         (0x1<<3) // CMU V2I filter enable
17682     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_SHIFT                   3
17683     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O                   (0x1<<4) // CMU VCO PMOS proportional current increase
17684     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_SHIFT             4
17685     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O                   (0x1<<5) // CMU VCO PMOS proportional current decrease
17686     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_SHIFT             5
17687     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_VREGREF_O                                  (0x3<<6) // CMU reference clock regulator setting
17688     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_VREGREF_O_SHIFT                            6
17689 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X99                                                           0x00018cUL //Access:RW   DataWidth:0x8   CMU AFE spares  Chips: K2
17690 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100                                                          0x000190UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17691     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_PFD_PW_O                                  (0x3<<0) // PFD pulse width setting
17692     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_PFD_PW_O_SHIFT                            0
17693     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O                                 (0x1<<2) // Enable to reduce charge pump reference current
17694     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O_SHIFT                           2
17695     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O                              (0x1f<<3) // CMU PLL KVCO setting
17696     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O_SHIFT                        3
17697 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X101                                                          0x000194UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17698     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X101_AHB_PMA_CM_DIVPSEL_O                                 (0x7f<<0) // CMU P-divider setting
17699     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X101_AHB_PMA_CM_DIVPSEL_O_SHIFT                           0
17700     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X101_RESERVEDFIELD0                                       (0x1<<7) // Reserved
17701     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X101_RESERVEDFIELD0_SHIFT                                 7
17702 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102                                                          0x000198UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17703     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_O                                   (0x7<<0) // AHB override for calibrated VCOFR value.
17704     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_O_SHIFT                             0
17705     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O                               (0x1<<3) // Override enable for overriding VCOFR value
17706     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O_SHIFT                         3
17707     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_RESERVEDFIELD1                                       (0xf<<4) // Reserved
17708     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X102_RESERVEDFIELD1_SHIFT                                 4
17709 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG0                                                  0x00019cUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
17710 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG1                                                  0x0001a0UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
17711 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG2                                                  0x0001a4UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
17712 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG3                                                  0x0001a8UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
17713 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG4                                                  0x0001acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17714     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG4_RESERVEDFIELD6                               (0xf<<0) // Reserved
17715     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG4_RESERVEDFIELD6_SHIFT                         0
17716     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG4_UNUSED_0                                     (0xf<<4) // reserved
17717     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG4_UNUSED_0_SHIFT                               4
17718 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108                                                          0x0001b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17719     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_RESERVEDFIELD7                                       (0x7<<0) // Reserved
17720     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_RESERVEDFIELD7_SHIFT                                 0
17721     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0                          (0xf<<3) // Reference clock output select
17722     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_SHIFT                    3
17723     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O                                 (0x1<<7) // Reference clock select override
17724     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O_SHIFT                           7
17725 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109                                                          0x0001b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17726     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O                                    (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
17727     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O_SHIFT                              0
17728     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O                                    (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
17729     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O_SHIFT                              1
17730     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O                                     (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
17731     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O_SHIFT                               2
17732     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O                                     (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
17733     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O_SHIFT                               3
17734     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O                                    (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
17735     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O_SHIFT                              4
17736     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_RESERVEDFIELD8                                       (0x1<<5) // Reserved
17737     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_RESERVEDFIELD8_SHIFT                                 5
17738     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O                                  (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
17739     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O_SHIFT                            6
17740     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O                                  (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
17741     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O_SHIFT                            7
17742 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X110                                                          0x0001b8UL //Access:RW   DataWidth:0x8   Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode  Chips: K2
17743 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X111                                                          0x0001bcUL //Access:RW   DataWidth:0x8   Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode  Chips: K2
17744 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112                                                          0x0001c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17745     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_FCNTL_O_19_16                                    (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
17746     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_FCNTL_O_19_16_SHIFT                              0
17747     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O                                         (0x1<<4) // Active high Enable for SSC generator SSC mode
17748     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O_SHIFT                                   4
17749     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O                                             (0x1<<5) // Active high Enable for SSC block synth or SSC mode
17750     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O_SHIFT                                       5
17751     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_UNUSED_0                                             (0x3<<6) // reserved
17752     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X112_UNUSED_0_SHIFT                                       6
17753 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X113                                                          0x0001c4UL //Access:RW   DataWidth:0x8   SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz  Chips: K2
17754 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X114                                                          0x0001c8UL //Access:RW   DataWidth:0x8   SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz  Chips: K2
17755 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115                                                          0x0001ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17756     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_MATCH_VAL_O_19_16                            (0xf<<0) // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
17757     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_MATCH_VAL_O_19_16_SHIFT                      0
17758     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O                                 (0x1<<4) // Enable for SSC generator with Fractional Synthesis
17759     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O_SHIFT                           4
17760     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O                               (0x1<<5) // Enable fractional division mode and SSC mode
17761     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O_SHIFT                         5
17762     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O                                  (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
17763     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O_SHIFT                            6
17764     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_UNUSED_0                                             (0x1<<7) // reserved
17765     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X115_UNUSED_0_SHIFT                                       7
17766 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X116                                                          0x0001d0UL //Access:RW   DataWidth:0x8   In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word  Chips: K2
17767 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X117                                                          0x0001d4UL //Access:RW   DataWidth:0x8   In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word  Chips: K2
17768 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118                                                          0x0001d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17769     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_IN_O                                   (0xf<<0) // Test input bus
17770     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_IN_O_SHIFT                             0
17771     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_CTRL_O                                 (0x3<<4) // Test i/p control source :  0-modulator  1-bypass modulator  2-modulator  3-sr_txt_in_i
17772     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_CTRL_O_SHIFT                           4
17773     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O                              (0x1<<6) // Clock Select for High Speed clock source :  0-clk_hs_fbk  1-clk_hs_refout
17774     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O_SHIFT                        6
17775     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O                              (0x1<<7) // Clock divider for High Speed clock source
17776     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O_SHIFT                        7
17777 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119                                                          0x0001dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17778     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0                           (0x1f<<0) // override for the counter value
17779     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_SHIFT                     0
17780     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O                           (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
17781     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_SHIFT                     5
17782     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O                          (0x1<<6) // chicken bit for counter polarity
17783     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O_SHIFT                    6
17784     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O                            (0x1<<7) // override enable to use above value
17785     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_SHIFT                      7
17786 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X120                                                          0x0001e0UL //Access:RW   DataWidth:0x8   Divider input for Div-by-N counter  Chips: K2
17787 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X121                                                          0x0001e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17788     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8                      (0x7f<<0) // Divider input for Div-by-N counter
17789     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_SHIFT                0
17790     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X121_UNUSED_0                                             (0x1<<7) // reserved
17791     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X121_UNUSED_0_SHIFT                                       7
17792 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122                                                          0x0001e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17793     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_O                             (0x1f<<0) // Refclk Termination override value
17794     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_O_SHIFT                       0
17795     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O                          (0x1<<5) // Refclk Termination override enable
17796     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_SHIFT                    5
17797     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_UNUSED_0                                             (0x3<<6) // reserved
17798     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X122_UNUSED_0_SHIFT                                       6
17799 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123                                                          0x0001ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17800     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_O                                 (0x1f<<0) // Rx Termination override value, every rx lane gets the same value
17801     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_O_SHIFT                           0
17802     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O                              (0x1<<5) // Rx Termination override enable
17803     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O_SHIFT                        5
17804     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_UNUSED_0                                             (0x3<<6) // reserved
17805     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X123_UNUSED_0_SHIFT                                       6
17806 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X124                                                          0x0001f0UL //Access:RW   DataWidth:0x8   In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  Chips: K2
17807 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125                                                          0x0001f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17808     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8                             (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
17809     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8_SHIFT                       0
17810     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE                           (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
17811     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_SHIFT                     1
17812     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_UP_NUM_SAMPLES                             (0xf<<4) // in txterm calibration, the number of samples to take from the same comparator
17813     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_UP_NUM_SAMPLES_SHIFT                       4
17814 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126                                                          0x0001f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17815     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR                                 (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
17816     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR_SHIFT                           0
17817     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR                                   (0x7<<1) // Bit 3:1 RX termination calibration DAC override setting
17818     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR_SHIFT                             1
17819     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_UNUSED_0                                             (0xf<<4) // reserved
17820     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X126_UNUSED_0_SHIFT                                       4
17821 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127                                                          0x0001fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17822     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O                                     (0x1<<0) // Master reset for CMU
17823     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O_SHIFT                               0
17824     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O                                           (0x3<<1) // Determines rate for PLL clock pcs_rate_o[0] :      0: VCO clock untouched      1: VCO clock divided by 2                                                 pcs_rate_o[1] :      0: PMA operates in 10b/20b mode Enables %5 circuit      1: PMA operates in 8b/16b mode   Enables %4 circuit
17825     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O_SHIFT                                     1
17826     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_UNUSED_0                                             (0x1f<<3) // reserved
17827     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X127_UNUSED_0_SHIFT                                       3
17828 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X128                                                          0x000200UL //Access:RW   DataWidth:0x8   Bit 7:5 amux_ena[2:0] Bit 4:0 amux_sel_o[4:0] For detailed description please refer to Phy User manual.  Chips: K2
17829 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129                                                          0x000204UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17830     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_CMU_IN_OVR_O_3_0                                     (0xf<<0) // Override for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] - CMU Reset Pin IO
17831     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_CMU_IN_OVR_O_3_0_SHIFT                               0
17832     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_CMU_OUT_OVR_O_1_0                                    (0x3<<4) // Override for Reset_smu_fl
17833     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_CMU_OUT_OVR_O_1_0_SHIFT                              4
17834     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_UNUSED_0                                             (0x3<<6) // reserved
17835     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X129_UNUSED_0_SHIFT                                       6
17836 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130                                                          0x000208UL //Access:R    DataWidth:0x8   Snapshot of digital test bus data [7:0]  Chips: K2
17837 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131                                                          0x00020cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
17838     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_TBUS_DATA_SMPL_11_8                                  (0xf<<0) // Snapshot of digital test bus data [11:8]
17839     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_TBUS_DATA_SMPL_11_8_SHIFT                            0
17840     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_UNUSED_0                                             (0xf<<4) // reserved
17841     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_UNUSED_0_SHIFT                                       4
17842 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132                                                          0x000210UL //Access:RW   DataWidth:0x8   CMU Test Bus address 7-0  Chips: K2
17843 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133                                                          0x000214UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17844     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_TBUS_ADDR_OVR_O_10_8                                 (0x7<<0) // CMU Test Bus address 10-8
17845     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_TBUS_ADDR_OVR_O_10_8_SHIFT                           0
17846     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_UNUSED_0                                             (0x1f<<3) // reserved
17847     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_UNUSED_0_SHIFT                                       3
17848 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X134                                                          0x000218UL //Access:RW   DataWidth:0x8   Not used  Chips: K2
17849 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X144                                                          0x000240UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17850     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X144_UNUSED_0                                             (0x1f<<0) // reserved
17851     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X144_UNUSED_0_SHIFT                                       0
17852     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X144_RESERVEDFIELD9                                       (0x1<<5) // Reserved
17853     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X144_RESERVEDFIELD9_SHIFT                                 5
17854     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X144_UNUSED_1                                             (0x3<<6) // reserved
17855     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X144_UNUSED_1_SHIFT                                       6
17856 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X146                                                          0x000248UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17857     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X146_UNUSED_0                                             (0x7f<<0) // reserved
17858     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X146_UNUSED_0_SHIFT                                       0
17859     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X146_RESERVEDFIELD10                                      (0x1<<7) // Reserved
17860     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X146_RESERVEDFIELD10_SHIFT                                7
17861 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X147                                                          0x00024cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17862     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O                     (0x7<<0) // wait multiplication factor for msm_cmu_databank
17863     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_SHIFT               0
17864     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X147_RESERVEDFIELD11                                      (0x1f<<3) // Reserved
17865     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X147_RESERVEDFIELD11_SHIFT                                3
17866 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG5                                                  0x000250UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
17867 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X149                                                          0x000254UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17868     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X149_AHB_PMA_CM_EN_REGLN_O                                (0xf<<0) // Not used
17869     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X149_AHB_PMA_CM_EN_REGLN_O_SHIFT                          0
17870     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X149_UNUSED_0                                             (0xf<<4) // reserved
17871     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X149_UNUSED_0_SHIFT                                       4
17872 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X153                                                          0x000264UL //Access:RW   DataWidth:0x8   Inverts up_i when set to 1  Chips: K2
17873 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X154                                                          0x000268UL //Access:RW   DataWidth:0x8   Inverts up_i when set to 1  Chips: K2
17874 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X161                                                          0x000284UL //Access:RW   DataWidth:0x8   Function info for each MSM function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of commands to run  Chips: K2
17875 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X162                                                          0x000288UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17876 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X163                                                          0x00028cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17877 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X164                                                          0x000290UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17878 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X165                                                          0x000294UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17879 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X166                                                          0x000298UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17880 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X167                                                          0x00029cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17881 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X168                                                          0x0002a0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17882 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X169                                                          0x0002a4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17883 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X170                                                          0x0002a8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17884 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X171                                                          0x0002acUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17885 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X172                                                          0x0002b0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17886 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X173                                                          0x0002b4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17887 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X174                                                          0x0002b8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17888 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X175                                                          0x0002bcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17889 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X176                                                          0x0002c0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17890 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X177                                                          0x0002c4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17891 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X178                                                          0x0002c8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17892 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X179                                                          0x0002ccUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17893 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X180                                                          0x0002d0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17894 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X181                                                          0x0002d4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17895 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X182                                                          0x0002d8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17896 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X183                                                          0x0002dcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17897 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X184                                                          0x0002e0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17898 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X185                                                          0x0002e4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17899 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X186                                                          0x0002e8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17900 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X187                                                          0x0002ecUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17901 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X188                                                          0x0002f0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
17902 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG6                                                  0x0002f4UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
17903 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_RESERVEDREG7                                                  0x0002f8UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
17904 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191                                                          0x0002fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17905     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O                              (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
17906     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O_SHIFT                        0
17907     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O                                (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
17908     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O_SHIFT                          1
17909     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O                    (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
17910     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_SHIFT              2
17911     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O                                 (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
17912     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O_SHIFT                           3
17913     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O                              (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
17914     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O_SHIFT                        4
17915     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O                           (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
17916     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O_SHIFT                     5
17917     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O                                 (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
17918     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O_SHIFT                           6
17919     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O                           (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
17920     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_SHIFT                     7
17921 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192                                                          0x000300UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17922     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O                              (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
17923     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O_SHIFT                        0
17924     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O                         (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
17925     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_SHIFT                   1
17926     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O                           (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
17927     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O_SHIFT                     2
17928     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O                        (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
17929     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_SHIFT                  3
17930     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O                         (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
17931     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_SHIFT                   4
17932     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O                           (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
17933     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O_SHIFT                     5
17934     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O                         (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
17935     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_SHIFT                   6
17936     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O                            (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
17937     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_SHIFT                      7
17938 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193                                                          0x000304UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17939     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O                             (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
17940     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O_SHIFT                       0
17941     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O                              (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
17942     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O_SHIFT                        1
17943     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O                            (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
17944     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_SHIFT                      2
17945     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O                            (0x1<<3) // Not used
17946     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_SHIFT                      3
17947     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O                           (0x1<<4) // Not used
17948     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O_SHIFT                     4
17949     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O                              (0x1<<5) // Not used
17950     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O_SHIFT                        5
17951     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O                  (0x1<<6) // Not used
17952     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_SHIFT            6
17953     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O                 (0x1<<7) // Not used
17954     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_SHIFT           7
17955 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194                                                          0x000308UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17956     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O                               (0x1<<0) // MSM Function RST mode default value for iddq_bias
17957     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O_SHIFT                         0
17958     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O                                 (0x1<<1) // MSM Function RST mode default value for pd_bias
17959     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O_SHIFT                           1
17960     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O                     (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
17961     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_SHIFT               2
17962     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O                                  (0x1<<3) // MSM Function RST mode default value for pd_cmu
17963     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O_SHIFT                            3
17964     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O                               (0x1<<4) // MSM Function RST mode default value for pd_cmureg
17965     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O_SHIFT                         4
17966     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O                            (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
17967     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O_SHIFT                      5
17968     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O                                  (0x1<<6) // MSM Function RST mode default value for pd_ref
17969     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O_SHIFT                            6
17970     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O                            (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
17971     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O_SHIFT                      7
17972 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195                                                          0x00030cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17973     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O                               (0x1<<0) // MSM Function RST mode default value for reset_cmu
17974     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O_SHIFT                         0
17975     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O                          (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
17976     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_SHIFT                    1
17977     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O                            (0x1<<2) // MSM Function RST mode default value for reset_cmureg
17978     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O_SHIFT                      2
17979     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O                         (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
17980     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O_SHIFT                   3
17981     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O                          (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
17982     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O_SHIFT                    4
17983     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O                            (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
17984     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O_SHIFT                      5
17985     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O                          (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
17986     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O_SHIFT                    6
17987     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O                             (0x1<<7) // MSM Function RST mode default value for lfi_extzero
17988     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O_SHIFT                       7
17989 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196                                                          0x000310UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
17990     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O                              (0x1<<0) // MSM Function RST mode default value for soc_clk_en
17991     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O_SHIFT                        0
17992     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O                               (0x1<<1) // MSM Function RST mode default value for refclk_en
17993     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O_SHIFT                         1
17994     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O                             (0x1<<2) // MSM Function RST mode default value for pll_lock_en
17995     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O_SHIFT                       2
17996     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O                             (0x1<<3) // Not used
17997     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_SHIFT                       3
17998     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O                            (0x1<<4) // Not used
17999     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O_SHIFT                      4
18000     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O                               (0x1<<5) // Not used
18001     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O_SHIFT                         5
18002     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O                   (0x1<<6) // Not used
18003     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_SHIFT             6
18004     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O                  (0x1<<7) // Not used
18005     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_SHIFT            7
18006 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197                                                          0x000314UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18007     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O                              (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
18008     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O_SHIFT                        0
18009     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O                                (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
18010     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O_SHIFT                          1
18011     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O                    (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
18012     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_SHIFT              2
18013     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O                                 (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
18014     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O_SHIFT                           3
18015     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O                              (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
18016     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O_SHIFT                        4
18017     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O                           (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
18018     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O_SHIFT                     5
18019     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O                                 (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
18020     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O_SHIFT                           6
18021     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O                           (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
18022     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O_SHIFT                     7
18023 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198                                                          0x000318UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18024     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O                              (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
18025     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O_SHIFT                        0
18026     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O                         (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
18027     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_SHIFT                   1
18028     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O                           (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
18029     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O_SHIFT                     2
18030     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O                        (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
18031     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O_SHIFT                  3
18032     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O                         (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
18033     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O_SHIFT                   4
18034     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O                           (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
18035     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O_SHIFT                     5
18036     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O                         (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
18037     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_SHIFT                   6
18038     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O                            (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
18039     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O_SHIFT                      7
18040 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199                                                          0x00031cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18041     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O                             (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
18042     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O_SHIFT                       0
18043     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O                              (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
18044     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O_SHIFT                        1
18045     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O                            (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
18046     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O_SHIFT                      2
18047     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O                            (0x1<<3) // Not used
18048     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_SHIFT                      3
18049     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O                           (0x1<<4) // Not used
18050     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O_SHIFT                     4
18051     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O                              (0x1<<5) // Not used
18052     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O_SHIFT                        5
18053     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O                  (0x1<<6) // Not used
18054     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_SHIFT            6
18055     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O                 (0x1<<7) // Not used
18056     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_SHIFT           7
18057 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200                                                          0x000320UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18058     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O                                (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
18059     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O_SHIFT                          0
18060     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O                                  (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
18061     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O_SHIFT                            1
18062     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O                      (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
18063     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_SHIFT                2
18064     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O                                   (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
18065     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O_SHIFT                             3
18066     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O                                (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
18067     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O_SHIFT                          4
18068     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O                             (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
18069     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O_SHIFT                       5
18070     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O                                   (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
18071     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O_SHIFT                             6
18072     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O                             (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
18073     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O_SHIFT                       7
18074 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201                                                          0x000324UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18075     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O                                (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
18076     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O_SHIFT                          0
18077     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O                           (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
18078     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O_SHIFT                     1
18079     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O                             (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
18080     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O_SHIFT                       2
18081     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O                          (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
18082     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O_SHIFT                    3
18083     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O                           (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
18084     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O_SHIFT                     4
18085     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O                             (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
18086     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O_SHIFT                       5
18087     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O                           (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
18088     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O_SHIFT                     6
18089     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O                              (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
18090     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O_SHIFT                        7
18091 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202                                                          0x000328UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18092     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O                               (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
18093     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O_SHIFT                         0
18094     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O                                (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
18095     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O_SHIFT                          1
18096     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O                              (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
18097     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O_SHIFT                        2
18098     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O                              (0x1<<3) // Not used
18099     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_SHIFT                        3
18100     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O                             (0x1<<4) // Not used
18101     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O_SHIFT                       4
18102     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O                                (0x1<<5) // Not used
18103     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O_SHIFT                          5
18104     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O                    (0x1<<6) // Not used
18105     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_SHIFT              6
18106     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O                   (0x1<<7) // Not used
18107     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_SHIFT             7
18108 #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X210                                                          0x000348UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18109     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X210_UNUSED_0                                             (0x7f<<0) // reserved
18110     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X210_UNUSED_0_SHIFT                                       0
18111     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X210_RESERVEDFIELD15                                      (0x1<<7) // Reserved
18112     #define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X210_RESERVEDFIELD15_SHIFT                                7
18113 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0                                                           0x001000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18114     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_SRC_SEL_O                            (0x7<<0) // Clock source select for TX path branch 1 clock :  3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b010 - pma_lX_rxb_iRecovered byte clock 3'b011 - ck_soc1_int_root 3'b100,3'b101,3'b110 - Reserved 3'b111 - test_clk_0_i
18115     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_SRC_SEL_O_SHIFT                      0
18116     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_DIV_SEL_O                            (0x1<<3) // Clock divider for TX path branch 1 : 0-No division, 1- Divide by 2
18117     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH1_DIV_SEL_O_SHIFT                      3
18118     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_SRC_SEL_O                            (0x7<<4) // Clock source select for TX path branch 2 clock : 3'b000 - lnX_clk_i 3'b001- qd_ck_i 3'b011 - ck_soc1_int_root 3'b010,3'b100,3'b101,3'b110 - Reserved 3'b111 - test_clk_0_i
18119     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_SRC_SEL_O_SHIFT                      4
18120     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O                            (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
18121     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_SHIFT                      7
18122 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1                                                           0x001004UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18123     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_SRC_SEL_O                            (0x7<<0) // Clock source select for RX path branch 1 clock : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b011,3'b100,3'b101,3'b110 - Reserved 3'b111 - test_clk_1_i
18124     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_SRC_SEL_O_SHIFT                      0
18125     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O                            (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
18126     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_SHIFT                      3
18127     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_SRC_SEL_O                            (0x7<<4) // Clock source select for RX path branch 2 clock : 3'b000 - pma_lX_rxb_iRecovered byte clock 3'b001- pma_lX_txb_iTransmit byte clock 3'b010,3'b011,3'b100,3'b101,3'b110 - Reserved 3'b111 - test_clk_1_i
18128     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_SRC_SEL_O_SHIFT                      4
18129     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O                            (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
18130     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_SHIFT                      7
18131 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2                                                           0x001008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18132     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_SRC_SEL_O                            (0x7<<0) // Clock source select for RX path branch 3 clock : 3'b000 - qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmit byte clock 3'b100 - ck_soc1_int_root 3'b101,3'b110 - Reserved 3'b111 - test_clk_1_i
18133     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_SRC_SEL_O_SHIFT                      0
18134     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_DIV_SEL_O                            (0x1<<3) // Clock divider for RX path branch 3 : 0-No division, 1- Divide by 2
18135     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH3_DIV_SEL_O_SHIFT                      3
18136     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_SRC_SEL_O                            (0x7<<4) // Clock source select for RX path branch 4 clock : 3'b000 - qd_ck_i 3'b001- pma_lX_rxb_iRecovered byte clock 3'b010 - lnX_clk_i 3'b011 - pma_lX_txb_iTransmit byte clock 3'b100 - ck_soc1_int_root 3'b101,3'b110 - Reserved 3'b111 - test_clk_1_i
18137     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_SRC_SEL_O_SHIFT                      4
18138     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O                            (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
18139     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_SHIFT                      7
18140 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3                                                           0x00100cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18141     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0                                       (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
18142     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0_SHIFT                                 0
18143     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1                                     (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
18144     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1_SHIFT                               1
18145     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_UNUSED_0                                              (0x3f<<2) // reserved
18146     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X3_UNUSED_0_SHIFT                                        2
18147 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4                                                           0x001010UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18148     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_CDRCTRL_DIV_EN_O_1_0                                  (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
18149     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_CDRCTRL_DIV_EN_O_1_0_SHIFT                            0
18150     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_GCFSM_DIV_EN_O_1_0                                    (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
18151     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_GCFSM_DIV_EN_O_1_0_SHIFT                              2
18152     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_UNUSED_0                                              (0x7<<4) // reserved
18153     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_UNUSED_0_SHIFT                                        4
18154     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_RESERVEDFIELD130                                      (0x1<<7) // Reserved
18155     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X4_RESERVEDFIELD130_SHIFT                                7
18156 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5                                                           0x001014UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18157     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_REF_CLK_DIV_EN_O_1_0                                  (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
18158     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_REF_CLK_DIV_EN_O_1_0_SHIFT                            0
18159     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_OOB_CLK_DIV_EN_O_1_0                                  (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
18160     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_OOB_CLK_DIV_EN_O_1_0_SHIFT                            2
18161     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_UNUSED_0                                              (0xf<<4) // reserved
18162     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X5_UNUSED_0_SHIFT                                        4
18163 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7                                                           0x00101cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18164     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O                                           (0x3<<0) // Rate control for BIST
18165     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O_SHIFT                                     0
18166     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O                                     (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
18167     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O_SHIFT                               2
18168     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O                                        (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
18169     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O_SHIFT                                  3
18170     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE                                  (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
18171     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE_SHIFT                            4
18172     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O                                        (0x1<<5) // Bist generator master reset.
18173     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O_SHIFT                                  5
18174     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O                                       (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
18175     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O_SHIFT                                 6
18176     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O                                         (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
18177     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O_SHIFT                                   7
18178 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8                                                           0x001020UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18179     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_CLK_SEL_O_2_0                                (0x7<<0) // BIST Generation Clock Selection
18180     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_CLK_SEL_O_2_0_SHIFT                          0
18181     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O                                 (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
18182     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O_SHIFT                           3
18183     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_INSERT_COUNT_O_2_0                           (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
18184     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_INSERT_COUNT_O_2_0_SHIFT                     4
18185     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_UNUSED_0                                              (0x1<<7) // reserved
18186     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X8_UNUSED_0_SHIFT                                        7
18187 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X9                                                           0x001024UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
18188 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X10                                                          0x001028UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
18189 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X11                                                          0x00102cUL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
18190 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X12                                                          0x001030UL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
18191 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X13                                                          0x001034UL //Access:RW   DataWidth:0x8   Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.  Chips: K2
18192 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14                                                          0x001038UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18193     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BIST_GEN_INSERT_DELAY_O_11_8                         (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
18194     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BIST_GEN_INSERT_DELAY_O_11_8_SHIFT                   0
18195     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_RESERVEDFIELD131                                     (0x1<<4) // Reserved
18196     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_RESERVEDFIELD131_SHIFT                               4
18197     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O                                            (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
18198     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O_SHIFT                                      5
18199     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O                                           (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
18200     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O_SHIFT                                     6
18201     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_UNUSED_0                                             (0x1<<7) // reserved
18202     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X14_UNUSED_0_SHIFT                                       7
18203 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15                                                          0x00103cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18204     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BCHK_SRC_O_1_0                                       (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
18205     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BCHK_SRC_O_1_0_SHIFT                                 0
18206     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_RESERVEDFIELD132                                     (0x1<<2) // Reserved
18207     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_RESERVEDFIELD132_SHIFT                               2
18208     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O                                 (0x1<<3) // Bist checker mode select. 0X0 ? UDP pattern. 0x1 ? PRBS pattern
18209     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O_SHIFT                           3
18210     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_LFSR_LENGTH_O_1_0                           (0x3<<4) // BIST PRBS pattern selector.
18211     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_LFSR_LENGTH_O_1_0_SHIFT                     4
18212     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_RESERVEDFIELD133                                     (0x1<<6) // Reserved
18213     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_RESERVEDFIELD133_SHIFT                               6
18214     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE                                 (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
18215     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE_SHIFT                           7
18216 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X16                                                          0x001040UL //Access:RW   DataWidth:0x8   Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.  Chips: K2
18217 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17                                                          0x001044UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18218     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_PREAM0_O_9_8                                (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
18219     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_PREAM0_O_9_8_SHIFT                          0
18220     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_INSERT_LENGTH_O_2_0                         (0x7<<2) // BIST Checker Insert word length.
18221     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_INSERT_LENGTH_O_2_0_SHIFT                   2
18222     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS                               (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
18223     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS_SHIFT                         5
18224     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_UNUSED_0                                             (0x3<<6) // reserved
18225     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X17_UNUSED_0_SHIFT                                       6
18226 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X18                                                          0x001048UL //Access:RW   DataWidth:0x8   BIST Check Preamble  Chips: K2
18227 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X19                                                          0x00104cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18228     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X19_BIST_CHK_PREAM1_O_9_8                                (0x3<<0) // BIST Check Preamble
18229     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X19_BIST_CHK_PREAM1_O_9_8_SHIFT                          0
18230     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X19_UNUSED_0                                             (0x3f<<2) // reserved
18231     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X19_UNUSED_0_SHIFT                                       2
18232 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X20                                                          0x001050UL //Access:RW   DataWidth:0x8   Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.  Chips: K2
18233 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X21                                                          0x001054UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
18234 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X22                                                          0x001058UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
18235 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X23                                                          0x00105cUL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
18236 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X24                                                          0x001060UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
18237 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X25                                                          0x001064UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
18238 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X26                                                          0x001068UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
18239 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X27                                                          0x00106cUL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
18240 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X28                                                          0x001070UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
18241 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X29                                                          0x001074UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
18242 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X30                                                          0x001078UL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
18243 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X31                                                          0x00107cUL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
18244 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X32                                                          0x001080UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
18245 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X33                                                          0x001084UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
18246 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X34                                                          0x001088UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
18247 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X35                                                          0x00108cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
18248 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X36                                                          0x001090UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
18249 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X37                                                          0x001094UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
18250 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X38                                                          0x001098UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
18251 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X39                                                          0x00109cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
18252 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X40                                                          0x0010a0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
18253 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X41                                                          0x0010a4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
18254 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X42                                                          0x0010a8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
18255 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X43                                                          0x0010acUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
18256 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X44                                                          0x0010b0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
18257 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X45                                                          0x0010b4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
18258 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X46                                                          0x0010b8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
18259 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X47                                                          0x0010bcUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
18260 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X48                                                          0x0010c0UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 1/2 - for the new ICA method  Chips: K2
18261 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X49                                                          0x0010c4UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 3 - for the new ICA method  Chips: K2
18262 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X50                                                          0x0010c8UL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method  Chips: K2
18263 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X51                                                          0x0010ccUL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method  Chips: K2
18264 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X52                                                          0x0010d0UL //Access:RW   DataWidth:0x8   The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.  Chips: K2
18265 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53                                                          0x0010d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18266     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0                 (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
18267     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_SHIFT           0
18268     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2                          (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
18269     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_SHIFT                    5
18270     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN                              (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
18271     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN_SHIFT                        6
18272     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR                              (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
18273     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR_SHIFT                        7
18274 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X54                                                          0x0010d8UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
18275 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X55                                                          0x0010dcUL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
18276 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X56                                                          0x0010e0UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
18277 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57                                                          0x0010e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18278     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_OVR_O_27_24                                    (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
18279     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_OVR_O_27_24_SHIFT                              0
18280     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O                              (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
18281     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O_SHIFT                        4
18282     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O                           (0x1<<5) // GCFSM pma_latch_o override
18283     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O_SHIFT                     5
18284     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O                              (0x1<<6) // GCFSM pma_go_o override
18285     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O_SHIFT                        6
18286     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O                            (0x1<<7) // GCFSM pma_read_o override.
18287     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O_SHIFT                      7
18288 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X58                                                          0x0010e8UL //Access:RW   DataWidth:0x8   GCFSM pma_data_o override data. Bits applied to PMA are [8:15]  Chips: K2
18289 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X59                                                          0x0010ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18290     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8                       (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
18291     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_SHIFT                 0
18292     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X59_UNUSED_0                                             (0xf<<4) // reserved
18293     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X59_UNUSED_0_SHIFT                                       4
18294 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X60                                                          0x0010f0UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
18295 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X61                                                          0x0010f4UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
18296 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62                                                          0x0010f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18297     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_REQ_IN_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
18298     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_REQ_IN_OVR_O_SHIFT                            0
18299     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_FUNC_IN_OVR_O                                 (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
18300     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_FUNC_IN_OVR_O_SHIFT                           2
18301 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG41                                                0x0010fcUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18302 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG42                                                0x001100UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18303 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65                                                          0x001104UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18304     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28                                       (0x1<<0) // Not currently used
18305     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28_SHIFT                                 0
18306     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65_RESERVEDFIELD136                                     (0x7f<<1) // Reserved
18307     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X65_RESERVEDFIELD136_SHIFT                               1
18308 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X66                                                          0x001108UL //Access:RW   DataWidth:0x8   Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.  Chips: K2
18309 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67                                                          0x00110cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18310     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_DLY_CDR_O_6_0                               (0x7f<<0) // Number of clock cycles between signal detect indicator
18311     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_DLY_CDR_O_6_0_SHIFT                         0
18312     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8                          (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
18313     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_SHIFT                    7
18314 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X68                                                          0x001110UL //Access:RW   DataWidth:0x8   Number of clock cycles between CISEL assertion  Chips: K2
18315 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69                                                          0x001114UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18316     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_DLY_LANE_O_9_8                              (0x3<<0) // Number of clock cycles between CISEL assertion
18317     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_DLY_LANE_O_9_8_SHIFT                        0
18318     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_START_LEN_O_3_0                             (0xf<<2) // Number of clock cycles between when CDR control block
18319     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_START_LEN_O_3_0_SHIFT                       2
18320     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_INT_FIL_O_1_0                               (0x3<<6) // CDR control DLPF positioning control.
18321     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_INT_FIL_O_1_0_SHIFT                         6
18322 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X70                                                          0x001118UL //Access:RW   DataWidth:0x8   CDR control block cycle length When not in PCIe Gen3.  Chips: K2
18323 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72                                                          0x001120UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18324     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MAX_DIFF_O_4_0                              (0x1f<<0) // Maximum difference from DLPF center point.
18325     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MAX_DIFF_O_4_0_SHIFT                        0
18326     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MIN_BOUNCE_O_2_0                            (0x7<<5) // Maximum difference from DLPF center point.
18327     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_SHIFT                      5
18328 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73                                                          0x001124UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18329     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN                                (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
18330     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN_SHIFT                          0
18331     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O                               (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
18332     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O_SHIFT                         1
18333     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O                                       (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
18334     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O_SHIFT                                 2
18335     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7                               (0x7<<3) // Number of clock cycles between signal detect indicator
18336     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_SHIFT                         3
18337     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_UNUSED_0                                             (0x3<<6) // reserved
18338     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X73_UNUSED_0_SHIFT                                       6
18339 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X74                                                          0x001128UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
18340 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X75                                                          0x00112cUL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
18341 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X76                                                          0x001130UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
18342 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77                                                          0x001134UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18343     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_OUT_OVR_O_29_24                             (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
18344     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_OUT_OVR_O_29_24_SHIFT                       0
18345     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR                                (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
18346     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR_SHIFT                          6
18347     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_UNUSED_0                                             (0x1<<7) // reserved
18348     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X77_UNUSED_0_SHIFT                                       7
18349 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78                                                          0x001138UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18350     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_ALIGN_POS_O_5_0                            (0x3f<<0) // Symbol aligner position override enable.
18351     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_ALIGN_POS_O_5_0_SHIFT                      0
18352     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_MODE_O_1_0                                 (0x3<<6) // Symbol aligner mode select.
18353     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_MODE_O_1_0_SHIFT                           6
18354 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79                                                          0x00113cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18355     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O                                   (0x1<<0) // Asserting this register will bypass the symbol aligner
18356     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O_SHIFT                             0
18357     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79_UNUSED_0                                             (0x7f<<1) // reserved
18358     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X79_UNUSED_0_SHIFT                                       1
18359 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X80                                                          0x001140UL //Access:RW   DataWidth:0x8   Number of cycles to wait before forcing exit form EI  Chips: K2
18360 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81                                                          0x001144UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18361     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8                   (0x3<<0) // Number of cycles to wait before forcing exit form EI
18362     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_SHIFT             0
18363     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O                              (0x1<<2) // Clears the elec idle control error flag
18364     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O_SHIFT                        2
18365     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O                          (0x1<<3) // Override for ei_inferred signal
18366     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_SHIFT                    3
18367     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O                       (0x1<<4) // Override for ei_mask signal
18368     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_SHIFT                 4
18369     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O                        (0x1<<5) // Override for ei_exit_type signal
18370     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_SHIFT                  5
18371     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O                                  (0x1<<6) // EI control override enable
18372     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O_SHIFT                            6
18373     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_UNUSED_0                                             (0x1<<7) // reserved
18374     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X81_UNUSED_0_SHIFT                                       7
18375 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X82                                                          0x001148UL //Access:RW   DataWidth:0x8   Number of cycles to wait before entering back into EI  Chips: K2
18376 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X83                                                          0x00114cUL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect glitch filter counter  Chips: K2
18377 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X84                                                          0x001150UL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect low filter min value  Chips: K2
18378 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85                                                          0x001154UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18379     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8                   (0x3<<0) // Number of cycles to wait before entering back into EI
18380     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_SHIFT             0
18381     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0                    (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
18382     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_SHIFT              2
18383     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O                                        (0x1<<4) // Control signal to force decoder into loopback mode
18384     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O_SHIFT                                  4
18385     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_UNUSED_0                                             (0x7<<5) // reserved
18386     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X85_UNUSED_0_SHIFT                                       5
18387 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86                                                          0x001158UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18388     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O                                         (0x1<<0) // FES loopback enable.
18389     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O_SHIFT                                   0
18390     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O                                         (0x1<<1) // NES loopback enable.
18391     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O_SHIFT                                   1
18392     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O                                       (0x1<<2) // HS recovered clock to transmit loopback enable.
18393     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O_SHIFT                                 2
18394     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_UNUSED_0                                             (0x1f<<3) // reserved
18395     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X86_UNUSED_0_SHIFT                                       3
18396 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87                                                          0x00115cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18397     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O                            (0x1<<0) // RX boost override enable
18398     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O_SHIFT                      0
18399     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0                         (0x7f<<1) // RX boost override setting. Thermometer coded.
18400     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_SHIFT                   1
18401 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X88                                                          0x001160UL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
18402 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89                                                          0x001164UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18403     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV1_O                           (0x7<<0) // Signal detect threshold select for Full rate
18404     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_SHIFT                     0
18405     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O                           (0x7<<3) // Signal detect threshold select for div-by-2 rate
18406     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_SHIFT                     3
18407     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O                                    (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
18408     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O_SHIFT                              6
18409     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O                           (0x1<<7) // RX FL calibration clock DIV4 enable
18410     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_SHIFT                     7
18411 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90                                                          0x001168UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18412     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_SD_THSEL_DIV4_O                           (0x7<<0) // Signal detect threshold select for div-by-4 rate
18413     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_SHIFT                     0
18414     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O                               (0x7<<3) // AGC threshold select
18415     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O_SHIFT                         3
18416     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_VREGH_O                                   (0x3<<6) // Regulator VREGH setting
18417     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_VREGH_O_SHIFT                             6
18418 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X91                                                          0x00116cUL //Access:RW   DataWidth:0x8   RX FL calibration LDHS  Chips: K2
18419 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92                                                          0x001170UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18420     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXFL_LDHS_O_9_8                           (0x3<<0) // RX FL calibration LDHS
18421     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXFL_LDHS_O_9_8_SHIFT                     0
18422     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXVCO_BIAS_O                              (0xf<<2) // CDR VCO bias setting.
18423     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXVCO_BIAS_O_SHIFT                        2
18424     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O                           (0x1<<6) // DLPF DIV2 enable
18425     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_SHIFT                     6
18426     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O                            (0x1<<7) // CDR DivN clock divider enable.
18427     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_SHIFT                      7
18428 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X93                                                          0x001174UL //Access:RW   DataWidth:0x8   AFE spare controls  Chips: K2
18429 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94                                                          0x001178UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18430     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_CDR_DVDR_O                                (0x3f<<0) // CDR DivN clock division ratio.
18431     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_CDR_DVDR_O_SHIFT                          0
18432     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_VREG_O                                    (0x3<<6) // Regulator VREG setting
18433     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_VREG_O_SHIFT                              6
18434 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95                                                          0x00117cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18435     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_BB_STEP_O                                 (0xf<<0) // CDR bb_step
18436     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_BB_STEP_O_SHIFT                           0
18437     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_INT_STEP_O                                (0x7<<4) // CDR int step
18438     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_INT_STEP_O_SHIFT                          4
18439     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O                                   (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
18440     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O_SHIFT                             7
18441 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96                                                          0x001180UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18442     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_O                                 (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
18443     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_O_SHIFT                           0
18444     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O                             (0x1<<3) // Override enable for RXVCOFR override vakue
18445     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_SHIFT                       3
18446     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RX_SELR_O                                 (0x7<<4) // CTLE R degeneration select
18447     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RX_SELR_O_SHIFT                           4
18448     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_RESERVEDFIELD137                                     (0x1<<7) // Reserved
18449     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X96_RESERVEDFIELD137_SHIFT                               7
18450 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X97                                                          0x001184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18451     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X97_AHB_PMA_LN_RX_SELC_O                                 (0x7<<0) // CTLE C degeneration select
18452     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X97_AHB_PMA_LN_RX_SELC_O_SHIFT                           0
18453     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X97_RESERVEDFIELD138                                     (0x1f<<3) // Reserved
18454     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X97_RESERVEDFIELD138_SHIFT                               3
18455 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG43                                                0x001188UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18456 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99                                                          0x00118cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18457     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_RESERVEDFIELD140                                     (0xf<<0) // Reserved
18458     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_RESERVEDFIELD140_SHIFT                               0
18459     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_DFE_BW_SCALE                                  (0x3<<4) // DFE Bandwidth Selection
18460     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_DFE_BW_SCALE_SHIFT                            4
18461     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_PHD_ENA_O_1_0                                 (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
18462     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_PHD_ENA_O_1_0_SHIFT                           6
18463 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X100                                                         0x001190UL //Access:RW   DataWidth:0x8   On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal  Chips: K2
18464 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101                                                         0x001194UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18465     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8                                (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
18466     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8_SHIFT                          0
18467     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_RESERVEDFIELD141                                    (0x1<<1) // Reserved
18468     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_RESERVEDFIELD141_SHIFT                              1
18469     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O                                (0x1<<2) // Reset signal for eye alignment mechanism.
18470     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O_SHIFT                          2
18471     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL                                     (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
18472     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL_SHIFT                               3
18473     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O                                 (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
18474     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O_SHIFT                           4
18475     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O                                  (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
18476     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O_SHIFT                            5
18477     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_UNUSED_0                                            (0x3<<6) // reserved
18478     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X101_UNUSED_0_SHIFT                                      6
18479 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X102                                                         0x001198UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18480     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X102_PMA_LN_DFE_BIAS_O_3_0                               (0xf<<0) // DFE bias setting.
18481     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X102_PMA_LN_DFE_BIAS_O_3_0_SHIFT                         0
18482     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X102_UNUSED_0                                            (0xf<<4) // reserved
18483     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X102_UNUSED_0_SHIFT                                      4
18484 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103                                                         0x00119cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18485     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TX_SR_FASTCAP_O_3_0                          (0xf<<0) // TX driver capacitive slew rate control.
18486     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_SHIFT                    0
18487     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TXEQ_POLARITY_O_3_0                          (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
18488     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TXEQ_POLARITY_O_3_0_SHIFT                    4
18489 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104                                                         0x0011a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18490     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_TX_SR_DAC_O_3_0                              (0xf<<0) // TX slew rate DAC bias current control
18491     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_TX_SR_DAC_O_3_0_SHIFT                        0
18492     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O                                  (0x1<<4) // CDR clock divider bypass enable.
18493     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O_SHIFT                            4
18494     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_UNUSED_0                                            (0x7<<5) // reserved
18495     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X104_UNUSED_0_SHIFT                                      5
18496 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105                                                         0x0011a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18497     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TX_VREG_LEV_O_4_0                            (0x1f<<0) // TX driver regulator voltage setting.
18498     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TX_VREG_LEV_O_4_0_SHIFT                      0
18499     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O                            (0x1<<5) // TX bleed enable
18500     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O_SHIFT                      5
18501     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_UNUSED_0                                            (0x3<<6) // reserved
18502     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X105_UNUSED_0_SHIFT                                      6
18503 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X115                                                         0x0011ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18504     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X115_UNUSED_0                                            (0x7<<0) // reserved
18505     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X115_UNUSED_0_SHIFT                                      0
18506     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X115_RESERVEDFIELD142                                    (0x1f<<3) // Reserved
18507     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X115_RESERVEDFIELD142_SHIFT                              3
18508 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG44                                                0x0011d0UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18509 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG45                                                0x0011d4UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18510 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG46                                                0x0011d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18511     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG46_RESERVEDFIELD145                           (0xf<<0) // Reserved
18512     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG46_RESERVEDFIELD145_SHIFT                     0
18513     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG46_UNUSED_0                                   (0xf<<4) // reserved
18514     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG46_UNUSED_0_SHIFT                             4
18515 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119                                                         0x0011dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18516     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXP_MARGIN                                   (0xf<<0) // Value to minus/add from the calibrated txterm value
18517     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXP_MARGIN_SHIFT                             0
18518     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXN_MARGIN                                   (0xf<<4) // Value to minus/add from the calibrated txterm value
18519     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXN_MARGIN_SHIFT                             4
18520 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120                                                         0x0011e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18521     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_CMP                             (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
18522     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_CMP_SHIFT                       0
18523     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE                          (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
18524     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_SHIFT                    4
18525     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_UNUSED_0                                            (0x1<<7) // reserved
18526     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X120_UNUSED_0_SHIFT                                      7
18527 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121                                                         0x0011e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18528     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES                       (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
18529     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_SHIFT                 0
18530     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0                             (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
18531     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0_SHIFT                       4
18532     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0                             (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
18533     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0_SHIFT                       5
18534     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA                                   (0x1<<6) // enable override calibrated txterm value
18535     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA_SHIFT                             6
18536     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR                              (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
18537     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR_SHIFT                        7
18538 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122                                                         0x0011e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18539     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXP_OVR                                      (0xf<<0) // override calibrated txterm value
18540     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXP_OVR_SHIFT                                0
18541     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXN_OVR                                      (0xf<<4) // override calibrated txterm value
18542     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXN_OVR_SHIFT                                4
18543 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123                                                         0x0011ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18544     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0                                         (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
18545     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0_SHIFT                                   0
18546     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_RESERVEDFIELD146                                    (0x1<<1) // Reserved
18547     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_RESERVEDFIELD146_SHIFT                              1
18548     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_7_2                                       (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
18549     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_7_2_SHIFT                                 2
18550 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X124                                                         0x0011f0UL //Access:RW   DataWidth:0x8   Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]  Chips: K2
18551 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X125                                                         0x0011f4UL //Access:RW   DataWidth:0x8   Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode  Chips: K2
18552 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126                                                         0x0011f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18553     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O                                           (0x1<<0) // DFE block enable signal.
18554     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O_SHIFT                                     0
18555     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0                               (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
18556     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0_SHIFT                         1
18557     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3                            (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
18558     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3_SHIFT                      4
18559     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4                            (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
18560     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4_SHIFT                      5
18561     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5                            (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
18562     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5_SHIFT                      6
18563     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6                               (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
18564     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6_SHIFT                         7
18565 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X127                                                         0x0011fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18566     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X127_RXEQ_CONT_CAL_O_6_0                                 (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
18567     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X127_RXEQ_CONT_CAL_O_6_0_SHIFT                           0
18568     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X127_UNUSED_0                                            (0x1<<7) // reserved
18569     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X127_UNUSED_0_SHIFT                                      7
18570 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X128                                                         0x001200UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18571     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X128_RXEQ_INIT_CAL_O_6_0                                 (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
18572     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X128_RXEQ_INIT_CAL_O_6_0_SHIFT                           0
18573     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X128_UNUSED_0                                            (0x1<<7) // reserved
18574     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X128_UNUSED_0_SHIFT                                      7
18575 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130                                                         0x001208UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18576     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_ATT_START_O_3_0                          (0xf<<0) // ATT start value for rate1
18577     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_ATT_START_O_3_0_SHIFT                    0
18578     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_BOOST_START_O_3_0                        (0xf<<4) // Boost start value for rate1
18579     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_BOOST_START_O_3_0_SHIFT                  4
18580 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131                                                         0x00120cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18581     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_ATT_START_O_3_0                          (0xf<<0) // ATT start value for rate2
18582     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_ATT_START_O_3_0_SHIFT                    0
18583     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_BOOST_START_O_3_0                        (0xf<<4) // Boost start value for rate2
18584     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_BOOST_START_O_3_0_SHIFT                  4
18585 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X132                                                         0x001210UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18586     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X132_RXEQ_RATE2_TAP1_START_O_6_0                         (0x7f<<0) // DFE Tap1 start value for rate2
18587     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X132_RXEQ_RATE2_TAP1_START_O_6_0_SHIFT                   0
18588     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X132_UNUSED_0                                            (0x1<<7) // reserved
18589     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X132_UNUSED_0_SHIFT                                      7
18590 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X133                                                         0x001214UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18591     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X133_RXEQ_RATE2_TAP2_START_O_5_0                         (0x3f<<0) // DFE Tap2 start value for rate2
18592     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X133_RXEQ_RATE2_TAP2_START_O_5_0_SHIFT                   0
18593     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X133_UNUSED_0                                            (0x3<<6) // reserved
18594     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X133_UNUSED_0_SHIFT                                      6
18595 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X134                                                         0x001218UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18596     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X134_RXEQ_RATE2_TAP3_START_O_5_0                         (0x3f<<0) // DFE Tap3 start value for rate2
18597     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X134_RXEQ_RATE2_TAP3_START_O_5_0_SHIFT                   0
18598     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X134_UNUSED_0                                            (0x3<<6) // reserved
18599     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X134_UNUSED_0_SHIFT                                      6
18600 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X135                                                         0x00121cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18601     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X135_RXEQ_RATE2_TAP4_START_O_5_0                         (0x3f<<0) // DFE Tap4 start value for rate2
18602     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X135_RXEQ_RATE2_TAP4_START_O_5_0_SHIFT                   0
18603     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X135_UNUSED_0                                            (0x3<<6) // reserved
18604     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X135_UNUSED_0_SHIFT                                      6
18605 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X136                                                         0x001220UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18606     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X136_RXEQ_RATE2_TAP5_START_O_5_0                         (0x3f<<0) // DFE Tap5 start value for rate2
18607     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X136_RXEQ_RATE2_TAP5_START_O_5_0_SHIFT                   0
18608     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X136_UNUSED_0                                            (0x3<<6) // reserved
18609     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X136_UNUSED_0_SHIFT                                      6
18610 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137                                                         0x001224UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18611     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_ATT_START_O_3_0                          (0xf<<0) // ATT start value for rate3
18612     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_ATT_START_O_3_0_SHIFT                    0
18613     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_BOOST_START_O_3_0                        (0xf<<4) // Boost start value for rate3
18614     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_BOOST_START_O_3_0_SHIFT                  4
18615 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X138                                                         0x001228UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18616     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X138_RXEQ_RATE3_TAP1_START_O_6_0                         (0x7f<<0) // DFE Tap1 start value for rate3
18617     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X138_RXEQ_RATE3_TAP1_START_O_6_0_SHIFT                   0
18618     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X138_UNUSED_0                                            (0x1<<7) // reserved
18619     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X138_UNUSED_0_SHIFT                                      7
18620 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X139                                                         0x00122cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18621     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X139_RXEQ_RATE3_TAP2_START_O_5_0                         (0x3f<<0) // DFE Tap2 start value for rate3
18622     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X139_RXEQ_RATE3_TAP2_START_O_5_0_SHIFT                   0
18623     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X139_UNUSED_0                                            (0x3<<6) // reserved
18624     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X139_UNUSED_0_SHIFT                                      6
18625 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X140                                                         0x001230UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18626     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X140_RXEQ_RATE3_TAP3_START_O_5_0                         (0x3f<<0) // DFE Tap3 start value for rate3
18627     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X140_RXEQ_RATE3_TAP3_START_O_5_0_SHIFT                   0
18628     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X140_UNUSED_0                                            (0x3<<6) // reserved
18629     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X140_UNUSED_0_SHIFT                                      6
18630 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X141                                                         0x001234UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18631     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X141_RXEQ_RATE3_TAP4_START_O_5_0                         (0x3f<<0) // DFE Tap4 start value for rate3
18632     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X141_RXEQ_RATE3_TAP4_START_O_5_0_SHIFT                   0
18633     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X141_UNUSED_0                                            (0x3<<6) // reserved
18634     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X141_UNUSED_0_SHIFT                                      6
18635 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X142                                                         0x001238UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18636     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X142_RXEQ_RATE3_TAP5_START_O_5_0                         (0x3f<<0) // DFE Tap5 start value for rate3
18637     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X142_RXEQ_RATE3_TAP5_START_O_5_0_SHIFT                   0
18638     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X142_UNUSED_0                                            (0x3<<6) // reserved
18639     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X142_UNUSED_0_SHIFT                                      6
18640 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143                                                         0x00123cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18641     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS                           (0x1<<0) // Disable auto cal w/ rx_superbst
18642     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS_SHIFT                     0
18643     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O                                   (0xf<<1) // Max limit value for BOOST auto-calibration
18644     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O_SHIFT                             1
18645     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O                                (0x1<<5) // Enable Max limiting for BOOST auto-calibration
18646     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O_SHIFT                          5
18647     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RX_ATT_BOOST_CAL_O_1_0                              (0x3<<6) // rx_att_boost setting used during ATT calibration
18648     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X143_RX_ATT_BOOST_CAL_O_1_0_SHIFT                        6
18649 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144                                                         0x001240UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18650     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RX_ATT_BOOST_NORM_O_1_0                             (0x3<<0) // rx_att_boost setting used after ATT calibration
18651     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RX_ATT_BOOST_NORM_O_1_0_SHIFT                       0
18652     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O                                 (0x1<<2) // boost_adj_en
18653     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O_SHIFT                           2
18654     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O                                (0x1<<3) // boost_adj_dir
18655     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_SHIFT                          3
18656     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_VAL_O                                (0xf<<4) // boost_adj_val This register Is not bit reversed
18657     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_VAL_O_SHIFT                          4
18658 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145                                                         0x001244UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18659     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0                   (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
18660     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_SHIFT             0
18661     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O                                 (0x1<<7) // CMP Offset Noise Averaging Enable
18662     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O_SHIFT                           7
18663 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X146                                                         0x001248UL //Access:RW   DataWidth:0x8     Chips: K2
18664 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147                                                         0x00124cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18665     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_DFE_TAP_PD_WAIT_11_8                           (0xf<<0) //
18666     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_SHIFT                     0
18667     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_PMA_LN_DFE_OFS_CAL_ENA                              (0x3<<4) // DFE offset calibration enable
18668     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_PMA_LN_DFE_OFS_CAL_ENA_SHIFT                        4
18669     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS                           (0x1<<6) // Disable auto cal w/ rx_att_gain
18670     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_SHIFT                     6
18671     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O                           (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
18672     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O_SHIFT                     7
18673 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148                                                         0x001250UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18674     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_LOAD_EN_O_6_0                              (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
18675     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_LOAD_EN_O_6_0_SHIFT                        0
18676     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O                                       (0x1<<7) // Override enable for DFE signals.
18677     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O_SHIFT                                 7
18678 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149                                                         0x001254UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18679     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LOAD_O_6_0                                 (0x7f<<0) // Override for RXEQ_CTRL output register load value.
18680     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LOAD_O_6_0_SHIFT                           0
18681     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O                                    (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
18682     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O_SHIFT                              7
18683 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150                                                         0x001258UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18684     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0                          (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
18685     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_SHIFT                    0
18686     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR                                   (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
18687     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR_SHIFT                             3
18688     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR                               (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
18689     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR_SHIFT                         5
18690     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6                      (0x1<<6) // DFE TAP CMP no offset override enable
18691     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_SHIFT                6
18692     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7                                  (0x1<<7) // DFE TAP override enable
18693     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7_SHIFT                            7
18694 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151                                                         0x00125cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18695     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3                     (0x1f<<0) // DFE offset calibration TAP enable override
18696     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_SHIFT               0
18697     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0                       (0x1<<5) // DFE offset calibrated value override enable
18698     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_SHIFT                 5
18699     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1                           (0x1<<6) // DFE offset cal enable override
18700     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1_SHIFT                     6
18701     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2                              (0x1<<7) // DFE comparator cal enable override
18702     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2_SHIFT                        7
18703 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X152                                                         0x001260UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18704     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X152_DFE_TAP1_OVR_VAL_O_6_0                              (0x7f<<0) // DFE Tap 1 Override Value
18705     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X152_DFE_TAP1_OVR_VAL_O_6_0_SHIFT                        0
18706     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X152_RESERVEDFIELD147                                    (0x1<<7) // Reserved
18707     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X152_RESERVEDFIELD147_SHIFT                              7
18708 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X153                                                         0x001264UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18709     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X153_DFE_TAP2_OVR_VAL_O_5_0                              (0x3f<<0) // DFE Tap 2 Override Value
18710     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X153_DFE_TAP2_OVR_VAL_O_5_0_SHIFT                        0
18711     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X153_RESERVEDFIELD148                                    (0x3<<6) // Reserved
18712     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X153_RESERVEDFIELD148_SHIFT                              6
18713 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X154                                                         0x001268UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18714     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X154_DFE_TAP3_OVR_VAL_O_5_0                              (0x3f<<0) // DFE Tap 3 Override Value
18715     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X154_DFE_TAP3_OVR_VAL_O_5_0_SHIFT                        0
18716     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X154_RESERVEDFIELD149                                    (0x3<<6) // Reserved
18717     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X154_RESERVEDFIELD149_SHIFT                              6
18718 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X155                                                         0x00126cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18719     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X155_DFE_TAP4_OVR_VAL_O_5_0                              (0x3f<<0) // DFE Tap 4 Override Value
18720     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X155_DFE_TAP4_OVR_VAL_O_5_0_SHIFT                        0
18721     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X155_RESERVEDFIELD150                                    (0x3<<6) // Reserved
18722     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X155_RESERVEDFIELD150_SHIFT                              6
18723 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X156                                                         0x001270UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18724     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X156_DFE_TAP5_OVR_VAL_O_5_0                              (0x3f<<0) // DFE Tap 5 Override Value
18725     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X156_DFE_TAP5_OVR_VAL_O_5_0_SHIFT                        0
18726     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X156_UNUSED_0                                            (0x3<<6) // reserved
18727     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X156_UNUSED_0_SHIFT                                      6
18728 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X158                                                         0x001278UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
18729     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X158_UNUSED_0                                            (0x3<<0) // reserved
18730     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X158_UNUSED_0_SHIFT                                      0
18731     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X158_RESERVEDFIELD151                                    (0x1f<<2) // Reserved
18732     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X158_RESERVEDFIELD151_SHIFT                              2
18733     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X158_UNUSED_1                                            (0x1<<7) // reserved
18734     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X158_UNUSED_1_SHIFT                                      7
18735 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X159                                                         0x00127cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
18736     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X159_UNUSED_0                                            (0x3<<0) // reserved
18737     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X159_UNUSED_0_SHIFT                                      0
18738     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X159_RESERVEDFIELD152                                    (0x3f<<2) // Reserved
18739     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X159_RESERVEDFIELD152_SHIFT                              2
18740 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X161                                                         0x001284UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
18741     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X161_UNUSED_0                                            (0x3<<0) // reserved
18742     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X161_UNUSED_0_SHIFT                                      0
18743     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X161_RESERVEDFIELD153                                    (0x3f<<2) // Reserved
18744     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X161_RESERVEDFIELD153_SHIFT                              2
18745 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167                                                         0x00129cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18746     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7                               (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
18747     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7_SHIFT                         0
18748     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167_UNUSED_0                                            (0x7f<<1) // reserved
18749     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X167_UNUSED_0_SHIFT                                      1
18750 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201                                                         0x001324UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18751     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0                                         (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
18752     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0_SHIFT                                   0
18753     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0                                  (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
18754     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0_SHIFT                            1
18755     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0                               (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
18756     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0_SHIFT                         3
18757     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_RATE_OV_O_2_0                                  (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
18758     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X201_CDFE_RATE_OV_O_2_0_SHIFT                            5
18759 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X202                                                         0x001328UL //Access:RW   DataWidth:0x8     Chips: K2
18760 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203                                                         0x00132cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18761     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_RESERVEDFIELD154                                    (0xf<<0) // Reserved
18762     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_RESERVEDFIELD154_SHIFT                              0
18763     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO                                             (0x1<<4) //
18764     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO_SHIFT                                       4
18765     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL                                   (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
18766     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL_SHIFT                             5
18767     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL                             (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
18768     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL_SHIFT                       6
18769     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL                                 (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
18770     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL_SHIFT                           7
18771 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204                                                         0x001330UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18772     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL                                    (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
18773     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL_SHIFT                              0
18774     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL                        (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
18775     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_SHIFT                  1
18776     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL                         (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
18777     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_SHIFT                   2
18778     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN                                (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
18779     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN_SHIFT                          3
18780     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN                                (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
18781     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN_SHIFT                          4
18782     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_UNUSED_0                                            (0x7<<5) // reserved
18783     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X204_UNUSED_0_SHIFT                                      5
18784 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X205                                                         0x001334UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
18785 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X206                                                         0x001338UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
18786 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X207                                                         0x00133cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
18787 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208                                                         0x001340UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18788     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_RESERVEDFIELD155                                    (0x7f<<0) // Reserved
18789     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_RESERVEDFIELD155_SHIFT                              0
18790     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN                           (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
18791     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_SHIFT                     7
18792 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG47                                                0x001344UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18793 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG48                                                0x001348UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18794 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG49                                                0x00134cUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18795 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG50                                                0x001350UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18796 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X213                                                         0x001354UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
18797 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X214                                                         0x001358UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
18798 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X215                                                         0x00135cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
18799 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X216                                                         0x001360UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
18800 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X217                                                         0x001364UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
18801 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG51                                                0x001368UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18802 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG52                                                0x00136cUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
18803 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X220                                                         0x001370UL //Access:RW   DataWidth:0x8   Start value for dlev_ref.  Chips: K2
18804 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X221                                                         0x001374UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18805     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0              (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
18806     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT        0
18807     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X221_RESERVEDFIELD162                                    (0x7<<5) // Reserved
18808     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X221_RESERVEDFIELD162_SHIFT                              5
18809 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X222                                                         0x001378UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18810     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0          (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
18811     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT    0
18812     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X222_RESERVEDFIELD163                                    (0x7<<5) // Reserved
18813     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X222_RESERVEDFIELD163_SHIFT                              5
18814 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X223                                                         0x00137cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18815     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X223_AHB_CDFE_CMP1_TAP1_OFFSET                           (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
18816     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X223_AHB_CDFE_CMP1_TAP1_OFFSET_SHIFT                     0
18817     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X223_UNUSED_0                                            (0x1<<7) // reserved
18818     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X223_UNUSED_0_SHIFT                                      7
18819 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X224                                                         0x001380UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18820     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0                       (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
18821     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_SHIFT                 0
18822     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X224_UNUSED_0                                            (0x3<<6) // reserved
18823     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X224_UNUSED_0_SHIFT                                      6
18824 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X225                                                         0x001384UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18825     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0                       (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
18826     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_SHIFT                 0
18827     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X225_UNUSED_0                                            (0x3<<6) // reserved
18828     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X225_UNUSED_0_SHIFT                                      6
18829 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X226                                                         0x001388UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18830     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0                       (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
18831     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_SHIFT                 0
18832     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X226_UNUSED_0                                            (0x3<<6) // reserved
18833     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X226_UNUSED_0_SHIFT                                      6
18834 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X227                                                         0x00138cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18835     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X227_AHB_CDFE_CMP1_TAP5_OFFSET                           (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
18836     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X227_AHB_CDFE_CMP1_TAP5_OFFSET_SHIFT                     0
18837     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X227_UNUSED_0                                            (0x3<<6) // reserved
18838     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X227_UNUSED_0_SHIFT                                      6
18839 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X228                                                         0x001390UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18840     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X228_AHB_CDFE_CMP2_TAP1_OFFSET                           (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
18841     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X228_AHB_CDFE_CMP2_TAP1_OFFSET_SHIFT                     0
18842     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X228_UNUSED_0                                            (0x1<<7) // reserved
18843     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X228_UNUSED_0_SHIFT                                      7
18844 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X229                                                         0x001394UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18845     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0                       (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
18846     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_SHIFT                 0
18847     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X229_UNUSED_0                                            (0x3<<6) // reserved
18848     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X229_UNUSED_0_SHIFT                                      6
18849 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X230                                                         0x001398UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18850     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0                       (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
18851     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_SHIFT                 0
18852     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X230_UNUSED_0                                            (0x3<<6) // reserved
18853     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X230_UNUSED_0_SHIFT                                      6
18854 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X231                                                         0x00139cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18855     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0                       (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
18856     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_SHIFT                 0
18857     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X231_UNUSED_0                                            (0x3<<6) // reserved
18858     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X231_UNUSED_0_SHIFT                                      6
18859 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X232                                                         0x0013a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18860     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X232_AHB_CDFE_CMP2_TAP5_OFFSET                           (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
18861     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X232_AHB_CDFE_CMP2_TAP5_OFFSET_SHIFT                     0
18862     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X232_UNUSED_0                                            (0x3<<6) // reserved
18863     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X232_UNUSED_0_SHIFT                                      6
18864 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X233                                                         0x0013a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18865     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X233_AHB_CDFE_CMP3_TAP1_OFFSET                           (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
18866     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X233_AHB_CDFE_CMP3_TAP1_OFFSET_SHIFT                     0
18867     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X233_UNUSED_0                                            (0x1<<7) // reserved
18868     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X233_UNUSED_0_SHIFT                                      7
18869 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X234                                                         0x0013a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18870     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0                       (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
18871     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_SHIFT                 0
18872     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X234_UNUSED_0                                            (0x3<<6) // reserved
18873     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X234_UNUSED_0_SHIFT                                      6
18874 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X235                                                         0x0013acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18875     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0                       (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
18876     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_SHIFT                 0
18877     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X235_UNUSED_0                                            (0x3<<6) // reserved
18878     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X235_UNUSED_0_SHIFT                                      6
18879 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X236                                                         0x0013b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18880     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0                       (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
18881     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_SHIFT                 0
18882     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X236_UNUSED_0                                            (0x3<<6) // reserved
18883     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X236_UNUSED_0_SHIFT                                      6
18884 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X237                                                         0x0013b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18885     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X237_AHB_CDFE_CMP3_TAP5_OFFSET                           (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
18886     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X237_AHB_CDFE_CMP3_TAP5_OFFSET_SHIFT                     0
18887     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X237_UNUSED_0                                            (0x3<<6) // reserved
18888     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X237_UNUSED_0_SHIFT                                      6
18889 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X238                                                         0x0013b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18890     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X238_AHB_CDFE_CMP4_TAP1_OFFSET                           (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
18891     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X238_AHB_CDFE_CMP4_TAP1_OFFSET_SHIFT                     0
18892     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X238_UNUSED_0                                            (0x1<<7) // reserved
18893     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X238_UNUSED_0_SHIFT                                      7
18894 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X239                                                         0x0013bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18895     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0                       (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
18896     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_SHIFT                 0
18897     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X239_UNUSED_0                                            (0x3<<6) // reserved
18898     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X239_UNUSED_0_SHIFT                                      6
18899 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X240                                                         0x0013c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18900     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0                       (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
18901     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_SHIFT                 0
18902     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X240_UNUSED_0                                            (0x3<<6) // reserved
18903     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X240_UNUSED_0_SHIFT                                      6
18904 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X241                                                         0x0013c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18905     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0                       (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
18906     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_SHIFT                 0
18907     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X241_UNUSED_0                                            (0x3<<6) // reserved
18908     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X241_UNUSED_0_SHIFT                                      6
18909 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X242                                                         0x0013c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18910     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X242_AHB_CDFE_CMP4_TAP5_OFFSET                           (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
18911     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X242_AHB_CDFE_CMP4_TAP5_OFFSET_SHIFT                     0
18912     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X242_UNUSED_0                                            (0x3<<6) // reserved
18913     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X242_UNUSED_0_SHIFT                                      6
18914 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X243                                                         0x0013ccUL //Access:RW   DataWidth:0x8   Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]  Chips: K2
18915 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X244                                                         0x0013d0UL //Access:RW   DataWidth:0x8   Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]  Chips: K2
18916 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X245                                                         0x0013d4UL //Access:RW   DataWidth:0x8   Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]  Chips: K2
18917 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X246                                                         0x0013d8UL //Access:RW   DataWidth:0x8   Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]  Chips: K2
18918 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X247                                                         0x0013dcUL //Access:RW   DataWidth:0x8     Chips: K2
18919 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248                                                         0x0013e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18920     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8                          (0x3<<0) //
18921     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8_SHIFT                    0
18922     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT                        (0xf<<2) //
18923     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_SHIFT                  2
18924     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_UNUSED_0                                            (0x3<<6) // reserved
18925     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X248_UNUSED_0_SHIFT                                      6
18926 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249                                                         0x0013e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18927     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_ERR_SMPL_SHIFT                             (0xf<<0) //
18928     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_ERR_SMPL_SHIFT_SHIFT                       0
18929     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN                             (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
18930     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN_SHIFT                       4
18931     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_UNUSED_0                                            (0x7<<5) // reserved
18932     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X249_UNUSED_0_SHIFT                                      5
18933 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250                                                         0x0013e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18934     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8                   (0x1<<0) //
18935     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_SHIFT             0
18936     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8                  (0x1<<1) //
18937     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_SHIFT            1
18938     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8                   (0x1<<2) //
18939     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_SHIFT             2
18940     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8                  (0x1<<3) //
18941     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_SHIFT            3
18942     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_UNUSED_0                                            (0xf<<4) // reserved
18943     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X250_UNUSED_0_SHIFT                                      4
18944 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X251                                                         0x0013ecUL //Access:RW   DataWidth:0x8     Chips: K2
18945 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X252                                                         0x0013f0UL //Access:RW   DataWidth:0x8     Chips: K2
18946 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X253                                                         0x0013f4UL //Access:RW   DataWidth:0x8     Chips: K2
18947 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X254                                                         0x0013f8UL //Access:RW   DataWidth:0x8     Chips: K2
18948 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255                                                         0x0013fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18949     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN                                      (0x1<<0) // Override enable for CDFE calibration direction
18950     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN_SHIFT                                0
18951     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL                                     (0x1<<1) // Override value for CDFE calibration direction
18952     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL_SHIFT                               1
18953     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O                          (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
18954     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O_SHIFT                    2
18955     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O                           (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
18956     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_SHIFT                     3
18957     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O                             (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
18958     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O_SHIFT                       4
18959     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O                             (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
18960     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O_SHIFT                       5
18961     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O                         (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
18962     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_SHIFT                   6
18963     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_UNUSED_0                                            (0x1<<7) // reserved
18964     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X255_UNUSED_0_SHIFT                                      7
18965 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X256                                                         0x001400UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK90.  Chips: K2
18966 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257                                                         0x001404UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18967     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8                      (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
18968     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_SHIFT                0
18969     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0              (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
18970     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_SHIFT        1
18971 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X258                                                         0x001408UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK270.  Chips: K2
18972 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259                                                         0x00140cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18973     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8                     (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
18974     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_SHIFT               0
18975     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN                                 (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
18976     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN_SHIFT                           1
18977     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0                   (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
18978     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_SHIFT             2
18979     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8              (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
18980     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_SHIFT        7
18981 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X260                                                         0x001410UL //Access:RW   DataWidth:0x8   Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value  Chips: K2
18982 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X261                                                         0x001414UL //Access:RW   DataWidth:0x8   cdfe dlevn overwrite value.  Chips: K2
18983 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X262                                                         0x001418UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18984     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X262_AHB_CDFE_TAP_OV_EN                                  (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
18985     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X262_AHB_CDFE_TAP_OV_EN_SHIFT                            0
18986     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X262_UNUSED_0                                            (0x7<<5) // reserved
18987     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X262_UNUSED_0_SHIFT                                      5
18988 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X263                                                         0x00141cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18989     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X263_AHB_CDFE_TAP1_OV                                    (0x7f<<0) // cdfe tap1 overwrite value
18990     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X263_AHB_CDFE_TAP1_OV_SHIFT                              0
18991     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X263_UNUSED_0                                            (0x1<<7) // reserved
18992     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X263_UNUSED_0_SHIFT                                      7
18993 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X264                                                         0x001420UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18994     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X264_AHB_CDFE_TAP2_OV                                    (0x3f<<0) // cdfe tap2 overwrite value
18995     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X264_AHB_CDFE_TAP2_OV_SHIFT                              0
18996     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X264_UNUSED_0                                            (0x3<<6) // reserved
18997     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X264_UNUSED_0_SHIFT                                      6
18998 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X265                                                         0x001424UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
18999     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X265_AHB_CDFE_TAP3_OV                                    (0x3f<<0) // cdfe tap3 overwrite value
19000     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X265_AHB_CDFE_TAP3_OV_SHIFT                              0
19001     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X265_UNUSED_0                                            (0x3<<6) // reserved
19002     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X265_UNUSED_0_SHIFT                                      6
19003 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X266                                                         0x001428UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19004     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X266_AHB_CDFE_TAP4_OV                                    (0x3f<<0) // cdfe tap4 overwrite value
19005     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X266_AHB_CDFE_TAP4_OV_SHIFT                              0
19006     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X266_UNUSED_0                                            (0x3<<6) // reserved
19007     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X266_UNUSED_0_SHIFT                                      6
19008 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267                                                         0x00142cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19009     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_AHB_CDFE_TAP5_OV                                    (0x3f<<0) // cdfe tap5 overwrite value
19010     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_AHB_CDFE_TAP5_OV_SHIFT                              0
19011     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_RESERVEDFIELD164                                    (0x1<<6) // Reserved
19012     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_RESERVEDFIELD164_SHIFT                              6
19013     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O              (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
19014     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_SHIFT        7
19015 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268                                                         0x001430UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19016     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O                      (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
19017     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_SHIFT                0
19018     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O            (0x1<<1) //
19019     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_SHIFT      1
19020     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O        (0x1<<2) //
19021     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_SHIFT  2
19022     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_RESERVEDFIELD165                                    (0xf<<3) // Reserved
19023     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_RESERVEDFIELD165_SHIFT                              3
19024     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O                           (0x1<<7) //
19025     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_SHIFT                     7
19026 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269                                                         0x001434UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19027     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O                    (0x1<<0) //
19028     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_SHIFT              0
19029     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O                                (0x1<<1) //
19030     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_SHIFT                          1
19031     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_CMP_ENA_O                                  (0xf<<2) //
19032     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_CMP_ENA_O_SHIFT                            2
19033     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_UNUSED_0                                            (0x3<<6) // reserved
19034     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X269_UNUSED_0_SHIFT                                      6
19035 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X270                                                         0x001438UL //Access:RW   DataWidth:0x8     Chips: K2
19036 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271                                                         0x00143cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19037     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0                         (0x1f<<0) //
19038     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_SHIFT                   0
19039     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O                 (0x1<<5) // Forces the positive dlev training pattern to be used
19040     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_SHIFT           5
19041     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O                 (0x1<<6) // Forces the negative dlev training pattern to be used
19042     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_SHIFT           6
19043     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_RESERVEDFIELD166                                    (0x1<<7) // Reserved
19044     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X271_RESERVEDFIELD166_SHIFT                              7
19045 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272                                                         0x001440UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19046     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SCALE_O_2_0                               (0x7<<0) // Scale factor CDFE TAP1 adapted value
19047     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SCALE_O_2_0_SHIFT                         0
19048     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0                               (0x1f<<3) // Shift factor CDFE TAP1 adapted value
19049     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0_SHIFT                         3
19050 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273                                                         0x001444UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19051     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SCALE_O_2_0                               (0x7<<0) // Scale factor CDFE TAP2 adapted value
19052     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SCALE_O_2_0_SHIFT                         0
19053     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0                               (0x1f<<3) // Shift factor CDFE TAP2 adapted value
19054     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0_SHIFT                         3
19055 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274                                                         0x001448UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19056     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SCALE_O_2_0                               (0x7<<0) // Scale factor CDFE TAP3 adapted value
19057     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SCALE_O_2_0_SHIFT                         0
19058     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0                               (0x1f<<3) // Shift factor CDFE TAP3 adapted value
19059     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0_SHIFT                         3
19060 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275                                                         0x00144cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19061     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SCALE_O_2_0                               (0x7<<0) // Scale factor CDFE TAP4 adapted value
19062     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SCALE_O_2_0_SHIFT                         0
19063     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0                               (0x1f<<3) // Shift factor CDFE TAP4 adapted value
19064     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0_SHIFT                         3
19065 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276                                                         0x001450UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19066     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SCALE_O_2_0                               (0x7<<0) // Scale factor CDFE TAP5 adapted value
19067     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SCALE_O_2_0_SHIFT                         0
19068     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0                               (0x1f<<3) // Shift factor CDFE TAP5 adapted value
19069     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0_SHIFT                         3
19070 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277                                                         0x001454UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19071     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_RA_OVR_O                               (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
19072     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_RA_OVR_O_SHIFT                         0
19073     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_P2S_OVR_O                              (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
19074     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_P2S_OVR_O_SHIFT                        2
19075     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREGH_OVR_O                           (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
19076     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREGH_OVR_O_SHIFT                     4
19077     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREG_OVR_O                            (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
19078     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREG_OVR_O_SHIFT                      6
19079 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278                                                         0x001458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19080     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_CDR_OVR_O                              (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
19081     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_CDR_OVR_O_SHIFT                        0
19082     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_DFE_OVR_O                              (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
19083     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_DFE_OVR_O_SHIFT                        2
19084     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_LNREGH_OVR_O                              (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
19085     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_LNREGH_OVR_O_SHIFT                        4
19086     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_VCO_BUF_OVR_O                             (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
19087     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_VCO_BUF_OVR_O_SHIFT                       6
19088 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279                                                         0x00145cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19089     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_CDR_GCRX_OVR_O                         (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
19090     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_SHIFT                   0
19091     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RXGATE_EN_OVR_O                              (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
19092     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RXGATE_EN_OVR_O_SHIFT                        2
19093     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_VCO_OVR_O                              (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
19094     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_VCO_OVR_O_SHIFT                        4
19095     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_IDDQ_SD_OVR_O                                (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
19096     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_IDDQ_SD_OVR_O_SHIFT                          6
19097 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280                                                         0x001460UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19098     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_OVR_O                                 (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
19099     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_OVR_O_SHIFT                           0
19100     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_BIAS_OVR_O                            (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
19101     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_BIAS_OVR_O_SHIFT                      2
19102     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O                          (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
19103     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_SHIFT                    4
19104     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O                        (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
19105     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_SHIFT                  6
19106 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281                                                         0x001464UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19107     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_TXREG_OVR_O                               (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
19108     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_TXREG_OVR_O_SHIFT                         0
19109     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_LNREG_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
19110     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_LNREG_OVR_O_SHIFT                         2
19111     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_P2S_OVR_O                                 (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
19112     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_P2S_OVR_O_SHIFT                           4
19113     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_RA_OVR_O                                  (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
19114     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_RA_OVR_O_SHIFT                            6
19115 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282                                                         0x001468UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19116     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_RESERVEDFIELD167                                    (0x3<<0) // Reserved
19117     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_RESERVEDFIELD167_SHIFT                              0
19118     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_SLV_BIAS_OVR_O                            (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
19119     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_SLV_BIAS_OVR_O_SHIFT                      2
19120     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_TXDRV_OVR_O                               (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
19121     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_TXDRV_OVR_O_SHIFT                         4
19122     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_VCO_OVR_O                                 (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
19123     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_VCO_OVR_O_SHIFT                           6
19124 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283                                                         0x00146cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19125     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_CDR_EN_OVR_O                                 (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
19126     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_CDR_EN_OVR_O_SHIFT                           0
19127     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RESET_S2P_OVR_O                              (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
19128     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RESET_S2P_OVR_O_SHIFT                        2
19129     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RXCLK_EN_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
19130     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RXCLK_EN_OVR_O_SHIFT                         4
19131     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_WORD_OVR_O                                   (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
19132     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_WORD_OVR_O_SHIFT                             6
19133 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284                                                         0x001470UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19134     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RATE_OVR_O                                   (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
19135     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RATE_OVR_O_SHIFT                             0
19136     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O                               (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
19137     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O_SHIFT                         3
19138     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O                        (0x3<<6) // Not currently used
19139     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_SHIFT                  6
19140 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X285                                                         0x001474UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19141     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X285_LN_MSM_TXVCODIV_OVR_O                               (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
19142     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X285_LN_MSM_TXVCODIV_OVR_O_SHIFT                         0
19143     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X285_UNUSED_0                                            (0x1f<<3) // reserved
19144     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X285_UNUSED_0_SHIFT                                      3
19145 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301                                                         0x0014b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19146     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O                                            (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
19147     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O_SHIFT                                      0
19148     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O                                         (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
19149     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O_SHIFT                                   1
19150     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O                                         (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
19151     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O_SHIFT                                   2
19152     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O                                        (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
19153     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O_SHIFT                                  3
19154     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_DMUX_TXA_SEL_O_1_0                                  (0x3<<4) // Transmit mux A data input select.
19155     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_DMUX_TXA_SEL_O_1_0_SHIFT                            4
19156     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O                                  (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
19157     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O_SHIFT                            6
19158     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_UNUSED_0                                            (0x1<<7) // reserved
19159     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X301_UNUSED_0_SHIFT                                      7
19160 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302                                                         0x0014b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19161     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O                                         (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
19162     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O_SHIFT                                   0
19163     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O                                         (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
19164     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O_SHIFT                                   1
19165     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O                                        (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
19166     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O_SHIFT                                  2
19167     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O                                          (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
19168     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O_SHIFT                                    3
19169     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O                                          (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
19170     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O_SHIFT                                    4
19171     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O                                         (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
19172     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O_SHIFT                                   5
19173     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O                                          (0x1<<6) // Used as Reg0 polarity select
19174     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O_SHIFT                                    6
19175     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_UNUSED_0                                            (0x1<<7) // reserved
19176     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X302_UNUSED_0_SHIFT                                      7
19177 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303                                                         0x0014bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19178     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O                                          (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
19179     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O_SHIFT                                    0
19180     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O                                         (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
19181     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O_SHIFT                                   1
19182     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_DMUX_TXB_SEL_O_2_0                                  (0x7<<2) // Transmit mux B data input select enable.
19183     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_DMUX_TXB_SEL_O_2_0_SHIFT                            2
19184     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24                                        (0x1<<5) // Bit 24: txdrv_c2_in[3]
19185     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24_SHIFT                                  5
19186     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O                                     (0x1<<6) // Enable bit for width_chng module
19187     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O_SHIFT                               6
19188     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O                                 (0x1<<7) // Txterm calibration enable
19189     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O_SHIFT                           7
19190 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304                                                         0x0014c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19191     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_TXTERM_CAL_RSEL                                     (0x7<<0) // tx termination calibration comparator threshold select
19192     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_TXTERM_CAL_RSEL_SHIFT                               0
19193     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O                                (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2?b00: no bit stripping 2?b01: 2x bit stripping 2?b10: reserved 2?b11: 4x bit stripping
19194     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O_SHIFT                          3
19195     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_MAC_WIDTH_O                                     (0x3<<5) // Data width selector for PCS/MAC interface. 2?b00: GigE or XAUI 2?b01: GigE or XAUI 2?b10: RXAUI 2?b11: XFI
19196     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_AHB_MAC_WIDTH_O_SHIFT                               5
19197     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_UNUSED_0                                            (0x1<<7) // reserved
19198     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X304_UNUSED_0_SHIFT                                      7
19199 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305                                                         0x0014c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19200     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_AHB_TXMAC_THRESHOLD_O                               (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
19201     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_AHB_TXMAC_THRESHOLD_O_SHIFT                         0
19202     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_AHB_LN_TXBIT_REPEAT_O                               (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2?b00: no bit stuffing nor stripping 2?b01: 2x bit stuffing and stripping 2?b10: reserved 2?b11: 4x bit stuffing and stripping
19203     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_AHB_LN_TXBIT_REPEAT_O_SHIFT                         2
19204     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_MODE_8B_O_1_0                                       (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
19205     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_MODE_8B_O_1_0_SHIFT                                 4
19206     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O                                            (0x1<<6) // 8b/10b encoder enable.
19207     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O_SHIFT                                      6
19208     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O                                            (0x1<<7) // 8b/10b decoder enable.
19209     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O_SHIFT                                      7
19210 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X306                                                         0x0014c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19211     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X306_AHB_TX_CDAC_OVR                                     (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
19212     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X306_AHB_TX_CDAC_OVR_SHIFT                               0
19213     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X306_UNUSED_0                                            (0xf<<4) // reserved
19214     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X306_UNUSED_0_SHIFT                                      4
19215 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307                                                         0x0014ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19216     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_UNUSED_0                                            (0x1f<<0) // reserved
19217     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_UNUSED_0_SHIFT                                      0
19218     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O                                           (0x1<<5) // PIPE interface block enable.
19219     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O_SHIFT                                     5
19220     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O                                          (0x1<<6) // SAPIS interface block enable.
19221     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O_SHIFT                                    6
19222     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE                                            (0x1<<7) // Signal Detect USB mode enable
19223     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE_SHIFT                                      7
19224 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308                                                         0x0014d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19225     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_RESERVEDFIELD168                                    (0x1<<0) // Reserved
19226     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_RESERVEDFIELD168_SHIFT                              0
19227     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_UNUSED_0                                            (0x1<<1) // reserved
19228     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_UNUSED_0_SHIFT                                      1
19229     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_RESERVEDFIELD169                                    (0x1<<2) // Reserved
19230     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_RESERVEDFIELD169_SHIFT                              2
19231     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_UNUSED_1                                            (0x1f<<3) // reserved
19232     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X308_UNUSED_1_SHIFT                                      3
19233 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X310                                                         0x0014d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19234     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X310_UNUSED_0                                            (0xf<<0) // reserved
19235     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X310_UNUSED_0_SHIFT                                      0
19236     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X310_RESERVEDFIELD170                                    (0x1<<4) // Reserved
19237     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X310_RESERVEDFIELD170_SHIFT                              4
19238     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X310_UNUSED_1                                            (0x7<<5) // reserved
19239     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X310_UNUSED_1_SHIFT                                      5
19240 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG53                                                0x0014e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19241     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG53_RESERVEDFIELD171                           (0x1<<0) // Reserved
19242     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG53_RESERVEDFIELD171_SHIFT                     0
19243     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG53_RESERVEDFIELD172                           (0x1<<1) // Reserved
19244     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG53_RESERVEDFIELD172_SHIFT                     1
19245     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG53_UNUSED_0                                   (0x3f<<2) // reserved
19246     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG53_UNUSED_0_SHIFT                             2
19247 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314                                                         0x0014e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19248     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC                                 (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
19249     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC_SHIFT                           0
19250     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O                                     (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
19251     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O_SHIFT                               1
19252     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O                                    (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
19253     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O_SHIFT                              2
19254     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0                          (0x1<<3) // Receive amplifier powerdown override, when cisel is high
19255     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_SHIFT                    3
19256     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_UNUSED_0                                            (0xf<<4) // reserved
19257     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X314_UNUSED_0_SHIFT                                      4
19258 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X315                                                         0x0014ecUL //Access:RW   DataWidth:0x8   Delays the beacon_ena propagation to PMA  Chips: K2
19259 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X316                                                         0x0014f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19260     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_O_11_8              (0xf<<0) // Delays the beacon_ena propagation to PMA
19261     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_O_11_8_SHIFT        0
19262     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X316_UNUSED_0                                            (0xf<<4) // reserved
19263     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X316_UNUSED_0_SHIFT                                      4
19264 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317                                                         0x0014f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19265     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O                            (0x1<<0) // Beacon Override Enable
19266     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O_SHIFT                      0
19267     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O                                (0x1<<1) // Beacon Override
19268     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O_SHIFT                          1
19269     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O                                        (0x1<<2) // Enables 16b/20b decoder
19270     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O_SHIFT                                  2
19271     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O                                        (0x1<<3) // Enables 16b/20b encoder
19272     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O_SHIFT                                  3
19273     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_REGP_OVR_3_0                                        (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
19274     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X317_REGP_OVR_3_0_SHIFT                                  4
19275 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318                                                         0x0014f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19276     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_SIGDET_OVR_O_1_0                                    (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
19277     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_SIGDET_OVR_O_1_0_SHIFT                              0
19278     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_LN_OUT_OVR_1_0                                      (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
19279     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_LN_OUT_OVR_1_0_SHIFT                                2
19280     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_RXEQ_SIGDET_1_0                                     (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
19281     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_RXEQ_SIGDET_1_0_SHIFT                               4
19282     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_UNUSED_0                                            (0x3<<6) // reserved
19283     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X318_UNUSED_0_SHIFT                                      6
19284 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319                                                         0x0014fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19285     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_TXDETECTRX_OVR_O_1_0                                (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
19286     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_TXDETECTRX_OVR_O_1_0_SHIFT                          0
19287     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_RXDET_STATUS_OVR_O_1_0                              (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
19288     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_RXDET_STATUS_OVR_O_1_0_SHIFT                        2
19289     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_LOCKED_OVR_O_1_0                                    (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
19290     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_LOCKED_OVR_O_1_0_SHIFT                              4
19291     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O                    (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
19292     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_SHIFT              6
19293     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O                        (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
19294     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_SHIFT                  7
19295 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X320                                                         0x001500UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
19296 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X321                                                         0x001504UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
19297 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X322                                                         0x001508UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
19298 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X323                                                         0x00150cUL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
19299 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X324                                                         0x001510UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
19300 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X325                                                         0x001514UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
19301 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326                                                         0x001518UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19302     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48                                      (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
19303     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48_SHIFT                                0
19304     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O                            (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
19305     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O_SHIFT                      1
19306     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_UNUSED_0                                            (0xf<<2) // reserved
19307     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_UNUSED_0_SHIFT                                      2
19308     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN                                          (0x1<<6) // OOB detect enable
19309     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN_SHIFT                                    6
19310     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49                                      (0x1<<7) // OOB detect enable
19311     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49_SHIFT                                7
19312 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X327                                                         0x00151cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19313     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X327_CDR_CTRL_DLY_DLPF_EN_O                              (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
19314     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X327_CDR_CTRL_DLY_DLPF_EN_O_SHIFT                        0
19315     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X327_UNUSED_0                                            (0x7<<5) // reserved
19316     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X327_UNUSED_0_SHIFT                                      5
19317 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG54                                                0x001520UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
19318 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG55                                                0x001524UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19319     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG55_RESERVEDFIELD174                           (0x3f<<0) // Reserved
19320     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG55_RESERVEDFIELD174_SHIFT                     0
19321     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG55_UNUSED_0                                   (0x3<<6) // reserved
19322     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_RESERVEDREG55_UNUSED_0_SHIFT                             6
19323 #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330                                                         0x001528UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19324     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0                    (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
19325     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_SHIFT              0
19326     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50                                      (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
19327     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50_SHIFT                                3
19328     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_UNUSED_0                                            (0xf<<4) // reserved
19329     #define PHY_SGMII_IP_REG_AHB_LANE_CSR_1_X330_UNUSED_0_SHIFT                                      4
19330 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0                                                        0x002800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19331     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O                                     (0x1<<0) // Lane Reference Clock Enable.  0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - gcfsm_refmux_clk = lane_ref_clk
19332     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O_SHIFT                               0
19333     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0_UNUSED_0                                           (0x7f<<1) // reserved
19334     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X0_UNUSED_0_SHIFT                                     1
19335 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1                                                        0x002804UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19336     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O                                (0x1<<0) // Enable/Disable the internal PRBS data pattern inverter. 0x0 ? Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 ? Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
19337     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O_SHIFT                          0
19338     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O                                (0x1<<1) // Enable/Disable the internal PRBS data pattern inverter. 0x0 ? Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 ? Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
19339     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O_SHIFT                          1
19340     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_RESERVEDFIELD32                                    (0x1<<2) // Reserved
19341     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_RESERVEDFIELD32_SHIFT                              2
19342     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_UNUSED_0                                           (0x1f<<3) // reserved
19343     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X1_UNUSED_0_SHIFT                                     3
19344 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X4                                                        0x002810UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19345     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X4_P2S_RBUF_PTR_DIFF_O_2_0                            (0x7<<0) // P2S ring buffer initial startup pointer difference.
19346     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X4_P2S_RBUF_PTR_DIFF_O_2_0_SHIFT                      0
19347     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X4_UNUSED_0                                           (0x1f<<3) // reserved
19348     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X4_UNUSED_0_SHIFT                                     3
19349 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG16                                             0x002814UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19350     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG16_RESERVEDFIELD33                         (0x1f<<0) // Reserved
19351     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG16_RESERVEDFIELD33_SHIFT                   0
19352     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG16_RESERVEDFIELD34                         (0x3<<5) // Reserved
19353     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG16_RESERVEDFIELD34_SHIFT                   5
19354     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG16_RESERVEDFIELD35                         (0x1<<7) // Reserved
19355     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG16_RESERVEDFIELD35_SHIFT                   7
19356 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X6                                                        0x002818UL //Access:RW   DataWidth:0x8   Symbol aligner alignment word. Expects bit 0 received first  Chips: K2
19357 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X7                                                        0x00281cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19358     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X7_SYM_ALIGN_WORD_O_9_8                               (0x3<<0) // Symbol aligner alignment word. Expects bit 0 received first
19359     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X7_SYM_ALIGN_WORD_O_9_8_SHIFT                         0
19360     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X7_UNUSED_0                                           (0x3f<<2) // reserved
19361     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X7_UNUSED_0_SHIFT                                     2
19362 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8                                                        0x002820UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19363     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_LOCK_NUM_O_3_0                                 (0xf<<0) // Number of properly aligned align words that must be detected
19364     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_LOCK_NUM_O_3_0_SHIFT                           0
19365     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_UNLOCK_NUM_O_3_0                               (0xf<<4) // Number of improperly aligned align words that must be detected
19366     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_UNLOCK_NUM_O_3_0_SHIFT                         4
19367 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X31                                                       0x00287cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19368     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X31_UNUSED_0                                          (0x3f<<0) // reserved
19369     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X31_UNUSED_0_SHIFT                                    0
19370     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X31_RESERVEDFIELD36                                   (0x3<<6) // Reserved
19371     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X31_RESERVEDFIELD36_SHIFT                             6
19372 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG17                                             0x0028a8UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
19373 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43                                                       0x0028acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19374     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_RESERVEDFIELD38                                   (0x1<<0) // Reserved
19375     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_RESERVEDFIELD38_SHIFT                             0
19376     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O                       (0x1<<1) // Enable resetting of railed DLPF
19377     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_SHIFT                 1
19378     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_UNUSED_0                                          (0x3f<<2) // reserved
19379     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X43_UNUSED_0_SHIFT                                    2
19380 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44                                                       0x0028b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19381     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O                  (0x1<<0) // Enable DOSC adjustement for railed DLPF
19382     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O_SHIFT            0
19383     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O                 (0x1f<<1) // Default DOSC adjustement value for railed DLPF
19384     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_SHIFT           1
19385     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O                 (0x1<<6) // Default DOSC adjustement direction for railed DLPF
19386     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O_SHIFT           6
19387     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_UNUSED_0                                          (0x1<<7) // reserved
19388     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X44_UNUSED_0_SHIFT                                    7
19389 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49                                                       0x0028c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19390     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O                             (0x1<<0) // Enable eye scan counter
19391     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O_SHIFT                       0
19392     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O                                    (0x1<<1) // Run eye scan counter
19393     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O_SHIFT                              1
19394     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O                                  (0x1<<2) // Shift edge samples
19395     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O_SHIFT                            2
19396     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O                              (0x1<<3) // Determines shift direction of edge samples
19397     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_SHIFT                        3
19398     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O                            (0x1<<4) // Shift edge samples by 2 bits
19399     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O_SHIFT                      4
19400     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_UNUSED_0                                          (0x7<<5) // reserved
19401     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X49_UNUSED_0_SHIFT                                    5
19402 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X50                                                       0x0028c8UL //Access:RW   DataWidth:0x8   Mask eye scan results  Chips: K2
19403 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X51                                                       0x0028ccUL //Access:RW   DataWidth:0x8   Mask eye scan results  Chips: K2
19404 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X52                                                       0x0028d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19405     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X52_EYE_SCAN_MASK_O_18_16                             (0x7<<0) // Mask eye scan results
19406     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X52_EYE_SCAN_MASK_O_18_16_SHIFT                       0
19407     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X52_UNUSED_0                                          (0x1f<<3) // reserved
19408     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X52_UNUSED_0_SHIFT                                    3
19409 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X53                                                       0x0028d4UL //Access:RW   DataWidth:0x8   Eye scan wait time  Chips: K2
19410 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X54                                                       0x0028d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19411     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X54_EYE_SCAN_WAIT_LEN_O_11_8                          (0xf<<0) // Eye scan wait time
19412     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X54_EYE_SCAN_WAIT_LEN_O_11_8_SHIFT                    0
19413     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X54_RESERVEDFIELD39                                   (0xf<<4) // Reserved
19414     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X54_RESERVEDFIELD39_SHIFT                             4
19415 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X55                                                       0x0028dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19416     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X55_GCFSM_DIV_EN_O_1_0                                (0x3<<0) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
19417     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X55_GCFSM_DIV_EN_O_1_0_SHIFT                          0
19418     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X55_UNUSED_0                                          (0x3f<<2) // reserved
19419     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X55_UNUSED_0_SHIFT                                    2
19420 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X56                                                       0x0028e0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
19421 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X57                                                       0x0028e4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
19422 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X58                                                       0x0028e8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
19423 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X59                                                       0x0028ecUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
19424 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X60                                                       0x0028f0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
19425 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X61                                                       0x0028f4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
19426 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X62                                                       0x0028f8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
19427 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X63                                                       0x0028fcUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
19428 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X64                                                       0x002900UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
19429 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X65                                                       0x002904UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
19430 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X66                                                       0x002908UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
19431 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X67                                                       0x00290cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
19432 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X68                                                       0x002910UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
19433 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X69                                                       0x002914UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
19434 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X70                                                       0x002918UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
19435 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X71                                                       0x00291cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
19436 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X72                                                       0x002920UL //Access:RW   DataWidth:0x8   GCFSM calibraton direction  Chips: K2
19437 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X73                                                       0x002924UL //Access:RW   DataWidth:0x8   GCFSM calibraton direction  Chips: K2
19438 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X74                                                       0x002928UL //Access:RW   DataWidth:0x8   Function info for each MSM function. Varies depending on function number.   Bits 15-7: Address of first command to run Bits: 6-0: Number of commands to run  Chips: K2
19439 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X75                                                       0x00292cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19440 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X76                                                       0x002930UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19441 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X77                                                       0x002934UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19442 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X78                                                       0x002938UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19443 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X79                                                       0x00293cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19444 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X80                                                       0x002940UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19445 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X81                                                       0x002944UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19446 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X82                                                       0x002948UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19447 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X83                                                       0x00294cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19448 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X84                                                       0x002950UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19449 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X85                                                       0x002954UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19450 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X86                                                       0x002958UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19451 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X87                                                       0x00295cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19452 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X88                                                       0x002960UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19453 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X89                                                       0x002964UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19454 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X90                                                       0x002968UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19455 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X91                                                       0x00296cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19456 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X92                                                       0x002970UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19457 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X93                                                       0x002974UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19458 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X94                                                       0x002978UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19459 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X95                                                       0x00297cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19460 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X96                                                       0x002980UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19461 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X97                                                       0x002984UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19462 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X98                                                       0x002988UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19463 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X99                                                       0x00298cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19464 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X100                                                      0x002990UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19465 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X101                                                      0x002994UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19466 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X102                                                      0x002998UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19467 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X103                                                      0x00299cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19468 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X104                                                      0x0029a0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19469 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X105                                                      0x0029a4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19470 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X106                                                      0x0029a8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19471 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X107                                                      0x0029acUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19472 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X108                                                      0x0029b0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19473 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X109                                                      0x0029b4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19474 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X110                                                      0x0029b8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19475 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X111                                                      0x0029bcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19476 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X112                                                      0x0029c0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19477 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X113                                                      0x0029c4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19478 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X114                                                      0x0029c8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19479 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X115                                                      0x0029ccUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19480 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X116                                                      0x0029d0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19481 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X117                                                      0x0029d4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19482 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X118                                                      0x0029d8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19483 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X119                                                      0x0029dcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19484 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X120                                                      0x0029e0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19485 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X121                                                      0x0029e4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19486 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X122                                                      0x0029e8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19487 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X123                                                      0x0029ecUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19488 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X124                                                      0x0029f0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19489 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X125                                                      0x0029f4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19490 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X126                                                      0x0029f8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19491 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X127                                                      0x0029fcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19492 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X128                                                      0x002a00UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19493 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X129                                                      0x002a04UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19494 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X130                                                      0x002a08UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19495 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X131                                                      0x002a0cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19496 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X132                                                      0x002a10UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19497 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X133                                                      0x002a14UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19498 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X134                                                      0x002a18UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19499 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X135                                                      0x002a1cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19500 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X136                                                      0x002a20UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19501 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X137                                                      0x002a24UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
19502 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138                                                      0x002a28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19503     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O         (0x1<<0) // Enables programmable tx det rx pulse
19504     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O_SHIFT   0
19505     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138_RESERVEDFIELD40                                  (0x7f<<1) // Reserved
19506     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X138_RESERVEDFIELD40_SHIFT                            1
19507 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X139                                                      0x002a2cUL //Access:RW   DataWidth:0x8   Programmable width of tx det rx pulse  Chips: K2
19508 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X140                                                      0x002a30UL //Access:RW   DataWidth:0x8   Programmable width of tx det rx pulse  Chips: K2
19509 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X141                                                      0x002a34UL //Access:RW   DataWidth:0x8   Delay for MFSM state transition from P2 to P1 in non-PIPE mode.  The MFSM waits for the analog cuircuity to recover from power-down. The actual delay is 4*<reference clock period	*<value of this register	.  Chips: K2
19510 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X142                                                      0x002a38UL //Access:RW   DataWidth:0x8   Delay for MFSM state transition from P2 to P1 in non-PIPE mode.  The MFSM waits for the analog cuircuity to recover from power-down. The actual delay is 4*<reference clock period	*<value of this register	.  Chips: K2
19511 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143                                                      0x002a3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19512     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O                          (0x1<<0) // MSM Function IDDQ state's default value for iddq_sd in SAPIS mode
19513     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O_SHIFT                    0
19514     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O                           (0x1<<1) // MSM Function IDDQ state's default value for pd_dfe in SAPIS mode
19515     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_SHIFT                     1
19516     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O                      (0x1<<2) // MSM Function IDDQ state's default value for pd_dfe_bias in SAPIS mode
19517     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O_SHIFT                2
19518     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O                         (0x1<<3) // MSM Function IDDQ state's default value for pd_lnreg in SAPIS mode
19519     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_SHIFT                   3
19520     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O                        (0x1<<4) // MSM Function IDDQ state's default value for pd_lnregh in SAPIS mode
19521     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O_SHIFT                  4
19522     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O                           (0x1<<5) // MSM Function IDDQ state's default value for pd_p2s in SAPIS mode
19523     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O_SHIFT                     5
19524     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O                            (0x1<<6) // MSM Function IDDQ state's default value for pd_ra in SAPIS mode
19525     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O_SHIFT                      6
19526     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O                           (0x1<<7) // MSM Function IDDQ state's default value for pd_s2p in SAPIS mode
19527     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_SHIFT                     7
19528 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144                                                      0x002a40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19529     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O                      (0x1<<0) // MSM Function IDDQ state's default value for pd_slv_bias in SAPIS mode
19530     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O_SHIFT                0
19531     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O                         (0x1<<1) // MSM Function IDDQ state's default value for pd_txdrv in SAPIS mode
19532     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_SHIFT                   1
19533     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O                         (0x1<<2) // MSM Function IDDQ state's default value for pd_txreg in SAPIS mode
19534     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O_SHIFT                   2
19535     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O                           (0x1<<3) // MSM Function IDDQ state's default value for pd_vco in SAPIS mode
19536     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_SHIFT                     3
19537     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O                       (0x1<<4) // MSM Function IDDQ state's default value for pd_vco_buf in SAPIS mode
19538     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O_SHIFT                 4
19539     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O                        (0x1<<5) // MSM Function IDDQ state's default value for reset_cdr in SAPIS mode
19540     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O_SHIFT                  5
19541     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O                   (0x1<<6) // MSM Function IDDQ state's default value for reset_cdr_gcrx in SAPIS mode
19542     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O_SHIFT             6
19543     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O                        (0x1<<7) // MSM Function IDDQ state's default value for reset_dfe in SAPIS mode
19544     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_SHIFT                  7
19545 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145                                                      0x002a44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19546     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O                      (0x1<<0) // MSM Function IDDQ state's default value for reset_lnreg in SAPIS mode
19547     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O_SHIFT                0
19548     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O                     (0x1<<1) // MSM Function IDDQ state's default value for reset_lnregh in SAPIS mode
19549     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_SHIFT               1
19550     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O                        (0x1<<2) // MSM Function IDDQ state's default value for reset_p2s in SAPIS mode
19551     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O_SHIFT                  2
19552     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O                         (0x1<<3) // MSM Function IDDQ state's default value for reset_ra in SAPIS mode
19553     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_SHIFT                   3
19554     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O                        (0x1<<4) // MSM Function IDDQ state's default value for reset_s2p in SAPIS mode
19555     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O_SHIFT                  4
19556     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O                        (0x1<<5) // MSM Function IDDQ state's default value for reset_vco in SAPIS mode
19557     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O_SHIFT                  5
19558     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O                  (0x1<<6) // MSM Function IDDQ state's default value for txreg_bleed_ena in SAPIS mode
19559     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O_SHIFT            6
19560     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O               (0x1<<7) // MSM Function IDDQ state's default value for tx_lowpwr_idle_ena in SAPIS mode
19561     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_SHIFT         7
19562 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146                                                      0x002a48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19563     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O                           (0x1<<0) // MSM Function IDDQ state's default value for cdr_en in SAPIS mode
19564     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O_SHIFT                     0
19565     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O                        (0x1<<1) // MSM Function IDDQ state's default value for rxbclk_en in SAPIS mode
19566     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_SHIFT                  1
19567     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O                       (0x1<<2) // MSM Function IDDQ state's default value for rx_gate_en in SAPIS mode
19568     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O_SHIFT                 2
19569     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O                  (0x1<<3) // MSM Function IDDQ state's default value for reset_tx_clkdiv in SAPIS mode
19570     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_SHIFT            3
19571     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_RESERVEDFIELD41                                  (0x1<<4) // Reserved
19572     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_RESERVEDFIELD41_SHIFT                            4
19573     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_RESERVEDFIELD42                                  (0x1<<5) // Reserved
19574     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_RESERVEDFIELD42_SHIFT                            5
19575     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_RESERVEDFIELD43                                  (0x1<<6) // Reserved
19576     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_RESERVEDFIELD43_SHIFT                            6
19577     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_RESERVEDFIELD44                                  (0x1<<7) // Reserved
19578     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X146_RESERVEDFIELD44_SHIFT                            7
19579 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147                                                      0x002a4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19580     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O                           (0x1<<0) // MSM Function RESET state's default value for iddq_sd in SAPIS mode
19581     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O_SHIFT                     0
19582     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O                            (0x1<<1) // MSM Function RESET state's default value for pd_dfe in SAPIS mode
19583     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_SHIFT                      1
19584     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O                       (0x1<<2) // MSM Function RESET state's default value for pd_dfe_bias in SAPIS mode
19585     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O_SHIFT                 2
19586     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O                          (0x1<<3) // MSM Function RESET state's default value for pd_lnreg in SAPIS mode
19587     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_SHIFT                    3
19588     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O                         (0x1<<4) // MSM Function RESET state's default value for pd_lnregh in SAPIS mode
19589     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O_SHIFT                   4
19590     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O                            (0x1<<5) // MSM Function RESET state's default value for pd_p2s in SAPIS mode
19591     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O_SHIFT                      5
19592     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O                             (0x1<<6) // MSM Function RESET state's default value for pd_ra in SAPIS mode
19593     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O_SHIFT                       6
19594     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O                            (0x1<<7) // MSM Function RESET state's default value for pd_s2p in SAPIS mode
19595     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_SHIFT                      7
19596 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148                                                      0x002a50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19597     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O                       (0x1<<0) // MSM Function RESET state's default value for pd_slv_bias in SAPIS mode
19598     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O_SHIFT                 0
19599     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O                          (0x1<<1) // MSM Function RESET state's default value for pd_txdrv in SAPIS mode
19600     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_SHIFT                    1
19601     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O                          (0x1<<2) // MSM Function RESET state's default value for pd_txreg in SAPIS mode
19602     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O_SHIFT                    2
19603     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O                            (0x1<<3) // MSM Function RESET state's default value for pd_vco in SAPIS mode
19604     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_SHIFT                      3
19605     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O                        (0x1<<4) // MSM Function RESET state's default value for pd_vco_buf in SAPIS mode
19606     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O_SHIFT                  4
19607     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O                         (0x1<<5) // MSM Function RESET state's default value for reset_cdr in SAPIS mode
19608     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O_SHIFT                   5
19609     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O                    (0x1<<6) // MSM Function RESET state's default value for reset_cdr_gcrx in SAPIS mode
19610     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O_SHIFT              6
19611     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O                         (0x1<<7) // MSM Function RESET state's default value for reset_dfe in SAPIS mode
19612     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_SHIFT                   7
19613 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149                                                      0x002a54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19614     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O                       (0x1<<0) // MSM Function RESET state's default value for reset_lnreg in SAPIS mode
19615     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O_SHIFT                 0
19616     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O                      (0x1<<1) // MSM Function RESET state's default value for reset_lnregh in SAPIS mode
19617     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_SHIFT                1
19618     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O                         (0x1<<2) // MSM Function RESET state's default value for reset_p2s in SAPIS mode
19619     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O_SHIFT                   2
19620     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O                          (0x1<<3) // MSM Function RESET state's default value for reset_ra in SAPIS mode
19621     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_SHIFT                    3
19622     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O                         (0x1<<4) // MSM Function RESET state's default value for reset_s2p in SAPIS mode
19623     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O_SHIFT                   4
19624     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O                         (0x1<<5) // MSM Function RESET state's default value for reset_vco in SAPIS mode
19625     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O_SHIFT                   5
19626     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O                   (0x1<<6) // MSM Function RESET state's default value for txreg_bleed_ena in SAPIS mode
19627     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O_SHIFT             6
19628     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O                (0x1<<7) // MSM Function RESET state's default value for tx_lowpwr_idle_ena in SAPIS mode
19629     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_SHIFT          7
19630 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150                                                      0x002a58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19631     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O                            (0x1<<0) // MSM Function RESET state's default value for cdr_en in SAPIS mode
19632     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O_SHIFT                      0
19633     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O                         (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode
19634     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_SHIFT                   1
19635     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O                        (0x1<<2) // MSM Function RESET state's default value for rx_gate_en in SAPIS mode
19636     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O_SHIFT                  2
19637     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O                   (0x1<<3) // MSM Function RESET state's default value for reset_tx_clkdiv in SAPIS mode
19638     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_SHIFT             3
19639     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_RESERVEDFIELD45                                  (0x1<<4) // Reserved
19640     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_RESERVEDFIELD45_SHIFT                            4
19641     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_RESERVEDFIELD46                                  (0x1<<5) // Reserved
19642     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_RESERVEDFIELD46_SHIFT                            5
19643     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_RESERVEDFIELD47                                  (0x1<<6) // Reserved
19644     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_RESERVEDFIELD47_SHIFT                            6
19645     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_RESERVEDFIELD48                                  (0x1<<7) // Reserved
19646     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X150_RESERVEDFIELD48_SHIFT                            7
19647 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151                                                      0x002a5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19648     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O                          (0x1<<0) // MSM Function NORMAL state's default value for iddq_sd in SAPIS mode
19649     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O_SHIFT                    0
19650     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O                           (0x1<<1) // MSM Function NORMAL state's default value for pd_dfe in SAPIS mode
19651     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_SHIFT                     1
19652     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O                      (0x1<<2) // MSM Function NORMAL state's default value for pd_dfe_bias in SAPIS mode
19653     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O_SHIFT                2
19654     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O                         (0x1<<3) // MSM Function NORMAL state's default value for pd_lnreg in SAPIS mode
19655     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_SHIFT                   3
19656     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O                        (0x1<<4) // MSM Function NORMAL state's default value for pd_lnregh in SAPIS mode
19657     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O_SHIFT                  4
19658     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O                           (0x1<<5) // MSM Function NORMAL state's default value for pd_p2s in SAPIS mode
19659     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O_SHIFT                     5
19660     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O                            (0x1<<6) // MSM Function NORMAL state's default value for pd_ra in SAPIS mode
19661     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O_SHIFT                      6
19662     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O                           (0x1<<7) // MSM Function NORMAL state's default value for pd_s2p in SAPIS mode
19663     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_SHIFT                     7
19664 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152                                                      0x002a60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19665     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O                      (0x1<<0) // MSM Function NORMAL state's default value for pd_slv_bias in SAPIS mode
19666     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O_SHIFT                0
19667     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O                         (0x1<<1) // MSM Function NORMAL state's default value for pd_txdrv in SAPIS mode
19668     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_SHIFT                   1
19669     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O                         (0x1<<2) // MSM Function NORMAL state's default value for pd_txreg in SAPIS mode
19670     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O_SHIFT                   2
19671     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O                           (0x1<<3) // MSM Function NORMAL state's default value for pd_vco in SAPIS mode
19672     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_SHIFT                     3
19673     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O                       (0x1<<4) // MSM Function NORMAL state's default value for pd_vco_buf in SAPIS mode
19674     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O_SHIFT                 4
19675     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O                        (0x1<<5) // MSM Function NORMAL state's default value for reset_cdr in SAPIS mode
19676     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O_SHIFT                  5
19677     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O                   (0x1<<6) // MSM Function NORMAL state's default value for reset_cdr_gcrx in SAPIS mode
19678     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O_SHIFT             6
19679     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O                        (0x1<<7) // MSM Function NORMAL state's default value for reset_dfe in SAPIS mode
19680     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_SHIFT                  7
19681 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153                                                      0x002a64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19682     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O                      (0x1<<0) // MSM Function NORMAL state's default value for reset_lnreg in SAPIS mode
19683     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O_SHIFT                0
19684     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O                     (0x1<<1) // MSM Function NORMAL state's default value for reset_lnregh in SAPIS mode
19685     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_SHIFT               1
19686     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O                        (0x1<<2) // MSM Function NORMAL state's default value for reset_p2s in SAPIS mode
19687     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O_SHIFT                  2
19688     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O                         (0x1<<3) // MSM Function NORMAL state's default value for reset_ra in SAPIS mode
19689     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_SHIFT                   3
19690     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O                        (0x1<<4) // MSM Function NORMAL state's default value for reset_s2p in SAPIS mode
19691     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O_SHIFT                  4
19692     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O                        (0x1<<5) // MSM Function NORMAL state's default value for reset_vco in SAPIS mode
19693     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O_SHIFT                  5
19694     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O                  (0x1<<6) // MSM Function NORMAL state's default value for txreg_bleed_ena in SAPIS mode
19695     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_SHIFT            6
19696     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O               (0x1<<7) // MSM Function NORMAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
19697     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_SHIFT         7
19698 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154                                                      0x002a68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19699     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O                           (0x1<<0) // MSM Function NORMAL state's default value for cdr_en in SAPIS mode
19700     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O_SHIFT                     0
19701     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O                        (0x1<<1) // MSM Function NORMAL state's default value for rxbclk_en in SAPIS mode
19702     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_SHIFT                  1
19703     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O                       (0x1<<2) // MSM Function NORMAL state's default value for rx_gate_en in SAPIS mode
19704     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O_SHIFT                 2
19705     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O                  (0x1<<3) // MSM Function NORMAL state's default value for reset_tx_clkdiv in SAPIS mode
19706     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_SHIFT            3
19707     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_RESERVEDFIELD49                                  (0x1<<4) // Reserved
19708     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_RESERVEDFIELD49_SHIFT                            4
19709     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_RESERVEDFIELD50                                  (0x1<<5) // Reserved
19710     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_RESERVEDFIELD50_SHIFT                            5
19711     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_RESERVEDFIELD51                                  (0x1<<6) // Reserved
19712     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_RESERVEDFIELD51_SHIFT                            6
19713     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_RESERVEDFIELD52                                  (0x1<<7) // Reserved
19714     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X154_RESERVEDFIELD52_SHIFT                            7
19715 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155                                                      0x002a6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19716     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O                       (0x1<<0) // MSM Function PARTIAL state's default value for iddq_sd in SAPIS mode
19717     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O_SHIFT                 0
19718     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O                        (0x1<<1) // MSM Function PARTIAL state's default value for pd_dfe in SAPIS mode
19719     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_SHIFT                  1
19720     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O                   (0x1<<2) // MSM Function PARTIAL state's default value for pd_dfe_bias in SAPIS mode
19721     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_SHIFT             2
19722     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O                      (0x1<<3) // MSM Function PARTIAL state's default value for pd_lnreg in SAPIS mode
19723     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_SHIFT                3
19724     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O                     (0x1<<4) // MSM Function PARTIAL state's default value for pd_lnregh in SAPIS mode
19725     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O_SHIFT               4
19726     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O                        (0x1<<5) // MSM Function PARTIAL state's default value for pd_p2s in SAPIS mode
19727     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O_SHIFT                  5
19728     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O                         (0x1<<6) // MSM Function PARTIAL state's default value for pd_ra in SAPIS mode
19729     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O_SHIFT                   6
19730     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O                        (0x1<<7) // MSM Function PARTIAL state's default value for pd_s2p in SAPIS mode
19731     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_SHIFT                  7
19732 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156                                                      0x002a70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19733     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O                   (0x1<<0) // MSM Function PARTIAL state's default value for pd_slv_bias in SAPIS mode
19734     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_SHIFT             0
19735     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O                      (0x1<<1) // MSM Function PARTIAL state's default value for pd_txdrv in SAPIS mode
19736     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_SHIFT                1
19737     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O                      (0x1<<2) // MSM Function PARTIAL state's default value for pd_txreg in SAPIS mode
19738     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O_SHIFT                2
19739     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O                        (0x1<<3) // MSM Function PARTIAL state's default value for pd_vco in SAPIS mode
19740     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_SHIFT                  3
19741     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O                    (0x1<<4) // MSM Function PARTIAL state's default value for pd_vco_buf in SAPIS mode
19742     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O_SHIFT              4
19743     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O                     (0x1<<5) // MSM Function PARTIAL state's default value for reset_cdr in SAPIS mode
19744     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O_SHIFT               5
19745     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O                (0x1<<6) // MSM Function PARTIAL state's default value for reset_cdr_gcrx in SAPIS mode
19746     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O_SHIFT          6
19747     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O                     (0x1<<7) // MSM Function PARTIAL state's default value for reset_dfe in SAPIS mode
19748     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_SHIFT               7
19749 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157                                                      0x002a74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19750     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O                   (0x1<<0) // MSM Function PARTIAL state's default value for reset_lnreg in SAPIS mode
19751     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O_SHIFT             0
19752     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O                  (0x1<<1) // MSM Function PARTIAL state's default value for reset_lnregh in SAPIS mode
19753     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_SHIFT            1
19754     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O                     (0x1<<2) // MSM Function PARTIAL state's default value for reset_p2s in SAPIS mode
19755     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O_SHIFT               2
19756     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O                      (0x1<<3) // MSM Function PARTIAL state's default value for reset_ra in SAPIS mode
19757     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_SHIFT                3
19758     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O                     (0x1<<4) // MSM Function PARTIAL state's default value for reset_s2p in SAPIS mode
19759     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O_SHIFT               4
19760     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O                     (0x1<<5) // MSM Function PARTIAL state's default value for reset_vco in SAPIS mode
19761     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O_SHIFT               5
19762     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O               (0x1<<6) // MSM Function PARTIAL state's default value for txreg_bleed_ena in SAPIS mode
19763     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_SHIFT         6
19764     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O            (0x1<<7) // MSM Function PARTIAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
19765     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_SHIFT      7
19766 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158                                                      0x002a78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19767     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O                        (0x1<<0) // MSM Function PARTIAL state's default value for cdr_en in SAPIS mode
19768     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O_SHIFT                  0
19769     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O                     (0x1<<1) // MSM Function PARTIAL state's default value for rxbclk_en in SAPIS mode
19770     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_SHIFT               1
19771     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O                    (0x1<<2) // MSM Function PARTIAL state's default value for rx_gate_en in SAPIS mode
19772     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O_SHIFT              2
19773     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O               (0x1<<3) // MSM Function PARTIAL state's default value for reset_tx_clkdiv in SAPIS mode
19774     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_SHIFT         3
19775     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_RESERVEDFIELD53                                  (0x1<<4) // Reserved
19776     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_RESERVEDFIELD53_SHIFT                            4
19777     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_RESERVEDFIELD54                                  (0x1<<5) // Reserved
19778     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_RESERVEDFIELD54_SHIFT                            5
19779     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_RESERVEDFIELD55                                  (0x1<<6) // Reserved
19780     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_RESERVEDFIELD55_SHIFT                            6
19781     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_RESERVEDFIELD56                                  (0x1<<7) // Reserved
19782     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X158_RESERVEDFIELD56_SHIFT                            7
19783 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159                                                      0x002a7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19784     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O                       (0x1<<0) // MSM Function SLUMBER state's default value for iddq_sd in SAPIS mode
19785     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O_SHIFT                 0
19786     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O                        (0x1<<1) // MSM Function SLUMBER state's default value for pd_dfe in SAPIS mode
19787     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_SHIFT                  1
19788     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O                   (0x1<<2) // MSM Function SLUMBER state's default value for pd_dfe_bias in SAPIS mode
19789     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_SHIFT             2
19790     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O                      (0x1<<3) // MSM Function SLUMBER state's default value for pd_lnreg in SAPIS mode
19791     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_SHIFT                3
19792     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O                     (0x1<<4) // MSM Function SLUMBER state's default value for pd_lnregh in SAPIS mode
19793     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O_SHIFT               4
19794     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O                        (0x1<<5) // MSM Function SLUMBER state's default value for pd_p2s in SAPIS mode
19795     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O_SHIFT                  5
19796     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O                         (0x1<<6) // MSM Function SLUMBER state's default value for pd_ra in SAPIS mode
19797     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O_SHIFT                   6
19798     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O                        (0x1<<7) // MSM Function SLUMBER state's default value for pd_s2p in SAPIS mode
19799     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_SHIFT                  7
19800 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160                                                      0x002a80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19801     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O                   (0x1<<0) // MSM Function SLUMBER state's default value for pd_slv_bias in SAPIS mode
19802     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_SHIFT             0
19803     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O                      (0x1<<1) // MSM Function SLUMBER state's default value for pd_txdrv in SAPIS mode
19804     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_SHIFT                1
19805     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O                      (0x1<<2) // MSM Function SLUMBER state's default value for pd_txreg in SAPIS mode
19806     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O_SHIFT                2
19807     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O                        (0x1<<3) // MSM Function SLUMBER state's default value for pd_vco in SAPIS mode
19808     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_SHIFT                  3
19809     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O                    (0x1<<4) // MSM Function SLUMBER state's default value for pd_vco_buf in SAPIS mode
19810     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O_SHIFT              4
19811     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O                     (0x1<<5) // MSM Function SLUMBER state's default value for reset_cdr in SAPIS mode
19812     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O_SHIFT               5
19813     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O                (0x1<<6) // MSM Function SLUMBER state's default value for reset_cdr_gcrx in SAPIS mode
19814     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O_SHIFT          6
19815     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O                     (0x1<<7) // MSM Function SLUMBER state's default value for reset_dfe in SAPIS mode
19816     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_SHIFT               7
19817 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161                                                      0x002a84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19818     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O                   (0x1<<0) // MSM Function SLUMBER state's default value for reset_lnreg in SAPIS mode
19819     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O_SHIFT             0
19820     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O                  (0x1<<1) // MSM Function SLUMBER state's default value for reset_lnregh in SAPIS mode
19821     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_SHIFT            1
19822     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O                     (0x1<<2) // MSM Function SLUMBER state's default value for reset_p2s in SAPIS mode
19823     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O_SHIFT               2
19824     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O                      (0x1<<3) // MSM Function SLUMBER state's default value for reset_ra in SAPIS mode
19825     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_SHIFT                3
19826     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O                     (0x1<<4) // MSM Function SLUMBER state's default value for reset_s2p in SAPIS mode
19827     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O_SHIFT               4
19828     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O                     (0x1<<5) // MSM Function SLUMBER state's default value for reset_vco in SAPIS mode
19829     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O_SHIFT               5
19830     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O               (0x1<<6) // MSM Function SLUMBER state's default value for txreg_bleed_ena in SAPIS mode
19831     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_SHIFT         6
19832     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O            (0x1<<7) // MSM Function SLUMBER state's default value for tx_lowpwr_idle_ena in SAPIS mode
19833     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_SHIFT      7
19834 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162                                                      0x002a88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19835     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O                        (0x1<<0) // MSM Function SLUMBER state's default value for cdr_en in SAPIS mode
19836     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O_SHIFT                  0
19837     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O                     (0x1<<1) // MSM Function SLUMBER state's default value for rxbclk_en in SAPIS mode
19838     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_SHIFT               1
19839     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O                    (0x1<<2) // MSM Function SLUMBER state's default value for rx_gate_en in SAPIS mode
19840     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O_SHIFT              2
19841     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O               (0x1<<3) // MSM Function SLUMBER state's default value for reset_tx_clkdiv in SAPIS mode
19842     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_SHIFT         3
19843     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_RESERVEDFIELD57                                  (0x1<<4) // Reserved
19844     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_RESERVEDFIELD57_SHIFT                            4
19845     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_RESERVEDFIELD58                                  (0x1<<5) // Reserved
19846     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_RESERVEDFIELD58_SHIFT                            5
19847     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_RESERVEDFIELD59                                  (0x1<<6) // Reserved
19848     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_RESERVEDFIELD59_SHIFT                            6
19849     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_RESERVEDFIELD60                                  (0x1<<7) // Reserved
19850     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X162_RESERVEDFIELD60_SHIFT                            7
19851 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG18                                             0x002a8cUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
19852 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG19                                             0x002a90UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
19853 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG20                                             0x002a94UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
19854 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG21                                             0x002a98UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
19855 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG22                                             0x002a9cUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
19856 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X168                                                      0x002aa0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19857     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X168_OOB_DET_BLEN_MIN_O_6_0                           (0x7f<<0) // OOB detector minimum burst length.
19858     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X168_OOB_DET_BLEN_MIN_O_6_0_SHIFT                     0
19859     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X168_UNUSED_0                                         (0x1<<7) // reserved
19860     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X168_UNUSED_0_SHIFT                                   7
19861 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X169                                                      0x002aa4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19862     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X169_OOB_DET_BLEN_MAX_O_6_0                           (0x7f<<0) // OOB detector maximum burst length.
19863     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X169_OOB_DET_BLEN_MAX_O_6_0_SHIFT                     0
19864     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X169_UNUSED_0                                         (0x1<<7) // reserved
19865     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X169_UNUSED_0_SHIFT                                   7
19866 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X170                                                      0x002aa8UL //Access:RW   DataWidth:0x8   OOB detector COMINIT maximum idle length.  Chips: K2
19867 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171                                                      0x002aacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19868     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8                          (0x1<<0) // OOB detector COMINIT maximum idle length.
19869     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8_SHIFT                    0
19870     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171_UNUSED_0                                         (0x7f<<1) // reserved
19871     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X171_UNUSED_0_SHIFT                                   1
19872 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X172                                                      0x002ab0UL //Access:RW   DataWidth:0x8   OOB detector COMINIT maximum idle length.  Chips: K2
19873 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173                                                      0x002ab4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19874     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8                          (0x1<<0) // OOB detector COMINIT maximum idle length.
19875     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8_SHIFT                    0
19876     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173_UNUSED_0                                         (0x7f<<1) // reserved
19877     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X173_UNUSED_0_SHIFT                                   1
19878 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X174                                                      0x002ab8UL //Access:RW   DataWidth:0x8   OOB detector COMWAKE minimum idle length.  Chips: K2
19879 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175                                                      0x002abcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19880     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8                          (0x1<<0) // OOB detector COMWAKE minimum idle length.
19881     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8_SHIFT                    0
19882     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175_UNUSED_0                                         (0x7f<<1) // reserved
19883     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X175_UNUSED_0_SHIFT                                   1
19884 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X176                                                      0x002ac0UL //Access:RW   DataWidth:0x8   OOB detector COMWAKE maximum idle length.  Chips: K2
19885 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177                                                      0x002ac4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19886     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8                          (0x1<<0) // OOB detector COMWAKE maximum idle length.
19887     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8_SHIFT                    0
19888     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177_UNUSED_0                                         (0x7f<<1) // reserved
19889     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X177_UNUSED_0_SHIFT                                   1
19890 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X178                                                      0x002ac8UL //Access:RW   DataWidth:0x8   OOB detector COMSAS maximum idle length.  Chips: K2
19891 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179                                                      0x002accUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19892     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8                           (0x1<<0) // OOB detector COMSAS maximum idle length.
19893     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8_SHIFT                     0
19894     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179_UNUSED_0                                         (0x7f<<1) // reserved
19895     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X179_UNUSED_0_SHIFT                                   1
19896 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X180                                                      0x002ad0UL //Access:RW   DataWidth:0x8   OOB detector COMSAS maximum idle length.  Chips: K2
19897 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181                                                      0x002ad4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19898     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8                           (0x1<<0) // OOB detector COMSAS maximum idle length.
19899     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8_SHIFT                     0
19900     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181_UNUSED_0                                         (0x7f<<1) // reserved
19901     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X181_UNUSED_0_SHIFT                                   1
19902 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210                                                      0x002b48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19903     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_UNUSED_0                                         (0x3f<<0) // reserved
19904     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_UNUSED_0_SHIFT                                   0
19905     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O                          (0x1<<6) // Brings the TxEq pre-cursor down to a programmable value txeq_cm1_min_limit if pre cursor tuning is bypassed
19906     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O_SHIFT                    6
19907     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O                           (0x1<<7) // Brings the TxEq pre-cursor down to a programmable value txeq_c1_min_limit if pre cursor tuning is bypassed
19908     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O_SHIFT                     7
19909 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211                                                      0x002b4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19910     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_00_O_2_0                                 (0x7<<0) // AFE rx_bias setting. Used when rxvcodiv is 00
19911     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_00_O_2_0_SHIFT                           0
19912     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0                                 (0x7<<3) // AFE rx_bias setting. Used when rxvcodiv is 01 or 10
19913     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0_SHIFT                           3
19914     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_UNUSED_0                                         (0x3<<6) // reserved
19915     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X211_UNUSED_0_SHIFT                                   6
19916 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X212                                                      0x002b50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19917     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X212_RX_BIAS_11_O_2_0                                 (0x7<<0) // AFE rx_bias setting. Used when rxvcodiv is 11
19918     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X212_RX_BIAS_11_O_2_0_SHIFT                           0
19919     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X212_UNUSED_0                                         (0x1f<<3) // reserved
19920     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X212_UNUSED_0_SHIFT                                   3
19921 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213                                                      0x002b54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19922     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_RESERVEDFIELD66                                  (0x3f<<0) // Reserved
19923     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_RESERVEDFIELD66_SHIFT                            0
19924     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O                       (0x1<<6) // Enable phase detector during CDR VCO calibration
19925     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O_SHIFT                 6
19926     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_UNUSED_0                                         (0x1<<7) // reserved
19927     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X213_UNUSED_0_SHIFT                                   7
19928 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214                                                      0x002b58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19929     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_CDR_LOCK_WAIT_O_3_0                         (0xf<<0) // Number of wait cycles for the CDR to lock [3:0] times 64
19930     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_CDR_LOCK_WAIT_O_3_0_SHIFT                   0
19931     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O                             (0x1<<4) // Assertion causes repeat of calibration for rate switch or electrical idle exit. Calibrations to be performed are selected by rxeq_recal_o[6:0]/rxeq_rate2_recal_o[6:0].
19932     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O_SHIFT                       4
19933     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RESERVEDFIELD67                                  (0x1<<5) // Reserved
19934     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RESERVEDFIELD67_SHIFT                            5
19935     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O                            (0x1<<6) // Set all DFE calibration values to mid-scale instead of using start values at start of calibration
19936     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O_SHIFT                      6
19937     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_UNUSED_0                                         (0x1<<7) // reserved
19938     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X214_UNUSED_0_SHIFT                                   7
19939 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X215                                                      0x002b5cUL //Access:RW   DataWidth:0x8   DFE block -continuous calibration wait delay. DFE block will wait this number of cycles between each continuous calibration cycle  Chips: K2
19940 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X216                                                      0x002b60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19941     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X216_RXEQ_CONT_LENGTH_O_14_8                          (0x7f<<0) // DFE block -continuous calibration wait delay. DFE block will wait this number of cycles between each continuous calibration cycle
19942     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X216_RXEQ_CONT_LENGTH_O_14_8_SHIFT                    0
19943     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X216_UNUSED_0                                         (0x1<<7) // reserved
19944     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X216_UNUSED_0_SHIFT                                   7
19945 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X217                                                      0x002b64UL //Access:RW   DataWidth:0x8   DFE block - ATT calibration cycle length. This is the number of cycles the DFE will wait between changing the ATT value and examining the output.  Chips: K2
19946 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X218                                                      0x002b68UL //Access:RW   DataWidth:0x8   DFE block - Boost calibration cycle length. This is the number of cycles the DFE will wait between changing the boost value and examining the output.  Chips: K2
19947 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X219                                                      0x002b6cUL //Access:RW   DataWidth:0x8   DFE block - TAP1 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP1 value and examining the output.  Chips: K2
19948 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X220                                                      0x002b70UL //Access:RW   DataWidth:0x8   DFE block - TAP2 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.  Chips: K2
19949 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X221                                                      0x002b74UL //Access:RW   DataWidth:0x8   DFE block - TAP3 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.  Chips: K2
19950 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X222                                                      0x002b78UL //Access:RW   DataWidth:0x8   DFE block - TAP4 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.  Chips: K2
19951 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X223                                                      0x002b7cUL //Access:RW   DataWidth:0x8   DFE block - TAP5 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.  Chips: K2
19952 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224                                                      0x002b80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19953     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O                               (0x1<<0) // Repeat calibration whenever exiting RX electrical idle. Calibrations performed are selected by rxeq_recal_o[6:0]/rxeq_lane2_recal_o[6:0]
19954     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O_SHIFT                         0
19955     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0                                 (0x7f<<1) // Enables re-calibration for { Tap5, Tap4, Tap3, Tap2, Tap1, Boost, ATT} at rate3 after exit from electrical idle when rxeq_ei_exit_cal_o is asserted and after rate change when rxeq_rate_chng_cal_o is asserted.
19956     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0_SHIFT                           1
19957 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X225                                                      0x002b84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19958     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X225_RXEQ_RATE2_INIT_CAL_O_6_0                        (0x7f<<0) // Specify which block needs initial calibration upon exit from RX electrical idle state for rate2: bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bit [2]: Enables DFE Tap1 calibration when asserted bit [3]: Enables DFE Tap2 calibration when asserted bit [4]: Enables DFE Tap3 calibration when asserted bit [5]: Enables DFE Tap4 calibration when asserted bit [6]: Enables DFE Tap5 calibration when asserted
19959     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X225_RXEQ_RATE2_INIT_CAL_O_6_0_SHIFT                  0
19960     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X225_UNUSED_0                                         (0x1<<7) // reserved
19961     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X225_UNUSED_0_SHIFT                                   7
19962 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X226                                                      0x002b88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19963     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X226_RXEQ_RATE2_CONT_CAL_O_6_0                        (0x7f<<0) // Specify which block needs continuous calibration during RX data reception for rate2 bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bit [2]: Enables DFE Tap1 calibration when asserted bit [3]: Enables DFE Tap2 calibration when asserted bit [4]: Enables DFE Tap3 calibration when asserted bit [5]: Enables DFE Tap4 calibration when asserted bit [6]: Enables DFE Tap5 calibration when asserted
19964     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X226_RXEQ_RATE2_CONT_CAL_O_6_0_SHIFT                  0
19965     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X226_UNUSED_0                                         (0x1<<7) // reserved
19966     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X226_UNUSED_0_SHIFT                                   7
19967 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X227                                                      0x002b8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19968     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X227_RXEQ_RATE2_RECAL_O_6_0                           (0x7f<<0) // Enables re-calibration for { Tap5, Tap4, Tap3, Tap2, Tap1, Boost, ATT} at rate2 after exit from electrical idle when rxeq_ei_exit_cal_o is asserted and after rate change when rxeq_rate_chng_cal_o is asserted.
19969     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X227_RXEQ_RATE2_RECAL_O_6_0_SHIFT                     0
19970     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X227_UNUSED_0                                         (0x1<<7) // reserved
19971     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X227_UNUSED_0_SHIFT                                   7
19972 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228                                                      0x002b90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19973     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_ATT_BOUNCE_O_3_0                            (0xf<<0) // Number of bounces before calibration stops for ATT
19974     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_ATT_BOUNCE_O_3_0_SHIFT                      0
19975     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_BOOST_BOUNCE_O_3_0                          (0xf<<4) // Number of bounces before calibration stops for Boost
19976     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_BOOST_BOUNCE_O_3_0_SHIFT                    4
19977 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229                                                      0x002b94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19978     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP1_BOUNCE_O_3_0                           (0xf<<0) // Number of bounces before calibration stops for DFE tap1
19979     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP1_BOUNCE_O_3_0_SHIFT                     0
19980     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP2_BOUNCE_O_3_0                           (0xf<<4) // Number of bounces before calibration stops for DFE tap2
19981     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP2_BOUNCE_O_3_0_SHIFT                     4
19982 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230                                                      0x002b98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19983     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP3_BOUNCE_O_3_0                           (0xf<<0) // Number of bounces before calibration stops for DFE tap3
19984     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP3_BOUNCE_O_3_0_SHIFT                     0
19985     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP4_BOUNCE_O_3_0                           (0xf<<4) // Number of bounces before calibration stops for DFE tap4
19986     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP4_BOUNCE_O_3_0_SHIFT                     4
19987 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231                                                      0x002b9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19988     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_TAP5_BOUNCE_O_3_0                           (0xf<<0) // Number of bounces before calibration stops for DFE tap5
19989     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_TAP5_BOUNCE_O_3_0_SHIFT                     0
19990     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_COARSE_STEP_SIZE_O_3_0                      (0xf<<4) // Initial calibration coarse step size
19991     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_COARSE_STEP_SIZE_O_3_0_SHIFT                4
19992 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X232                                                      0x002ba0UL //Access:RW   DataWidth:0x8   comparator offset override value  Chips: K2
19993 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233                                                      0x002ba4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19994     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O                              (0x1<<0) // comparator offset override enable
19995     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O_SHIFT                        0
19996     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0                              (0x7f<<1) // Enable final calibration value plus one for individual blocks
19997     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0_SHIFT                        1
19998 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234                                                      0x002ba8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
19999     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_RXEQ_FIN_LOW_O_6_0                               (0x7f<<0) // Enable final calibration value minus one for individual blocks
20000     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_RXEQ_FIN_LOW_O_6_0_SHIFT                         0
20001     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O                             (0x1<<7) // Testbus select for comp_offset and tap_offset 1: Raw output from i_dfe_tap_dc_offset 0: Input to pma
20002     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O_SHIFT                       7
20003 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X235                                                      0x002bacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20004     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X235_RXEQ_ERR_SIGN_O_6_0                              (0x7f<<0) // Controls polarity of RX calibration: bit [0]: Reverses polarity of ATT calibration when asserted bit [1]: Reverses polarity of Boost calibration when asserted bit [2]: Reverses polarity of DFE Tap1 calibration when asserted bit [3]: Reverses polarity of DFE Tap2 calibration when asserted bit [4]: Reverses polarity of DFE Tap3 calibration when asserted bit [5]: Reverses polarity of DFE Tap4 calibration when asserted bit [6]: Reverses polarity of DFE Tap5 calibration when asserted
20005     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X235_RXEQ_ERR_SIGN_O_6_0_SHIFT                        0
20006     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X235_UNUSED_0                                         (0x1<<7) // reserved
20007     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X235_UNUSED_0_SHIFT                                   7
20008 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X236                                                      0x002bb0UL //Access:RW   DataWidth:0x8   Training pattern for boost  Chips: K2
20009 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237                                                      0x002bb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20010     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8               (0x1<<0) // Training pattern for boost
20011     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_SHIFT         0
20012     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237_UNUSED_0                                         (0x7f<<1) // reserved
20013     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X237_UNUSED_0_SHIFT                                   1
20014 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X238                                                      0x002bb8UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap1  Chips: K2
20015 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239                                                      0x002bbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20016     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8                      (0x1<<0) // Training pattern for DFE tap1
20017     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8_SHIFT                0
20018     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239_UNUSED_0                                         (0x7f<<1) // reserved
20019     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X239_UNUSED_0_SHIFT                                   1
20020 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X240                                                      0x002bc0UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap2  Chips: K2
20021 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241                                                      0x002bc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20022     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8                      (0x1<<0) // Training pattern for DFE tap2
20023     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8_SHIFT                0
20024     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241_UNUSED_0                                         (0x7f<<1) // reserved
20025     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X241_UNUSED_0_SHIFT                                   1
20026 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X242                                                      0x002bc8UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap3  Chips: K2
20027 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243                                                      0x002bccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20028     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8                      (0x1<<0) // Training pattern for DFE tap3
20029     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8_SHIFT                0
20030     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243_UNUSED_0                                         (0x7f<<1) // reserved
20031     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X243_UNUSED_0_SHIFT                                   1
20032 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X244                                                      0x002bd0UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap4  Chips: K2
20033 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245                                                      0x002bd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20034     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8                      (0x1<<0) // Training pattern for DFE tap4
20035     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8_SHIFT                0
20036     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245_UNUSED_0                                         (0x7f<<1) // reserved
20037     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X245_UNUSED_0_SHIFT                                   1
20038 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X246                                                      0x002bd8UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap5  Chips: K2
20039 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247                                                      0x002bdcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20040     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8                      (0x1<<0) // Training pattern for DFE tap5
20041     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8_SHIFT                0
20042     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247_UNUSED_0                                         (0x7f<<1) // reserved
20043     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X247_UNUSED_0_SHIFT                                   1
20044 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248                                                      0x002be0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20045     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_DONT_CARE_O_5_0                             (0x3f<<0) // Sets certain bits in training pattern as don't care
20046     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_DONT_CARE_O_5_0_SHIFT                       0
20047     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O                                 (0x1<<6) // RXEQ ctrl_test mode enable
20048     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O_SHIFT                           6
20049     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O                                      (0x1<<7) // Step calibration in test mode, rising edge triggers step
20050     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O_SHIFT                                7
20051 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249                                                      0x002be4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20052     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_AVG4_O_6_0                                  (0x7f<<0) // Enable average 4 in calibration, otherwise average2
20053     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_AVG4_O_6_0_SHIFT                            0
20054     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O                                     (0x1<<7) // Take the floor of the calibration result
20055     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O_SHIFT                               7
20056 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X250                                                      0x002be8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20057     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X250_RXEQ_SHIFT_O_3_0                                 (0xf<<0) // Shift the edge samples in rxeq_ctrl
20058     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X250_RXEQ_SHIFT_O_3_0_SHIFT                           0
20059     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X250_UNUSED_0                                         (0xf<<4) // reserved
20060     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X250_UNUSED_0_SHIFT                                   4
20061 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X251                                                      0x002becUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20062     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X251_RXEQ_RATE3_DFE_TAP_PD_O_4_0                      (0x1f<<0) // DFE tap powerdown for rate3
20063     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X251_RXEQ_RATE3_DFE_TAP_PD_O_4_0_SHIFT                0
20064     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X251_UNUSED_0                                         (0x7<<5) // reserved
20065     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X251_UNUSED_0_SHIFT                                   5
20066 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252                                                      0x002bf0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20067     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_RXEQ_RATE2_DFE_TAP_PD_O_4_0                      (0x1f<<0) // DFE tap powerdown for rate2
20068     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_RXEQ_RATE2_DFE_TAP_PD_O_4_0_SHIFT                0
20069     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O                           (0x1<<5) // Reverse order of tap power down signals
20070     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O_SHIFT                     5
20071     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_UNUSED_0                                         (0x3<<6) // reserved
20072     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X252_UNUSED_0_SHIFT                                   6
20073 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253                                                      0x002bf4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20074     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_MSM_LN_DFE_TAP_WAIT_O_4_0                        (0x1f<<0) // Wait time between each DFE tap DC offset calibration
20075     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_MSM_LN_DFE_TAP_WAIT_O_4_0_SHIFT                  0
20076     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O                                    (0x1<<5) // By pass comparator DC offset calibration
20077     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O_SHIFT                              5
20078     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O                         (0x1<<6) // Changes the dfe tap offset cal direction
20079     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O_SHIFT                   6
20080     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_UNUSED_0                                         (0x1<<7) // reserved
20081     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X253_UNUSED_0_SHIFT                                   7
20082 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X254                                                      0x002bf8UL //Access:RW   DataWidth:0x8   Training pattern for boost in rate2  Chips: K2
20083 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255                                                      0x002bfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20084     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8               (0x1<<0) // Training pattern for boost in rate2
20085     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_SHIFT         0
20086     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255_UNUSED_0                                         (0x7f<<1) // reserved
20087     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X255_UNUSED_0_SHIFT                                   1
20088 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X256                                                      0x002c00UL //Access:RW   DataWidth:0x8   Training pattern for boost in rate3  Chips: K2
20089 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257                                                      0x002c04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20090     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8               (0x1<<0) // Training pattern for boost in rate3
20091     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_SHIFT         0
20092     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257_UNUSED_0                                         (0x7f<<1) // reserved
20093     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X257_UNUSED_0_SHIFT                                   1
20094 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X258                                                      0x002c08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20095     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X258_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0                 (0x3f<<0) // Sets certain bits in training pattern as don't care in rate1
20096     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X258_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_SHIFT           0
20097     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X258_UNUSED_0                                         (0x3<<6) // reserved
20098     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X258_UNUSED_0_SHIFT                                   6
20099 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X259                                                      0x002c0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20100     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X259_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0                 (0x3f<<0) // Sets certain bits in training pattern as don't care in rate2
20101     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X259_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_SHIFT           0
20102     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X259_UNUSED_0                                         (0x3<<6) // reserved
20103     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X259_UNUSED_0_SHIFT                                   6
20104 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X260                                                      0x002c10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20105     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X260_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0                 (0x3f<<0) // Sets certain bits in training pattern as don't care in rate3
20106     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X260_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_SHIFT           0
20107     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X260_UNUSED_0                                         (0x3<<6) // reserved
20108     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X260_UNUSED_0_SHIFT                                   6
20109 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261                                                      0x002c14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20110     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_RESERVEDFIELD68                                  (0x1f<<0) // Reserved
20111     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_RESERVEDFIELD68_SHIFT                            0
20112     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_LANE_SEL                              (0x3<<5) // DFE TAP shadow register lane select
20113     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_LANE_SEL_SHIFT                        5
20114     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL                           (0x1<<7) // DFE shadow offset read select
20115     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_SHIFT                     7
20116 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X263                                                      0x002c1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20117     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X263_RATE3_RATESWITCH_RXRECAL_CFG_6_0                 (0x7f<<0) // Gen3 rate switch cal elements
20118     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X263_RATE3_RATESWITCH_RXRECAL_CFG_6_0_SHIFT           0
20119     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X263_UNUSED_0                                         (0x1<<7) // reserved
20120     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X263_UNUSED_0_SHIFT                                   7
20121 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X264                                                      0x002c20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20122     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X264_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0                 (0x7f<<0) // Gen3 beginning of TxEQ RxEQ cal elements
20123     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X264_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_SHIFT           0
20124     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X264_UNUSED_0                                         (0x1<<7) // reserved
20125     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X264_UNUSED_0_SHIFT                                   7
20126 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X265                                                      0x002c24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20127     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X265_RATE3_TXEQ_RXRECAL_END_CFG_6_0                   (0x7f<<0) // Gen3 end of TxEQ RxEQ cal elements
20128     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X265_RATE3_TXEQ_RXRECAL_END_CFG_6_0_SHIFT             0
20129     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X265_UNUSED_0                                         (0x1<<7) // reserved
20130     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X265_UNUSED_0_SHIFT                                   7
20131 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X266                                                      0x002c28UL //Access:R    DataWidth:0x8   DFE CMP value read  Chips: K2
20132 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X267                                                      0x002c2cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20133     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X267_DFE_TAP1_VAL                                     (0x7f<<0) // DFE TAP1 value read
20134     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X267_DFE_TAP1_VAL_SHIFT                               0
20135     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X267_UNUSED_0                                         (0x1<<7) // reserved
20136     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X267_UNUSED_0_SHIFT                                   7
20137 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X268                                                      0x002c30UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20138     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X268_DFE_TAP2_VAL                                     (0x3f<<0) // DFE TAP2 value read
20139     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X268_DFE_TAP2_VAL_SHIFT                               0
20140     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X268_UNUSED_0                                         (0x3<<6) // reserved
20141     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X268_UNUSED_0_SHIFT                                   6
20142 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X269                                                      0x002c34UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20143     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X269_DFE_TAP3_VAL                                     (0x3f<<0) // DFE TAP3 value read
20144     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X269_DFE_TAP3_VAL_SHIFT                               0
20145     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X269_UNUSED_0                                         (0x3<<6) // reserved
20146     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X269_UNUSED_0_SHIFT                                   6
20147 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X270                                                      0x002c38UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20148     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X270_DFE_TAP4_VAL                                     (0x3f<<0) // DFE TAP4 value read
20149     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X270_DFE_TAP4_VAL_SHIFT                               0
20150     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X270_UNUSED_0                                         (0x3<<6) // reserved
20151     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X270_UNUSED_0_SHIFT                                   6
20152 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X271                                                      0x002c3cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20153     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X271_DFE_TAP5_VAL                                     (0x3f<<0) // DFE TAP5 value read
20154     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X271_DFE_TAP5_VAL_SHIFT                               0
20155     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X271_UNUSED_0                                         (0x3<<6) // reserved
20156     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X271_UNUSED_0_SHIFT                                   6
20157 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X272                                                      0x002c40UL //Access:RW   DataWidth:0x8   Training pattern for TxEQ adapt DFE tap1 cm1 [7:0]  Chips: K2
20158 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273                                                      0x002c44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20159     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8                         (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 cm1 [8]
20160     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8_SHIFT                   0
20161     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0                               (0x3<<1) // TxEQ Adapt 2 TAPs
20162     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0_SHIFT                         1
20163     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_UNUSED_0                                         (0x1f<<3) // reserved
20164     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X273_UNUSED_0_SHIFT                                   3
20165 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X274                                                      0x002c48UL //Access:RW   DataWidth:0x8   Training pattern for TxEQ adapt DFE tap1 c1 [7:0]  Chips: K2
20166 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275                                                      0x002c4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20167     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8                          (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 c1 [8]
20168     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8_SHIFT                    0
20169     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1                              (0x1<<1) // Initiate TXEQ adaptation for Gen3 rate
20170     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1_SHIFT                        1
20171     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_UNUSED_0                                         (0x3f<<2) // reserved
20172     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X275_UNUSED_0_SHIFT                                   2
20173 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281                                                      0x002c64UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20174     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_RXEQ_CAL_DONE_I_3_0                              (0xf<<0) // RXEQ calibration done status - per lane
20175     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_RXEQ_CAL_DONE_I_3_0_SHIFT                        0
20176     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_TXEQ_ADAPT_DONE_I_3_0                            (0xf<<4) // TXEQ Adapt Done status - per lane
20177     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X281_TXEQ_ADAPT_DONE_I_3_0_SHIFT                      4
20178 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X296                                                      0x002ca0UL //Access:RW   DataWidth:0x8   Txeq CM1 coefficient adpatation error measurment wait time during each iteration  Chips: K2
20179 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X297                                                      0x002ca4UL //Access:RW   DataWidth:0x8   Txeq C1 coefficient adpatation error measurment wait time during each iteration  Chips: K2
20180 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X301                                                      0x002cb4UL //Access:RW   DataWidth:0x8     Chips: K2
20181 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG23                                             0x002cbcUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20182 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304                                                      0x002cc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20183     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_LOAD_EYE_CNT_WAIT                (0xf<<0) //
20184     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_LOAD_EYE_CNT_WAIT_SHIFT          0
20185     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_EYE_IN_RST_WAIT_3_0              (0xf<<4) //
20186     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_EYE_IN_RST_WAIT_3_0_SHIFT        4
20187 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305                                                      0x002cc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20188     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_EXIT_EYE_RST_WAIT                (0xf<<0) //
20189     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_EXIT_EYE_RST_WAIT_SHIFT          0
20190     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_DFE_STROBE_REDGE_WAIT_3_0        (0xf<<4) //
20191     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_DFE_STROBE_REDGE_WAIT_3_0_SHIFT  4
20192 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X306                                                      0x002cc8UL //Access:RW   DataWidth:0x8     Chips: K2
20193 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X307                                                      0x002cccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20194     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY                      (0x7f<<0) // Minimum eye delay value for rate3 during dll calibration
20195     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY_SHIFT                0
20196     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X307_UNUSED_0                                         (0x1<<7) // reserved
20197     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X307_UNUSED_0_SHIFT                                   7
20198 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X308                                                      0x002cd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20199     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X308_QAHB_CDFE_RATE3_MAX_EYE_DLY                      (0x7f<<0) // Maximum eye delay value for rate3 during dll calibration
20200     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X308_QAHB_CDFE_RATE3_MAX_EYE_DLY_SHIFT                0
20201     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X308_UNUSED_0                                         (0x1<<7) // reserved
20202     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X308_UNUSED_0_SHIFT                                   7
20203 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X310                                                      0x002cd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20204     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X310_QAHB_CDFE_RATE3_TAP1_PATT_MASK_6_0               (0x7f<<0) // cdfe tap1 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20205     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X310_QAHB_CDFE_RATE3_TAP1_PATT_MASK_6_0_SHIFT         0
20206     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X310_UNUSED_0                                         (0x1<<7) // reserved
20207     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X310_UNUSED_0_SHIFT                                   7
20208 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X311                                                      0x002cdcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20209     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X311_QAHB_CDFE_RATE3_TAP2_PATT_MASK_6_0               (0x7f<<0) // cdfe tap2 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20210     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X311_QAHB_CDFE_RATE3_TAP2_PATT_MASK_6_0_SHIFT         0
20211     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X311_UNUSED_0                                         (0x1<<7) // reserved
20212     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X311_UNUSED_0_SHIFT                                   7
20213 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X312                                                      0x002ce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20214     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X312_QAHB_CDFE_RATE3_TAP3_PATT_MASK_6_0               (0x7f<<0) // cdfe tap3 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20215     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X312_QAHB_CDFE_RATE3_TAP3_PATT_MASK_6_0_SHIFT         0
20216     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X312_UNUSED_0                                         (0x1<<7) // reserved
20217     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X312_UNUSED_0_SHIFT                                   7
20218 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X313                                                      0x002ce4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20219     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X313_QAHB_CDFE_RATE3_TAP4_PATT_MASK_6_0               (0x7f<<0) // cdfe tap4 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20220     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X313_QAHB_CDFE_RATE3_TAP4_PATT_MASK_6_0_SHIFT         0
20221     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X313_UNUSED_0                                         (0x1<<7) // reserved
20222     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X313_UNUSED_0_SHIFT                                   7
20223 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X314                                                      0x002ce8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20224     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X314_QAHB_CDFE_RATE3_TAP5_PATT_MASK_6_0               (0x7f<<0) // cdfe tap5 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20225     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X314_QAHB_CDFE_RATE3_TAP5_PATT_MASK_6_0_SHIFT         0
20226     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X314_UNUSED_0                                         (0x1<<7) // reserved
20227     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X314_UNUSED_0_SHIFT                                   7
20228 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X315                                                      0x002cecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20229     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X315_QAHB_CDFE_RATE3_DLEV_PATT_MASK_6_0               (0x7f<<0) // cdfe dlev training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20230     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X315_QAHB_CDFE_RATE3_DLEV_PATT_MASK_6_0_SHIFT         0
20231     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X315_UNUSED_0                                         (0x1<<7) // reserved
20232     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X315_UNUSED_0_SHIFT                                   7
20233 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG24                                             0x002cf4UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20234 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318                                                      0x002cf8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20235     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_LOAD_EYE_CNT_WAIT                (0xf<<0) //
20236     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_LOAD_EYE_CNT_WAIT_SHIFT          0
20237     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_EYE_IN_RST_WAIT_3_0              (0xf<<4) //
20238     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_EYE_IN_RST_WAIT_3_0_SHIFT        4
20239 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319                                                      0x002cfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20240     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_EXIT_EYE_RST_WAIT                (0xf<<0) //
20241     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_EXIT_EYE_RST_WAIT_SHIFT          0
20242     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_DFE_STROBE_REDGE_WAIT_3_0        (0xf<<4) //
20243     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_DFE_STROBE_REDGE_WAIT_3_0_SHIFT  4
20244 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X320                                                      0x002d00UL //Access:RW   DataWidth:0x8     Chips: K2
20245 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X321                                                      0x002d04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20246     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X321_QAHB_CDFE_RATE2_MIN_EYE_DLY_6_0                  (0x7f<<0) // Minimum eye delay value for rate2 during dll calibration
20247     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X321_QAHB_CDFE_RATE2_MIN_EYE_DLY_6_0_SHIFT            0
20248     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X321_UNUSED_0                                         (0x1<<7) // reserved
20249     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X321_UNUSED_0_SHIFT                                   7
20250 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X322                                                      0x002d08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20251     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X322_QAHB_CDFE_RATE2_MAX_EYE_DLY                      (0x7f<<0) // Maximum eye delay value for rate2 during dll calibration
20252     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X322_QAHB_CDFE_RATE2_MAX_EYE_DLY_SHIFT                0
20253     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X322_UNUSED_0                                         (0x1<<7) // reserved
20254     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X322_UNUSED_0_SHIFT                                   7
20255 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X324                                                      0x002d10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20256     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X324_QAHB_CDFE_RATE2_TAP1_PATT_MASK                   (0x7f<<0) // cdfe tap1 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20257     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X324_QAHB_CDFE_RATE2_TAP1_PATT_MASK_SHIFT             0
20258     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X324_UNUSED_0                                         (0x1<<7) // reserved
20259     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X324_UNUSED_0_SHIFT                                   7
20260 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X325                                                      0x002d14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20261     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X325_QAHB_CDFE_RATE2_TAP2_PATT_MASK_6_0               (0x7f<<0) // cdfe tap2 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20262     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X325_QAHB_CDFE_RATE2_TAP2_PATT_MASK_6_0_SHIFT         0
20263     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X325_UNUSED_0                                         (0x1<<7) // reserved
20264     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X325_UNUSED_0_SHIFT                                   7
20265 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X326                                                      0x002d18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20266     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X326_QAHB_CDFE_RATE2_TAP3_PATT_MASK_6_0               (0x7f<<0) // cdfe tap3 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20267     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X326_QAHB_CDFE_RATE2_TAP3_PATT_MASK_6_0_SHIFT         0
20268     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X326_UNUSED_0                                         (0x1<<7) // reserved
20269     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X326_UNUSED_0_SHIFT                                   7
20270 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X327                                                      0x002d1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20271     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X327_QAHB_CDFE_RATE2_TAP4_PATT_MASK_6_0               (0x7f<<0) // cdfe tap4 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20272     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X327_QAHB_CDFE_RATE2_TAP4_PATT_MASK_6_0_SHIFT         0
20273     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X327_UNUSED_0                                         (0x1<<7) // reserved
20274     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X327_UNUSED_0_SHIFT                                   7
20275 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X328                                                      0x002d20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20276     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X328_QAHB_CDFE_RATE2_TAP5_PATT_MASK_6_0               (0x7f<<0) // cdfe tap5 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20277     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X328_QAHB_CDFE_RATE2_TAP5_PATT_MASK_6_0_SHIFT         0
20278     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X328_UNUSED_0                                         (0x1<<7) // reserved
20279     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X328_UNUSED_0_SHIFT                                   7
20280 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X329                                                      0x002d24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20281     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X329_QAHB_CDFE_RATE2_DLEV_PATT_MASK_6_0               (0x7f<<0) // cdfe dlev training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
20282     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X329_QAHB_CDFE_RATE2_DLEV_PATT_MASK_6_0_SHIFT         0
20283     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X329_UNUSED_0                                         (0x1<<7) // reserved
20284     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X329_UNUSED_0_SHIFT                                   7
20285 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X330                                                      0x002d28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20286     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X330_QAHB_CDFE_CMP1_PRESET_OFFSET_5_0                 (0x3f<<0) // cdfe comparator1 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
20287     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X330_QAHB_CDFE_CMP1_PRESET_OFFSET_5_0_SHIFT           0
20288     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X330_UNUSED_0                                         (0x3<<6) // reserved
20289     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X330_UNUSED_0_SHIFT                                   6
20290 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X331                                                      0x002d2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20291     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X331_QAHB_CDFE_CMP2_PRESET_OFFSET_5_0                 (0x3f<<0) // cdfe comparator2 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
20292     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X331_QAHB_CDFE_CMP2_PRESET_OFFSET_5_0_SHIFT           0
20293     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X331_UNUSED_0                                         (0x3<<6) // reserved
20294     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X331_UNUSED_0_SHIFT                                   6
20295 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X332                                                      0x002d30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20296     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X332_QAHB_CDFE_CMP3_PRESET_OFFSET_5_0                 (0x3f<<0) // cdfe comparator3 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
20297     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X332_QAHB_CDFE_CMP3_PRESET_OFFSET_5_0_SHIFT           0
20298     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X332_UNUSED_0                                         (0x3<<6) // reserved
20299     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X332_UNUSED_0_SHIFT                                   6
20300 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X333                                                      0x002d34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20301     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X333_QAHB_CDFE_CMP4_PRESET_OFFSET_5_0                 (0x3f<<0) // cdfe comparator4 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
20302     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X333_QAHB_CDFE_CMP4_PRESET_OFFSET_5_0_SHIFT           0
20303     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X333_RESERVEDFIELD71                                  (0x3<<6) // Reserved
20304     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X333_RESERVEDFIELD71_SHIFT                            6
20305 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG25                                             0x002d38UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20306 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG26                                             0x002d3cUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20307 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG27                                             0x002d40UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20308 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG28                                             0x002d44UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20309 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X338                                                      0x002d48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20310     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X338_QAHB_CDFE_COARSE_DLL_ERR_AVG_NUM_6_0             (0x7f<<0) //
20311     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X338_QAHB_CDFE_COARSE_DLL_ERR_AVG_NUM_6_0_SHIFT       0
20312     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X338_UNUSED_0                                         (0x1<<7) // reserved
20313     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X338_UNUSED_0_SHIFT                                   7
20314 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X339                                                      0x002d4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20315     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X339_QAHB_CDFE_DLEV_ERR_AVG_NUM_6_0                   (0x7f<<0) //
20316     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X339_QAHB_CDFE_DLEV_ERR_AVG_NUM_6_0_SHIFT             0
20317     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X339_UNUSED_0                                         (0x1<<7) // reserved
20318     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X339_UNUSED_0_SHIFT                                   7
20319 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG29                                             0x002d50UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20320 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X341                                                      0x002d54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20321     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X341_QAHB_CDFE_COARSE_DLL_ERR_AVG_THRESHOLD_6_0       (0x7f<<0) //
20322     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X341_QAHB_CDFE_COARSE_DLL_ERR_AVG_THRESHOLD_6_0_SHIFT 0
20323     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X341_UNUSED_0                                         (0x1<<7) // reserved
20324     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X341_UNUSED_0_SHIFT                                   7
20325 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X342                                                      0x002d58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20326     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X342_QAHB_CDFE_DLEV_ERR_AVG_THRESHOLD                 (0x7f<<0) //
20327     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X342_QAHB_CDFE_DLEV_ERR_AVG_THRESHOLD_SHIFT           0
20328     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X342_UNUSED_0                                         (0x1<<7) // reserved
20329     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X342_UNUSED_0_SHIFT                                   7
20330 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG30                                             0x002d5cUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20331 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344                                                      0x002d60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20332     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_COARSE_AVG_1_0                     (0x3<<0) // Level of averaging used during cdfe dll coarse calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
20333     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_COARSE_AVG_1_0_SHIFT               0
20334     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_FINE_AVG                           (0x3<<2) // Level of averaging used during cdfe dll fine calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
20335     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_FINE_AVG_SHIFT                     2
20336     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLEV_AVG                               (0x3<<4) // Level of averaging used during cdfe dlev calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
20337     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLEV_AVG_SHIFT                         4
20338     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_RESERVEDFIELD78                                  (0x3<<6) // Reserved
20339     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X344_RESERVEDFIELD78_SHIFT                            6
20340 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31                                             0x002d64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20341     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_RESERVEDFIELD79                         (0x3<<0) // Reserved
20342     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_RESERVEDFIELD79_SHIFT                   0
20343     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_RESERVEDFIELD80                         (0x3<<2) // Reserved
20344     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_RESERVEDFIELD80_SHIFT                   2
20345     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_RESERVEDFIELD81                         (0x3<<4) // Reserved
20346     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_RESERVEDFIELD81_SHIFT                   4
20347     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_RESERVEDFIELD82                         (0x3<<6) // Reserved
20348     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG31_RESERVEDFIELD82_SHIFT                   6
20349 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346                                                      0x002d68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20350     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN                  (0x1<<0) //
20351     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN_SHIFT            0
20352     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN                  (0x1<<1) //
20353     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_SHIFT            1
20354     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_UNUSED_0                                         (0x3f<<2) // reserved
20355     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X346_UNUSED_0_SHIFT                                   2
20356 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X347                                                      0x002d6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20357     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X347_QAHB_CDFE_DLEV_TRAINING_PATT                     (0x7f<<0) // cdfe dlev training pattern.
20358     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X347_QAHB_CDFE_DLEV_TRAINING_PATT_SHIFT               0
20359     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X347_UNUSED_0                                         (0x1<<7) // reserved
20360     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X347_UNUSED_0_SHIFT                                   7
20361 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X348                                                      0x002d70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20362     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X348_QAHB_CDFE_TAP1_TRAINING_PATT_6_0                 (0x7f<<0) // cdfe tap1 training pattern.
20363     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X348_QAHB_CDFE_TAP1_TRAINING_PATT_6_0_SHIFT           0
20364     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X348_UNUSED_0                                         (0x1<<7) // reserved
20365     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X348_UNUSED_0_SHIFT                                   7
20366 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X349                                                      0x002d74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20367     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X349_QAHB_CDFE_TAP2_TRAINING_PATT_6_0                 (0x7f<<0) // cdfe tap2 training pattern.
20368     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X349_QAHB_CDFE_TAP2_TRAINING_PATT_6_0_SHIFT           0
20369     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X349_UNUSED_0                                         (0x1<<7) // reserved
20370     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X349_UNUSED_0_SHIFT                                   7
20371 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X350                                                      0x002d78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20372     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X350_QAHB_CDFE_TAP3_TRAINING_PATT_6_0                 (0x7f<<0) // cdfe tap3 training pattern.
20373     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X350_QAHB_CDFE_TAP3_TRAINING_PATT_6_0_SHIFT           0
20374     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X350_UNUSED_0                                         (0x1<<7) // reserved
20375     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X350_UNUSED_0_SHIFT                                   7
20376 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X351                                                      0x002d7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20377     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X351_QAHB_CDFE_TAP4_TRAINING_PATT_6_0                 (0x7f<<0) // cdfe tap4 training pattern.
20378     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X351_QAHB_CDFE_TAP4_TRAINING_PATT_6_0_SHIFT           0
20379     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X351_UNUSED_0                                         (0x1<<7) // reserved
20380     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X351_UNUSED_0_SHIFT                                   7
20381 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X352                                                      0x002d80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20382     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X352_QAHB_CDFE_TAP5_TRAINING_PATT_6_0                 (0x7f<<0) // cdfe tap5 training pattern.
20383     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X352_QAHB_CDFE_TAP5_TRAINING_PATT_6_0_SHIFT           0
20384     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X352_UNUSED_0                                         (0x1<<7) // reserved
20385     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X352_UNUSED_0_SHIFT                                   7
20386 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X353                                                      0x002d84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20387     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X353_QAHB_CDFE_DLL_COARSE_BOUNCE                      (0xf<<0) // Bounce number for cdfe dll coarse calibration
20388     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X353_QAHB_CDFE_DLL_COARSE_BOUNCE_SHIFT                0
20389     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X353_UNUSED_0                                         (0xf<<4) // reserved
20390     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X353_UNUSED_0_SHIFT                                   4
20391 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X354                                                      0x002d88UL //Access:RW   DataWidth:0x8   Bounce number for cdfe dll fine calibration  Chips: K2
20392 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X355                                                      0x002d8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20393     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X355_QAHB_CDFE_DLEV_BOUNCE                            (0xf<<0) // Bounce number for cdfe dlev calibration
20394     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X355_QAHB_CDFE_DLEV_BOUNCE_SHIFT                      0
20395     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X355_RESERVEDFIELD83                                  (0xf<<4) // Reserved
20396     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X355_RESERVEDFIELD83_SHIFT                            4
20397 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG32                                             0x002d90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20398     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG32_RESERVEDFIELD84                         (0xf<<0) // Reserved
20399     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG32_RESERVEDFIELD84_SHIFT                   0
20400     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG32_RESERVEDFIELD85                         (0xf<<4) // Reserved
20401     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG32_RESERVEDFIELD85_SHIFT                   4
20402 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG33                                             0x002d94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20403     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG33_RESERVEDFIELD86                         (0xf<<0) // Reserved
20404     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG33_RESERVEDFIELD86_SHIFT                   0
20405     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG33_RESERVEDFIELD87                         (0xf<<4) // Reserved
20406     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG33_RESERVEDFIELD87_SHIFT                   4
20407 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358                                                      0x002d98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20408     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLL_COARSE_STEP                        (0xf<<0) // Calibration step size for cdfe dll coarse calibration
20409     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLL_COARSE_STEP_SHIFT                  0
20410     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLEV_STEP_3_0                          (0xf<<4) // Calibration step size for cdfe dlev calibration
20411     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLEV_STEP_3_0_SHIFT                    4
20412 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG34                                             0x002d9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20413     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG34_RESERVEDFIELD88                         (0xf<<0) // Reserved
20414     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG34_RESERVEDFIELD88_SHIFT                   0
20415     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG34_RESERVEDFIELD89                         (0xf<<4) // Reserved
20416     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG34_RESERVEDFIELD89_SHIFT                   4
20417 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG35                                             0x002da0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20418     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG35_RESERVEDFIELD90                         (0xf<<0) // Reserved
20419     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG35_RESERVEDFIELD90_SHIFT                   0
20420     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG35_RESERVEDFIELD91                         (0xf<<4) // Reserved
20421     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG35_RESERVEDFIELD91_SHIFT                   4
20422 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG36                                             0x002da4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20423     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG36_RESERVEDFIELD92                         (0xf<<0) // Reserved
20424     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG36_RESERVEDFIELD92_SHIFT                   0
20425     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG36_RESERVEDFIELD93                         (0xf<<4) // Reserved
20426     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG36_RESERVEDFIELD93_SHIFT                   4
20427 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X362                                                      0x002da8UL //Access:RW   DataWidth:0x8   Maximum dlev value for cdfe  Chips: K2
20428 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X363                                                      0x002dacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20429     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X363_QAHB_CDFE_TAP1_MAX_6_0                           (0x7f<<0) // Maximum tap1 value for cdfe
20430     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X363_QAHB_CDFE_TAP1_MAX_6_0_SHIFT                     0
20431     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X363_UNUSED_0                                         (0x1<<7) // reserved
20432     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X363_UNUSED_0_SHIFT                                   7
20433 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X364                                                      0x002db0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20434     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X364_QAHB_CDFE_TAP2_MAX                               (0x3f<<0) // Maximum tap2 value for cdfe
20435     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X364_QAHB_CDFE_TAP2_MAX_SHIFT                         0
20436     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X364_UNUSED_0                                         (0x3<<6) // reserved
20437     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X364_UNUSED_0_SHIFT                                   6
20438 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X365                                                      0x002db4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20439     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X365_QAHB_CDFE_TAP3_MAX_5_0                           (0x3f<<0) // Maximum tap3 value for cdfe
20440     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X365_QAHB_CDFE_TAP3_MAX_5_0_SHIFT                     0
20441     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X365_UNUSED_0                                         (0x3<<6) // reserved
20442     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X365_UNUSED_0_SHIFT                                   6
20443 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X366                                                      0x002db8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20444     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X366_QAHB_CDFE_TAP4_MAX_5_0                           (0x3f<<0) // Maximum tap4 value for cdfe
20445     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X366_QAHB_CDFE_TAP4_MAX_5_0_SHIFT                     0
20446     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X366_UNUSED_0                                         (0x3<<6) // reserved
20447     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X366_UNUSED_0_SHIFT                                   6
20448 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367                                                      0x002dbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20449     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_TAP5_MAX_5_0                           (0x3f<<0) // Maximum tap5 value for cdfe
20450     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_TAP5_MAX_5_0_SHIFT                     0
20451     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN                          (0x1<<6) //
20452     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN_SHIFT                    6
20453     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_UNUSED_0                                         (0x1<<7) // reserved
20454     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X367_UNUSED_0_SHIFT                                   7
20455 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368                                                      0x002dc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20456     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE2_DFE_CMP_DATA_WAIT                (0xf<<0) //
20457     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE2_DFE_CMP_DATA_WAIT_SHIFT          0
20458     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE3_DFE_CMP_DATA_WAIT                (0xf<<4) //
20459     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE3_DFE_CMP_DATA_WAIT_SHIFT          4
20460 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369                                                      0x002dc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20461     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_RESERVEDFIELD94                                  (0x1<<0) // Reserved
20462     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_RESERVEDFIELD94_SHIFT                            0
20463     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O                        (0x3f<<1) // Mask bits for CM1 training pattern
20464     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_SHIFT                  1
20465     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O             (0x1<<7) //
20466     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_SHIFT       7
20467 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X370                                                      0x002dc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20468     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X370_QAHB_TAP1_C1_DONT_CARE_O                         (0x3f<<0) // Mask bits for C1 training pattern
20469     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X370_QAHB_TAP1_C1_DONT_CARE_O_SHIFT                   0
20470     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X370_UNUSED_0                                         (0x3<<6) // reserved
20471     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X370_UNUSED_0_SHIFT                                   6
20472 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371                                                      0x002dccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20473     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_CMP_SEL_ENA_O                          (0xf<<0) //
20474     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_CMP_SEL_ENA_O_SHIFT                    0
20475     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_DFE_STROBE_CNT_O                       (0x7<<4) //
20476     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_DFE_STROBE_CNT_O_SHIFT                 4
20477     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_UNUSED_0                                         (0x1<<7) // reserved
20478     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X371_UNUSED_0_SHIFT                                   7
20479 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372                                                      0x002dd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20480     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_WAIT_TIMER_1_O                         (0x7<<0) //
20481     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_WAIT_TIMER_1_O_SHIFT                   0
20482     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O                   (0x1<<3) //
20483     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_SHIFT             3
20484     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_UNUSED_0                                         (0xf<<4) // reserved
20485     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X372_UNUSED_0_SHIFT                                   4
20486 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X373                                                      0x002dd4UL //Access:RW   DataWidth:0x8     Chips: K2
20487 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG37                                             0x002dd8UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20488 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG38                                             0x002ddcUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20489 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376                                                      0x002de0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20490     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O                           (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20491     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O_SHIFT                     0
20492     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20493     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_SHIFT                      1
20494     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O                       (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20495     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O_SHIFT                 2
20496     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O                          (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20497     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_SHIFT                    3
20498     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O                         (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20499     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O_SHIFT                   4
20500     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O                            (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20501     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O_SHIFT                      5
20502     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O                             (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20503     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O_SHIFT                       6
20504     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O                            (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20505     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_SHIFT                      7
20506 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377                                                      0x002de4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20507     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O                       (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20508     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O_SHIFT                 0
20509     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O                          (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20510     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_SHIFT                    1
20511     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20512     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O_SHIFT                    2
20513     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20514     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_SHIFT                      3
20515     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O                        (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20516     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O_SHIFT                  4
20517     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O                         (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20518     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O_SHIFT                   5
20519     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O                    (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20520     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O_SHIFT              6
20521     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O                         (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20522     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_SHIFT                   7
20523 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378                                                      0x002de8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20524     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O                       (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20525     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O_SHIFT                 0
20526     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O                      (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20527     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_SHIFT                1
20528     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20529     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O_SHIFT                   2
20530     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O                          (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20531     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_SHIFT                    3
20532     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O                         (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20533     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O_SHIFT                   4
20534     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O                         (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20535     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O_SHIFT                   5
20536     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O                   (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20537     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O_SHIFT             6
20538     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O                (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20539     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_SHIFT          7
20540 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379                                                      0x002decUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20541     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20542     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O_SHIFT                      0
20543     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O                         (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20544     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_SHIFT                   1
20545     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20546     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O_SHIFT                  2
20547     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O                   (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20548     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_SHIFT             3
20549     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_RESERVEDFIELD97                                  (0x1<<4) // Reserved
20550     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_RESERVEDFIELD97_SHIFT                            4
20551     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_RESERVEDFIELD98                                  (0x1<<5) // Reserved
20552     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_RESERVEDFIELD98_SHIFT                            5
20553     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_RESERVEDFIELD99                                  (0x1<<6) // Reserved
20554     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_RESERVEDFIELD99_SHIFT                            6
20555     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_RESERVEDFIELD100                                 (0x1<<7) // Reserved
20556     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X379_RESERVEDFIELD100_SHIFT                           7
20557 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380                                                      0x002df0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20558     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20559     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O_SHIFT                      0
20560     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O                             (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20561     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_SHIFT                       1
20562     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20563     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O_SHIFT                  2
20564     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20565     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_SHIFT                     3
20566     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20567     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O_SHIFT                    4
20568     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20569     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O_SHIFT                       5
20570     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O                              (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20571     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O_SHIFT                        6
20572     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20573     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_SHIFT                       7
20574 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381                                                      0x002df4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20575     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20576     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O_SHIFT                  0
20577     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20578     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_SHIFT                     1
20579     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20580     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O_SHIFT                     2
20581     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O                             (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20582     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_SHIFT                       3
20583     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O                         (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20584     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O_SHIFT                   4
20585     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20586     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O_SHIFT                    5
20587     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O                     (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20588     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O_SHIFT               6
20589     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O                          (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20590     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_SHIFT                    7
20591 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382                                                      0x002df8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20592     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20593     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O_SHIFT                  0
20594     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20595     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_SHIFT                 1
20596     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20597     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O_SHIFT                    2
20598     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20599     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_SHIFT                     3
20600     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20601     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O_SHIFT                    4
20602     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20603     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O_SHIFT                    5
20604     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O                    (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20605     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O_SHIFT              6
20606     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20607     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_SHIFT           7
20608 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383                                                      0x002dfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20609     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20610     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O_SHIFT                       0
20611     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O                          (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20612     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_SHIFT                    1
20613     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20614     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O_SHIFT                   2
20615     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O                    (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20616     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_SHIFT              3
20617     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_RESERVEDFIELD101                                 (0x1<<4) // Reserved
20618     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_RESERVEDFIELD101_SHIFT                           4
20619     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_RESERVEDFIELD102                                 (0x1<<5) // Reserved
20620     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_RESERVEDFIELD102_SHIFT                           5
20621     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_RESERVEDFIELD103                                 (0x1<<6) // Reserved
20622     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_RESERVEDFIELD103_SHIFT                           6
20623     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_RESERVEDFIELD104                                 (0x1<<7) // Reserved
20624     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X383_RESERVEDFIELD104_SHIFT                           7
20625 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384                                                      0x002e00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20626     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20627     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O_SHIFT                      0
20628     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O                             (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20629     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_SHIFT                       1
20630     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20631     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O_SHIFT                  2
20632     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20633     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_SHIFT                     3
20634     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20635     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O_SHIFT                    4
20636     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20637     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O_SHIFT                       5
20638     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O                              (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20639     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O_SHIFT                        6
20640     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20641     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_SHIFT                       7
20642 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385                                                      0x002e04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20643     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20644     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O_SHIFT                  0
20645     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20646     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_SHIFT                     1
20647     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20648     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O_SHIFT                     2
20649     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O                             (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20650     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_SHIFT                       3
20651     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O                         (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20652     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O_SHIFT                   4
20653     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20654     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O_SHIFT                    5
20655     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O                     (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20656     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O_SHIFT               6
20657     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O                          (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20658     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_SHIFT                    7
20659 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386                                                      0x002e08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20660     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20661     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O_SHIFT                  0
20662     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20663     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_SHIFT                 1
20664     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20665     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O_SHIFT                    2
20666     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20667     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_SHIFT                     3
20668     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20669     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O_SHIFT                    4
20670     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20671     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O_SHIFT                    5
20672     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O                    (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20673     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O_SHIFT              6
20674     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20675     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_SHIFT           7
20676 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387                                                      0x002e0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20677     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20678     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O_SHIFT                       0
20679     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O                          (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20680     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_SHIFT                    1
20681     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20682     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O_SHIFT                   2
20683     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O                    (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20684     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_SHIFT              3
20685     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_RESERVEDFIELD105                                 (0x1<<4) // Reserved
20686     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_RESERVEDFIELD105_SHIFT                           4
20687     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_RESERVEDFIELD106                                 (0x1<<5) // Reserved
20688     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_RESERVEDFIELD106_SHIFT                           5
20689     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_RESERVEDFIELD107                                 (0x1<<6) // Reserved
20690     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_RESERVEDFIELD107_SHIFT                           6
20691     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_RESERVEDFIELD108                                 (0x1<<7) // Reserved
20692     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X387_RESERVEDFIELD108_SHIFT                           7
20693 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388                                                      0x002e10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20694     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20695     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O_SHIFT                      0
20696     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O                             (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20697     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_SHIFT                       1
20698     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20699     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O_SHIFT                  2
20700     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20701     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_SHIFT                     3
20702     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20703     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O_SHIFT                    4
20704     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20705     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O_SHIFT                       5
20706     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O                              (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20707     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O_SHIFT                        6
20708     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20709     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_SHIFT                       7
20710 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389                                                      0x002e14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20711     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20712     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O_SHIFT                  0
20713     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20714     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_SHIFT                     1
20715     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20716     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O_SHIFT                     2
20717     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O                             (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20718     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_SHIFT                       3
20719     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O                         (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20720     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O_SHIFT                   4
20721     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20722     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O_SHIFT                    5
20723     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O                     (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20724     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O_SHIFT               6
20725     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O                          (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20726     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_SHIFT                    7
20727 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390                                                      0x002e18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20728     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20729     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O_SHIFT                  0
20730     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20731     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_SHIFT                 1
20732     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20733     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O_SHIFT                    2
20734     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20735     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_SHIFT                     3
20736     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20737     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O_SHIFT                    4
20738     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20739     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O_SHIFT                    5
20740     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O                    (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20741     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O_SHIFT              6
20742     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20743     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_SHIFT           7
20744 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391                                                      0x002e1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20745     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20746     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O_SHIFT                       0
20747     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O                          (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20748     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_SHIFT                    1
20749     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20750     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O_SHIFT                   2
20751     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O                    (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20752     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_SHIFT              3
20753     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_RESERVEDFIELD109                                 (0x1<<4) // Reserved
20754     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_RESERVEDFIELD109_SHIFT                           4
20755     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_RESERVEDFIELD110                                 (0x1<<5) // Reserved
20756     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_RESERVEDFIELD110_SHIFT                           5
20757     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_RESERVEDFIELD111                                 (0x1<<6) // Reserved
20758     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_RESERVEDFIELD111_SHIFT                           6
20759     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_RESERVEDFIELD112                                 (0x1<<7) // Reserved
20760     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X391_RESERVEDFIELD112_SHIFT                           7
20761 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X392                                                      0x002e20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20762     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X392_MSM_PROG_MULT_DELAY_IDDQ_RESET_1_4_0             (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20763     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X392_MSM_PROG_MULT_DELAY_IDDQ_RESET_1_4_0_SHIFT       0
20764     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X392_UNUSED_0                                         (0x7<<5) // reserved
20765     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X392_UNUSED_0_SHIFT                                   5
20766 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG39                                             0x002e24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20767     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG39_RESERVEDFIELD113                        (0x7<<0) // Reserved
20768     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG39_RESERVEDFIELD113_SHIFT                  0
20769     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG39_UNUSED_0                                (0x1f<<3) // reserved
20770     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG39_UNUSED_0_SHIFT                          3
20771 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X394                                                      0x002e28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20772     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X394_MSM_PROG_MULT_DELAY_IDDQ_RESET_2_4_0             (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
20773     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X394_MSM_PROG_MULT_DELAY_IDDQ_RESET_2_4_0_SHIFT       0
20774     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X394_RESERVEDFIELD114                                 (0x7<<5) // Reserved
20775     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X394_RESERVEDFIELD114_SHIFT                           5
20776 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401                                                      0x002e44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20777     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O                                  (0x1<<0) // Lane0 master reset
20778     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O_SHIFT                            0
20779     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O                                  (0x1<<1) // Lane1 master reset
20780     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O_SHIFT                            1
20781     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O                                  (0x1<<2) // Lane2 master reset
20782     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O_SHIFT                            2
20783     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O                                  (0x1<<3) // Lane3 master reset
20784     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O_SHIFT                            3
20785     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_UNUSED_0                                         (0xf<<4) // reserved
20786     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X401_UNUSED_0_SHIFT                                   4
20787 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402                                                      0x002e48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20788     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O                                       (0x1<<0) // fast_sim_register
20789     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O_SHIFT                                 0
20790     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402_UNUSED_0                                         (0x7f<<1) // reserved
20791     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X402_UNUSED_0_SHIFT                                   1
20792 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X403                                                      0x002e4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20793     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X403_TBUS_DFE_CMP_SEL_O_2_0                           (0x7<<0) // Selects which comparator offsets come out on tbus
20794     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X403_TBUS_DFE_CMP_SEL_O_2_0_SHIFT                     0
20795     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X403_UNUSED_0                                         (0x1f<<3) // reserved
20796     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X403_UNUSED_0_SHIFT                                   3
20797 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406                                                      0x002e58UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20798     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_MODE_I_2_0                                       (0x7<<0) // 1000Base-KX Mode status for CPU
20799     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_MODE_I_2_0_SHIFT                                 0
20800     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0                                       (0x1<<3) // CMU OK Status
20801     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0_SHIFT                                 3
20802     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1                                      (0x1<<4) // CMU1 OK Status
20803     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1_SHIFT                                4
20804     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_UNUSED_0                                         (0x7<<5) // reserved
20805     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X406_UNUSED_0_SHIFT                                   5
20806 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407                                                      0x002e5cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20807     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0                          (0x1<<0) // Lane 0 Signal Detect Valid Status
20808     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0_SHIFT                    0
20809     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1                          (0x1<<1) // Lane 1 Signal Detect Valid Status
20810     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1_SHIFT                    1
20811     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2                          (0x1<<2) // Lane 2 Signal Detect Valid Status
20812     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2_SHIFT                    2
20813     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3                          (0x1<<3) // Lane 3 Signal Detect Valid Status
20814     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3_SHIFT                    3
20815     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4                                       (0x1<<4) // Lane 0 OK Status
20816     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4_SHIFT                                 4
20817     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5                                       (0x1<<5) // Lane 1 OK Status
20818     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5_SHIFT                                 5
20819     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6                                       (0x1<<6) // Lane 2 OK Status
20820     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6_SHIFT                                 6
20821     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7                                       (0x1<<7) // Lane 3 OK Status
20822     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7_SHIFT                                 7
20823 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408                                                      0x002e60UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
20824     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN0_RX_LOCKED_I_1_0                              (0x3<<0) // Lane 0 RX Locked status
20825     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN0_RX_LOCKED_I_1_0_SHIFT                        0
20826     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN1_RX_LOCKED_I_3_2                              (0x3<<2) // Lane 1 RX Locked Status
20827     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN1_RX_LOCKED_I_3_2_SHIFT                        2
20828     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN2_RX_LOCKED_I_5_4                              (0x3<<4) // Lane 2 RX Locked Status
20829     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN2_RX_LOCKED_I_5_4_SHIFT                        4
20830     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN3_RX_LOCKED_I_7_6                              (0x3<<6) // Lane 3 RX Locked Status
20831     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X408_LN3_RX_LOCKED_I_7_6_SHIFT                        6
20832 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X409                                                      0x002e64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20833     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X409_UNUSED_0                                         (0x1<<0) // reserved
20834     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X409_UNUSED_0_SHIFT                                   0
20835     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X409_RESERVEDFIELD115                                 (0x7f<<1) // Reserved
20836     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X409_RESERVEDFIELD115_SHIFT                           1
20837 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_RESERVEDREG40                                             0x002e70UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
20838 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X446                                                      0x002ef8UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20839 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X447                                                      0x002efcUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20840 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X448                                                      0x002f00UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20841 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X449                                                      0x002f04UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20842 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X450                                                      0x002f08UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20843 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X451                                                      0x002f0cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20844 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X452                                                      0x002f10UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20845 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X453                                                      0x002f14UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20846 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X454                                                      0x002f18UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20847 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X455                                                      0x002f1cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20848 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X456                                                      0x002f20UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20849 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X457                                                      0x002f24UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20850 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X458                                                      0x002f28UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20851 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X459                                                      0x002f2cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20852 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X460                                                      0x002f30UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20853 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X461                                                      0x002f34UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20854 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X462                                                      0x002f38UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20855 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X463                                                      0x002f3cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20856 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X464                                                      0x002f40UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20857 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X465                                                      0x002f44UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20858 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X466                                                      0x002f48UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20859 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X467                                                      0x002f4cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20860 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X468                                                      0x002f50UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20861 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X469                                                      0x002f54UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20862 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X470                                                      0x002f58UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20863 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X471                                                      0x002f5cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20864 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X472                                                      0x002f60UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20865 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X473                                                      0x002f64UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20866 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X474                                                      0x002f68UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20867 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X475                                                      0x002f6cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20868 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X476                                                      0x002f70UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20869 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X477                                                      0x002f74UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20870 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X478                                                      0x002f78UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20871 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X479                                                      0x002f7cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20872 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X480                                                      0x002f80UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20873 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X481                                                      0x002f84UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20874 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X482                                                      0x002f88UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
20875 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483                                                      0x002f8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20876     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20877     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O_SHIFT                  0
20878     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20879     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_SHIFT                 1
20880     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O                   (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20881     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O_SHIFT             2
20882     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O                       (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20883     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_SHIFT                 3
20884     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O                      (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20885     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O_SHIFT                4
20886     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O                        (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20887     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O_SHIFT                  5
20888     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O                        (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20889     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O_SHIFT                  6
20890     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O                        (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20891     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_SHIFT                  7
20892 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484                                                      0x002f90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20893     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20894     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O_SHIFT                  0
20895     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20896     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_SHIFT                  1
20897     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20898     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O_SHIFT                   2
20899     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O                     (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20900     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_SHIFT               3
20901     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20902     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O_SHIFT                     4
20903     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O                         (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20904     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O_SHIFT                   5
20905     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O                           (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20906     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O_SHIFT                     6
20907     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O                            (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20908     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_SHIFT                      7
20909 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485                                                      0x002f94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20910     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O                           (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20911     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O_SHIFT                     0
20912     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O                      (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20913     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_SHIFT                1
20914     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20915     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O_SHIFT                   2
20916     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20917     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_SHIFT                     3
20918     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O                      (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20919     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O_SHIFT                4
20920     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20921     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O_SHIFT                    5
20922     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O                           (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20923     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O_SHIFT                     6
20924     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O                        (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20925     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_SHIFT                  7
20926 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486                                                      0x002f98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20927     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O               (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20928     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O_SHIFT         0
20929     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O                  (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20930     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_SHIFT            1
20931     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20932     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O_SHIFT                   2
20933     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O                  (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20934     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_SHIFT            3
20935     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_RESERVEDFIELD117                                 (0x1<<4) // Reserved
20936     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_RESERVEDFIELD117_SHIFT                           4
20937     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_RESERVEDFIELD118                                 (0x1<<5) // Reserved
20938     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_RESERVEDFIELD118_SHIFT                           5
20939     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_RESERVEDFIELD119                                 (0x1<<6) // Reserved
20940     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_RESERVEDFIELD119_SHIFT                           6
20941     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_RESERVEDFIELD120                                 (0x1<<7) // Reserved
20942     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X486_RESERVEDFIELD120_SHIFT                           7
20943 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487                                                      0x002f9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20944     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20945     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O_SHIFT                  0
20946     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20947     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_SHIFT                 1
20948     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O                   (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20949     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O_SHIFT             2
20950     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O                       (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20951     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_SHIFT                 3
20952     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O                      (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20953     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O_SHIFT                4
20954     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O                        (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20955     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O_SHIFT                  5
20956     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O                        (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20957     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O_SHIFT                  6
20958     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O                        (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20959     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_SHIFT                  7
20960 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488                                                      0x002fa0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20961     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20962     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O_SHIFT                  0
20963     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20964     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_SHIFT                  1
20965     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20966     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O_SHIFT                   2
20967     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O                     (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20968     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_SHIFT               3
20969     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20970     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O_SHIFT                     4
20971     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O                         (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20972     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O_SHIFT                   5
20973     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O                           (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20974     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O_SHIFT                     6
20975     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O                            (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20976     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_SHIFT                      7
20977 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489                                                      0x002fa4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20978     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O                           (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20979     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O_SHIFT                     0
20980     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O                      (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20981     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_SHIFT                1
20982     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20983     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O_SHIFT                   2
20984     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20985     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_SHIFT                     3
20986     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O                      (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20987     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O_SHIFT                4
20988     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20989     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O_SHIFT                    5
20990     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O                           (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20991     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O_SHIFT                     6
20992     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O                  (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20993     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_SHIFT            7
20994 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490                                                      0x002fa8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
20995     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20996     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O_SHIFT                  0
20997     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
20998     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_SHIFT         1
20999     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O                  (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21000     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O_SHIFT            2
21001     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21002     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_SHIFT                   3
21003     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_RESERVEDFIELD121                                 (0x1<<4) // Reserved
21004     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_RESERVEDFIELD121_SHIFT                           4
21005     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_RESERVEDFIELD122                                 (0x1<<5) // Reserved
21006     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_RESERVEDFIELD122_SHIFT                           5
21007     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_RESERVEDFIELD123                                 (0x1<<6) // Reserved
21008     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_RESERVEDFIELD123_SHIFT                           6
21009     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_RESERVEDFIELD124                                 (0x1<<7) // Reserved
21010     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X490_RESERVEDFIELD124_SHIFT                           7
21011 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491                                                      0x002facUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21012     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21013     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O_SHIFT                  0
21014     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21015     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_SHIFT                 1
21016     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O                   (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21017     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O_SHIFT             2
21018     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O                       (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21019     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_SHIFT                 3
21020     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O                      (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21021     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O_SHIFT                4
21022     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O                        (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21023     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O_SHIFT                  5
21024     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O                        (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21025     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O_SHIFT                  6
21026     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O                  (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21027     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_SHIFT            7
21028 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492                                                      0x002fb0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21029     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21030     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O_SHIFT                  0
21031     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21032     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_SHIFT                  1
21033     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21034     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O_SHIFT                  2
21035     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21036     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_SHIFT                   3
21037     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O                     (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21038     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O_SHIFT               4
21039     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21040     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O_SHIFT                     5
21041     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21042     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O_SHIFT                   6
21043     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O                           (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21044     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_SHIFT                     7
21045 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493                                                      0x002fb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21046     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21047     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O_SHIFT                      0
21048     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21049     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_SHIFT                     1
21050     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O                      (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21051     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O_SHIFT                2
21052     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21053     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_SHIFT                   3
21054     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21055     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O_SHIFT                     4
21056     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O                      (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21057     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O_SHIFT                5
21058     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O                          (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21059     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O_SHIFT                    6
21060     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O                           (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21061     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_SHIFT                     7
21062 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494                                                      0x002fb8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21063     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21064     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O_SHIFT                  0
21065     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O               (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21066     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_SHIFT         1
21067     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O                  (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21068     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O_SHIFT            2
21069     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O                         (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21070     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_SHIFT                   3
21071     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_RESERVEDFIELD125                                 (0x1<<4) // Reserved
21072     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_RESERVEDFIELD125_SHIFT                           4
21073     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_RESERVEDFIELD126                                 (0x1<<5) // Reserved
21074     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_RESERVEDFIELD126_SHIFT                           5
21075     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_RESERVEDFIELD127                                 (0x1<<6) // Reserved
21076     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_RESERVEDFIELD127_SHIFT                           6
21077     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_RESERVEDFIELD128                                 (0x1<<7) // Reserved
21078     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X494_RESERVEDFIELD128_SHIFT                           7
21079 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X495                                                      0x002fbcUL //Access:RW   DataWidth:0x8   MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode  Chips: K2
21080 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X496                                                      0x002fc0UL //Access:RW   DataWidth:0x8   MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode  Chips: K2
21081 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X497                                                      0x002fc4UL //Access:RW   DataWidth:0x8   MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode  Chips: K2
21082 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X498                                                      0x002fc8UL //Access:RW   DataWidth:0x8   MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode  Chips: K2
21083 #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X499                                                      0x002fccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21084     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X499_PROG_MULT_REF_CLK_WAIT_O                         (0x7<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
21085     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X499_PROG_MULT_REF_CLK_WAIT_O_SHIFT                   0
21086     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X499_RESERVEDFIELD129                                 (0x1f<<3) // Reserved
21087     #define PHY_SGMII_IP_REG_AHB_COMLANE_CSR_5_X499_RESERVEDFIELD129_SHIFT                           3
21088 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0                                                           0x003000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21089     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_SOC0_DIV_O                                            (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an override
21090     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_SOC0_DIV_O_SHIFT                                      0
21091     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_SOC1_DIV_O                                            (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an override
21092     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X0_SOC1_DIV_O_SHIFT                                      4
21093 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1                                                           0x003004UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21094     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_CK_SOC_DIV_OVR_O_2_0                                  (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for pins ck_soc_div_i [1:0]
21095     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_CK_SOC_DIV_OVR_O_2_0_SHIFT                            0
21096     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_PMA_CM_REF_CLK_DIV_O                                  (0x3<<3) // Divider for pma_cm_ref_clk
21097     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_PMA_CM_REF_CLK_DIV_O_SHIFT                            3
21098     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_GCFSM_CLK_DIV_O                                       (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
21099     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_GCFSM_CLK_DIV_O_SHIFT                                 5
21100     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_BURNIN_REF_LIFE_CLK_SEL_O                             (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
21101     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X1_BURNIN_REF_LIFE_CLK_SEL_O_SHIFT                       7
21102 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2                                                           0x003008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21103     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_SSC_CLK_DIV_O                                         (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /4 4?d3:  /8:
21104     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_SSC_CLK_DIV_O_SHIFT                                   0
21105     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFCLK_SEL_O_2_0                                  (0x7<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
21106     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFCLK_SEL_O_2_0_SHIFT                            3
21107     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFDIV_O_1_0                                      (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by 4
21108     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X2_CDR_REFDIV_O_1_0_SHIFT                                6
21109 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X3                                                           0x00300cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21110     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X3_AHB_PMA_CM_DIVNSEL_O_6_0                              (0x7f<<0) // CMU N-divider setting
21111     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X3_AHB_PMA_CM_DIVNSEL_O_6_0_SHIFT                        0
21112     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X3_UNUSED_0                                              (0x1<<7) // reserved
21113     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X3_UNUSED_0_SHIFT                                        7
21114 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X4                                                           0x003010UL //Access:RW   DataWidth:0x8   CMU FL LDHS count value  Chips: K2
21115 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5                                                           0x003014UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21116     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_FL_LDHS_O_9_8                              (0x3<<0) // CMU FL LDHS count value
21117     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_FL_LDHS_O_9_8_SHIFT                        0
21118     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O                          (0x1<<2) // CMU reference div2 enable
21119     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_SHIFT                    2
21120     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PREDIV4_ENA_O                              (0x1<<3) // CMU FL prediv4 enable
21121     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_PREDIV4_ENA_O_SHIFT                        3
21122     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O                      (0x1<<4) // Reference clock startup deglitch circuit disable
21123     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_SHIFT                4
21124     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_UNUSED_0                                              (0x7<<5) // reserved
21125     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X5_UNUSED_0_SHIFT                                        5
21126 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X6                                                           0x003018UL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
21127 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X7                                                           0x00301cUL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
21128 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X8                                                           0x003020UL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
21129 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X9                                                           0x003024UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21130     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X9_GCFSM_OVR_O_27_24                                     (0xf<<0) // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
21131     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X9_GCFSM_OVR_O_27_24_SHIFT                               0
21132     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X9_UNUSED_0                                              (0xf<<4) // reserved
21133     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X9_UNUSED_0_SHIFT                                        4
21134 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X10                                                          0x003028UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
21135 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X11                                                          0x00302cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
21136 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X12                                                          0x003030UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
21137 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X13                                                          0x003034UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
21138 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X14                                                          0x003038UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
21139 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X15                                                          0x00303cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
21140 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X16                                                          0x003040UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
21141 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X17                                                          0x003044UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
21142 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X18                                                          0x003048UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
21143 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X19                                                          0x00304cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
21144 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X20                                                          0x003050UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
21145 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X21                                                          0x003054UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
21146 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X22                                                          0x003058UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
21147 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X23                                                          0x00305cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
21148 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X24                                                          0x003060UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
21149 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X25                                                          0x003064UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
21150 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26                                                          0x003068UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21151     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_OUT_OVR_EN_O                               (0x1<<0) // GCFSM output override enable
21152     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_OUT_OVR_EN_O_SHIFT                         0
21153     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0                         (0x7f<<1) // GCFSM pma_data_o override
21154     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_SHIFT                   1
21155 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27                                                          0x00306cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21156     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7                        (0x1f<<0) // GCFSM pma_data_o override
21157     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_SHIFT                  0
21158     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_LATCH_OVR_O                            (0x1<<5) // GCFSM pma_latch_o override
21159     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_LATCH_OVR_O_SHIFT                      5
21160     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_GO_OVR_O                               (0x1<<6) // GCFSM pma_go_o override
21161     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_GO_OVR_O_SHIFT                         6
21162     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_READ_OVR_O                             (0x1<<7) // GCFSM pma_read_o override
21163     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X27_GCFSM_CMU_PMA_READ_OVR_O_SHIFT                       7
21164 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X28                                                          0x003070UL //Access:RW   DataWidth:0x8   GCFSM pma_cal_o override  Chips: K2
21165 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X29                                                          0x003074UL //Access:RW   DataWidth:0x8   GCFSM pma_cal_o override  Chips: K2
21166 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30                                                          0x003078UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21167     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O                         (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable
21168     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_SHIFT                   0
21169     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O                         (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - REF clock output enable
21170     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_SHIFT                   2
21171     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_LOCK_EN_OUT_OVR_O                            (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LOCK output enable
21172     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_SHIFT                      4
21173     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O                        (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU
21174     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_SHIFT                  6
21175 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31                                                          0x00307cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21176     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O                     (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable - switches to SOC from life clock
21177     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_SHIFT               0
21178     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O                   (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU SYNTH
21179     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_SHIFT             2
21180     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O                     (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU VC0
21181     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_SHIFT               4
21182     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O                      (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - IDDQ BIAS
21183     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_SHIFT                6
21184 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32                                                          0x003080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21185     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O                        (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD BIAS
21186     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_SHIFT                  0
21187     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O                         (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU
21188     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_SHIFT                   2
21189     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O                      (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REG
21190     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_SHIFT                4
21191     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O                         (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD REF OUT
21192     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_SHIFT                   6
21193 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33                                                          0x003084UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21194     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O                (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PCS CLK ENA
21195     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_SHIFT          0
21196     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O                     (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU FL
21197     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_SHIFT               2
21198     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O                   (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU GCRX
21199     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_SHIFT             4
21200     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O                     (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LF EXTZERO ENA
21201     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_SHIFT               6
21202 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34                                                          0x003088UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21203     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O                    (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LFI EXTZERO ENA
21204     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_SHIFT              0
21205     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O                   (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REGREF
21206     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_SHIFT             2
21207     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O                    (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU REGREF
21208     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_SHIFT              4
21209     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_PMA_RESET_TXCLK_OVR_O                            (0x3<<6) // Override register for reset_txclk
21210     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X34_MSM_PMA_RESET_TXCLK_OVR_O_SHIFT                      6
21211 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35                                                          0x00308cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21212     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_RESET_CLKDIV_OVR_O                           (0x3<<0) // Override register for reset_clkdiv_ovr
21213     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_RESET_CLKDIV_OVR_O_SHIFT                     0
21214     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_OVR_O                              (0x3<<2) // Override register for pd_clkdiv_ovr
21215     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_OVR_O_SHIFT                        2
21216     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_REFCLK_LEFT_OVR_O                  (0x3<<4) // Override register for pd_clkdiv_refclk_left_ovr
21217     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_REFCLK_LEFT_OVR_O_SHIFT            4
21218     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_REFCLK_RIGHT_OVR_O                 (0x3<<6) // Override register for pd_clkdiv_refclk_right_ovr
21219     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X35_MSM_PMA_PD_CLKDIV_REFCLK_RIGHT_OVR_O_SHIFT           6
21220 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X56                                                          0x0030e0UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21221 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X57                                                          0x0030e4UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21222 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X58                                                          0x0030e8UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21223 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X59                                                          0x0030ecUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21224 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X60                                                          0x0030f0UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21225 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X61                                                          0x0030f4UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21226 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X62                                                          0x0030f8UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21227 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X63                                                          0x0030fcUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21228 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X64                                                          0x003100UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21229 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X65                                                          0x003104UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21230 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X66                                                          0x003108UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21231 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X67                                                          0x00310cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21232 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X68                                                          0x003110UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21233 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X69                                                          0x003114UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21234 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X70                                                          0x003118UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21235 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X71                                                          0x00311cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21236 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X72                                                          0x003120UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21237 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X73                                                          0x003124UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21238 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X74                                                          0x003128UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21239 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X75                                                          0x00312cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21240 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X76                                                          0x003130UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21241 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X77                                                          0x003134UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21242 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X78                                                          0x003138UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21243 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X79                                                          0x00313cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21244 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X80                                                          0x003140UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21245 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X81                                                          0x003144UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21246 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X82                                                          0x003148UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21247 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X83                                                          0x00314cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21248 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X84                                                          0x003150UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21249 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X85                                                          0x003154UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21250 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X86                                                          0x003158UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21251 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X87                                                          0x00315cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21252 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X88                                                          0x003160UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21253 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X89                                                          0x003164UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21254 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X90                                                          0x003168UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21255 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X91                                                          0x00316cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21256 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92                                                          0x003170UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21257     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_MSM_FUNC_DATA_O_289_288                              (0x3<<0) // MSM Function Data Bus slice
21258     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_MSM_FUNC_DATA_O_289_288_SHIFT                        0
21259     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_MSM_IN_OVR_O_5_0                                     (0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag override [3:0] - MFSM function override
21260     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X92_MSM_IN_OVR_O_5_0_SHIFT                               2
21261 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X93                                                          0x003174UL //Access:RW   DataWidth:0x8   Number of reference clock cycles to count after qsample is ok, before PLL is declared locked  Chips: K2
21262 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94                                                          0x003178UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21263     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_NUM_CYCLES_O_9_8                            (0x3<<0) // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
21264     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_NUM_CYCLES_O_9_8_SHIFT                      0
21265     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_GOOD_STATE_O                                (0x1<<2) // State of qsample for PLL to be considered locked
21266     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_GOOD_STATE_O_SHIFT                          2
21267     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_OVR_O                                       (0x7<<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycle count after qsample is ok [0] - Qsample override
21268     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_PLL_CTRL_OVR_O_SHIFT                                 3
21269     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_UNUSED_0                                             (0x3<<6) // reserved
21270     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X94_UNUSED_0_SHIFT                                       6
21271 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95                                                          0x00317cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21272     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_KVCO_SEL_O                              (0x3<<0) // CMU VCO integral path gain
21273     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_KVCO_SEL_O_SHIFT                        0
21274     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_FORCE_ILF_O                               (0x3<<2) // CMU loop filter force to common mode
21275     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_FORCE_ILF_O_SHIFT                         2
21276     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_CP_SEL_O                                (0x3<<4) // Charge pump current gain select.
21277     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_CP_SEL_O_SHIFT                          4
21278     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_HIZ_O                                   (0x1<<6) // CMU PLL HIZ setting
21279     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_I_HIZ_O_SHIFT                             6
21280     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_C1_SEL_O                                  (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
21281     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X95_AHB_PMA_CM_C1_SEL_O_SHIFT                            7
21282 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96                                                          0x003180UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21283     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_P_CAP_SEL_O                               (0x7<<0) // CMU VCO proportional path cap select
21284     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_P_CAP_SEL_O_SHIFT                         0
21285     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O                         (0x1<<3) // Charge pump chop enable
21286     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_SHIFT                   3
21287     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_I_CAP_SEL_O                               (0x7<<4) // CMU VCO integral path cap select
21288     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_I_CAP_SEL_O_SHIFT                         4
21289     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_BGSTART_BYP_O                             (0x1<<7) // Bandgap startup circuit bypass
21290     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X96_AHB_PMA_CM_BGSTART_BYP_O_SHIFT                       7
21291 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97                                                          0x003184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21292     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VCO_BIAS_O                                (0xf<<0) // CMU VCO bias current setting.
21293     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VCO_BIAS_O_SHIFT                          0
21294     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VREG_O                                    (0x3<<4) // CMU VREG setting
21295     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VREG_O_SHIFT                              4
21296     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VREGH_O                                   (0x3<<6) // CMU VREGH setting
21297     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X97_AHB_PMA_CM_VREGH_O_SHIFT                             6
21298 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98                                                          0x003188UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21299     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_DN_O                            (0x1<<0) // Force PFD to output down
21300     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_DN_O_SHIFT                      0
21301     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_UP_O                            (0x1<<1) // Force PFD to output up
21302     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PFD_FORCE_UP_O_SHIFT                      1
21303     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_SR_NDIV_OVR_ENA_O                                    (0x1<<2) // Override enable for overriding N-div value
21304     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_SR_NDIV_OVR_ENA_O_SHIFT                              2
21305     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O                        (0x1<<3) // CMU V2I filter enable
21306     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_SHIFT                  3
21307     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O                  (0x1<<4) // CMU VCO PMOS proportional current increase
21308     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_SHIFT            4
21309     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O                  (0x1<<5) // CMU VCO PMOS proportional current decrease
21310     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_SHIFT            5
21311     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_VREGREF_O                                 (0x3<<6) // CMU reference clock regulator setting
21312     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X98_AHB_PMA_CM_VREGREF_O_SHIFT                           6
21313 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X99                                                          0x00318cUL //Access:RW   DataWidth:0x8   CMU AFE spares  Chips: K2
21314 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100                                                         0x003190UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21315     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_PFD_PW_O                                 (0x3<<0) // PFD pulse width setting
21316     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_PFD_PW_O_SHIFT                           0
21317     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_I_DROPI_O                                (0x1<<2) // Enable to reduce charge pump reference current
21318     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_I_DROPI_O_SHIFT                          2
21319     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_P_KVCO_SEL_O                             (0x1f<<3) // CMU PLL KVCO setting
21320     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X100_AHB_PMA_CM_P_KVCO_SEL_O_SHIFT                       3
21321 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X101                                                         0x003194UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21322     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X101_AHB_PMA_CM_DIVPSEL_O                                (0x7f<<0) // CMU P-divider setting
21323     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X101_AHB_PMA_CM_DIVPSEL_O_SHIFT                          0
21324     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X101_RESERVEDFIELD16                                     (0x1<<7) // Reserved
21325     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X101_RESERVEDFIELD16_SHIFT                               7
21326 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102                                                         0x003198UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21327     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_O                                  (0x7<<0) // AHB override for calibrated VCOFR value.
21328     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_O_SHIFT                            0
21329     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_SEL_O                              (0x1<<3) // Override enable for overriding VCOFR value
21330     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_AHB_PMA_CM_VCOFR_SEL_O_SHIFT                        3
21331     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_RESERVEDFIELD17                                     (0xf<<4) // Reserved
21332     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X102_RESERVEDFIELD17_SHIFT                               4
21333 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG8                                                 0x00319cUL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
21334 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG9                                                 0x0031a0UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
21335 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG10                                                0x0031a4UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
21336 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG11                                                0x0031a8UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
21337 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG12                                                0x0031acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21338     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG12_RESERVEDFIELD22                            (0xf<<0) // Reserved
21339     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG12_RESERVEDFIELD22_SHIFT                      0
21340     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG12_UNUSED_0                                   (0xf<<4) // reserved
21341     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG12_UNUSED_0_SHIFT                             4
21342 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108                                                         0x0031b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21343     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_RESERVEDFIELD23                                     (0x7<<0) // Reserved
21344     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_RESERVEDFIELD23_SHIFT                               0
21345     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0                         (0xf<<3) // Reference clock output select
21346     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_SHIFT                   3
21347     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_SEL_OVR_O                                (0x1<<7) // Reference clock select override
21348     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X108_PMA_REFCLK_SEL_OVR_O_SHIFT                          7
21349 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109                                                         0x0031b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21350     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_L_O                                   (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
21351     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_L_O_SHIFT                             0
21352     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_R_O                                   (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
21353     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_OE_R_O_SHIFT                             1
21354     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_L_O                                    (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
21355     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_L_O_SHIFT                              2
21356     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_R_O                                    (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
21357     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_RXCLK_OE_R_O_SHIFT                              3
21358     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_CM_HV2P5SEL_O                                   (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
21359     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_CM_HV2P5SEL_O_SHIFT                             4
21360     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_RESERVEDFIELD24                                     (0x1<<5) // Reserved
21361     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_RESERVEDFIELD24_SHIFT                               5
21362     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_L_O                                 (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
21363     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_L_O_SHIFT                           6
21364     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_R_O                                 (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
21365     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X109_PMA_REFCLK_QFWD_R_O_SHIFT                           7
21366 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X110                                                         0x0031b8UL //Access:RW   DataWidth:0x8   Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode  Chips: K2
21367 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X111                                                         0x0031bcUL //Access:RW   DataWidth:0x8   Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode  Chips: K2
21368 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112                                                         0x0031c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21369     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_FCNTL_O_19_16                                   (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
21370     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_FCNTL_O_19_16_SHIFT                             0
21371     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_GEN_EN_O                                        (0x1<<4) // Active high Enable for SSC generator SSC mode
21372     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_GEN_EN_O_SHIFT                                  4
21373     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_EN_O                                            (0x1<<5) // Active high Enable for SSC block synth or SSC mode
21374     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_SSC_EN_O_SHIFT                                      5
21375     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_UNUSED_0                                            (0x3<<6) // reserved
21376     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X112_UNUSED_0_SHIFT                                      6
21377 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X113                                                         0x0031c4UL //Access:RW   DataWidth:0x8   SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz  Chips: K2
21378 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X114                                                         0x0031c8UL //Access:RW   DataWidth:0x8   SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz  Chips: K2
21379 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115                                                         0x0031ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21380     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_MATCH_VAL_O_19_16                           (0xf<<0) // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
21381     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_MATCH_VAL_O_19_16_SHIFT                     0
21382     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_FRACSYN_EN_O                                (0x1<<4) // Enable for SSC generator with Fractional Synthesis
21383     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_FRACSYN_EN_O_SHIFT                          4
21384     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_EN_FRACN_FRCDIV_MODE_O                              (0x1<<5) // Enable fractional division mode and SSC mode
21385     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_EN_FRACN_FRCDIV_MODE_O_SHIFT                        5
21386     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_UPDOWN_EN_O                                 (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
21387     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_SSC_GEN_UPDOWN_EN_O_SHIFT                           6
21388     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_UNUSED_0                                            (0x1<<7) // reserved
21389     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X115_UNUSED_0_SHIFT                                      7
21390 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X116                                                         0x0031d0UL //Access:RW   DataWidth:0x8   In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word  Chips: K2
21391 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X117                                                         0x0031d4UL //Access:RW   DataWidth:0x8   In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word  Chips: K2
21392 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118                                                         0x0031d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21393     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_MOD_TST_IN_O                                  (0xf<<0) // Test input bus
21394     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_MOD_TST_IN_O_SHIFT                            0
21395     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_MOD_TST_CTRL_O                                (0x3<<4) // Test i/p control source :  0-modulator  1-bypass modulator  2-modulator  3-sr_txt_in_i
21396     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_MOD_TST_CTRL_O_SHIFT                          4
21397     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_SRC_SEL_O                             (0x1<<6) // Clock Select for High Speed clock source :  0-clk_hs_fbk  1-clk_hs_refout
21398     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_SRC_SEL_O_SHIFT                       6
21399     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_DIV_SEL_O                             (0x1<<7) // Clock divider for High Speed clock source
21400     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X118_FRACN_FBK_CLK_DIV_SEL_O_SHIFT                       7
21401 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119                                                         0x0031dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21402     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0                          (0x1f<<0) // override for the counter value
21403     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_SHIFT                    0
21404     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLL_EN_O                          (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
21405     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_SHIFT                    5
21406     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLARITY_O                         (0x1<<6) // chicken bit for counter polarity
21407     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_POLARITY_O_SHIFT                   6
21408     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_EN_O                           (0x1<<7) // override enable to use above value
21409     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_SHIFT                     7
21410 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X120                                                         0x0031e0UL //Access:RW   DataWidth:0x8   Divider input for Div-by-N counter  Chips: K2
21411 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X121                                                         0x0031e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21412     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8                     (0x7f<<0) // Divider input for Div-by-N counter
21413     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_SHIFT               0
21414     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X121_UNUSED_0                                            (0x1<<7) // reserved
21415     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X121_UNUSED_0_SHIFT                                      7
21416 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122                                                         0x0031e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21417     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_O                            (0x1f<<0) // Refclk Termination override value
21418     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_O_SHIFT                      0
21419     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_EN_O                         (0x1<<5) // Refclk Termination override enable
21420     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_SHIFT                   5
21421     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_UNUSED_0                                            (0x3<<6) // reserved
21422     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X122_UNUSED_0_SHIFT                                      6
21423 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123                                                         0x0031ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21424     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_O                                (0x1f<<0) // Rx Termination override value, every rx lane gets the same value
21425     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_O_SHIFT                          0
21426     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_EN_O                             (0x1<<5) // Rx Termination override enable
21427     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_PMA_CM_RX_TERM_OVR_EN_O_SHIFT                       5
21428     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_UNUSED_0                                            (0x3<<6) // reserved
21429     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X123_UNUSED_0_SHIFT                                      6
21430 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X124                                                         0x0031f0UL //Access:RW   DataWidth:0x8   In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  Chips: K2
21431 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125                                                         0x0031f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21432     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_UP_8                            (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
21433     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_UP_8_SHIFT                      0
21434     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE                          (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
21435     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_SHIFT                    1
21436     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_UP_NUM_SAMPLES                            (0xf<<4) // in txterm calibration, the number of samples to take from the same comparator
21437     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X125_AHB_RX_TC_UP_NUM_SAMPLES_SHIFT                      4
21438 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126                                                         0x0031f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21439     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_GC_TCCAL_ENA_OVR                                (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
21440     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_GC_TCCAL_ENA_OVR_SHIFT                          0
21441     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_RX_TC_BIAS_OVR                                  (0x7<<1) // Bit 3:1 RX termination calibration DAC override setting
21442     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_AHB_RX_TC_BIAS_OVR_SHIFT                            1
21443     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_UNUSED_0                                            (0xf<<4) // reserved
21444     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X126_UNUSED_0_SHIFT                                      4
21445 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127                                                         0x0031fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21446     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_CMU_MASTER_CDN_O                                    (0x1<<0) // Master reset for CMU
21447     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_CMU_MASTER_CDN_O_SHIFT                              0
21448     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_PCS_RATE_O                                          (0x3<<1) // Determines rate for PLL clock pcs_rate_o[0] :      0: VCO clock untouched      1: VCO clock divided by 2                                                 pcs_rate_o[1] :      0: PMA operates in 10b/20b mode Enables %5 circuit      1: PMA operates in 8b/16b mode   Enables %4 circuit
21449     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_PCS_RATE_O_SHIFT                                    1
21450     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_UNUSED_0                                            (0x1f<<3) // reserved
21451     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X127_UNUSED_0_SHIFT                                      3
21452 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X128                                                         0x003200UL //Access:RW   DataWidth:0x8   Not used  Chips: K2
21453 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129                                                         0x003204UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21454     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_CMU_IN_OVR_O_3_0                                    (0xf<<0) // Override for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] - CMU Reset Pin IO
21455     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_CMU_IN_OVR_O_3_0_SHIFT                              0
21456     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_CMU_OUT_OVR_O_1_0                                   (0x3<<4) // Override for Reset_smu_fl
21457     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_CMU_OUT_OVR_O_1_0_SHIFT                             4
21458     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_UNUSED_0                                            (0x3<<6) // reserved
21459     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X129_UNUSED_0_SHIFT                                      6
21460 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X130                                                         0x003208UL //Access:R    DataWidth:0x8   Snapshot of digital test bus data [7:0]  Chips: K2
21461 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X131                                                         0x00320cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
21462     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X131_TBUS_DATA_SMPL_11_8                                 (0xf<<0) // Snapshot of digital test bus data [11:8]
21463     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X131_TBUS_DATA_SMPL_11_8_SHIFT                           0
21464     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X131_UNUSED_0                                            (0xf<<4) // reserved
21465     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X131_UNUSED_0_SHIFT                                      4
21466 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X132                                                         0x003210UL //Access:RW   DataWidth:0x8   CMU Test Bus address 7-0  Chips: K2
21467 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X133                                                         0x003214UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21468     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X133_TBUS_ADDR_OVR_O_10_8                                (0x7<<0) // CMU Test Bus address 10-8
21469     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X133_TBUS_ADDR_OVR_O_10_8_SHIFT                          0
21470     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X133_UNUSED_0                                            (0x1f<<3) // reserved
21471     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X133_UNUSED_0_SHIFT                                      3
21472 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X134                                                         0x003218UL //Access:RW   DataWidth:0x8   Not used  Chips: K2
21473 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X144                                                         0x003240UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21474     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X144_UNUSED_0                                            (0x1f<<0) // reserved
21475     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X144_UNUSED_0_SHIFT                                      0
21476     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X144_RESERVEDFIELD25                                     (0x1<<5) // Reserved
21477     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X144_RESERVEDFIELD25_SHIFT                               5
21478     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X144_UNUSED_1                                            (0x3<<6) // reserved
21479     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X144_UNUSED_1_SHIFT                                      6
21480 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X146                                                         0x003248UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21481     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X146_UNUSED_0                                            (0x7f<<0) // reserved
21482     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X146_UNUSED_0_SHIFT                                      0
21483     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X146_RESERVEDFIELD26                                     (0x1<<7) // Reserved
21484     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X146_RESERVEDFIELD26_SHIFT                               7
21485 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X147                                                         0x00324cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21486     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O                    (0x7<<0) // Not used
21487     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_SHIFT              0
21488     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X147_RESERVEDFIELD27                                     (0x1f<<3) // Reserved
21489     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X147_RESERVEDFIELD27_SHIFT                               3
21490 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG13                                                0x003250UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
21491 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X149                                                         0x003254UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21492     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X149_AHB_PMA_CM_EN_REGLN_O                               (0xf<<0) // Not used
21493     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X149_AHB_PMA_CM_EN_REGLN_O_SHIFT                         0
21494     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X149_UNUSED_0                                            (0xf<<4) // reserved
21495     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X149_UNUSED_0_SHIFT                                      4
21496 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X153                                                         0x003264UL //Access:RW   DataWidth:0x8   Inverts up_i when set to 1  Chips: K2
21497 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X154                                                         0x003268UL //Access:RW   DataWidth:0x8   Inverts up_i when set to 1  Chips: K2
21498 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X161                                                         0x003284UL //Access:RW   DataWidth:0x8   Function info for each MSM function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of commands to run  Chips: K2
21499 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X162                                                         0x003288UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21500 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X163                                                         0x00328cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21501 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X164                                                         0x003290UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21502 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X165                                                         0x003294UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21503 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X166                                                         0x003298UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21504 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X167                                                         0x00329cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21505 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X168                                                         0x0032a0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21506 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X169                                                         0x0032a4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21507 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X170                                                         0x0032a8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21508 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X171                                                         0x0032acUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21509 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X172                                                         0x0032b0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21510 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X173                                                         0x0032b4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21511 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X174                                                         0x0032b8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21512 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X175                                                         0x0032bcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21513 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X176                                                         0x0032c0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21514 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X177                                                         0x0032c4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21515 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X178                                                         0x0032c8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21516 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X179                                                         0x0032ccUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21517 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X180                                                         0x0032d0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21518 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X181                                                         0x0032d4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21519 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X182                                                         0x0032d8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21520 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X183                                                         0x0032dcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21521 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X184                                                         0x0032e0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21522 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X185                                                         0x0032e4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21523 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X186                                                         0x0032e8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21524 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X187                                                         0x0032ecUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21525 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X188                                                         0x0032f0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
21526 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG14                                                0x0032f4UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
21527 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_RESERVEDREG15                                                0x0032f8UL //Access:RW   DataWidth:0x8   Reserved  Chips: K2
21528 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191                                                         0x0032fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21529     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_IDDQ_BIAS_IDDQ_SETVAL_O                             (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
21530     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_IDDQ_BIAS_IDDQ_SETVAL_O_SHIFT                       0
21531     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_BIAS_IDDQ_SETVAL_O                               (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
21532     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_BIAS_IDDQ_SETVAL_O_SHIFT                         1
21533     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O                   (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
21534     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_SHIFT             2
21535     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMU_IDDQ_SETVAL_O                                (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
21536     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMU_IDDQ_SETVAL_O_SHIFT                          3
21537     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREG_IDDQ_SETVAL_O                             (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
21538     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREG_IDDQ_SETVAL_O_SHIFT                       4
21539     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREGREF_IDDQ_SETVAL_O                          (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
21540     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_CMUREGREF_IDDQ_SETVAL_O_SHIFT                    5
21541     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_REF_IDDQ_SETVAL_O                                (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
21542     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_PD_REF_IDDQ_SETVAL_O_SHIFT                          6
21543     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_CMU_FL_IDDQ_SETVAL_O                          (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
21544     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X191_RESET_CMU_FL_IDDQ_SETVAL_O_SHIFT                    7
21545 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192                                                         0x003300UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21546     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_IDDQ_SETVAL_O                             (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
21547     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_IDDQ_SETVAL_O_SHIFT                       0
21548     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O                        (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
21549     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_SHIFT                  1
21550     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREG_IDDQ_SETVAL_O                          (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
21551     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREG_IDDQ_SETVAL_O_SHIFT                    2
21552     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREGREF_IDDQ_SETVAL_O                       (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
21553     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_SHIFT                 3
21554     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O                        (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
21555     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_SHIFT                  4
21556     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUVCO_IDDQ_SETVAL_O                          (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
21557     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_RESET_CMUVCO_IDDQ_SETVAL_O_SHIFT                    5
21558     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O                        (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
21559     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_SHIFT                  6
21560     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LFI_EXTZERO_IDDQ_SETVAL_O                           (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
21561     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X192_LFI_EXTZERO_IDDQ_SETVAL_O_SHIFT                     7
21562 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193                                                         0x003304UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21563     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_SOC_CLK_EN_IDDQ_SETVAL_O                            (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
21564     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_SOC_CLK_EN_IDDQ_SETVAL_O_SHIFT                      0
21565     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_REFCLK_EN_IDDQ_SETVAL_O                             (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
21566     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_REFCLK_EN_IDDQ_SETVAL_O_SHIFT                       1
21567     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PLL_LOCK_EN_IDDQ_SETVAL_O                           (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
21568     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_SHIFT                     2
21569     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_TXCLK_IDDQ_SETVAL_O                           (0x1<<3) // Not used
21570     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_TXCLK_IDDQ_SETVAL_O_SHIFT                     3
21571     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_CLKDIV_IDDQ_SETVAL_O                          (0x1<<4) // Not used
21572     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_RESET_CLKDIV_IDDQ_SETVAL_O_SHIFT                    4
21573     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_IDDQ_SETVAL_O                             (0x1<<5) // Not used
21574     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_IDDQ_SETVAL_O_SHIFT                       5
21575     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O                 (0x1<<6) // Not used
21576     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_SHIFT           6
21577     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O                (0x1<<7) // Not used
21578     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_SHIFT          7
21579 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194                                                         0x003308UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21580     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_IDDQ_BIAS_RST_SETVAL_O                              (0x1<<0) // MSM Function RST mode default value for iddq_bias
21581     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_IDDQ_BIAS_RST_SETVAL_O_SHIFT                        0
21582     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_BIAS_RST_SETVAL_O                                (0x1<<1) // MSM Function RST mode default value for pd_bias
21583     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_BIAS_RST_SETVAL_O_SHIFT                          1
21584     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O                    (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
21585     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_SHIFT              2
21586     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMU_RST_SETVAL_O                                 (0x1<<3) // MSM Function RST mode default value for pd_cmu
21587     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMU_RST_SETVAL_O_SHIFT                           3
21588     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREG_RST_SETVAL_O                              (0x1<<4) // MSM Function RST mode default value for pd_cmureg
21589     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREG_RST_SETVAL_O_SHIFT                        4
21590     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREGREF_RST_SETVAL_O                           (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
21591     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_CMUREGREF_RST_SETVAL_O_SHIFT                     5
21592     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_REF_RST_SETVAL_O                                 (0x1<<6) // MSM Function RST mode default value for pd_ref
21593     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_PD_REF_RST_SETVAL_O_SHIFT                           6
21594     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_CMU_FL_RST_SETVAL_O                           (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
21595     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X194_RESET_CMU_FL_RST_SETVAL_O_SHIFT                     7
21596 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195                                                         0x00330cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21597     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_RST_SETVAL_O                              (0x1<<0) // MSM Function RST mode default value for reset_cmu
21598     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_RST_SETVAL_O_SHIFT                        0
21599     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_GCRX_RST_SETVAL_O                         (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
21600     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMU_GCRX_RST_SETVAL_O_SHIFT                   1
21601     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREG_RST_SETVAL_O                           (0x1<<2) // MSM Function RST mode default value for reset_cmureg
21602     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREG_RST_SETVAL_O_SHIFT                     2
21603     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREGREF_RST_SETVAL_O                        (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
21604     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUREGREF_RST_SETVAL_O_SHIFT                  3
21605     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUSYNTH_RST_SETVAL_O                         (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
21606     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUSYNTH_RST_SETVAL_O_SHIFT                   4
21607     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUVCO_RST_SETVAL_O                           (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
21608     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_RESET_CMUVCO_RST_SETVAL_O_SHIFT                     5
21609     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LF_EXTZERO_ENA_RST_SETVAL_O                         (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
21610     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LF_EXTZERO_ENA_RST_SETVAL_O_SHIFT                   6
21611     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LFI_EXTZERO_RST_SETVAL_O                            (0x1<<7) // MSM Function RST mode default value for lfi_extzero
21612     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X195_LFI_EXTZERO_RST_SETVAL_O_SHIFT                      7
21613 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196                                                         0x003310UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21614     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_SOC_CLK_EN_RST_SETVAL_O                             (0x1<<0) // MSM Function RST mode default value for soc_clk_en
21615     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_SOC_CLK_EN_RST_SETVAL_O_SHIFT                       0
21616     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_REFCLK_EN_RST_SETVAL_O                              (0x1<<1) // MSM Function RST mode default value for refclk_en
21617     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_REFCLK_EN_RST_SETVAL_O_SHIFT                        1
21618     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PLL_LOCK_EN_RST_SETVAL_O                            (0x1<<2) // MSM Function RST mode default value for pll_lock_en
21619     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PLL_LOCK_EN_RST_SETVAL_O_SHIFT                      2
21620     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_TXCLK_RST_SETVAL_O                            (0x1<<3) // Not used
21621     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_TXCLK_RST_SETVAL_O_SHIFT                      3
21622     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_CLKDIV_RST_SETVAL_O                           (0x1<<4) // Not used
21623     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_RESET_CLKDIV_RST_SETVAL_O_SHIFT                     4
21624     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_RST_SETVAL_O                              (0x1<<5) // Not used
21625     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_RST_SETVAL_O_SHIFT                        5
21626     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O                  (0x1<<6) // Not used
21627     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_SHIFT            6
21628     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O                 (0x1<<7) // Not used
21629     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_SHIFT           7
21630 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197                                                         0x003314UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21631     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_IDDQ_BIAS_NORM_SETVAL_O                             (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
21632     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_IDDQ_BIAS_NORM_SETVAL_O_SHIFT                       0
21633     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_BIAS_NORM_SETVAL_O                               (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
21634     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_BIAS_NORM_SETVAL_O_SHIFT                         1
21635     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O                   (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
21636     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_SHIFT             2
21637     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMU_NORM_SETVAL_O                                (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
21638     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMU_NORM_SETVAL_O_SHIFT                          3
21639     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREG_NORM_SETVAL_O                             (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
21640     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREG_NORM_SETVAL_O_SHIFT                       4
21641     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREGREF_NORM_SETVAL_O                          (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
21642     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_CMUREGREF_NORM_SETVAL_O_SHIFT                    5
21643     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_REF_NORM_SETVAL_O                                (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
21644     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_PD_REF_NORM_SETVAL_O_SHIFT                          6
21645     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_CMU_FL_NORM_SETVAL_O                          (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
21646     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X197_RESET_CMU_FL_NORM_SETVAL_O_SHIFT                    7
21647 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198                                                         0x003318UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21648     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_NORM_SETVAL_O                             (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
21649     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_NORM_SETVAL_O_SHIFT                       0
21650     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_GCRX_NORM_SETVAL_O                        (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
21651     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMU_GCRX_NORM_SETVAL_O_SHIFT                  1
21652     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREG_NORM_SETVAL_O                          (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
21653     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREG_NORM_SETVAL_O_SHIFT                    2
21654     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREGREF_NORM_SETVAL_O                       (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
21655     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUREGREF_NORM_SETVAL_O_SHIFT                 3
21656     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUSYNTH_NORM_SETVAL_O                        (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
21657     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUSYNTH_NORM_SETVAL_O_SHIFT                  4
21658     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUVCO_NORM_SETVAL_O                          (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
21659     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_RESET_CMUVCO_NORM_SETVAL_O_SHIFT                    5
21660     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LF_EXTZERO_ENA_NORM_SETVAL_O                        (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
21661     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_SHIFT                  6
21662     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LFI_EXTZERO_NORM_SETVAL_O                           (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
21663     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X198_LFI_EXTZERO_NORM_SETVAL_O_SHIFT                     7
21664 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199                                                         0x00331cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21665     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_SOC_CLK_EN_NORM_SETVAL_O                            (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
21666     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_SOC_CLK_EN_NORM_SETVAL_O_SHIFT                      0
21667     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_REFCLK_EN_NORM_SETVAL_O                             (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
21668     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_REFCLK_EN_NORM_SETVAL_O_SHIFT                       1
21669     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PLL_LOCK_EN_NORM_SETVAL_O                           (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
21670     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PLL_LOCK_EN_NORM_SETVAL_O_SHIFT                     2
21671     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_TXCLK_NORM_SETVAL_O                           (0x1<<3) // Not used
21672     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_TXCLK_NORM_SETVAL_O_SHIFT                     3
21673     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_CLKDIV_NORM_SETVAL_O                          (0x1<<4) // Not used
21674     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_RESET_CLKDIV_NORM_SETVAL_O_SHIFT                    4
21675     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_NORM_SETVAL_O                             (0x1<<5) // Not used
21676     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_NORM_SETVAL_O_SHIFT                       5
21677     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O                 (0x1<<6) // Not used
21678     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_SHIFT           6
21679     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O                (0x1<<7) // Not used
21680     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_SHIFT          7
21681 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200                                                         0x003320UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21682     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_IDDQ_BIAS_PD_SETVAL_O                               (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
21683     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_IDDQ_BIAS_PD_SETVAL_O_SHIFT                         0
21684     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_BIAS_PD_SETVAL_O                                 (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
21685     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_BIAS_PD_SETVAL_O_SHIFT                           1
21686     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O                     (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
21687     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_SHIFT               2
21688     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMU_PD_SETVAL_O                                  (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
21689     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMU_PD_SETVAL_O_SHIFT                            3
21690     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREG_PD_SETVAL_O                               (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
21691     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREG_PD_SETVAL_O_SHIFT                         4
21692     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREGREF_PD_SETVAL_O                            (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
21693     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_CMUREGREF_PD_SETVAL_O_SHIFT                      5
21694     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_REF_PD_SETVAL_O                                  (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
21695     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_PD_REF_PD_SETVAL_O_SHIFT                            6
21696     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_CMU_FL_PD_SETVAL_O                            (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
21697     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X200_RESET_CMU_FL_PD_SETVAL_O_SHIFT                      7
21698 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201                                                         0x003324UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21699     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_PD_SETVAL_O                               (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
21700     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_PD_SETVAL_O_SHIFT                         0
21701     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_GCRX_PD_SETVAL_O                          (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
21702     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMU_GCRX_PD_SETVAL_O_SHIFT                    1
21703     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREG_PD_SETVAL_O                            (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
21704     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREG_PD_SETVAL_O_SHIFT                      2
21705     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREGREF_PD_SETVAL_O                         (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
21706     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUREGREF_PD_SETVAL_O_SHIFT                   3
21707     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUSYNTH_PD_SETVAL_O                          (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
21708     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUSYNTH_PD_SETVAL_O_SHIFT                    4
21709     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUVCO_PD_SETVAL_O                            (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
21710     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_RESET_CMUVCO_PD_SETVAL_O_SHIFT                      5
21711     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LF_EXTZERO_ENA_PD_SETVAL_O                          (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
21712     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LF_EXTZERO_ENA_PD_SETVAL_O_SHIFT                    6
21713     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LFI_EXTZERO_PD_SETVAL_O                             (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
21714     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X201_LFI_EXTZERO_PD_SETVAL_O_SHIFT                       7
21715 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202                                                         0x003328UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21716     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_SOC_CLK_EN_PD_SETVAL_O                              (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
21717     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_SOC_CLK_EN_PD_SETVAL_O_SHIFT                        0
21718     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_REFCLK_EN_PD_SETVAL_O                               (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
21719     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_REFCLK_EN_PD_SETVAL_O_SHIFT                         1
21720     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PLL_LOCK_EN_PD_SETVAL_O                             (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
21721     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PLL_LOCK_EN_PD_SETVAL_O_SHIFT                       2
21722     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_TXCLK_PD_SETVAL_O                             (0x1<<3) // Not used
21723     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_TXCLK_PD_SETVAL_O_SHIFT                       3
21724     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_CLKDIV_PD_SETVAL_O                            (0x1<<4) // Not used
21725     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_RESET_CLKDIV_PD_SETVAL_O_SHIFT                      4
21726     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_PD_SETVAL_O                               (0x1<<5) // Not used
21727     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_PD_SETVAL_O_SHIFT                         5
21728     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O                   (0x1<<6) // Not used
21729     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_SHIFT             6
21730     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O                  (0x1<<7) // Not used
21731     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_SHIFT            7
21732 #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X210                                                         0x003348UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21733     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X210_UNUSED_0                                            (0x7f<<0) // reserved
21734     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X210_UNUSED_0_SHIFT                                      0
21735     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X210_RESERVEDFIELD31                                     (0x1<<7) // Reserved
21736     #define PHY_SGMII_IP_REG_AHB_CMU1_CSR_6_X210_RESERVEDFIELD31_SHIFT                               7
21737 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0                                                             0x000000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21738     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_SOC0_DIV_O                                              (0xf<<0) // Static divider control for SOC0 The only access to this divider. Not an override
21739     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_SOC0_DIV_O_SHIFT                                        0
21740     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_SOC1_DIV_O                                              (0xf<<4) // Static divider control for SOC1 The only access to this divider. Not an override
21741     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X0_SOC1_DIV_O_SHIFT                                        4
21742 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1                                                             0x000004UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21743     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_CK_SOC_DIV_OVR_O_2_0                                    (0x7<<0) // Override for Primary IO: ck_soc_div_i [1:0] [2] - active high, Override Enable [1:0] - Override for pins ck_soc_div_i [1:0]
21744     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_CK_SOC_DIV_OVR_O_2_0_SHIFT                              0
21745     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O                                    (0x3<<3) // Divider for pma_cm_ref_clk
21746     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_PMA_CM_REF_CLK_DIV_O_SHIFT                              3
21747     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_GCFSM_CLK_DIV_O                                         (0x3<<5) // Static divider control for CMU GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
21748     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_GCFSM_CLK_DIV_O_SHIFT                                   5
21749     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O                               (0x1<<7) // Reference clock select override value for burn_in mode. This override is enabled by primary input pin burn_in_i
21750     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X1_BURNIN_REF_LIFE_CLK_SEL_O_SHIFT                         7
21751 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2                                                             0x000008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21752     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_SSC_CLK_DIV_O                                           (0x7<<0) // Static divider control for the SSC block The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /4 4?d3:  /8:
21753     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_SSC_CLK_DIV_O_SHIFT                                     0
21754     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0                                    (0x7<<3) // Selects one lane's recovered byte clock of all existing lanes, which goes to refclk buffer.
21755     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFCLK_SEL_O_2_0_SHIFT                              3
21756     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFDIV_O_1_0                                        (0x3<<6) // CDR "Ref" clock into CMU divider. 0 - no div, 1/2 - div by 2, 3 - div by 4
21757     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X2_CDR_REFDIV_O_1_0_SHIFT                                  6
21758 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X3                                                             0x00000cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21759     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X3_AHB_PMA_CM_DIVNSEL_6_0_O                                (0x7f<<0) // CMU N-divider setting
21760     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X3_AHB_PMA_CM_DIVNSEL_6_0_O_SHIFT                          0
21761     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X3_UNUSED_0                                                (0x1<<7) // reserved
21762     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X3_UNUSED_0_SHIFT                                          7
21763 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X4                                                             0x000010UL //Access:RW   DataWidth:0x8   CMU FL LDHS count value  Chips: K2
21764 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5                                                             0x000014UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21765     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_FL_LDHS_9_8_O                                (0x3<<0) // CMU FL LDHS count value
21766     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_FL_LDHS_9_8_O_SHIFT                          0
21767     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O                            (0x1<<2) // CMU reference div2 enable
21768     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PLL_REFDIV2_ENA_O_SHIFT                      2
21769     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O                                (0x1<<3) // CMU FL prediv4 enable
21770     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_PREDIV4_ENA_O_SHIFT                          3
21771     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O                        (0x1<<4) // Reference clock startup deglitch circuit disable
21772     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_AHB_PMA_CM_REFCLK_DEGLITCH_DIS_O_SHIFT                  4
21773     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_UNUSED_0                                                (0x7<<5) // reserved
21774     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X5_UNUSED_0_SHIFT                                          5
21775 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X6                                                             0x000018UL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
21776 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X7                                                             0x00001cUL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
21777 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X8                                                             0x000020UL //Access:RW   DataWidth:0x8   CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal  Chips: K2
21778 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X9                                                             0x000024UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21779     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X9_GCFSM_OVR_O_27_24                                       (0xf<<0) // CMU GCFSM Output Overrides for the following functions: [27] - active high, Override Enable [26]  - GCFSM Request flag [25:24] - GCFSM Function [23:0] - GCFSM Control Signal
21780     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X9_GCFSM_OVR_O_27_24_SHIFT                                 0
21781     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X9_UNUSED_0                                                (0xf<<4) // reserved
21782     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X9_UNUSED_0_SHIFT                                          4
21783 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X10                                                            0x000028UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
21784 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X11                                                            0x00002cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
21785 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X12                                                            0x000030UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
21786 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X13                                                            0x000034UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
21787 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X14                                                            0x000038UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
21788 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X15                                                            0x00003cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
21789 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X16                                                            0x000040UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
21790 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X17                                                            0x000044UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
21791 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X18                                                            0x000048UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
21792 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X19                                                            0x00004cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
21793 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X20                                                            0x000050UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
21794 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X21                                                            0x000054UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
21795 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X22                                                            0x000058UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
21796 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X23                                                            0x00005cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
21797 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X24                                                            0x000060UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
21798 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X25                                                            0x000064UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
21799 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26                                                            0x000068UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21800     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O                                 (0x1<<0) // GCFSM output override enable
21801     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_OUT_OVR_EN_O_SHIFT                           0
21802     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0                           (0x7f<<1) // GCFSM pma_data_o override
21803     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X26_GCFSM_CMU_PMA_DATA_OVR_O_6_0_SHIFT                     1
21804 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27                                                            0x00006cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21805     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7                          (0x1f<<0) // GCFSM pma_data_o override
21806     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_DATA_OVR_O_11_7_SHIFT                    0
21807     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O                              (0x1<<5) // GCFSM pma_latch_o override
21808     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_LATCH_OVR_O_SHIFT                        5
21809     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O                                 (0x1<<6) // GCFSM pma_go_o override
21810     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_GO_OVR_O_SHIFT                           6
21811     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O                               (0x1<<7) // GCFSM pma_read_o override
21812     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X27_GCFSM_CMU_PMA_READ_OVR_O_SHIFT                         7
21813 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X28                                                            0x000070UL //Access:RW   DataWidth:0x8   GCFSM pma_cal_o override  Chips: K2
21814 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X29                                                            0x000074UL //Access:RW   DataWidth:0x8   GCFSM pma_cal_o override  Chips: K2
21815 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30                                                            0x000078UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21816     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O                           (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable
21817     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_SOC_CLK_EN_OUT_OVR_O_SHIFT                     0
21818     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O                           (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - REF clock output enable
21819     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_REF_CLK_EN_OUT_OVR_O_SHIFT                     2
21820     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_LOCK_EN_OUT_OVR_O                              (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LOCK output enable
21821     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_LOCK_EN_OUT_OVR_O_SHIFT                        4
21822     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O                          (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU
21823     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X30_MSM_CMU_PMA_RST_CMU_OUT_OVR_O_SHIFT                    6
21824 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31                                                            0x00007cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21825     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O                       (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - SOC clock output enable - switches to SOC from life clock
21826     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUREG_OUT_OVR_O_SHIFT                 0
21827     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O                     (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU SYNTH
21828     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUSYNTH_OUT_OVR_O_SHIFT               2
21829     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O                       (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU VC0
21830     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_RST_CMUVCO_OUT_OVR_O_SHIFT                 4
21831     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O                        (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - IDDQ BIAS
21832     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X31_MSM_CMU_PMA_IDDQ_BIAS_OUT_OVR_O_SHIFT                  6
21833 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32                                                            0x000080UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21834     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O                          (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD BIAS
21835     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_BIAS_OUT_OVR_O_SHIFT                    0
21836     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O                           (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU
21837     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMU_OUT_OVR_O_SHIFT                     2
21838     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O                        (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REG
21839     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_CMUREG_OUT_OVR_O_SHIFT                  4
21840     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O                           (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD REF OUT
21841     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X32_MSM_CMU_PMA_PD_REF_OUT_OVR_O_SHIFT                     6
21842 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33                                                            0x000084UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21843     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O                  (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PCS CLK ENA
21844     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RESET_TXCLK_PCS_CLK_OVR_O_SHIFT            0
21845     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O                       (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU FL
21846     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_FL_OUT_OVR_O_SHIFT                 2
21847     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O                     (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU GCRX
21848     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_CMU_PMA_RST_CMU_GCRX_OUT_OVR_O_SHIFT               4
21849     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O                       (0x3<<6) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LF EXTZERO ENA
21850     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X33_MSM_PMA_LF_EXTZERO_ENA_OUT_OVR_O_SHIFT                 6
21851 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34                                                            0x000088UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21852     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O                      (0x3<<0) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - LFI EXTZERO ENA
21853     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_LFI_EXTZERO_OUT_OVR_O_SHIFT                0
21854     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O                     (0x3<<2) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - PD CMU REGREF
21855     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_CMU_PMA_PD_CMUREGREF_OUT_OVR_O_SHIFT               2
21856     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O                      (0x3<<4) // MFSM Output Overrides for the following functions:                  [0] - active high, Override Enable [1] - RESET CMU REGREF
21857     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_MSM_PMA_RESET_CMUREGREF_OUT_OVR_O_SHIFT                4
21858     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_UNUSED_0                                               (0x3<<6) // reserved
21859     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X34_UNUSED_0_SHIFT                                         6
21860 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X56                                                            0x0000e0UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21861 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X57                                                            0x0000e4UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21862 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X58                                                            0x0000e8UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21863 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X59                                                            0x0000ecUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21864 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X60                                                            0x0000f0UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21865 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X61                                                            0x0000f4UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21866 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X62                                                            0x0000f8UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21867 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X63                                                            0x0000fcUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21868 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X64                                                            0x000100UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21869 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X65                                                            0x000104UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21870 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X66                                                            0x000108UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21871 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X67                                                            0x00010cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21872 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X68                                                            0x000110UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21873 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X69                                                            0x000114UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21874 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X70                                                            0x000118UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21875 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X71                                                            0x00011cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21876 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X72                                                            0x000120UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21877 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X73                                                            0x000124UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21878 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X74                                                            0x000128UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21879 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X75                                                            0x00012cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21880 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X76                                                            0x000130UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21881 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X77                                                            0x000134UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21882 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X78                                                            0x000138UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21883 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X79                                                            0x00013cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21884 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X80                                                            0x000140UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21885 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X81                                                            0x000144UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21886 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X82                                                            0x000148UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21887 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X83                                                            0x00014cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21888 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X84                                                            0x000150UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21889 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X85                                                            0x000154UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21890 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X86                                                            0x000158UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21891 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X87                                                            0x00015cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21892 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X88                                                            0x000160UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21893 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X89                                                            0x000164UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21894 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X90                                                            0x000168UL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21895 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X91                                                            0x00016cUL //Access:RW   DataWidth:0x8   MSM Function Data Bus slice  Chips: K2
21896 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92                                                            0x000170UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21897     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_MSM_FUNC_DATA_O_289_288                                (0x3<<0) // MSM Function Data Bus slice
21898     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_MSM_FUNC_DATA_O_289_288_SHIFT                          0
21899     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_MSM_IN_OVR_O_5_0                                       (0x3f<<2) // Override for MFSM inputs [5] - active high, override enable [4] - MFSM request flag override [3:0] - MFSM function override
21900     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X92_MSM_IN_OVR_O_5_0_SHIFT                                 2
21901 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X93                                                            0x000174UL //Access:RW   DataWidth:0x8   Number of reference clock cycles to count after qsample is ok, before PLL is declared locked  Chips: K2
21902 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94                                                            0x000178UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21903     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_NUM_CYCLES_O_9_8                              (0x3<<0) // Number of reference clock cycles to count after qsample is ok, before PLL is declared locked
21904     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_NUM_CYCLES_O_9_8_SHIFT                        0
21905     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O                                  (0x1<<2) // State of qsample for PLL to be considered locked
21906     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_GOOD_STATE_O_SHIFT                            2
21907     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O                                         (0x7<<3) // Overrides for PLL lock signals [2] - Active high, override enable [1] - PLL ok override, bypasses ref clock cycle count after qsample is ok [0] - Qsample override
21908     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_PLL_CTRL_OVR_O_SHIFT                                   3
21909     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_UNUSED_0                                               (0x3<<6) // reserved
21910     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X94_UNUSED_0_SHIFT                                         6
21911 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95                                                            0x00017cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21912     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_KVCO_SEL_O                                (0x3<<0) // CMU VCO integral path gain
21913     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_KVCO_SEL_O_SHIFT                          0
21914     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_FORCE_ILF_O                                 (0x3<<2) // CMU loop filter force to common mode
21915     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_FORCE_ILF_O_SHIFT                           2
21916     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_CP_SEL_O                                  (0x3<<4) // Charge pump current gain select.
21917     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_CP_SEL_O_SHIFT                            4
21918     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O                                     (0x1<<6) // CMU PLL HIZ setting
21919     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_I_HIZ_O_SHIFT                               6
21920     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O                                    (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
21921     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X95_AHB_PMA_CM_C1_SEL_O_SHIFT                              7
21922 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96                                                            0x000180UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21923     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_P_CAP_SEL_O                                 (0x7<<0) // CMU VCO proportional path cap select
21924     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_P_CAP_SEL_O_SHIFT                           0
21925     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O                           (0x1<<3) // Charge pump chop enable
21926     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_CHPMP_CHOP_ENAN_O_SHIFT                     3
21927     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_I_CAP_SEL_O                                 (0x7<<4) // CMU VCO integral path cap select
21928     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_I_CAP_SEL_O_SHIFT                           4
21929     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O                               (0x1<<7) // Bandgap startup circuit bypass
21930     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X96_AHB_PMA_CM_BGSTART_BYP_O_SHIFT                         7
21931 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97                                                            0x000184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21932     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VCO_BIAS_O                                  (0xf<<0) // CMU VCO bias current setting.
21933     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VCO_BIAS_O_SHIFT                            0
21934     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREG_O                                      (0x3<<4) // CMU VREG setting
21935     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREG_O_SHIFT                                4
21936     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREGH_O                                     (0x3<<6) // CMU VREGH setting
21937     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X97_AHB_PMA_CM_VREGH_O_SHIFT                               6
21938 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98                                                            0x000188UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21939     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O                              (0x1<<0) // Force PFD to output down
21940     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_DN_O_SHIFT                        0
21941     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O                              (0x1<<1) // Force PFD to output up
21942     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PFD_FORCE_UP_O_SHIFT                        1
21943     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O                                      (0x1<<2) // Override enable for overriding N-div value
21944     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_SR_NDIV_OVR_ENA_O_SHIFT                                2
21945     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O                          (0x1<<3) // CMU V2I filter enable
21946     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_V2I_FILTER_SW_ON_O_SHIFT                    3
21947     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O                    (0x1<<4) // CMU VCO PMOS proportional current increase
21948     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_O_SHIFT              4
21949     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O                    (0x1<<5) // CMU VCO PMOS proportional current decrease
21950     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_O_SHIFT              5
21951     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_VREGREF_O                                   (0x3<<6) // CMU reference clock regulator setting
21952     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X98_AHB_PMA_CM_VREGREF_O_SHIFT                             6
21953 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X99                                                            0x00018cUL //Access:RW   DataWidth:0x8   CMU AFE spares  Chips: K2
21954 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100                                                           0x000190UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21955     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_PFD_PW_O                                   (0x3<<0) // PFD pulse width setting
21956     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_PFD_PW_O_SHIFT                             0
21957     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O                                  (0x1<<2) // Enable to reduce charge pump reference current
21958     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_I_DROPI_O_SHIFT                            2
21959     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O                               (0x1f<<3) // CMU PLL KVCO setting
21960     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X100_AHB_PMA_CM_P_KVCO_SEL_O_SHIFT                         3
21961 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X101                                                           0x000194UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21962     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X101_AHB_PMA_CM_DIVPSEL_O                                  (0x7f<<0) // CMU P-divider setting
21963     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X101_AHB_PMA_CM_DIVPSEL_O_SHIFT                            0
21964     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X101_UNUSED_0                                              (0x1<<7) // reserved
21965     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X101_UNUSED_0_SHIFT                                        7
21966 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102                                                           0x000198UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21967     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_O                                    (0x7<<0) // AHB override for calibrated VCOFR value.
21968     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_O_SHIFT                              0
21969     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O                                (0x1<<3) // Override enable for overriding VCOFR value
21970     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_AHB_PMA_CM_VCOFR_SEL_O_SHIFT                          3
21971     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_UNUSED_0                                              (0xf<<4) // reserved
21972     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X102_UNUSED_0_SHIFT                                        4
21973 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108                                                           0x0001b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21974     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_UNUSED_0                                              (0x7<<0) // reserved
21975     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_UNUSED_0_SHIFT                                        0
21976     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0                           (0xf<<3) // Reference clock output select
21977     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_OUTPUT_SEL_O_3_0_SHIFT                     3
21978     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O                                  (0x1<<7) // Reference clock select override
21979     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X108_PMA_REFCLK_SEL_OVR_O_SHIFT                            7
21980 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109                                                           0x0001b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
21981     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O                                     (0x1<<0) // Override for primary IO: refclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
21982     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_L_O_SHIFT                               0
21983     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O                                     (0x1<<1) // "Override for primary IO: refclk_oe_r_i Enabled by pma_refclk_sel_ovr_o"
21984     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_OE_R_O_SHIFT                               1
21985     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O                                      (0x1<<2) // "Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o"
21986     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_L_O_SHIFT                                2
21987     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O                                      (0x1<<3) // Override for primary IO: rxclk_oe_l_i Enabled by pma_refclk_sel_ovr_o
21988     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_RXCLK_OE_R_O_SHIFT                                3
21989     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O                                     (0x1<<4) // Enable additonal LF cap for 2.5V/3.3V process
21990     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_CM_HV2P5SEL_O_SHIFT                               4
21991     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_UNUSED_0                                              (0x1<<5) // reserved
21992     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_UNUSED_0_SHIFT                                        5
21993     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O                                   (0x1<<6) // Override for primary IO: refclk_qfwd_l_i Enabled by pma_refclk_sel_ovr_o
21994     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_L_O_SHIFT                             6
21995     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O                                   (0x1<<7) // Override for primary IO: refclk_qfwd_r_i Enabled by pma_refclk_sel_ovr_o
21996     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X109_PMA_REFCLK_QFWD_R_O_SHIFT                             7
21997 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X110                                                           0x0001b8UL //Access:RW   DataWidth:0x8   Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode  Chips: K2
21998 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X111                                                           0x0001bcUL //Access:RW   DataWidth:0x8   Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode  Chips: K2
21999 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112                                                           0x0001c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22000     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_FCNTL_O_19_16                                     (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode
22001     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_FCNTL_O_19_16_SHIFT                               0
22002     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O                                          (0x1<<4) // Active high Enable for SSC generator SSC mode
22003     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_GEN_EN_O_SHIFT                                    4
22004     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O                                              (0x1<<5) // Active high Enable for SSC block synth or SSC mode
22005     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_SSC_EN_O_SHIFT                                        5
22006     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_UNUSED_0                                              (0x3<<6) // reserved
22007     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X112_UNUSED_0_SHIFT                                        6
22008 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X113                                                           0x0001c4UL //Access:RW   DataWidth:0x8   SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz  Chips: K2
22009 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X114                                                           0x0001c8UL //Access:RW   DataWidth:0x8   SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz  Chips: K2
22010 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115                                                           0x0001ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22011     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_MATCH_VAL_O_19_16                             (0xf<<0) // SSC match value for Spread Spectrum Generation mode. Represents the magntude of maximum frequency deviation from the offset. Referes to the SSC word, not actual frequency in Hz
22012     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_MATCH_VAL_O_19_16_SHIFT                       0
22013     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O                                  (0x1<<4) // Enable for SSC generator with Fractional Synthesis
22014     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_FRACSYN_EN_O_SHIFT                            4
22015     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O                                (0x1<<5) // Enable fractional division mode and SSC mode
22016     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_EN_FRACN_FRCDIV_MODE_O_SHIFT                          5
22017     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O                                   (0x1<<6) // Enable in SSC_GEN mode for upwards and downwards spreading. 0- downspread only, 1 -up and down spreading
22018     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_SSC_GEN_UPDOWN_EN_O_SHIFT                             6
22019     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_UNUSED_0                                              (0x1<<7) // reserved
22020     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X115_UNUSED_0_SHIFT                                        7
22021 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X116                                                           0x0001d0UL //Access:RW   DataWidth:0x8   In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word  Chips: K2
22022 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X117                                                           0x0001d4UL //Access:RW   DataWidth:0x8   In Spread Spectrum Generation mode, represents the magnitude of the incremental step in the SSC word  Chips: K2
22023 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118                                                           0x0001d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22024     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_IN_O                                    (0xf<<0) // Test input bus
22025     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_IN_O_SHIFT                              0
22026     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_CTRL_O                                  (0x3<<4) // Test i/p control source :  0-modulator  1-bypass modulator  2-modulator  3-sr_txt_in_i
22027     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_MOD_TST_CTRL_O_SHIFT                            4
22028     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O                               (0x1<<6) // Clock Select for High Speed clock source :  0-clk_hs_fbk  1-clk_hs_refout
22029     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_SRC_SEL_O_SHIFT                         6
22030     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O                               (0x1<<7) // Clock divider for High Speed clock source
22031     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X118_FRACN_FBK_CLK_DIV_SEL_O_SHIFT                         7
22032 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119                                                           0x0001dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22033     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0                            (0x1f<<0) // override for the counter value
22034     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_O_4_0_SHIFT                      0
22035     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O                            (0x1<<5) // CMU Temperature Calibration Polling Enable: enables the periodic polling and counter adjustment
22036     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLL_EN_O_SHIFT                      5
22037     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O                           (0x1<<6) // chicken bit for counter polarity
22038     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_POLARITY_O_SHIFT                     6
22039     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O                             (0x1<<7) // override enable to use above value
22040     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X119_AHB_CMU_TEMP_CAL_OVR_EN_O_SHIFT                       7
22041 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X120                                                           0x0001e0UL //Access:RW   DataWidth:0x8   Divider input for Div-by-N counter  Chips: K2
22042 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X121                                                           0x0001e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22043     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8                       (0x7f<<0) // Divider input for Div-by-N counter
22044     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X121_AHB_CMU_TEMP_CAL_CLK_DIV_O_14_8_SHIFT                 0
22045     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X121_UNUSED_0                                              (0x1<<7) // reserved
22046     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X121_UNUSED_0_SHIFT                                        7
22047 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122                                                           0x0001e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22048     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_O                              (0x1f<<0) // Refclk Termination override value
22049     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_O_SHIFT                        0
22050     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O                           (0x1<<5) // Refclk Termination override enable
22051     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_PMA_CM_REFCLK_TERM_OVR_EN_O_SHIFT                     5
22052     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_UNUSED_0                                              (0x3<<6) // reserved
22053     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X122_UNUSED_0_SHIFT                                        6
22054 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123                                                           0x0001ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22055     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_O                                  (0x1f<<0) // Rx Termination override value, every rx lane gets the same value
22056     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_O_SHIFT                            0
22057     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O                               (0x1<<5) // Rx Termination override enable
22058     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_PMA_CM_RX_TERM_OVR_EN_O_SHIFT                         5
22059     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_UNUSED_0                                              (0x3<<6) // reserved
22060     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X123_UNUSED_0_SHIFT                                        6
22061 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X124                                                           0x0001f0UL //Access:RW   DataWidth:0x8   In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  Chips: K2
22062 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125                                                           0x0001f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22063     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8                              (0x1<<0) // In txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator
22064     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_UP_8_SHIFT                        0
22065     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE                            (0x7<<1) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
22066     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_WAIT_NEXT_SAMPLE_SHIFT                      1
22067     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_UP_NUM_SAMPLES                              (0xf<<4) // in txterm calibration, the number of samples to take from the same comparator
22068     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X125_AHB_RX_TC_UP_NUM_SAMPLES_SHIFT                        4
22069 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126                                                           0x0001f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22070     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR                                  (0x1<<0) // Debug feature, when set forces circuit RX termination calibration circuit to be enabled allowing ahb_tx_tc_bias_ovr to take effect
22071     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_GC_TCCAL_ENA_OVR_SHIFT                            0
22072     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR                                    (0x7<<1) // Bit 3:1 RX termination calibration DAC override setting
22073     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_AHB_RX_TC_BIAS_OVR_SHIFT                              1
22074     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_UNUSED_0                                              (0xf<<4) // reserved
22075     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X126_UNUSED_0_SHIFT                                        4
22076 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127                                                           0x0001fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22077     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O                                      (0x1<<0) // Master reset for CMU
22078     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_CMU_MASTER_CDN_O_SHIFT                                0
22079     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O                                            (0x3<<1) // Determines rate for PLL clock pcs_rate_o[0] :      0: VCO clock untouched      1: VCO clock divided by 2                                                 pcs_rate_o[1] :      0: PMA operates in 10b/20b mode Enables %5 circuit      1: PMA operates in 8b/16b mode   Enables %4 circuit
22080     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_PCS_RATE_O_SHIFT                                      1
22081     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_UNUSED_0                                              (0x1f<<3) // reserved
22082     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X127_UNUSED_0_SHIFT                                        3
22083 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X128                                                           0x000200UL //Access:RW   DataWidth:0x8   Not used  Chips: K2
22084 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129                                                           0x000204UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22085     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_CMU_IN_OVR_O_3_0                                      (0xf<<0) // Override for following CMU Control Signals [2] - active high, override enable [1] - CMU Powerdown Pin IO [0] - CMU Reset Pin IO
22086     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_CMU_IN_OVR_O_3_0_SHIFT                                0
22087     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_CMU_OUT_OVR_O_1_0                                     (0x3<<4) // Override for Reset_smu_fl
22088     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_CMU_OUT_OVR_O_1_0_SHIFT                               4
22089     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_UNUSED_0                                              (0x3<<6) // reserved
22090     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X129_UNUSED_0_SHIFT                                        6
22091 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130                                                           0x000208UL //Access:R    DataWidth:0x8   Snapshot of digital test bus data [7:0]  Chips: K2
22092 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131                                                           0x00020cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
22093     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_TBUS_DATA_SMPL_11_8                                   (0xf<<0) // Snapshot of digital test bus data [11:8]
22094     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_TBUS_DATA_SMPL_11_8_SHIFT                             0
22095     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_UNUSED_0                                              (0xf<<4) // reserved
22096     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_UNUSED_0_SHIFT                                        4
22097 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132                                                           0x000210UL //Access:RW   DataWidth:0x8   CMU Test Bus address 7-0  Chips: K2
22098 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133                                                           0x000214UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22099     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_TBUS_ADDR_OVR_O_10_8                                  (0x7<<0) // CMU Test Bus address 10-8
22100     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_TBUS_ADDR_OVR_O_10_8_SHIFT                            0
22101     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_UNUSED_0                                              (0x1f<<3) // reserved
22102     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_UNUSED_0_SHIFT                                        3
22103 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X134                                                           0x000218UL //Access:RW   DataWidth:0x8   Not used  Chips: K2
22104 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135                                                           0x00021cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22105     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_PMA_CM_REF_CLK_DIV_O                             (0x3<<0) // "Divider for pma_cm_ref_clk in gen3 rate. Used only in PCIe3 1CMU config"
22106     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_PMA_CM_REF_CLK_DIV_O_SHIFT                       0
22107     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_GCFSM_CLK_DIV_O                                  (0x3<<2) // Static divider control for CMU GCFSM clock in gen3 rate The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4: Used only in PCIe3 1CMU config
22108     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_GCFSM_CLK_DIV_O_SHIFT                            2
22109     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_SSC_CLK_DIV_O                                    (0x7<<4) // Static divider control for the SSC clock in gen3 rate. The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /4 4?d3:  /8 Used only in PCIe3 1CMU config
22110     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_GEN3_SSC_CLK_DIV_O_SHIFT                              4
22111     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_UNUSED_0                                              (0x1<<7) // reserved
22112     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X135_UNUSED_0_SHIFT                                        7
22113 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136                                                           0x000220UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22114     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_GEN3_PCS_RATE_O                                       (0x3<<0) // Determines rate for PLL clock in gen3 rate pcs_rate_o[0] :      0: VCO clock untouched      1: VCO clock divided by 2                                                 pcs_rate_o[1] :      0: PMA operates in 10b/20b mode Enables %5 circuit      1: PMA operates in 8b/16b mode   Enables %4 circuit Used only in PCIe3 1CMU config
22115     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_GEN3_PCS_RATE_O_SHIFT                                 0
22116     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_EN_O                             (0x1<<2) // Override enable for overridng internal signal cmu_rate_is_gen3
22117     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_EN_O_SHIFT                       2
22118     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_O                                (0x1<<3) // Override for internal signal cmu_rate_is_gen3
22119     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_CMU_RATE_IS_GEN3_OVR_O_SHIFT                          3
22120     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_UNUSED_0                                              (0xf<<4) // reserved
22121     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X136_UNUSED_0_SHIFT                                        4
22122 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137                                                           0x000224UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22123     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_KVCO_SEL_GEN3_O                          (0x3<<0) // CMU VCO proportional current gain
22124     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_KVCO_SEL_GEN3_O_SHIFT                    0
22125     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_FORCE_ILF_GEN3_O                           (0x3<<2) // CMU LF Force value in gen3 rate Used only in PCIe3 1CMU config
22126     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_FORCE_ILF_GEN3_O_SHIFT                     2
22127     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_CP_SEL_GEN3_O                            (0x3<<4) // Charge pump current gain select.
22128     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_CP_SEL_GEN3_O_SHIFT                      4
22129     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_HIZ_GEN3_O                               (0x1<<6) // CMU PLL HIZ setting in gen3 rate Used only in PCIe3 1CMU config
22130     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_I_HIZ_GEN3_O_SHIFT                         6
22131     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_C1_SEL_GEN3_O                              (0x1<<7) // CMU LF C1 cap select. Enabling increases C1 cap.
22132     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X137_AHB_PMA_CM_C1_SEL_GEN3_O_SHIFT                        7
22133 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138                                                           0x000228UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22134     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_P_CAP_SEL_GEN3_O                           (0x7<<0) // CMU VCO proportional path cap select
22135     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_P_CAP_SEL_GEN3_O_SHIFT                     0
22136     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O                     (0x1<<3) // Charge pump chop enable in gen3 rate Used only in PCIe3 1CMU config
22137     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_CHPMP_CHOP_ENAN_GEN3_O_SHIFT               3
22138     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_I_CAP_SEL_GEN3_O                           (0x7<<4) // CMU VCO integral path cap select
22139     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_I_CAP_SEL_GEN3_O_SHIFT                     4
22140     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_BGSTART_BYP_GEN3_O                         (0x1<<7) // Bandgap startup circuit bypass
22141     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X138_AHB_PMA_CM_BGSTART_BYP_GEN3_O_SHIFT                   7
22142 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139                                                           0x00022cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22143     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VCO_BIAS_GEN3_O                            (0xf<<0) // CMU VCO bias current setting
22144     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VCO_BIAS_GEN3_O_SHIFT                      0
22145     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VREG_GEN3_O                                (0x3<<4) // CMU VREG setting in gen3 rate Used only in PCIe3 1CMU config
22146     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VREG_GEN3_O_SHIFT                          4
22147     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VREGH_GEN3_O                               (0x3<<6) // CMU VREGH setting in gen3 rate Used only in PCIe3 1CMU config
22148     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X139_AHB_PMA_CM_VREGH_GEN3_O_SHIFT                         6
22149 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140                                                           0x000230UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22150     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_DN_GEN3_O                        (0x1<<0) // Force PFD to output down in gen3 rate Used only in PCIe3 1CMU config
22151     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_DN_GEN3_O_SHIFT                  0
22152     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_UP_GEN3_O                        (0x1<<1) // Force PFD to output up in gen3 rate Used only in PCIe3 1CMU config
22153     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PFD_FORCE_UP_GEN3_O_SHIFT                  1
22154     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_V2I_FILTER_SW_ON_GEN3_O                    (0x1<<2) // CMU V2I filter enable in gen3 rate Used only in PCIe3 1CMU config
22155     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_V2I_FILTER_SW_ON_GEN3_O_SHIFT              2
22156     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O              (0x1<<3) // CMU VCO PMOS proportional current increase
22157     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_MORE_EN_GEN3_O_SHIFT        3
22158     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_GEN3_O              (0x1<<4) // CMU VCO PMOS proportional current decrease
22159     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_PRP_DAC_DOWN_I_LESS_EN_GEN3_O_SHIFT        4
22160     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_VREGREF_GEN3_O                             (0x3<<5) // CMU VDREGREF setting
22161     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_AHB_PMA_CM_VREGREF_GEN3_O_SHIFT                       5
22162     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_UNUSED_0                                              (0x1<<7) // reserved
22163     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X140_UNUSED_0_SHIFT                                        7
22164 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X141                                                           0x000234UL //Access:RW   DataWidth:0x8   CMU AFE spares in gen3 rate Used only in PCIe3 1CMU config  Chips: K2
22165 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142                                                           0x000238UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22166     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_PFD_PW_GEN3_O                              (0x3<<0) // PFD pulse width setting in gen3 rate Used only in PCIe3 1CMU config
22167     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_PFD_PW_GEN3_O_SHIFT                        0
22168     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_I_DROPI_GEN3_O                             (0x1<<2) // Enable to reduce charge pump reference current
22169     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_I_DROPI_GEN3_O_SHIFT                       2
22170     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_P_KVCO_SEL_GEN3_O                          (0x1f<<3) // CMU PLL KVCO setting in gen3 rate Used only in PCIe3 1CMU config
22171     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X142_AHB_PMA_CM_P_KVCO_SEL_GEN3_O_SHIFT                    3
22172 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X143                                                           0x00023cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22173     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X143_AHB_PMA_CM_DIVPSEL_GEN3_O                             (0x7f<<0) // CMU P-divider setting in gen3 rate Used only in PCIe3 1CMU config
22174     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X143_AHB_PMA_CM_DIVPSEL_GEN3_O_SHIFT                       0
22175     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X143_UNUSED_0                                              (0x1<<7) // reserved
22176     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X143_UNUSED_0_SHIFT                                        7
22177 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144                                                           0x000240UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22178     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_VCOFR_GEN3_O                               (0x7<<0) // Override enable for overriding VCOFR value in gen3 rate Used only in PCIe3 1CMU config
22179     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_VCOFR_GEN3_O_SHIFT                         0
22180     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PLL_REFDIV2_ENA_GEN3_O                     (0x1<<3) // Not used
22181     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PLL_REFDIV2_ENA_GEN3_O_SHIFT               3
22182     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PREDIV4_ENA_GEN3_O                         (0x1<<4) // Not used
22183     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_PREDIV4_ENA_GEN3_O_SHIFT                   4
22184     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_UNUSED_0                                              (0x1<<5) // reserved
22185     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_UNUSED_0_SHIFT                                        5
22186     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_FL_LDHS_GEN3_9_8_O                         (0x3<<6) // Not used
22187     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X144_AHB_PMA_CM_FL_LDHS_GEN3_9_8_O_SHIFT                   6
22188 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X145                                                           0x000244UL //Access:RW   DataWidth:0x8   Not used  Chips: K2
22189 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X146                                                           0x000248UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22190     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X146_AHB_PMA_CM_DIVNSEL_GEN3_O                             (0x7f<<0) // Not used
22191     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X146_AHB_PMA_CM_DIVNSEL_GEN3_O_SHIFT                       0
22192     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X146_UNUSED_0                                              (0x1<<7) // reserved
22193     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X146_UNUSED_0_SHIFT                                        7
22194 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147                                                           0x00024cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22195     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O                      (0x7<<0) // wait multiplication factor for msm_cmu_databank
22196     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_AHB_CMU_PROG_MULT_REF_CLK_WAIT_O_SHIFT                0
22197     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_UNUSED_0                                              (0x1f<<3) // reserved
22198     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X147_UNUSED_0_SHIFT                                        3
22199 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X149                                                           0x000254UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22200     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X149_AHB_PMA_CM_EN_REGLN_O                                 (0xf<<0) // Not used
22201     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X149_AHB_PMA_CM_EN_REGLN_O_SHIFT                           0
22202     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X149_UNUSED_0                                              (0xf<<4) // reserved
22203     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X149_UNUSED_0_SHIFT                                        4
22204 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X150                                                           0x000258UL //Access:RW   DataWidth:0x8   Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config  Chips: K2
22205 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X151                                                           0x00025cUL //Access:RW   DataWidth:0x8   Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config  Chips: K2
22206 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X152                                                           0x000260UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22207     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X152_GEN3_SSC_FCNTL_O_19_16                                (0xf<<0) // Frequency offset control word for SSC in synth mode or SSC_GEN fracsyn_en mode in gen3 rate Used only in PCIe3 1CMU config
22208     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X152_GEN3_SSC_FCNTL_O_19_16_SHIFT                          0
22209     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X152_UNUSED_0                                              (0xf<<4) // reserved
22210     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X152_UNUSED_0_SHIFT                                        4
22211 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X153                                                           0x000264UL //Access:RW   DataWidth:0x8   Inverts up_i when set to 1  Chips: K2
22212 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X154                                                           0x000268UL //Access:RW   DataWidth:0x8   Inverts up_i when set to 1  Chips: K2
22213 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X161                                                           0x000284UL //Access:RW   DataWidth:0x8   Function info for each MSM function. Varies depending on function number. _13:06 - Address of first command to run _05:00 - Number of commands to run  Chips: K2
22214 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X162                                                           0x000288UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22215 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X163                                                           0x00028cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22216 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X164                                                           0x000290UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22217 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X165                                                           0x000294UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22218 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X166                                                           0x000298UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22219 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X167                                                           0x00029cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22220 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X168                                                           0x0002a0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22221 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X169                                                           0x0002a4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22222 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X170                                                           0x0002a8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22223 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X171                                                           0x0002acUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22224 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X172                                                           0x0002b0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22225 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X173                                                           0x0002b4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22226 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X174                                                           0x0002b8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22227 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X175                                                           0x0002bcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22228 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X176                                                           0x0002c0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22229 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X177                                                           0x0002c4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22230 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X178                                                           0x0002c8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22231 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X179                                                           0x0002ccUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22232 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X180                                                           0x0002d0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22233 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X181                                                           0x0002d4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22234 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X182                                                           0x0002d8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22235 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X183                                                           0x0002dcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22236 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X184                                                           0x0002e0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22237 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X185                                                           0x0002e4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22238 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X186                                                           0x0002e8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22239 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X187                                                           0x0002ecUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22240 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X188                                                           0x0002f0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
22241 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191                                                           0x0002fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22242     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O                               (0x1<<0) // MSM Function IDDQ mode default value for iddq_bias
22243     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_IDDQ_BIAS_IDDQ_SETVAL_O_SHIFT                         0
22244     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O                                 (0x1<<1) // MSM Function IDDQ mode default value for pd_bias
22245     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_BIAS_IDDQ_SETVAL_O_SHIFT                           1
22246     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O                     (0x1<<2) // MSM Function IDDQ mode default value for pcs_clk_ena
22247     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_TXCLK_PCS_CLK_IDDQ_SETVAL_O_SHIFT               2
22248     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O                                  (0x1<<3) // MSM Function IDDQ mode default value for pd_cmu
22249     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMU_IDDQ_SETVAL_O_SHIFT                            3
22250     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O                               (0x1<<4) // MSM Function IDDQ mode default value for pd_cmureg
22251     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREG_IDDQ_SETVAL_O_SHIFT                         4
22252     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O                            (0x1<<5) // MSM Function IDDQ mode default value for pd_cmuregref
22253     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_CMUREGREF_IDDQ_SETVAL_O_SHIFT                      5
22254     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O                                  (0x1<<6) // MSM Function IDDQ mode default value for pd_ref
22255     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_PD_REF_IDDQ_SETVAL_O_SHIFT                            6
22256     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O                            (0x1<<7) // MSM Function IDDQ mode default value for reset_cmu_fl
22257     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X191_RESET_CMU_FL_IDDQ_SETVAL_O_SHIFT                      7
22258 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192                                                           0x000300UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22259     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O                               (0x1<<0) // MSM Function IDDQ mode default value for reset_cmu
22260     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_IDDQ_SETVAL_O_SHIFT                         0
22261     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O                          (0x1<<1) // MSM Function IDDQ mode default value for reset_cmu_gcrx
22262     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMU_GCRX_IDDQ_SETVAL_O_SHIFT                    1
22263     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O                            (0x1<<2) // MSM Function IDDQ mode default value for reset_cmureg
22264     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREG_IDDQ_SETVAL_O_SHIFT                      2
22265     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O                         (0x1<<3) // MSM Function IDDQ mode default value for reset_cmuregref
22266     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUREGREF_IDDQ_SETVAL_O_SHIFT                   3
22267     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O                          (0x1<<4) // MSM Function IDDQ mode default value for reset_cmusynth
22268     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUSYNTH_IDDQ_SETVAL_O_SHIFT                    4
22269     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O                            (0x1<<5) // MSM Function IDDQ mode default value for reset_cmuvco
22270     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_RESET_CMUVCO_IDDQ_SETVAL_O_SHIFT                      5
22271     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O                          (0x1<<6) // MSM Function IDDQ mode default value for lf_extzero_ena
22272     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LF_EXTZERO_ENA_IDDQ_SETVAL_O_SHIFT                    6
22273     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O                             (0x1<<7) // MSM Function IDDQ mode default value for lfi_extzero
22274     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X192_LFI_EXTZERO_IDDQ_SETVAL_O_SHIFT                       7
22275 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193                                                           0x000304UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22276     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O                              (0x1<<0) // MSM Function IDDQ mode default value for soc_clk_en
22277     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_SOC_CLK_EN_IDDQ_SETVAL_O_SHIFT                        0
22278     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O                               (0x1<<1) // MSM Function IDDQ mode default value for refclk_en
22279     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_REFCLK_EN_IDDQ_SETVAL_O_SHIFT                         1
22280     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O                             (0x1<<2) // MSM Function IDDQ mode default value for pll_lock_en
22281     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PLL_LOCK_EN_IDDQ_SETVAL_O_SHIFT                       2
22282     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O                             (0x1<<3) // Not used
22283     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_TXCLK_IDDQ_SETVAL_O_SHIFT                       3
22284     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O                            (0x1<<4) // Not used
22285     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_RESET_CLKDIV_IDDQ_SETVAL_O_SHIFT                      4
22286     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O                               (0x1<<5) // Not used
22287     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_IDDQ_SETVAL_O_SHIFT                         5
22288     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O                   (0x1<<6) // Not used
22289     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_LEFT_IDDQ_SETVAL_O_SHIFT             6
22290     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O                  (0x1<<7) // Not used
22291     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X193_PD_CLKDIV_REFCLK_RIGHT_IDDQ_SETVAL_O_SHIFT            7
22292 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194                                                           0x000308UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22293     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O                                (0x1<<0) // MSM Function RST mode default value for iddq_bias
22294     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_IDDQ_BIAS_RST_SETVAL_O_SHIFT                          0
22295     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O                                  (0x1<<1) // MSM Function RST mode default value for pd_bias
22296     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_BIAS_RST_SETVAL_O_SHIFT                            1
22297     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O                      (0x1<<2) // MSM Function RST mode default value for pcs_clk_ena
22298     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_TXCLK_PCS_CLK_RST_SETVAL_O_SHIFT                2
22299     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O                                   (0x1<<3) // MSM Function RST mode default value for pd_cmu
22300     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMU_RST_SETVAL_O_SHIFT                             3
22301     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O                                (0x1<<4) // MSM Function RST mode default value for pd_cmureg
22302     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREG_RST_SETVAL_O_SHIFT                          4
22303     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O                             (0x1<<5) // MSM Function RST mode default value for pd_cmuregref
22304     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_CMUREGREF_RST_SETVAL_O_SHIFT                       5
22305     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O                                   (0x1<<6) // MSM Function RST mode default value for pd_ref
22306     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_PD_REF_RST_SETVAL_O_SHIFT                             6
22307     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O                             (0x1<<7) // MSM Function RST mode default value for reset_cmu_fl
22308     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X194_RESET_CMU_FL_RST_SETVAL_O_SHIFT                       7
22309 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195                                                           0x00030cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22310     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O                                (0x1<<0) // MSM Function RST mode default value for reset_cmu
22311     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_RST_SETVAL_O_SHIFT                          0
22312     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O                           (0x1<<1) // MSM Function RST mode default value for reset_cmu_gcrx
22313     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMU_GCRX_RST_SETVAL_O_SHIFT                     1
22314     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O                             (0x1<<2) // MSM Function RST mode default value for reset_cmureg
22315     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREG_RST_SETVAL_O_SHIFT                       2
22316     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O                          (0x1<<3) // MSM Function RST mode default value for reset_cmuregref
22317     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUREGREF_RST_SETVAL_O_SHIFT                    3
22318     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O                           (0x1<<4) // MSM Function RST mode default value for reset_cmusynth
22319     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUSYNTH_RST_SETVAL_O_SHIFT                     4
22320     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O                             (0x1<<5) // MSM Function RST mode default value for reset_cmuvco
22321     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_RESET_CMUVCO_RST_SETVAL_O_SHIFT                       5
22322     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O                           (0x1<<6) // MSM Function RST mode default value for lf_extzero_ena
22323     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LF_EXTZERO_ENA_RST_SETVAL_O_SHIFT                     6
22324     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O                              (0x1<<7) // MSM Function RST mode default value for lfi_extzero
22325     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X195_LFI_EXTZERO_RST_SETVAL_O_SHIFT                        7
22326 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196                                                           0x000310UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22327     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O                               (0x1<<0) // MSM Function RST mode default value for soc_clk_en
22328     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_SOC_CLK_EN_RST_SETVAL_O_SHIFT                         0
22329     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O                                (0x1<<1) // MSM Function RST mode default value for refclk_en
22330     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_REFCLK_EN_RST_SETVAL_O_SHIFT                          1
22331     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O                              (0x1<<2) // MSM Function RST mode default value for pll_lock_en
22332     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PLL_LOCK_EN_RST_SETVAL_O_SHIFT                        2
22333     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O                              (0x1<<3) // Not used
22334     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_TXCLK_RST_SETVAL_O_SHIFT                        3
22335     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O                             (0x1<<4) // Not used
22336     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_RESET_CLKDIV_RST_SETVAL_O_SHIFT                       4
22337     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O                                (0x1<<5) // Not used
22338     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_RST_SETVAL_O_SHIFT                          5
22339     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O                    (0x1<<6) // Not used
22340     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_LEFT_RST_SETVAL_O_SHIFT              6
22341     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O                   (0x1<<7) // Not used
22342     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X196_PD_CLKDIV_REFCLK_RIGHT_RST_SETVAL_O_SHIFT             7
22343 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197                                                           0x000314UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22344     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O                               (0x1<<0) // MSM Function NORMAL mode default value for iddq_bias
22345     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_IDDQ_BIAS_NORM_SETVAL_O_SHIFT                         0
22346     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O                                 (0x1<<1) // MSM Function NORMAL mode default value for pd_bias
22347     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_BIAS_NORM_SETVAL_O_SHIFT                           1
22348     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O                     (0x1<<2) // MSM Function NORMAL mode default value for pcs_clk_ena
22349     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_TXCLK_PCS_CLK_NORM_SETVAL_O_SHIFT               2
22350     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O                                  (0x1<<3) // MSM Function NORMAL mode default value for pd_cmu
22351     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMU_NORM_SETVAL_O_SHIFT                            3
22352     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O                               (0x1<<4) // MSM Function NORMAL mode default value for pd_cmureg
22353     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREG_NORM_SETVAL_O_SHIFT                         4
22354     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O                            (0x1<<5) // MSM Function NORMAL mode default value for pd_cmuregref
22355     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_CMUREGREF_NORM_SETVAL_O_SHIFT                      5
22356     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O                                  (0x1<<6) // MSM Function NORMAL mode default value for pd_ref
22357     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_PD_REF_NORM_SETVAL_O_SHIFT                            6
22358     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O                            (0x1<<7) // MSM Function NORMAL mode default value for reset_cmu_fl
22359     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X197_RESET_CMU_FL_NORM_SETVAL_O_SHIFT                      7
22360 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198                                                           0x000318UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22361     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O                               (0x1<<0) // MSM Function NORMAL mode default value for reset_cmu
22362     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_NORM_SETVAL_O_SHIFT                         0
22363     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O                          (0x1<<1) // MSM Function NORMAL mode default value for reset_cmu_gcrx
22364     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMU_GCRX_NORM_SETVAL_O_SHIFT                    1
22365     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O                            (0x1<<2) // MSM Function NORMAL mode default value for reset_cmureg
22366     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREG_NORM_SETVAL_O_SHIFT                      2
22367     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O                         (0x1<<3) // MSM Function NORMAL mode default value for reset_cmuregref
22368     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUREGREF_NORM_SETVAL_O_SHIFT                   3
22369     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O                          (0x1<<4) // MSM Function NORMAL mode default value for reset_cmusynth
22370     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUSYNTH_NORM_SETVAL_O_SHIFT                    4
22371     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O                            (0x1<<5) // MSM Function NORMAL mode default value for reset_cmuvco
22372     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_RESET_CMUVCO_NORM_SETVAL_O_SHIFT                      5
22373     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O                          (0x1<<6) // MSM Function NORMAL mode default value for lf_extzero_ena
22374     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LF_EXTZERO_ENA_NORM_SETVAL_O_SHIFT                    6
22375     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O                             (0x1<<7) // MSM Function NORMAL mode default value for lfi_extzero
22376     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X198_LFI_EXTZERO_NORM_SETVAL_O_SHIFT                       7
22377 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199                                                           0x00031cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22378     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O                              (0x1<<0) // MSM Function NORMAL mode default value for soc_clk_en
22379     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_SOC_CLK_EN_NORM_SETVAL_O_SHIFT                        0
22380     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O                               (0x1<<1) // MSM Function NORMAL mode default value for refclk_en
22381     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_REFCLK_EN_NORM_SETVAL_O_SHIFT                         1
22382     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O                             (0x1<<2) // MSM Function NORMAL mode default value for pll_lock_en
22383     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PLL_LOCK_EN_NORM_SETVAL_O_SHIFT                       2
22384     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O                             (0x1<<3) // Not used
22385     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_TXCLK_NORM_SETVAL_O_SHIFT                       3
22386     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O                            (0x1<<4) // Not used
22387     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_RESET_CLKDIV_NORM_SETVAL_O_SHIFT                      4
22388     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O                               (0x1<<5) // Not used
22389     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_NORM_SETVAL_O_SHIFT                         5
22390     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O                   (0x1<<6) // Not used
22391     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_LEFT_NORM_SETVAL_O_SHIFT             6
22392     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O                  (0x1<<7) // Not used
22393     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X199_PD_CLKDIV_REFCLK_RIGHT_NORM_SETVAL_O_SHIFT            7
22394 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200                                                           0x000320UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22395     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O                                 (0x1<<0) // MSM Function POWER DOWN mode default value for iddq_bias
22396     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_IDDQ_BIAS_PD_SETVAL_O_SHIFT                           0
22397     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O                                   (0x1<<1) // MSM Function POWER DOWN mode default value for pd_bias
22398     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_BIAS_PD_SETVAL_O_SHIFT                             1
22399     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O                       (0x1<<2) // MSM Function POWER DOWN mode default value for pcs_clk_ena
22400     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_TXCLK_PCS_CLK_PD_SETVAL_O_SHIFT                 2
22401     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O                                    (0x1<<3) // MSM Function POWER DOWN mode default value for pd_cmu
22402     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMU_PD_SETVAL_O_SHIFT                              3
22403     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O                                 (0x1<<4) // MSM Function POWER DOWN mode default value for pd_cmureg
22404     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREG_PD_SETVAL_O_SHIFT                           4
22405     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O                              (0x1<<5) // MSM Function POWER DOWN mode default value for pd_cmuregref
22406     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_CMUREGREF_PD_SETVAL_O_SHIFT                        5
22407     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O                                    (0x1<<6) // MSM Function POWER DOWN mode default value for pd_ref
22408     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_PD_REF_PD_SETVAL_O_SHIFT                              6
22409     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O                              (0x1<<7) // MSM Function POWER DOWN mode default value for reset_cmu_fl
22410     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X200_RESET_CMU_FL_PD_SETVAL_O_SHIFT                        7
22411 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201                                                           0x000324UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22412     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O                                 (0x1<<0) // MSM Function POWER DOWN mode default value for reset_cmu
22413     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_PD_SETVAL_O_SHIFT                           0
22414     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O                            (0x1<<1) // MSM Function POWER DOWN mode default value for reset_cmu_gcrx
22415     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMU_GCRX_PD_SETVAL_O_SHIFT                      1
22416     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O                              (0x1<<2) // MSM Function POWER DOWN mode default value for reset_cmureg
22417     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREG_PD_SETVAL_O_SHIFT                        2
22418     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O                           (0x1<<3) // MSM Function POWER DOWN mode default value for reset_cmuregref
22419     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUREGREF_PD_SETVAL_O_SHIFT                     3
22420     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O                            (0x1<<4) // MSM Function POWER DOWN mode default value for reset_cmusynth
22421     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUSYNTH_PD_SETVAL_O_SHIFT                      4
22422     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O                              (0x1<<5) // MSM Function POWER DOWN mode default value for reset_cmuvco
22423     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_RESET_CMUVCO_PD_SETVAL_O_SHIFT                        5
22424     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O                            (0x1<<6) // MSM Function POWER DOWN mode default value for lf_extzero_ena
22425     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LF_EXTZERO_ENA_PD_SETVAL_O_SHIFT                      6
22426     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O                               (0x1<<7) // MSM Function POWER DOWN mode default value for lfi_extzero
22427     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X201_LFI_EXTZERO_PD_SETVAL_O_SHIFT                         7
22428 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202                                                           0x000328UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22429     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O                                (0x1<<0) // MSM Function POWER DOWN mode default value for soc_clk_en
22430     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_SOC_CLK_EN_PD_SETVAL_O_SHIFT                          0
22431     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O                                 (0x1<<1) // MSM Function POWER DOWN mode default value for refclk_en
22432     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_REFCLK_EN_PD_SETVAL_O_SHIFT                           1
22433     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O                               (0x1<<2) // MSM Function POWER DOWN mode default value for pll_lock_en
22434     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PLL_LOCK_EN_PD_SETVAL_O_SHIFT                         2
22435     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O                               (0x1<<3) // Not used
22436     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_TXCLK_PD_SETVAL_O_SHIFT                         3
22437     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O                              (0x1<<4) // Not used
22438     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_RESET_CLKDIV_PD_SETVAL_O_SHIFT                        4
22439     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O                                 (0x1<<5) // Not used
22440     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_PD_SETVAL_O_SHIFT                           5
22441     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O                     (0x1<<6) // Not used
22442     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_LEFT_PD_SETVAL_O_SHIFT               6
22443     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O                    (0x1<<7) // Not used
22444     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X202_PD_CLKDIV_REFCLK_RIGHT_PD_SETVAL_O_SHIFT              7
22445 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203                                                           0x00032cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22446     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_IDDQ_BIAS_NORM_REFCLK_SETVAL_O                        (0x1<<0) // MSM Function NORM REFCLK mode default value for iddq_bias
22447     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_IDDQ_BIAS_NORM_REFCLK_SETVAL_O_SHIFT                  0
22448     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_BIAS_NORM_REFCLK_SETVAL_O                          (0x1<<1) // MSM Function NORM REFCLK mode default value for pd_bias
22449     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_BIAS_NORM_REFCLK_SETVAL_O_SHIFT                    1
22450     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_TXCLK_PCS_CLK_NORM_REFCLK_SETVAL_O              (0x1<<2) // MSM Function NORM REFCLK mode default value for pcs_clk_ena
22451     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_TXCLK_PCS_CLK_NORM_REFCLK_SETVAL_O_SHIFT        2
22452     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMU_NORM_REFCLK_SETVAL_O                           (0x1<<3) // MSM Function NORM REFCLK mode default value for pd_cmu
22453     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMU_NORM_REFCLK_SETVAL_O_SHIFT                     3
22454     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREG_NORM_REFCLK_SETVAL_O                        (0x1<<4) // MSM Function NORM REFCLK mode default value for pd_cmureg
22455     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREG_NORM_REFCLK_SETVAL_O_SHIFT                  4
22456     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREGREF_NORM_REFCLK_SETVAL_O                     (0x1<<5) // MSM Function NORM REFCLK mode default value for pd_cmuregref
22457     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_CMUREGREF_NORM_REFCLK_SETVAL_O_SHIFT               5
22458     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_REF_NORM_REFCLK_SETVAL_O                           (0x1<<6) // MSM Function NORM REFCLK mode default value for pd_ref
22459     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_PD_REF_NORM_REFCLK_SETVAL_O_SHIFT                     6
22460     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_CMU_FL_NORM_REFCLK_SETVAL_O                     (0x1<<7) // MSM Function NORM REFCLK mode default value for reset_cmu_fl
22461     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X203_RESET_CMU_FL_NORM_REFCLK_SETVAL_O_SHIFT               7
22462 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204                                                           0x000330UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22463     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_NORM_REFCLK_SETVAL_O                        (0x1<<0) // MSM Function NORM REFCLK mode default value for reset_cmu
22464     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_NORM_REFCLK_SETVAL_O_SHIFT                  0
22465     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_GCRX_NORM_REFCLK_SETVAL_O                   (0x1<<1) // MSM Function NORM REFCLK mode default value for reset_cmu_gcrx
22466     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMU_GCRX_NORM_REFCLK_SETVAL_O_SHIFT             1
22467     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREG_NORM_REFCLK_SETVAL_O                     (0x1<<2) // MSM Function NORM REFCLK mode default value for reset_cmureg
22468     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREG_NORM_REFCLK_SETVAL_O_SHIFT               2
22469     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREGREF_NORM_REFCLK_SETVAL_O                  (0x1<<3) // MSM Function NORM REFCLK mode default value for reset_cmuregref
22470     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUREGREF_NORM_REFCLK_SETVAL_O_SHIFT            3
22471     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUSYNTH_NORM_REFCLK_SETVAL_O                   (0x1<<4) // MSM Function NORM REFCLK mode default value for reset_cmusynth
22472     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUSYNTH_NORM_REFCLK_SETVAL_O_SHIFT             4
22473     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUVCO_NORM_REFCLK_SETVAL_O                     (0x1<<5) // MSM Function NORM REFCLK mode default value for reset_cmuvco
22474     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_RESET_CMUVCO_NORM_REFCLK_SETVAL_O_SHIFT               5
22475     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LF_EXTZERO_ENA_NORM_REFCLK_SETVAL_O                   (0x1<<6) // MSM Function NORM REFCLK mode default value for lf_extzero_ena
22476     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LF_EXTZERO_ENA_NORM_REFCLK_SETVAL_O_SHIFT             6
22477     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LFI_EXTZERO_NORM_REFCLK_SETVAL_O                      (0x1<<7) // MSM Function NORM REFCLK mode default value for lfi_extzero
22478     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X204_LFI_EXTZERO_NORM_REFCLK_SETVAL_O_SHIFT                7
22479 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205                                                           0x000334UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22480     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_SOC_CLK_EN_NORM_REFCLK_SETVAL_O                       (0x1<<0) // MSM Function NORM REFCLK mode default value for soc_clk_en
22481     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_SOC_CLK_EN_NORM_REFCLK_SETVAL_O_SHIFT                 0
22482     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_REFCLK_EN_NORM_REFCLK_SETVAL_O                        (0x1<<1) // MSM Function NORM REFCLK mode default value for refclk_en
22483     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_REFCLK_EN_NORM_REFCLK_SETVAL_O_SHIFT                  1
22484     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PLL_LOCK_EN_NORM_REFCLK_SETVAL_O                      (0x1<<2) // MSM Function NORM REFCLK mode default value for pll_lock_en
22485     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PLL_LOCK_EN_NORM_REFCLK_SETVAL_O_SHIFT                2
22486     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_TXCLK_NORM_REFCLK_SETVAL_O                      (0x1<<3) // Not used
22487     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_TXCLK_NORM_REFCLK_SETVAL_O_SHIFT                3
22488     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_CLKDIV_NORM_REFCLK_SETVAL_O                     (0x1<<4) // Not used
22489     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_RESET_CLKDIV_NORM_REFCLK_SETVAL_O_SHIFT               4
22490     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_NORM_REFCLK_SETVAL_O                        (0x1<<5) // Not used
22491     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_NORM_REFCLK_SETVAL_O_SHIFT                  5
22492     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_LEFT_NORM_REFCLK_SETVAL_O            (0x1<<6) // Not used
22493     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_LEFT_NORM_REFCLK_SETVAL_O_SHIFT      6
22494     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_RIGHT_NORM_REFCLK_SETVAL_O           (0x1<<7) // Not used
22495     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X205_PD_CLKDIV_REFCLK_RIGHT_NORM_REFCLK_SETVAL_O_SHIFT     7
22496 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206                                                           0x000338UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22497     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_IDDQ_BIAS_P1_2_SETVAL_O                               (0x1<<0) // MSM Function P1_2 mode default value for iddq_bias
22498     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_IDDQ_BIAS_P1_2_SETVAL_O_SHIFT                         0
22499     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_BIAS_P1_2_SETVAL_O                                 (0x1<<1) // MSM Function P1_2 mode default value for pd_bias
22500     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_BIAS_P1_2_SETVAL_O_SHIFT                           1
22501     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_TXCLK_PCS_CLK_P1_2_SETVAL_O                     (0x1<<2) // MSM Function P1_2 mode default value for pcs_clk_ena
22502     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_TXCLK_PCS_CLK_P1_2_SETVAL_O_SHIFT               2
22503     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMU_P1_2_SETVAL_O                                  (0x1<<3) // MSM Function P1_2 mode default value for pd_cmu
22504     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMU_P1_2_SETVAL_O_SHIFT                            3
22505     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREG_P1_2_SETVAL_O                               (0x1<<4) // MSM Function P1_2 mode default value for pd_cmureg
22506     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREG_P1_2_SETVAL_O_SHIFT                         4
22507     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREGREF_P1_2_SETVAL_O                            (0x1<<5) // MSM Function P1_2 mode default value for pd_cmuregref
22508     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_CMUREGREF_P1_2_SETVAL_O_SHIFT                      5
22509     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_REF_P1_2_SETVAL_O                                  (0x1<<6) // MSM Function P1_2 mode default value for pd_ref
22510     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_PD_REF_P1_2_SETVAL_O_SHIFT                            6
22511     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_CMU_FL_P1_2_SETVAL_O                            (0x1<<7) // MSM Function P1_2 mode default value for reset_cmu_fl
22512     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X206_RESET_CMU_FL_P1_2_SETVAL_O_SHIFT                      7
22513 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207                                                           0x00033cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22514     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_P1_2_SETVAL_O                               (0x1<<0) // MSM Function P1_2 mode default value for reset_cmu
22515     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_P1_2_SETVAL_O_SHIFT                         0
22516     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_GCRX_P1_2_SETVAL_O                          (0x1<<1) // MSM Function P1_2 mode default value for reset_cmu_gcrx
22517     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMU_GCRX_P1_2_SETVAL_O_SHIFT                    1
22518     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREG_P1_2_SETVAL_O                            (0x1<<2) // MSM Function P1_2 mode default value for reset_cmureg
22519     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREG_P1_2_SETVAL_O_SHIFT                      2
22520     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREGREF_P1_2_SETVAL_O                         (0x1<<3) // MSM Function P1_2 mode default value for reset_cmuregref
22521     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUREGREF_P1_2_SETVAL_O_SHIFT                   3
22522     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUSYNTH_P1_2_SETVAL_O                          (0x1<<4) // MSM Function P1_2 mode default value for reset_cmusynth
22523     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUSYNTH_P1_2_SETVAL_O_SHIFT                    4
22524     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUVCO_P1_2_SETVAL_O                            (0x1<<5) // MSM Function P1_2 mode default value for reset_cmuvco
22525     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_RESET_CMUVCO_P1_2_SETVAL_O_SHIFT                      5
22526     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LF_EXTZERO_ENA_P1_2_SETVAL_O                          (0x1<<6) // MSM Function P1_2 mode default value for lf_extzero_ena
22527     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LF_EXTZERO_ENA_P1_2_SETVAL_O_SHIFT                    6
22528     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LFI_EXTZERO_P1_2_SETVAL_O                             (0x1<<7) // MSM Function P1_2 mode default value for lfi_extzero
22529     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X207_LFI_EXTZERO_P1_2_SETVAL_O_SHIFT                       7
22530 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208                                                           0x000340UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22531     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_SOC_CLK_EN_P1_2_SETVAL_O                              (0x1<<0) // MSM Function P1_2 mode default value for soc_clk_en
22532     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_SOC_CLK_EN_P1_2_SETVAL_O_SHIFT                        0
22533     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_REFCLK_EN_P1_2_SETVAL_O                               (0x1<<1) // MSM Function P1_2 mode default value for refclk_en
22534     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_REFCLK_EN_P1_2_SETVAL_O_SHIFT                         1
22535     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PLL_LOCK_EN_P1_2_SETVAL_O                             (0x1<<2) // MSM Function P1_2 mode default value for pll_lock_en
22536     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PLL_LOCK_EN_P1_2_SETVAL_O_SHIFT                       2
22537     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_TXCLK_P1_2_SETVAL_O                             (0x1<<3) // Not used
22538     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_TXCLK_P1_2_SETVAL_O_SHIFT                       3
22539     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_CLKDIV_P1_2_SETVAL_O                            (0x1<<4) // Not used
22540     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_RESET_CLKDIV_P1_2_SETVAL_O_SHIFT                      4
22541     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_P1_2_SETVAL_O                               (0x1<<5) // Not used
22542     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_P1_2_SETVAL_O_SHIFT                         5
22543     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_LEFT_P1_2_SETVAL_O                   (0x1<<6) // Not used
22544     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_LEFT_P1_2_SETVAL_O_SHIFT             6
22545     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_RIGHT_P1_2_SETVAL_O                  (0x1<<7) // Not used
22546     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X208_PD_CLKDIV_REFCLK_RIGHT_P1_2_SETVAL_O_SHIFT            7
22547 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X209                                                           0x000344UL //Access:RW   DataWidth:0x8   Not used  Chips: K2
22548 #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X210                                                           0x000348UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22549     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X210_AHB_P1_2_TO_NORM_REFCLK_GATE_DELAY_O_14_8             (0x7f<<0) // Not used
22550     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X210_AHB_P1_2_TO_NORM_REFCLK_GATE_DELAY_O_14_8_SHIFT       0
22551     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X210_UNUSED_0                                              (0x1<<7) // reserved
22552     #define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X210_UNUSED_0_SHIFT                                        7
22553 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0                                                            0x000800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22554     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_UNUSED_0                                               (0x7f<<0) // reserved
22555     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_UNUSED_0_SHIFT                                         0
22556     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O                             (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
22557     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_SHIFT                       7
22558 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1                                                            0x000804UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22559     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_UNUSED_0                                               (0x7<<0) // reserved
22560     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_UNUSED_0_SHIFT                                         0
22561     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O                             (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
22562     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_SHIFT                       3
22563     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_UNUSED_1                                               (0x7<<4) // reserved
22564     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_UNUSED_1_SHIFT                                         4
22565     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O                             (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
22566     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_SHIFT                       7
22567 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2                                                            0x000808UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22568     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_UNUSED_0                                               (0x7f<<0) // reserved
22569     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_UNUSED_0_SHIFT                                         0
22570     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O                             (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
22571     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_SHIFT                       7
22572 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3                                                            0x00080cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22573     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0                                        (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
22574     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_CMU_SEL_O_0_SHIFT                                  0
22575     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1                                      (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
22576     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_PMA_TXCLK_SEL_O_1_SHIFT                                1
22577     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_UNUSED_0                                               (0x3f<<2) // reserved
22578     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X3_UNUSED_0_SHIFT                                         2
22579 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4                                                            0x000810UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22580     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_CDRCTRL_DIV_EN_O_1_0                                   (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
22581     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_CDRCTRL_DIV_EN_O_1_0_SHIFT                             0
22582     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_GCFSM_DIV_EN_O_1_0                                     (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
22583     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_GCFSM_DIV_EN_O_1_0_SHIFT                               2
22584     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_LN_CLK_TXB_DIV24OR1_O                                  (0x3<<4) // Divide ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state:                                            2'b00: lnX_ck_txb_o is divided by 1 version of the tx byte clock from PMA.                     2'b01/2'b10: lnX_ck_txb_o is divided by 2 version of the tx byte clock from PMA.                  2'b11: lnX_ck_txb_o is divided by 4 version of the tx byte clock from PMA.
22585     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_LN_CLK_TXB_DIV24OR1_O_SHIFT                            4
22586     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_AHB_CHNG_REQ_Z_O                                       (0x1<<6) // Not currently used
22587     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_AHB_CHNG_REQ_Z_O_SHIFT                                 6
22588     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_UNUSED_0                                               (0x1<<7) // reserved
22589     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X4_UNUSED_0_SHIFT                                         7
22590 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5                                                            0x000814UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22591     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_REF_CLK_DIV_EN_O_1_0                                   (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
22592     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_REF_CLK_DIV_EN_O_1_0_SHIFT                             0
22593     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_OOB_CLK_DIV_EN_O_1_0                                   (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
22594     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_OOB_CLK_DIV_EN_O_1_0_SHIFT                             2
22595     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_UNUSED_0                                               (0xf<<4) // reserved
22596     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X5_UNUSED_0_SHIFT                                         4
22597 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7                                                            0x00081cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22598     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O                                            (0x3<<0) // Rate control for BIST
22599     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_RATE_O_SHIFT                                      0
22600     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O                                      (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
22601     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_MODE8B_O_SHIFT                                2
22602     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O                                         (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
22603     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_ERR_O_SHIFT                                   3
22604     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE                                   (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
22605     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_TX_CLOCK_ENABLE_SHIFT                             4
22606     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O                                         (0x1<<5) // Bist generator master reset.
22607     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_CDN_O_SHIFT                                   5
22608     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O                                        (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
22609     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_WORD_O_SHIFT                                  6
22610     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O                                          (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
22611     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X7_BIST_GEN_EN_O_SHIFT                                    7
22612 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8                                                            0x000820UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22613     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_CLK_SEL_O_2_0                                 (0x7<<0) // BIST Generation Clock Selection
22614     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_CLK_SEL_O_2_0_SHIFT                           0
22615     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O                                  (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
22616     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_SEND_PREAM_O_SHIFT                            3
22617     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_INSERT_COUNT_O_2_0                            (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
22618     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_BIST_GEN_INSERT_COUNT_O_2_0_SHIFT                      4
22619     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_UNUSED_0                                               (0x1<<7) // reserved
22620     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X8_UNUSED_0_SHIFT                                         7
22621 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X9                                                            0x000824UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
22622 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X10                                                           0x000828UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
22623 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X11                                                           0x00082cUL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
22624 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X12                                                           0x000830UL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
22625 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X13                                                           0x000834UL //Access:RW   DataWidth:0x8   Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.  Chips: K2
22626 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14                                                           0x000838UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22627     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BIST_GEN_INSERT_DELAY_O_11_8                          (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
22628     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BIST_GEN_INSERT_DELAY_O_11_8_SHIFT                    0
22629     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_UNUSED_0                                              (0x1<<4) // reserved
22630     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_UNUSED_0_SHIFT                                        4
22631     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O                                             (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
22632     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_EN_O_SHIFT                                       5
22633     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O                                            (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
22634     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_BCHK_CLR_O_SHIFT                                      6
22635     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_UNUSED_1                                              (0x1<<7) // reserved
22636     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X14_UNUSED_1_SHIFT                                        7
22637 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15                                                           0x00083cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22638     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BCHK_SRC_O_1_0                                        (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
22639     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BCHK_SRC_O_1_0_SHIFT                                  0
22640     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_UNUSED_0                                              (0x1<<2) // reserved
22641     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_UNUSED_0_SHIFT                                        2
22642     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O                                  (0x1<<3) // Bist checker mode select. 0X0 ? UDP pattern. 0x1 ? PRBS pattern
22643     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_DATA_MODE_O_SHIFT                            3
22644     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_LFSR_LENGTH_O_1_0                            (0x3<<4) // BIST PRBS pattern selector.
22645     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_CHK_LFSR_LENGTH_O_1_0_SHIFT                      4
22646     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_UNUSED_1                                              (0x1<<6) // reserved
22647     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_UNUSED_1_SHIFT                                        6
22648     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE                                  (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
22649     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X15_BIST_RX_CLOCK_ENABLE_SHIFT                            7
22650 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X16                                                           0x000840UL //Access:RW   DataWidth:0x8   Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.  Chips: K2
22651 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17                                                           0x000844UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22652     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_PREAM0_O_9_8                                 (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
22653     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_PREAM0_O_9_8_SHIFT                           0
22654     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_INSERT_LENGTH_O_2_0                          (0x7<<2) // BIST Checker Insert word length.
22655     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_INSERT_LENGTH_O_2_0_SHIFT                    2
22656     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS                                (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
22657     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_BIST_CHK_SYNC_ON_ZEROS_SHIFT                          5
22658     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_UNUSED_0                                              (0x3<<6) // reserved
22659     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X17_UNUSED_0_SHIFT                                        6
22660 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X18                                                           0x000848UL //Access:RW   DataWidth:0x8   BIST Check Preamble  Chips: K2
22661 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X19                                                           0x00084cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22662     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X19_BIST_CHK_PREAM1_O_9_8                                 (0x3<<0) // BIST Check Preamble
22663     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X19_BIST_CHK_PREAM1_O_9_8_SHIFT                           0
22664     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X19_UNUSED_0                                              (0x3f<<2) // reserved
22665     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X19_UNUSED_0_SHIFT                                        2
22666 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X20                                                           0x000850UL //Access:RW   DataWidth:0x8   Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.  Chips: K2
22667 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X21                                                           0x000854UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
22668 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X22                                                           0x000858UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
22669 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X23                                                           0x00085cUL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
22670 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X24                                                           0x000860UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
22671 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X25                                                           0x000864UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
22672 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X26                                                           0x000868UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
22673 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X27                                                           0x00086cUL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
22674 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X28                                                           0x000870UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
22675 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X29                                                           0x000874UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
22676 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X30                                                           0x000878UL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
22677 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X31                                                           0x00087cUL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
22678 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X32                                                           0x000880UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
22679 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X33                                                           0x000884UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
22680 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X34                                                           0x000888UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
22681 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X35                                                           0x00088cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
22682 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X36                                                           0x000890UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
22683 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X37                                                           0x000894UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
22684 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X38                                                           0x000898UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
22685 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X39                                                           0x00089cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
22686 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X40                                                           0x0008a0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
22687 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X41                                                           0x0008a4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
22688 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X42                                                           0x0008a8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
22689 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X43                                                           0x0008acUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
22690 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X44                                                           0x0008b0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
22691 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X45                                                           0x0008b4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
22692 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X46                                                           0x0008b8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
22693 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X47                                                           0x0008bcUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
22694 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X48                                                           0x0008c0UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 1/2 - for the new ICA method  Chips: K2
22695 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X49                                                           0x0008c4UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 3 - for the new ICA method  Chips: K2
22696 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X50                                                           0x0008c8UL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method  Chips: K2
22697 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X51                                                           0x0008ccUL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method  Chips: K2
22698 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X52                                                           0x0008d0UL //Access:RW   DataWidth:0x8   The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.  Chips: K2
22699 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53                                                           0x0008d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22700     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0                  (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
22701     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_SHIFT            0
22702     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2                           (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
22703     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_SHIFT                     5
22704     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN                               (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
22705     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_TW_METHOD_EN_SHIFT                         6
22706     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR                               (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
22707     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X53_GCFSM_LANE_PMA_LOAD_OVR_SHIFT                         7
22708 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X54                                                           0x0008d8UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
22709 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X55                                                           0x0008dcUL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
22710 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X56                                                           0x0008e0UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
22711 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57                                                           0x0008e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22712     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_OVR_O_27_24                                     (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
22713     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_OVR_O_27_24_SHIFT                               0
22714     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O                               (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
22715     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_OUT_OVR_EN_O_SHIFT                         4
22716     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O                            (0x1<<5) // GCFSM pma_latch_o override
22717     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_LATCH_OVR_O_SHIFT                      5
22718     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O                               (0x1<<6) // GCFSM pma_go_o override
22719     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_GO_OVR_O_SHIFT                         6
22720     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O                             (0x1<<7) // GCFSM pma_read_o override.
22721     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X57_GCFSM_LANE_PMA_READ_OVR_O_SHIFT                       7
22722 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X58                                                           0x0008e8UL //Access:RW   DataWidth:0x8   GCFSM pma_data_o override data. Bits applied to PMA are [8:15]  Chips: K2
22723 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X59                                                           0x0008ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22724     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8                        (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
22725     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_SHIFT                  0
22726     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X59_UNUSED_0                                              (0xf<<4) // reserved
22727     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X59_UNUSED_0_SHIFT                                        4
22728 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X60                                                           0x0008f0UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
22729 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X61                                                           0x0008f4UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
22730 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62                                                           0x0008f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22731     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_REQ_IN_OVR_O                                   (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
22732     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_REQ_IN_OVR_O_SHIFT                             0
22733     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_FUNC_IN_OVR_O                                  (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
22734     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X62_LN_MSM_FUNC_IN_OVR_O_SHIFT                            2
22735 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65                                                           0x000904UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22736     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28                                        (0x1<<0) // Not currently used
22737     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65_GCFSM_OVR_O_28_SHIFT                                  0
22738     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65_UNUSED_0                                              (0x7f<<1) // reserved
22739     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X65_UNUSED_0_SHIFT                                        1
22740 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X66                                                           0x000908UL //Access:RW   DataWidth:0x8   Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.  Chips: K2
22741 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67                                                           0x00090cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22742     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_DLY_CDR_O_6_0                                (0x7f<<0) // Number of clock cycles between signal detect indicator
22743     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_DLY_CDR_O_6_0_SHIFT                          0
22744     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8                           (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
22745     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_SHIFT                     7
22746 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X68                                                           0x000910UL //Access:RW   DataWidth:0x8   Number of clock cycles between CISEL assertion  Chips: K2
22747 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69                                                           0x000914UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22748     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_DLY_LANE_O_9_8                               (0x3<<0) // Number of clock cycles between CISEL assertion
22749     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_DLY_LANE_O_9_8_SHIFT                         0
22750     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_START_LEN_O_3_0                              (0xf<<2) // Number of clock cycles between when CDR control block
22751     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_START_LEN_O_3_0_SHIFT                        2
22752     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_INT_FIL_O_1_0                                (0x3<<6) // CDR control DLPF positioning control.
22753     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X69_CDR_CTRL_INT_FIL_O_1_0_SHIFT                          6
22754 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X70                                                           0x000918UL //Access:RW   DataWidth:0x8   CDR control block cycle length When not in PCIe Gen3.  Chips: K2
22755 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X71                                                           0x00091cUL //Access:RW   DataWidth:0x8   CDR control block cycle length When in PCIe Gen3.  Chips: K2
22756 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72                                                           0x000920UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22757     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MAX_DIFF_O_4_0                               (0x1f<<0) // Maximum difference from DLPF center point.
22758     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MAX_DIFF_O_4_0_SHIFT                         0
22759     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MIN_BOUNCE_O_2_0                             (0x7<<5) // Maximum difference from DLPF center point.
22760     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_SHIFT                       5
22761 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73                                                           0x000924UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22762     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN                                 (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
22763     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_TW_METHOD_EN_SHIFT                           0
22764     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O                                (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
22765     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CONTROL_ATT_CTRL_O_SHIFT                          1
22766     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O                                        (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
22767     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_RXEQ_WAIT_EN_O_SHIFT                                  2
22768     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7                                (0x7<<3) // Number of clock cycles between signal detect indicator
22769     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_CDR_CTRL_DLY_CDR_O_9_7_SHIFT                          3
22770     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_UNUSED_0                                              (0x3<<6) // reserved
22771     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X73_UNUSED_0_SHIFT                                        6
22772 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X74                                                           0x000928UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
22773 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X75                                                           0x00092cUL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
22774 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X76                                                           0x000930UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
22775 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77                                                           0x000934UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22776     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_OUT_OVR_O_29_24                              (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
22777     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_OUT_OVR_O_29_24_SHIFT                        0
22778     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR                                 (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
22779     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_CDR_CTRL_CAL_LOAD_OVR_SHIFT                           6
22780     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_UNUSED_0                                              (0x1<<7) // reserved
22781     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X77_UNUSED_0_SHIFT                                        7
22782 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78                                                           0x000938UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22783     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_ALIGN_POS_O_5_0                             (0x3f<<0) // Symbol aligner position override enable.
22784     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_ALIGN_POS_O_5_0_SHIFT                       0
22785     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_MODE_O_1_0                                  (0x3<<6) // Symbol aligner mode select.
22786     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X78_SYM_ALIGN_MODE_O_1_0_SHIFT                            6
22787 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79                                                           0x00093cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22788     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O                                    (0x1<<0) // Asserting this register will bypass the symbol aligner
22789     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79_SYM_ALIGN_BYPASS_O_SHIFT                              0
22790     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79_UNUSED_0                                              (0x7f<<1) // reserved
22791     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X79_UNUSED_0_SHIFT                                        1
22792 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X80                                                           0x000940UL //Access:RW   DataWidth:0x8   Number of cycles to wait before forcing exit form EI  Chips: K2
22793 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81                                                           0x000944UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22794     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8                    (0x3<<0) // Number of cycles to wait before forcing exit form EI
22795     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_SHIFT              0
22796     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O                               (0x1<<2) // Clears the elec idle control error flag
22797     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_CLR_ERR_O_SHIFT                         2
22798     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O                           (0x1<<3) // Override for ei_inferred signal
22799     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_INFERRED_O_SHIFT                     3
22800     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O                        (0x1<<4) // Override for ei_mask signal
22801     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_SHIFT                  4
22802     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O                         (0x1<<5) // Override for ei_exit_type signal
22803     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_SHIFT                   5
22804     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O                                   (0x1<<6) // EI control override enable
22805     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_ELECIDLE_CTRL_OVR_O_SHIFT                             6
22806     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_UNUSED_0                                              (0x1<<7) // reserved
22807     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X81_UNUSED_0_SHIFT                                        7
22808 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X82                                                           0x000948UL //Access:RW   DataWidth:0x8   Number of cycles to wait before entering back into EI  Chips: K2
22809 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X83                                                           0x00094cUL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect glitch filter counter  Chips: K2
22810 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X84                                                           0x000950UL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect low filter min value  Chips: K2
22811 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85                                                           0x000954UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22812     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8                    (0x3<<0) // Number of cycles to wait before entering back into EI
22813     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_SHIFT              0
22814     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0                     (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
22815     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_SHIFT               2
22816     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O                                         (0x1<<4) // Control signal to force decoder into loopback mode
22817     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_LOOPBACK_EN_O_SHIFT                                   4
22818     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_UNUSED_0                                              (0x7<<5) // reserved
22819     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X85_UNUSED_0_SHIFT                                        5
22820 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86                                                           0x000958UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22821     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O                                          (0x1<<0) // FES loopback enable.
22822     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_FES_LB_ENA_O_SHIFT                                    0
22823     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O                                          (0x1<<1) // NES loopback enable.
22824     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_NES_LB_ENA_O_SHIFT                                    1
22825     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O                                        (0x1<<2) // HS recovered clock to transmit loopback enable.
22826     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_RXCLK_LB_ENA_O_SHIFT                                  2
22827     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_UNUSED_0                                              (0x1f<<3) // reserved
22828     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X86_UNUSED_0_SHIFT                                        3
22829 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87                                                           0x00095cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22830     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O                             (0x1<<0) // RX boost override enable
22831     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOST_OVR_O_SHIFT                       0
22832     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O                        (0x7f<<1) // RX boost override setting. Thermometer coded.
22833     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_SHIFT                  1
22834 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X88                                                           0x000960UL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
22835 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89                                                           0x000964UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22836     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV1_O                            (0x7<<0) // Signal detect threshold select for Full rate
22837     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_SHIFT                      0
22838     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O                            (0x7<<3) // Signal detect threshold select for div-by-2 rate
22839     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_SHIFT                      3
22840     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O                                     (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
22841     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXUP_O_SHIFT                               6
22842     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O                            (0x1<<7) // RX FL calibration clock DIV4 enable
22843     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_SHIFT                      7
22844 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90                                                           0x000968UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22845     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_SD_THSEL_DIV4_O                            (0x7<<0) // Signal detect threshold select for div-by-4 rate
22846     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_SHIFT                      0
22847     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O                                (0x7<<3) // AGC threshold select
22848     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_AGC_THSEL_O_SHIFT                          3
22849     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_VREGH_O                                    (0x3<<6) // Regulator VREGH setting
22850     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X90_AHB_PMA_LN_VREGH_O_SHIFT                              6
22851 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X91                                                           0x00096cUL //Access:RW   DataWidth:0x8   RX FL calibration LDHS  Chips: K2
22852 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92                                                           0x000970UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22853     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O                            (0x3<<0) // RX FL calibration LDHS
22854     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_SHIFT                      0
22855     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXVCO_BIAS_O                               (0xf<<2) // CDR VCO bias setting.
22856     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_RXVCO_BIAS_O_SHIFT                         2
22857     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O                            (0x1<<6) // DLPF DIV2 enable
22858     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_SHIFT                      6
22859     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O                             (0x1<<7) // CDR DivN clock divider enable.
22860     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_SHIFT                       7
22861 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X93                                                           0x000974UL //Access:RW   DataWidth:0x8   AFE spare controls  Chips: K2
22862 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94                                                           0x000978UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22863     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_CDR_DVDR_O                                 (0x3f<<0) // CDR DivN clock division ratio.
22864     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_CDR_DVDR_O_SHIFT                           0
22865     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_VREG_O                                     (0x3<<6) // Regulator VREG setting
22866     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X94_AHB_PMA_LN_VREG_O_SHIFT                               6
22867 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95                                                           0x00097cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22868     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_BB_STEP_O                                  (0xf<<0) // CDR bb_step
22869     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_BB_STEP_O_SHIFT                            0
22870     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_INT_STEP_O                                 (0x7<<4) // CDR int step
22871     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_INT_STEP_O_SHIFT                           4
22872     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O                                    (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
22873     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X95_AHB_PMA_LN_RXDWN_O_SHIFT                              7
22874 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96                                                           0x000980UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22875     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_O                                  (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
22876     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_O_SHIFT                            0
22877     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O                              (0x1<<3) // Override enable for RXVCOFR override vakue
22878     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RXVCOFR_SEL_O_SHIFT                        3
22879     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RX_SELR_O                                  (0x7<<4) // CTLE R degeneration select
22880     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_AHB_PMA_LN_RX_SELR_O_SHIFT                            4
22881     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_UNUSED_0                                              (0x1<<7) // reserved
22882     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X96_UNUSED_0_SHIFT                                        7
22883 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X97                                                           0x000984UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22884     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X97_AHB_PMA_LN_RX_SELC_O                                  (0x7<<0) // CTLE C degeneration select
22885     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X97_AHB_PMA_LN_RX_SELC_O_SHIFT                            0
22886     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X97_UNUSED_0                                              (0x1f<<3) // reserved
22887     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X97_UNUSED_0_SHIFT                                        3
22888 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99                                                           0x00098cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22889     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_UNUSED_0                                              (0xf<<0) // reserved
22890     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_UNUSED_0_SHIFT                                        0
22891     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_DFE_BW_SCALE                                   (0x3<<4) // DFE Bandwidth Selection
22892     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_DFE_BW_SCALE_SHIFT                             4
22893     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_PHD_ENA_O_1_0                                  (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
22894     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X99_PMA_LN_PHD_ENA_O_1_0_SHIFT                            6
22895 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X100                                                          0x000990UL //Access:RW   DataWidth:0x8   On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal  Chips: K2
22896 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101                                                          0x000994UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22897     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8                                 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
22898     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_DLY_O_8_8_SHIFT                           0
22899     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_UNUSED_0                                             (0x1<<1) // reserved
22900     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_UNUSED_0_SHIFT                                       1
22901     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O                                 (0x1<<2) // Reset signal for eye alignment mechanism.
22902     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_SGN_RST_O_SHIFT                           2
22903     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL                                      (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
22904     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_SD_BWSEL_SHIFT                                3
22905     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O                                  (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
22906     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA270_O_SHIFT                            4
22907     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O                                   (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
22908     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_PMA_LN_EYE_ENA90_O_SHIFT                             5
22909     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_UNUSED_1                                             (0x3<<6) // reserved
22910     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X101_UNUSED_1_SHIFT                                       6
22911 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X102                                                          0x000998UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22912     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X102_PMA_LN_DFE_BIAS_O_3_0                                (0xf<<0) // DFE bias setting.
22913     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X102_PMA_LN_DFE_BIAS_O_3_0_SHIFT                          0
22914     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X102_UNUSED_0                                             (0xf<<4) // reserved
22915     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X102_UNUSED_0_SHIFT                                       4
22916 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103                                                          0x00099cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22917     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TX_SR_FASTCAP_O_3_0                           (0xf<<0) // TX driver capacitive slew rate control.
22918     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_SHIFT                     0
22919     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TXEQ_POLARITY_O_3_0                           (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
22920     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X103_PMA_LN_TXEQ_POLARITY_O_3_0_SHIFT                     4
22921 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104                                                          0x0009a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22922     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_TX_SR_DAC_O_3_0                               (0xf<<0) // TX slew rate DAC bias current control
22923     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_TX_SR_DAC_O_3_0_SHIFT                         0
22924     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O                                   (0x1<<4) // CDR clock divider bypass enable.
22925     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_PMA_LN_HSCLK_SEL_O_SHIFT                             4
22926     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_UNUSED_0                                             (0x7<<5) // reserved
22927     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X104_UNUSED_0_SHIFT                                       5
22928 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105                                                          0x0009a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22929     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TX_VREG_LEV_O_4_0                             (0x1f<<0) // TX driver regulator voltage setting.
22930     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TX_VREG_LEV_O_4_0_SHIFT                       0
22931     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O                             (0x1<<5) // TX bleed enable
22932     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_PMA_LN_TXDRV_BLEED_ENA_O_SHIFT                       5
22933     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_UNUSED_0                                             (0x3<<6) // reserved
22934     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X105_UNUSED_0_SHIFT                                       6
22935 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106                                                          0x0009a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22936     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O                       (0x1<<0) // RX boost override enable.
22937     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_SHIFT                 0
22938     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O                    (0x7f<<1) // RX boost override setting. Thermometer coded.
22939     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_SHIFT              1
22940 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X107                                                          0x0009acUL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
22941 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108                                                          0x0009b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22942     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_SD_THSEL_GEN3_O                           (0x7<<0) // Signal detect threshold select for Gen3
22943     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_SHIFT                     0
22944     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O                          (0x7<<3) // AGC threshold select for Gen3
22945     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_SHIFT                    3
22946     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXUP_GEN3_O                               (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
22947     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXUP_GEN3_O_SHIFT                         6
22948     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O                      (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
22949     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_SHIFT                7
22950 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X109                                                          0x0009b4UL //Access:RW   DataWidth:0x8   RX FL calibration LDHS for Gen3  Chips: K2
22951 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110                                                          0x0009b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22952     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O                      (0x3<<0) // RX FL calibration LDHS for Gen3
22953     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_SHIFT                0
22954     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O                         (0xf<<2) // CDR VCO bias setting.
22955     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_SHIFT                   2
22956     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O                      (0x1<<6) // DLPF DIV2 enable
22957     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_SHIFT                6
22958     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O                       (0x1<<7) // CDR DivN clock divider enable.
22959     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_SHIFT                 7
22960 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X111                                                          0x0009bcUL //Access:RW   DataWidth:0x8   AFE spare controls for Gen3  Chips: K2
22961 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112                                                          0x0009c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22962     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O                           (0x3f<<0) // CDR DivN clock divider ratio..
22963     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_SHIFT                     0
22964     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_AHB_PMA_LN_VREG_GEN3_O                               (0x3<<6) // Regulator VREG setting for Gen3
22965     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X112_AHB_PMA_LN_VREG_GEN3_O_SHIFT                         6
22966 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113                                                          0x0009c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22967     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_BB_STEP_GEN3_O                            (0xf<<0) // CDR bb_step for Gen3
22968     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_BB_STEP_GEN3_O_SHIFT                      0
22969     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_INT_STEP_GEN3_O                           (0x7<<4) // CDR int step for Gen3
22970     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_INT_STEP_GEN3_O_SHIFT                     4
22971     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_RXDWN_GEN3_O                              (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
22972     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X113_AHB_PMA_LN_RXDWN_GEN3_O_SHIFT                        7
22973 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114                                                          0x0009c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22974     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RXVCOFR_GEN3_O                            (0x7<<0) // RXVCOFR override value for Gen3 Enabled by pma_ln_dr_rxvcofr_sel_o
22975     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_SHIFT                      0
22976     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RX_SELR_GEN3_O                            (0x7<<3) // CTLE R degeneration select for Gen3
22977     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_RX_SELR_GEN3_O_SHIFT                      3
22978     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_VREGH_GEN3_O                              (0x3<<6) // Not currently used
22979     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X114_AHB_PMA_LN_VREGH_GEN3_O_SHIFT                        6
22980 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X115                                                          0x0009ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22981     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X115_AHB_PMA_LN_RX_SELC_GEN3_O                            (0x7<<0) // CTLE R degeneration select for Gen3
22982     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X115_AHB_PMA_LN_RX_SELC_GEN3_O_SHIFT                      0
22983     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X115_UNUSED_0                                             (0x1f<<3) // reserved
22984     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X115_UNUSED_0_SHIFT                                       3
22985 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119                                                          0x0009dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22986     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXP_MARGIN                                    (0xf<<0) // Value to minus/add from the calibrated txterm value
22987     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXP_MARGIN_SHIFT                              0
22988     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXN_MARGIN                                    (0xf<<4) // Value to minus/add from the calibrated txterm value
22989     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X119_AHB_TX_CXN_MARGIN_SHIFT                              4
22990 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120                                                          0x0009e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22991     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_CMP                              (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
22992     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_CMP_SHIFT                        0
22993     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE                           (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
22994     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_SHIFT                     4
22995     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_UNUSED_0                                             (0x1<<7) // reserved
22996     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X120_UNUSED_0_SHIFT                                       7
22997 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121                                                          0x0009e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
22998     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES                        (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
22999     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_SHIFT                  0
23000     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0                              (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
23001     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXP_MARGIN_ADD_0_SHIFT                        4
23002     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0                              (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
23003     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CXN_MARGIN_ADD_0_SHIFT                        5
23004     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA                                    (0x1<<6) // enable override calibrated txterm value
23005     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_CX_OVR_ENA_SHIFT                              6
23006     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR                               (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
23007     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X121_AHB_TX_TERM_EN_CAL_OVR_SHIFT                         7
23008 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122                                                          0x0009e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23009     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXP_OVR                                       (0xf<<0) // override calibrated txterm value
23010     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXP_OVR_SHIFT                                 0
23011     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXN_OVR                                       (0xf<<4) // override calibrated txterm value
23012     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X122_AHB_TX_CXN_OVR_SHIFT                                 4
23013 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123                                                          0x0009ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23014     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0                                          (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
23015     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_0_SHIFT                                    0
23016     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_UNUSED_0                                             (0x1<<1) // reserved
23017     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_UNUSED_0_SHIFT                                       1
23018     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_7_2                                        (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
23019     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X123_TX_CTRL_O_7_2_SHIFT                                  2
23020 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X124                                                          0x0009f0UL //Access:RW   DataWidth:0x8   Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]  Chips: K2
23021 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X125                                                          0x0009f4UL //Access:RW   DataWidth:0x8   Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode  Chips: K2
23022 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126                                                          0x0009f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23023     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O                                            (0x1<<0) // DFE block enable signal.
23024     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_EN_O_SHIFT                                      0
23025     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0                                (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
23026     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE_OW_O_2_0_SHIFT                          1
23027     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3                             (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
23028     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE1_CAL_EN_O_3_SHIFT                       4
23029     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4                             (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
23030     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE2_CAL_EN_O_4_SHIFT                       5
23031     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5                             (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
23032     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_RATE3_CAL_EN_O_5_SHIFT                       6
23033     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6                                (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
23034     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X126_RXEQ_LN_FORCE_CAL_O_6_SHIFT                          7
23035 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X127                                                          0x0009fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23036     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X127_RXEQ_CONT_CAL_O_6_0                                  (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
23037     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X127_RXEQ_CONT_CAL_O_6_0_SHIFT                            0
23038     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X127_UNUSED_0                                             (0x1<<7) // reserved
23039     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X127_UNUSED_0_SHIFT                                       7
23040 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X128                                                          0x000a00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23041     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X128_RXEQ_INIT_CAL_O_6_0                                  (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
23042     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X128_RXEQ_INIT_CAL_O_6_0_SHIFT                            0
23043     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X128_UNUSED_0                                             (0x1<<7) // reserved
23044     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X128_UNUSED_0_SHIFT                                       7
23045 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130                                                          0x000a08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23046     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate1
23047     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_ATT_START_O_3_0_SHIFT                     0
23048     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate1
23049     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X130_RXEQ_RATE1_BOOST_START_O_3_0_SHIFT                   4
23050 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131                                                          0x000a0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23051     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate2
23052     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_ATT_START_O_3_0_SHIFT                     0
23053     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate2
23054     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X131_RXEQ_RATE2_BOOST_START_O_3_0_SHIFT                   4
23055 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X132                                                          0x000a10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23056     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X132_RXEQ_RATE2_TAP1_START_O_6_0                          (0x7f<<0) // DFE Tap1 start value for rate2
23057     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X132_RXEQ_RATE2_TAP1_START_O_6_0_SHIFT                    0
23058     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X132_UNUSED_0                                             (0x1<<7) // reserved
23059     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X132_UNUSED_0_SHIFT                                       7
23060 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X133                                                          0x000a14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23061     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X133_RXEQ_RATE2_TAP2_START_O_5_0                          (0x3f<<0) // DFE Tap2 start value for rate2
23062     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X133_RXEQ_RATE2_TAP2_START_O_5_0_SHIFT                    0
23063     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X133_UNUSED_0                                             (0x3<<6) // reserved
23064     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X133_UNUSED_0_SHIFT                                       6
23065 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X134                                                          0x000a18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23066     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X134_RXEQ_RATE2_TAP3_START_O_5_0                          (0x3f<<0) // DFE Tap3 start value for rate2
23067     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X134_RXEQ_RATE2_TAP3_START_O_5_0_SHIFT                    0
23068     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X134_UNUSED_0                                             (0x3<<6) // reserved
23069     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X134_UNUSED_0_SHIFT                                       6
23070 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X135                                                          0x000a1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23071     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X135_RXEQ_RATE2_TAP4_START_O_5_0                          (0x3f<<0) // DFE Tap4 start value for rate2
23072     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X135_RXEQ_RATE2_TAP4_START_O_5_0_SHIFT                    0
23073     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X135_UNUSED_0                                             (0x3<<6) // reserved
23074     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X135_UNUSED_0_SHIFT                                       6
23075 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X136                                                          0x000a20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23076     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X136_RXEQ_RATE2_TAP5_START_O_5_0                          (0x3f<<0) // DFE Tap5 start value for rate2
23077     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X136_RXEQ_RATE2_TAP5_START_O_5_0_SHIFT                    0
23078     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X136_UNUSED_0                                             (0x3<<6) // reserved
23079     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X136_UNUSED_0_SHIFT                                       6
23080 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137                                                          0x000a24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23081     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate3
23082     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_ATT_START_O_3_0_SHIFT                     0
23083     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate3
23084     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X137_RXEQ_RATE3_BOOST_START_O_3_0_SHIFT                   4
23085 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X138                                                          0x000a28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23086     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X138_RXEQ_RATE3_TAP1_START_O_6_0                          (0x7f<<0) // DFE Tap1 start value for rate3
23087     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X138_RXEQ_RATE3_TAP1_START_O_6_0_SHIFT                    0
23088     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X138_UNUSED_0                                             (0x1<<7) // reserved
23089     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X138_UNUSED_0_SHIFT                                       7
23090 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X139                                                          0x000a2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23091     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X139_RXEQ_RATE3_TAP2_START_O_5_0                          (0x3f<<0) // DFE Tap2 start value for rate3
23092     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X139_RXEQ_RATE3_TAP2_START_O_5_0_SHIFT                    0
23093     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X139_UNUSED_0                                             (0x3<<6) // reserved
23094     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X139_UNUSED_0_SHIFT                                       6
23095 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X140                                                          0x000a30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23096     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X140_RXEQ_RATE3_TAP3_START_O_5_0                          (0x3f<<0) // DFE Tap3 start value for rate3
23097     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X140_RXEQ_RATE3_TAP3_START_O_5_0_SHIFT                    0
23098     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X140_UNUSED_0                                             (0x3<<6) // reserved
23099     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X140_UNUSED_0_SHIFT                                       6
23100 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X141                                                          0x000a34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23101     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X141_RXEQ_RATE3_TAP4_START_O_5_0                          (0x3f<<0) // DFE Tap4 start value for rate3
23102     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X141_RXEQ_RATE3_TAP4_START_O_5_0_SHIFT                    0
23103     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X141_UNUSED_0                                             (0x3<<6) // reserved
23104     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X141_UNUSED_0_SHIFT                                       6
23105 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X142                                                          0x000a38UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23106     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X142_RXEQ_RATE3_TAP5_START_O_5_0                          (0x3f<<0) // DFE Tap5 start value for rate3
23107     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X142_RXEQ_RATE3_TAP5_START_O_5_0_SHIFT                    0
23108     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X142_UNUSED_0                                             (0x3<<6) // reserved
23109     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X142_UNUSED_0_SHIFT                                       6
23110 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143                                                          0x000a3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23111     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS                            (0x1<<0) // Disable auto cal w/ rx_superbst
23112     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RXEQ_SUPERBST_AUTOCAL_DIS_SHIFT                      0
23113     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O                                    (0xf<<1) // Max limit value for BOOST auto-calibration
23114     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_O_SHIFT                              1
23115     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O                                 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
23116     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_BOOST_MAX_LIMIT_EN_O_SHIFT                           5
23117     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RX_ATT_BOOST_CAL_O_1_0                               (0x3<<6) // rx_att_boost setting used during ATT calibration
23118     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X143_RX_ATT_BOOST_CAL_O_1_0_SHIFT                         6
23119 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144                                                          0x000a40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23120     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RX_ATT_BOOST_NORM_O_1_0                              (0x3<<0) // rx_att_boost setting used after ATT calibration
23121     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RX_ATT_BOOST_NORM_O_1_0_SHIFT                        0
23122     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O                                  (0x1<<2) // boost_adj_en
23123     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_EN_O_SHIFT                            2
23124     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O                                 (0x1<<3) // boost_adj_dir
23125     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_DIR_O_SHIFT                           3
23126     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_VAL_O                                 (0xf<<4) // boost_adj_val This register Is not bit reversed
23127     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X144_RXEQ_BOOST_ADJ_VAL_O_SHIFT                           4
23128 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145                                                          0x000a44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23129     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0                    (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
23130     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_SHIFT              0
23131     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O                                  (0x1<<7) // CMP Offset Noise Averaging Enable
23132     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X145_CMP_OFFSET_AVG_EN_O_SHIFT                            7
23133 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X146                                                          0x000a48UL //Access:RW   DataWidth:0x8     Chips: K2
23134 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147                                                          0x000a4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23135     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_DFE_TAP_PD_WAIT_11_8                            (0xf<<0) //
23136     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_SHIFT                      0
23137     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_PMA_LN_DFE_OFS_CAL_ENA                               (0x3<<4) // DFE offset calibration enable
23138     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_PMA_LN_DFE_OFS_CAL_ENA_SHIFT                         4
23139     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS                            (0x1<<6) // Disable auto cal w/ rx_att_gain
23140     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_SHIFT                      6
23141     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O                            (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
23142     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X147_RXEQ_SUPERBST_EN_INVERT_O_SHIFT                      7
23143 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148                                                          0x000a50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23144     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_LOAD_EN_O_6_0                               (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
23145     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_LOAD_EN_O_6_0_SHIFT                         0
23146     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O                                        (0x1<<7) // Override enable for DFE signals.
23147     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X148_RXEQ_OVR_EN_O_SHIFT                                  7
23148 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149                                                          0x000a54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23149     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LOAD_O_6_0                                  (0x7f<<0) // Override for RXEQ_CTRL output register load value.
23150     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LOAD_O_6_0_SHIFT                            0
23151     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O                                     (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
23152     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X149_RXEQ_OVR_LATCH_O_SHIFT                               7
23153 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150                                                          0x000a58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23154     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0                           (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
23155     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_SHIFT                     0
23156     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR                                    (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
23157     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_ATT_GAIN_OVR_SHIFT                              3
23158     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR                                (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
23159     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_RXEQ_SUPERBST_ENA_OVR_SHIFT                          5
23160     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6                       (0x1<<6) // DFE TAP CMP no offset override enable
23161     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_SHIFT                 6
23162     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7                                   (0x1<<7) // DFE TAP override enable
23163     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X150_DFE_TAP_OVR_EN_O_7_SHIFT                             7
23164 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151                                                          0x000a5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23165     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3                      (0x1f<<0) // DFE offset calibration TAP enable override
23166     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_SHIFT                0
23167     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0                        (0x1<<5) // DFE offset calibrated value override enable
23168     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_SHIFT                  5
23169     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1                            (0x1<<6) // DFE offset cal enable override
23170     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_OFFSET_CAL_EN_OVR_O_1_SHIFT                      6
23171     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2                               (0x1<<7) // DFE comparator cal enable override
23172     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X151_DFE_CMP_CAL_EN_OVR_O_2_SHIFT                         7
23173 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X152                                                          0x000a60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23174     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X152_DFE_TAP1_OVR_VAL_O_6_0                               (0x7f<<0) // DFE Tap 1 Override Value
23175     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X152_DFE_TAP1_OVR_VAL_O_6_0_SHIFT                         0
23176     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X152_UNUSED_0                                             (0x1<<7) // reserved
23177     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X152_UNUSED_0_SHIFT                                       7
23178 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X153                                                          0x000a64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23179     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X153_DFE_TAP2_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 2 Override Value
23180     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X153_DFE_TAP2_OVR_VAL_O_5_0_SHIFT                         0
23181     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X153_UNUSED_0                                             (0x3<<6) // reserved
23182     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X153_UNUSED_0_SHIFT                                       6
23183 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X154                                                          0x000a68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23184     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X154_DFE_TAP3_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 3 Override Value
23185     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X154_DFE_TAP3_OVR_VAL_O_5_0_SHIFT                         0
23186     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X154_UNUSED_0                                             (0x3<<6) // reserved
23187     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X154_UNUSED_0_SHIFT                                       6
23188 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155                                                          0x000a6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23189     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_DFE_TAP4_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 4 Override Value
23190     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_DFE_TAP4_OVR_VAL_O_5_0_SHIFT                         0
23191     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_UNUSED_0                                             (0x3<<6) // reserved
23192     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X155_UNUSED_0_SHIFT                                       6
23193 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X156                                                          0x000a70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23194     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X156_DFE_TAP5_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 5 Override Value
23195     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X156_DFE_TAP5_OVR_VAL_O_5_0_SHIFT                         0
23196     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X156_UNUSED_0                                             (0x3<<6) // reserved
23197     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X156_UNUSED_0_SHIFT                                       6
23198 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157                                                          0x000a74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23199     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ADAPT_EN_O_0                                    (0x1<<0) // TX Equalizer adaptation function enable
23200     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ADAPT_EN_O_0_SHIFT                              0
23201     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ERR_SIGN_O_1                                    (0x1<<1) // TX Equalizer Error Sign
23202     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_ERR_SIGN_O_1_SHIFT                              1
23203     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_FW_OVRIDE_O_2                                   (0x1<<2) // TX Equalization Firmware over ride  0 -	 Disable firmware based adaptation  1 -	 Enbale firmware based adaptation
23204     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_TXEQ_FW_OVRIDE_O_2_SHIFT                             2
23205     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_UNUSED_0                                             (0x1f<<3) // reserved
23206     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X157_UNUSED_0_SHIFT                                       3
23207 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X158                                                          0x000a78UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
23208     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X158_TXEQ_ERR_STAT_I_1_0                                  (0x3<<0) // TX Equalization error state
23209     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X158_TXEQ_ERR_STAT_I_1_0_SHIFT                            0
23210     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X158_UNUSED_0                                             (0x3f<<2) // reserved
23211     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X158_UNUSED_0_SHIFT                                       2
23212 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X159                                                          0x000a7cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
23213     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X159_TXEQ_OVER_EQ_CNT_I_9_8                               (0x3<<0) // Over equalization count 9-8
23214     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X159_TXEQ_OVER_EQ_CNT_I_9_8_SHIFT                         0
23215     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X159_UNUSED_0                                             (0x3f<<2) // reserved
23216     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X159_UNUSED_0_SHIFT                                       2
23217 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X160                                                          0x000a80UL //Access:R    DataWidth:0x8   Over equalization count 7-0  Chips: K2
23218 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X161                                                          0x000a84UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
23219     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X161_TXEQ_UNDER_EQ_CNT_I_9_8                              (0x3<<0) // Under equalization count 9-8
23220     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X161_TXEQ_UNDER_EQ_CNT_I_9_8_SHIFT                        0
23221     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X161_UNUSED_0                                             (0x3f<<2) // reserved
23222     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X161_UNUSED_0_SHIFT                                       2
23223 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X162                                                          0x000a88UL //Access:R    DataWidth:0x8   Under equalization count 7-0  Chips: K2
23224 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X163                                                          0x000a8cUL //Access:RW   DataWidth:0x8   TX Equalizer Training Pattern  Chips: K2
23225 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164                                                          0x000a90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23226     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164_TXEQ_TRAINING_PATT_O_8                               (0x1<<0) // TX Equalizer Training Pattern
23227     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164_TXEQ_TRAINING_PATT_O_8_SHIFT                         0
23228     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164_UNUSED_0                                             (0x7f<<1) // reserved
23229     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X164_UNUSED_0_SHIFT                                       1
23230 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X165                                                          0x000a94UL //Access:RW   DataWidth:0x8   Mask bit for Txeq training pattern  Chips: K2
23231 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166                                                          0x000a98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23232     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166_TXEQ_DONT_CARE_O_8                                   (0x1<<0) // Mask bit for Txeq training pattern
23233     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166_TXEQ_DONT_CARE_O_8_SHIFT                             0
23234     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166_UNUSED_0                                             (0x7f<<1) // reserved
23235     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X166_UNUSED_0_SHIFT                                       1
23236 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167                                                          0x000a9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23237     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7                                (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
23238     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167_TXEQ_RXRECAL_INIT_O_7_SHIFT                          0
23239     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167_UNUSED_0                                             (0x7f<<1) // reserved
23240     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X167_UNUSED_0_SHIFT                                       1
23241 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168                                                          0x000aa0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23242     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_INIT_RX_PRESET_HINT_EN_O                             (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
23243     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_INIT_RX_PRESET_HINT_EN_O_SHIFT                       0
23244     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_RECAL_RX_PRESET_HINT_EN_O                            (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
23245     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_RECAL_RX_PRESET_HINT_EN_O_SHIFT                      1
23246     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_UNUSED_0                                             (0x3f<<2) // reserved
23247     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X168_UNUSED_0_SHIFT                                       2
23248 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169                                                          0x000aa4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
23249     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169_TXEQ_RXRECAL_DONE_I_0                                (0x1<<0) // TX - RECAL RX Equalization status
23250     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169_TXEQ_RXRECAL_DONE_I_0_SHIFT                          0
23251     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169_UNUSED_0                                             (0x7f<<1) // reserved
23252     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X169_UNUSED_0_SHIFT                                       1
23253 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170                                                          0x000aa8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
23254     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170_BLOCK_DEC_ERR                                        (0x1<<0) // decoder sync header error
23255     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170_BLOCK_DEC_ERR_SHIFT                                  0
23256     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170_UNUSED_0                                             (0x7f<<1) // reserved
23257     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X170_UNUSED_0_SHIFT                                       1
23258 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201                                                          0x000b24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23259     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0                                          (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
23260     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_EN_O_0_SHIFT                                    0
23261     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0                                   (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
23262     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_WORD_OV_O_1_0_SHIFT                             1
23263     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0                                (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
23264     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_MODE_8B_OV_O_1_0_SHIFT                          3
23265     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_RATE_OV_O_2_0                                   (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
23266     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X201_CDFE_RATE_OV_O_2_0_SHIFT                             5
23267 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X202                                                          0x000b28UL //Access:RW   DataWidth:0x8     Chips: K2
23268 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203                                                          0x000b2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23269     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_UNUSED_0                                             (0xf<<0) // reserved
23270     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_UNUSED_0_SHIFT                                       0
23271     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO                                              (0x1<<4) //
23272     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_GO_SHIFT                                        4
23273     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL                                    (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
23274     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_FORCE_CAL_SHIFT                              5
23275     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL                              (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
23276     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_RATE_CHANGE_CAL_SHIFT                        6
23277     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL                                  (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
23278     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X203_CDFE_LN_EI_EXIT_CAL_SHIFT                            7
23279 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204                                                          0x000b30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23280     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL                                     (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
23281     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_CONT_CAL_SHIFT                               0
23282     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL                         (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
23283     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_SHIFT                   1
23284     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL                          (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
23285     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_SHIFT                    2
23286     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN                                 (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
23287     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE3_CAL_EN_SHIFT                           3
23288     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN                                 (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
23289     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_CDFE_LN_RATE2_CAL_EN_SHIFT                           4
23290     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_UNUSED_0                                             (0x7<<5) // reserved
23291     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X204_UNUSED_0_SHIFT                                       5
23292 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X205                                                          0x000b34UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
23293 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X206                                                          0x000b38UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
23294 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X207                                                          0x000b3cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
23295 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208                                                          0x000b40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23296     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_UNUSED_0                                             (0x7f<<0) // reserved
23297     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_UNUSED_0_SHIFT                                       0
23298     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN                            (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
23299     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X208_AHB_CDFE_COARSE_DLL_OV_EN_SHIFT                      7
23300 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X213                                                          0x000b54UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
23301 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X214                                                          0x000b58UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
23302 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X215                                                          0x000b5cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
23303 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X216                                                          0x000b60UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
23304 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X217                                                          0x000b64UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
23305 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X220                                                          0x000b70UL //Access:RW   DataWidth:0x8   Start value for dlev_ref.  Chips: K2
23306 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X221                                                          0x000b74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23307     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0               (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
23308     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT         0
23309     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X221_UNUSED_0                                             (0x7<<5) // reserved
23310     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X221_UNUSED_0_SHIFT                                       5
23311 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X222                                                          0x000b78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23312     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0           (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
23313     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT     0
23314     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X222_UNUSED_0                                             (0x7<<5) // reserved
23315     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X222_UNUSED_0_SHIFT                                       5
23316 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X223                                                          0x000b7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23317     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X223_AHB_CDFE_CMP1_TAP1_OFFSET                            (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
23318     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X223_AHB_CDFE_CMP1_TAP1_OFFSET_SHIFT                      0
23319     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X223_UNUSED_0                                             (0x1<<7) // reserved
23320     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X223_UNUSED_0_SHIFT                                       7
23321 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X224                                                          0x000b80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23322     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
23323     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_SHIFT                  0
23324     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X224_UNUSED_0                                             (0x3<<6) // reserved
23325     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X224_UNUSED_0_SHIFT                                       6
23326 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X225                                                          0x000b84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23327     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
23328     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_SHIFT                  0
23329     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X225_UNUSED_0                                             (0x3<<6) // reserved
23330     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X225_UNUSED_0_SHIFT                                       6
23331 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226                                                          0x000b88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23332     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
23333     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_SHIFT                  0
23334     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_UNUSED_0                                             (0x3<<6) // reserved
23335     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X226_UNUSED_0_SHIFT                                       6
23336 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X227                                                          0x000b8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23337     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X227_AHB_CDFE_CMP1_TAP5_OFFSET                            (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
23338     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X227_AHB_CDFE_CMP1_TAP5_OFFSET_SHIFT                      0
23339     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X227_UNUSED_0                                             (0x3<<6) // reserved
23340     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X227_UNUSED_0_SHIFT                                       6
23341 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X228                                                          0x000b90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23342     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X228_AHB_CDFE_CMP2_TAP1_OFFSET                            (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
23343     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X228_AHB_CDFE_CMP2_TAP1_OFFSET_SHIFT                      0
23344     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X228_UNUSED_0                                             (0x1<<7) // reserved
23345     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X228_UNUSED_0_SHIFT                                       7
23346 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X229                                                          0x000b94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23347     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
23348     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_SHIFT                  0
23349     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X229_UNUSED_0                                             (0x3<<6) // reserved
23350     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X229_UNUSED_0_SHIFT                                       6
23351 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X230                                                          0x000b98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23352     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
23353     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_SHIFT                  0
23354     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X230_UNUSED_0                                             (0x3<<6) // reserved
23355     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X230_UNUSED_0_SHIFT                                       6
23356 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X231                                                          0x000b9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23357     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
23358     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_SHIFT                  0
23359     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X231_UNUSED_0                                             (0x3<<6) // reserved
23360     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X231_UNUSED_0_SHIFT                                       6
23361 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X232                                                          0x000ba0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23362     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X232_AHB_CDFE_CMP2_TAP5_OFFSET                            (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
23363     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X232_AHB_CDFE_CMP2_TAP5_OFFSET_SHIFT                      0
23364     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X232_UNUSED_0                                             (0x3<<6) // reserved
23365     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X232_UNUSED_0_SHIFT                                       6
23366 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X233                                                          0x000ba4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23367     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X233_AHB_CDFE_CMP3_TAP1_OFFSET                            (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
23368     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X233_AHB_CDFE_CMP3_TAP1_OFFSET_SHIFT                      0
23369     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X233_UNUSED_0                                             (0x1<<7) // reserved
23370     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X233_UNUSED_0_SHIFT                                       7
23371 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X234                                                          0x000ba8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23372     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
23373     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_SHIFT                  0
23374     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X234_UNUSED_0                                             (0x3<<6) // reserved
23375     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X234_UNUSED_0_SHIFT                                       6
23376 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X235                                                          0x000bacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23377     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
23378     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_SHIFT                  0
23379     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X235_UNUSED_0                                             (0x3<<6) // reserved
23380     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X235_UNUSED_0_SHIFT                                       6
23381 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X236                                                          0x000bb0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23382     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
23383     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_SHIFT                  0
23384     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X236_UNUSED_0                                             (0x3<<6) // reserved
23385     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X236_UNUSED_0_SHIFT                                       6
23386 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X237                                                          0x000bb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23387     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X237_AHB_CDFE_CMP3_TAP5_OFFSET                            (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
23388     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X237_AHB_CDFE_CMP3_TAP5_OFFSET_SHIFT                      0
23389     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X237_UNUSED_0                                             (0x3<<6) // reserved
23390     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X237_UNUSED_0_SHIFT                                       6
23391 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X238                                                          0x000bb8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23392     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X238_AHB_CDFE_CMP4_TAP1_OFFSET                            (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
23393     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X238_AHB_CDFE_CMP4_TAP1_OFFSET_SHIFT                      0
23394     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X238_UNUSED_0                                             (0x1<<7) // reserved
23395     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X238_UNUSED_0_SHIFT                                       7
23396 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X239                                                          0x000bbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23397     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
23398     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_SHIFT                  0
23399     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X239_UNUSED_0                                             (0x3<<6) // reserved
23400     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X239_UNUSED_0_SHIFT                                       6
23401 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X240                                                          0x000bc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23402     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
23403     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_SHIFT                  0
23404     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X240_UNUSED_0                                             (0x3<<6) // reserved
23405     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X240_UNUSED_0_SHIFT                                       6
23406 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X241                                                          0x000bc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23407     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
23408     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_SHIFT                  0
23409     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X241_UNUSED_0                                             (0x3<<6) // reserved
23410     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X241_UNUSED_0_SHIFT                                       6
23411 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X242                                                          0x000bc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23412     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X242_AHB_CDFE_CMP4_TAP5_OFFSET                            (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
23413     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X242_AHB_CDFE_CMP4_TAP5_OFFSET_SHIFT                      0
23414     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X242_UNUSED_0                                             (0x3<<6) // reserved
23415     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X242_UNUSED_0_SHIFT                                       6
23416 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X243                                                          0x000bccUL //Access:RW   DataWidth:0x8   Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]  Chips: K2
23417 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X244                                                          0x000bd0UL //Access:RW   DataWidth:0x8   Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]  Chips: K2
23418 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X245                                                          0x000bd4UL //Access:RW   DataWidth:0x8   Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]  Chips: K2
23419 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X246                                                          0x000bd8UL //Access:RW   DataWidth:0x8   Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]  Chips: K2
23420 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X247                                                          0x000bdcUL //Access:RW   DataWidth:0x8     Chips: K2
23421 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248                                                          0x000be0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23422     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8                           (0x3<<0) //
23423     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_DLL_FINE_MASK_9_8_SHIFT                     0
23424     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT                         (0xf<<2) //
23425     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_SHIFT                   2
23426     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_UNUSED_0                                             (0x3<<6) // reserved
23427     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X248_UNUSED_0_SHIFT                                       6
23428 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249                                                          0x000be4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23429     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_ERR_SMPL_SHIFT                              (0xf<<0) //
23430     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_ERR_SMPL_SHIFT_SHIFT                        0
23431     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN                              (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
23432     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_AHB_CDFE_FINE_DLL_OV_EN_SHIFT                        4
23433     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_UNUSED_0                                             (0x7<<5) // reserved
23434     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X249_UNUSED_0_SHIFT                                       5
23435 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250                                                          0x000be8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23436     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8                    (0x1<<0) //
23437     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_SHIFT              0
23438     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8                   (0x1<<1) //
23439     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_SHIFT             1
23440     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8                    (0x1<<2) //
23441     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_SHIFT              2
23442     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8                   (0x1<<3) //
23443     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_SHIFT             3
23444     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_UNUSED_0                                             (0xf<<4) // reserved
23445     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X250_UNUSED_0_SHIFT                                       4
23446 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X251                                                          0x000becUL //Access:RW   DataWidth:0x8     Chips: K2
23447 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X252                                                          0x000bf0UL //Access:RW   DataWidth:0x8     Chips: K2
23448 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X253                                                          0x000bf4UL //Access:RW   DataWidth:0x8     Chips: K2
23449 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X254                                                          0x000bf8UL //Access:RW   DataWidth:0x8     Chips: K2
23450 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255                                                          0x000bfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23451     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN                                       (0x1<<0) // Override enable for CDFE calibration direction
23452     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_EN_SHIFT                                 0
23453     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL                                      (0x1<<1) // Override value for CDFE calibration direction
23454     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_CDFE_DIR_OV_VAL_SHIFT                                1
23455     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O                           (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
23456     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA270_OVR_EN_O_SHIFT                     2
23457     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O                            (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
23458     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_ENA90_OVR_EN_O_SHIFT                      3
23459     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O                              (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
23460     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_PHD_ENA_OVR_EN_O_SHIFT                        4
23461     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O                              (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
23462     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_DLY_OVR_EN_O_SHIFT                        5
23463     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O                          (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
23464     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_SHIFT                    6
23465     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_UNUSED_0                                             (0x1<<7) // reserved
23466     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X255_UNUSED_0_SHIFT                                       7
23467 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X256                                                          0x000c00UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK90.  Chips: K2
23468 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257                                                          0x000c04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23469     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8                       (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
23470     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_SHIFT                 0
23471     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0               (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
23472     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_SHIFT         1
23473 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X258                                                          0x000c08UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK270.  Chips: K2
23474 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259                                                          0x000c0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23475     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8                      (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
23476     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_SHIFT                0
23477     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN                                  (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
23478     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_AHB_CDFE_DLEV_OV_EN_SHIFT                            1
23479     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0                    (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
23480     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_SHIFT              2
23481     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8               (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
23482     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_SHIFT         7
23483 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X260                                                          0x000c10UL //Access:RW   DataWidth:0x8   Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value  Chips: K2
23484 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X261                                                          0x000c14UL //Access:RW   DataWidth:0x8   cdfe dlevn overwrite value.  Chips: K2
23485 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X262                                                          0x000c18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23486     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X262_AHB_CDFE_TAP_OV_EN                                   (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
23487     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X262_AHB_CDFE_TAP_OV_EN_SHIFT                             0
23488     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X262_UNUSED_0                                             (0x7<<5) // reserved
23489     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X262_UNUSED_0_SHIFT                                       5
23490 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X263                                                          0x000c1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23491     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X263_AHB_CDFE_TAP1_OV                                     (0x7f<<0) // cdfe tap1 overwrite value
23492     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X263_AHB_CDFE_TAP1_OV_SHIFT                               0
23493     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X263_UNUSED_0                                             (0x1<<7) // reserved
23494     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X263_UNUSED_0_SHIFT                                       7
23495 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X264                                                          0x000c20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23496     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X264_AHB_CDFE_TAP2_OV                                     (0x3f<<0) // cdfe tap2 overwrite value
23497     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X264_AHB_CDFE_TAP2_OV_SHIFT                               0
23498     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X264_UNUSED_0                                             (0x3<<6) // reserved
23499     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X264_UNUSED_0_SHIFT                                       6
23500 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X265                                                          0x000c24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23501     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X265_AHB_CDFE_TAP3_OV                                     (0x3f<<0) // cdfe tap3 overwrite value
23502     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X265_AHB_CDFE_TAP3_OV_SHIFT                               0
23503     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X265_UNUSED_0                                             (0x3<<6) // reserved
23504     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X265_UNUSED_0_SHIFT                                       6
23505 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X266                                                          0x000c28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23506     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X266_AHB_CDFE_TAP4_OV                                     (0x3f<<0) // cdfe tap4 overwrite value
23507     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X266_AHB_CDFE_TAP4_OV_SHIFT                               0
23508     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X266_UNUSED_0                                             (0x3<<6) // reserved
23509     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X266_UNUSED_0_SHIFT                                       6
23510 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267                                                          0x000c2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23511     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_AHB_CDFE_TAP5_OV                                     (0x3f<<0) // cdfe tap5 overwrite value
23512     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_AHB_CDFE_TAP5_OV_SHIFT                               0
23513     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_UNUSED_0                                             (0x1<<6) // reserved
23514     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_UNUSED_0_SHIFT                                       6
23515     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O               (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
23516     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_SHIFT         7
23517 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268                                                          0x000c30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23518     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O                       (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
23519     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_SHIFT                 0
23520     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O             (0x1<<1) //
23521     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_SHIFT       1
23522     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O         (0x1<<2) //
23523     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_SHIFT   2
23524     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_UNUSED_0                                             (0xf<<3) // reserved
23525     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_UNUSED_0_SHIFT                                       3
23526     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O                            (0x1<<7) //
23527     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_SHIFT                      7
23528 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269                                                          0x000c34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23529     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O                     (0x1<<0) //
23530     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_SHIFT               0
23531     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O                                 (0x1<<1) //
23532     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_STROBE_EN_O_SHIFT                           1
23533     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_CMP_ENA_O                                   (0xf<<2) //
23534     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_AHB_CDFE_CMP_ENA_O_SHIFT                             2
23535     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_UNUSED_0                                             (0x3<<6) // reserved
23536     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X269_UNUSED_0_SHIFT                                       6
23537 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X270                                                          0x000c38UL //Access:RW   DataWidth:0x8     Chips: K2
23538 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271                                                          0x000c3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23539     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0                          (0x1f<<0) //
23540     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_SHIFT                    0
23541     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O                  (0x1<<5) // Forces the positive dlev training pattern to be used
23542     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_SHIFT            5
23543     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O                  (0x1<<6) // Forces the negative dlev training pattern to be used
23544     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_SHIFT            6
23545     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_UNUSED_0                                             (0x1<<7) // reserved
23546     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X271_UNUSED_0_SHIFT                                       7
23547 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272                                                          0x000c40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23548     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP1 adapted value
23549     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SCALE_O_2_0_SHIFT                          0
23550     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP1 adapted value
23551     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X272_CDFE_TAP1_SHIFT_O_4_0_SHIFT                          3
23552 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273                                                          0x000c44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23553     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP2 adapted value
23554     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SCALE_O_2_0_SHIFT                          0
23555     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP2 adapted value
23556     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X273_CDFE_TAP2_SHIFT_O_4_0_SHIFT                          3
23557 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274                                                          0x000c48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23558     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP3 adapted value
23559     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SCALE_O_2_0_SHIFT                          0
23560     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP3 adapted value
23561     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X274_CDFE_TAP3_SHIFT_O_4_0_SHIFT                          3
23562 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275                                                          0x000c4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23563     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP4 adapted value
23564     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SCALE_O_2_0_SHIFT                          0
23565     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP4 adapted value
23566     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X275_CDFE_TAP4_SHIFT_O_4_0_SHIFT                          3
23567 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276                                                          0x000c50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23568     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP5 adapted value
23569     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SCALE_O_2_0_SHIFT                          0
23570     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP5 adapted value
23571     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X276_CDFE_TAP5_SHIFT_O_4_0_SHIFT                          3
23572 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277                                                          0x000c54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23573     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_RA_OVR_O                                (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
23574     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_RA_OVR_O_SHIFT                          0
23575     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_P2S_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
23576     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_P2S_OVR_O_SHIFT                         2
23577     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREGH_OVR_O                            (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
23578     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREGH_OVR_O_SHIFT                      4
23579     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREG_OVR_O                             (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
23580     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X277_LN_MSM_RESET_LNREG_OVR_O_SHIFT                       6
23581 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278                                                          0x000c58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23582     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_CDR_OVR_O                               (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
23583     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_CDR_OVR_O_SHIFT                         0
23584     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_DFE_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
23585     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_RESET_DFE_OVR_O_SHIFT                         2
23586     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_LNREGH_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
23587     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_LNREGH_OVR_O_SHIFT                         4
23588     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_VCO_BUF_OVR_O                              (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
23589     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X278_LN_MSM_PD_VCO_BUF_OVR_O_SHIFT                        6
23590 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279                                                          0x000c5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23591     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_CDR_GCRX_OVR_O                          (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
23592     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_SHIFT                    0
23593     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RXGATE_EN_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
23594     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RXGATE_EN_OVR_O_SHIFT                         2
23595     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_VCO_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
23596     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_RESET_VCO_OVR_O_SHIFT                         4
23597     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_IDDQ_SD_OVR_O                                 (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
23598     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X279_LN_MSM_IDDQ_SD_OVR_O_SHIFT                           6
23599 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280                                                          0x000c60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23600     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
23601     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_OVR_O_SHIFT                            0
23602     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_BIAS_OVR_O                             (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
23603     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_PD_DFE_BIAS_OVR_O_SHIFT                       2
23604     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O                           (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
23605     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_SHIFT                     4
23606     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O                         (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
23607     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_SHIFT                   6
23608 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281                                                          0x000c64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23609     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_TXREG_OVR_O                                (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
23610     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_TXREG_OVR_O_SHIFT                          0
23611     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_LNREG_OVR_O                                (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
23612     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_LNREG_OVR_O_SHIFT                          2
23613     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_P2S_OVR_O                                  (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
23614     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_P2S_OVR_O_SHIFT                            4
23615     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_RA_OVR_O                                   (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
23616     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X281_LN_MSM_PD_RA_OVR_O_SHIFT                             6
23617 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282                                                          0x000c68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23618     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_UNUSED_0                                             (0x3<<0) // reserved
23619     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_UNUSED_0_SHIFT                                       0
23620     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_SLV_BIAS_OVR_O                             (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
23621     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_SLV_BIAS_OVR_O_SHIFT                       2
23622     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_TXDRV_OVR_O                                (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
23623     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_TXDRV_OVR_O_SHIFT                          4
23624     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_VCO_OVR_O                                  (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
23625     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X282_LN_MSM_PD_VCO_OVR_O_SHIFT                            6
23626 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283                                                          0x000c6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23627     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_CDR_EN_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
23628     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_CDR_EN_OVR_O_SHIFT                            0
23629     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RESET_S2P_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
23630     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RESET_S2P_OVR_O_SHIFT                         2
23631     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RXCLK_EN_OVR_O                                (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
23632     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_RXCLK_EN_OVR_O_SHIFT                          4
23633     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_WORD_OVR_O                                    (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
23634     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X283_LN_MSM_WORD_OVR_O_SHIFT                              6
23635 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284                                                          0x000c70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23636     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RATE_OVR_O                                    (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
23637     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RATE_OVR_O_SHIFT                              0
23638     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O                                (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
23639     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RXVCODIV_OVR_O_SHIFT                          3
23640     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O                         (0x3<<6) // Not currently used
23641     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_SHIFT                   6
23642 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X285                                                          0x000c74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23643     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X285_LN_MSM_TXVCODIV_OVR_O                                (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
23644     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X285_LN_MSM_TXVCODIV_OVR_O_SHIFT                          0
23645     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X285_UNUSED_0                                             (0x1f<<3) // reserved
23646     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X285_UNUSED_0_SHIFT                                       3
23647 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301                                                          0x000cb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23648     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O                                             (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
23649     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_RX_SRC_O_SHIFT                                       0
23650     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O                                          (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
23651     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_POL_O_SHIFT                                    1
23652     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O                                          (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
23653     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_BIT_O_SHIFT                                    2
23654     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O                                         (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
23655     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_TREG0_WORD_O_SHIFT                                   3
23656     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_DMUX_TXA_SEL_O_1_0                                   (0x3<<4) // Transmit mux A data input select.
23657     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_DMUX_TXA_SEL_O_1_0_SHIFT                             4
23658     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O                                   (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
23659     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_P2S_RBUF_AUTOFIX_O_SHIFT                             6
23660     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_UNUSED_0                                             (0x1<<7) // reserved
23661     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X301_UNUSED_0_SHIFT                                       7
23662 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302                                                          0x000cb8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23663     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O                                          (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
23664     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_POL_O_SHIFT                                    0
23665     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O                                          (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
23666     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_BIT_O_SHIFT                                    1
23667     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O                                         (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
23668     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_TREG1_WORD_O_SHIFT                                   2
23669     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O                                           (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
23670     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_POL_O_SHIFT                                     3
23671     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O                                           (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
23672     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_BIT_O_SHIFT                                     4
23673     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O                                          (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
23674     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG1_WORD_O_SHIFT                                    5
23675     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O                                           (0x1<<6) // Used as Reg0 polarity select
23676     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_REG0_POL_O_SHIFT                                     6
23677     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_UNUSED_0                                             (0x1<<7) // reserved
23678     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X302_UNUSED_0_SHIFT                                       7
23679 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303                                                          0x000cbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23680     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O                                           (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
23681     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_BIT_O_SHIFT                                     0
23682     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O                                          (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
23683     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_REG0_WORD_O_SHIFT                                    1
23684     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_DMUX_TXB_SEL_O_2_0                                   (0x7<<2) // Transmit mux B data input select enable.
23685     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_DMUX_TXB_SEL_O_2_0_SHIFT                             2
23686     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24                                         (0x1<<5) // Bit 24: txdrv_c2_in[3]
23687     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TX_CTRL_O_24_SHIFT                                   5
23688     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O                                      (0x1<<6) // Enable bit for width_chng module
23689     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_WIDTH_CHNG_EN_O_SHIFT                                6
23690     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O                                  (0x1<<7) // Txterm calibration enable
23691     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X303_TXTERM_CAL_SEQ_EN_O_SHIFT                            7
23692 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304                                                          0x000cc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23693     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_TXTERM_CAL_RSEL                                      (0x7<<0) // tx termination calibration comparator threshold select
23694     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_TXTERM_CAL_RSEL_SHIFT                                0
23695     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O                                 (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2?b00: no bit stripping 2?b01: 2x bit stripping 2?b10: reserved 2?b11: 4x bit stripping
23696     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_LN_RXBIT_STRIP_O_SHIFT                           3
23697     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_MAC_WIDTH_O                                      (0x3<<5) // Data width selector for PCS/MAC interface. 2?b00: GigE or XAUI 2?b01: GigE or XAUI 2?b10: RXAUI 2?b11: XFI
23698     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_AHB_MAC_WIDTH_O_SHIFT                                5
23699     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_UNUSED_0                                             (0x1<<7) // reserved
23700     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X304_UNUSED_0_SHIFT                                       7
23701 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305                                                          0x000cc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23702     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_AHB_TXMAC_THRESHOLD_O                                (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
23703     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_AHB_TXMAC_THRESHOLD_O_SHIFT                          0
23704     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_AHB_LN_TXBIT_REPEAT_O                                (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2?b00: no bit stuffing nor stripping 2?b01: 2x bit stuffing and stripping 2?b10: reserved 2?b11: 4x bit stuffing and stripping
23705     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_AHB_LN_TXBIT_REPEAT_O_SHIFT                          2
23706     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_MODE_8B_O_1_0                                        (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
23707     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_MODE_8B_O_1_0_SHIFT                                  4
23708     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O                                             (0x1<<6) // 8b/10b encoder enable.
23709     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_ENC_EN_O_SHIFT                                       6
23710     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O                                             (0x1<<7) // 8b/10b decoder enable.
23711     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X305_DEC_EN_O_SHIFT                                       7
23712 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306                                                          0x000cc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23713     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_AHB_TX_CDAC_OVR                                      (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
23714     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_AHB_TX_CDAC_OVR_SHIFT                                0
23715     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_LN_COMMON_SYNC_TXCLK_EN_O                            (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
23716     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_LN_COMMON_SYNC_TXCLK_EN_O_SHIFT                      4
23717     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_UNUSED_0                                             (0x7<<5) // reserved
23718     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X306_UNUSED_0_SHIFT                                       5
23719 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307                                                          0x000cccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23720     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_LN_TO_CLK_TXB_WAIT_O                                 (0x1f<<0) // In per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA. The lnX_ok_o will get asserted after lnX_to_clk_txb_wait_o lnX_ck_txb_o cycles.
23721     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_LN_TO_CLK_TXB_WAIT_O_SHIFT                           0
23722     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O                                            (0x1<<5) // PIPE interface block enable.
23723     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_PIPE_EN_O_SHIFT                                      5
23724     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O                                           (0x1<<6) // SAPIS interface block enable.
23725     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_SAPIS_EN_O_SHIFT                                     6
23726     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE                                             (0x1<<7) // Signal Detect USB mode enable
23727     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X307_USB_MODE_SHIFT                                       7
23728 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308                                                          0x000cd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23729     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_UNUSED_0                                             (0x1<<0) // reserved
23730     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_UNUSED_0_SHIFT                                       0
23731     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_ENC_CLR_ERR_O                                  (0x1<<1) // 128b/130b encoder clear error
23732     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_ENC_CLR_ERR_O_SHIFT                            1
23733     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_UNUSED_1                                             (0x1<<2) // reserved
23734     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_UNUSED_1_SHIFT                                       2
23735     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_EN_ERR_CHK_O                               (0x1<<3) // 130b/128b error check enable
23736     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_EN_ERR_CHK_O_SHIFT                         3
23737     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0                          (0x7<<4) // 130b/128b: number of OS indicating end of data
23738     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_SHIFT                    4
23739     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CLR_ERR_O                                  (0x1<<7) // 130b/128b: clear error flag
23740     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X308_BLOCK_DEC_CLR_ERR_O_SHIFT                            7
23741 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309                                                          0x000cd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23742     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0                        (0xf<<0) // 130b/128b: number of sync hdr errors before asserting sync error flag
23743     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_SHIFT                  0
23744     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0                         (0xf<<4) // 130b/128b: number of continuous blocks checked
23745     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_SHIFT                   4
23746 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310                                                          0x000cd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23747     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_RSTN_O                                          (0x1<<0) // Synchronous clear for elastic buffer
23748     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_RSTN_O_SHIFT                                    0
23749     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_ALIGN_RSTN_O                                         (0x1<<1) // Synchronous clear for block/symbol aligner
23750     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_ALIGN_RSTN_O_SHIFT                                   1
23751     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_SKP_ADD_EN_O                                    (0x1<<2) // Elastic buffer SKP add enable
23752     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EBUF_SKP_ADD_EN_O_SHIFT                              2
23753     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_RBUF_RSTN_O                                          (0x1<<3) // TX FIFO synchronous reset
23754     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_RBUF_RSTN_O_SHIFT                                    3
23755     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_UNUSED_0                                             (0x1<<4) // reserved
23756     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_UNUSED_0_SHIFT                                       4
23757     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EN_SKPOS_ERR_O                                       (0x1<<5) // Enables skpos error status propagation in Gen3
23758     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_EN_SKPOS_ERR_O_SHIFT                                 5
23759     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_UNUSED_1                                             (0x3<<6) // reserved
23760     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X310_UNUSED_1_SHIFT                                       6
23761 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311                                                          0x000cdcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23762     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_PIPE_LFREQ                                           (0x3f<<0) // LF value for full swing
23763     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_PIPE_LFREQ_SHIFT                                     0
23764     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_BLOCK_ALIGN_CTRL_O                               (0x1<<6) // Disables the primary input lnX_block_align_control
23765     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_BLOCK_ALIGN_CTRL_O_SHIFT                         6
23766     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_EIEOS_CHK_IN_LB_O                                (0x1<<7) // Disables the EIEOS check in loopback
23767     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X311_DIS_EIEOS_CHK_IN_LB_O_SHIFT                          7
23768 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312                                                          0x000ce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23769     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_COEF_FE_LIMIT_EN_O                                   (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
23770     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_COEF_FE_LIMIT_EN_O_SHIFT                             0
23771     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_RXVALID_DIS_AT_RATE_CHG_O_0                          (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
23772     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_RXVALID_DIS_AT_RATE_CHG_O_0_SHIFT                    1
23773     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_P2S_RBUF_BUF_THRESH_O_3_0                            (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted
23774     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_P2S_RBUF_BUF_THRESH_O_3_0_SHIFT                      2
23775     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_UNUSED_0                                             (0x3<<6) // reserved
23776     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X312_UNUSED_0_SHIFT                                       6
23777 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313                                                          0x000ce4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23778     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_RX_GEARBOX_DISABLE_O                             (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
23779     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_RX_GEARBOX_DISABLE_O_SHIFT                       0
23780     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_TX_GEARBOX_DISABLE_O                             (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
23781     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_AHB_TX_GEARBOX_DISABLE_O_SHIFT                       1
23782     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_UNUSED_0                                             (0x3f<<2) // reserved
23783     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X313_UNUSED_0_SHIFT                                       2
23784 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314                                                          0x000ce8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23785     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC                                  (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
23786     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_GEN1_OLD_RXDATA_SRC_SHIFT                            0
23787     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O                                      (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
23788     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN3_O_SHIFT                                1
23789     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O                                     (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
23790     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_SKIP_CDR_GEN12_O_SHIFT                               2
23791     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0                           (0x1<<3) // Receive amplifier powerdown override, when cisel is high
23792     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_SHIFT                     3
23793     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_LN_P2S_RBUF_REALIGN_DIFF_O                           (0xf<<4) // In per lane common synchronous clock mode, ln_p2x_rbuf_realign_diff_o defines the starting difference between write pointer and read pointer when re aligning the pointer of TxFIFO.
23794     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X314_LN_P2S_RBUF_REALIGN_DIFF_O_SHIFT                     4
23795 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X315                                                          0x000cecUL //Access:RW   DataWidth:0x8   Delays the beacon_ena propagation to PMA  Chips: K2
23796 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X316                                                          0x000cf0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23797     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O               (0xf<<0) // Delays the beacon_ena propagation to PMA
23798     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_SHIFT         0
23799     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X316_UNUSED_0                                             (0xf<<4) // reserved
23800     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X316_UNUSED_0_SHIFT                                       4
23801 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317                                                          0x000cf4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23802     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O                             (0x1<<0) // Beacon Override Enable
23803     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_ENA_O_SHIFT                       0
23804     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O                                 (0x1<<1) // Beacon Override
23805     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_AHB_BEACON_ENA_OVR_O_SHIFT                           1
23806     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O                                         (0x1<<2) // Enables 16b/20b decoder
23807     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_DEC_EN_OVR_O_SHIFT                                   2
23808     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O                                         (0x1<<3) // Enables 16b/20b encoder
23809     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_ENC_EN_OVR_O_SHIFT                                   3
23810     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_REGP_OVR_3_0                                         (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
23811     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X317_REGP_OVR_3_0_SHIFT                                   4
23812 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318                                                          0x000cf8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23813     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_SIGDET_OVR_O_1_0                                     (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
23814     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_SIGDET_OVR_O_1_0_SHIFT                               0
23815     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_LN_OUT_OVR_1_0                                       (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
23816     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_LN_OUT_OVR_1_0_SHIFT                                 2
23817     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_RXEQ_SIGDET_1_0                                      (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
23818     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_RXEQ_SIGDET_1_0_SHIFT                                4
23819     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_UNUSED_0                                             (0x3<<6) // reserved
23820     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X318_UNUSED_0_SHIFT                                       6
23821 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319                                                          0x000cfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23822     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_TXDETECTRX_OVR_O_1_0                                 (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
23823     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_TXDETECTRX_OVR_O_1_0_SHIFT                           0
23824     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_RXDET_STATUS_OVR_O_1_0                               (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
23825     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_RXDET_STATUS_OVR_O_1_0_SHIFT                         2
23826     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_LOCKED_OVR_O_1_0                                     (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
23827     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_LOCKED_OVR_O_1_0_SHIFT                               4
23828     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O                     (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
23829     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_SHIFT               6
23830     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O                         (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
23831     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_SHIFT                   7
23832 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X320                                                          0x000d00UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
23833 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X321                                                          0x000d04UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
23834 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X322                                                          0x000d08UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
23835 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X323                                                          0x000d0cUL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
23836 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X324                                                          0x000d10UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
23837 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X325                                                          0x000d14UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
23838 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326                                                          0x000d18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23839     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48                                       (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
23840     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_48_SHIFT                                 0
23841     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O                             (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
23842     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_AHB_LN_IN_OVR_CHG_FLAG_O_SHIFT                       1
23843     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_REGP1_OVR_O_3_0                                      (0xf<<2) // Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
23844     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_REGP1_OVR_O_3_0_SHIFT                                2
23845     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN                                           (0x1<<6) // OOB detect enable
23846     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_OOB_DET_EN_SHIFT                                     6
23847     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49                                       (0x1<<7) // OOB detect enable
23848     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X326_LN_IN_OVR_O_49_SHIFT                                 7
23849 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X327                                                          0x000d1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23850     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X327_CDR_CTRL_DLY_DLPF_EN_O                               (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
23851     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X327_CDR_CTRL_DLY_DLPF_EN_O_SHIFT                         0
23852     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X327_UNUSED_0                                             (0x7<<5) // reserved
23853     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X327_UNUSED_0_SHIFT                                       5
23854 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330                                                          0x000d28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23855     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0                     (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
23856     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_SHIFT               0
23857     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50                                       (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
23858     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_LN_IN_OVR_O_50_SHIFT                                 3
23859     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_UNUSED_0                                             (0xf<<4) // reserved
23860     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_1_X330_UNUSED_0_SHIFT                                       4
23861 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0                                                            0x001000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23862     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_UNUSED_0                                               (0x7f<<0) // reserved
23863     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_UNUSED_0_SHIFT                                         0
23864     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O                             (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
23865     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_SHIFT                       7
23866 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1                                                            0x001004UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23867     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_UNUSED_0                                               (0x7<<0) // reserved
23868     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_UNUSED_0_SHIFT                                         0
23869     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O                             (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
23870     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_SHIFT                       3
23871     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_UNUSED_1                                               (0x7<<4) // reserved
23872     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_UNUSED_1_SHIFT                                         4
23873     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O                             (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
23874     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_SHIFT                       7
23875 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2                                                            0x001008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23876     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_UNUSED_0                                               (0x7f<<0) // reserved
23877     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_UNUSED_0_SHIFT                                         0
23878     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O                             (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
23879     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_SHIFT                       7
23880 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3                                                            0x00100cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23881     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_CMU_SEL_O_0                                        (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
23882     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_CMU_SEL_O_0_SHIFT                                  0
23883     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_TXCLK_SEL_O_1                                      (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
23884     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_PMA_TXCLK_SEL_O_1_SHIFT                                1
23885     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_UNUSED_0                                               (0x3f<<2) // reserved
23886     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X3_UNUSED_0_SHIFT                                         2
23887 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4                                                            0x001010UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23888     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_CDRCTRL_DIV_EN_O_1_0                                   (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
23889     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_CDRCTRL_DIV_EN_O_1_0_SHIFT                             0
23890     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_GCFSM_DIV_EN_O_1_0                                     (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
23891     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_GCFSM_DIV_EN_O_1_0_SHIFT                               2
23892     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_LN_CLK_TXB_DIV24OR1_O                                  (0x3<<4) // Divide ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state:                                            2'b00: lnX_ck_txb_o is divided by 1 version of the tx byte clock from PMA.                     2'b01/2'b10: lnX_ck_txb_o is divided by 2 version of the tx byte clock from PMA.                  2'b11: lnX_ck_txb_o is divided by 4 version of the tx byte clock from PMA.
23893     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_LN_CLK_TXB_DIV24OR1_O_SHIFT                            4
23894     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_AHB_CHNG_REQ_Z_O                                       (0x1<<6) // Not currently used
23895     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_AHB_CHNG_REQ_Z_O_SHIFT                                 6
23896     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_UNUSED_0                                               (0x1<<7) // reserved
23897     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X4_UNUSED_0_SHIFT                                         7
23898 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5                                                            0x001014UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23899     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_REF_CLK_DIV_EN_O_1_0                                   (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
23900     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_REF_CLK_DIV_EN_O_1_0_SHIFT                             0
23901     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_OOB_CLK_DIV_EN_O_1_0                                   (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
23902     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_OOB_CLK_DIV_EN_O_1_0_SHIFT                             2
23903     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_UNUSED_0                                               (0xf<<4) // reserved
23904     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X5_UNUSED_0_SHIFT                                         4
23905 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7                                                            0x00101cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23906     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_RATE_O                                            (0x3<<0) // Rate control for BIST
23907     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_RATE_O_SHIFT                                      0
23908     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_MODE8B_O                                      (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
23909     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_MODE8B_O_SHIFT                                2
23910     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_ERR_O                                         (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
23911     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_ERR_O_SHIFT                                   3
23912     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_TX_CLOCK_ENABLE                                   (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
23913     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_TX_CLOCK_ENABLE_SHIFT                             4
23914     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_CDN_O                                         (0x1<<5) // Bist generator master reset.
23915     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_CDN_O_SHIFT                                   5
23916     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_WORD_O                                        (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
23917     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_WORD_O_SHIFT                                  6
23918     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_EN_O                                          (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
23919     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X7_BIST_GEN_EN_O_SHIFT                                    7
23920 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8                                                            0x001020UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23921     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_CLK_SEL_O_2_0                                 (0x7<<0) // BIST Generation Clock Selection
23922     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_CLK_SEL_O_2_0_SHIFT                           0
23923     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_SEND_PREAM_O                                  (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
23924     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_SEND_PREAM_O_SHIFT                            3
23925     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_INSERT_COUNT_O_2_0                            (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
23926     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_BIST_GEN_INSERT_COUNT_O_2_0_SHIFT                      4
23927     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_UNUSED_0                                               (0x1<<7) // reserved
23928     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X8_UNUSED_0_SHIFT                                         7
23929 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X9                                                            0x001024UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
23930 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X10                                                           0x001028UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
23931 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X11                                                           0x00102cUL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
23932 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X12                                                           0x001030UL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
23933 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X13                                                           0x001034UL //Access:RW   DataWidth:0x8   Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.  Chips: K2
23934 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14                                                           0x001038UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23935     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BIST_GEN_INSERT_DELAY_O_11_8                          (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
23936     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BIST_GEN_INSERT_DELAY_O_11_8_SHIFT                    0
23937     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_UNUSED_0                                              (0x1<<4) // reserved
23938     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_UNUSED_0_SHIFT                                        4
23939     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_EN_O                                             (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
23940     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_EN_O_SHIFT                                       5
23941     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_CLR_O                                            (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
23942     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_BCHK_CLR_O_SHIFT                                      6
23943     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_UNUSED_1                                              (0x1<<7) // reserved
23944     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X14_UNUSED_1_SHIFT                                        7
23945 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15                                                           0x00103cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23946     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BCHK_SRC_O_1_0                                        (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
23947     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BCHK_SRC_O_1_0_SHIFT                                  0
23948     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_UNUSED_0                                              (0x1<<2) // reserved
23949     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_UNUSED_0_SHIFT                                        2
23950     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_DATA_MODE_O                                  (0x1<<3) // Bist checker mode select. 0X0 ? UDP pattern. 0x1 ? PRBS pattern
23951     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_DATA_MODE_O_SHIFT                            3
23952     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_LFSR_LENGTH_O_1_0                            (0x3<<4) // BIST PRBS pattern selector.
23953     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_CHK_LFSR_LENGTH_O_1_0_SHIFT                      4
23954     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_UNUSED_1                                              (0x1<<6) // reserved
23955     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_UNUSED_1_SHIFT                                        6
23956     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_RX_CLOCK_ENABLE                                  (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
23957     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X15_BIST_RX_CLOCK_ENABLE_SHIFT                            7
23958 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X16                                                           0x001040UL //Access:RW   DataWidth:0x8   Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.  Chips: K2
23959 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17                                                           0x001044UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23960     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_PREAM0_O_9_8                                 (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
23961     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_PREAM0_O_9_8_SHIFT                           0
23962     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_INSERT_LENGTH_O_2_0                          (0x7<<2) // BIST Checker Insert word length.
23963     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_INSERT_LENGTH_O_2_0_SHIFT                    2
23964     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_SYNC_ON_ZEROS                                (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
23965     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_BIST_CHK_SYNC_ON_ZEROS_SHIFT                          5
23966     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_UNUSED_0                                              (0x3<<6) // reserved
23967     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X17_UNUSED_0_SHIFT                                        6
23968 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X18                                                           0x001048UL //Access:RW   DataWidth:0x8   BIST Check Preamble  Chips: K2
23969 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X19                                                           0x00104cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
23970     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X19_BIST_CHK_PREAM1_O_9_8                                 (0x3<<0) // BIST Check Preamble
23971     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X19_BIST_CHK_PREAM1_O_9_8_SHIFT                           0
23972     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X19_UNUSED_0                                              (0x3f<<2) // reserved
23973     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X19_UNUSED_0_SHIFT                                        2
23974 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X20                                                           0x001050UL //Access:RW   DataWidth:0x8   Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.  Chips: K2
23975 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X21                                                           0x001054UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
23976 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X22                                                           0x001058UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
23977 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X23                                                           0x00105cUL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
23978 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X24                                                           0x001060UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
23979 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X25                                                           0x001064UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
23980 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X26                                                           0x001068UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
23981 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X27                                                           0x00106cUL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
23982 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X28                                                           0x001070UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
23983 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X29                                                           0x001074UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
23984 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X30                                                           0x001078UL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
23985 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X31                                                           0x00107cUL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
23986 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X32                                                           0x001080UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
23987 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X33                                                           0x001084UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
23988 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X34                                                           0x001088UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
23989 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X35                                                           0x00108cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
23990 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X36                                                           0x001090UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
23991 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X37                                                           0x001094UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
23992 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X38                                                           0x001098UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
23993 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X39                                                           0x00109cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
23994 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X40                                                           0x0010a0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
23995 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X41                                                           0x0010a4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
23996 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X42                                                           0x0010a8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
23997 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X43                                                           0x0010acUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
23998 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X44                                                           0x0010b0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
23999 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X45                                                           0x0010b4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
24000 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X46                                                           0x0010b8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
24001 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X47                                                           0x0010bcUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
24002 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X48                                                           0x0010c0UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 1/2 - for the new ICA method  Chips: K2
24003 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X49                                                           0x0010c4UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 3 - for the new ICA method  Chips: K2
24004 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X50                                                           0x0010c8UL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method  Chips: K2
24005 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X51                                                           0x0010ccUL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method  Chips: K2
24006 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X52                                                           0x0010d0UL //Access:RW   DataWidth:0x8   The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.  Chips: K2
24007 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53                                                           0x0010d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24008     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0                  (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
24009     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_SHIFT            0
24010     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2                           (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
24011     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_SHIFT                     5
24012     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_TW_METHOD_EN                               (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
24013     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_TW_METHOD_EN_SHIFT                         6
24014     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_PMA_LOAD_OVR                               (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
24015     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X53_GCFSM_LANE_PMA_LOAD_OVR_SHIFT                         7
24016 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X54                                                           0x0010d8UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
24017 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X55                                                           0x0010dcUL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
24018 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X56                                                           0x0010e0UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
24019 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57                                                           0x0010e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24020     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_OVR_O_27_24                                     (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
24021     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_OVR_O_27_24_SHIFT                               0
24022     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_OUT_OVR_EN_O                               (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
24023     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_OUT_OVR_EN_O_SHIFT                         4
24024     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_LATCH_OVR_O                            (0x1<<5) // GCFSM pma_latch_o override
24025     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_LATCH_OVR_O_SHIFT                      5
24026     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_GO_OVR_O                               (0x1<<6) // GCFSM pma_go_o override
24027     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_GO_OVR_O_SHIFT                         6
24028     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_READ_OVR_O                             (0x1<<7) // GCFSM pma_read_o override.
24029     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X57_GCFSM_LANE_PMA_READ_OVR_O_SHIFT                       7
24030 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X58                                                           0x0010e8UL //Access:RW   DataWidth:0x8   GCFSM pma_data_o override data. Bits applied to PMA are [8:15]  Chips: K2
24031 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X59                                                           0x0010ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24032     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8                        (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
24033     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_SHIFT                  0
24034     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X59_UNUSED_0                                              (0xf<<4) // reserved
24035     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X59_UNUSED_0_SHIFT                                        4
24036 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X60                                                           0x0010f0UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
24037 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X61                                                           0x0010f4UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
24038 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62                                                           0x0010f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24039     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_LN_MSM_REQ_IN_OVR_O                                   (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
24040     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_LN_MSM_REQ_IN_OVR_O_SHIFT                             0
24041     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_LN_MSM_FUNC_IN_OVR_O                                  (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
24042     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X62_LN_MSM_FUNC_IN_OVR_O_SHIFT                            2
24043 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65                                                           0x001104UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24044     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65_GCFSM_OVR_O_28                                        (0x1<<0) // Not currently used
24045     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65_GCFSM_OVR_O_28_SHIFT                                  0
24046     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65_UNUSED_0                                              (0x7f<<1) // reserved
24047     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X65_UNUSED_0_SHIFT                                        1
24048 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X66                                                           0x001108UL //Access:RW   DataWidth:0x8   Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.  Chips: K2
24049 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67                                                           0x00110cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24050     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_DLY_CDR_O_6_0                                (0x7f<<0) // Number of clock cycles between signal detect indicator
24051     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_DLY_CDR_O_6_0_SHIFT                          0
24052     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8                           (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
24053     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_SHIFT                     7
24054 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X68                                                           0x001110UL //Access:RW   DataWidth:0x8   Number of clock cycles between CISEL assertion  Chips: K2
24055 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69                                                           0x001114UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24056     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_DLY_LANE_O_9_8                               (0x3<<0) // Number of clock cycles between CISEL assertion
24057     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_DLY_LANE_O_9_8_SHIFT                         0
24058     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_START_LEN_O_3_0                              (0xf<<2) // Number of clock cycles between when CDR control block
24059     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_START_LEN_O_3_0_SHIFT                        2
24060     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_INT_FIL_O_1_0                                (0x3<<6) // CDR control DLPF positioning control.
24061     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X69_CDR_CTRL_INT_FIL_O_1_0_SHIFT                          6
24062 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X70                                                           0x001118UL //Access:RW   DataWidth:0x8   CDR control block cycle length When not in PCIe Gen3.  Chips: K2
24063 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X71                                                           0x00111cUL //Access:RW   DataWidth:0x8   CDR control block cycle length When in PCIe Gen3.  Chips: K2
24064 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72                                                           0x001120UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24065     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_CDR_CTRL_MAX_DIFF_O_4_0                               (0x1f<<0) // Maximum difference from DLPF center point.
24066     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_CDR_CTRL_MAX_DIFF_O_4_0_SHIFT                         0
24067     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_CDR_CTRL_MIN_BOUNCE_O_2_0                             (0x7<<5) // Maximum difference from DLPF center point.
24068     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_SHIFT                       5
24069 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73                                                           0x001124UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24070     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_TW_METHOD_EN                                 (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
24071     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_TW_METHOD_EN_SHIFT                           0
24072     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CONTROL_ATT_CTRL_O                                (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
24073     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CONTROL_ATT_CTRL_O_SHIFT                          1
24074     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_RXEQ_WAIT_EN_O                                        (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
24075     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_RXEQ_WAIT_EN_O_SHIFT                                  2
24076     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_DLY_CDR_O_9_7                                (0x7<<3) // Number of clock cycles between signal detect indicator
24077     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_CDR_CTRL_DLY_CDR_O_9_7_SHIFT                          3
24078     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_UNUSED_0                                              (0x3<<6) // reserved
24079     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X73_UNUSED_0_SHIFT                                        6
24080 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X74                                                           0x001128UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
24081 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X75                                                           0x00112cUL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
24082 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X76                                                           0x001130UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
24083 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77                                                           0x001134UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24084     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_OUT_OVR_O_29_24                              (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
24085     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_OUT_OVR_O_29_24_SHIFT                        0
24086     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_CAL_LOAD_OVR                                 (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
24087     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_CDR_CTRL_CAL_LOAD_OVR_SHIFT                           6
24088     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_UNUSED_0                                              (0x1<<7) // reserved
24089     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X77_UNUSED_0_SHIFT                                        7
24090 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78                                                           0x001138UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24091     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_SYM_ALIGN_ALIGN_POS_O_5_0                             (0x3f<<0) // Symbol aligner position override enable.
24092     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_SYM_ALIGN_ALIGN_POS_O_5_0_SHIFT                       0
24093     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_SYM_ALIGN_MODE_O_1_0                                  (0x3<<6) // Symbol aligner mode select.
24094     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X78_SYM_ALIGN_MODE_O_1_0_SHIFT                            6
24095 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79                                                           0x00113cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24096     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79_SYM_ALIGN_BYPASS_O                                    (0x1<<0) // Asserting this register will bypass the symbol aligner
24097     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79_SYM_ALIGN_BYPASS_O_SHIFT                              0
24098     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79_UNUSED_0                                              (0x7f<<1) // reserved
24099     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X79_UNUSED_0_SHIFT                                        1
24100 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X80                                                           0x001140UL //Access:RW   DataWidth:0x8   Number of cycles to wait before forcing exit form EI  Chips: K2
24101 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81                                                           0x001144UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24102     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8                    (0x3<<0) // Number of cycles to wait before forcing exit form EI
24103     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_SHIFT              0
24104     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_CLR_ERR_O                               (0x1<<2) // Clears the elec idle control error flag
24105     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_CLR_ERR_O_SHIFT                         2
24106     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_INFERRED_O                           (0x1<<3) // Override for ei_inferred signal
24107     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_INFERRED_O_SHIFT                     3
24108     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O                        (0x1<<4) // Override for ei_mask signal
24109     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_SHIFT                  4
24110     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O                         (0x1<<5) // Override for ei_exit_type signal
24111     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_SHIFT                   5
24112     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_OVR_O                                   (0x1<<6) // EI control override enable
24113     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_ELECIDLE_CTRL_OVR_O_SHIFT                             6
24114     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_UNUSED_0                                              (0x1<<7) // reserved
24115     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X81_UNUSED_0_SHIFT                                        7
24116 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X82                                                           0x001148UL //Access:RW   DataWidth:0x8   Number of cycles to wait before entering back into EI  Chips: K2
24117 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X83                                                           0x00114cUL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect glitch filter counter  Chips: K2
24118 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X84                                                           0x001150UL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect low filter min value  Chips: K2
24119 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85                                                           0x001154UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24120     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8                    (0x3<<0) // Number of cycles to wait before entering back into EI
24121     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_SHIFT              0
24122     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0                     (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
24123     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_SHIFT               2
24124     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_LOOPBACK_EN_O                                         (0x1<<4) // Control signal to force decoder into loopback mode
24125     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_LOOPBACK_EN_O_SHIFT                                   4
24126     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_UNUSED_0                                              (0x7<<5) // reserved
24127     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X85_UNUSED_0_SHIFT                                        5
24128 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86                                                           0x001158UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24129     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_FES_LB_ENA_O                                          (0x1<<0) // FES loopback enable.
24130     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_FES_LB_ENA_O_SHIFT                                    0
24131     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_NES_LB_ENA_O                                          (0x1<<1) // NES loopback enable.
24132     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_NES_LB_ENA_O_SHIFT                                    1
24133     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_RXCLK_LB_ENA_O                                        (0x1<<2) // HS recovered clock to transmit loopback enable.
24134     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_RXCLK_LB_ENA_O_SHIFT                                  2
24135     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_UNUSED_0                                              (0x1f<<3) // reserved
24136     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X86_UNUSED_0_SHIFT                                        3
24137 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87                                                           0x00115cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24138     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOST_OVR_O                             (0x1<<0) // RX boost override enable
24139     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOST_OVR_O_SHIFT                       0
24140     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O                        (0x7f<<1) // RX boost override setting. Thermometer coded.
24141     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_SHIFT                  1
24142 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X88                                                           0x001160UL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
24143 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89                                                           0x001164UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24144     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV1_O                            (0x7<<0) // Signal detect threshold select for Full rate
24145     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_SHIFT                      0
24146     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV2_O                            (0x7<<3) // Signal detect threshold select for div-by-2 rate
24147     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_SHIFT                      3
24148     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXUP_O                                     (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
24149     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXUP_O_SHIFT                               6
24150     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXPREDIV4_ENA_O                            (0x1<<7) // RX FL calibration clock DIV4 enable
24151     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_SHIFT                      7
24152 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90                                                           0x001168UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24153     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_SD_THSEL_DIV4_O                            (0x7<<0) // Signal detect threshold select for div-by-4 rate
24154     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_SHIFT                      0
24155     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_AGC_THSEL_O                                (0x7<<3) // AGC threshold select
24156     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_AGC_THSEL_O_SHIFT                          3
24157     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_VREGH_O                                    (0x3<<6) // Regulator VREGH setting
24158     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X90_AHB_PMA_LN_VREGH_O_SHIFT                              6
24159 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X91                                                           0x00116cUL //Access:RW   DataWidth:0x8   RX FL calibration LDHS  Chips: K2
24160 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92                                                           0x001170UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24161     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O                            (0x3<<0) // RX FL calibration LDHS
24162     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_SHIFT                      0
24163     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_RXVCO_BIAS_O                               (0xf<<2) // CDR VCO bias setting.
24164     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_RXVCO_BIAS_O_SHIFT                         2
24165     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O                            (0x1<<6) // DLPF DIV2 enable
24166     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_SHIFT                      6
24167     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_CDR_DVDR_ENA_O                             (0x1<<7) // CDR DivN clock divider enable.
24168     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_SHIFT                       7
24169 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X93                                                           0x001174UL //Access:RW   DataWidth:0x8   AFE spare controls  Chips: K2
24170 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94                                                           0x001178UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24171     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_AHB_PMA_LN_CDR_DVDR_O                                 (0x3f<<0) // CDR DivN clock division ratio.
24172     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_AHB_PMA_LN_CDR_DVDR_O_SHIFT                           0
24173     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_AHB_PMA_LN_VREG_O                                     (0x3<<6) // Regulator VREG setting
24174     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X94_AHB_PMA_LN_VREG_O_SHIFT                               6
24175 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95                                                           0x00117cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24176     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_BB_STEP_O                                  (0xf<<0) // CDR bb_step
24177     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_BB_STEP_O_SHIFT                            0
24178     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_INT_STEP_O                                 (0x7<<4) // CDR int step
24179     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_INT_STEP_O_SHIFT                           4
24180     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_RXDWN_O                                    (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
24181     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X95_AHB_PMA_LN_RXDWN_O_SHIFT                              7
24182 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96                                                           0x001180UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24183     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_O                                  (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
24184     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_O_SHIFT                            0
24185     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_SEL_O                              (0x1<<3) // Override enable for RXVCOFR override vakue
24186     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RXVCOFR_SEL_O_SHIFT                        3
24187     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RX_SELR_O                                  (0x7<<4) // CTLE R degeneration select
24188     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_AHB_PMA_LN_RX_SELR_O_SHIFT                            4
24189     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_UNUSED_0                                              (0x1<<7) // reserved
24190     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X96_UNUSED_0_SHIFT                                        7
24191 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X97                                                           0x001184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24192     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X97_AHB_PMA_LN_RX_SELC_O                                  (0x7<<0) // CTLE C degeneration select
24193     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X97_AHB_PMA_LN_RX_SELC_O_SHIFT                            0
24194     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X97_UNUSED_0                                              (0x1f<<3) // reserved
24195     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X97_UNUSED_0_SHIFT                                        3
24196 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99                                                           0x00118cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24197     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_UNUSED_0                                              (0xf<<0) // reserved
24198     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_UNUSED_0_SHIFT                                        0
24199     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_PMA_LN_DFE_BW_SCALE                                   (0x3<<4) // DFE Bandwidth Selection
24200     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_PMA_LN_DFE_BW_SCALE_SHIFT                             4
24201     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_PMA_LN_PHD_ENA_O_1_0                                  (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
24202     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X99_PMA_LN_PHD_ENA_O_1_0_SHIFT                            6
24203 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X100                                                          0x001190UL //Access:RW   DataWidth:0x8   On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal  Chips: K2
24204 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101                                                          0x001194UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24205     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_DLY_O_8_8                                 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
24206     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_DLY_O_8_8_SHIFT                           0
24207     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_UNUSED_0                                             (0x1<<1) // reserved
24208     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_UNUSED_0_SHIFT                                       1
24209     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_SGN_RST_O                                 (0x1<<2) // Reset signal for eye alignment mechanism.
24210     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_SGN_RST_O_SHIFT                           2
24211     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_SD_BWSEL                                      (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
24212     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_SD_BWSEL_SHIFT                                3
24213     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA270_O                                  (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
24214     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA270_O_SHIFT                            4
24215     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA90_O                                   (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
24216     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_PMA_LN_EYE_ENA90_O_SHIFT                             5
24217     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_UNUSED_1                                             (0x3<<6) // reserved
24218     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X101_UNUSED_1_SHIFT                                       6
24219 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X102                                                          0x001198UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24220     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X102_PMA_LN_DFE_BIAS_O_3_0                                (0xf<<0) // DFE bias setting.
24221     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X102_PMA_LN_DFE_BIAS_O_3_0_SHIFT                          0
24222     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X102_UNUSED_0                                             (0xf<<4) // reserved
24223     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X102_UNUSED_0_SHIFT                                       4
24224 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103                                                          0x00119cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24225     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_PMA_LN_TX_SR_FASTCAP_O_3_0                           (0xf<<0) // TX driver capacitive slew rate control.
24226     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_SHIFT                     0
24227     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_PMA_LN_TXEQ_POLARITY_O_3_0                           (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
24228     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X103_PMA_LN_TXEQ_POLARITY_O_3_0_SHIFT                     4
24229 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104                                                          0x0011a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24230     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_TX_SR_DAC_O_3_0                               (0xf<<0) // TX slew rate DAC bias current control
24231     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_TX_SR_DAC_O_3_0_SHIFT                         0
24232     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_HSCLK_SEL_O                                   (0x1<<4) // CDR clock divider bypass enable.
24233     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_PMA_LN_HSCLK_SEL_O_SHIFT                             4
24234     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_UNUSED_0                                             (0x7<<5) // reserved
24235     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X104_UNUSED_0_SHIFT                                       5
24236 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105                                                          0x0011a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24237     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TX_VREG_LEV_O_4_0                             (0x1f<<0) // TX driver regulator voltage setting.
24238     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TX_VREG_LEV_O_4_0_SHIFT                       0
24239     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TXDRV_BLEED_ENA_O                             (0x1<<5) // TX bleed enable
24240     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_PMA_LN_TXDRV_BLEED_ENA_O_SHIFT                       5
24241     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_UNUSED_0                                             (0x3<<6) // reserved
24242     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X105_UNUSED_0_SHIFT                                       6
24243 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106                                                          0x0011a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24244     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O                       (0x1<<0) // RX boost override enable.
24245     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_SHIFT                 0
24246     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O                    (0x7f<<1) // RX boost override setting. Thermometer coded.
24247     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_SHIFT              1
24248 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X107                                                          0x0011acUL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
24249 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108                                                          0x0011b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24250     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_SD_THSEL_GEN3_O                           (0x7<<0) // Signal detect threshold select for Gen3
24251     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_SHIFT                     0
24252     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O                          (0x7<<3) // AGC threshold select for Gen3
24253     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_SHIFT                    3
24254     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXUP_GEN3_O                               (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
24255     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXUP_GEN3_O_SHIFT                         6
24256     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O                      (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
24257     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_SHIFT                7
24258 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X109                                                          0x0011b4UL //Access:RW   DataWidth:0x8   RX FL calibration LDHS for Gen3  Chips: K2
24259 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110                                                          0x0011b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24260     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O                      (0x3<<0) // RX FL calibration LDHS for Gen3
24261     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_SHIFT                0
24262     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O                         (0xf<<2) // CDR VCO bias setting.
24263     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_SHIFT                   2
24264     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O                      (0x1<<6) // DLPF DIV2 enable
24265     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_SHIFT                6
24266     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O                       (0x1<<7) // CDR DivN clock divider enable.
24267     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_SHIFT                 7
24268 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X111                                                          0x0011bcUL //Access:RW   DataWidth:0x8   AFE spare controls for Gen3  Chips: K2
24269 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112                                                          0x0011c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24270     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O                           (0x3f<<0) // CDR DivN clock divider ratio..
24271     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_SHIFT                     0
24272     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_AHB_PMA_LN_VREG_GEN3_O                               (0x3<<6) // Regulator VREG setting for Gen3
24273     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X112_AHB_PMA_LN_VREG_GEN3_O_SHIFT                         6
24274 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113                                                          0x0011c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24275     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_BB_STEP_GEN3_O                            (0xf<<0) // CDR bb_step for Gen3
24276     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_BB_STEP_GEN3_O_SHIFT                      0
24277     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_INT_STEP_GEN3_O                           (0x7<<4) // CDR int step for Gen3
24278     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_INT_STEP_GEN3_O_SHIFT                     4
24279     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_RXDWN_GEN3_O                              (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
24280     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X113_AHB_PMA_LN_RXDWN_GEN3_O_SHIFT                        7
24281 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114                                                          0x0011c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24282     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RXVCOFR_GEN3_O                            (0x7<<0) // RXVCOFR override value for Gen3 Enabled by pma_ln_dr_rxvcofr_sel_o
24283     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_SHIFT                      0
24284     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RX_SELR_GEN3_O                            (0x7<<3) // CTLE R degeneration select for Gen3
24285     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_RX_SELR_GEN3_O_SHIFT                      3
24286     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_VREGH_GEN3_O                              (0x3<<6) // Not currently used
24287     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X114_AHB_PMA_LN_VREGH_GEN3_O_SHIFT                        6
24288 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X115                                                          0x0011ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24289     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X115_AHB_PMA_LN_RX_SELC_GEN3_O                            (0x7<<0) // CTLE R degeneration select for Gen3
24290     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X115_AHB_PMA_LN_RX_SELC_GEN3_O_SHIFT                      0
24291     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X115_UNUSED_0                                             (0x1f<<3) // reserved
24292     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X115_UNUSED_0_SHIFT                                       3
24293 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119                                                          0x0011dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24294     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXP_MARGIN                                    (0xf<<0) // Value to minus/add from the calibrated txterm value
24295     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXP_MARGIN_SHIFT                              0
24296     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXN_MARGIN                                    (0xf<<4) // Value to minus/add from the calibrated txterm value
24297     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X119_AHB_TX_CXN_MARGIN_SHIFT                              4
24298 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120                                                          0x0011e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24299     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_AHB_TX_TC_WAIT_NEXT_CMP                              (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
24300     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_AHB_TX_TC_WAIT_NEXT_CMP_SHIFT                        0
24301     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE                           (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
24302     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_SHIFT                     4
24303     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_UNUSED_0                                             (0x1<<7) // reserved
24304     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X120_UNUSED_0_SHIFT                                       7
24305 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121                                                          0x0011e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24306     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES                        (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
24307     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_SHIFT                  0
24308     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXP_MARGIN_ADD_0                              (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
24309     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXP_MARGIN_ADD_0_SHIFT                        4
24310     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXN_MARGIN_ADD_0                              (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
24311     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CXN_MARGIN_ADD_0_SHIFT                        5
24312     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CX_OVR_ENA                                    (0x1<<6) // enable override calibrated txterm value
24313     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_CX_OVR_ENA_SHIFT                              6
24314     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TERM_EN_CAL_OVR                               (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
24315     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X121_AHB_TX_TERM_EN_CAL_OVR_SHIFT                         7
24316 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122                                                          0x0011e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24317     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_AHB_TX_CXP_OVR                                       (0xf<<0) // override calibrated txterm value
24318     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_AHB_TX_CXP_OVR_SHIFT                                 0
24319     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_AHB_TX_CXN_OVR                                       (0xf<<4) // override calibrated txterm value
24320     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X122_AHB_TX_CXN_OVR_SHIFT                                 4
24321 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123                                                          0x0011ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24322     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_0                                          (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
24323     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_0_SHIFT                                    0
24324     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_UNUSED_0                                             (0x1<<1) // reserved
24325     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_UNUSED_0_SHIFT                                       1
24326     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_7_2                                        (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
24327     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X123_TX_CTRL_O_7_2_SHIFT                                  2
24328 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X124                                                          0x0011f0UL //Access:RW   DataWidth:0x8   Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]  Chips: K2
24329 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X125                                                          0x0011f4UL //Access:RW   DataWidth:0x8   Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode  Chips: K2
24330 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126                                                          0x0011f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24331     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_EN_O                                            (0x1<<0) // DFE block enable signal.
24332     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_EN_O_SHIFT                                      0
24333     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE_OW_O_2_0                                (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
24334     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE_OW_O_2_0_SHIFT                          1
24335     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE1_CAL_EN_O_3                             (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
24336     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE1_CAL_EN_O_3_SHIFT                       4
24337     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE2_CAL_EN_O_4                             (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
24338     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE2_CAL_EN_O_4_SHIFT                       5
24339     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE3_CAL_EN_O_5                             (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
24340     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_RATE3_CAL_EN_O_5_SHIFT                       6
24341     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_FORCE_CAL_O_6                                (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
24342     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X126_RXEQ_LN_FORCE_CAL_O_6_SHIFT                          7
24343 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X127                                                          0x0011fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24344     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X127_RXEQ_CONT_CAL_O_6_0                                  (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
24345     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X127_RXEQ_CONT_CAL_O_6_0_SHIFT                            0
24346     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X127_UNUSED_0                                             (0x1<<7) // reserved
24347     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X127_UNUSED_0_SHIFT                                       7
24348 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X128                                                          0x001200UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24349     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X128_RXEQ_INIT_CAL_O_6_0                                  (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
24350     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X128_RXEQ_INIT_CAL_O_6_0_SHIFT                            0
24351     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X128_UNUSED_0                                             (0x1<<7) // reserved
24352     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X128_UNUSED_0_SHIFT                                       7
24353 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130                                                          0x001208UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24354     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_RXEQ_RATE1_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate1
24355     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_RXEQ_RATE1_ATT_START_O_3_0_SHIFT                     0
24356     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_RXEQ_RATE1_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate1
24357     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X130_RXEQ_RATE1_BOOST_START_O_3_0_SHIFT                   4
24358 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131                                                          0x00120cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24359     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_RXEQ_RATE2_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate2
24360     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_RXEQ_RATE2_ATT_START_O_3_0_SHIFT                     0
24361     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_RXEQ_RATE2_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate2
24362     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X131_RXEQ_RATE2_BOOST_START_O_3_0_SHIFT                   4
24363 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X132                                                          0x001210UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24364     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X132_RXEQ_RATE2_TAP1_START_O_6_0                          (0x7f<<0) // DFE Tap1 start value for rate2
24365     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X132_RXEQ_RATE2_TAP1_START_O_6_0_SHIFT                    0
24366     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X132_UNUSED_0                                             (0x1<<7) // reserved
24367     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X132_UNUSED_0_SHIFT                                       7
24368 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X133                                                          0x001214UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24369     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X133_RXEQ_RATE2_TAP2_START_O_5_0                          (0x3f<<0) // DFE Tap2 start value for rate2
24370     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X133_RXEQ_RATE2_TAP2_START_O_5_0_SHIFT                    0
24371     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X133_UNUSED_0                                             (0x3<<6) // reserved
24372     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X133_UNUSED_0_SHIFT                                       6
24373 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X134                                                          0x001218UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24374     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X134_RXEQ_RATE2_TAP3_START_O_5_0                          (0x3f<<0) // DFE Tap3 start value for rate2
24375     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X134_RXEQ_RATE2_TAP3_START_O_5_0_SHIFT                    0
24376     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X134_UNUSED_0                                             (0x3<<6) // reserved
24377     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X134_UNUSED_0_SHIFT                                       6
24378 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X135                                                          0x00121cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24379     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X135_RXEQ_RATE2_TAP4_START_O_5_0                          (0x3f<<0) // DFE Tap4 start value for rate2
24380     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X135_RXEQ_RATE2_TAP4_START_O_5_0_SHIFT                    0
24381     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X135_UNUSED_0                                             (0x3<<6) // reserved
24382     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X135_UNUSED_0_SHIFT                                       6
24383 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X136                                                          0x001220UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24384     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X136_RXEQ_RATE2_TAP5_START_O_5_0                          (0x3f<<0) // DFE Tap5 start value for rate2
24385     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X136_RXEQ_RATE2_TAP5_START_O_5_0_SHIFT                    0
24386     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X136_UNUSED_0                                             (0x3<<6) // reserved
24387     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X136_UNUSED_0_SHIFT                                       6
24388 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137                                                          0x001224UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24389     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_RXEQ_RATE3_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate3
24390     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_RXEQ_RATE3_ATT_START_O_3_0_SHIFT                     0
24391     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_RXEQ_RATE3_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate3
24392     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X137_RXEQ_RATE3_BOOST_START_O_3_0_SHIFT                   4
24393 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X138                                                          0x001228UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24394     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X138_RXEQ_RATE3_TAP1_START_O_6_0                          (0x7f<<0) // DFE Tap1 start value for rate3
24395     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X138_RXEQ_RATE3_TAP1_START_O_6_0_SHIFT                    0
24396     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X138_UNUSED_0                                             (0x1<<7) // reserved
24397     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X138_UNUSED_0_SHIFT                                       7
24398 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X139                                                          0x00122cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24399     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X139_RXEQ_RATE3_TAP2_START_O_5_0                          (0x3f<<0) // DFE Tap2 start value for rate3
24400     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X139_RXEQ_RATE3_TAP2_START_O_5_0_SHIFT                    0
24401     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X139_UNUSED_0                                             (0x3<<6) // reserved
24402     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X139_UNUSED_0_SHIFT                                       6
24403 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X140                                                          0x001230UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24404     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X140_RXEQ_RATE3_TAP3_START_O_5_0                          (0x3f<<0) // DFE Tap3 start value for rate3
24405     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X140_RXEQ_RATE3_TAP3_START_O_5_0_SHIFT                    0
24406     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X140_UNUSED_0                                             (0x3<<6) // reserved
24407     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X140_UNUSED_0_SHIFT                                       6
24408 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X141                                                          0x001234UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24409     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X141_RXEQ_RATE3_TAP4_START_O_5_0                          (0x3f<<0) // DFE Tap4 start value for rate3
24410     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X141_RXEQ_RATE3_TAP4_START_O_5_0_SHIFT                    0
24411     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X141_UNUSED_0                                             (0x3<<6) // reserved
24412     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X141_UNUSED_0_SHIFT                                       6
24413 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X142                                                          0x001238UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24414     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X142_RXEQ_RATE3_TAP5_START_O_5_0                          (0x3f<<0) // DFE Tap5 start value for rate3
24415     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X142_RXEQ_RATE3_TAP5_START_O_5_0_SHIFT                    0
24416     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X142_UNUSED_0                                             (0x3<<6) // reserved
24417     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X142_UNUSED_0_SHIFT                                       6
24418 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143                                                          0x00123cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24419     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RXEQ_SUPERBST_AUTOCAL_DIS                            (0x1<<0) // Disable auto cal w/ rx_superbst
24420     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RXEQ_SUPERBST_AUTOCAL_DIS_SHIFT                      0
24421     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_O                                    (0xf<<1) // Max limit value for BOOST auto-calibration
24422     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_O_SHIFT                              1
24423     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_EN_O                                 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
24424     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_BOOST_MAX_LIMIT_EN_O_SHIFT                           5
24425     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RX_ATT_BOOST_CAL_O_1_0                               (0x3<<6) // rx_att_boost setting used during ATT calibration
24426     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X143_RX_ATT_BOOST_CAL_O_1_0_SHIFT                         6
24427 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144                                                          0x001240UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24428     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RX_ATT_BOOST_NORM_O_1_0                              (0x3<<0) // rx_att_boost setting used after ATT calibration
24429     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RX_ATT_BOOST_NORM_O_1_0_SHIFT                        0
24430     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_EN_O                                  (0x1<<2) // boost_adj_en
24431     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_EN_O_SHIFT                            2
24432     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_DIR_O                                 (0x1<<3) // boost_adj_dir
24433     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_DIR_O_SHIFT                           3
24434     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_VAL_O                                 (0xf<<4) // boost_adj_val This register Is not bit reversed
24435     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X144_RXEQ_BOOST_ADJ_VAL_O_SHIFT                           4
24436 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145                                                          0x001244UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24437     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0                    (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
24438     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_SHIFT              0
24439     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_EN_O                                  (0x1<<7) // CMP Offset Noise Averaging Enable
24440     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X145_CMP_OFFSET_AVG_EN_O_SHIFT                            7
24441 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X146                                                          0x001248UL //Access:RW   DataWidth:0x8     Chips: K2
24442 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147                                                          0x00124cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24443     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_DFE_TAP_PD_WAIT_11_8                            (0xf<<0) //
24444     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_SHIFT                      0
24445     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_PMA_LN_DFE_OFS_CAL_ENA                               (0x3<<4) // DFE offset calibration enable
24446     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_PMA_LN_DFE_OFS_CAL_ENA_SHIFT                         4
24447     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS                            (0x1<<6) // Disable auto cal w/ rx_att_gain
24448     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_SHIFT                      6
24449     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_SUPERBST_EN_INVERT_O                            (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
24450     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X147_RXEQ_SUPERBST_EN_INVERT_O_SHIFT                      7
24451 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148                                                          0x001250UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24452     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_LOAD_EN_O_6_0                               (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
24453     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_LOAD_EN_O_6_0_SHIFT                         0
24454     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_EN_O                                        (0x1<<7) // Override enable for DFE signals.
24455     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X148_RXEQ_OVR_EN_O_SHIFT                                  7
24456 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149                                                          0x001254UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24457     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LOAD_O_6_0                                  (0x7f<<0) // Override for RXEQ_CTRL output register load value.
24458     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LOAD_O_6_0_SHIFT                            0
24459     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LATCH_O                                     (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
24460     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X149_RXEQ_OVR_LATCH_O_SHIFT                               7
24461 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150                                                          0x001258UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24462     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0                           (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
24463     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_SHIFT                     0
24464     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_ATT_GAIN_OVR                                    (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
24465     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_ATT_GAIN_OVR_SHIFT                              3
24466     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_SUPERBST_ENA_OVR                                (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
24467     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_RXEQ_SUPERBST_ENA_OVR_SHIFT                          5
24468     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6                       (0x1<<6) // DFE TAP CMP no offset override enable
24469     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_SHIFT                 6
24470     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_OVR_EN_O_7                                   (0x1<<7) // DFE TAP override enable
24471     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X150_DFE_TAP_OVR_EN_O_7_SHIFT                             7
24472 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151                                                          0x00125cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24473     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3                      (0x1f<<0) // DFE offset calibration TAP enable override
24474     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_SHIFT                0
24475     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0                        (0x1<<5) // DFE offset calibrated value override enable
24476     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_SHIFT                  5
24477     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_EN_OVR_O_1                            (0x1<<6) // DFE offset cal enable override
24478     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_OFFSET_CAL_EN_OVR_O_1_SHIFT                      6
24479     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_CMP_CAL_EN_OVR_O_2                               (0x1<<7) // DFE comparator cal enable override
24480     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X151_DFE_CMP_CAL_EN_OVR_O_2_SHIFT                         7
24481 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X152                                                          0x001260UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24482     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X152_DFE_TAP1_OVR_VAL_O_6_0                               (0x7f<<0) // DFE Tap 1 Override Value
24483     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X152_DFE_TAP1_OVR_VAL_O_6_0_SHIFT                         0
24484     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X152_UNUSED_0                                             (0x1<<7) // reserved
24485     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X152_UNUSED_0_SHIFT                                       7
24486 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X153                                                          0x001264UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24487     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X153_DFE_TAP2_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 2 Override Value
24488     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X153_DFE_TAP2_OVR_VAL_O_5_0_SHIFT                         0
24489     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X153_UNUSED_0                                             (0x3<<6) // reserved
24490     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X153_UNUSED_0_SHIFT                                       6
24491 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X154                                                          0x001268UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24492     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X154_DFE_TAP3_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 3 Override Value
24493     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X154_DFE_TAP3_OVR_VAL_O_5_0_SHIFT                         0
24494     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X154_UNUSED_0                                             (0x3<<6) // reserved
24495     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X154_UNUSED_0_SHIFT                                       6
24496 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X155                                                          0x00126cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24497     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X155_DFE_TAP4_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 4 Override Value
24498     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X155_DFE_TAP4_OVR_VAL_O_5_0_SHIFT                         0
24499     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X155_UNUSED_0                                             (0x3<<6) // reserved
24500     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X155_UNUSED_0_SHIFT                                       6
24501 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X156                                                          0x001270UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24502     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X156_DFE_TAP5_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 5 Override Value
24503     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X156_DFE_TAP5_OVR_VAL_O_5_0_SHIFT                         0
24504     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X156_UNUSED_0                                             (0x3<<6) // reserved
24505     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X156_UNUSED_0_SHIFT                                       6
24506 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157                                                          0x001274UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24507     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ADAPT_EN_O_0                                    (0x1<<0) // TX Equalizer adaptation function enable
24508     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ADAPT_EN_O_0_SHIFT                              0
24509     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ERR_SIGN_O_1                                    (0x1<<1) // TX Equalizer Error Sign
24510     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_ERR_SIGN_O_1_SHIFT                              1
24511     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_FW_OVRIDE_O_2                                   (0x1<<2) // TX Equalization Firmware over ride  0 -	 Disable firmware based adaptation  1 -	 Enbale firmware based adaptation
24512     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_TXEQ_FW_OVRIDE_O_2_SHIFT                             2
24513     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_UNUSED_0                                             (0x1f<<3) // reserved
24514     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X157_UNUSED_0_SHIFT                                       3
24515 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X158                                                          0x001278UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
24516     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X158_TXEQ_ERR_STAT_I_1_0                                  (0x3<<0) // TX Equalization error state
24517     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X158_TXEQ_ERR_STAT_I_1_0_SHIFT                            0
24518     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X158_UNUSED_0                                             (0x3f<<2) // reserved
24519     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X158_UNUSED_0_SHIFT                                       2
24520 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X159                                                          0x00127cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
24521     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X159_TXEQ_OVER_EQ_CNT_I_9_8                               (0x3<<0) // Over equalization count 9-8
24522     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X159_TXEQ_OVER_EQ_CNT_I_9_8_SHIFT                         0
24523     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X159_UNUSED_0                                             (0x3f<<2) // reserved
24524     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X159_UNUSED_0_SHIFT                                       2
24525 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X160                                                          0x001280UL //Access:R    DataWidth:0x8   Over equalization count 7-0  Chips: K2
24526 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X161                                                          0x001284UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
24527     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X161_TXEQ_UNDER_EQ_CNT_I_9_8                              (0x3<<0) // Under equalization count 9-8
24528     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X161_TXEQ_UNDER_EQ_CNT_I_9_8_SHIFT                        0
24529     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X161_UNUSED_0                                             (0x3f<<2) // reserved
24530     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X161_UNUSED_0_SHIFT                                       2
24531 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X162                                                          0x001288UL //Access:R    DataWidth:0x8   Under equalization count 7-0  Chips: K2
24532 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X163                                                          0x00128cUL //Access:RW   DataWidth:0x8   TX Equalizer Training Pattern  Chips: K2
24533 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164                                                          0x001290UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24534     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164_TXEQ_TRAINING_PATT_O_8                               (0x1<<0) // TX Equalizer Training Pattern
24535     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164_TXEQ_TRAINING_PATT_O_8_SHIFT                         0
24536     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164_UNUSED_0                                             (0x7f<<1) // reserved
24537     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X164_UNUSED_0_SHIFT                                       1
24538 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X165                                                          0x001294UL //Access:RW   DataWidth:0x8   Mask bit for Txeq training pattern  Chips: K2
24539 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166                                                          0x001298UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24540     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166_TXEQ_DONT_CARE_O_8                                   (0x1<<0) // Mask bit for Txeq training pattern
24541     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166_TXEQ_DONT_CARE_O_8_SHIFT                             0
24542     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166_UNUSED_0                                             (0x7f<<1) // reserved
24543     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X166_UNUSED_0_SHIFT                                       1
24544 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167                                                          0x00129cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24545     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167_TXEQ_RXRECAL_INIT_O_7                                (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
24546     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167_TXEQ_RXRECAL_INIT_O_7_SHIFT                          0
24547     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167_UNUSED_0                                             (0x7f<<1) // reserved
24548     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X167_UNUSED_0_SHIFT                                       1
24549 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168                                                          0x0012a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24550     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_INIT_RX_PRESET_HINT_EN_O                             (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
24551     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_INIT_RX_PRESET_HINT_EN_O_SHIFT                       0
24552     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_RECAL_RX_PRESET_HINT_EN_O                            (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
24553     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_RECAL_RX_PRESET_HINT_EN_O_SHIFT                      1
24554     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_UNUSED_0                                             (0x3f<<2) // reserved
24555     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X168_UNUSED_0_SHIFT                                       2
24556 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169                                                          0x0012a4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
24557     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169_TXEQ_RXRECAL_DONE_I_0                                (0x1<<0) // TX - RECAL RX Equalization status
24558     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169_TXEQ_RXRECAL_DONE_I_0_SHIFT                          0
24559     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169_UNUSED_0                                             (0x7f<<1) // reserved
24560     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X169_UNUSED_0_SHIFT                                       1
24561 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170                                                          0x0012a8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
24562     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170_BLOCK_DEC_ERR                                        (0x1<<0) // decoder sync header error
24563     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170_BLOCK_DEC_ERR_SHIFT                                  0
24564     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170_UNUSED_0                                             (0x7f<<1) // reserved
24565     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X170_UNUSED_0_SHIFT                                       1
24566 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201                                                          0x001324UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24567     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_EN_O_0                                          (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
24568     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_EN_O_0_SHIFT                                    0
24569     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_WORD_OV_O_1_0                                   (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
24570     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_WORD_OV_O_1_0_SHIFT                             1
24571     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_MODE_8B_OV_O_1_0                                (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
24572     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_MODE_8B_OV_O_1_0_SHIFT                          3
24573     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_RATE_OV_O_2_0                                   (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
24574     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X201_CDFE_RATE_OV_O_2_0_SHIFT                             5
24575 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X202                                                          0x001328UL //Access:RW   DataWidth:0x8     Chips: K2
24576 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203                                                          0x00132cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24577     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_UNUSED_0                                             (0xf<<0) // reserved
24578     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_UNUSED_0_SHIFT                                       0
24579     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_GO                                              (0x1<<4) //
24580     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_GO_SHIFT                                        4
24581     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_FORCE_CAL                                    (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
24582     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_FORCE_CAL_SHIFT                              5
24583     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_RATE_CHANGE_CAL                              (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
24584     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_RATE_CHANGE_CAL_SHIFT                        6
24585     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_EI_EXIT_CAL                                  (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
24586     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X203_CDFE_LN_EI_EXIT_CAL_SHIFT                            7
24587 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204                                                          0x001330UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24588     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_CONT_CAL                                     (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
24589     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_CONT_CAL_SHIFT                               0
24590     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL                         (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
24591     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_SHIFT                   1
24592     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL                          (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
24593     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_SHIFT                    2
24594     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_CAL_EN                                 (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
24595     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE3_CAL_EN_SHIFT                           3
24596     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE2_CAL_EN                                 (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
24597     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_CDFE_LN_RATE2_CAL_EN_SHIFT                           4
24598     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_UNUSED_0                                             (0x7<<5) // reserved
24599     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X204_UNUSED_0_SHIFT                                       5
24600 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X205                                                          0x001334UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
24601 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X206                                                          0x001338UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
24602 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X207                                                          0x00133cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
24603 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208                                                          0x001340UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24604     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_UNUSED_0                                             (0x7f<<0) // reserved
24605     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_UNUSED_0_SHIFT                                       0
24606     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_AHB_CDFE_COARSE_DLL_OV_EN                            (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
24607     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X208_AHB_CDFE_COARSE_DLL_OV_EN_SHIFT                      7
24608 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X213                                                          0x001354UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
24609 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X214                                                          0x001358UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
24610 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X215                                                          0x00135cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
24611 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X216                                                          0x001360UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
24612 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X217                                                          0x001364UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
24613 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X220                                                          0x001370UL //Access:RW   DataWidth:0x8   Start value for dlev_ref.  Chips: K2
24614 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X221                                                          0x001374UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24615     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0               (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
24616     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT         0
24617     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X221_UNUSED_0                                             (0x7<<5) // reserved
24618     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X221_UNUSED_0_SHIFT                                       5
24619 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X222                                                          0x001378UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24620     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0           (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
24621     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT     0
24622     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X222_UNUSED_0                                             (0x7<<5) // reserved
24623     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X222_UNUSED_0_SHIFT                                       5
24624 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X223                                                          0x00137cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24625     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X223_AHB_CDFE_CMP1_TAP1_OFFSET                            (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
24626     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X223_AHB_CDFE_CMP1_TAP1_OFFSET_SHIFT                      0
24627     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X223_UNUSED_0                                             (0x1<<7) // reserved
24628     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X223_UNUSED_0_SHIFT                                       7
24629 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X224                                                          0x001380UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24630     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
24631     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_SHIFT                  0
24632     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X224_UNUSED_0                                             (0x3<<6) // reserved
24633     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X224_UNUSED_0_SHIFT                                       6
24634 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X225                                                          0x001384UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24635     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
24636     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_SHIFT                  0
24637     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X225_UNUSED_0                                             (0x3<<6) // reserved
24638     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X225_UNUSED_0_SHIFT                                       6
24639 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X226                                                          0x001388UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24640     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
24641     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_SHIFT                  0
24642     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X226_UNUSED_0                                             (0x3<<6) // reserved
24643     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X226_UNUSED_0_SHIFT                                       6
24644 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X227                                                          0x00138cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24645     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X227_AHB_CDFE_CMP1_TAP5_OFFSET                            (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
24646     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X227_AHB_CDFE_CMP1_TAP5_OFFSET_SHIFT                      0
24647     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X227_UNUSED_0                                             (0x3<<6) // reserved
24648     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X227_UNUSED_0_SHIFT                                       6
24649 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X228                                                          0x001390UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24650     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X228_AHB_CDFE_CMP2_TAP1_OFFSET                            (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
24651     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X228_AHB_CDFE_CMP2_TAP1_OFFSET_SHIFT                      0
24652     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X228_UNUSED_0                                             (0x1<<7) // reserved
24653     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X228_UNUSED_0_SHIFT                                       7
24654 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X229                                                          0x001394UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24655     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
24656     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_SHIFT                  0
24657     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X229_UNUSED_0                                             (0x3<<6) // reserved
24658     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X229_UNUSED_0_SHIFT                                       6
24659 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X230                                                          0x001398UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24660     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
24661     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_SHIFT                  0
24662     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X230_UNUSED_0                                             (0x3<<6) // reserved
24663     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X230_UNUSED_0_SHIFT                                       6
24664 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X231                                                          0x00139cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24665     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
24666     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_SHIFT                  0
24667     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X231_UNUSED_0                                             (0x3<<6) // reserved
24668     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X231_UNUSED_0_SHIFT                                       6
24669 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X232                                                          0x0013a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24670     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X232_AHB_CDFE_CMP2_TAP5_OFFSET                            (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
24671     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X232_AHB_CDFE_CMP2_TAP5_OFFSET_SHIFT                      0
24672     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X232_UNUSED_0                                             (0x3<<6) // reserved
24673     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X232_UNUSED_0_SHIFT                                       6
24674 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X233                                                          0x0013a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24675     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X233_AHB_CDFE_CMP3_TAP1_OFFSET                            (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
24676     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X233_AHB_CDFE_CMP3_TAP1_OFFSET_SHIFT                      0
24677     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X233_UNUSED_0                                             (0x1<<7) // reserved
24678     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X233_UNUSED_0_SHIFT                                       7
24679 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X234                                                          0x0013a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24680     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
24681     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_SHIFT                  0
24682     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X234_UNUSED_0                                             (0x3<<6) // reserved
24683     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X234_UNUSED_0_SHIFT                                       6
24684 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X235                                                          0x0013acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24685     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
24686     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_SHIFT                  0
24687     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X235_UNUSED_0                                             (0x3<<6) // reserved
24688     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X235_UNUSED_0_SHIFT                                       6
24689 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X236                                                          0x0013b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24690     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
24691     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_SHIFT                  0
24692     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X236_UNUSED_0                                             (0x3<<6) // reserved
24693     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X236_UNUSED_0_SHIFT                                       6
24694 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X237                                                          0x0013b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24695     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X237_AHB_CDFE_CMP3_TAP5_OFFSET                            (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
24696     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X237_AHB_CDFE_CMP3_TAP5_OFFSET_SHIFT                      0
24697     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X237_UNUSED_0                                             (0x3<<6) // reserved
24698     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X237_UNUSED_0_SHIFT                                       6
24699 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X238                                                          0x0013b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24700     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X238_AHB_CDFE_CMP4_TAP1_OFFSET                            (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
24701     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X238_AHB_CDFE_CMP4_TAP1_OFFSET_SHIFT                      0
24702     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X238_UNUSED_0                                             (0x1<<7) // reserved
24703     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X238_UNUSED_0_SHIFT                                       7
24704 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X239                                                          0x0013bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24705     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
24706     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_SHIFT                  0
24707     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X239_UNUSED_0                                             (0x3<<6) // reserved
24708     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X239_UNUSED_0_SHIFT                                       6
24709 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X240                                                          0x0013c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24710     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
24711     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_SHIFT                  0
24712     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X240_UNUSED_0                                             (0x3<<6) // reserved
24713     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X240_UNUSED_0_SHIFT                                       6
24714 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X241                                                          0x0013c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24715     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
24716     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_SHIFT                  0
24717     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X241_UNUSED_0                                             (0x3<<6) // reserved
24718     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X241_UNUSED_0_SHIFT                                       6
24719 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X242                                                          0x0013c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24720     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X242_AHB_CDFE_CMP4_TAP5_OFFSET                            (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
24721     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X242_AHB_CDFE_CMP4_TAP5_OFFSET_SHIFT                      0
24722     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X242_UNUSED_0                                             (0x3<<6) // reserved
24723     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X242_UNUSED_0_SHIFT                                       6
24724 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X243                                                          0x0013ccUL //Access:RW   DataWidth:0x8   Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]  Chips: K2
24725 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X244                                                          0x0013d0UL //Access:RW   DataWidth:0x8   Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]  Chips: K2
24726 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X245                                                          0x0013d4UL //Access:RW   DataWidth:0x8   Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]  Chips: K2
24727 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X246                                                          0x0013d8UL //Access:RW   DataWidth:0x8   Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]  Chips: K2
24728 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X247                                                          0x0013dcUL //Access:RW   DataWidth:0x8     Chips: K2
24729 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248                                                          0x0013e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24730     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_AHB_CDFE_DLL_FINE_MASK_9_8                           (0x3<<0) //
24731     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_AHB_CDFE_DLL_FINE_MASK_9_8_SHIFT                     0
24732     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT                         (0xf<<2) //
24733     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_SHIFT                   2
24734     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_UNUSED_0                                             (0x3<<6) // reserved
24735     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X248_UNUSED_0_SHIFT                                       6
24736 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249                                                          0x0013e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24737     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_ERR_SMPL_SHIFT                              (0xf<<0) //
24738     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_ERR_SMPL_SHIFT_SHIFT                        0
24739     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_FINE_DLL_OV_EN                              (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
24740     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_AHB_CDFE_FINE_DLL_OV_EN_SHIFT                        4
24741     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_UNUSED_0                                             (0x7<<5) // reserved
24742     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X249_UNUSED_0_SHIFT                                       5
24743 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250                                                          0x0013e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24744     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8                    (0x1<<0) //
24745     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_SHIFT              0
24746     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8                   (0x1<<1) //
24747     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_SHIFT             1
24748     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8                    (0x1<<2) //
24749     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_SHIFT              2
24750     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8                   (0x1<<3) //
24751     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_SHIFT             3
24752     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_UNUSED_0                                             (0xf<<4) // reserved
24753     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X250_UNUSED_0_SHIFT                                       4
24754 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X251                                                          0x0013ecUL //Access:RW   DataWidth:0x8     Chips: K2
24755 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X252                                                          0x0013f0UL //Access:RW   DataWidth:0x8     Chips: K2
24756 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X253                                                          0x0013f4UL //Access:RW   DataWidth:0x8     Chips: K2
24757 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X254                                                          0x0013f8UL //Access:RW   DataWidth:0x8     Chips: K2
24758 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255                                                          0x0013fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24759     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_EN                                       (0x1<<0) // Override enable for CDFE calibration direction
24760     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_EN_SHIFT                                 0
24761     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_VAL                                      (0x1<<1) // Override value for CDFE calibration direction
24762     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_CDFE_DIR_OV_VAL_SHIFT                                1
24763     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA270_OVR_EN_O                           (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
24764     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA270_OVR_EN_O_SHIFT                     2
24765     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA90_OVR_EN_O                            (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
24766     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_ENA90_OVR_EN_O_SHIFT                      3
24767     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_PHD_ENA_OVR_EN_O                              (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
24768     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_PHD_ENA_OVR_EN_O_SHIFT                        4
24769     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_DLY_OVR_EN_O                              (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
24770     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_DLY_OVR_EN_O_SHIFT                        5
24771     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O                          (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
24772     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_SHIFT                    6
24773     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_UNUSED_0                                             (0x1<<7) // reserved
24774     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X255_UNUSED_0_SHIFT                                       7
24775 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X256                                                          0x001400UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK90.  Chips: K2
24776 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257                                                          0x001404UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24777     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8                       (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
24778     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_SHIFT                 0
24779     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0               (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
24780     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_SHIFT         1
24781 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X258                                                          0x001408UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK270.  Chips: K2
24782 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259                                                          0x00140cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24783     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8                      (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
24784     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_SHIFT                0
24785     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_DLEV_OV_EN                                  (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
24786     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_AHB_CDFE_DLEV_OV_EN_SHIFT                            1
24787     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0                    (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
24788     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_SHIFT              2
24789     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8               (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
24790     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_SHIFT         7
24791 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X260                                                          0x001410UL //Access:RW   DataWidth:0x8   Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value  Chips: K2
24792 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X261                                                          0x001414UL //Access:RW   DataWidth:0x8   cdfe dlevn overwrite value.  Chips: K2
24793 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X262                                                          0x001418UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24794     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X262_AHB_CDFE_TAP_OV_EN                                   (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
24795     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X262_AHB_CDFE_TAP_OV_EN_SHIFT                             0
24796     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X262_UNUSED_0                                             (0x7<<5) // reserved
24797     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X262_UNUSED_0_SHIFT                                       5
24798 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X263                                                          0x00141cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24799     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X263_AHB_CDFE_TAP1_OV                                     (0x7f<<0) // cdfe tap1 overwrite value
24800     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X263_AHB_CDFE_TAP1_OV_SHIFT                               0
24801     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X263_UNUSED_0                                             (0x1<<7) // reserved
24802     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X263_UNUSED_0_SHIFT                                       7
24803 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X264                                                          0x001420UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24804     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X264_AHB_CDFE_TAP2_OV                                     (0x3f<<0) // cdfe tap2 overwrite value
24805     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X264_AHB_CDFE_TAP2_OV_SHIFT                               0
24806     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X264_UNUSED_0                                             (0x3<<6) // reserved
24807     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X264_UNUSED_0_SHIFT                                       6
24808 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X265                                                          0x001424UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24809     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X265_AHB_CDFE_TAP3_OV                                     (0x3f<<0) // cdfe tap3 overwrite value
24810     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X265_AHB_CDFE_TAP3_OV_SHIFT                               0
24811     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X265_UNUSED_0                                             (0x3<<6) // reserved
24812     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X265_UNUSED_0_SHIFT                                       6
24813 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X266                                                          0x001428UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24814     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X266_AHB_CDFE_TAP4_OV                                     (0x3f<<0) // cdfe tap4 overwrite value
24815     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X266_AHB_CDFE_TAP4_OV_SHIFT                               0
24816     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X266_UNUSED_0                                             (0x3<<6) // reserved
24817     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X266_UNUSED_0_SHIFT                                       6
24818 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267                                                          0x00142cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24819     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_AHB_CDFE_TAP5_OV                                     (0x3f<<0) // cdfe tap5 overwrite value
24820     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_AHB_CDFE_TAP5_OV_SHIFT                               0
24821     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_UNUSED_0                                             (0x1<<6) // reserved
24822     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_UNUSED_0_SHIFT                                       6
24823     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O               (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
24824     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_SHIFT         7
24825 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268                                                          0x001430UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24826     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O                       (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
24827     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_SHIFT                 0
24828     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O             (0x1<<1) //
24829     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_SHIFT       1
24830     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O         (0x1<<2) //
24831     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_SHIFT   2
24832     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_UNUSED_0                                             (0xf<<3) // reserved
24833     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_UNUSED_0_SHIFT                                       3
24834     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_AHB_CDFE_DFE_VAL_OVR_EN_O                            (0x1<<7) //
24835     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_SHIFT                      7
24836 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269                                                          0x001434UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24837     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O                     (0x1<<0) //
24838     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_SHIFT               0
24839     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_STROBE_EN_O                                 (0x1<<1) //
24840     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_STROBE_EN_O_SHIFT                           1
24841     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_CMP_ENA_O                                   (0xf<<2) //
24842     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_AHB_CDFE_CMP_ENA_O_SHIFT                             2
24843     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_UNUSED_0                                             (0x3<<6) // reserved
24844     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X269_UNUSED_0_SHIFT                                       6
24845 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X270                                                          0x001438UL //Access:RW   DataWidth:0x8     Chips: K2
24846 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271                                                          0x00143cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24847     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0                          (0x1f<<0) //
24848     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_SHIFT                    0
24849     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O                  (0x1<<5) // Forces the positive dlev training pattern to be used
24850     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_SHIFT            5
24851     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O                  (0x1<<6) // Forces the negative dlev training pattern to be used
24852     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_SHIFT            6
24853     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_UNUSED_0                                             (0x1<<7) // reserved
24854     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X271_UNUSED_0_SHIFT                                       7
24855 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272                                                          0x001440UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24856     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP1 adapted value
24857     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SCALE_O_2_0_SHIFT                          0
24858     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP1 adapted value
24859     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X272_CDFE_TAP1_SHIFT_O_4_0_SHIFT                          3
24860 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273                                                          0x001444UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24861     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP2 adapted value
24862     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SCALE_O_2_0_SHIFT                          0
24863     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP2 adapted value
24864     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X273_CDFE_TAP2_SHIFT_O_4_0_SHIFT                          3
24865 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274                                                          0x001448UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24866     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP3 adapted value
24867     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SCALE_O_2_0_SHIFT                          0
24868     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP3 adapted value
24869     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X274_CDFE_TAP3_SHIFT_O_4_0_SHIFT                          3
24870 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275                                                          0x00144cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24871     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP4 adapted value
24872     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SCALE_O_2_0_SHIFT                          0
24873     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP4 adapted value
24874     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X275_CDFE_TAP4_SHIFT_O_4_0_SHIFT                          3
24875 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276                                                          0x001450UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24876     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP5 adapted value
24877     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SCALE_O_2_0_SHIFT                          0
24878     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP5 adapted value
24879     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X276_CDFE_TAP5_SHIFT_O_4_0_SHIFT                          3
24880 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277                                                          0x001454UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24881     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_RA_OVR_O                                (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
24882     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_RA_OVR_O_SHIFT                          0
24883     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_P2S_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
24884     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_P2S_OVR_O_SHIFT                         2
24885     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_LNREGH_OVR_O                            (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
24886     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_LNREGH_OVR_O_SHIFT                      4
24887     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_LNREG_OVR_O                             (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
24888     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X277_LN_MSM_RESET_LNREG_OVR_O_SHIFT                       6
24889 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278                                                          0x001458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24890     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_RESET_CDR_OVR_O                               (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
24891     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_RESET_CDR_OVR_O_SHIFT                         0
24892     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_RESET_DFE_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
24893     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_RESET_DFE_OVR_O_SHIFT                         2
24894     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_PD_LNREGH_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
24895     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_PD_LNREGH_OVR_O_SHIFT                         4
24896     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_PD_VCO_BUF_OVR_O                              (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
24897     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X278_LN_MSM_PD_VCO_BUF_OVR_O_SHIFT                        6
24898 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279                                                          0x00145cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24899     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RESET_CDR_GCRX_OVR_O                          (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
24900     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_SHIFT                    0
24901     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RXGATE_EN_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
24902     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RXGATE_EN_OVR_O_SHIFT                         2
24903     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RESET_VCO_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
24904     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_RESET_VCO_OVR_O_SHIFT                         4
24905     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_IDDQ_SD_OVR_O                                 (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
24906     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X279_LN_MSM_IDDQ_SD_OVR_O_SHIFT                           6
24907 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280                                                          0x001460UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24908     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_PD_DFE_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
24909     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_PD_DFE_OVR_O_SHIFT                            0
24910     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_PD_DFE_BIAS_OVR_O                             (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
24911     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_PD_DFE_BIAS_OVR_O_SHIFT                       2
24912     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O                           (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
24913     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_SHIFT                     4
24914     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O                         (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
24915     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_SHIFT                   6
24916 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281                                                          0x001464UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24917     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_TXREG_OVR_O                                (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
24918     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_TXREG_OVR_O_SHIFT                          0
24919     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_LNREG_OVR_O                                (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
24920     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_LNREG_OVR_O_SHIFT                          2
24921     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_P2S_OVR_O                                  (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
24922     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_P2S_OVR_O_SHIFT                            4
24923     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_RA_OVR_O                                   (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
24924     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X281_LN_MSM_PD_RA_OVR_O_SHIFT                             6
24925 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282                                                          0x001468UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24926     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_UNUSED_0                                             (0x3<<0) // reserved
24927     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_UNUSED_0_SHIFT                                       0
24928     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_SLV_BIAS_OVR_O                             (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
24929     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_SLV_BIAS_OVR_O_SHIFT                       2
24930     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_TXDRV_OVR_O                                (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
24931     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_TXDRV_OVR_O_SHIFT                          4
24932     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_VCO_OVR_O                                  (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
24933     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X282_LN_MSM_PD_VCO_OVR_O_SHIFT                            6
24934 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283                                                          0x00146cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24935     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_CDR_EN_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
24936     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_CDR_EN_OVR_O_SHIFT                            0
24937     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_RESET_S2P_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
24938     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_RESET_S2P_OVR_O_SHIFT                         2
24939     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_RXCLK_EN_OVR_O                                (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
24940     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_RXCLK_EN_OVR_O_SHIFT                          4
24941     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_WORD_OVR_O                                    (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
24942     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X283_LN_MSM_WORD_OVR_O_SHIFT                              6
24943 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284                                                          0x001470UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24944     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RATE_OVR_O                                    (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
24945     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RATE_OVR_O_SHIFT                              0
24946     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RXVCODIV_OVR_O                                (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
24947     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RXVCODIV_OVR_O_SHIFT                          3
24948     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O                         (0x3<<6) // Not currently used
24949     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_SHIFT                   6
24950 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X285                                                          0x001474UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24951     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X285_LN_MSM_TXVCODIV_OVR_O                                (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
24952     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X285_LN_MSM_TXVCODIV_OVR_O_SHIFT                          0
24953     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X285_UNUSED_0                                             (0x1f<<3) // reserved
24954     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X285_UNUSED_0_SHIFT                                       3
24955 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301                                                          0x0014b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24956     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_RX_SRC_O                                             (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
24957     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_RX_SRC_O_SHIFT                                       0
24958     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_POL_O                                          (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
24959     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_POL_O_SHIFT                                    1
24960     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_BIT_O                                          (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
24961     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_BIT_O_SHIFT                                    2
24962     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_WORD_O                                         (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
24963     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_TREG0_WORD_O_SHIFT                                   3
24964     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_DMUX_TXA_SEL_O_1_0                                   (0x3<<4) // Transmit mux A data input select.
24965     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_DMUX_TXA_SEL_O_1_0_SHIFT                             4
24966     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_P2S_RBUF_AUTOFIX_O                                   (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
24967     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_P2S_RBUF_AUTOFIX_O_SHIFT                             6
24968     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_UNUSED_0                                             (0x1<<7) // reserved
24969     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X301_UNUSED_0_SHIFT                                       7
24970 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302                                                          0x0014b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24971     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_POL_O                                          (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
24972     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_POL_O_SHIFT                                    0
24973     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_BIT_O                                          (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
24974     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_BIT_O_SHIFT                                    1
24975     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_WORD_O                                         (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
24976     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_TREG1_WORD_O_SHIFT                                   2
24977     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_POL_O                                           (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
24978     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_POL_O_SHIFT                                     3
24979     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_BIT_O                                           (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
24980     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_BIT_O_SHIFT                                     4
24981     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_WORD_O                                          (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
24982     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG1_WORD_O_SHIFT                                    5
24983     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG0_POL_O                                           (0x1<<6) // Used as Reg0 polarity select
24984     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_REG0_POL_O_SHIFT                                     6
24985     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_UNUSED_0                                             (0x1<<7) // reserved
24986     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X302_UNUSED_0_SHIFT                                       7
24987 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303                                                          0x0014bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
24988     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_BIT_O                                           (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
24989     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_BIT_O_SHIFT                                     0
24990     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_WORD_O                                          (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
24991     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_REG0_WORD_O_SHIFT                                    1
24992     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_DMUX_TXB_SEL_O_2_0                                   (0x7<<2) // Transmit mux B data input select enable.
24993     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_DMUX_TXB_SEL_O_2_0_SHIFT                             2
24994     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TX_CTRL_O_24                                         (0x1<<5) // Bit 24: txdrv_c2_in[3]
24995     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TX_CTRL_O_24_SHIFT                                   5
24996     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_WIDTH_CHNG_EN_O                                      (0x1<<6) // Enable bit for width_chng module
24997     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_WIDTH_CHNG_EN_O_SHIFT                                6
24998     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TXTERM_CAL_SEQ_EN_O                                  (0x1<<7) // Txterm calibration enable
24999     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X303_TXTERM_CAL_SEQ_EN_O_SHIFT                            7
25000 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304                                                          0x0014c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25001     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_TXTERM_CAL_RSEL                                      (0x7<<0) // tx termination calibration comparator threshold select
25002     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_TXTERM_CAL_RSEL_SHIFT                                0
25003     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_LN_RXBIT_STRIP_O                                 (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2?b00: no bit stripping 2?b01: 2x bit stripping 2?b10: reserved 2?b11: 4x bit stripping
25004     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_LN_RXBIT_STRIP_O_SHIFT                           3
25005     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_MAC_WIDTH_O                                      (0x3<<5) // Data width selector for PCS/MAC interface. 2?b00: GigE or XAUI 2?b01: GigE or XAUI 2?b10: RXAUI 2?b11: XFI
25006     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_AHB_MAC_WIDTH_O_SHIFT                                5
25007     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_UNUSED_0                                             (0x1<<7) // reserved
25008     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X304_UNUSED_0_SHIFT                                       7
25009 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305                                                          0x0014c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25010     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_AHB_TXMAC_THRESHOLD_O                                (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
25011     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_AHB_TXMAC_THRESHOLD_O_SHIFT                          0
25012     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_AHB_LN_TXBIT_REPEAT_O                                (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2?b00: no bit stuffing nor stripping 2?b01: 2x bit stuffing and stripping 2?b10: reserved 2?b11: 4x bit stuffing and stripping
25013     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_AHB_LN_TXBIT_REPEAT_O_SHIFT                          2
25014     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_MODE_8B_O_1_0                                        (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
25015     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_MODE_8B_O_1_0_SHIFT                                  4
25016     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_ENC_EN_O                                             (0x1<<6) // 8b/10b encoder enable.
25017     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_ENC_EN_O_SHIFT                                       6
25018     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_DEC_EN_O                                             (0x1<<7) // 8b/10b decoder enable.
25019     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X305_DEC_EN_O_SHIFT                                       7
25020 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306                                                          0x0014c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25021     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_AHB_TX_CDAC_OVR                                      (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
25022     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_AHB_TX_CDAC_OVR_SHIFT                                0
25023     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_LN_COMMON_SYNC_TXCLK_EN_O                            (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
25024     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_LN_COMMON_SYNC_TXCLK_EN_O_SHIFT                      4
25025     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_UNUSED_0                                             (0x7<<5) // reserved
25026     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X306_UNUSED_0_SHIFT                                       5
25027 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307                                                          0x0014ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25028     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_LN_TO_CLK_TXB_WAIT_O                                 (0x1f<<0) // In per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA. The lnX_ok_o will get asserted after lnX_to_clk_txb_wait_o lnX_ck_txb_o cycles.
25029     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_LN_TO_CLK_TXB_WAIT_O_SHIFT                           0
25030     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_PIPE_EN_O                                            (0x1<<5) // PIPE interface block enable.
25031     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_PIPE_EN_O_SHIFT                                      5
25032     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_SAPIS_EN_O                                           (0x1<<6) // SAPIS interface block enable.
25033     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_SAPIS_EN_O_SHIFT                                     6
25034     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_USB_MODE                                             (0x1<<7) // Signal Detect USB mode enable
25035     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X307_USB_MODE_SHIFT                                       7
25036 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308                                                          0x0014d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25037     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_UNUSED_0                                             (0x1<<0) // reserved
25038     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_UNUSED_0_SHIFT                                       0
25039     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_ENC_CLR_ERR_O                                  (0x1<<1) // 128b/130b encoder clear error
25040     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_ENC_CLR_ERR_O_SHIFT                            1
25041     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_UNUSED_1                                             (0x1<<2) // reserved
25042     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_UNUSED_1_SHIFT                                       2
25043     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_EN_ERR_CHK_O                               (0x1<<3) // 130b/128b error check enable
25044     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_EN_ERR_CHK_O_SHIFT                         3
25045     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0                          (0x7<<4) // 130b/128b: number of OS indicating end of data
25046     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_SHIFT                    4
25047     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CLR_ERR_O                                  (0x1<<7) // 130b/128b: clear error flag
25048     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X308_BLOCK_DEC_CLR_ERR_O_SHIFT                            7
25049 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309                                                          0x0014d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25050     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0                        (0xf<<0) // 130b/128b: number of sync hdr errors before asserting sync error flag
25051     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_SHIFT                  0
25052     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0                         (0xf<<4) // 130b/128b: number of continuous blocks checked
25053     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_SHIFT                   4
25054 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310                                                          0x0014d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25055     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_RSTN_O                                          (0x1<<0) // Synchronous clear for elastic buffer
25056     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_RSTN_O_SHIFT                                    0
25057     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_ALIGN_RSTN_O                                         (0x1<<1) // Synchronous clear for block/symbol aligner
25058     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_ALIGN_RSTN_O_SHIFT                                   1
25059     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_SKP_ADD_EN_O                                    (0x1<<2) // Elastic buffer SKP add enable
25060     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EBUF_SKP_ADD_EN_O_SHIFT                              2
25061     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_RBUF_RSTN_O                                          (0x1<<3) // TX FIFO synchronous reset
25062     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_RBUF_RSTN_O_SHIFT                                    3
25063     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_UNUSED_0                                             (0x1<<4) // reserved
25064     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_UNUSED_0_SHIFT                                       4
25065     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EN_SKPOS_ERR_O                                       (0x1<<5) // Enables skpos error status propagation in Gen3
25066     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_EN_SKPOS_ERR_O_SHIFT                                 5
25067     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_UNUSED_1                                             (0x3<<6) // reserved
25068     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X310_UNUSED_1_SHIFT                                       6
25069 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311                                                          0x0014dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25070     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_PIPE_LFREQ                                           (0x3f<<0) // LF value for full swing
25071     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_PIPE_LFREQ_SHIFT                                     0
25072     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_BLOCK_ALIGN_CTRL_O                               (0x1<<6) // Disables the primary input lnX_block_align_control
25073     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_BLOCK_ALIGN_CTRL_O_SHIFT                         6
25074     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_EIEOS_CHK_IN_LB_O                                (0x1<<7) // Disables the EIEOS check in loopback
25075     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X311_DIS_EIEOS_CHK_IN_LB_O_SHIFT                          7
25076 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312                                                          0x0014e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25077     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_COEF_FE_LIMIT_EN_O                                   (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
25078     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_COEF_FE_LIMIT_EN_O_SHIFT                             0
25079     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_RXVALID_DIS_AT_RATE_CHG_O_0                          (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
25080     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_RXVALID_DIS_AT_RATE_CHG_O_0_SHIFT                    1
25081     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_P2S_RBUF_BUF_THRESH_O_3_0                            (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted
25082     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_P2S_RBUF_BUF_THRESH_O_3_0_SHIFT                      2
25083     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_UNUSED_0                                             (0x3<<6) // reserved
25084     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X312_UNUSED_0_SHIFT                                       6
25085 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313                                                          0x0014e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25086     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_RX_GEARBOX_DISABLE_O                             (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
25087     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_RX_GEARBOX_DISABLE_O_SHIFT                       0
25088     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_TX_GEARBOX_DISABLE_O                             (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
25089     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_AHB_TX_GEARBOX_DISABLE_O_SHIFT                       1
25090     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_UNUSED_0                                             (0x3f<<2) // reserved
25091     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X313_UNUSED_0_SHIFT                                       2
25092 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314                                                          0x0014e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25093     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_GEN1_OLD_RXDATA_SRC                                  (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
25094     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_GEN1_OLD_RXDATA_SRC_SHIFT                            0
25095     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN3_O                                      (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
25096     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN3_O_SHIFT                                1
25097     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN12_O                                     (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
25098     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_SKIP_CDR_GEN12_O_SHIFT                               2
25099     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_AHB_LN_PD_RA_CISEL_OVR_O_0                           (0x1<<3) // Receive amplifier powerdown override, when cisel is high
25100     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_SHIFT                     3
25101     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_LN_P2S_RBUF_REALIGN_DIFF_O                           (0xf<<4) // In per lane common synchronous clock mode, ln_p2x_rbuf_realign_diff_o defines the starting difference between write pointer and read pointer when re aligning the pointer of TxFIFO.
25102     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X314_LN_P2S_RBUF_REALIGN_DIFF_O_SHIFT                     4
25103 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X315                                                          0x0014ecUL //Access:RW   DataWidth:0x8   Delays the beacon_ena propagation to PMA  Chips: K2
25104 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X316                                                          0x0014f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25105     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O               (0xf<<0) // Delays the beacon_ena propagation to PMA
25106     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_SHIFT         0
25107     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X316_UNUSED_0                                             (0xf<<4) // reserved
25108     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X316_UNUSED_0_SHIFT                                       4
25109 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317                                                          0x0014f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25110     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_ENA_O                             (0x1<<0) // Beacon Override Enable
25111     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_ENA_O_SHIFT                       0
25112     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_O                                 (0x1<<1) // Beacon Override
25113     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_AHB_BEACON_ENA_OVR_O_SHIFT                           1
25114     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_DEC_EN_OVR_O                                         (0x1<<2) // Enables 16b/20b decoder
25115     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_DEC_EN_OVR_O_SHIFT                                   2
25116     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_ENC_EN_OVR_O                                         (0x1<<3) // Enables 16b/20b encoder
25117     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_ENC_EN_OVR_O_SHIFT                                   3
25118     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_REGP_OVR_3_0                                         (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
25119     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X317_REGP_OVR_3_0_SHIFT                                   4
25120 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318                                                          0x0014f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25121     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_SIGDET_OVR_O_1_0                                     (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
25122     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_SIGDET_OVR_O_1_0_SHIFT                               0
25123     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_LN_OUT_OVR_1_0                                       (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
25124     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_LN_OUT_OVR_1_0_SHIFT                                 2
25125     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_RXEQ_SIGDET_1_0                                      (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
25126     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_RXEQ_SIGDET_1_0_SHIFT                                4
25127     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_UNUSED_0                                             (0x3<<6) // reserved
25128     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X318_UNUSED_0_SHIFT                                       6
25129 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319                                                          0x0014fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25130     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_TXDETECTRX_OVR_O_1_0                                 (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
25131     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_TXDETECTRX_OVR_O_1_0_SHIFT                           0
25132     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_RXDET_STATUS_OVR_O_1_0                               (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
25133     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_RXDET_STATUS_OVR_O_1_0_SHIFT                         2
25134     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_LOCKED_OVR_O_1_0                                     (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
25135     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_LOCKED_OVR_O_1_0_SHIFT                               4
25136     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O                     (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
25137     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_SHIFT               6
25138     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O                         (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
25139     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_SHIFT                   7
25140 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X320                                                          0x001500UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
25141 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X321                                                          0x001504UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
25142 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X322                                                          0x001508UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
25143 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X323                                                          0x00150cUL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
25144 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X324                                                          0x001510UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
25145 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X325                                                          0x001514UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
25146 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326                                                          0x001518UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25147     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_48                                       (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
25148     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_48_SHIFT                                 0
25149     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_AHB_LN_IN_OVR_CHG_FLAG_O                             (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
25150     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_AHB_LN_IN_OVR_CHG_FLAG_O_SHIFT                       1
25151     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_REGP1_OVR_O_3_0                                      (0xf<<2) // Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
25152     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_REGP1_OVR_O_3_0_SHIFT                                2
25153     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_OOB_DET_EN                                           (0x1<<6) // OOB detect enable
25154     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_OOB_DET_EN_SHIFT                                     6
25155     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_49                                       (0x1<<7) // OOB detect enable
25156     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X326_LN_IN_OVR_O_49_SHIFT                                 7
25157 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X327                                                          0x00151cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25158     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X327_CDR_CTRL_DLY_DLPF_EN_O                               (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
25159     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X327_CDR_CTRL_DLY_DLPF_EN_O_SHIFT                         0
25160     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X327_UNUSED_0                                             (0x7<<5) // reserved
25161     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X327_UNUSED_0_SHIFT                                       5
25162 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330                                                          0x001528UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25163     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0                     (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
25164     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_SHIFT               0
25165     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_LN_IN_OVR_O_50                                       (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
25166     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_LN_IN_OVR_O_50_SHIFT                                 3
25167     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_UNUSED_0                                             (0xf<<4) // reserved
25168     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_2_X330_UNUSED_0_SHIFT                                       4
25169 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0                                                            0x001800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25170     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_UNUSED_0                                               (0x7f<<0) // reserved
25171     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_UNUSED_0_SHIFT                                         0
25172     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O                             (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
25173     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_SHIFT                       7
25174 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1                                                            0x001804UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25175     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_UNUSED_0                                               (0x7<<0) // reserved
25176     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_UNUSED_0_SHIFT                                         0
25177     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O                             (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
25178     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_SHIFT                       3
25179     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_UNUSED_1                                               (0x7<<4) // reserved
25180     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_UNUSED_1_SHIFT                                         4
25181     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O                             (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
25182     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_SHIFT                       7
25183 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2                                                            0x001808UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25184     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_UNUSED_0                                               (0x7f<<0) // reserved
25185     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_UNUSED_0_SHIFT                                         0
25186     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O                             (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
25187     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_SHIFT                       7
25188 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3                                                            0x00180cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25189     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_CMU_SEL_O_0                                        (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
25190     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_CMU_SEL_O_0_SHIFT                                  0
25191     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_TXCLK_SEL_O_1                                      (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
25192     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_PMA_TXCLK_SEL_O_1_SHIFT                                1
25193     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_UNUSED_0                                               (0x3f<<2) // reserved
25194     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X3_UNUSED_0_SHIFT                                         2
25195 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4                                                            0x001810UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25196     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_CDRCTRL_DIV_EN_O_1_0                                   (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
25197     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_CDRCTRL_DIV_EN_O_1_0_SHIFT                             0
25198     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_GCFSM_DIV_EN_O_1_0                                     (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
25199     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_GCFSM_DIV_EN_O_1_0_SHIFT                               2
25200     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_LN_CLK_TXB_DIV24OR1_O                                  (0x3<<4) // Divide ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state:                                            2'b00: lnX_ck_txb_o is divided by 1 version of the tx byte clock from PMA.                     2'b01/2'b10: lnX_ck_txb_o is divided by 2 version of the tx byte clock from PMA.                  2'b11: lnX_ck_txb_o is divided by 4 version of the tx byte clock from PMA.
25201     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_LN_CLK_TXB_DIV24OR1_O_SHIFT                            4
25202     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_AHB_CHNG_REQ_Z_O                                       (0x1<<6) // Not currently used
25203     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_AHB_CHNG_REQ_Z_O_SHIFT                                 6
25204     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_UNUSED_0                                               (0x1<<7) // reserved
25205     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X4_UNUSED_0_SHIFT                                         7
25206 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5                                                            0x001814UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25207     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_REF_CLK_DIV_EN_O_1_0                                   (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
25208     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_REF_CLK_DIV_EN_O_1_0_SHIFT                             0
25209     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_OOB_CLK_DIV_EN_O_1_0                                   (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
25210     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_OOB_CLK_DIV_EN_O_1_0_SHIFT                             2
25211     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_UNUSED_0                                               (0xf<<4) // reserved
25212     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X5_UNUSED_0_SHIFT                                         4
25213 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7                                                            0x00181cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25214     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_RATE_O                                            (0x3<<0) // Rate control for BIST
25215     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_RATE_O_SHIFT                                      0
25216     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_MODE8B_O                                      (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
25217     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_MODE8B_O_SHIFT                                2
25218     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_ERR_O                                         (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
25219     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_ERR_O_SHIFT                                   3
25220     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_TX_CLOCK_ENABLE                                   (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
25221     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_TX_CLOCK_ENABLE_SHIFT                             4
25222     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_CDN_O                                         (0x1<<5) // Bist generator master reset.
25223     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_CDN_O_SHIFT                                   5
25224     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_WORD_O                                        (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
25225     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_WORD_O_SHIFT                                  6
25226     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_EN_O                                          (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
25227     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X7_BIST_GEN_EN_O_SHIFT                                    7
25228 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8                                                            0x001820UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25229     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_CLK_SEL_O_2_0                                 (0x7<<0) // BIST Generation Clock Selection
25230     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_CLK_SEL_O_2_0_SHIFT                           0
25231     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_SEND_PREAM_O                                  (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
25232     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_SEND_PREAM_O_SHIFT                            3
25233     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_INSERT_COUNT_O_2_0                            (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
25234     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_BIST_GEN_INSERT_COUNT_O_2_0_SHIFT                      4
25235     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_UNUSED_0                                               (0x1<<7) // reserved
25236     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X8_UNUSED_0_SHIFT                                         7
25237 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X9                                                            0x001824UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
25238 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X10                                                           0x001828UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
25239 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X11                                                           0x00182cUL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
25240 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X12                                                           0x001830UL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
25241 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X13                                                           0x001834UL //Access:RW   DataWidth:0x8   Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.  Chips: K2
25242 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14                                                           0x001838UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25243     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BIST_GEN_INSERT_DELAY_O_11_8                          (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
25244     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BIST_GEN_INSERT_DELAY_O_11_8_SHIFT                    0
25245     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_UNUSED_0                                              (0x1<<4) // reserved
25246     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_UNUSED_0_SHIFT                                        4
25247     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_EN_O                                             (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
25248     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_EN_O_SHIFT                                       5
25249     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_CLR_O                                            (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
25250     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_BCHK_CLR_O_SHIFT                                      6
25251     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_UNUSED_1                                              (0x1<<7) // reserved
25252     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X14_UNUSED_1_SHIFT                                        7
25253 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15                                                           0x00183cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25254     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BCHK_SRC_O_1_0                                        (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
25255     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BCHK_SRC_O_1_0_SHIFT                                  0
25256     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_UNUSED_0                                              (0x1<<2) // reserved
25257     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_UNUSED_0_SHIFT                                        2
25258     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_DATA_MODE_O                                  (0x1<<3) // Bist checker mode select. 0X0 ? UDP pattern. 0x1 ? PRBS pattern
25259     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_DATA_MODE_O_SHIFT                            3
25260     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_LFSR_LENGTH_O_1_0                            (0x3<<4) // BIST PRBS pattern selector.
25261     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_CHK_LFSR_LENGTH_O_1_0_SHIFT                      4
25262     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_UNUSED_1                                              (0x1<<6) // reserved
25263     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_UNUSED_1_SHIFT                                        6
25264     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_RX_CLOCK_ENABLE                                  (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
25265     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X15_BIST_RX_CLOCK_ENABLE_SHIFT                            7
25266 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X16                                                           0x001840UL //Access:RW   DataWidth:0x8   Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.  Chips: K2
25267 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17                                                           0x001844UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25268     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_PREAM0_O_9_8                                 (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
25269     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_PREAM0_O_9_8_SHIFT                           0
25270     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_INSERT_LENGTH_O_2_0                          (0x7<<2) // BIST Checker Insert word length.
25271     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_INSERT_LENGTH_O_2_0_SHIFT                    2
25272     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_SYNC_ON_ZEROS                                (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
25273     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_BIST_CHK_SYNC_ON_ZEROS_SHIFT                          5
25274     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_UNUSED_0                                              (0x3<<6) // reserved
25275     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X17_UNUSED_0_SHIFT                                        6
25276 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X18                                                           0x001848UL //Access:RW   DataWidth:0x8   BIST Check Preamble  Chips: K2
25277 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X19                                                           0x00184cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25278     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X19_BIST_CHK_PREAM1_O_9_8                                 (0x3<<0) // BIST Check Preamble
25279     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X19_BIST_CHK_PREAM1_O_9_8_SHIFT                           0
25280     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X19_UNUSED_0                                              (0x3f<<2) // reserved
25281     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X19_UNUSED_0_SHIFT                                        2
25282 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X20                                                           0x001850UL //Access:RW   DataWidth:0x8   Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.  Chips: K2
25283 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X21                                                           0x001854UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
25284 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X22                                                           0x001858UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
25285 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X23                                                           0x00185cUL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
25286 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X24                                                           0x001860UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
25287 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X25                                                           0x001864UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
25288 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X26                                                           0x001868UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
25289 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X27                                                           0x00186cUL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
25290 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X28                                                           0x001870UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
25291 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X29                                                           0x001874UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
25292 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X30                                                           0x001878UL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
25293 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X31                                                           0x00187cUL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
25294 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X32                                                           0x001880UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
25295 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X33                                                           0x001884UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
25296 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X34                                                           0x001888UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
25297 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X35                                                           0x00188cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
25298 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X36                                                           0x001890UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
25299 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X37                                                           0x001894UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
25300 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X38                                                           0x001898UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
25301 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X39                                                           0x00189cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
25302 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X40                                                           0x0018a0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
25303 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X41                                                           0x0018a4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
25304 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X42                                                           0x0018a8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
25305 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X43                                                           0x0018acUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
25306 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X44                                                           0x0018b0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
25307 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X45                                                           0x0018b4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
25308 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X46                                                           0x0018b8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
25309 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X47                                                           0x0018bcUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
25310 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X48                                                           0x0018c0UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 1/2 - for the new ICA method  Chips: K2
25311 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X49                                                           0x0018c4UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 3 - for the new ICA method  Chips: K2
25312 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X50                                                           0x0018c8UL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method  Chips: K2
25313 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X51                                                           0x0018ccUL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method  Chips: K2
25314 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X52                                                           0x0018d0UL //Access:RW   DataWidth:0x8   The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.  Chips: K2
25315 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53                                                           0x0018d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25316     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0                  (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
25317     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_SHIFT            0
25318     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2                           (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
25319     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_SHIFT                     5
25320     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_TW_METHOD_EN                               (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
25321     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_TW_METHOD_EN_SHIFT                         6
25322     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_PMA_LOAD_OVR                               (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
25323     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X53_GCFSM_LANE_PMA_LOAD_OVR_SHIFT                         7
25324 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X54                                                           0x0018d8UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
25325 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X55                                                           0x0018dcUL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
25326 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X56                                                           0x0018e0UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
25327 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57                                                           0x0018e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25328     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_OVR_O_27_24                                     (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
25329     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_OVR_O_27_24_SHIFT                               0
25330     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_OUT_OVR_EN_O                               (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
25331     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_OUT_OVR_EN_O_SHIFT                         4
25332     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_LATCH_OVR_O                            (0x1<<5) // GCFSM pma_latch_o override
25333     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_LATCH_OVR_O_SHIFT                      5
25334     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_GO_OVR_O                               (0x1<<6) // GCFSM pma_go_o override
25335     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_GO_OVR_O_SHIFT                         6
25336     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_READ_OVR_O                             (0x1<<7) // GCFSM pma_read_o override.
25337     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X57_GCFSM_LANE_PMA_READ_OVR_O_SHIFT                       7
25338 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X58                                                           0x0018e8UL //Access:RW   DataWidth:0x8   GCFSM pma_data_o override data. Bits applied to PMA are [8:15]  Chips: K2
25339 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X59                                                           0x0018ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25340     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8                        (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
25341     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_SHIFT                  0
25342     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X59_UNUSED_0                                              (0xf<<4) // reserved
25343     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X59_UNUSED_0_SHIFT                                        4
25344 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X60                                                           0x0018f0UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
25345 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X61                                                           0x0018f4UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
25346 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62                                                           0x0018f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25347     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_LN_MSM_REQ_IN_OVR_O                                   (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
25348     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_LN_MSM_REQ_IN_OVR_O_SHIFT                             0
25349     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_LN_MSM_FUNC_IN_OVR_O                                  (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
25350     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X62_LN_MSM_FUNC_IN_OVR_O_SHIFT                            2
25351 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65                                                           0x001904UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25352     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65_GCFSM_OVR_O_28                                        (0x1<<0) // Not currently used
25353     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65_GCFSM_OVR_O_28_SHIFT                                  0
25354     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65_UNUSED_0                                              (0x7f<<1) // reserved
25355     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X65_UNUSED_0_SHIFT                                        1
25356 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X66                                                           0x001908UL //Access:RW   DataWidth:0x8   Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.  Chips: K2
25357 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67                                                           0x00190cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25358     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_DLY_CDR_O_6_0                                (0x7f<<0) // Number of clock cycles between signal detect indicator
25359     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_DLY_CDR_O_6_0_SHIFT                          0
25360     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8                           (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
25361     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_SHIFT                     7
25362 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X68                                                           0x001910UL //Access:RW   DataWidth:0x8   Number of clock cycles between CISEL assertion  Chips: K2
25363 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69                                                           0x001914UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25364     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_DLY_LANE_O_9_8                               (0x3<<0) // Number of clock cycles between CISEL assertion
25365     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_DLY_LANE_O_9_8_SHIFT                         0
25366     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_START_LEN_O_3_0                              (0xf<<2) // Number of clock cycles between when CDR control block
25367     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_START_LEN_O_3_0_SHIFT                        2
25368     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_INT_FIL_O_1_0                                (0x3<<6) // CDR control DLPF positioning control.
25369     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X69_CDR_CTRL_INT_FIL_O_1_0_SHIFT                          6
25370 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X70                                                           0x001918UL //Access:RW   DataWidth:0x8   CDR control block cycle length When not in PCIe Gen3.  Chips: K2
25371 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X71                                                           0x00191cUL //Access:RW   DataWidth:0x8   CDR control block cycle length When in PCIe Gen3.  Chips: K2
25372 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72                                                           0x001920UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25373     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_CDR_CTRL_MAX_DIFF_O_4_0                               (0x1f<<0) // Maximum difference from DLPF center point.
25374     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_CDR_CTRL_MAX_DIFF_O_4_0_SHIFT                         0
25375     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_CDR_CTRL_MIN_BOUNCE_O_2_0                             (0x7<<5) // Maximum difference from DLPF center point.
25376     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_SHIFT                       5
25377 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73                                                           0x001924UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25378     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_TW_METHOD_EN                                 (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
25379     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_TW_METHOD_EN_SHIFT                           0
25380     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CONTROL_ATT_CTRL_O                                (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
25381     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CONTROL_ATT_CTRL_O_SHIFT                          1
25382     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_RXEQ_WAIT_EN_O                                        (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
25383     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_RXEQ_WAIT_EN_O_SHIFT                                  2
25384     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_DLY_CDR_O_9_7                                (0x7<<3) // Number of clock cycles between signal detect indicator
25385     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_CDR_CTRL_DLY_CDR_O_9_7_SHIFT                          3
25386     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_UNUSED_0                                              (0x3<<6) // reserved
25387     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X73_UNUSED_0_SHIFT                                        6
25388 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X74                                                           0x001928UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
25389 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X75                                                           0x00192cUL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
25390 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X76                                                           0x001930UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
25391 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77                                                           0x001934UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25392     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_OUT_OVR_O_29_24                              (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
25393     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_OUT_OVR_O_29_24_SHIFT                        0
25394     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_CAL_LOAD_OVR                                 (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
25395     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_CDR_CTRL_CAL_LOAD_OVR_SHIFT                           6
25396     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_UNUSED_0                                              (0x1<<7) // reserved
25397     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X77_UNUSED_0_SHIFT                                        7
25398 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78                                                           0x001938UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25399     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_SYM_ALIGN_ALIGN_POS_O_5_0                             (0x3f<<0) // Symbol aligner position override enable.
25400     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_SYM_ALIGN_ALIGN_POS_O_5_0_SHIFT                       0
25401     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_SYM_ALIGN_MODE_O_1_0                                  (0x3<<6) // Symbol aligner mode select.
25402     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X78_SYM_ALIGN_MODE_O_1_0_SHIFT                            6
25403 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79                                                           0x00193cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25404     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79_SYM_ALIGN_BYPASS_O                                    (0x1<<0) // Asserting this register will bypass the symbol aligner
25405     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79_SYM_ALIGN_BYPASS_O_SHIFT                              0
25406     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79_UNUSED_0                                              (0x7f<<1) // reserved
25407     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X79_UNUSED_0_SHIFT                                        1
25408 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X80                                                           0x001940UL //Access:RW   DataWidth:0x8   Number of cycles to wait before forcing exit form EI  Chips: K2
25409 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81                                                           0x001944UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25410     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8                    (0x3<<0) // Number of cycles to wait before forcing exit form EI
25411     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_SHIFT              0
25412     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_CLR_ERR_O                               (0x1<<2) // Clears the elec idle control error flag
25413     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_CLR_ERR_O_SHIFT                         2
25414     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_INFERRED_O                           (0x1<<3) // Override for ei_inferred signal
25415     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_INFERRED_O_SHIFT                     3
25416     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O                        (0x1<<4) // Override for ei_mask signal
25417     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_SHIFT                  4
25418     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O                         (0x1<<5) // Override for ei_exit_type signal
25419     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_SHIFT                   5
25420     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_OVR_O                                   (0x1<<6) // EI control override enable
25421     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_ELECIDLE_CTRL_OVR_O_SHIFT                             6
25422     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_UNUSED_0                                              (0x1<<7) // reserved
25423     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X81_UNUSED_0_SHIFT                                        7
25424 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X82                                                           0x001948UL //Access:RW   DataWidth:0x8   Number of cycles to wait before entering back into EI  Chips: K2
25425 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X83                                                           0x00194cUL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect glitch filter counter  Chips: K2
25426 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X84                                                           0x001950UL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect low filter min value  Chips: K2
25427 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85                                                           0x001954UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25428     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8                    (0x3<<0) // Number of cycles to wait before entering back into EI
25429     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_SHIFT              0
25430     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0                     (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
25431     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_SHIFT               2
25432     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_LOOPBACK_EN_O                                         (0x1<<4) // Control signal to force decoder into loopback mode
25433     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_LOOPBACK_EN_O_SHIFT                                   4
25434     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_UNUSED_0                                              (0x7<<5) // reserved
25435     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X85_UNUSED_0_SHIFT                                        5
25436 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86                                                           0x001958UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25437     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_FES_LB_ENA_O                                          (0x1<<0) // FES loopback enable.
25438     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_FES_LB_ENA_O_SHIFT                                    0
25439     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_NES_LB_ENA_O                                          (0x1<<1) // NES loopback enable.
25440     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_NES_LB_ENA_O_SHIFT                                    1
25441     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_RXCLK_LB_ENA_O                                        (0x1<<2) // HS recovered clock to transmit loopback enable.
25442     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_RXCLK_LB_ENA_O_SHIFT                                  2
25443     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_UNUSED_0                                              (0x1f<<3) // reserved
25444     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X86_UNUSED_0_SHIFT                                        3
25445 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87                                                           0x00195cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25446     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOST_OVR_O                             (0x1<<0) // RX boost override enable
25447     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOST_OVR_O_SHIFT                       0
25448     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O                        (0x7f<<1) // RX boost override setting. Thermometer coded.
25449     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_SHIFT                  1
25450 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X88                                                           0x001960UL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
25451 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89                                                           0x001964UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25452     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV1_O                            (0x7<<0) // Signal detect threshold select for Full rate
25453     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_SHIFT                      0
25454     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV2_O                            (0x7<<3) // Signal detect threshold select for div-by-2 rate
25455     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_SHIFT                      3
25456     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXUP_O                                     (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
25457     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXUP_O_SHIFT                               6
25458     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXPREDIV4_ENA_O                            (0x1<<7) // RX FL calibration clock DIV4 enable
25459     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_SHIFT                      7
25460 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90                                                           0x001968UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25461     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_SD_THSEL_DIV4_O                            (0x7<<0) // Signal detect threshold select for div-by-4 rate
25462     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_SHIFT                      0
25463     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_AGC_THSEL_O                                (0x7<<3) // AGC threshold select
25464     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_AGC_THSEL_O_SHIFT                          3
25465     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_VREGH_O                                    (0x3<<6) // Regulator VREGH setting
25466     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X90_AHB_PMA_LN_VREGH_O_SHIFT                              6
25467 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X91                                                           0x00196cUL //Access:RW   DataWidth:0x8   RX FL calibration LDHS  Chips: K2
25468 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92                                                           0x001970UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25469     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O                            (0x3<<0) // RX FL calibration LDHS
25470     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_SHIFT                      0
25471     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_RXVCO_BIAS_O                               (0xf<<2) // CDR VCO bias setting.
25472     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_RXVCO_BIAS_O_SHIFT                         2
25473     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O                            (0x1<<6) // DLPF DIV2 enable
25474     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_SHIFT                      6
25475     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_CDR_DVDR_ENA_O                             (0x1<<7) // CDR DivN clock divider enable.
25476     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_SHIFT                       7
25477 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X93                                                           0x001974UL //Access:RW   DataWidth:0x8   AFE spare controls  Chips: K2
25478 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94                                                           0x001978UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25479     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_AHB_PMA_LN_CDR_DVDR_O                                 (0x3f<<0) // CDR DivN clock division ratio.
25480     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_AHB_PMA_LN_CDR_DVDR_O_SHIFT                           0
25481     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_AHB_PMA_LN_VREG_O                                     (0x3<<6) // Regulator VREG setting
25482     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X94_AHB_PMA_LN_VREG_O_SHIFT                               6
25483 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95                                                           0x00197cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25484     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_BB_STEP_O                                  (0xf<<0) // CDR bb_step
25485     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_BB_STEP_O_SHIFT                            0
25486     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_INT_STEP_O                                 (0x7<<4) // CDR int step
25487     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_INT_STEP_O_SHIFT                           4
25488     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_RXDWN_O                                    (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
25489     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X95_AHB_PMA_LN_RXDWN_O_SHIFT                              7
25490 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96                                                           0x001980UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25491     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_O                                  (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
25492     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_O_SHIFT                            0
25493     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_SEL_O                              (0x1<<3) // Override enable for RXVCOFR override vakue
25494     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RXVCOFR_SEL_O_SHIFT                        3
25495     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RX_SELR_O                                  (0x7<<4) // CTLE R degeneration select
25496     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_AHB_PMA_LN_RX_SELR_O_SHIFT                            4
25497     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_UNUSED_0                                              (0x1<<7) // reserved
25498     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X96_UNUSED_0_SHIFT                                        7
25499 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X97                                                           0x001984UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25500     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X97_AHB_PMA_LN_RX_SELC_O                                  (0x7<<0) // CTLE C degeneration select
25501     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X97_AHB_PMA_LN_RX_SELC_O_SHIFT                            0
25502     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X97_UNUSED_0                                              (0x1f<<3) // reserved
25503     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X97_UNUSED_0_SHIFT                                        3
25504 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99                                                           0x00198cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25505     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_UNUSED_0                                              (0xf<<0) // reserved
25506     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_UNUSED_0_SHIFT                                        0
25507     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_PMA_LN_DFE_BW_SCALE                                   (0x3<<4) // DFE Bandwidth Selection
25508     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_PMA_LN_DFE_BW_SCALE_SHIFT                             4
25509     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_PMA_LN_PHD_ENA_O_1_0                                  (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
25510     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X99_PMA_LN_PHD_ENA_O_1_0_SHIFT                            6
25511 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X100                                                          0x001990UL //Access:RW   DataWidth:0x8   On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal  Chips: K2
25512 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101                                                          0x001994UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25513     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_DLY_O_8_8                                 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
25514     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_DLY_O_8_8_SHIFT                           0
25515     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_UNUSED_0                                             (0x1<<1) // reserved
25516     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_UNUSED_0_SHIFT                                       1
25517     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_SGN_RST_O                                 (0x1<<2) // Reset signal for eye alignment mechanism.
25518     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_SGN_RST_O_SHIFT                           2
25519     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_SD_BWSEL                                      (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
25520     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_SD_BWSEL_SHIFT                                3
25521     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA270_O                                  (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
25522     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA270_O_SHIFT                            4
25523     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA90_O                                   (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
25524     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_PMA_LN_EYE_ENA90_O_SHIFT                             5
25525     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_UNUSED_1                                             (0x3<<6) // reserved
25526     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X101_UNUSED_1_SHIFT                                       6
25527 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X102                                                          0x001998UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25528     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X102_PMA_LN_DFE_BIAS_O_3_0                                (0xf<<0) // DFE bias setting.
25529     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X102_PMA_LN_DFE_BIAS_O_3_0_SHIFT                          0
25530     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X102_UNUSED_0                                             (0xf<<4) // reserved
25531     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X102_UNUSED_0_SHIFT                                       4
25532 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103                                                          0x00199cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25533     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_PMA_LN_TX_SR_FASTCAP_O_3_0                           (0xf<<0) // TX driver capacitive slew rate control.
25534     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_SHIFT                     0
25535     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_PMA_LN_TXEQ_POLARITY_O_3_0                           (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
25536     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X103_PMA_LN_TXEQ_POLARITY_O_3_0_SHIFT                     4
25537 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104                                                          0x0019a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25538     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_TX_SR_DAC_O_3_0                               (0xf<<0) // TX slew rate DAC bias current control
25539     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_TX_SR_DAC_O_3_0_SHIFT                         0
25540     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_HSCLK_SEL_O                                   (0x1<<4) // CDR clock divider bypass enable.
25541     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_PMA_LN_HSCLK_SEL_O_SHIFT                             4
25542     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_UNUSED_0                                             (0x7<<5) // reserved
25543     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X104_UNUSED_0_SHIFT                                       5
25544 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105                                                          0x0019a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25545     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TX_VREG_LEV_O_4_0                             (0x1f<<0) // TX driver regulator voltage setting.
25546     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TX_VREG_LEV_O_4_0_SHIFT                       0
25547     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TXDRV_BLEED_ENA_O                             (0x1<<5) // TX bleed enable
25548     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_PMA_LN_TXDRV_BLEED_ENA_O_SHIFT                       5
25549     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_UNUSED_0                                             (0x3<<6) // reserved
25550     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X105_UNUSED_0_SHIFT                                       6
25551 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106                                                          0x0019a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25552     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O                       (0x1<<0) // RX boost override enable.
25553     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_SHIFT                 0
25554     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O                    (0x7f<<1) // RX boost override setting. Thermometer coded.
25555     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_SHIFT              1
25556 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X107                                                          0x0019acUL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
25557 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108                                                          0x0019b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25558     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_SD_THSEL_GEN3_O                           (0x7<<0) // Signal detect threshold select for Gen3
25559     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_SHIFT                     0
25560     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O                          (0x7<<3) // AGC threshold select for Gen3
25561     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_SHIFT                    3
25562     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXUP_GEN3_O                               (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
25563     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXUP_GEN3_O_SHIFT                         6
25564     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O                      (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
25565     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_SHIFT                7
25566 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X109                                                          0x0019b4UL //Access:RW   DataWidth:0x8   RX FL calibration LDHS for Gen3  Chips: K2
25567 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110                                                          0x0019b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25568     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O                      (0x3<<0) // RX FL calibration LDHS for Gen3
25569     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_SHIFT                0
25570     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O                         (0xf<<2) // CDR VCO bias setting.
25571     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_SHIFT                   2
25572     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O                      (0x1<<6) // DLPF DIV2 enable
25573     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_SHIFT                6
25574     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O                       (0x1<<7) // CDR DivN clock divider enable.
25575     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_SHIFT                 7
25576 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X111                                                          0x0019bcUL //Access:RW   DataWidth:0x8   AFE spare controls for Gen3  Chips: K2
25577 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112                                                          0x0019c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25578     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O                           (0x3f<<0) // CDR DivN clock divider ratio..
25579     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_SHIFT                     0
25580     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_AHB_PMA_LN_VREG_GEN3_O                               (0x3<<6) // Regulator VREG setting for Gen3
25581     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X112_AHB_PMA_LN_VREG_GEN3_O_SHIFT                         6
25582 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113                                                          0x0019c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25583     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_BB_STEP_GEN3_O                            (0xf<<0) // CDR bb_step for Gen3
25584     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_BB_STEP_GEN3_O_SHIFT                      0
25585     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_INT_STEP_GEN3_O                           (0x7<<4) // CDR int step for Gen3
25586     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_INT_STEP_GEN3_O_SHIFT                     4
25587     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_RXDWN_GEN3_O                              (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
25588     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X113_AHB_PMA_LN_RXDWN_GEN3_O_SHIFT                        7
25589 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114                                                          0x0019c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25590     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RXVCOFR_GEN3_O                            (0x7<<0) // RXVCOFR override value for Gen3 Enabled by pma_ln_dr_rxvcofr_sel_o
25591     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_SHIFT                      0
25592     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RX_SELR_GEN3_O                            (0x7<<3) // CTLE R degeneration select for Gen3
25593     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_RX_SELR_GEN3_O_SHIFT                      3
25594     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_VREGH_GEN3_O                              (0x3<<6) // Not currently used
25595     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X114_AHB_PMA_LN_VREGH_GEN3_O_SHIFT                        6
25596 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X115                                                          0x0019ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25597     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X115_AHB_PMA_LN_RX_SELC_GEN3_O                            (0x7<<0) // CTLE R degeneration select for Gen3
25598     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X115_AHB_PMA_LN_RX_SELC_GEN3_O_SHIFT                      0
25599     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X115_UNUSED_0                                             (0x1f<<3) // reserved
25600     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X115_UNUSED_0_SHIFT                                       3
25601 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119                                                          0x0019dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25602     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_AHB_TX_CXP_MARGIN                                    (0xf<<0) // Value to minus/add from the calibrated txterm value
25603     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_AHB_TX_CXP_MARGIN_SHIFT                              0
25604     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_AHB_TX_CXN_MARGIN                                    (0xf<<4) // Value to minus/add from the calibrated txterm value
25605     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X119_AHB_TX_CXN_MARGIN_SHIFT                              4
25606 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120                                                          0x0019e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25607     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_AHB_TX_TC_WAIT_NEXT_CMP                              (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
25608     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_AHB_TX_TC_WAIT_NEXT_CMP_SHIFT                        0
25609     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE                           (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
25610     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_SHIFT                     4
25611     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_UNUSED_0                                             (0x1<<7) // reserved
25612     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X120_UNUSED_0_SHIFT                                       7
25613 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121                                                          0x0019e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25614     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES                        (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
25615     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_SHIFT                  0
25616     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXP_MARGIN_ADD_0                              (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
25617     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXP_MARGIN_ADD_0_SHIFT                        4
25618     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXN_MARGIN_ADD_0                              (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
25619     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CXN_MARGIN_ADD_0_SHIFT                        5
25620     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CX_OVR_ENA                                    (0x1<<6) // enable override calibrated txterm value
25621     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_CX_OVR_ENA_SHIFT                              6
25622     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TERM_EN_CAL_OVR                               (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
25623     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X121_AHB_TX_TERM_EN_CAL_OVR_SHIFT                         7
25624 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122                                                          0x0019e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25625     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_AHB_TX_CXP_OVR                                       (0xf<<0) // override calibrated txterm value
25626     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_AHB_TX_CXP_OVR_SHIFT                                 0
25627     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_AHB_TX_CXN_OVR                                       (0xf<<4) // override calibrated txterm value
25628     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X122_AHB_TX_CXN_OVR_SHIFT                                 4
25629 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123                                                          0x0019ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25630     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_0                                          (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
25631     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_0_SHIFT                                    0
25632     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_UNUSED_0                                             (0x1<<1) // reserved
25633     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_UNUSED_0_SHIFT                                       1
25634     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_7_2                                        (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
25635     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X123_TX_CTRL_O_7_2_SHIFT                                  2
25636 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X124                                                          0x0019f0UL //Access:RW   DataWidth:0x8   Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]  Chips: K2
25637 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X125                                                          0x0019f4UL //Access:RW   DataWidth:0x8   Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode  Chips: K2
25638 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126                                                          0x0019f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25639     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_EN_O                                            (0x1<<0) // DFE block enable signal.
25640     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_EN_O_SHIFT                                      0
25641     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE_OW_O_2_0                                (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
25642     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE_OW_O_2_0_SHIFT                          1
25643     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE1_CAL_EN_O_3                             (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
25644     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE1_CAL_EN_O_3_SHIFT                       4
25645     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE2_CAL_EN_O_4                             (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
25646     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE2_CAL_EN_O_4_SHIFT                       5
25647     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE3_CAL_EN_O_5                             (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
25648     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_RATE3_CAL_EN_O_5_SHIFT                       6
25649     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_FORCE_CAL_O_6                                (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
25650     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X126_RXEQ_LN_FORCE_CAL_O_6_SHIFT                          7
25651 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127                                                          0x0019fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25652     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_RXEQ_CONT_CAL_O_6_0                                  (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
25653     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_RXEQ_CONT_CAL_O_6_0_SHIFT                            0
25654     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_UNUSED_0                                             (0x1<<7) // reserved
25655     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X127_UNUSED_0_SHIFT                                       7
25656 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X128                                                          0x001a00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25657     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X128_RXEQ_INIT_CAL_O_6_0                                  (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
25658     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X128_RXEQ_INIT_CAL_O_6_0_SHIFT                            0
25659     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X128_UNUSED_0                                             (0x1<<7) // reserved
25660     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X128_UNUSED_0_SHIFT                                       7
25661 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130                                                          0x001a08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25662     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_RXEQ_RATE1_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate1
25663     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_RXEQ_RATE1_ATT_START_O_3_0_SHIFT                     0
25664     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_RXEQ_RATE1_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate1
25665     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X130_RXEQ_RATE1_BOOST_START_O_3_0_SHIFT                   4
25666 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131                                                          0x001a0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25667     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_RXEQ_RATE2_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate2
25668     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_RXEQ_RATE2_ATT_START_O_3_0_SHIFT                     0
25669     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_RXEQ_RATE2_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate2
25670     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X131_RXEQ_RATE2_BOOST_START_O_3_0_SHIFT                   4
25671 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X132                                                          0x001a10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25672     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X132_RXEQ_RATE2_TAP1_START_O_6_0                          (0x7f<<0) // DFE Tap1 start value for rate2
25673     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X132_RXEQ_RATE2_TAP1_START_O_6_0_SHIFT                    0
25674     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X132_UNUSED_0                                             (0x1<<7) // reserved
25675     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X132_UNUSED_0_SHIFT                                       7
25676 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X133                                                          0x001a14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25677     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X133_RXEQ_RATE2_TAP2_START_O_5_0                          (0x3f<<0) // DFE Tap2 start value for rate2
25678     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X133_RXEQ_RATE2_TAP2_START_O_5_0_SHIFT                    0
25679     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X133_UNUSED_0                                             (0x3<<6) // reserved
25680     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X133_UNUSED_0_SHIFT                                       6
25681 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X134                                                          0x001a18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25682     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X134_RXEQ_RATE2_TAP3_START_O_5_0                          (0x3f<<0) // DFE Tap3 start value for rate2
25683     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X134_RXEQ_RATE2_TAP3_START_O_5_0_SHIFT                    0
25684     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X134_UNUSED_0                                             (0x3<<6) // reserved
25685     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X134_UNUSED_0_SHIFT                                       6
25686 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X135                                                          0x001a1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25687     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X135_RXEQ_RATE2_TAP4_START_O_5_0                          (0x3f<<0) // DFE Tap4 start value for rate2
25688     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X135_RXEQ_RATE2_TAP4_START_O_5_0_SHIFT                    0
25689     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X135_UNUSED_0                                             (0x3<<6) // reserved
25690     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X135_UNUSED_0_SHIFT                                       6
25691 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X136                                                          0x001a20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25692     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X136_RXEQ_RATE2_TAP5_START_O_5_0                          (0x3f<<0) // DFE Tap5 start value for rate2
25693     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X136_RXEQ_RATE2_TAP5_START_O_5_0_SHIFT                    0
25694     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X136_UNUSED_0                                             (0x3<<6) // reserved
25695     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X136_UNUSED_0_SHIFT                                       6
25696 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137                                                          0x001a24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25697     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_RXEQ_RATE3_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate3
25698     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_RXEQ_RATE3_ATT_START_O_3_0_SHIFT                     0
25699     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_RXEQ_RATE3_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate3
25700     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X137_RXEQ_RATE3_BOOST_START_O_3_0_SHIFT                   4
25701 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X138                                                          0x001a28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25702     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X138_RXEQ_RATE3_TAP1_START_O_6_0                          (0x7f<<0) // DFE Tap1 start value for rate3
25703     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X138_RXEQ_RATE3_TAP1_START_O_6_0_SHIFT                    0
25704     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X138_UNUSED_0                                             (0x1<<7) // reserved
25705     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X138_UNUSED_0_SHIFT                                       7
25706 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X139                                                          0x001a2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25707     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X139_RXEQ_RATE3_TAP2_START_O_5_0                          (0x3f<<0) // DFE Tap2 start value for rate3
25708     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X139_RXEQ_RATE3_TAP2_START_O_5_0_SHIFT                    0
25709     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X139_UNUSED_0                                             (0x3<<6) // reserved
25710     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X139_UNUSED_0_SHIFT                                       6
25711 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X140                                                          0x001a30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25712     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X140_RXEQ_RATE3_TAP3_START_O_5_0                          (0x3f<<0) // DFE Tap3 start value for rate3
25713     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X140_RXEQ_RATE3_TAP3_START_O_5_0_SHIFT                    0
25714     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X140_UNUSED_0                                             (0x3<<6) // reserved
25715     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X140_UNUSED_0_SHIFT                                       6
25716 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X141                                                          0x001a34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25717     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X141_RXEQ_RATE3_TAP4_START_O_5_0                          (0x3f<<0) // DFE Tap4 start value for rate3
25718     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X141_RXEQ_RATE3_TAP4_START_O_5_0_SHIFT                    0
25719     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X141_UNUSED_0                                             (0x3<<6) // reserved
25720     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X141_UNUSED_0_SHIFT                                       6
25721 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X142                                                          0x001a38UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25722     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X142_RXEQ_RATE3_TAP5_START_O_5_0                          (0x3f<<0) // DFE Tap5 start value for rate3
25723     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X142_RXEQ_RATE3_TAP5_START_O_5_0_SHIFT                    0
25724     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X142_UNUSED_0                                             (0x3<<6) // reserved
25725     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X142_UNUSED_0_SHIFT                                       6
25726 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143                                                          0x001a3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25727     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RXEQ_SUPERBST_AUTOCAL_DIS                            (0x1<<0) // Disable auto cal w/ rx_superbst
25728     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RXEQ_SUPERBST_AUTOCAL_DIS_SHIFT                      0
25729     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_O                                    (0xf<<1) // Max limit value for BOOST auto-calibration
25730     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_O_SHIFT                              1
25731     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_EN_O                                 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
25732     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_BOOST_MAX_LIMIT_EN_O_SHIFT                           5
25733     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RX_ATT_BOOST_CAL_O_1_0                               (0x3<<6) // rx_att_boost setting used during ATT calibration
25734     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X143_RX_ATT_BOOST_CAL_O_1_0_SHIFT                         6
25735 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144                                                          0x001a40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25736     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RX_ATT_BOOST_NORM_O_1_0                              (0x3<<0) // rx_att_boost setting used after ATT calibration
25737     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RX_ATT_BOOST_NORM_O_1_0_SHIFT                        0
25738     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_EN_O                                  (0x1<<2) // boost_adj_en
25739     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_EN_O_SHIFT                            2
25740     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_DIR_O                                 (0x1<<3) // boost_adj_dir
25741     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_DIR_O_SHIFT                           3
25742     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_VAL_O                                 (0xf<<4) // boost_adj_val This register Is not bit reversed
25743     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X144_RXEQ_BOOST_ADJ_VAL_O_SHIFT                           4
25744 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145                                                          0x001a44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25745     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0                    (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
25746     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_SHIFT              0
25747     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_EN_O                                  (0x1<<7) // CMP Offset Noise Averaging Enable
25748     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X145_CMP_OFFSET_AVG_EN_O_SHIFT                            7
25749 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X146                                                          0x001a48UL //Access:RW   DataWidth:0x8     Chips: K2
25750 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147                                                          0x001a4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25751     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_DFE_TAP_PD_WAIT_11_8                            (0xf<<0) //
25752     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_SHIFT                      0
25753     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_PMA_LN_DFE_OFS_CAL_ENA                               (0x3<<4) // DFE offset calibration enable
25754     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_PMA_LN_DFE_OFS_CAL_ENA_SHIFT                         4
25755     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS                            (0x1<<6) // Disable auto cal w/ rx_att_gain
25756     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_SHIFT                      6
25757     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_SUPERBST_EN_INVERT_O                            (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
25758     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X147_RXEQ_SUPERBST_EN_INVERT_O_SHIFT                      7
25759 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148                                                          0x001a50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25760     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_LOAD_EN_O_6_0                               (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
25761     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_LOAD_EN_O_6_0_SHIFT                         0
25762     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_EN_O                                        (0x1<<7) // Override enable for DFE signals.
25763     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X148_RXEQ_OVR_EN_O_SHIFT                                  7
25764 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149                                                          0x001a54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25765     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LOAD_O_6_0                                  (0x7f<<0) // Override for RXEQ_CTRL output register load value.
25766     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LOAD_O_6_0_SHIFT                            0
25767     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LATCH_O                                     (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
25768     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X149_RXEQ_OVR_LATCH_O_SHIFT                               7
25769 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150                                                          0x001a58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25770     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0                           (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
25771     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_SHIFT                     0
25772     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_ATT_GAIN_OVR                                    (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
25773     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_ATT_GAIN_OVR_SHIFT                              3
25774     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_SUPERBST_ENA_OVR                                (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
25775     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_RXEQ_SUPERBST_ENA_OVR_SHIFT                          5
25776     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6                       (0x1<<6) // DFE TAP CMP no offset override enable
25777     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_SHIFT                 6
25778     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_OVR_EN_O_7                                   (0x1<<7) // DFE TAP override enable
25779     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X150_DFE_TAP_OVR_EN_O_7_SHIFT                             7
25780 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151                                                          0x001a5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25781     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3                      (0x1f<<0) // DFE offset calibration TAP enable override
25782     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_SHIFT                0
25783     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0                        (0x1<<5) // DFE offset calibrated value override enable
25784     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_SHIFT                  5
25785     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_EN_OVR_O_1                            (0x1<<6) // DFE offset cal enable override
25786     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_OFFSET_CAL_EN_OVR_O_1_SHIFT                      6
25787     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_CMP_CAL_EN_OVR_O_2                               (0x1<<7) // DFE comparator cal enable override
25788     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X151_DFE_CMP_CAL_EN_OVR_O_2_SHIFT                         7
25789 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X152                                                          0x001a60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25790     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X152_DFE_TAP1_OVR_VAL_O_6_0                               (0x7f<<0) // DFE Tap 1 Override Value
25791     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X152_DFE_TAP1_OVR_VAL_O_6_0_SHIFT                         0
25792     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X152_UNUSED_0                                             (0x1<<7) // reserved
25793     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X152_UNUSED_0_SHIFT                                       7
25794 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X153                                                          0x001a64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25795     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X153_DFE_TAP2_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 2 Override Value
25796     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X153_DFE_TAP2_OVR_VAL_O_5_0_SHIFT                         0
25797     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X153_UNUSED_0                                             (0x3<<6) // reserved
25798     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X153_UNUSED_0_SHIFT                                       6
25799 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X154                                                          0x001a68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25800     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X154_DFE_TAP3_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 3 Override Value
25801     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X154_DFE_TAP3_OVR_VAL_O_5_0_SHIFT                         0
25802     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X154_UNUSED_0                                             (0x3<<6) // reserved
25803     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X154_UNUSED_0_SHIFT                                       6
25804 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X155                                                          0x001a6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25805     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X155_DFE_TAP4_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 4 Override Value
25806     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X155_DFE_TAP4_OVR_VAL_O_5_0_SHIFT                         0
25807     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X155_UNUSED_0                                             (0x3<<6) // reserved
25808     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X155_UNUSED_0_SHIFT                                       6
25809 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X156                                                          0x001a70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25810     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X156_DFE_TAP5_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 5 Override Value
25811     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X156_DFE_TAP5_OVR_VAL_O_5_0_SHIFT                         0
25812     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X156_UNUSED_0                                             (0x3<<6) // reserved
25813     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X156_UNUSED_0_SHIFT                                       6
25814 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157                                                          0x001a74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25815     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ADAPT_EN_O_0                                    (0x1<<0) // TX Equalizer adaptation function enable
25816     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ADAPT_EN_O_0_SHIFT                              0
25817     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ERR_SIGN_O_1                                    (0x1<<1) // TX Equalizer Error Sign
25818     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_ERR_SIGN_O_1_SHIFT                              1
25819     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_FW_OVRIDE_O_2                                   (0x1<<2) // TX Equalization Firmware over ride  0 -	 Disable firmware based adaptation  1 -	 Enbale firmware based adaptation
25820     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_TXEQ_FW_OVRIDE_O_2_SHIFT                             2
25821     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_UNUSED_0                                             (0x1f<<3) // reserved
25822     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X157_UNUSED_0_SHIFT                                       3
25823 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X158                                                          0x001a78UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
25824     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X158_TXEQ_ERR_STAT_I_1_0                                  (0x3<<0) // TX Equalization error state
25825     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X158_TXEQ_ERR_STAT_I_1_0_SHIFT                            0
25826     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X158_UNUSED_0                                             (0x3f<<2) // reserved
25827     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X158_UNUSED_0_SHIFT                                       2
25828 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X159                                                          0x001a7cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
25829     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X159_TXEQ_OVER_EQ_CNT_I_9_8                               (0x3<<0) // Over equalization count 9-8
25830     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X159_TXEQ_OVER_EQ_CNT_I_9_8_SHIFT                         0
25831     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X159_UNUSED_0                                             (0x3f<<2) // reserved
25832     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X159_UNUSED_0_SHIFT                                       2
25833 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X160                                                          0x001a80UL //Access:R    DataWidth:0x8   Over equalization count 7-0  Chips: K2
25834 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X161                                                          0x001a84UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
25835     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X161_TXEQ_UNDER_EQ_CNT_I_9_8                              (0x3<<0) // Under equalization count 9-8
25836     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X161_TXEQ_UNDER_EQ_CNT_I_9_8_SHIFT                        0
25837     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X161_UNUSED_0                                             (0x3f<<2) // reserved
25838     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X161_UNUSED_0_SHIFT                                       2
25839 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X162                                                          0x001a88UL //Access:R    DataWidth:0x8   Under equalization count 7-0  Chips: K2
25840 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X163                                                          0x001a8cUL //Access:RW   DataWidth:0x8   TX Equalizer Training Pattern  Chips: K2
25841 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164                                                          0x001a90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25842     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164_TXEQ_TRAINING_PATT_O_8                               (0x1<<0) // TX Equalizer Training Pattern
25843     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164_TXEQ_TRAINING_PATT_O_8_SHIFT                         0
25844     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164_UNUSED_0                                             (0x7f<<1) // reserved
25845     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X164_UNUSED_0_SHIFT                                       1
25846 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X165                                                          0x001a94UL //Access:RW   DataWidth:0x8   Mask bit for Txeq training pattern  Chips: K2
25847 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166                                                          0x001a98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25848     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166_TXEQ_DONT_CARE_O_8                                   (0x1<<0) // Mask bit for Txeq training pattern
25849     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166_TXEQ_DONT_CARE_O_8_SHIFT                             0
25850     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166_UNUSED_0                                             (0x7f<<1) // reserved
25851     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X166_UNUSED_0_SHIFT                                       1
25852 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167                                                          0x001a9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25853     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167_TXEQ_RXRECAL_INIT_O_7                                (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
25854     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167_TXEQ_RXRECAL_INIT_O_7_SHIFT                          0
25855     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167_UNUSED_0                                             (0x7f<<1) // reserved
25856     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X167_UNUSED_0_SHIFT                                       1
25857 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168                                                          0x001aa0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25858     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_INIT_RX_PRESET_HINT_EN_O                             (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
25859     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_INIT_RX_PRESET_HINT_EN_O_SHIFT                       0
25860     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_RECAL_RX_PRESET_HINT_EN_O                            (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
25861     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_RECAL_RX_PRESET_HINT_EN_O_SHIFT                      1
25862     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_UNUSED_0                                             (0x3f<<2) // reserved
25863     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X168_UNUSED_0_SHIFT                                       2
25864 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169                                                          0x001aa4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
25865     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169_TXEQ_RXRECAL_DONE_I_0                                (0x1<<0) // TX - RECAL RX Equalization status
25866     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169_TXEQ_RXRECAL_DONE_I_0_SHIFT                          0
25867     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169_UNUSED_0                                             (0x7f<<1) // reserved
25868     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X169_UNUSED_0_SHIFT                                       1
25869 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170                                                          0x001aa8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
25870     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170_BLOCK_DEC_ERR                                        (0x1<<0) // decoder sync header error
25871     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170_BLOCK_DEC_ERR_SHIFT                                  0
25872     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170_UNUSED_0                                             (0x7f<<1) // reserved
25873     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X170_UNUSED_0_SHIFT                                       1
25874 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201                                                          0x001b24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25875     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_EN_O_0                                          (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
25876     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_EN_O_0_SHIFT                                    0
25877     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_WORD_OV_O_1_0                                   (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
25878     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_WORD_OV_O_1_0_SHIFT                             1
25879     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_MODE_8B_OV_O_1_0                                (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
25880     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_MODE_8B_OV_O_1_0_SHIFT                          3
25881     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_RATE_OV_O_2_0                                   (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
25882     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X201_CDFE_RATE_OV_O_2_0_SHIFT                             5
25883 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X202                                                          0x001b28UL //Access:RW   DataWidth:0x8     Chips: K2
25884 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203                                                          0x001b2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25885     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_UNUSED_0                                             (0xf<<0) // reserved
25886     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_UNUSED_0_SHIFT                                       0
25887     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_GO                                              (0x1<<4) //
25888     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_GO_SHIFT                                        4
25889     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_FORCE_CAL                                    (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
25890     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_FORCE_CAL_SHIFT                              5
25891     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_RATE_CHANGE_CAL                              (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
25892     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_RATE_CHANGE_CAL_SHIFT                        6
25893     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_EI_EXIT_CAL                                  (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
25894     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X203_CDFE_LN_EI_EXIT_CAL_SHIFT                            7
25895 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204                                                          0x001b30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25896     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_CONT_CAL                                     (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
25897     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_CONT_CAL_SHIFT                               0
25898     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL                         (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
25899     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_SHIFT                   1
25900     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL                          (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
25901     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_SHIFT                    2
25902     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_CAL_EN                                 (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
25903     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE3_CAL_EN_SHIFT                           3
25904     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE2_CAL_EN                                 (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
25905     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_CDFE_LN_RATE2_CAL_EN_SHIFT                           4
25906     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_UNUSED_0                                             (0x7<<5) // reserved
25907     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X204_UNUSED_0_SHIFT                                       5
25908 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X205                                                          0x001b34UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
25909 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X206                                                          0x001b38UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
25910 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X207                                                          0x001b3cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
25911 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208                                                          0x001b40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25912     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_UNUSED_0                                             (0x7f<<0) // reserved
25913     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_UNUSED_0_SHIFT                                       0
25914     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_AHB_CDFE_COARSE_DLL_OV_EN                            (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
25915     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X208_AHB_CDFE_COARSE_DLL_OV_EN_SHIFT                      7
25916 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X213                                                          0x001b54UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
25917 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X214                                                          0x001b58UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
25918 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X215                                                          0x001b5cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
25919 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X216                                                          0x001b60UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
25920 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X217                                                          0x001b64UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
25921 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X220                                                          0x001b70UL //Access:RW   DataWidth:0x8   Start value for dlev_ref.  Chips: K2
25922 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X221                                                          0x001b74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25923     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0               (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
25924     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT         0
25925     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X221_UNUSED_0                                             (0x7<<5) // reserved
25926     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X221_UNUSED_0_SHIFT                                       5
25927 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X222                                                          0x001b78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25928     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0           (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
25929     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT     0
25930     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X222_UNUSED_0                                             (0x7<<5) // reserved
25931     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X222_UNUSED_0_SHIFT                                       5
25932 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X223                                                          0x001b7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25933     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X223_AHB_CDFE_CMP1_TAP1_OFFSET                            (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
25934     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X223_AHB_CDFE_CMP1_TAP1_OFFSET_SHIFT                      0
25935     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X223_UNUSED_0                                             (0x1<<7) // reserved
25936     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X223_UNUSED_0_SHIFT                                       7
25937 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X224                                                          0x001b80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25938     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
25939     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_SHIFT                  0
25940     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X224_UNUSED_0                                             (0x3<<6) // reserved
25941     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X224_UNUSED_0_SHIFT                                       6
25942 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X225                                                          0x001b84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25943     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
25944     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_SHIFT                  0
25945     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X225_UNUSED_0                                             (0x3<<6) // reserved
25946     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X225_UNUSED_0_SHIFT                                       6
25947 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X226                                                          0x001b88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25948     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
25949     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_SHIFT                  0
25950     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X226_UNUSED_0                                             (0x3<<6) // reserved
25951     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X226_UNUSED_0_SHIFT                                       6
25952 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X227                                                          0x001b8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25953     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X227_AHB_CDFE_CMP1_TAP5_OFFSET                            (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
25954     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X227_AHB_CDFE_CMP1_TAP5_OFFSET_SHIFT                      0
25955     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X227_UNUSED_0                                             (0x3<<6) // reserved
25956     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X227_UNUSED_0_SHIFT                                       6
25957 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X228                                                          0x001b90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25958     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X228_AHB_CDFE_CMP2_TAP1_OFFSET                            (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
25959     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X228_AHB_CDFE_CMP2_TAP1_OFFSET_SHIFT                      0
25960     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X228_UNUSED_0                                             (0x1<<7) // reserved
25961     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X228_UNUSED_0_SHIFT                                       7
25962 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X229                                                          0x001b94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25963     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
25964     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_SHIFT                  0
25965     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X229_UNUSED_0                                             (0x3<<6) // reserved
25966     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X229_UNUSED_0_SHIFT                                       6
25967 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X230                                                          0x001b98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25968     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
25969     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_SHIFT                  0
25970     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X230_UNUSED_0                                             (0x3<<6) // reserved
25971     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X230_UNUSED_0_SHIFT                                       6
25972 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X231                                                          0x001b9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25973     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
25974     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_SHIFT                  0
25975     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X231_UNUSED_0                                             (0x3<<6) // reserved
25976     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X231_UNUSED_0_SHIFT                                       6
25977 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X232                                                          0x001ba0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25978     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X232_AHB_CDFE_CMP2_TAP5_OFFSET                            (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
25979     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X232_AHB_CDFE_CMP2_TAP5_OFFSET_SHIFT                      0
25980     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X232_UNUSED_0                                             (0x3<<6) // reserved
25981     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X232_UNUSED_0_SHIFT                                       6
25982 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X233                                                          0x001ba4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25983     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X233_AHB_CDFE_CMP3_TAP1_OFFSET                            (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
25984     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X233_AHB_CDFE_CMP3_TAP1_OFFSET_SHIFT                      0
25985     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X233_UNUSED_0                                             (0x1<<7) // reserved
25986     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X233_UNUSED_0_SHIFT                                       7
25987 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X234                                                          0x001ba8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25988     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
25989     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_SHIFT                  0
25990     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X234_UNUSED_0                                             (0x3<<6) // reserved
25991     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X234_UNUSED_0_SHIFT                                       6
25992 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X235                                                          0x001bacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25993     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
25994     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_SHIFT                  0
25995     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X235_UNUSED_0                                             (0x3<<6) // reserved
25996     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X235_UNUSED_0_SHIFT                                       6
25997 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X236                                                          0x001bb0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
25998     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
25999     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_SHIFT                  0
26000     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X236_UNUSED_0                                             (0x3<<6) // reserved
26001     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X236_UNUSED_0_SHIFT                                       6
26002 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X237                                                          0x001bb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26003     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X237_AHB_CDFE_CMP3_TAP5_OFFSET                            (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
26004     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X237_AHB_CDFE_CMP3_TAP5_OFFSET_SHIFT                      0
26005     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X237_UNUSED_0                                             (0x3<<6) // reserved
26006     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X237_UNUSED_0_SHIFT                                       6
26007 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X238                                                          0x001bb8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26008     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X238_AHB_CDFE_CMP4_TAP1_OFFSET                            (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
26009     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X238_AHB_CDFE_CMP4_TAP1_OFFSET_SHIFT                      0
26010     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X238_UNUSED_0                                             (0x1<<7) // reserved
26011     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X238_UNUSED_0_SHIFT                                       7
26012 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X239                                                          0x001bbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26013     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
26014     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_SHIFT                  0
26015     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X239_UNUSED_0                                             (0x3<<6) // reserved
26016     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X239_UNUSED_0_SHIFT                                       6
26017 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X240                                                          0x001bc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26018     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
26019     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_SHIFT                  0
26020     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X240_UNUSED_0                                             (0x3<<6) // reserved
26021     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X240_UNUSED_0_SHIFT                                       6
26022 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X241                                                          0x001bc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26023     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
26024     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_SHIFT                  0
26025     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X241_UNUSED_0                                             (0x3<<6) // reserved
26026     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X241_UNUSED_0_SHIFT                                       6
26027 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X242                                                          0x001bc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26028     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X242_AHB_CDFE_CMP4_TAP5_OFFSET                            (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
26029     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X242_AHB_CDFE_CMP4_TAP5_OFFSET_SHIFT                      0
26030     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X242_UNUSED_0                                             (0x3<<6) // reserved
26031     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X242_UNUSED_0_SHIFT                                       6
26032 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X243                                                          0x001bccUL //Access:RW   DataWidth:0x8   Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]  Chips: K2
26033 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X244                                                          0x001bd0UL //Access:RW   DataWidth:0x8   Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]  Chips: K2
26034 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X245                                                          0x001bd4UL //Access:RW   DataWidth:0x8   Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]  Chips: K2
26035 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X246                                                          0x001bd8UL //Access:RW   DataWidth:0x8   Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]  Chips: K2
26036 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X247                                                          0x001bdcUL //Access:RW   DataWidth:0x8     Chips: K2
26037 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248                                                          0x001be0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26038     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_AHB_CDFE_DLL_FINE_MASK_9_8                           (0x3<<0) //
26039     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_AHB_CDFE_DLL_FINE_MASK_9_8_SHIFT                     0
26040     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT                         (0xf<<2) //
26041     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_SHIFT                   2
26042     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_UNUSED_0                                             (0x3<<6) // reserved
26043     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X248_UNUSED_0_SHIFT                                       6
26044 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249                                                          0x001be4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26045     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_ERR_SMPL_SHIFT                              (0xf<<0) //
26046     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_ERR_SMPL_SHIFT_SHIFT                        0
26047     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_FINE_DLL_OV_EN                              (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
26048     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_AHB_CDFE_FINE_DLL_OV_EN_SHIFT                        4
26049     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_UNUSED_0                                             (0x7<<5) // reserved
26050     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X249_UNUSED_0_SHIFT                                       5
26051 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250                                                          0x001be8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26052     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8                    (0x1<<0) //
26053     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_SHIFT              0
26054     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8                   (0x1<<1) //
26055     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_SHIFT             1
26056     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8                    (0x1<<2) //
26057     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_SHIFT              2
26058     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8                   (0x1<<3) //
26059     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_SHIFT             3
26060     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_UNUSED_0                                             (0xf<<4) // reserved
26061     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X250_UNUSED_0_SHIFT                                       4
26062 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X251                                                          0x001becUL //Access:RW   DataWidth:0x8     Chips: K2
26063 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X252                                                          0x001bf0UL //Access:RW   DataWidth:0x8     Chips: K2
26064 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X253                                                          0x001bf4UL //Access:RW   DataWidth:0x8     Chips: K2
26065 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X254                                                          0x001bf8UL //Access:RW   DataWidth:0x8     Chips: K2
26066 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255                                                          0x001bfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26067     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_EN                                       (0x1<<0) // Override enable for CDFE calibration direction
26068     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_EN_SHIFT                                 0
26069     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_VAL                                      (0x1<<1) // Override value for CDFE calibration direction
26070     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_CDFE_DIR_OV_VAL_SHIFT                                1
26071     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA270_OVR_EN_O                           (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
26072     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA270_OVR_EN_O_SHIFT                     2
26073     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA90_OVR_EN_O                            (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
26074     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_ENA90_OVR_EN_O_SHIFT                      3
26075     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_PHD_ENA_OVR_EN_O                              (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
26076     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_PHD_ENA_OVR_EN_O_SHIFT                        4
26077     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_DLY_OVR_EN_O                              (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
26078     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_DLY_OVR_EN_O_SHIFT                        5
26079     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O                          (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
26080     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_SHIFT                    6
26081     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_UNUSED_0                                             (0x1<<7) // reserved
26082     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X255_UNUSED_0_SHIFT                                       7
26083 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X256                                                          0x001c00UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK90.  Chips: K2
26084 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257                                                          0x001c04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26085     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8                       (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
26086     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_SHIFT                 0
26087     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0               (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
26088     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_SHIFT         1
26089 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X258                                                          0x001c08UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK270.  Chips: K2
26090 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259                                                          0x001c0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26091     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8                      (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
26092     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_SHIFT                0
26093     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_DLEV_OV_EN                                  (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
26094     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_AHB_CDFE_DLEV_OV_EN_SHIFT                            1
26095     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0                    (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
26096     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_SHIFT              2
26097     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8               (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
26098     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_SHIFT         7
26099 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X260                                                          0x001c10UL //Access:RW   DataWidth:0x8   Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value  Chips: K2
26100 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X261                                                          0x001c14UL //Access:RW   DataWidth:0x8   cdfe dlevn overwrite value.  Chips: K2
26101 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X262                                                          0x001c18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26102     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X262_AHB_CDFE_TAP_OV_EN                                   (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
26103     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X262_AHB_CDFE_TAP_OV_EN_SHIFT                             0
26104     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X262_UNUSED_0                                             (0x7<<5) // reserved
26105     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X262_UNUSED_0_SHIFT                                       5
26106 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X263                                                          0x001c1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26107     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X263_AHB_CDFE_TAP1_OV                                     (0x7f<<0) // cdfe tap1 overwrite value
26108     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X263_AHB_CDFE_TAP1_OV_SHIFT                               0
26109     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X263_UNUSED_0                                             (0x1<<7) // reserved
26110     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X263_UNUSED_0_SHIFT                                       7
26111 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X264                                                          0x001c20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26112     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X264_AHB_CDFE_TAP2_OV                                     (0x3f<<0) // cdfe tap2 overwrite value
26113     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X264_AHB_CDFE_TAP2_OV_SHIFT                               0
26114     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X264_UNUSED_0                                             (0x3<<6) // reserved
26115     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X264_UNUSED_0_SHIFT                                       6
26116 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X265                                                          0x001c24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26117     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X265_AHB_CDFE_TAP3_OV                                     (0x3f<<0) // cdfe tap3 overwrite value
26118     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X265_AHB_CDFE_TAP3_OV_SHIFT                               0
26119     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X265_UNUSED_0                                             (0x3<<6) // reserved
26120     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X265_UNUSED_0_SHIFT                                       6
26121 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X266                                                          0x001c28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26122     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X266_AHB_CDFE_TAP4_OV                                     (0x3f<<0) // cdfe tap4 overwrite value
26123     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X266_AHB_CDFE_TAP4_OV_SHIFT                               0
26124     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X266_UNUSED_0                                             (0x3<<6) // reserved
26125     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X266_UNUSED_0_SHIFT                                       6
26126 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267                                                          0x001c2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26127     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_AHB_CDFE_TAP5_OV                                     (0x3f<<0) // cdfe tap5 overwrite value
26128     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_AHB_CDFE_TAP5_OV_SHIFT                               0
26129     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_UNUSED_0                                             (0x1<<6) // reserved
26130     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_UNUSED_0_SHIFT                                       6
26131     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O               (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
26132     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_SHIFT         7
26133 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268                                                          0x001c30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26134     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O                       (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
26135     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_SHIFT                 0
26136     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O             (0x1<<1) //
26137     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_SHIFT       1
26138     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O         (0x1<<2) //
26139     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_SHIFT   2
26140     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_UNUSED_0                                             (0xf<<3) // reserved
26141     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_UNUSED_0_SHIFT                                       3
26142     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_AHB_CDFE_DFE_VAL_OVR_EN_O                            (0x1<<7) //
26143     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_SHIFT                      7
26144 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269                                                          0x001c34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26145     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O                     (0x1<<0) //
26146     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_SHIFT               0
26147     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_STROBE_EN_O                                 (0x1<<1) //
26148     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_STROBE_EN_O_SHIFT                           1
26149     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_CMP_ENA_O                                   (0xf<<2) //
26150     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_AHB_CDFE_CMP_ENA_O_SHIFT                             2
26151     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_UNUSED_0                                             (0x3<<6) // reserved
26152     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X269_UNUSED_0_SHIFT                                       6
26153 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X270                                                          0x001c38UL //Access:RW   DataWidth:0x8     Chips: K2
26154 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271                                                          0x001c3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26155     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0                          (0x1f<<0) //
26156     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_SHIFT                    0
26157     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O                  (0x1<<5) // Forces the positive dlev training pattern to be used
26158     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_SHIFT            5
26159     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O                  (0x1<<6) // Forces the negative dlev training pattern to be used
26160     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_SHIFT            6
26161     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_UNUSED_0                                             (0x1<<7) // reserved
26162     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X271_UNUSED_0_SHIFT                                       7
26163 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272                                                          0x001c40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26164     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP1 adapted value
26165     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SCALE_O_2_0_SHIFT                          0
26166     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP1 adapted value
26167     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X272_CDFE_TAP1_SHIFT_O_4_0_SHIFT                          3
26168 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273                                                          0x001c44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26169     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP2 adapted value
26170     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SCALE_O_2_0_SHIFT                          0
26171     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP2 adapted value
26172     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X273_CDFE_TAP2_SHIFT_O_4_0_SHIFT                          3
26173 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274                                                          0x001c48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26174     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP3 adapted value
26175     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SCALE_O_2_0_SHIFT                          0
26176     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP3 adapted value
26177     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X274_CDFE_TAP3_SHIFT_O_4_0_SHIFT                          3
26178 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275                                                          0x001c4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26179     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP4 adapted value
26180     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SCALE_O_2_0_SHIFT                          0
26181     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP4 adapted value
26182     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X275_CDFE_TAP4_SHIFT_O_4_0_SHIFT                          3
26183 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276                                                          0x001c50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26184     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP5 adapted value
26185     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SCALE_O_2_0_SHIFT                          0
26186     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP5 adapted value
26187     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X276_CDFE_TAP5_SHIFT_O_4_0_SHIFT                          3
26188 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277                                                          0x001c54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26189     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_RA_OVR_O                                (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
26190     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_RA_OVR_O_SHIFT                          0
26191     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_P2S_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
26192     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_P2S_OVR_O_SHIFT                         2
26193     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_LNREGH_OVR_O                            (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
26194     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_LNREGH_OVR_O_SHIFT                      4
26195     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_LNREG_OVR_O                             (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
26196     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X277_LN_MSM_RESET_LNREG_OVR_O_SHIFT                       6
26197 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278                                                          0x001c58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26198     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_RESET_CDR_OVR_O                               (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
26199     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_RESET_CDR_OVR_O_SHIFT                         0
26200     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_RESET_DFE_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
26201     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_RESET_DFE_OVR_O_SHIFT                         2
26202     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_PD_LNREGH_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
26203     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_PD_LNREGH_OVR_O_SHIFT                         4
26204     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_PD_VCO_BUF_OVR_O                              (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
26205     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X278_LN_MSM_PD_VCO_BUF_OVR_O_SHIFT                        6
26206 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279                                                          0x001c5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26207     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RESET_CDR_GCRX_OVR_O                          (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
26208     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_SHIFT                    0
26209     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RXGATE_EN_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
26210     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RXGATE_EN_OVR_O_SHIFT                         2
26211     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RESET_VCO_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
26212     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_RESET_VCO_OVR_O_SHIFT                         4
26213     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_IDDQ_SD_OVR_O                                 (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
26214     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X279_LN_MSM_IDDQ_SD_OVR_O_SHIFT                           6
26215 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280                                                          0x001c60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26216     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_PD_DFE_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
26217     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_PD_DFE_OVR_O_SHIFT                            0
26218     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_PD_DFE_BIAS_OVR_O                             (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
26219     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_PD_DFE_BIAS_OVR_O_SHIFT                       2
26220     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O                           (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
26221     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_SHIFT                     4
26222     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O                         (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
26223     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_SHIFT                   6
26224 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281                                                          0x001c64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26225     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_TXREG_OVR_O                                (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
26226     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_TXREG_OVR_O_SHIFT                          0
26227     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_LNREG_OVR_O                                (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
26228     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_LNREG_OVR_O_SHIFT                          2
26229     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_P2S_OVR_O                                  (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
26230     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_P2S_OVR_O_SHIFT                            4
26231     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_RA_OVR_O                                   (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
26232     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X281_LN_MSM_PD_RA_OVR_O_SHIFT                             6
26233 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282                                                          0x001c68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26234     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_UNUSED_0                                             (0x3<<0) // reserved
26235     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_UNUSED_0_SHIFT                                       0
26236     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_SLV_BIAS_OVR_O                             (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
26237     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_SLV_BIAS_OVR_O_SHIFT                       2
26238     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_TXDRV_OVR_O                                (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
26239     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_TXDRV_OVR_O_SHIFT                          4
26240     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_VCO_OVR_O                                  (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
26241     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X282_LN_MSM_PD_VCO_OVR_O_SHIFT                            6
26242 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283                                                          0x001c6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26243     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_CDR_EN_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
26244     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_CDR_EN_OVR_O_SHIFT                            0
26245     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_RESET_S2P_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
26246     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_RESET_S2P_OVR_O_SHIFT                         2
26247     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_RXCLK_EN_OVR_O                                (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
26248     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_RXCLK_EN_OVR_O_SHIFT                          4
26249     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_WORD_OVR_O                                    (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
26250     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X283_LN_MSM_WORD_OVR_O_SHIFT                              6
26251 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284                                                          0x001c70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26252     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RATE_OVR_O                                    (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
26253     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RATE_OVR_O_SHIFT                              0
26254     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RXVCODIV_OVR_O                                (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
26255     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RXVCODIV_OVR_O_SHIFT                          3
26256     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O                         (0x3<<6) // Not currently used
26257     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_SHIFT                   6
26258 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X285                                                          0x001c74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26259     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X285_LN_MSM_TXVCODIV_OVR_O                                (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
26260     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X285_LN_MSM_TXVCODIV_OVR_O_SHIFT                          0
26261     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X285_UNUSED_0                                             (0x1f<<3) // reserved
26262     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X285_UNUSED_0_SHIFT                                       3
26263 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301                                                          0x001cb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26264     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_RX_SRC_O                                             (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
26265     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_RX_SRC_O_SHIFT                                       0
26266     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_POL_O                                          (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
26267     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_POL_O_SHIFT                                    1
26268     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_BIT_O                                          (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
26269     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_BIT_O_SHIFT                                    2
26270     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_WORD_O                                         (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
26271     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_TREG0_WORD_O_SHIFT                                   3
26272     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_DMUX_TXA_SEL_O_1_0                                   (0x3<<4) // Transmit mux A data input select.
26273     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_DMUX_TXA_SEL_O_1_0_SHIFT                             4
26274     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_P2S_RBUF_AUTOFIX_O                                   (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
26275     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_P2S_RBUF_AUTOFIX_O_SHIFT                             6
26276     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_UNUSED_0                                             (0x1<<7) // reserved
26277     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X301_UNUSED_0_SHIFT                                       7
26278 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302                                                          0x001cb8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26279     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_POL_O                                          (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
26280     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_POL_O_SHIFT                                    0
26281     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_BIT_O                                          (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
26282     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_BIT_O_SHIFT                                    1
26283     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_WORD_O                                         (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
26284     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_TREG1_WORD_O_SHIFT                                   2
26285     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_POL_O                                           (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
26286     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_POL_O_SHIFT                                     3
26287     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_BIT_O                                           (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
26288     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_BIT_O_SHIFT                                     4
26289     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_WORD_O                                          (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
26290     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG1_WORD_O_SHIFT                                    5
26291     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG0_POL_O                                           (0x1<<6) // Used as Reg0 polarity select
26292     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_REG0_POL_O_SHIFT                                     6
26293     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_UNUSED_0                                             (0x1<<7) // reserved
26294     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X302_UNUSED_0_SHIFT                                       7
26295 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303                                                          0x001cbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26296     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_BIT_O                                           (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
26297     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_BIT_O_SHIFT                                     0
26298     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_WORD_O                                          (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
26299     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_REG0_WORD_O_SHIFT                                    1
26300     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_DMUX_TXB_SEL_O_2_0                                   (0x7<<2) // Transmit mux B data input select enable.
26301     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_DMUX_TXB_SEL_O_2_0_SHIFT                             2
26302     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TX_CTRL_O_24                                         (0x1<<5) // Bit 24: txdrv_c2_in[3]
26303     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TX_CTRL_O_24_SHIFT                                   5
26304     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_WIDTH_CHNG_EN_O                                      (0x1<<6) // Enable bit for width_chng module
26305     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_WIDTH_CHNG_EN_O_SHIFT                                6
26306     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TXTERM_CAL_SEQ_EN_O                                  (0x1<<7) // Txterm calibration enable
26307     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X303_TXTERM_CAL_SEQ_EN_O_SHIFT                            7
26308 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304                                                          0x001cc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26309     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_TXTERM_CAL_RSEL                                      (0x7<<0) // tx termination calibration comparator threshold select
26310     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_TXTERM_CAL_RSEL_SHIFT                                0
26311     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_LN_RXBIT_STRIP_O                                 (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2?b00: no bit stripping 2?b01: 2x bit stripping 2?b10: reserved 2?b11: 4x bit stripping
26312     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_LN_RXBIT_STRIP_O_SHIFT                           3
26313     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_MAC_WIDTH_O                                      (0x3<<5) // Data width selector for PCS/MAC interface. 2?b00: GigE or XAUI 2?b01: GigE or XAUI 2?b10: RXAUI 2?b11: XFI
26314     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_AHB_MAC_WIDTH_O_SHIFT                                5
26315     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_UNUSED_0                                             (0x1<<7) // reserved
26316     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X304_UNUSED_0_SHIFT                                       7
26317 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305                                                          0x001cc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26318     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_AHB_TXMAC_THRESHOLD_O                                (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
26319     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_AHB_TXMAC_THRESHOLD_O_SHIFT                          0
26320     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_AHB_LN_TXBIT_REPEAT_O                                (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2?b00: no bit stuffing nor stripping 2?b01: 2x bit stuffing and stripping 2?b10: reserved 2?b11: 4x bit stuffing and stripping
26321     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_AHB_LN_TXBIT_REPEAT_O_SHIFT                          2
26322     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_MODE_8B_O_1_0                                        (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
26323     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_MODE_8B_O_1_0_SHIFT                                  4
26324     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_ENC_EN_O                                             (0x1<<6) // 8b/10b encoder enable.
26325     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_ENC_EN_O_SHIFT                                       6
26326     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_DEC_EN_O                                             (0x1<<7) // 8b/10b decoder enable.
26327     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X305_DEC_EN_O_SHIFT                                       7
26328 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306                                                          0x001cc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26329     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_AHB_TX_CDAC_OVR                                      (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
26330     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_AHB_TX_CDAC_OVR_SHIFT                                0
26331     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_LN_COMMON_SYNC_TXCLK_EN_O                            (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
26332     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_LN_COMMON_SYNC_TXCLK_EN_O_SHIFT                      4
26333     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_UNUSED_0                                             (0x7<<5) // reserved
26334     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X306_UNUSED_0_SHIFT                                       5
26335 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307                                                          0x001cccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26336     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_LN_TO_CLK_TXB_WAIT_O                                 (0x1f<<0) // In per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA. The lnX_ok_o will get asserted after lnX_to_clk_txb_wait_o lnX_ck_txb_o cycles.
26337     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_LN_TO_CLK_TXB_WAIT_O_SHIFT                           0
26338     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_PIPE_EN_O                                            (0x1<<5) // PIPE interface block enable.
26339     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_PIPE_EN_O_SHIFT                                      5
26340     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_SAPIS_EN_O                                           (0x1<<6) // SAPIS interface block enable.
26341     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_SAPIS_EN_O_SHIFT                                     6
26342     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_USB_MODE                                             (0x1<<7) // Signal Detect USB mode enable
26343     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X307_USB_MODE_SHIFT                                       7
26344 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308                                                          0x001cd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26345     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_UNUSED_0                                             (0x1<<0) // reserved
26346     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_UNUSED_0_SHIFT                                       0
26347     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_ENC_CLR_ERR_O                                  (0x1<<1) // 128b/130b encoder clear error
26348     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_ENC_CLR_ERR_O_SHIFT                            1
26349     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_UNUSED_1                                             (0x1<<2) // reserved
26350     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_UNUSED_1_SHIFT                                       2
26351     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_EN_ERR_CHK_O                               (0x1<<3) // 130b/128b error check enable
26352     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_EN_ERR_CHK_O_SHIFT                         3
26353     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0                          (0x7<<4) // 130b/128b: number of OS indicating end of data
26354     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_SHIFT                    4
26355     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CLR_ERR_O                                  (0x1<<7) // 130b/128b: clear error flag
26356     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X308_BLOCK_DEC_CLR_ERR_O_SHIFT                            7
26357 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309                                                          0x001cd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26358     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0                        (0xf<<0) // 130b/128b: number of sync hdr errors before asserting sync error flag
26359     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_SHIFT                  0
26360     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0                         (0xf<<4) // 130b/128b: number of continuous blocks checked
26361     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_SHIFT                   4
26362 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310                                                          0x001cd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26363     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_RSTN_O                                          (0x1<<0) // Synchronous clear for elastic buffer
26364     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_RSTN_O_SHIFT                                    0
26365     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_ALIGN_RSTN_O                                         (0x1<<1) // Synchronous clear for block/symbol aligner
26366     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_ALIGN_RSTN_O_SHIFT                                   1
26367     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_SKP_ADD_EN_O                                    (0x1<<2) // Elastic buffer SKP add enable
26368     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EBUF_SKP_ADD_EN_O_SHIFT                              2
26369     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_RBUF_RSTN_O                                          (0x1<<3) // TX FIFO synchronous reset
26370     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_RBUF_RSTN_O_SHIFT                                    3
26371     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_UNUSED_0                                             (0x1<<4) // reserved
26372     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_UNUSED_0_SHIFT                                       4
26373     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EN_SKPOS_ERR_O                                       (0x1<<5) // Enables skpos error status propagation in Gen3
26374     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_EN_SKPOS_ERR_O_SHIFT                                 5
26375     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_UNUSED_1                                             (0x3<<6) // reserved
26376     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X310_UNUSED_1_SHIFT                                       6
26377 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311                                                          0x001cdcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26378     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_PIPE_LFREQ                                           (0x3f<<0) // LF value for full swing
26379     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_PIPE_LFREQ_SHIFT                                     0
26380     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_BLOCK_ALIGN_CTRL_O                               (0x1<<6) // Disables the primary input lnX_block_align_control
26381     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_BLOCK_ALIGN_CTRL_O_SHIFT                         6
26382     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_EIEOS_CHK_IN_LB_O                                (0x1<<7) // Disables the EIEOS check in loopback
26383     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X311_DIS_EIEOS_CHK_IN_LB_O_SHIFT                          7
26384 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312                                                          0x001ce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26385     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_COEF_FE_LIMIT_EN_O                                   (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
26386     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_COEF_FE_LIMIT_EN_O_SHIFT                             0
26387     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_RXVALID_DIS_AT_RATE_CHG_O_0                          (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
26388     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_RXVALID_DIS_AT_RATE_CHG_O_0_SHIFT                    1
26389     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_P2S_RBUF_BUF_THRESH_O_3_0                            (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted
26390     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_P2S_RBUF_BUF_THRESH_O_3_0_SHIFT                      2
26391     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_UNUSED_0                                             (0x3<<6) // reserved
26392     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X312_UNUSED_0_SHIFT                                       6
26393 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313                                                          0x001ce4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26394     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_RX_GEARBOX_DISABLE_O                             (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
26395     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_RX_GEARBOX_DISABLE_O_SHIFT                       0
26396     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_TX_GEARBOX_DISABLE_O                             (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
26397     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_AHB_TX_GEARBOX_DISABLE_O_SHIFT                       1
26398     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_UNUSED_0                                             (0x3f<<2) // reserved
26399     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X313_UNUSED_0_SHIFT                                       2
26400 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314                                                          0x001ce8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26401     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_GEN1_OLD_RXDATA_SRC                                  (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
26402     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_GEN1_OLD_RXDATA_SRC_SHIFT                            0
26403     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN3_O                                      (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
26404     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN3_O_SHIFT                                1
26405     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN12_O                                     (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
26406     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_SKIP_CDR_GEN12_O_SHIFT                               2
26407     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_AHB_LN_PD_RA_CISEL_OVR_O_0                           (0x1<<3) // Receive amplifier powerdown override, when cisel is high
26408     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_SHIFT                     3
26409     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_LN_P2S_RBUF_REALIGN_DIFF_O                           (0xf<<4) // In per lane common synchronous clock mode, ln_p2x_rbuf_realign_diff_o defines the starting difference between write pointer and read pointer when re aligning the pointer of TxFIFO.
26410     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X314_LN_P2S_RBUF_REALIGN_DIFF_O_SHIFT                     4
26411 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X315                                                          0x001cecUL //Access:RW   DataWidth:0x8   Delays the beacon_ena propagation to PMA  Chips: K2
26412 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X316                                                          0x001cf0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26413     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O               (0xf<<0) // Delays the beacon_ena propagation to PMA
26414     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_SHIFT         0
26415     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X316_UNUSED_0                                             (0xf<<4) // reserved
26416     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X316_UNUSED_0_SHIFT                                       4
26417 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317                                                          0x001cf4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26418     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_ENA_O                             (0x1<<0) // Beacon Override Enable
26419     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_ENA_O_SHIFT                       0
26420     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_O                                 (0x1<<1) // Beacon Override
26421     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_AHB_BEACON_ENA_OVR_O_SHIFT                           1
26422     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_DEC_EN_OVR_O                                         (0x1<<2) // Enables 16b/20b decoder
26423     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_DEC_EN_OVR_O_SHIFT                                   2
26424     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_ENC_EN_OVR_O                                         (0x1<<3) // Enables 16b/20b encoder
26425     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_ENC_EN_OVR_O_SHIFT                                   3
26426     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_REGP_OVR_3_0                                         (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
26427     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X317_REGP_OVR_3_0_SHIFT                                   4
26428 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318                                                          0x001cf8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26429     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_SIGDET_OVR_O_1_0                                     (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
26430     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_SIGDET_OVR_O_1_0_SHIFT                               0
26431     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_LN_OUT_OVR_1_0                                       (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
26432     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_LN_OUT_OVR_1_0_SHIFT                                 2
26433     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_RXEQ_SIGDET_1_0                                      (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
26434     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_RXEQ_SIGDET_1_0_SHIFT                                4
26435     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_UNUSED_0                                             (0x3<<6) // reserved
26436     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X318_UNUSED_0_SHIFT                                       6
26437 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319                                                          0x001cfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26438     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_TXDETECTRX_OVR_O_1_0                                 (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
26439     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_TXDETECTRX_OVR_O_1_0_SHIFT                           0
26440     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_RXDET_STATUS_OVR_O_1_0                               (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
26441     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_RXDET_STATUS_OVR_O_1_0_SHIFT                         2
26442     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_LOCKED_OVR_O_1_0                                     (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
26443     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_LOCKED_OVR_O_1_0_SHIFT                               4
26444     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O                     (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
26445     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_SHIFT               6
26446     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O                         (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
26447     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_SHIFT                   7
26448 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X320                                                          0x001d00UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
26449 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X321                                                          0x001d04UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
26450 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X322                                                          0x001d08UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
26451 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X323                                                          0x001d0cUL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
26452 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X324                                                          0x001d10UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
26453 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X325                                                          0x001d14UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
26454 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326                                                          0x001d18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26455     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_48                                       (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
26456     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_48_SHIFT                                 0
26457     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_AHB_LN_IN_OVR_CHG_FLAG_O                             (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
26458     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_AHB_LN_IN_OVR_CHG_FLAG_O_SHIFT                       1
26459     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_REGP1_OVR_O_3_0                                      (0xf<<2) // Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
26460     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_REGP1_OVR_O_3_0_SHIFT                                2
26461     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_OOB_DET_EN                                           (0x1<<6) // OOB detect enable
26462     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_OOB_DET_EN_SHIFT                                     6
26463     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_49                                       (0x1<<7) // OOB detect enable
26464     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X326_LN_IN_OVR_O_49_SHIFT                                 7
26465 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X327                                                          0x001d1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26466     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X327_CDR_CTRL_DLY_DLPF_EN_O                               (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
26467     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X327_CDR_CTRL_DLY_DLPF_EN_O_SHIFT                         0
26468     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X327_UNUSED_0                                             (0x7<<5) // reserved
26469     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X327_UNUSED_0_SHIFT                                       5
26470 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330                                                          0x001d28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26471     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0                     (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
26472     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_SHIFT               0
26473     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_LN_IN_OVR_O_50                                       (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
26474     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_LN_IN_OVR_O_50_SHIFT                                 3
26475     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_UNUSED_0                                             (0xf<<4) // reserved
26476     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_3_X330_UNUSED_0_SHIFT                                       4
26477 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0                                                            0x002000UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26478     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_UNUSED_0                                               (0x7f<<0) // reserved
26479     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_UNUSED_0_SHIFT                                         0
26480     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O                             (0x1<<7) // Clock divider for TX path branch 2 : 0-No division, 1- Divide by 2
26481     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X0_AHB_TX_CLK_BRCH2_DIV_SEL_O_SHIFT                       7
26482 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1                                                            0x002004UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26483     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_UNUSED_0                                               (0x7<<0) // reserved
26484     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_UNUSED_0_SHIFT                                         0
26485     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O                             (0x1<<3) // Clock divider for RX path branch 1 : 0-No division, 1- Divide by 2
26486     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH1_DIV_SEL_O_SHIFT                       3
26487     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_UNUSED_1                                               (0x7<<4) // reserved
26488     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_UNUSED_1_SHIFT                                         4
26489     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O                             (0x1<<7) // Clock divider for RX path branch 2 : 0-No division, 1- Divide by 2
26490     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X1_AHB_RX_CLK_BRCH2_DIV_SEL_O_SHIFT                       7
26491 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2                                                            0x002008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26492     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_UNUSED_0                                               (0x7f<<0) // reserved
26493     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_UNUSED_0_SHIFT                                         0
26494     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O                             (0x1<<7) // Clock divider for RX path branch 4 : 0-No division, 1- Divide by 2
26495     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X2_AHB_RX_CLK_BRCH4_DIV_SEL_O_SHIFT                       7
26496 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3                                                            0x00200cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26497     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_CMU_SEL_O_0                                        (0x1<<0) // CMU Select for lane  0 -	 Select CMU0  1 -	 Select CMU1
26498     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_CMU_SEL_O_0_SHIFT                                  0
26499     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_TXCLK_SEL_O_1                                      (0x1<<1) // PMA TX Clock Select for TX CDR VCO  0 -	 CMU0 Clock  1 -	 CMU1 Clock
26500     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_PMA_TXCLK_SEL_O_1_SHIFT                                1
26501     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_UNUSED_0                                               (0x3f<<2) // reserved
26502     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X3_UNUSED_0_SHIFT                                         2
26503 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4                                                            0x002010UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26504     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_CDRCTRL_DIV_EN_O_1_0                                   (0x3<<0) // 0 - Divide by 1 1/2 - Divide by 2 3 - Divide by 4
26505     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_CDRCTRL_DIV_EN_O_1_0_SHIFT                             0
26506     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_GCFSM_DIV_EN_O_1_0                                     (0x3<<2) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
26507     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_GCFSM_DIV_EN_O_1_0_SHIFT                               2
26508     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_LN_CLK_TXB_DIV24OR1_O                                  (0x3<<4) // Divide ratio setting for lnX_ck_txb_o. When ln_common_sync_txclk_en_o is high and in NORM state:                                            2'b00: lnX_ck_txb_o is divided by 1 version of the tx byte clock from PMA.                     2'b01/2'b10: lnX_ck_txb_o is divided by 2 version of the tx byte clock from PMA.                  2'b11: lnX_ck_txb_o is divided by 4 version of the tx byte clock from PMA.
26509     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_LN_CLK_TXB_DIV24OR1_O_SHIFT                            4
26510     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_AHB_CHNG_REQ_Z_O                                       (0x1<<6) // Not currently used
26511     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_AHB_CHNG_REQ_Z_O_SHIFT                                 6
26512     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_UNUSED_0                                               (0x1<<7) // reserved
26513     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X4_UNUSED_0_SHIFT                                         7
26514 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5                                                            0x002014UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26515     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_REF_CLK_DIV_EN_O_1_0                                   (0x3<<0) // Clock divider for ref clock going to lane_top : 0-No division, 1- Divide by 2
26516     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_REF_CLK_DIV_EN_O_1_0_SHIFT                             0
26517     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_OOB_CLK_DIV_EN_O_1_0                                   (0x3<<2) // Clock divider for ref clock going to oob_detection module : 0-No division, 1- Divide by 2
26518     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_OOB_CLK_DIV_EN_O_1_0_SHIFT                             2
26519     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_UNUSED_0                                               (0xf<<4) // reserved
26520     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X5_UNUSED_0_SHIFT                                         4
26521 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7                                                            0x00201cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26522     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_RATE_O                                            (0x3<<0) // Rate control for BIST
26523     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_RATE_O_SHIFT                                      0
26524     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_MODE8B_O                                      (0x1<<2) // Bist generator 8b mode control 0 - Generated data word is 10 bits 1 - Generated data word is 8 bits
26525     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_MODE8B_O_SHIFT                                2
26526     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_ERR_O                                         (0x1<<3) // Bist generator error insert enable. 0 - BIST generator outputs normal pattern. 1 - BIST generator outputs erroneous pattern.
26527     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_ERR_O_SHIFT                                   3
26528     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_TX_CLOCK_ENABLE                                   (0x1<<4) // Active HIGH clock enable signal for the BIST transmit clock
26529     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_TX_CLOCK_ENABLE_SHIFT                             4
26530     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_CDN_O                                         (0x1<<5) // Bist generator master reset.
26531     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_CDN_O_SHIFT                                   5
26532     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_WORD_O                                        (0x1<<6) // Bist generator word enable. 0 - Bist generator generates single word 8 or 10 1 - Bist generator generates double word 16 or 20
26533     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_WORD_O_SHIFT                                  6
26534     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_EN_O                                          (0x1<<7) // Bist generator enable.  0 - Bist generator idle. 1 - Bist generator generates data
26535     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X7_BIST_GEN_EN_O_SHIFT                                    7
26536 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8                                                            0x002020UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26537     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_CLK_SEL_O_2_0                                 (0x7<<0) // BIST Generation Clock Selection
26538     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_CLK_SEL_O_2_0_SHIFT                           0
26539     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_SEND_PREAM_O                                  (0x1<<3) // Bist generator preamble send. Valid only if generator enabled. 0 - Bist generator sends normal data. 1 - Bist generator sends preamble.
26540     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_SEND_PREAM_O_SHIFT                            3
26541     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_INSERT_COUNT_O_2_0                            (0x7<<4) // Bist generator - Number of bist_chk_insert_word_i words to insert at a time. If 0, no word is ever inserted into the stream. In 20-bit mode, the product of bist_gen_insert_length x bist_gen_insert_count must be even.
26542     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_BIST_GEN_INSERT_COUNT_O_2_0_SHIFT                      4
26543     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_UNUSED_0                                               (0x1<<7) // reserved
26544     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X8_UNUSED_0_SHIFT                                         7
26545 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X9                                                            0x002024UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
26546 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X10                                                           0x002028UL //Access:RW   DataWidth:0x8   Bist generator low-period control. If not 0, output data enable will be low for this number of words, and then high for en_high_i_X:0 number of words, repeating. If 0, data output enable will be asserted for entire test.  Chips: K2
26547 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X11                                                           0x00202cUL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
26548 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X12                                                           0x002030UL //Access:RW   DataWidth:0x8   Bist generator high-period control. Refer to bist_gen_en_low_o and BIST documentation for further information.  Chips: K2
26549 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X13                                                           0x002034UL //Access:RW   DataWidth:0x8   Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.  Chips: K2
26550 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14                                                           0x002038UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26551     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BIST_GEN_INSERT_DELAY_O_11_8                          (0xf<<0) // Bist generator - Number of words between insert word insertions. Insertions are done in both pream and data transmission. In 20-bit mode, this number must be even.
26552     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BIST_GEN_INSERT_DELAY_O_11_8_SHIFT                    0
26553     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_UNUSED_0                                              (0x1<<4) // reserved
26554     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_UNUSED_0_SHIFT                                        4
26555     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_EN_O                                             (0x1<<5) // BIST checker enable Enables BIST RX Control block, which enables the actual BIST RX block when appropriate
26556     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_EN_O_SHIFT                                       5
26557     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_CLR_O                                            (0x1<<6) // BIST checker clear signal. Zeroes error counter output. Does NOT go through the RX BIST control block
26558     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_BCHK_CLR_O_SHIFT                                      6
26559     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_UNUSED_1                                              (0x1<<7) // reserved
26560     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X14_UNUSED_1_SHIFT                                        7
26561 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15                                                           0x00203cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26562     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BCHK_SRC_O_1_0                                        (0x3<<0) // BIST checker source. 0 - BIST uses output of initial RX polbit before Symbol Aligner 1 - BIST uses output of Symbol Aligner before Elastic Buffer 2 - BIST uses output of RX loopback mux before Decoder and Polbits 3 - BIST uses output of reg1 flop bank before Interface blocks
26563     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BCHK_SRC_O_1_0_SHIFT                                  0
26564     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_UNUSED_0                                              (0x1<<2) // reserved
26565     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_UNUSED_0_SHIFT                                        2
26566     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_DATA_MODE_O                                  (0x1<<3) // Bist checker mode select. 0X0 ? UDP pattern. 0x1 ? PRBS pattern
26567     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_DATA_MODE_O_SHIFT                            3
26568     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_LFSR_LENGTH_O_1_0                            (0x3<<4) // BIST PRBS pattern selector.
26569     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_CHK_LFSR_LENGTH_O_1_0_SHIFT                      4
26570     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_UNUSED_1                                              (0x1<<6) // reserved
26571     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_UNUSED_1_SHIFT                                        6
26572     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_RX_CLOCK_ENABLE                                  (0x1<<7) // Active HIGH clock enable signal for the BIST receive clock
26573     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X15_BIST_RX_CLOCK_ENABLE_SHIFT                            7
26574 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X16                                                           0x002040UL //Access:RW   DataWidth:0x8   Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.  Chips: K2
26575 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17                                                           0x002044UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26576     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_PREAM0_O_9_8                                 (0x3<<0) // Bist checker preamble word 0. When in 8b mode, and prior to the 8b/10b encoder, bit 8 is expected to be the K indicator. This word should correspond to the alignment character used for the symbol alignment block.
26577     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_PREAM0_O_9_8_SHIFT                           0
26578     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_INSERT_LENGTH_O_2_0                          (0x7<<2) // BIST Checker Insert word length.
26579     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_INSERT_LENGTH_O_2_0_SHIFT                    2
26580     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_SYNC_ON_ZEROS                                (0x1<<5) // Setting this bit allows BIST to sync to RX value of zero
26581     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_BIST_CHK_SYNC_ON_ZEROS_SHIFT                          5
26582     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_UNUSED_0                                              (0x3<<6) // reserved
26583     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X17_UNUSED_0_SHIFT                                        6
26584 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X18                                                           0x002048UL //Access:RW   DataWidth:0x8   BIST Check Preamble  Chips: K2
26585 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X19                                                           0x00204cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26586     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X19_BIST_CHK_PREAM1_O_9_8                                 (0x3<<0) // BIST Check Preamble
26587     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X19_BIST_CHK_PREAM1_O_9_8_SHIFT                           0
26588     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X19_UNUSED_0                                              (0x3f<<2) // reserved
26589     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X19_UNUSED_0_SHIFT                                        2
26590 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X20                                                           0x002050UL //Access:RW   DataWidth:0x8   Bist checker 40-bit user defined data pattern. In 10-bit mode, corresponds to 4 10-bit words. In 8-bit mode, corresponds to 5 8-bit words. K code is assumed to be 0 in 8-bit mode.  Chips: K2
26591 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X21                                                           0x002054UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
26592 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X22                                                           0x002058UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
26593 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X23                                                           0x00205cUL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
26594 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X24                                                           0x002060UL //Access:RW   DataWidth:0x8   BIST Check User-defined pattern  Chips: K2
26595 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X25                                                           0x002064UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
26596 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X26                                                           0x002068UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
26597 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X27                                                           0x00206cUL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
26598 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X28                                                           0x002070UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
26599 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X29                                                           0x002074UL //Access:RW   DataWidth:0x8   Bist checker insertion word.  Chips: K2
26600 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X30                                                           0x002078UL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
26601 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X31                                                           0x00207cUL //Access:R    DataWidth:0x8   Bist errors detected  Chips: K2
26602 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X32                                                           0x002080UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
26603 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X33                                                           0x002084UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
26604 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X34                                                           0x002088UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
26605 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X35                                                           0x00208cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
26606 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X36                                                           0x002090UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
26607 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X37                                                           0x002094UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
26608 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X38                                                           0x002098UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
26609 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X39                                                           0x00209cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
26610 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X40                                                           0x0020a0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
26611 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X41                                                           0x0020a4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
26612 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X42                                                           0x0020a8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
26613 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X43                                                           0x0020acUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
26614 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X44                                                           0x0020b0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
26615 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X45                                                           0x0020b4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
26616 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X46                                                           0x0020b8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
26617 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X47                                                           0x0020bcUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
26618 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X48                                                           0x0020c0UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 1/2 - for the new ICA method  Chips: K2
26619 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X49                                                           0x0020c4UL //Access:RW   DataWidth:0x8   Timing Window length for GCFSM for Gen 3 - for the new ICA method  Chips: K2
26620 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X50                                                           0x0020c8UL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 1/2 - for the new ICA method  Chips: K2
26621 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X51                                                           0x0020ccUL //Access:RW   DataWidth:0x8   Timing Window length for cdr_ctrl for Gen 3 - for the new ICA method  Chips: K2
26622 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X52                                                           0x0020d0UL //Access:RW   DataWidth:0x8   The start length of DFE offset calibration's first cycle is the value of this register multiplied by 4.  Chips: K2
26623 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53                                                           0x0020d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26624     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0                  (0x1f<<0) // The start length of DFE offset calibration, except for the 1st cycle.
26625     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_DFE_OFFSET_CAL_START_LEN_O_4_0_SHIFT            0
26626     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2                           (0x1<<5) // COMLANE or LANE CSR Select for GCFSM Cycle Length registers  0 -	 Select COMLANE registers  1 -	 Select LANE registers
26627     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_CYCLE_LEN_REG_SEL_O_2_SHIFT                     5
26628     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_TW_METHOD_EN                               (0x1<<6) // ICA Timing Window Method Enable control - for GCFSM
26629     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_TW_METHOD_EN_SHIFT                         6
26630     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_PMA_LOAD_OVR                               (0x1<<7) // ICA Method PMA Load signal Override - for GCFSM
26631     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X53_GCFSM_LANE_PMA_LOAD_OVR_SHIFT                         7
26632 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X54                                                           0x0020d8UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
26633 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X55                                                           0x0020dcUL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
26634 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X56                                                           0x0020e0UL //Access:RW   DataWidth:0x8   Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow  Chips: K2
26635 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57                                                           0x0020e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26636     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_OVR_O_27_24                                     (0xf<<0) // Bit[27] :Override enable for Lane GCFSM inputs. Bit[26]: Overide value for msm_ln_gcfsm_req_ow Bit[25:24]:Overide value for msm_ln_gcfsm_func_ow Bit[23:00]: Overide value for msm_ln_gcfsm_ctrl_ow
26637     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_OVR_O_27_24_SHIFT                               0
26638     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_OUT_OVR_EN_O                               (0x1<<4) // General Calibration Finite State Machine GCFSM output override enable - assertion causes data stored in gcfsm_lane_pma_data_ovr_o to override calibration values for the block selected by gcfsm_lane_pma_cal_ovr_o.
26639     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_OUT_OVR_EN_O_SHIFT                         4
26640     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_LATCH_OVR_O                            (0x1<<5) // GCFSM pma_latch_o override
26641     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_LATCH_OVR_O_SHIFT                      5
26642     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_GO_OVR_O                               (0x1<<6) // GCFSM pma_go_o override
26643     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_GO_OVR_O_SHIFT                         6
26644     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_READ_OVR_O                             (0x1<<7) // GCFSM pma_read_o override.
26645     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X57_GCFSM_LANE_PMA_READ_OVR_O_SHIFT                       7
26646 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X58                                                           0x0020e8UL //Access:RW   DataWidth:0x8   GCFSM pma_data_o override data. Bits applied to PMA are [8:15]  Chips: K2
26647 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X59                                                           0x0020ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26648     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8                        (0xf<<0) // GCFSM pma_data_o override data. Bits applied to PMA are [8:15]
26649     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X59_GCFSM_LANE_PMA_DATA_OVR_O_11_8_SHIFT                  0
26650     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X59_UNUSED_0                                              (0xf<<4) // reserved
26651     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X59_UNUSED_0_SHIFT                                        4
26652 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X60                                                           0x0020f0UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
26653 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X61                                                           0x0020f4UL //Access:RW   DataWidth:0x8   General Calibration Finite State Machine GCFSM overide select, enabled by gcfsm_lane_out_ovr_en. Only one bit should be asserted at a given time. Assertion of a given bit causes the value stored in gcfsm_lane_pma_data_ovr_o to the associated PMA compone  Chips: K2
26654 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62                                                           0x0020f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26655     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_LN_MSM_REQ_IN_OVR_O                                   (0x3<<0) // Bit 0:  Override enable for msm_ln_req Bit 1 : Override msm_ln_req
26656     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_LN_MSM_REQ_IN_OVR_O_SHIFT                             0
26657     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_LN_MSM_FUNC_IN_OVR_O                                  (0x3f<<2) // Bit 2:  Override enable for msm_func Bits [7:3] : Override msm_func
26658     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X62_LN_MSM_FUNC_IN_OVR_O_SHIFT                            2
26659 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65                                                           0x002104UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26660     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65_GCFSM_OVR_O_28                                        (0x1<<0) // Not currently used
26661     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65_GCFSM_OVR_O_28_SHIFT                                  0
26662     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65_UNUSED_0                                              (0x7f<<1) // reserved
26663     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X65_UNUSED_0_SHIFT                                        1
26664 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X66                                                           0x002108UL //Access:RW   DataWidth:0x8   Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.  Chips: K2
26665 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67                                                           0x00210cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26666     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_DLY_CDR_O_6_0                                (0x7f<<0) // Number of clock cycles between signal detect indicator
26667     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_DLY_CDR_O_6_0_SHIFT                          0
26668     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8                           (0x1<<7) // Number of cycles of low signal detect output required for RX electrical idle to be declared. Clock cycle length is controlled by cdrctrl_div_en register in common lane AHB.
26669     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X67_CDR_CTRL_SIGDET_LOW_MIN_O_8_SHIFT                     7
26670 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X68                                                           0x002110UL //Access:RW   DataWidth:0x8   Number of clock cycles between CISEL assertion  Chips: K2
26671 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69                                                           0x002114UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26672     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_DLY_LANE_O_9_8                               (0x3<<0) // Number of clock cycles between CISEL assertion
26673     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_DLY_LANE_O_9_8_SHIFT                         0
26674     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_START_LEN_O_3_0                              (0xf<<2) // Number of clock cycles between when CDR control block
26675     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_START_LEN_O_3_0_SHIFT                        2
26676     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_INT_FIL_O_1_0                                (0x3<<6) // CDR control DLPF positioning control.
26677     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X69_CDR_CTRL_INT_FIL_O_1_0_SHIFT                          6
26678 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X70                                                           0x002118UL //Access:RW   DataWidth:0x8   CDR control block cycle length When not in PCIe Gen3.  Chips: K2
26679 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X71                                                           0x00211cUL //Access:RW   DataWidth:0x8   CDR control block cycle length When in PCIe Gen3.  Chips: K2
26680 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72                                                           0x002120UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26681     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_CDR_CTRL_MAX_DIFF_O_4_0                               (0x1f<<0) // Maximum difference from DLPF center point.
26682     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_CDR_CTRL_MAX_DIFF_O_4_0_SHIFT                         0
26683     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_CDR_CTRL_MIN_BOUNCE_O_2_0                             (0x7<<5) // Maximum difference from DLPF center point.
26684     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X72_CDR_CTRL_MIN_BOUNCE_O_2_0_SHIFT                       5
26685 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73                                                           0x002124UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26686     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_TW_METHOD_EN                                 (0x1<<0) // ICA Timing Window Method Enable control - for cdr_control
26687     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_TW_METHOD_EN_SHIFT                           0
26688     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CONTROL_ATT_CTRL_O                                (0x1<<1) // ATT wait control. Upon detection of signal, DFE ATT calibration is enabled, without CISEL being asserted to the CDR.  0 - CDR control block will wait for ATT calibration before proceeding 1 - CDR control block will not wait for ATT calibration
26689     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CONTROL_ATT_CTRL_O_SHIFT                          1
26690     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_RXEQ_WAIT_EN_O                                        (0x1<<2) // CDR control block wait for DFE signal.  0 - Do not wait for DFE calibration before enabling rx data 1 - Wait for DFE calibration before enabling rx data
26691     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_RXEQ_WAIT_EN_O_SHIFT                                  2
26692     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_DLY_CDR_O_9_7                                (0x7<<3) // Number of clock cycles between signal detect indicator
26693     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_CDR_CTRL_DLY_CDR_O_9_7_SHIFT                          3
26694     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_UNUSED_0                                              (0x3<<6) // reserved
26695     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X73_UNUSED_0_SHIFT                                        6
26696 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X74                                                           0x002128UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
26697 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X75                                                           0x00212cUL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
26698 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X76                                                           0x002130UL //Access:RW   DataWidth:0x8   Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel  Chips: K2
26699 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77                                                           0x002134UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26700     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_OUT_OVR_O_29_24                              (0x3f<<0) // Override enable for CDR control block outputs. [0:29] Bit 29 - Override enable Bit 28 - Override for cdr_control_dlpf_frz Bit 27 - Override for cdr_control_dlpf_en Bit 26:13 - Override for cdr_control_dlpf Bit 12:5 - Override for cdr_control_cdr_cal_data Bit 4 - Override cdr_control_cdr_cal_go Bit 3 - Override for cdr_control_cdr_cal_latch Bit 2 - Override for cdr_control_cdr_cal_en Bit 1 - Override for cdr_control_data_en Bit 0 - Override for cdr_control_dfe_cisel
26701     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_OUT_OVR_O_29_24_SHIFT                        0
26702     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_CAL_LOAD_OVR                                 (0x1<<6) // ICA Method PMA Load signal Override - for cdr_control
26703     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_CDR_CTRL_CAL_LOAD_OVR_SHIFT                           6
26704     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_UNUSED_0                                              (0x1<<7) // reserved
26705     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X77_UNUSED_0_SHIFT                                        7
26706 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78                                                           0x002138UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26707     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_SYM_ALIGN_ALIGN_POS_O_5_0                             (0x3f<<0) // Symbol aligner position override enable.
26708     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_SYM_ALIGN_ALIGN_POS_O_5_0_SHIFT                       0
26709     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_SYM_ALIGN_MODE_O_1_0                                  (0x3<<6) // Symbol aligner mode select.
26710     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X78_SYM_ALIGN_MODE_O_1_0_SHIFT                            6
26711 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79                                                           0x00213cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26712     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79_SYM_ALIGN_BYPASS_O                                    (0x1<<0) // Asserting this register will bypass the symbol aligner
26713     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79_SYM_ALIGN_BYPASS_O_SHIFT                              0
26714     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79_UNUSED_0                                              (0x7f<<1) // reserved
26715     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X79_UNUSED_0_SHIFT                                        1
26716 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X80                                                           0x002140UL //Access:RW   DataWidth:0x8   Number of cycles to wait before forcing exit form EI  Chips: K2
26717 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81                                                           0x002144UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26718     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8                    (0x3<<0) // Number of cycles to wait before forcing exit form EI
26719     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EXIT_TIMER_LEN_O_9_8_SHIFT              0
26720     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_CLR_ERR_O                               (0x1<<2) // Clears the elec idle control error flag
26721     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_CLR_ERR_O_SHIFT                         2
26722     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_INFERRED_O                           (0x1<<3) // Override for ei_inferred signal
26723     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_INFERRED_O_SHIFT                     3
26724     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O                        (0x1<<4) // Override for ei_mask signal
26725     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EI_DETECT_MASK_O_SHIFT                  4
26726     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O                         (0x1<<5) // Override for ei_exit_type signal
26727     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_EII_EXIT_TYPE_O_SHIFT                   5
26728     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_OVR_O                                   (0x1<<6) // EI control override enable
26729     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_ELECIDLE_CTRL_OVR_O_SHIFT                             6
26730     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_UNUSED_0                                              (0x1<<7) // reserved
26731     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X81_UNUSED_0_SHIFT                                        7
26732 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X82                                                           0x002148UL //Access:RW   DataWidth:0x8   Number of cycles to wait before entering back into EI  Chips: K2
26733 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X83                                                           0x00214cUL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect glitch filter counter  Chips: K2
26734 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X84                                                           0x002150UL //Access:RW   DataWidth:0x8   Electrical Idle Control signal detect low filter min value  Chips: K2
26735 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85                                                           0x002154UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26736     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8                    (0x3<<0) // Number of cycles to wait before entering back into EI
26737     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_ELECIDLE_CTRL_LOCK_TIMER_LEN_O_9_8_SHIFT              0
26738     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0                     (0x3<<2) // EI Exit time cycles = timer_len_sel[1:0]+1*exit_timer_len_i[9:0]
26739     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_ELECIDLE_CTRL_TIMER_LEN_SEL_O_1_0_SHIFT               2
26740     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_LOOPBACK_EN_O                                         (0x1<<4) // Control signal to force decoder into loopback mode
26741     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_LOOPBACK_EN_O_SHIFT                                   4
26742     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_UNUSED_0                                              (0x7<<5) // reserved
26743     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X85_UNUSED_0_SHIFT                                        5
26744 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86                                                           0x002158UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26745     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_FES_LB_ENA_O                                          (0x1<<0) // FES loopback enable.
26746     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_FES_LB_ENA_O_SHIFT                                    0
26747     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_NES_LB_ENA_O                                          (0x1<<1) // NES loopback enable.
26748     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_NES_LB_ENA_O_SHIFT                                    1
26749     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_RXCLK_LB_ENA_O                                        (0x1<<2) // HS recovered clock to transmit loopback enable.
26750     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_RXCLK_LB_ENA_O_SHIFT                                  2
26751     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_UNUSED_0                                              (0x1f<<3) // reserved
26752     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X86_UNUSED_0_SHIFT                                        3
26753 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87                                                           0x00215cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26754     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOST_OVR_O                             (0x1<<0) // RX boost override enable
26755     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOST_OVR_O_SHIFT                       0
26756     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O                        (0x7f<<1) // RX boost override setting. Thermometer coded.
26757     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X87_AHB_PMA_LN_RX_BOOSTOVR_O_6_0_O_SHIFT                  1
26758 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X88                                                           0x002160UL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
26759 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89                                                           0x002164UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26760     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV1_O                            (0x7<<0) // Signal detect threshold select for Full rate
26761     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV1_O_SHIFT                      0
26762     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV2_O                            (0x7<<3) // Signal detect threshold select for div-by-2 rate
26763     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_SD_THSEL_DIV2_O_SHIFT                      3
26764     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXUP_O                                     (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
26765     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXUP_O_SHIFT                               6
26766     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXPREDIV4_ENA_O                            (0x1<<7) // RX FL calibration clock DIV4 enable
26767     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X89_AHB_PMA_LN_RXPREDIV4_ENA_O_SHIFT                      7
26768 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90                                                           0x002168UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26769     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_SD_THSEL_DIV4_O                            (0x7<<0) // Signal detect threshold select for div-by-4 rate
26770     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_SD_THSEL_DIV4_O_SHIFT                      0
26771     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_AGC_THSEL_O                                (0x7<<3) // AGC threshold select
26772     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_AGC_THSEL_O_SHIFT                          3
26773     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_VREGH_O                                    (0x3<<6) // Regulator VREGH setting
26774     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X90_AHB_PMA_LN_VREGH_O_SHIFT                              6
26775 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X91                                                           0x00216cUL //Access:RW   DataWidth:0x8   RX FL calibration LDHS  Chips: K2
26776 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92                                                           0x002170UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26777     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O                            (0x3<<0) // RX FL calibration LDHS
26778     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_RXFL_LDHS_9_8_O_SHIFT                      0
26779     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_RXVCO_BIAS_O                               (0xf<<2) // CDR VCO bias setting.
26780     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_RXVCO_BIAS_O_SHIFT                         2
26781     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O                            (0x1<<6) // DLPF DIV2 enable
26782     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_DLPF_DIV2_ENA_O_SHIFT                      6
26783     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_CDR_DVDR_ENA_O                             (0x1<<7) // CDR DivN clock divider enable.
26784     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X92_AHB_PMA_LN_CDR_DVDR_ENA_O_SHIFT                       7
26785 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X93                                                           0x002174UL //Access:RW   DataWidth:0x8   AFE spare controls  Chips: K2
26786 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94                                                           0x002178UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26787     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_AHB_PMA_LN_CDR_DVDR_O                                 (0x3f<<0) // CDR DivN clock division ratio.
26788     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_AHB_PMA_LN_CDR_DVDR_O_SHIFT                           0
26789     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_AHB_PMA_LN_VREG_O                                     (0x3<<6) // Regulator VREG setting
26790     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X94_AHB_PMA_LN_VREG_O_SHIFT                               6
26791 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95                                                           0x00217cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26792     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_BB_STEP_O                                  (0xf<<0) // CDR bb_step
26793     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_BB_STEP_O_SHIFT                            0
26794     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_INT_STEP_O                                 (0x7<<4) // CDR int step
26795     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_INT_STEP_O_SHIFT                           4
26796     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_RXDWN_O                                    (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
26797     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X95_AHB_PMA_LN_RXDWN_O_SHIFT                              7
26798 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96                                                           0x002180UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26799     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_O                                  (0x7<<0) // RXVCOFR override value Enabled by pma_ln_dr_rxvcofr_sel_o
26800     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_O_SHIFT                            0
26801     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_SEL_O                              (0x1<<3) // Override enable for RXVCOFR override vakue
26802     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RXVCOFR_SEL_O_SHIFT                        3
26803     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RX_SELR_O                                  (0x7<<4) // CTLE R degeneration select
26804     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_AHB_PMA_LN_RX_SELR_O_SHIFT                            4
26805     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_UNUSED_0                                              (0x1<<7) // reserved
26806     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X96_UNUSED_0_SHIFT                                        7
26807 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X97                                                           0x002184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26808     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X97_AHB_PMA_LN_RX_SELC_O                                  (0x7<<0) // CTLE C degeneration select
26809     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X97_AHB_PMA_LN_RX_SELC_O_SHIFT                            0
26810     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X97_UNUSED_0                                              (0x1f<<3) // reserved
26811     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X97_UNUSED_0_SHIFT                                        3
26812 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99                                                           0x00218cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26813     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_UNUSED_0                                              (0xf<<0) // reserved
26814     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_UNUSED_0_SHIFT                                        0
26815     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_PMA_LN_DFE_BW_SCALE                                   (0x3<<4) // DFE Bandwidth Selection
26816     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_PMA_LN_DFE_BW_SCALE_SHIFT                             4
26817     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_PMA_LN_PHD_ENA_O_1_0                                  (0x3<<6) // CDR phase detector proportional path enable bit 0: enables D4/D3 data/edge samplers bit 1: enables D1/D2 data/edge samplers
26818     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X99_PMA_LN_PHD_ENA_O_1_0_SHIFT                            6
26819 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X100                                                          0x002190UL //Access:RW   DataWidth:0x8   On-chip eye diagram X-direction offset control: Bit 0: unused Bits 1-2: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 3-9: Fine x-direction offset, note bit reversal  Chips: K2
26820 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101                                                          0x002194UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26821     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_DLY_O_8_8                                 (0x1<<0) // On-chip eye diagram X-direction offset control: Bits 0-1: Coarse x-direction offset, in steps of 1/2UI - note bit reversal Bits 2-8: Fine x-direction offset, note bit reversal
26822     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_DLY_O_8_8_SHIFT                           0
26823     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_UNUSED_0                                             (0x1<<1) // reserved
26824     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_UNUSED_0_SHIFT                                       1
26825     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_SGN_RST_O                                 (0x1<<2) // Reset signal for eye alignment mechanism.
26826     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_SGN_RST_O_SHIFT                           2
26827     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_SD_BWSEL                                      (0x1<<3) // RX signal detector bandwidth select. 0: Nominal bandwidth 1: 10% higher bandwidth
26828     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_SD_BWSEL_SHIFT                                3
26829     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA270_O                                  (0x1<<4) // In eye diagram generation mode, assertion overrides the ck_270 DFE clock "right" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
26830     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA270_O_SHIFT                            4
26831     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA90_O                                   (0x1<<5) // In eye diagram generation mode, assertion overrides the ck_90 DFE clock "left" eye edge clock with the shifted clock. Only assert one of pma_ln_eye_ena270_o and pma_ln_eye_ena90_o at the same time
26832     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_PMA_LN_EYE_ENA90_O_SHIFT                             5
26833     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_UNUSED_1                                             (0x3<<6) // reserved
26834     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X101_UNUSED_1_SHIFT                                       6
26835 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X102                                                          0x002198UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26836     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X102_PMA_LN_DFE_BIAS_O_3_0                                (0xf<<0) // DFE bias setting.
26837     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X102_PMA_LN_DFE_BIAS_O_3_0_SHIFT                          0
26838     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X102_UNUSED_0                                             (0xf<<4) // reserved
26839     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X102_UNUSED_0_SHIFT                                       4
26840 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103                                                          0x00219cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26841     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_PMA_LN_TX_SR_FASTCAP_O_3_0                           (0xf<<0) // TX driver capacitive slew rate control.
26842     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_PMA_LN_TX_SR_FASTCAP_O_3_0_SHIFT                     0
26843     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_PMA_LN_TXEQ_POLARITY_O_3_0                           (0xf<<4) // TX coefficient polarity enable. Set to "1" for negative polarity. bit 0: Cm bit 1: C0 bit 2: C1
26844     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X103_PMA_LN_TXEQ_POLARITY_O_3_0_SHIFT                     4
26845 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104                                                          0x0021a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26846     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_TX_SR_DAC_O_3_0                               (0xf<<0) // TX slew rate DAC bias current control
26847     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_TX_SR_DAC_O_3_0_SHIFT                         0
26848     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_HSCLK_SEL_O                                   (0x1<<4) // CDR clock divider bypass enable.
26849     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_PMA_LN_HSCLK_SEL_O_SHIFT                             4
26850     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_UNUSED_0                                             (0x7<<5) // reserved
26851     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X104_UNUSED_0_SHIFT                                       5
26852 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105                                                          0x0021a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26853     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TX_VREG_LEV_O_4_0                             (0x1f<<0) // TX driver regulator voltage setting.
26854     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TX_VREG_LEV_O_4_0_SHIFT                       0
26855     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TXDRV_BLEED_ENA_O                             (0x1<<5) // TX bleed enable
26856     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_PMA_LN_TXDRV_BLEED_ENA_O_SHIFT                       5
26857     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_UNUSED_0                                             (0x3<<6) // reserved
26858     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X105_UNUSED_0_SHIFT                                       6
26859 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106                                                          0x0021a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26860     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O                       (0x1<<0) // RX boost override enable.
26861     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOST_OVR_GEN3_O_SHIFT                 0
26862     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O                    (0x7f<<1) // RX boost override setting. Thermometer coded.
26863     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X106_AHB_PMA_LN_RX_BOOSTOVR_GEN3_6_0_O_SHIFT              1
26864 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X107                                                          0x0021acUL //Access:RW   DataWidth:0x8   RX boost override setting. Thermometer coded.  Chips: K2
26865 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108                                                          0x0021b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26866     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_SD_THSEL_GEN3_O                           (0x7<<0) // Signal detect threshold select for Gen3
26867     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_SD_THSEL_GEN3_O_SHIFT                     0
26868     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O                          (0x7<<3) // AGC threshold select for Gen3
26869     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_AGC_THSEL_GEN3_O_SHIFT                    3
26870     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXUP_GEN3_O                               (0x1<<6) // dfe_edge_by[1]. Adjust timing in 270 degree resampler from flop to latch. Eye monitor mode usage only.
26871     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXUP_GEN3_O_SHIFT                         6
26872     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O                      (0x1<<7) // CDR VCO frequency lock counter divide by 4 enable.
26873     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X108_AHB_PMA_LN_RXPREDIV4_ENA_GEN3_O_SHIFT                7
26874 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X109                                                          0x0021b4UL //Access:RW   DataWidth:0x8   RX FL calibration LDHS for Gen3  Chips: K2
26875 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110                                                          0x0021b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26876     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O                      (0x3<<0) // RX FL calibration LDHS for Gen3
26877     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_RXFL_LDHS_GEN3_9_8_O_SHIFT                0
26878     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O                         (0xf<<2) // CDR VCO bias setting.
26879     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_RXVCO_BIAS_GEN3_O_SHIFT                   2
26880     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O                      (0x1<<6) // DLPF DIV2 enable
26881     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_DLPF_DIV2_ENA_GEN3_O_SHIFT                6
26882     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O                       (0x1<<7) // CDR DivN clock divider enable.
26883     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X110_AHB_PMA_LN_CDR_DVDR_ENA_GEN3_O_SHIFT                 7
26884 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X111                                                          0x0021bcUL //Access:RW   DataWidth:0x8   AFE spare controls for Gen3  Chips: K2
26885 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112                                                          0x0021c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26886     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O                           (0x3f<<0) // CDR DivN clock divider ratio..
26887     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_AHB_PMA_LN_CDR_DVDR_GEN3_O_SHIFT                     0
26888     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_AHB_PMA_LN_VREG_GEN3_O                               (0x3<<6) // Regulator VREG setting for Gen3
26889     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X112_AHB_PMA_LN_VREG_GEN3_O_SHIFT                         6
26890 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113                                                          0x0021c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26891     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_BB_STEP_GEN3_O                            (0xf<<0) // CDR bb_step for Gen3
26892     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_BB_STEP_GEN3_O_SHIFT                      0
26893     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_INT_STEP_GEN3_O                           (0x7<<4) // CDR int step for Gen3
26894     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_INT_STEP_GEN3_O_SHIFT                     4
26895     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_RXDWN_GEN3_O                              (0x1<<7) // dfe_edge_by[0]. Adjust timing in 90 degree resampler from flop to latch. Eye monitor mode usage only.
26896     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X113_AHB_PMA_LN_RXDWN_GEN3_O_SHIFT                        7
26897 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114                                                          0x0021c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26898     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RXVCOFR_GEN3_O                            (0x7<<0) // RXVCOFR override value for Gen3 Enabled by pma_ln_dr_rxvcofr_sel_o
26899     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RXVCOFR_GEN3_O_SHIFT                      0
26900     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RX_SELR_GEN3_O                            (0x7<<3) // CTLE R degeneration select for Gen3
26901     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_RX_SELR_GEN3_O_SHIFT                      3
26902     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_VREGH_GEN3_O                              (0x3<<6) // Not currently used
26903     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X114_AHB_PMA_LN_VREGH_GEN3_O_SHIFT                        6
26904 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X115                                                          0x0021ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26905     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X115_AHB_PMA_LN_RX_SELC_GEN3_O                            (0x7<<0) // CTLE R degeneration select for Gen3
26906     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X115_AHB_PMA_LN_RX_SELC_GEN3_O_SHIFT                      0
26907     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X115_UNUSED_0                                             (0x1f<<3) // reserved
26908     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X115_UNUSED_0_SHIFT                                       3
26909 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119                                                          0x0021dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26910     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_AHB_TX_CXP_MARGIN                                    (0xf<<0) // Value to minus/add from the calibrated txterm value
26911     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_AHB_TX_CXP_MARGIN_SHIFT                              0
26912     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_AHB_TX_CXN_MARGIN                                    (0xf<<4) // Value to minus/add from the calibrated txterm value
26913     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X119_AHB_TX_CXN_MARGIN_SHIFT                              4
26914 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120                                                          0x0021e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26915     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_AHB_TX_TC_WAIT_NEXT_CMP                              (0xf<<0) // in txterm calibration, the number refclk cycles to wait before sampling the up from a different comparator  the register ix X2 is the actual number of wait cycle
26916     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_AHB_TX_TC_WAIT_NEXT_CMP_SHIFT                        0
26917     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE                           (0x7<<4) // in txterm calibration, the number refclk cycles to wait before sampling the up from the same comparator
26918     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_AHB_TX_TC_WAIT_NEXT_SAMPLE_SHIFT                     4
26919     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_UNUSED_0                                             (0x1<<7) // reserved
26920     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X120_UNUSED_0_SHIFT                                       7
26921 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121                                                          0x0021e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26922     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES                        (0xf<<0) // in txterm calibration, the number of samples to take from the same comparator
26923     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TC_CMP_OUT_NUM_SAMPLES_SHIFT                  0
26924     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXP_MARGIN_ADD_0                              (0x1<<4) // when 1, the final tx term value is calibrated txterm value + tx_cxp_margin; when 0, the final tx term value is calibrated txterm value - tx_cxp_margin
26925     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXP_MARGIN_ADD_0_SHIFT                        4
26926     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXN_MARGIN_ADD_0                              (0x1<<5) // when 1, the final tx term value is calibrated txterm value + tx_cxn_margin; when 0, the final tx term value is calibrated txterm value - tx_cxn_margin
26927     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CXN_MARGIN_ADD_0_SHIFT                        5
26928     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CX_OVR_ENA                                    (0x1<<6) // enable override calibrated txterm value
26929     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_CX_OVR_ENA_SHIFT                              6
26930     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TERM_EN_CAL_OVR                               (0x1<<7) // Debug feature, when set forces circuit to be affected by ahb_tx_cdac_ovr
26931     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X121_AHB_TX_TERM_EN_CAL_OVR_SHIFT                         7
26932 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122                                                          0x0021e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26933     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_AHB_TX_CXP_OVR                                       (0xf<<0) // override calibrated txterm value
26934     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_AHB_TX_CXP_OVR_SHIFT                                 0
26935     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_AHB_TX_CXN_OVR                                       (0xf<<4) // override calibrated txterm value
26936     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X122_AHB_TX_CXN_OVR_SHIFT                                 4
26937 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123                                                          0x0021ecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26938     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_0                                          (0x1<<0) // TX Control override enable. Bit 0: txdrv_sel_sw_map Bit 1: not currently used
26939     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_0_SHIFT                                    0
26940     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_UNUSED_0                                             (0x1<<1) // reserved
26941     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_UNUSED_0_SHIFT                                       1
26942     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_7_2                                        (0x3f<<2) // TX Control override enable. Bits 5:2:txdrv_att_in[3:0] Bits 7:6 : tx_slew_sld[1:0]
26943     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X123_TX_CTRL_O_7_2_SHIFT                                  2
26944 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X124                                                          0x0021f0UL //Access:RW   DataWidth:0x8   Bits 12:8: txdrv_c1_in[4:0] Bits 15:13: txdrv_c2_in[2:0]  Chips: K2
26945 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X125                                                          0x0021f4UL //Access:RW   DataWidth:0x8   Bits 19-16: txdrv_cm_in[3:0]  Bits 22-20: tx_slew_sld3f[2:0] Bit 23: txdrv_preem_1lsb_mode  Chips: K2
26946 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126                                                          0x0021f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26947     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_EN_O                                            (0x1<<0) // DFE block enable signal.
26948     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_EN_O_SHIFT                                      0
26949     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE_OW_O_2_0                                (0x7<<1) // These bits have similar functionality as rxeq_rate_ow_o_2_0 bits in COMLANE CSR. These are used mainly in COMBINATION modes of operation. They are logically OR'ed with the bits in COMLANE.
26950     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE_OW_O_2_0_SHIFT                          1
26951     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE1_CAL_EN_O_3                             (0x1<<4) // This bit has similar function as rxeq_rate1_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
26952     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE1_CAL_EN_O_3_SHIFT                       4
26953     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE2_CAL_EN_O_4                             (0x1<<5) // This bit has similar function as rxeq_rate2_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE.
26954     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE2_CAL_EN_O_4_SHIFT                       5
26955     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE3_CAL_EN_O_5                             (0x1<<6) // This bit has similar function as rxeq_rate3_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
26956     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_RATE3_CAL_EN_O_5_SHIFT                       6
26957     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_FORCE_CAL_O_6                                (0x1<<7) // This bit has similar function as rxeq_force_cal_en_o in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
26958     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X126_RXEQ_LN_FORCE_CAL_O_6_SHIFT                          7
26959 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X127                                                          0x0021fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26960     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X127_RXEQ_CONT_CAL_O_6_0                                  (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
26961     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X127_RXEQ_CONT_CAL_O_6_0_SHIFT                            0
26962     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X127_UNUSED_0                                             (0x1<<7) // reserved
26963     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X127_UNUSED_0_SHIFT                                       7
26964 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X128                                                          0x002200UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26965     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X128_RXEQ_INIT_CAL_O_6_0                                  (0x7f<<0) // 0 : enables att calibration 1: enables Boost calibration 2: enables tap1 dfe calibration 3: enables tap2 dfe calibration 4: enables tap3 dfe calibration 5: enables tap4 dfe calibration 6: enables tap5 dfe calibration This register Is not bit reversed
26966     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X128_RXEQ_INIT_CAL_O_6_0_SHIFT                            0
26967     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X128_UNUSED_0                                             (0x1<<7) // reserved
26968     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X128_UNUSED_0_SHIFT                                       7
26969 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130                                                          0x002208UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26970     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_RXEQ_RATE1_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate1
26971     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_RXEQ_RATE1_ATT_START_O_3_0_SHIFT                     0
26972     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_RXEQ_RATE1_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate1
26973     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X130_RXEQ_RATE1_BOOST_START_O_3_0_SHIFT                   4
26974 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131                                                          0x00220cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26975     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_RXEQ_RATE2_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate2
26976     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_RXEQ_RATE2_ATT_START_O_3_0_SHIFT                     0
26977     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_RXEQ_RATE2_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate2
26978     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X131_RXEQ_RATE2_BOOST_START_O_3_0_SHIFT                   4
26979 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X132                                                          0x002210UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26980     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X132_RXEQ_RATE2_TAP1_START_O_6_0                          (0x7f<<0) // DFE Tap1 start value for rate2
26981     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X132_RXEQ_RATE2_TAP1_START_O_6_0_SHIFT                    0
26982     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X132_UNUSED_0                                             (0x1<<7) // reserved
26983     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X132_UNUSED_0_SHIFT                                       7
26984 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X133                                                          0x002214UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26985     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X133_RXEQ_RATE2_TAP2_START_O_5_0                          (0x3f<<0) // DFE Tap2 start value for rate2
26986     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X133_RXEQ_RATE2_TAP2_START_O_5_0_SHIFT                    0
26987     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X133_UNUSED_0                                             (0x3<<6) // reserved
26988     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X133_UNUSED_0_SHIFT                                       6
26989 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X134                                                          0x002218UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26990     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X134_RXEQ_RATE2_TAP3_START_O_5_0                          (0x3f<<0) // DFE Tap3 start value for rate2
26991     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X134_RXEQ_RATE2_TAP3_START_O_5_0_SHIFT                    0
26992     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X134_UNUSED_0                                             (0x3<<6) // reserved
26993     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X134_UNUSED_0_SHIFT                                       6
26994 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X135                                                          0x00221cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
26995     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X135_RXEQ_RATE2_TAP4_START_O_5_0                          (0x3f<<0) // DFE Tap4 start value for rate2
26996     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X135_RXEQ_RATE2_TAP4_START_O_5_0_SHIFT                    0
26997     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X135_UNUSED_0                                             (0x3<<6) // reserved
26998     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X135_UNUSED_0_SHIFT                                       6
26999 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X136                                                          0x002220UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27000     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X136_RXEQ_RATE2_TAP5_START_O_5_0                          (0x3f<<0) // DFE Tap5 start value for rate2
27001     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X136_RXEQ_RATE2_TAP5_START_O_5_0_SHIFT                    0
27002     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X136_UNUSED_0                                             (0x3<<6) // reserved
27003     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X136_UNUSED_0_SHIFT                                       6
27004 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137                                                          0x002224UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27005     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_RXEQ_RATE3_ATT_START_O_3_0                           (0xf<<0) // ATT start value for rate3
27006     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_RXEQ_RATE3_ATT_START_O_3_0_SHIFT                     0
27007     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_RXEQ_RATE3_BOOST_START_O_3_0                         (0xf<<4) // Boost start value for rate3
27008     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X137_RXEQ_RATE3_BOOST_START_O_3_0_SHIFT                   4
27009 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X138                                                          0x002228UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27010     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X138_RXEQ_RATE3_TAP1_START_O_6_0                          (0x7f<<0) // DFE Tap1 start value for rate3
27011     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X138_RXEQ_RATE3_TAP1_START_O_6_0_SHIFT                    0
27012     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X138_UNUSED_0                                             (0x1<<7) // reserved
27013     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X138_UNUSED_0_SHIFT                                       7
27014 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X139                                                          0x00222cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27015     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X139_RXEQ_RATE3_TAP2_START_O_5_0                          (0x3f<<0) // DFE Tap2 start value for rate3
27016     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X139_RXEQ_RATE3_TAP2_START_O_5_0_SHIFT                    0
27017     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X139_UNUSED_0                                             (0x3<<6) // reserved
27018     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X139_UNUSED_0_SHIFT                                       6
27019 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X140                                                          0x002230UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27020     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X140_RXEQ_RATE3_TAP3_START_O_5_0                          (0x3f<<0) // DFE Tap3 start value for rate3
27021     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X140_RXEQ_RATE3_TAP3_START_O_5_0_SHIFT                    0
27022     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X140_UNUSED_0                                             (0x3<<6) // reserved
27023     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X140_UNUSED_0_SHIFT                                       6
27024 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X141                                                          0x002234UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27025     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X141_RXEQ_RATE3_TAP4_START_O_5_0                          (0x3f<<0) // DFE Tap4 start value for rate3
27026     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X141_RXEQ_RATE3_TAP4_START_O_5_0_SHIFT                    0
27027     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X141_UNUSED_0                                             (0x3<<6) // reserved
27028     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X141_UNUSED_0_SHIFT                                       6
27029 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X142                                                          0x002238UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27030     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X142_RXEQ_RATE3_TAP5_START_O_5_0                          (0x3f<<0) // DFE Tap5 start value for rate3
27031     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X142_RXEQ_RATE3_TAP5_START_O_5_0_SHIFT                    0
27032     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X142_UNUSED_0                                             (0x3<<6) // reserved
27033     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X142_UNUSED_0_SHIFT                                       6
27034 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143                                                          0x00223cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27035     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RXEQ_SUPERBST_AUTOCAL_DIS                            (0x1<<0) // Disable auto cal w/ rx_superbst
27036     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RXEQ_SUPERBST_AUTOCAL_DIS_SHIFT                      0
27037     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_O                                    (0xf<<1) // Max limit value for BOOST auto-calibration
27038     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_O_SHIFT                              1
27039     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_EN_O                                 (0x1<<5) // Enable Max limiting for BOOST auto-calibration
27040     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_BOOST_MAX_LIMIT_EN_O_SHIFT                           5
27041     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RX_ATT_BOOST_CAL_O_1_0                               (0x3<<6) // rx_att_boost setting used during ATT calibration
27042     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X143_RX_ATT_BOOST_CAL_O_1_0_SHIFT                         6
27043 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144                                                          0x002240UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27044     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RX_ATT_BOOST_NORM_O_1_0                              (0x3<<0) // rx_att_boost setting used after ATT calibration
27045     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RX_ATT_BOOST_NORM_O_1_0_SHIFT                        0
27046     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_EN_O                                  (0x1<<2) // boost_adj_en
27047     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_EN_O_SHIFT                            2
27048     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_DIR_O                                 (0x1<<3) // boost_adj_dir
27049     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_DIR_O_SHIFT                           3
27050     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_VAL_O                                 (0xf<<4) // boost_adj_val This register Is not bit reversed
27051     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X144_RXEQ_BOOST_ADJ_VAL_O_SHIFT                           4
27052 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145                                                          0x002244UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27053     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0                    (0x7f<<0) // Max number of samples to be used for CMP Offset Noise Averaging
27054     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_MAX_NUMSAMPLES_6_0_SHIFT              0
27055     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_EN_O                                  (0x1<<7) // CMP Offset Noise Averaging Enable
27056     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X145_CMP_OFFSET_AVG_EN_O_SHIFT                            7
27057 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X146                                                          0x002248UL //Access:RW   DataWidth:0x8     Chips: K2
27058 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147                                                          0x00224cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27059     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_DFE_TAP_PD_WAIT_11_8                            (0xf<<0) //
27060     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_DFE_TAP_PD_WAIT_11_8_SHIFT                      0
27061     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_PMA_LN_DFE_OFS_CAL_ENA                               (0x3<<4) // DFE offset calibration enable
27062     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_PMA_LN_DFE_OFS_CAL_ENA_SHIFT                         4
27063     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS                            (0x1<<6) // Disable auto cal w/ rx_att_gain
27064     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_ATT_GAIN_AUTOCAL_DIS_SHIFT                      6
27065     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_SUPERBST_EN_INVERT_O                            (0x1<<7) // Inverts the polarity of superboost_en before assigning to PMA
27066     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X147_RXEQ_SUPERBST_EN_INVERT_O_SHIFT                      7
27067 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148                                                          0x002250UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27068     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_LOAD_EN_O_6_0                               (0x7f<<0) // Override for RXEQ_CTRL output register load enable.
27069     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_LOAD_EN_O_6_0_SHIFT                         0
27070     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_EN_O                                        (0x1<<7) // Override enable for DFE signals.
27071     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X148_RXEQ_OVR_EN_O_SHIFT                                  7
27072 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149                                                          0x002254UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27073     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LOAD_O_6_0                                  (0x7f<<0) // Override for RXEQ_CTRL output register load value.
27074     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LOAD_O_6_0_SHIFT                            0
27075     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LATCH_O                                     (0x1<<7) // Override for DFE latch signal. Negative edge causes AFE to store values of DFE output registers.
27076     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X149_RXEQ_OVR_LATCH_O_SHIFT                               7
27077 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150                                                          0x002258UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27078     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0                           (0x7<<0) // Override value for comparator calibration select. Enabled by rxeq_ovr_en_o: 1: Calibrate DFE comparator 1 2: Calibrate DFE comparator 2 3: Calibrate DFE comparator 3 4: Calibrate DFE comparator 4
27079     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_DFE_CMP_SEL_OVR_O_2_0_SHIFT                     0
27080     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_ATT_GAIN_OVR                                    (0x3<<3) // Override the value of rx_att_gain output to PMA when rx_att_gain_autocal_dis=1
27081     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_ATT_GAIN_OVR_SHIFT                              3
27082     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_SUPERBST_ENA_OVR                                (0x1<<5) // Override the value of rx_superbst_ena output to PMA when superbst_autocal_dis=1
27083     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_RXEQ_SUPERBST_ENA_OVR_SHIFT                          5
27084     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6                       (0x1<<6) // DFE TAP CMP no offset override enable
27085     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_CMP_NO_OFST_OVR_EN_O_6_SHIFT                 6
27086     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_OVR_EN_O_7                                   (0x1<<7) // DFE TAP override enable
27087     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X150_DFE_TAP_OVR_EN_O_7_SHIFT                             7
27088 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151                                                          0x00225cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27089     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3                      (0x1f<<0) // DFE offset calibration TAP enable override
27090     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_TAP_EN_OVR_O_7_3_SHIFT                0
27091     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0                        (0x1<<5) // DFE offset calibrated value override enable
27092     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_VAL_OVR_EN_O_0_SHIFT                  5
27093     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_EN_OVR_O_1                            (0x1<<6) // DFE offset cal enable override
27094     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_OFFSET_CAL_EN_OVR_O_1_SHIFT                      6
27095     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_CMP_CAL_EN_OVR_O_2                               (0x1<<7) // DFE comparator cal enable override
27096     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X151_DFE_CMP_CAL_EN_OVR_O_2_SHIFT                         7
27097 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X152                                                          0x002260UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27098     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X152_DFE_TAP1_OVR_VAL_O_6_0                               (0x7f<<0) // DFE Tap 1 Override Value
27099     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X152_DFE_TAP1_OVR_VAL_O_6_0_SHIFT                         0
27100     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X152_UNUSED_0                                             (0x1<<7) // reserved
27101     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X152_UNUSED_0_SHIFT                                       7
27102 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X153                                                          0x002264UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27103     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X153_DFE_TAP2_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 2 Override Value
27104     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X153_DFE_TAP2_OVR_VAL_O_5_0_SHIFT                         0
27105     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X153_UNUSED_0                                             (0x3<<6) // reserved
27106     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X153_UNUSED_0_SHIFT                                       6
27107 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X154                                                          0x002268UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27108     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X154_DFE_TAP3_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 3 Override Value
27109     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X154_DFE_TAP3_OVR_VAL_O_5_0_SHIFT                         0
27110     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X154_UNUSED_0                                             (0x3<<6) // reserved
27111     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X154_UNUSED_0_SHIFT                                       6
27112 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X155                                                          0x00226cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27113     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X155_DFE_TAP4_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 4 Override Value
27114     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X155_DFE_TAP4_OVR_VAL_O_5_0_SHIFT                         0
27115     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X155_UNUSED_0                                             (0x3<<6) // reserved
27116     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X155_UNUSED_0_SHIFT                                       6
27117 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X156                                                          0x002270UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27118     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X156_DFE_TAP5_OVR_VAL_O_5_0                               (0x3f<<0) // DFE Tap 5 Override Value
27119     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X156_DFE_TAP5_OVR_VAL_O_5_0_SHIFT                         0
27120     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X156_UNUSED_0                                             (0x3<<6) // reserved
27121     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X156_UNUSED_0_SHIFT                                       6
27122 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157                                                          0x002274UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27123     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ADAPT_EN_O_0                                    (0x1<<0) // TX Equalizer adaptation function enable
27124     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ADAPT_EN_O_0_SHIFT                              0
27125     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ERR_SIGN_O_1                                    (0x1<<1) // TX Equalizer Error Sign
27126     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_ERR_SIGN_O_1_SHIFT                              1
27127     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_FW_OVRIDE_O_2                                   (0x1<<2) // TX Equalization Firmware over ride  0 -	 Disable firmware based adaptation  1 -	 Enbale firmware based adaptation
27128     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_TXEQ_FW_OVRIDE_O_2_SHIFT                             2
27129     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_UNUSED_0                                             (0x1f<<3) // reserved
27130     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X157_UNUSED_0_SHIFT                                       3
27131 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X158                                                          0x002278UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27132     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X158_TXEQ_ERR_STAT_I_1_0                                  (0x3<<0) // TX Equalization error state
27133     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X158_TXEQ_ERR_STAT_I_1_0_SHIFT                            0
27134     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X158_UNUSED_0                                             (0x3f<<2) // reserved
27135     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X158_UNUSED_0_SHIFT                                       2
27136 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X159                                                          0x00227cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27137     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X159_TXEQ_OVER_EQ_CNT_I_9_8                               (0x3<<0) // Over equalization count 9-8
27138     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X159_TXEQ_OVER_EQ_CNT_I_9_8_SHIFT                         0
27139     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X159_UNUSED_0                                             (0x3f<<2) // reserved
27140     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X159_UNUSED_0_SHIFT                                       2
27141 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X160                                                          0x002280UL //Access:R    DataWidth:0x8   Over equalization count 7-0  Chips: K2
27142 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X161                                                          0x002284UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27143     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X161_TXEQ_UNDER_EQ_CNT_I_9_8                              (0x3<<0) // Under equalization count 9-8
27144     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X161_TXEQ_UNDER_EQ_CNT_I_9_8_SHIFT                        0
27145     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X161_UNUSED_0                                             (0x3f<<2) // reserved
27146     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X161_UNUSED_0_SHIFT                                       2
27147 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X162                                                          0x002288UL //Access:R    DataWidth:0x8   Under equalization count 7-0  Chips: K2
27148 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X163                                                          0x00228cUL //Access:RW   DataWidth:0x8   TX Equalizer Training Pattern  Chips: K2
27149 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164                                                          0x002290UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27150     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164_TXEQ_TRAINING_PATT_O_8                               (0x1<<0) // TX Equalizer Training Pattern
27151     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164_TXEQ_TRAINING_PATT_O_8_SHIFT                         0
27152     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164_UNUSED_0                                             (0x7f<<1) // reserved
27153     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X164_UNUSED_0_SHIFT                                       1
27154 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X165                                                          0x002294UL //Access:RW   DataWidth:0x8   Mask bit for Txeq training pattern  Chips: K2
27155 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166                                                          0x002298UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27156     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166_TXEQ_DONT_CARE_O_8                                   (0x1<<0) // Mask bit for Txeq training pattern
27157     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166_TXEQ_DONT_CARE_O_8_SHIFT                             0
27158     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166_UNUSED_0                                             (0x7f<<1) // reserved
27159     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X166_UNUSED_0_SHIFT                                       1
27160 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167                                                          0x00229cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27161     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167_TXEQ_RXRECAL_INIT_O_7                                (0x1<<0) // This bit has similar function as txeq_rxrecal_init  in COMLANE CSR. It is logically OR'ed with the bit in COMLANE
27162     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167_TXEQ_RXRECAL_INIT_O_7_SHIFT                          0
27163     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167_UNUSED_0                                             (0x7f<<1) // reserved
27164     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X167_UNUSED_0_SHIFT                                       1
27165 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168                                                          0x0022a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27166     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_INIT_RX_PRESET_HINT_EN_O                             (0x1<<0) // Enable for primary input lnx_rx_preset_hint during init cal.
27167     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_INIT_RX_PRESET_HINT_EN_O_SHIFT                       0
27168     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_RECAL_RX_PRESET_HINT_EN_O                            (0x1<<1) // Enable for primary input lnx_rx_preset_hint during recal.
27169     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_RECAL_RX_PRESET_HINT_EN_O_SHIFT                      1
27170     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_UNUSED_0                                             (0x3f<<2) // reserved
27171     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X168_UNUSED_0_SHIFT                                       2
27172 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169                                                          0x0022a4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27173     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169_TXEQ_RXRECAL_DONE_I_0                                (0x1<<0) // TX - RECAL RX Equalization status
27174     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169_TXEQ_RXRECAL_DONE_I_0_SHIFT                          0
27175     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169_UNUSED_0                                             (0x7f<<1) // reserved
27176     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X169_UNUSED_0_SHIFT                                       1
27177 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170                                                          0x0022a8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27178     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170_BLOCK_DEC_ERR                                        (0x1<<0) // decoder sync header error
27179     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170_BLOCK_DEC_ERR_SHIFT                                  0
27180     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170_UNUSED_0                                             (0x7f<<1) // reserved
27181     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X170_UNUSED_0_SHIFT                                       1
27182 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201                                                          0x002324UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27183     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_EN_O_0                                          (0x1<<0) // cdfe enable bit.  1: enable cdfe when rate is 2'b01 or 2'b10.  0: disable cdfe.
27184     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_EN_O_0_SHIFT                                    0
27185     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_WORD_OV_O_1_0                                   (0x3<<1) // The cdfe input word_i overwrite.                                                                                                         2'b00: the word_i input for cdfe block is internally generated.                                     2'b10: the word_i input for cdfe block is set to 0 8-bit or 10-bit mode.                                                       2'b11: the word_i input for cdfe block is set to 1 16-bit or 20-bit mode.
27186     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_WORD_OV_O_1_0_SHIFT                             1
27187     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_MODE_8B_OV_O_1_0                                (0x3<<3) // The cdfe input mode_8b_i overwrite.                                                                                                         2'b00: the mode_8b_i input for cdfe block is internally generated.                                      2'b01: the mode_8b_i input for cdfe block is set to 0 10-bit or 20-bit mode.                                                      2'b11: the mode_8b_i input for cdfe block is set to 1 8-bit or 16-bit mode.
27188     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_MODE_8B_OV_O_1_0_SHIFT                          3
27189     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_RATE_OV_O_2_0                                   (0x7<<5) // The cdfe input rate_i[1:0] overwrite.                                                                                                         3'b0xx: the rate_i input for cdfe block is internally generated.                                     3'b1xx: the rate_i[1:0] input for cdfe block is set to cdfe_rate_ov_o[1:0]
27190     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X201_CDFE_RATE_OV_O_2_0_SHIFT                             5
27191 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X202                                                          0x002328UL //Access:RW   DataWidth:0x8     Chips: K2
27192 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203                                                          0x00232cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27193     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_UNUSED_0                                             (0xf<<0) // reserved
27194     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_UNUSED_0_SHIFT                                       0
27195     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_GO                                              (0x1<<4) //
27196     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_GO_SHIFT                                        4
27197     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_FORCE_CAL                                    (0x1<<5) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
27198     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_FORCE_CAL_SHIFT                              5
27199     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_RATE_CHANGE_CAL                              (0x1<<6) // The cdfe force calibration enable.  1: enable force cdfe calibration.  0: disable force cdfe calibration.  Note: Force cdfe calibration is only enabled when force edfe calibration is also enabled.
27200     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_RATE_CHANGE_CAL_SHIFT                        6
27201     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_EI_EXIT_CAL                                  (0x1<<7) // EI exit cdfe calibration enable.                                                                                                   1: the cdfe calibration is enabled when EI exits and when rate is  2'b01 or 2'b10.                                  0: the cdfe calibration is disabled when EI exits.                                                                    Note: EI exit cdfe calibration is only enabled when EI exit edfe calibration is also enabled.
27202     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X203_CDFE_LN_EI_EXIT_CAL_SHIFT                            7
27203 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204                                                          0x002330UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27204     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_CONT_CAL                                     (0x1<<0) // Continuous cdfe calibration enable.                                                                                            1: the continuous cdfe calibration is enabled when the rate is  2'b01 or 2'b10.                                  0: the continuous cdfe calibration is disabled.                                                                        Note: Continuout cdfe calibration is only enabled when continuous edfe calibration is also enabled.
27205     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_CONT_CAL_SHIFT                               0
27206     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL                         (0x1<<1) // Enables cdfe calibration during Txeq adaptation phase.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
27207     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_ADAPT_CAL_SHIFT                   1
27208     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL                          (0x1<<2) // Enables cdfe calibration post Txeq adaptation.                                                                                            1: the cdfe calibration is enabled when the rate is  2'b10.                                  0: the cdfe calibration is disabled.
27209     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_TXEQ_RXEQ_CAL_SHIFT                    2
27210     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_CAL_EN                                 (0x1<<3) // Enables the cdfe calibration in rate3.  1: enables cdfe calibration.  0: disables cdfe calibration.
27211     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE3_CAL_EN_SHIFT                           3
27212     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE2_CAL_EN                                 (0x1<<4) // Enables the cdfe calibration in rate2.  1: enables cdfe calibration.  0: disables cdfe calibration.
27213     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_CDFE_LN_RATE2_CAL_EN_SHIFT                           4
27214     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_UNUSED_0                                             (0x7<<5) // reserved
27215     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X204_UNUSED_0_SHIFT                                       5
27216 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X205                                                          0x002334UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
27217 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X206                                                          0x002338UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
27218 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X207                                                          0x00233cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
27219 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208                                                          0x002340UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27220     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_UNUSED_0                                             (0x7f<<0) // reserved
27221     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_UNUSED_0_SHIFT                                       0
27222     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_AHB_CDFE_COARSE_DLL_OV_EN                            (0x1<<7) // cdfe coarse dll overwrite enable.  1: enable coarse dll overwrite for cdfe.  0: disable coarse dll overwrite for cdfe.
27223     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X208_AHB_CDFE_COARSE_DLL_OV_EN_SHIFT                      7
27224 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X213                                                          0x002354UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during txeq adaptation phase in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
27225 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X214                                                          0x002358UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during post  txeq adaptation  in rate3 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
27226 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X215                                                          0x00235cUL //Access:RW   DataWidth:0x8   Enables for various cdfe component during init cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
27227 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X216                                                          0x002360UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during continuos cal in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
27228 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X217                                                          0x002364UL //Access:RW   DataWidth:0x8   Enables for various cdfe component during re-calibration in rate2 bit[0] : enables/disables dll coarse calibration bit[1] : enables/disables dll fine calibration bit[2] : enables/disables dlev calibration bit[3] : enables/disables tap1 calibration bit[4] : enables/disables tap2 calibration bit[5] : enables/disables tap3 calibration bit[6] : enables/disables tap4 calibration bit[7] : enables/disables tap5 calibration  Chips: K2
27229 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X220                                                          0x002370UL //Access:RW   DataWidth:0x8   Start value for dlev_ref.  Chips: K2
27230 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X221                                                          0x002374UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27231     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0               (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
27232     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X221_CDFE_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT         0
27233     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X221_UNUSED_0                                             (0x7<<5) // reserved
27234     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X221_UNUSED_0_SHIFT                                       5
27235 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X222                                                          0x002378UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27236     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0           (0x1f<<0) // Enables copying of adapted tap values to cmp2 taps bit[0] : enables/disables copying to tap1 bit[1] : enables/disables copying to tap2 bit[2] : enables/disables copying to tap3 bit[3] : enables/disables copying to tap4 bit[4] : enables/disables copying to tap5
27237     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X222_CDFE_NON_ADAPTATION_EDGE_CMP_TAP_SEL_O_4_0_SHIFT     0
27238     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X222_UNUSED_0                                             (0x7<<5) // reserved
27239     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X222_UNUSED_0_SHIFT                                       5
27240 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X223                                                          0x00237cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27241     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X223_AHB_CDFE_CMP1_TAP1_OFFSET                            (0x7f<<0) // Override for CMP1 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[1]
27242     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X223_AHB_CDFE_CMP1_TAP1_OFFSET_SHIFT                      0
27243     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X223_UNUSED_0                                             (0x1<<7) // reserved
27244     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X223_UNUSED_0_SHIFT                                       7
27245 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X224                                                          0x002380UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27246     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[2]
27247     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X224_AHB_CDFE_CMP1_TAP2_OFFSET_5_0_SHIFT                  0
27248     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X224_UNUSED_0                                             (0x3<<6) // reserved
27249     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X224_UNUSED_0_SHIFT                                       6
27250 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X225                                                          0x002384UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27251     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[3]
27252     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X225_AHB_CDFE_CMP1_TAP3_OFFSET_5_0_SHIFT                  0
27253     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X225_UNUSED_0                                             (0x3<<6) // reserved
27254     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X225_UNUSED_0_SHIFT                                       6
27255 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X226                                                          0x002388UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27256     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP1 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[4]
27257     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X226_AHB_CDFE_CMP1_TAP4_OFFSET_5_0_SHIFT                  0
27258     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X226_UNUSED_0                                             (0x3<<6) // reserved
27259     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X226_UNUSED_0_SHIFT                                       6
27260 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X227                                                          0x00238cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27261     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X227_AHB_CDFE_CMP1_TAP5_OFFSET                            (0x3f<<0) // Override for CMP1 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[5]
27262     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X227_AHB_CDFE_CMP1_TAP5_OFFSET_SHIFT                      0
27263     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X227_UNUSED_0                                             (0x3<<6) // reserved
27264     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X227_UNUSED_0_SHIFT                                       6
27265 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X228                                                          0x002390UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27266     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X228_AHB_CDFE_CMP2_TAP1_OFFSET                            (0x7f<<0) // Override for CMP2 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[1]
27267     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X228_AHB_CDFE_CMP2_TAP1_OFFSET_SHIFT                      0
27268     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X228_UNUSED_0                                             (0x1<<7) // reserved
27269     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X228_UNUSED_0_SHIFT                                       7
27270 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X229                                                          0x002394UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27271     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[2]
27272     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X229_AHB_CDFE_CMP2_TAP2_OFFSET_5_0_SHIFT                  0
27273     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X229_UNUSED_0                                             (0x3<<6) // reserved
27274     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X229_UNUSED_0_SHIFT                                       6
27275 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X230                                                          0x002398UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27276     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[3]
27277     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X230_AHB_CDFE_CMP2_TAP3_OFFSET_5_0_SHIFT                  0
27278     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X230_UNUSED_0                                             (0x3<<6) // reserved
27279     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X230_UNUSED_0_SHIFT                                       6
27280 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X231                                                          0x00239cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27281     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP2 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[4]
27282     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X231_AHB_CDFE_CMP2_TAP4_OFFSET_5_0_SHIFT                  0
27283     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X231_UNUSED_0                                             (0x3<<6) // reserved
27284     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X231_UNUSED_0_SHIFT                                       6
27285 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X232                                                          0x0023a0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27286     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X232_AHB_CDFE_CMP2_TAP5_OFFSET                            (0x3f<<0) // Override for CMP2 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[5]
27287     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X232_AHB_CDFE_CMP2_TAP5_OFFSET_SHIFT                      0
27288     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X232_UNUSED_0                                             (0x3<<6) // reserved
27289     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X232_UNUSED_0_SHIFT                                       6
27290 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X233                                                          0x0023a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27291     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X233_AHB_CDFE_CMP3_TAP1_OFFSET                            (0x7f<<0) // Override for CMP3 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[1]
27292     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X233_AHB_CDFE_CMP3_TAP1_OFFSET_SHIFT                      0
27293     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X233_UNUSED_0                                             (0x1<<7) // reserved
27294     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X233_UNUSED_0_SHIFT                                       7
27295 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X234                                                          0x0023a8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27296     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[2]
27297     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X234_AHB_CDFE_CMP3_TAP2_OFFSET_5_0_SHIFT                  0
27298     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X234_UNUSED_0                                             (0x3<<6) // reserved
27299     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X234_UNUSED_0_SHIFT                                       6
27300 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X235                                                          0x0023acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27301     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[3]
27302     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X235_AHB_CDFE_CMP3_TAP3_OFFSET_5_0_SHIFT                  0
27303     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X235_UNUSED_0                                             (0x3<<6) // reserved
27304     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X235_UNUSED_0_SHIFT                                       6
27305 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X236                                                          0x0023b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27306     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP3 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[4]
27307     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X236_AHB_CDFE_CMP3_TAP4_OFFSET_5_0_SHIFT                  0
27308     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X236_UNUSED_0                                             (0x3<<6) // reserved
27309     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X236_UNUSED_0_SHIFT                                       6
27310 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X237                                                          0x0023b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27311     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X237_AHB_CDFE_CMP3_TAP5_OFFSET                            (0x3f<<0) // Override for CMP3 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[5]
27312     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X237_AHB_CDFE_CMP3_TAP5_OFFSET_SHIFT                      0
27313     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X237_UNUSED_0                                             (0x3<<6) // reserved
27314     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X237_UNUSED_0_SHIFT                                       6
27315 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X238                                                          0x0023b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27316     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X238_AHB_CDFE_CMP4_TAP1_OFFSET                            (0x7f<<0) // Override for CMP4 TAP1 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[1]
27317     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X238_AHB_CDFE_CMP4_TAP1_OFFSET_SHIFT                      0
27318     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X238_UNUSED_0                                             (0x1<<7) // reserved
27319     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X238_UNUSED_0_SHIFT                                       7
27320 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X239                                                          0x0023bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27321     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP2 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[2]
27322     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X239_AHB_CDFE_CMP4_TAP2_OFFSET_5_0_SHIFT                  0
27323     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X239_UNUSED_0                                             (0x3<<6) // reserved
27324     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X239_UNUSED_0_SHIFT                                       6
27325 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X240                                                          0x0023c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27326     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP3 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[3]
27327     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X240_AHB_CDFE_CMP4_TAP3_OFFSET_5_0_SHIFT                  0
27328     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X240_UNUSED_0                                             (0x3<<6) // reserved
27329     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X240_UNUSED_0_SHIFT                                       6
27330 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X241                                                          0x0023c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27331     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0                        (0x3f<<0) // Override for CMP4 TAP4 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[4]
27332     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X241_AHB_CDFE_CMP4_TAP4_OFFSET_5_0_SHIFT                  0
27333     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X241_UNUSED_0                                             (0x3<<6) // reserved
27334     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X241_UNUSED_0_SHIFT                                       6
27335 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X242                                                          0x0023c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27336     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X242_AHB_CDFE_CMP4_TAP5_OFFSET                            (0x3f<<0) // Override for CMP4 TAP5 calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[5]
27337     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X242_AHB_CDFE_CMP4_TAP5_OFFSET_SHIFT                      0
27338     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X242_UNUSED_0                                             (0x3<<6) // reserved
27339     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X242_UNUSED_0_SHIFT                                       6
27340 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X243                                                          0x0023ccUL //Access:RW   DataWidth:0x8   Override for CMP1 main calibrated offset value. Enabled by qahb_cdfe_cmp1_preset_offset_5_0[0]  Chips: K2
27341 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X244                                                          0x0023d0UL //Access:RW   DataWidth:0x8   Override for CMP2 main calibrated offset value. Enabled by qahb_cdfe_cmp2_preset_offset_5_0[0]  Chips: K2
27342 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X245                                                          0x0023d4UL //Access:RW   DataWidth:0x8   Override for CMP3 main calibrated offset value. Enabled by qahb_cdfe_cmp3_preset_offset_5_0[0]  Chips: K2
27343 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X246                                                          0x0023d8UL //Access:RW   DataWidth:0x8   Override for CMP4 main calibrated offset value. Enabled by qahb_cdfe_cmp4_preset_offset_5_0[0]  Chips: K2
27344 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X247                                                          0x0023dcUL //Access:RW   DataWidth:0x8     Chips: K2
27345 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248                                                          0x0023e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27346     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_AHB_CDFE_DLL_FINE_MASK_9_8                           (0x3<<0) //
27347     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_AHB_CDFE_DLL_FINE_MASK_9_8_SHIFT                     0
27348     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT                         (0xf<<2) //
27349     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_AHB_CDFE_FINE_DLL_EDGE_SHIFT_SHIFT                   2
27350     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_UNUSED_0                                             (0x3<<6) // reserved
27351     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X248_UNUSED_0_SHIFT                                       6
27352 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249                                                          0x0023e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27353     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_ERR_SMPL_SHIFT                              (0xf<<0) //
27354     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_ERR_SMPL_SHIFT_SHIFT                        0
27355     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_FINE_DLL_OV_EN                              (0x1<<4) // cdfe fine dll overwrite enable.  1: enable fine dll overwrite for cdfe.  0: disable fine dll overwrite for cdfe.
27356     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_AHB_CDFE_FINE_DLL_OV_EN_SHIFT                        4
27357     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_UNUSED_0                                             (0x7<<5) // reserved
27358     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X249_UNUSED_0_SHIFT                                       5
27359 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250                                                          0x0023e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27360     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8                    (0x1<<0) //
27361     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK90_8_SHIFT              0
27362     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8                   (0x1<<1) //
27363     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE2_EYE_DLY_TO_CLK270_8_SHIFT             1
27364     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8                    (0x1<<2) //
27365     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK90_8_SHIFT              2
27366     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8                   (0x1<<3) //
27367     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_AHB_CDFE_RATE3_EYE_DLY_TO_CLK270_8_SHIFT             3
27368     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_UNUSED_0                                             (0xf<<4) // reserved
27369     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X250_UNUSED_0_SHIFT                                       4
27370 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X251                                                          0x0023ecUL //Access:RW   DataWidth:0x8     Chips: K2
27371 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X252                                                          0x0023f0UL //Access:RW   DataWidth:0x8     Chips: K2
27372 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X253                                                          0x0023f4UL //Access:RW   DataWidth:0x8     Chips: K2
27373 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X254                                                          0x0023f8UL //Access:RW   DataWidth:0x8     Chips: K2
27374 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255                                                          0x0023fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27375     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_EN                                       (0x1<<0) // Override enable for CDFE calibration direction
27376     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_EN_SHIFT                                 0
27377     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_VAL                                      (0x1<<1) // Override value for CDFE calibration direction
27378     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_CDFE_DIR_OV_VAL_SHIFT                                1
27379     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA270_OVR_EN_O                           (0x1<<2) // Override enable for CDFE output eye_ena270. When 1, AHB value is passed to PMA
27380     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA270_OVR_EN_O_SHIFT                     2
27381     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA90_OVR_EN_O                            (0x1<<3) // Override enable for CDFE output eye_ena90. When 1, AHB value is passed to PMA
27382     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_ENA90_OVR_EN_O_SHIFT                      3
27383     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_PHD_ENA_OVR_EN_O                              (0x1<<4) // Override enable for CDFE output phd_ena. When 1, AHB value is passed to PMA
27384     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_PHD_ENA_OVR_EN_O_SHIFT                        4
27385     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_DLY_OVR_EN_O                              (0x1<<5) // cdfe eye delay overwrite enable.  1: enable eye delay overwrite for cdfe.  0: disable eye delay overwrite for cdfe.
27386     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_DLY_OVR_EN_O_SHIFT                        5
27387     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O                          (0x1<<6) // Override enable for CDFE output eye_sgn_rst. When 1, AHB value is passed to PMA
27388     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_PMA_LN_EYE_SGN_RST_OVR_EN_O_SHIFT                    6
27389     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_UNUSED_0                                             (0x1<<7) // reserved
27390     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X255_UNUSED_0_SHIFT                                       7
27391 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X256                                                          0x002400UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK90.  Chips: K2
27392 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257                                                          0x002404UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27393     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8                       (0x1<<0) // cdfe eye delay count overwrite value for CLK90.
27394     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_AHB_CDFE_EYE_DLY_TO_CLK90_OV_8_SHIFT                 0
27395     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0               (0x7f<<1) // This register represents the maximum comparator offset from the midpoint code 127/128 that must be met for the comparator to be selected as adaptation comparator during dlev and tap adaptation.
27396     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X257_CDFE_DLEV_CMP_SEL_MAX_ABS_THRESH_O_6_0_SHIFT         1
27397 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X258                                                          0x002408UL //Access:RW   DataWidth:0x8   cdfe eye delay count overwrite value for CLK270.  Chips: K2
27398 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259                                                          0x00240cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27399     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8                      (0x1<<0) // cdfe eye delay count overwrite value for CLK270.
27400     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_EYE_DLY_TO_CLK270_OV_8_SHIFT                0
27401     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_DLEV_OV_EN                                  (0x1<<1) // cdfe dlev overwrite enable.  1: enable dlev overwrite for cdfe.  0: disable dlev overwrite for cdfe.
27402     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_AHB_CDFE_DLEV_OV_EN_SHIFT                            1
27403     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0                    (0x1f<<2) // Register override for overriding adaptation comparator select bit [0] : override enable bit [4:1] : override value
27404     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_SEL_OVR_O_4_0_SHIFT              2
27405     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8               (0x1<<7) // Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value
27406     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X259_CDFE_DLEV_ADAPT_CMP_OFFSET_VAL_OVR_O_8_SHIFT         7
27407 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X260                                                          0x002410UL //Access:RW   DataWidth:0x8   Register override for overriding adaptation comparator offset value bit [0] : override enable bit [8:1] : override value  Chips: K2
27408 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X261                                                          0x002414UL //Access:RW   DataWidth:0x8   cdfe dlevn overwrite value.  Chips: K2
27409 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X262                                                          0x002418UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27410     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X262_AHB_CDFE_TAP_OV_EN                                   (0x1f<<0) // cdfe tap1~5 overwrite enable.                                                                                                    Bit[0]: enable tap1 overwrite for cdfe. Bit[1]: enable tap2 overwrite for cdfe Bit[2]: enable tap3 overwrite for cdfe.  Bit[3]: enable tap4 overwrite for cdfe. Bit[4]: enable tap5 overwrite for cdfe.
27411     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X262_AHB_CDFE_TAP_OV_EN_SHIFT                             0
27412     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X262_UNUSED_0                                             (0x7<<5) // reserved
27413     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X262_UNUSED_0_SHIFT                                       5
27414 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X263                                                          0x00241cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27415     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X263_AHB_CDFE_TAP1_OV                                     (0x7f<<0) // cdfe tap1 overwrite value
27416     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X263_AHB_CDFE_TAP1_OV_SHIFT                               0
27417     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X263_UNUSED_0                                             (0x1<<7) // reserved
27418     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X263_UNUSED_0_SHIFT                                       7
27419 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X264                                                          0x002420UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27420     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X264_AHB_CDFE_TAP2_OV                                     (0x3f<<0) // cdfe tap2 overwrite value
27421     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X264_AHB_CDFE_TAP2_OV_SHIFT                               0
27422     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X264_UNUSED_0                                             (0x3<<6) // reserved
27423     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X264_UNUSED_0_SHIFT                                       6
27424 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X265                                                          0x002424UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27425     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X265_AHB_CDFE_TAP3_OV                                     (0x3f<<0) // cdfe tap3 overwrite value
27426     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X265_AHB_CDFE_TAP3_OV_SHIFT                               0
27427     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X265_UNUSED_0                                             (0x3<<6) // reserved
27428     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X265_UNUSED_0_SHIFT                                       6
27429 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X266                                                          0x002428UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27430     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X266_AHB_CDFE_TAP4_OV                                     (0x3f<<0) // cdfe tap4 overwrite value
27431     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X266_AHB_CDFE_TAP4_OV_SHIFT                               0
27432     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X266_UNUSED_0                                             (0x3<<6) // reserved
27433     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X266_UNUSED_0_SHIFT                                       6
27434 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267                                                          0x00242cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27435     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_AHB_CDFE_TAP5_OV                                     (0x3f<<0) // cdfe tap5 overwrite value
27436     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_AHB_CDFE_TAP5_OV_SHIFT                               0
27437     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_UNUSED_0                                             (0x1<<6) // reserved
27438     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_UNUSED_0_SHIFT                                       6
27439     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O               (0x1<<7) // Enables FW enable control for TAP adapt using DLEV
27440     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X267_CDFE_TAP_ADAPT_USING_DLEV_FI_CTRL_EN_O_SHIFT         7
27441 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268                                                          0x002430UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27442     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O                       (0x1<<0) // Instucts to start TAP adapt using DLEV in FW enabled mode
27443     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_TAP_ADAPT_USING_DLEV_GO_O_SHIFT                 0
27444     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O             (0x1<<1) //
27445     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_RESULT_DURING_RECAL_O_SHIFT       1
27446     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O         (0x1<<2) //
27447     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_CDFE_LOAD_PREVIOUS_ADAPTED_VAL_BEFORE_DLEV_O_SHIFT   2
27448     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_UNUSED_0                                             (0xf<<3) // reserved
27449     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_UNUSED_0_SHIFT                                       3
27450     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_AHB_CDFE_DFE_VAL_OVR_EN_O                            (0x1<<7) //
27451     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X268_AHB_CDFE_DFE_VAL_OVR_EN_O_SHIFT                      7
27452 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269                                                          0x002434UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27453     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O                     (0x1<<0) //
27454     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_TAP_N_OFST_CAPTURE_EN_O_SHIFT               0
27455     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_STROBE_EN_O                                 (0x1<<1) //
27456     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_STROBE_EN_O_SHIFT                           1
27457     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_CMP_ENA_O                                   (0xf<<2) //
27458     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_AHB_CDFE_CMP_ENA_O_SHIFT                             2
27459     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_UNUSED_0                                             (0x3<<6) // reserved
27460     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X269_UNUSED_0_SHIFT                                       6
27461 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X270                                                          0x002438UL //Access:RW   DataWidth:0x8     Chips: K2
27462 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271                                                          0x00243cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27463     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0                          (0x1f<<0) //
27464     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_AHB_CDFE_DIV_SIGN_BIT_O_4_0_SHIFT                    0
27465     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O                  (0x1<<5) // Forces the positive dlev training pattern to be used
27466     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_POS_DLEV_TRAINING_PATT_O_SHIFT            5
27467     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O                  (0x1<<6) // Forces the negative dlev training pattern to be used
27468     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_CDFE_FORCE_NEG_DLEV_TRAINING_PATT_O_SHIFT            6
27469     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_UNUSED_0                                             (0x1<<7) // reserved
27470     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X271_UNUSED_0_SHIFT                                       7
27471 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272                                                          0x002440UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27472     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP1 adapted value
27473     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SCALE_O_2_0_SHIFT                          0
27474     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP1 adapted value
27475     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X272_CDFE_TAP1_SHIFT_O_4_0_SHIFT                          3
27476 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273                                                          0x002444UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27477     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP2 adapted value
27478     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SCALE_O_2_0_SHIFT                          0
27479     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP2 adapted value
27480     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X273_CDFE_TAP2_SHIFT_O_4_0_SHIFT                          3
27481 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274                                                          0x002448UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27482     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP3 adapted value
27483     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SCALE_O_2_0_SHIFT                          0
27484     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP3 adapted value
27485     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X274_CDFE_TAP3_SHIFT_O_4_0_SHIFT                          3
27486 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275                                                          0x00244cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27487     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP4 adapted value
27488     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SCALE_O_2_0_SHIFT                          0
27489     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP4 adapted value
27490     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X275_CDFE_TAP4_SHIFT_O_4_0_SHIFT                          3
27491 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276                                                          0x002450UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27492     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SCALE_O_2_0                                (0x7<<0) // Scale factor CDFE TAP5 adapted value
27493     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SCALE_O_2_0_SHIFT                          0
27494     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SHIFT_O_4_0                                (0x1f<<3) // Shift factor CDFE TAP5 adapted value
27495     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X276_CDFE_TAP5_SHIFT_O_4_0_SHIFT                          3
27496 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277                                                          0x002454UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27497     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_RA_OVR_O                                (0x3<<0) // Bit 0:  Override enable for msm_reset_ra Bit 1: Override msm_reset_ra
27498     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_RA_OVR_O_SHIFT                          0
27499     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_P2S_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_p2s Bit 1: Override msm_reset_p2s
27500     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_P2S_OVR_O_SHIFT                         2
27501     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_LNREGH_OVR_O                            (0x3<<4) // Bit 0:  Override enable for msm_reset_lnregh Bit 1: Override msm_reset_lnregh
27502     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_LNREGH_OVR_O_SHIFT                      4
27503     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_LNREG_OVR_O                             (0x3<<6) // Bit 0:  Override enable for msm_reset_lnreg Bit 1: Override msm_reset_lnreg
27504     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X277_LN_MSM_RESET_LNREG_OVR_O_SHIFT                       6
27505 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278                                                          0x002458UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27506     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_RESET_CDR_OVR_O                               (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr Bit 1: Override msm_reset_cdr
27507     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_RESET_CDR_OVR_O_SHIFT                         0
27508     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_RESET_DFE_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_dfe Bit 1: Override msm_reset_dfe
27509     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_RESET_DFE_OVR_O_SHIFT                         2
27510     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_PD_LNREGH_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_pd_lnregh Bit 1: Override msm_pd_lnregh
27511     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_PD_LNREGH_OVR_O_SHIFT                         4
27512     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_PD_VCO_BUF_OVR_O                              (0x3<<6) // Bit 0:  Override enable for msm_pd_vco_buf Bit 1: Override msm_pd_vco_buf
27513     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X278_LN_MSM_PD_VCO_BUF_OVR_O_SHIFT                        6
27514 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279                                                          0x00245cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27515     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RESET_CDR_GCRX_OVR_O                          (0x3<<0) // Bit 0:  Override enable for msm_reset_cdr_gcrx Bit 1: Override msm_reset_cdr_gcrx
27516     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RESET_CDR_GCRX_OVR_O_SHIFT                    0
27517     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RXGATE_EN_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_rxgate_en Bit 1: Override msm_rxgate_en
27518     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RXGATE_EN_OVR_O_SHIFT                         2
27519     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RESET_VCO_OVR_O                               (0x3<<4) // Bit 0:  Override enable for msm_reset_vco Bit 1: Override msm_reset_vco
27520     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_RESET_VCO_OVR_O_SHIFT                         4
27521     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_IDDQ_SD_OVR_O                                 (0x3<<6) // Bit 0:  Override enable for msm_iddq_sd Bit 1: Override msm_iddq_sd
27522     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X279_LN_MSM_IDDQ_SD_OVR_O_SHIFT                           6
27523 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280                                                          0x002460UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27524     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_PD_DFE_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_pd_dfe Bit 1: Override msm_pd_dfe
27525     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_PD_DFE_OVR_O_SHIFT                            0
27526     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_PD_DFE_BIAS_OVR_O                             (0x3<<2) // Bit 0:  Override enable for msm_pd_dfe_bias Bit 1: Override msm_pd_dfe_bias
27527     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_PD_DFE_BIAS_OVR_O_SHIFT                       2
27528     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O                           (0x3<<4) // Bit 0:  Override enable for msm_txdrv_lp_idle Bit 1: Override msm_txdrv_lp_idle
27529     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_TXDRV_LP_IDLE_OVR_O_SHIFT                     4
27530     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O                         (0x3<<6) // Bit 0:  Override enable for msm_txreg_bleed_ena Bit 1: Override msm_txreg_bleed_ena
27531     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X280_LN_MSM_TXREG_BLEED_ENA_OVR_O_SHIFT                   6
27532 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281                                                          0x002464UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27533     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_TXREG_OVR_O                                (0x3<<0) // Bit 0:  Override enable for msm_pd_txreg Bit 1: Override msm_pd_txreg
27534     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_TXREG_OVR_O_SHIFT                          0
27535     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_LNREG_OVR_O                                (0x3<<2) // Bit 0:  Override enable for msm_pd_lnreg Bit 1: Override msm_pd_lnreg
27536     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_LNREG_OVR_O_SHIFT                          2
27537     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_P2S_OVR_O                                  (0x3<<4) // Bit 0:  Override enable for pd_p2s Bit 1: Override pd_p2s
27538     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_P2S_OVR_O_SHIFT                            4
27539     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_RA_OVR_O                                   (0x3<<6) // Bit 0:  Override enable for pd_ra Bit 1: Override pd_ra
27540     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X281_LN_MSM_PD_RA_OVR_O_SHIFT                             6
27541 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282                                                          0x002468UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27542     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_UNUSED_0                                             (0x3<<0) // reserved
27543     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_UNUSED_0_SHIFT                                       0
27544     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_SLV_BIAS_OVR_O                             (0x3<<2) // Bit 0:  Override enable for pd_slv_bias Bit 1: Override pd_slv_bias
27545     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_SLV_BIAS_OVR_O_SHIFT                       2
27546     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_TXDRV_OVR_O                                (0x3<<4) // Bit 0:  Override enable for pd_txdrv Bit 1: Override pd_txdrv
27547     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_TXDRV_OVR_O_SHIFT                          4
27548     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_VCO_OVR_O                                  (0x3<<6) // Bit 0:  Override enable for msm_pd_vco Bit 1: Override msm_pd_vco
27549     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X282_LN_MSM_PD_VCO_OVR_O_SHIFT                            6
27550 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283                                                          0x00246cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27551     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_CDR_EN_OVR_O                                  (0x3<<0) // Bit 0:  Override enable for msm_cdr_en Bit 1: Override msm_cdr_en
27552     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_CDR_EN_OVR_O_SHIFT                            0
27553     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_RESET_S2P_OVR_O                               (0x3<<2) // Bit 0:  Override enable for msm_reset_s2p Bit 1: Override msm_reset_s2p
27554     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_RESET_S2P_OVR_O_SHIFT                         2
27555     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_RXCLK_EN_OVR_O                                (0x3<<4) // Bit 0:  Override enable for msm_rxclk_en Bit 1: Override msm_rxclk_en
27556     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_RXCLK_EN_OVR_O_SHIFT                          4
27557     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_WORD_OVR_O                                    (0x3<<6) // Bit 0:  Override enable for msm_word Bit 1: Override msm_word
27558     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X283_LN_MSM_WORD_OVR_O_SHIFT                              6
27559 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284                                                          0x002470UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27560     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RATE_OVR_O                                    (0x7<<0) // Bit 0:  Override enable for msm_rate Bit [2:1] : Override msm_rate
27561     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RATE_OVR_O_SHIFT                              0
27562     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RXVCODIV_OVR_O                                (0x7<<3) // Bit 0:  Override enable for msm_rxvcodiv Bit [2:1] : Override msm_rxvcodiv
27563     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RXVCODIV_OVR_O_SHIFT                          3
27564     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O                         (0x3<<6) // Not currently used
27565     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X284_LN_MSM_RESET_TX_CLKDIV_OVR_O_SHIFT                   6
27566 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X285                                                          0x002474UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27567     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X285_LN_MSM_TXVCODIV_OVR_O                                (0x7<<0) // Bit 0:  Override enable for msm_txvcodiv Bit [2:1] : Override msm_txvcodiv
27568     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X285_LN_MSM_TXVCODIV_OVR_O_SHIFT                          0
27569     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X285_UNUSED_0                                             (0x1f<<3) // reserved
27570     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X285_UNUSED_0_SHIFT                                       3
27571 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301                                                          0x0024b4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27572     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_RX_SRC_O                                             (0x1<<0) // RX loopback mux input select. 0 - Output of mux is normal RX data path. 1 - Output of mux is output from 8b/10b encoder.
27573     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_RX_SRC_O_SHIFT                                       0
27574     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_POL_O                                          (0x1<<1) // TReg0 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
27575     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_POL_O_SHIFT                                    1
27576     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_BIT_O                                          (0x1<<2) // TReg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
27577     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_BIT_O_SHIFT                                    2
27578     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_WORD_O                                         (0x1<<3) // TReg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
27579     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_TREG0_WORD_O_SHIFT                                   3
27580     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_DMUX_TXA_SEL_O_1_0                                   (0x3<<4) // Transmit mux A data input select.
27581     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_DMUX_TXA_SEL_O_1_0_SHIFT                             4
27582     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_P2S_RBUF_AUTOFIX_O                                   (0x1<<6) // P2S ring buffer autofix enable. 0 - Ring buffer will not attempt to fix overflow / underflows 1 - Ring buffer will reset upon detection of overflow/underflow
27583     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_P2S_RBUF_AUTOFIX_O_SHIFT                             6
27584     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_UNUSED_0                                             (0x1<<7) // reserved
27585     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X301_UNUSED_0_SHIFT                                       7
27586 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302                                                          0x0024b8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27587     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_POL_O                                          (0x1<<0) // TReg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
27588     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_POL_O_SHIFT                                    0
27589     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_BIT_O                                          (0x1<<1) // TReg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
27590     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_BIT_O_SHIFT                                    1
27591     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_WORD_O                                         (0x1<<2) // TReg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
27592     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_TREG1_WORD_O_SHIFT                                   2
27593     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_POL_O                                           (0x1<<3) // Reg1 data bank polarity select. 0 - Data is unmodified. 1 - Data polarity is reversed.
27594     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_POL_O_SHIFT                                     3
27595     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_BIT_O                                           (0x1<<4) // Reg1 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
27596     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_BIT_O_SHIFT                                     4
27597     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_WORD_O                                          (0x1<<5) // Reg1 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
27598     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG1_WORD_O_SHIFT                                    5
27599     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG0_POL_O                                           (0x1<<6) // Used as Reg0 polarity select
27600     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_REG0_POL_O_SHIFT                                     6
27601     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_UNUSED_0                                             (0x1<<7) // reserved
27602     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X302_UNUSED_0_SHIFT                                       7
27603 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303                                                          0x0024bcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27604     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_BIT_O                                           (0x1<<0) // Reg0 data bank bit order select. 0 - Normal bit order used. Bit order unmodified. 1 - Reversed bit order used. Bit order in each word reversed.
27605     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_BIT_O_SHIFT                                     0
27606     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_WORD_O                                          (0x1<<1) // Reg0 data bank word order select. 0 - Normal word order used - words are not modified. 1 - Flipped word order used - lower and upper words are flipped.
27607     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_REG0_WORD_O_SHIFT                                    1
27608     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_DMUX_TXB_SEL_O_2_0                                   (0x7<<2) // Transmit mux B data input select enable.
27609     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_DMUX_TXB_SEL_O_2_0_SHIFT                             2
27610     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TX_CTRL_O_24                                         (0x1<<5) // Bit 24: txdrv_c2_in[3]
27611     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TX_CTRL_O_24_SHIFT                                   5
27612     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_WIDTH_CHNG_EN_O                                      (0x1<<6) // Enable bit for width_chng module
27613     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_WIDTH_CHNG_EN_O_SHIFT                                6
27614     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TXTERM_CAL_SEQ_EN_O                                  (0x1<<7) // Txterm calibration enable
27615     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X303_TXTERM_CAL_SEQ_EN_O_SHIFT                            7
27616 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304                                                          0x0024c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27617     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_TXTERM_CAL_RSEL                                      (0x7<<0) // tx termination calibration comparator threshold select
27618     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_TXTERM_CAL_RSEL_SHIFT                                0
27619     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_LN_RXBIT_STRIP_O                                 (0x3<<3) // Bit stripping on rxdata from PMA to PCS 2?b00: no bit stripping 2?b01: 2x bit stripping 2?b10: reserved 2?b11: 4x bit stripping
27620     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_LN_RXBIT_STRIP_O_SHIFT                           3
27621     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_MAC_WIDTH_O                                      (0x3<<5) // Data width selector for PCS/MAC interface. 2?b00: GigE or XAUI 2?b01: GigE or XAUI 2?b10: RXAUI 2?b11: XFI
27622     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_AHB_MAC_WIDTH_O_SHIFT                                5
27623     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_UNUSED_0                                             (0x1<<7) // reserved
27624     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X304_UNUSED_0_SHIFT                                       7
27625 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305                                                          0x0024c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27626     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_AHB_TXMAC_THRESHOLD_O                                (0x3<<0) // An internal FIFO is included to handle the communication between the external 64-bit data and the internal 20-bit data. The reading operation will begin only when the difference between the write pointer and read pointer for this FIFO reaches ahb_txmac_threshold_o.
27627     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_AHB_TXMAC_THRESHOLD_O_SHIFT                          0
27628     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_AHB_LN_TXBIT_REPEAT_O                                (0x3<<2) // Bit stuffing on txdata from PCS to PMA, bit stripping on rxdata from PMA to PCS 2?b00: no bit stuffing nor stripping 2?b01: 2x bit stuffing and stripping 2?b10: reserved 2?b11: 4x bit stuffing and stripping
27629     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_AHB_LN_TXBIT_REPEAT_O_SHIFT                          2
27630     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_MODE_8B_O_1_0                                        (0x3<<4) // 8b mode control, blocks prior AFE side of 8b/10b enc/dec 0 - Data word is 10 bits 1 - Data word 8 bits
27631     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_MODE_8B_O_1_0_SHIFT                                  4
27632     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_ENC_EN_O                                             (0x1<<6) // 8b/10b encoder enable.
27633     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_ENC_EN_O_SHIFT                                       6
27634     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_DEC_EN_O                                             (0x1<<7) // 8b/10b decoder enable.
27635     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X305_DEC_EN_O_SHIFT                                       7
27636 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306                                                          0x0024c8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27637     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_AHB_TX_CDAC_OVR                                      (0xf<<0) // TX termination calibration DAC override. Signal ahb_tx_term_en_cal_ovr must also be asserted to take effect.
27638     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_AHB_TX_CDAC_OVR_SHIFT                                0
27639     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_LN_COMMON_SYNC_TXCLK_EN_O                            (0x1<<4) // Per lane common synchronous clock between PMA, PCS and SoC logic enable bit. 1: in NORM state, lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA or its divided down version and this clock can be used as a common synchronous clock between PMA, PCS and SoC logic. In other state, it is switched to cmu_ck_soc_o[1]. 0: lnX_ck_txb_o is swtiched to cmu_ck_soc_o[1].
27640     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_LN_COMMON_SYNC_TXCLK_EN_O_SHIFT                      4
27641     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_UNUSED_0                                             (0x7<<5) // reserved
27642     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X306_UNUSED_0_SHIFT                                       5
27643 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307                                                          0x0024ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27644     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_LN_TO_CLK_TXB_WAIT_O                                 (0x1f<<0) // In per lane common synchronous clock mode, after the lnX_ck_txb_o is switched to the per lane transmit byte clock from PMA. The lnX_ok_o will get asserted after lnX_to_clk_txb_wait_o lnX_ck_txb_o cycles.
27645     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_LN_TO_CLK_TXB_WAIT_O_SHIFT                           0
27646     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_PIPE_EN_O                                            (0x1<<5) // PIPE interface block enable.
27647     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_PIPE_EN_O_SHIFT                                      5
27648     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_SAPIS_EN_O                                           (0x1<<6) // SAPIS interface block enable.
27649     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_SAPIS_EN_O_SHIFT                                     6
27650     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_USB_MODE                                             (0x1<<7) // Signal Detect USB mode enable
27651     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X307_USB_MODE_SHIFT                                       7
27652 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308                                                          0x0024d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27653     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_UNUSED_0                                             (0x1<<0) // reserved
27654     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_UNUSED_0_SHIFT                                       0
27655     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_ENC_CLR_ERR_O                                  (0x1<<1) // 128b/130b encoder clear error
27656     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_ENC_CLR_ERR_O_SHIFT                            1
27657     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_UNUSED_1                                             (0x1<<2) // reserved
27658     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_UNUSED_1_SHIFT                                       2
27659     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_EN_ERR_CHK_O                               (0x1<<3) // 130b/128b error check enable
27660     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_EN_ERR_CHK_O_SHIFT                         3
27661     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0                          (0x7<<4) // 130b/128b: number of OS indicating end of data
27662     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CHK_OS_NMBR_O_2_0_SHIFT                    4
27663     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CLR_ERR_O                                  (0x1<<7) // 130b/128b: clear error flag
27664     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X308_BLOCK_DEC_CLR_ERR_O_SHIFT                            7
27665 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309                                                          0x0024d4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27666     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0                        (0xf<<0) // 130b/128b: number of sync hdr errors before asserting sync error flag
27667     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_BLOCK_DEC_ERR_THRESHOLD_O_3_0_SHIFT                  0
27668     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0                         (0xf<<4) // 130b/128b: number of continuous blocks checked
27669     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X309_BLOCK_DEC_CHK_BLK_NMBR_O_3_0_SHIFT                   4
27670 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310                                                          0x0024d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27671     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_RSTN_O                                          (0x1<<0) // Synchronous clear for elastic buffer
27672     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_RSTN_O_SHIFT                                    0
27673     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_ALIGN_RSTN_O                                         (0x1<<1) // Synchronous clear for block/symbol aligner
27674     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_ALIGN_RSTN_O_SHIFT                                   1
27675     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_SKP_ADD_EN_O                                    (0x1<<2) // Elastic buffer SKP add enable
27676     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EBUF_SKP_ADD_EN_O_SHIFT                              2
27677     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_RBUF_RSTN_O                                          (0x1<<3) // TX FIFO synchronous reset
27678     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_RBUF_RSTN_O_SHIFT                                    3
27679     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_UNUSED_0                                             (0x1<<4) // reserved
27680     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_UNUSED_0_SHIFT                                       4
27681     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EN_SKPOS_ERR_O                                       (0x1<<5) // Enables skpos error status propagation in Gen3
27682     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_EN_SKPOS_ERR_O_SHIFT                                 5
27683     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_UNUSED_1                                             (0x3<<6) // reserved
27684     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X310_UNUSED_1_SHIFT                                       6
27685 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311                                                          0x0024dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27686     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_PIPE_LFREQ                                           (0x3f<<0) // LF value for full swing
27687     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_PIPE_LFREQ_SHIFT                                     0
27688     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_BLOCK_ALIGN_CTRL_O                               (0x1<<6) // Disables the primary input lnX_block_align_control
27689     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_BLOCK_ALIGN_CTRL_O_SHIFT                         6
27690     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_EIEOS_CHK_IN_LB_O                                (0x1<<7) // Disables the EIEOS check in loopback
27691     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X311_DIS_EIEOS_CHK_IN_LB_O_SHIFT                          7
27692 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312                                                          0x0024e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27693     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_COEF_FE_LIMIT_EN_O                                   (0x1<<0) // FE TxEq Co-efficient Limiting Enable control
27694     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_COEF_FE_LIMIT_EN_O_SHIFT                             0
27695     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_RXVALID_DIS_AT_RATE_CHG_O_0                          (0x1<<1) // Value 1 forces rxvalid to be deasserted during rate change to gen 3
27696     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_RXVALID_DIS_AT_RATE_CHG_O_0_SHIFT                    1
27697     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_P2S_RBUF_BUF_THRESH_O_3_0                            (0xf<<2) // TX FIFO: specifies how far write pointer need to be ahead of read pointer before almost_full_o is asserted
27698     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_P2S_RBUF_BUF_THRESH_O_3_0_SHIFT                      2
27699     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_UNUSED_0                                             (0x3<<6) // reserved
27700     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X312_UNUSED_0_SHIFT                                       6
27701 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313                                                          0x0024e4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27702     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_RX_GEARBOX_DISABLE_O                             (0x1<<0) // 0: enable rx_gearbox, 1: disable rx_gearbox
27703     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_RX_GEARBOX_DISABLE_O_SHIFT                       0
27704     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_TX_GEARBOX_DISABLE_O                             (0x1<<1) // 0: enable tx_gearbox, 1: disable tx_gearbox
27705     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_AHB_TX_GEARBOX_DISABLE_O_SHIFT                       1
27706     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_UNUSED_0                                             (0x3f<<2) // reserved
27707     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X313_UNUSED_0_SHIFT                                       2
27708 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314                                                          0x0024e8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27709     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_GEN1_OLD_RXDATA_SRC                                  (0x1<<0) // Mux select for data input to polbit_reg0  0:pma_ln_dfe_err_i , 1: pma_ln_rxdata_i
27710     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_GEN1_OLD_RXDATA_SRC_SHIFT                            0
27711     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN3_O                                      (0x1<<1) // To skip cdr calibration routines for PCIe gen3.  Can be used when PHY is operating in gen1,2 only.
27712     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN3_O_SHIFT                                1
27713     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN12_O                                     (0x1<<2) // To skip cdr calibration routines for PCIe gen1,2.  May not be needed in real scenario.
27714     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_SKIP_CDR_GEN12_O_SHIFT                               2
27715     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_AHB_LN_PD_RA_CISEL_OVR_O_0                           (0x1<<3) // Receive amplifier powerdown override, when cisel is high
27716     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_AHB_LN_PD_RA_CISEL_OVR_O_0_SHIFT                     3
27717     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_LN_P2S_RBUF_REALIGN_DIFF_O                           (0xf<<4) // In per lane common synchronous clock mode, ln_p2x_rbuf_realign_diff_o defines the starting difference between write pointer and read pointer when re aligning the pointer of TxFIFO.
27718     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X314_LN_P2S_RBUF_REALIGN_DIFF_O_SHIFT                     4
27719 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X315                                                          0x0024ecUL //Access:RW   DataWidth:0x8   Delays the beacon_ena propagation to PMA  Chips: K2
27720 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X316                                                          0x0024f0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27721     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O               (0xf<<0) // Delays the beacon_ena propagation to PMA
27722     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X316_AHB_BEACON_DELAYED_COUNT_NUMBER_11_8_O_SHIFT         0
27723     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X316_UNUSED_0                                             (0xf<<4) // reserved
27724     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X316_UNUSED_0_SHIFT                                       4
27725 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317                                                          0x0024f4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27726     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_ENA_O                             (0x1<<0) // Beacon Override Enable
27727     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_ENA_O_SHIFT                       0
27728     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_O                                 (0x1<<1) // Beacon Override
27729     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_AHB_BEACON_ENA_OVR_O_SHIFT                           1
27730     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_DEC_EN_OVR_O                                         (0x1<<2) // Enables 16b/20b decoder
27731     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_DEC_EN_OVR_O_SHIFT                                   2
27732     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_ENC_EN_OVR_O                                         (0x1<<3) // Enables 16b/20b encoder
27733     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_ENC_EN_OVR_O_SHIFT                                   3
27734     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_REGP_OVR_3_0                                         (0xf<<4) // Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
27735     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X317_REGP_OVR_3_0_SHIFT                                   4
27736 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318                                                          0x0024f8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27737     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_SIGDET_OVR_O_1_0                                     (0x3<<0) // Bit[0]: Overide value. Bit[1] :Override enable for signal detect output
27738     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_SIGDET_OVR_O_1_0_SHIFT                               0
27739     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_LN_OUT_OVR_1_0                                       (0x3<<2) // Override for CDR VCO calibration counter reset. Bit 1 enables the override, while bit 0 is the override value.
27740     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_LN_OUT_OVR_1_0_SHIFT                                 2
27741     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_RXEQ_SIGDET_1_0                                      (0x3<<4) // Override enable for DFE signal detect indicator input. Bit 1 is overide enable , 0 is overide value
27742     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_RXEQ_SIGDET_1_0_SHIFT                                4
27743     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_UNUSED_0                                             (0x3<<6) // reserved
27744     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X318_UNUSED_0_SHIFT                                       6
27745 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319                                                          0x0024fcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27746     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_TXDETECTRX_OVR_O_1_0                                 (0x3<<0) // Override signal for txdetectrx input - bit 1 is override enable, bit 0 is override value.
27747     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_TXDETECTRX_OVR_O_1_0_SHIFT                           0
27748     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_RXDET_STATUS_OVR_O_1_0                               (0x3<<2) // Override signal for txdetectrx output - bit 1 is override enable, bit 0 is override value.
27749     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_RXDET_STATUS_OVR_O_1_0_SHIFT                         2
27750     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_LOCKED_OVR_O_1_0                                     (0x3<<4) // Override signal for symbol align locked output. Bit 1 is the override enable, and bit 0 is the override value.
27751     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_LOCKED_OVR_O_1_0_SHIFT                               4
27752     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O                     (0x1<<6) // override enable for tx_lowpwr_idle_ena output to PMA
27753     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_ENA_O_SHIFT               6
27754     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O                         (0x1<<7) // override value for tx_lowpwr_idle_ena output to PMA
27755     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X319_AHB_TX_LOWPWR_IDLE_ENA_OVR_O_SHIFT                   7
27756 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X320                                                          0x002500UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
27757 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X321                                                          0x002504UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
27758 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X322                                                          0x002508UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
27759 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X323                                                          0x00250cUL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
27760 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X324                                                          0x002510UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
27761 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X325                                                          0x002514UL //Access:RW   DataWidth:0x8   Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used  Chips: K2
27762 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326                                                          0x002518UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27763     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_48                                       (0x1<<0) // Override for primary lane inputs For PCIE3 mode bit 0 : override enable bit 1 : override for lnx_rstn bit [3:2] : override for lnx_rate bit [5:4] : override for lnX_pd bit [48:6] : override for lnx_ctrl For SAPIS Mode bit 0 : override enable bit 1 : override for lnx_rstn bit {[17:15],[3:2]} : override for lnx_rate bit [5:4] : override for lnX_pd bit [14:6] : override for lnx_ctrl bit [48:15] : not used
27764     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_48_SHIFT                                 0
27765     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_AHB_LN_IN_OVR_CHG_FLAG_O                             (0x1<<1) // Flag to guard around each write to lnX_in_ovr_o_14_1 when the lane is out of reset. Set this bit to '1' before writing to the corresponding lnX_in_ovr_o_14_1 and set it back to '0' after the write. It is not needed for configuration writes.
27766     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_AHB_LN_IN_OVR_CHG_FLAG_O_SHIFT                       1
27767     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_REGP1_OVR_O_3_0                                      (0xf<<2) // Overrides for polbit block polbit_regp1 Bit[3]: Polarity register block input override enable. Bit[0]: Overide values for polarty  Bit[1]: Overide values for bit reverse  Bit[2]: Overide values for word reverse
27768     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_REGP1_OVR_O_3_0_SHIFT                                2
27769     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_OOB_DET_EN                                           (0x1<<6) // OOB detect enable
27770     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_OOB_DET_EN_SHIFT                                     6
27771     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_49                                       (0x1<<7) // OOB detect enable
27772     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X326_LN_IN_OVR_O_49_SHIFT                                 7
27773 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X327                                                          0x00251cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27774     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X327_CDR_CTRL_DLY_DLPF_EN_O                               (0x1f<<0) // Delay between cisel assertion and enabling the CDR loop pma_lX_dlpf_ext_ena=0  R-platform requires 150ns delay
27775     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X327_CDR_CTRL_DLY_DLPF_EN_O_SHIFT                         0
27776     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X327_UNUSED_0                                             (0x7<<5) // reserved
27777     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X327_UNUSED_0_SHIFT                                       5
27778 #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330                                                          0x002528UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27779     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0                     (0x7<<0) // Override signals for lane: msm_ln_rate_ow[4:2]
27780     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_MSM_LN_RATE_EXTRA_BITS_OVR_O_2_0_SHIFT               0
27781     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_LN_IN_OVR_O_50                                       (0x1<<3) // Override signals for lane: msm_ln_rate_ow[4:2]
27782     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_LN_IN_OVR_O_50_SHIFT                                 3
27783     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_UNUSED_0                                             (0xf<<4) // reserved
27784     #define PHY_PCIE_IP_REG_AHB_LANE_CSR_4_X330_UNUSED_0_SHIFT                                       4
27785 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0                                                         0x002800UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27786     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O                                      (0x1<<0) // Lane Reference Clock Enable.  0 - gcfsm_refmux_clk = pma_cm_ref_clk_i 1 - gcfsm_refmux_clk = lane_ref_clk
27787     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0_LN_CMUREF_EN_O_SHIFT                                0
27788     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0_UNUSED_0                                            (0x7f<<1) // reserved
27789     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X0_UNUSED_0_SHIFT                                      1
27790 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1                                                         0x002804UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27791     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O                                 (0x1<<0) // Enable/Disable the internal PRBS data pattern inverter. 0x0 ? Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 ? Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
27792     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_CHK_INV_PRBS_O_SHIFT                           0
27793     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O                                 (0x1<<1) // Enable/Disable the internal PRBS data pattern inverter. 0x0 ? Invert the PRBS data pattern for PRBS-31 and not invert the PRBS data pattern for the other PRBS types. 0x1 ? Not invert the PRBS data pattern for PRBS-31 and invert the PRBS data pattern for the other PRBS types.
27794     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_BIST_GEN_INV_PRBS_O_SHIFT                           1
27795     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_UNUSED_0                                            (0x3f<<2) // reserved
27796     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X1_UNUSED_0_SHIFT                                      2
27797 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X2                                                         0x002808UL //Access:RW   DataWidth:0x8   BIST alignment pattern for Gen3  Chips: K2
27798 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X3                                                         0x00280cUL //Access:RW   DataWidth:0x8   BIST alignment pattern for Gen3  Chips: K2
27799 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X4                                                         0x002810UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27800     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X4_P2S_RBUF_PTR_DIFF_O_2_0                             (0x7<<0) // P2S ring buffer initial startup pointer difference.
27801     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X4_P2S_RBUF_PTR_DIFF_O_2_0_SHIFT                       0
27802     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X4_UNUSED_0                                            (0x1f<<3) // reserved
27803     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X4_UNUSED_0_SHIFT                                      3
27804 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X6                                                         0x002818UL //Access:RW   DataWidth:0x8   Symbol aligner alignment word. Expects bit 0 received first  Chips: K2
27805 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X7                                                         0x00281cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27806     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X7_SYM_ALIGN_WORD_O_9_8                                (0x3<<0) // Symbol aligner alignment word. Expects bit 0 received first
27807     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X7_SYM_ALIGN_WORD_O_9_8_SHIFT                          0
27808     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X7_UNUSED_0                                            (0x3f<<2) // reserved
27809     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X7_UNUSED_0_SHIFT                                      2
27810 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8                                                         0x002820UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27811     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_LOCK_NUM_O_3_0                                  (0xf<<0) // Number of properly aligned align words that must be detected
27812     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_LOCK_NUM_O_3_0_SHIFT                            0
27813     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_UNLOCK_NUM_O_3_0                                (0xf<<4) // Number of improperly aligned align words that must be detected
27814     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X8_SYM_UNLOCK_NUM_O_3_0_SHIFT                          4
27815 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X9                                                         0x002824UL //Access:RW   DataWidth:0x8   Block aligner skp end word  Chips: K2
27816 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X10                                                        0x002828UL //Access:RW   DataWidth:0x8   The first 16 bits of an encoded EIEOS in Gen3  Chips: K2
27817 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X11                                                        0x00282cUL //Access:RW   DataWidth:0x8   The first 16 bits of an encoded EIEOS in Gen3  Chips: K2
27818 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X12                                                        0x002830UL //Access:RW   DataWidth:0x8   The remaining 16 bit words of an EIEOS in Gen3  Chips: K2
27819 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X13                                                        0x002834UL //Access:RW   DataWidth:0x8   The remaining 16 bit words of an EIEOS in Gen3  Chips: K2
27820 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X14                                                        0x002838UL //Access:RW   DataWidth:0x8   The first 16 bits of an encoded SDSOS in Gen3  Chips: K2
27821 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X15                                                        0x00283cUL //Access:RW   DataWidth:0x8   The first 16 bits of an encoded SDSOS in Gen3  Chips: K2
27822 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X16                                                        0x002840UL //Access:RW   DataWidth:0x8   The remaining 16 bit words of an SDSOS in Gen3  Chips: K2
27823 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X17                                                        0x002844UL //Access:RW   DataWidth:0x8   The remaining 16 bit words of an SDSOS in Gen3  Chips: K2
27824 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X18                                                        0x002848UL //Access:RW   DataWidth:0x8   The first 16 bits of an encoded SKPOS in Gen3  Chips: K2
27825 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X19                                                        0x00284cUL //Access:RW   DataWidth:0x8   The first 16 bits of an encoded SKPOS in Gen3  Chips: K2
27826 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X20                                                        0x002850UL //Access:RW   DataWidth:0x8   The remaining 16 bit words of a SKPOS in Gen3  Chips: K2
27827 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X21                                                        0x002854UL //Access:RW   DataWidth:0x8   The remaining 16 bit words of a SKPOS in Gen3  Chips: K2
27828 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22                                                        0x002858UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27829     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22_SYNC_HDR_QUAL_EN_O                                 (0x1<<0) // Enables block_aligner skpos_hdr_det qualification
27830     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22_SYNC_HDR_QUAL_EN_O_SHIFT                           0
27831     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22_UNUSED_0                                           (0x7f<<1) // reserved
27832     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X22_UNUSED_0_SHIFT                                     1
27833 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X23                                                        0x00285cUL //Access:RW   DataWidth:0x8   Elastic buffer s0 [7:0]  Chips: K2
27834 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X24                                                        0x002860UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27835     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X24_EBUF_SYMB0_O_9_8                                   (0x3<<0) // Elastic buffer s0 [9:8]
27836     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X24_EBUF_SYMB0_O_9_8_SHIFT                             0
27837     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X24_UNUSED_0                                           (0x3f<<2) // reserved
27838     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X24_UNUSED_0_SHIFT                                     2
27839 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X25                                                        0x002864UL //Access:RW   DataWidth:0x8   Elastic buffer s1 [7:0]  Chips: K2
27840 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26                                                        0x002868UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27841     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_SYMB1_O_9_8                                   (0x3<<0) // Elastic buffer s1 [9:8]
27842     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_SYMB1_O_9_8_SHIFT                             0
27843     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_EN_O                                          (0x1<<2) // Elastic buffer enable
27844     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_EBUF_EN_O_SHIFT                                    2
27845     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_UNUSED_0                                           (0x1f<<3) // reserved
27846     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X26_UNUSED_0_SHIFT                                     3
27847 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X29                                                        0x002874UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27848     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X29_EBUF_FIFO_MID_O_5_0                                (0x3f<<0) // Elastic buffer FIFO mid thershold
27849     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X29_EBUF_FIFO_MID_O_5_0_SHIFT                          0
27850     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X29_UNUSED_0                                           (0x3<<6) // reserved
27851     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X29_UNUSED_0_SHIFT                                     6
27852 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X30                                                        0x002878UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27853     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X30_EBUF_FIFO_FULL_O_5_0                               (0x3f<<0) // Elastic buffer FIFO full threshold
27854     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X30_EBUF_FIFO_FULL_O_5_0_SHIFT                         0
27855     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X30_UNUSED_0                                           (0x3<<6) // reserved
27856     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X30_UNUSED_0_SHIFT                                     6
27857 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X31                                                        0x00287cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27858     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X31_EBUF_FIFO_EMPTY_O_5_0                              (0x3f<<0) // Elastic buffer FIFO empty threshold
27859     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X31_EBUF_FIFO_EMPTY_O_5_0_SHIFT                        0
27860     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X31_UNUSED_0                                           (0x3<<6) // reserved
27861     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X31_UNUSED_0_SHIFT                                     6
27862 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X32                                                        0x002880UL //Access:RW   DataWidth:0x8   SKP symbol for PCIe Gen3 SKP OS ---8'hAA  Chips: K2
27863 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X33                                                        0x002884UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27864     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X33_EBUF_FIFO_ADD_O_5_0                                (0x3f<<0) // SKP addition threshold value.
27865     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X33_EBUF_FIFO_ADD_O_5_0_SHIFT                          0
27866     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X33_UNUSED_0                                           (0x3<<6) // reserved
27867     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X33_UNUSED_0_SHIFT                                     6
27868 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X34                                                        0x002888UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27869     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X34_EBUF_FIFO_RMV_O_5_0                                (0x3f<<0) // SKP removal threshold value.
27870     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X34_EBUF_FIFO_RMV_O_5_0_SHIFT                          0
27871     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X34_UNUSED_0                                           (0x3<<6) // reserved
27872     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X34_UNUSED_0_SHIFT                                     6
27873 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X35                                                        0x00288cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27874     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X35_EBUF_FIFO_DEPTH_O_5_0                              (0x3f<<0) // FIFO read enable threshold value .
27875     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X35_EBUF_FIFO_DEPTH_O_5_0_SHIFT                        0
27876     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X35_UNUSED_0                                           (0x3<<6) // reserved
27877     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X35_UNUSED_0_SHIFT                                     6
27878 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X38                                                        0x002898UL //Access:RW   DataWidth:0x8   10-bit align symbol for ebuf during PIPE loopback [7:0]  Chips: K2
27879 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X39                                                        0x00289cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27880     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X39_S0_LB_P_O_9_8                                      (0x3<<0) // 10-bit align symbol for ebuf during PIPE loopback [9:8]
27881     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X39_S0_LB_P_O_9_8_SHIFT                                0
27882     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X39_UNUSED_0                                           (0x3f<<2) // reserved
27883     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X39_UNUSED_0_SHIFT                                     2
27884 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X40                                                        0x0028a0UL //Access:RW   DataWidth:0x8   10-bit align symbol for ebuf during PIPE loopback [7:0]  Chips: K2
27885 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X41                                                        0x0028a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27886     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X41_S1_LB_P_O_9_8                                      (0x3<<0) // 10-bit align symbol for ebuf during PIPE loopback [9:8]
27887     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X41_S1_LB_P_O_9_8_SHIFT                                0
27888     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X41_UNUSED_0                                           (0x3f<<2) // reserved
27889     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X41_UNUSED_0_SHIFT                                     2
27890 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43                                                        0x0028acUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27891     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_UNUSED_0                                           (0x1<<0) // reserved
27892     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_UNUSED_0_SHIFT                                     0
27893     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O                        (0x1<<1) // Enable resetting of railed DLPF
27894     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_CDR_CTRL_DLPF_RAIL_RST_EN_O_SHIFT                  1
27895     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_UNUSED_1                                           (0x3f<<2) // reserved
27896     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X43_UNUSED_1_SHIFT                                     2
27897 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44                                                        0x0028b0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27898     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O                   (0x1<<0) // Enable DOSC adjustement for railed DLPF
27899     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_EN_O_SHIFT             0
27900     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O                  (0x1f<<1) // Default DOSC adjustement value for railed DLPF
27901     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_VAL_O_SHIFT            1
27902     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O                  (0x1<<6) // Default DOSC adjustement direction for railed DLPF
27903     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_CDR_CTRL_DLPF_RAIL_DOSC_ADJ_DIR_O_SHIFT            6
27904     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_UNUSED_0                                           (0x1<<7) // reserved
27905     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X44_UNUSED_0_SHIFT                                     7
27906 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45                                                        0x0028b4UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27907     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPUCLK_DIV_LATCHED_I_1_0                           (0x3<<0) //
27908     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPUCLK_DIV_LATCHED_I_1_0_SHIFT                     0
27909     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPU_LOS_INT_EN_O_3_0                               (0xf<<2) //
27910     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPU_LOS_INT_EN_O_3_0_SHIFT                         2
27911     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPUCLK_DIV_O_1_0                                   (0x3<<6) //
27912     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X45_CPUCLK_DIV_O_1_0_SHIFT                             6
27913 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46                                                        0x0028b8UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27914     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_DIV_OVRD_O                                  (0x1<<0) //
27915     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_DIV_OVRD_O_SHIFT                            0
27916     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_SEL_O                                       (0x1<<1) //
27917     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_SEL_O_SHIFT                                 1
27918     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPU_AHB_CK_RATIO_O_3_0                             (0xf<<2) //
27919     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPU_AHB_CK_RATIO_O_3_0_SHIFT                       2
27920     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_EN_O                                        (0x1<<6) //
27921     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_CPUCLK_EN_O_SHIFT                                  6
27922     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_UNUSED_0                                           (0x1<<7) // reserved
27923     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X46_UNUSED_0_SHIFT                                     7
27924 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47                                                        0x0028bcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27925     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_CPU_LOS_CHANGE_I_3_0                               (0xf<<0) //
27926     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_CPU_LOS_CHANGE_I_3_0_SHIFT                         0
27927     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_CPU_LOS_NEW_I_3_0                                  (0xf<<4) //
27928     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X47_CPU_LOS_NEW_I_3_0_SHIFT                            4
27929 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48                                                        0x0028c0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
27930     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN0_INTRPT_I_0                                 (0x1<<0) //
27931     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN0_INTRPT_I_0_SHIFT                           0
27932     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN1_INTRPT_I_1                                 (0x1<<1) //
27933     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN1_INTRPT_I_1_SHIFT                           1
27934     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN2_INTRPT_I_2                                 (0x1<<2) //
27935     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN2_INTRPT_I_2_SHIFT                           2
27936     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN3_INTRPT_I_3                                 (0x1<<3) //
27937     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_LOS_LN3_INTRPT_I_3_SHIFT                           3
27938     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_UNUSED_0                                           (0xf<<4) // reserved
27939     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X48_UNUSED_0_SHIFT                                     4
27940 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49                                                        0x0028c4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27941     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O                              (0x1<<0) // Enable eye scan counter
27942     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_COUNTER_EN_O_SHIFT                        0
27943     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O                                     (0x1<<1) // Run eye scan counter
27944     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_RUN_O_SHIFT                               1
27945     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O                                   (0x1<<2) // Shift edge samples
27946     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_O_SHIFT                             2
27947     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O                               (0x1<<3) // Determines shift direction of edge samples
27948     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_DIR_O_SHIFT                         3
27949     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O                             (0x1<<4) // Shift edge samples by 2 bits
27950     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_EYE_SCAN_SHIFT_2BITS_O_SHIFT                       4
27951     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_UNUSED_0                                           (0x7<<5) // reserved
27952     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X49_UNUSED_0_SHIFT                                     5
27953 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X50                                                        0x0028c8UL //Access:RW   DataWidth:0x8   Mask eye scan results  Chips: K2
27954 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X51                                                        0x0028ccUL //Access:RW   DataWidth:0x8   Mask eye scan results  Chips: K2
27955 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X52                                                        0x0028d0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27956     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X52_EYE_SCAN_MASK_O_18_16                              (0x7<<0) // Mask eye scan results
27957     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X52_EYE_SCAN_MASK_O_18_16_SHIFT                        0
27958     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X52_UNUSED_0                                           (0x1f<<3) // reserved
27959     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X52_UNUSED_0_SHIFT                                     3
27960 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X53                                                        0x0028d4UL //Access:RW   DataWidth:0x8   Eye scan wait time  Chips: K2
27961 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X54                                                        0x0028d8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27962     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X54_EYE_SCAN_WAIT_LEN_O_11_8                           (0xf<<0) // Eye scan wait time
27963     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X54_EYE_SCAN_WAIT_LEN_O_11_8_SHIFT                     0
27964     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X54_UNUSED_0                                           (0xf<<4) // reserved
27965     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X54_UNUSED_0_SHIFT                                     4
27966 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X55                                                        0x0028dcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
27967     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X55_GCFSM_DIV_EN_O_1_0                                 (0x3<<0) // Static divider control for Lane GCFSM clock The only access to this divider. Not an override 4?d0:  No division  4?d1:  /2 4?d2:  /2 4?d3:  /4:
27968     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X55_GCFSM_DIV_EN_O_1_0_SHIFT                           0
27969     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X55_UNUSED_0                                           (0x3f<<2) // reserved
27970     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X55_UNUSED_0_SHIFT                                     2
27971 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X56                                                        0x0028e0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 7-0  Chips: K2
27972 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X57                                                        0x0028e4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 15-8  Chips: K2
27973 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X58                                                        0x0028e8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 23-16  Chips: K2
27974 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X59                                                        0x0028ecUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 31-24  Chips: K2
27975 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X60                                                        0x0028f0UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 39-32  Chips: K2
27976 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X61                                                        0x0028f4UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 47-40  Chips: K2
27977 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X62                                                        0x0028f8UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 55-48  Chips: K2
27978 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X63                                                        0x0028fcUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 63-56  Chips: K2
27979 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X64                                                        0x002900UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 71-64  Chips: K2
27980 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X65                                                        0x002904UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 79-72  Chips: K2
27981 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X66                                                        0x002908UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 87-80  Chips: K2
27982 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X67                                                        0x00290cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 95-88  Chips: K2
27983 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X68                                                        0x002910UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 103-96  Chips: K2
27984 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X69                                                        0x002914UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 111-104  Chips: K2
27985 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X70                                                        0x002918UL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 119-112  Chips: K2
27986 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X71                                                        0x00291cUL //Access:RW   DataWidth:0x8   GCFSM Cycle Length Input bits 127-120  Chips: K2
27987 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X72                                                        0x002920UL //Access:RW   DataWidth:0x8   GCFSM calibraton direction  Chips: K2
27988 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X73                                                        0x002924UL //Access:RW   DataWidth:0x8   GCFSM calibraton direction  Chips: K2
27989 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X74                                                        0x002928UL //Access:RW   DataWidth:0x8   Function info for each MSM function. Varies depending on function number.   Bits 15-7: Address of first command to run Bits: 6-0: Number of commands to run  Chips: K2
27990 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X75                                                        0x00292cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27991 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X76                                                        0x002930UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27992 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X77                                                        0x002934UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27993 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X78                                                        0x002938UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27994 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X79                                                        0x00293cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27995 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X80                                                        0x002940UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27996 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X81                                                        0x002944UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27997 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X82                                                        0x002948UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27998 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X83                                                        0x00294cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
27999 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X84                                                        0x002950UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28000 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X85                                                        0x002954UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28001 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X86                                                        0x002958UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28002 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X87                                                        0x00295cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28003 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X88                                                        0x002960UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28004 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X89                                                        0x002964UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28005 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X90                                                        0x002968UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28006 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X91                                                        0x00296cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28007 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X92                                                        0x002970UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28008 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X93                                                        0x002974UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28009 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X94                                                        0x002978UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28010 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X95                                                        0x00297cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28011 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X96                                                        0x002980UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28012 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X97                                                        0x002984UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28013 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X98                                                        0x002988UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28014 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X99                                                        0x00298cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28015 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X100                                                       0x002990UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28016 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X101                                                       0x002994UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28017 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X102                                                       0x002998UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28018 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X103                                                       0x00299cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28019 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X104                                                       0x0029a0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28020 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X105                                                       0x0029a4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28021 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X106                                                       0x0029a8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28022 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X107                                                       0x0029acUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28023 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X108                                                       0x0029b0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28024 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X109                                                       0x0029b4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28025 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X110                                                       0x0029b8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28026 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X111                                                       0x0029bcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28027 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X112                                                       0x0029c0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28028 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X113                                                       0x0029c4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28029 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X114                                                       0x0029c8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28030 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X115                                                       0x0029ccUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28031 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X116                                                       0x0029d0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28032 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X117                                                       0x0029d4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28033 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X118                                                       0x0029d8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28034 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X119                                                       0x0029dcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28035 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X120                                                       0x0029e0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28036 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X121                                                       0x0029e4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28037 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X122                                                       0x0029e8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28038 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X123                                                       0x0029ecUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28039 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X124                                                       0x0029f0UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28040 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X125                                                       0x0029f4UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28041 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X126                                                       0x0029f8UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28042 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X127                                                       0x0029fcUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28043 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X128                                                       0x002a00UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28044 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X129                                                       0x002a04UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28045 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X130                                                       0x002a08UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28046 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X131                                                       0x002a0cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28047 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X132                                                       0x002a10UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28048 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X133                                                       0x002a14UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28049 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X134                                                       0x002a18UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28050 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X135                                                       0x002a1cUL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28051 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X136                                                       0x002a20UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28052 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X137                                                       0x002a24UL //Access:RW   DataWidth:0x8   See description for msm_func_info_o_7_0  Chips: K2
28053 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138                                                       0x002a28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28054     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O          (0x1<<0) // Enables programmable tx det rx pulse
28055     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138_QAHB_MSM_PIPE_EN_PROG_TXDETECTRX_PULSE_O_SHIFT    0
28056     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138_UNUSED_0                                          (0x7f<<1) // reserved
28057     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X138_UNUSED_0_SHIFT                                    1
28058 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X139                                                       0x002a2cUL //Access:RW   DataWidth:0x8   Programmable width of tx det rx pulse  Chips: K2
28059 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X140                                                       0x002a30UL //Access:RW   DataWidth:0x8   Programmable width of tx det rx pulse  Chips: K2
28060 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X141                                                       0x002a34UL //Access:RW   DataWidth:0x8   Delay for MFSM state transition from P2 to P1 in non-PIPE mode.  The MFSM waits for the analog cuircuity to recover from power-down. The actual delay is 4*<reference clock period	*<value of this register	.  Chips: K2
28061 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X142                                                       0x002a38UL //Access:RW   DataWidth:0x8   Delay for MFSM state transition from P2 to P1 in non-PIPE mode.  The MFSM waits for the analog cuircuity to recover from power-down. The actual delay is 4*<reference clock period	*<value of this register	.  Chips: K2
28062 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143                                                       0x002a3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28063     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O                           (0x1<<0) // MSM Function IDDQ state's default value for iddq_sd in SAPIS mode
28064     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_IDDQ_SD_O_SHIFT                     0
28065     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O                            (0x1<<1) // MSM Function IDDQ state's default value for pd_dfe in SAPIS mode
28066     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_O_SHIFT                      1
28067     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O                       (0x1<<2) // MSM Function IDDQ state's default value for pd_dfe_bias in SAPIS mode
28068     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_DFE_BIAS_O_SHIFT                 2
28069     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O                          (0x1<<3) // MSM Function IDDQ state's default value for pd_lnreg in SAPIS mode
28070     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREG_O_SHIFT                    3
28071     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O                         (0x1<<4) // MSM Function IDDQ state's default value for pd_lnregh in SAPIS mode
28072     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_LNREGH_O_SHIFT                   4
28073     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O                            (0x1<<5) // MSM Function IDDQ state's default value for pd_p2s in SAPIS mode
28074     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_P2S_O_SHIFT                      5
28075     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O                             (0x1<<6) // MSM Function IDDQ state's default value for pd_ra in SAPIS mode
28076     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_RA_O_SHIFT                       6
28077     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O                            (0x1<<7) // MSM Function IDDQ state's default value for pd_s2p in SAPIS mode
28078     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X143_MSM_SAPI_IDDQ_PD_S2P_O_SHIFT                      7
28079 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144                                                       0x002a40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28080     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O                       (0x1<<0) // MSM Function IDDQ state's default value for pd_slv_bias in SAPIS mode
28081     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_SLV_BIAS_O_SHIFT                 0
28082     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O                          (0x1<<1) // MSM Function IDDQ state's default value for pd_txdrv in SAPIS mode
28083     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXDRV_O_SHIFT                    1
28084     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O                          (0x1<<2) // MSM Function IDDQ state's default value for pd_txreg in SAPIS mode
28085     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_TXREG_O_SHIFT                    2
28086     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O                            (0x1<<3) // MSM Function IDDQ state's default value for pd_vco in SAPIS mode
28087     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_O_SHIFT                      3
28088     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O                        (0x1<<4) // MSM Function IDDQ state's default value for pd_vco_buf in SAPIS mode
28089     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_PD_VCO_BUF_O_SHIFT                  4
28090     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O                         (0x1<<5) // MSM Function IDDQ state's default value for reset_cdr in SAPIS mode
28091     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_O_SHIFT                   5
28092     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O                    (0x1<<6) // MSM Function IDDQ state's default value for reset_cdr_gcrx in SAPIS mode
28093     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_CDR_GCRX_O_SHIFT              6
28094     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O                         (0x1<<7) // MSM Function IDDQ state's default value for reset_dfe in SAPIS mode
28095     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X144_MSM_SAPI_IDDQ_RESET_DFE_O_SHIFT                   7
28096 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145                                                       0x002a44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28097     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O                       (0x1<<0) // MSM Function IDDQ state's default value for reset_lnreg in SAPIS mode
28098     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREG_O_SHIFT                 0
28099     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O                      (0x1<<1) // MSM Function IDDQ state's default value for reset_lnregh in SAPIS mode
28100     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_LNREGH_O_SHIFT                1
28101     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O                         (0x1<<2) // MSM Function IDDQ state's default value for reset_p2s in SAPIS mode
28102     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_P2S_O_SHIFT                   2
28103     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O                          (0x1<<3) // MSM Function IDDQ state's default value for reset_ra in SAPIS mode
28104     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_RA_O_SHIFT                    3
28105     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O                         (0x1<<4) // MSM Function IDDQ state's default value for reset_s2p in SAPIS mode
28106     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_S2P_O_SHIFT                   4
28107     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O                         (0x1<<5) // MSM Function IDDQ state's default value for reset_vco in SAPIS mode
28108     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_RESET_VCO_O_SHIFT                   5
28109     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O                   (0x1<<6) // MSM Function IDDQ state's default value for txreg_bleed_ena in SAPIS mode
28110     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TXREG_BLEED_ENA_O_SHIFT             6
28111     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O                (0x1<<7) // MSM Function IDDQ state's default value for tx_lowpwr_idle_ena in SAPIS mode
28112     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X145_MSM_SAPI_IDDQ_TX_LOWPWR_IDLE_ENA_O_SHIFT          7
28113 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146                                                       0x002a48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28114     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O                            (0x1<<0) // MSM Function IDDQ state's default value for cdr_en in SAPIS mode
28115     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_CDR_EN_O_SHIFT                      0
28116     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O                         (0x1<<1) // MSM Function IDDQ state's default value for rxbclk_en in SAPIS mode
28117     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RXBCLK_EN_O_SHIFT                   1
28118     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O                        (0x1<<2) // MSM Function IDDQ state's default value for rx_gate_en in SAPIS mode
28119     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RX_GATE_EN_O_SHIFT                  2
28120     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O                   (0x1<<3) // MSM Function IDDQ state's default value for reset_tx_clkdiv in SAPIS mode
28121     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_MSM_SAPI_IDDQ_RESET_TX_CLKDIV_O_SHIFT             3
28122     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_UNUSED_0                                          (0xf<<4) // reserved
28123     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X146_UNUSED_0_SHIFT                                    4
28124 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147                                                       0x002a4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28125     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O                            (0x1<<0) // MSM Function RESET state's default value for iddq_sd in SAPIS mode
28126     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_IDDQ_SD_O_SHIFT                      0
28127     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O                             (0x1<<1) // MSM Function RESET state's default value for pd_dfe in SAPIS mode
28128     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_O_SHIFT                       1
28129     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O                        (0x1<<2) // MSM Function RESET state's default value for pd_dfe_bias in SAPIS mode
28130     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_DFE_BIAS_O_SHIFT                  2
28131     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O                           (0x1<<3) // MSM Function RESET state's default value for pd_lnreg in SAPIS mode
28132     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREG_O_SHIFT                     3
28133     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O                          (0x1<<4) // MSM Function RESET state's default value for pd_lnregh in SAPIS mode
28134     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_LNREGH_O_SHIFT                    4
28135     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O                             (0x1<<5) // MSM Function RESET state's default value for pd_p2s in SAPIS mode
28136     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_P2S_O_SHIFT                       5
28137     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O                              (0x1<<6) // MSM Function RESET state's default value for pd_ra in SAPIS mode
28138     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_RA_O_SHIFT                        6
28139     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O                             (0x1<<7) // MSM Function RESET state's default value for pd_s2p in SAPIS mode
28140     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X147_MSM_SAPI_RST_PD_S2P_O_SHIFT                       7
28141 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148                                                       0x002a50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28142     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O                        (0x1<<0) // MSM Function RESET state's default value for pd_slv_bias in SAPIS mode
28143     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_SLV_BIAS_O_SHIFT                  0
28144     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O                           (0x1<<1) // MSM Function RESET state's default value for pd_txdrv in SAPIS mode
28145     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXDRV_O_SHIFT                     1
28146     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O                           (0x1<<2) // MSM Function RESET state's default value for pd_txreg in SAPIS mode
28147     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_TXREG_O_SHIFT                     2
28148     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O                             (0x1<<3) // MSM Function RESET state's default value for pd_vco in SAPIS mode
28149     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_O_SHIFT                       3
28150     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O                         (0x1<<4) // MSM Function RESET state's default value for pd_vco_buf in SAPIS mode
28151     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_PD_VCO_BUF_O_SHIFT                   4
28152     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O                          (0x1<<5) // MSM Function RESET state's default value for reset_cdr in SAPIS mode
28153     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_O_SHIFT                    5
28154     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O                     (0x1<<6) // MSM Function RESET state's default value for reset_cdr_gcrx in SAPIS mode
28155     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_CDR_GCRX_O_SHIFT               6
28156     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O                          (0x1<<7) // MSM Function RESET state's default value for reset_dfe in SAPIS mode
28157     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X148_MSM_SAPI_RST_RESET_DFE_O_SHIFT                    7
28158 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149                                                       0x002a54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28159     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O                        (0x1<<0) // MSM Function RESET state's default value for reset_lnreg in SAPIS mode
28160     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREG_O_SHIFT                  0
28161     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O                       (0x1<<1) // MSM Function RESET state's default value for reset_lnregh in SAPIS mode
28162     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_LNREGH_O_SHIFT                 1
28163     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O                          (0x1<<2) // MSM Function RESET state's default value for reset_p2s in SAPIS mode
28164     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_P2S_O_SHIFT                    2
28165     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O                           (0x1<<3) // MSM Function RESET state's default value for reset_ra in SAPIS mode
28166     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_RA_O_SHIFT                     3
28167     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O                          (0x1<<4) // MSM Function RESET state's default value for reset_s2p in SAPIS mode
28168     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_S2P_O_SHIFT                    4
28169     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O                          (0x1<<5) // MSM Function RESET state's default value for reset_vco in SAPIS mode
28170     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_RESET_VCO_O_SHIFT                    5
28171     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O                    (0x1<<6) // MSM Function RESET state's default value for txreg_bleed_ena in SAPIS mode
28172     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TXREG_BLEED_ENA_O_SHIFT              6
28173     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O                 (0x1<<7) // MSM Function RESET state's default value for tx_lowpwr_idle_ena in SAPIS mode
28174     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X149_MSM_SAPI_RST_TX_LOWPWR_IDLE_ENA_O_SHIFT           7
28175 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150                                                       0x002a58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28176     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O                             (0x1<<0) // MSM Function RESET state's default value for cdr_en in SAPIS mode
28177     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_CDR_EN_O_SHIFT                       0
28178     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O                          (0x1<<1) // MSM Function RESET state's default value for rxbclk_en in SAPIS mode
28179     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RXBCLK_EN_O_SHIFT                    1
28180     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O                         (0x1<<2) // MSM Function RESET state's default value for rx_gate_en in SAPIS mode
28181     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RX_GATE_EN_O_SHIFT                   2
28182     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O                    (0x1<<3) // MSM Function RESET state's default value for reset_tx_clkdiv in SAPIS mode
28183     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_MSM_SAPI_RST_RESET_TX_CLKDIV_O_SHIFT              3
28184     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_UNUSED_0                                          (0xf<<4) // reserved
28185     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X150_UNUSED_0_SHIFT                                    4
28186 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151                                                       0x002a5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28187     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O                           (0x1<<0) // MSM Function NORMAL state's default value for iddq_sd in SAPIS mode
28188     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_IDDQ_SD_O_SHIFT                     0
28189     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O                            (0x1<<1) // MSM Function NORMAL state's default value for pd_dfe in SAPIS mode
28190     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_O_SHIFT                      1
28191     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O                       (0x1<<2) // MSM Function NORMAL state's default value for pd_dfe_bias in SAPIS mode
28192     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_DFE_BIAS_O_SHIFT                 2
28193     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O                          (0x1<<3) // MSM Function NORMAL state's default value for pd_lnreg in SAPIS mode
28194     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREG_O_SHIFT                    3
28195     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O                         (0x1<<4) // MSM Function NORMAL state's default value for pd_lnregh in SAPIS mode
28196     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_LNREGH_O_SHIFT                   4
28197     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O                            (0x1<<5) // MSM Function NORMAL state's default value for pd_p2s in SAPIS mode
28198     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_P2S_O_SHIFT                      5
28199     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O                             (0x1<<6) // MSM Function NORMAL state's default value for pd_ra in SAPIS mode
28200     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_RA_O_SHIFT                       6
28201     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O                            (0x1<<7) // MSM Function NORMAL state's default value for pd_s2p in SAPIS mode
28202     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X151_MSM_SAPI_NORM_PD_S2P_O_SHIFT                      7
28203 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152                                                       0x002a60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28204     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O                       (0x1<<0) // MSM Function NORMAL state's default value for pd_slv_bias in SAPIS mode
28205     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_SLV_BIAS_O_SHIFT                 0
28206     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O                          (0x1<<1) // MSM Function NORMAL state's default value for pd_txdrv in SAPIS mode
28207     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXDRV_O_SHIFT                    1
28208     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O                          (0x1<<2) // MSM Function NORMAL state's default value for pd_txreg in SAPIS mode
28209     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_TXREG_O_SHIFT                    2
28210     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O                            (0x1<<3) // MSM Function NORMAL state's default value for pd_vco in SAPIS mode
28211     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_O_SHIFT                      3
28212     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O                        (0x1<<4) // MSM Function NORMAL state's default value for pd_vco_buf in SAPIS mode
28213     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_PD_VCO_BUF_O_SHIFT                  4
28214     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O                         (0x1<<5) // MSM Function NORMAL state's default value for reset_cdr in SAPIS mode
28215     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_O_SHIFT                   5
28216     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O                    (0x1<<6) // MSM Function NORMAL state's default value for reset_cdr_gcrx in SAPIS mode
28217     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_CDR_GCRX_O_SHIFT              6
28218     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O                         (0x1<<7) // MSM Function NORMAL state's default value for reset_dfe in SAPIS mode
28219     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X152_MSM_SAPI_NORM_RESET_DFE_O_SHIFT                   7
28220 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153                                                       0x002a64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28221     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O                       (0x1<<0) // MSM Function NORMAL state's default value for reset_lnreg in SAPIS mode
28222     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREG_O_SHIFT                 0
28223     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O                      (0x1<<1) // MSM Function NORMAL state's default value for reset_lnregh in SAPIS mode
28224     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_LNREGH_O_SHIFT                1
28225     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O                         (0x1<<2) // MSM Function NORMAL state's default value for reset_p2s in SAPIS mode
28226     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_P2S_O_SHIFT                   2
28227     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O                          (0x1<<3) // MSM Function NORMAL state's default value for reset_ra in SAPIS mode
28228     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_RA_O_SHIFT                    3
28229     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O                         (0x1<<4) // MSM Function NORMAL state's default value for reset_s2p in SAPIS mode
28230     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_S2P_O_SHIFT                   4
28231     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O                         (0x1<<5) // MSM Function NORMAL state's default value for reset_vco in SAPIS mode
28232     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_RESET_VCO_O_SHIFT                   5
28233     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O                   (0x1<<6) // MSM Function NORMAL state's default value for txreg_bleed_ena in SAPIS mode
28234     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TXREG_BLEED_ENA_O_SHIFT             6
28235     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O                (0x1<<7) // MSM Function NORMAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
28236     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X153_MSM_SAPI_NORM_TX_LOWPWR_IDLE_ENA_O_SHIFT          7
28237 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154                                                       0x002a68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28238     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O                            (0x1<<0) // MSM Function NORMAL state's default value for cdr_en in SAPIS mode
28239     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_CDR_EN_O_SHIFT                      0
28240     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O                         (0x1<<1) // MSM Function NORMAL state's default value for rxbclk_en in SAPIS mode
28241     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RXBCLK_EN_O_SHIFT                   1
28242     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O                        (0x1<<2) // MSM Function NORMAL state's default value for rx_gate_en in SAPIS mode
28243     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RX_GATE_EN_O_SHIFT                  2
28244     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O                   (0x1<<3) // MSM Function NORMAL state's default value for reset_tx_clkdiv in SAPIS mode
28245     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_MSM_SAPI_NORM_RESET_TX_CLKDIV_O_SHIFT             3
28246     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_UNUSED_0                                          (0xf<<4) // reserved
28247     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X154_UNUSED_0_SHIFT                                    4
28248 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155                                                       0x002a6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28249     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O                        (0x1<<0) // MSM Function PARTIAL state's default value for iddq_sd in SAPIS mode
28250     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_IDDQ_SD_O_SHIFT                  0
28251     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O                         (0x1<<1) // MSM Function PARTIAL state's default value for pd_dfe in SAPIS mode
28252     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_O_SHIFT                   1
28253     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O                    (0x1<<2) // MSM Function PARTIAL state's default value for pd_dfe_bias in SAPIS mode
28254     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_DFE_BIAS_O_SHIFT              2
28255     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O                       (0x1<<3) // MSM Function PARTIAL state's default value for pd_lnreg in SAPIS mode
28256     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREG_O_SHIFT                 3
28257     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O                      (0x1<<4) // MSM Function PARTIAL state's default value for pd_lnregh in SAPIS mode
28258     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_LNREGH_O_SHIFT                4
28259     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O                         (0x1<<5) // MSM Function PARTIAL state's default value for pd_p2s in SAPIS mode
28260     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_P2S_O_SHIFT                   5
28261     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O                          (0x1<<6) // MSM Function PARTIAL state's default value for pd_ra in SAPIS mode
28262     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_RA_O_SHIFT                    6
28263     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O                         (0x1<<7) // MSM Function PARTIAL state's default value for pd_s2p in SAPIS mode
28264     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X155_MSM_SAPI_PARTIAL_PD_S2P_O_SHIFT                   7
28265 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156                                                       0x002a70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28266     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O                    (0x1<<0) // MSM Function PARTIAL state's default value for pd_slv_bias in SAPIS mode
28267     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_SLV_BIAS_O_SHIFT              0
28268     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O                       (0x1<<1) // MSM Function PARTIAL state's default value for pd_txdrv in SAPIS mode
28269     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXDRV_O_SHIFT                 1
28270     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O                       (0x1<<2) // MSM Function PARTIAL state's default value for pd_txreg in SAPIS mode
28271     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_TXREG_O_SHIFT                 2
28272     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O                         (0x1<<3) // MSM Function PARTIAL state's default value for pd_vco in SAPIS mode
28273     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_O_SHIFT                   3
28274     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O                     (0x1<<4) // MSM Function PARTIAL state's default value for pd_vco_buf in SAPIS mode
28275     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_PD_VCO_BUF_O_SHIFT               4
28276     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O                      (0x1<<5) // MSM Function PARTIAL state's default value for reset_cdr in SAPIS mode
28277     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_O_SHIFT                5
28278     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O                 (0x1<<6) // MSM Function PARTIAL state's default value for reset_cdr_gcrx in SAPIS mode
28279     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_CDR_GCRX_O_SHIFT           6
28280     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O                      (0x1<<7) // MSM Function PARTIAL state's default value for reset_dfe in SAPIS mode
28281     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X156_MSM_SAPI_PARTIAL_RESET_DFE_O_SHIFT                7
28282 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157                                                       0x002a74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28283     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O                    (0x1<<0) // MSM Function PARTIAL state's default value for reset_lnreg in SAPIS mode
28284     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREG_O_SHIFT              0
28285     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O                   (0x1<<1) // MSM Function PARTIAL state's default value for reset_lnregh in SAPIS mode
28286     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_LNREGH_O_SHIFT             1
28287     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O                      (0x1<<2) // MSM Function PARTIAL state's default value for reset_p2s in SAPIS mode
28288     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_P2S_O_SHIFT                2
28289     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O                       (0x1<<3) // MSM Function PARTIAL state's default value for reset_ra in SAPIS mode
28290     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_RA_O_SHIFT                 3
28291     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O                      (0x1<<4) // MSM Function PARTIAL state's default value for reset_s2p in SAPIS mode
28292     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_S2P_O_SHIFT                4
28293     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O                      (0x1<<5) // MSM Function PARTIAL state's default value for reset_vco in SAPIS mode
28294     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_RESET_VCO_O_SHIFT                5
28295     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O                (0x1<<6) // MSM Function PARTIAL state's default value for txreg_bleed_ena in SAPIS mode
28296     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TXREG_BLEED_ENA_O_SHIFT          6
28297     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O             (0x1<<7) // MSM Function PARTIAL state's default value for tx_lowpwr_idle_ena in SAPIS mode
28298     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X157_MSM_SAPI_PARTIAL_TX_LOWPWR_IDLE_ENA_O_SHIFT       7
28299 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158                                                       0x002a78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28300     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O                         (0x1<<0) // MSM Function PARTIAL state's default value for cdr_en in SAPIS mode
28301     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_CDR_EN_O_SHIFT                   0
28302     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O                      (0x1<<1) // MSM Function PARTIAL state's default value for rxbclk_en in SAPIS mode
28303     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RXBCLK_EN_O_SHIFT                1
28304     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O                     (0x1<<2) // MSM Function PARTIAL state's default value for rx_gate_en in SAPIS mode
28305     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RX_GATE_EN_O_SHIFT               2
28306     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O                (0x1<<3) // MSM Function PARTIAL state's default value for reset_tx_clkdiv in SAPIS mode
28307     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_MSM_SAPI_PARTIAL_RESET_TX_CLKDIV_O_SHIFT          3
28308     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_UNUSED_0                                          (0xf<<4) // reserved
28309     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X158_UNUSED_0_SHIFT                                    4
28310 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159                                                       0x002a7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28311     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O                        (0x1<<0) // MSM Function SLUMBER state's default value for iddq_sd in SAPIS mode
28312     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_IDDQ_SD_O_SHIFT                  0
28313     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O                         (0x1<<1) // MSM Function SLUMBER state's default value for pd_dfe in SAPIS mode
28314     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_O_SHIFT                   1
28315     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O                    (0x1<<2) // MSM Function SLUMBER state's default value for pd_dfe_bias in SAPIS mode
28316     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_DFE_BIAS_O_SHIFT              2
28317     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O                       (0x1<<3) // MSM Function SLUMBER state's default value for pd_lnreg in SAPIS mode
28318     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREG_O_SHIFT                 3
28319     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O                      (0x1<<4) // MSM Function SLUMBER state's default value for pd_lnregh in SAPIS mode
28320     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_LNREGH_O_SHIFT                4
28321     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O                         (0x1<<5) // MSM Function SLUMBER state's default value for pd_p2s in SAPIS mode
28322     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_P2S_O_SHIFT                   5
28323     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O                          (0x1<<6) // MSM Function SLUMBER state's default value for pd_ra in SAPIS mode
28324     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_RA_O_SHIFT                    6
28325     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O                         (0x1<<7) // MSM Function SLUMBER state's default value for pd_s2p in SAPIS mode
28326     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X159_MSM_SAPI_SLUMBER_PD_S2P_O_SHIFT                   7
28327 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160                                                       0x002a80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28328     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O                    (0x1<<0) // MSM Function SLUMBER state's default value for pd_slv_bias in SAPIS mode
28329     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_SLV_BIAS_O_SHIFT              0
28330     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O                       (0x1<<1) // MSM Function SLUMBER state's default value for pd_txdrv in SAPIS mode
28331     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXDRV_O_SHIFT                 1
28332     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O                       (0x1<<2) // MSM Function SLUMBER state's default value for pd_txreg in SAPIS mode
28333     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_TXREG_O_SHIFT                 2
28334     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O                         (0x1<<3) // MSM Function SLUMBER state's default value for pd_vco in SAPIS mode
28335     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_O_SHIFT                   3
28336     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O                     (0x1<<4) // MSM Function SLUMBER state's default value for pd_vco_buf in SAPIS mode
28337     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_PD_VCO_BUF_O_SHIFT               4
28338     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O                      (0x1<<5) // MSM Function SLUMBER state's default value for reset_cdr in SAPIS mode
28339     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_O_SHIFT                5
28340     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O                 (0x1<<6) // MSM Function SLUMBER state's default value for reset_cdr_gcrx in SAPIS mode
28341     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_CDR_GCRX_O_SHIFT           6
28342     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O                      (0x1<<7) // MSM Function SLUMBER state's default value for reset_dfe in SAPIS mode
28343     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X160_MSM_SAPI_SLUMBER_RESET_DFE_O_SHIFT                7
28344 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161                                                       0x002a84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28345     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O                    (0x1<<0) // MSM Function SLUMBER state's default value for reset_lnreg in SAPIS mode
28346     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREG_O_SHIFT              0
28347     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O                   (0x1<<1) // MSM Function SLUMBER state's default value for reset_lnregh in SAPIS mode
28348     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_LNREGH_O_SHIFT             1
28349     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O                      (0x1<<2) // MSM Function SLUMBER state's default value for reset_p2s in SAPIS mode
28350     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_P2S_O_SHIFT                2
28351     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O                       (0x1<<3) // MSM Function SLUMBER state's default value for reset_ra in SAPIS mode
28352     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_RA_O_SHIFT                 3
28353     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O                      (0x1<<4) // MSM Function SLUMBER state's default value for reset_s2p in SAPIS mode
28354     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_S2P_O_SHIFT                4
28355     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O                      (0x1<<5) // MSM Function SLUMBER state's default value for reset_vco in SAPIS mode
28356     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_RESET_VCO_O_SHIFT                5
28357     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O                (0x1<<6) // MSM Function SLUMBER state's default value for txreg_bleed_ena in SAPIS mode
28358     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TXREG_BLEED_ENA_O_SHIFT          6
28359     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O             (0x1<<7) // MSM Function SLUMBER state's default value for tx_lowpwr_idle_ena in SAPIS mode
28360     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X161_MSM_SAPI_SLUMBER_TX_LOWPWR_IDLE_ENA_O_SHIFT       7
28361 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162                                                       0x002a88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28362     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O                         (0x1<<0) // MSM Function SLUMBER state's default value for cdr_en in SAPIS mode
28363     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_CDR_EN_O_SHIFT                   0
28364     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O                      (0x1<<1) // MSM Function SLUMBER state's default value for rxbclk_en in SAPIS mode
28365     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RXBCLK_EN_O_SHIFT                1
28366     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O                     (0x1<<2) // MSM Function SLUMBER state's default value for rx_gate_en in SAPIS mode
28367     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RX_GATE_EN_O_SHIFT               2
28368     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O                (0x1<<3) // MSM Function SLUMBER state's default value for reset_tx_clkdiv in SAPIS mode
28369     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_MSM_SAPI_SLUMBER_RESET_TX_CLKDIV_O_SHIFT          3
28370     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_UNUSED_0                                          (0xf<<4) // reserved
28371     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X162_UNUSED_0_SHIFT                                    4
28372 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X168                                                       0x002aa0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28373     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X168_OOB_DET_BLEN_MIN_O_6_0                            (0x7f<<0) // OOB detector minimum burst length.
28374     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X168_OOB_DET_BLEN_MIN_O_6_0_SHIFT                      0
28375     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X168_UNUSED_0                                          (0x1<<7) // reserved
28376     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X168_UNUSED_0_SHIFT                                    7
28377 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X169                                                       0x002aa4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28378     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X169_OOB_DET_BLEN_MAX_O_6_0                            (0x7f<<0) // OOB detector maximum burst length.
28379     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X169_OOB_DET_BLEN_MAX_O_6_0_SHIFT                      0
28380     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X169_UNUSED_0                                          (0x1<<7) // reserved
28381     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X169_UNUSED_0_SHIFT                                    7
28382 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X170                                                       0x002aa8UL //Access:RW   DataWidth:0x8   OOB detector COMINIT maximum idle length.  Chips: K2
28383 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171                                                       0x002aacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28384     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8                           (0x1<<0) // OOB detector COMINIT maximum idle length.
28385     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171_OOB_DET_COMINIT_MIN_O_8_SHIFT                     0
28386     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171_UNUSED_0                                          (0x7f<<1) // reserved
28387     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X171_UNUSED_0_SHIFT                                    1
28388 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X172                                                       0x002ab0UL //Access:RW   DataWidth:0x8   OOB detector COMINIT maximum idle length.  Chips: K2
28389 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173                                                       0x002ab4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28390     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8                           (0x1<<0) // OOB detector COMINIT maximum idle length.
28391     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173_OOB_DET_COMINIT_MAX_O_8_SHIFT                     0
28392     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173_UNUSED_0                                          (0x7f<<1) // reserved
28393     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X173_UNUSED_0_SHIFT                                    1
28394 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X174                                                       0x002ab8UL //Access:RW   DataWidth:0x8   OOB detector COMWAKE minimum idle length.  Chips: K2
28395 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175                                                       0x002abcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28396     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8                           (0x1<<0) // OOB detector COMWAKE minimum idle length.
28397     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175_OOB_DET_COMWAKE_MIN_O_8_SHIFT                     0
28398     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175_UNUSED_0                                          (0x7f<<1) // reserved
28399     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X175_UNUSED_0_SHIFT                                    1
28400 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X176                                                       0x002ac0UL //Access:RW   DataWidth:0x8   OOB detector COMWAKE maximum idle length.  Chips: K2
28401 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177                                                       0x002ac4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28402     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8                           (0x1<<0) // OOB detector COMWAKE maximum idle length.
28403     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177_OOB_DET_COMWAKE_MAX_O_8_SHIFT                     0
28404     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177_UNUSED_0                                          (0x7f<<1) // reserved
28405     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X177_UNUSED_0_SHIFT                                    1
28406 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X178                                                       0x002ac8UL //Access:RW   DataWidth:0x8   OOB detector COMSAS maximum idle length.  Chips: K2
28407 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179                                                       0x002accUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28408     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8                            (0x1<<0) // OOB detector COMSAS maximum idle length.
28409     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179_OOB_DET_COMSAS_MIN_O_8_SHIFT                      0
28410     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179_UNUSED_0                                          (0x7f<<1) // reserved
28411     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X179_UNUSED_0_SHIFT                                    1
28412 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X180                                                       0x002ad0UL //Access:RW   DataWidth:0x8   OOB detector COMSAS maximum idle length.  Chips: K2
28413 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181                                                       0x002ad4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28414     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8                            (0x1<<0) // OOB detector COMSAS maximum idle length.
28415     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181_OOB_DET_COMSAS_MAX_O_8_SHIFT                      0
28416     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181_UNUSED_0                                          (0x7f<<1) // reserved
28417     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X181_UNUSED_0_SHIFT                                    1
28418 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182                                                       0x002ad8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28419     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_TXCTRL_FASTCAP_3_0                                (0xf<<0) // TX fastcap slew rate adjust
28420     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_TXCTRL_FASTCAP_3_0_SHIFT                          0
28421     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_TXCTRL_FASTCAP_OVR_3_0                            (0xf<<4) // Override  value for Fastcap.
28422     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X182_TXCTRL_FASTCAP_OVR_3_0_SHIFT                      4
28423 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183                                                       0x002adcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28424     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_TXCTRL_RATE1_TX_SR_DAC_3_0                        (0xf<<0) // TX rate1 slew rate DAC setting
28425     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_TXCTRL_RATE1_TX_SR_DAC_3_0_SHIFT                  0
28426     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_TXCTRL_RATE2_TX_SR_DAC_3_0                        (0xf<<4) // TX rate2 slew rate DAC setting
28427     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X183_TXCTRL_RATE2_TX_SR_DAC_3_0_SHIFT                  4
28428 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184                                                       0x002ae0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28429     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_TXCTRL_RATE3_TX_SR_DAC_3_0                        (0xf<<0) // TX rate3 slew rate DAC setting
28430     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_TXCTRL_RATE3_TX_SR_DAC_3_0_SHIFT                  0
28431     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_TXCTRL_MASTER_TX_SR_DAC_OVR_3_0                   (0xf<<4) // TX master slew rate DAC overrides
28432     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X184_TXCTRL_MASTER_TX_SR_DAC_OVR_3_0_SHIFT             4
28433 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185                                                       0x002ae4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28434     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_TXCTRL_RATE1_TXEQ_POLARITY_3_0                    (0xf<<0) // TX rate1 coefficent polarity
28435     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_TXCTRL_RATE1_TXEQ_POLARITY_3_0_SHIFT              0
28436     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_TXCTRL_RATE2_TXEQ_POLARITY_3_0                    (0xf<<4) // TX rate2 coefficent polarity
28437     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X185_TXCTRL_RATE2_TXEQ_POLARITY_3_0_SHIFT              4
28438 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186                                                       0x002ae8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28439     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_TXCTRL_RATE3_TXEQ_POLARITY_3_0                    (0xf<<0) // TX rate3 coefficent polarity
28440     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_TXCTRL_RATE3_TXEQ_POLARITY_3_0_SHIFT              0
28441     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_TXCTRL_MASTER_TXEQ_POLARITY_OVR_3_0               (0xf<<4) // TX master coefficient polarity overrides.
28442     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X186_TXCTRL_MASTER_TXEQ_POLARITY_OVR_3_0_SHIFT         4
28443 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187                                                       0x002aecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28444     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE12_3_0     (0xf<<0) // PIPE tx_margin low swing setting
28445     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE12_3_0_SHIFT 0
28446     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE12_3_0     (0xf<<4) // PIPE tx_margin low swing setting
28447     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X187_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE12_3_0_SHIFT 4
28448 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188                                                       0x002af0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28449     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE12_3_0     (0xf<<0) // PIPE tx_margin low swing setting
28450     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE12_3_0_SHIFT 0
28451     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE12_3_0     (0xf<<4) // PIPE tx_margin low swing setting
28452     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X188_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE12_3_0_SHIFT 4
28453 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189                                                       0x002af4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28454     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE12_3_0     (0xf<<0) // PIPE tx_margin low swing setting
28455     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE12_3_0_SHIFT 0
28456     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE12_3_0     (0xf<<4) // PIPE tx_margin low swing setting
28457     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X189_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE12_3_0_SHIFT 4
28458 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190                                                       0x002af8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28459     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE12_3_0     (0xf<<0) // PIPE tx_margin low swing setting
28460     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE12_3_0_SHIFT 0
28461     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE12_3_0     (0xf<<4) // PIPE tx_margin low swing setting
28462     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X190_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE12_3_0_SHIFT 4
28463 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191                                                       0x002afcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28464     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE12_3_0    (0xf<<0) // PIPE tx_margin full swing setting
28465     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE12_3_0_SHIFT 0
28466     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE12_3_0    (0xf<<4) // PIPE tx_margin full swing setting
28467     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X191_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE12_3_0_SHIFT 4
28468 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192                                                       0x002b00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28469     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE12_3_0    (0xf<<0) // PIPE tx_margin full swing setting
28470     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE12_3_0_SHIFT 0
28471     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE12_3_0    (0xf<<4) // PIPE tx_margin full swing setting
28472     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X192_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE12_3_0_SHIFT 4
28473 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193                                                       0x002b04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28474     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE12_3_0    (0xf<<0) // PIPE tx_margin full swing setting
28475     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE12_3_0_SHIFT 0
28476     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE12_3_0    (0xf<<4) // PIPE tx_margin full swing setting
28477     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X193_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE12_3_0_SHIFT 4
28478 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194                                                       0x002b08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28479     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE12_3_0    (0xf<<0) // PIPE tx_margin full swing setting
28480     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE12_3_0_SHIFT 0
28481     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE12_3_0    (0xf<<4) // PIPE tx_margin full swing setting
28482     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X194_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE12_3_0_SHIFT 4
28483 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X195                                                       0x002b0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28484     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X195_TXCTRL_MASTER_ATT_IN_OVR_3_0                      (0xf<<0) // Override  value for att in.
28485     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X195_TXCTRL_MASTER_ATT_IN_OVR_3_0_SHIFT                0
28486     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X195_UNUSED_0                                          (0xf<<4) // reserved
28487     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X195_UNUSED_0_SHIFT                                    4
28488 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196                                                       0x002b10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28489     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE1_TX_SLEW_SLD_1_0                      (0x3<<0) // TX rate1 slew rate setting
28490     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE1_TX_SLEW_SLD_1_0_SHIFT                0
28491     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE2_TX_SLEW_SLD_1_0                      (0x3<<2) // TX rate2 slew rate setting
28492     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE2_TX_SLEW_SLD_1_0_SHIFT                2
28493     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE3_TX_SLEW_SLD_1_0                      (0x3<<4) // TX rate3 slew rate setting
28494     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_RATE3_TX_SLEW_SLD_1_0_SHIFT                4
28495     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_MASTER_TX_SLEW_SLD_OVR_1_0                 (0x3<<6) // TX master slew rate setting overrides.
28496     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X196_TXCTRL_MASTER_TX_SLEW_SLD_OVR_1_0_SHIFT           6
28497 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197                                                       0x002b14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28498     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_PREEM_1LSB_MODE                            (0x1<<0) // TX 1lsb mode
28499     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_PREEM_1LSB_MODE_SHIFT                      0
28500     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_MASTER_PREEM_1LSB_MODE_OVR                 (0x1<<1) // TX master 1lsb mode overrides.
28501     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_MASTER_PREEM_1LSB_MODE_OVR_SHIFT           1
28502     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_RATE1_TX_SLEW_SLD3F_2_0                    (0x7<<2) // TX enable fastest slew rate set to 1.
28503     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_RATE1_TX_SLEW_SLD3F_2_0_SHIFT              2
28504     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_RATE2_TX_SLEW_SLD3F_2_0                    (0x7<<5) // TX enable fastest slew rate set to 1.
28505     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X197_TXCTRL_RATE2_TX_SLEW_SLD3F_2_0_SHIFT              5
28506 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198                                                       0x002b18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28507     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_RATE3_TX_SLEW_SLD3F_2_0                    (0x7<<0) // TX enable fastest slew rate set to 1.
28508     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_RATE3_TX_SLEW_SLD3F_2_0_SHIFT              0
28509     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_TX_SLEW_SLD3F_OVR_2_0               (0x7<<3) // TX enable fastest slew rate override.
28510     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_TX_SLEW_SLD3F_OVR_2_0_SHIFT         3
28511     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_OVR_EN_O                            (0x1<<6) // Tx control master override enable
28512     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_TXCTRL_MASTER_OVR_EN_O_SHIFT                      6
28513     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_UNUSED_0                                          (0x1<<7) // reserved
28514     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X198_UNUSED_0_SHIFT                                    7
28515 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X199                                                       0x002b1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28516     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X199_TXCTRL_RATE1_FULLSWG_C1_IN_4_0                    (0x1f<<0) // TX rate1 full swing C1 coefficient
28517     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X199_TXCTRL_RATE1_FULLSWG_C1_IN_4_0_SHIFT              0
28518     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X199_UNUSED_0                                          (0x7<<5) // reserved
28519     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X199_UNUSED_0_SHIFT                                    5
28520 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X200                                                       0x002b20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28521     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X200_TXCTRL_RATE1_LOWSWG_C1_IN_4_0                     (0x1f<<0) // TX rate1 low swing C1 coefficient
28522     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X200_TXCTRL_RATE1_LOWSWG_C1_IN_4_0_SHIFT               0
28523     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X200_UNUSED_0                                          (0x7<<5) // reserved
28524     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X200_UNUSED_0_SHIFT                                    5
28525 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201                                                       0x002b24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28526     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_TXCTRL_RATE1_FULLSWG_C2_IN_3_0                    (0xf<<0) // TX rate1 full swing C2 coefficient
28527     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_TXCTRL_RATE1_FULLSWG_C2_IN_3_0_SHIFT              0
28528     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_TXCTRL_RATE1_LOWSWG_C2_IN_3_0                     (0xf<<4) // TX rate1 low swing C2 coefficient
28529     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X201_TXCTRL_RATE1_LOWSWG_C2_IN_3_0_SHIFT               4
28530 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X202                                                       0x002b28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28531     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X202_TXCTRL_RATE2_FULLSWG_6DB_C1_IN_4_0                (0x1f<<0) // TX rate2 full swing C1 coefficient for 6 dB
28532     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X202_TXCTRL_RATE2_FULLSWG_6DB_C1_IN_4_0_SHIFT          0
28533     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X202_UNUSED_0                                          (0x7<<5) // reserved
28534     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X202_UNUSED_0_SHIFT                                    5
28535 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X203                                                       0x002b2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28536     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X203_TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_4_0              (0x1f<<0) // TX rate2 full swing C1 coefficient for 3.5 dB
28537     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X203_TXCTRL_RATE2_FULLSWG_3P5DB_C1_IN_4_0_SHIFT        0
28538     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X203_UNUSED_0                                          (0x7<<5) // reserved
28539     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X203_UNUSED_0_SHIFT                                    5
28540 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204                                                       0x002b30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28541     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_TXCTRL_RATE2_FULLSWG_6DB_C2_IN_3_0                (0xf<<0) // TX rate2 full swing C2 coefficient for 6 dB
28542     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_TXCTRL_RATE2_FULLSWG_6DB_C2_IN_3_0_SHIFT          0
28543     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_3_0              (0xf<<4) // TX rate2 full swing C2 coefficient for 3.5 dB
28544     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X204_TXCTRL_RATE2_FULLSWG_3P5DB_C2_IN_3_0_SHIFT        4
28545 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X205                                                       0x002b34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28546     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X205_TXCTRL_RATE2_LOWSWG_C1_IN_4_0                     (0x1f<<0) // TX rate2 low swing C1 coefficient for 6 dB
28547     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X205_TXCTRL_RATE2_LOWSWG_C1_IN_4_0_SHIFT               0
28548     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X205_UNUSED_0                                          (0x7<<5) // reserved
28549     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X205_UNUSED_0_SHIFT                                    5
28550 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206                                                       0x002b38UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28551     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_TXCTRL_RATE2_LOWSWG_C2_IN_3_0                     (0xf<<0) // TX rate2 low swing C2 coefficient for 6 dB
28552     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_TXCTRL_RATE2_LOWSWG_C2_IN_3_0_SHIFT               0
28553     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_TXCTRL_RATE3_C2_IN_3_0                            (0xf<<4) // TX rate3 C2 coefficient
28554     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X206_TXCTRL_RATE3_C2_IN_3_0_SHIFT                      4
28555 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X207                                                       0x002b3cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28556     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X207_TXCTRL_MASTER_C1_IN_OVR_4_0                       (0x1f<<0) // TX master C1 coefficient overrides.
28557     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X207_TXCTRL_MASTER_C1_IN_OVR_4_0_SHIFT                 0
28558     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X207_UNUSED_0                                          (0x7<<5) // reserved
28559     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X207_UNUSED_0_SHIFT                                    5
28560 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208                                                       0x002b40UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28561     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_TXCTRL_MASTER_C2_IN_OVR_3_0                       (0xf<<0) // TX master C2 coefficient overrides.
28562     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_TXCTRL_MASTER_C2_IN_OVR_3_0_SHIFT                 0
28563     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_TXCTRL_RATE1_CM_IN_3_0                            (0xf<<4) // TX rate1 CM coefficient
28564     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X208_TXCTRL_RATE1_CM_IN_3_0_SHIFT                      4
28565 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209                                                       0x002b44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28566     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_TXCTRL_RATE2_CM_IN_3_0                            (0xf<<0) // TX rate2 CM coefficient
28567     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_TXCTRL_RATE2_CM_IN_3_0_SHIFT                      0
28568     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_TXCTRL_MASTER_CM_IN_OVR_3_0                       (0xf<<4) // TX master CM coefficient overrides.
28569     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X209_TXCTRL_MASTER_CM_IN_OVR_3_0_SHIFT                 4
28570 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210                                                       0x002b48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28571     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_REDUCED_SWING_LF_VAL_O_5_0                        (0x3f<<0) // Reduced swing LowFreq value
28572     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_REDUCED_SWING_LF_VAL_O_5_0_SHIFT                  0
28573     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O                           (0x1<<6) // Brings the TxEq pre-cursor down to a programmable value txeq_cm1_min_limit if pre cursor tuning is bypassed
28574     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_CM1_FORCE_LOW_EN_O_SHIFT                     6
28575     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O                            (0x1<<7) // Brings the TxEq pre-cursor down to a programmable value txeq_c1_min_limit if pre cursor tuning is bypassed
28576     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X210_TXEQ_C1_FORCE_LOW_EN_O_SHIFT                      7
28577 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211                                                       0x002b4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28578     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_00_O_2_0                                  (0x7<<0) // AFE rx_bias setting. Used when rxvcodiv is 00
28579     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_00_O_2_0_SHIFT                            0
28580     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0                                  (0x7<<3) // AFE rx_bias setting. Used when rxvcodiv is 01 or 10
28581     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_RX_BIAS_01_O_2_0_SHIFT                            3
28582     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_UNUSED_0                                          (0x3<<6) // reserved
28583     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X211_UNUSED_0_SHIFT                                    6
28584 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X212                                                       0x002b50UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28585     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X212_RX_BIAS_11_O_2_0                                  (0x7<<0) // AFE rx_bias setting. Used when rxvcodiv is 11
28586     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X212_RX_BIAS_11_O_2_0_SHIFT                            0
28587     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X212_UNUSED_0                                          (0x1f<<3) // reserved
28588     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X212_UNUSED_0_SHIFT                                    3
28589 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213                                                       0x002b54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28590     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_UNUSED_0                                          (0x3f<<0) // reserved
28591     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_UNUSED_0_SHIFT                                    0
28592     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O                        (0x1<<6) // Enable phase detector during CDR VCO calibration
28593     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_QAHB_CDR_VCO_CAL_PHD_ENA_O_SHIFT                  6
28594     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_UNUSED_1                                          (0x1<<7) // reserved
28595     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X213_UNUSED_1_SHIFT                                    7
28596 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214                                                       0x002b58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28597     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_CDR_LOCK_WAIT_O_3_0                          (0xf<<0) // Number of wait cycles for the CDR to lock [3:0] times 64
28598     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_CDR_LOCK_WAIT_O_3_0_SHIFT                    0
28599     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O                              (0x1<<4) // Assertion causes repeat of calibration for rate switch or electrical idle exit. Calibrations to be performed are selected by rxeq_recal_o[6:0]/rxeq_rate2_recal_o[6:0].
28600     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_RATE_CHNG_CAL_O_SHIFT                        4
28601     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_UNUSED_0                                          (0x1<<5) // reserved
28602     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_UNUSED_0_SHIFT                                    5
28603     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O                             (0x1<<6) // Set all DFE calibration values to mid-scale instead of using start values at start of calibration
28604     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_RXEQ_PRESET_CLR_DFE_O_SHIFT                       6
28605     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_UNUSED_1                                          (0x1<<7) // reserved
28606     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X214_UNUSED_1_SHIFT                                    7
28607 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X215                                                       0x002b5cUL //Access:RW   DataWidth:0x8   DFE block -continuous calibration wait delay. DFE block will wait this number of cycles between each continuous calibration cycle  Chips: K2
28608 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X216                                                       0x002b60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28609     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X216_RXEQ_CONT_LENGTH_O_14_8                           (0x7f<<0) // DFE block -continuous calibration wait delay. DFE block will wait this number of cycles between each continuous calibration cycle
28610     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X216_RXEQ_CONT_LENGTH_O_14_8_SHIFT                     0
28611     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X216_UNUSED_0                                          (0x1<<7) // reserved
28612     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X216_UNUSED_0_SHIFT                                    7
28613 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X217                                                       0x002b64UL //Access:RW   DataWidth:0x8   DFE block - ATT calibration cycle length. This is the number of cycles the DFE will wait between changing the ATT value and examining the output.  Chips: K2
28614 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X218                                                       0x002b68UL //Access:RW   DataWidth:0x8   DFE block - Boost calibration cycle length. This is the number of cycles the DFE will wait between changing the boost value and examining the output.  Chips: K2
28615 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X219                                                       0x002b6cUL //Access:RW   DataWidth:0x8   DFE block - TAP1 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP1 value and examining the output.  Chips: K2
28616 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X220                                                       0x002b70UL //Access:RW   DataWidth:0x8   DFE block - TAP2 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.  Chips: K2
28617 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X221                                                       0x002b74UL //Access:RW   DataWidth:0x8   DFE block - TAP3 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.  Chips: K2
28618 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X222                                                       0x002b78UL //Access:RW   DataWidth:0x8   DFE block - TAP4 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.  Chips: K2
28619 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X223                                                       0x002b7cUL //Access:RW   DataWidth:0x8   DFE block - TAP5 calibration cycle length. This is the number of cycles the DFE will wait between changing the TAP2 value and examining the output.  Chips: K2
28620 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224                                                       0x002b80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28621     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O                                (0x1<<0) // Repeat calibration whenever exiting RX electrical idle. Calibrations performed are selected by rxeq_recal_o[6:0]/rxeq_lane2_recal_o[6:0]
28622     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_EI_EXIT_CAL_O_SHIFT                          0
28623     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0                                  (0x7f<<1) // Enables re-calibration for { Tap5, Tap4, Tap3, Tap2, Tap1, Boost, ATT} at rate3 after exit from electrical idle when rxeq_ei_exit_cal_o is asserted and after rate change when rxeq_rate_chng_cal_o is asserted.
28624     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X224_RXEQ_RECAL_O_6_0_SHIFT                            1
28625 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225                                                       0x002b84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28626     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_RXEQ_RATE2_INIT_CAL_O_6_0                         (0x7f<<0) // Specify which block needs initial calibration upon exit from RX electrical idle state for rate2: bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bit [2]: Enables DFE Tap1 calibration when asserted bit [3]: Enables DFE Tap2 calibration when asserted bit [4]: Enables DFE Tap3 calibration when asserted bit [5]: Enables DFE Tap4 calibration when asserted bit [6]: Enables DFE Tap5 calibration when asserted
28627     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_RXEQ_RATE2_INIT_CAL_O_6_0_SHIFT                   0
28628     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_UNUSED_0                                          (0x1<<7) // reserved
28629     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X225_UNUSED_0_SHIFT                                    7
28630 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X226                                                       0x002b88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28631     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X226_RXEQ_RATE2_CONT_CAL_O_6_0                         (0x7f<<0) // Specify which block needs continuous calibration during RX data reception for rate2 bit [0]: Enables ATT calibration when asserted bit [1]: Enables Boost calibration when asserted bit [2]: Enables DFE Tap1 calibration when asserted bit [3]: Enables DFE Tap2 calibration when asserted bit [4]: Enables DFE Tap3 calibration when asserted bit [5]: Enables DFE Tap4 calibration when asserted bit [6]: Enables DFE Tap5 calibration when asserted
28632     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X226_RXEQ_RATE2_CONT_CAL_O_6_0_SHIFT                   0
28633     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X226_UNUSED_0                                          (0x1<<7) // reserved
28634     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X226_UNUSED_0_SHIFT                                    7
28635 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X227                                                       0x002b8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28636     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X227_RXEQ_RATE2_RECAL_O_6_0                            (0x7f<<0) // Enables re-calibration for { Tap5, Tap4, Tap3, Tap2, Tap1, Boost, ATT} at rate2 after exit from electrical idle when rxeq_ei_exit_cal_o is asserted and after rate change when rxeq_rate_chng_cal_o is asserted.
28637     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X227_RXEQ_RATE2_RECAL_O_6_0_SHIFT                      0
28638     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X227_UNUSED_0                                          (0x1<<7) // reserved
28639     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X227_UNUSED_0_SHIFT                                    7
28640 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228                                                       0x002b90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28641     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_ATT_BOUNCE_O_3_0                             (0xf<<0) // Number of bounces before calibration stops for ATT
28642     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_ATT_BOUNCE_O_3_0_SHIFT                       0
28643     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_BOOST_BOUNCE_O_3_0                           (0xf<<4) // Number of bounces before calibration stops for Boost
28644     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X228_RXEQ_BOOST_BOUNCE_O_3_0_SHIFT                     4
28645 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229                                                       0x002b94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28646     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP1_BOUNCE_O_3_0                            (0xf<<0) // Number of bounces before calibration stops for DFE tap1
28647     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP1_BOUNCE_O_3_0_SHIFT                      0
28648     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP2_BOUNCE_O_3_0                            (0xf<<4) // Number of bounces before calibration stops for DFE tap2
28649     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X229_RXEQ_TAP2_BOUNCE_O_3_0_SHIFT                      4
28650 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230                                                       0x002b98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28651     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP3_BOUNCE_O_3_0                            (0xf<<0) // Number of bounces before calibration stops for DFE tap3
28652     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP3_BOUNCE_O_3_0_SHIFT                      0
28653     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP4_BOUNCE_O_3_0                            (0xf<<4) // Number of bounces before calibration stops for DFE tap4
28654     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X230_RXEQ_TAP4_BOUNCE_O_3_0_SHIFT                      4
28655 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231                                                       0x002b9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28656     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_TAP5_BOUNCE_O_3_0                            (0xf<<0) // Number of bounces before calibration stops for DFE tap5
28657     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_TAP5_BOUNCE_O_3_0_SHIFT                      0
28658     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_COARSE_STEP_SIZE_O_3_0                       (0xf<<4) // Initial calibration coarse step size
28659     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X231_RXEQ_COARSE_STEP_SIZE_O_3_0_SHIFT                 4
28660 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X232                                                       0x002ba0UL //Access:RW   DataWidth:0x8   comparator offset override value  Chips: K2
28661 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233                                                       0x002ba4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28662     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O                               (0x1<<0) // comparator offset override enable
28663     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_CMP_OFFSET_OVR_EN_O_SHIFT                         0
28664     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0                               (0x7f<<1) // Enable final calibration value plus one for individual blocks
28665     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X233_RXEQ_FIN_HIGH_O_6_0_SHIFT                         1
28666 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234                                                       0x002ba8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28667     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_RXEQ_FIN_LOW_O_6_0                                (0x7f<<0) // Enable final calibration value minus one for individual blocks
28668     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_RXEQ_FIN_LOW_O_6_0_SHIFT                          0
28669     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O                              (0x1<<7) // Testbus select for comp_offset and tap_offset 1: Raw output from i_dfe_tap_dc_offset 0: Input to pma
28670     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X234_QAHB_DFE_RAW_VALUE_O_SHIFT                        7
28671 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X235                                                       0x002bacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28672     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X235_RXEQ_ERR_SIGN_O_6_0                               (0x7f<<0) // Controls polarity of RX calibration: bit [0]: Reverses polarity of ATT calibration when asserted bit [1]: Reverses polarity of Boost calibration when asserted bit [2]: Reverses polarity of DFE Tap1 calibration when asserted bit [3]: Reverses polarity of DFE Tap2 calibration when asserted bit [4]: Reverses polarity of DFE Tap3 calibration when asserted bit [5]: Reverses polarity of DFE Tap4 calibration when asserted bit [6]: Reverses polarity of DFE Tap5 calibration when asserted
28673     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X235_RXEQ_ERR_SIGN_O_6_0_SHIFT                         0
28674     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X235_UNUSED_0                                          (0x1<<7) // reserved
28675     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X235_UNUSED_0_SHIFT                                    7
28676 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X236                                                       0x002bb0UL //Access:RW   DataWidth:0x8   Training pattern for boost  Chips: K2
28677 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237                                                       0x002bb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28678     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8                (0x1<<0) // Training pattern for boost
28679     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237_RXEQ_RATE1_BOOST_TRAINING_PATT_O_8_SHIFT          0
28680     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237_UNUSED_0                                          (0x7f<<1) // reserved
28681     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X237_UNUSED_0_SHIFT                                    1
28682 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X238                                                       0x002bb8UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap1  Chips: K2
28683 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239                                                       0x002bbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28684     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8                       (0x1<<0) // Training pattern for DFE tap1
28685     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239_RXEQ_TAP1_TRAINING_PATT_O_8_SHIFT                 0
28686     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239_UNUSED_0                                          (0x7f<<1) // reserved
28687     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X239_UNUSED_0_SHIFT                                    1
28688 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X240                                                       0x002bc0UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap2  Chips: K2
28689 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241                                                       0x002bc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28690     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8                       (0x1<<0) // Training pattern for DFE tap2
28691     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241_RXEQ_TAP2_TRAINING_PATT_O_8_SHIFT                 0
28692     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241_UNUSED_0                                          (0x7f<<1) // reserved
28693     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X241_UNUSED_0_SHIFT                                    1
28694 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X242                                                       0x002bc8UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap3  Chips: K2
28695 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243                                                       0x002bccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28696     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8                       (0x1<<0) // Training pattern for DFE tap3
28697     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243_RXEQ_TAP3_TRAINING_PATT_O_8_SHIFT                 0
28698     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243_UNUSED_0                                          (0x7f<<1) // reserved
28699     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X243_UNUSED_0_SHIFT                                    1
28700 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X244                                                       0x002bd0UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap4  Chips: K2
28701 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245                                                       0x002bd4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28702     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8                       (0x1<<0) // Training pattern for DFE tap4
28703     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245_RXEQ_TAP4_TRAINING_PATT_O_8_SHIFT                 0
28704     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245_UNUSED_0                                          (0x7f<<1) // reserved
28705     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X245_UNUSED_0_SHIFT                                    1
28706 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X246                                                       0x002bd8UL //Access:RW   DataWidth:0x8   Training pattern for DFE tap5  Chips: K2
28707 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247                                                       0x002bdcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28708     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8                       (0x1<<0) // Training pattern for DFE tap5
28709     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247_RXEQ_TAP5_TRAINING_PATT_O_8_SHIFT                 0
28710     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247_UNUSED_0                                          (0x7f<<1) // reserved
28711     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X247_UNUSED_0_SHIFT                                    1
28712 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248                                                       0x002be0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28713     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_DONT_CARE_O_5_0                              (0x3f<<0) // Sets certain bits in training pattern as don't care
28714     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_DONT_CARE_O_5_0_SHIFT                        0
28715     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O                                  (0x1<<6) // RXEQ ctrl_test mode enable
28716     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_MODE_O_SHIFT                            6
28717     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O                                       (0x1<<7) // Step calibration in test mode, rising edge triggers step
28718     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X248_RXEQ_STEP_O_SHIFT                                 7
28719 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249                                                       0x002be4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28720     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_AVG4_O_6_0                                   (0x7f<<0) // Enable average 4 in calibration, otherwise average2
28721     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_AVG4_O_6_0_SHIFT                             0
28722     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O                                      (0x1<<7) // Take the floor of the calibration result
28723     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X249_RXEQ_FLOOR_O_SHIFT                                7
28724 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X250                                                       0x002be8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28725     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X250_RXEQ_SHIFT_O_3_0                                  (0xf<<0) // Shift the edge samples in rxeq_ctrl
28726     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X250_RXEQ_SHIFT_O_3_0_SHIFT                            0
28727     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X250_UNUSED_0                                          (0xf<<4) // reserved
28728     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X250_UNUSED_0_SHIFT                                    4
28729 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X251                                                       0x002becUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28730     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X251_RXEQ_RATE3_DFE_TAP_PD_O_4_0                       (0x1f<<0) // DFE tap powerdown for rate3
28731     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X251_RXEQ_RATE3_DFE_TAP_PD_O_4_0_SHIFT                 0
28732     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X251_UNUSED_0                                          (0x7<<5) // reserved
28733     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X251_UNUSED_0_SHIFT                                    5
28734 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252                                                       0x002bf0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28735     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_RXEQ_RATE2_DFE_TAP_PD_O_4_0                       (0x1f<<0) // DFE tap powerdown for rate2
28736     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_RXEQ_RATE2_DFE_TAP_PD_O_4_0_SHIFT                 0
28737     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O                            (0x1<<5) // Reverse order of tap power down signals
28738     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_REVERSE_TAP_PD_ORDER_O_SHIFT                      5
28739     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_UNUSED_0                                          (0x3<<6) // reserved
28740     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X252_UNUSED_0_SHIFT                                    6
28741 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253                                                       0x002bf4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28742     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_MSM_LN_DFE_TAP_WAIT_O_4_0                         (0x1f<<0) // Wait time between each DFE tap DC offset calibration
28743     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_MSM_LN_DFE_TAP_WAIT_O_4_0_SHIFT                   0
28744     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O                                     (0x1<<5) // By pass comparator DC offset calibration
28745     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_SKP_CMP_CAL_O_SHIFT                               5
28746     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O                          (0x1<<6) // Changes the dfe tap offset cal direction
28747     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_DFE_TAP_OFFSET_CAL_DIR_O_SHIFT                    6
28748     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_UNUSED_0                                          (0x1<<7) // reserved
28749     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X253_UNUSED_0_SHIFT                                    7
28750 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X254                                                       0x002bf8UL //Access:RW   DataWidth:0x8   Training pattern for boost in rate2  Chips: K2
28751 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255                                                       0x002bfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28752     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8                (0x1<<0) // Training pattern for boost in rate2
28753     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255_RXEQ_RATE2_BOOST_TRAINING_PATT_O_8_SHIFT          0
28754     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255_UNUSED_0                                          (0x7f<<1) // reserved
28755     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X255_UNUSED_0_SHIFT                                    1
28756 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X256                                                       0x002c00UL //Access:RW   DataWidth:0x8   Training pattern for boost in rate3  Chips: K2
28757 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257                                                       0x002c04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28758     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8                (0x1<<0) // Training pattern for boost in rate3
28759     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257_RXEQ_RATE3_BOOST_TRAINING_PATT_O_8_SHIFT          0
28760     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257_UNUSED_0                                          (0x7f<<1) // reserved
28761     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X257_UNUSED_0_SHIFT                                    1
28762 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X258                                                       0x002c08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28763     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X258_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0                  (0x3f<<0) // Sets certain bits in training pattern as don't care in rate1
28764     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X258_RXEQ_RATE1_BOOST_DONT_CARE_O_5_0_SHIFT            0
28765     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X258_UNUSED_0                                          (0x3<<6) // reserved
28766     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X258_UNUSED_0_SHIFT                                    6
28767 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X259                                                       0x002c0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28768     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X259_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0                  (0x3f<<0) // Sets certain bits in training pattern as don't care in rate2
28769     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X259_RXEQ_RATE2_BOOST_DONT_CARE_O_5_0_SHIFT            0
28770     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X259_UNUSED_0                                          (0x3<<6) // reserved
28771     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X259_UNUSED_0_SHIFT                                    6
28772 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X260                                                       0x002c10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28773     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X260_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0                  (0x3f<<0) // Sets certain bits in training pattern as don't care in rate3
28774     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X260_RXEQ_RATE3_BOOST_DONT_CARE_O_5_0_SHIFT            0
28775     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X260_UNUSED_0                                          (0x3<<6) // reserved
28776     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X260_UNUSED_0_SHIFT                                    6
28777 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261                                                       0x002c14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28778     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_UNUSED_0                                          (0x1f<<0) // reserved
28779     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_UNUSED_0_SHIFT                                    0
28780     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_LANE_SEL                               (0x3<<5) // DFE TAP shadow register lane select
28781     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_LANE_SEL_SHIFT                         5
28782     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL                            (0x1<<7) // DFE shadow offset read select
28783     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X261_DFE_SHADOW_OFST_RD_SEL_SHIFT                      7
28784 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X263                                                       0x002c1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28785     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X263_RATE3_RATESWITCH_RXRECAL_CFG_6_0                  (0x7f<<0) // Gen3 rate switch cal elements
28786     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X263_RATE3_RATESWITCH_RXRECAL_CFG_6_0_SHIFT            0
28787     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X263_UNUSED_0                                          (0x1<<7) // reserved
28788     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X263_UNUSED_0_SHIFT                                    7
28789 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X264                                                       0x002c20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28790     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X264_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0                  (0x7f<<0) // Gen3 beginning of TxEQ RxEQ cal elements
28791     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X264_RATE3_TXEQ_RXRECAL_BEGIN_CFG_6_0_SHIFT            0
28792     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X264_UNUSED_0                                          (0x1<<7) // reserved
28793     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X264_UNUSED_0_SHIFT                                    7
28794 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X265                                                       0x002c24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28795     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X265_RATE3_TXEQ_RXRECAL_END_CFG_6_0                    (0x7f<<0) // Gen3 end of TxEQ RxEQ cal elements
28796     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X265_RATE3_TXEQ_RXRECAL_END_CFG_6_0_SHIFT              0
28797     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X265_UNUSED_0                                          (0x1<<7) // reserved
28798     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X265_UNUSED_0_SHIFT                                    7
28799 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X266                                                       0x002c28UL //Access:R    DataWidth:0x8   DFE CMP value read  Chips: K2
28800 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X267                                                       0x002c2cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
28801     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X267_DFE_TAP1_VAL                                      (0x7f<<0) // DFE TAP1 value read
28802     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X267_DFE_TAP1_VAL_SHIFT                                0
28803     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X267_UNUSED_0                                          (0x1<<7) // reserved
28804     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X267_UNUSED_0_SHIFT                                    7
28805 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X268                                                       0x002c30UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
28806     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X268_DFE_TAP2_VAL                                      (0x3f<<0) // DFE TAP2 value read
28807     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X268_DFE_TAP2_VAL_SHIFT                                0
28808     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X268_UNUSED_0                                          (0x3<<6) // reserved
28809     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X268_UNUSED_0_SHIFT                                    6
28810 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X269                                                       0x002c34UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
28811     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X269_DFE_TAP3_VAL                                      (0x3f<<0) // DFE TAP3 value read
28812     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X269_DFE_TAP3_VAL_SHIFT                                0
28813     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X269_UNUSED_0                                          (0x3<<6) // reserved
28814     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X269_UNUSED_0_SHIFT                                    6
28815 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X270                                                       0x002c38UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
28816     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X270_DFE_TAP4_VAL                                      (0x3f<<0) // DFE TAP4 value read
28817     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X270_DFE_TAP4_VAL_SHIFT                                0
28818     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X270_UNUSED_0                                          (0x3<<6) // reserved
28819     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X270_UNUSED_0_SHIFT                                    6
28820 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X271                                                       0x002c3cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
28821     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X271_DFE_TAP5_VAL                                      (0x3f<<0) // DFE TAP5 value read
28822     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X271_DFE_TAP5_VAL_SHIFT                                0
28823     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X271_UNUSED_0                                          (0x3<<6) // reserved
28824     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X271_UNUSED_0_SHIFT                                    6
28825 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X272                                                       0x002c40UL //Access:RW   DataWidth:0x8   Training pattern for TxEQ adapt DFE tap1 cm1 [7:0]  Chips: K2
28826 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273                                                       0x002c44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28827     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8                          (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 cm1 [8]
28828     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TAP1_CM1_TRAINING_PATT_8_SHIFT                    0
28829     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0                                (0x3<<1) // TxEQ Adapt 2 TAPs
28830     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_TXEQ_ADAPT_RUN_1_0_SHIFT                          1
28831     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_UNUSED_0                                          (0x1f<<3) // reserved
28832     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X273_UNUSED_0_SHIFT                                    3
28833 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X274                                                       0x002c48UL //Access:RW   DataWidth:0x8   Training pattern for TxEQ adapt DFE tap1 c1 [7:0]  Chips: K2
28834 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275                                                       0x002c4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28835     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8                           (0x1<<0) // Training pattern for TxEQ adapt DFE tap1 c1 [8]
28836     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TAP1_C1_TRAINING_PATT_8_SHIFT                     0
28837     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1                               (0x1<<1) // Initiate TXEQ adaptation for Gen3 rate
28838     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_TXEQ_ADAPT_INIT_O_1_SHIFT                         1
28839     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_UNUSED_0                                          (0x3f<<2) // reserved
28840     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X275_UNUSED_0_SHIFT                                    2
28841 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X276                                                       0x002c50UL //Access:RW   DataWidth:0x8   TX Equalizer Training Pattern select  Chips: K2
28842 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277                                                       0x002c54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28843     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277_TXEQ_TRAINING_PATT_O_8                            (0x1<<0) // TX Equalizer Training Pattern select
28844     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277_TXEQ_TRAINING_PATT_O_8_SHIFT                      0
28845     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277_UNUSED_0                                          (0x7f<<1) // reserved
28846     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X277_UNUSED_0_SHIFT                                    1
28847 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X278                                                       0x002c58UL //Access:RW   DataWidth:0x8   TX Equalizer Training Pattern mask during Link Training  Chips: K2
28848 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279                                                       0x002c5cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28849     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279_TXEQ_DONT_CARE_O_8                                (0x1<<0) // TX Equalizer Training Pattern mask during Link Training
28850     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279_TXEQ_DONT_CARE_O_8_SHIFT                          0
28851     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279_UNUSED_0                                          (0x7f<<1) // reserved
28852     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X279_UNUSED_0_SHIFT                                    1
28853 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X280                                                       0x002c60UL //Access:RW   DataWidth:0x8   Number of Link Training frames per TX Equalization Iteration  Chips: K2
28854 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281                                                       0x002c64UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
28855     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_RXEQ_CAL_DONE_I_3_0                               (0xf<<0) // RXEQ calibration done status - per lane
28856     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_RXEQ_CAL_DONE_I_3_0_SHIFT                         0
28857     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_TXEQ_ADAPT_DONE_I_3_0                             (0xf<<4) // TXEQ Adapt Done status - per lane
28858     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X281_TXEQ_ADAPT_DONE_I_3_0_SHIFT                       4
28859 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282                                                       0x002c68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28860     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_TXEQ_ADAPT_CM1_CHNG_DIR_SUM_THRESHOLD_O           (0xf<<0) // CM1 coefficient change direction sum threshold value
28861     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_TXEQ_ADAPT_CM1_CHNG_DIR_SUM_THRESHOLD_O_SHIFT     0
28862     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_TXEQ_ADAPT_C1_CHNG_DIR_SUM_THRESHOLD_O_3_0        (0xf<<4) // C1 coefficient change direction sum threshold value
28863     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X282_TXEQ_ADAPT_C1_CHNG_DIR_SUM_THRESHOLD_O_3_0_SHIFT  4
28864 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X283                                                       0x002c6cUL //Access:RW   DataWidth:0x8   Txeq adaptation iteration count threshold  Chips: K2
28865 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X284                                                       0x002c70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28866     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X284_LATENCY_CHK_CONTROL_O                             (0x1f<<0) // Bit 4 - latency check control enable Bit 3:0 - latency counter value
28867     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X284_LATENCY_CHK_CONTROL_O_SHIFT                       0
28868     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X284_UNUSED_0                                          (0x7<<5) // reserved
28869     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X284_UNUSED_0_SHIFT                                    5
28870 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285                                                       0x002c74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28871     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE3_3_0      (0xf<<0) // PIPE tx_margin low swing setting rate3
28872     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_TXCTRL_TX_MARGIN_000_LOWSWG_ATT_IN_RATE3_3_0_SHIFT 0
28873     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE3_3_0      (0xf<<4) // PIPE tx_margin low swing setting rate3
28874     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X285_TXCTRL_TX_MARGIN_001_LOWSWG_ATT_IN_RATE3_3_0_SHIFT 4
28875 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286                                                       0x002c78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28876     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE3_3_0      (0xf<<0) // PIPE tx_margin low swing setting rate3
28877     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_TXCTRL_TX_MARGIN_010_LOWSWG_ATT_IN_RATE3_3_0_SHIFT 0
28878     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE3_3_0      (0xf<<4) // PIPE tx_margin low swing setting rate3
28879     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X286_TXCTRL_TX_MARGIN_011_LOWSWG_ATT_IN_RATE3_3_0_SHIFT 4
28880 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287                                                       0x002c7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28881     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE3_3_0      (0xf<<0) // PIPE tx_margin low swing setting rate3
28882     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_TXCTRL_TX_MARGIN_100_LOWSWG_ATT_IN_RATE3_3_0_SHIFT 0
28883     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE3_3_0      (0xf<<4) // PIPE tx_margin low swing setting rate3
28884     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X287_TXCTRL_TX_MARGIN_101_LOWSWG_ATT_IN_RATE3_3_0_SHIFT 4
28885 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288                                                       0x002c80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28886     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE3_3_0      (0xf<<0) // PIPE tx_margin low swing setting rate3
28887     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_TXCTRL_TX_MARGIN_110_LOWSWG_ATT_IN_RATE3_3_0_SHIFT 0
28888     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE3_3_0      (0xf<<4) // PIPE tx_margin low swing setting rate3
28889     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X288_TXCTRL_TX_MARGIN_111_LOWSWG_ATT_IN_RATE3_3_0_SHIFT 4
28890 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289                                                       0x002c84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28891     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE3_3_0     (0xf<<0) // PIPE tx_margin full swing setting rate3
28892     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_TXCTRL_TX_MARGIN_000_FULLSWG_ATT_IN_RATE3_3_0_SHIFT 0
28893     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE3_3_0     (0xf<<4) // PIPE tx_margin full swing setting rate3
28894     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X289_TXCTRL_TX_MARGIN_001_FULLSWG_ATT_IN_RATE3_3_0_SHIFT 4
28895 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290                                                       0x002c88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28896     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE3_3_0     (0xf<<0) // PIPE tx_margin full swing setting rate3
28897     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_TXCTRL_TX_MARGIN_010_FULLSWG_ATT_IN_RATE3_3_0_SHIFT 0
28898     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE3_3_0     (0xf<<4) // PIPE tx_margin full swing setting rate3
28899     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X290_TXCTRL_TX_MARGIN_011_FULLSWG_ATT_IN_RATE3_3_0_SHIFT 4
28900 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291                                                       0x002c8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28901     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE3_3_0     (0xf<<0) // PIPE tx_margin full swing setting rate3
28902     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_TXCTRL_TX_MARGIN_100_FULLSWG_ATT_IN_RATE3_3_0_SHIFT 0
28903     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE3_3_0     (0xf<<4) // PIPE tx_margin full swing setting rate3
28904     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X291_TXCTRL_TX_MARGIN_101_FULLSWG_ATT_IN_RATE3_3_0_SHIFT 4
28905 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292                                                       0x002c90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28906     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE3_3_0     (0xf<<0) // PIPE tx_margin full swing setting rate3
28907     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_TXCTRL_TX_MARGIN_110_FULLSWG_ATT_IN_RATE3_3_0_SHIFT 0
28908     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE3_3_0     (0xf<<4) // PIPE tx_margin full swing setting rate3
28909     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X292_TXCTRL_TX_MARGIN_111_FULLSWG_ATT_IN_RATE3_3_0_SHIFT 4
28910 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X293                                                       0x002c94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28911     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X293_TXCTRL_RATE12_TX_VREG_LEV_4_0                     (0x1f<<0) // TX driver regulator voltage setting.
28912     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X293_TXCTRL_RATE12_TX_VREG_LEV_4_0_SHIFT               0
28913     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X293_UNUSED_0                                          (0x7<<5) // reserved
28914     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X293_UNUSED_0_SHIFT                                    5
28915 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X294                                                       0x002c98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28916     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X294_TXCTRL_RATE3_TX_VREG_LEV_4_0                      (0x1f<<0) // TX driver regulator voltage setting.
28917     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X294_TXCTRL_RATE3_TX_VREG_LEV_4_0_SHIFT                0
28918     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X294_UNUSED_0                                          (0x7<<5) // reserved
28919     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X294_UNUSED_0_SHIFT                                    5
28920 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X295                                                       0x002c9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28921     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X295_TXCTRL_MASTER_VREG_LEV_OVR_4_0                    (0x1f<<0) // Does not exist!
28922     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X295_TXCTRL_MASTER_VREG_LEV_OVR_4_0_SHIFT              0
28923     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X295_UNUSED_0                                          (0x7<<5) // reserved
28924     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X295_UNUSED_0_SHIFT                                    5
28925 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X296                                                       0x002ca0UL //Access:RW   DataWidth:0x8   Txeq CM1 coefficient adpatation error measurment wait time during each iteration  Chips: K2
28926 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X297                                                       0x002ca4UL //Access:RW   DataWidth:0x8   Txeq C1 coefficient adpatation error measurment wait time during each iteration  Chips: K2
28927 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X301                                                       0x002cb4UL //Access:RW   DataWidth:0x8     Chips: K2
28928 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304                                                       0x002cc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28929     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_LOAD_EYE_CNT_WAIT                 (0xf<<0) //
28930     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_LOAD_EYE_CNT_WAIT_SHIFT           0
28931     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_EYE_IN_RST_WAIT_3_0               (0xf<<4) //
28932     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X304_QAHB_CDFE_RATE3_EYE_IN_RST_WAIT_3_0_SHIFT         4
28933 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305                                                       0x002cc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28934     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_EXIT_EYE_RST_WAIT                 (0xf<<0) //
28935     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_EXIT_EYE_RST_WAIT_SHIFT           0
28936     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_DFE_STROBE_REDGE_WAIT_3_0         (0xf<<4) //
28937     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X305_QAHB_CDFE_RATE3_DFE_STROBE_REDGE_WAIT_3_0_SHIFT   4
28938 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X306                                                       0x002cc8UL //Access:RW   DataWidth:0x8     Chips: K2
28939 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307                                                       0x002cccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28940     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY                       (0x7f<<0) // Minimum eye delay value for rate3 during dll calibration
28941     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_QAHB_CDFE_RATE3_MIN_EYE_DLY_SHIFT                 0
28942     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_UNUSED_0                                          (0x1<<7) // reserved
28943     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X307_UNUSED_0_SHIFT                                    7
28944 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X308                                                       0x002cd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28945     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X308_QAHB_CDFE_RATE3_MAX_EYE_DLY                       (0x7f<<0) // Maximum eye delay value for rate3 during dll calibration
28946     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X308_QAHB_CDFE_RATE3_MAX_EYE_DLY_SHIFT                 0
28947     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X308_UNUSED_0                                          (0x1<<7) // reserved
28948     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X308_UNUSED_0_SHIFT                                    7
28949 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X310                                                       0x002cd8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28950     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X310_QAHB_CDFE_RATE3_TAP1_PATT_MASK_6_0                (0x7f<<0) // cdfe tap1 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
28951     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X310_QAHB_CDFE_RATE3_TAP1_PATT_MASK_6_0_SHIFT          0
28952     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X310_UNUSED_0                                          (0x1<<7) // reserved
28953     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X310_UNUSED_0_SHIFT                                    7
28954 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X311                                                       0x002cdcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28955     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X311_QAHB_CDFE_RATE3_TAP2_PATT_MASK_6_0                (0x7f<<0) // cdfe tap2 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
28956     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X311_QAHB_CDFE_RATE3_TAP2_PATT_MASK_6_0_SHIFT          0
28957     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X311_UNUSED_0                                          (0x1<<7) // reserved
28958     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X311_UNUSED_0_SHIFT                                    7
28959 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X312                                                       0x002ce0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28960     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X312_QAHB_CDFE_RATE3_TAP3_PATT_MASK_6_0                (0x7f<<0) // cdfe tap3 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
28961     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X312_QAHB_CDFE_RATE3_TAP3_PATT_MASK_6_0_SHIFT          0
28962     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X312_UNUSED_0                                          (0x1<<7) // reserved
28963     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X312_UNUSED_0_SHIFT                                    7
28964 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X313                                                       0x002ce4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28965     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X313_QAHB_CDFE_RATE3_TAP4_PATT_MASK_6_0                (0x7f<<0) // cdfe tap4 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
28966     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X313_QAHB_CDFE_RATE3_TAP4_PATT_MASK_6_0_SHIFT          0
28967     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X313_UNUSED_0                                          (0x1<<7) // reserved
28968     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X313_UNUSED_0_SHIFT                                    7
28969 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X314                                                       0x002ce8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28970     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X314_QAHB_CDFE_RATE3_TAP5_PATT_MASK_6_0                (0x7f<<0) // cdfe tap5 training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
28971     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X314_QAHB_CDFE_RATE3_TAP5_PATT_MASK_6_0_SHIFT          0
28972     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X314_UNUSED_0                                          (0x1<<7) // reserved
28973     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X314_UNUSED_0_SHIFT                                    7
28974 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X315                                                       0x002cecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28975     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X315_QAHB_CDFE_RATE3_DLEV_PATT_MASK_6_0                (0x7f<<0) // cdfe dlev training pattern masking bits for Gen 3 when rate is 2'b10. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
28976     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X315_QAHB_CDFE_RATE3_DLEV_PATT_MASK_6_0_SHIFT          0
28977     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X315_UNUSED_0                                          (0x1<<7) // reserved
28978     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X315_UNUSED_0_SHIFT                                    7
28979 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318                                                       0x002cf8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28980     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_LOAD_EYE_CNT_WAIT                 (0xf<<0) //
28981     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_LOAD_EYE_CNT_WAIT_SHIFT           0
28982     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_EYE_IN_RST_WAIT_3_0               (0xf<<4) //
28983     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X318_QAHB_CDFE_RATE2_EYE_IN_RST_WAIT_3_0_SHIFT         4
28984 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319                                                       0x002cfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28985     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_EXIT_EYE_RST_WAIT                 (0xf<<0) //
28986     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_EXIT_EYE_RST_WAIT_SHIFT           0
28987     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_DFE_STROBE_REDGE_WAIT_3_0         (0xf<<4) //
28988     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X319_QAHB_CDFE_RATE2_DFE_STROBE_REDGE_WAIT_3_0_SHIFT   4
28989 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X320                                                       0x002d00UL //Access:RW   DataWidth:0x8     Chips: K2
28990 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X321                                                       0x002d04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28991     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X321_QAHB_CDFE_RATE2_MIN_EYE_DLY_6_0                   (0x7f<<0) // Minimum eye delay value for rate2 during dll calibration
28992     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X321_QAHB_CDFE_RATE2_MIN_EYE_DLY_6_0_SHIFT             0
28993     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X321_UNUSED_0                                          (0x1<<7) // reserved
28994     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X321_UNUSED_0_SHIFT                                    7
28995 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X322                                                       0x002d08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
28996     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X322_QAHB_CDFE_RATE2_MAX_EYE_DLY                       (0x7f<<0) // Maximum eye delay value for rate2 during dll calibration
28997     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X322_QAHB_CDFE_RATE2_MAX_EYE_DLY_SHIFT                 0
28998     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X322_UNUSED_0                                          (0x1<<7) // reserved
28999     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X322_UNUSED_0_SHIFT                                    7
29000 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X324                                                       0x002d10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29001     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X324_QAHB_CDFE_RATE2_TAP1_PATT_MASK                    (0x7f<<0) // cdfe tap1 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
29002     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X324_QAHB_CDFE_RATE2_TAP1_PATT_MASK_SHIFT              0
29003     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X324_UNUSED_0                                          (0x1<<7) // reserved
29004     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X324_UNUSED_0_SHIFT                                    7
29005 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X325                                                       0x002d14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29006     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X325_QAHB_CDFE_RATE2_TAP2_PATT_MASK_6_0                (0x7f<<0) // cdfe tap2 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
29007     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X325_QAHB_CDFE_RATE2_TAP2_PATT_MASK_6_0_SHIFT          0
29008     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X325_UNUSED_0                                          (0x1<<7) // reserved
29009     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X325_UNUSED_0_SHIFT                                    7
29010 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X326                                                       0x002d18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29011     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X326_QAHB_CDFE_RATE2_TAP3_PATT_MASK_6_0                (0x7f<<0) // cdfe tap3 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
29012     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X326_QAHB_CDFE_RATE2_TAP3_PATT_MASK_6_0_SHIFT          0
29013     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X326_UNUSED_0                                          (0x1<<7) // reserved
29014     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X326_UNUSED_0_SHIFT                                    7
29015 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X327                                                       0x002d1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29016     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X327_QAHB_CDFE_RATE2_TAP4_PATT_MASK_6_0                (0x7f<<0) // cdfe tap4 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
29017     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X327_QAHB_CDFE_RATE2_TAP4_PATT_MASK_6_0_SHIFT          0
29018     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X327_UNUSED_0                                          (0x1<<7) // reserved
29019     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X327_UNUSED_0_SHIFT                                    7
29020 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X328                                                       0x002d20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29021     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X328_QAHB_CDFE_RATE2_TAP5_PATT_MASK_6_0                (0x7f<<0) // cdfe tap5 training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
29022     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X328_QAHB_CDFE_RATE2_TAP5_PATT_MASK_6_0_SHIFT          0
29023     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X328_UNUSED_0                                          (0x1<<7) // reserved
29024     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X328_UNUSED_0_SHIFT                                    7
29025 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X329                                                       0x002d24UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29026     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X329_QAHB_CDFE_RATE2_DLEV_PATT_MASK_6_0                (0x7f<<0) // cdfe dlev training pattern masking bits for Gen 2 when rate is 2'b01. When a masking bit is 1, the corresponding training pattern bit is regarded as DON'T CARE.
29027     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X329_QAHB_CDFE_RATE2_DLEV_PATT_MASK_6_0_SHIFT          0
29028     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X329_UNUSED_0                                          (0x1<<7) // reserved
29029     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X329_UNUSED_0_SHIFT                                    7
29030 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X330                                                       0x002d28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29031     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X330_QAHB_CDFE_CMP1_PRESET_OFFSET_5_0                  (0x3f<<0) // cdfe comparator1 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
29032     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X330_QAHB_CDFE_CMP1_PRESET_OFFSET_5_0_SHIFT            0
29033     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X330_UNUSED_0                                          (0x3<<6) // reserved
29034     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X330_UNUSED_0_SHIFT                                    6
29035 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X331                                                       0x002d2cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29036     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X331_QAHB_CDFE_CMP2_PRESET_OFFSET_5_0                  (0x3f<<0) // cdfe comparator2 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
29037     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X331_QAHB_CDFE_CMP2_PRESET_OFFSET_5_0_SHIFT            0
29038     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X331_UNUSED_0                                          (0x3<<6) // reserved
29039     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X331_UNUSED_0_SHIFT                                    6
29040 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X332                                                       0x002d30UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29041     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X332_QAHB_CDFE_CMP3_PRESET_OFFSET_5_0                  (0x3f<<0) // cdfe comparator3 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
29042     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X332_QAHB_CDFE_CMP3_PRESET_OFFSET_5_0_SHIFT            0
29043     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X332_UNUSED_0                                          (0x3<<6) // reserved
29044     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X332_UNUSED_0_SHIFT                                    6
29045 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X333                                                       0x002d34UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29046     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X333_QAHB_CDFE_CMP4_PRESET_OFFSET_5_0                  (0x3f<<0) // cdfe comparator4 offset values ovrride enable bit[0] : enables overriding main cmp offset bit[1] : enables overriding tap1 offset bit[2] : enables overriding tap2 offset bit[3] : enables overriding tap3 offset bit[4] : enables overriding tap4 offset bit[5] : enables overriding tap5 offset
29047     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X333_QAHB_CDFE_CMP4_PRESET_OFFSET_5_0_SHIFT            0
29048     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X333_UNUSED_0                                          (0x3<<6) // reserved
29049     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X333_UNUSED_0_SHIFT                                    6
29050 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X338                                                       0x002d48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29051     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X338_QAHB_CDFE_COARSE_DLL_ERR_AVG_NUM_6_0              (0x7f<<0) //
29052     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X338_QAHB_CDFE_COARSE_DLL_ERR_AVG_NUM_6_0_SHIFT        0
29053     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X338_UNUSED_0                                          (0x1<<7) // reserved
29054     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X338_UNUSED_0_SHIFT                                    7
29055 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X339                                                       0x002d4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29056     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X339_QAHB_CDFE_DLEV_ERR_AVG_NUM_6_0                    (0x7f<<0) //
29057     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X339_QAHB_CDFE_DLEV_ERR_AVG_NUM_6_0_SHIFT              0
29058     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X339_UNUSED_0                                          (0x1<<7) // reserved
29059     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X339_UNUSED_0_SHIFT                                    7
29060 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X341                                                       0x002d54UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29061     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X341_QAHB_CDFE_COARSE_DLL_ERR_AVG_THRESHOLD_6_0        (0x7f<<0) //
29062     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X341_QAHB_CDFE_COARSE_DLL_ERR_AVG_THRESHOLD_6_0_SHIFT  0
29063     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X341_UNUSED_0                                          (0x1<<7) // reserved
29064     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X341_UNUSED_0_SHIFT                                    7
29065 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X342                                                       0x002d58UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29066     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X342_QAHB_CDFE_DLEV_ERR_AVG_THRESHOLD                  (0x7f<<0) //
29067     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X342_QAHB_CDFE_DLEV_ERR_AVG_THRESHOLD_SHIFT            0
29068     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X342_UNUSED_0                                          (0x1<<7) // reserved
29069     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X342_UNUSED_0_SHIFT                                    7
29070 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344                                                       0x002d60UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29071     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_COARSE_AVG_1_0                      (0x3<<0) // Level of averaging used during cdfe dll coarse calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
29072     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_COARSE_AVG_1_0_SHIFT                0
29073     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_FINE_AVG                            (0x3<<2) // Level of averaging used during cdfe dll fine calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
29074     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLL_FINE_AVG_SHIFT                      2
29075     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLEV_AVG                                (0x3<<4) // Level of averaging used during cdfe dlev calibration 0: last data,  1: avg of last two data,  2: avg of last four data,  3: last data
29076     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_QAHB_CDFE_DLEV_AVG_SHIFT                          4
29077     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_UNUSED_0                                          (0x3<<6) // reserved
29078     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X344_UNUSED_0_SHIFT                                    6
29079 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346                                                       0x002d68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29080     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN                   (0x1<<0) //
29081     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_FINE_OV_COARSE_EN_SHIFT             0
29082     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN                   (0x1<<1) //
29083     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_QAHB_CDFE_DLL_COARSE_OV_FINE_EN_SHIFT             1
29084     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_UNUSED_0                                          (0x3f<<2) // reserved
29085     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X346_UNUSED_0_SHIFT                                    2
29086 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X347                                                       0x002d6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29087     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X347_QAHB_CDFE_DLEV_TRAINING_PATT                      (0x7f<<0) // cdfe dlev training pattern.
29088     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X347_QAHB_CDFE_DLEV_TRAINING_PATT_SHIFT                0
29089     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X347_UNUSED_0                                          (0x1<<7) // reserved
29090     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X347_UNUSED_0_SHIFT                                    7
29091 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X348                                                       0x002d70UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29092     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X348_QAHB_CDFE_TAP1_TRAINING_PATT_6_0                  (0x7f<<0) // cdfe tap1 training pattern.
29093     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X348_QAHB_CDFE_TAP1_TRAINING_PATT_6_0_SHIFT            0
29094     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X348_UNUSED_0                                          (0x1<<7) // reserved
29095     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X348_UNUSED_0_SHIFT                                    7
29096 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X349                                                       0x002d74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29097     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X349_QAHB_CDFE_TAP2_TRAINING_PATT_6_0                  (0x7f<<0) // cdfe tap2 training pattern.
29098     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X349_QAHB_CDFE_TAP2_TRAINING_PATT_6_0_SHIFT            0
29099     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X349_UNUSED_0                                          (0x1<<7) // reserved
29100     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X349_UNUSED_0_SHIFT                                    7
29101 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X350                                                       0x002d78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29102     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X350_QAHB_CDFE_TAP3_TRAINING_PATT_6_0                  (0x7f<<0) // cdfe tap3 training pattern.
29103     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X350_QAHB_CDFE_TAP3_TRAINING_PATT_6_0_SHIFT            0
29104     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X350_UNUSED_0                                          (0x1<<7) // reserved
29105     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X350_UNUSED_0_SHIFT                                    7
29106 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X351                                                       0x002d7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29107     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X351_QAHB_CDFE_TAP4_TRAINING_PATT_6_0                  (0x7f<<0) // cdfe tap4 training pattern.
29108     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X351_QAHB_CDFE_TAP4_TRAINING_PATT_6_0_SHIFT            0
29109     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X351_UNUSED_0                                          (0x1<<7) // reserved
29110     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X351_UNUSED_0_SHIFT                                    7
29111 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X352                                                       0x002d80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29112     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X352_QAHB_CDFE_TAP5_TRAINING_PATT_6_0                  (0x7f<<0) // cdfe tap5 training pattern.
29113     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X352_QAHB_CDFE_TAP5_TRAINING_PATT_6_0_SHIFT            0
29114     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X352_UNUSED_0                                          (0x1<<7) // reserved
29115     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X352_UNUSED_0_SHIFT                                    7
29116 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X353                                                       0x002d84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29117     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X353_QAHB_CDFE_DLL_COARSE_BOUNCE                       (0xf<<0) // Bounce number for cdfe dll coarse calibration
29118     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X353_QAHB_CDFE_DLL_COARSE_BOUNCE_SHIFT                 0
29119     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X353_UNUSED_0                                          (0xf<<4) // reserved
29120     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X353_UNUSED_0_SHIFT                                    4
29121 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X354                                                       0x002d88UL //Access:RW   DataWidth:0x8   Bounce number for cdfe dll fine calibration  Chips: K2
29122 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X355                                                       0x002d8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29123     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X355_QAHB_CDFE_DLEV_BOUNCE                             (0xf<<0) // Bounce number for cdfe dlev calibration
29124     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X355_QAHB_CDFE_DLEV_BOUNCE_SHIFT                       0
29125     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X355_UNUSED_0                                          (0xf<<4) // reserved
29126     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X355_UNUSED_0_SHIFT                                    4
29127 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358                                                       0x002d98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29128     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLL_COARSE_STEP                         (0xf<<0) // Calibration step size for cdfe dll coarse calibration
29129     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLL_COARSE_STEP_SHIFT                   0
29130     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLEV_STEP_3_0                           (0xf<<4) // Calibration step size for cdfe dlev calibration
29131     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X358_QAHB_CDFE_DLEV_STEP_3_0_SHIFT                     4
29132 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X362                                                       0x002da8UL //Access:RW   DataWidth:0x8   Maximum dlev value for cdfe  Chips: K2
29133 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X363                                                       0x002dacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29134     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X363_QAHB_CDFE_TAP1_MAX_6_0                            (0x7f<<0) // Maximum tap1 value for cdfe
29135     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X363_QAHB_CDFE_TAP1_MAX_6_0_SHIFT                      0
29136     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X363_UNUSED_0                                          (0x1<<7) // reserved
29137     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X363_UNUSED_0_SHIFT                                    7
29138 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X364                                                       0x002db0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29139     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X364_QAHB_CDFE_TAP2_MAX                                (0x3f<<0) // Maximum tap2 value for cdfe
29140     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X364_QAHB_CDFE_TAP2_MAX_SHIFT                          0
29141     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X364_UNUSED_0                                          (0x3<<6) // reserved
29142     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X364_UNUSED_0_SHIFT                                    6
29143 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X365                                                       0x002db4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29144     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X365_QAHB_CDFE_TAP3_MAX_5_0                            (0x3f<<0) // Maximum tap3 value for cdfe
29145     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X365_QAHB_CDFE_TAP3_MAX_5_0_SHIFT                      0
29146     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X365_UNUSED_0                                          (0x3<<6) // reserved
29147     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X365_UNUSED_0_SHIFT                                    6
29148 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X366                                                       0x002db8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29149     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X366_QAHB_CDFE_TAP4_MAX_5_0                            (0x3f<<0) // Maximum tap4 value for cdfe
29150     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X366_QAHB_CDFE_TAP4_MAX_5_0_SHIFT                      0
29151     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X366_UNUSED_0                                          (0x3<<6) // reserved
29152     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X366_UNUSED_0_SHIFT                                    6
29153 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367                                                       0x002dbcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29154     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_TAP5_MAX_5_0                            (0x3f<<0) // Maximum tap5 value for cdfe
29155     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_TAP5_MAX_5_0_SHIFT                      0
29156     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN                           (0x1<<6) //
29157     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_QAHB_CDFE_CLR_BOUNCE_EN_SHIFT                     6
29158     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_UNUSED_0                                          (0x1<<7) // reserved
29159     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X367_UNUSED_0_SHIFT                                    7
29160 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368                                                       0x002dc0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29161     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE2_DFE_CMP_DATA_WAIT                 (0xf<<0) //
29162     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE2_DFE_CMP_DATA_WAIT_SHIFT           0
29163     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE3_DFE_CMP_DATA_WAIT                 (0xf<<4) //
29164     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X368_QAHB_CDFE_RATE3_DFE_CMP_DATA_WAIT_SHIFT           4
29165 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369                                                       0x002dc4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29166     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_UNUSED_0                                          (0x1<<0) // reserved
29167     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_UNUSED_0_SHIFT                                    0
29168     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O                         (0x3f<<1) // Mask bits for CM1 training pattern
29169     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_TAP1_CM1_DONT_CARE_O_SHIFT                   1
29170     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O              (0x1<<7) //
29171     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X369_QAHB_CDFE_SELECT_CLK90_CLK270_ONLY_O_SHIFT        7
29172 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X370                                                       0x002dc8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29173     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X370_QAHB_TAP1_C1_DONT_CARE_O                          (0x3f<<0) // Mask bits for C1 training pattern
29174     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X370_QAHB_TAP1_C1_DONT_CARE_O_SHIFT                    0
29175     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X370_UNUSED_0                                          (0x3<<6) // reserved
29176     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X370_UNUSED_0_SHIFT                                    6
29177 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371                                                       0x002dccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29178     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_CMP_SEL_ENA_O                           (0xf<<0) //
29179     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_CMP_SEL_ENA_O_SHIFT                     0
29180     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_DFE_STROBE_CNT_O                        (0x7<<4) //
29181     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_QAHB_CDFE_DFE_STROBE_CNT_O_SHIFT                  4
29182     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_UNUSED_0                                          (0x1<<7) // reserved
29183     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X371_UNUSED_0_SHIFT                                    7
29184 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372                                                       0x002dd0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29185     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_WAIT_TIMER_1_O                          (0x7<<0) //
29186     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_WAIT_TIMER_1_O_SHIFT                    0
29187     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O                    (0x1<<3) //
29188     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_QAHB_CDFE_FINAL_CMP_WRITE_EN_O_SHIFT              3
29189     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_UNUSED_0                                          (0xf<<4) // reserved
29190     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X372_UNUSED_0_SHIFT                                    4
29191 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X373                                                       0x002dd4UL //Access:RW   DataWidth:0x8     Chips: K2
29192 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376                                                       0x002de0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29193     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29194     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_IDDQ_SD_O_SHIFT                      0
29195     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O                             (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29196     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_O_SHIFT                       1
29197     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O                        (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29198     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_DFE_BIAS_O_SHIFT                  2
29199     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29200     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREG_O_SHIFT                     3
29201     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29202     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_LNREGH_O_SHIFT                    4
29203     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O                             (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29204     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_P2S_O_SHIFT                       5
29205     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O                              (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29206     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_RA_O_SHIFT                        6
29207     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29208     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X376_MSM_PIPE_RST_PD_S2P_O_SHIFT                       7
29209 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377                                                       0x002de4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29210     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29211     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_SLV_BIAS_O_SHIFT                  0
29212     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29213     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXDRV_O_SHIFT                     1
29214     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29215     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_TXREG_O_SHIFT                     2
29216     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O                             (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29217     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_O_SHIFT                       3
29218     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O                         (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29219     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_PD_VCO_BUF_O_SHIFT                   4
29220     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29221     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_O_SHIFT                    5
29222     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O                     (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29223     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_CDR_GCRX_O_SHIFT               6
29224     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O                          (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29225     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X377_MSM_PIPE_RST_RESET_DFE_O_SHIFT                    7
29226 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378                                                       0x002de8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29227     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O                        (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29228     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREG_O_SHIFT                  0
29229     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29230     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_LNREGH_O_SHIFT                 1
29231     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29232     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_P2S_O_SHIFT                    2
29233     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O                           (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29234     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_RA_O_SHIFT                     3
29235     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29236     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_S2P_O_SHIFT                    4
29237     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29238     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_RESET_VCO_O_SHIFT                    5
29239     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O                    (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29240     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TXREG_BLEED_ENA_O_SHIFT              6
29241     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O                 (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29242     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X378_MSM_PIPE_RST_TX_LOWPWR_IDLE_ENA_O_SHIFT           7
29243 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379                                                       0x002decUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29244     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29245     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_CDR_EN_O_SHIFT                       0
29246     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O                          (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29247     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RXBCLK_EN_O_SHIFT                    1
29248     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29249     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RX_GATE_EN_O_SHIFT                   2
29250     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O                    (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29251     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_MSM_PIPE_RST_RESET_TX_CLKDIV_O_SHIFT              3
29252     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_UNUSED_0                                          (0xf<<4) // reserved
29253     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X379_UNUSED_0_SHIFT                                    4
29254 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380                                                       0x002df0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29255     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29256     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_IDDQ_SD_O_SHIFT                       0
29257     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O                              (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29258     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_O_SHIFT                        1
29259     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29260     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_DFE_BIAS_O_SHIFT                   2
29261     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29262     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREG_O_SHIFT                      3
29263     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29264     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_LNREGH_O_SHIFT                     4
29265     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29266     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_P2S_O_SHIFT                        5
29267     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O                               (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29268     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_RA_O_SHIFT                         6
29269     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O                              (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29270     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X380_MSM_PIPE_P0_PD_S2P_O_SHIFT                        7
29271 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381                                                       0x002df4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29272     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29273     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_SLV_BIAS_O_SHIFT                   0
29274     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29275     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXDRV_O_SHIFT                      1
29276     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29277     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_TXREG_O_SHIFT                      2
29278     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29279     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_O_SHIFT                        3
29280     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29281     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_PD_VCO_BUF_O_SHIFT                    4
29282     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29283     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_O_SHIFT                     5
29284     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O                      (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29285     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_CDR_GCRX_O_SHIFT                6
29286     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O                           (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29287     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X381_MSM_PIPE_P0_RESET_DFE_O_SHIFT                     7
29288 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382                                                       0x002df8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29289     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29290     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREG_O_SHIFT                   0
29291     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29292     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_LNREGH_O_SHIFT                  1
29293     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29294     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_P2S_O_SHIFT                     2
29295     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29296     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_RA_O_SHIFT                      3
29297     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29298     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_S2P_O_SHIFT                     4
29299     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29300     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_RESET_VCO_O_SHIFT                     5
29301     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O                     (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29302     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TXREG_BLEED_ENA_O_SHIFT               6
29303     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O                  (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29304     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X382_MSM_PIPE_P0_TX_LOWPWR_IDLE_ENA_O_SHIFT            7
29305 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383                                                       0x002dfcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29306     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O                              (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29307     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_CDR_EN_O_SHIFT                        0
29308     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29309     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RXBCLK_EN_O_SHIFT                     1
29310     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29311     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RX_GATE_EN_O_SHIFT                    2
29312     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O                     (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29313     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_MSM_PIPE_P0_RESET_TX_CLKDIV_O_SHIFT               3
29314     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_UNUSED_0                                          (0xf<<4) // reserved
29315     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X383_UNUSED_0_SHIFT                                    4
29316 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384                                                       0x002e00UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29317     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29318     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_IDDQ_SD_O_SHIFT                       0
29319     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O                              (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29320     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_O_SHIFT                        1
29321     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29322     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_DFE_BIAS_O_SHIFT                   2
29323     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29324     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREG_O_SHIFT                      3
29325     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29326     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_LNREGH_O_SHIFT                     4
29327     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29328     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_P2S_O_SHIFT                        5
29329     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O                               (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29330     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_RA_O_SHIFT                         6
29331     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O                              (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29332     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X384_MSM_PIPE_P1_PD_S2P_O_SHIFT                        7
29333 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385                                                       0x002e04UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29334     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29335     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_SLV_BIAS_O_SHIFT                   0
29336     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29337     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXDRV_O_SHIFT                      1
29338     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29339     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_TXREG_O_SHIFT                      2
29340     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29341     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_O_SHIFT                        3
29342     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29343     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_PD_VCO_BUF_O_SHIFT                    4
29344     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29345     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_O_SHIFT                     5
29346     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O                      (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29347     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_CDR_GCRX_O_SHIFT                6
29348     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O                           (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29349     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X385_MSM_PIPE_P1_RESET_DFE_O_SHIFT                     7
29350 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386                                                       0x002e08UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29351     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29352     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREG_O_SHIFT                   0
29353     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29354     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_LNREGH_O_SHIFT                  1
29355     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29356     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_P2S_O_SHIFT                     2
29357     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29358     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_RA_O_SHIFT                      3
29359     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29360     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_S2P_O_SHIFT                     4
29361     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29362     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_RESET_VCO_O_SHIFT                     5
29363     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O                     (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29364     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TXREG_BLEED_ENA_O_SHIFT               6
29365     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O                  (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29366     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X386_MSM_PIPE_P1_TX_LOWPWR_IDLE_ENA_O_SHIFT            7
29367 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387                                                       0x002e0cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29368     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O                              (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29369     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_CDR_EN_O_SHIFT                        0
29370     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29371     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RXBCLK_EN_O_SHIFT                     1
29372     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29373     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RX_GATE_EN_O_SHIFT                    2
29374     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O                     (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29375     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_MSM_PIPE_P1_RESET_TX_CLKDIV_O_SHIFT               3
29376     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_UNUSED_0                                          (0xf<<4) // reserved
29377     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X387_UNUSED_0_SHIFT                                    4
29378 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388                                                       0x002e10UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29379     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29380     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_IDDQ_SD_O_SHIFT                       0
29381     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O                              (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29382     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_O_SHIFT                        1
29383     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29384     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_DFE_BIAS_O_SHIFT                   2
29385     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29386     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREG_O_SHIFT                      3
29387     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29388     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_LNREGH_O_SHIFT                     4
29389     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O                              (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29390     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_P2S_O_SHIFT                        5
29391     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O                               (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29392     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_RA_O_SHIFT                         6
29393     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O                              (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29394     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X388_MSM_PIPE_P2_PD_S2P_O_SHIFT                        7
29395 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389                                                       0x002e14UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29396     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29397     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_SLV_BIAS_O_SHIFT                   0
29398     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29399     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXDRV_O_SHIFT                      1
29400     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O                            (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29401     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_TXREG_O_SHIFT                      2
29402     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O                              (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29403     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_O_SHIFT                        3
29404     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O                          (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29405     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_PD_VCO_BUF_O_SHIFT                    4
29406     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29407     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_O_SHIFT                     5
29408     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O                      (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29409     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_CDR_GCRX_O_SHIFT                6
29410     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O                           (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29411     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X389_MSM_PIPE_P2_RESET_DFE_O_SHIFT                     7
29412 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390                                                       0x002e18UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29413     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29414     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREG_O_SHIFT                   0
29415     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29416     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_LNREGH_O_SHIFT                  1
29417     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O                           (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29418     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_P2S_O_SHIFT                     2
29419     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29420     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_RA_O_SHIFT                      3
29421     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O                           (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29422     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_S2P_O_SHIFT                     4
29423     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29424     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_RESET_VCO_O_SHIFT                     5
29425     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O                     (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29426     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TXREG_BLEED_ENA_O_SHIFT               6
29427     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O                  (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29428     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X390_MSM_PIPE_P2_TX_LOWPWR_IDLE_ENA_O_SHIFT            7
29429 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391                                                       0x002e1cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29430     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O                              (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29431     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_CDR_EN_O_SHIFT                        0
29432     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O                           (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29433     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RXBCLK_EN_O_SHIFT                     1
29434     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29435     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RX_GATE_EN_O_SHIFT                    2
29436     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O                     (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29437     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_MSM_PIPE_P2_RESET_TX_CLKDIV_O_SHIFT               3
29438     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_UNUSED_0                                          (0xf<<4) // reserved
29439     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X391_UNUSED_0_SHIFT                                    4
29440 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X392                                                       0x002e20UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29441     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X392_MSM_PROG_MULT_DELAY_IDDQ_RESET_1_4_0              (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29442     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X392_MSM_PROG_MULT_DELAY_IDDQ_RESET_1_4_0_SHIFT        0
29443     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X392_UNUSED_0                                          (0x7<<5) // reserved
29444     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X392_UNUSED_0_SHIFT                                    5
29445 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X394                                                       0x002e28UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29446     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X394_MSM_PROG_MULT_DELAY_IDDQ_RESET_2_4_0              (0x1f<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1 state in PIPE mode
29447     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X394_MSM_PROG_MULT_DELAY_IDDQ_RESET_2_4_0_SHIFT        0
29448     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X394_UNUSED_0                                          (0x7<<5) // reserved
29449     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X394_UNUSED_0_SHIFT                                    5
29450 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401                                                       0x002e44UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29451     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O                                   (0x1<<0) // Lane0 master reset
29452     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L0_MASTER_CDN_O_SHIFT                             0
29453     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O                                   (0x1<<1) // Lane1 master reset
29454     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L1_MASTER_CDN_O_SHIFT                             1
29455     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O                                   (0x1<<2) // Lane2 master reset
29456     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L2_MASTER_CDN_O_SHIFT                             2
29457     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O                                   (0x1<<3) // Lane3 master reset
29458     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_L3_MASTER_CDN_O_SHIFT                             3
29459     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_UNUSED_0                                          (0xf<<4) // reserved
29460     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X401_UNUSED_0_SHIFT                                    4
29461 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402                                                       0x002e48UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29462     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O                                        (0x1<<0) // fast_sim_register
29463     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402_FAST_SIM_O_SHIFT                                  0
29464     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402_UNUSED_0                                          (0x7f<<1) // reserved
29465     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X402_UNUSED_0_SHIFT                                    1
29466 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403                                                       0x002e4cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29467     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TBUS_DFE_CMP_SEL_O_2_0                            (0x7<<0) // Selects which comparator offsets come out on tbus
29468     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TBUS_DFE_CMP_SEL_O_2_0_SHIFT                      0
29469     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TXDP_IDLE_IN_DELAY                                (0x3<<3) // Controls the number of clk cycles delay from data_en of p2s_rbuf to propagate to the idle_in of txdp_control_dig 0 is 2 cycles celay, 3 is 5 cycles delay
29470     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_TXDP_IDLE_IN_DELAY_SHIFT                          3
29471     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_UNUSED_0                                          (0x7<<5) // reserved
29472     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X403_UNUSED_0_SHIFT                                    5
29473 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X404                                                       0x002e50UL //Access:RW   DataWidth:0x8     Chips: K2
29474 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X405                                                       0x002e54UL //Access:RW   DataWidth:0x8     Chips: K2
29475 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406                                                       0x002e58UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
29476     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_MODE_I_2_0                                        (0x7<<0) // 1000Base-KX Mode status for CPU
29477     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_MODE_I_2_0_SHIFT                                  0
29478     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0                                        (0x1<<3) // CMU OK Status
29479     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU_OK_I_0_SHIFT                                  3
29480     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1                                       (0x1<<4) // CMU1 OK Status
29481     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_CMU1_OK_I_1_SHIFT                                 4
29482     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_UNUSED_0                                          (0x7<<5) // reserved
29483     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X406_UNUSED_0_SHIFT                                    5
29484 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407                                                       0x002e5cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
29485     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0                           (0x1<<0) // Lane 0 Signal Detect Valid Status
29486     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_SIG_LEVEL_VALID_I_0_SHIFT                     0
29487     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1                           (0x1<<1) // Lane 1 Signal Detect Valid Status
29488     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_SIG_LEVEL_VALID_I_1_SHIFT                     1
29489     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2                           (0x1<<2) // Lane 2 Signal Detect Valid Status
29490     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_SIG_LEVEL_VALID_I_2_SHIFT                     2
29491     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3                           (0x1<<3) // Lane 3 Signal Detect Valid Status
29492     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_SIG_LEVEL_VALID_I_3_SHIFT                     3
29493     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4                                        (0x1<<4) // Lane 0 OK Status
29494     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN0_OK_I_4_SHIFT                                  4
29495     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5                                        (0x1<<5) // Lane 1 OK Status
29496     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN1_OK_I_5_SHIFT                                  5
29497     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6                                        (0x1<<6) // Lane 2 OK Status
29498     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN2_OK_I_6_SHIFT                                  6
29499     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7                                        (0x1<<7) // Lane 3 OK Status
29500     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X407_LN3_OK_I_7_SHIFT                                  7
29501 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408                                                       0x002e60UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
29502     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN0_RX_LOCKED_I_1_0                               (0x3<<0) // Lane 0 RX Locked status
29503     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN0_RX_LOCKED_I_1_0_SHIFT                         0
29504     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN1_RX_LOCKED_I_3_2                               (0x3<<2) // Lane 1 RX Locked Status
29505     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN1_RX_LOCKED_I_3_2_SHIFT                         2
29506     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN2_RX_LOCKED_I_5_4                               (0x3<<4) // Lane 2 RX Locked Status
29507     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN2_RX_LOCKED_I_5_4_SHIFT                         4
29508     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN3_RX_LOCKED_I_7_6                               (0x3<<6) // Lane 3 RX Locked Status
29509     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X408_LN3_RX_LOCKED_I_7_6_SHIFT                         6
29510 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409                                                       0x002e64UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29511     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409_EI_GLUE_EN_O                                      (0x1<<0) // Unused
29512     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409_EI_GLUE_EN_O_SHIFT                                0
29513     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409_UNUSED_0                                          (0x7f<<1) // reserved
29514     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X409_UNUSED_0_SHIFT                                    1
29515 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410                                                       0x002e68UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29516     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_GEN12_ONLY_O                                      (0x1<<0) // Newly added for PCIe3 1CMU
29517     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_GEN12_ONLY_O_SHIFT                                0
29518     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RESETN_RESET_CMU_EN_O                        (0x1<<1) // Newly added for PCIe3 1CMU
29519     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RESETN_RESET_CMU_EN_O_SHIFT                  1
29520     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_EN_O                           (0x1<<2) // Newly added for PCIe3 1CMU
29521     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_EN_O_SHIFT                     2
29522     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_O                              (0x1<<3) // Newly added for PCIe3 1CMU
29523     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_CHNG_OVR_O_SHIFT                        3
29524     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_EN_O                       (0x1<<4) // Newly added for PCIe3 1CMU
29525     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_EN_O_SHIFT                 4
29526     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_O                          (0x1<<5) // Newly added for PCIe3 1CMU
29527     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_GEN3_CAL_DONE_OVR_O_SHIFT                    5
29528     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_EN_O                        (0x1<<6) // Newly added for PCIe3 1CMU
29529     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_EN_O_SHIFT                  6
29530     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_O                           (0x1<<7) // Newly added for PCIe3 1CMU
29531     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X410_LANE_RATE_IS_GEN3_OVR_O_SHIFT                     7
29532 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411                                                       0x002e6cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29533     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_EN_O_3_0                                     (0xf<<0) // Newly added for PCIe3 1CMU
29534     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_EN_O_3_0_SHIFT                               0
29535     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_EN_O                              (0x1<<4) // Newly added for PCIe3 1CMU
29536     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_EN_O_SHIFT                        4
29537     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_O                                 (0x1<<5) // Newly added for PCIe3 1CMU
29538     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_LANE_RESETN_OVR_O_SHIFT                           5
29539     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_UNUSED_0                                          (0x3<<6) // reserved
29540     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X411_UNUSED_0_SHIFT                                    6
29541 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X413                                                       0x002e74UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29542     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X413_TXPRESET_COEFF_P0C_O                              (0x3f<<0) // txpreset_coeff P0 C
29543     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X413_TXPRESET_COEFF_P0C_O_SHIFT                        0
29544     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X413_UNUSED_0                                          (0x3<<6) // reserved
29545     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X413_UNUSED_0_SHIFT                                    6
29546 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X414                                                       0x002e78UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29547     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X414_TXPRESET_COEFF_P0CM1_O                            (0x3f<<0) // txpreset_coeff P0 C-1
29548     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X414_TXPRESET_COEFF_P0CM1_O_SHIFT                      0
29549     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X414_UNUSED_0                                          (0x3<<6) // reserved
29550     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X414_UNUSED_0_SHIFT                                    6
29551 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X415                                                       0x002e7cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29552     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X415_TXPRESET_COEFF_P0CP1_O                            (0x3f<<0) // txpreset_coeff P0 C+1
29553     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X415_TXPRESET_COEFF_P0CP1_O_SHIFT                      0
29554     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X415_UNUSED_0                                          (0x3<<6) // reserved
29555     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X415_UNUSED_0_SHIFT                                    6
29556 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X416                                                       0x002e80UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29557     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X416_TXPRESET_COEFF_P1C_O                              (0x3f<<0) // txpreset_coeff P1 C
29558     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X416_TXPRESET_COEFF_P1C_O_SHIFT                        0
29559     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X416_UNUSED_0                                          (0x3<<6) // reserved
29560     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X416_UNUSED_0_SHIFT                                    6
29561 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X417                                                       0x002e84UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29562     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X417_TXPRESET_COEFF_P1CM1_O                            (0x3f<<0) // txpreset_coeff P1 C-1
29563     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X417_TXPRESET_COEFF_P1CM1_O_SHIFT                      0
29564     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X417_UNUSED_0                                          (0x3<<6) // reserved
29565     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X417_UNUSED_0_SHIFT                                    6
29566 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X418                                                       0x002e88UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29567     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X418_TXPRESET_COEFF_P1CP1_O                            (0x3f<<0) // txpreset_coeff P1 C+1
29568     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X418_TXPRESET_COEFF_P1CP1_O_SHIFT                      0
29569     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X418_UNUSED_0                                          (0x3<<6) // reserved
29570     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X418_UNUSED_0_SHIFT                                    6
29571 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X419                                                       0x002e8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29572     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X419_TXPRESET_COEFF_P2C_O                              (0x3f<<0) // txpreset_coeff P2 C
29573     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X419_TXPRESET_COEFF_P2C_O_SHIFT                        0
29574     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X419_UNUSED_0                                          (0x3<<6) // reserved
29575     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X419_UNUSED_0_SHIFT                                    6
29576 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X420                                                       0x002e90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29577     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X420_TXPRESET_COEFF_P2CM1_O                            (0x3f<<0) // txpreset_coeff P2 C-1
29578     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X420_TXPRESET_COEFF_P2CM1_O_SHIFT                      0
29579     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X420_UNUSED_0                                          (0x3<<6) // reserved
29580     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X420_UNUSED_0_SHIFT                                    6
29581 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X421                                                       0x002e94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29582     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X421_TXPRESET_COEFF_P2CP1_O                            (0x3f<<0) // txpreset_coeff P2 C+1
29583     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X421_TXPRESET_COEFF_P2CP1_O_SHIFT                      0
29584     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X421_UNUSED_0                                          (0x3<<6) // reserved
29585     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X421_UNUSED_0_SHIFT                                    6
29586 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X422                                                       0x002e98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29587     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X422_TXPRESET_COEFF_P3C_O                              (0x3f<<0) // txpreset_coeff P3 C
29588     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X422_TXPRESET_COEFF_P3C_O_SHIFT                        0
29589     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X422_UNUSED_0                                          (0x3<<6) // reserved
29590     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X422_UNUSED_0_SHIFT                                    6
29591 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X423                                                       0x002e9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29592     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X423_TXPRESET_COEFF_P3CM1_O                            (0x3f<<0) // txpreset_coeff P3 C-1
29593     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X423_TXPRESET_COEFF_P3CM1_O_SHIFT                      0
29594     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X423_UNUSED_0                                          (0x3<<6) // reserved
29595     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X423_UNUSED_0_SHIFT                                    6
29596 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X424                                                       0x002ea0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29597     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X424_TXPRESET_COEFF_P3CP1_O                            (0x3f<<0) // txpreset_coeff P3 C+1
29598     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X424_TXPRESET_COEFF_P3CP1_O_SHIFT                      0
29599     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X424_UNUSED_0                                          (0x3<<6) // reserved
29600     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X424_UNUSED_0_SHIFT                                    6
29601 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X425                                                       0x002ea4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29602     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X425_TXPRESET_COEFF_P4C_O                              (0x3f<<0) // txpreset_coeff P4 C
29603     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X425_TXPRESET_COEFF_P4C_O_SHIFT                        0
29604     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X425_UNUSED_0                                          (0x3<<6) // reserved
29605     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X425_UNUSED_0_SHIFT                                    6
29606 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X426                                                       0x002ea8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29607     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X426_TXPRESET_COEFF_P4CM1_O                            (0x3f<<0) // txpreset_coeff P4 C-1
29608     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X426_TXPRESET_COEFF_P4CM1_O_SHIFT                      0
29609     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X426_UNUSED_0                                          (0x3<<6) // reserved
29610     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X426_UNUSED_0_SHIFT                                    6
29611 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X427                                                       0x002eacUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29612     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X427_TXPRESET_COEFF_P4CP1_O                            (0x3f<<0) // txpreset_coeff P4 C+1
29613     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X427_TXPRESET_COEFF_P4CP1_O_SHIFT                      0
29614     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X427_UNUSED_0                                          (0x3<<6) // reserved
29615     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X427_UNUSED_0_SHIFT                                    6
29616 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X428                                                       0x002eb0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29617     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X428_TXPRESET_COEFF_P5C_O                              (0x3f<<0) // txpreset_coeff P5 C
29618     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X428_TXPRESET_COEFF_P5C_O_SHIFT                        0
29619     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X428_UNUSED_0                                          (0x3<<6) // reserved
29620     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X428_UNUSED_0_SHIFT                                    6
29621 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X429                                                       0x002eb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29622     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X429_TXPRESET_COEFF_P5CM1_O                            (0x3f<<0) // txpreset_coeff P5 C-1
29623     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X429_TXPRESET_COEFF_P5CM1_O_SHIFT                      0
29624     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X429_UNUSED_0                                          (0x3<<6) // reserved
29625     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X429_UNUSED_0_SHIFT                                    6
29626 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X430                                                       0x002eb8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29627     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X430_TXPRESET_COEFF_P5CP1_O                            (0x3f<<0) // txpreset_coeff P5 C+1
29628     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X430_TXPRESET_COEFF_P5CP1_O_SHIFT                      0
29629     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X430_UNUSED_0                                          (0x3<<6) // reserved
29630     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X430_UNUSED_0_SHIFT                                    6
29631 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X431                                                       0x002ebcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29632     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X431_TXPRESET_COEFF_P6C_O                              (0x3f<<0) // txpreset_coeff P6 C
29633     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X431_TXPRESET_COEFF_P6C_O_SHIFT                        0
29634     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X431_UNUSED_0                                          (0x3<<6) // reserved
29635     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X431_UNUSED_0_SHIFT                                    6
29636 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X432                                                       0x002ec0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29637     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X432_TXPRESET_COEFF_P6CM1_O                            (0x3f<<0) // txpreset_coeff P6 C-1
29638     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X432_TXPRESET_COEFF_P6CM1_O_SHIFT                      0
29639     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X432_UNUSED_0                                          (0x3<<6) // reserved
29640     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X432_UNUSED_0_SHIFT                                    6
29641 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X433                                                       0x002ec4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29642     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X433_TXPRESET_COEFF_P6CP1_O                            (0x3f<<0) // txpreset_coeff P6 C+1
29643     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X433_TXPRESET_COEFF_P6CP1_O_SHIFT                      0
29644     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X433_UNUSED_0                                          (0x3<<6) // reserved
29645     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X433_UNUSED_0_SHIFT                                    6
29646 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X434                                                       0x002ec8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29647     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X434_TXPRESET_COEFF_P7C_O                              (0x3f<<0) // txpreset_coeff P7 C
29648     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X434_TXPRESET_COEFF_P7C_O_SHIFT                        0
29649     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X434_UNUSED_0                                          (0x3<<6) // reserved
29650     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X434_UNUSED_0_SHIFT                                    6
29651 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X435                                                       0x002eccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29652     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X435_TXPRESET_COEFF_P7CM1_O                            (0x3f<<0) // txpreset_coeff P7 C-1
29653     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X435_TXPRESET_COEFF_P7CM1_O_SHIFT                      0
29654     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X435_UNUSED_0                                          (0x3<<6) // reserved
29655     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X435_UNUSED_0_SHIFT                                    6
29656 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X436                                                       0x002ed0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29657     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X436_TXPRESET_COEFF_P7CP1_O                            (0x3f<<0) // txpreset_coeff P7 C+1
29658     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X436_TXPRESET_COEFF_P7CP1_O_SHIFT                      0
29659     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X436_UNUSED_0                                          (0x3<<6) // reserved
29660     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X436_UNUSED_0_SHIFT                                    6
29661 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X437                                                       0x002ed4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29662     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X437_TXPRESET_COEFF_P8C_O                              (0x3f<<0) // txpreset_coeff P8 C
29663     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X437_TXPRESET_COEFF_P8C_O_SHIFT                        0
29664     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X437_UNUSED_0                                          (0x3<<6) // reserved
29665     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X437_UNUSED_0_SHIFT                                    6
29666 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X438                                                       0x002ed8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29667     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X438_TXPRESET_COEFF_P8CM1_O                            (0x3f<<0) // txpreset_coeff P8 C-1
29668     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X438_TXPRESET_COEFF_P8CM1_O_SHIFT                      0
29669     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X438_UNUSED_0                                          (0x3<<6) // reserved
29670     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X438_UNUSED_0_SHIFT                                    6
29671 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X439                                                       0x002edcUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29672     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X439_TXPRESET_COEFF_P8CP1_O                            (0x3f<<0) // txpreset_coeff P8 C+1
29673     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X439_TXPRESET_COEFF_P8CP1_O_SHIFT                      0
29674     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X439_UNUSED_0                                          (0x3<<6) // reserved
29675     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X439_UNUSED_0_SHIFT                                    6
29676 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X440                                                       0x002ee0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29677     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X440_TXPRESET_COEFF_P9C_O                              (0x3f<<0) // txpreset_coeff P9 C
29678     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X440_TXPRESET_COEFF_P9C_O_SHIFT                        0
29679     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X440_UNUSED_0                                          (0x3<<6) // reserved
29680     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X440_UNUSED_0_SHIFT                                    6
29681 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X441                                                       0x002ee4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29682     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X441_TXPRESET_COEFF_P9CM1_O                            (0x3f<<0) // txpreset_coeff P9 C-1
29683     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X441_TXPRESET_COEFF_P9CM1_O_SHIFT                      0
29684     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X441_UNUSED_0                                          (0x3<<6) // reserved
29685     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X441_UNUSED_0_SHIFT                                    6
29686 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X442                                                       0x002ee8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29687     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X442_TXPRESET_COEFF_P9CP1_O                            (0x3f<<0) // txpreset_coeff P9 C+1
29688     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X442_TXPRESET_COEFF_P9CP1_O_SHIFT                      0
29689     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X442_UNUSED_0                                          (0x3<<6) // reserved
29690     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X442_UNUSED_0_SHIFT                                    6
29691 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X443                                                       0x002eecUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29692     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X443_TXPRESET_COEFF_P10C_O                             (0x3f<<0) // txpreset_coeff P10 C
29693     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X443_TXPRESET_COEFF_P10C_O_SHIFT                       0
29694     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X443_UNUSED_0                                          (0x3<<6) // reserved
29695     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X443_UNUSED_0_SHIFT                                    6
29696 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X444                                                       0x002ef0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29697     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X444_TXPRESET_COEFF_P10CM1_O                           (0x3f<<0) // txpreset_coeff P10 C-1
29698     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X444_TXPRESET_COEFF_P10CM1_O_SHIFT                     0
29699     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X444_UNUSED_0                                          (0x3<<6) // reserved
29700     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X444_UNUSED_0_SHIFT                                    6
29701 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X445                                                       0x002ef4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29702     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X445_TXPRESET_COEFF_P10CP1_O                           (0x3f<<0) // txpreset_coeff P10 C+1
29703     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X445_TXPRESET_COEFF_P10CP1_O_SHIFT                     0
29704     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X445_UNUSED_0                                          (0x3<<6) // reserved
29705     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X445_UNUSED_0_SHIFT                                    6
29706 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X446                                                       0x002ef8UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29707 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X447                                                       0x002efcUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29708 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X448                                                       0x002f00UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29709 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X449                                                       0x002f04UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29710 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X450                                                       0x002f08UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29711 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X451                                                       0x002f0cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29712 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X452                                                       0x002f10UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29713 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X453                                                       0x002f14UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29714 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X454                                                       0x002f18UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29715 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X455                                                       0x002f1cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29716 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X456                                                       0x002f20UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29717 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X457                                                       0x002f24UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29718 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X458                                                       0x002f28UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29719 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X459                                                       0x002f2cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29720 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X460                                                       0x002f30UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29721 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X461                                                       0x002f34UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29722 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X462                                                       0x002f38UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29723 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X463                                                       0x002f3cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29724 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X464                                                       0x002f40UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29725 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X465                                                       0x002f44UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29726 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X466                                                       0x002f48UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29727 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X467                                                       0x002f4cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29728 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X468                                                       0x002f50UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29729 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X469                                                       0x002f54UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29730 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X470                                                       0x002f58UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29731 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X471                                                       0x002f5cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29732 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X472                                                       0x002f60UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29733 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X473                                                       0x002f64UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29734 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X474                                                       0x002f68UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29735 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X475                                                       0x002f6cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29736 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X476                                                       0x002f70UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29737 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X477                                                       0x002f74UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29738 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X478                                                       0x002f78UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29739 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X479                                                       0x002f7cUL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29740 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X480                                                       0x002f80UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29741 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X481                                                       0x002f84UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29742 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X482                                                       0x002f88UL //Access:RW   DataWidth:0x8   MSM Lane Dbank Data  Chips: K2
29743 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483                                                       0x002f8cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29744     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29745     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_LNREGH_O_SHIFT                   0
29746     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29747     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_PD_VCO_BUF_O_SHIFT                  1
29748     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O                    (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29749     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_GCRX_O_SHIFT              2
29750     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O                        (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29751     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RX_GATE_EN_O_SHIFT                  3
29752     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O                       (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29753     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_LNREG_O_SHIFT                 4
29754     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O                         (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29755     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_P2S_O_SHIFT                   5
29756     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29757     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_S2P_O_SHIFT                   6
29758     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O                         (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29759     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X483_MSM_PIPE_P1_0_RESET_CDR_O_SHIFT                   7
29760 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484                                                       0x002f90UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29761     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29762     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_DFE_O_SHIFT                   0
29763     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O                         (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29764     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_VCO_O_SHIFT                   1
29765     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29766     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_RA_O_SHIFT                    2
29767     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O                      (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29768     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_RESET_LNREGH_O_SHIFT                3
29769     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O                            (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29770     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_DFE_O_SHIFT                      4
29771     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29772     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_LNREG_O_SHIFT                    5
29773     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O                            (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29774     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_P2S_O_SHIFT                      6
29775     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29776     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X484_MSM_PIPE_P1_0_PD_RA_O_SHIFT                       7
29777 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485                                                       0x002f94UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29778     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29779     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_S2P_O_SHIFT                      0
29780     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29781     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_SLV_BIAS_O_SHIFT                 1
29782     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29783     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_TXDRV_O_SHIFT                    2
29784     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29785     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_VCO_O_SHIFT                      3
29786     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O                       (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29787     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_PD_DFE_BIAS_O_SHIFT                 4
29788     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29789     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_IDDQ_SD_O_SHIFT                     5
29790     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O                            (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29791     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_CDR_EN_O_SHIFT                      6
29792     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O                         (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29793     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X485_MSM_PIPE_P1_0_RXBCLK_EN_O_SHIFT                   7
29794 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486                                                       0x002f98UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29795     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O                (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29796     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TX_LOWPWR_IDLE_ENA_O_SHIFT          0
29797     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O                   (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29798     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_TXREG_BLEED_ENA_O_SHIFT             1
29799     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29800     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_PD_TXREG_O_SHIFT                    2
29801     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O                   (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29802     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_MSM_PIPE_P1_0_RESET_TX_CLKDIV_O_SHIFT             3
29803     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_UNUSED_0                                          (0xf<<4) // reserved
29804     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X486_UNUSED_0_SHIFT                                    4
29805 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487                                                       0x002f9cUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29806     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29807     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_LNREGH_O_SHIFT                   0
29808     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29809     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_PD_VCO_BUF_O_SHIFT                  1
29810     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O                    (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29811     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_GCRX_O_SHIFT              2
29812     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O                        (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29813     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RX_GATE_EN_O_SHIFT                  3
29814     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O                       (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29815     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_LNREG_O_SHIFT                 4
29816     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O                         (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29817     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_P2S_O_SHIFT                   5
29818     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29819     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_S2P_O_SHIFT                   6
29820     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O                         (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29821     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X487_MSM_PIPE_P1_1_RESET_CDR_O_SHIFT                   7
29822 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488                                                       0x002fa0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29823     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29824     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_DFE_O_SHIFT                   0
29825     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O                         (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29826     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_VCO_O_SHIFT                   1
29827     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29828     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_RA_O_SHIFT                    2
29829     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O                      (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29830     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_RESET_LNREGH_O_SHIFT                3
29831     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O                            (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29832     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_DFE_O_SHIFT                      4
29833     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O                          (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29834     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_LNREG_O_SHIFT                    5
29835     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O                            (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29836     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_P2S_O_SHIFT                      6
29837     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O                             (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29838     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X488_MSM_PIPE_P1_1_PD_RA_O_SHIFT                       7
29839 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489                                                       0x002fa4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29840     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O                            (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29841     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_S2P_O_SHIFT                      0
29842     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O                       (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29843     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_SLV_BIAS_O_SHIFT                 1
29844     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O                          (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29845     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_TXDRV_O_SHIFT                    2
29846     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O                            (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29847     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_VCO_O_SHIFT                      3
29848     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O                       (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29849     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_PD_DFE_BIAS_O_SHIFT                 4
29850     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O                           (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29851     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_IDDQ_SD_O_SHIFT                     5
29852     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O                            (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29853     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_CDR_EN_O_SHIFT                      6
29854     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O                   (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29855     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X489_MSM_PIPE_P1_1_RESET_TX_CLKDIV_O_SHIFT             7
29856 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490                                                       0x002fa8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29857     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29858     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_RXBCLK_EN_O_SHIFT                   0
29859     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O                (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29860     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TX_LOWPWR_IDLE_ENA_O_SHIFT          1
29861     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O                   (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29862     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_TXREG_BLEED_ENA_O_SHIFT             2
29863     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O                          (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29864     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_MSM_PIPE_P1_1_PD_TXREG_O_SHIFT                    3
29865     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_UNUSED_0                                          (0xf<<4) // reserved
29866     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X490_UNUSED_0_SHIFT                                    4
29867 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491                                                       0x002facUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29868     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29869     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_LNREGH_O_SHIFT                   0
29870     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O                        (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29871     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_PD_VCO_BUF_O_SHIFT                  1
29872     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O                    (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29873     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_CDR_GCRX_O_SHIFT              2
29874     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O                        (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29875     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RX_GATE_EN_O_SHIFT                  3
29876     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O                       (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29877     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_LNREG_O_SHIFT                 4
29878     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O                         (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29879     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_P2S_O_SHIFT                   5
29880     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O                         (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29881     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_S2P_O_SHIFT                   6
29882     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O                   (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29883     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X491_MSM_PIPE_P1_2_RESET_TX_CLKDIV_O_SHIFT             7
29884 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492                                                       0x002fb0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29885     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29886     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_CDR_O_SHIFT                   0
29887     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O                         (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29888     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_DFE_O_SHIFT                   1
29889     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O                         (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29890     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_VCO_O_SHIFT                   2
29891     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O                          (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29892     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_RA_O_SHIFT                    3
29893     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O                      (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29894     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_RESET_LNREGH_O_SHIFT                4
29895     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O                            (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29896     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_DFE_O_SHIFT                      5
29897     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O                          (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29898     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_LNREG_O_SHIFT                    6
29899     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O                            (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29900     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X492_MSM_PIPE_P1_2_PD_P2S_O_SHIFT                      7
29901 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493                                                       0x002fb4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29902     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O                             (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29903     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_RA_O_SHIFT                       0
29904     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O                            (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29905     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_S2P_O_SHIFT                      1
29906     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O                       (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29907     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_SLV_BIAS_O_SHIFT                 2
29908     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O                          (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29909     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_TXDRV_O_SHIFT                    3
29910     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O                            (0x1<<4) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29911     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_VCO_O_SHIFT                      4
29912     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O                       (0x1<<5) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29913     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_PD_DFE_BIAS_O_SHIFT                 5
29914     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O                           (0x1<<6) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29915     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_IDDQ_SD_O_SHIFT                     6
29916     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O                            (0x1<<7) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29917     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X493_MSM_PIPE_P1_2_CDR_EN_O_SHIFT                      7
29918 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494                                                       0x002fb8UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29919     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O                         (0x1<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29920     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_RXBCLK_EN_O_SHIFT                   0
29921     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O                (0x1<<1) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29922     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TX_LOWPWR_IDLE_ENA_O_SHIFT          1
29923     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O                   (0x1<<2) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29924     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_TXREG_BLEED_ENA_O_SHIFT             2
29925     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O                          (0x1<<3) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29926     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_MSM_PIPE_P1_2_PD_TXREG_O_SHIFT                    3
29927     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_UNUSED_0                                          (0xf<<4) // reserved
29928     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X494_UNUSED_0_SHIFT                                    4
29929 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X495                                                       0x002fbcUL //Access:RW   DataWidth:0x8   MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode  Chips: K2
29930 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X496                                                       0x002fc0UL //Access:RW   DataWidth:0x8   MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode  Chips: K2
29931 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X497                                                       0x002fc4UL //Access:RW   DataWidth:0x8   MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode  Chips: K2
29932 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X498                                                       0x002fc8UL //Access:RW   DataWidth:0x8   MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode  Chips: K2
29933 #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X499                                                       0x002fccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
29934     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X499_PROG_MULT_REF_CLK_WAIT_O                          (0x7<<0) // MFSM's PMA pd/reset input control signal for the PIPE P1_0 state in PIPE mode
29935     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X499_PROG_MULT_REF_CLK_WAIT_O_SHIFT                    0
29936     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X499_UNUSED_0                                          (0x1f<<3) // reserved
29937     #define PHY_PCIE_IP_REG_AHB_COMLANE_CSR_5_X499_UNUSED_0_SHIFT                                    3
29938 #define MISC_REG_RESET_CONFIG                                                                        0x008040UL //Access:RW   DataWidth:0x20  Reset configuration register. inside order of the bits is: [0] rst_pswrq_auto_mode (0- no auto deassertion; 1 - auto deassertion); [1] rst_pswrd_auto_mode (0- no auto deassertion; 1 - auto deassertion); [2] rst_pswwr_auto_mode (0- no auto deassertion; 1 - auto deassertion); [3] rst_pswhst_auto_mode (0- no auto deassertion; 1 - auto deassertion); [4] reserved; [5] rst_rbcp_auto_mode (0- no auto deassertion; 1 - auto deassertion); [6] rst_dmae_assert_on_core_rst(0 - no; 1 - yes); [7-12] reserved; [13] rst_dbg_auto_mode (0- no auto deassertion; 1 - auto deassertion); [14] rst_misc_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [15] reserved; [16] grc_reset_assert_on_core_rst (0 - no; 1 - yes); [17] reserved; [18] rst_rbcz_assert_on_core_rst(0 - no; 1 - yes); [19] rst_rbc{n|h}_assert_on_core_rst(0 - no; 1 - yes); [20] rst_dbg_assert_on_core_rst (0 - no; 1 - yes); [21] rst_misc_core_assert_on_core_rst (0 - no; 1 - yes); [22] rst_wol_assert_on_core_rst; [23]wrappers_iddq_and_rst_signals_assert_on_core_rst (0 - no; 1 - yes); [24] rst_atc_auto_mode (0- no auto deassertion; 1 - auto deassertion); [25-31] reserved; Reset on hard reset.  Chips: BB_A0 BB_B0 K2
29939 #define MISC_REG_RESET_PL_UA                                                                         0x008050UL //Access:RW   DataWidth:0x20  Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_misc_core; [1] rst_grc; [2] rst_rbcn; [3] rst_rbcz; [4] reserved;  Chips: BB_A0 BB_B0 K2
29940 #define MISC_REG_RESET_PL_UA_SIZE                                                                    3
29941 #define MISC_REG_RESET_PL_HV                                                                         0x008060UL //Access:RW   DataWidth:0x20  Reset_reg: Non-shared blocks which can be reset also by driver in HV (PL=HV); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_pswhst; [1] rst_pswrq; [2] rst_pswrd; [3] rst_pswwr; [4] rst_atc;  Chips: BB_A0 BB_B0 K2
29942 #define MISC_REG_RESET_PL_HV_SIZE                                                                    3
29943 #define MISC_REG_RESET_PL_PDA_VMAIN_1                                                                0x008070UL //Access:RW   DataWidth:0x20  Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_brb; [1] rst_prs; [2] rst_src; [3] rst_tsdm; [4] rst_tsem; [5] rst_tcm; [6] rst_rbcr;[7] rst_usdm; [8]rst_ucm; [9] rst_usem; [10] rst_btb; [11] rst_pbf_pb1; [12] rst_pbf_pb2; [13] rst_rpb; [14] rst_rbcu; [15] rst_pbf; [16] rst_qm; [17] rst_tm; [18] rst_dorq; [19] rst_xcm; [20] rst_xsdm; [21] rst_xsem; [22] rst_rbct; [23] rst_cdu; [24] rst_ccfc;[25] rst_tcfc;[26] rst_rbcp; [27] rst_igu; [28] rst_dmae; [29] rst_semi_rtc;.  Chips: BB_A0 BB_B0 K2
29944 #define MISC_REG_RESET_PL_PDA_VMAIN_1_SIZE                                                           3
29945 #define MISC_REG_RESET_PL_PDA_VMAIN_2                                                                0x008080UL //Access:RW   DataWidth:0x20  Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vmain domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_rbcf; [1] rst_rbcx; [2] rst_rbcs; [3] rst_mcm; [4] rst_pcm; [5] rst_ycm; [6] rst_msdm; [7] rst_ysdm; [8] rst_psdm;  [9] rst_msem; [10] rst_ysem; [11] rst_psem; [12] rst_xyld; [13] rst_tmld; [14] rst_muld; [15] rst_yuld; [16] rst_rdif; [17] rst_tdif; [18] rst_rss; [19] rst_cau; [20] rst_ptu; [21] rst_prm; [22] rst_rbcy; [23] rst_rbcq; [24] rst_rbcm; [25] rst_rbcb; [26] rst_rbcv; [27-31] reserved.  Chips: BB_A0 BB_B0 K2
29946 #define MISC_REG_RESET_PL_PDA_VMAIN_2_SIZE                                                           3
29947 #define MISC_REG_RESET_PL_PDA_VAUX                                                                   0x008090UL //Access:RW   DataWidth:0x20  Reset_reg: Unprotected non-shared blocks: Will include the reset of the blocks which can be reset by all types of PF drivers (PL=PDA) Vaux domain; Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nig; [1] rst_rbch; [2] rst_nig_hard; [3] rst_dbg; [6:4] reserved; [7] rst_wol; [8] rst_wol_hard; [9] rst_bmbn;  Chips: BB_A0 BB_B0 K2
29948 #define MISC_REG_RESET_PL_PDA_VAUX_SIZE                                                              3
29949 #define MISC_REG_RESET_PL_UA_VMAIN                                                                   0x0080a0UL //Access:RW   DataWidth:0x4   Reset_reg: Non-shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_vmain_pd_ars;  Chips: BB_B0
29950 #define MISC_REG_RESET_PL_UA_VMAIN_SIZE                                                              3
29951 #define MISC_REG_INT_STS                                                                             0x008180UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
29952     #define MISC_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
29953     #define MISC_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
29954 #define MISC_REG_INT_MASK                                                                            0x008184UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
29955     #define MISC_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: MISC_REG_INT_STS.ADDRESS_ERROR .
29956     #define MISC_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
29957 #define MISC_REG_INT_STS_WR                                                                          0x008188UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
29958     #define MISC_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
29959     #define MISC_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
29960 #define MISC_REG_INT_STS_CLR                                                                         0x00818cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
29961     #define MISC_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
29962     #define MISC_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
29963 #define MISC_REG_AEU_GENERAL_ATTN_0                                                                  0x008400UL //Access:RW   DataWidth:0x1   Set/clr general attention 0; this will set/clr bit 48 in AEU vector.  Chips: BB_A0 BB_B0 K2
29964 #define MISC_REG_AEU_GENERAL_ATTN_1                                                                  0x008404UL //Access:RW   DataWidth:0x1   Set/clr general attention  1; this will set/clr bit 49 in AEU vector.  Chips: BB_A0 BB_B0 K2
29965 #define MISC_REG_AEU_GENERAL_ATTN_2                                                                  0x008408UL //Access:RW   DataWidth:0x1   Set/clr general attention  2; this will set/clr bit 50 in AEU vector.  Chips: BB_A0 BB_B0 K2
29966 #define MISC_REG_AEU_GENERAL_ATTN_3                                                                  0x00840cUL //Access:RW   DataWidth:0x1   Set/clr general attention  3; this will set/clr bit 51 in AEU vector.  Chips: BB_A0 BB_B0 K2
29967 #define MISC_REG_AEU_GENERAL_ATTN_4                                                                  0x008410UL //Access:RW   DataWidth:0x1   Set/clr general attention 4; this will set/clr bit 52 in AEU vector.  Chips: BB_A0 BB_B0 K2
29968 #define MISC_REG_AEU_GENERAL_ATTN_5                                                                  0x008414UL //Access:RW   DataWidth:0x1   Set/clr general attention 5; this will set/clr bit 53 in AEU vector.  Chips: BB_A0 BB_B0 K2
29969 #define MISC_REG_AEU_GENERAL_ATTN_6                                                                  0x008418UL //Access:RW   DataWidth:0x1   Set/clr general attention 6; this will set/clr bit 54 in AEU vector.  Chips: BB_A0 BB_B0 K2
29970 #define MISC_REG_AEU_GENERAL_ATTN_7                                                                  0x00841cUL //Access:RW   DataWidth:0x1   Set/clr general attention 7; this will set/clr bit 55 in AEU vector.  Chips: BB_A0 BB_B0 K2
29971 #define MISC_REG_AEU_GENERAL_ATTN_8                                                                  0x008420UL //Access:RW   DataWidth:0x1   Set/clr general attention 8; this will set/clr bit 56 in AEU vector.  Chips: BB_A0 BB_B0 K2
29972 #define MISC_REG_AEU_GENERAL_ATTN_9                                                                  0x008424UL //Access:RW   DataWidth:0x1   Set/clr general attention 9; this will set/clr bit 57 in AEU vector.  Chips: BB_A0 BB_B0 K2
29973 #define MISC_REG_AEU_GENERAL_ATTN_10                                                                 0x008428UL //Access:RW   DataWidth:0x1   Set/clr general attention 10; this will set/clr bit 58 in AEU vector.  Chips: BB_A0 BB_B0 K2
29974 #define MISC_REG_AEU_GENERAL_ATTN_11                                                                 0x00842cUL //Access:RW   DataWidth:0x1   Set/clr general attention 11; this will set/clr bit 59 in AEU vector.  Chips: BB_A0 BB_B0 K2
29975 #define MISC_REG_AEU_GENERAL_ATTN_12                                                                 0x008430UL //Access:RW   DataWidth:0x1   Set/clr general attention 12; this will set/clr bit 60 in AEU vector.  Chips: BB_A0 BB_B0 K2
29976 #define MISC_REG_AEU_GENERAL_ATTN_13                                                                 0x008434UL //Access:RW   DataWidth:0x1   Set/clr general attention 13; this will set/clr bit 61 in AEU vector.  Chips: BB_A0 BB_B0 K2
29977 #define MISC_REG_AEU_GENERAL_ATTN_14                                                                 0x008438UL //Access:RW   DataWidth:0x1   Set/clr general attention 14; this will set/clr bit 62 in AEU vector.  Chips: BB_A0 BB_B0 K2
29978 #define MISC_REG_AEU_GENERAL_ATTN_15                                                                 0x00843cUL //Access:RW   DataWidth:0x1   Set/clr general attention 15; this will set/clr bit 63 in AEU vector.  Chips: BB_A0 BB_B0 K2
29979 #define MISC_REG_AEU_GENERAL_ATTN_16                                                                 0x008440UL //Access:RW   DataWidth:0x1   Set/clr general attention 16; this will set/clr bit 64 in AEU vector.  Chips: BB_A0 BB_B0 K2
29980 #define MISC_REG_AEU_GENERAL_ATTN_17                                                                 0x008444UL //Access:RW   DataWidth:0x1   Set/clr general attention 17; this will set/clr bit 65 in AEU vector.  Chips: BB_A0 BB_B0 K2
29981 #define MISC_REG_AEU_GENERAL_ATTN_18                                                                 0x008448UL //Access:RW   DataWidth:0x1   Set/clr general attention 18; this will set/clr bit 66 in AEU vector.  Chips: BB_A0 BB_B0 K2
29982 #define MISC_REG_AEU_GENERAL_ATTN_19                                                                 0x00844cUL //Access:RW   DataWidth:0x1   Set/clr general attention 19; this will set/clr bit 67 in AEU vector.  Chips: BB_A0 BB_B0 K2
29983 #define MISC_REG_AEU_GENERAL_ATTN_20                                                                 0x008450UL //Access:RW   DataWidth:0x1   Set/clr general attention 20; this will set/clr bit 68 in AEU vector.  Chips: BB_A0 BB_B0 K2
29984 #define MISC_REG_AEU_GENERAL_ATTN_21                                                                 0x008454UL //Access:RW   DataWidth:0x1   Set/clr general attention 21; this will set/clr bit 69 in AEU vector.  Chips: BB_A0 BB_B0 K2
29985 #define MISC_REG_AEU_GENERAL_ATTN_22                                                                 0x008458UL //Access:RW   DataWidth:0x1   Set/clr general attention 22; this will set/clr bit 70 in AEU vector.  Chips: BB_A0 BB_B0 K2
29986 #define MISC_REG_AEU_GENERAL_ATTN_23                                                                 0x00845cUL //Access:RW   DataWidth:0x1   Set/clr general attention 23; this will set/clr bit 71 in AEU vector.  Chips: BB_A0 BB_B0 K2
29987 #define MISC_REG_AEU_GENERAL_ATTN_24                                                                 0x008460UL //Access:RW   DataWidth:0x1   Set/clr general attention 24; this will set/clr bit 72 in AEU vector.  Chips: BB_A0 BB_B0 K2
29988 #define MISC_REG_AEU_GENERAL_ATTN_25                                                                 0x008464UL //Access:RW   DataWidth:0x1   Set/clr general attention 25; this will set/clr bit 73 in AEU vector.  Chips: BB_A0 BB_B0 K2
29989 #define MISC_REG_AEU_GENERAL_ATTN_26                                                                 0x008468UL //Access:RW   DataWidth:0x1   Set/clr general attention 26; this will set/clr bit 74 in AEU vector.  Chips: BB_A0 BB_B0 K2
29990 #define MISC_REG_AEU_GENERAL_ATTN_27                                                                 0x00846cUL //Access:RW   DataWidth:0x1   Set/clr general attention 27; this will set/clr bit 75 in AEU vector.  Chips: BB_A0 BB_B0 K2
29991 #define MISC_REG_AEU_GENERAL_ATTN_28                                                                 0x008470UL //Access:RW   DataWidth:0x1   Set/clr general attention 28; this will set/clr bit 76 in AEU vector.  Chips: BB_A0 BB_B0 K2
29992 #define MISC_REG_AEU_GENERAL_ATTN_29                                                                 0x008474UL //Access:RW   DataWidth:0x1   Set/clr general attention 29; this will set/clr bit 77 in AEU vector.  Chips: BB_A0 BB_B0 K2
29993 #define MISC_REG_AEU_GENERAL_ATTN_30                                                                 0x008478UL //Access:RW   DataWidth:0x1   Set/clr general attention 30; this will set/clr bit 78 in AEU vector.  Chips: BB_A0 BB_B0 K2
29994 #define MISC_REG_AEU_GENERAL_ATTN_31                                                                 0x00847cUL //Access:RW   DataWidth:0x1   Set/clr general attention 31; this will set/clr bit 79 in AEU vector.  Chips: BB_A0 BB_B0 K2
29995 #define MISC_REG_AEU_GENERAL_ATTN_32                                                                 0x008480UL //Access:RW   DataWidth:0x1   Set/clr general attention 32; this will set/clr bit 80 in AEU vector.  Chips: BB_A0 BB_B0 K2
29996 #define MISC_REG_AEU_GENERAL_ATTN_33                                                                 0x008484UL //Access:RW   DataWidth:0x1   Set/clr general attention 33; this will set/clr bit 81 in AEU vector.  Chips: BB_A0 BB_B0 K2
29997 #define MISC_REG_AEU_GENERAL_ATTN_34                                                                 0x008488UL //Access:RW   DataWidth:0x1   Set/clr general attention 34; this will set/clr bit 82 in AEU vector.  Chips: BB_A0 BB_B0 K2
29998 #define MISC_REG_AEU_GENERAL_ATTN_35                                                                 0x00848cUL //Access:RW   DataWidth:0x1   Set/clr general attention 35; this will set/clr bit 83 in AEU vector.  Chips: BB_A0 BB_B0 K2
29999 #define MISC_REG_AEU_EVENT_ENABLE                                                                    0x008490UL //Access:RW   DataWidth:0x1   Event_enable control; when this bit is clear the event enable toward the MCP is masked.  Chips: BB_A0 BB_B0 K2
30000 #define MISC_REG_AEU_MASK_ATTN_IGU                                                                   0x008494UL //Access:RW   DataWidth:0x8   [7:0] = mask 8 attention output signals toward IGU; 0 = mask; 1 = unmask.  Chips: BB_A0 BB_B0 K2
30001 #define MISC_REG_AEU_MASK_ATTN_MCP                                                                   0x008498UL //Access:RW   DataWidth:0x8   Masks 8 attention output signals toward MCP. Zero = mask; one = unmask.  Chips: BB_A0 BB_B0 K2
30002 #define MISC_REG_AEU_ENABLE1_IGU_OUT_0                                                               0x00849cUL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30003 #define MISC_REG_AEU_ENABLE2_IGU_OUT_0                                                               0x0084a0UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output0. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30004 #define MISC_REG_AEU_ENABLE3_IGU_OUT_0                                                               0x0084a4UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output0. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30005 #define MISC_REG_AEU_ENABLE4_IGU_OUT_0                                                               0x0084a8UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30006 #define MISC_REG_AEU_ENABLE5_IGU_OUT_0                                                               0x0084acUL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output0. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30007 #define MISC_REG_AEU_ENABLE6_IGU_OUT_0                                                               0x0084b0UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output0. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30008 #define MISC_REG_AEU_ENABLE7_IGU_OUT_0                                                               0x0084b4UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output0. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30009 #define MISC_REG_AEU_ENABLE8_IGU_OUT_0                                                               0x0084b8UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output0. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30010 #define MISC_REG_AEU_ENABLE9_IGU_OUT_0                                                               0x0084bcUL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output0. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30011 #define MISC_REG_AEU_ENABLE1_IGU_OUT_1                                                               0x0084c0UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output1. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30012 #define MISC_REG_AEU_ENABLE2_IGU_OUT_1                                                               0x0084c4UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output1. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30013 #define MISC_REG_AEU_ENABLE3_IGU_OUT_1                                                               0x0084c8UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output1. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30014 #define MISC_REG_AEU_ENABLE4_IGU_OUT_1                                                               0x0084ccUL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output1. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30015 #define MISC_REG_AEU_ENABLE5_IGU_OUT_1                                                               0x0084d0UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output1. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30016 #define MISC_REG_AEU_ENABLE6_IGU_OUT_1                                                               0x0084d4UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output1. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30017 #define MISC_REG_AEU_ENABLE7_IGU_OUT_1                                                               0x0084d8UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output1. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30018 #define MISC_REG_AEU_ENABLE8_IGU_OUT_1                                                               0x0084dcUL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output1. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30019 #define MISC_REG_AEU_ENABLE9_IGU_OUT_1                                                               0x0084e0UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output1. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30020 #define MISC_REG_AEU_ENABLE1_IGU_OUT_2                                                               0x0084e4UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output2. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30021 #define MISC_REG_AEU_ENABLE2_IGU_OUT_2                                                               0x0084e8UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output2. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30022 #define MISC_REG_AEU_ENABLE3_IGU_OUT_2                                                               0x0084ecUL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output2. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30023 #define MISC_REG_AEU_ENABLE4_IGU_OUT_2                                                               0x0084f0UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output2. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30024 #define MISC_REG_AEU_ENABLE5_IGU_OUT_2                                                               0x0084f4UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output2. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30025 #define MISC_REG_AEU_ENABLE6_IGU_OUT_2                                                               0x0084f8UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output2. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30026 #define MISC_REG_AEU_ENABLE7_IGU_OUT_2                                                               0x0084fcUL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output2. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30027 #define MISC_REG_AEU_ENABLE8_IGU_OUT_2                                                               0x008500UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output2. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30028 #define MISC_REG_AEU_ENABLE9_IGU_OUT_2                                                               0x008504UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output2. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30029 #define MISC_REG_AEU_ENABLE1_IGU_OUT_3                                                               0x008508UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output3. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30030 #define MISC_REG_AEU_ENABLE2_IGU_OUT_3                                                               0x00850cUL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output3. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30031 #define MISC_REG_AEU_ENABLE3_IGU_OUT_3                                                               0x008510UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output3. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30032 #define MISC_REG_AEU_ENABLE4_IGU_OUT_3                                                               0x008514UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output3. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30033 #define MISC_REG_AEU_ENABLE5_IGU_OUT_3                                                               0x008518UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output3. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30034 #define MISC_REG_AEU_ENABLE6_IGU_OUT_3                                                               0x00851cUL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output3. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30035 #define MISC_REG_AEU_ENABLE7_IGU_OUT_3                                                               0x008520UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output3. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30036 #define MISC_REG_AEU_ENABLE8_IGU_OUT_3                                                               0x008524UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output3. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30037 #define MISC_REG_AEU_ENABLE9_IGU_OUT_3                                                               0x008528UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output3. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30038 #define MISC_REG_AEU_ENABLE1_IGU_OUT_4                                                               0x00852cUL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output4. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30039 #define MISC_REG_AEU_ENABLE2_IGU_OUT_4                                                               0x008530UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output4. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30040 #define MISC_REG_AEU_ENABLE3_IGU_OUT_4                                                               0x008534UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output4. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30041 #define MISC_REG_AEU_ENABLE4_IGU_OUT_4                                                               0x008538UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output4. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30042 #define MISC_REG_AEU_ENABLE5_IGU_OUT_4                                                               0x00853cUL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output4. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30043 #define MISC_REG_AEU_ENABLE6_IGU_OUT_4                                                               0x008540UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output4. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30044 #define MISC_REG_AEU_ENABLE7_IGU_OUT_4                                                               0x008544UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output4. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30045 #define MISC_REG_AEU_ENABLE8_IGU_OUT_4                                                               0x008548UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output4. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30046 #define MISC_REG_AEU_ENABLE9_IGU_OUT_4                                                               0x00854cUL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output4. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30047 #define MISC_REG_AEU_ENABLE1_IGU_OUT_5                                                               0x008550UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output5. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30048 #define MISC_REG_AEU_ENABLE2_IGU_OUT_5                                                               0x008554UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output5. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30049 #define MISC_REG_AEU_ENABLE3_IGU_OUT_5                                                               0x008558UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output5. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30050 #define MISC_REG_AEU_ENABLE4_IGU_OUT_5                                                               0x00855cUL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output5. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30051 #define MISC_REG_AEU_ENABLE5_IGU_OUT_5                                                               0x008560UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output5. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30052 #define MISC_REG_AEU_ENABLE6_IGU_OUT_5                                                               0x008564UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output5. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30053 #define MISC_REG_AEU_ENABLE7_IGU_OUT_5                                                               0x008568UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output5. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30054 #define MISC_REG_AEU_ENABLE8_IGU_OUT_5                                                               0x00856cUL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output5. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30055 #define MISC_REG_AEU_ENABLE9_IGU_OUT_5                                                               0x008570UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output5. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30056 #define MISC_REG_AEU_ENABLE1_IGU_OUT_6                                                               0x008574UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output6. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30057 #define MISC_REG_AEU_ENABLE2_IGU_OUT_6                                                               0x008578UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output6. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30058 #define MISC_REG_AEU_ENABLE3_IGU_OUT_6                                                               0x00857cUL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output6. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30059 #define MISC_REG_AEU_ENABLE4_IGU_OUT_6                                                               0x008580UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output6. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30060 #define MISC_REG_AEU_ENABLE5_IGU_OUT_6                                                               0x008584UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output6. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30061 #define MISC_REG_AEU_ENABLE6_IGU_OUT_6                                                               0x008588UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output6. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30062 #define MISC_REG_AEU_ENABLE7_IGU_OUT_6                                                               0x00858cUL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output6. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30063 #define MISC_REG_AEU_ENABLE8_IGU_OUT_6                                                               0x008590UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output6. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30064 #define MISC_REG_AEU_ENABLE9_IGU_OUT_6                                                               0x008594UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output6. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30065 #define MISC_REG_AEU_ENABLE1_IGU_OUT_7                                                               0x008598UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output7. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30066 #define MISC_REG_AEU_ENABLE2_IGU_OUT_7                                                               0x00859cUL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output7. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30067 #define MISC_REG_AEU_ENABLE3_IGU_OUT_7                                                               0x0085a0UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output7. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30068 #define MISC_REG_AEU_ENABLE4_IGU_OUT_7                                                               0x0085a4UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output7. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30069 #define MISC_REG_AEU_ENABLE5_IGU_OUT_7                                                               0x0085a8UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output7. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30070 #define MISC_REG_AEU_ENABLE6_IGU_OUT_7                                                               0x0085acUL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output7. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30071 #define MISC_REG_AEU_ENABLE7_IGU_OUT_7                                                               0x0085b0UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output7. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30072 #define MISC_REG_AEU_ENABLE8_IGU_OUT_7                                                               0x0085b4UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output7. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30073 #define MISC_REG_AEU_ENABLE9_IGU_OUT_7                                                               0x0085b8UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output7. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30074 #define MISC_REG_AEU_ENABLE1_NIG                                                                     0x0085bcUL //Access:RW   DataWidth:0x20  First 32b for enabling the output for close the gate nig. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30075 #define MISC_REG_AEU_ENABLE2_NIG                                                                     0x0085c0UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for close the gate nig. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30076 #define MISC_REG_AEU_ENABLE3_NIG                                                                     0x0085c4UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for close the gate nig. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30077 #define MISC_REG_AEU_ENABLE4_NIG                                                                     0x0085c8UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for close the gate nig. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30078 #define MISC_REG_AEU_ENABLE5_NIG                                                                     0x0085ccUL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for close the gate nig. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30079 #define MISC_REG_AEU_ENABLE6_NIG                                                                     0x0085d0UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for close the gate nig. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30080 #define MISC_REG_AEU_ENABLE7_NIG                                                                     0x0085d4UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for close the gate nig. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30081 #define MISC_REG_AEU_ENABLE8_NIG                                                                     0x0085d8UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for close the gate nig. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30082 #define MISC_REG_AEU_ENABLE9_NIG                                                                     0x0085dcUL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for close the gate nig. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30083 #define MISC_REG_AEU_ENABLE1_PXP                                                                     0x0085e0UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for close the gate pxp. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30084 #define MISC_REG_AEU_ENABLE2_PXP                                                                     0x0085e4UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for close the gate pxp. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30085 #define MISC_REG_AEU_ENABLE3_PXP                                                                     0x0085e8UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for close the gate pxp. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30086 #define MISC_REG_AEU_ENABLE4_PXP                                                                     0x0085ecUL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30087 #define MISC_REG_AEU_ENABLE5_PXP                                                                     0x0085f0UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30088 #define MISC_REG_AEU_ENABLE6_PXP                                                                     0x0085f4UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30089 #define MISC_REG_AEU_ENABLE7_PXP                                                                     0x0085f8UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for close the gate pxp. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30090 #define MISC_REG_AEU_ENABLE8_PXP                                                                     0x0085fcUL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30091 #define MISC_REG_AEU_ENABLE9_PXP                                                                     0x008600UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for close the gate pxp. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30092 #define MISC_REG_AEU_ENABLE1_SYS_KILL                                                                0x008604UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for system kill. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30093 #define MISC_REG_AEU_ENABLE2_SYS_KILL                                                                0x008608UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for system kill. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30094 #define MISC_REG_AEU_ENABLE3_SYS_KILL                                                                0x00860cUL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for system kill. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30095 #define MISC_REG_AEU_ENABLE4_SYS_KILL                                                                0x008610UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for system kill. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30096 #define MISC_REG_AEU_ENABLE5_SYS_KILL                                                                0x008614UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for system kill. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30097 #define MISC_REG_AEU_ENABLE6_SYS_KILL                                                                0x008618UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for system kill. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30098 #define MISC_REG_AEU_ENABLE7_SYS_KILL                                                                0x00861cUL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for system kill. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30099 #define MISC_REG_AEU_ENABLE8_SYS_KILL                                                                0x008620UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for system kill. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30100 #define MISC_REG_AEU_ENABLE9_SYS_KILL                                                                0x008624UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for system kill. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30101 #define MISC_REG_AEU_ENABLE1_MCP_OUT_0                                                               0x008628UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30102 #define MISC_REG_AEU_ENABLE2_MCP_OUT_0                                                               0x00862cUL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output0. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30103 #define MISC_REG_AEU_ENABLE3_MCP_OUT_0                                                               0x008630UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output0. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30104 #define MISC_REG_AEU_ENABLE4_MCP_OUT_0                                                               0x008634UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30105 #define MISC_REG_AEU_ENABLE5_MCP_OUT_0                                                               0x008638UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output0. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30106 #define MISC_REG_AEU_ENABLE6_MCP_OUT_0                                                               0x00863cUL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output0. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30107 #define MISC_REG_AEU_ENABLE7_MCP_OUT_0                                                               0x008640UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output0. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30108 #define MISC_REG_AEU_ENABLE8_MCP_OUT_0                                                               0x008644UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output0. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30109 #define MISC_REG_AEU_ENABLE9_MCP_OUT_0                                                               0x008648UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output0. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30110 #define MISC_REG_AEU_ENABLE1_MCP_OUT_1                                                               0x00864cUL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output1. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30111 #define MISC_REG_AEU_ENABLE2_MCP_OUT_1                                                               0x008650UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output1. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30112 #define MISC_REG_AEU_ENABLE3_MCP_OUT_1                                                               0x008654UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output1. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30113 #define MISC_REG_AEU_ENABLE4_MCP_OUT_1                                                               0x008658UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output1. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30114 #define MISC_REG_AEU_ENABLE5_MCP_OUT_1                                                               0x00865cUL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output1. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30115 #define MISC_REG_AEU_ENABLE6_MCP_OUT_1                                                               0x008660UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output1. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30116 #define MISC_REG_AEU_ENABLE7_MCP_OUT_1                                                               0x008664UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output1. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30117 #define MISC_REG_AEU_ENABLE8_MCP_OUT_1                                                               0x008668UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output1. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30118 #define MISC_REG_AEU_ENABLE9_MCP_OUT_1                                                               0x00866cUL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output1. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30119 #define MISC_REG_AEU_ENABLE1_MCP_OUT_2                                                               0x008670UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output2. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30120 #define MISC_REG_AEU_ENABLE2_MCP_OUT_2                                                               0x008674UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output2. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30121 #define MISC_REG_AEU_ENABLE3_MCP_OUT_2                                                               0x008678UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output2. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30122 #define MISC_REG_AEU_ENABLE4_MCP_OUT_2                                                               0x00867cUL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output2. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30123 #define MISC_REG_AEU_ENABLE5_MCP_OUT_2                                                               0x008680UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output2. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30124 #define MISC_REG_AEU_ENABLE6_MCP_OUT_2                                                               0x008684UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output2. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30125 #define MISC_REG_AEU_ENABLE7_MCP_OUT_2                                                               0x008688UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output2. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30126 #define MISC_REG_AEU_ENABLE8_MCP_OUT_2                                                               0x00868cUL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output2. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30127 #define MISC_REG_AEU_ENABLE9_MCP_OUT_2                                                               0x008690UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output2. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30128 #define MISC_REG_AEU_ENABLE1_MCP_OUT_3                                                               0x008694UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output3. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30129 #define MISC_REG_AEU_ENABLE2_MCP_OUT_3                                                               0x008698UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output3. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30130 #define MISC_REG_AEU_ENABLE3_MCP_OUT_3                                                               0x00869cUL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output3. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30131 #define MISC_REG_AEU_ENABLE4_MCP_OUT_3                                                               0x0086a0UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output3. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30132 #define MISC_REG_AEU_ENABLE5_MCP_OUT_3                                                               0x0086a4UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output3. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30133 #define MISC_REG_AEU_ENABLE6_MCP_OUT_3                                                               0x0086a8UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output3. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30134 #define MISC_REG_AEU_ENABLE7_MCP_OUT_3                                                               0x0086acUL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output3. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30135 #define MISC_REG_AEU_ENABLE8_MCP_OUT_3                                                               0x0086b0UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output3. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30136 #define MISC_REG_AEU_ENABLE9_MCP_OUT_3                                                               0x0086b4UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output3. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30137 #define MISC_REG_AEU_ENABLE1_MCP_OUT_4                                                               0x0086b8UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output4. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30138 #define MISC_REG_AEU_ENABLE2_MCP_OUT_4                                                               0x0086bcUL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output4. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30139 #define MISC_REG_AEU_ENABLE3_MCP_OUT_4                                                               0x0086c0UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output4. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30140 #define MISC_REG_AEU_ENABLE4_MCP_OUT_4                                                               0x0086c4UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output4. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30141 #define MISC_REG_AEU_ENABLE5_MCP_OUT_4                                                               0x0086c8UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output4. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30142 #define MISC_REG_AEU_ENABLE6_MCP_OUT_4                                                               0x0086ccUL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output4. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30143 #define MISC_REG_AEU_ENABLE7_MCP_OUT_4                                                               0x0086d0UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output4. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30144 #define MISC_REG_AEU_ENABLE8_MCP_OUT_4                                                               0x0086d4UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output4. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30145 #define MISC_REG_AEU_ENABLE9_MCP_OUT_4                                                               0x0086d8UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output4. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30146 #define MISC_REG_AEU_ENABLE1_MCP_OUT_5                                                               0x0086dcUL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output5. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30147 #define MISC_REG_AEU_ENABLE2_MCP_OUT_5                                                               0x0086e0UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output5. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30148 #define MISC_REG_AEU_ENABLE3_MCP_OUT_5                                                               0x0086e4UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output5. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30149 #define MISC_REG_AEU_ENABLE4_MCP_OUT_5                                                               0x0086e8UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output5. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30150 #define MISC_REG_AEU_ENABLE5_MCP_OUT_5                                                               0x0086ecUL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output5. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30151 #define MISC_REG_AEU_ENABLE6_MCP_OUT_5                                                               0x0086f0UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output5. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30152 #define MISC_REG_AEU_ENABLE7_MCP_OUT_5                                                               0x0086f4UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output5. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30153 #define MISC_REG_AEU_ENABLE8_MCP_OUT_5                                                               0x0086f8UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output5. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30154 #define MISC_REG_AEU_ENABLE9_MCP_OUT_5                                                               0x0086fcUL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output5. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30155 #define MISC_REG_AEU_ENABLE1_MCP_OUT_6                                                               0x008700UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output6. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30156 #define MISC_REG_AEU_ENABLE2_MCP_OUT_6                                                               0x008704UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output6. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30157 #define MISC_REG_AEU_ENABLE3_MCP_OUT_6                                                               0x008708UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output6. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30158 #define MISC_REG_AEU_ENABLE4_MCP_OUT_6                                                               0x00870cUL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output6. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30159 #define MISC_REG_AEU_ENABLE5_MCP_OUT_6                                                               0x008710UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output6. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30160 #define MISC_REG_AEU_ENABLE6_MCP_OUT_6                                                               0x008714UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output6. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30161 #define MISC_REG_AEU_ENABLE7_MCP_OUT_6                                                               0x008718UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output6. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30162 #define MISC_REG_AEU_ENABLE8_MCP_OUT_6                                                               0x00871cUL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output6. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30163 #define MISC_REG_AEU_ENABLE9_MCP_OUT_6                                                               0x008720UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output6. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30164 #define MISC_REG_AEU_ENABLE1_MCP_OUT_7                                                               0x008724UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for output7. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30165 #define MISC_REG_AEU_ENABLE2_MCP_OUT_7                                                               0x008728UL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for output7. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30166 #define MISC_REG_AEU_ENABLE3_MCP_OUT_7                                                               0x00872cUL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for output7. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30167 #define MISC_REG_AEU_ENABLE4_MCP_OUT_7                                                               0x008730UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for output7. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30168 #define MISC_REG_AEU_ENABLE5_MCP_OUT_7                                                               0x008734UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for output7. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30169 #define MISC_REG_AEU_ENABLE6_MCP_OUT_7                                                               0x008738UL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for output7. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30170 #define MISC_REG_AEU_ENABLE7_MCP_OUT_7                                                               0x00873cUL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for output7. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30171 #define MISC_REG_AEU_ENABLE8_MCP_OUT_7                                                               0x008740UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for output7. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30172 #define MISC_REG_AEU_ENABLE9_MCP_OUT_7                                                               0x008744UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for output7. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30173 #define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR                                                             0x008748UL //Access:RW   DataWidth:0x20  First 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30174 #define MISC_REG_AEU_ENABLE2_GLB_UNC_ERR                                                             0x00874cUL //Access:RW   DataWidth:0x20  Second 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30175 #define MISC_REG_AEU_ENABLE3_GLB_UNC_ERR                                                             0x008750UL //Access:RW   DataWidth:0x20  Third 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30176 #define MISC_REG_AEU_ENABLE4_GLB_UNC_ERR                                                             0x008754UL //Access:RW   DataWidth:0x20  Fourth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30177 #define MISC_REG_AEU_ENABLE5_GLB_UNC_ERR                                                             0x008758UL //Access:RW   DataWidth:0x20  Fifth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30178 #define MISC_REG_AEU_ENABLE6_GLB_UNC_ERR                                                             0x00875cUL //Access:RW   DataWidth:0x20  Sixth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30179 #define MISC_REG_AEU_ENABLE7_GLB_UNC_ERR                                                             0x008760UL //Access:RW   DataWidth:0x20  Seventh 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30180 #define MISC_REG_AEU_ENABLE8_GLB_UNC_ERR                                                             0x008764UL //Access:RW   DataWidth:0x20  Eighth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30181 #define MISC_REG_AEU_ENABLE9_GLB_UNC_ERR                                                             0x008768UL //Access:RW   DataWidth:0x20  Nineth 32b for enabling the output for global uncorrectable eror. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30182 #define MISC_REG_AEU_INVERTER_1_IGU                                                                  0x00876cUL //Access:RW   DataWidth:0x20  First 32b for inverting the input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30183 #define MISC_REG_AEU_INVERTER_2_IGU                                                                  0x008770UL //Access:RW   DataWidth:0x20  Second 32b for inverting the input. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30184 #define MISC_REG_AEU_INVERTER_3_IGU                                                                  0x008774UL //Access:RW   DataWidth:0x20  Third 32b for inverting the input. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30185 #define MISC_REG_AEU_INVERTER_4_IGU                                                                  0x008778UL //Access:RW   DataWidth:0x20  Fourth 32b for inverting the input. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30186 #define MISC_REG_AEU_INVERTER_5_IGU                                                                  0x00877cUL //Access:RW   DataWidth:0x20  Fifth 32b for inverting the input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30187 #define MISC_REG_AEU_INVERTER_6_IGU                                                                  0x008780UL //Access:RW   DataWidth:0x20  Sixth 32b for inverting the input. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30188 #define MISC_REG_AEU_INVERTER_7_IGU                                                                  0x008784UL //Access:RW   DataWidth:0x20  Seventh 32b for inverting the input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30189 #define MISC_REG_AEU_INVERTER_8_IGU                                                                  0x008788UL //Access:RW   DataWidth:0x20  Eighth 32b for inverting the input. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30190 #define MISC_REG_AEU_INVERTER_9_IGU                                                                  0x00878cUL //Access:RW   DataWidth:0x20  Nineth 32b for inverting the input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30191 #define MISC_REG_AEU_INVERTER_1_MCP                                                                  0x008790UL //Access:RW   DataWidth:0x20  First 32b for inverting the input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30192 #define MISC_REG_AEU_INVERTER_2_MCP                                                                  0x008794UL //Access:RW   DataWidth:0x20  Second 32b for inverting the input. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30193 #define MISC_REG_AEU_INVERTER_3_MCP                                                                  0x008798UL //Access:RW   DataWidth:0x20  Third 32b for inverting the input. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30194 #define MISC_REG_AEU_INVERTER_4_MCP                                                                  0x00879cUL //Access:RW   DataWidth:0x20  Fourth 32b for inverting the input. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30195 #define MISC_REG_AEU_INVERTER_5_MCP                                                                  0x0087a0UL //Access:RW   DataWidth:0x20  Fifth 32b for inverting the input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30196 #define MISC_REG_AEU_INVERTER_6_MCP                                                                  0x0087a4UL //Access:RW   DataWidth:0x20  Sixth 32b for inverting the input. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30197 #define MISC_REG_AEU_INVERTER_7_MCP                                                                  0x0087a8UL //Access:RW   DataWidth:0x20  Seventh 32b for inverting the input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30198 #define MISC_REG_AEU_INVERTER_8_MCP                                                                  0x0087acUL //Access:RW   DataWidth:0x20  Eighth 32b for inverting the input. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30199 #define MISC_REG_AEU_INVERTER_9_MCP                                                                  0x0087b0UL //Access:RW   DataWidth:0x20  Nineth 32b for inverting the input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30200 #define MISC_REG_AEU_AFTER_INVERT_1_IGU                                                              0x0087b4UL //Access:R    DataWidth:0x20  First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30201 #define MISC_REG_AEU_AFTER_INVERT_2_IGU                                                              0x0087b8UL //Access:R    DataWidth:0x20  Second 32b read after invert of input. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30202 #define MISC_REG_AEU_AFTER_INVERT_3_IGU                                                              0x0087bcUL //Access:R    DataWidth:0x20  Third 32b read after invert of input. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30203 #define MISC_REG_AEU_AFTER_INVERT_4_IGU                                                              0x0087c0UL //Access:R    DataWidth:0x20  Fourth 32b read after invert of input. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30204 #define MISC_REG_AEU_AFTER_INVERT_5_IGU                                                              0x0087c4UL //Access:R    DataWidth:0x20  Fifth 32b read after invert of input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30205 #define MISC_REG_AEU_AFTER_INVERT_6_IGU                                                              0x0087c8UL //Access:R    DataWidth:0x20  Sixth 32b read after invert of input. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30206 #define MISC_REG_AEU_AFTER_INVERT_7_IGU                                                              0x0087ccUL //Access:R    DataWidth:0x20  Seventh 32b read after invert of input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30207 #define MISC_REG_AEU_AFTER_INVERT_8_IGU                                                              0x0087d0UL //Access:R    DataWidth:0x20  Eighth 32b read after invert of input. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30208 #define MISC_REG_AEU_AFTER_INVERT_9_IGU                                                              0x0087d4UL //Access:R    DataWidth:0x20  Nineth 32b read after invert of input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30209 #define MISC_REG_AEU_AFTER_INVERT_1_MCP                                                              0x0087d8UL //Access:R    DataWidth:0x20  First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30210 #define MISC_REG_AEU_AFTER_INVERT_2_MCP                                                              0x0087dcUL //Access:R    DataWidth:0x20  Second 32b read after invert of input. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30211 #define MISC_REG_AEU_AFTER_INVERT_3_MCP                                                              0x0087e0UL //Access:R    DataWidth:0x20  Third 32b read after invert of input. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30212 #define MISC_REG_AEU_AFTER_INVERT_4_MCP                                                              0x0087e4UL //Access:R    DataWidth:0x20  Fourth 32b read after invert of input. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30213 #define MISC_REG_AEU_AFTER_INVERT_5_MCP                                                              0x0087e8UL //Access:R    DataWidth:0x20  Fifth 32b read after invert of input. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30214 #define MISC_REG_AEU_AFTER_INVERT_6_MCP                                                              0x0087ecUL //Access:R    DataWidth:0x20  Sixth 32b read after invert of input. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30215 #define MISC_REG_AEU_AFTER_INVERT_7_MCP                                                              0x0087f0UL //Access:R    DataWidth:0x20  Seventh 32b read after invert of input. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30216 #define MISC_REG_AEU_AFTER_INVERT_8_MCP                                                              0x0087f4UL //Access:R    DataWidth:0x20  Eighth 32b read after invert of input. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30217 #define MISC_REG_AEU_AFTER_INVERT_9_MCP                                                              0x0087f8UL //Access:R    DataWidth:0x20  Nineth 32b read after invert of input. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30218 #define MISC_REG_AEU_SYS_KILL_OCCURRED                                                               0x0087fcUL //Access:RW   DataWidth:0x1   If set a system kill occurred. Reset on POR reset.  Chips: BB_A0 BB_B0 K2
30219 #define MISC_REG_AEU_SYS_KILL_BEHAVIOR                                                               0x008800UL //Access:RW   DataWidth:0x1   The System Kill enable: 0 - none; 1 - hard reset. Reset on POR reset.  Chips: BB_A0 BB_B0 K2
30220 #define MISC_REG_AEU_SYS_KILL_STATUS_0                                                               0x008804UL //Access:RW   DataWidth:0x20  First 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;  Chips: BB_A0 BB_B0 K2
30221 #define MISC_REG_AEU_SYS_KILL_STATUS_1                                                               0x008808UL //Access:RW   DataWidth:0x20  Second 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt;  [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;  Chips: BB_A0 BB_B0 K2
30222 #define MISC_REG_AEU_SYS_KILL_STATUS_2                                                               0x00880cUL //Access:RW   DataWidth:0x20  Third 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;  Chips: BB_A0 BB_B0 K2
30223 #define MISC_REG_AEU_SYS_KILL_STATUS_3                                                               0x008810UL //Access:RW   DataWidth:0x20  Fourth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;  Chips: BB_A0 BB_B0 K2
30224 #define MISC_REG_AEU_SYS_KILL_STATUS_4                                                               0x008814UL //Access:RW   DataWidth:0x20  Fifth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] SRC Parity error; [1] SRC HW interrupt; [2] PB Client1 Parity error; [3] PB Client1 Hw interrupt; [4] PB Client2 Parity error; [5] PB Client2 Hw interrupt; [6] RPB Parity error; [7] RPB Hw interrupt; [8] PBF Parity error; [9] PBF Hw interrupt; [10] QM Parity error; [11] QM Hw interrupt; [12] TM Parity error; [13] TM Hw interrupt; [14] MCM Parity error; [15] MCM Hw interrupt; [16] MSDM Parity error; [17] MSDM Hw interrupt; [18] MSEM Parity error; [19] MSEM Hw interrupt; [20] PCM Parity error; [21] PCM Hw interrupt; [22] PSDM Parity error; [23] PSDM Hw interrupt; [24] PSEM Parity error; [25] PSEM Hw interrupt; [26] TCM Parity error; [27] TCM Hw interrupt; [28] TSDM Parity error; [29] TSDM Hw interrupt; [30] TSEM Parity error; [31] TSEM Hw interrupt;  Chips: BB_A0 BB_B0 K2
30225 #define MISC_REG_AEU_SYS_KILL_STATUS_5                                                               0x008818UL //Access:RW   DataWidth:0x20  Sixth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] UCM Parity error; [1] UCM Hw interrupt; [2] USDM Parity error; [3] USDM Hw interrupt; [4] USEM Parity error; [5] USEM Hw interrupt; [6] XCM Parity error; [7] XCM Hw interrupt; [8] XSDM Parity error; [9] XSDM Hw interrupt; [10] XSEM Parity error; [11] XSEM Hw interrupt; [12] YCM Parity error; [13] YCM Hw interrupt; [14] YSDM Parity error; [15] YSDM Hw interrupt; [16] YSEM Parity error; [17] YSEM Hw interrupt; [18] XYLD Parity error; [19] XYLD Hw interrupt; [20] TMLD Parity error; [21] TMLD Hw interrupt; [22] MYLD Parity error; [23] MYLD Hw interrupt; [24] YULD Parity error; [25] YULD Hw interrupt; [26] DORQ Parity error; [27] DORQ Hw interrupt; [28] DBG Parity error; [29] DBG Hw interrupt; [30] IPC Parity error; [31] IPC Hw interrupt;  Chips: BB_A0 BB_B0 K2
30226 #define MISC_REG_AEU_SYS_KILL_STATUS_6                                                               0x00881cUL //Access:RW   DataWidth:0x20  Seventh 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] CCFC Parity error; [1] CCFC Hw interrupt; [2] CDU Parity error; [3]CDU Hw interrupt; [4] DMAE Parity error; [5] DMAE Hw interrupt; [6] IGU Parity error; [7] IGU Hw interrupt; [8] ATC Parity error; [9] ATC Hw interrupt; [10] CAU Parity error; [11] CAU Hw interrupt; [12] PTU Parity error; [13] PTU Hw interrupt; [14] PRM Parity error; [15] PRM Hw interrupt; [16] TCFC Parity error; [17] TCFC Hw interrupt; [18] RDIF Parity error; [19] RDIF Hw interrupt; [20] TDIF Parity error; [21] TDIF Hw interrupt; [22] RSS Parity error; [23] RSS Hw interrupt; [24] MISC Parity error; [25] MISC Hw interrupt; [26] MISCS Parity error; [27] MISCS Hw interrupt; [28] Vaux PCI core or PGLUE config space Parity error; [29] Vaux PCI core Hw interrupt; [30] PSWRQ Parity error; [31] PSWRQ Hw interrupt;  Chips: BB_A0 BB_B0 K2
30227 #define MISC_REG_AEU_SYS_KILL_STATUS_7                                                               0x008820UL //Access:RW   DataWidth:0x20  Eighth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PSWRQ (pci_clk) Parity error; [1] PSWRQ (pci_clk) Hw interrupt; [2] PSWWR Parity error; [3] PSWWR Hw interrupt; [4] PSWWR (pci_clk) Parity error; [5] PSWWR (pci_clk) Hw interrupt; [6] PSWRD Parity error; [7] PSWRD Hw interrupt; [8] PSWRD (pci_clk) Parity error; [9] PSWRD (pci_clk) Hw interrupt; [10] PSWHST Parity error; [11] PSWHST Hw interrupt; [12] PSWHST (pci_clk) Parity error; [13] PSWHST (pci_clk) Hw interrupt; [14] GRC Parity error; [15] GRC Hw interrupt; [16] CPMU Parity error; [17] CPMU Hw interrupt; [18] NCSI Parity error; [19] NCSI Hw interrupt; [20] YSEM PRAM Parity error; [21] XSEM PRAM Parity error; [22] USEM PRAM Parity error; [23] TSEM PRAM Parity error; [24] PSEM PRAM Parity error; [25] MSEM PRAM Parity error; [26] pxp_misc_mps_attn; [27] PCIE glue/PXP Expansion ROM event; [28] PERST_B assertion; [29] PERST_B de-assertion; [30] WOL Parity error; [31] WOL Hw interrupt;  Chips: BB_A0 BB_B0 K2
30228 #define MISC_REG_AEU_SYS_KILL_STATUS_8                                                               0x008824UL //Access:RW   DataWidth:0x20  Nineth 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] MCP Latched memory parity; [1] MCP Latched scratchpad cache; [2] AVS Parity error; [3] AVS Hw interrupt; [4] PCIe core Hw interrupt; [5] pcie_rst_b de-assertion latched; [31:6] reserved;  Chips: BB_A0 BB_B0 K2
30229 #define MISC_REG_AEU_GENERAL_MASK                                                                    0x008828UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30230     #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK                                             (0x1<<0) // Pxp close the gate mask bit; 0 = masked; 1 = unmasked.
30231     #define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK_SHIFT                                       0
30232     #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK                                             (0x1<<1) // Nig close the gate mask bit; 0 = masked; 1 = unmasked.
30233     #define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK_SHIFT                                       1
30234     #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK                                              (0x1<<2) // System kill mask bit; 0 = masked; 1 = unmasked.
30235     #define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK_SHIFT                                        2
30236     #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK                                           (0x1<<3) // Global uncorrectable error mask bit; 0 = masked; 1 = unmasked.
30237     #define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK_SHIFT                                     3
30238 #define MISC_REG_AEU_CLR_LATCH_SIGNAL                                                                0x00882cUL //Access:W    DataWidth:0xa   Write to this register results with the clear of the latched signals; [0] one clears Latched MCP memory parity; [1] one clears Latched MCP Scratchpad Cache attention; [3:2] reserved; [4] one clears pglue_misc_mps_attn; [5] one clears pxp_misc_exp_rom_attn; [6] one clears PERST_N assertion (goes 0); [7] one clears PERST_N de-assertion (goes 1). [8] one clears PCIe link up. [9] one clears PCIe hot reset.  Chips: BB_A0 BB_B0 K2
30239 #define MISC_REG_AEU_MASK_ATTN_IGU_MSB                                                               0x008830UL //Access:RW   DataWidth:0xa   Mask 10 MSB attention output signals toward IGU; Zero = mask; one = unmask.  Chips: BB_A0 BB_B0 K2
30240 #define MISC_REG_AEU_CLR_VPD_LATCH_SIGNAL                                                            0x008834UL //Access:W    DataWidth:0x10  Write to this register results with the clear of the latched signals; [0] - clears pglue_misc_vpd_attn[0], [1] - clears pglue_misc_vpd_attn[1], so forth;  read from this register returns 0.  Chips: BB_A0 BB_B0 K2
30241 #define MISC_REG_AEU_VPD_LATCH_STATUS                                                                0x008838UL //Access:R    DataWidth:0x10  Represent the status of pglue_misc_vpd_attn after latching.  Chips: BB_A0 BB_B0 K2
30242 #define MISC_REG_ATTN_NUM_ST                                                                         0x00883cUL //Access:RW   DataWidth:0x9   Attention sticky number - latches first attention number within attentions vector. The number is produced as the index of aeu_after_invert_* multiplied by 32 plus index of the attention bit. Should be written to 0x1ff to release latch.  Chips: BB_B0 K2
30243 #define MISC_REG_PORT_MODE                                                                           0x008c00UL //Access:RW   DataWidth:0x2   Port mode. 0 - single port; 1 - 2 ports; 2 - 4 ports. 2 is prohibited configuration in 2 path device. Reset on POR reset.  Chips: BB_A0 BB_B0 K2
30244 #define MISC_REG_XMAC_PHY_PORT_MODE                                                                  0x008c04UL //Access:RW   DataWidth:0x2   XMAC PHY port mode. Indicates the number of ports on the Warp Core. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 1x - Quad Port Mode; This is a strap input for the XMAC_MP core; and should be changed only while reset is held low. Reset on Hard reset. Not used.  Chips: BB_A0 BB_B0
30245 #define MISC_REG_XMAC_CORE_PORT_MODE                                                                 0x008c08UL //Access:RW   DataWidth:0x2   XMAC Core port mode. Indicates the number of ports on the system side. This should be less than or equal to phy_port_mode; if some of the ports are not used. This enables reduction of frequency on the core side. This is a strap input for the XMAC_MP core. 00 - Single Port Mode; 01 - Dual Port Mode; 10 - Tri Port Mode; 11 - Quad Port Mode. This is a strap input for the XMAC_MP core; and should be changed only while reset is held low. Reset on Hard reset. Not used.  Chips: BB_A0 BB_B0
30246 #define MISC_REG_OPTE_MODE                                                                           0x008c0cUL //Access:RW   DataWidth:0x1   0 - disabled, 1 - enabled. When OPTE mode is enabled, it connects two engines to one MAC port.  Port 0 of each engine is used in this configuration, with support for 8 TCs, 1 pure-LB TC, and 8 global PFs.  Chips: BB_A0 BB_B0 K2
30247 #define MISC_REG_CLK_100G_MODE                                                                       0x008c10UL //Access:RW   DataWidth:0x3   Per bit; 1:  clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0:  clk_nw and main clk are synchronous and sync FIFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB/BTB control, bit2 - NIG control. Reset on Hard reset.  Chips: BB_A0 BB_B0 K2
30248 #define MISC_REG_BLOCK_256B_EN                                                                       0x008c14UL //Access:RW   DataWidth:0x2   This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB, PBF;  Chips: BB_A0 BB_B0 K2
30249 #define MISC_REG_PERST_STATUS                                                                        0x008c18UL //Access:R    DataWidth:0x1   PERST_B status.  Chips: BB_A0 BB_B0 K2
30250 #define MISC_REG_SEM_STALL                                                                           0x008c1cUL //Access:RW   DataWidth:0x3   0 - Storms stall is disallowed; AEU unifier bit[7] output to MCP is disabled; 1 - All Storms are forced to be stopped; AEU unifier bit[7] output to MCP is disabled; 2 - All Storms will be stopped in case AEU unifier bit[7] is set; AEU unifier bit[7] output to MCP is disabled; 4 - Storms stall is disallowed; AEU unifier bit[7] output to MCP is allowed; 5 - All Storms are forced to be stopped; AEU unifier bit[7] output to MCP is allowed; 6 - All Storms will be stopped in case AEU unifier bit[7] is set; AEU unifier bit[7] output to MCP is allowed; 3, 7 are not defined;  Chips: BB_A0 BB_B0 K2
30251 #define MISC_REG_SHARED_MEM_ADDR                                                                     0x008c20UL //Access:RW   DataWidth:0x17  23 bit GRC address where the scratch-pad of the MCP that is shared with the driver resides.  Chips: BB_A0 BB_B0 K2
30252 #define MISC_REG_SW_TIMER_CFG_1                                                                      0x008c24UL //Access:RW   DataWidth:0x6   SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 1 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_1.SW_TIMER_RELOAD_VAL_1 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 1 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).  Chips: BB_A0 BB_B0 K2
30253 #define MISC_REG_SW_TIMER_CFG_2                                                                      0x008c28UL //Access:RW   DataWidth:0x6   SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 2 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_2.SW_TIMER_RELOAD_VAL_2 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 2 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).  Chips: BB_A0 BB_B0 K2
30254 #define MISC_REG_SW_TIMER_CFG_3                                                                      0x008c2cUL //Access:RW   DataWidth:0x6   SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 3 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_3.SW_TIMER_RELOAD_VAL_3 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 3 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).  Chips: BB_A0 BB_B0 K2
30255 #define MISC_REG_SW_TIMER_CFG_4                                                                      0x008c30UL //Access:RW   DataWidth:0x6   SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 4 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_4.SW_TIMER_RELOAD_VAL_4 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 4 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).  Chips: BB_A0 BB_B0 K2
30256 #define MISC_REG_SW_TIMER_CFG_5                                                                      0x008c34UL //Access:RW   DataWidth:0x6   SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 5 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_5.SW_TIMER_RELOAD_VAL_5 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 5 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).  Chips: BB_A0 BB_B0 K2
30257 #define MISC_REG_SW_TIMER_CFG_6                                                                      0x008c38UL //Access:RW   DataWidth:0x6   SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 6 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_6.SW_TIMER_RELOAD_VAL_6 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 6 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).  Chips: BB_A0 BB_B0 K2
30258 #define MISC_REG_SW_TIMER_CFG_7                                                                      0x008c3cUL //Access:RW   DataWidth:0x6   SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 7 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_7.SW_TIMER_RELOAD_VAL_7 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 7 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).  Chips: BB_A0 BB_B0 K2
30259 #define MISC_REG_SW_TIMER_CFG_8                                                                      0x008c40UL //Access:RW   DataWidth:0x6   SW timer 1 configuration register. Maped as follows: bit0=en (0-stop counting; 1-counting); bit1=reload (0-no reload; 1-when MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 8 reach zero the register will be reload with MISC_REGISTERS_SW_TIMER_RELOAD_VAL_8.SW_TIMER_RELOAD_VAL_8 )  ; bit2=attn (0-no attention; 1-attention signal will be send to the AEU when the MISC_REGISTERS_SW_TIMER_VAL.SW_TIMER_VAL of timer 8 reach zero); bit4-5=resolution (00-10us; 01-100us; 10-1ms; 11- 1us).  Chips: BB_A0 BB_B0 K2
30260 #define MISC_REG_SW_TIMER_RELOAD_VAL_1                                                               0x008c44UL //Access:RW   DataWidth:0x20  Reload value for counter 1 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_1 [1] ) is set.  Chips: BB_A0 BB_B0 K2
30261 #define MISC_REG_SW_TIMER_RELOAD_VAL_2                                                               0x008c48UL //Access:RW   DataWidth:0x20  Reload value for counter 2 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_2.SW_TIMER_CFG_2 [1]  ) is set.  Chips: BB_A0 BB_B0 K2
30262 #define MISC_REG_SW_TIMER_RELOAD_VAL_3                                                               0x008c4cUL //Access:RW   DataWidth:0x20  Reload value for counter 3 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_3.SW_TIMER_CFG_3 [1]  ) is set.  Chips: BB_A0 BB_B0 K2
30263 #define MISC_REG_SW_TIMER_RELOAD_VAL_4                                                               0x008c50UL //Access:RW   DataWidth:0x20  Reload value for counter 4 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_4.SW_TIMER_CFG_4 [1]  ) is set.  Chips: BB_A0 BB_B0 K2
30264 #define MISC_REG_SW_TIMER_RELOAD_VAL_5                                                               0x008c54UL //Access:RW   DataWidth:0x20  Reload value for counter 5 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_5 [1]  ) is set.  Chips: BB_A0 BB_B0 K2
30265 #define MISC_REG_SW_TIMER_RELOAD_VAL_6                                                               0x008c58UL //Access:RW   DataWidth:0x20  Reload value for counter 6 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_6 [1]  ) is set.  Chips: BB_A0 BB_B0 K2
30266 #define MISC_REG_SW_TIMER_RELOAD_VAL_7                                                               0x008c5cUL //Access:RW   DataWidth:0x20  Reload value for counter 1 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_7 [1] ) is set.  Chips: BB_A0 BB_B0 K2
30267 #define MISC_REG_SW_TIMER_RELOAD_VAL_8                                                               0x008c60UL //Access:RW   DataWidth:0x20  Reload value for counter 8 if reload; the value will be reload if the counter reached zero and the reload bit ( MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_8 [1] ) is set.  Chips: BB_A0 BB_B0 K2
30268 #define MISC_REG_SW_TIMER_EVENT_CLR                                                                  0x008c64UL //Access:W    DataWidth:0x8   Write one for the appropriate bit will clear the appropriate event to the AEU (if the attn bit (bit 2) in the MISC_REGISTERS_SW_TIMER_CFG_1.SW_TIMER_CFG_1 [2]; MISC_REGISTERS_SW_TIMER_CFG_2.SW_TIMER_CFG_2 [2]; MISC_REGISTERS_SW_TIMER_CFG_3.SW_TIMER_CFG_3 [2]; MISC_REGISTERS_SW_TIMER_CFG_4.SW_TIMER_CFG_4 [2]; MISC_REGISTERS_SW_TIMER_CFG_5.SW_TIMER_CFG_5 [2]; MISC_REGISTERS_SW_TIMER_CFG_6.SW_TIMER_CFG_6 [2]; MISC_REGISTERS_SW_TIMER_CFG_7.SW_TIMER_CFG_7 [2]; MISC_REGISTERS_SW_TIMER_CFG_8.SW_TIMER_CFG_8 [2] is set). [0] timer1; [1] timer2; [2] timer3; [3] timer4; [4] timer5; [5] timer6; [6] timer7; [7] timer8.  Chips: BB_A0 BB_B0 K2
30269 #define MISC_REG_SW_TIMER_EVENT                                                                      0x008c68UL //Access:R    DataWidth:0x8   The appropriate timer had reach to zero. [0] timer1; [1]timer2; [2] timer3; [3] timer4; [4] timer5; [5] timer6; [6] timer7; [7] timer8.  Chips: BB_A0 BB_B0 K2
30270 #define MISC_REG_SW_TIMER_10US_RESOLUTION                                                            0x008c6cUL //Access:RW   DataWidth:0xa   Fine tuning for sw 10us timer; max value=300; min value=200. the 10us timer is the base counter for all the timers.  Chips: BB_A0 BB_B0 K2
30271 #define MISC_REG_GEN_PURP_HW0                                                                        0x008c70UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by hard reset.  Chips: BB_A0 BB_B0 K2
30272 #define MISC_REG_GEN_PURP_HW1                                                                        0x008c74UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by hard reset.  Chips: BB_A0 BB_B0 K2
30273 #define MISC_REG_GEN_PURP_HW2                                                                        0x008c78UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by hard reset.  Chips: BB_A0 BB_B0 K2
30274 #define MISC_REG_GEN_PURP_HW3                                                                        0x008c7cUL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by hard reset.  Chips: BB_A0 BB_B0 K2
30275 #define MISC_REG_GEN_PURP_CR0                                                                        0x008c80UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by core reset.  Chips: BB_A0 BB_B0 K2
30276 #define MISC_REG_GEN_PURP_CR1                                                                        0x008c84UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by core reset.  Chips: BB_A0 BB_B0 K2
30277 #define MISC_REG_GEN_PURP_CR2                                                                        0x008c88UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by core reset.  Chips: BB_A0 BB_B0 K2
30278 #define MISC_REG_GEN_PURP_CR3                                                                        0x008c8cUL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by core reset.  Chips: BB_A0 BB_B0 K2
30279 #define MISC_REG_GEN_PURP_POR0                                                                       0x008c90UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by por reset.  Chips: BB_A0 BB_B0 K2
30280 #define MISC_REG_GEN_PURP_POR1                                                                       0x008c94UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by por reset.  Chips: BB_A0 BB_B0 K2
30281 #define MISC_REG_GEN_PURP_POR2                                                                       0x008c98UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by por reset.  Chips: BB_A0 BB_B0 K2
30282 #define MISC_REG_GEN_PURP_POR3                                                                       0x008c9cUL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by por reset.  Chips: BB_A0 BB_B0 K2
30283 #define MISC_REG_ECO_RESERVED                                                                        0x008ca0UL //Access:RW   DataWidth:0x20  Eco reserved. Global register.  Chips: BB_A0 BB_B0 K2
30284 #define MISC_REG_SW_TIMER_VAL                                                                        0x008d00UL //Access:RW   DataWidth:0x20  The value of the counter for sw timers1-8. there are 8 addresses in this register. address 0 - timer 1; address 1 - timer 2; etc ; address 7 - timer 8.  Chips: BB_A0 BB_B0 K2
30285 #define MISC_REG_SW_TIMER_VAL_SIZE                                                                   8
30286 #define MISCS_REG_RESET_CONFIG                                                                       0x009040UL //Access:RW   DataWidth:0x20  Reset configuration register. inside order of the bits is: [0] rst_ncsi_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [1] rst_umac_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [2] rst_mstat_on_core_rst (0- no auto deassertion; 1 - auto deassertion); [3] rst_cpmu_auto_mode (0- no auto deassertion; 1 - auto deassertion); [4] rst_pxpv_auto_mode (0- no auto deassertion; 1 - auto deassertion); [5] rst_nwm_mac_core_assert_on_core_rst (0 - no; 1 - yes); [6] reserved; [7] rst_mcp_n_reset_reg_hard_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [8] rst_mcp_n_hard_core_rst_b_auto_mode (0- no auto deassertion; 1 - auto deassertion); [9] rst_mcp_n_reset_cmn_cpu_auto_mode (0- no auto deassertion; 1 - auto deassertion); [10] rst_mcp_n_reset_cmn_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [11-13] reserved; [14] rst_misc_core_auto_mode (0- no auto deassertion; 1 - auto deassertion); [15] rst_dbue_auto_mode (0- no auto deassertion; 1 - auto deassertion); [16] grc_reset_assert_on_core_rst (0 - no; 1 - yes); [17] rst_mcp_n_reset_cmn_cpu_assert_on_core_rst (0 - no; 1 - yes); [18] rst_mcp_n_reset_cmn_core_assert_on_core_rst (0 - no; 1 - yes); [19] rst_rbc{n|h}_assert_on_core_rst (0 - no; 1 - yes); [20] rst_nwm_core_assert_on_core_rst (0 - no; 1 - yes); [21] rst_misc_core_assert_on_core_rst (0 - no; 1 - yes); [22] rst_dbue_assert_on_core_rst (0 - no; 1 - yes); [23] wrappers_iddq_and_rst_signals_assert_on_core_rst (0 - no; 1 - yes); [24] rst_rbcw_core_assert_on_core_rst (0 - no; 1 - yes); [25] rst_pglc_auto_mode (0- no auto deassertion; 1 - auto deassertion); [26] rst_bmb_on_core_rst (0- no reset on core reset; 1 - reset on core reset); [27] rst_opte_on_core_rst (0- no reset on core reset; 1 - reset on core reset); [28] rst_opcs_core_assert_on_core_rst (0 - no; 1 - yes); [29] rst_nws_core_assert_on_core_rst (0 - no; 1 - yes); [30] rst_ms_core_assert_on_core_rst (0 - no; 1 - yes); [31] rst_led_core_assert_on_core_rst (0 - no; 1 - yes) Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30287 #define MISCS_REG_RESET_CONFIG_POR                                                                   0x009044UL //Access:RW   DataWidth:0x4   Reset configuration register. inside order of the bits is: [0] rst_n_reg_hard_misc_rbc_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [1] rst_n_hard_misc_rbc_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [2] rst_n_hard_misc_erstclk_pcie (0 - is not reset on hard reset; 1 - is reset on hard reset); [3] reserved; Reset on POR reset.  Chips: BB_A0 BB_B0 K2
30288 #define MISCS_REG_RESET_PL_UA                                                                        0x009050UL //Access:RW   DataWidth:0x20  Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_cgrc; [1] rst_mcp_n_reset_reg_hard_core; [2] rst_mcp_n_hard_core_rst_b; [3] rst_mcp_n_reset_cmn_cpu; [4] rst_mcp_n_reset_cmn_core; [5] rst_misc_core; [6] rst_dbue (UART); [7] rst_bmb; [8] rst_ipc; [9]rst_crbcn; [10] reserved; [11] rst_avs; [31-10] reserved; Global register.  Chips: BB_A0 BB_B0 K2
30289 #define MISCS_REG_RESET_PL_UA_SIZE                                                                   3
30290 #define MISCS_REG_RESET_PL_HV                                                                        0x009060UL //Access:RW   DataWidth:0x20  Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_cnig; [1] rst_pglc; [2] rst_pxpv; [3] rst_crbch; [4] rst_opte; [5] rst_ncsi; [6] rst_umac; [7] rst_mstat; [8] rst_cpmu; [9] reserved; [10] rst_rbcw; [11] rst_opcs; [12] rst_nws; [13] rst_ms;  [14] rst_led; [31:15] reserved; Global register.  Chips: BB_A0 BB_B0 K2
30291 #define MISCS_REG_RESET_PL_HV_SIZE                                                                   3
30292 #define MISCS_REG_CLK_100G_MODE                                                                      0x009070UL //Access:RW   DataWidth:0x1   This register indicates if clk_nw frequency is faster than main clock frequency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. In AH it control SYNC FIFOs in the BMB.  Chips: BB_A0 BB_B0 K2
30293 #define MISCS_REG_BLOCK_256B_EN                                                                      0x009074UL //Access:RW   DataWidth:0x1   This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset.  Chips: BB_A0 BB_B0 K2
30294 #define MISCS_REG_MFW_SECURITY_MODE                                                                  0x009078UL //Access:RW   DataWidth:0x3   Determines the MFW security mode. [0] - source of privilege level, 0 - the source is external pin, 1 - the source are bits[2:1] of this register. [2:1] - privilege level to override that defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - fully-secured mode.  Chips: BB_A0 BB_B0 K2
30295 #define MISCS_REG_MFW_SECURITY_MODE_IO                                                               0x00907cUL //Access:R    DataWidth:0x2   Privilege level as defined by external pin. 0 - non-secured mode; 1 - secured mode; 2 - fully-secured mode.  Chips: BB_A0 BB_B0 K2
30296 #define MISCS_REG_NVM_WR_EN                                                                          0x009080UL //Access:RW   DataWidth:0x2   These bits control how the write-disable to the NVM block is generated. '0' - PROTECT: This value protects the NVM from any writes. '1' - PCI: This value allows writes only when PCI\_RST\ is high.' 2' - ALLOW: This value allows writes to the NVM using normal NVM commands. '3' - ALLOW2: This value allows writes to the NVM using normal NVM commands.  Chips: BB_A0 BB_B0 K2
30297 #define MISCS_REG_DRIVER_CONTROL_0                                                                   0x009088UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30298 #define MISCS_REG_DRIVER_CONTROL_0_SIZE                                                              2
30299 #define MISCS_REG_DRIVER_CONTROL_1                                                                   0x009090UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30300 #define MISCS_REG_DRIVER_CONTROL_1_SIZE                                                              2
30301 #define MISCS_REG_DRIVER_CONTROL_2                                                                   0x009098UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30302 #define MISCS_REG_DRIVER_CONTROL_2_SIZE                                                              2
30303 #define MISCS_REG_DRIVER_CONTROL_3                                                                   0x0090a0UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30304 #define MISCS_REG_DRIVER_CONTROL_3_SIZE                                                              2
30305 #define MISCS_REG_DRIVER_CONTROL_4                                                                   0x0090a8UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30306 #define MISCS_REG_DRIVER_CONTROL_4_SIZE                                                              2
30307 #define MISCS_REG_DRIVER_CONTROL_5                                                                   0x0090b0UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30308 #define MISCS_REG_DRIVER_CONTROL_5_SIZE                                                              2
30309 #define MISCS_REG_DRIVER_CONTROL_6                                                                   0x0090b8UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30310 #define MISCS_REG_DRIVER_CONTROL_6_SIZE                                                              2
30311 #define MISCS_REG_DRIVER_CONTROL_7                                                                   0x0090c0UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30312 #define MISCS_REG_DRIVER_CONTROL_7_SIZE                                                              2
30313 #define MISCS_REG_DRIVER_CONTROL_8                                                                   0x0090c8UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30314 #define MISCS_REG_DRIVER_CONTROL_8_SIZE                                                              2
30315 #define MISCS_REG_DRIVER_CONTROL_9                                                                   0x0090d0UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30316 #define MISCS_REG_DRIVER_CONTROL_9_SIZE                                                              2
30317 #define MISCS_REG_DRIVER_CONTROL_10                                                                  0x0090d8UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30318 #define MISCS_REG_DRIVER_CONTROL_10_SIZE                                                             2
30319 #define MISCS_REG_DRIVER_CONTROL_11                                                                  0x0090e0UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30320 #define MISCS_REG_DRIVER_CONTROL_11_SIZE                                                             2
30321 #define MISCS_REG_DRIVER_CONTROL_12                                                                  0x0090e8UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30322 #define MISCS_REG_DRIVER_CONTROL_12_SIZE                                                             2
30323 #define MISCS_REG_DRIVER_CONTROL_13                                                                  0x0090f0UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30324 #define MISCS_REG_DRIVER_CONTROL_13_SIZE                                                             2
30325 #define MISCS_REG_DRIVER_CONTROL_14                                                                  0x0090f8UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30326 #define MISCS_REG_DRIVER_CONTROL_14_SIZE                                                             2
30327 #define MISCS_REG_DRIVER_CONTROL_15                                                                  0x009100UL //Access:RW   DataWidth:0x20  These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: BB_A0 BB_B0 K2
30328 #define MISCS_REG_DRIVER_CONTROL_15_SIZE                                                             2
30329 #define MISCS_REG_DRIVER_K2_CONTROL_0                                                                0x009108UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30330 #define MISCS_REG_DRIVER_K2_CONTROL_0_SIZE                                                           2
30331 #define MISCS_REG_DRIVER_K2_CONTROL_1                                                                0x009110UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30332 #define MISCS_REG_DRIVER_K2_CONTROL_1_SIZE                                                           2
30333 #define MISCS_REG_DRIVER_K2_CONTROL_2                                                                0x009118UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30334 #define MISCS_REG_DRIVER_K2_CONTROL_2_SIZE                                                           2
30335 #define MISCS_REG_DRIVER_K2_CONTROL_3                                                                0x009120UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30336 #define MISCS_REG_DRIVER_K2_CONTROL_3_SIZE                                                           2
30337 #define MISCS_REG_DRIVER_K2_CONTROL_4                                                                0x009128UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30338 #define MISCS_REG_DRIVER_K2_CONTROL_4_SIZE                                                           2
30339 #define MISCS_REG_DRIVER_K2_CONTROL_5                                                                0x009130UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30340 #define MISCS_REG_DRIVER_K2_CONTROL_5_SIZE                                                           2
30341 #define MISCS_REG_DRIVER_K2_CONTROL_6                                                                0x009138UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30342 #define MISCS_REG_DRIVER_K2_CONTROL_6_SIZE                                                           2
30343 #define MISCS_REG_DRIVER_K2_CONTROL_7                                                                0x009140UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30344 #define MISCS_REG_DRIVER_K2_CONTROL_7_SIZE                                                           2
30345 #define MISCS_REG_RESET_PL_HV_2                                                                      0x009150UL //Access:RW   DataWidth:0x20  Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0"  resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0"  doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nwm; [1] rst_nwm_mac0; [2] rst_nwm_mac1; [3] rst_nwm_mac2; [4] rst_nwm_mac3; [5] rst_nwm_gpcs0; [6] rst_nwm_gpcs1; [7] rst_nwm_gpcs2; [8] rst_nwm_gpcs3; [9] rst_nwm_xpcs0; [10] rst_nwm_xpcs1; [11] rst_nwm_xpcs2; [12] rst_nwm_xpcs3; [13] rst_nwm_xpcs4; [14] rst_nwm_xpcs5; [15] rst_nwm_xpcs6; [16] rst_nwm_xpcs7;  [17] rst_nwm_tx_lane0; [18] rst_nwm_tx_lane1; [19] rst_nwm_tx_lane2; [20] rst_nwm_tx_lane3; [21] rst_nwm_rx_lane0; [22] rst_nwm_rx_lane1; [23] rst_nwm_rx_lane2; [24] rst_nwm_rx_lane3; [25] rst_nwm_sdgb; [31:26] reserved; Global register.  Chips: K2
30346 #define MISCS_REG_RESET_PL_HV_2_SIZE                                                                 3
30347 #define MISCS_REG_MEMCTRL_WR_RD_N                                                                    0x009160UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
30348 #define MISCS_REG_MEMCTRL_CMD                                                                        0x009164UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
30349 #define MISCS_REG_MEMCTRL_ADDRESS                                                                    0x009168UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
30350 #define MISCS_REG_MEMCTRL_STATUS                                                                     0x00916cUL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0 K2
30351 #define MISCS_REG_BSC_SMBIO_ENABLE_GLITCH_FILTER                                                     0x009170UL //Access:RW   DataWidth:0x1   When set enables the deglitching circuit for the SMBus inputs per I2C requirement.  Chips: K2
30352 #define MISCS_REG_INT_STS_0                                                                          0x009180UL //Access:R    DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30353     #define MISCS_REG_INT_STS_0_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
30354     #define MISCS_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                  0
30355     #define MISCS_REG_INT_STS_0_GENERIC_SW                                                           (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
30356     #define MISCS_REG_INT_STS_0_GENERIC_SW_SHIFT                                                     1
30357     #define MISCS_REG_INT_STS_0_CNIG_INTERRUPT                                                       (0x1<<2) // CNIG HW interrupt.
30358     #define MISCS_REG_INT_STS_0_CNIG_INTERRUPT_SHIFT                                                 2
30359 #define MISCS_REG_INT_MASK_0                                                                         0x009184UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30360     #define MISCS_REG_INT_MASK_0_ADDRESS_ERROR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.ADDRESS_ERROR .
30361     #define MISCS_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                 0
30362     #define MISCS_REG_INT_MASK_0_GENERIC_SW                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.GENERIC_SW .
30363     #define MISCS_REG_INT_MASK_0_GENERIC_SW_SHIFT                                                    1
30364     #define MISCS_REG_INT_MASK_0_CNIG_INTERRUPT                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_0.CNIG_INTERRUPT .
30365     #define MISCS_REG_INT_MASK_0_CNIG_INTERRUPT_SHIFT                                                2
30366 #define MISCS_REG_INT_STS_WR_0                                                                       0x009188UL //Access:WR   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30367     #define MISCS_REG_INT_STS_WR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
30368     #define MISCS_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                               0
30369     #define MISCS_REG_INT_STS_WR_0_GENERIC_SW                                                        (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
30370     #define MISCS_REG_INT_STS_WR_0_GENERIC_SW_SHIFT                                                  1
30371     #define MISCS_REG_INT_STS_WR_0_CNIG_INTERRUPT                                                    (0x1<<2) // CNIG HW interrupt.
30372     #define MISCS_REG_INT_STS_WR_0_CNIG_INTERRUPT_SHIFT                                              2
30373 #define MISCS_REG_INT_STS_CLR_0                                                                      0x00918cUL //Access:RC   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30374     #define MISCS_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                    (0x1<<0) // Signals an unknown address to the rf module.
30375     #define MISCS_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                              0
30376     #define MISCS_REG_INT_STS_CLR_0_GENERIC_SW                                                       (0x1<<1) // Generic sw overrule; request from an occupied source or free to an unoccupied source.
30377     #define MISCS_REG_INT_STS_CLR_0_GENERIC_SW_SHIFT                                                 1
30378     #define MISCS_REG_INT_STS_CLR_0_CNIG_INTERRUPT                                                   (0x1<<2) // CNIG HW interrupt.
30379     #define MISCS_REG_INT_STS_CLR_0_CNIG_INTERRUPT_SHIFT                                             2
30380 #define MISCS_REG_INT_STS_1                                                                          0x009190UL //Access:R    DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0
30381     #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG1                                              (0x1<<0) // DORQ FIFO error interrupt for engine 1
30382     #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG1_SHIFT                                        0
30383     #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG0                                              (0x1<<1) // DORQ FIFO error interrupt for engine 0
30384     #define MISCS_REG_INT_STS_1_OPTE_DORQ_FIFO_ERR_ENG0_SHIFT                                        1
30385     #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG1                                               (0x1<<2) // DBG FIFO error interrupt for engine 1
30386     #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG1_SHIFT                                         2
30387     #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG0                                               (0x1<<3) // DBG FIFO error interrupt for engine 0
30388     #define MISCS_REG_INT_STS_1_OPTE_DBG_FIFO_ERR_ENG0_SHIFT                                         3
30389     #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG1                                           (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
30390     #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_SHIFT                                     4
30391     #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG0                                           (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
30392     #define MISCS_REG_INT_STS_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_SHIFT                                     5
30393     #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG1                                           (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
30394     #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_SHIFT                                     6
30395     #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG0                                           (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
30396     #define MISCS_REG_INT_STS_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_SHIFT                                     7
30397     #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG1                                           (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
30398     #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_SHIFT                                     8
30399     #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG0                                           (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
30400     #define MISCS_REG_INT_STS_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_SHIFT                                     9
30401     #define MISCS_REG_INT_STS_1_OPTE_STORM_FIFO_ERR_ENG0                                             (0x1<<10) // STORM FIFO error interrupt
30402     #define MISCS_REG_INT_STS_1_OPTE_STORM_FIFO_ERR_ENG0_SHIFT                                       10
30403 #define MISCS_REG_INT_MASK_1                                                                         0x009194UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0
30404     #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG1                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DORQ_FIFO_ERR_ENG1 .
30405     #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG1_SHIFT                                       0
30406     #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG0                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DORQ_FIFO_ERR_ENG0 .
30407     #define MISCS_REG_INT_MASK_1_OPTE_DORQ_FIFO_ERR_ENG0_SHIFT                                       1
30408     #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG1                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DBG_FIFO_ERR_ENG1 .
30409     #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG1_SHIFT                                        2
30410     #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG0                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_DBG_FIFO_ERR_ENG0 .
30411     #define MISCS_REG_INT_MASK_1_OPTE_DBG_FIFO_ERR_ENG0_SHIFT                                        3
30412     #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG1                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF1_FIFO_ERR_ENG1 .
30413     #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_SHIFT                                    4
30414     #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG0                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF1_FIFO_ERR_ENG0 .
30415     #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_SHIFT                                    5
30416     #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG1                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF0_FIFO_ERR_ENG1 .
30417     #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_SHIFT                                    6
30418     #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG0                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_IF0_FIFO_ERR_ENG0 .
30419     #define MISCS_REG_INT_MASK_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_SHIFT                                    7
30420     #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG1                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_SOP_FIFO_ERR_ENG1 .
30421     #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_SHIFT                                    8
30422     #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG0                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_BTB_SOP_FIFO_ERR_ENG0 .
30423     #define MISCS_REG_INT_MASK_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_SHIFT                                    9
30424     #define MISCS_REG_INT_MASK_1_OPTE_STORM_FIFO_ERR_ENG0                                            (0x1<<10) // This bit masks, when set, the Interrupt bit: MISCS_REG_INT_STS_1.OPTE_STORM_FIFO_ERR_ENG0 .
30425     #define MISCS_REG_INT_MASK_1_OPTE_STORM_FIFO_ERR_ENG0_SHIFT                                      10
30426 #define MISCS_REG_INT_STS_WR_1                                                                       0x009198UL //Access:WR   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0
30427     #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG1                                           (0x1<<0) // DORQ FIFO error interrupt for engine 1
30428     #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG1_SHIFT                                     0
30429     #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG0                                           (0x1<<1) // DORQ FIFO error interrupt for engine 0
30430     #define MISCS_REG_INT_STS_WR_1_OPTE_DORQ_FIFO_ERR_ENG0_SHIFT                                     1
30431     #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG1                                            (0x1<<2) // DBG FIFO error interrupt for engine 1
30432     #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG1_SHIFT                                      2
30433     #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG0                                            (0x1<<3) // DBG FIFO error interrupt for engine 0
30434     #define MISCS_REG_INT_STS_WR_1_OPTE_DBG_FIFO_ERR_ENG0_SHIFT                                      3
30435     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1                                        (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
30436     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_SHIFT                                  4
30437     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0                                        (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
30438     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_SHIFT                                  5
30439     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1                                        (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
30440     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_SHIFT                                  6
30441     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0                                        (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
30442     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_SHIFT                                  7
30443     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1                                        (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
30444     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_SHIFT                                  8
30445     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0                                        (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
30446     #define MISCS_REG_INT_STS_WR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_SHIFT                                  9
30447     #define MISCS_REG_INT_STS_WR_1_OPTE_STORM_FIFO_ERR_ENG0                                          (0x1<<10) // STORM FIFO error interrupt
30448     #define MISCS_REG_INT_STS_WR_1_OPTE_STORM_FIFO_ERR_ENG0_SHIFT                                    10
30449 #define MISCS_REG_INT_STS_CLR_1                                                                      0x00919cUL //Access:RC   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0
30450     #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG1                                          (0x1<<0) // DORQ FIFO error interrupt for engine 1
30451     #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG1_SHIFT                                    0
30452     #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG0                                          (0x1<<1) // DORQ FIFO error interrupt for engine 0
30453     #define MISCS_REG_INT_STS_CLR_1_OPTE_DORQ_FIFO_ERR_ENG0_SHIFT                                    1
30454     #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG1                                           (0x1<<2) // DBG FIFO error interrupt for engine 1
30455     #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG1_SHIFT                                     2
30456     #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG0                                           (0x1<<3) // DBG FIFO error interrupt for engine 0
30457     #define MISCS_REG_INT_STS_CLR_1_OPTE_DBG_FIFO_ERR_ENG0_SHIFT                                     3
30458     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1                                       (0x1<<4) // BTB_IF1 FIFO error interrupt for engine 1
30459     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG1_SHIFT                                 4
30460     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0                                       (0x1<<5) // BTB_IF1 FIFO error interrupt for engine 0
30461     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF1_FIFO_ERR_ENG0_SHIFT                                 5
30462     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1                                       (0x1<<6) // BTB_IF0 FIFO error interrupt for engine 1
30463     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG1_SHIFT                                 6
30464     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0                                       (0x1<<7) // BTB_IF0 FIFO error interrupt for engine 0
30465     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_IF0_FIFO_ERR_ENG0_SHIFT                                 7
30466     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1                                       (0x1<<8) // BTB_SOP FIFO error interrupt for engine 1
30467     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG1_SHIFT                                 8
30468     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0                                       (0x1<<9) // BTB_SOP FIFO error interrupt for engine 0
30469     #define MISCS_REG_INT_STS_CLR_1_OPTE_BTB_SOP_FIFO_ERR_ENG0_SHIFT                                 9
30470     #define MISCS_REG_INT_STS_CLR_1_OPTE_STORM_FIFO_ERR_ENG0                                         (0x1<<10) // STORM FIFO error interrupt
30471     #define MISCS_REG_INT_STS_CLR_1_OPTE_STORM_FIFO_ERR_ENG0_SHIFT                                   10
30472 #define MISCS_REG_PRTY_MASK_0                                                                        0x0091a4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
30473     #define MISCS_REG_PRTY_MASK_0_CNIG_PARITY                                                        (0x1<<0) // This bit masks, when set, the Parity bit: MISCS_REG_PRTY_STS_0.CNIG_PARITY .
30474     #define MISCS_REG_PRTY_MASK_0_CNIG_PARITY_SHIFT                                                  0
30475 #define MISCS_REG_PCIE_LINK_UP_STATE                                                                 0x0093c0UL //Access:R    DataWidth:0x1   Indicates the current state of the ptw_miscs_pcie_link_up signal which is driven by the PCIE core - a pulse at the beginning of PCIe link up.  Chips: K2
30476 #define MISCS_REG_PCIE_HOT_RESET_STATE                                                               0x0093c4UL //Access:R    DataWidth:0x1   Indicates the current state of the ptw_miscs_pcie_hot_reset signal which is driven by the PCIE core - a pulse at the beginning of PCIe hot reset.  Chips: K2
30477 #define MISCS_REG_HOT_RESET_PREPARED_CNT                                                             0x0093c8UL //Access:RW   DataWidth:0x10  Accounts for HOT RESET assertion when the chip is in prepared state. Is reset on POR reset.  Chips: K2
30478 #define MISCS_REG_HOT_RESET_UNPREPARED_CNT                                                           0x0093ccUL //Access:RW   DataWidth:0x10  Accounts for HOT RESET assertion when the chip is in un-prepared state. Is reset on POR reset.  Chips: K2
30479 #define MISCS_REG_PCIE_LINK_UP_CNT                                                                   0x0093d0UL //Access:RW   DataWidth:0x10  Accounts for PCIE LINK UP assertion. Is reset on POR reset.  Chips: K2
30480 #define MISCS_REG_MAIN_PLL_STATUS                                                                    0x0093d4UL //Access:RW   DataWidth:0x1   Set to 1 when main PLL lock indication is de-asserted when hard reset is de-asserted. Reset to 0 by FW. Is reset on POR reset.  Chips: K2
30481 #define MISCS_REG_GPIO0_DRIVER                                                                       0x009400UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO0. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30482 #define MISCS_REG_GPIO1_DRIVER                                                                       0x009404UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO1. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30483 #define MISCS_REG_GPIO2_DRIVER                                                                       0x009408UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO2. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30484 #define MISCS_REG_GPIO3_DRIVER                                                                       0x00940cUL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO3. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30485 #define MISCS_REG_GPIO4_DRIVER                                                                       0x009410UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO4. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30486 #define MISCS_REG_GPIO5_DRIVER                                                                       0x009414UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO5. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30487 #define MISCS_REG_GPIO6_DRIVER                                                                       0x009418UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO6. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30488 #define MISCS_REG_GPIO7_DRIVER                                                                       0x00941cUL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO7. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30489 #define MISCS_REG_GPIO8_DRIVER                                                                       0x009420UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO8. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30490 #define MISCS_REG_GPIO9_DRIVER                                                                       0x009424UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO9. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30491 #define MISCS_REG_GPIO10_DRIVER                                                                      0x009428UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO10. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30492 #define MISCS_REG_GPIO11_DRIVER                                                                      0x00942cUL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO11. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30493 #define MISCS_REG_GPIO12_DRIVER                                                                      0x009430UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO12. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30494 #define MISCS_REG_GPIO13_DRIVER                                                                      0x009434UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO13. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30495 #define MISCS_REG_GPIO14_DRIVER                                                                      0x009438UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO14. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30496 #define MISCS_REG_GPIO15_DRIVER                                                                      0x00943cUL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO15. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30497 #define MISCS_REG_GPIO16_DRIVER                                                                      0x009440UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO16. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30498 #define MISCS_REG_GPIO17_DRIVER                                                                      0x009444UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO17. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30499 #define MISCS_REG_GPIO18_DRIVER                                                                      0x009448UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO18. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30500 #define MISCS_REG_GPIO19_DRIVER                                                                      0x00944cUL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO19. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30501 #define MISCS_REG_GPIO20_DRIVER                                                                      0x009450UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO20. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30502 #define MISCS_REG_GPIO21_DRIVER                                                                      0x009454UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO21. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30503 #define MISCS_REG_GPIO22_DRIVER                                                                      0x009458UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO22. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30504 #define MISCS_REG_GPIO23_DRIVER                                                                      0x00945cUL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO23. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30505 #define MISCS_REG_GPIO24_DRIVER                                                                      0x009460UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO24. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30506 #define MISCS_REG_GPIO25_DRIVER                                                                      0x009464UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO25. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30507 #define MISCS_REG_GPIO26_DRIVER                                                                      0x009468UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO26. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30508 #define MISCS_REG_GPIO27_DRIVER                                                                      0x00946cUL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO27. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30509 #define MISCS_REG_GPIO28_DRIVER                                                                      0x009470UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO28. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30510 #define MISCS_REG_GPIO29_DRIVER                                                                      0x009474UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO29. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30511 #define MISCS_REG_GPIO30_DRIVER                                                                      0x009478UL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO30. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30512 #define MISCS_REG_GPIO31_DRIVER                                                                      0x00947cUL //Access:RW   DataWidth:0x2   Defines what is the driver of GPIO31. 0 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 0; 1 - GPIO output is driven by per-path output control (gpio_set_path/gpio_clr_path) path 1; 3 - GPIO output is driven by shared output control (gpio_set_shared/gpio_clr_shared);  Chips: BB_A0 BB_B0 K2
30513 #define MISCS_REG_GPIO_FLOAT                                                                         0x009480UL //Access:RW   DataWidth:0x20  FLOAT: When any of these bits is written as a '1'; the corresponding GPIO bit will turn off it's drivers and become an input. This is the reset state of all GPIO pins.  Chips: BB_A0 BB_B0 K2
30514 #define MISCS_REG_GPIO0_CTRL_SHARED                                                                  0x009484UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30515 #define MISCS_REG_GPIO1_CTRL_SHARED                                                                  0x009488UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30516 #define MISCS_REG_GPIO2_CTRL_SHARED                                                                  0x00948cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30517 #define MISCS_REG_GPIO3_CTRL_SHARED                                                                  0x009490UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30518 #define MISCS_REG_GPIO4_CTRL_SHARED                                                                  0x009494UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30519 #define MISCS_REG_GPIO5_CTRL_SHARED                                                                  0x009498UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30520 #define MISCS_REG_GPIO6_CTRL_SHARED                                                                  0x00949cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30521 #define MISCS_REG_GPIO7_CTRL_SHARED                                                                  0x0094a0UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30522 #define MISCS_REG_GPIO8_CTRL_SHARED                                                                  0x0094a4UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30523 #define MISCS_REG_GPIO9_CTRL_SHARED                                                                  0x0094a8UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30524 #define MISCS_REG_GPIO10_CTRL_SHARED                                                                 0x0094acUL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30525 #define MISCS_REG_GPIO11_CTRL_SHARED                                                                 0x0094b0UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30526 #define MISCS_REG_GPIO12_CTRL_SHARED                                                                 0x0094b4UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30527 #define MISCS_REG_GPIO13_CTRL_SHARED                                                                 0x0094b8UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30528 #define MISCS_REG_GPIO14_CTRL_SHARED                                                                 0x0094bcUL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30529 #define MISCS_REG_GPIO15_CTRL_SHARED                                                                 0x0094c0UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30530 #define MISCS_REG_GPIO16_CTRL_SHARED                                                                 0x0094c4UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30531 #define MISCS_REG_GPIO17_CTRL_SHARED                                                                 0x0094c8UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30532 #define MISCS_REG_GPIO18_CTRL_SHARED                                                                 0x0094ccUL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30533 #define MISCS_REG_GPIO19_CTRL_SHARED                                                                 0x0094d0UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30534 #define MISCS_REG_GPIO20_CTRL_SHARED                                                                 0x0094d4UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30535 #define MISCS_REG_GPIO21_CTRL_SHARED                                                                 0x0094d8UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30536 #define MISCS_REG_GPIO22_CTRL_SHARED                                                                 0x0094dcUL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30537 #define MISCS_REG_GPIO23_CTRL_SHARED                                                                 0x0094e0UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30538 #define MISCS_REG_GPIO24_CTRL_SHARED                                                                 0x0094e4UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30539 #define MISCS_REG_GPIO25_CTRL_SHARED                                                                 0x0094e8UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30540 #define MISCS_REG_GPIO26_CTRL_SHARED                                                                 0x0094ecUL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30541 #define MISCS_REG_GPIO27_CTRL_SHARED                                                                 0x0094f0UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30542 #define MISCS_REG_GPIO28_CTRL_SHARED                                                                 0x0094f4UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30543 #define MISCS_REG_GPIO29_CTRL_SHARED                                                                 0x0094f8UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30544 #define MISCS_REG_GPIO30_CTRL_SHARED                                                                 0x0094fcUL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30545 #define MISCS_REG_GPIO31_CTRL_SHARED                                                                 0x009500UL //Access:RW   DataWidth:0x2   GPIO SET/CLR shared: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is shared as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30546 #define MISCS_REG_GPIO0_CTRL_PATH                                                                    0x009504UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30547 #define MISCS_REG_GPIO1_CTRL_PATH                                                                    0x009508UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30548 #define MISCS_REG_GPIO2_CTRL_PATH                                                                    0x00950cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30549 #define MISCS_REG_GPIO3_CTRL_PATH                                                                    0x009510UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30550 #define MISCS_REG_GPIO4_CTRL_PATH                                                                    0x009514UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30551 #define MISCS_REG_GPIO5_CTRL_PATH                                                                    0x009518UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30552 #define MISCS_REG_GPIO6_CTRL_PATH                                                                    0x00951cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30553 #define MISCS_REG_GPIO7_CTRL_PATH                                                                    0x009520UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30554 #define MISCS_REG_GPIO8_CTRL_PATH                                                                    0x009524UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30555 #define MISCS_REG_GPIO9_CTRL_PATH                                                                    0x009528UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30556 #define MISCS_REG_GPIO10_CTRL_PATH                                                                   0x00952cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30557 #define MISCS_REG_GPIO11_CTRL_PATH                                                                   0x009530UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30558 #define MISCS_REG_GPIO12_CTRL_PATH                                                                   0x009534UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30559 #define MISCS_REG_GPIO13_CTRL_PATH                                                                   0x009538UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30560 #define MISCS_REG_GPIO14_CTRL_PATH                                                                   0x00953cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30561 #define MISCS_REG_GPIO15_CTRL_PATH                                                                   0x009540UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30562 #define MISCS_REG_GPIO16_CTRL_PATH                                                                   0x009544UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30563 #define MISCS_REG_GPIO17_CTRL_PATH                                                                   0x009548UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30564 #define MISCS_REG_GPIO18_CTRL_PATH                                                                   0x00954cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30565 #define MISCS_REG_GPIO19_CTRL_PATH                                                                   0x009550UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30566 #define MISCS_REG_GPIO20_CTRL_PATH                                                                   0x009554UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30567 #define MISCS_REG_GPIO21_CTRL_PATH                                                                   0x009558UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30568 #define MISCS_REG_GPIO22_CTRL_PATH                                                                   0x00955cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30569 #define MISCS_REG_GPIO23_CTRL_PATH                                                                   0x009560UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30570 #define MISCS_REG_GPIO24_CTRL_PATH                                                                   0x009564UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30571 #define MISCS_REG_GPIO25_CTRL_PATH                                                                   0x009568UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30572 #define MISCS_REG_GPIO26_CTRL_PATH                                                                   0x00956cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30573 #define MISCS_REG_GPIO27_CTRL_PATH                                                                   0x009570UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30574 #define MISCS_REG_GPIO28_CTRL_PATH                                                                   0x009574UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30575 #define MISCS_REG_GPIO29_CTRL_PATH                                                                   0x009578UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30576 #define MISCS_REG_GPIO30_CTRL_PATH                                                                   0x00957cUL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30577 #define MISCS_REG_GPIO31_CTRL_PATH                                                                   0x009580UL //Access:RW   DataWidth:0x2   GPIO SET/CLR path: SET: bit[0]: When this bit is written as '1', the corresponding GPIO bit will drive high (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was SET. CLR: bit[1]: When this bit is written as '1', the corresponding GPIO bit will drive low (if corresponding gpio_float is set and the driver is path as set by gpio_driver). The read value of this bit will be '1' if the last command ( CLR ; SET ) for this bit was CLR.  Chips: BB_A0 BB_B0 K2
30578 #define MISCS_REG_GPIO_VAL                                                                           0x009584UL //Access:R    DataWidth:0x20  These bits indicate the read value of each of the 32 GPIO pins. This is the result value of the pin; not the drive value.  Chips: BB_A0 BB_B0 K2
30579 #define MISCS_REG_GPIO0_INT                                                                          0x009588UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30580 #define MISCS_REG_GPIO1_INT                                                                          0x00958cUL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30581 #define MISCS_REG_GPIO2_INT                                                                          0x009590UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30582 #define MISCS_REG_GPIO3_INT                                                                          0x009594UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30583 #define MISCS_REG_GPIO4_INT                                                                          0x009598UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30584 #define MISCS_REG_GPIO5_INT                                                                          0x00959cUL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30585 #define MISCS_REG_GPIO6_INT                                                                          0x0095a0UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30586 #define MISCS_REG_GPIO7_INT                                                                          0x0095a4UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30587 #define MISCS_REG_GPIO8_INT                                                                          0x0095a8UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30588 #define MISCS_REG_GPIO9_INT                                                                          0x0095acUL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30589 #define MISCS_REG_GPIO10_INT                                                                         0x0095b0UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30590 #define MISCS_REG_GPIO11_INT                                                                         0x0095b4UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30591 #define MISCS_REG_GPIO12_INT                                                                         0x0095b8UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30592 #define MISCS_REG_GPIO13_INT                                                                         0x0095bcUL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30593 #define MISCS_REG_GPIO14_INT                                                                         0x0095c0UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30594 #define MISCS_REG_GPIO15_INT                                                                         0x0095c4UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30595 #define MISCS_REG_GPIO16_INT                                                                         0x0095c8UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30596 #define MISCS_REG_GPIO17_INT                                                                         0x0095ccUL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30597 #define MISCS_REG_GPIO18_INT                                                                         0x0095d0UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30598 #define MISCS_REG_GPIO19_INT                                                                         0x0095d4UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30599 #define MISCS_REG_GPIO20_INT                                                                         0x0095d8UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30600 #define MISCS_REG_GPIO21_INT                                                                         0x0095dcUL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30601 #define MISCS_REG_GPIO22_INT                                                                         0x0095e0UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30602 #define MISCS_REG_GPIO23_INT                                                                         0x0095e4UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30603 #define MISCS_REG_GPIO24_INT                                                                         0x0095e8UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30604 #define MISCS_REG_GPIO25_INT                                                                         0x0095ecUL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30605 #define MISCS_REG_GPIO26_INT                                                                         0x0095f0UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30606 #define MISCS_REG_GPIO27_INT                                                                         0x0095f4UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30607 #define MISCS_REG_GPIO28_INT                                                                         0x0095f8UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30608 #define MISCS_REG_GPIO29_INT                                                                         0x0095fcUL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30609 #define MISCS_REG_GPIO30_INT                                                                         0x009600UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30610 #define MISCS_REG_GPIO31_INT                                                                         0x009604UL //Access:RW   DataWidth:0x4   GPIO INT. [3] OLD_CLR; Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding GPIO input (reset value 0). [2]  OLD_SET; Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding GPIO input (reset value 0). [1] OLD_VALUE; RO; This bit indicate the old value of the GPIO input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [0]  INT_STATE; These bits indicate the current GPIO interrupt state for each GPIO pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the GPIO input does not match the current value in OLD_VALUE (reset value 0).  Chips: BB_A0 BB_B0 K2
30611 #define MISCS_REG_GPIO_EVENT_EN                                                                      0x009608UL //Access:RW   DataWidth:0x20  These bits enable the GPIO_INTs to signals event to the IGU/MCP for GPIO0..31.  Chips: BB_A0 BB_B0 K2
30612 #define MISCS_REG_DRIVER_K2_CONTROL_8                                                                0x009610UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30613 #define MISCS_REG_DRIVER_K2_CONTROL_8_SIZE                                                           2
30614 #define MISCS_REG_DRIVER_K2_CONTROL_9                                                                0x009618UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30615 #define MISCS_REG_DRIVER_K2_CONTROL_9_SIZE                                                           2
30616 #define MISCS_REG_DRIVER_K2_CONTROL_10                                                               0x009620UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30617 #define MISCS_REG_DRIVER_K2_CONTROL_10_SIZE                                                          2
30618 #define MISCS_REG_DRIVER_K2_CONTROL_11                                                               0x009628UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30619 #define MISCS_REG_DRIVER_K2_CONTROL_11_SIZE                                                          2
30620 #define MISCS_REG_DRIVER_K2_CONTROL_12                                                               0x009630UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30621 #define MISCS_REG_DRIVER_K2_CONTROL_12_SIZE                                                          2
30622 #define MISCS_REG_DRIVER_K2_CONTROL_13                                                               0x009638UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30623 #define MISCS_REG_DRIVER_K2_CONTROL_13_SIZE                                                          2
30624 #define MISCS_REG_DRIVER_K2_CONTROL_14                                                               0x009640UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30625 #define MISCS_REG_DRIVER_K2_CONTROL_14_SIZE                                                          2
30626 #define MISCS_REG_DRIVER_K2_CONTROL_15                                                               0x009648UL //Access:RW   DataWidth:0x20  These registers represent 16 clients and 32 resources for single path chip. In single path chip 16 clients are handled by MISC_REGISTERS_DRIVER_CONTROL.DRIVER_CONTROL and another 16 clients are handled by this register. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.  Chips: K2
30627 #define MISCS_REG_DRIVER_K2_CONTROL_15_SIZE                                                          2
30628 #define MISCS_REG_BSC_SDA_SEL                                                                        0x009650UL //Access:RW   DataWidth:0x2   00: connect SDA interface to BSC_SDA0 IO. 01: connect SDA interface to BSC_SDA1 IO. 10: connect SDA interface to BSC_SDA2 IO. 11: connect SDA interface to BSC_SDA3 IO.  Chips: K2
30629 #define MISCS_REG_CHIP_CORE_RESET_SOURCE                                                             0x009654UL //Access:RW   DataWidth:0x3   Bit[0]: PERST# IO de-assertion. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. Bit[1]: PCIE HOT reset. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. Bit[2]: PCIE link is up. If == 1, triggers chip core reset. If == 0, doesn't trigger chip core reset. More than one bit can be set to 1. This register is reset on hard reset event.  Chips: K2
30630 #define MISCS_REG_WOL_CONFIG                                                                         0x009658UL //Access:RW   DataWidth:0x2   Bit[0]: Out of the Box (OOB) WOL enable. Set to 1 to enable use of NIC magic packet detection to assert WAKE OOB. Reset on POR reset and PERST# de-assert. Bit[1]: WAKE control ? direct MFW control of the WAKE# IO. Set to 1 to asserts WAKE# = 0. Reset on POR reset and PERST# de-assert.  Chips: K2
30631 #define MISCS_REG_PCIE_CORE_RST_N_STATUS                                                             0x00965cUL //Access:RW   DataWidth:0x1   When 0, indicated PCIE EP controller is in reset, except for PMC module. Refer to PCIE EP controller databook.  Chips: K2
30632 #define MISCS_REG_PCIE_PHY_RST_N_STATUS                                                              0x009660UL //Access:RW   DataWidth:0x1   When 0, indicated PCIE PHY is in reset Refer to PCIE PHY user manual.  Chips: K2
30633 #define MISCS_REG_CORE_RST_N_STATUS                                                                  0x0096b8UL //Access:R    DataWidth:0x1   Chip core_rst_n status. 0 - asserted; 1 - de-asserted.  Chips: K2
30634 #define MISCS_REG_LINK_HOLDOFF_STATUS                                                                0x0096bcUL //Access:R    DataWidth:0x2   Indicates if MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ succeeded or failed. Once MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ is set, this register should be polled till one of the fields is set to 1. Bit 0 : LINK_HOLDOFF_SUCCESS When =1,  indicates the PCIE link is successfully being held from starting training. Used in conjunction with MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ . Bit 1 : LINK_HOLDOFF_FAILURE When =1, indicates the PCIE link is failed to being held from starting training. Used in conjunction with MISC_REGISTERS_LINK_HOLDOFF_REQ.LINK_HOLDOFF_REQ .  Chips: BB_A0 BB_B0 K2
30635 #define MISCS_REG_LINK_HOLDOFF_REQ                                                                   0x0096c0UL //Access:RW   DataWidth:0x1   This bit is written to a '1' to request that the PCIE link not begin training yet. Software should set this bit; and then check the MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_STATUS register. Pulling may be required till one of the fields is set: If MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_SUCCESS is set; configure the PCIE link and then clear this bit. If MISC_REGISTERS_LINK_HOLDOFF_STATUS.LINK_HOLDOFF_FAILURE is set; the PCIE link has already begun training so it's too late to do any configuration. Clear this bit.  Chips: BB_A0 BB_B0 K2
30636 #define MISCS_REG_GENERIC_HW_0                                                                       0x0096c4UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by hard reset. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30637 #define MISCS_REG_GENERIC_HW_1                                                                       0x0096c8UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by hard reset. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30638 #define MISCS_REG_GENERIC_CR_0                                                                       0x0096ccUL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by core reset. Reset on core reset.  Chips: BB_A0 BB_B0 K2
30639 #define MISCS_REG_GENERIC_CR_1                                                                       0x0096d0UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by core reset. Reset on core reset.  Chips: BB_A0 BB_B0 K2
30640 #define MISCS_REG_GENERIC_POR_0                                                                      0x0096d4UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the Vmain state machine. Reset on POR reset.  Chips: BB_A0 BB_B0 K2
30641 #define MISCS_REG_GENERIC_POR_1                                                                      0x0096d8UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by por reset. Reset on POR reset.  Chips: BB_A0 BB_B0 K2
30642 #define MISCS_REG_GEN_PURP_HWG                                                                       0x0096dcUL //Access:RW   DataWidth:0x20  Bit[0]: EPIO MODE SEL: Setting this bit to 1 will allow SW/FW to use all of the 32 Extended GPIO pins. Without setting this bit; an EPIO can not be configured as an output. Each output has its output enable in the MCP register space; but this bit needs to be set to make use of that. Bit[3:1] spare. Bit[4]: WCVTMON_PWRDN: Powerdown for Warpcore VTMON. When set to 1 - Powerdown. Bit[5]: WCVTMON_RESETB: Reset for Warpcore VTMON. When set to 0 - vTMON is in reset. Bit[6]: setting this bit will change the i/o to an output and will drive the TimeSync output. Bit[31:7]: spare. Global register. Reset by hard reset.  Chips: BB_A0 BB_B0 K2
30643 #define MISCS_REG_GEN_PURP_CRG                                                                       0x0096e0UL //Access:RW   DataWidth:0x20  Debug only: spare RW register reset by core reset. Bit[0]: used for VCCMIN control to select 25MHz clock on XMAC; UMAC and PCIE Serdes. Global register.  Chips: BB_A0 BB_B0 K2
30644 #define MISCS_REG_GEN_PURP_PORG                                                                      0x0096e4UL //Access:RW   DataWidth:0x20  Debug only: [31:11] - spare RW register reset by por reset; [10:8] : PCIe Device Type: 3'b000 - Endpoint mode; 3'b010 - RC mode; 3'b011 - RC mode, with Refclk provided by Serdes. [7:5] - spare RW register reset by por reset; [4] - SW control to the serdes uController reset. When =1 the serdes uController is reset; [3] - when 1 reset the Vmain Switching Regulator Controller PMU registers; [2] - when 1 disable the Vmain Switching Regulator Controller; [1] -  when 1 reset the Vmgmt Switching Regulator Controller PMU registers; [0] - when 1 disable the Vmgmt Switching Regulator Controller. Global register.  Chips: BB_A0 BB_B0 K2
30645 #define MISCS_REG_ISOLATION_LOGIC                                                                    0x0096e8UL //Access:R    DataWidth:0x1   The isolation between Vaux and Vmain read value.  Chips: BB_A0 BB_B0 K2
30646 #define MISCS_REG_VMAIN_POR                                                                          0x0096ecUL //Access:RW   DataWidth:0x2   0-bypass the Vmain PORBG. for Vmain POR; if sel=1 the output wil be MISC_REGISTERS_VMAIN_POR.VMAIN_POR [1]; 1- bypass the Vmain PORBG. If MISC_REGISTERS_VMAIN_POR.VMAIN_POR [0] is '1' the output of Vmain POR will be this field.  Chips: BB_A0 BB_B0 K2
30647 #define MISCS_REG_FUNCTION_HIDE                                                                      0x0096f0UL //Access:RW   DataWidth:0x10  Bypass to the FUNC_HIDE pin. Bit 0 - bypass select; Bits[15:1] - bypass value per function (1 - function 1; 2 -function 2; etc.). When bypass select is 0, the value is selected depending on FUNC_HIDE pin and 4 port/2 port mode; when bypass select = 1; bypass value is selected. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30648 #define MISCS_REG_PWR_ATTN                                                                           0x0096f4UL //Access:RW   DataWidth:0x1   This bit indicates that a Vmain powerdown event occurred. Write 0 to clear the event. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30649 #define MISCS_REG_SMBIO_ENABLE_GLITCH_FILTER                                                         0x0096f8UL //Access:RW   DataWidth:0x1   When set enables the deglitching circuit for the SMBus inputs per I2C requirement.  Chips: BB_A0 BB_B0 K2
30650 #define MISCS_REG_PCIE_HOT_RESET                                                                     0x0096fcUL //Access:RC   DataWidth:0x1   If set indicate that the pcie_rst_b was asserted without perst assertion.  Chips: BB_A0 BB_B0 K2
30651 #define MISCS_REG_FUNC_HIDE_PIN                                                                      0x009700UL //Access:R    DataWidth:0x1   Synchronised value of ifmux_misc_func_hide.  Chips: BB_A0 BB_B0 K2
30652 #define MISCS_REG_NIG_DBG_VECTOR                                                                     0x009704UL //Access:RW   DataWidth:0x1   NIG debug mux vector control. 0 - NIG0 debug vector is output to IFMUX; 1 -  NIG1 debug vector is output to IFMUX.  Chips: BB_A0 BB_B0
30653 #define MISCS_REG_FOUR_PORT_SHARED_MDIO_EN                                                           0x009708UL //Access:RW   DataWidth:0x1   When set this will allow any of the four emacs MDIO masters to initiate MDIO transactions to access XGXS0 or the four external GPHYs. Drives misc_cnig_mux_4port_shared_mdio_en output. Applicable both in 2-port and 4-port mode.  Chips: BB_A0 BB_B0 K2
30654 #define MISCS_REG_SEL_DBG_IFMUX_TEST                                                                 0x00970cUL //Access:RW   DataWidth:0x1   NIG EMAC debug source selector. If 0 - path0 gmii/mii emac debug outputs are selected by NIG; If 1 - path1 gmii/mii emac debug outputs are selected by NIG. Drives output misc_cnig_sel_dbg_ifmux_test.  Chips: BB_A0 BB_B0 K2
30655 #define MISCS_REG_SEL_VAUX                                                                           0x009710UL //Access:R    DataWidth:0x2   SEL_VAUX_B - Control to power switching logic. [0] - output value driven by MISC; [1] - input pin value.  Chips: BB_A0 BB_B0 K2
30656 #define MISCS_REG_PCIE_DIS                                                                           0x009714UL //Access:RW   DataWidth:0x1   PCIE disable register bit. PCIE DIS. Has same functionality as the external IO PCIE_DIS: Internal PCIE DIS = external IO PCIE DIS or MISCS_REG_PCIE_DIS.  Chips: BB_A0 BB_B0 K2
30657 #define MISCS_REG_CLK_NW_MAC_FAST_MODE                                                               0x009718UL //Access:RW   DataWidth:0x1   When set to 1, HiGig is supported on 40G and the nw mac clock frequency is higher than the main clock frequency. When set to 0, HiGig is not supported on 40G and the nw mac clock frequency is identical to the main clock frequency. Applicable only for K2.  Chips: BB_A0 BB_B0 K2
30658 #define MISCS_REG_CMT_ENABLED_FOR_PAIR                                                               0x00971cUL //Access:RW   DataWidth:0x8   For Coupled Mode Teaming. Each bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If the bit is clear then the PFs for that pair are not coupled and the even PF is mapped to path 0 and the odd PF is mapped to path 1. This is the same mapping E2 and E3 have. If the bit is set then those PFs are coupled. In this case the even PF is mapped to both paths and the odd PF is disabled.  Chips: BB_A0 BB_B0 K2
30659 #define MISCS_REG_ISOLATE_PATH                                                                       0x009720UL //Access:RW   DataWidth:0x1   This bit will be set by the MCP when the device works in PDA mode. The value of this register also drives the isolate_path output of the MISC block.  Chips: BB_A0 BB_B0 K2
30660 #define MISCS_REG_MDIO_OVERRIDE                                                                      0x009724UL //Access:RW   DataWidth:0x1   MDIO Override. Enables the values on MISC_REGISTERS_MDIO_SUBSCRIPTION.MDIO_SUBSCRIPTION to override the hardware mode defined defaults. Global register. Reset on Hard reset.  Chips: BB_A0 BB_B0 K2
30661 #define MISCS_REG_MDIO_SUBSCRIPTION                                                                  0x009728UL //Access:RW   DataWidth:0x20  MDIO Subscription. Is used to configure the subscriptions of on-chip PHY devices and MAC ports to the four MDIO domains. It is only used when MISC_REGISTERS_MDIO_OVERRIDE.MDIO_OVERRIDE is set. [3:0] - ch0_rr; [7:4] - ch1_rr; [11:8] - ch2_rr; [15:12] - ch3_rr; [19:16] - ch0_phy; [23:20] - ch1_phy; [27:24] - ch2_phy; [31:28] - ch3_phy. Global register. Reset on Hard reset.  Chips: BB_A0 BB_B0 K2
30662 #define MISCS_REG_HOT_RESET_UNPREPARED                                                               0x00972cUL //Access:RW   DataWidth:0x1   Set to 1 when pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state. Reset to 0 by the FW. Reset on por reset.  Chips: BB_A0 BB_B0 K2
30663 #define MISCS_REG_OTP_MISC_DO                                                                        0x009730UL //Access:R    DataWidth:0x5   OTP IO 5 msb.  Chips: BB_A0 BB_B0 K2
30664 #define MISCS_REG_PARITY_MODE                                                                        0x009734UL //Access:RW   DataWidth:0x1   Debug only : parity mode to MCP. Setting this bit changes the parity checking on the memories from even to odd parity. Global register.  Chips: BB_A0 BB_B0 K2
30665 #define MISCS_REG_IPOR_CMD_REG                                                                       0x009738UL //Access:RW   DataWidth:0x1   Writing this bit as a '1' will cause the chip to do an internal reset exactly like a power-up reset. There is not protection for this request and it may cause any current PCI cycle to lock up. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30666 #define MISCS_REG_MAIN_SEQ_BYP_SEL                                                                   0x00973cUL //Access:RW   DataWidth:0x5   Debug only. main_sequencer_bypass select. For each bit; when set; the compatible bit in the MISC_REGISTERS_MAIN_SEQ_BYP_VAL.MAIN_SEQ_BYP_VAL affects the controls; when reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - unprepared_power_down_detection; Bit 3 - PCIE_reset_b; Bit 4 - sel_vaux_b. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30667 #define MISCS_REG_MAIN_SEQ_BYP_VAL                                                                   0x009740UL //Access:RW   DataWidth:0x5   Debug only. main_sequencer_bypass values. For each bit; the written value affects the control only if the compatible bit in the MISC_REGISTERS_MAIN_SEQ_BYP_SEL.MAIN_SEQ_BYP_VAL is set; when reset; the SM affects the controls. Bit 0 - Vmain OTP reset; Bit 1 - isolation_logic_b; Bit 2 - uprepared_power_down_detection; Bit 3 - PCIE_reset_b; Bit 4 - sel_vaux_b. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30668 #define MISCS_REG_UNCOND_ENTER_PLAY_DEAD                                                             0x009744UL //Access:RW   DataWidth:0x1   Writing to this register results in resetting entire chip via the play dead mechanism.  Chips: BB_A0 BB_B0 K2
30669 #define MISCS_REG_COND_ENTER_PLAY_DEAD                                                               0x009748UL //Access:RW   DataWidth:0x1   Writing to this register result with resetting entire chip via the play dead mechanism if PERST is asserted.  Chips: BB_A0 BB_B0 K2
30670 #define MISCS_REG_PLL_MAIN_CTRL_4                                                                    0x00974cUL //Access:RW   DataWidth:0x2   Bit0 = Controls the glitch-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bit 1 in this regitser); reset (to 0) with hard_rst_b. bit1 =Glichless mux manual setting has affect when bit 0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset (to 0) with hard_rst_b. Reset on POR reset.  Chips: BB_A0 BB_B0 K2
30671 #define MISCS_REG_PLL_STORM_CTRL_4                                                                   0x009750UL //Access:RW   DataWidth:0x1   [0]clock storm bypass: 0-select Storm SPLL clock; 1-select external clock; Reset on POR reset.  Chips: BB_A0 BB_B0 K2
30672 #define MISCS_REG_UNPREPARED                                                                         0x009754UL //Access:RW   DataWidth:0x1   Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30673 #define MISCS_REG_UNPREPARED_FW                                                                      0x009758UL //Access:RW   DataWidth:0x1   Set by the MCP to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30674 #define MISCS_REG_UNPREPARED_DR                                                                      0x00975cUL //Access:RW   DataWidth:0x1   Set by the Driver to remember if one or more of the drivers is/are loaded; 0-prepare; 1-unprepare. Reset on hard reset.  Chips: BB_A0 BB_B0 K2
30675 #define MISCS_REG_VAUX_PRESENT                                                                       0x009760UL //Access:R    DataWidth:0x1   0 - VAUX is not present; 1 - VAUX is present.  Chips: BB_A0 BB_B0 K2
30676 #define MISCS_REG_VAUX_EN_DIS                                                                        0x009764UL //Access:RW   DataWidth:0x8   VAUX_ENABLE/DISABLE. [7-6]  FLOAT  When any of these bits is written as a '1'; the corresponding vaux_enable/vaux_disable bit will turn off it's drivers and become an input. This is the reset state of all pins. The read value of these bits will be a '1' if the last command ( SET ; CL ; or FLOAT ) for this bit was a FLOAT . (reset value 0x3). [5-4]  CLR  When any of these bits is written as a '1'; the corresponding vaux_enable/vaux_disable bit will drive low. The read value of these bits will be a '1' if the last command ( SET ; CLR ; or FLOAT ) for this bit was a CLR . (reset value 0). [3-2]  SET  When any of these bits is written as a '1'; the corresponding vaux_enable/vaux_disable bit will drive high. The read value of these bits will be a '1' if the last command ( SET ; CLR ; or FLOAT ) for this bit was a SET .  (reset value 0). [1-0]  VALUE  RO; These bits indicate the read value of vaux_enable/vaux_disable pins. This is the result value of the pin; not the drive value. Writing these bits will have not effect. [0] VAUX Enable; when pulsed low; enables supply from VAUX. (This is an output pin only; the FLOAT field is not applicable for this pin); [1] VAUX Disable; when pulsed low; disables supply form VAUX. (This is an output pin only; FLOAT field is not applicable for this pin); Global register.  Chips: BB_A0 BB_B0 K2
30677 #define MISCS_REG_VAUX_EN_DIS_INT                                                                    0x009768UL //Access:RW   DataWidth:0x8   VAUX_ENABLE/DISABLE INT. [7-6]  OLD_CLR  Writing a '1' to these bit clears the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the falling edge of corresponding vaux_enable/vaux_disable input (reset value 0). [5-4]  OLD_SET  Writing a '1' to these bit sets the corresponding bit in the OLD_VALUE register. This will acknowledge an interrupt on the rising edge of corresponding vaux_enable/vaux_disable input (reset value 0). [3-2] OLD_VALUE  RO; These bits indicate the old value of the vaux_enable/vaux_disable input value. When the INT_STATE bit is set; this bit indicates the OLD value of the pin such that if INT_STATE is set and this bit is '0'; then the interrupt is due to a low to high edge. If INT_STATE is set and this bit is '1'; then the interrupt is due to a high to low edge (reset value 0). [1-0]  INT_STATE  RO; These bits indicate the current vaux_enable/vaux_disable interrupt state for each vaux_enable/vaux_disable pin. This bit is cleared when the appropriate OLD_SET or OLD_CLR command bit is written. This bit is set when the vaux_enable/vaux_disable input does not match the current value in OLD_VALUE (reset value 0). Global register.  Chips: BB_A0 BB_B0 K2
30678 #define MISCS_REG_CHIP_NUM                                                                           0x00976cUL //Access:R    DataWidth:0x10  These bits indicate the part number for the chip.  Chips: BB_A0 BB_B0 K2
30679 #define MISCS_REG_CHIP_REV                                                                           0x009770UL //Access:R    DataWidth:0x4   These bits indicate the base revision of the chip. This value starts at 0x0 for the A0 tape-out and increments by one for each all-layer tape-out.  Chips: BB_A0 BB_B0 K2
30680 #define MISCS_REG_CHIP_METAL                                                                         0x009774UL //Access:R    DataWidth:0x8   These bits indicate the metal revision of the chip. This value starts at 0x00 for each all-layer tape-out and increments by one for each tape-out.  Chips: BB_A0 BB_B0 K2
30681 #define MISCS_REG_CHIP_TEST_REG                                                                      0x009778UL //Access:R    DataWidth:0x8   These bits indicate the silent revision of the chip.  Chips: BB_A0 BB_B0 K2
30682 #define MISCS_REG_LINK_IN_L23                                                                        0x00977cUL //Access:R    DataWidth:0x1   When this bit is 1 it indicates that the link is down and PCIE is prepared for operation off of VAUX.  Chips: BB_A0 BB_B0 K2
30683 #define MISCS_REG_PCIE_DIS_IO                                                                        0x009780UL //Access:R    DataWidth:0x1   This bit reports the current state of the PCIE_DIS pin. If this bit is 1 it means that the LOM design has been strapped to support management only. The PCI power will always read as '0' in this state; as if the chip is in Out-Of-Box WOL mode.  Chips: BB_A0 BB_B0 K2
30684 #define MISCS_REG_INTERNAL_PERST_N                                                                   0x009784UL //Access:R    DataWidth:0x1   The status of the internal perst_n control (active low) that goes to the PCIE CORE.  Chips: BB_A0 BB_B0 K2
30685 #define MISCS_REG_HRST_ASSERT_CNT                                                                    0x009788UL //Access:RW   DataWidth:0x10  Accounts for Hard reset assertion. Is reset on POR reset.  Chips: BB_A0 BB_B0 K2
30686 #define MISCS_REG_HRST_DEASSERT_CNT                                                                  0x00978cUL //Access:RW   DataWidth:0x10  Accounts for Hard reset de-assertion. Is reset on POR reset.  Chips: BB_A0 BB_B0 K2
30687 #define MISCS_REG_CRST_ASSERT_CNT                                                                    0x009790UL //Access:RW   DataWidth:0x10  Accounts for Core reset assertion. Is reset on POR reset.  Chips: BB_A0 BB_B0 K2
30688 #define MISCS_REG_CRST_DEASSERT_CNT                                                                  0x009794UL //Access:RW   DataWidth:0x10  Accounts for Core de-reset assertion. Is reset on POR reset.  Chips: BB_A0 BB_B0 K2
30689 #define MISCS_REG_PERST_ASSERT_CNT                                                                   0x009798UL //Access:RW   DataWidth:0x10  Accounts for PERST_B reset assertion. Is reset on POR reset.  Chips: BB_A0 BB_B0 K2
30690 #define MISCS_REG_PERST_DEASSERT_CNT                                                                 0x00979cUL //Access:RW   DataWidth:0x10  Accounts for PERST_B reset de-assertion. Is reset on POR reset.  Chips: BB_A0 BB_B0 K2
30691 #define MISCS_REG_PCIE_RST_PREPARED_ASSERT_CNT                                                       0x0097a0UL //Access:RW   DataWidth:0x10  Accounts for PCI_RST_N assertion when the chip is in prepared state. Is reset on POR reset.  Chips: BB_A0 BB_B0
30692 #define MISCS_REG_PCIE_RST_UNPREPARED_ASSERT_CNT                                                     0x0097a4UL //Access:RW   DataWidth:0x10  Accounts for PCI_RST_N assertion when the chip is in un-prepared state. Is reset on POR reset.  Chips: BB_A0 BB_B0
30693 #define MISCS_REG_PCIE_RST_DEASSERT_CNT                                                              0x0097a8UL //Access:RW   DataWidth:0x10  Accounts for PCI_RST_N de-assertion. Is reset on POR reset.  Chips: BB_A0 BB_B0
30694 #define MISCS_REG_HOT_RESET_EN                                                                       0x0097acUL //Access:RW   DataWidth:0x1   When =1, when ptw_miscs_pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state, hard reset is asserted. When =0, when ptw_miscs_pcie_hot_reset is asserted (Hot Reset / SBR / Link Down / Link Disable) and the chip is in un-prepared state, hard reset is not asserted. Reset on por reset.  Chips: BB_A0 BB_B0 K2
30695 #define MISCS_REG_PCIE_RST_N                                                                         0x0097b0UL //Access:R    DataWidth:0x1   Indicates the current state of the pcie_rst_n control which is driven by the PCIE CORE. Active low control.  Chips: BB_A0 BB_B0
30696 #define MISCS_REG_ECO_RESERVED                                                                       0x0097b4UL //Access:RW   DataWidth:0x20  Eco reserved. Global register. [31:30] - used to programm loopback into Emulation (3\|2\|1\|0 (Enable loopback within the same port\|Enable loopback between ports (0 and 1, 2 and 3) of different engines\|Enable loopback between ports (0 and 2, 1 and 3) of the same engine\|Disable loopback)).  Chips: BB_A0 BB_B0 K2
30697 #define MISCS_REG_MCP_ROM_TM                                                                         0x0097b8UL //Access:RW   DataWidth:0x20  Mcp_rom_tm  Chips: BB_A0 BB_B0 K2
30698 #define MISCS_REG_AVS_OTP_SRAM_CTRL                                                                  0x0097bcUL //Access:RW   DataWidth:0x9   [31:9]  Reserved [8]     OTP_AVS_SRAM_MON_VALID [7:6]   OTP_AVS_SRAM_MON_N_PROCESS [5:4]   OTP_AVS_SRAM_MON_P_PROCESS [3:0]   OTP_ADJUST_VOLTAGE  Chips: BB_A0 BB_B0
30699 #define MISCS_REG_AVS_OTP_CTRL_VMAIN                                                                 0x0097c0UL //Access:RW   DataWidth:0xf   [31:15]  Reserved [14:12] OTP_VTRAP_TRIM_CODE: BG_adj [11:9]  OTP_VTRAP_TRIM_CODE: MAX0_adj [8:6]   OTP_VTRAP_TRIM_CODE: MIN1_adj [5:2]   OTP_VTRAP_TRIM_CODE: MIN0_adj [1]     OTP_VTRAP_ENABLE [0]     OTP_AVS_DISABLE  Chips: BB_A0 BB_B0
30700 #define MISCS_REG_AVS_OTP_CTRL_VMGMT                                                                 0x0097c4UL //Access:RW   DataWidth:0xf   [31:15]  Reserved [14:12] OTP_VTRAP_TRIM_CODE: BG_adj [11:9]  OTP_VTRAP_TRIM_CODE: MAX0_adj [8:6]   OTP_VTRAP_TRIM_CODE: MIN1_adj [5:2]   OTP_VTRAP_TRIM_CODE: MIN0_adj [1]     OTP_VTRAP_ENABLE [0]     OTP_AVS_DISABLE  Chips: BB_A0 BB_B0
30701 #define MISCS_REG_AVS_TOP_ADDR                                                                       0x0097c8UL //Access:RW   DataWidth:0x11  Indirect address.  Used to addrerss a register in avs_top.  Chips: BB_A0 BB_B0
30702 #define MISCS_REG_AVS_TOP_DATA                                                                       0x0097ccUL //Access:RW   DataWidth:0x20  Indirect data. Reading from this fetches data from top_addr.                          Writing stores data to top_addr.  Chips: BB_A0 BB_B0
30703 #define MISCS_REG_AVS_PVTMON_DACCODE                                                                 0x0097d0UL //Access:RW   DataWidth:0x16  [31:22] Reserved [21]    VMgmt DAC Over-ride: When set, over-ride DAC code from AVS monitor with on from this register [20:11] VMgmt DAC Codeword [10]    VMain DAC Over-ride: When set, over-ride DAC code from AVS monitor with on from this register [9:0]   VMain DAC Codeword  Chips: BB_A0 BB_B0
30704 #define MISCS_REG_OPTE_EMPTY_STATUS                                                                  0x0097d4UL //Access:R    DataWidth:0x1c  Packet available and FIFO empty status signals: [27:11] - Per-TC packet available status; [10] -  STORM FIFO; [9] - BTB SOP FIFO for engine 0; [8] - BTB SOP FIFO for engine 1; [7] - BTB IF0 FIFO for engine 0; [6] - BTB IF0 FIFO for engine 1; [5] - BTB IF1 FIFO for engine 0; [4] - BTB IF1 FIFO for engine 1; [3] - DBG FIFO for engine 0; [2] - DBG FIFO for engine 1; [1] - DORQ FIFO for engine 0; [0] - DORQ FIFO for engine 1;  Chips: BB_A0 BB_B0
30705 #define MISCS_REG_OPTE_FULL_STATUS                                                                   0x0097d8UL //Access:R    DataWidth:0xc   FIFO full status signals: [11] -  STORM FIFO almost full; [10] -  STORM FIFO full; [9] -  BTB SOP FIFO full for engine 0; [8] -  BTB SOP FIFO full for engine 1; [7] -  BTB IF0 FIFO full for engine 0; [6] -  BTB IF0 FIFO full for engine 1; [5] -  BTB IF1 FIFO full for engine 0; [4] -  BTB IF1 FIFO full for engine 1; [3] -  DBG FIFO full for engine 0; [2] -  DBG FIFO full for engine 1; [1] -  DORQ FIFO full for engine 0; [0] -  DORQ FIFO full for engine 1;  Chips: BB_A0 BB_B0
30706 #define MISCS_REG_OPTE_STATS_VECTOR                                                                  0x0097dcUL //Access:R    DataWidth:0x8   Signals for statistics counters, one bit for each statistics. [7] -  Received packet from BTB IF0 of engine 0; [6] -  Received packet from BTB IF0 of engine 1; [5] -  Received packet from BTB IF1 of engine 0; [4] -  Received packet from BTB IF1 of engine 1; [3] -  Sent packet to BRB IF0 of engine 0; [2] -  Sent packet to BRB IF0 of engine 1; [1] -  Sent packet to BRB IF1 of engine 0; [0] -  Sent packet to BRB IF1 of engine 1;  Chips: BB_A0 BB_B0
30707 #define MISCS_REG_OPTE_CTRL                                                                          0x0097e0UL //Access:RW   DataWidth:0x8   Opte Control configuration. [7:4] -  storm_init_crd: Credits for the output STORM Packet interface. [3:2] -  storm_pkt_dst: Select the destination engine for STORM packets. Set bit 2 to send STORM packets to engine 0. Set bit 3 to send STORM packets to engine 1. Set both bits to send STORM packets to both engines.  At least one destination has to be selected at any given time. [1:0] -  pxp_msg_dst: Select the destination engine for PXP messages. Set bit 0 to send PXP messages to engine 0. Set bit 1 to send PXP messages to engine 1. Set both bits to send PXP messages to both engines.  At least one destination has to be selected at any given time.  Chips: BB_A0 BB_B0
30708 #define MISCS_REG_OPTE_ALMFULL_THR                                                                   0x0097e4UL //Access:RW   DataWidth:0x1e  OPTE Almost-full Threshold. [29:25] -  Btb_if0_fifo_almfull_thr: Almost-full threshold for BTB main traffic FIFO. [24:20] -  Btb_if1_fifo_almfull_thr: Almost-full threshold for BTB LB traffic FIFO. [19:15] -  Storm_fifo_almfull_thr: Almost-full threshold for STORM FIFO. While this threshold is met or exceeded, OPTE stops returning credits to NIG since OPTE has to be able to honor the credits that NIG has for the STORM Packet interface.  Note that the actual assertion of the almost full flag is 1-3 entries more than the configured threshold. [14:5] -  reserved. [4:0] - Dbg_fifo_almfull_thr: Almost-full threshold for Debug FIFO.  Chips: BB_A0 BB_B0
30709 #define MISCS_REG_AVS_CLOCK_OBSERVE                                                                  0x0097ecUL //Access:RW   DataWidth:0x6   [31:6] Reserved [5]    Divide enable [4]    Enable [3:0]  Control  Chips: BB_B0
30710 #define MISCS_REG_AVS_TP_OUT_CTRL                                                                    0x0097f0UL //Access:RW   DataWidth:0x3   [31:3] Reserved [2]    Enable [1:0]  Select  Chips: BB_B0
30711 #define MISCS_REG_AVS_TP_IN                                                                          0x0097f4UL //Access:RW   DataWidth:0x20  [31:0] Data  Chips: BB_B0
30712 #define MISCS_REG_AVS_TP_OUT                                                                         0x0097f8UL //Access:R    DataWidth:0x20  [31:0] Data  Chips: BB_B0
30713 #define DBU_REG_CMD                                                                                  0x00a000UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30714     #define DBU_REG_CMD_ENABLE                                                                       (0x1<<0) // This bit will always read '1', as it is not possible to disable the dbu block.
30715     #define DBU_REG_CMD_ENABLE_SHIFT                                                                 0
30716     #define DBU_REG_CMD_RX_ERROR                                                                     (0x1<<1) // This bit will read '1' if a byte has been received with a framing error. It will continue to read as a '1' until the command register is written with a '1' in this bit position.
30717     #define DBU_REG_CMD_RX_ERROR_SHIFT                                                               1
30718     #define DBU_REG_CMD_RX_OVERFLOW                                                                  (0x1<<2) // This bit will read '1' of a receive overflow has occurred. It will continue to read as a '1' until the command register is written with a '1' in this bit position.
30719     #define DBU_REG_CMD_RX_OVERFLOW_SHIFT                                                            2
30720 #define DBU_REG_STATUS                                                                               0x00a004UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30721     #define DBU_REG_STATUS_RXDATA_VALID                                                              (0x1<<0) // This bit will read '1' if there is a valid byte to read in dbu_rxdata. Once dbu_rxdata is read, this bit will automatically clear.
30722     #define DBU_REG_STATUS_RXDATA_VALID_SHIFT                                                        0
30723     #define DBU_REG_STATUS_TXDATA_OCCUPIED                                                           (0x1<<1) // This bit will read '1' if there is data pending to be transmitted in the txdata register. The bit will automatically clear when the txdata register is emptied.
30724     #define DBU_REG_STATUS_TXDATA_OCCUPIED_SHIFT                                                     1
30725 #define DBU_REG_CONFIG                                                                               0x00a008UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30726     #define DBU_REG_CONFIG_TIMING_OVERRIDE                                                           (0x1<<0) // When this bit is set, the UART timing will be determined by the values in the dbu_timing register. When the bit is clear, the UART timing will be determined by the timing_select inputs to the block.
30727     #define DBU_REG_CONFIG_TIMING_OVERRIDE_SHIFT                                                     0
30728     #define DBU_REG_CONFIG_DEBUGSM_ENABLE                                                            (0x1<<1) // When this bit is set, the debug state machine shall respond to received characters by performing GRC master transactions and returning received data.
30729     #define DBU_REG_CONFIG_DEBUGSM_ENABLE_SHIFT                                                      1
30730     #define DBU_REG_CONFIG_CRLF_ENABLE                                                               (0x1<<2) // When this bit is set, all line feeds shall be preceded by a carriage return. Note that this bit has no impact on carriage returns transmitted by a GRC master via the txdata register.
30731     #define DBU_REG_CONFIG_CRLF_ENABLE_SHIFT                                                         2
30732 #define DBU_REG_TIMING                                                                               0x00a00cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
30733     #define DBU_REG_TIMING_FB_SMPL_OFFSET                                                            (0xffff<<0) // These bits set the number of core_clock cycles after the falling edge of the rx_data pin that the start bit should be sampled. The default value of 0x6C results in 115200 baud operation with CK25 at 25MHz. Baud Rate 2400     : 0x1458 Baud Rate 4800     : 0x0A2C Baud Rate 9600     : 0x0516 Baud Rate 19200    : 0x028B Baud Rate 38400    : 0x0145 Baud Rate 57600    : 0x00D9 Baud Rate 115200   : 0x006c Baud Rate 230400   : 0x0036 Baud Rate 460800   : 0x001B
30734     #define DBU_REG_TIMING_FB_SMPL_OFFSET_SHIFT                                                      0
30735     #define DBU_REG_TIMING_BIT_INTERVAL                                                              (0xffff<<16) // These bits set the number of core_clock cycles in between bits for both rx and tx. The default value of 0xD9 results in 115200 baud operation with CK25 at 25MHz. Baud Rate 2400     : 0x28B0 Baud Rate 4800     : 0x1458 Baud Rate 9600     : 0x0A2C Baud Rate 19200    : 0x0516 Baud Rate 38400    : 0x028B Baud Rate 57600    : 0x0145 Baud Rate 115200   : 0x00D9 Baud Rate 230400   : 0x006c Baud Rate 460800   : 0x0036
30736     #define DBU_REG_TIMING_BIT_INTERVAL_SHIFT                                                        16
30737 #define DBU_REG_RXDATA                                                                               0x00a010UL //Access:R    DataWidth:0x8   This bit indicates that the data currently in bits 7:0 of this register was received in error. This bit is valid only if rx_valid is set in the status register.  Chips: BB_A0 BB_B0 K2
30738 #define DBU_REG_TXDATA                                                                               0x00a014UL //Access:RW   DataWidth:0x8   This register can be written to transmit a single byte of data on the serial interface. Firmware should poll the txdata_occupied bit in the status register before writing this register to make sure that a previously written byte has been transmitted. This register will read back the last txdata byte that was written.  Chips: BB_A0 BB_B0 K2
30739 #define DBU_REG_VFID_CFG                                                                             0x00a018UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
30740     #define DBU_REG_VFID_CFG_VFID_VALUE                                                              (0xff<<0) // Set the VF for which the registers need to be accessed
30741     #define DBU_REG_VFID_CFG_VFID_VALUE_SHIFT                                                        0
30742     #define DBU_REG_VFID_CFG_PORT_VALUE                                                              (0xff<<8) // Set the Port for which the registers need to be accessed
30743     #define DBU_REG_VFID_CFG_PORT_VALUE_SHIFT                                                        8
30744     #define DBU_REG_VFID_CFG_VFID_VALID                                                              (0x1<<16) // The vfid_value bits are valid only if this bit is set. If this bit is cleared, PF registers will be accessed
30745     #define DBU_REG_VFID_CFG_VFID_VALID_SHIFT                                                        16
30746     #define DBU_REG_VFID_CFG_PATHID                                                                  (0x1<<20) // Set the path ID if the access is forced as indicated by bit 31.
30747     #define DBU_REG_VFID_CFG_PATHID_SHIFT                                                            20
30748     #define DBU_REG_VFID_CFG_PATH_FORCE                                                              (0x1<<31) // When 0, the path selection is done by PFID[0]. When 1,  the path selection is done by the PATHID field in this register.
30749     #define DBU_REG_VFID_CFG_PATH_FORCE_SHIFT                                                        31
30750 #define DMAE_REG_INIT                                                                                0x00c000UL //Access:RW   DataWidth:0x1   Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.  Chips: BB_A0 BB_B0 K2
30751 #define DMAE_REG_PCI_IFEN                                                                            0x00c040UL //Access:RW   DataWidth:0x1   DMAE PCI Interface (Request;Read;Write) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; full is asserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
30752 #define DMAE_REG_GRC_IFEN                                                                            0x00c044UL //Access:RW   DataWidth:0x1   DMAE GRC Interface (Target;Master) enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
30753 #define DMAE_REG_GO_C0                                                                               0x00c048UL //Access:RW   DataWidth:0x1   Command 0 go.  Chips: BB_A0 BB_B0 K2
30754 #define DMAE_REG_GO_C1                                                                               0x00c04cUL //Access:RW   DataWidth:0x1   Command 1 go.  Chips: BB_A0 BB_B0 K2
30755 #define DMAE_REG_GO_C2                                                                               0x00c050UL //Access:RW   DataWidth:0x1   Command 2 go.  Chips: BB_A0 BB_B0 K2
30756 #define DMAE_REG_GO_C3                                                                               0x00c054UL //Access:RW   DataWidth:0x1   Command 3 go.  Chips: BB_A0 BB_B0 K2
30757 #define DMAE_REG_GO_C4                                                                               0x00c058UL //Access:RW   DataWidth:0x1   Command 4 go.  Chips: BB_A0 BB_B0 K2
30758 #define DMAE_REG_GO_C5                                                                               0x00c05cUL //Access:RW   DataWidth:0x1   Command 5 go.  Chips: BB_A0 BB_B0 K2
30759 #define DMAE_REG_GO_C6                                                                               0x00c060UL //Access:RW   DataWidth:0x1   Command 6 go.  Chips: BB_A0 BB_B0 K2
30760 #define DMAE_REG_GO_C7                                                                               0x00c064UL //Access:RW   DataWidth:0x1   Command 7 go.  Chips: BB_A0 BB_B0 K2
30761 #define DMAE_REG_GO_C8                                                                               0x00c068UL //Access:RW   DataWidth:0x1   Command 8 go.  Chips: BB_A0 BB_B0 K2
30762 #define DMAE_REG_GO_C9                                                                               0x00c06cUL //Access:RW   DataWidth:0x1   Command 9 go.  Chips: BB_A0 BB_B0 K2
30763 #define DMAE_REG_GO_C10                                                                              0x00c070UL //Access:RW   DataWidth:0x1   Command 10 go.  Chips: BB_A0 BB_B0 K2
30764 #define DMAE_REG_GO_C11                                                                              0x00c074UL //Access:RW   DataWidth:0x1   Command 11 go.  Chips: BB_A0 BB_B0 K2
30765 #define DMAE_REG_GO_C12                                                                              0x00c078UL //Access:RW   DataWidth:0x1   Command 12 go.  Chips: BB_A0 BB_B0 K2
30766 #define DMAE_REG_GO_C13                                                                              0x00c07cUL //Access:RW   DataWidth:0x1   Command 13 go.  Chips: BB_A0 BB_B0 K2
30767 #define DMAE_REG_GO_C14                                                                              0x00c080UL //Access:RW   DataWidth:0x1   Command 14 go.  Chips: BB_A0 BB_B0 K2
30768 #define DMAE_REG_GO_C15                                                                              0x00c084UL //Access:RW   DataWidth:0x1   Command 15 go.  Chips: BB_A0 BB_B0 K2
30769 #define DMAE_REG_GO_C16                                                                              0x00c088UL //Access:RW   DataWidth:0x1   Command 16 go.  Chips: BB_A0 BB_B0 K2
30770 #define DMAE_REG_GO_C17                                                                              0x00c08cUL //Access:RW   DataWidth:0x1   Command 17 go.  Chips: BB_A0 BB_B0 K2
30771 #define DMAE_REG_GO_C18                                                                              0x00c090UL //Access:RW   DataWidth:0x1   Command 18 go.  Chips: BB_A0 BB_B0 K2
30772 #define DMAE_REG_GO_C19                                                                              0x00c094UL //Access:RW   DataWidth:0x1   Command 19 go.  Chips: BB_A0 BB_B0 K2
30773 #define DMAE_REG_GO_C20                                                                              0x00c098UL //Access:RW   DataWidth:0x1   Command 20 go.  Chips: BB_A0 BB_B0 K2
30774 #define DMAE_REG_GO_C21                                                                              0x00c09cUL //Access:RW   DataWidth:0x1   Command 21 go.  Chips: BB_A0 BB_B0 K2
30775 #define DMAE_REG_GO_C22                                                                              0x00c0a0UL //Access:RW   DataWidth:0x1   Command 22 go.  Chips: BB_A0 BB_B0 K2
30776 #define DMAE_REG_GO_C23                                                                              0x00c0a4UL //Access:RW   DataWidth:0x1   Command 23 go.  Chips: BB_A0 BB_B0 K2
30777 #define DMAE_REG_GO_C24                                                                              0x00c0a8UL //Access:RW   DataWidth:0x1   Command 24 go.  Chips: BB_A0 BB_B0 K2
30778 #define DMAE_REG_GO_C25                                                                              0x00c0acUL //Access:RW   DataWidth:0x1   Command 25 go.  Chips: BB_A0 BB_B0 K2
30779 #define DMAE_REG_GO_C26                                                                              0x00c0b0UL //Access:RW   DataWidth:0x1   Command 26 go.  Chips: BB_A0 BB_B0 K2
30780 #define DMAE_REG_GO_C27                                                                              0x00c0b4UL //Access:RW   DataWidth:0x1   Command 27 go.  Chips: BB_A0 BB_B0 K2
30781 #define DMAE_REG_GO_C28                                                                              0x00c0b8UL //Access:RW   DataWidth:0x1   Command 28 go.  Chips: BB_A0 BB_B0 K2
30782 #define DMAE_REG_GO_C29                                                                              0x00c0bcUL //Access:RW   DataWidth:0x1   Command 29 go.  Chips: BB_A0 BB_B0 K2
30783 #define DMAE_REG_GO_C30                                                                              0x00c0c0UL //Access:RW   DataWidth:0x1   Command 30 go.  Chips: BB_A0 BB_B0 K2
30784 #define DMAE_REG_GO_C31                                                                              0x00c0c4UL //Access:RW   DataWidth:0x1   Command 31 go.  Chips: BB_A0 BB_B0 K2
30785 #define DMAE_REG_INT_STS                                                                             0x00c180UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30786     #define DMAE_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
30787     #define DMAE_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
30788     #define DMAE_REG_INT_STS_PCI_RD_BUF_ERR                                                          (0x1<<1) // PCI read buffer error.
30789     #define DMAE_REG_INT_STS_PCI_RD_BUF_ERR_SHIFT                                                    1
30790 #define DMAE_REG_INT_MASK                                                                            0x00c184UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30791     #define DMAE_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: DMAE_REG_INT_STS.ADDRESS_ERROR .
30792     #define DMAE_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
30793     #define DMAE_REG_INT_MASK_PCI_RD_BUF_ERR                                                         (0x1<<1) // This bit masks, when set, the Interrupt bit: DMAE_REG_INT_STS.PCI_RD_BUF_ERR .
30794     #define DMAE_REG_INT_MASK_PCI_RD_BUF_ERR_SHIFT                                                   1
30795 #define DMAE_REG_INT_STS_WR                                                                          0x00c188UL //Access:WR   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30796     #define DMAE_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
30797     #define DMAE_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
30798     #define DMAE_REG_INT_STS_WR_PCI_RD_BUF_ERR                                                       (0x1<<1) // PCI read buffer error.
30799     #define DMAE_REG_INT_STS_WR_PCI_RD_BUF_ERR_SHIFT                                                 1
30800 #define DMAE_REG_INT_STS_CLR                                                                         0x00c18cUL //Access:RC   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30801     #define DMAE_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
30802     #define DMAE_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
30803     #define DMAE_REG_INT_STS_CLR_PCI_RD_BUF_ERR                                                      (0x1<<1) // PCI read buffer error.
30804     #define DMAE_REG_INT_STS_CLR_PCI_RD_BUF_ERR_SHIFT                                                1
30805 #define DMAE_REG_PRTY_MASK_H_0                                                                       0x00c204UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30806     #define DMAE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
30807     #define DMAE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           0
30808     #define DMAE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
30809     #define DMAE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           1
30810     #define DMAE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: DMAE_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
30811     #define DMAE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           2
30812 #define DMAE_REG_MEM_ECC_EVENTS                                                                      0x00c210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
30813 #define DMAE_REG_MEM002_I_MEM_DFT_K2                                                                 0x00c218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dmae.i_buf_ram_low.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
30814 #define DMAE_REG_MEM001_I_MEM_DFT_K2                                                                 0x00c21cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dmae.i_buf_ram_high.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
30815 #define DMAE_REG_MEM003_I_MEM_DFT_K2                                                                 0x00c220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dmae.i_cmd.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
30816 #define DMAE_REG_PXP_REQ_INIT_CRD                                                                    0x00c400UL //Access:RW   DataWidth:0x4   DMAE- PCI Request Interface initial credit. Write writes the initial value to the credit counter; related to the address. Read returns the current value of the counter.  Chips: BB_A0 BB_B0 K2
30817 #define DMAE_REG_RLXD_ORDR                                                                           0x00c404UL //Access:RW   DataWidth:0x1   Relaxed ordering. 0-strict PCI ordering is used;1-PCI-X relaxed ordering is enabled.  Chips: BB_A0 BB_B0 K2
30818 #define DMAE_REG_NO_SNOOP                                                                            0x00c408UL //Access:RW   DataWidth:0x1   0-PCI type cache snoop protection is required;1-system isn't required to cause processor cache snoop for coherency.  Chips: BB_A0 BB_B0 K2
30819 #define DMAE_REG_CRC16I_INIT                                                                         0x00c40cUL //Access:RW   DataWidth:0x1   If 0 - the CRC-16 initial value is all zeroes; if 1 - the CRC-16 initial value is all ones.  Chips: BB_A0 BB_B0 K2
30820 #define DMAE_REG_CRC16_BSWAP                                                                         0x00c410UL //Access:RW   DataWidth:0x1   If 0 - the CRC-16 final calculation result isn't byte swapped; if 1 - the CRC-16 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).  Chips: BB_A0 BB_B0 K2
30821 #define DMAE_REG_CRC16C_INIT                                                                         0x00c414UL //Access:RW   DataWidth:0x1   If 0 - the CRC-16c initial value is all zeroes; if 1 - the CRC-16c initial value is all ones.  Chips: BB_A0 BB_B0 K2
30822 #define DMAE_REG_CRC16T10_INIT                                                                       0x00c418UL //Access:RW   DataWidth:0x1   If 0 - the CRC-16 T10 initial value is all zeroes; if 1 - the CRC-16 T10 initial value is all ones.  Chips: BB_A0 BB_B0 K2
30823 #define DMAE_REG_CRC32I_INIT                                                                         0x00c41cUL //Access:RW   DataWidth:0x1   If 0 - the CRC-32 initial value is all zeroes; if 1 - the CRC-32 initial value is all ones.  Chips: BB_A0 BB_B0 K2
30824 #define DMAE_REG_CRC32I_BSWAP                                                                        0x00c420UL //Access:RW   DataWidth:0x1   If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).  Chips: BB_A0 BB_B0 K2
30825 #define DMAE_REG_CRC32C_INIT                                                                         0x00c424UL //Access:RW   DataWidth:0x1   If 0 - the CRC-32c initial value is all zeroes; if 1 - the CRC-32c initial value is all ones.  Chips: BB_A0 BB_B0 K2
30826 #define DMAE_REG_CRC32C_BSWAP                                                                        0x00c428UL //Access:RW   DataWidth:0x1   If 0 - the CRC-32c final calculation result isn't byte swapped; if 1 - the CRC-32c final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).  Chips: BB_A0 BB_B0 K2
30827 #define DMAE_REG_CHKSUM0_FIX                                                                         0x00c42cUL //Access:RW   DataWidth:0x1   If 0 - the final checksum equal 0 won't be changed;if 1 - the final checksum equal 0 will be fixed to all ones.  Chips: BB_A0 BB_B0 K2
30828 #define DMAE_REG_WR_ATC_FLAGS                                                                        0x00c430UL //Access:RW   DataWidth:0x3   Write request ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; ATC Flags[2]:0 - Low Priority;  - High Priority.  Chips: BB_A0 BB_B0 K2
30829 #define DMAE_REG_RD_ATC_FLAGS                                                                        0x00c434UL //Access:RW   DataWidth:0x3   Read request ATC Flags[1:0]: 00 - Do nothing; 01 - Search only; 10 - Search & Cache; 11 - Search & Release; ATC Flags[2]:0 - Low Priority;  - High Priority.  Chips: BB_A0 BB_B0 K2
30830 #define DMAE_REG_PCI_ERR_DISCARD_EN                                                                  0x00c438UL //Access:RW   DataWidth:0x1   When set discards 1- or 2-Dword PCI transaction read in case there is PCI error.  Chips: BB_A0 BB_B0 K2
30831 #define DMAE_REG_PCI_ERR_DISCARD_ADDR                                                                0x00c43cUL //Access:RW   DataWidth:0x14  GRC address in case 1- or 2-Dword PCI transaction is discardd due to PCI error and dmae.pci_err_discard set.  Chips: BB_A0 BB_B0 K2
30832 #define DMAE_REG_TPH_FLAGS                                                                           0x00c440UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30833     #define DMAE_REG_TPH_FLAGS_TPH_STR_TAG_INDX                                                      (0x1ff<<0) // Steering Tag Index (value of 0x1FF means no steering tag in which case steering tag will be set to 0).
30834     #define DMAE_REG_TPH_FLAGS_TPH_STR_TAG_INDX_SHIFT                                                0
30835     #define DMAE_REG_TPH_FLAGS_TPH_ST_HINT                                                           (0x3<<9) // ST hint. 00 - Bidirectional shared data structure; 01 - Device writes/reads then device reads/writes soon; 10 - Device writes then host reads soon or Device reads data that the Host is believed to have recently written; 11 - like 10 but with higher priority.
30836     #define DMAE_REG_TPH_FLAGS_TPH_ST_HINT_SHIFT                                                     9
30837     #define DMAE_REG_TPH_FLAGS_TPH_VALID                                                             (0x1<<11) // TPH valid.
30838     #define DMAE_REG_TPH_FLAGS_TPH_VALID_SHIFT                                                       11
30839 #define DMAE_REG_ECO_RESERVED                                                                        0x00c444UL //Access:RW   DataWidth:0x8   Chicken bits.  Chips: BB_A0 BB_B0 K2
30840 #define DMAE_REG_GRC_PRIVILEGE_LEVEL                                                                 0x00c448UL //Access:RW   DataWidth:0x2   GRC privilege level: generates PRV field in FID: 0 - VN Virtualized NIC (Used for VF access); 1 - PDA Physical Device Assignment (Assigned to VM-s); 2 - HV HyperVisor (Assigned to HV); 3 - UA Un-restricted Access;  Chips: BB_A0 BB_B0 K2
30841 #define DMAE_REG_FSM_ST                                                                              0x00c44cUL //Access:R    DataWidth:0x4   DMAE FSM current state.  Chips: BB_A0 BB_B0 K2
30842 #define DMAE_REG_MEMCTRL_WR_RD_N                                                                     0x00c500UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
30843 #define DMAE_REG_MEMCTRL_CMD                                                                         0x00c504UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
30844 #define DMAE_REG_MEMCTRL_ADDRESS                                                                     0x00c508UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
30845 #define DMAE_REG_MEMCTRL_STATUS                                                                      0x00c50cUL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0 K2
30846 #define DMAE_REG_DBG_SELECT                                                                          0x00c510UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
30847 #define DMAE_REG_DBG_DWORD_ENABLE                                                                    0x00c514UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
30848 #define DMAE_REG_DBG_SHIFT                                                                           0x00c518UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
30849 #define DMAE_REG_DBG_FORCE_VALID                                                                     0x00c51cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
30850 #define DMAE_REG_DBG_FORCE_FRAME                                                                     0x00c520UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
30851 #define DMAE_REG_DBG_OUT_DATA                                                                        0x00c540UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
30852 #define DMAE_REG_DBG_OUT_DATA_SIZE                                                                   8
30853 #define DMAE_REG_DBG_OUT_VALID                                                                       0x00c560UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
30854 #define DMAE_REG_DBG_OUT_FRAME                                                                       0x00c564UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
30855 #define DMAE_REG_CMD_MEM                                                                             0x00c800UL //Access:RW   DataWidth:0x20  Commands memory. The address to command X; row Y is to calculated as 14*X+Y.  Chips: BB_A0 BB_B0 K2
30856 #define DMAE_REG_CMD_MEM_SIZE                                                                        448
30857 #define DBG_REG_CLIENT_ENABLE                                                                        0x010004UL //Access:RW   DataWidth:0x13  Enable to client interfaces: Bits 0- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other engine input; 11-Timestamp client; 12-CPU client; 13-RBCY; 14-RBCQ; 15-RBCM; 16-RBCB; 17-RBCW; 18-RBCV;  Chips: BB_A0 BB_B0 K2
30858 #define DBG_REG_OTHER_CLIENT_ENABLE                                                                  0x010008UL //Access:RW   DataWidth:0x13  Enable to client interfaces for output to other engine: Bits 0- RBCN; 1- RBCP; 2-RBCR; 3- RBCT; 4- RBCU; 5- RBCF; 6- RBCX; 7- RBCS; 8-RBCH; 9-RBCZ; 10 - other engine input (bit 10 should be constnantly 0); 11-Timestamp client; 12-CPU client; 13-RBCY; 14-RBCQ; 15-RBCM; 16-RBCB; 17-RBCW; 18-RBCV;  Chips: BB_A0 BB_B0 K2
30859 #define DBG_REG_OUTPUT_ENABLE                                                                        0x01000cUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30860     #define DBG_REG_OUTPUT_ENABLE_PCI_REQ_ENABLE                                                     (0x1<<0) // Debug only:  This bit is an enable to PCI output request interface; This bit should be enabled/disabled together along with DBG_REGISTERS_OUTPUT_ENABLE.PCI_DATA_ENABLE . When DBG_REGISTERS_OUTPUT_ENABLE.NIG_ENABLE is enabled this register must be disabled.
30861     #define DBG_REG_OUTPUT_ENABLE_PCI_REQ_ENABLE_SHIFT                                               0
30862     #define DBG_REG_OUTPUT_ENABLE_PCI_DATA_ENABLE                                                    (0x1<<1) // Debug only:  This bit is an enable to PCI output data interface; This bit should be enabled/disabled together along with DBG_REGISTERS_OUTPUT_ENABLE.PCI_REQ_ENABLE . When DBG_REGISTERS_OUTPUT_ENABLE.NIG_ENABLE is enabled this register must be disabled.
30863     #define DBG_REG_OUTPUT_ENABLE_PCI_DATA_ENABLE_SHIFT                                              1
30864     #define DBG_REG_OUTPUT_ENABLE_NIG_ENABLE                                                         (0x1<<2) // Debug only:  This bit is an enable to NIG output data interface. When DBG_REGISTERS_OUTPUT_ENABLE.PCI_REQ_ENABLE and DBG_REGISTERS_OUTPUT_ENABLE.PCI_DATA_ENABLE are enabled this bit should be disabled.
30865     #define DBG_REG_OUTPUT_ENABLE_NIG_ENABLE_SHIFT                                                   2
30866 #define DBG_REG_OTHER_ENGINE_MODE                                                                    0x010010UL //Access:RW   DataWidth:0x3   Working mode with the other DBG instance engine as follows: 0-NONE; 1-DoubleBwTx (DoubleBw the TX side); 2-DoubleBwRx (DoubleBw the RX side); 3-CrossEngineTx (CrossEngineTx the TX side);4-CrossEngineRx (CrossEngineRx the RX side).  Chips: BB_A0 BB_B0 K2
30867 #define DBG_REG_CALENDAR_SLOT0                                                                       0x010014UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 0 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30868 #define DBG_REG_CALENDAR_SLOT1                                                                       0x010018UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 1 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30869 #define DBG_REG_CALENDAR_SLOT2                                                                       0x01001cUL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 2 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30870 #define DBG_REG_CALENDAR_SLOT3                                                                       0x010020UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 3 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30871 #define DBG_REG_CALENDAR_SLOT4                                                                       0x010024UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 4 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30872 #define DBG_REG_CALENDAR_SLOT5                                                                       0x010028UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 5 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30873 #define DBG_REG_CALENDAR_SLOT6                                                                       0x01002cUL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 6 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30874 #define DBG_REG_CALENDAR_SLOT7                                                                       0x010030UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 7 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30875 #define DBG_REG_CALENDAR_SLOT8                                                                       0x010034UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 8 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30876 #define DBG_REG_CALENDAR_SLOT9                                                                       0x010038UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 9 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30877 #define DBG_REG_CALENDAR_SLOT10                                                                      0x01003cUL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 10 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30878 #define DBG_REG_CALENDAR_SLOT11                                                                      0x010040UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 11 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30879 #define DBG_REG_CALENDAR_SLOT12                                                                      0x010044UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 12 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30880 #define DBG_REG_CALENDAR_SLOT13                                                                      0x010048UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 13 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30881 #define DBG_REG_CALENDAR_SLOT14                                                                      0x01004cUL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 14 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30882 #define DBG_REG_CALENDAR_SLOT15                                                                      0x010050UL //Access:RW   DataWidth:0x3   Debug only: These bits are a client index for slot 15 in calendar as follows: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM; 6-7 is none.  Chips: BB_A0 BB_B0 K2
30883 #define DBG_REG_CALENDAR_PACE                                                                        0x010054UL //Access:RW   DataWidth:0x8   Debug only: This bit indicates the calendar pacing which is the number of cycles the calendar stays on the same slot before moving to the next slot to support lower rates (During the number of cycles configured in the DBG_REGISTERS_CALENDAR_PACE only one cycle can be valid).  Chips: BB_A0 BB_B0 K2
30884 #define DBG_REG_FRAMING_MODE                                                                         0x010058UL //Access:RW   DataWidth:0x3   Framing mode 0 is 128b from one STORM;  Framing mode 1 is 2 HW blocks of 32b + 64b STORM; Framing mode 2 is 3 HW blocks of 32b + 32b STORM; Framing mode 3 is 4 HW blocks of 32b; Framing mode 4 is 4 HW blocks of 64b  Chips: BB_A0 BB_B0 K2
30885 #define DBG_REG_DEBUG_TARGET                                                                         0x01005cUL //Access:RW   DataWidth:0x2   Debug only:  These bits indicates the target of the debug data:  0 - internal buffer;  1 - NIG;   2 - PCI;.  Chips: BB_A0 BB_B0 K2
30886 #define DBG_REG_FULL_MODE                                                                            0x010060UL //Access:RW   DataWidth:0x1   Debug only: This bit indicates whether data will be wrapped (oldest data is thrown) or overflowed-one shot (newest data is thrown) as follows: (a) When DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer): 1- wrap internal buffer; 0 - One Shot; b) When DBG_REGISTERS_DEBUG_TARGET =1 (NIG):  1 - constant send; 0 - One Shot; c) When DBG_REGISTERS_DEBUG_TARGET =2 (PXP): 1 - wrap host memory in PXP; 0 - One Shot;.  Chips: BB_A0 BB_B0 K2
30887 #define DBG_REG_INT_STS                                                                              0x010180UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30888     #define DBG_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
30889     #define DBG_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
30890 #define DBG_REG_INT_MASK                                                                             0x010184UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30891     #define DBG_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: DBG_REG_INT_STS.ADDRESS_ERROR .
30892     #define DBG_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
30893 #define DBG_REG_INT_STS_WR                                                                           0x010188UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30894     #define DBG_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
30895     #define DBG_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
30896 #define DBG_REG_INT_STS_CLR                                                                          0x01018cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30897     #define DBG_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
30898     #define DBG_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
30899 #define DBG_REG_PRTY_MASK_H_0                                                                        0x010204UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
30900     #define DBG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: DBG_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
30901     #define DBG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            0
30902 #define DBG_REG_MEM_ECC_EVENTS                                                                       0x010210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
30903 #define DBG_REG_MEM001_I_MEM_DFT_K2                                                                  0x010218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dbg.i_dbg_int_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
30904 #define DBG_REG_INTR_BUFFER_RD_PTR                                                                   0x010400UL //Access:R    DataWidth:0x8   Debug only: These bits indicate the value of the read pointer for the internal buffer; The read pointer describes the next address to be read from the internal buffer.  Chips: BB_A0 BB_B0 K2
30905 #define DBG_REG_INTR_BUFFER_WR_PTR                                                                   0x010404UL //Access:R    DataWidth:0x8   Debug only:  These bits indicate the value of the write pointer for the internal buffer; The write pointer describes the last address that was written to the internal buffer. An exception exists after reset when DBG_REGISTERS_INTR_BUFFER_WR_PTR is 0 until first data is written.  Chips: BB_A0 BB_B0 K2
30906 #define DBG_REG_EXT_BUFFER_RD_PTR                                                                    0x010408UL //Access:WB_R DataWidth:0x40  Debug only:   These bits indicate the value of the read pointer for the external pci buffer; relevant only when DBG_REGISTERS_DEBUG_TARGET =2 (PCI); The read pointer describes the next address to be read from the external buffer; WB Read Only (write request will not be acknowledged); (in bytes).  Chips: BB_A0 BB_B0 K2
30907 #define DBG_REG_EXT_BUFFER_RD_PTR_SIZE                                                               2
30908 #define DBG_REG_EXT_BUFFER_WR_PTR                                                                    0x010410UL //Access:WB_R DataWidth:0x40  Debug only:  These bits indicate the value of the write pointer for the external pci buffer when DBG_REGISTERS_DEBUG_TARGET =2 (PCI). It describes the next address to write to the external buffer; TARGET_PACKET_SIZE chunks counter when DBG_REGISTERS_DEBUG_TARGET =1 (NIG) and DBG_REGISTERS_FULL_MODE =0 (one-shot); WB Read Only (write request will not be acknowledged);.  Chips: BB_A0 BB_B0 K2
30909 #define DBG_REG_EXT_BUFFER_WR_PTR_SIZE                                                               2
30910 #define DBG_REG_WRAP_ON_INT_BUFFER                                                                   0x010418UL //Access:R    DataWidth:0x1   Debug only: This bit indicates wheter the internal buffer was wrapped (oldest data was thrown) Relevant only when DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer).  Chips: BB_A0 BB_B0 K2
30911 #define DBG_REG_WRAP_ON_EXT_BUFFER                                                                   0x01041cUL //Access:R    DataWidth:0x1   Debug only:  This bit indicates wheter  indicates that external buffer was wrapped (oldest data was thrown); Relevant only when DBG_REGISTERS_DEBUG_TARGET =2 (PCI) & DBG_REGISTERS_FULL_MODE =1 (wrap);.  Chips: BB_A0 BB_B0 K2
30912 #define DBG_REG_OVL_ON_INT_BUFFER                                                                    0x010420UL //Access:R    DataWidth:0x1   Debug only:  This bit indicates that the internal buffer was overflowed (newest data was thrown); Not relevant if DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer) & DBG_REGISTERS_FULL_MODE =1 (wrap);.  Chips: BB_A0 BB_B0 K2
30913 #define DBG_REG_OVL_ON_EXT_BUFFER                                                                    0x010424UL //Access:R    DataWidth:0x1   Debug only: This bit indicates that the external buffer was overflowed (newest data was thrown); Relevant only for (a) DBG_REGISTERS_DEBUG_TARGET =2 (PCI) & DBG_REGISTERS_FULL_MODE =0 (one shot); or  (b) DBG_REGISTERS_DEBUG_TARGET =1 (NIG) & DBG_REGISTERS_FULL_MODE =0 (one shot).  Chips: BB_A0 BB_B0 K2
30914 #define DBG_REG_FULL_ON_INT_BUFFER                                                                   0x010428UL //Access:R    DataWidth:0x1   Debug only:  This bit indicates that the internal buffer was filled.  Chips: BB_A0 BB_B0 K2
30915 #define DBG_REG_FULL_ON_EXT_BUFFER                                                                   0x01042cUL //Access:R    DataWidth:0x1   Debug only: This bit indicates that the external buffer was filled; Relevant only when DBG_REGISTERS_FULL_MODE =0 (one shot).  Chips: BB_A0 BB_B0 K2
30916 #define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_LSB                                                         0x010430UL //Access:RW   DataWidth:0x20  Debug only: LSB of external PCI buffer start address; MUST be configured BEFORE pci_req_credit is configured.  Chips: BB_A0 BB_B0 K2
30917 #define DBG_REG_PCI_EXT_BUFFER_STRT_ADDR_MSB                                                         0x010434UL //Access:RW   DataWidth:0x20  Debug only: MSB of external PCI buffer start address; MUST be configured BEFORE pci_req_credit is configured.  Chips: BB_A0 BB_B0 K2
30918 #define DBG_REG_PCI_EXT_BUFFER_SIZE                                                                  0x010438UL //Access:RW   DataWidth:0x18  Debug only:  These bits indicate the value of the external PCI buffer size in target_packet_size chunks  (The reset value is for 128 Mbyte buffer).  Chips: BB_A0 BB_B0 K2
30919 #define DBG_REG_NIG_DATA_LIMIT_SIZE                                                                  0x01043cUL //Access:RW   DataWidth:0x16  Debug only: These bits indicate the max value of target_packet_size data chunks sent through the NIG (The reset value is for 4M chunks of target_packet_size data byte each); Relevant only when debug_target=1 (NIG) & full_mode=0 (one-shot).  Chips: BB_A0 BB_B0 K2
30920 #define DBG_REG_PCI_REQ_CREDIT                                                                       0x010440UL //Access:RW   DataWidth:0x2   Debug only:  These bits indicate the credit  for PCI request type 4 interface; MUST be configured AFTER pci_ext_buffer_strt_addr_lsb/msb are configured.  Chips: BB_A0 BB_B0 K2
30921 #define DBG_REG_PCI_VQ_ID                                                                            0x010444UL //Access:RW   DataWidth:0x5   Debug only: This bit is a handle given to the PCI block to refer to this request.  Chips: BB_A0 BB_B0 K2
30922 #define DBG_REG_CPU_DEBUG_DATA                                                                       0x010448UL //Access:RW   DataWidth:0x20  Debug only:  These bits indicate debug data that arrives from the CPU client.  Chips: BB_A0 BB_B0 K2
30923 #define DBG_REG_CPU_DEBUG_FRAME                                                                      0x01044cUL //Access:RW   DataWidth:0x1   Debug only: This bit indicate the frame signal of the debug data that arrives from the CPU. Must be configured before cpu_debug_data is configured.  Chips: BB_A0 BB_B0 K2
30924 #define DBG_REG_CPU_TIMEOUT                                                                          0x010450UL //Access:RW   DataWidth:0x1   Debug only: Timeout operation initiated by the CPU; prior to initiating a timeout event all inputs must be disabled; Timeout signal must stay high until all data was fully sent to nig or pci and the internal buffer is empty.  Chips: BB_A0 BB_B0 K2
30925 #define DBG_REG_DBG_BLOCK_ON                                                                         0x010454UL //Access:RW   DataWidth:0x1   Debug only: This bit enables the operation of the debug block; This bit should be set upon completion of all required configuration for the dbg block and shouldn't be reset during all operational phase of the block;.  Chips: BB_A0 BB_B0 K2
30926 #define DBG_REG_NO_GRANT_ON_FULL                                                                     0x010458UL //Access:RW   DataWidth:0x1   Debug only: This bit indicate whether grant will be issued by the dbg block towards the storms in case the internal buffer is almost full as follows: (a) 1 -  no grants will be made to the storms when the internal buffer is almost full. When the buffer will be partialy freed (enough for a complete data chunk) then grant is resumed; b) 0 - grant is supplied every time the matching storms's slot is chosen disregarding the volume status of the internal buffer.  Chips: BB_A0 BB_B0 K2
30927 #define DBG_REG_FULL_BUFFER_THR                                                                      0x01045cUL //Access:RW   DataWidth:0x9   Debug only: These bits indicate the value of the internal buffer almost full threshold used for deciding when dbg_sem_buffer_full output should go high/low; holds the number of 512 bit free lines in the internal buffer under which the full would go high; not applicable when DBG_REGISTERS_DEBUG_TARGET =0 (internal buffer) and DBG_REGISTERS_FULL_MODE =1 (wrap). NOTE: When filter_enable > 0 then this register should be >= 12.  Chips: BB_A0 BB_B0 K2
30928 #define DBG_REG_PCI_LOGIC_ADDR                                                                       0x010460UL //Access:RW   DataWidth:0x1   Debug only:  This bit indicates logical/physical address in PCI request as follows:  (a) 1 - logical address; (b) 0 - physical address;.  Chips: BB_A0 BB_B0 K2
30929 #define DBG_REG_IFMUX_SELECT                                                                         0x010464UL //Access:RW   DataWidth:0x3   Debug only: Selects 32b of data, valid and frame from the input stream to internal buffer to be output to IFMUX interface. 0 - bits[31:0] 1 - bits[63:32] 2:6 - etc. 7 - bits[255:224] Note: In framing modes 0-3, the maximum value is 3.  Chips: K2
30930 #define DBG_REG_CALENDAR_OUT_DATA                                                                    0x010480UL //Access:WB_R DataWidth:0x115 Debug only: These bits indicate the value of the sop; data; frame and valid output of the calendar; The concatenation is done as follows: bits 255:0 - data; bits 259:256 - frame; bits 263:260 - valid; bits 275:264 - ID; bits 276 - SOP.  Chips: BB_A0 BB_B0 K2
30931 #define DBG_REG_CALENDAR_OUT_DATA_SIZE                                                               16
30932 #define DBG_REG_EXPECTED_PATTERN                                                                     0x0104c0UL //Access:WB   DataWidth:0x115 Debug only:  For pattern recognition usage:  These bits represent the pattern to be compared with the vector {sop[276]; id[11:0]; valid[3:0];frame[3:0]; data[255:0]}; This vector represent the debug data it's slot number and it's frame signals that are going to stored in the internal buffer; to allow recognize sop the following should be applied: trigger_enable=1 and filter_enable>0.NOTE: In order to take into consideration the SOP value set trigger_enable=1 and filter_enable>0  Chips: BB_A0 BB_B0 K2
30933 #define DBG_REG_EXPECTED_PATTERN_SIZE                                                                16
30934 #define DBG_REG_EXPECTED_PATTERN_BIT_MASK                                                            0x010500UL //Access:WB   DataWidth:0x115 Debug only: For pattern recognition usage: These bits represent a mask bit vector that refers to the DBG_REGISTERS_EXPECTED_PATTERN vector as follows:  (a) 1 - bit is masked. This bit won't be compared with the DBG_REGISTERS_EXPECTED_PATTERN referred bit;  (b) 0 - bit is enabled. This bit will be compared with the DBG_REGISTERS_EXPECTED_PATTERN reffered bit;.  Chips: BB_A0 BB_B0 K2
30935 #define DBG_REG_EXPECTED_PATTERN_BIT_MASK_SIZE                                                       16
30936 #define DBG_REG_PATTERN_RECOGNITION_DISABLE                                                          0x010540UL //Access:RW   DataWidth:0x1   Debug only: For pattern recognition usage: This bit indicates whether the pattern recognition feature is disabled/enabled as follows:   (a) 1 - disabled;  (b) 0 - enabled;.  Chips: BB_A0 BB_B0 K2
30937 #define DBG_REG_PATTERN_RECOGNITION_STORAGE_MODE                                                     0x010544UL //Access:RW   DataWidth:0x1   Debug only:  For pattern recognition usage: This bit indicates the trigger behavior of the pattern recognition feature as follows:  (a) 1 - stop debug data storgae when the expected pattern is initially recognized; (b) 0 - start debug data storage when the expected pattern is initially recognized. When pattern_recognition_filter=0 then this register must be 0  Chips: BB_A0 BB_B0 K2
30938 #define DBG_REG_PATTERN_RECOGNITION_FILTER                                                           0x010548UL //Access:RW   DataWidth:0x1   Debug only: For pattern recognition usage:  This bit indicates whether data is continously stored in the dbg block until/from pattern recognition initial event; or stored only in cycles of a pattern recognition event occurence as follows: (a) 1 - enable continuously data storage after/before first occurence of pattern recognition;  (b) 0 - enable data storage only in cycles of a pttern recognition event occurence.  Chips: BB_A0 BB_B0 K2
30939 #define DBG_REG_TRIGGER_ENABLE                                                                       0x01054cUL //Access:RW   DataWidth:0x1   (a) 0 - trigger machine is off (all data will bypass the triggering machine);  dbg_sem_trgr_evnt may be asserted in this mode. (b) 1 - trigger machine is on; before AND/OR upon trigger_event assertion data will be recorded according to the configuration of the recording mode before/upon triggering event: rcrd_on_window_pre_trgr_evnt_mode  & rcrd_on_window_post_trgr_evnt_mode.  Chips: BB_A0 BB_B0 K2
30940 #define DBG_REG_TRIGGER_INTERLEAVED_ENABLE                                                           0x010550UL //Access:RW   DataWidth:0x1   (a) 0 - triggering interleaved messages is disabled. (b) 1 - triggering interleaved messages is enabled; will be used for triggering on recorded handler messages. NOTE: (1) triggering is possible on one level depth of interleaved messages; i.e. if message B is interleaved within message A then it is ok; However if message C is interleaved within message B and message B is interleaved within message A this scenario is NOT supported. (2) when triggering interleaved messages is enabled, set trigger_enable=1 and filter_enable>0, and trigger_id_num not equal with filter_id_num (because filtering machine does not support interleaving)  Chips: BB_A0 BB_B0 K2
30941 #define DBG_REG_TRIGGER_STATE_ID_0                                                                   0x010554UL //Access:RW   DataWidth:0x3   Number of ID that should be triggerd.  Chips: BB_A0 BB_B0 K2
30942 #define DBG_REG_TRIGGER_STATE_ID_1                                                                   0x010558UL //Access:RW   DataWidth:0x3   Number of ID that should be triggerd.  Chips: BB_A0 BB_B0 K2
30943 #define DBG_REG_TRIGGER_STATE_ID_2                                                                   0x01055cUL //Access:RW   DataWidth:0x3   Number of ID that should be triggerd.  Chips: BB_A0 BB_B0 K2
30944 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_0                                                        0x010560UL //Access:RW   DataWidth:0x1   (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.  Chips: BB_A0 BB_B0 K2
30945 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_1                                                        0x010564UL //Access:RW   DataWidth:0x1   (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.  Chips: BB_A0 BB_B0 K2
30946 #define DBG_REG_TRIGGER_STATE_USE_BOTH_SETS_2                                                        0x010568UL //Access:RW   DataWidth:0x1   (a) 1 - use both constraint set0 and constraint set1 in relevant state. (b) 0 - use only constraint set0 in relevant state.  Chips: BB_A0 BB_B0 K2
30947 #define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_0                                                        0x01056cUL //Access:RW   DataWidth:0x2   Next state in the fsm triggering machine if the referred constraints set in the specified state are met.  Chips: BB_A0 BB_B0 K2
30948 #define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_1                                                        0x010570UL //Access:RW   DataWidth:0x2   Next state in the fsm triggering machine if the referred constraints set in the specified state are met.  Chips: BB_A0 BB_B0 K2
30949 #define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_2                                                        0x010574UL //Access:RW   DataWidth:0x2   Next state in the fsm triggering machine if the referred constraints set in the specified state are met.  Chips: BB_A0 BB_B0 K2
30950 #define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_3                                                        0x010578UL //Access:RW   DataWidth:0x2   Next state in the fsm triggering machine if the referred constraints set in the specified state are met.  Chips: BB_A0 BB_B0 K2
30951 #define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_4                                                        0x01057cUL //Access:RW   DataWidth:0x2   Next state in the fsm triggering machine if the referred constraints set in the specified state are met.  Chips: BB_A0 BB_B0 K2
30952 #define DBG_REG_TRIGGER_STATE_SET_NXT_STATE_5                                                        0x010580UL //Access:RW   DataWidth:0x2   Next state in the fsm triggering machine if the referred constraints set in the specified state are met.  Chips: BB_A0 BB_B0 K2
30953 #define DBG_REG_TRIGGER_STATE_SET_COUNT_0                                                            0x010584UL //Access:RW   DataWidth:0x10  Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.  Chips: BB_A0 BB_B0 K2
30954 #define DBG_REG_TRIGGER_STATE_SET_COUNT_1                                                            0x010588UL //Access:RW   DataWidth:0x10  Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.  Chips: BB_A0 BB_B0 K2
30955 #define DBG_REG_TRIGGER_STATE_SET_COUNT_2                                                            0x01058cUL //Access:RW   DataWidth:0x10  Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.  Chips: BB_A0 BB_B0 K2
30956 #define DBG_REG_TRIGGER_STATE_SET_COUNT_3                                                            0x010590UL //Access:RW   DataWidth:0x10  Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.  Chips: BB_A0 BB_B0 K2
30957 #define DBG_REG_TRIGGER_STATE_SET_COUNT_4                                                            0x010594UL //Access:RW   DataWidth:0x10  Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.  Chips: BB_A0 BB_B0 K2
30958 #define DBG_REG_TRIGGER_STATE_SET_COUNT_5                                                            0x010598UL //Access:RW   DataWidth:0x10  Number of times that the referred constraints set should be met prior to recognition (moving to next state). NOTE: value of 0 is NA.  Chips: BB_A0 BB_B0 K2
30959 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_0                                                       0x01059cUL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30960 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_1                                                       0x0105a0UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30961 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_2                                                       0x0105a4UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30962 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_3                                                       0x0105a8UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30963 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_4                                                       0x0105acUL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30964 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_5                                                       0x0105b0UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30965 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_6                                                       0x0105b4UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30966 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_7                                                       0x0105b8UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30967 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_8                                                       0x0105bcUL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30968 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_9                                                       0x0105c0UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30969 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_10                                                      0x0105c4UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30970 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_11                                                      0x0105c8UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30971 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_12                                                      0x0105ccUL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30972 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_13                                                      0x0105d0UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30973 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_14                                                      0x0105d4UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30974 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_15                                                      0x0105d8UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30975 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_16                                                      0x0105dcUL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30976 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_17                                                      0x0105e0UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30977 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_18                                                      0x0105e4UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30978 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_19                                                      0x0105e8UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30979 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_20                                                      0x0105ecUL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30980 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_21                                                      0x0105f0UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30981 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_22                                                      0x0105f4UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30982 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_23                                                      0x0105f8UL //Access:RW   DataWidth:0x20  The data that need to be compared. The 32 bit vector is determined as follows: (a) data[31:0] - if trigger_state_set_cnstr_offseti[1:0] = 0  OR (b) data[63:32] - if trigger_state_set_cnstr_offseti[1:0] = 1 OR (c) data[95:64] - if trigger_state_set_cnstr_offseti[1:0] = 2  OR  (d) data[127:96] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30983 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_0                                                      0x0105fcUL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30984 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_1                                                      0x010600UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30985 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_2                                                      0x010604UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30986 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_3                                                      0x010608UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30987 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_4                                                      0x01060cUL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30988 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_5                                                      0x010610UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30989 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_6                                                      0x010614UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30990 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_7                                                      0x010618UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30991 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_8                                                      0x01061cUL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30992 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_9                                                      0x010620UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30993 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_10                                                     0x010624UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30994 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_11                                                     0x010628UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30995 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_12                                                     0x01062cUL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30996 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_13                                                     0x010630UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30997 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_14                                                     0x010634UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30998 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_15                                                     0x010638UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
30999 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_16                                                     0x01063cUL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31000 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_17                                                     0x010640UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31001 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_18                                                     0x010644UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31002 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_19                                                     0x010648UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31003 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_20                                                     0x01064cUL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31004 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_21                                                     0x010650UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31005 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_22                                                     0x010654UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31006 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_23                                                     0x010658UL //Access:RW   DataWidth:0x1   The frame that need to be compared. The 1 bit vector is determined as follows:  (a) frame[0] - if trigger_state_set_cnstr_offseti[1:0] = 0 OR  (b) frame[1] - if trigger_state_set_cnstr_offseti[1:0] = 1  OR (c) frame[2] - if trigger_state_set_cnstr_offseti[1:0] = 2 OR (d) frame[3] - if trigger_state_set_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31007 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_0                                                  0x01065cUL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31008 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_1                                                  0x010660UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31009 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_2                                                  0x010664UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31010 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_3                                                  0x010668UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31011 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_4                                                  0x01066cUL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31012 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_5                                                  0x010670UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31013 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_6                                                  0x010674UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31014 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_7                                                  0x010678UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31015 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_8                                                  0x01067cUL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31016 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_9                                                  0x010680UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31017 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_10                                                 0x010684UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31018 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_11                                                 0x010688UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31019 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_12                                                 0x01068cUL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31020 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_13                                                 0x010690UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31021 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_14                                                 0x010694UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31022 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_15                                                 0x010698UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31023 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_16                                                 0x01069cUL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31024 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_17                                                 0x0106a0UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31025 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_18                                                 0x0106a4UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31026 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_19                                                 0x0106a8UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31027 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_20                                                 0x0106acUL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31028 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_21                                                 0x0106b0UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31029 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_22                                                 0x0106b4UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31030 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_DATA_MASK_23                                                 0x0106b8UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not equal operations (trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31031 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_0                                                 0x0106bcUL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31032 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_1                                                 0x0106c0UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31033 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_2                                                 0x0106c4UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31034 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_3                                                 0x0106c8UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31035 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_4                                                 0x0106ccUL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31036 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_5                                                 0x0106d0UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31037 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_6                                                 0x0106d4UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31038 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_7                                                 0x0106d8UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31039 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_8                                                 0x0106dcUL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31040 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_9                                                 0x0106e0UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31041 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_10                                                0x0106e4UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31042 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_11                                                0x0106e8UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31043 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_12                                                0x0106ecUL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31044 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_13                                                0x0106f0UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31045 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_14                                                0x0106f4UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31046 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_15                                                0x0106f8UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31047 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_16                                                0x0106fcUL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31048 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_17                                                0x010700UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31049 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_18                                                0x010704UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31050 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_19                                                0x010708UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31051 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_20                                                0x01070cUL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31052 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_21                                                0x010710UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31053 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_22                                                0x010714UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31054 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_FRAME_MASK_23                                                0x010718UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 - the frame is compared; the mask is valid only for the equal and not equal operation s(trigger_state_set_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31055 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_0                                                      0x01071cUL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31056 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_1                                                      0x010720UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31057 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_2                                                      0x010724UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31058 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_3                                                      0x010728UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31059 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_4                                                      0x01072cUL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31060 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_5                                                      0x010730UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31061 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_6                                                      0x010734UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31062 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_7                                                      0x010738UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31063 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_8                                                      0x01073cUL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31064 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_9                                                      0x010740UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31065 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_10                                                     0x010744UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31066 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_11                                                     0x010748UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31067 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_12                                                     0x01074cUL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31068 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_13                                                     0x010750UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31069 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_14                                                     0x010754UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31070 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_15                                                     0x010758UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31071 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_16                                                     0x01075cUL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31072 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_17                                                     0x010760UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31073 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_18                                                     0x010764UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31074 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_19                                                     0x010768UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31075 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_20                                                     0x01076cUL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31076 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_21                                                     0x010770UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31077 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_22                                                     0x010774UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31078 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OPRTN_23                                                     0x010778UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and trigger_state_set_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<);  (c) 010 - smaller or equal (<=); (d) 011 greater or equal (>=);   (e) 100 = greater than (>); (f) 101 = not equal (!=).  Chips: BB_A0 BB_B0 K2
31079 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0                                                      0x01077cUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31080     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_0            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31081     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_0_SHIFT      0
31082     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_0              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31083     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_0_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_0_SHIFT        5
31084 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1                                                      0x010780UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31085     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_1            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31086     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_1_SHIFT      0
31087     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_1              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31088     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_1_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_1_SHIFT        5
31089 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2                                                      0x010784UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31090     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_2            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31091     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_2_SHIFT      0
31092     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_2              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31093     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_2_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_2_SHIFT        5
31094 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3                                                      0x010788UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31095     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_3            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31096     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_3_SHIFT      0
31097     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_3              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31098     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_3_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_3_SHIFT        5
31099 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4                                                      0x01078cUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31100     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_4            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31101     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_4_SHIFT      0
31102     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_4              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31103     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_4_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_4_SHIFT        5
31104 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5                                                      0x010790UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31105     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_5            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31106     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_5_SHIFT      0
31107     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_5              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31108     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_5_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_5_SHIFT        5
31109 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6                                                      0x010794UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31110     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_6            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31111     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_6_SHIFT      0
31112     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_6              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31113     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_6_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_6_SHIFT        5
31114 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7                                                      0x010798UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31115     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_7            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31116     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_7_SHIFT      0
31117     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_7              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31118     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_7_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_7_SHIFT        5
31119 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8                                                      0x01079cUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31120     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_8            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31121     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_8_SHIFT      0
31122     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_8              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31123     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_8_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_8_SHIFT        5
31124 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9                                                      0x0107a0UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31125     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_9            (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31126     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_9_SHIFT      0
31127     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_9              (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31128     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_9_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_9_SHIFT        5
31129 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10                                                     0x0107a4UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31130     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_10          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31131     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_10_SHIFT    0
31132     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_10            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31133     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_10_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_10_SHIFT      5
31134 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11                                                     0x0107a8UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31135     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_11          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31136     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_11_SHIFT    0
31137     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_11            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31138     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_11_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_11_SHIFT      5
31139 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12                                                     0x0107acUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31140     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_12          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31141     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_12_SHIFT    0
31142     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_12            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31143     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_12_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_12_SHIFT      5
31144 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13                                                     0x0107b0UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31145     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_13          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31146     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_13_SHIFT    0
31147     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_13            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31148     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_13_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_13_SHIFT      5
31149 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14                                                     0x0107b4UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31150     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_14          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31151     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_14_SHIFT    0
31152     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_14            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31153     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_14_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_14_SHIFT      5
31154 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15                                                     0x0107b8UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31155     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_15          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31156     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_15_SHIFT    0
31157     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_15            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31158     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_15_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_15_SHIFT      5
31159 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16                                                     0x0107bcUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31160     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_16          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31161     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_16_SHIFT    0
31162     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_16            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31163     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_16_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_16_SHIFT      5
31164 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17                                                     0x0107c0UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31165     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_17          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31166     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_17_SHIFT    0
31167     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_17            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31168     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_17_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_17_SHIFT      5
31169 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18                                                     0x0107c4UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31170     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_18          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31171     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_18_SHIFT    0
31172     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_18            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31173     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_18_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_18_SHIFT      5
31174 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19                                                     0x0107c8UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31175     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_19          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31176     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_19_SHIFT    0
31177     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_19            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31178     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_19_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_19_SHIFT      5
31179 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20                                                     0x0107ccUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31180     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_20          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31181     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_20_SHIFT    0
31182     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_20            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31183     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_20_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_20_SHIFT      5
31184 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21                                                     0x0107d0UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31185     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_21          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31186     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_21_SHIFT    0
31187     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_21            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31188     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_21_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_21_SHIFT      5
31189 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22                                                     0x0107d4UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31190     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_22          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31191     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_22_SHIFT    0
31192     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_22            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31193     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_22_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_22_SHIFT      5
31194 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23                                                     0x0107d8UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31195     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_23          (0x1f<<0) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31196     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23_TRIGGER_STATE_SET_CNSTR_RANGE_WIDTH_23_SHIFT    0
31197     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_23            (0x1f<<5) // If the comparison operation is not (equal or not equal) (trigger_state_set_cnstr_oprtni>000 or 101) than apply the operation on a field of width trigger_state_set_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit trigger_state_set_cnstr_range_lsb (values: 0..31) of the actual coming data;   For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and trigger_state_set_cnstr_datai =0x3f and trigger_state_set_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31198     #define DBG_REG_TRIGGER_STATE_SET_CNSTR_RANGE_23_TRIGGER_STATE_SET_CNSTR_RANGE_LSB_23_SHIFT      5
31199 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_0                                                     0x0107dcUL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31200 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_1                                                     0x0107e0UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31201 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_2                                                     0x0107e4UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31202 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_3                                                     0x0107e8UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31203 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_4                                                     0x0107ecUL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31204 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_5                                                     0x0107f0UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31205 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_6                                                     0x0107f4UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31206 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_7                                                     0x0107f8UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31207 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_8                                                     0x0107fcUL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31208 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_9                                                     0x010800UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31209 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_10                                                    0x010804UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31210 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_11                                                    0x010808UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31211 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_12                                                    0x01080cUL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31212 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_13                                                    0x010810UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31213 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_14                                                    0x010814UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31214 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_15                                                    0x010818UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31215 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_16                                                    0x01081cUL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31216 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_17                                                    0x010820UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31217 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_18                                                    0x010824UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31218 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_19                                                    0x010828UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31219 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_20                                                    0x01082cUL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31220 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_21                                                    0x010830UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31221 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_22                                                    0x010834UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31222 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_OFFSET_23                                                    0x010838UL //Access:RW   DataWidth:0xa   The above value vector (data & frame) should be compared trigger_state_set_cnstr_offseti / 4 cycles after start of message.  Chips: BB_A0 BB_B0 K2
31223 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_0                                                       0x01083cUL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31224 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_1                                                       0x010840UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31225 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_2                                                       0x010844UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31226 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_3                                                       0x010848UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31227 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_4                                                       0x01084cUL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31228 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_5                                                       0x010850UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31229 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_6                                                       0x010854UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31230 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_7                                                       0x010858UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31231 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_8                                                       0x01085cUL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31232 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_9                                                       0x010860UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31233 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_10                                                      0x010864UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31234 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_11                                                      0x010868UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31235 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_12                                                      0x01086cUL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31236 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_13                                                      0x010870UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31237 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_14                                                      0x010874UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31238 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_15                                                      0x010878UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31239 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_16                                                      0x01087cUL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31240 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_17                                                      0x010880UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31241 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_18                                                      0x010884UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31242 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_19                                                      0x010888UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31243 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_20                                                      0x01088cUL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31244 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_21                                                      0x010890UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31245 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_22                                                      0x010894UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31246 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_MUST_23                                                      0x010898UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector must exist as part of the message. (b) 0: the above value vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31247 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_0                                                     0x01089cUL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31248 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_1                                                     0x0108a0UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31249 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_2                                                     0x0108a4UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31250 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_3                                                     0x0108a8UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31251 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_4                                                     0x0108acUL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31252 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_5                                                     0x0108b0UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31253 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_6                                                     0x0108b4UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31254 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_7                                                     0x0108b8UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31255 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_8                                                     0x0108bcUL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31256 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_9                                                     0x0108c0UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31257 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_10                                                    0x0108c4UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31258 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_11                                                    0x0108c8UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31259 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_12                                                    0x0108ccUL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31260 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_13                                                    0x0108d0UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31261 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_14                                                    0x0108d4UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31262 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_15                                                    0x0108d8UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31263 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_16                                                    0x0108dcUL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31264 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_17                                                    0x0108e0UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31265 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_18                                                    0x0108e4UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31266 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_19                                                    0x0108e8UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31267 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_20                                                    0x0108ecUL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31268 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_21                                                    0x0108f0UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31269 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_22                                                    0x0108f4UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31270 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_INDRCT_23                                                    0x0108f8UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the trigger_state_set_cnstr_datai.  (b) 01: indirect: use the recorded value from of fsm triggering machine (trigger_indirect0_recorded_data).  (c) 10: indirect: use the recorded value from of fsm triggering machine (trigger_indirect1_recorded_data).  Chips: BB_A0 BB_B0 K2
31271 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_0                                                     0x0108fcUL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31272 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_1                                                     0x010900UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31273 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_2                                                     0x010904UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31274 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_3                                                     0x010908UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31275 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_4                                                     0x01090cUL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31276 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_5                                                     0x010910UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31277 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_6                                                     0x010914UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31278 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_7                                                     0x010918UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b operation is NOT equal (trigger_state_set_cnstr_oprtni > 0)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31279 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_8                                                     0x01091cUL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31280 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_9                                                     0x010920UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31281 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_10                                                    0x010924UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31282 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_11                                                    0x010928UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31283 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_12                                                    0x01092cUL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31284 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_13                                                    0x010930UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31285 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_14                                                    0x010934UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31286 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_15                                                    0x010938UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31287 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_16                                                    0x01093cUL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31288 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_17                                                    0x010940UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31289 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_18                                                    0x010944UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31290 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_19                                                    0x010948UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31291 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_20                                                    0x01094cUL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31292 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_21                                                    0x010950UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31293 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_22                                                    0x010954UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31294 #define DBG_REG_TRIGGER_STATE_SET_CNSTR_CYCLIC_23                                                    0x010958UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal) (trigger_state_set_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0  (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31295 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_0                                                    0x01095cUL //Access:RW   DataWidth:0x1   (a) 1: use trigger_state_msg_lengthi  to determine message boundary. (b) 0: use masking according to trigger_state_id only.  Chips: BB_A0 BB_B0 K2
31296 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_1                                                    0x010960UL //Access:RW   DataWidth:0x1   (a) 1: use trigger_state_msg_lengthi  to determine message boundary. (b) 0: use masking according to trigger_state_id only.  Chips: BB_A0 BB_B0 K2
31297 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_ENABLE_2                                                    0x010964UL //Access:RW   DataWidth:0x1   (a) 1: use trigger_state_msg_lengthi  to determine message boundary. (b) 0: use masking according to trigger_state_id only.  Chips: BB_A0 BB_B0 K2
31298 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_0                                                           0x010968UL //Access:RW   DataWidth:0x8   Message length-1  in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc.   (c) Applicable only when trigger_state_msg_length_eni = 1.  Chips: BB_A0 BB_B0 K2
31299 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_1                                                           0x01096cUL //Access:RW   DataWidth:0x8   Message length-1  in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc.   (c) Applicable only when trigger_state_msg_length_eni = 1.  Chips: BB_A0 BB_B0 K2
31300 #define DBG_REG_TRIGGER_STATE_MSG_LENGTH_2                                                           0x010970UL //Access:RW   DataWidth:0x8   Message length-1  in terms of numbers of 128-bit cycles. NOTE: (a) if for example trigger_state_msg_lengthi=0 then Message length = 1 cycle. (b) if for example trigger_state_msg_lengthi=1 then Message length = 2 cycles. etc.   (c) Applicable only when trigger_state_msg_length_eni = 1.  Chips: BB_A0 BB_B0 K2
31301 #define DBG_REG_TRIGGER_EVENT                                                                        0x010974UL //Access:R    DataWidth:0x1   Configured messages sequencing was identified.  Chips: BB_A0 BB_B0 K2
31302 #define DBG_REG_TRIGGER_INDIRECT0_STATE                                                              0x010978UL //Access:RW   DataWidth:0x3   If set then record data in relevant state;  If clear then do not record data in relevant state;    b0: state0; b1: state1; b2: state2;.  Chips: BB_A0 BB_B0 K2
31303 #define DBG_REG_TRIGGER_INDIRECT0_OFFSET_0                                                           0x01097cUL //Access:RW   DataWidth:0xa   The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect0_offseti from the last message will be recorded.   NOTE: offset[1:0] is used inside 128-bit row offset as following: 0 -for 32 LSB bits; 1- for bits 63:32; 2- or bits 95:64; 3- for 32 MSB bits. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.  Chips: BB_A0 BB_B0 K2
31304 #define DBG_REG_TRIGGER_INDIRECT0_OFFSET_1                                                           0x010980UL //Access:RW   DataWidth:0xa   The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect0_offseti from the last message will be recorded.   NOTE: offset[1:0] is used inside 128-bit row offset as following: 0 -for 32 LSB bits; 1- for bits 63:32; 2- or bits 95:64; 3- for 32 MSB bits. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.  Chips: BB_A0 BB_B0 K2
31305 #define DBG_REG_TRIGGER_INDIRECT0_OFFSET_2                                                           0x010984UL //Access:RW   DataWidth:0xa   The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage. If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect0_offseti from the last message will be recorded.   NOTE: offset[1:0] is used inside 128-bit row offset as following: 0 -for 32 LSB bits; 1- for bits 63:32; 2- or bits 95:64; 3- for 32 MSB bits. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.  Chips: BB_A0 BB_B0 K2
31306 #define DBG_REG_TRIGGER_INDIRECT0_SHIFT_0                                                            0x010988UL //Access:RW   DataWidth:0x5   Shift vector (bit resolution) for the data trigger_indirect0_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.  Chips: BB_A0 BB_B0 K2
31307 #define DBG_REG_TRIGGER_INDIRECT0_SHIFT_1                                                            0x01098cUL //Access:RW   DataWidth:0x5   Shift vector (bit resolution) for the data trigger_indirect0_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.  Chips: BB_A0 BB_B0 K2
31308 #define DBG_REG_TRIGGER_INDIRECT0_SHIFT_2                                                            0x010990UL //Access:RW   DataWidth:0x5   Shift vector (bit resolution) for the data trigger_indirect0_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.  Chips: BB_A0 BB_B0 K2
31309 #define DBG_REG_TRIGGER_INDIRECT0_MASK_0                                                             0x010994UL //Access:RW   DataWidth:0x20  If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).  Chips: BB_A0 BB_B0 K2
31310 #define DBG_REG_TRIGGER_INDIRECT0_MASK_1                                                             0x010998UL //Access:RW   DataWidth:0x20  If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).  Chips: BB_A0 BB_B0 K2
31311 #define DBG_REG_TRIGGER_INDIRECT0_MASK_2                                                             0x01099cUL //Access:RW   DataWidth:0x20  If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data. NOTE: (a) Mask is implemented prior to registering the recorded data to trigger_indirect0_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).  Chips: BB_A0 BB_B0 K2
31312 #define DBG_REG_TRIGGER_INDIRECT0_RECORDED_DATA                                                      0x0109a0UL //Access:R    DataWidth:0x20  The data that was recorded trigger_indirect0_offset cycles after start of message (during triggering machine operation in state trigger_indirect0_state); NOTE: CID recording for filtering purpose within the sem must use this register (and NOT trigger_indirect1_recorded_data register).  Chips: BB_A0 BB_B0 K2
31313 #define DBG_REG_TRIGGER_INDIRECT1_STATE                                                              0x0109a4UL //Access:RW   DataWidth:0x3   If set then record data in relevant state;  If clear then do not record data in relevant state; b0: state0; b1: state1; b2: state2;.  Chips: BB_A0 BB_B0 K2
31314 #define DBG_REG_TRIGGER_INDIRECT1_OFFSET_0                                                           0x0109a8UL //Access:RW   DataWidth:0xa   The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage.  If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect1_offseti from the last message will be recorded.  NOTE: offset[1:0] is used inside 128-bit row offset as following: 0 -for 32 LSB bits; 1- for bits 63:32; 2- or bits 95:64; 3- for 32 MSB bits. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.  Chips: BB_A0 BB_B0 K2
31315 #define DBG_REG_TRIGGER_INDIRECT1_OFFSET_1                                                           0x0109acUL //Access:RW   DataWidth:0xa   The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage.  If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect1_offseti from the last message will be recorded.  NOTE: offset[1:0] is used inside 128-bit row offset as following: 0 -for 32 LSB bits; 1- for bits 63:32; 2- or bits 95:64; 3- for 32 MSB bits. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.  Chips: BB_A0 BB_B0 K2
31316 #define DBG_REG_TRIGGER_INDIRECT1_OFFSET_2                                                           0x0109b0UL //Access:RW   DataWidth:0xa   The offset in relevant state (fsm triggering machine) from beginning of message to the data that should be recorded for indirect value usage.  If set of constraints appear more than once (trigger_state_set_counti >1) then cycle trigger_indirect1_offseti from the last message will be recorded.  NOTE: offset[1:0] is used inside 128-bit row offset as following: 0 -for 32 LSB bits; 1- for bits 63:32; 2- or bits 95:64; 3- for 32 MSB bits. For example offset=0 is for 128-bit cycle 0 for the 32 lsb; offset=1 is for 128-bit cycle 0 for the bits 63:32; offset=4N is for 128-bit cycle N for the 32 lsb; offset=4N+2 is for 128-bit cycle N for the bits 95:64.  Chips: BB_A0 BB_B0 K2
31317 #define DBG_REG_TRIGGER_INDIRECT1_SHIFT_0                                                            0x0109b4UL //Access:RW   DataWidth:0x5   Shift vector (bit resolution) for the data trigger_indirect1_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.  Chips: BB_A0 BB_B0 K2
31318 #define DBG_REG_TRIGGER_INDIRECT1_SHIFT_1                                                            0x0109b8UL //Access:RW   DataWidth:0x5   Shift vector (bit resolution) for the data trigger_indirect1_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.  Chips: BB_A0 BB_B0 K2
31319 #define DBG_REG_TRIGGER_INDIRECT1_SHIFT_2                                                            0x0109bcUL //Access:RW   DataWidth:0x5   Shift vector (bit resolution) for the data trigger_indirect1_recorded_data  The shift is implemented after the recording (after the registering) of the indirect register is implemented. The comparison with the actual coming data is implemented on the shifted data.  Chips: BB_A0 BB_B0 K2
31320 #define DBG_REG_TRIGGER_INDIRECT1_MASK_0                                                             0x0109c0UL //Access:RW   DataWidth:0x20  If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data.  NOTE:  (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).  Chips: BB_A0 BB_B0 K2
31321 #define DBG_REG_TRIGGER_INDIRECT1_MASK_1                                                             0x0109c4UL //Access:RW   DataWidth:0x20  If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data.  NOTE:  (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).  Chips: BB_A0 BB_B0 K2
31322 #define DBG_REG_TRIGGER_INDIRECT1_MASK_2                                                             0x0109c8UL //Access:RW   DataWidth:0x20  If set then the relevant bit will be zeroed; if clear then the relevant bit will be registered with its exact data.  NOTE:  (a) Mask is implemented prior to registering the recorded data to trigger_indirect1_recorded_data; (b) The mask is implemented in bit resolution. (c) useful when trigger_state_set_cnstr_oprtni is in (>/</=</=>).  Chips: BB_A0 BB_B0 K2
31323 #define DBG_REG_TRIGGER_INDIRECT1_RECORDED_DATA                                                      0x0109ccUL //Access:R    DataWidth:0x20  The data that was recorded trigger_indirect1_offset cycles after start of message (during triggering machine operation in state trigger_indirect0_state);.  Chips: BB_A0 BB_B0 K2
31324 #define DBG_REG_FILTER_ENABLE                                                                        0x0109d0UL //Access:RW   DataWidth:0x2   (a) 00 - Filter off; in that case all data should be transmitted to the internal buffer without any filtering implemented (data should bypass filtering machine). (b) 01 - Filter on prior (in time domain) to trigger_event (asserted by the triggering machine block) only; When off (after trigger event) - data should be transmitted to the internal buffer without any filtering. in this mode trigger_enable must be set.  (c) 10 - Filter on upon trigger_event (asserted by the triggering machine) only. When off (before trigger event) - data should be transmitted to the internal buffer without any filtering. in this mode trigger_enable must be set. (d) 11 - Filter on - constant filtering; in this case the triggering event (asserted by the triggering machine) is irrelevant.  Chips: BB_A0 BB_B0 K2
31325 #define DBG_REG_FILTER_ID_NUM                                                                        0x0109d4UL //Access:RW   DataWidth:0x3   Number of ID that should be filtered.  Chips: BB_A0 BB_B0 K2
31326 #define DBG_REG_FILTER_CNSTR_DATA_0                                                                  0x0109d8UL //Access:RW   DataWidth:0x20  The value that need to be compared.  (a) data[31:0] - if filter_cnstr_offseti[1:0] = 0; OR  (b) data[63:32] - if filter_cnstr_offseti[1:0] = 1; OR (c) data[95:64] - if filter_cnstr_offseti[1:0] = 2; OR (d) data[127:96] - if filter_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31327 #define DBG_REG_FILTER_CNSTR_DATA_1                                                                  0x0109dcUL //Access:RW   DataWidth:0x20  The value that need to be compared.  (a) data[31:0] - if filter_cnstr_offseti[1:0] = 0; OR  (b) data[63:32] - if filter_cnstr_offseti[1:0] = 1; OR (c) data[95:64] - if filter_cnstr_offseti[1:0] = 2; OR (d) data[127:96] - if filter_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31328 #define DBG_REG_FILTER_CNSTR_DATA_2                                                                  0x0109e0UL //Access:RW   DataWidth:0x20  The value that need to be compared.  (a) data[31:0] - if filter_cnstr_offseti[1:0] = 0; OR  (b) data[63:32] - if filter_cnstr_offseti[1:0] = 1; OR (c) data[95:64] - if filter_cnstr_offseti[1:0] = 2; OR (d) data[127:96] - if filter_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31329 #define DBG_REG_FILTER_CNSTR_DATA_3                                                                  0x0109e4UL //Access:RW   DataWidth:0x20  The value that need to be compared.  (a) data[31:0] - if filter_cnstr_offseti[1:0] = 0; OR  (b) data[63:32] - if filter_cnstr_offseti[1:0] = 1; OR (c) data[95:64] - if filter_cnstr_offseti[1:0] = 2; OR (d) data[127:96] - if filter_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31330 #define DBG_REG_FILTER_CNSTR_FRAME_0                                                                 0x0109e8UL //Access:RW   DataWidth:0x1   The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[1:0] = 0; OR  (b) frame[1] - if filter_cnstr_offseti[1:0] = 1; OR (a) frame[2] - if filter_cnstr_offseti[1:0] = 2; OR  (b) frame[3] - if filter_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31331 #define DBG_REG_FILTER_CNSTR_FRAME_1                                                                 0x0109ecUL //Access:RW   DataWidth:0x1   The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[1:0] = 0; OR  (b) frame[1] - if filter_cnstr_offseti[1:0] = 1; OR (a) frame[2] - if filter_cnstr_offseti[1:0] = 2; OR  (b) frame[3] - if filter_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31332 #define DBG_REG_FILTER_CNSTR_FRAME_2                                                                 0x0109f0UL //Access:RW   DataWidth:0x1   The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[1:0] = 0; OR  (b) frame[1] - if filter_cnstr_offseti[1:0] = 1; OR (a) frame[2] - if filter_cnstr_offseti[1:0] = 2; OR  (b) frame[3] - if filter_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31333 #define DBG_REG_FILTER_CNSTR_FRAME_3                                                                 0x0109f4UL //Access:RW   DataWidth:0x1   The value that need to be compared. (a) frame[0] - if filter_cnstr_offseti[1:0] = 0; OR  (b) frame[1] - if filter_cnstr_offseti[1:0] = 1; OR (a) frame[2] - if filter_cnstr_offseti[1:0] = 2; OR  (b) frame[3] - if filter_cnstr_offseti[1:0] = 3.  Chips: BB_A0 BB_B0 K2
31334 #define DBG_REG_FILTER_CNSTR_DATA_MASK_0                                                             0x0109f8UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not operation (filter_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31335 #define DBG_REG_FILTER_CNSTR_DATA_MASK_1                                                             0x0109fcUL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not operation (filter_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31336 #define DBG_REG_FILTER_CNSTR_DATA_MASK_2                                                             0x010a00UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not operation (filter_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31337 #define DBG_REG_FILTER_CNSTR_DATA_MASK_3                                                             0x010a04UL //Access:RW   DataWidth:0x20  If specific bit is 1 then the matched bit in the above data vector is masked (not compared); the mask is valid only for the equal and not operation (filter_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31338 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_0                                                            0x010a08UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 -  the frame is compared; NOTE:  The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31339 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_1                                                            0x010a0cUL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 -  the frame is compared; NOTE:  The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31340 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_2                                                            0x010a10UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 -  the frame is compared; NOTE:  The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31341 #define DBG_REG_FILTER_CNSTR_FRAME_MASK_3                                                            0x010a14UL //Access:RW   DataWidth:0x1   (a) 1 - the frame is masked (not compared); (b) 0 -  the frame is compared; NOTE:  The mask is valid only for the equal and not equal operations (trigger_cnstr_oprtni=000 and 101); i.e. not valid for </<=/>=/>.  Chips: BB_A0 BB_B0 K2
31342 #define DBG_REG_FILTER_CNSTR_OFFSET_0                                                                0x010a18UL //Access:RW   DataWidth:0x4   The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti/4 cycles after start of message; valid values: 0..15. 2 lsbs represent the dword offset within a cycle.  Chips: BB_A0 BB_B0 K2
31343 #define DBG_REG_FILTER_CNSTR_OFFSET_1                                                                0x010a1cUL //Access:RW   DataWidth:0x4   The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti/4 cycles after start of message; valid values: 0..15. 2 lsbs represent the dword offset within a cycle.  Chips: BB_A0 BB_B0 K2
31344 #define DBG_REG_FILTER_CNSTR_OFFSET_2                                                                0x010a20UL //Access:RW   DataWidth:0x4   The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti/4 cycles after start of message; valid values: 0..15. 2 lsbs represent the dword offset within a cycle.  Chips: BB_A0 BB_B0 K2
31345 #define DBG_REG_FILTER_CNSTR_OFFSET_3                                                                0x010a24UL //Access:RW   DataWidth:0x4   The filtering is implemented according to the data on the first 4 cycles only. The above value vector (data and frame) should be compared filter_cnstr_offseti/4 cycles after start of message; valid values: 0..15. 2 lsbs represent the dword offset within a cycle.  Chips: BB_A0 BB_B0 K2
31346 #define DBG_REG_FILTER_CNSTR_OPRTN_0                                                                 0x010a28UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>); (f) 101 = not equal (!=);.  Chips: BB_A0 BB_B0 K2
31347 #define DBG_REG_FILTER_CNSTR_OPRTN_1                                                                 0x010a2cUL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>); (f) 101 = not equal (!=);.  Chips: BB_A0 BB_B0 K2
31348 #define DBG_REG_FILTER_CNSTR_OPRTN_2                                                                 0x010a30UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>); (f) 101 = not equal (!=);.  Chips: BB_A0 BB_B0 K2
31349 #define DBG_REG_FILTER_CNSTR_OPRTN_3                                                                 0x010a34UL //Access:RW   DataWidth:0x3   The comparison operation that should be implemented between actual data and filter_cnstr_datai as follows: (a) 000 - equal; (b) 001 - smaller than (<); (c)010 - smaller or equal (<=); (d) 011 greater or equal (>=); (e) 100 = greater than (>); (f) 101 = not equal (!=);.  Chips: BB_A0 BB_B0 K2
31350 #define DBG_REG_FILTER_CNSTR_RANGE_0                                                                 0x010a38UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31351     #define DBG_REG_FILTER_CNSTR_RANGE_0_FILTER_CNSTR_RANGE_WIDTH_0                                  (0x1f<<0) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31352     #define DBG_REG_FILTER_CNSTR_RANGE_0_FILTER_CNSTR_RANGE_WIDTH_0_SHIFT                            0
31353     #define DBG_REG_FILTER_CNSTR_RANGE_0_FILTER_CNSTR_RANGE_LSB_0                                    (0x1f<<5) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31354     #define DBG_REG_FILTER_CNSTR_RANGE_0_FILTER_CNSTR_RANGE_LSB_0_SHIFT                              5
31355 #define DBG_REG_FILTER_CNSTR_RANGE_1                                                                 0x010a3cUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31356     #define DBG_REG_FILTER_CNSTR_RANGE_1_FILTER_CNSTR_RANGE_WIDTH_1                                  (0x1f<<0) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31357     #define DBG_REG_FILTER_CNSTR_RANGE_1_FILTER_CNSTR_RANGE_WIDTH_1_SHIFT                            0
31358     #define DBG_REG_FILTER_CNSTR_RANGE_1_FILTER_CNSTR_RANGE_LSB_1                                    (0x1f<<5) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31359     #define DBG_REG_FILTER_CNSTR_RANGE_1_FILTER_CNSTR_RANGE_LSB_1_SHIFT                              5
31360 #define DBG_REG_FILTER_CNSTR_RANGE_2                                                                 0x010a40UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31361     #define DBG_REG_FILTER_CNSTR_RANGE_2_FILTER_CNSTR_RANGE_WIDTH_2                                  (0x1f<<0) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31362     #define DBG_REG_FILTER_CNSTR_RANGE_2_FILTER_CNSTR_RANGE_WIDTH_2_SHIFT                            0
31363     #define DBG_REG_FILTER_CNSTR_RANGE_2_FILTER_CNSTR_RANGE_LSB_2                                    (0x1f<<5) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31364     #define DBG_REG_FILTER_CNSTR_RANGE_2_FILTER_CNSTR_RANGE_LSB_2_SHIFT                              5
31365 #define DBG_REG_FILTER_CNSTR_RANGE_3                                                                 0x010a44UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
31366     #define DBG_REG_FILTER_CNSTR_RANGE_3_FILTER_CNSTR_RANGE_WIDTH_3                                  (0x1f<<0) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data; For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31367     #define DBG_REG_FILTER_CNSTR_RANGE_3_FILTER_CNSTR_RANGE_WIDTH_3_SHIFT                            0
31368     #define DBG_REG_FILTER_CNSTR_RANGE_3_FILTER_CNSTR_RANGE_LSB_3                                    (0x1f<<5) // If the comparison operation is not (equal or not equal) (filter_cnstr_oprtni>000 or 101) than apply the operation on a field of width filter_cnstr_range_width+1 (values: 0..31) from the actual coming data from bit filter_cnstr_range_lsb (values: 0..31) of the actual coming data;  For example if width=12 and lsb=8 and actual coming data=0xabcf9a1e and filter_cnstr_datai =0x3f and filter_cnstr_oprtni =001 (<)  THEN the applied comparison is:0x3f < 0xf9a (which is TRUE).
31369     #define DBG_REG_FILTER_CNSTR_RANGE_3_FILTER_CNSTR_RANGE_LSB_3_SHIFT                              5
31370 #define DBG_REG_FILTER_CNSTR_MUST_0                                                                  0x010a48UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector & frame must exist as part of the message.  (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31371 #define DBG_REG_FILTER_CNSTR_MUST_1                                                                  0x010a4cUL //Access:RW   DataWidth:0x1   (a) 1: the above data vector & frame must exist as part of the message.  (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31372 #define DBG_REG_FILTER_CNSTR_MUST_2                                                                  0x010a50UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector & frame must exist as part of the message.  (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31373 #define DBG_REG_FILTER_CNSTR_MUST_3                                                                  0x010a54UL //Access:RW   DataWidth:0x1   (a) 1: the above data vector & frame must exist as part of the message.  (b) 0: the above data vector & vector is not mandatory for the message; However at least one of those (low) constraints must exist as part of the message.  Chips: BB_A0 BB_B0 K2
31374 #define DBG_REG_FILTER_CNSTR_INDIRECT_0                                                              0x010a58UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data).   (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine).  Chips: BB_A0 BB_B0 K2
31375 #define DBG_REG_FILTER_CNSTR_INDIRECT_1                                                              0x010a5cUL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data).   (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine).  Chips: BB_A0 BB_B0 K2
31376 #define DBG_REG_FILTER_CNSTR_INDIRECT_2                                                              0x010a60UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data).   (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine).  Chips: BB_A0 BB_B0 K2
31377 #define DBG_REG_FILTER_CNSTR_INDIRECT_3                                                              0x010a64UL //Access:RW   DataWidth:0x2   (a) 00: direct: use the value which was configured in the filter_cnstr_datai.(b) 01: indirect: use the recorded value 0 from of fsm triggering machine (trigger_indirect0_recorded_data).   (c) 10: indirect: use the recorded value 1 from of fsm triggering machine (trigger_indirect1_recorded_data). NOTE: if filter_enable=11 OR filter_enable=01 then filter_cnstr_indirecti MUST be all 0 (need to filter prior to triggering machine event and hence cannot use the recorded data from state 0 in triggering machine).  Chips: BB_A0 BB_B0 K2
31378 #define DBG_REG_FILTER_CNSTR_CYCLIC_0                                                                0x010a68UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal)  (filter_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31379 #define DBG_REG_FILTER_CNSTR_CYCLIC_1                                                                0x010a6cUL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal)  (filter_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31380 #define DBG_REG_FILTER_CNSTR_CYCLIC_2                                                                0x010a70UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal)  (filter_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31381 #define DBG_REG_FILTER_CNSTR_CYCLIC_3                                                                0x010a74UL //Access:RW   DataWidth:0x1   Refers the comparison which is implemented in case the operation is NOT (equal or not equal)  (filter_cnstr_oprtni > 000 or 101)  (a) 0 - regular comparsion (not cyclic): a>b if a-b >0 (b) 1 - cyclic comparison: a>b if a-b<2^31-1 (half the range of 32 bit).  Chips: BB_A0 BB_B0 K2
31382 #define DBG_REG_FILTER_MSG_LENGTH_ENABLE                                                             0x010a78UL //Access:RW   DataWidth:0x1   (a) 1: use filter_msg_length to determine message boundary. (b) 0: use the frame bit to determine message boundary.  Chips: BB_A0 BB_B0 K2
31383 #define DBG_REG_FILTER_MSG_LENGTH                                                                    0x010a7cUL //Access:RW   DataWidth:0x8   Message length-1  in terms of numbers of 128-bit cycles.  NOTE: (a) if for example filter_msg_length=0 then Message length = 1 cycle. (b) if for example filter_msg_lengthi=1 then Message length = 2 cycles. etc (c) Applicable only when filter_msg_length_en = 1.  Chips: BB_A0 BB_B0 K2
31384 #define DBG_REG_FILTER_PARTIAL_RECORD_EN                                                             0x010a80UL //Access:RW   DataWidth:0x1   When set that enables of partial message record. Other way record is done for whole message (when message is filtered). Note: (a) When filter_enable = 1 (Filter on prior to trigger_event) the messages are partially recorded not only before the trigger_event but also after trigger_event (for the messages that are not filtered). (b) when filter_enable = 2 (Filter on upon trigger_event) the messages are partially recorded not only after the trigger_event, but also before trigger_event (for the messages that are not filtered).  Chips: BB_A0 BB_B0 K2
31385 #define DBG_REG_FILTER_PARTIAL_RECORD_NUM                                                            0x010a84UL //Access:RW   DataWidth:0x8   The message length-1 of the recorded part size in terms of numbers of 128-bit cycles: 0 is 1 cycle; 1 is 2 cycles; etc. Applicable only when filter_partial_record_en = 1.  Chips: BB_A0 BB_B0 K2
31386 #define DBG_REG_RCRD_ON_WINDOW_PRE_TRGR_EVNT_MODE                                                    0x010a88UL //Access:RW   DataWidth:0x2   Recording mode prior to trigger event: (a) 00 - record from time=0;  (b) 01 - record rcrd_on_window_pre_num_chunks chunks to internal buffer prior to triggering event; (c) 10 - Don't record prior to triggering event (drop data).  NOTE: applicable only if trigger_enable=1.  Chips: BB_A0 BB_B0 K2
31387 #define DBG_REG_RCRD_ON_WINDOW_POST_TRGR_EVNT_MODE                                                   0x010a8cUL //Access:RW   DataWidth:0x1   Recording mode upon trigger event:  (a) 0- enable recording data upon triggering event; in that case record for rcrd_on_window_post_num_cycles valid cycles upon the event;  (b) 1 - disable recording data upon triggering event. NOTE:  applicable only if trigger_enable=1.  Chips: BB_A0 BB_B0 K2
31388 #define DBG_REG_RCRD_ON_WINDOW_PRE_NUM_CHUNKS                                                        0x010a90UL //Access:RW   DataWidth:0x6   Number of chunks (chunk = 4 lines of 512 bit each within the internal buffer) that should be recorded to the internal buffer prior to triggering event. NOTE:  (1) applicable only when rcrd_on_window_pre_trgr_evnt_mode=01; (2) valid values are 1..47;  (3) the data that will be stored in the internal buffer is the most recent data prior to the triggering event. (4) rcrd_on_window_pre_num_chunks represents the maximum number of chunks that will be written to the internal buffer; if from since time=0 until triggering event the amount of driven data is smaller then the amount of the above value the amount of data stored in the internal buffer will be smaller then the above value.  Chips: BB_A0 BB_B0 K2
31389 #define DBG_REG_RCRD_ON_WINDOW_POST_NUM_CYCLES                                                       0x010a94UL //Access:RW   DataWidth:0x20  Number of valid cycles that should be recorded upon triggering event.  NOTE: (1) applicable only when rcrd_on_window_post_trgr_evnt_mode=0; (2) value of 0xffffffff (maximum value) result in recording of unlimited amount of cycles (infinite amount of cycles).  Chips: BB_A0 BB_B0 K2
31390 #define DBG_REG_PCI_FUNC_NUM                                                                         0x010a98UL //Access:RW   DataWidth:0x10  16-bit opaque FID for pci request interface.  Chips: BB_A0 BB_B0 K2
31391 #define DBG_REG_INT_BUFFER_WRAP_COUNTER                                                              0x010a9cUL //Access:R    DataWidth:0x20  Number of wraps on internal buffer; NOTE: valid only when debug_target=0 (internal buffer) and full_mode=1 (wrap) . Will stuck on all ones.  Chips: BB_A0 BB_B0 K2
31392 #define DBG_REG_DBG_NM_MBIST1_CNTRL_CMD                                                              0x010aa0UL //Access:RW   DataWidth:0x5   NA.  Chips: BB_A0 BB_B0 K2
31393 #define DBG_REG_NM_CLK_MBIST1_CNTRL_DBG_STATUS_0                                                     0x010aa4UL //Access:R    DataWidth:0x20  NA.  Chips: BB_A0 BB_B0 K2
31394 #define DBG_REG_NM_CLK_MBIST1_CNTRL_DBG_STATUS_1                                                     0x010aa8UL //Access:R    DataWidth:0x20  NA.  Chips: BB_A0 BB_B0 K2
31395 #define DBG_REG_NM_CLK_CP_MBIST1_CNTRL_DBG_STATUS_0                                                  0x010aacUL //Access:R    DataWidth:0x20  NA.  Chips: BB_A0 BB_B0 K2
31396 #define DBG_REG_INTERNAL_BUFFER_LSB_TM                                                               0x010ab0UL //Access:RW   DataWidth:0x8   Tm port for the internal buffer lsb memory instance.  Chips: BB_A0 BB_B0 K2
31397 #define DBG_REG_INTERNAL_BUFFER_MSB_TM                                                               0x010ab4UL //Access:RW   DataWidth:0x8   Tm port for the internal buffer msb memory instance.  Chips: BB_A0 BB_B0 K2
31398 #define DBG_REG_ECO_RESERVED                                                                         0x010ab8UL //Access:RW   DataWidth:0x8   Eco reserved register.  Chips: BB_A0 BB_B0 K2
31399 #define DBG_REG_DBG_DRIVER_TRIGGER                                                                   0x010abcUL //Access:RW   DataWidth:0x1   Used for triggering on driver assertions. For example this can be used in Emulation when The driver identifies an error and write to the for triggerig purpose  Chips: BB_A0 BB_B0 K2
31400 #define DBG_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD                                                        0x010ac0UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31401 #define DBG_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD                                                        0x010ac4UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31402 #define DBG_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD                                                        0x010ac8UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31403 #define DBG_REG_CPU_MBIST_MEMCTRL_3_CNTRL_CMD                                                        0x010accUL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31404 #define DBG_REG_CPU_MBIST_MEMCTRL_4_CNTRL_CMD                                                        0x010ad0UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31405 #define DBG_REG_CPU_MBIST_MEMCTRL_5_CNTRL_CMD                                                        0x010ad4UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31406 #define DBG_REG_CPU_MBIST_MEMCTRL_6_CNTRL_CMD                                                        0x010ad8UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31407 #define DBG_REG_CPU_MBIST_MEMCTRL_7_CNTRL_CMD                                                        0x010adcUL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31408 #define DBG_REG_CPU_MBIST_MEMCTRL_8_CNTRL_CMD                                                        0x010ae0UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31409 #define DBG_REG_CPU_MBIST_MEMCTRL_9_CNTRL_CMD                                                        0x010ae4UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0
31410 #define DBG_REG_HW_ID_NUM                                                                            0x010b10UL //Access:RW   DataWidth:0xc   ID number for each HW block that will be added to trailer when HW block will be selected: B2:0 for bits [31:0]; B5:3 for bits[63:32]; B8:6 for bits [95:64]; B11:9 for bits [127:96].  Chips: BB_A0 BB_B0 K2
31411 #define DBG_REG_STORM_ID_NUM                                                                         0x010b14UL //Access:RW   DataWidth:0x12  ID number for each STORM that will be added to trailer when STORM will be selected: B2:0 - TSEM; B5:3- MSEM; B8:6- USEM; B11:9- XSEM; B14:12 is YSEM; B17:15 is PSEM;.  Chips: BB_A0 BB_B0 K2
31412 #define DBG_REG_ETHERNET_HDR_0                                                                       0x010b18UL //Access:RW   DataWidth:0x20  Ethernet header . Its size depends os ethernet_hdr_width register.  Chips: BB_A0 BB_B0 K2
31413 #define DBG_REG_ETHERNET_HDR_1                                                                       0x010b1cUL //Access:RW   DataWidth:0x20  Ethernet header . Its size depends os ethernet_hdr_width register.  Chips: BB_A0 BB_B0 K2
31414 #define DBG_REG_ETHERNET_HDR_2                                                                       0x010b20UL //Access:RW   DataWidth:0x20  Ethernet header . Its size depends os ethernet_hdr_width register.  Chips: BB_A0 BB_B0 K2
31415 #define DBG_REG_ETHERNET_HDR_3                                                                       0x010b24UL //Access:RW   DataWidth:0x20  Ethernet header . Its size depends os ethernet_hdr_width register.  Chips: BB_A0 BB_B0 K2
31416 #define DBG_REG_ETHERNET_HDR_4                                                                       0x010b28UL //Access:RW   DataWidth:0x20  Ethernet header . Its size depends os ethernet_hdr_width register.  Chips: BB_A0 BB_B0 K2
31417 #define DBG_REG_ETHERNET_HDR_5                                                                       0x010b2cUL //Access:RW   DataWidth:0x20  Ethernet header . Its size depends os ethernet_hdr_width register.  Chips: BB_A0 BB_B0 K2
31418 #define DBG_REG_ETHERNET_HDR_6                                                                       0x010b30UL //Access:RW   DataWidth:0x20  Ethernet header . Its size depends os ethernet_hdr_width register.  Chips: BB_A0 BB_B0 K2
31419 #define DBG_REG_ETHERNET_HDR_7                                                                       0x010b34UL //Access:RW   DataWidth:0x20  Ethernet header . Its size depends os ethernet_hdr_width register.  Chips: BB_A0 BB_B0 K2
31420 #define DBG_REG_ETHERNET_HDR_WIDTH                                                                   0x010b38UL //Access:RW   DataWidth:0x4   Ethernet header width: 0 - 14 MSB bytes; 1- 16 MSB bytes; .. ; 8 - 30 MSB bytes; 9 -32 MSB bytes. Values 10-15 are not supported.  Chips: BB_A0 BB_B0 K2
31421 #define DBG_REG_TARGET_PACKET_SIZE                                                                   0x010b3cUL //Access:RW   DataWidth:0x6   The packet size to NIG or PXP target is in granularity of chunks. The allowed range is 1-48 that suits to packet size of 256B-12KB. Values 49-63 are unused.  Chips: BB_A0 BB_B0 K2
31422 #define DBG_REG_NW_PACKET_COUNTER_EN                                                                 0x010b40UL //Access:RW   DataWidth:0x1   When 1 enables inserting packet counter at the output to NIG between Ethernet header and data.  Chips: BB_A0 BB_B0 K2
31423 #define DBG_REG_NW_PACKET_COUNTER_STATUS                                                             0x010b44UL //Access:R    DataWidth:0x10  Packet counter value. Contains number of packets that were sent to NIG.  Chips: BB_A0 BB_B0 K2
31424 #define DBG_REG_NW_PACKET_OVERFLOW_COUNTER                                                           0x010b48UL //Access:RC   DataWidth:0x10  Number of overflows for nw_packet_counter. Should stuck on all ones.  Chips: BB_A0 BB_B0 K2
31425 #define DBG_REG_TIMESTAMP                                                                            0x010b4cUL //Access:RW   DataWidth:0x20  Timestamp value. This counter will be incremented when tick counter reaches timestamp_tick value. It may be reset from RBC or set to any init value. This counter starts to count immediately after reset.  Chips: BB_A0 BB_B0 K2
31426 #define DBG_REG_TIMESTAMP_TICK                                                                       0x010b50UL //Access:RW   DataWidth:0x20  Timestamp tick value.  Chips: BB_A0 BB_B0 K2
31427 #define DBG_REG_TIMESTAMP_FRAME_EN                                                                   0x010b54UL //Access:RW   DataWidth:0x3   Timestamp frame enable. This register enables inserting timestamp to bits 31:0 when B0 is set and frame[1] is set or B1 is set and frame[2] is set or B2 is set and frame[3] is set.  Chips: BB_A0 BB_B0 K2
31428 #define DBG_REG_TIMESTAMP_VALID_EN                                                                   0x010b58UL //Access:RW   DataWidth:0x3   Timestamp valid enable. This register enables inserting timestamp to bits 31:0 when B0 is set and valid[1] is set or B1 is set and valid[2] is set or B2 is set and valid[3] is set.  Chips: BB_A0 BB_B0 K2
31429 #define DBG_REG_TRIGGER_STALL_EN                                                                     0x010b5cUL //Access:RW   DataWidth:0x6   Stall enable per SEM block. When set enable stall output from DBG to SEM block as result of trigger event: 0 is TSEM; 1- MSEM; 2- USEM; 3- XSEM; 4 is YSEM; 5 is PSEM;.  Chips: BB_A0 BB_B0 K2
31430 #define DBG_REG_TRIGGER_STATUS_CUR_STATE                                                             0x010b60UL //Access:R    DataWidth:0x2   Current state machine status of trigger block in dbg_trigger.v: states 0-2 are functional state (comparsion is implemented on the constraints) ; state 3 is triggering event.  Chips: BB_A0 BB_B0 K2
31431 #define DBG_REG_TRIGGER_STATUS_PAUSE_STATE                                                           0x010b64UL //Access:R    DataWidth:0x2   Pause state machine status of trigger block in dbg_trigger_state.v: : state 0 - NOT_HNDLR_MSG; state 1- FRST_HNDLR_MSG; state 2- SCND_HNDLR_MSG; state 3 - unused.  Chips: BB_A0 BB_B0 K2
31432 #define DBG_REG_TRIGGER_STATUS_MATCH_COUNTER_SET0                                                    0x010b68UL //Access:R    DataWidth:0x10  Counter for number of times set 0 appeared in current state in dbg_trigger_state.v.  Chips: BB_A0 BB_B0 K2
31433 #define DBG_REG_TRIGGER_STATUS_MATCH_COUNTER_SET1                                                    0x010b6cUL //Access:R    DataWidth:0x10  Counter for number of times set 1 appeared in current state in dbg_trigger_state.v.  Chips: BB_A0 BB_B0 K2
31434 #define DBG_REG_TRIGGER_STATUS_MATCH_CNSTR                                                           0x010b70UL //Access:R    DataWidth:0x8   Statistics. Match constraint status. B0 - constraint 0 set0; B1 - constraint 1 set0; B2 - constraint 2 set0; B3 - constraint 3 set0; B4 - constraint 0 set1; B5 - constraint 1 set1; B6 - constraint 2 set1; B7 - constraint 3 set1.  Chips: BB_A0 BB_B0 K2
31435 #define DBG_REG_TRIGGER_STATUS_CYCLE_CNT                                                             0x010b74UL //Access:R    DataWidth:0x8   Statistics. Cycle counter from beginning of message.  Chips: BB_A0 BB_B0 K2
31436 #define DBG_REG_NUM_OF_CYCLES_SENT                                                                   0x010b78UL //Access:RC   DataWidth:0x20  Debug only: These bits represent the total number of 128-bit cycles sent from the dbg block to output interface (NIG/PCI).  Chips: BB_A0 BB_B0 K2
31437 #define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_0                                                   0x010b7cUL //Access:R    DataWidth:0x10  Debug only: Number of transitions per state.  Chips: BB_A0 BB_B0 K2
31438 #define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_1                                                   0x010b80UL //Access:R    DataWidth:0x10  Debug only: Number of transitions per state.  Chips: BB_A0 BB_B0 K2
31439 #define DBG_REG_TRIGGER_STATUS_STATE_TRANSITIONS_2                                                   0x010b84UL //Access:R    DataWidth:0x10  Debug only: Number of transitions per state.  Chips: BB_A0 BB_B0 K2
31440 #define DBG_REG_TRAILER_STATUS_CUR_STATE                                                             0x010b88UL //Access:R    DataWidth:0x3   Debug only: Current state status in trailer block : 0 - Wait for new line; 1- END_OF_CHUNK; 2- RESET_NUM_OF_VALID_DWORDS; 3- SEND_ADDITIONAL_CHUNK; 4- SEND_ADDITIONAL_LINE.  Chips: BB_A0 BB_B0 K2
31441 #define DBG_REG_TRAILER_STATUS_VALID_DWORDS                                                          0x010b8cUL //Access:R    DataWidth:0x6   Debug only: number of valid dwords in trailer block.  Chips: BB_A0 BB_B0 K2
31442 #define DBG_REG_FILTER_STATUS_MATCH_CNSTR                                                            0x010b90UL //Access:R    DataWidth:0x4   Statistics. Match constraint status. B0 - constraint 0; B1 - constraint 1; B2 - constraint 2 ; B3 - constraint 3.  Chips: BB_A0 BB_B0 K2
31443 #define DBG_REG_MEMCTRL_WR_RD_N                                                                      0x010b94UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
31444 #define DBG_REG_MEMCTRL_CMD                                                                          0x010b98UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
31445 #define DBG_REG_MEMCTRL_ADDRESS                                                                      0x010b9cUL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
31446 #define DBG_REG_MEMCTRL_STATUS                                                                       0x010ba0UL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0 K2
31447 #define DBG_REG_NUM_OF_EMPTY_LINES_IN_INT_BUFFER                                                     0x010ba4UL //Access:R    DataWidth:0x8   Number of empty lines in internal buffer.  Chips: BB_B0 K2
31448 #define DBG_REG_INTR_BUFFER                                                                          0x014000UL //Access:WB   DataWidth:0x200 Debug only:  Internal buffer of 12KByte buffer.  Chips: BB_A0 BB_B0 K2
31449 #define DBG_REG_INTR_BUFFER_SIZE                                                                     3072
31450 #define IPC_REG_PLL_MAIN_DIVR_K2                                                                     0x020200UL //Access:RW   DataWidth:0x6   PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value  Chips: K2
31451 #define IPC_REG_MDIO_VOLTAGE_SEL_BB_A0                                                               0x020200UL //Access:RW   DataWidth:0x1   Select line for MDIO Voltage Select 0 : MDIO VDDIO is 1.8V or below. 1 : MDIO VDDIO is 1.8+V or above.  Chips: BB_A0
31452 #define IPC_REG_MDIO_VOLTAGE_SEL_BB_B0                                                               0x020200UL //Access:RW   DataWidth:0x1   Select line for MDIO Voltage Select 0 : MDIO VDDIO is 1.8V or below. 1 : MDIO VDDIO is 1.8+V or above.  Chips: BB_B0
31453 #define IPC_REG_PLL_MAIN_DIVF_K2                                                                     0x020204UL //Access:RW   DataWidth:0x9   Feedback divider value  Chips: K2
31454 #define IPC_REG_CPU_OTP_CTRL1_BB_A0                                                                  0x020204UL //Access:RW   DataWidth:0x20  [0]: cpu_cmd_wr_en: A rising edge of this bit will execute the OTP "command" in the next field.  This bit should be set to Low and high again for the next command execution to start; [5:1]: Command: 0: Read; 1: OTP_ProgEnable (OTP must be put in ProgEnable mode by writing 0xF; 0x4; 0x8; 0xD in sequence with OTP_ProgEnable command before you do any actual  write to OTP. Sequence Data is taken from bitsel bus and therefore word_address and wdata do not play any role during this authentication process; 2: OTP_ProgDisable (Disable OTP with this command once you are done with programming); 3: Verify( vsel and tm are used from control bits); 4: Init (vsel and tm are used from strap module); 5: lock_cmd. used to program the lock bits that can not be programmed by using  regular program bit and program Word cmd. OTP word address 6 and 7 are allocated for lock bits and to program these bits lock command must be used; 6: stby (Not used in this IP); 7: wakeup (Not used in this IP); 9: Prescreen test. Upon getting a prescrn_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE until it reaches the max word_addr or it finds any programmed bit; 10: Program Bit; 11: Program Word; 12: burnin. Upon getting a burnin_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE. It keeps looping until the cmd is changed from burnin to something else; 13: auto_reload; 14: ovst_read; 15: ovst_prog; [17:6]: Address; [18]: cpu_mode: When set, enables command execution through this cpu interface; [19]: cpu_disable_otp_access: When set, disables any command execution through this cpu interface. [31:20]: RESERVED;  Chips: BB_A0
31455 #define IPC_REG_CPU_OTP_CTRL1_BB_B0                                                                  0x020204UL //Access:RW   DataWidth:0x20  [0]: cpu_cmd_wr_en: A rising edge of this bit will execute the OTP "command" in the next field.  This bit should be set to Low and high again for the next command execution to start; [5:1]: Command: 0: Read; 1: OTP_ProgEnable (OTP must be put in ProgEnable mode by writing 0xF; 0x4; 0x8; 0xD in sequence with OTP_ProgEnable command before you do any actual  write to OTP. Sequence Data is taken from bitsel bus and therefore word_address and wdata do not play any role during this authentication process; 2: OTP_ProgDisable (Disable OTP with this command once you are done with programming); 3: Verify( vsel and tm are used from control bits); 4: Init (vsel and tm are used from strap module); 5: lock_cmd. used to program the lock bits that can not be programmed by using  regular program bit and program Word cmd. OTP word address 6 and 7 are allocated for lock bits and to program these bits lock command must be used; 6: stby (Not used in this IP); 7: wakeup (Not used in this IP); 9: Prescreen test. Upon getting a prescrn_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE until it reaches the max word_addr or it finds any programmed bit; 10: Program Bit; 11: Program Word; 12: burnin. Upon getting a burnin_cmd; word_addr; and bit_sel; otp_controller keeps reading(simple read) the OTP MEMORY SPACE. It keeps looping until the cmd is changed from burnin to something else; 13: auto_reload; 14: ovst_read; 15: ovst_prog; [17:6]: Address; [18]: cpu_mode: When set, enables command execution through this cpu interface; [19]: cpu_disable_otp_access: When set, disables any command execution through this cpu interface. [31:20]: RESERVED;  Chips: BB_B0
31456 #define IPC_REG_PLL_MAIN_DIVQ_K2                                                                     0x020208UL //Access:RW   DataWidth:0x3   output divider value, 2^binary value  Chips: K2
31457 #define IPC_REG_CPU_OTP_STATUS_BB_A0                                                                 0x020208UL //Access:R    DataWidth:0x20  [0]: data_valid: This bit is used to sample READ data in burst mode; [1]: cmd_done: Command Done, This signal indicates the completion of the command; [2]: progok: Program OK, This signal is set when PROG ENABLE sequence is issued correctly; [3]: fdone: This signal is set when fout bits are loaded; [4]: cmd_fail: Command Failure, This bit is set when locked address is accessed using program related commands; [5]: refok: OTP RefOK signal; [6]: debug_mode_set: This bit is set when ctrl_wr_cmd is issued; [7]: mst_fsm_error: An illegal state has executed. This bit is set to '0' in idle state, otherwise '1' in all other states; [8]: debug_mode: This bit is set using ctrl_wr command and indicates the debug mode option; [9]: invalid_addr: This bit is set when Locked address is accessed by program related commands or when address is out of range; [10]: prog_word_fail: This bit is set when Programming fails for a bit during word program; [11]: prog_screen_fail: This bit is set when screening fails for word programming. [12]: prog_block_cmd: Invalid for CPU mode; [13]: prog_en: By default this is set to enable PROG command; [14]: prgm_wd_rp_fail: TBD; [15]: max_rw: TBD; [16]: max_rwp: TBD; [17]: auto_rw_max_set: TBD; [18]: max_sw: TBD; [19]: addr_in_illegal_range: TBD; [31:20]: Reserved;  Chips: BB_A0
31458 #define IPC_REG_CPU_OTP_STATUS_BB_B0                                                                 0x020208UL //Access:R    DataWidth:0x20  [0]: data_valid: This bit is used to sample READ data in burst mode; [1]: cmd_done: Command Done, This signal indicates the completion of the command; [2]: progok: Program OK, This signal is set when PROG ENABLE sequence is issued correctly; [3]: fdone: This signal is set when fout bits are loaded; [4]: cmd_fail: Command Failure, This bit is set when locked address is accessed using program related commands; [5]: refok: OTP RefOK signal; [6]: debug_mode_set: This bit is set when ctrl_wr_cmd is issued; [7]: mst_fsm_error: An illegal state has executed. This bit is set to '0' in idle state, otherwise '1' in all other states; [8]: debug_mode: This bit is set using ctrl_wr command and indicates the debug mode option; [9]: invalid_addr: This bit is set when Locked address is accessed by program related commands or when address is out of range; [10]: prog_word_fail: This bit is set when Programming fails for a bit during word program; [11]: prog_screen_fail: This bit is set when screening fails for word programming. [12]: prog_block_cmd: Invalid for CPU mode; [13]: prog_en: By default this is set to enable PROG command; [14]: prgm_wd_rp_fail: TBD; [15]: max_rw: TBD; [16]: max_rwp: TBD; [17]: auto_rw_max_set: TBD; [18]: max_sw: TBD; [19]: addr_in_illegal_range: TBD; [31:20]: Reserved;  Chips: BB_B0
31459 #define IPC_REG_PLL_MAIN_RANGE_K2                                                                    0x02020cUL //Access:RW   DataWidth:0x3   PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz  Chips: K2
31460 #define IPC_REG_CPU_OTP_WRITE_DATA_BB_A0                                                             0x02020cUL //Access:RW   DataWidth:0x20  Used to provide write data with burst write command from CPU side.  Chips: BB_A0
31461 #define IPC_REG_CPU_OTP_WRITE_DATA_BB_B0                                                             0x02020cUL //Access:RW   DataWidth:0x20  Used to provide write data with burst write command from CPU side.  Chips: BB_B0
31462 #define IPC_REG_PLL_MAIN_BYPASS_K2                                                                   0x020210UL //Access:RW   DataWidth:0x1   pll bypass signal  Chips: K2
31463 #define IPC_REG_CPU_OTP_READ_DATA_BB_A0                                                              0x020210UL //Access:R    DataWidth:0x20  Data output from the OTP read data command.  Chips: BB_A0
31464 #define IPC_REG_CPU_OTP_READ_DATA_BB_B0                                                              0x020210UL //Access:R    DataWidth:0x20  Data output from the OTP read data command.  Chips: BB_B0
31465 #define IPC_REG_PLL_MAIN_LOCK_K2                                                                     0x020214UL //Access:R    DataWidth:0x1   pll lock signal  Chips: K2
31466 #define IPC_REG_OSC_E28_XCORE_BIAS_BB_A0                                                             0x020214UL //Access:RW   DataWidth:0x4   XTAL core current control 4'b0010: 27Mhz 4'b0100: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 4. Global Register, Reset on POR  Chips: BB_A0
31467 #define IPC_REG_OSC_E28_XCORE_BIAS_BB_B0                                                             0x020214UL //Access:RW   DataWidth:0x4   XTAL core current control 4'b0010: 27Mhz 4'b0100: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 4. Global Register, Reset on POR  Chips: BB_B0
31468 #define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_K2                                                0x020218UL //Access:R    DataWidth:0x1   pll lock detected filter status  Chips: K2
31469 #define IPC_REG_OSC_E28_XCORE_BIAS_OVERRIDE_BB_A0                                                    0x020218UL //Access:RW   DataWidth:0x1   XCORE_BIAS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_xcore_bias Global Register, Reset on POR  Chips: BB_A0
31470 #define IPC_REG_OSC_E28_XCORE_BIAS_OVERRIDE_BB_B0                                                    0x020218UL //Access:RW   DataWidth:0x1   XCORE_BIAS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_xcore_bias Global Register, Reset on POR  Chips: BB_B0
31471 #define IPC_REG_PLL_MAIN_NEWDIV_K2                                                                   0x02021cUL //Access:RW   DataWidth:0x1   Divider input control  Chips: K2
31472 #define IPC_REG_OSC_E28_HIPASS_BB_A0                                                                 0x02021cUL //Access:RW   DataWidth:0x1   XTAL core Highpass Filter Corner Frequency control 0: 27Mhz 1: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 1. Global Register, Reset on POR  Chips: BB_A0
31473 #define IPC_REG_OSC_E28_HIPASS_BB_B0                                                                 0x02021cUL //Access:RW   DataWidth:0x1   XTAL core Highpass Filter Corner Frequency control 0: 27Mhz 1: 50Mhz Device will be using 50Mhz crytal, so defaults to a value of 1. Global Register, Reset on POR  Chips: BB_B0
31474 #define IPC_REG_PLL_MAIN_DIVACK_K2                                                                   0x020220UL //Access:R    DataWidth:0x1   Divider handshake signal  Chips: K2
31475 #define IPC_REG_OSC_E28_HIPASS_OVERRIDE_BB_A0                                                        0x020220UL //Access:RW   DataWidth:0x1   HIPASS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_hipass Global Register, Reset on POR  Chips: BB_A0
31476 #define IPC_REG_OSC_E28_HIPASS_OVERRIDE_BB_B0                                                        0x020220UL //Access:RW   DataWidth:0x1   HIPASS in normal operation is controlled by straps on the board. This bit allows it SW to override the setting based on register osc_e28_hipass Global Register, Reset on POR  Chips: BB_B0
31477 #define IPC_REG_PLL_MAIN_RESET_K2                                                                    0x020224UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: K2
31478     #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET                                                    (0x1<<0) // 1 : Reset the PLL. The reset is active high.
31479     #define IPC_REG_PLL_MAIN_RESET_PLL_MAIN_RESET_SHIFT                                              0
31480     #define IPC_REG_PLL_MAIN_RESET_OVERRIDE                                                          (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
31481     #define IPC_REG_PLL_MAIN_RESET_OVERRIDE_SHIFT                                                    4
31482 #define IPC_REG_OSC_E28_D2C_BIAS_BB_A0                                                               0x020224UL //Access:RW   DataWidth:0x3   D2C Bias Current Control Global Register, Reset on POR  Chips: BB_A0
31483 #define IPC_REG_OSC_E28_D2C_BIAS_BB_B0                                                               0x020224UL //Access:RW   DataWidth:0x3   D2C Bias Current Control Global Register, Reset on POR  Chips: BB_B0
31484 #define IPC_REG_PLL_MAIN_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2                                    0x020228UL //Access:RW   DataWidth:0x1   Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.  Chips: K2
31485 #define IPC_REG_OSC_E28_CML_CUR_BB_A0                                                                0x020228UL //Access:RW   DataWidth:0x1   CML Current Control Global Register, Reset on POR  Chips: BB_A0
31486 #define IPC_REG_OSC_E28_CML_CUR_BB_B0                                                                0x020228UL //Access:RW   DataWidth:0x1   CML Current Control Global Register, Reset on POR  Chips: BB_B0
31487 #define IPC_REG_PLL_NWM_DIVR_K2                                                                      0x02022cUL //Access:RW   DataWidth:0x6   PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value  Chips: K2
31488 #define IPC_REG_OSC_E28_DRV_CUR_BB_A0                                                                0x02022cUL //Access:RW   DataWidth:0x2   50ohm Driver Current Control 00 = 5mA 01 = 10mA 10 = 15mA 11 = 20mA Global Register, Reset on POR  Chips: BB_A0
31489 #define IPC_REG_OSC_E28_DRV_CUR_BB_B0                                                                0x02022cUL //Access:RW   DataWidth:0x2   50ohm Driver Current Control 00 = 5mA 01 = 10mA 10 = 15mA 11 = 20mA Global Register, Reset on POR  Chips: BB_B0
31490 #define IPC_REG_PLL_NWM_DIVF_K2                                                                      0x020230UL //Access:RW   DataWidth:0x9   Feedback divider value  Chips: K2
31491 #define IPC_REG_OSC_E28_DIV2_SEL_BB_A0                                                               0x020230UL //Access:RW   DataWidth:0x1   Divide by 2 Selection for pad_op/n_cml output 0=XTAL Freq. 1=XTAL Freq. / 2 Global Register, Reset on POR  Chips: BB_A0
31492 #define IPC_REG_OSC_E28_DIV2_SEL_BB_B0                                                               0x020230UL //Access:RW   DataWidth:0x1   Divide by 2 Selection for pad_op/n_cml output 0=XTAL Freq. 1=XTAL Freq. / 2 Global Register, Reset on POR  Chips: BB_B0
31493 #define IPC_REG_PLL_NWM_DIVQ_K2                                                                      0x020234UL //Access:RW   DataWidth:0x3   output divider value, 2^binary value  Chips: K2
31494 #define IPC_REG_OSC_E28_LDO_CTRL_BB_A0                                                               0x020234UL //Access:RW   DataWidth:0x4   [3:2] LDO Output Stage Bias Control [1:0] LDO Output Voltage Level Control 00 = 1.05V 01 = 1.00V 10 = 0.95V 11 = 0.90V Global Register, Reset on POR  Chips: BB_A0
31495 #define IPC_REG_OSC_E28_LDO_CTRL_BB_B0                                                               0x020234UL //Access:RW   DataWidth:0x4   [3:2] LDO Output Stage Bias Control [1:0] LDO Output Voltage Level Control 00 = 1.05V 01 = 1.00V 10 = 0.95V 11 = 0.90V Global Register, Reset on POR  Chips: BB_B0
31496 #define IPC_REG_PLL_NWM_RANGE_K2                                                                     0x020238UL //Access:RW   DataWidth:0x3   PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz  Chips: K2
31497 #define IPC_REG_OSC_E28_CMOS_EN_ALL_BB_A0                                                            0x020238UL //Access:RW   DataWidth:0x1   ENABLE All CMOS Outputs 0=o_xtal_ck[5:0] depends on i_resetb and i_cmos_en_ch[5:0] 1=o_xtal_ck[5:0] ALL ON Global Register, Reset on POR  Chips: BB_A0
31498 #define IPC_REG_OSC_E28_CMOS_EN_ALL_BB_B0                                                            0x020238UL //Access:RW   DataWidth:0x1   ENABLE All CMOS Outputs 0=o_xtal_ck[5:0] depends on i_resetb and i_cmos_en_ch[5:0] 1=o_xtal_ck[5:0] ALL ON Global Register, Reset on POR  Chips: BB_B0
31499 #define IPC_REG_PLL_NWM_RESET_K2                                                                     0x02023cUL //Access:RW   DataWidth:0x1   pll reset signal  Chips: K2
31500 #define IPC_REG_OSC_E28_CMOS_EN_CH_BB_A0                                                             0x02023cUL //Access:RW   DataWidth:0x6   Enable for CMOS outputs 0=CMOS output DISABLED 1=CMOS output ENABLED Bit[0] = o_xtal_ck0 Bit[1] = o_xtal_ck1 Bit[2] = o_xtal_ck2 Bit[3] = o_xtal_ck3 Bit[4] = o_xtal_ck4 Bit[5] = o_xtal_ck5 Global Register, Reset on POR  Chips: BB_A0
31501 #define IPC_REG_OSC_E28_CMOS_EN_CH_BB_B0                                                             0x02023cUL //Access:RW   DataWidth:0x6   Enable for CMOS outputs 0=CMOS output DISABLED 1=CMOS output ENABLED Bit[0] = o_xtal_ck0 Bit[1] = o_xtal_ck1 Bit[2] = o_xtal_ck2 Bit[3] = o_xtal_ck3 Bit[4] = o_xtal_ck4 Bit[5] = o_xtal_ck5 Global Register, Reset on POR  Chips: BB_B0
31502 #define IPC_REG_PLL_NWM_BYPASS_K2                                                                    0x020240UL //Access:RW   DataWidth:0x1   pll bypass signal  Chips: K2
31503 #define IPC_REG_OSC_E28_CML_EN_CH_BB_A0                                                              0x020240UL //Access:RW   DataWidth:0x4   CML Output Channel Power Down 0=CML output ON 1=CML output OFF Bit[0] = o_cml_p/n 0 Bit[1] = o_cml_p/n 1 Bit[2] = o_cml_p/n 2 Bit[3] = o_cml_p/n 3 Global Register, Reset on POR  Chips: BB_A0
31504 #define IPC_REG_OSC_E28_CML_EN_CH_BB_B0                                                              0x020240UL //Access:RW   DataWidth:0x4   CML Output Channel Power Down 0=CML output ON 1=CML output OFF Bit[0] = o_cml_p/n 0 Bit[1] = o_cml_p/n 1 Bit[2] = o_cml_p/n 2 Bit[3] = o_cml_p/n 3 Global Register, Reset on POR  Chips: BB_B0
31505 #define IPC_REG_PLL_NWM_LOCK_K2                                                                      0x020244UL //Access:R    DataWidth:0x1   pll lock signal  Chips: K2
31506 #define IPC_REG_OSC_E28_PD_DRV_BB_A0                                                                 0x020244UL //Access:RW   DataWidth:0x1   50ohm Driver Power Down 0=Driver ENABLED 1=Driver DISABLED Global Register, Reset on POR  Chips: BB_A0
31507 #define IPC_REG_OSC_E28_PD_DRV_BB_B0                                                                 0x020244UL //Access:RW   DataWidth:0x1   50ohm Driver Power Down 0=Driver ENABLED 1=Driver DISABLED Global Register, Reset on POR  Chips: BB_B0
31508 #define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_K2                                                 0x020248UL //Access:R    DataWidth:0x1   pll lock detected filter status  Chips: K2
31509 #define IPC_REG_OSC_E28_MISC_BB_A0                                                                   0x020248UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0
31510 #define IPC_REG_OSC_E28_MISC_BB_B0                                                                   0x020248UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0
31511     #define IPC_REG_OSC_E28_MISC_OSC_E28_POWER_SAVE                                                  (0x1<<0) // Future Use
31512     #define IPC_REG_OSC_E28_MISC_OSC_E28_POWER_SAVE_SHIFT                                            0
31513     #define IPC_REG_OSC_E28_MISC_OSC_E28_BIAS                                                        (0x7<<1) // Future Use
31514     #define IPC_REG_OSC_E28_MISC_OSC_E28_BIAS_SHIFT                                                  1
31515     #define IPC_REG_OSC_E28_MISC_OSC_E28_XCORE_CM_SEL                                                (0x1<<4) // Future Use
31516     #define IPC_REG_OSC_E28_MISC_OSC_E28_XCORE_CM_SEL_SHIFT                                          4
31517 #define IPC_REG_PLL_NWM_NEWDIV_K2                                                                    0x02024cUL //Access:RW   DataWidth:0x1   Divider input control  Chips: K2
31518 #define IPC_REG_PLL_MAIN_E28_PWRDN_BB_A0                                                             0x02024cUL //Access:RW   DataWidth:0x1   PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR  Chips: BB_A0
31519 #define IPC_REG_PLL_MAIN_E28_PWRDN_BB_B0                                                             0x02024cUL //Access:RW   DataWidth:0x1   PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR  Chips: BB_B0
31520 #define IPC_REG_PLL_NWM_DIVACK_K2                                                                    0x020250UL //Access:R    DataWidth:0x1   Divider handshake signal  Chips: K2
31521 #define IPC_REG_PLL_MAIN_E28_RESET_VCO_BB_A0                                                         0x020250UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0
31522 #define IPC_REG_PLL_MAIN_E28_RESET_VCO_BB_B0                                                         0x020250UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0
31523     #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO                                        (0x1<<0) // 1 : Reset the VCO of the PLL. The reset is active high. Global Register, Reset on POR
31524     #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_SHIFT                                  0
31525     #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_OVERRIDE                               (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
31526     #define IPC_REG_PLL_MAIN_E28_RESET_VCO_PLL_MAIN_RESET_VCO_OVERRIDE_SHIFT                         4
31527 #define IPC_REG_PLL_NWM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2                                     0x020254UL //Access:RW   DataWidth:0x1   Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.  Chips: K2
31528 #define IPC_REG_PLL_MAIN_E28_RESET_POST_BB_A0                                                        0x020254UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0
31529 #define IPC_REG_PLL_MAIN_E28_RESET_POST_BB_B0                                                        0x020254UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0
31530     #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST                                      (0x1<<0) // 1 : Reset the Post Divider of the PLL. The reset is active high. Global Register, Reset on POR
31531     #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_SHIFT                                0
31532     #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_OVERRIDE                             (0x1<<4) // 1 : Override the init state machine and control the PLL reset using bit[0] of the register.
31533     #define IPC_REG_PLL_MAIN_E28_RESET_POST_PLL_MAIN_RESET_POST_OVERRIDE_SHIFT                       4
31534 #define IPC_REG_PLL_STORM_DIVR_K2                                                                    0x020258UL //Access:RW   DataWidth:0x6   PLLLOUT = REF / DIVR_Value * DIVF_Value * 2 / DIVQ_Value Reference divider value  Chips: K2
31535 #define IPC_REG_PLL_MAIN_E28_PDIV_BB_A0                                                              0x020258UL //Access:RW   DataWidth:0x4   Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.  Chips: BB_A0
31536 #define IPC_REG_PLL_MAIN_E28_PDIV_BB_B0                                                              0x020258UL //Access:RW   DataWidth:0x4   Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.  Chips: BB_B0
31537 #define IPC_REG_PLL_STORM_DIVF_K2                                                                    0x02025cUL //Access:RW   DataWidth:0x9   Feedback divider value  Chips: K2
31538 #define IPC_REG_PLL_MAIN_E28_NDIV_INT_BB_A0                                                          0x02025cUL //Access:RW   DataWidth:0xa   Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset.  Chips: BB_A0
31539 #define IPC_REG_PLL_MAIN_E28_NDIV_INT_BB_B0                                                          0x02025cUL //Access:RW   DataWidth:0xa   Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset.  Chips: BB_B0
31540 #define IPC_REG_PLL_STORM_DIVQ_K2                                                                    0x020260UL //Access:RW   DataWidth:0x3   output divider value, 2^binary value  Chips: K2
31541 #define IPC_REG_PLL_MAIN_E28_NDIV_FRAC_BB_A0                                                         0x020260UL //Access:RW   DataWidth:0x14  Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.  Chips: BB_A0
31542 #define IPC_REG_PLL_MAIN_E28_NDIV_FRAC_BB_B0                                                         0x020260UL //Access:RW   DataWidth:0x14  Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.  Chips: BB_B0
31543 #define IPC_REG_PLL_STORM_RANGE_K2                                                                   0x020264UL //Access:RW   DataWidth:0x3   PLL Filter Range 000 = BYPASS 100 = 30-50MHz 001 = 7-11MHz 101 = 50-80MHz 010 = 11-18MHz 110 = 80-130MHz 011 = 18-30MHz 111 = 130-200MHz  Chips: K2
31544 #define IPC_REG_PLL_MAIN_E28_CH0_MDIV_BB_A0                                                          0x020264UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_A0
31545 #define IPC_REG_PLL_MAIN_E28_CH0_MDIV_BB_B0                                                          0x020264UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_B0
31546 #define IPC_REG_PLL_STORM_RESET_K2                                                                   0x020268UL //Access:RW   DataWidth:0x1   pll reset signal  Chips: K2
31547 #define IPC_REG_PLL_MAIN_E28_CH1_MDIV_BB_A0                                                          0x020268UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_A0
31548 #define IPC_REG_PLL_MAIN_E28_CH1_MDIV_BB_B0                                                          0x020268UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_B0
31549 #define IPC_REG_PLL_STORM_BYPASS_K2                                                                  0x02026cUL //Access:RW   DataWidth:0x1   pll bypass signal  Chips: K2
31550 #define IPC_REG_PLL_MAIN_E28_CH2_MDIV_BB_A0                                                          0x02026cUL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-2 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_A0
31551 #define IPC_REG_PLL_MAIN_E28_CH2_MDIV_BB_B0                                                          0x02026cUL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-2 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_B0
31552 #define IPC_REG_PLL_STORM_LOCK_K2                                                                    0x020270UL //Access:R    DataWidth:0x1   pll lock signal  Chips: K2
31553 #define IPC_REG_PLL_MAIN_E28_CH3_MDIV_BB_A0                                                          0x020270UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-3 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_A0
31554 #define IPC_REG_PLL_MAIN_E28_CH3_MDIV_BB_B0                                                          0x020270UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-3 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_B0
31555 #define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_K2                                               0x020274UL //Access:R    DataWidth:0x1   pll lock detected filter status  Chips: K2
31556 #define IPC_REG_PLL_MAIN_E28_CH4_MDIV_BB_A0                                                          0x020274UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-4 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_A0
31557 #define IPC_REG_PLL_MAIN_E28_CH4_MDIV_BB_B0                                                          0x020274UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-4 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_B0
31558 #define IPC_REG_PLL_STORM_NEWDIV_K2                                                                  0x020278UL //Access:RW   DataWidth:0x1   Divider input control  Chips: K2
31559 #define IPC_REG_PLL_MAIN_E28_CH5_MDIV_BB_A0                                                          0x020278UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-5 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_A0
31560 #define IPC_REG_PLL_MAIN_E28_CH5_MDIV_BB_B0                                                          0x020278UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-5 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_B0
31561 #define IPC_REG_PLL_STORM_DIVACK_K2                                                                  0x02027cUL //Access:R    DataWidth:0x1   Divider handshake signal  Chips: K2
31562 #define IPC_REG_PLL_MAIN_E28_CH2_MDEL_BB_A0                                                          0x02027cUL //Access:RW   DataWidth:0x10  Number to VCO clock to delay Channel 2 Global register. Reset on POR reset.  Chips: BB_A0
31563 #define IPC_REG_PLL_MAIN_E28_CH2_MDEL_BB_B0                                                          0x02027cUL //Access:RW   DataWidth:0x10  Number to VCO clock to delay Channel 2 Global register. Reset on POR reset.  Chips: BB_B0
31564 #define IPC_REG_PLL_STORM_LOCK_DETECT_FILTER_STATUS_WAS_CLEARED_K2                                   0x020280UL //Access:RW   DataWidth:0x1   Used for debug, will be set when pll_lock_detect_filter_status went from 1 to 0. This scenario shouldn't happen in normal cases.  Chips: K2
31565 #define IPC_REG_PLL_MAIN_E28_CH3_MDEL_BB_A0                                                          0x020280UL //Access:RW   DataWidth:0x10  Number to VCO clock to delay Channel 3 Global register. Reset on POR reset.  Chips: BB_A0
31566 #define IPC_REG_PLL_MAIN_E28_CH3_MDEL_BB_B0                                                          0x020280UL //Access:RW   DataWidth:0x10  Number to VCO clock to delay Channel 3 Global register. Reset on POR reset.  Chips: BB_B0
31567 #define IPC_REG_MDIO_MODE_BB_A0                                                                      0x020494UL //Access:RW   DataWidth:0x16  [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [0] -> FREE_DIS 1 -> Diable Free running MDIO clock All other field in the register are reserved  Chips: BB_A0
31568 #define IPC_REG_MDIO_MODE_BB_B0                                                                      0x020494UL //Access:RW   DataWidth:0x16  [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [0] -> FREE_DIS 1 -> Diable Free running MDIO clock All other field in the register are reserved  Chips: BB_B0
31569 #define IPC_REG_MDIO_MODE_K2                                                                         0x020284UL //Access:RW   DataWidth:0x16  [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [7:4] RESERVED [3] -> CLAUSE_45/CLAUSE_22 1 -> clause 45 mode 0 -> clause 22 mode [2] -> AUTO_POLL Setting this bit to 1 will enable the auto poll mode which will constantly read from a specified register address 1. clause 22 the register address is always 1 and the phy addr is programable. Clause 45 the register address is always 1 and the deivce type and phy_addr are configurable [1] -> SHORT_PREAMBLE setting this bit will cancell the preamble frame of 32 consecutive 1s [0] -> FREE_DIS 1 -> Disable Free running MDIO clock  Chips: K2
31570 #define IPC_REG_PLL_MAIN_E28_CH4_MDEL_BB_A0                                                          0x020284UL //Access:RW   DataWidth:0x10  Number to VCO clock to delay Channel 4 Global register. Reset on POR reset.  Chips: BB_A0
31571 #define IPC_REG_PLL_MAIN_E28_CH4_MDEL_BB_B0                                                          0x020284UL //Access:RW   DataWidth:0x10  Number to VCO clock to delay Channel 4 Global register. Reset on POR reset.  Chips: BB_B0
31572 #define IPC_REG_MDIO_COMM_BB_A0                                                                      0x02048cUL //Access:RW   DataWidth:0x1e  [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 1 -> Write 2 -> Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction 1 -> SWREG VMGMT 2 -> SWREG VMAIN 3 -> SWREG VANALOG 4 -> SWREG V1p8 [20:16] -> REG_ADDR This value is used to define the register address portion of the MDIO transaction [15:0]  -> DATA When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed.  Chips: BB_A0
31573 #define IPC_REG_MDIO_COMM_BB_B0                                                                      0x02048cUL //Access:RW   DataWidth:0x1e  [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 1 -> Write 2 -> Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction 1 -> SWREG VMGMT 2 -> SWREG VMAIN 3 -> SWREG VANALOG 4 -> SWREG V1p8 [20:16] -> REG_ADDR This value is used to define the register address portion of the MDIO transaction [15:0]  -> DATA When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed.  Chips: BB_B0
31574 #define IPC_REG_MDIO_COMM_K2                                                                         0x020288UL //Access:RW   DataWidth:0x1e  [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 00 -> clause 45 address 01 -> Write 10 -> clause 22 Read, clause 45 read_inc 11 -> clause 45 Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction. [20:16] -> REG_ADDR clause 22 - This value is used to define the register address portion of the MDIO transaction. clause 45 - This value is used to define the device type portion of the MDIO transaction. [15:0]  -> DATA Clause 22: When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. Clause 45: for the first frame, this register contain the adsress of the command. for the second frame, it returns the results of the last MDIO transaction that was performed for read operation or the data to be written for write operation.  Chips: K2
31575 #define IPC_REG_PLL_MAIN_E28_CH5_MDEL_BB_A0                                                          0x020288UL //Access:RW   DataWidth:0x10  Number to VCO clock to delay Channel 5 Global register. Reset on POR reset.  Chips: BB_A0
31576 #define IPC_REG_PLL_MAIN_E28_CH5_MDEL_BB_B0                                                          0x020288UL //Access:RW   DataWidth:0x10  Number to VCO clock to delay Channel 5 Global register. Reset on POR reset.  Chips: BB_B0
31577 #define IPC_REG_MDIO_STATUS_BB_A0                                                                    0x020490UL //Access:R    DataWidth:0x2   [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.  Chips: BB_A0
31578 #define IPC_REG_MDIO_STATUS_BB_B0                                                                    0x020490UL //Access:R    DataWidth:0x2   [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.  Chips: BB_B0
31579 #define IPC_REG_MDIO_STATUS_K2                                                                       0x02028cUL //Access:R    DataWidth:0x2   [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.  Chips: K2
31580 #define IPC_REG_PLL_MAIN_E28_CH_DELAY_DONE_BB_A0                                                     0x02028cUL //Access:R    DataWidth:0x4   Delay for each channel 2-5 is completed.  Chips: BB_A0
31581 #define IPC_REG_PLL_MAIN_E28_CH_DELAY_DONE_BB_B0                                                     0x02028cUL //Access:R    DataWidth:0x4   Delay for each channel 2-5 is completed.  Chips: BB_B0
31582 #define IPC_REG_SGMII_MDIO_ADDR_K2                                                                   0x020290UL //Access:RW   DataWidth:0x5   PHY Address for MDIO Transaction  Chips: K2
31583 #define IPC_REG_PLL_MAIN_E28_CH_ENABLEB_BB_A0                                                        0x020290UL //Access:RW   DataWidth:0x6   Active Low Channel Enable. Global register. Reset on POR reset.  Chips: BB_A0
31584 #define IPC_REG_PLL_MAIN_E28_CH_ENABLEB_BB_B0                                                        0x020290UL //Access:RW   DataWidth:0x6   Active Low Channel Enable. Global register. Reset on POR reset.  Chips: BB_B0
31585 #define IPC_REG_SGMII_RSTB_MDIOREGS_K2                                                               0x020294UL //Access:RW   DataWidth:0x1   reset of sgmii mdio registers. This is an active high reset. The name "rstb" is mistakenly suggest an active low reset.  Chips: K2
31586 #define IPC_REG_PLL_MAIN_E28_CTRL_0_BB_A0                                                            0x020294UL //Access:RW   DataWidth:0x20  PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved  Chips: BB_A0
31587 #define IPC_REG_PLL_MAIN_E28_CTRL_0_BB_B0                                                            0x020294UL //Access:RW   DataWidth:0x20  PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved  Chips: BB_B0
31588 #define IPC_REG_FREQ_CAPTURE_BB_A0                                                                   0x0204a4UL //Access:W    DataWidth:0x1   Setting this bit high will result in the HW to capture the frequency of Main, STORM and NW clocks. This is a self clearing bit.  Chips: BB_A0
31589 #define IPC_REG_FREQ_CAPTURE_BB_B0                                                                   0x0204a4UL //Access:W    DataWidth:0x1   Setting this bit high will result in the HW to capture the frequency of Main, STORM and NW clocks. This is a self clearing bit.  Chips: BB_B0
31590 #define IPC_REG_FREQ_CAPTURE_K2                                                                      0x020298UL //Access:W    DataWidth:0x1   Setting this bit high will result in the HW to capture the frequency of Main, STORM and NWM clocks. This is a self clearing bit.  Chips: K2
31591 #define IPC_REG_PLL_MAIN_E28_CTRL_1_BB_A0                                                            0x020298UL //Access:RW   DataWidth:0x20  PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved  Chips: BB_A0
31592 #define IPC_REG_PLL_MAIN_E28_CTRL_1_BB_B0                                                            0x020298UL //Access:RW   DataWidth:0x20  PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved  Chips: BB_B0
31593 #define IPC_REG_FREQ_MAIN_BB_A0                                                                      0x0204a8UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: BB_A0
31594 #define IPC_REG_FREQ_MAIN_BB_B0                                                                      0x0204a8UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: BB_B0
31595 #define IPC_REG_FREQ_MAIN_K2                                                                         0x02029cUL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: K2
31596     #define IPC_REG_FREQ_MAIN_CNT                                                                    (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. Main Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement.
31597     #define IPC_REG_FREQ_MAIN_CNT_SHIFT                                                              0
31598     #define IPC_REG_FREQ_MAIN_CNT_VALID                                                              (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
31599     #define IPC_REG_FREQ_MAIN_CNT_VALID_SHIFT                                                        16
31600 #define IPC_REG_PLL_MAIN_E28_KA_BB_A0                                                                0x02029cUL //Access:RW   DataWidth:0x3   Loop gain in frequency acquisition mode Global register. Reset on POR reset.  Chips: BB_A0
31601 #define IPC_REG_PLL_MAIN_E28_KA_BB_B0                                                                0x02029cUL //Access:RW   DataWidth:0x3   Loop gain in frequency acquisition mode Global register. Reset on POR reset.  Chips: BB_B0
31602 #define IPC_REG_FREQ_STORM_BB_A0                                                                     0x0204acUL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: BB_A0
31603 #define IPC_REG_FREQ_STORM_BB_B0                                                                     0x0204acUL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: BB_B0
31604 #define IPC_REG_FREQ_STORM_K2                                                                        0x0202a0UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: K2
31605     #define IPC_REG_FREQ_STORM_CNT                                                                   (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. Storm Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement.
31606     #define IPC_REG_FREQ_STORM_CNT_SHIFT                                                             0
31607     #define IPC_REG_FREQ_STORM_CNT_VALID                                                             (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
31608     #define IPC_REG_FREQ_STORM_CNT_VALID_SHIFT                                                       16
31609 #define IPC_REG_PLL_MAIN_E28_KI_BB_A0                                                                0x0202a0UL //Access:RW   DataWidth:0x3   Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset.  Chips: BB_A0
31610 #define IPC_REG_PLL_MAIN_E28_KI_BB_B0                                                                0x0202a0UL //Access:RW   DataWidth:0x3   Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset.  Chips: BB_B0
31611 #define IPC_REG_FREQ_NWM_K2                                                                          0x0202a4UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: K2
31612     #define IPC_REG_FREQ_NWM_CNT                                                                     (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. NW Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement.
31613     #define IPC_REG_FREQ_NWM_CNT_SHIFT                                                               0
31614     #define IPC_REG_FREQ_NWM_CNT_VALID                                                               (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
31615     #define IPC_REG_FREQ_NWM_CNT_VALID_SHIFT                                                         16
31616 #define IPC_REG_PLL_MAIN_E28_KP_BB_A0                                                                0x0202a4UL //Access:RW   DataWidth:0x4   Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset.  Chips: BB_A0
31617 #define IPC_REG_PLL_MAIN_E28_KP_BB_B0                                                                0x0202a4UL //Access:RW   DataWidth:0x4   Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset.  Chips: BB_B0
31618 #define IPC_REG_FREE_RUNNING_CNTR_0_BB_A0                                                            0x0204b4UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 1us resolution.  Chips: BB_A0
31619 #define IPC_REG_FREE_RUNNING_CNTR_0_BB_B0                                                            0x0204b4UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 1us resolution.  Chips: BB_B0
31620 #define IPC_REG_FREE_RUNNING_CNTR_0_K2                                                               0x0202a8UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 1us resolution.  Chips: K2
31621 #define IPC_REG_PLL_MAIN_E28_LOCK_BB_A0                                                              0x0202a8UL //Access:R    DataWidth:0x1   LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.  Chips: BB_A0
31622 #define IPC_REG_PLL_MAIN_E28_LOCK_BB_B0                                                              0x0202a8UL //Access:R    DataWidth:0x1   LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.  Chips: BB_B0
31623 #define IPC_REG_FREE_RUNNING_CNTR_1_BB_A0                                                            0x0204b8UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 16us resolution.  Chips: BB_A0
31624 #define IPC_REG_FREE_RUNNING_CNTR_1_BB_B0                                                            0x0204b8UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 16us resolution.  Chips: BB_B0
31625 #define IPC_REG_FREE_RUNNING_CNTR_1_K2                                                               0x0202acUL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 16us resolution.  Chips: K2
31626 #define IPC_REG_PLL_MAIN_E28_STATUS_BB_A0                                                            0x0202acUL //Access:R    DataWidth:0xc   Status Bits from the PLL Global register. Reset on POR reset.  Chips: BB_A0
31627 #define IPC_REG_PLL_MAIN_E28_STATUS_BB_B0                                                            0x0202acUL //Access:R    DataWidth:0xc   Status Bits from the PLL Global register. Reset on POR reset.  Chips: BB_B0
31628 #define IPC_REG_FREE_RUNNING_CNTR_2_BB_A0                                                            0x0204bcUL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 256us resolution.  Chips: BB_A0
31629 #define IPC_REG_FREE_RUNNING_CNTR_2_BB_B0                                                            0x0204bcUL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 256us resolution.  Chips: BB_B0
31630 #define IPC_REG_FREE_RUNNING_CNTR_2_K2                                                               0x0202b0UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 256us resolution.  Chips: K2
31631 #define IPC_REG_PLL_NW_E28_PWRDN_BB_A0                                                               0x0202b0UL //Access:RW   DataWidth:0x1   PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR  Chips: BB_A0
31632 #define IPC_REG_PLL_NW_E28_PWRDN_BB_B0                                                               0x0202b0UL //Access:RW   DataWidth:0x1   PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR  Chips: BB_B0
31633 #define IPC_REG_FREE_RUNNING_CNTR_3_BB_A0                                                            0x0204c0UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 4096us resolution.  Chips: BB_A0
31634 #define IPC_REG_FREE_RUNNING_CNTR_3_BB_B0                                                            0x0204c0UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 4096us resolution.  Chips: BB_B0
31635 #define IPC_REG_FREE_RUNNING_CNTR_3_K2                                                               0x0202b4UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 4096us resolution.  Chips: K2
31636 #define IPC_REG_PLL_NW_E28_RESET_VCO_BB_A0                                                           0x0202b4UL //Access:RW   DataWidth:0x1   Resets the VCO logic in the PLL. The reset is Active High  Chips: BB_A0
31637 #define IPC_REG_PLL_NW_E28_RESET_VCO_BB_B0                                                           0x0202b4UL //Access:RW   DataWidth:0x1   Resets the VCO logic in the PLL. The reset is Active High  Chips: BB_B0
31638 #define IPC_REG_FREE_RUNNING_CNTR_4_BB_A0                                                            0x0204c4UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 65536us resolution.  Chips: BB_A0
31639 #define IPC_REG_FREE_RUNNING_CNTR_4_BB_B0                                                            0x0204c4UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 65536us resolution.  Chips: BB_B0
31640 #define IPC_REG_FREE_RUNNING_CNTR_4_K2                                                               0x0202b8UL //Access:R    DataWidth:0x20  This is a 32-bit free running counter that has 65536us resolution.  Chips: K2
31641 #define IPC_REG_PLL_NW_E28_RESET_POST_BB_A0                                                          0x0202b8UL //Access:RW   DataWidth:0x1   Resets the Post Divider logic in the PLL. The reset is Active High  Chips: BB_A0
31642 #define IPC_REG_PLL_NW_E28_RESET_POST_BB_B0                                                          0x0202b8UL //Access:RW   DataWidth:0x1   Resets the Post Divider logic in the PLL. The reset is Active High  Chips: BB_B0
31643 #define IPC_REG_VMAIN_POR_STATUS_BB_A0                                                               0x0204c8UL //Access:R    DataWidth:0x1   This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up  Chips: BB_A0
31644 #define IPC_REG_VMAIN_POR_STATUS_BB_B0                                                               0x0204c8UL //Access:R    DataWidth:0x1   This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up  Chips: BB_B0
31645 #define IPC_REG_VMAIN_POR_STATUS_K2                                                                  0x0202bcUL //Access:R    DataWidth:0x1   This register shows the current status of the VMAIN POR. 0 -> VMAIN is down 1 -> VMAIN is up  Chips: K2
31646 #define IPC_REG_PLL_NW_E28_PDIV_BB_A0                                                                0x0202bcUL //Access:RW   DataWidth:0x4   Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.  Chips: BB_A0
31647 #define IPC_REG_PLL_NW_E28_PDIV_BB_B0                                                                0x0202bcUL //Access:RW   DataWidth:0x4   Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.  Chips: BB_B0
31648 #define IPC_REG_STAT_VMAIN_POR_ASSERTION_BB_A0                                                       0x0204ccUL //Access:RC   DataWidth:0x8   This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down.  Chips: BB_A0
31649 #define IPC_REG_STAT_VMAIN_POR_ASSERTION_BB_B0                                                       0x0204ccUL //Access:RC   DataWidth:0x8   This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down.  Chips: BB_B0
31650 #define IPC_REG_STAT_VMAIN_POR_ASSERTION_K2                                                          0x0202c0UL //Access:RC   DataWidth:0x8   This register provides the number of times VMAIN POR was asserted. This would be the count of number of times VMAIN went down.  Chips: K2
31651 #define IPC_REG_PLL_NW_E28_NDIV_INT_BB_A0                                                            0x0202c0UL //Access:RW   DataWidth:0xa   Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset.  Chips: BB_A0
31652 #define IPC_REG_PLL_NW_E28_NDIV_INT_BB_B0                                                            0x0202c0UL //Access:RW   DataWidth:0xa   Feedback divider control 0000000000= divide-by-1024 0000000001= XXX 0000000010= XXX : 0000001011= XXX 0000001100= divide-by-12 0000001101= divide-by-13 0000001110= divide-by-14 : 1111111110= divide-by-1022 1111111111= divide-by-1023 Global register. Reset on POR reset.  Chips: BB_B0
31653 #define IPC_REG_STAT_VMAIN_POR_DEASSERTION_BB_A0                                                     0x0204d0UL //Access:RC   DataWidth:0x8   This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up.  Chips: BB_A0
31654 #define IPC_REG_STAT_VMAIN_POR_DEASSERTION_BB_B0                                                     0x0204d0UL //Access:RC   DataWidth:0x8   This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up.  Chips: BB_B0
31655 #define IPC_REG_STAT_VMAIN_POR_DEASSERTION_K2                                                        0x0202c4UL //Access:RC   DataWidth:0x8   This register provides the number of times VMAIN POR was de-asserted. This would be the count of number of times VMAIN came up.  Chips: K2
31656 #define IPC_REG_PLL_NW_E28_NDIV_FRAC_BB_A0                                                           0x0202c4UL //Access:RW   DataWidth:0x14  Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.  Chips: BB_A0
31657 #define IPC_REG_PLL_NW_E28_NDIV_FRAC_BB_B0                                                           0x0202c4UL //Access:RW   DataWidth:0x14  Fractional feedback divider control. Resolution= 1/(2^20). Global register. Reset on POR reset.  Chips: BB_B0
31658 #define IPC_REG_PERST_POR_STATUS_BB_A0                                                               0x0204d4UL //Access:R    DataWidth:0x1   This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted  Chips: BB_A0
31659 #define IPC_REG_PERST_POR_STATUS_BB_B0                                                               0x0204d4UL //Access:R    DataWidth:0x1   This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted  Chips: BB_B0
31660 #define IPC_REG_PERST_POR_STATUS_K2                                                                  0x0202c8UL //Access:R    DataWidth:0x1   This register shows the current status of the PERST#. 0 -> PERST is asserted 1 -> PERST is de-asserted  Chips: K2
31661 #define IPC_REG_PLL_NW_E28_CH0_MDIV_BB_A0                                                            0x0202c8UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_A0
31662 #define IPC_REG_PLL_NW_E28_CH0_MDIV_BB_B0                                                            0x0202c8UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-0 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_B0
31663 #define IPC_REG_STAT_PERST_ASSERTION_BB_A0                                                           0x0204d8UL //Access:RC   DataWidth:0x8   This register provides the number of times PERST# was asserted  Chips: BB_A0
31664 #define IPC_REG_STAT_PERST_ASSERTION_BB_B0                                                           0x0204d8UL //Access:RC   DataWidth:0x8   This register provides the number of times PERST# was asserted  Chips: BB_B0
31665 #define IPC_REG_STAT_PERST_ASSERTION_K2                                                              0x0202ccUL //Access:RC   DataWidth:0x8   This register provides the number of times PERST# was asserted  Chips: K2
31666 #define IPC_REG_PLL_NW_E28_CH1_MDIV_BB_A0                                                            0x0202ccUL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_A0
31667 #define IPC_REG_PLL_NW_E28_CH1_MDIV_BB_B0                                                            0x0202ccUL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-1 00000000: 256 00000001: 1 00000010: 2 00000011: 3 : : 11111101: 253 11111110: 254 11111111: 255 Global register. Reset on POR reset.  Chips: BB_B0
31668 #define IPC_REG_STAT_PERST_DEASSERTION_BB_A0                                                         0x0204dcUL //Access:RC   DataWidth:0x8   This register provides the number of times PERST# was de-asserted  Chips: BB_A0
31669 #define IPC_REG_STAT_PERST_DEASSERTION_BB_B0                                                         0x0204dcUL //Access:RC   DataWidth:0x8   This register provides the number of times PERST# was de-asserted  Chips: BB_B0
31670 #define IPC_REG_STAT_PERST_DEASSERTION_K2                                                            0x0202d0UL //Access:RC   DataWidth:0x8   This register provides the number of times PERST# was de-asserted  Chips: K2
31671 #define IPC_REG_PLL_NW_E28_CH_ENABLEB_BB_A0                                                          0x0202d0UL //Access:RW   DataWidth:0x6   Active Low Channel Enable. Global register. Reset on POR reset.  Chips: BB_A0
31672 #define IPC_REG_PLL_NW_E28_CH_ENABLEB_BB_B0                                                          0x0202d0UL //Access:RW   DataWidth:0x6   Active Low Channel Enable. Global register. Reset on POR reset.  Chips: BB_B0
31673 #define IPC_REG_CHIP_MODE_BB_A0                                                                      0x0204e0UL //Access:R    DataWidth:0x6   This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode  Chips: BB_A0
31674 #define IPC_REG_CHIP_MODE_BB_B0                                                                      0x0204e0UL //Access:R    DataWidth:0x6   This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode  Chips: BB_B0
31675 #define IPC_REG_CHIP_MODE_K2                                                                         0x0202d4UL //Access:R    DataWidth:0x6   This register shows the current status of the Mode Pins of the chip. 6'bXX0000 -> Mission Mode 6'bXX0001 -> Scan Mode 6'bXX0010 -> Debug Mode 6'bXX0011 -> PCIe SERDES Standalone mode 6'bXX0100 -> MAC SERDES Standalone mode 6'bXX0101 -> IDDQ Mode 6'bXX0110 -> OVSTB Mode 6'bX1XXXX -> Run all the modes in Fast Reset (useful in Simulation/ATE) 6'b1XXXXX -> Run all the modes in POR Bypass mode  Chips: K2
31676 #define IPC_REG_PLL_NW_E28_CTRL_0_BB_A0                                                              0x0202d4UL //Access:RW   DataWidth:0x20  PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved  Chips: BB_A0
31677 #define IPC_REG_PLL_NW_E28_CTRL_0_BB_B0                                                              0x0202d4UL //Access:RW   DataWidth:0x20  PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved  Chips: BB_B0
31678 #define IPC_REG_HW_STRAPS_BB_A0                                                                      0x0204e4UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: BB_A0
31679 #define IPC_REG_HW_STRAPS_BB_B0                                                                      0x0204e4UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: BB_B0
31680 #define IPC_REG_HW_STRAPS_K2                                                                         0x0202d8UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: K2
31681     #define IPC_REG_HW_STRAPS_TESTIN_STRAPS                                                          (0xff<<0) // Strap value on TEST IN pins
31682     #define IPC_REG_HW_STRAPS_TESTIN_STRAPS_SHIFT                                                    0
31683     #define IPC_REG_HW_STRAPS_FLASH_STRAPS                                                           (0xf<<8) // Strap value on FLASH pins
31684     #define IPC_REG_HW_STRAPS_FLASH_STRAPS_SHIFT                                                     8
31685 #define IPC_REG_PLL_NW_E28_CTRL_1_BB_A0                                                              0x0202d8UL //Access:RW   DataWidth:0x20  PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved  Chips: BB_A0
31686 #define IPC_REG_PLL_NW_E28_CTRL_1_BB_B0                                                              0x0202d8UL //Access:RW   DataWidth:0x20  PLL Control Register [11:0] dco_ctrl_bypass[11:0] direct programming of DAC: 00...00 = MIN VCO clock frequency : 11...11 = MAX VCO clock frequency [12] dco_ctrl_bypass_enable enable of direct programming of DAC: 0 =normal mode 1 =DAC programming mode [13] stat_reset reset of phase error measurement: 0 =normal mode 1 =reset [16:14] stat_select[2:0] select of test output: 000 = 000000000000 001 = minimum phase error 010 = maximum phase error 011 = lock_state 100 = dac control word 101 = 000000000000 110 = 000000000000 111 = 000000000000 [17] stat_update On the synchronized rising edge of this control signal the value selected by stat_select[2:0] is clocked into o_statout [19:18] Reserved [21:20] Stat_mode[1:0] Statistics Mode 00 = disabled 01 = phase error stats 10 : period stats 11 : Feedback phase error stats [23:22] Pwm_rate[1:0] Set PWM rate Vco_fb_div2 == 0 00 = 5 ( default) 01 = 4 10 = 3 11 = 2 Vco_fb_div2 == 1 00 = 10 (default) 01 = 8 10 = 6 11 = 4 00 for VCO gt 800MHz 10 for VCO lt 800MHz [25:24] post_resetb select post channel resetb selection 00 = lock or post_resetb 01 = flock or post_resetb 10 = resetb or post_resetb 11 = post_resetb [26] vco_fb_div2 Divide vco_fdbk clock by 2 0= vco clock 1=vco/2 clock 0 for VCO lt 2.0GHz 1 for VCO gt 2.0GHz [27] fast_lock Reduces the number of refclk cycles of delay between frequency lock and setting o_lock output high. 0 = 256 refclk delay 1 = 32 refclk delay [28] ndiv_relock Forces lock state machine to return to frequency acquisition state when ndiv_int/ndiv_frac changes. 0 = Loop responds to ndiv change. May or may not switch back to frequency acquisition mode. 1 = Re-enter frequency acquisition state, without resetting the initial frequency (starts from current frequency). This produces smoother transition to new frequency for steps greater than 1 percent [29] Reserved [31:30] Vco_range Set VCO frequency range 00 = 800 - 2000 MHz 01 = 500 - 1200 MHz 10 = 1600 - 4000 MHz [33:32] LDO[1:0] LDO output voltage control 00 = 1.05 V 01 = 1.00 V 10 = 0.95 V 11 = 0.90 V [34] testout_en Test output buffer enable 0= normal mode 1= test output buffer enable [37:35] testout_sel Test output clock selection 000 = no clock 001 = o_fref 010 = o_clkout[0] 011 = o_clkout[1] 100 = o_clkout[2] 101 = o_clkout[3] 110 = o_clkout[4] 111 = o_clkout[5] [63:38] Reserved  Chips: BB_B0
31687 #define IPC_REG_INT_STS_0_BB_A0                                                                      0x02050cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: BB_A0
31688 #define IPC_REG_INT_STS_0_BB_B0                                                                      0x02050cUL //Access:R    DataWidth:0x10  Multi Field Register.  Chips: BB_B0
31689 #define IPC_REG_INT_STS_0_K2                                                                         0x0202dcUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
31690     #define IPC_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
31691     #define IPC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
31692     #define IPC_REG_INT_STS_0_VMAIN_POR_ASSERT                                                       (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
31693     #define IPC_REG_INT_STS_0_VMAIN_POR_ASSERT_SHIFT                                                 4
31694     #define IPC_REG_INT_STS_0_VMAIN_POR_DEASSERT                                                     (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
31695     #define IPC_REG_INT_STS_0_VMAIN_POR_DEASSERT_SHIFT                                               5
31696     #define IPC_REG_INT_STS_0_PERST_ASSERT                                                           (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
31697     #define IPC_REG_INT_STS_0_PERST_ASSERT_SHIFT                                                     6
31698     #define IPC_REG_INT_STS_0_PERST_DEASSERT                                                         (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
31699     #define IPC_REG_INT_STS_0_PERST_DEASSERT_SHIFT                                                   7
31700     #define IPC_REG_INT_STS_0_OTP_ECC_DED_0                                                          (0x1<<8) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
31701     #define IPC_REG_INT_STS_0_OTP_ECC_DED_0_SHIFT                                                    8
31702     #define IPC_REG_INT_STS_0_OTP_ECC_DED_1                                                          (0x1<<9) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 1 is asserted.
31703     #define IPC_REG_INT_STS_0_OTP_ECC_DED_1_SHIFT                                                    9
31704     #define IPC_REG_INT_STS_0_OTP_ECC_DED_2                                                          (0x1<<10) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 2 is asserted.
31705     #define IPC_REG_INT_STS_0_OTP_ECC_DED_2_SHIFT                                                    10
31706     #define IPC_REG_INT_STS_0_OTP_ECC_DED_3                                                          (0x1<<11) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 3 is asserted.
31707     #define IPC_REG_INT_STS_0_OTP_ECC_DED_3_SHIFT                                                    11
31708     #define IPC_REG_INT_STS_0_OTP_ECC_DED_4                                                          (0x1<<12) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 4 is asserted.
31709     #define IPC_REG_INT_STS_0_OTP_ECC_DED_4_SHIFT                                                    12
31710     #define IPC_REG_INT_STS_0_OTP_ECC_DED_5                                                          (0x1<<13) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 5 is asserted.
31711     #define IPC_REG_INT_STS_0_OTP_ECC_DED_5_SHIFT                                                    13
31712     #define IPC_REG_INT_STS_0_OTP_ECC_DED_6                                                          (0x1<<14) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 6 is asserted.
31713     #define IPC_REG_INT_STS_0_OTP_ECC_DED_6_SHIFT                                                    14
31714     #define IPC_REG_INT_STS_0_OTP_ECC_DED_7                                                          (0x1<<15) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
31715     #define IPC_REG_INT_STS_0_OTP_ECC_DED_7_SHIFT                                                    15
31716 #define IPC_REG_PLL_NW_E28_KA_BB_A0                                                                  0x0202dcUL //Access:RW   DataWidth:0x3   Loop gain in frequency acquisition mode Global register. Reset on POR reset.  Chips: BB_A0
31717 #define IPC_REG_PLL_NW_E28_KA_BB_B0                                                                  0x0202dcUL //Access:RW   DataWidth:0x3   Loop gain in frequency acquisition mode Global register. Reset on POR reset.  Chips: BB_B0
31718 #define IPC_REG_INT_MASK_0_BB_A0                                                                     0x020510UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0
31719 #define IPC_REG_INT_MASK_0_BB_B0                                                                     0x020510UL //Access:RW   DataWidth:0x10  Multi Field Register.  Chips: BB_B0
31720 #define IPC_REG_INT_MASK_0_K2                                                                        0x0202e0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
31721     #define IPC_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.ADDRESS_ERROR .
31722     #define IPC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
31723     #define IPC_REG_INT_MASK_0_VMAIN_POR_ASSERT                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.VMAIN_POR_ASSERT .
31724     #define IPC_REG_INT_MASK_0_VMAIN_POR_ASSERT_SHIFT                                                4
31725     #define IPC_REG_INT_MASK_0_VMAIN_POR_DEASSERT                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.VMAIN_POR_DEASSERT .
31726     #define IPC_REG_INT_MASK_0_VMAIN_POR_DEASSERT_SHIFT                                              5
31727     #define IPC_REG_INT_MASK_0_PERST_ASSERT                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.PERST_ASSERT .
31728     #define IPC_REG_INT_MASK_0_PERST_ASSERT_SHIFT                                                    6
31729     #define IPC_REG_INT_MASK_0_PERST_DEASSERT                                                        (0x1<<7) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.PERST_DEASSERT .
31730     #define IPC_REG_INT_MASK_0_PERST_DEASSERT_SHIFT                                                  7
31731     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_0                                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_0 .
31732     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_0_SHIFT                                                   8
31733     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_1                                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_1 .
31734     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_1_SHIFT                                                   9
31735     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_2                                                         (0x1<<10) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_2 .
31736     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_2_SHIFT                                                   10
31737     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_3                                                         (0x1<<11) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_3 .
31738     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_3_SHIFT                                                   11
31739     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_4                                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_4 .
31740     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_4_SHIFT                                                   12
31741     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_5                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_5 .
31742     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_5_SHIFT                                                   13
31743     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_6                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_6 .
31744     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_6_SHIFT                                                   14
31745     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_7                                                         (0x1<<15) // This bit masks, when set, the Interrupt bit: IPC_REG_INT_STS_0.OTP_ECC_DED_7 .
31746     #define IPC_REG_INT_MASK_0_OTP_ECC_DED_7_SHIFT                                                   15
31747 #define IPC_REG_PLL_NW_E28_KI_BB_A0                                                                  0x0202e0UL //Access:RW   DataWidth:0x3   Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset.  Chips: BB_A0
31748 #define IPC_REG_PLL_NW_E28_KI_BB_B0                                                                  0x0202e0UL //Access:RW   DataWidth:0x3   Gain of P/I loop filter integrator path during fine phase acquisition mode Global register. Reset on POR reset.  Chips: BB_B0
31749 #define IPC_REG_INT_STS_WR_0_BB_A0                                                                   0x020514UL //Access:WR   DataWidth:0x8   Multi Field Register.  Chips: BB_A0
31750 #define IPC_REG_INT_STS_WR_0_BB_B0                                                                   0x020514UL //Access:WR   DataWidth:0x10  Multi Field Register.  Chips: BB_B0
31751 #define IPC_REG_INT_STS_WR_0_K2                                                                      0x0202e4UL //Access:WR   DataWidth:0x8   Multi Field Register.  Chips: K2
31752     #define IPC_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
31753     #define IPC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
31754     #define IPC_REG_INT_STS_WR_0_VMAIN_POR_ASSERT                                                    (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
31755     #define IPC_REG_INT_STS_WR_0_VMAIN_POR_ASSERT_SHIFT                                              4
31756     #define IPC_REG_INT_STS_WR_0_VMAIN_POR_DEASSERT                                                  (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
31757     #define IPC_REG_INT_STS_WR_0_VMAIN_POR_DEASSERT_SHIFT                                            5
31758     #define IPC_REG_INT_STS_WR_0_PERST_ASSERT                                                        (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
31759     #define IPC_REG_INT_STS_WR_0_PERST_ASSERT_SHIFT                                                  6
31760     #define IPC_REG_INT_STS_WR_0_PERST_DEASSERT                                                      (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
31761     #define IPC_REG_INT_STS_WR_0_PERST_DEASSERT_SHIFT                                                7
31762     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_0                                                       (0x1<<8) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
31763     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_0_SHIFT                                                 8
31764     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_1                                                       (0x1<<9) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 1 is asserted.
31765     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_1_SHIFT                                                 9
31766     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_2                                                       (0x1<<10) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 2 is asserted.
31767     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_2_SHIFT                                                 10
31768     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_3                                                       (0x1<<11) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 3 is asserted.
31769     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_3_SHIFT                                                 11
31770     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_4                                                       (0x1<<12) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 4 is asserted.
31771     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_4_SHIFT                                                 12
31772     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_5                                                       (0x1<<13) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 5 is asserted.
31773     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_5_SHIFT                                                 13
31774     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_6                                                       (0x1<<14) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 6 is asserted.
31775     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_6_SHIFT                                                 14
31776     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_7                                                       (0x1<<15) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
31777     #define IPC_REG_INT_STS_WR_0_OTP_ECC_DED_7_SHIFT                                                 15
31778 #define IPC_REG_PLL_NW_E28_KP_BB_A0                                                                  0x0202e4UL //Access:RW   DataWidth:0x4   Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset.  Chips: BB_A0
31779 #define IPC_REG_PLL_NW_E28_KP_BB_B0                                                                  0x0202e4UL //Access:RW   DataWidth:0x4   Gain of P/I loop filter proportional path during fine phase acquisition mode. SW needs to use the following transformation to program this register. For 0, Write 0 For 1, Write 1 For 2, Write 4 For 3, Write 5 For 4, Write 2 For 5, Write 3 For 6, Write 6 For 7, Write 7 For 8, Write 8 For 9, Write 9 For 10, Write 12 For 11, Write 13 For 12, Write 10 For 13, Write 11 For 14, Write 14 For 15, Write 15 A default of 5 implies that the PLL sees a value of 3. Global register. Reset on POR reset.  Chips: BB_B0
31780 #define IPC_REG_INT_STS_CLR_0_BB_A0                                                                  0x020518UL //Access:RC   DataWidth:0x8   Multi Field Register.  Chips: BB_A0
31781 #define IPC_REG_INT_STS_CLR_0_BB_B0                                                                  0x020518UL //Access:RC   DataWidth:0x10  Multi Field Register.  Chips: BB_B0
31782 #define IPC_REG_INT_STS_CLR_0_K2                                                                     0x0202e8UL //Access:RC   DataWidth:0x8   Multi Field Register.  Chips: K2
31783     #define IPC_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
31784     #define IPC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
31785     #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_ASSERT                                                   (0x1<<4) // This bit generates an interrupt when VMAIN POR is asserted, ie VMAIN goes from high to low
31786     #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_ASSERT_SHIFT                                             4
31787     #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_DEASSERT                                                 (0x1<<5) // This bit generates an interrupt when VMAIN POR is de-asserted, ie VMAIN goes from low to high
31788     #define IPC_REG_INT_STS_CLR_0_VMAIN_POR_DEASSERT_SHIFT                                           5
31789     #define IPC_REG_INT_STS_CLR_0_PERST_ASSERT                                                       (0x1<<6) // This bit generates an interrupt when PERST# is asserted, ie PERST# goes from high to low
31790     #define IPC_REG_INT_STS_CLR_0_PERST_ASSERT_SHIFT                                                 6
31791     #define IPC_REG_INT_STS_CLR_0_PERST_DEASSERT                                                     (0x1<<7) // This bit generates an interrupt when PERST# is de-asserted, ie PERST# goes from low to high
31792     #define IPC_REG_INT_STS_CLR_0_PERST_DEASSERT_SHIFT                                               7
31793     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_0                                                      (0x1<<8) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
31794     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_0_SHIFT                                                8
31795     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_1                                                      (0x1<<9) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 1 is asserted.
31796     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_1_SHIFT                                                9
31797     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_2                                                      (0x1<<10) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 2 is asserted.
31798     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_2_SHIFT                                                10
31799     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_3                                                      (0x1<<11) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 3 is asserted.
31800     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_3_SHIFT                                                11
31801     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_4                                                      (0x1<<12) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 4 is asserted.
31802     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_4_SHIFT                                                12
31803     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_5                                                      (0x1<<13) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 5 is asserted.
31804     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_5_SHIFT                                                13
31805     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_6                                                      (0x1<<14) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 6 is asserted.
31806     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_6_SHIFT                                                14
31807     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_7                                                      (0x1<<15) // This bit generates an interrupt when         Fdone Double Error Detection status flag  for AUTOLOAD word 0 is asserted.
31808     #define IPC_REG_INT_STS_CLR_0_OTP_ECC_DED_7_SHIFT                                                15
31809 #define IPC_REG_PLL_NW_E28_LOCK_BB_A0                                                                0x0202e8UL //Access:R    DataWidth:0x1   LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.  Chips: BB_A0
31810 #define IPC_REG_PLL_NW_E28_LOCK_BB_B0                                                                0x0202e8UL //Access:R    DataWidth:0x1   LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.  Chips: BB_B0
31811 #define IPC_REG_JTAG_COMPLIANCE_BB_A0                                                                0x020508UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0
31812 #define IPC_REG_JTAG_COMPLIANCE_BB_B0                                                                0x020508UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0
31813 #define IPC_REG_JTAG_COMPLIANCE_K2                                                                   0x0202ecUL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: K2
31814     #define IPC_REG_JTAG_COMPLIANCE_EN                                                               (0x3<<0) // These bits set the compliance enable for JTAG pins. the JTAG interface is shared by four masters and there is a dedicated 2-bit compliance enable pins on the ballout. These bits are used to override the pins if needed. 2'b00 --> LV JTAG is selected 2'b01 --> AVS JTAG is selected 2'b10 --> MCP EJTAG is selected 2'b11 --> AVS EJTAG is selected
31815     #define IPC_REG_JTAG_COMPLIANCE_EN_SHIFT                                                         0
31816     #define IPC_REG_JTAG_COMPLIANCE_OVERRIDE                                                         (0x1<<4) // Set this bit to override the pins on the chip with bits[1:0]
31817     #define IPC_REG_JTAG_COMPLIANCE_OVERRIDE_SHIFT                                                   4
31818 #define IPC_REG_PLL_NW_E28_STATUS_BB_A0                                                              0x0202ecUL //Access:R    DataWidth:0xc   Status Bits from the PLL Global register. Reset on POR reset.  Chips: BB_A0
31819 #define IPC_REG_PLL_NW_E28_STATUS_BB_B0                                                              0x0202ecUL //Access:R    DataWidth:0xc   Status Bits from the PLL Global register. Reset on POR reset.  Chips: BB_B0
31820 #define IPC_REG_TCAM_BIST_REGISTER_OR_EXTERNAL_SELECT_K2                                             0x0202f0UL //Access:RW   DataWidth:0x1   0 - control of the tcam bist is from the IPC register tcam_bist_control and tcam_bist_num. 1 - control of the tcam bist is from the external pins. by default these pins are gurenteed to be zero so tcam bist will not start running.  Chips: K2
31821 #define IPC_REG_PLL_STORM_E28_PWRDN_BB_A0                                                            0x0202f0UL //Access:RW   DataWidth:0x1   PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR  Chips: BB_A0
31822 #define IPC_REG_PLL_STORM_E28_PWRDN_BB_B0                                                            0x0202f0UL //Access:RW   DataWidth:0x1   PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR  Chips: BB_B0
31823 #define IPC_REG_TCAM_BIST_NUM_K2                                                                     0x0202f4UL //Access:RW   DataWidth:0x5   select the cam instance when reading the status of the cam in tcam_bist_status 0 ccfc_ccam 1 ccfc_scam 2 igu 3 msem 4 prs_gft 5 prs_h 6 prs_l 7 psem 8 psem_vfc 9 qm 10 tcfc_ccam 11 tsem 12 tsem_vfc 13 usem 14 xsem 15 ysem  Chips: K2
31824 #define IPC_REG_PLL_STORM_E28_RESET_VCO_BB_A0                                                        0x0202f4UL //Access:RW   DataWidth:0x1   Resets the VCO logic in the PLL. The reset is Active High  Chips: BB_A0
31825 #define IPC_REG_PLL_STORM_E28_RESET_VCO_BB_B0                                                        0x0202f4UL //Access:RW   DataWidth:0x1   Resets the VCO logic in the PLL. The reset is Active High  Chips: BB_B0
31826 #define IPC_REG_TCAM_BIST_STATUS_K2                                                                  0x0202f8UL //Access:R    DataWidth:0x6   tcam bist status bus bit 0 - bist_pass bit 1 - bist_failed bit 2 - bist_paused bit 3 - reserved(bist_sho) bit 4 - reserved bit 5 - reserved  Chips: K2
31827 #define IPC_REG_PLL_STORM_E28_RESET_POST_BB_A0                                                       0x0202f8UL //Access:RW   DataWidth:0x1   Resets the Post Divider logic in the PLL. The reset is Active High  Chips: BB_A0
31828 #define IPC_REG_PLL_STORM_E28_RESET_POST_BB_B0                                                       0x0202f8UL //Access:RW   DataWidth:0x1   Resets the Post Divider logic in the PLL. The reset is Active High  Chips: BB_B0
31829 #define IPC_REG_TCAM_BIST_CONTROL_CCFC_CCAM_K2                                                       0x0202fcUL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31830 #define IPC_REG_PLL_STORM_E28_PDIV_BB_A0                                                             0x0202fcUL //Access:RW   DataWidth:0x4   Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.  Chips: BB_A0
31831 #define IPC_REG_PLL_STORM_E28_PDIV_BB_B0                                                             0x0202fcUL //Access:RW   DataWidth:0x4   Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.  Chips: BB_B0
31832 #define IPC_REG_TCAM_BIST_CONTROL_CCFC_SCAM_K2                                                       0x020300UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31833 #define IPC_REG_PLL_STORM_E28_NDIV_INT_BB_A0                                                         0x020300UL //Access:RW   DataWidth:0xa   Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset.  Chips: BB_A0
31834 #define IPC_REG_PLL_STORM_E28_NDIV_INT_BB_B0                                                         0x020300UL //Access:RW   DataWidth:0xa   Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset.  Chips: BB_B0
31835 #define IPC_REG_TCAM_BIST_CONTROL_TCFC_CCAM_K2                                                       0x020304UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31836 #define IPC_REG_PLL_STORM_E28_CH0_MDIV_BB_A0                                                         0x020304UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.  Chips: BB_A0
31837 #define IPC_REG_PLL_STORM_E28_CH0_MDIV_BB_B0                                                         0x020304UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.  Chips: BB_B0
31838 #define IPC_REG_TCAM_BIST_CONTROL_QM_K2                                                              0x020308UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31839 #define IPC_REG_PLL_STORM_E28_CH1_MDIV_BB_A0                                                         0x020308UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.  Chips: BB_A0
31840 #define IPC_REG_PLL_STORM_E28_CH1_MDIV_BB_B0                                                         0x020308UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.  Chips: BB_B0
31841 #define IPC_REG_TCAM_BIST_CONTROL_XSEM_K2                                                            0x02030cUL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31842 #define IPC_REG_PLL_STORM_E28_CH_ENABLEB_BB_A0                                                       0x02030cUL //Access:RW   DataWidth:0x6   Active Low Channel Enable. Global register. Reset on POR reset.  Chips: BB_A0
31843 #define IPC_REG_PLL_STORM_E28_CH_ENABLEB_BB_B0                                                       0x02030cUL //Access:RW   DataWidth:0x6   Active Low Channel Enable. Global register. Reset on POR reset.  Chips: BB_B0
31844 #define IPC_REG_TCAM_BIST_CONTROL_YSEM_K2                                                            0x020310UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31845 #define IPC_REG_PLL_STORM_E28_CTRL_0_BB_A0                                                           0x020310UL //Access:RW   DataWidth:0x20  PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_A0
31846 #define IPC_REG_PLL_STORM_E28_CTRL_0_BB_B0                                                           0x020310UL //Access:RW   DataWidth:0x20  PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_B0
31847 #define IPC_REG_TCAM_BIST_CONTROL_PSEM_K2                                                            0x020314UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31848 #define IPC_REG_PLL_STORM_E28_CTRL_1_BB_A0                                                           0x020314UL //Access:RW   DataWidth:0x20  PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_A0
31849 #define IPC_REG_PLL_STORM_E28_CTRL_1_BB_B0                                                           0x020314UL //Access:RW   DataWidth:0x20  PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_B0
31850 #define IPC_REG_TCAM_BIST_CONTROL_PSEM_VFC_K2                                                        0x020318UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31851 #define IPC_REG_PLL_STORM_E28_CTRL_2_BB_A0                                                           0x020318UL //Access:RW   DataWidth:0x2   PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_A0
31852 #define IPC_REG_PLL_STORM_E28_CTRL_2_BB_B0                                                           0x020318UL //Access:RW   DataWidth:0x2   PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_B0
31853 #define IPC_REG_TCAM_BIST_CONTROL_USEM_K2                                                            0x02031cUL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31854 #define IPC_REG_PLL_STORM_E28_KI_BB_A0                                                               0x02031cUL //Access:RW   DataWidth:0x3   Integrator gain control of the PLL digital filter. Global register. Reset on POR reset.  Chips: BB_A0
31855 #define IPC_REG_PLL_STORM_E28_KI_BB_B0                                                               0x02031cUL //Access:RW   DataWidth:0x3   Integrator gain control of the PLL digital filter. Global register. Reset on POR reset.  Chips: BB_B0
31856 #define IPC_REG_TCAM_BIST_CONTROL_TSEM_K2                                                            0x020320UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31857 #define IPC_REG_PLL_STORM_E28_KP_BB_A0                                                               0x020320UL //Access:RW   DataWidth:0x4   Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.  Chips: BB_A0
31858 #define IPC_REG_PLL_STORM_E28_KP_BB_B0                                                               0x020320UL //Access:RW   DataWidth:0x4   Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.  Chips: BB_B0
31859 #define IPC_REG_TCAM_BIST_CONTROL_TSEM_VFC_K2                                                        0x020324UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31860 #define IPC_REG_PLL_STORM_E28_KPP_BB_A0                                                              0x020324UL //Access:RW   DataWidth:0x4   Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset.  Chips: BB_A0
31861 #define IPC_REG_PLL_STORM_E28_KPP_BB_B0                                                              0x020324UL //Access:RW   DataWidth:0x4   Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset.  Chips: BB_B0
31862 #define IPC_REG_TCAM_BIST_CONTROL_MSEM_K2                                                            0x020328UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31863 #define IPC_REG_PLL_STORM_E28_LOCK_BB_A0                                                             0x020328UL //Access:R    DataWidth:0x1   LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.  Chips: BB_A0
31864 #define IPC_REG_PLL_STORM_E28_LOCK_BB_B0                                                             0x020328UL //Access:R    DataWidth:0x1   LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.  Chips: BB_B0
31865 #define IPC_REG_TCAM_BIST_CONTROL_PRS_GFT_K2                                                         0x02032cUL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31866 #define IPC_REG_PLL_STORM_E28_STATUS_BB_A0                                                           0x02032cUL //Access:R    DataWidth:0xc   Internal Status Bits of the PLL Global register. Reset on POR reset.  Chips: BB_A0
31867 #define IPC_REG_PLL_STORM_E28_STATUS_BB_B0                                                           0x02032cUL //Access:R    DataWidth:0xc   Internal Status Bits of the PLL Global register. Reset on POR reset.  Chips: BB_B0
31868 #define IPC_REG_TCAM_BIST_CONTROL_PRS_L_K2                                                           0x020330UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31869 #define IPC_REG_LCPLL_E28_PWRDN_BB_A0                                                                0x020330UL //Access:RW   DataWidth:0x1   PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR  Chips: BB_A0
31870 #define IPC_REG_LCPLL_E28_PWRDN_BB_B0                                                                0x020330UL //Access:RW   DataWidth:0x1   PLL Power on. 1 = PLL is powered down. 0 = PLL is powered on. The bit is Active High. Global Register, Reset on POR  Chips: BB_B0
31871 #define IPC_REG_TCAM_BIST_CONTROL_PRS_H_K2                                                           0x020334UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31872 #define IPC_REG_LCPLL_E28_RESET_VCO_BB_A0                                                            0x020334UL //Access:RW   DataWidth:0x1   Resets the VCO logic in the PLL. The reset is Active High  Chips: BB_A0
31873 #define IPC_REG_LCPLL_E28_RESET_VCO_BB_B0                                                            0x020334UL //Access:RW   DataWidth:0x1   Resets the VCO logic in the PLL. The reset is Active High  Chips: BB_B0
31874 #define IPC_REG_TCAM_BIST_CONTROL_IGU_K2                                                             0x020338UL //Access:RW   DataWidth:0x6   tcam bist control bus bit 0 - bist_run bit 1 - retention_en bit 2 - bist_resume bit 3 - reserved(connected the bist_shi,should be zero) bit 4 - reserved(connected the bist_she, should be zero) bit 5 - reserved  Chips: K2
31875 #define IPC_REG_LCPLL_E28_RESET_POST_BB_A0                                                           0x020338UL //Access:RW   DataWidth:0x1   Resets the Post Divider logic in the PLL. The reset is Active High  Chips: BB_A0
31876 #define IPC_REG_LCPLL_E28_RESET_POST_BB_B0                                                           0x020338UL //Access:RW   DataWidth:0x1   Resets the Post Divider logic in the PLL. The reset is Active High  Chips: BB_B0
31877 #define IPC_REG_CLK_DFT_MS_125M_DIV_K2                                                               0x02033cUL //Access:RW   DataWidth:0x8   divider value for clk_dft_ms_125, the division is 2*value. this value is output at ipc_clkdec_clk_dft_ms_125m_div 0 - no division 1- divide by 2 2- divide by 4  Chips: K2
31878 #define IPC_REG_LCPLL_E28_PDIV_BB_A0                                                                 0x02033cUL //Access:RW   DataWidth:0x4   Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.  Chips: BB_A0
31879 #define IPC_REG_LCPLL_E28_PDIV_BB_B0                                                                 0x02033cUL //Access:RW   DataWidth:0x4   Input reference clock pre-divider control 0000= illegal state 0001= divide-by-1 0010= divide-by-2 0011= divide-by-3 0100= divide-by-4 0101= divide-by-5 0110= divide-by-6 0111= divide-by-7 1111 = divide-by-15 Global register. Reset on POR reset.  Chips: BB_B0
31880 #define IPC_REG_CLK_DFT_MS_150M_DIV_K2                                                               0x020340UL //Access:RW   DataWidth:0x8     Chips: K2
31881 #define IPC_REG_LCPLL_E28_NDIV_INT_BB_A0                                                             0x020340UL //Access:RW   DataWidth:0xa   Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset.  Chips: BB_A0
31882 #define IPC_REG_LCPLL_E28_NDIV_INT_BB_B0                                                             0x020340UL //Access:RW   DataWidth:0xa   Feedback divider control 0000000000 = not usable 0000000001 = not usable ... 0000001111 = not usable 0000010000 = 16 ... 1111111111 = 1023 Global register. Reset on POR reset.  Chips: BB_B0
31883 #define IPC_REG_CLK_DFT_MS_60M_DIV_K2                                                                0x020344UL //Access:RW   DataWidth:0x8     Chips: K2
31884 #define IPC_REG_LCPLL_E28_CH0_MDIV_BB_A0                                                             0x020344UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.  Chips: BB_A0
31885 #define IPC_REG_LCPLL_E28_CH0_MDIV_BB_B0                                                             0x020344UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-0 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.  Chips: BB_B0
31886 #define IPC_REG_CLK_DFT_MS_70M_DIV_K2                                                                0x020348UL //Access:RW   DataWidth:0x8     Chips: K2
31887 #define IPC_REG_LCPLL_E28_CH1_MDIV_BB_A0                                                             0x020348UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.  Chips: BB_A0
31888 #define IPC_REG_LCPLL_E28_CH1_MDIV_BB_B0                                                             0x020348UL //Access:RW   DataWidth:0x8   Post-divider ratio for channel-1 00000000 = divide by 256 00000001 = divide by 1 00000010 = divide by 2 ... 11111111 = divide by 255 Global register. Reset on POR reset.  Chips: BB_B0
31889 #define IPC_REG_CLK_DFT_MS_412M_DIV_K2                                                               0x02034cUL //Access:RW   DataWidth:0x8     Chips: K2
31890 #define IPC_REG_LCPLL_E28_CH_ENABLEB_BB_A0                                                           0x02034cUL //Access:RW   DataWidth:0x6   Active Low Channel Enable. Global register. Reset on POR reset.  Chips: BB_A0
31891 #define IPC_REG_LCPLL_E28_CH_ENABLEB_BB_B0                                                           0x02034cUL //Access:RW   DataWidth:0x6   Active Low Channel Enable. Global register. Reset on POR reset.  Chips: BB_B0
31892 #define IPC_REG_CLK_DFT_NWS_644M_DIV_K2                                                              0x020350UL //Access:RW   DataWidth:0x8     Chips: K2
31893 #define IPC_REG_LCPLL_E28_CTRL_0_BB_A0                                                               0x020350UL //Access:RW   DataWidth:0x20  PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_A0
31894 #define IPC_REG_LCPLL_E28_CTRL_0_BB_B0                                                               0x020350UL //Access:RW   DataWidth:0x20  PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_B0
31895 #define IPC_REG_CLK_DFT_NWS_300M_DIV_K2                                                              0x020354UL //Access:RW   DataWidth:0x8     Chips: K2
31896 #define IPC_REG_LCPLL_E28_CTRL_1_BB_A0                                                               0x020354UL //Access:RW   DataWidth:0x20  PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_A0
31897 #define IPC_REG_LCPLL_E28_CTRL_1_BB_B0                                                               0x020354UL //Access:RW   DataWidth:0x20  PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_B0
31898 #define IPC_REG_CLK_DFT_NWS_100M_DIV_K2                                                              0x020358UL //Access:RW   DataWidth:0x8     Chips: K2
31899 #define IPC_REG_LCPLL_E28_CTRL_2_BB_A0                                                               0x020358UL //Access:RW   DataWidth:0x2   PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_A0
31900 #define IPC_REG_LCPLL_E28_CTRL_2_BB_B0                                                               0x020358UL //Access:RW   DataWidth:0x2   PLL Control Register [65:56] reserved Reserved digital control input. [55:54] post_rst_sel Reset mode of the post-divider. i_post_resetb will be ANDed with the internal post-divider reset control, which can be set to the following values: 00 = lock, PLL phase locking indicator; 01 = flock, PLL frequency locking indicator; 10 = resetb, PLL digital control reset; 11 = 1 [53:50] bin_sel TDC offset Control, for test and debug only. [49] bang_bang TDC mode control 0 = linear mode (normal operation) 1 = bang-bang mode [48:47] pwm_rate Control of internal PWM frequency. 00 = fpwm is set to fdco/5; 01 = fpwm is set to fdco/4; 10 = fpwm is set to fdco/3; 11 = fpwm is set to fdco/2. [46:41] ldo_ctrl Output level control of PLL internal LDOs. Bit[1:0] controls the analog LDO level, bit[3:2] controls the digital LDO level, and bit[5:4] controls the T2D LDO level. Each word segment has the following effect on the corresponding LDO level: 00 = 1.0V 01 = 1.05V 10 = 0.90V 11 = 0.95V [40] testbuf_pwron Power on control of 50Ohm test buffer 0 = test buffer powered off 1 = test buffer powered on [39:37] mux_test_sel Selection of the test output clock for pad_testp and pad_testn. 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = reference or feedback clock from T2D block 011 = output of post-divider channel 5 100 = lc oscillator clock, at the frequency flc = 2*fdco 101 = input clock of post-divider, at the frequency fdco 110 = o_fref 111 = unused [36] cmlbuf1_pwron Power on control of the CML buffer 1 which drives o_ch0_cml2p and o_ch0_cml2n. 0 = power off 1 = power on [35] cmlbuf0_pwron Power on control of the CML buffer 0 which drives o_ch0_cmlp and o_ch0_cmln. 0 = power off 1 = power on [34:32] mux_out_sel Selection of the output clock for o_ch0_cmlp and o_ch0_cmln, and o_ch0_cml2p and o_ch0_cml2n 000 = output of post-divider channel 0 001 = pad_frefp and pad_frefn 010 = input clock of post-divider at the frequency of fdco 011 = unused 100 = lc oscillator clock at the frequency of flc = 2*fdco 101 = o_fref 110 = reference or feedback clock in T2D 111 = unused [31:30] reserved [29] en_vco_clk Enabling of the output of LC oscillator clock. 0 = LC oscillator clock output disabled 1 = LC oscillator clock output enabled [28] div4_div2b Pre-divider control of the DCO clock. 0 = Fdco is one half of the LC oscillator frequency 1 = Fdco is one quater of the LC oscillator frequency [27] lc_boost Boost control of the bias current of the LC oscillator. 0 = normal operation 1 = bias current boosted [26] t2dclk_sel Selection of the clock to be output from T2D block 0 = clock from reference pre-divider 1 = clock from the feedback divider [25] t2dclk_en Enabling of the output of the effective clock from TDC, which could be either feedback clock or effective reference clock at the frequency of fref/pdiv. 0 = disable the output of T2D clock 1 = enable the output of T2D clock [24] stat_update Toggle this bit to update the internal status read-out. [23:22] stat_mode Mode selection of digital controller's internal status. 00 = unused 01 = Measurement of min and max phase error 10 = unused 11 = measurement of min and max dco control [21:19] stat_select Selection of the digital controller's internal status for read-out. 000 = unused 001 = minimum value based on stat_mode selection 010 = maximum value based on stat_mode selection 011 = Misc. PLL lock status 100 = DCO control code 101 = unused 110 = unused 111 = unused [18] stat_reset Reset control of the digital controller's internal status read-out. 0 = internal status read-out enabled 1 = internal status read-out disabled [17] bypass_fine Select the DAC to be loaded in open-loop mode. 0 = dco_bypass value loaded into coarse DAC, 4 LSBs discarded 1 = dco_bypass value loaded into fine DAC, 1 MSB discarded [16] bypass_en Enabling of DCO bypass mode, or PLL open-loop mode. 0 = normal operation 1 = bypass enabled [15:0] dco_bypass DCO bypass control value in open-loop mode of PLL. 0x0000 = minimum Fdco within the range ... 0xffff = maximum Fdco within the range Global register. Reset on POR reset.  Chips: BB_B0
31901 #define IPC_REG_CLK_DFT_PCIES_500M_DIV_K2                                                            0x02035cUL //Access:RW   DataWidth:0x8     Chips: K2
31902 #define IPC_REG_LCPLL_E28_KI_BB_A0                                                                   0x02035cUL //Access:RW   DataWidth:0x3   Integrator gain control of the PLL digital filter. Global register. Reset on POR reset.  Chips: BB_A0
31903 #define IPC_REG_LCPLL_E28_KI_BB_B0                                                                   0x02035cUL //Access:RW   DataWidth:0x3   Integrator gain control of the PLL digital filter. Global register. Reset on POR reset.  Chips: BB_B0
31904 #define IPC_REG_CLK_DFT_PCIES_100M_DIV_K2                                                            0x020360UL //Access:RW   DataWidth:0x8     Chips: K2
31905 #define IPC_REG_LCPLL_E28_KP_BB_A0                                                                   0x020360UL //Access:RW   DataWidth:0x4   Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.  Chips: BB_A0
31906 #define IPC_REG_LCPLL_E28_KP_BB_B0                                                                   0x020360UL //Access:RW   DataWidth:0x4   Gain of P/I loop filter proportional path during fine phase acquisition mode. Global register. Reset on POR reset.  Chips: BB_B0
31907 #define IPC_REG_CLK_DFT_PCIES_50M_DIV_K2                                                             0x020364UL //Access:RW   DataWidth:0x8     Chips: K2
31908 #define IPC_REG_LCPLL_E28_KPP_BB_A0                                                                  0x020364UL //Access:RW   DataWidth:0x4   Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset.  Chips: BB_A0
31909 #define IPC_REG_LCPLL_E28_KPP_BB_B0                                                                  0x020364UL //Access:RW   DataWidth:0x4   Control of the non-zero pole in the PLL digital filter. Global register. Reset on POR reset.  Chips: BB_B0
31910 #define IPC_REG_STRENGTH_IO_CONTROL_K2                                                               0x020368UL //Access:RW   DataWidth:0x6   Sets the CTL# (# in [0..5]) I/Os of the PADS in non - scan/mbist modes  Chips: K2
31911 #define IPC_REG_LCPLL_E28_LOCK_BB_A0                                                                 0x020368UL //Access:R    DataWidth:0x1   LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.  Chips: BB_A0
31912 #define IPC_REG_LCPLL_E28_LOCK_BB_B0                                                                 0x020368UL //Access:R    DataWidth:0x1   LOCK detector output 0= PLL unlocked 1= PLL locked Global register. Reset on POR reset.  Chips: BB_B0
31913 #define IPC_REG_SLEW_IO_CONTROL_K2                                                                   0x02036cUL //Access:RW   DataWidth:0x2   Sets the SL# (# in [0..1]) I/Os of the PADS in non - scan/mbist modes  Chips: K2
31914 #define IPC_REG_LCPLL_E28_STATUS_BB_A0                                                               0x02036cUL //Access:R    DataWidth:0xc   Internal Status Bits of the PLL Global register. Reset on POR reset.  Chips: BB_A0
31915 #define IPC_REG_LCPLL_E28_STATUS_BB_B0                                                               0x02036cUL //Access:R    DataWidth:0xc   Internal Status Bits of the PLL Global register. Reset on POR reset.  Chips: BB_B0
31916 #define IPC_REG_ECO_RESERVED_K2                                                                      0x020370UL //Access:RW   DataWidth:0x20  This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: K2
31917 #define IPC_REG_PMFC_DVT_EN_BB_A0                                                                    0x020370UL //Access:RW   DataWidth:0x1   Enable the MAC SERDES  Chips: BB_A0
31918 #define IPC_REG_PMFC_DVT_EN_BB_B0                                                                    0x020370UL //Access:RW   DataWidth:0x1   Enable the MAC SERDES  Chips: BB_B0
31919 #define IPC_REG_PMFC_DVT_IDDQ                                                                        0x020374UL //Access:RW   DataWidth:0x1   MAC SERDES IDDQ  Chips: BB_A0 BB_B0
31920 #define IPC_REG_PMFC_DVT_PWRDWN                                                                      0x020378UL //Access:RW   DataWidth:0x1   MAC SERDES Power Down  Chips: BB_A0 BB_B0
31921 #define IPC_REG_PMFC_DVT_REFIN_EN                                                                    0x02037cUL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31922 #define IPC_REG_PMFC_DVT_REFOUT_EN                                                                   0x020380UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31923 #define IPC_REG_PMFC_DVT_TSC_RESET                                                                   0x020384UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31924 #define IPC_REG_PMFC_DVT_MDIO_FAST_MODE                                                              0x020388UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31925 #define IPC_REG_PMFC_PHY_ADDR                                                                        0x02038cUL //Access:RW   DataWidth:0x5   MDIO PHY Address. The SERDES uses this address to determine whether or not it is the recipient of the message on the MDIO interface.  Chips: BB_A0 BB_B0
31926 #define IPC_REG_PMFC_TX_DRV_HV_DISABLE                                                               0x020390UL //Access:RW   DataWidth:0x1   1 : Disable high voltage for Tx Driver  Chips: BB_A0 BB_B0
31927 #define IPC_REG_PMFC_BOND_OPTION                                                                     0x020394UL //Access:RW   DataWidth:0x9   Bonding option for PM Falcon  Chips: BB_A0 BB_B0
31928 #define IPC_REG_PMFC_PLL_LOCK                                                                        0x020398UL //Access:R    DataWidth:0x1   MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.  Chips: BB_A0 BB_B0
31929 #define IPC_REG_PMFC_RECOVER_CLOCK_LOCK                                                              0x02039cUL //Access:R    DataWidth:0x4   MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.  Chips: BB_A0 BB_B0
31930 #define IPC_REG_PMEG_DVT_EN                                                                          0x0203a0UL //Access:RW   DataWidth:0x1   Enable the MAC SERDES  Chips: BB_A0 BB_B0
31931 #define IPC_REG_PMEG_DVT_IDDQ                                                                        0x0203a4UL //Access:RW   DataWidth:0x1   MAC SERDES IDDQ  Chips: BB_A0 BB_B0
31932 #define IPC_REG_PMEG_DVT_PWRDWN                                                                      0x0203a8UL //Access:RW   DataWidth:0x1   MAC SERDES Power Down  Chips: BB_A0 BB_B0
31933 #define IPC_REG_PMEG_DVT_REFIN_EN                                                                    0x0203acUL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31934 #define IPC_REG_PMEG_DVT_REFOUT_EN                                                                   0x0203b0UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31935 #define IPC_REG_PMEG_DVT_TSC_RESET                                                                   0x0203b4UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31936 #define IPC_REG_PMEG_DVT_MDIO_FAST_MODE                                                              0x0203b8UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31937 #define IPC_REG_PMEG_PHY_ADDR                                                                        0x0203bcUL //Access:RW   DataWidth:0x5   MDIO PHY Address. The SERDES uses this address to determine whether or not it is the recipient of the message on the MDIO interface.  Chips: BB_A0 BB_B0
31938 #define IPC_REG_PMEG_BOND_OPTION                                                                     0x0203c0UL //Access:RW   DataWidth:0xd   Bonding option for PM Eagle  Chips: BB_A0 BB_B0
31939 #define IPC_REG_PMEG_PLL_LOCK                                                                        0x0203c4UL //Access:R    DataWidth:0x1   MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.  Chips: BB_A0 BB_B0
31940 #define IPC_REG_PMEG_RECOVER_CLOCK_LOCK                                                              0x0203c8UL //Access:R    DataWidth:0x4   MAC SERDES PLL lock. 0-unlocked; 1-locked. Global register.  Chips: BB_A0 BB_B0
31941 #define IPC_REG_PCIE_PIPE_PLL_LOCK                                                                   0x0203ccUL //Access:R    DataWidth:0x8   PCIe lock signals. 0-unlocked; 1-locked. Global register.  Chips: BB_A0 BB_B0
31942 #define IPC_REG_PCIES_PIPE_IDDQ                                                                      0x0203d0UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31943 #define IPC_REG_PCIES_RESETMDIO_N                                                                    0x0203d4UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31944 #define IPC_REG_PCIES_ALT_CLK_SELECT                                                                 0x0203d8UL //Access:RW   DataWidth:0x1     Chips: BB_A0 BB_B0
31945 #define IPC_REG_SGMII_RESETS                                                                         0x0203dcUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0
31946     #define IPC_REG_SGMII_RESETS_SGMII_RST_HW                                                        (0x1<<0) // 1 : Reset the entire SGMII Core. Global Register, Reset on POR
31947     #define IPC_REG_SGMII_RESETS_SGMII_RST_HW_SHIFT                                                  0
31948     #define IPC_REG_SGMII_RESETS_SGMII_RST_MDIO                                                      (0x1<<1) // 1 : Reset the MDIO Registers. Global Register, Reset on POR
31949     #define IPC_REG_SGMII_RESETS_SGMII_RST_MDIO_SHIFT                                                1
31950     #define IPC_REG_SGMII_RESETS_SGMII_RST_PLL                                                       (0x1<<2) // 1 : Resets the PLL and digital logic.. Global Register, Reset on POR
31951     #define IPC_REG_SGMII_RESETS_SGMII_RST_PLL_SHIFT                                                 2
31952 #define IPC_REG_SGMII_MD_DEVAD                                                                       0x0203e0UL //Access:RW   DataWidth:0x5   Device Address Global Register, Reset on POR  Chips: BB_A0 BB_B0
31953 #define IPC_REG_SGMII_MD_ST                                                                          0x0203e4UL //Access:RW   DataWidth:0x1   0 : CL22 1 : CL45 Global Register, Reset on POR  Chips: BB_A0 BB_B0
31954 #define IPC_REG_SGMII_PHY_ADDR                                                                       0x0203e8UL //Access:RW   DataWidth:0x5   PHY Address for MDIO Transaction Global Register, Reset on POR  Chips: BB_A0 BB_B0
31955 #define IPC_REG_SGMII_PWRDWN                                                                         0x0203ecUL //Access:RW   DataWidth:0x1   1 : powers down for the analog front end and turns off all clocks except refclk. MDIO is operational Global Register, Reset on POR  Chips: BB_A0 BB_B0
31956 #define IPC_REG_SGMII_IDDQ                                                                           0x0203f0UL //Access:RW   DataWidth:0x1   1 : iddq enable, powers down analog and turns off all clocks. MDIO is not operational Global Register, Reset on POR  Chips: BB_A0 BB_B0
31957 #define IPC_REG_SGMII_REFSEL                                                                         0x0203f4UL //Access:RW   DataWidth:0x3   TBD. Global Register, Reset on POR  Chips: BB_A0 BB_B0
31958 #define IPC_REG_SGMII_STATUS                                                                         0x0203f8UL //Access:R    DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0
31959     #define IPC_REG_SGMII_STATUS_SGMII_LINK_STATUS                                                   (0x1<<0) // Link Status 1: Link has been achieve Global Register, Reset on POR
31960     #define IPC_REG_SGMII_STATUS_SGMII_LINK_STATUS_SHIFT                                             0
31961     #define IPC_REG_SGMII_STATUS_SGMII_RX_SIGDET                                                     (0x1<<1) // Signal Detect Global Register, Reset on POR
31962     #define IPC_REG_SGMII_STATUS_SGMII_RX_SIGDET_SHIFT                                               1
31963     #define IPC_REG_SGMII_STATUS_SGMII_RX_SEQDONE1G                                                  (0x1<<2) // 1: Bit Alignment Done Global Register, Reset on POR
31964     #define IPC_REG_SGMII_STATUS_SGMII_RX_SEQDONE1G_SHIFT                                            2
31965     #define IPC_REG_SGMII_STATUS_SGMII_SYNC_STATUS                                                   (0x1<<3) // 1: Symbol Alignment Global Register, Reset on POR
31966     #define IPC_REG_SGMII_STATUS_SGMII_SYNC_STATUS_SHIFT                                             3
31967     #define IPC_REG_SGMII_STATUS_SGMII_SPEED_10                                                      (0x1<<4) // 1: Speed is 10M Global Register, Reset on POR
31968     #define IPC_REG_SGMII_STATUS_SGMII_SPEED_10_SHIFT                                                4
31969     #define IPC_REG_SGMII_STATUS_SGMII_SPEED_100                                                     (0x1<<5) // 1: Speed is 100M Global Register, Reset on POR
31970     #define IPC_REG_SGMII_STATUS_SGMII_SPEED_100_SHIFT                                               5
31971     #define IPC_REG_SGMII_STATUS_SGMII_SPEED_1000                                                    (0x1<<6) // 1: Speed is 1G Global Register, Reset on POR
31972     #define IPC_REG_SGMII_STATUS_SGMII_SPEED_1000_SHIFT                                              6
31973     #define IPC_REG_SGMII_STATUS_SGMII_TXPLL_LOCK                                                    (0x1<<8) // 1: PLL is locked Global Register, Reset on POR
31974     #define IPC_REG_SGMII_STATUS_SGMII_TXPLL_LOCK_SHIFT                                              8
31975     #define IPC_REG_SGMII_STATUS_SGMII_MODE                                                          (0x1<<12) // 1: Running in SGMII mode. Global Register, Reset on POR
31976     #define IPC_REG_SGMII_STATUS_SGMII_MODE_SHIFT                                                    12
31977 #define IPC_REG_PM_TMON_CTRL                                                                         0x0203fcUL //Access:RW   DataWidth:0x3   Control the Bandgap voltage of the monitor  Chips: BB_A0 BB_B0
31978 #define IPC_REG_PM_TMON_ENA                                                                          0x020400UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0
31979     #define IPC_REG_PM_TMON_ENA_PM_TMON_RESET                                                        (0x1<<0) // 1 : Reset the VTMON registers.
31980     #define IPC_REG_PM_TMON_ENA_PM_TMON_RESET_SHIFT                                                  0
31981     #define IPC_REG_PM_TMON_ENA_PM_TMON_PWRDN                                                        (0x1<<1) // 1 : Hold the VTMON in powerdown state.
31982     #define IPC_REG_PM_TMON_ENA_PM_TMON_PWRDN_SHIFT                                                  1
31983 #define IPC_REG_PM_TMON_HOLD                                                                         0x020404UL //Access:RW   DataWidth:0x1   Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. Reset on POR reset.  Chips: BB_A0 BB_B0
31984 #define IPC_REG_PM_TMON_DATA                                                                         0x020408UL //Access:R    DataWidth:0xa   Voltage/Temperature Monitor output.Global register. Reset on POR reset.  Chips: BB_A0 BB_B0
31985 #define IPC_REG_PCIE_TMON_CTRL                                                                       0x02040cUL //Access:RW   DataWidth:0x3   Control the Bandgap voltage of the monitor  Chips: BB_A0 BB_B0
31986 #define IPC_REG_PCIE_TMON_ENA                                                                        0x020410UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0
31987     #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_RESET                                                    (0x1<<0) // 1 : Reset the VTMON registers.
31988     #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_RESET_SHIFT                                              0
31989     #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_PWRDN                                                    (0x1<<1) // 1 : Hold the VTMON in powerdown state.
31990     #define IPC_REG_PCIE_TMON_ENA_PCIE_TMON_PWRDN_SHIFT                                              1
31991 #define IPC_REG_PCIE_TMON_HOLD                                                                       0x020414UL //Access:RW   DataWidth:0x1   Voltage/Temperature Monitor hold. 0 - update; 1 - hold on to the value forever. Global register. Reset on POR reset.  Chips: BB_A0 BB_B0
31992 #define IPC_REG_PCIE_TMON_DATA                                                                       0x020418UL //Access:R    DataWidth:0xa   Voltage/Temperature Monitor output.Global register. Reset on POR reset.  Chips: BB_A0 BB_B0
31993 #define IPC_REG_RESCAL_E28_PWRDN                                                                     0x02041cUL //Access:RW   DataWidth:0x1   Powerdown the Rescal 0: Normal Operation Mode 1: Powerdown the RESCAL block Transition from 1->0 to start calibration Global Register, Reset on POR  Chips: BB_A0 BB_B0
31994 #define IPC_REG_RESCAL_E28_RST                                                                       0x020420UL //Access:RW   DataWidth:0x1   Reset the RESCAL block 0: Normal Operation Mode 1: Reset the RESCAL block Global Register, Reset on POR  Chips: BB_A0 BB_B0
31995 #define IPC_REG_RESCAL_E28_OVERRIDE                                                                  0x020424UL //Access:RW   DataWidth:0x1   By Setting this bit, FW takes control of the RESCAL block manitpulates the pwrdn and reset signals to start its own calibration. 0: Normal Operation Mode 1: FW override Global Register, Reset on POR  Chips: BB_A0 BB_B0
31996 #define IPC_REG_RESCAL_E28_RESTART_CALIBRATION                                                       0x020428UL //Access:RW   DataWidth:0x1   Setting this bit starts the HW based calibration engine to recalibrate the rescal block. 0: Normal Operation Mode 1: Restart the calibration Global Register, Reset on POR  Chips: BB_A0 BB_B0
31997 #define IPC_REG_RESCAL_E28_DIAG_ON                                                                   0x02042cUL //Access:RW   DataWidth:0x1   0: Normal Operation Mode 1: Freeze Internal Digital ciruit Global Register, Reset on POR  Chips: BB_A0 BB_B0
31998 #define IPC_REG_RESCAL_E28_CTRL                                                                      0x020430UL //Access:RW   DataWidth:0xd   [12:11] inversion of compcrradj[1:0] to analog [10] inversion of vrefs to analog [9] wait time after increasing pon 1'b0: 8 refclk 1'b1: 16 refclk [8:7] power-up time before starting calibration 2'b00: 32 refclk = 1.28us 2'b01: 128 refclk = 5.12us 2'b10: 256 refclk = 10.24us 2'b11: 8 refclk = 320ns [6:5] resistor comparison accumulation time 2'b00: 16 refclk 2'b01: 32 refclk 2'b10: 8 refclk [4:1] override resistor pon value when [0] is asserted 0000: min resistance -24%~-21% 1111: max resistance +21%~+24% [0] 1: override pon value to analog 0: normal mode Global Register, Reset on POR  Chips: BB_A0 BB_B0
31999 #define IPC_REG_RESCAL_E28_STATUS                                                                    0x020434UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0
32000     #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_CALIB_DONE                                          (0x1<<0) // Indicates if the calibraion operation is done. 0: Calibration in progress 1: Calibration Done Global Register, Reset on POR
32001     #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_CALIB_DONE_SHIFT                                    0
32002     #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_VALID                                               (0x1<<1) // Indicates if the pon data is valid when calib_done is set 0: Data is invalid 1: Data is valid Global Register, Reset on POR
32003     #define IPC_REG_RESCAL_E28_STATUS_RESCAL_E28_VALID_SHIFT                                         1
32004 #define IPC_REG_RESCAL_E28_PON                                                                       0x020438UL //Access:R    DataWidth:0x4   pon value; stable after rescal is done or o_done is asserted Output On-chip Sheet Resistance 0000 -24% ~ -21% 0001 -21% ~ -18% 0010 -18% ~ -15% 0011 -15% ~ -12% 0100 -12% ~ -9% 0101 -9% ~ -6% 0110 -6% ~ -3% 0111    -3% ~ +0% 1000    +0% ~ +3% 1001 +3% ~ +6% 1010 +6% ~ +9% 1011 +9% ~ +12% 1100 +12% ~ +15% 1101 +15% ~ +18% 1110 +18% ~ +21% 1111 +21% ~ +24% Global Register, Reset on POR  Chips: BB_A0 BB_B0
32005 #define IPC_REG_RESCAL_E28_CURR_COMP_CNT                                                             0x02043cUL //Access:R    DataWidth:0x6   accumulated comparison for current pon value Global Register, Reset on POR  Chips: BB_A0 BB_B0
32006 #define IPC_REG_RESCAL_E28_PREV_COMP_CNT                                                             0x020440UL //Access:R    DataWidth:0x4   accumulated comparison for previous pon value Global Register, Reset on POR  Chips: BB_A0 BB_B0
32007 #define IPC_REG_RESCAL_E28_COMP                                                                      0x020444UL //Access:R    DataWidth:0x1   RESCAL Comp Value Global Register, Reset on POR  Chips: BB_A0 BB_B0
32008 #define IPC_REG_RESCAL_E28_CTRL_DFS                                                                  0x020448UL //Access:R    DataWidth:0xd   default values for the rescal control signals. Global Register, Reset on POR  Chips: BB_A0 BB_B0
32009 #define IPC_REG_RESCAL_E28_STATE                                                                     0x02044cUL //Access:R    DataWidth:0x3   Internal State machine status 0: INIT 1: WAIT_PWRUP 2: COMP_ACC 3: WAIT_PON_INC 4: CAL_DONE Global Register, Reset on POR  Chips: BB_A0 BB_B0
32010 #define IPC_REG_RESCAL_E28_FSM_STATE                                                                 0x020450UL //Access:R    DataWidth:0x3   External State machine status 0: POR 1: INIT 2: RESET 3: PWRDN 4: CALIB 5: PONVALID 6: RESULT 7: IDLE Global Register, Reset on POR  Chips: BB_A0 BB_B0
32011 #define IPC_REG_SWREG_VMGMT_E28_PWRDN                                                                0x020454UL //Access:RW   DataWidth:0x1   Powerdown the VManagement Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR  Chips: BB_A0 BB_B0
32012 #define IPC_REG_SWREG_VMGMT_E28_REG_RESET                                                            0x020458UL //Access:RW   DataWidth:0x1   Reset the Registers in VManagement Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR  Chips: BB_A0 BB_B0
32013 #define IPC_REG_SWREG_VMGMT_E28_STABLE                                                               0x02045cUL //Access:R    DataWidth:0x1   1: PMU is stable Global Register, Reset on POR  Chips: BB_A0 BB_B0
32014 #define IPC_REG_SWREG_VMAIN_E28_PWRDN                                                                0x020460UL //Access:RW   DataWidth:0x1   Powerdown the VMain Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR  Chips: BB_A0 BB_B0
32015 #define IPC_REG_SWREG_VMAIN_E28_REG_RESET                                                            0x020464UL //Access:RW   DataWidth:0x1   Reset the Registers in VMain Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR  Chips: BB_A0 BB_B0
32016 #define IPC_REG_SWREG_VMAIN_E28_STABLE                                                               0x020468UL //Access:R    DataWidth:0x1   1: PMU is stable Global Register, Reset on POR  Chips: BB_A0 BB_B0
32017 #define IPC_REG_SWREG_VANALOG_E28_PWRDN                                                              0x02046cUL //Access:RW   DataWidth:0x1   Powerdown the VAnalog Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR  Chips: BB_A0 BB_B0
32018 #define IPC_REG_SWREG_VANALOG_E28_REG_RESET                                                          0x020470UL //Access:RW   DataWidth:0x1   Reset the Registers in VAnalog Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR  Chips: BB_A0 BB_B0
32019 #define IPC_REG_SWREG_VANALOG_E28_STABLE                                                             0x020474UL //Access:R    DataWidth:0x1   1: PMU is stable Global Register, Reset on POR  Chips: BB_A0 BB_B0
32020 #define IPC_REG_SWREG_V1P8_E28_PWRDN                                                                 0x020478UL //Access:RW   DataWidth:0x1   Powerdown the V1p8 Switching Regulator 0: Normal Operation Mode 1: Powerdown the SWREG block Global Register, Reset on POR  Chips: BB_A0 BB_B0
32021 #define IPC_REG_SWREG_V1P8_E28_REG_RESET                                                             0x02047cUL //Access:RW   DataWidth:0x1   Reset the Registers in V1p8 Switching Regulator 0: Normal Operation Mode 1: Reset the switchin regulator block Global Register, Reset on POR  Chips: BB_A0 BB_B0
32022 #define IPC_REG_SWREG_V1P8_E28_STABLE                                                                0x020480UL //Access:R    DataWidth:0x1   1: PMU is stable Global Register, Reset on POR  Chips: BB_A0 BB_B0
32023 #define IPC_REG_SWREG_SYNC_CLK_SELECT                                                                0x020484UL //Access:RW   DataWidth:0x1   All three SWREG with external FETs are sync'ed such that they are running on different phases of alternate clock. This lowers the overall power consumption. 1: Select 1Mhz Clock 0: Select 500Khz Clock Global Register, Reset on POR  Chips: BB_A0 BB_B0
32024 #define IPC_REG_SWREG_SYNC_CLK_EN                                                                    0x020488UL //Access:RW   DataWidth:0x1   Setting this bit to "1" will enable the phase shift logic betweent the three swreg to start working. Global Register, Reset on POR  Chips: BB_A0 BB_B0
32025 #define IPC_REG_NW_SERDES_MDIO_COMM                                                                  0x020498UL //Access:RW   DataWidth:0x1e  [29] -> START_BUSY This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. [28] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction. [27:26] -> COMMAND 1 -> Write 2 -> Read [25:21] -> PHY_ADDR This value is used to define the PHY address portion of the MDIO transaction 1 -> SWREG VMGMT 2 -> SWREG VMAIN 3 -> SWREG VANALOG 4 -> SWREG V1p8 [20:16] -> REG_ADDR This value is used to define the register address portion of the MDIO transaction [15:0]  -> DATA When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed.  Chips: BB_A0 BB_B0
32026 #define IPC_REG_NW_SERDES_MDIO_STATUS                                                                0x02049cUL //Access:R    DataWidth:0x2   [0] -> DONE This bit is set each time the MDIO transaction has completed. This bit is cleared when the next transaction starts. [1] -> FAIL This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.  Chips: BB_A0 BB_B0
32027 #define IPC_REG_NW_SERDES_MDIO_MODE                                                                  0x0204a0UL //Access:RW   DataWidth:0x16  [21:12] -> CLOCK_CNT This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register. [11] -> MDC Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set. [10] -> MDIO_OE Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input. [9] -> MDIO The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin. [8] -> BIT_BANG If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed. [0] -> FREE_DIS 1 -> Diable Free running MDIO clock All other field in the register are reserved  Chips: BB_A0 BB_B0
32028 #define IPC_REG_FREQ_NW                                                                              0x0204b0UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0
32029     #define IPC_REG_FREQ_NW_CNT                                                                      (0xffff<<0) // This field shows the frequency counter for main clock over a 10uS interval. NW Clock Frequency = ~(FreqCnt / 10)MHz. This field is not reset between measurements. For example, it shows X MHz in first measurement, 2*X in second measurement, 3*X MHz in third measurement.
32030     #define IPC_REG_FREQ_NW_CNT_SHIFT                                                                0
32031     #define IPC_REG_FREQ_NW_CNT_VALID                                                                (0x1<<16) // 0: Value in freq_cnt field is not valid 1: Value in freq_cnt field is valid
32032     #define IPC_REG_FREQ_NW_CNT_VALID_SHIFT                                                          16
32033 #define IPC_REG_OTP_CONFIG_0                                                                         0x0204e8UL //Access:R    DataWidth:0x20  These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.  Chips: BB_A0 BB_B0
32034 #define IPC_REG_OTP_CONFIG_1                                                                         0x0204ecUL //Access:R    DataWidth:0x20  These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.  Chips: BB_A0 BB_B0
32035 #define IPC_REG_OTP_CONFIG_2                                                                         0x0204f0UL //Access:R    DataWidth:0x20  These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.  Chips: BB_A0 BB_B0
32036 #define IPC_REG_OTP_CONFIG_3                                                                         0x0204f4UL //Access:R    DataWidth:0x20  These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.  Chips: BB_A0 BB_B0
32037 #define IPC_REG_OTP_CONFIG_4                                                                         0x0204f8UL //Access:R    DataWidth:0x20  These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.  Chips: BB_A0 BB_B0
32038 #define IPC_REG_OTP_CONFIG_5                                                                         0x0204fcUL //Access:R    DataWidth:0x20  These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.  Chips: BB_A0 BB_B0
32039 #define IPC_REG_OTP_CONFIG_6                                                                         0x020500UL //Access:R    DataWidth:0x20  These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.  Chips: BB_A0 BB_B0
32040 #define IPC_REG_OTP_CONFIG_7                                                                         0x020504UL //Access:R    DataWidth:0x20  These bits represent the 256-bits of the configuration space in the OTP that is read out at POR.  Chips: BB_A0 BB_B0
32041 #define IPC_REG_PRTY_MASK                                                                            0x020520UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0
32042     #define IPC_REG_PRTY_MASK_FAKE_PAR_ERR                                                           (0x1<<0) // This bit masks, when set, the Parity bit: IPC_REG_PRTY_STS.FAKE_PAR_ERR .
32043     #define IPC_REG_PRTY_MASK_FAKE_PAR_ERR_SHIFT                                                     0
32044 #define IPC_REG_LCPLL_REFCLK_SEL                                                                     0x02052cUL //Access:RW   DataWidth:0x1   Selects the reference clock for the PLL 0= CMOS Reference clock, output of the differential oscillator 1= CML reference clock, from the chip pins Global register. Reset on POR reset.  Chips: BB_B0
32045 #define IPC_REG_OTP_ECC_DED_FLAG                                                                     0x020530UL //Access:R    DataWidth:0x8   Fdone Double Error Detection status flag      for each AUTOLOAD word  Chips: BB_B0
32046 #define IPC_REG_OTP_ECC_SEC_FLAG                                                                     0x020534UL //Access:R    DataWidth:0x8   Fdone Single Error Correction status flag for      each AUTOLOAD word  Chips: BB_B0
32047 #define IPC_REG_OTP_ECC_SEC_LATCH                                                                    0x020538UL //Access:R    DataWidth:0x8   Fdone Single Error Correction status latch.                         If Single Error Correction status flag was 1, this bit is latched with value 1.  Chips: BB_B0
32048 #define IPC_REG_CPU_OTP_RD_SYNDROME                                                                  0x02053cUL //Access:R    DataWidth:0x7   Syndrome output from the OTP read data command.  Chips: BB_B0
32049 #define CPMU_REG_LPI_EN                                                                              0x030200UL //Access:RW   DataWidth:0x1   0 : LPI is not enabled. 1 : LPI is enabled, LPI_REQ will be generated by the transmitter.  Chips: BB_A0 BB_B0 K2
32050 #define CPMU_REG_LPI_BNB_MODE                                                                        0x030204UL //Access:RW   DataWidth:0x1   Setting this bit will enable a special Batch and Burst mode in the LPI request logic. When this mode is enabled, CPMU will not exit LPI at the earliest indication (L1 exit or DORQ event for ex) but rather wait for BTB to be filled with a certain threshold bytes and then exit LPI. This allows for the system to not wake up just to send a single packet for ex and go back to LPI state. In this mode, the LPI exit can also happen after a programmable time tha the first packet is in the Tx Pipeline.  Chips: BB_A0 BB_B0 K2
32051 #define CPMU_REG_LPI_MODE_SLEEP_THRESHOLD                                                            0x030208UL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for the LPI mode. When the transmitter is IDLE, CPMU will wait for the sleep threshold to expire before setting the LPI request to the map. The resolution of this register is 40ns. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32052 #define CPMU_REG_LPI_BNB_MODE_SLEEP_THRESHOLD                                                        0x03020cUL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for the LPI mode in the Batch and Burst mode. LPI exit logic will wait for this time before exiting LPI. The resolution of this register is 40ns. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32053 #define CPMU_REG_LPI_MODE_ENTRY_EN                                                                   0x030210UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32054     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PBF_EMPTY_EN                                              (0x1<<0) // 0 : PBF Empty is not part of LPI request generation logic. 1 : PBF Empty is part of LPI request generation logic.
32055     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PBF_EMPTY_EN_SHIFT                                        0
32056     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_QM_EMPTY_EN                                               (0x1<<1) // 0 : QM Empty is not part of LPI request generation logic. 1 : QM Empty is part of LPI request generation logic. QM Empty only includes Network traffic for that port. Loopback traffic is not part of the LPI equation.
32057     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_QM_EMPTY_EN_SHIFT                                         1
32058     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_ALL_SQ_EMPTY_EN                                           (0x1<<2) // 0 : All Send Queue Empty is not part of LPI request generation logic. 1 : All Send Queue Empty is part of LPI request generation logic.
32059     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_ALL_SQ_EMPTY_EN_SHIFT                                     2
32060     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_MGMT_EMPTY_EN                                             (0x1<<3) // 0 : Management Traffic is not part of LPI request generation logic. 1 : Management Traffic is part of LPI request generation logic.
32061     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_MGMT_EMPTY_EN_SHIFT                                       3
32062     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_RX_LPI_STATUS_EN                                          (0x1<<4) // 0 : LPI receive status is not part of LPI request generation logic. 1 : LPI receive status is part of LPI request generation logic.
32063     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_RX_LPI_STATUS_EN_SHIFT                                    4
32064     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_OBFF_STATE_EN                                             (0x1<<5) // 0 : OBFF State (non CPU_ACTIVE) is not part of LPI request generation logic. 1 : OBFF State (non CPU_ACTIVE) is part of LPI request generation logic.
32065     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_OBFF_STATE_EN_SHIFT                                       5
32066     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PCIE_IN_D3_EN                                             (0x1<<6) // 0 : PCIe in D3 State is not part of LPI request generation logic. 1 : PCIe in D3 State is part of LPI request generation logic.
32067     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_PCIE_IN_D3_EN_SHIFT                                       6
32068     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_NIG_TX_EMPTY_EN                                           (0x1<<7) // 0 : NIG Tx is empty is not part of LPI request generation logic. 1 : NIG Tx is empty is part of LPI request generation logic.
32069     #define CPMU_REG_LPI_MODE_ENTRY_EN_LPI_NIG_TX_EMPTY_EN_SHIFT                                     7
32070 #define CPMU_REG_LPI_MODE_EXIT_EN                                                                    0x030214UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32071     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_DORQ_EVENT_EN                                              (0x1<<0) // 0 : DORQ Event is not part of the equation to exit LPI. 1 : DORQ Event is part of the equation to exit LPI.
32072     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_DORQ_EVENT_EN_SHIFT                                        0
32073     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_NCSI_EVENT_EN                                              (0x1<<1) // 0 : NCSI Event is not part of the equation to exit LPI. 1 : NCSI Event is part of the equation to exit LPI.
32074     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_NCSI_EVENT_EN_SHIFT                                        1
32075     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PCIE_L1_EXIT_EN                                            (0x1<<2) // 0 : PCIe L1 exit is not part of the equation to exit LPI. 1 : PCIe L1 exit is part of the equation to exit LPI.
32076     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PCIE_L1_EXIT_EN_SHIFT                                      2
32077     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PBF_ALMOST_FULL_EN                                         (0x1<<3) // This bit will be used in the Batch and Burst mode. In this mode, 0 : pbf almost full is not part of the equation to exit LPI. 1 : pbf almost full is part of the equation to exit LPI.
32078     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_PBF_ALMOST_FULL_EN_SHIFT                                   3
32079     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_BMB_ALMOST_FULL_EN                                         (0x1<<4) // This bit will be used in the Batch and Burst mode. In this mode, 0 : BMB almost full is not part of the equation to exit LPI. 1 : BMB almost full is part of the equation to exit LPI.
32080     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_BMB_ALMOST_FULL_EN_SHIFT                                   4
32081     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_SQ_EARLY_EXIT_EN                                           (0x1<<5) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the LPI exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, LPI will exit.
32082     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_SQ_EARLY_EXIT_EN_SHIFT                                     5
32083     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_RX_LPI_STATUS_EXIT_EN                                      (0x1<<6) // 0 : LPI receive status is not part of LPI request exit logic. 1 : LPI receive status is part of LPI request exit logic.
32084     #define CPMU_REG_LPI_MODE_EXIT_EN_LPI_RX_LPI_STATUS_EXIT_EN_SHIFT                                6
32085 #define CPMU_REG_SW_FORCE_LPI                                                                        0x030218UL //Access:RW   DataWidth:0x1   Setting this bit to "1" will allow software to force an LPI request on the interface. Clearing this bit will not automatically guarantee an exit from LPI if other elements in the LPI equation is causing an LPI request to go out. To do a forceful exit, SW needs to assert the sw_lpi_exit register.  Chips: BB_A0 BB_B0 K2
32086 #define CPMU_REG_SW_LPI_EXIT                                                                         0x03021cUL //Access:W    DataWidth:0x1   Setting this bit to "1" will allow software to provide an early indication to exit LPI state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.  Chips: BB_A0 BB_B0 K2
32087 #define CPMU_REG_OBFF_ENABLE                                                                         0x030220UL //Access:RW   DataWidth:0x1   0 : OBFF is not enabled. 1 : OBFF is enabled, DMA master requests could be stalled based on OBFF state machine.  Chips: BB_A0 BB_B0 K2
32088 #define CPMU_REG_OBFF_MODE_CONTROL                                                                   0x030224UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32089     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_FORCE                                                    (0x1<<0) // Reserved.
32090     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_FORCE_SHIFT                                              0
32091     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_ENGINE_IDLE_EN                                           (0x1<<1) // 0: Engine IDLE is not part of the OBFF state logic. 1: Engine IDLE is part of the OBFF state logic.
32092     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_ENGINE_IDLE_EN_SHIFT                                     1
32093     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_DEVICE_IDLE_FORCE                                        (0x1<<2) // Setting this bit forces the CPMU to force the device IDLE condition for OBFF operations.
32094     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_DEVICE_IDLE_FORCE_SHIFT                                  2
32095     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_IGU_PENDING_INTERRUPT_EN                                 (0x1<<3) // 0 : IGU Pending Interrupt is not part of OBFF logic w.r.t. IGU requests. 1 : IGU Pending Interrupt is part of OBFF logic w.r.t. IGU requests.
32096     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_IGU_PENDING_INTERRUPT_EN_SHIFT                           3
32097     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_VOQ_IGU_REQUESTS_EN                                      (0x1<<4) // 0 : VOQ for IGU requests is not part of OBFF logic w.r.t. IGU requests. 1 : VOQ for IGU requests is part of OBFF logic w.r.t. IGU requests.
32098     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_VOQ_IGU_REQUESTS_EN_SHIFT                                4
32099     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_INTERRUPTS_EN                                            (0x1<<5) // 0 : Interrupts are not part of OBFF logic w.r.t. IGU requests. 1 : Interrupts are part of OBFF logic w.r.t. IGU requests.
32100     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_INTERRUPTS_EN_SHIFT                                      5
32101     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_OVERRIDE                                                 (0x3<<6) // 00 : OBFF state that was received from the CPU is applicable. 01 : Forces the CPMU to override the OBFF state that was received from the CPU. The override state is OBFF. 10 : Forces the CPMU to override the OBFF state that was received from the CPU. The override state is IDLE. 11:  Reserved.
32102     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_OVERRIDE_SHIFT                                           6
32103     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_MEM_SET_VQ_EN                                      (0x1<<8) // 0 : For the FSM that drives stall_mem control, the control set logic is not conditioned with VOQ empty. 1 : For the FSM that drives stall_mem control, the control set logic is conditioned with VOQ empty.
32104     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_MEM_SET_VQ_EN_SHIFT                                8
32105     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_INT_SET_INT_EN                                     (0x1<<9) // 0 : For the FSM that drives stall_int control, the control set logic is not conditioned with VOQ empty / Interrupt Deasserted / No Pending Interrupt. 1 : For the FSM that drives stall_int control, the control set logic is conditioned with VOQ empty / Interrupt Deasserted / No Pending Interrupt.
32106     #define CPMU_REG_OBFF_MODE_CONTROL_OBFF_STALL_INT_SET_INT_EN_SHIFT                               9
32107 #define CPMU_REG_SW_OBFF_EXIT                                                                        0x030228UL //Access:W    DataWidth:0x1   Setting this bit to "1" will allow software to force an exit from the OBFF related stalls. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.  Chips: BB_A0 BB_B0 K2
32108 #define CPMU_REG_OBFF_MEM_TIMER_SHORT_THRESHOLD                                                      0x03022cUL //Access:RW   DataWidth:0x20  This register sets the short timer threshold for OBFF operation w.r.t memory requests in 40ns resolution. The OBFF state machine will launch a timer when memory requests are stalled. The Timer expires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported  Chips: BB_A0 BB_B0 K2
32109 #define CPMU_REG_OBFF_MEM_TIMER_LONG_THRESHOLD                                                       0x030230UL //Access:RW   DataWidth:0x20  This register sets the long timer threshold for OBFF operation w.r.t memory requests in 40ns resolution. The OBFF state machine will launch a timer when memory requests are stalled. The Timer expires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32110 #define CPMU_REG_OBFF_INT_TIMER_SHORT_THRESHOLD                                                      0x030234UL //Access:RW   DataWidth:0x20  This register sets the short timer threshold for OBFF operation w.r.t IGU requests in 40ns resolution. The OBFF state machine will launch a timer when IGU requests are stalled. The Timer expires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32111 #define CPMU_REG_OBFF_INT_TIMER_LONG_THRESHOLD                                                       0x030238UL //Access:RW   DataWidth:0x20  This register sets the long timer threshold for OBFF operation w.r.t IGU requests in 40ns resolution. The OBFF state machine will launch a timer when IGU requests are stalled. The Timer expires when it reaches this threshold and stall state is exited. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32112 #define CPMU_REG_OBFF_STALL_ON_OBFF_STATE_0                                                          0x03023cUL //Access:RW   DataWidth:0x20  Setting each bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the system in the "OBFF" state. If a bit is not set and the corresponding VOQ is not empty, the stall state is removed immediately. This register correcponds to bits [31:0] of the VOQ bus.  Chips: BB_A0 BB_B0 K2
32113 #define CPMU_REG_OBFF_STALL_ON_OBFF_STATE_1                                                          0x030240UL //Access:RW   DataWidth:0x2   Setting each bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the system in the "OBFF" state. If a bit is not set and the corresponding VOQ is not empty, the stall state is removed immediatelyempty. This register correcponds to bits [33:32] of the VOQ bus.  Chips: BB_A0 BB_B0 K2
32114 #define CPMU_REG_OBFF_STALL_ON_IDLE_STATE_0                                                          0x030244UL //Access:RW   DataWidth:0x20  Setting each bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the system in the "IDLE" state. If a bit is not set and the corresponding VOQ is not empty, the stall state is removed immediately. This register correcponds to bits [31:0] of the VOQ bus.  Chips: BB_A0 BB_B0 K2
32115 #define CPMU_REG_OBFF_STALL_ON_IDLE_STATE_1                                                          0x030248UL //Access:RW   DataWidth:0x2   Setting each bit in this register to "1" will cause the CPMU to launch a timer when the corresponding VOQ is not empty and the system in the "IDLE" state. If a bit is not set and the corresponding VOQ is not empty, the stall state is removed immediately. This register correcponds to bits [33:32] of the VOQ bus.  Chips: BB_A0 BB_B0 K2
32116 #define CPMU_REG_OBFF_MODE_SLEEP_THRESHOLD                                                           0x03024cUL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for entry to OBFF state. The resolution of this register is 40ns. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32117 #define CPMU_REG_OBFF_MODE_ENTRY_EN                                                                  0x030250UL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32118     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PBF_EMPTY_EN                                            (0x1<<0) // 0 : PBF Empty is not part of OBFF logic. 1 : PBF Empty is not part of OBFF logic.
32119     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PBF_EMPTY_EN_SHIFT                                      0
32120     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_TX_EN                                          (0x1<<1) // 0 : QM Tx Empty is not part of OBFF logic. 1 : QM Tx Empty is part of OBFF logic.
32121     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_TX_EN_SHIFT                                    1
32122     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_GLOBAL_EN                                      (0x1<<2) // 0 : QM Global Empty is not part of main clock slowdown generation logic. 1 : QM Global Empty is part of main clock slowdown generation logic.
32123     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_QM_EMPTY_GLOBAL_EN_SHIFT                                2
32124     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_ALL_SQ_EMPTY_EN                                         (0x1<<3) // 0 : All Send Queue Empty is not part of OBFF logic. 1 : All Send Queue Empty is part of OBFF logic.
32125     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_ALL_SQ_EMPTY_EN_SHIFT                                   3
32126     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MGMT_EMPTY_EN                                           (0x1<<4) // 0 : Management Traffic is not part of OBFF logic. 1 : Management Traffic is part of OBFF logic.
32127     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MGMT_EMPTY_EN_SHIFT                                     4
32128     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_BRB_EMPTY_EN                                            (0x1<<5) // 0 : BRB empty is not part of OBFF logic. 1 : BRB empty is part of OBFF logic.
32129     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_BRB_EMPTY_EN_SHIFT                                      5
32130     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PXP_EMPTY_EN                                            (0x1<<6) // 0 : PXP empty is not part of OBFF logic. 1 : PXP empty is part of OBFF logic.
32131     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PXP_EMPTY_EN_SHIFT                                      6
32132     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_CAU_IDLE_EN                                             (0x1<<7) // 0 : CAU IDLE is not part of OBFF logic. 1 : CAU IDLE is part of OBFF logic.
32133     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_CAU_IDLE_EN_SHIFT                                       7
32134     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TM_SCAN_EN                                              (0x1<<8) // 0 : Timer Scan status is not part of OBFF logic. 1 : Timer Scan status is part of OBFF logic.
32135     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TM_SCAN_EN_SHIFT                                        8
32136     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_OBFF_STATE_EN                                           (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of OBFF logic. 1 : OBFF State (non CPU_ACTIVE) is part of OBFF logic.
32137     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_OBFF_STATE_EN_SHIFT                                     9
32138     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TSEM_IDLE_EN                                            (0x1<<10) // 0 : TSEM IDLE is not part of OBFF logic. 1 : TSEM IDLE is part of OBFF logic.
32139     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_TSEM_IDLE_EN_SHIFT                                      10
32140     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MSEM_IDLE_EN                                            (0x1<<11) // 0 : MSEM IDLE is not part of OBFF logic. 1 : MSEM IDLE is part of OBFF logic.
32141     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_MSEM_IDLE_EN_SHIFT                                      11
32142     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_USEM_IDLE_EN                                            (0x1<<12) // 0 : USEM IDLE is not part of OBFF logic. 1 : USEM IDLE is part of OBFF logic.
32143     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_USEM_IDLE_EN_SHIFT                                      12
32144     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_XSEM_IDLE_EN                                            (0x1<<13) // 0 : XSEM IDLE is not part of OBFF logic. 1 : XSEM IDLE is part of OBFF logic.
32145     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_XSEM_IDLE_EN_SHIFT                                      13
32146     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_YSEM_IDLE_EN                                            (0x1<<14) // 0 : YSEM IDLE is not part of OBFF logic. 1 : YSEM IDLE is part of OBFF logic.
32147     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_YSEM_IDLE_EN_SHIFT                                      14
32148     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PSEM_IDLE_EN                                            (0x1<<15) // 0 : PSEM IDLE is not part of OBFF logic. 1 : PSEM IDLE is part of OBFF logic.
32149     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_PSEM_IDLE_EN_SHIFT                                      15
32150     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_RX_LPI_STATUS_EN                                        (0x1<<16) // 0 : LPI receive status is not part of OBFF logic. 1 : LPI receive status is part of OBFF logic.
32151     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_RX_LPI_STATUS_EN_SHIFT                                  16
32152     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NW_LINKDOWN_EN                                          (0x1<<17) // 0 : Network Link Down is not part of OBFF logic. 1 : Network Link Down is part of OBFF logic.
32153     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NW_LINKDOWN_EN_SHIFT                                    17
32154     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_RX_EMPTY_EN                                         (0x1<<18) // 0 : NIG Rx Empty is not part of OBFF logic. 1 : NIG Rx Empty is part of OBFF logic.
32155     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_RX_EMPTY_EN_SHIFT                                   18
32156     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_TX_EMPTY_EN                                         (0x1<<19) // 0 : NIG Tx Empty is not part of OBFF logic. 1 : NIG Tx Empty is part of OBFF logic.
32157     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_TX_EMPTY_EN_SHIFT                                   19
32158     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_LB_EMPTY_EN                                         (0x1<<20) // 0 : NIG lb Empty is not part of OBFF logic. 1 : NIG lb Empty is part of OBFF logic.
32159     #define CPMU_REG_OBFF_MODE_ENTRY_EN_OBFF_NIG_LB_EMPTY_EN_SHIFT                                   20
32160 #define CPMU_REG_OBFF_MODE_EXIT_EN                                                                   0x030254UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32161     #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_PCIE_L1_EXIT_EN                                          (0x1<<0) // 0 : PCIe L1 exit is not part of exit from OBFF logic 1 : PCIe L1 exit is part of exit from OBFF logic
32162     #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_PCIE_L1_EXIT_EN_SHIFT                                    0
32163     #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_DORQ_EVENT_EN                                            (0x1<<1) // 0 : DORQ Event is not part of exit from OBFF logic 1 : DORQ Event is part of exit from OBFF logic
32164     #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_DORQ_EVENT_EN_SHIFT                                      1
32165     #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_SQ_EARLY_EXIT_EN                                         (0x1<<2) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the OBFF exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, OBFF will exit.
32166     #define CPMU_REG_OBFF_MODE_EXIT_EN_OBFF_SQ_EARLY_EXIT_EN_SHIFT                                   2
32167 #define CPMU_REG_OBFF_IGU_VOQ_NUM                                                                    0x030258UL //Access:RW   DataWidth:0x6   This register sets the VOQ number for IGU request. This is used to distinguish between memory and interrupt transactions.  Chips: BB_A0 BB_B0 K2
32168 #define CPMU_REG_OBFF_VOQ_TIMEOUT_TYPE_0                                                             0x03025cUL //Access:RW   DataWidth:0x20  0 : use the short timer threshold for the corresponding VOQ. 1 : use the long timer threshold for the corresponding VOQ. This register correcponds to bits [31:0] of the VOQ bus.  Chips: BB_A0 BB_B0 K2
32169 #define CPMU_REG_OBFF_VOQ_TIMEOUT_TYPE_1                                                             0x030260UL //Access:RW   DataWidth:0x2   0 : use the short timer threshold for the corresponding VOQ. 1 : use the long timer threshold for the corresponding VOQ. This register correcponds to bits [33:32] of the VOQ bus.  Chips: BB_A0 BB_B0 K2
32170 #define CPMU_REG_L1_ENTRY_EN                                                                         0x030264UL //Access:RW   DataWidth:0x1   0 : Entry to PCIe L1 is not enabled. 1 : Entry to PCIe L1 is enabled. This reflects the CPMU output and it is in addition to PCIE CORE register which controls entry to L1.  Chips: BB_A0 BB_B0 K2
32171 #define CPMU_REG_L1_MODE_SLEEP_THRESHOLD                                                             0x030268UL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for the L1 mode. The resolution of this register is 40ns. Value of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32172 #define CPMU_REG_L1_MODE_ENTRY_EN                                                                    0x03026cUL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32173     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PBF_EMPTY_EN                                                (0x1<<0) // 0 : PBF Empty is not part of L1 request generation logic. 1 : PBF Empty is part of L1 request generation logic.
32174     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PBF_EMPTY_EN_SHIFT                                          0
32175     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_TX_EN                                              (0x1<<1) // 0 : QM Tx Empty is not part of L1 request generation logic. 1 : QM Tx Empty is part of L1 request generation logic.
32176     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_TX_EN_SHIFT                                        1
32177     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_GLOBAL_EN                                          (0x1<<2) // 0 : QM Global Empty is not part of L1 request generation logic. 1 : QM Global Empty is part of L1 request generation logic.
32178     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_QM_EMPTY_GLOBAL_EN_SHIFT                                    2
32179     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_ALL_SQ_EMPTY_EN                                             (0x1<<3) // 0 : All Send Queue Empty is not part of L1 request generation logic. 1 : All Send Queue Empty is part of L1 request generation logic.
32180     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_ALL_SQ_EMPTY_EN_SHIFT                                       3
32181     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_MGMT_EMPTY_EN                                               (0x1<<4) // 0 : Management Traffic is not part of L1 request generation logic. 1 : Management Traffic is part of L1 request generation logic.
32182     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_MGMT_EMPTY_EN_SHIFT                                         4
32183     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_BRB_EMPTY_EN                                                (0x1<<5) // 0 : BRB empty is not part of L1 request generation logic. 1 : BRB empty is part of L1 request generation logic.
32184     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_BRB_EMPTY_EN_SHIFT                                          5
32185     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PXP_EMPTY_EN                                                (0x1<<6) // 0 : PXP empty is not part of L1 request generation logic. 1 : PXP empty is part of L1 request generation logic.
32186     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PXP_EMPTY_EN_SHIFT                                          6
32187     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PGL_EMPTY_EN                                                (0x1<<7) // 0 : PGL empty is not part of L1 request generation logic. 1 : PGL empty is part of L1 request generation logic.
32188     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_PGL_EMPTY_EN_SHIFT                                          7
32189     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_CAU_IDLE_EN                                                 (0x1<<8) // 0 : CAU IDLE is not part of L1 request generation logic. 1 : CAU IDLE is part of L1 request generation logic.
32190     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_CAU_IDLE_EN_SHIFT                                           8
32191     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_TM_SCAN_EN                                                  (0x1<<9) // 0 : Timer Scan status is not part of L1 request generation logic. 1 : Timer Scan status is part of L1 request generation logic.
32192     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_TM_SCAN_EN_SHIFT                                            9
32193     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_RX_LPI_STATUS_EN                                            (0x1<<10) // 0 : LPI receive status is not part of L1 request generation logic. 1 : LPI receive status is part of L1 request generation logic.
32194     #define CPMU_REG_L1_MODE_ENTRY_EN_L1_RX_LPI_STATUS_EN_SHIFT                                      10
32195 #define CPMU_REG_L1_MODE_EXIT_EN                                                                     0x030270UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32196     #define CPMU_REG_L1_MODE_EXIT_EN_L1_RX_LPI_STATUS_EXIT_EN                                        (0x1<<0) // 0 : LPI recive status is not part of the L1 exit. 1 : LPI recive status is part of the L1 exit.
32197     #define CPMU_REG_L1_MODE_EXIT_EN_L1_RX_LPI_STATUS_EXIT_EN_SHIFT                                  0
32198     #define CPMU_REG_L1_MODE_EXIT_EN_L1_SQ_EARLY_EXIT_EN                                             (0x1<<1) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the L1 exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, L1 will exit.
32199     #define CPMU_REG_L1_MODE_EXIT_EN_L1_SQ_EARLY_EXIT_EN_SHIFT                                       1
32200 #define CPMU_REG_SW_FORCE_L1                                                                         0x030274UL //Access:RW   DataWidth:0x1   Setting this bit to "1" will allow software to force an L1 request on the interface. Clearing this bit will not automatically guarantee an exit from L1 if other elements in the L1 equation is causing an L1 request to go out. To do a forceful exit, SW needs to assert the sw_l1_exit register.  Chips: BB_A0 BB_B0 K2
32201 #define CPMU_REG_SW_L1_EXIT                                                                          0x030278UL //Access:W    DataWidth:0x1   Setting this bit to "1" will allow software to provide an early indication to exit L1 state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.  Chips: BB_A0 BB_B0 K2
32202 #define CPMU_REG_LTR_SEND_EN                                                                         0x03027cUL //Access:RW   DataWidth:0x1   0 : Entry to PCIe LTR is not enabled. 1 : Entry to PCIe LTR is enabled  Chips: BB_A0 BB_B0 K2
32203 #define CPMU_REG_LTR_MODE_SLEEP_THRESHOLD                                                            0x030280UL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for the LTR mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32204 #define CPMU_REG_LTR_MODE_ENTRY_EN                                                                   0x030284UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32205     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PBF_EMPTY_EN                                              (0x1<<0) // 0 : PBF Empty is not part of LTR request generation logic. 1 : PBF Empty is part of LTR request generation logic.
32206     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PBF_EMPTY_EN_SHIFT                                        0
32207     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_TX_EN                                            (0x1<<1) // 0 : QM Tx Empty is not part of LTR request generation logic. 1 : QM Tx Empty is part of LTR request generation logic.
32208     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_TX_EN_SHIFT                                      1
32209     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_GLOBAL_EN                                        (0x1<<2) // 0 : QM Global Empty is not part of LTR request generation logic. 1 : QM Global Empty is part of LTR request generation logic.
32210     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_QM_EMPTY_GLOBAL_EN_SHIFT                                  2
32211     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_ALL_SQ_EMPTY_EN                                           (0x1<<3) // 0 : All Send Queue Empty is not part of LTR request generation logic. 1 : All Send Queue Empty is part of LTR request generation logic.
32212     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_ALL_SQ_EMPTY_EN_SHIFT                                     3
32213     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_MGMT_EMPTY_EN                                             (0x1<<4) // 0 : Management Traffic is not part of LTR request generation logic. 1 : Management Traffic is part of LTR request generation logic.
32214     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_MGMT_EMPTY_EN_SHIFT                                       4
32215     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_BRB_CHECK_EN                                              (0x1<<5) // 0 : BRB above threshold is not part of LTR request generation logic. 1 : BRB above threshold is part of LTR request generation logic.
32216     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_BRB_CHECK_EN_SHIFT                                        5
32217     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PXP_EMPTY_EN                                              (0x1<<6) // 0 : PXP empty is not part of LTR request generation logic. 1 : PXP empty is part of LTR request generation logic.
32218     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PXP_EMPTY_EN_SHIFT                                        6
32219     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PGL_EMPTY_EN                                              (0x1<<7) // 0 : PGL empty is not part of LTR request generation logic. 1 : PGL empty is part of LTR request generation logic.
32220     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_PGL_EMPTY_EN_SHIFT                                        7
32221     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_CAU_IDLE_EN                                               (0x1<<8) // 0 : CAU IDLE is not part of LTR request generation logic. 1 : CAU IDLE is part of LTR request generation logic.
32222     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_CAU_IDLE_EN_SHIFT                                         8
32223     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_TM_SCAN_EN                                                (0x1<<9) // 0 : Timer Scan status is not part of LTR request generation logic. 1 : Timer Scan status is part of LTR request generation logic.
32224     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_TM_SCAN_EN_SHIFT                                          9
32225     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_RX_LPI_STATUS_EN                                          (0x1<<10) // 0 : LPI receive status is not part of LTR request generation logic. 1 : LPI receive status is part of LTR request generation logic.
32226     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_RX_LPI_STATUS_EN_SHIFT                                    10
32227     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_MEM_STALL_EN                                         (0x1<<11) // 0 : OBFF Memory access stall is not part of LTR request generation logic. 1 : OBFF Memory access stall is part of LTR request generation logic.
32228     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_MEM_STALL_EN_SHIFT                                   11
32229     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_INT_STALL_EN                                         (0x1<<12) // 0 : OBFF interrupt access stall is not part of LTR request generation logic. 1 : OBFF interrupt access stall is part of LTR request generation logic.
32230     #define CPMU_REG_LTR_MODE_ENTRY_EN_LTR_OBFF_INT_STALL_EN_SHIFT                                   12
32231 #define CPMU_REG_LTR_MODE_EXIT_EN                                                                    0x030288UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32232     #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_RX_LPI_STATUS_EXIT_EN                                      (0x1<<0) // 0 : LPI recive status is not part of the LTR exit. 1 : LPI recive status is part of the LTR exit.
32233     #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_RX_LPI_STATUS_EXIT_EN_SHIFT                                0
32234     #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_SQ_EARLY_EXIT_EN                                           (0x1<<1) // This bit will be used in the Normal mode. In this mode, 0 : Early exit indication from X or USTORM is not part of the LTR exit equation. 1 : When early exit is indicated either by XSTORM or USTORM, LTR will exit.
32235     #define CPMU_REG_LTR_MODE_EXIT_EN_LTR_SQ_EARLY_EXIT_EN_SHIFT                                     1
32236 #define CPMU_REG_SW_FORCE_LTR                                                                        0x03028cUL //Access:RW   DataWidth:0x1   Setting this bit to "1" will allow software to force an LTR request on the interface. Clearing this bit will not automatically guarantee an exit from LTR if other elements in the LTR equation is causing an LTR request to go out. To do a forceful exit, SW needs to assert the sw_ltr_exit register.  Chips: BB_A0 BB_B0 K2
32237 #define CPMU_REG_SW_LTR_EXIT                                                                         0x030290UL //Access:W    DataWidth:0x1   Setting this bit to "1" will allow software to provide an early indication to exit LTR state. HW will generate a pulse on low to high transition of this register. The resultant bit is Self Clearing.  Chips: BB_A0 BB_B0 K2
32238 #define CPMU_REG_CLK_EN_CONFIG                                                                       0x030294UL //Access:RW   DataWidth:0x19  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32239     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E0_EN                                                    (0x1<<0) // 0 : Shutdown Main Clock to Path 0 1 : Enable Main Clock to Path 0
32240     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E0_EN_SHIFT                                              0
32241     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E1_EN                                                    (0x1<<1) // 0 : Shutdown Main Clock to Path 1 1 : Enable Main Clock to Path 1
32242     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_E1_EN_SHIFT                                              1
32243     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E0_EN                                                 (0x1<<2) // 0 : Shutdown Main Clock to Path 0 on the Network side 1 : Enable Main Clock to Path 0 on the Network side
32244     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E0_EN_SHIFT                                           2
32245     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E1_EN                                                 (0x1<<3) // 0 : Shutdown Main Clock to Path 1 on the Network side 1 : Enable Main Clock to Path 1 on the Network side
32246     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NM_E1_EN_SHIFT                                           3
32247     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NMC_EN                                                   (0x1<<4) // 0 : Shutdown Main Clock to Common Logic on the Network side 1 : Enable Main Clock to Common Logic on the Network side
32248     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_NMC_EN_SHIFT                                             4
32249     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_HOST_EN                                                  (0x1<<5) // 0 : Shutdown Main Clock to Common Logic on the Host side 1 : Enable Main Clock to Common Logic on the Host side
32250     #define CPMU_REG_CLK_EN_CONFIG_MAIN_CLK_HOST_EN_SHIFT                                            5
32251     #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E0_EN                                                   (0x1<<6) // 0 : Shutdown STORM Clock to Path 0 1 : Enable STORM Clock to Path 0
32252     #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E0_EN_SHIFT                                             6
32253     #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E1_EN                                                   (0x1<<7) // 0 : Shutdown STORM Clock to Path 1 1 : Enable STORM Clock to Path 1
32254     #define CPMU_REG_CLK_EN_CONFIG_STORM_CLK_E1_EN_SHIFT                                             7
32255     #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E0_EN                                                      (0x1<<8) // 0 : Shutdown Network Clock to Path 0 1 : Enable Network Clock to Path 0
32256     #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E0_EN_SHIFT                                                8
32257     #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E1_EN                                                      (0x1<<9) // 0 : Shutdown Network Clock to Path 1 1 : Enable Network Clock to Path 1
32258     #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_E1_EN_SHIFT                                                9
32259     #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_CMN_EN                                                     (0x1<<10) // 0 : Shutdown Network Clock to Common logic 1 : Enable Network Clock to Common logic
32260     #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_CMN_EN_SHIFT                                               10
32261     #define CPMU_REG_CLK_EN_CONFIG_CFG_CLK_EN                                                        (0x1<<11) // 0 : Shutdown Configuration Clock to PCIe Core 1 : Enable Configuration Clock to PCIe Core
32262     #define CPMU_REG_CLK_EN_CONFIG_CFG_CLK_EN_SHIFT                                                  11
32263     #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E0_EN                                                     (0x1<<12) // 0 : Shutdown PCI Clock to Path 0 1 : Enable PCI clock to Path 0
32264     #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E0_EN_SHIFT                                               12
32265     #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E1_EN                                                     (0x1<<13) // 0 : Shutdown PCI Clock to Path 1 1 : Enable PCI clock to Path 1
32266     #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_E1_EN_SHIFT                                               13
32267     #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_HOST_EN                                                   (0x1<<14) // 0 : Shutdown PCI Clock to Common logic on the host side 1 : Enable PCI clock to Common logic on the host side
32268     #define CPMU_REG_CLK_EN_CONFIG_PCI_CLK_HOST_EN_SHIFT                                             14
32269     #define CPMU_REG_CLK_EN_CONFIG_PMFC_CLK_EN                                                       (0x1<<15) // 0 : Shutdown all clocks to the Falcon based Port Macro 1 : Enable all clocks to the Falcon based Port Macro
32270     #define CPMU_REG_CLK_EN_CONFIG_PMFC_CLK_EN_SHIFT                                                 15
32271     #define CPMU_REG_CLK_EN_CONFIG_PMEG_CLK_EN                                                       (0x1<<16) // 0 : Shutdown all clocks to the Eagle based Port Macro 1 : Enable all clocks to the Eagle based Port Macro
32272     #define CPMU_REG_CLK_EN_CONFIG_PMEG_CLK_EN_SHIFT                                                 16
32273     #define CPMU_REG_CLK_EN_CONFIG_NWM_CLK_EN                                                        (0x1<<17) // 0 : Shutdown NWM clock to the NW MAC 1 : Enable NWM clock to the NW MAC
32274     #define CPMU_REG_CLK_EN_CONFIG_NWM_CLK_EN_SHIFT                                                  17
32275     #define CPMU_REG_CLK_EN_CONFIG_BMB_CLK_EN                                                        (0x1<<18) // 0 : Shutdown Main Clock to the BMB PD 1 : Enable Main Clock to the BMB PD
32276     #define CPMU_REG_CLK_EN_CONFIG_BMB_CLK_EN_SHIFT                                                  18
32277     #define CPMU_REG_CLK_EN_CONFIG_BMB_NW_CLK_EN                                                     (0x1<<19) // 0 : Shutdown Network Clock to the BMB PD 1 : Enable Network Clock to the BMB PD
32278     #define CPMU_REG_CLK_EN_CONFIG_BMB_NW_CLK_EN_SHIFT                                               19
32279     #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_EN                                                         (0x1<<20) // 0 : Shutdown Main Clock to the NW PD 1 : Enable Main Clock to the NW PD
32280     #define CPMU_REG_CLK_EN_CONFIG_NW_CLK_EN_SHIFT                                                   20
32281     #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_CLK_EN                                                   (0x1<<21) // 0 : Shutdown Main Clock to the NMC PD 1 : Enable Main Clock to the NMC PD
32282     #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_CLK_EN_SHIFT                                             21
32283     #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_NW_CLK_EN                                                (0x1<<22) // 0 : Shutdown Network Clock to the NMC PD 1 : Enable Network Clock to the NMC PD
32284     #define CPMU_REG_CLK_EN_CONFIG_NMC_ONLY_NW_CLK_EN_SHIFT                                          22
32285     #define CPMU_REG_CLK_EN_CONFIG_NMC_AHB_CLK_EN                                                    (0x1<<23) // 0 : Shutdown AHB Clock to the NMC PD 1 : Enable AHB Clock to the NMC PD
32286     #define CPMU_REG_CLK_EN_CONFIG_NMC_AHB_CLK_EN_SHIFT                                              23
32287     #define CPMU_REG_CLK_EN_CONFIG_TOP_CLK_EN                                                        (0x1<<24) // 0 : Shutdown Main Clock to the TOP 1 : Enable Main Clock to the TOP
32288     #define CPMU_REG_CLK_EN_CONFIG_TOP_CLK_EN_SHIFT                                                  24
32289 #define CPMU_REG_CLK_PM_CONFIG                                                                       0x030298UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32290     #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_MAIN_CLK_EN                                              (0x1<<0) // 0 : Slowdown of Main Clock is not enabled. 1 : Slowdown of Main Clock is enabled
32291     #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_MAIN_CLK_EN_SHIFT                                        0
32292     #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_STORM_CLK_EN                                             (0x1<<1) // 0 : Slowdown of STORM Clock is not enabled. 1 : Slowdown of STORM Clock is enabled
32293     #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_STORM_CLK_EN_SHIFT                                       1
32294     #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_NW_CLK_EN                                                (0x1<<2) // 0 : Slowdown of Network Clock is not enabled. 1 : Slowdown of Network Clock is enabled
32295     #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_NW_CLK_EN_SHIFT                                          2
32296     #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_PCI_CLK_EN                                               (0x1<<3) // 0 : Slowdown of PCI Clock is not enabled. 1 : Slowdown of PCI Clock is enabled
32297     #define CPMU_REG_CLK_PM_CONFIG_SLOWDOWN_PCI_CLK_EN_SHIFT                                         3
32298 #define CPMU_REG_CLK_PM_CMN_CONFIG                                                                   0x03029cUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32299     #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_MAIN_CLK_CMN_EN                                      (0x1<<0) // 0 : Slowdown of Main Clock for common logic is not enabled. 1 : Slowdown of Main Clock for common logic is enabled
32300     #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_MAIN_CLK_CMN_EN_SHIFT                                0
32301     #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_NW_CLK_CMN_EN                                        (0x1<<1) // 0 : Slowdown of Network Clock for common logic is not enabled. 1 : Slowdown of Network Clock for common logic is enabled
32302     #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_NW_CLK_CMN_EN_SHIFT                                  1
32303     #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_PCI_CLK_CMN_EN                                       (0x1<<2) // 0 : Slowdown of PCI Clock for common logic is not enabled. 1 : Slowdown of PCI Clock for common logic is enabled
32304     #define CPMU_REG_CLK_PM_CMN_CONFIG_SLOWDOWN_PCI_CLK_CMN_EN_SHIFT                                 2
32305 #define CPMU_REG_MAIN_CLK_MODE_SLEEP_THRESHOLD                                                       0x0302a0UL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for the Main Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32306 #define CPMU_REG_STORM_CLK_MODE_SLEEP_THRESHOLD                                                      0x0302a4UL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for the storm Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32307 #define CPMU_REG_NW_CLK_MODE_SLEEP_THRESHOLD                                                         0x0302a8UL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for the storm Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32308 #define CPMU_REG_PCI_CLK_MODE_SLEEP_THRESHOLD                                                        0x0302acUL //Access:RW   DataWidth:0x20  This register sets the Sleep Threshold for the storm Clock slowdown mode. The resolution of this register is 40ns. Values of 0 and 1 are not supported.  Chips: BB_A0 BB_B0 K2
32309 #define CPMU_REG_SLOWDOWN_MAIN_CLK_RATIO                                                             0x0302b0UL //Access:RW   DataWidth:0x6   This register sets the ratio of how many MAIN clock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register will result in the clock generation logic to send 1 clock pulse through for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this feature. This register should be written when the CPMU is not enabled. In other words, SW/FW should ensure that this register is not programmed dynamically.  Chips: BB_A0 BB_B0 K2
32310 #define CPMU_REG_SLOWDOWN_STORM_CLK_RATIO                                                            0x0302b4UL //Access:RW   DataWidth:0x6   This register sets the ratio of how many STORM clock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register will result in the clock generation logic to send 1 clock pulse through for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this feature. This register should be written when the CPMU is not enabled. In other words, SW/FW should ensure that this register is not programmed dynamically.  Chips: BB_A0 BB_B0 K2
32311 #define CPMU_REG_SLOWDOWN_NW_CLK_RATIO                                                               0x0302b8UL //Access:RW   DataWidth:0x6   This register sets the ratio of how many NW clock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register will result in the clock generation logic to send 1 clock pulse through for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this feature. This register should be written when the CPMU is not enabled. In other words, SW/FW should ensure that this register is not programmed dynamically.  Chips: BB_A0 BB_B0 K2
32312 #define CPMU_REG_SLOWDOWN_PCI_CLK_RATIO                                                              0x0302bcUL //Access:RW   DataWidth:0x6   This register sets the ratio of how many PCI clock pulses to ignore before letting one clock pulse through. For ex a value of 15 in the register will result in the clock generation logic to send 1 clock pulse through for every 15 clock pulses. So for a clock rate of 375Mhz, the effective frequency will be 25Mhz. A value >= 2 should be set when using this feature. This register should be written when the CPMU is not enabled. In other words, SW/FW should ensure that this register is not programmed dynamically.  Chips: BB_A0 BB_B0 K2
32313 #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN                                                          0x0302c0UL //Access:RW   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32314     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PBF_EMPTY_EN                                     (0x1<<0) // 0 : PBF Empty is not part of main clock slowdown logic. 1 : PBF Empty is not part of main clock slowdown logic.
32315     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PBF_EMPTY_EN_SHIFT                               0
32316     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_TX_EN                                   (0x1<<1) // 0 : QM Tx Empty is not part of main clock slowdown generation logic. 1 : QM Tx Empty is part of main clock slowdown generation logic.
32317     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_TX_EN_SHIFT                             1
32318     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_GLOBAL_EN                               (0x1<<2) // 0 : QM Global Empty is not part of main clock slowdown generation logic. 1 : QM Global Empty is part of main clock slowdown generation logic.
32319     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_QM_EMPTY_GLOBAL_EN_SHIFT                         2
32320     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_ALL_SQ_EMPTY_EN                                  (0x1<<3) // 0 : All Send Queue Empty is not part of Main Clock slowdown logic. 1 : All Send Queue Empty is part of Main Clock slowdown logic.
32321     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_ALL_SQ_EMPTY_EN_SHIFT                            3
32322     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MGMT_EMPTY_EN                                    (0x1<<4) // 0 : Management Traffic is not part of Main Clock slowdown logic. 1 : Management Traffic is part of Main Clock slowdown logic.
32323     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MGMT_EMPTY_EN_SHIFT                              4
32324     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_BRB_EMPTY_EN                                     (0x1<<5) // 0 : BRB empty is not part of Main Clock slowdown logic. 1 : BRB empty is part of Main Clock slowdown logic.
32325     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_BRB_EMPTY_EN_SHIFT                               5
32326     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PXP_EMPTY_EN                                     (0x1<<6) // 0 : PXP empty is not part of Main Clock slowdown logic. 1 : PXP empty is part of Main Clock slowdown logic.
32327     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PXP_EMPTY_EN_SHIFT                               6
32328     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_CAU_IDLE_EN                                      (0x1<<7) // 0 : CAU IDLE is not part of Main Clock slowdown logic. 1 : CAU IDLE is part of Main Clock slowdown logic.
32329     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_CAU_IDLE_EN_SHIFT                                7
32330     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TM_SCAN_EN                                       (0x1<<8) // 0 : Timer Scan status is not part of Main Clock slowdown logic. 1 : Timer Scan status is part of Main Clock slowdown logic.
32331     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TM_SCAN_EN_SHIFT                                 8
32332     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_OBFF_STATE_EN                                    (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Main Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Main Clock slowdown logic.
32333     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_OBFF_STATE_EN_SHIFT                              9
32334     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TSEM_IDLE_EN                                     (0x1<<10) // 0 : TSEM IDLE is not part of Main Clock slowdown logic. 1 : TSEM IDLE is part of Main Clock slowdown logic.
32335     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_TSEM_IDLE_EN_SHIFT                               10
32336     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MSEM_IDLE_EN                                     (0x1<<11) // 0 : MSEM IDLE is not part of Main Clock slowdown logic. 1 : MSEM IDLE is part of Main Clock slowdown logic.
32337     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_MSEM_IDLE_EN_SHIFT                               11
32338     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_USEM_IDLE_EN                                     (0x1<<12) // 0 : USEM IDLE is not part of Main Clock slowdown logic. 1 : USEM IDLE is part of Main Clock slowdown logic.
32339     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_USEM_IDLE_EN_SHIFT                               12
32340     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_XSEM_IDLE_EN                                     (0x1<<13) // 0 : XSEM IDLE is not part of Main Clock slowdown logic. 1 : XSEM IDLE is part of Main Clock slowdown logic.
32341     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_XSEM_IDLE_EN_SHIFT                               13
32342     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_YSEM_IDLE_EN                                     (0x1<<14) // 0 : YSEM IDLE is not part of Main Clock slowdown logic. 1 : YSEM IDLE is part of Main Clock slowdown logic.
32343     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_YSEM_IDLE_EN_SHIFT                               14
32344     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PSEM_IDLE_EN                                     (0x1<<15) // 0 : PSEM IDLE is not part of Main Clock slowdown logic. 1 : PSEM IDLE is part of Main Clock slowdown logic.
32345     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PSEM_IDLE_EN_SHIFT                               15
32346     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_RX_LPI_STATUS_EN                                 (0x1<<16) // 0 : LPI receive status is not part of Main Clock slowdown logic. 1 : LPI receive status is part of Main Clock slowdown logic.
32347     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_RX_LPI_STATUS_EN_SHIFT                           16
32348     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NW_LINKDOWN_EN                                   (0x1<<17) // 0 : Network Link Down is not part of Main Clock slowdown logic. 1 : Network Link Down is part of Main Clock slowdown logic.
32349     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NW_LINKDOWN_EN_SHIFT                             17
32350     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_RX_EMPTY_EN                                  (0x1<<18) // 0 : NIG Rx Empty is not part of Main Clock slowdown logic. 1 : NIG Rx Empty is part of Main Clock slowdown logic.
32351     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_RX_EMPTY_EN_SHIFT                            18
32352     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_TX_EMPTY_EN                                  (0x1<<19) // 0 : NIG Tx Empty is not part of Main Clock slowdown logic. 1 : NIG Tx Empty is part of Main Clock slowdown logic.
32353     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_TX_EMPTY_EN_SHIFT                            19
32354     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_LB_EMPTY_EN                                  (0x1<<20) // 0 : NIG Loopback Empty is not part of Main Clock slowdown logic. 1 : NIG Loopback Empty is part of Main Clock slowdown logic.
32355     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_NIG_LB_EMPTY_EN_SHIFT                            20
32356     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PCIE_IN_D3_EN                                    (0x1<<21) // 0 : PCIE in D3 is not part of Main Clock slowdown logic. 1 : PCIE in D3 is part of Main Clock slowdown logic.
32357     #define CPMU_REG_MAIN_CLK_SLOWDOWN_ENTRY_EN_MCS_PCIE_IN_D3_EN_SHIFT                              21
32358 #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN                                                           0x0302c4UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32359     #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_PCIE_L1_EXIT_EN                                   (0x1<<0) // 0 : PCIe L1 exit is not part of exit from main clock slowdown logic 1 : PCIe L1 exit is part of exit from main clock slowdown logic
32360     #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_PCIE_L1_EXIT_EN_SHIFT                             0
32361     #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_DORQ_EVENT_EN                                     (0x1<<1) // 0 : DORQ Event is not part of exit from main clock slowdown logic 1 : DORQ Event is part of exit from main clock slowdown logic
32362     #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_DORQ_EVENT_EN_SHIFT                               1
32363     #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_NCSI_EVENT_EN                                     (0x1<<2) // 0 : NCSI Event is not part of exit from main clock slowdown logic 1 : NCSI Event is part of exit from main clock slowdown logic
32364     #define CPMU_REG_MAIN_CLK_SLOWDOWN_EXIT_EN_MCS_NCSI_EVENT_EN_SHIFT                               2
32365 #define CPMU_REG_SW_FORCE_MAIN_CLK_SLOWDOWN                                                          0x0302c8UL //Access:RW   DataWidth:0x1   Setting this bit to "1" will allow software to force slowdown of main clock for the corresponding path.  Chips: BB_A0 BB_B0 K2
32366 #define CPMU_REG_SW_FORCE_MAIN_CLK_EXIT                                                              0x0302ccUL //Access:W    DataWidth:0x1   Setting this bit to "1" will allow software to provide an early indication to exit main clock slowdown.  Chips: BB_A0 BB_B0 K2
32367 #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN                                                         0x0302d0UL //Access:RW   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32368     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PBF_EMPTY_EN                                    (0x1<<0) // 0 : PBF Empty is not part of storm clock slowdown logic. 1 : PBF Empty is not part of storm clock slowdown logic.
32369     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PBF_EMPTY_EN_SHIFT                              0
32370     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_TX_EN                                  (0x1<<1) // 0 : QM Tx Empty is not part of storm clock slowdown generation logic. 1 : QM Tx Empty is part of storm clock slowdown generation logic.
32371     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_TX_EN_SHIFT                            1
32372     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_GLOBAL_EN                              (0x1<<2) // 0 : QM Global Empty is not part of storm clock slowdown generation logic. 1 : QM Global Empty is part of storm clock slowdown generation logic.
32373     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_QM_EMPTY_GLOBAL_EN_SHIFT                        2
32374     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_ALL_SQ_EMPTY_EN                                 (0x1<<3) // 0 : All Send Queue Empty is not part of Storm Clock slowdown logic. 1 : All Send Queue Empty is part of Storm Clock slowdown logic.
32375     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_ALL_SQ_EMPTY_EN_SHIFT                           3
32376     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MGMT_EMPTY_EN                                   (0x1<<4) // 0 : Management Traffic is not part of Storm Clock slowdown logic. 1 : Management Traffic is part of Storm Clock slowdown logic.
32377     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MGMT_EMPTY_EN_SHIFT                             4
32378     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_BRB_EMPTY_EN                                    (0x1<<5) // 0 : BRB empty is not part of Storm Clock slowdown logic. 1 : BRB empty is part of Storm Clock slowdown logic.
32379     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_BRB_EMPTY_EN_SHIFT                              5
32380     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PXP_EMPTY_EN                                    (0x1<<6) // 0 : PXP empty is not part of Storm Clock slowdown logic. 1 : PXP empty is part of Storm Clock slowdown logic.
32381     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PXP_EMPTY_EN_SHIFT                              6
32382     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_CAU_IDLE_EN                                     (0x1<<7) // 0 : CAU IDLE is not part of Storm Clock slowdown logic. 1 : CAU IDLE is part of Storm Clock slowdown logic.
32383     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_CAU_IDLE_EN_SHIFT                               7
32384     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TM_SCAN_EN                                      (0x1<<8) // 0 : Timer Scan status is not part of Storm Clock slowdown logic. 1 : Timer Scan status is part of Storm Clock slowdown logic.
32385     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TM_SCAN_EN_SHIFT                                8
32386     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_OBFF_STATE_EN                                   (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Storm Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Storm Clock slowdown logic.
32387     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_OBFF_STATE_EN_SHIFT                             9
32388     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TSEM_IDLE_EN                                    (0x1<<10) // 0 : TSEM IDLE is not part of Storm Clock slowdown logic. 1 : TSEM IDLE is part of Storm Clock slowdown logic.
32389     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_TSEM_IDLE_EN_SHIFT                              10
32390     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MSEM_IDLE_EN                                    (0x1<<11) // 0 : MSEM IDLE is not part of Storm Clock slowdown logic. 1 : MSEM IDLE is part of Storm Clock slowdown logic.
32391     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_MSEM_IDLE_EN_SHIFT                              11
32392     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_USEM_IDLE_EN                                    (0x1<<12) // 0 : USEM IDLE is not part of Storm Clock slowdown logic. 1 : USEM IDLE is part of Storm Clock slowdown logic.
32393     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_USEM_IDLE_EN_SHIFT                              12
32394     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_XSEM_IDLE_EN                                    (0x1<<13) // 0 : XSEM IDLE is not part of Storm Clock slowdown logic. 1 : XSEM IDLE is part of Storm Clock slowdown logic.
32395     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_XSEM_IDLE_EN_SHIFT                              13
32396     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_YSEM_IDLE_EN                                    (0x1<<14) // 0 : YSEM IDLE is not part of Storm Clock slowdown logic. 1 : YSEM IDLE is part of Storm Clock slowdown logic.
32397     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_YSEM_IDLE_EN_SHIFT                              14
32398     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PSEM_IDLE_EN                                    (0x1<<15) // 0 : PSEM IDLE is not part of Storm Clock slowdown logic. 1 : PSEM IDLE is part of Storm Clock slowdown logic.
32399     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PSEM_IDLE_EN_SHIFT                              15
32400     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_RX_LPI_STATUS_EN                                (0x1<<16) // 0 : LPI receive status is not part of Storm Clock slowdown logic. 1 : LPI receive status is part of Storm Clock slowdown logic.
32401     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_RX_LPI_STATUS_EN_SHIFT                          16
32402     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NW_LINKDOWN_EN                                  (0x1<<17) // 0 : Network Link Down is not part of Storm Clock slowdown logic. 1 : Network Link Down is part of Storm Clock slowdown logic.
32403     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NW_LINKDOWN_EN_SHIFT                            17
32404     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_RX_EMPTY_EN                                 (0x1<<18) // 0 : NIG Rx Empty is not part of Storm Clock slowdown logic. 1 : NIG Rx Empty is part of Storm Clock slowdown logic.
32405     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_RX_EMPTY_EN_SHIFT                           18
32406     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_TX_EMPTY_EN                                 (0x1<<19) // 0 : NIG Tx Empty is not part of Storm Clock slowdown logic. 1 : NIG Tx Empty is part of Storm Clock slowdown logic.
32407     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_TX_EMPTY_EN_SHIFT                           19
32408     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_LB_EMPTY_EN                                 (0x1<<20) // 0 : NIG Loopback Empty is not part of Storm Clock slowdown logic. 1 : NIG Loopback Empty is part of Storm Clock slowdown logic.
32409     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_NIG_LB_EMPTY_EN_SHIFT                           20
32410     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PCIE_IN_D3_EN                                   (0x1<<21) // 0 : PCIE in D3 is not part of Storm Clock slowdown logic. 1 : PCIE in D3 is part of Storm Clock slowdown logic.
32411     #define CPMU_REG_STORM_CLK_SLOWDOWN_ENTRY_EN_SCS_PCIE_IN_D3_EN_SHIFT                             21
32412 #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN                                                          0x0302d4UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32413     #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_PCIE_L1_EXIT_EN                                  (0x1<<0) // 0 : PCIe L1 exit is not part of exit from storm clock slowdown logic 1 : PCIe L1 exit is part of exit from storm clock slowdown logic
32414     #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_PCIE_L1_EXIT_EN_SHIFT                            0
32415     #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_DORQ_EVENT_EN                                    (0x1<<1) // 0 : DORQ Event is not part of exit from storm clock slowdown logic 1 : DORQ Event is part of exit from storm clock slowdown logic
32416     #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_DORQ_EVENT_EN_SHIFT                              1
32417     #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_NCSI_EVENT_EN                                    (0x1<<2) // 0 : NCSI Event is not part of exit from storm clock slowdown logic 1 : NCSI Event is part of exit from storm clock slowdown logic
32418     #define CPMU_REG_STORM_CLK_SLOWDOWN_EXIT_EN_SCS_NCSI_EVENT_EN_SHIFT                              2
32419 #define CPMU_REG_SW_FORCE_STORM_CLK_SLOWDOWN                                                         0x0302d8UL //Access:RW   DataWidth:0x1   Setting this bit to "1" will allow software to force slowdown of storm clock for the corresponding path.  Chips: BB_A0 BB_B0 K2
32420 #define CPMU_REG_SW_FORCE_STORM_CLK_EXIT                                                             0x0302dcUL //Access:W    DataWidth:0x1   Setting this bit to "1" will allow software to provide an early indication to exit storm clock slowdown.  Chips: BB_A0 BB_B0 K2
32421 #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN                                                            0x0302e0UL //Access:RW   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32422     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PBF_EMPTY_EN                                       (0x1<<0) // 0 : PBF Empty is not part of nw clock slowdown logic. 1 : PBF Empty is not part of nw clock slowdown logic.
32423     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PBF_EMPTY_EN_SHIFT                                 0
32424     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_TX_EN                                     (0x1<<1) // 0 : QM Tx Empty is not part of nw clock slowdown generation logic. 1 : QM Tx Empty is part of nw clock slowdown generation logic.
32425     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_TX_EN_SHIFT                               1
32426     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_GLOBAL_EN                                 (0x1<<2) // 0 : QM Global Empty is not part of nw clock slowdown generation logic. 1 : QM Global Empty is part of nw clock slowdown generation logic.
32427     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_QM_EMPTY_GLOBAL_EN_SHIFT                           2
32428     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_ALL_SQ_EMPTY_EN                                    (0x1<<3) // 0 : All Send Queue Empty is not part of Nw Clock slowdown logic. 1 : All Send Queue Empty is part of Nw Clock slowdown logic.
32429     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_ALL_SQ_EMPTY_EN_SHIFT                              3
32430     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MGMT_EMPTY_EN                                      (0x1<<4) // 0 : Management Traffic is not part of Nw Clock slowdown logic. 1 : Management Traffic is part of Nw Clock slowdown logic.
32431     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MGMT_EMPTY_EN_SHIFT                                4
32432     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_BRB_EMPTY_EN                                       (0x1<<5) // 0 : BRB empty is not part of Nw Clock slowdown logic. 1 : BRB empty is part of Nw Clock slowdown logic.
32433     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_BRB_EMPTY_EN_SHIFT                                 5
32434     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PXP_EMPTY_EN                                       (0x1<<6) // 0 : PXP empty is not part of Nw Clock slowdown logic. 1 : PXP empty is part of Nw Clock slowdown logic.
32435     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PXP_EMPTY_EN_SHIFT                                 6
32436     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_CAU_IDLE_EN                                        (0x1<<7) // 0 : CAU IDLE is not part of Nw Clock slowdown logic. 1 : CAU IDLE is part of Nw Clock slowdown logic.
32437     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_CAU_IDLE_EN_SHIFT                                  7
32438     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TM_SCAN_EN                                         (0x1<<8) // 0 : Timer Scan status is not part of Nw Clock slowdown logic. 1 : Timer Scan status is part of Nw Clock slowdown logic.
32439     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TM_SCAN_EN_SHIFT                                   8
32440     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_OBFF_STATE_EN                                      (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of Nw Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of Nw Clock slowdown logic.
32441     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_OBFF_STATE_EN_SHIFT                                9
32442     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TSEM_IDLE_EN                                       (0x1<<10) // 0 : TSEM IDLE is not part of Nw Clock slowdown logic. 1 : TSEM IDLE is part of Nw Clock slowdown logic.
32443     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_TSEM_IDLE_EN_SHIFT                                 10
32444     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MSEM_IDLE_EN                                       (0x1<<11) // 0 : MSEM IDLE is not part of Nw Clock slowdown logic. 1 : MSEM IDLE is part of Nw Clock slowdown logic.
32445     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_MSEM_IDLE_EN_SHIFT                                 11
32446     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_USEM_IDLE_EN                                       (0x1<<12) // 0 : USEM IDLE is not part of Nw Clock slowdown logic. 1 : USEM IDLE is part of Nw Clock slowdown logic.
32447     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_USEM_IDLE_EN_SHIFT                                 12
32448     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_XSEM_IDLE_EN                                       (0x1<<13) // 0 : XSEM IDLE is not part of Nw Clock slowdown logic. 1 : XSEM IDLE is part of Nw Clock slowdown logic.
32449     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_XSEM_IDLE_EN_SHIFT                                 13
32450     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_YSEM_IDLE_EN                                       (0x1<<14) // 0 : YSEM IDLE is not part of Nw Clock slowdown logic. 1 : YSEM IDLE is part of Nw Clock slowdown logic.
32451     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_YSEM_IDLE_EN_SHIFT                                 14
32452     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PSEM_IDLE_EN                                       (0x1<<15) // 0 : PSEM IDLE is not part of Nw Clock slowdown logic. 1 : PSEM IDLE is part of Nw Clock slowdown logic.
32453     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PSEM_IDLE_EN_SHIFT                                 15
32454     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_RX_LPI_STATUS_EN                                   (0x1<<16) // 0 : LPI receive status is not part of Nw Clock slowdown logic. 1 : LPI receive status is part of Nw Clock slowdown logic.
32455     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_RX_LPI_STATUS_EN_SHIFT                             16
32456     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NW_LINKDOWN_EN                                     (0x1<<17) // 0 : Network Link Down is not part of Nw Clock slowdown logic. 1 : Network Link Down is part of Nw Clock slowdown logic.
32457     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NW_LINKDOWN_EN_SHIFT                               17
32458     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_RX_EMPTY_EN                                    (0x1<<18) // 0 : NIG Rx Empty is not part of Nw Clock slowdown logic. 1 : NIG Rx Empty is part of Nw Clock slowdown logic.
32459     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_RX_EMPTY_EN_SHIFT                              18
32460     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_TX_EMPTY_EN                                    (0x1<<19) // 0 : NIG Tx Empty is not part of Nw Clock slowdown logic. 1 : NIG Tx Empty is part of Nw Clock slowdown logic.
32461     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_TX_EMPTY_EN_SHIFT                              19
32462     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_LB_EMPTY_EN                                    (0x1<<20) // 0 : NIG Loopback Empty is not part of Nw Clock slowdown logic. 1 : NIG Loopback Empty is part of Nw Clock slowdown logic.
32463     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_NIG_LB_EMPTY_EN_SHIFT                              20
32464     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PCIE_IN_D3_EN                                      (0x1<<21) // 0 : PCIE in D3 is not part of NW Clock slowdown logic. 1 : PCIE in D3 is part of NW Clock slowdown logic.
32465     #define CPMU_REG_NW_CLK_SLOWDOWN_ENTRY_EN_NCS_PCIE_IN_D3_EN_SHIFT                                21
32466 #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN                                                             0x0302e4UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32467     #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_PCIE_L1_EXIT_EN                                     (0x1<<0) // 0 : PCIe L1 exit is not part of exit from nw clock slowdown logic 1 : PCIe L1 exit is part of exit from nw clock slowdown logic
32468     #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_PCIE_L1_EXIT_EN_SHIFT                               0
32469     #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_DORQ_EVENT_EN                                       (0x1<<1) // 0 : DORQ Event is not part of exit from nw clock slowdown logic 1 : DORQ Event is part of exit from nw clock slowdown logic
32470     #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_DORQ_EVENT_EN_SHIFT                                 1
32471     #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_NCSI_EVENT_EN                                       (0x1<<2) // 0 : NCSI Event is not part of exit from nw clock slowdown logic 1 : NCSI Event is part of exit from nw clock slowdown logic
32472     #define CPMU_REG_NW_CLK_SLOWDOWN_EXIT_EN_NCS_NCSI_EVENT_EN_SHIFT                                 2
32473 #define CPMU_REG_SW_FORCE_NW_CLK_SLOWDOWN                                                            0x0302e8UL //Access:RW   DataWidth:0x1   Setting this bit to "1" will allow software to force slowdown of nw clock for the corresponding path.  Chips: BB_A0 BB_B0 K2
32474 #define CPMU_REG_SW_FORCE_NW_CLK_EXIT                                                                0x0302ecUL //Access:W    DataWidth:0x1   Setting this bit to "1" will allow software to provide an early indication to exit nw clock slowdown.  Chips: BB_A0 BB_B0 K2
32475 #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN                                                           0x0302f0UL //Access:RW   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32476     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PBF_EMPTY_EN                                      (0x1<<0) // 0 : PBF Empty is not part of pci clock slowdown logic. 1 : PBF Empty is not part of pci clock slowdown logic.
32477     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PBF_EMPTY_EN_SHIFT                                0
32478     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_TX_EN                                    (0x1<<1) // 0 : QM Tx Empty is not part of pci clock slowdown generation logic. 1 : QM Tx Empty is part of pci clock slowdown generation logic.
32479     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_TX_EN_SHIFT                              1
32480     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_GLOBAL_EN                                (0x1<<2) // 0 : QM Global Empty is not part of pci clock slowdown generation logic. 1 : QM Global Empty is part of pci clock slowdown generation logic.
32481     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_QM_EMPTY_GLOBAL_EN_SHIFT                          2
32482     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_ALL_SQ_EMPTY_EN                                   (0x1<<3) // 0 : All Send Queue Empty is not part of PCI Clock slowdown logic. 1 : All Send Queue Empty is part of PCI Clock slowdown logic.
32483     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_ALL_SQ_EMPTY_EN_SHIFT                             3
32484     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MGMT_EMPTY_EN                                     (0x1<<4) // 0 : Management Traffic is not part of PCI Clock slowdown logic. 1 : Management Traffic is part of PCI Clock slowdown logic.
32485     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MGMT_EMPTY_EN_SHIFT                               4
32486     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_BRB_EMPTY_EN                                      (0x1<<5) // 0 : BRB empty is not part of PCI Clock slowdown logic. 1 : BRB empty is part of PCI Clock slowdown logic.
32487     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_BRB_EMPTY_EN_SHIFT                                5
32488     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PXP_EMPTY_EN                                      (0x1<<6) // 0 : PXP empty is not part of PCI Clock slowdown logic. 1 : PXP empty is part of PCI Clock slowdown logic.
32489     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PXP_EMPTY_EN_SHIFT                                6
32490     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_CAU_IDLE_EN                                       (0x1<<7) // 0 : CAU IDLE is not part of PCI Clock slowdown logic. 1 : CAU IDLE is part of PCI Clock slowdown logic.
32491     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_CAU_IDLE_EN_SHIFT                                 7
32492     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TM_SCAN_EN                                        (0x1<<8) // 0 : Timer Scan status is not part of PCI Clock slowdown logic. 1 : Timer Scan status is part of PCI Clock slowdown logic.
32493     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TM_SCAN_EN_SHIFT                                  8
32494     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_OBFF_STATE_EN                                     (0x1<<9) // 0 : OBFF State (non CPU_ACTIVE) is not part of PCI Clock slowdown logic. 1 : OBFF State (non CPU_ACTIVE) is part of PCI Clock slowdown logic.
32495     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_OBFF_STATE_EN_SHIFT                               9
32496     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TSEM_IDLE_EN                                      (0x1<<10) // 0 : TSEM IDLE is not part of PCI Clock slowdown logic. 1 : TSEM IDLE is part of PCI Clock slowdown logic.
32497     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_TSEM_IDLE_EN_SHIFT                                10
32498     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MSEM_IDLE_EN                                      (0x1<<11) // 0 : MSEM IDLE is not part of PCI Clock slowdown logic. 1 : MSEM IDLE is part of PCI Clock slowdown logic.
32499     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_MSEM_IDLE_EN_SHIFT                                11
32500     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_USEM_IDLE_EN                                      (0x1<<12) // 0 : USEM IDLE is not part of PCI Clock slowdown logic. 1 : USEM IDLE is part of PCI Clock slowdown logic.
32501     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_USEM_IDLE_EN_SHIFT                                12
32502     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_XSEM_IDLE_EN                                      (0x1<<13) // 0 : XSEM IDLE is not part of PCI Clock slowdown logic. 1 : XSEM IDLE is part of PCI Clock slowdown logic.
32503     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_XSEM_IDLE_EN_SHIFT                                13
32504     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_YSEM_IDLE_EN                                      (0x1<<14) // 0 : YSEM IDLE is not part of PCI Clock slowdown logic. 1 : YSEM IDLE is part of PCI Clock slowdown logic.
32505     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_YSEM_IDLE_EN_SHIFT                                14
32506     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PSEM_IDLE_EN                                      (0x1<<15) // 0 : PSEM IDLE is not part of PCI Clock slowdown logic. 1 : PSEM IDLE is part of PCI Clock slowdown logic.
32507     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PSEM_IDLE_EN_SHIFT                                15
32508     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_RX_LPI_STATUS_EN                                  (0x1<<16) // 0 : LPI receive status is not part of PCI Clock slowdown logic. 1 : LPI receive status is part of PCI Clock slowdown logic.
32509     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_RX_LPI_STATUS_EN_SHIFT                            16
32510     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NW_LINKDOWN_EN                                    (0x1<<17) // 0 : Network Link Down is not part of PCI Clock slowdown logic. 1 : Network Link Down is part of PCI Clock slowdown logic.
32511     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NW_LINKDOWN_EN_SHIFT                              17
32512     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_RX_EMPTY_EN                                   (0x1<<18) // 0 : NIG Rx Empty is not part of PCI Clock slowdown logic. 1 : NIG Rx Empty is part of PCI Clock slowdown logic.
32513     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_RX_EMPTY_EN_SHIFT                             18
32514     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_TX_EMPTY_EN                                   (0x1<<19) // 0 : NIG Tx Empty is not part of PCI Clock slowdown logic. 1 : NIG Tx Empty is part of PCI Clock slowdown logic.
32515     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_TX_EMPTY_EN_SHIFT                             19
32516     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_LB_EMPTY_EN                                   (0x1<<20) // 0 : NIG Loopback Empty is not part of PCI Clock slowdown logic. 1 : NIG Loopback Empty is part of PCI Clock slowdown logic.
32517     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_NIG_LB_EMPTY_EN_SHIFT                             20
32518     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PCIE_IN_D3_EN                                     (0x1<<21) // 0 : PCIE in D3 is not part of PCI Clock slowdown logic. 1 : PCIE in D3 is part of PCI Clock slowdown logic.
32519     #define CPMU_REG_PCI_CLK_SLOWDOWN_ENTRY_EN_PCS_PCIE_IN_D3_EN_SHIFT                               21
32520 #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN                                                            0x0302f4UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32521     #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_PCIE_L1_EXIT_EN                                    (0x1<<0) // 0 : PCIe L1 exit is not part of exit from pci clock slowdown logic 1 : PCIe L1 exit is part of exit from pci clock slowdown logic
32522     #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_PCIE_L1_EXIT_EN_SHIFT                              0
32523     #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_DORQ_EVENT_EN                                      (0x1<<1) // 0 : DORQ Event is not part of exit from pci clock slowdown logic 1 : DORQ Event is part of exit from pci clock slowdown logic
32524     #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_DORQ_EVENT_EN_SHIFT                                1
32525     #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_NCSI_EVENT_EN                                      (0x1<<2) // 0 : NCSI Event is not part of exit from pci clock slowdown logic 1 : NCSI Event is part of exit from pci clock slowdown logic
32526     #define CPMU_REG_PCI_CLK_SLOWDOWN_EXIT_EN_PCS_NCSI_EVENT_EN_SHIFT                                2
32527 #define CPMU_REG_SW_FORCE_PCI_CLK_SLOWDOWN                                                           0x0302f8UL //Access:RW   DataWidth:0x1   Setting this bit to "1" will allow software to force slowdown of pci clock for the corresponding path.  Chips: BB_A0 BB_B0 K2
32528 #define CPMU_REG_SW_FORCE_PCI_CLK_EXIT                                                               0x0302fcUL //Access:W    DataWidth:0x1   Setting this bit to "1" will allow software to provide an early indication to exit pci clock slowdown.  Chips: BB_A0 BB_B0 K2
32529 #define CPMU_REG_PXP_VQ_EMPTY_STATUS_E0_0                                                            0x030300UL //Access:R    DataWidth:0x20  First 32bits of VQ empty for Engine 0  Chips: BB_A0 BB_B0 K2
32530 #define CPMU_REG_PXP_VQ_EMPTY_STATUS_E0_1                                                            0x030304UL //Access:R    DataWidth:0x2   Bits [33:32] of VQ empty for engine 0  Chips: BB_A0 BB_B0 K2
32531 #define CPMU_REG_PXP_VQ_EMPTY_STATUS_E1_0                                                            0x030308UL //Access:R    DataWidth:0x20  First 32bits of VQ empty for Engine 1  Chips: BB_A0 BB_B0 K2
32532 #define CPMU_REG_PXP_VQ_EMPTY_STATUS_E1_1                                                            0x03030cUL //Access:R    DataWidth:0x2   Bits [33:32] of VQ empty for engine 1  Chips: BB_A0 BB_B0 K2
32533 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0                                                             0x030310UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32534     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_ABOVE_THRESHOLD_PORT_ISIG_STATUS                    (0xf<<0) // Current status of bmb_above_threshold_port
32535     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_ABOVE_THRESHOLD_PORT_ISIG_STATUS_SHIFT              0
32536     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PATH_EMPTY_ISIG_STATUS                              (0x1<<4) // Current status of bmb_path_empty
32537     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PATH_EMPTY_ISIG_STATUS_SHIFT                        4
32538     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PORT_EMPTY_ISIG_STATUS                              (0xf<<5) // Current status of bmb_port_empty
32539     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BMB_PORT_EMPTY_ISIG_STATUS_SHIFT                        5
32540     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_ABOVE_THRESHOLD_PATH_E0_ISIG_STATUS                 (0x3<<9) // Current status of brb_above_threshold_path_e0
32541     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_ABOVE_THRESHOLD_PATH_E0_ISIG_STATUS_SHIFT           9
32542     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_ABOVE_THRESHOLD_PATH_E1_ISIG_STATUS                 (0x3<<11) // Current status of brb_above_threshold_path_e1
32543     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_ABOVE_THRESHOLD_PATH_E1_ISIG_STATUS_SHIFT           11
32544     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E0_ISIG_STATUS                           (0x1<<13) // Current status of brb_path_empty_e0
32545     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E0_ISIG_STATUS_SHIFT                     13
32546     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E1_ISIG_STATUS                           (0x1<<14) // Current status of brb_path_empty_e1
32547     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BRB_PATH_EMPTY_E1_ISIG_STATUS_SHIFT                     14
32548     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_PBF_ABOVE_THRESHOLD_PORT_E0_ISIG_STATUS                 (0x3<<15) // Current status of pbf_above_threshold_port_e0
32549     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_PBF_ABOVE_THRESHOLD_PORT_E0_ISIG_STATUS_SHIFT           15
32550     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_PBF_ABOVE_THRESHOLD_PORT_E1_ISIG_STATUS                 (0x3<<17) // Current status of pbf_above_threshold_port_e1
32551     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_PBF_ABOVE_THRESHOLD_PORT_E1_ISIG_STATUS_SHIFT           17
32552     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E0_ISIG_STATUS                           (0x1<<19) // Current status of btb_path_empty_e0
32553     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E0_ISIG_STATUS_SHIFT                     19
32554     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E1_ISIG_STATUS                           (0x1<<20) // Current status of btb_path_empty_e1
32555     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PATH_EMPTY_E1_ISIG_STATUS_SHIFT                     20
32556     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PORT_EMPTY_E0_ISIG_STATUS                           (0x3<<21) // Current status of btb_port_empty_e0
32557     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PORT_EMPTY_E0_ISIG_STATUS_SHIFT                     21
32558     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PORT_EMPTY_E1_ISIG_STATUS                           (0x3<<23) // Current status of btb_port_empty_e1
32559     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_BTB_PORT_EMPTY_E1_ISIG_STATUS_SHIFT                     23
32560     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E0_ISIG_STATUS                            (0x1<<25) // Current status of cau_path_idle_e0
32561     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E0_ISIG_STATUS_SHIFT                      25
32562     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E1_ISIG_STATUS                            (0x1<<26) // Current status of cau_path_idle_e1
32563     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CAU_PATH_IDLE_E1_ISIG_STATUS_SHIFT                      26
32564     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E0_ISIG_STATUS                        (0x1<<27) // Current status of cnig_link_down_p0_e0
32565     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E0_ISIG_STATUS_SHIFT                  27
32566     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E1_ISIG_STATUS                        (0x1<<28) // Current status of cnig_link_down_p0_e1
32567     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P0_E1_ISIG_STATUS_SHIFT                  28
32568     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E0_ISIG_STATUS                        (0x1<<29) // Current status of cnig_link_down_p1_e0
32569     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E0_ISIG_STATUS_SHIFT                  29
32570     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E1_ISIG_STATUS                        (0x1<<30) // Current status of cnig_link_down_p1_e1
32571     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_LINK_DOWN_P1_E1_ISIG_STATUS_SHIFT                  30
32572     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_RX_LPI_P0_E0_ISIG_STATUS                           (0x1<<31) // Current status of cnig_rx_lpi_p0_e0
32573     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_0_CNIG_RX_LPI_P0_E0_ISIG_STATUS_SHIFT                     31
32574 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1                                                             0x030314UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32575     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P0_E1_ISIG_STATUS                           (0x1<<0) // Current status of cnig_rx_lpi_p0_e1
32576     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P0_E1_ISIG_STATUS_SHIFT                     0
32577     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E0_ISIG_STATUS                           (0x1<<1) // Current status of cnig_rx_lpi_p1_e0
32578     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E0_ISIG_STATUS_SHIFT                     1
32579     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E1_ISIG_STATUS                           (0x1<<2) // Current status of cnig_rx_lpi_p1_e1
32580     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_CNIG_RX_LPI_P1_E1_ISIG_STATUS_SHIFT                     2
32581     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E0_ISIG_STATUS                           (0x3<<3) // Current status of dorq_tx_wakeup_e0
32582     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E0_ISIG_STATUS_SHIFT                     3
32583     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E1_ISIG_STATUS                           (0x3<<5) // Current status of dorq_tx_wakeup_e1
32584     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_DORQ_TX_WAKEUP_E1_ISIG_STATUS_SHIFT                     5
32585     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E0_ISIG_STATUS                            (0x1<<7) // Current status of msem_sem_idle_e0
32586     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                      7
32587     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E1_ISIG_STATUS                            (0x1<<8) // Current status of msem_sem_idle_e1
32588     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_MSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                      8
32589     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NCSI_RX_EVENT_ISIG_STATUS                               (0x1<<9) // Current status of ncsi_rx_event
32590     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NCSI_RX_EVENT_ISIG_STATUS_SHIFT                         9
32591     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E0_ISIG_STATUS                          (0x1<<10) // Current status of nig_lb_empty_p0_e0
32592     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E0_ISIG_STATUS_SHIFT                    10
32593     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E1_ISIG_STATUS                          (0x1<<11) // Current status of nig_lb_empty_p0_e1
32594     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P0_E1_ISIG_STATUS_SHIFT                    11
32595     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E0_ISIG_STATUS                          (0x1<<12) // Current status of nig_lb_empty_p1_e0
32596     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E0_ISIG_STATUS_SHIFT                    12
32597     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E1_ISIG_STATUS                          (0x1<<13) // Current status of nig_lb_empty_p1_e1
32598     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_LB_EMPTY_P1_E1_ISIG_STATUS_SHIFT                    13
32599     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E0_ISIG_STATUS                          (0x1<<14) // Current status of nig_rx_empty_p0_e0
32600     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E0_ISIG_STATUS_SHIFT                    14
32601     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E1_ISIG_STATUS                          (0x1<<15) // Current status of nig_rx_empty_p0_e1
32602     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P0_E1_ISIG_STATUS_SHIFT                    15
32603     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E0_ISIG_STATUS                          (0x1<<16) // Current status of nig_rx_empty_p1_e0
32604     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E0_ISIG_STATUS_SHIFT                    16
32605     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E1_ISIG_STATUS                          (0x1<<17) // Current status of nig_rx_empty_p1_e1
32606     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_RX_EMPTY_P1_E1_ISIG_STATUS_SHIFT                    17
32607     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E0_ISIG_STATUS                          (0x1<<18) // Current status of nig_tx_empty_p0_e0
32608     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E0_ISIG_STATUS_SHIFT                    18
32609     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E1_ISIG_STATUS                          (0x1<<19) // Current status of nig_tx_empty_p0_e1
32610     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P0_E1_ISIG_STATUS_SHIFT                    19
32611     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E0_ISIG_STATUS                          (0x1<<20) // Current status of nig_tx_empty_p1_e0
32612     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E0_ISIG_STATUS_SHIFT                    20
32613     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E1_ISIG_STATUS                          (0x1<<21) // Current status of nig_tx_empty_p1_e1
32614     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_NIG_TX_EMPTY_P1_E1_ISIG_STATUS_SHIFT                    21
32615     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E0_ISIG_STATUS                           (0x1<<22) // Current status of pbf_path_empty_e0
32616     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E0_ISIG_STATUS_SHIFT                     22
32617     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E1_ISIG_STATUS                           (0x1<<23) // Current status of pbf_path_empty_e1
32618     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PATH_EMPTY_E1_ISIG_STATUS_SHIFT                     23
32619     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PORT_EMPTY_E0_ISIG_STATUS                           (0xf<<24) // Current status of pbf_port_empty_e0
32620     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PORT_EMPTY_E0_ISIG_STATUS_SHIFT                     24
32621     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PORT_EMPTY_E1_ISIG_STATUS                           (0xf<<28) // Current status of pbf_port_empty_e1
32622     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_1_PBF_PORT_EMPTY_E1_ISIG_STATUS_SHIFT                     28
32623 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2                                                             0x030318UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32624     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E0_ISIG_STATUS                       (0x1<<0) // Current status of pglue_int_deassert_e0
32625     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E0_ISIG_STATUS_SHIFT                 0
32626     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E1_ISIG_STATUS                       (0x1<<1) // Current status of pglue_int_deassert_e1
32627     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_INT_DEASSERT_E1_ISIG_STATUS_SHIFT                 1
32628     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_OBFF_STATE_ISIG_STATUS                            (0xf<<2) // Current status of pglue_obff_state
32629     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_OBFF_STATE_ISIG_STATUS_SHIFT                      2
32630     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E0_ISIG_STATUS                         (0x1<<6) // Current status of pglue_path_in_d3_e0
32631     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E0_ISIG_STATUS_SHIFT                   6
32632     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E1_ISIG_STATUS                         (0x1<<7) // Current status of pglue_path_in_d3_e1
32633     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PATH_IN_D3_E1_ISIG_STATUS_SHIFT                   7
32634     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PGL_EMPTY_ISIG_STATUS                             (0x1<<8) // Current status of pglue_pgl_empty
32635     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PGLUE_PGL_EMPTY_ISIG_STATUS_SHIFT                       8
32636     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E0_ISIG_STATUS                            (0x1<<9) // Current status of psem_sem_idle_e0
32637     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                      9
32638     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E1_ISIG_STATUS                            (0x1<<10) // Current status of psem_sem_idle_e1
32639     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                      10
32640     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E0_ISIG_STATUS                    (0x1<<11) // Current status of pxp_master_path_empty_e0
32641     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E0_ISIG_STATUS_SHIFT              11
32642     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E1_ISIG_STATUS                    (0x1<<12) // Current status of pxp_master_path_empty_e1
32643     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_MASTER_PATH_EMPTY_E1_ISIG_STATUS_SHIFT              12
32644     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E0_ISIG_STATUS                    (0x1<<13) // Current status of pxp_target_path_empty_e0
32645     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E0_ISIG_STATUS_SHIFT              13
32646     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E1_ISIG_STATUS                    (0x1<<14) // Current status of pxp_target_path_empty_e1
32647     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_PXP_TARGET_PATH_EMPTY_E1_ISIG_STATUS_SHIFT              14
32648     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E0_ISIG_STATUS                          (0x1<<15) // Current status of qm_global_empty_e0
32649     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E0_ISIG_STATUS_SHIFT                    15
32650     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E1_ISIG_STATUS                          (0x1<<16) // Current status of qm_global_empty_e1
32651     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_GLOBAL_EMPTY_E1_ISIG_STATUS_SHIFT                    16
32652     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_PORT_EMPTY_E0_ISIG_STATUS                            (0xf<<17) // Current status of qm_port_empty_e0
32653     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_PORT_EMPTY_E0_ISIG_STATUS_SHIFT                      17
32654     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_PORT_EMPTY_E1_ISIG_STATUS                            (0xf<<21) // Current status of qm_port_empty_e1
32655     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_PORT_EMPTY_E1_ISIG_STATUS_SHIFT                      21
32656     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E0_ISIG_STATUS                              (0x1<<25) // Current status of qm_tx_empty_e0
32657     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E0_ISIG_STATUS_SHIFT                        25
32658     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E1_ISIG_STATUS                              (0x1<<26) // Current status of qm_tx_empty_e1
32659     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_QM_TX_EMPTY_E1_ISIG_STATUS_SHIFT                        26
32660     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E0_ISIG_STATUS                           (0x1<<27) // Current status of tm_during_scan_e0
32661     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E0_ISIG_STATUS_SHIFT                     27
32662     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E1_ISIG_STATUS                           (0x1<<28) // Current status of tm_during_scan_e1
32663     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TM_DURING_SCAN_E1_ISIG_STATUS_SHIFT                     28
32664     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E0_ISIG_STATUS                            (0x1<<29) // Current status of tsem_sem_idle_e0
32665     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                      29
32666     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E1_ISIG_STATUS                            (0x1<<30) // Current status of tsem_sem_idle_e1
32667     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_TSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                      30
32668     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_USEM_SEM_IDLE_E0_ISIG_STATUS                            (0x1<<31) // Current status of usem_sem_idle_e0
32669     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_2_USEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                      31
32670 #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3                                                             0x03031cUL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32671     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_USEM_SEM_IDLE_E1_ISIG_STATUS                            (0x1<<0) // Current status of usem_sem_idle_e1
32672     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_USEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                      0
32673     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E0_ISIG_STATUS                            (0x1<<1) // Current status of xsem_sem_idle_e0
32674     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                      1
32675     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E1_ISIG_STATUS                            (0x1<<2) // Current status of xsem_sem_idle_e1
32676     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_XSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                      2
32677     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E0_ISIG_STATUS                            (0x1<<3) // Current status of ysem_sem_idle_e0
32678     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E0_ISIG_STATUS_SHIFT                      3
32679     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E1_ISIG_STATUS                            (0x1<<4) // Current status of ysem_sem_idle_e1
32680     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_YSEM_SEM_IDLE_E1_ISIG_STATUS_SHIFT                      4
32681     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_PCIE_LINK_IN_L1_ISIG_STATUS                             (0x1<<5) // Current status of pcie_link_in_l1
32682     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_PCIE_LINK_IN_L1_ISIG_STATUS_SHIFT                       5
32683     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E0_ISIG_STATUS           (0x1<<6) // Current status of igu_cpmu_eee_pending_interrupt_e0
32684     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E0_ISIG_STATUS_SHIFT     6
32685     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E1_ISIG_STATUS           (0x1<<7) // Current status of igu_cpmu_eee_pending_interrupt_e1
32686     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_IGU_CPMU_EEE_PENDING_INTERRUPT_E1_ISIG_STATUS_SHIFT     7
32687     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P2_E0_ISIG_STATUS                          (0x1<<8) // Current status of nig_tx_empty_p2_e0
32688     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P2_E0_ISIG_STATUS_SHIFT                    8
32689     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P3_E0_ISIG_STATUS                          (0x1<<9) // Current status of nig_tx_empty_p3_e0
32690     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_TX_EMPTY_P3_E0_ISIG_STATUS_SHIFT                    9
32691     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P2_E0_ISIG_STATUS                          (0x1<<10) // Current status of nig_rx_empty_p2_e0
32692     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P2_E0_ISIG_STATUS_SHIFT                    10
32693     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P3_E0_ISIG_STATUS                          (0x1<<11) // Current status of nig_rx_empty_p3_e0
32694     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_RX_EMPTY_P3_E0_ISIG_STATUS_SHIFT                    11
32695     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P2_E0_ISIG_STATUS                          (0x1<<12) // Current status of nig_lb_empty_p2_e0
32696     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P2_E0_ISIG_STATUS_SHIFT                    12
32697     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P3_E0_ISIG_STATUS                          (0x1<<13) // Current status of nig_lb_empty_p3_e0
32698     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_NIG_LB_EMPTY_P3_E0_ISIG_STATUS_SHIFT                    13
32699     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P2_E0_ISIG_STATUS                        (0x1<<14) // Current status of cnig_link_down_p2_e0
32700     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P2_E0_ISIG_STATUS_SHIFT                  14
32701     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P3_E0_ISIG_STATUS                        (0x1<<15) // Current status of cnig_link_down_p3_e0
32702     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_LINK_DOWN_P3_E0_ISIG_STATUS_SHIFT                  15
32703     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P2_E0_ISIG_STATUS                           (0x1<<16) // Current status of cnig_rx_lpi_p2_e0
32704     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P2_E0_ISIG_STATUS_SHIFT                     16
32705     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P3_E0_ISIG_STATUS                           (0x1<<17) // Current status of cnig_rx_lpi_p3_e0
32706     #define CPMU_REG_CPMU_INPUT_SIG_STATUS_3_CNIG_RX_LPI_P3_E0_ISIG_STATUS_SHIFT                     17
32707 #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS                                                              0x030320UL //Access:R    DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
32708     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E0_OSIG_STATUS                           (0x1<<0) // Current status of cnig_lpi_req_p0_e0
32709     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E0_OSIG_STATUS_SHIFT                     0
32710     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E1_OSIG_STATUS                           (0x1<<1) // Current status of cnig_lpi_req_p0_e1
32711     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P0_E1_OSIG_STATUS_SHIFT                     1
32712     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E0_OSIG_STATUS                           (0x1<<2) // Current status of cnig_lpi_req_p1_e0
32713     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E0_OSIG_STATUS_SHIFT                     2
32714     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E1_OSIG_STATUS                           (0x1<<3) // Current status of cnig_lpi_req_p1_e1
32715     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P1_E1_OSIG_STATUS_SHIFT                     3
32716     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_CMN_OSIG_STATUS                (0x1<<4) // Current status of erstclk_main_clk_slowdown_cmn
32717     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_CMN_OSIG_STATUS_SHIFT          4
32718     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E0_OSIG_STATUS                 (0x1<<5) // Current status of erstclk_main_clk_slowdown_e0
32719     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT           5
32720     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E1_OSIG_STATUS                 (0x1<<6) // Current status of erstclk_main_clk_slowdown_e1
32721     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_MAIN_CLK_SLOWDOWN_E1_OSIG_STATUS_SHIFT           6
32722     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_CMN_OSIG_STATUS                  (0x1<<7) // Current status of erstclk_nw_clk_slowdown_cmn
32723     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_CMN_OSIG_STATUS_SHIFT            7
32724     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E0_OSIG_STATUS                   (0x1<<8) // Current status of erstclk_nw_clk_slowdown_e0
32725     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT             8
32726     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E1_OSIG_STATUS                   (0x1<<9) // Current status of erstclk_nw_clk_slowdown_e1
32727     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_NW_CLK_SLOWDOWN_E1_OSIG_STATUS_SHIFT             9
32728     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_CMN_OSIG_STATUS                 (0x1<<10) // Current status of erstclk_pci_clk_slowdown_cmn
32729     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_CMN_OSIG_STATUS_SHIFT           10
32730     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E0_OSIG_STATUS                  (0x1<<11) // Current status of erstclk_pci_clk_slowdown_e0
32731     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT            11
32732     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E1_OSIG_STATUS                  (0x1<<12) // Current status of erstclk_pci_clk_slowdown_e1
32733     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_PCI_CLK_SLOWDOWN_E1_OSIG_STATUS_SHIFT            12
32734     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E0_OSIG_STATUS                (0x1<<13) // Current status of erstclk_storm_clk_slowdown_e0
32735     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E0_OSIG_STATUS_SHIFT          13
32736     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E1_OSIG_STATUS                (0x1<<14) // Current status of erstclk_storm_clk_slowdown_e1
32737     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_ERSTCLK_STORM_CLK_SLOWDOWN_E1_OSIG_STATUS_SHIFT          14
32738     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E0_OSIG_STATUS                             (0x1<<15) // Current status of igu_stall_int_e0
32739     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E0_OSIG_STATUS_SHIFT                       15
32740     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E1_OSIG_STATUS                             (0x1<<16) // Current status of igu_stall_int_e1
32741     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_IGU_STALL_INT_E1_OSIG_STATUS_SHIFT                       16
32742     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PCIE_EARLY_L1_EXIT_OSIG_STATUS                           (0x1<<17) // Current status of pcie_early_l1_exit
32743     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PCIE_EARLY_L1_EXIT_OSIG_STATUS_SHIFT                     17
32744     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PGLUE_SEND_LTR2_OSIG_STATUS                              (0x1<<18) // Current status of pglue_send_ltr2
32745     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PGLUE_SEND_LTR2_OSIG_STATUS_SHIFT                        18
32746     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E0_OSIG_STATUS                             (0x1<<19) // Current status of pxp_stall_mem_e0
32747     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E0_OSIG_STATUS_SHIFT                       19
32748     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E1_OSIG_STATUS                             (0x1<<20) // Current status of pxp_stall_mem_e1
32749     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_PXP_STALL_MEM_E1_OSIG_STATUS_SHIFT                       20
32750     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P2_E0_OSIG_STATUS                           (0x1<<21) // Current status of cnig_lpi_req_p2_e0
32751     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P2_E0_OSIG_STATUS_SHIFT                     21
32752     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P3_E0_OSIG_STATUS                           (0x1<<22) // Current status of cnig_lpi_req_p3_e0
32753     #define CPMU_REG_CPMU_OUTPUT_SIG_STATUS_CNIG_LPI_REQ_P3_E0_OSIG_STATUS_SHIFT                     22
32754 #define CPMU_REG_LPI_TX_REQ_STAT_RO                                                                  0x030324UL //Access:R    DataWidth:0x20  Event Counter: Counts number of times the device has gone into LPI.  Chips: BB_A0 BB_B0 K2
32755 #define CPMU_REG_LPI_TX_DURATION_STAT_RO                                                             0x030328UL //Access:R    DataWidth:0x20  Duration Counter: Counts number of ticks the device was in LPI state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32756 #define CPMU_REG_LPI_RX_REQ_STAT_RO                                                                  0x03032cUL //Access:R    DataWidth:0x20  Event Counter: Counts number of times a Rx LPI was received.  Chips: BB_A0 BB_B0 K2
32757 #define CPMU_REG_LPI_RX_DURATION_STAT_RO                                                             0x030330UL //Access:R    DataWidth:0x20  Duration Counter: Counts number of ticks the device was in RX LPI state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32758 #define CPMU_REG_LPI_REQ_STAT_RO                                                                     0x030334UL //Access:R    DataWidth:0x20  Event Counter: Counts number of times both sides went into LPI state.  Chips: BB_A0 BB_B0 K2
32759 #define CPMU_REG_LPI_DURATION_STAT_RO                                                                0x030338UL //Access:R    DataWidth:0x20  Duration Counter: Counts number of ticks the device was in LPI state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32760 #define CPMU_REG_OBFF_STALL_MEM_STAT_RO                                                              0x03033cUL //Access:R    DataWidth:0x20  Event Counter: Counts number of times the Stall Memory was asserted for OBFF.  Chips: BB_A0 BB_B0 K2
32761 #define CPMU_REG_OBFF_STALL_MEM_DURATION_STAT_RO                                                     0x030340UL //Access:R    DataWidth:0x20  Duration Counter: Counts number of ticks the device was in Stall Memory state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32762 #define CPMU_REG_OBFF_STALL_INT_STAT_RO                                                              0x030344UL //Access:R    DataWidth:0x20  Event Counter: Counts number of times the Stall Intterupt was asserted for OBFF.  Chips: BB_A0 BB_B0 K2
32763 #define CPMU_REG_OBFF_STALL_INT_DURATION_STAT_RO                                                     0x030348UL //Access:R    DataWidth:0x20  Duration Counter: Counts number of ticks the device was in Stall Intterupt state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32764 #define CPMU_REG_L1_ENTRY_STAT_RO                                                                    0x03034cUL //Access:R    DataWidth:0x20  Event Counter: Counts number of times the device has gone into L1  Chips: BB_A0 BB_B0 K2
32765 #define CPMU_REG_L1_ENTRY_DURATION_STAT_RO                                                           0x030350UL //Access:R    DataWidth:0x20  Duration Counter: Counts number of ticks the device was in L1 state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32766 #define CPMU_REG_LTR_SEND_STAT_RO                                                                    0x030354UL //Access:R    DataWidth:0x20  Event Counter: Counts number of times the device has gone into LTR  Chips: BB_A0 BB_B0 K2
32767 #define CPMU_REG_LTR_SEND_DURATION_STAT_RO                                                           0x030358UL //Access:R    DataWidth:0x20  Duration Counter: Counts number of ticks the device was in LTR state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32768 #define CPMU_REG_MCS_SLOWDOWN_STAT_RO                                                                0x03035cUL //Access:R    DataWidth:0x20  Event Counter:  Chips: BB_A0 BB_B0 K2
32769 #define CPMU_REG_MCS_DURATION_STAT_RO                                                                0x030360UL //Access:R    DataWidth:0x20  Duration Counter: counts number of ticks main clock was in slow down state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32770 #define CPMU_REG_SCS_SLOWDOWN_STAT_RO                                                                0x030364UL //Access:R    DataWidth:0x20  Event Counter:  Chips: BB_A0 BB_B0 K2
32771 #define CPMU_REG_SCS_DURATION_STAT_RO                                                                0x030368UL //Access:R    DataWidth:0x20  Duration Counter:  counts number of ticks storm clock was in slow down state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32772 #define CPMU_REG_NCS_SLOWDOWN_STAT_RO                                                                0x03036cUL //Access:R    DataWidth:0x20  Event Counter:  Chips: BB_A0 BB_B0 K2
32773 #define CPMU_REG_NCS_DURATION_STAT_RO                                                                0x030370UL //Access:R    DataWidth:0x20  Duration Counter: counts number of ticks network clock was in slow down state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32774 #define CPMU_REG_PCS_SLOWDOWN_STAT_RO                                                                0x030374UL //Access:R    DataWidth:0x20  Event Counter:  Chips: BB_A0 BB_B0 K2
32775 #define CPMU_REG_PCS_DURATION_STAT_RO                                                                0x030378UL //Access:R    DataWidth:0x20  Duration Counter: counts number of ticks pci clock was in slow down state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32776 #define CPMU_REG_LPI_TX_REQ_STAT                                                                     0x03037cUL //Access:RC   DataWidth:0x20  Event Counter: Counts number of times the device has gone into LPI.  Chips: BB_A0 BB_B0 K2
32777 #define CPMU_REG_LPI_TX_DURATION_STAT                                                                0x030380UL //Access:RC   DataWidth:0x20  Duration Counter: Counts number of ticks the device was in LPI state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32778 #define CPMU_REG_LPI_RX_REQ_STAT                                                                     0x030384UL //Access:RC   DataWidth:0x20  Event Counter: Counts number of times a Rx LPI was received.  Chips: BB_A0 BB_B0 K2
32779 #define CPMU_REG_LPI_RX_DURATION_STAT                                                                0x030388UL //Access:RC   DataWidth:0x20  Duration Counter: Counts number of ticks the device was in RX LPI state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32780 #define CPMU_REG_LPI_REQ_STAT                                                                        0x03038cUL //Access:RC   DataWidth:0x20  Event Counter: Counts number of times both sides went into LPI state.  Chips: BB_A0 BB_B0 K2
32781 #define CPMU_REG_LPI_DURATION_STAT                                                                   0x030390UL //Access:RC   DataWidth:0x20  Duration Counter: Counts number of ticks the device was in LPI state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32782 #define CPMU_REG_OBFF_STALL_MEM_STAT                                                                 0x030394UL //Access:RC   DataWidth:0x20  Event Counter: Counts number of times the Stall Memory was asserted for OBFF.  Chips: BB_A0 BB_B0 K2
32783 #define CPMU_REG_OBFF_STALL_MEM_DURATION_STAT                                                        0x030398UL //Access:RC   DataWidth:0x20  Duration Counter: Counts number of ticks the device was in Stall Memory state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32784 #define CPMU_REG_OBFF_STALL_INT_STAT                                                                 0x03039cUL //Access:RC   DataWidth:0x20  Event Counter: Counts number of times the Stall Intterupt was asserted for OBFF.  Chips: BB_A0 BB_B0 K2
32785 #define CPMU_REG_OBFF_STALL_INT_DURATION_STAT                                                        0x0303a0UL //Access:RC   DataWidth:0x20  Duration Counter: Counts number of ticks the device was in Stall Intterupt state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32786 #define CPMU_REG_L1_ENTRY_STAT                                                                       0x0303a4UL //Access:RC   DataWidth:0x20  Event Counter: Counts number of times the device has gone into L1  Chips: BB_A0 BB_B0 K2
32787 #define CPMU_REG_L1_ENTRY_DURATION_STAT                                                              0x0303a8UL //Access:RC   DataWidth:0x20  Duration Counter: Counts number of ticks the device was in L1 state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32788 #define CPMU_REG_LTR_SEND_STAT                                                                       0x0303acUL //Access:RC   DataWidth:0x20  Event Counter: Counts number of times the device has gone into LTR  Chips: BB_A0 BB_B0 K2
32789 #define CPMU_REG_LTR_SEND_DURATION_STAT                                                              0x0303b0UL //Access:RC   DataWidth:0x20  Duration Counter: Counts number of ticks the device was in LTR state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32790 #define CPMU_REG_MCS_SLOWDOWN_STAT                                                                   0x0303b4UL //Access:RC   DataWidth:0x20  Event Counter:  Chips: BB_A0 BB_B0 K2
32791 #define CPMU_REG_MCS_DURATION_STAT                                                                   0x0303b8UL //Access:RC   DataWidth:0x20  Duration Counter: Counts number of ticks main clock was in slow down state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32792 #define CPMU_REG_SCS_SLOWDOWN_STAT                                                                   0x0303bcUL //Access:RC   DataWidth:0x20  Event Counter:  Chips: BB_A0 BB_B0 K2
32793 #define CPMU_REG_SCS_DURATION_STAT                                                                   0x0303c0UL //Access:RC   DataWidth:0x20  Duration Counter: counts number of ticks storm clock was in slow down state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32794 #define CPMU_REG_NCS_SLOWDOWN_STAT                                                                   0x0303c4UL //Access:RC   DataWidth:0x20  Event Counter:  Chips: BB_A0 BB_B0 K2
32795 #define CPMU_REG_NCS_DURATION_STAT                                                                   0x0303c8UL //Access:RC   DataWidth:0x20  Duration Counter: counts number of ticks network clock was in slow down state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32796 #define CPMU_REG_PCS_SLOWDOWN_STAT                                                                   0x0303ccUL //Access:RC   DataWidth:0x20  Event Counter:  Chips: BB_A0 BB_B0 K2
32797 #define CPMU_REG_PCS_DURATION_STAT                                                                   0x0303d0UL //Access:RC   DataWidth:0x20  Duration Counter: counts number of ticks pci clock was in slow down state. this is a cumulative counter and has a 25us resolution.  Chips: BB_A0 BB_B0 K2
32798 #define CPMU_REG_CLK_TO_CLK_ST_CNT_VAL                                                               0x0303d4UL //Access:RW   DataWidth:0x5   This register configures the delay for slowing down of STORM clock after main clock is slowed down.  Chips: BB_A0 BB_B0 K2
32799 #define CPMU_REG_CLK_ST_TO_CLK_CNT_VAL                                                               0x0303d8UL //Access:RW   DataWidth:0x5   This register configures the delay for waking up of main clock after STORM clock is up and running.  Chips: BB_A0 BB_B0 K2
32800 #define CPMU_REG_ECO_RESERVED                                                                        0x0303dcUL //Access:RW   DataWidth:0x8   Reserved for future ECOs  Chips: BB_A0 BB_B0 K2
32801 #define CPMU_REG_INT_STS_0                                                                           0x0303e0UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32802     #define CPMU_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
32803     #define CPMU_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
32804 #define CPMU_REG_INT_MASK_0                                                                          0x0303e4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32805     #define CPMU_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: CPMU_REG_INT_STS_0.ADDRESS_ERROR .
32806     #define CPMU_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
32807 #define CPMU_REG_INT_STS_WR_0                                                                        0x0303e8UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32808     #define CPMU_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
32809     #define CPMU_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
32810 #define CPMU_REG_INT_STS_CLR_0                                                                       0x0303ecUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32811     #define CPMU_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
32812     #define CPMU_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
32813 #define CPMU_REG_SDM_SQ_COUNTER_E0_P0                                                                0x0303f0UL //Access:R    DataWidth:0x20  SDM SQ counter value for Engine 0, port 0.  Chips: BB_B0 K2
32814 #define CPMU_REG_SDM_SQ_COUNTER_E0_P1                                                                0x0303f4UL //Access:R    DataWidth:0x20  SDM SQ counter value for Engine 0, port 1.  Chips: BB_B0 K2
32815 #define CPMU_REG_SDM_SQ_COUNTER_E1_P0                                                                0x0303f8UL //Access:R    DataWidth:0x20  SDM SQ counter value for Engine 1, port 0.  Chips: BB_B0 K2
32816 #define CPMU_REG_SDM_SQ_COUNTER_E1_P1                                                                0x0303fcUL //Access:R    DataWidth:0x20  SDM SQ counter value for Engine 1, port 1.  Chips: BB_B0 K2
32817 #define CPMU_REG_SDM_SQ_COUNTER_E0_P2                                                                0x030400UL //Access:R    DataWidth:0x20  SDM SQ counter value for Engine 0, port 2.  Chips: K2
32818 #define CPMU_REG_SDM_SQ_COUNTER_E0_P3                                                                0x030404UL //Access:R    DataWidth:0x20  SDM SQ counter value for Engine 0, port 3.  Chips: K2
32819 #define NCSI_REG_PRTY_MASK_H_0                                                                       0x040004UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32820     #define NCSI_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: NCSI_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
32821     #define NCSI_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           0
32822 #define NCSI_REG_MEM_ECC_EVENTS                                                                      0x040010UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
32823 #define NCSI_REG_MEM002_I_MEM_DFT_K2                                                                 0x040018UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ncsi.i_ncsi_fc_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
32824 #define NCSI_REG_MEM001_I_MEM_DFT_K2                                                                 0x04001cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ncsi.i_ncsi_egress_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
32825 #define NCSI_REG_MEM003_I_MEM_DFT_K2                                                                 0x040020UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ncsi.i_ncsi_ingress_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
32826 #define NCSI_REG_CONFIG                                                                              0x040200UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32827     #define NCSI_REG_CONFIG_PROMISCOUS                                                               (0x1<<0) // Setting this bit to a '1' will result in all packets received from BMC to be routed to MCP.
32828     #define NCSI_REG_CONFIG_PROMISCOUS_SHIFT                                                         0
32829     #define NCSI_REG_CONFIG_ALL_MCP                                                                  (0x1<<1) // Setting this bit to a '1' will result in all packets received from BMC that meet the matching of Source MAC address of the packet to the stored channel MAC address criteria to be routed to MCP.
32830     #define NCSI_REG_CONFIG_ALL_MCP_SHIFT                                                            1
32831     #define NCSI_REG_CONFIG_FWD_BCAST_TO_MCP                                                         (0x1<<2) // 0 -> Send all broadcast packets to the appropriate network port. 1 -> Send all broadcast packets to MCP
32832     #define NCSI_REG_CONFIG_FWD_BCAST_TO_MCP_SHIFT                                                   2
32833     #define NCSI_REG_CONFIG_FWD_MCAST_TO_MCP                                                         (0x1<<3) // 0 -> Send all multicast packets to the appropriate network port. 1 -> Send all multicast packets to MCP
32834     #define NCSI_REG_CONFIG_FWD_MCAST_TO_MCP_SHIFT                                                   3
32835     #define NCSI_REG_CONFIG_USE_VLAN_FOR_COMP                                                        (0x1<<4) // 0 -> only MAC address is used for comparison to detect Host2BMC traffic. 1 -> MAC and VLAN are used for comparision to detect Host2BMC traffic.
32836     #define NCSI_REG_CONFIG_USE_VLAN_FOR_COMP_SHIFT                                                  4
32837     #define NCSI_REG_CONFIG_SA_LEARNING_EN                                                           (0x1<<5) // 0 -> Do not enable source MAC address learning for packets from Host to BMC. 1 -> Enable source MAC address learning for packets from Host to BMC.
32838     #define NCSI_REG_CONFIG_SA_LEARNING_EN_SHIFT                                                     5
32839     #define NCSI_REG_CONFIG_INVALIDATE_AGED_ENTRIES                                                  (0x1<<6) // 0 -> Entries in SA Learning Cache are valid even after they are aged. 1 -> Entries in SA Learning Cache become invalid after they are aged.
32840     #define NCSI_REG_CONFIG_INVALIDATE_AGED_ENTRIES_SHIFT                                            6
32841     #define NCSI_REG_CONFIG_FLOW_CONTROL_EN                                                          (0x1<<7) // Setting this bit to a '1' will result in enabling flow control towards the BMC.
32842     #define NCSI_REG_CONFIG_FLOW_CONTROL_EN_SHIFT                                                    7
32843     #define NCSI_REG_CONFIG_SW_PAUSE                                                                 (0x1<<8) // Setting this bit to a '1' will result in XOFF to be sent out to BMC. Clearing this register after it was set to '1' will cause an XON to be sent out.
32844     #define NCSI_REG_CONFIG_SW_PAUSE_SHIFT                                                           8
32845     #define NCSI_REG_CONFIG_HOST2BMC_EN                                                              (0x1<<9) // Setting this bit to a '1' tells the HW that Host2BMC traffic is enabled.
32846     #define NCSI_REG_CONFIG_HOST2BMC_EN_SHIFT                                                        9
32847     #define NCSI_REG_CONFIG_MII_SEL                                                                  (0x1<<10) // 0 -> Select NCSI RMII interface as the MII port 1 -> Select SGMII MII interface as the MII port
32848     #define NCSI_REG_CONFIG_MII_SEL_SHIFT                                                            10
32849     #define NCSI_REG_CONFIG_MGMT_SRC_SEL                                                             (0x1<<11) // 0 -> Select NCSI RMII interface as the Management Port 1 -> Select Proprietary SGMII interface as the Management port
32850     #define NCSI_REG_CONFIG_MGMT_SRC_SEL_SHIFT                                                       11
32851     #define NCSI_REG_CONFIG_DROP_ALL_PKTS_WHEN_FULL                                                  (0x1<<12) // 1 -> When BMB asserts any full condition, drop all the packets 0 -> Drop packets destined only to the particular TC when the TC specific full is asserted. Note: When global BMB Full condition is asserted, all the packets will be dropped irrespective of the settings of this register.
32852     #define NCSI_REG_CONFIG_DROP_ALL_PKTS_WHEN_FULL_SHIFT                                            12
32853     #define NCSI_REG_CONFIG_ALL_PASS_THRU_TO_HOST                                                    (0x1<<13) // 1 -> When this bit is set, all pass through traffic will be directed to host, if HOST2BMC is enabled. 0 -> When not set, packets will follow the normal decision tree.
32854     #define NCSI_REG_CONFIG_ALL_PASS_THRU_TO_HOST_SHIFT                                              13
32855 #define NCSI_REG_PKT_ETHERTYPE_VALID                                                                 0x040204UL //Access:RW   DataWidth:0x1   When set, this bit indicates that the value in pkt_ethertype register is valid.  Chips: BB_A0 BB_B0 K2
32856 #define NCSI_REG_PKT_ETHERTYPE                                                                       0x040208UL //Access:RW   DataWidth:0x10  A packet received from BMC will an ethertype of 0x88F8 will be sent to MCP as these are NCSI control packets as defined in the spec. This register allows SW to program one more ethertype other that 0x88F8, a match of which will result in packets being sent to MCP.  Chips: BB_A0 BB_B0 K2
32857 #define NCSI_REG_BMC_MAC_VALID_FLAG_0                                                                0x04020cUL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32858 #define NCSI_REG_BMC_MAC_VALID_FLAG_1                                                                0x040210UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32859 #define NCSI_REG_BMC_MAC_VALID_FLAG_2                                                                0x040214UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32860 #define NCSI_REG_BMC_MAC_VALID_FLAG_3                                                                0x040218UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the BMC MAC address + VLAN is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32861 #define NCSI_REG_BMC_MAC_ADDR_LO_0                                                                   0x04021cUL //Access:RW   DataWidth:0x20  When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32862 #define NCSI_REG_BMC_MAC_ADDR_HI_0                                                                   0x040220UL //Access:RW   DataWidth:0x10  When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32863 #define NCSI_REG_BMC_MAC_ADDR_LO_1                                                                   0x040224UL //Access:RW   DataWidth:0x20  When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32864 #define NCSI_REG_BMC_MAC_ADDR_HI_1                                                                   0x040228UL //Access:RW   DataWidth:0x10  When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32865 #define NCSI_REG_BMC_MAC_ADDR_LO_2                                                                   0x04022cUL //Access:RW   DataWidth:0x20  When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32866 #define NCSI_REG_BMC_MAC_ADDR_HI_2                                                                   0x040230UL //Access:RW   DataWidth:0x10  When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32867 #define NCSI_REG_BMC_MAC_ADDR_LO_3                                                                   0x040234UL //Access:RW   DataWidth:0x20  When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32868 #define NCSI_REG_BMC_MAC_ADDR_HI_3                                                                   0x040238UL //Access:RW   DataWidth:0x10  When the NCSI interface powers up, BMC communicates with the MCP FW on the number of channels available in the chip. Each channel represents the number of network ports in the chip. BMC will allocate one MAC address for each channel. When BMC wants to send a packet to that channel, it will use the MAC address as the Source MAC address in the packet. This allows the NIC to route the packet to the appropriate channel. MCP FW will write the MAC address to these registers so that HW can do the routing. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32869 #define NCSI_REG_BMC_VLAN_ID_0                                                                       0x04023cUL //Access:RW   DataWidth:0xc   This register stores the VLAN ID associated with the corresponding channel.  Chips: BB_A0 BB_B0 K2
32870 #define NCSI_REG_BMC_VLAN_ID_1                                                                       0x040240UL //Access:RW   DataWidth:0xc   This register stores the VLAN ID associated with the corresponding channel.  Chips: BB_A0 BB_B0 K2
32871 #define NCSI_REG_BMC_VLAN_ID_2                                                                       0x040244UL //Access:RW   DataWidth:0xc   This register stores the VLAN ID associated with the corresponding channel.  Chips: BB_A0 BB_B0 K2
32872 #define NCSI_REG_BMC_VLAN_ID_3                                                                       0x040248UL //Access:RW   DataWidth:0xc   This register stores the VLAN ID associated with the corresponding channel.  Chips: BB_A0 BB_B0 K2
32873 #define NCSI_REG_SA_STATIC_VALID_FLAG_0                                                              0x04024cUL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32874 #define NCSI_REG_SA_STATIC_VALID_FLAG_1                                                              0x040250UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32875 #define NCSI_REG_SA_STATIC_VALID_FLAG_2                                                              0x040254UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32876 #define NCSI_REG_SA_STATIC_VALID_FLAG_3                                                              0x040258UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32877 #define NCSI_REG_SA_STATIC_VALID_FLAG_4                                                              0x04025cUL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32878 #define NCSI_REG_SA_STATIC_VALID_FLAG_5                                                              0x040260UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32879 #define NCSI_REG_SA_STATIC_VALID_FLAG_6                                                              0x040264UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32880 #define NCSI_REG_SA_STATIC_VALID_FLAG_7                                                              0x040268UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32881 #define NCSI_REG_SA_STATIC_VALID_FLAG_8                                                              0x04026cUL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32882 #define NCSI_REG_SA_STATIC_VALID_FLAG_9                                                              0x040270UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32883 #define NCSI_REG_SA_STATIC_VALID_FLAG_10                                                             0x040274UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32884 #define NCSI_REG_SA_STATIC_VALID_FLAG_11                                                             0x040278UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32885 #define NCSI_REG_SA_STATIC_VALID_FLAG_12                                                             0x04027cUL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32886 #define NCSI_REG_SA_STATIC_VALID_FLAG_13                                                             0x040280UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32887 #define NCSI_REG_SA_STATIC_VALID_FLAG_14                                                             0x040284UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32888 #define NCSI_REG_SA_STATIC_VALID_FLAG_15                                                             0x040288UL //Access:RW   DataWidth:0x1   This bit shows whether the corresponding entry in the static MAC address + VLAN cache is valid or not. A '1' indicates valid entry. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32889 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_0                                                             0x04028cUL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32890 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_0                                                             0x040290UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32891 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_1                                                             0x040294UL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32892 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_1                                                             0x040298UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32893 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_2                                                             0x04029cUL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32894 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_2                                                             0x0402a0UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32895 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_3                                                             0x0402a4UL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32896 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_3                                                             0x0402a8UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32897 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_4                                                             0x0402acUL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32898 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_4                                                             0x0402b0UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32899 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_5                                                             0x0402b4UL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32900 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_5                                                             0x0402b8UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32901 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_6                                                             0x0402bcUL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32902 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_6                                                             0x0402c0UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32903 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_7                                                             0x0402c4UL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32904 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_7                                                             0x0402c8UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32905 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_8                                                             0x0402ccUL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32906 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_8                                                             0x0402d0UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32907 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_9                                                             0x0402d4UL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32908 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_9                                                             0x0402d8UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32909 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_10                                                            0x0402dcUL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32910 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_10                                                            0x0402e0UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32911 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_11                                                            0x0402e4UL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32912 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_11                                                            0x0402e8UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32913 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_12                                                            0x0402ecUL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32914 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_12                                                            0x0402f0UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32915 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_13                                                            0x0402f4UL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32916 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_13                                                            0x0402f8UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32917 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_14                                                            0x0402fcUL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32918 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_14                                                            0x040300UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32919 #define NCSI_REG_SA_STATIC_MAC_ADDR_LO_15                                                            0x040304UL //Access:RW   DataWidth:0x20  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32920 #define NCSI_REG_SA_STATIC_MAC_ADDR_HI_15                                                            0x040308UL //Access:RW   DataWidth:0x10  This is a static MAC address for HOST2BMC traffic. Everest4 support 16 Physical Functions, so there are total of 16 static MAC Addresses These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32921 #define NCSI_REG_SA_STATIC_VLAN_ID_0                                                                 0x04030cUL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32922 #define NCSI_REG_SA_STATIC_VLAN_ID_1                                                                 0x040310UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32923 #define NCSI_REG_SA_STATIC_VLAN_ID_2                                                                 0x040314UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32924 #define NCSI_REG_SA_STATIC_VLAN_ID_3                                                                 0x040318UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32925 #define NCSI_REG_SA_STATIC_VLAN_ID_4                                                                 0x04031cUL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32926 #define NCSI_REG_SA_STATIC_VLAN_ID_5                                                                 0x040320UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32927 #define NCSI_REG_SA_STATIC_VLAN_ID_6                                                                 0x040324UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32928 #define NCSI_REG_SA_STATIC_VLAN_ID_7                                                                 0x040328UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32929 #define NCSI_REG_SA_STATIC_VLAN_ID_8                                                                 0x04032cUL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32930 #define NCSI_REG_SA_STATIC_VLAN_ID_9                                                                 0x040330UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32931 #define NCSI_REG_SA_STATIC_VLAN_ID_10                                                                0x040334UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32932 #define NCSI_REG_SA_STATIC_VLAN_ID_11                                                                0x040338UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32933 #define NCSI_REG_SA_STATIC_VLAN_ID_12                                                                0x04033cUL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32934 #define NCSI_REG_SA_STATIC_VLAN_ID_13                                                                0x040340UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32935 #define NCSI_REG_SA_STATIC_VLAN_ID_14                                                                0x040344UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32936 #define NCSI_REG_SA_STATIC_VLAN_ID_15                                                                0x040348UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the corresponding MAC address of the static cache.  Chips: BB_A0 BB_B0 K2
32937 #define NCSI_REG_SA_CACHE_VALID_FLAG_0                                                               0x04034cUL //Access:RW   DataWidth:0x1   This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32938 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_0                                                         0x040350UL //Access:RW   DataWidth:0x1   This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.  Chips: BB_A0 BB_B0 K2
32939 #define NCSI_REG_SA_CACHE_VALID_FLAG_1                                                               0x040354UL //Access:RW   DataWidth:0x1   This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32940 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_1                                                         0x040358UL //Access:RW   DataWidth:0x1   This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.  Chips: BB_A0 BB_B0 K2
32941 #define NCSI_REG_SA_CACHE_VALID_FLAG_2                                                               0x04035cUL //Access:RW   DataWidth:0x1   This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32942 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_2                                                         0x040360UL //Access:RW   DataWidth:0x1   This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.  Chips: BB_A0 BB_B0 K2
32943 #define NCSI_REG_SA_CACHE_VALID_FLAG_3                                                               0x040364UL //Access:RW   DataWidth:0x1   This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32944 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_3                                                         0x040368UL //Access:RW   DataWidth:0x1   This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.  Chips: BB_A0 BB_B0 K2
32945 #define NCSI_REG_SA_CACHE_VALID_FLAG_4                                                               0x04036cUL //Access:RW   DataWidth:0x1   This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32946 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_4                                                         0x040370UL //Access:RW   DataWidth:0x1   This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.  Chips: BB_A0 BB_B0 K2
32947 #define NCSI_REG_SA_CACHE_VALID_FLAG_5                                                               0x040374UL //Access:RW   DataWidth:0x1   This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32948 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_5                                                         0x040378UL //Access:RW   DataWidth:0x1   This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.  Chips: BB_A0 BB_B0 K2
32949 #define NCSI_REG_SA_CACHE_VALID_FLAG_6                                                               0x04037cUL //Access:RW   DataWidth:0x1   This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32950 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_6                                                         0x040380UL //Access:RW   DataWidth:0x1   This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.  Chips: BB_A0 BB_B0 K2
32951 #define NCSI_REG_SA_CACHE_VALID_FLAG_7                                                               0x040384UL //Access:RW   DataWidth:0x1   This bit shows whether the entry in the cache is valid or not. A '1' implies entry is valid. Firmware steps of operation to write a new MAC Address + VLAN. 1. Clear Valid Flag 2. Write MAC Address [31:0] 3. Write MAC Address [47:32] 4. Program VLAN ID if needed 5. Set Valid Flag  Chips: BB_A0 BB_B0 K2
32952 #define NCSI_REG_SA_CACHE_REPLACEMENT_FLAG_7                                                         0x040388UL //Access:RW   DataWidth:0x1   This bit indicates whether the entry can be replaced or not. A '1' implies that the entry can be replaced. When a entry is logged into the cache, a timer is started. Every time another packet is received on the same entry, the timer is re-started. When the timer expires, the entry is deemed replaceable. Note that the timer doesn't clear the valid flag. So if the entry is not replaced and there is a hit on the entry, the replacement flag is cleared and timer is started again.  Chips: BB_A0 BB_B0 K2
32953 #define NCSI_REG_SA_CACHE_MAC_ADDR_LO_0                                                              0x04038cUL //Access:RW   DataWidth:0x20  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32954 #define NCSI_REG_SA_CACHE_MAC_ADDR_HI_0                                                              0x040390UL //Access:RW   DataWidth:0x10  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32955 #define NCSI_REG_SA_CACHE_MAC_ADDR_LO_1                                                              0x040394UL //Access:RW   DataWidth:0x20  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32956 #define NCSI_REG_SA_CACHE_MAC_ADDR_HI_1                                                              0x040398UL //Access:RW   DataWidth:0x10  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32957 #define NCSI_REG_SA_CACHE_MAC_ADDR_LO_2                                                              0x04039cUL //Access:RW   DataWidth:0x20  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32958 #define NCSI_REG_SA_CACHE_MAC_ADDR_HI_2                                                              0x0403a0UL //Access:RW   DataWidth:0x10  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32959 #define NCSI_REG_SA_CACHE_MAC_ADDR_LO_3                                                              0x0403a4UL //Access:RW   DataWidth:0x20  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32960 #define NCSI_REG_SA_CACHE_MAC_ADDR_HI_3                                                              0x0403a8UL //Access:RW   DataWidth:0x10  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32961 #define NCSI_REG_SA_CACHE_MAC_ADDR_LO_4                                                              0x0403acUL //Access:RW   DataWidth:0x20  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32962 #define NCSI_REG_SA_CACHE_MAC_ADDR_HI_4                                                              0x0403b0UL //Access:RW   DataWidth:0x10  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32963 #define NCSI_REG_SA_CACHE_MAC_ADDR_LO_5                                                              0x0403b4UL //Access:RW   DataWidth:0x20  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32964 #define NCSI_REG_SA_CACHE_MAC_ADDR_HI_5                                                              0x0403b8UL //Access:RW   DataWidth:0x10  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32965 #define NCSI_REG_SA_CACHE_MAC_ADDR_LO_6                                                              0x0403bcUL //Access:RW   DataWidth:0x20  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32966 #define NCSI_REG_SA_CACHE_MAC_ADDR_HI_6                                                              0x0403c0UL //Access:RW   DataWidth:0x10  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32967 #define NCSI_REG_SA_CACHE_MAC_ADDR_LO_7                                                              0x0403c4UL //Access:RW   DataWidth:0x20  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [31:0] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32968 #define NCSI_REG_SA_CACHE_MAC_ADDR_HI_7                                                              0x0403c8UL //Access:RW   DataWidth:0x10  NCSI block implements a Source MAC Address learning cache for packets from Host to BMC. The learning is done in HW. the next set of registers allows SW/FW to take a peek at what is stored in the cache and also allows SW/FW to override any cache entry. These are bits [47:32] of the MAC Address[47:0]  Chips: BB_A0 BB_B0 K2
32969 #define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_0                                                           0x0403ccUL //Access:RW   DataWidth:0x2   This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from.  Chips: BB_A0 BB_B0 K2
32970 #define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_1                                                           0x0403d0UL //Access:RW   DataWidth:0x2   This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from.  Chips: BB_A0 BB_B0 K2
32971 #define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_2                                                           0x0403d4UL //Access:RW   DataWidth:0x2   This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from.  Chips: BB_A0 BB_B0 K2
32972 #define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_3                                                           0x0403d8UL //Access:RW   DataWidth:0x2   This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from.  Chips: BB_A0 BB_B0 K2
32973 #define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_4                                                           0x0403dcUL //Access:RW   DataWidth:0x2   This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from.  Chips: BB_A0 BB_B0 K2
32974 #define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_5                                                           0x0403e0UL //Access:RW   DataWidth:0x2   This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from.  Chips: BB_A0 BB_B0 K2
32975 #define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_6                                                           0x0403e4UL //Access:RW   DataWidth:0x2   This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from.  Chips: BB_A0 BB_B0 K2
32976 #define NCSI_REG_SA_CACHE_DEST_HOST_FUNC_7                                                           0x0403e8UL //Access:RW   DataWidth:0x2   This is a debug only register. it captures which of the four channels in the host, the MAC address was learnt from.  Chips: BB_A0 BB_B0 K2
32977 #define NCSI_REG_SA_CACHE_VLAN_ID_0                                                                  0x0403ecUL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the MAC address of the corresponding Learning cache.  Chips: BB_A0 BB_B0 K2
32978 #define NCSI_REG_SA_CACHE_VLAN_ID_1                                                                  0x0403f0UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the MAC address of the corresponding Learning cache.  Chips: BB_A0 BB_B0 K2
32979 #define NCSI_REG_SA_CACHE_VLAN_ID_2                                                                  0x0403f4UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the MAC address of the corresponding Learning cache.  Chips: BB_A0 BB_B0 K2
32980 #define NCSI_REG_SA_CACHE_VLAN_ID_3                                                                  0x0403f8UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the MAC address of the corresponding Learning cache.  Chips: BB_A0 BB_B0 K2
32981 #define NCSI_REG_SA_CACHE_VLAN_ID_4                                                                  0x0403fcUL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the MAC address of the corresponding Learning cache.  Chips: BB_A0 BB_B0 K2
32982 #define NCSI_REG_SA_CACHE_VLAN_ID_5                                                                  0x040400UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the MAC address of the corresponding Learning cache.  Chips: BB_A0 BB_B0 K2
32983 #define NCSI_REG_SA_CACHE_VLAN_ID_6                                                                  0x040404UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the MAC address of the corresponding Learning cache.  Chips: BB_A0 BB_B0 K2
32984 #define NCSI_REG_SA_CACHE_VLAN_ID_7                                                                  0x040408UL //Access:RW   DataWidth:0xc   This is the VLAN ID associated with the MAC address of the corresponding Learning cache.  Chips: BB_A0 BB_B0 K2
32985 #define NCSI_REG_SA_CACHE_AGING_THRESHOLD                                                            0x04040cUL //Access:RW   DataWidth:0x20  Provides Aging threshold of Source Address Learning cache entries in seconds. When an entry is written to the cache, a timer is loaded with the aging threshold. When the timer expires, the entry can be replaced. The resolution of the aging timer is 1ms  Chips: BB_A0 BB_B0 K2
32986 #define NCSI_REG_SA_CACHE_CLR                                                                        0x040410UL //Access:RW   DataWidth:0x1   When this bit is set, all the entries in the cache will be cleared.  Chips: BB_A0 BB_B0 K2
32987 #define NCSI_REG_TAG_RM_CONFIG                                                                       0x040414UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
32988     #define NCSI_REG_TAG_RM_CONFIG_PROP_HEADER_RM                                                    (0x1<<0) // Setting this bit to "1" will result in removing proprietary headers from all packets.
32989     #define NCSI_REG_TAG_RM_CONFIG_PROP_HEADER_RM_SHIFT                                              0
32990     #define NCSI_REG_TAG_RM_CONFIG_PER_TAG_RM                                                        (0x3f<<1) // NCSI block has the capability to remove up-to six TAGs present in a packet. This field sets which of the TAGs need to be removed. This field works in conjuction with the TAG_EXIST field in the SOP descriptor. When a TAG exists in the packet and the corresponding bit is set, the TAG is removed.
32991     #define NCSI_REG_TAG_RM_CONFIG_PER_TAG_RM_SHIFT                                                  1
32992     #define NCSI_REG_TAG_RM_CONFIG_INNER_VLAN_RM                                                     (0x3<<7) // This bits are used to configure how the inner vlan tag needs to be handled. Inner VLAN is always the 2nd tag in a packet. 2'b00 -> Use the configuration bit associated with the Inner VLAN tag to decide whether to remove the tag or not. If the bit is 1, then remove the tag. 2'b01 -> Do not strip the inner VLAN Tag. Pass it on to BMC 2'b10 -> Always remove the inner VLAN Tag regardless of the configuration bit before sending the packet to BMC. 2'b11 -> Conditional Strip VLAN. If the inner VLAN in the packet is equal to a programmable management inner VLAN then remove the VLAN, else leave it in.
32993     #define NCSI_REG_TAG_RM_CONFIG_INNER_VLAN_RM_SHIFT                                               7
32994 #define NCSI_REG_TAG_RM_PROP_HEADER_LEN                                                              0x040418UL //Access:RW   DataWidth:0x5   This register indicates the size of the proprietary header at the beginning of the packet. The Tag removal logic will use this length to remove this header from the packet before sending it out to BMC. it is expected that once a non-zero value is set, all packets destined to BMC will have the proprietary header.  Chips: BB_A0 BB_B0 K2
32995 #define NCSI_REG_TAG_LEN_0                                                                           0x04041cUL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 0.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
32996 #define NCSI_REG_TAG_LEN_1                                                                           0x040420UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 1.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
32997 #define NCSI_REG_TAG_LEN_2                                                                           0x040424UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 2.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
32998 #define NCSI_REG_TAG_LEN_3                                                                           0x040428UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 3.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
32999 #define NCSI_REG_TAG_LEN_4                                                                           0x04042cUL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 4.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
33000 #define NCSI_REG_TAG_LEN_5                                                                           0x040430UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 5.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
33001 #define NCSI_REG_TAG_INS_CONFIG                                                                      0x040434UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33002     #define NCSI_REG_TAG_INS_CONFIG_INSERT_PROP_HEADER                                               (0x1<<0) // Tells HW to set the INS_PROP_HEADER flag in the SOP descriptor for a BMC to Network packet
33003     #define NCSI_REG_TAG_INS_CONFIG_INSERT_PROP_HEADER_SHIFT                                         0
33004     #define NCSI_REG_TAG_INS_CONFIG_INSERT_OUTER_TAG                                                 (0x1<<1) // Tells HW to set the INS_OUTER_TAG flag in the SOP descriptor for a BMC to Network packet
33005     #define NCSI_REG_TAG_INS_CONFIG_INSERT_OUTER_TAG_SHIFT                                           1
33006     #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN                                                 (0x1<<2) // Tells HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is non-zero
33007     #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN_SHIFT                                           2
33008     #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN_IF_NO_VLAN                                      (0x1<<3) // Tells HW to set the OVRRIDE_INNER_VLAN flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet and VLAN ID is zero or Set the INS_INNER_VLAN flag if there is no VLAN header in the packet. In this case even the priority is inserted
33009     #define NCSI_REG_TAG_INS_CONFIG_FORCE_INNER_VLAN_IF_NO_VLAN_SHIFT                                3
33010     #define NCSI_REG_TAG_INS_CONFIG_FORCE_PRIORITY                                                   (0x1<<4) // Tells HW to set the OVRRIDE_PRIORITY flag in the SOP descriptor for a BMC to Network packet if there is a VLAN header in the packet
33011     #define NCSI_REG_TAG_INS_CONFIG_FORCE_PRIORITY_SHIFT                                             4
33012 #define NCSI_REG_SIDEBAND_ARB                                                                        0x040438UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
33013     #define NCSI_REG_SIDEBAND_ARB_ARB_NCSI_ID                                                        (0x7<<0) // This field is used to set the ID of the current NCSI port. NCSI port with the lowest ID value is the master of the HW based arbitration.
33014     #define NCSI_REG_SIDEBAND_ARB_ARB_NCSI_ID_SHIFT                                                  0
33015     #define NCSI_REG_SIDEBAND_ARB_UNUSED0                                                            (0x1<<3) // Unused
33016     #define NCSI_REG_SIDEBAND_ARB_UNUSED0_SHIFT                                                      3
33017     #define NCSI_REG_SIDEBAND_ARB_ARB_DISABLE                                                        (0x1<<4) // Setting this field to '1' causes the hardware arbitration scheme to be disabled. This bit should be set when there is only one NCSI port on the board and tokens need not be passed out.
33018     #define NCSI_REG_SIDEBAND_ARB_ARB_DISABLE_SHIFT                                                  4
33019     #define NCSI_REG_SIDEBAND_ARB_ARB_START                                                          (0x1<<5) // Setting this field to '1' causes the hardware arbitration scheme to begin. Any NCSI port can re-start the arbitration.
33020     #define NCSI_REG_SIDEBAND_ARB_ARB_START_SHIFT                                                    5
33021     #define NCSI_REG_SIDEBAND_ARB_ARB_BYPASS                                                         (0x1<<6) // Setting this field to '1' the HW arbitration logic to function in bypass mode. This allows NCSI ports that don't have the firmware running to be automatically bypassed. Firmware should also set this bit when there is nothing to send. This will reduce the latency of the token around the loop.
33022     #define NCSI_REG_SIDEBAND_ARB_ARB_BYPASS_SHIFT                                                   6
33023     #define NCSI_REG_SIDEBAND_ARB_ARB_AUTO_BYPASS                                                    (0x1<<7) // Setting this field to '1' causes the NCSI port to cut latency when forwarding a token.
33024     #define NCSI_REG_SIDEBAND_ARB_ARB_AUTO_BYPASS_SHIFT                                              7
33025     #define NCSI_REG_SIDEBAND_ARB_ARB_TOKEN_IPG                                                      (0x1f<<8) // This field is a programmable inter-packet gap for when the token is sent out.
33026     #define NCSI_REG_SIDEBAND_ARB_ARB_TOKEN_IPG_SHIFT                                                8
33027     #define NCSI_REG_SIDEBAND_ARB_UNUSED1                                                            (0x1<<13) // unused
33028     #define NCSI_REG_SIDEBAND_ARB_UNUSED1_SHIFT                                                      13
33029     #define NCSI_REG_SIDEBAND_ARB_ARB_FC_DISABLE                                                     (0x1<<14) // Setting this bit disables the feature to send XOFF/XON ordered sets on the arbiter interface. This feature is enabled by default and allows a NCSI port that wants to send a XOFF/XON frame to use the sideband interface to accelerate sending the command on the MII bus. This helps reducing the size of the Rx FIFO needed when multiple NCSI ports are connected to the BMC.
33030     #define NCSI_REG_SIDEBAND_ARB_ARB_FC_DISABLE_SHIFT                                               14
33031     #define NCSI_REG_SIDEBAND_ARB_ARB_UPDATE                                                         (0x1<<15) // Toggle this bit to update this register. Write "1" and then write "0".
33032     #define NCSI_REG_SIDEBAND_ARB_ARB_UPDATE_SHIFT                                                   15
33033     #define NCSI_REG_SIDEBAND_ARB_ARB_TIMEOUT                                                        (0xffff<<16) // This field indicates the value in number of Ingress clock cycles that the arbitration master will wait before re-starting the arbitration process.
33034     #define NCSI_REG_SIDEBAND_ARB_ARB_TIMEOUT_SHIFT                                                  16
33035 #define NCSI_REG_ARB_TOKEN_VALID                                                                     0x04043cUL //Access:R    DataWidth:0x1   This bit indicates if the arbiter has a valid token.  Chips: BB_A0 BB_B0 K2
33036 #define NCSI_REG_NCSI_PKGID                                                                          0x040440UL //Access:R    DataWidth:0x2   These bits indicate the Package ID of the chip as programmed at the I/Os.  Chips: BB_A0 BB_B0 K2
33037 #define NCSI_REG_NCSI_RESET                                                                          0x040444UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33038     #define NCSI_REG_NCSI_RESET_EGRESS_RESET                                                         (0x1<<0) // Setting this bit will create an asychronous reset to the egress logic. Should be used only incase where the logic is stuck
33039     #define NCSI_REG_NCSI_RESET_EGRESS_RESET_SHIFT                                                   0
33040     #define NCSI_REG_NCSI_RESET_INGRESS_RESET                                                        (0x1<<1) // Setting this bit will create an asychronous reset to the ingress logic. Should be used only incase where the logic is stuck
33041     #define NCSI_REG_NCSI_RESET_INGRESS_RESET_SHIFT                                                  1
33042 #define NCSI_REG_STAT_NUM_PACKETS_TO_NETWORK_RO                                                      0x040448UL //Access:R    DataWidth:0x20  Event Counter: Counts the number of packets sent to Network  Chips: BB_A0 BB_B0 K2
33043 #define NCSI_REG_STAT_NUM_PACKETS_TO_HOST_RO                                                         0x04044cUL //Access:R    DataWidth:0x20  Event Counter: Counts the number of packets sent to Host  Chips: BB_A0 BB_B0 K2
33044 #define NCSI_REG_STAT_NUM_PACKETS_TO_MCP_RO                                                          0x040450UL //Access:R    DataWidth:0x20  Event Counter: Counts the number of packets sent to mcp  Chips: BB_A0 BB_B0 K2
33045 #define NCSI_REG_STAT_PKT_DROP_SA_MISMATCH_RO                                                        0x040454UL //Access:R    DataWidth:0x20  Event Counter: Counts the number of packets that were dropped due to source Address mismatch.  Chips: BB_A0 BB_B0 K2
33046 #define NCSI_REG_STAT_PKT_DROP_BMB_FULL_RO                                                           0x040458UL //Access:R    DataWidth:0x20  Event Counter: Counts the number of packets that were dropped due to BMB full.  Chips: BB_A0 BB_B0 K2
33047 #define NCSI_REG_STAT_NUM_PACKETS_TO_NETWORK                                                         0x04045cUL //Access:RC   DataWidth:0x20  Event Counter: Counts the number of packets sent to Network  Chips: BB_A0 BB_B0 K2
33048 #define NCSI_REG_STAT_NUM_PACKETS_TO_HOST                                                            0x040460UL //Access:RC   DataWidth:0x20  Event Counter: Counts the number of packets sent to Host  Chips: BB_A0 BB_B0 K2
33049 #define NCSI_REG_STAT_NUM_PACKETS_TO_MCP                                                             0x040464UL //Access:RC   DataWidth:0x20  Event Counter: Counts the number of packets sent to mcp  Chips: BB_A0 BB_B0 K2
33050 #define NCSI_REG_STAT_PKT_DROP_SA_MISMATCH                                                           0x040468UL //Access:RC   DataWidth:0x20  Event Counter: Counts the number of packets that were dropped due to source Address mismatch.  Chips: BB_A0 BB_B0 K2
33051 #define NCSI_REG_STAT_PKT_DROP_BMB_FULL                                                              0x04046cUL //Access:RC   DataWidth:0x20  Event Counter: Counts the number of packets that were dropped due to BMB full.  Chips: BB_A0 BB_B0 K2
33052 #define NCSI_REG_INGRESS_FIFO_ALMOST_FULL_THRES                                                      0x040470UL //Access:RW   DataWidth:0x6   This register sets the number for 16byte words need to be accumulated before starting a transfer to the BMC. this register is provided to prevent any underrun that can happen if BMB is too slow to send data to the NCSI module as the data transfer to NCSI has started. Setting a value of all 1s in this register will guarantee a store-and-forward operation. Normally this register needs not be programmed and the default value should suffice.  Chips: BB_A0 BB_B0 K2
33053 #define NCSI_REG_DBG_SELECT                                                                          0x040474UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
33054 #define NCSI_REG_DBG_DWORD_ENABLE                                                                    0x040478UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
33055 #define NCSI_REG_DBG_SHIFT                                                                           0x04047cUL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
33056 #define NCSI_REG_DBG_FORCE_VALID                                                                     0x040480UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
33057 #define NCSI_REG_DBG_FORCE_FRAME                                                                     0x040484UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
33058 #define NCSI_REG_DBG_OUT_DATA                                                                        0x0404a0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
33059 #define NCSI_REG_DBG_OUT_DATA_SIZE                                                                   8
33060 #define NCSI_REG_DBG_OUT_VALID                                                                       0x0404c0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
33061 #define NCSI_REG_DBG_OUT_FRAME                                                                       0x0404c4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
33062 #define NCSI_REG_ECO_RESERVED                                                                        0x0404c8UL //Access:RW   DataWidth:0x8   Reserved for future ECOs  Chips: BB_A0 BB_B0 K2
33063 #define NCSI_REG_INT_STS_0                                                                           0x0404ccUL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33064     #define NCSI_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
33065     #define NCSI_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
33066 #define NCSI_REG_INT_MASK_0                                                                          0x0404d0UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33067     #define NCSI_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: NCSI_REG_INT_STS_0.ADDRESS_ERROR .
33068     #define NCSI_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
33069 #define NCSI_REG_INT_STS_WR_0                                                                        0x0404d4UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33070     #define NCSI_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
33071     #define NCSI_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
33072 #define NCSI_REG_INT_STS_CLR_0                                                                       0x0404d8UL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33073     #define NCSI_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
33074     #define NCSI_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
33075 #define GRC_REG_OVERRIDE_WINDOW_MEM_SELF_INIT_START                                                  0x050000UL //Access:RW   DataWidth:0x1   Reset the protection override window memory. When set to 1, protection override window memory self init starts.  Chips: BB_A0 BB_B0 K2
33076 #define GRC_REG_OVERRIDE_WINDOW_MEM_SELF_INIT_DONE                                                   0x050004UL //Access:R    DataWidth:0x1   When = 1, the self init for the protection override window memory is done.  Chips: BB_A0 BB_B0 K2
33077 #define GRC_REG_RSV_ATTN_ACCESS_DATA_0                                                               0x050040UL //Access:R    DataWidth:0x1c  Holds the data regarding the last access that caused reserved address interrupt. Bits [22:0]:  Address (4 bytes resolution). Bits [23]:    Wr/rd. If = 1 it is write, If = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.  Chips: BB_A0 BB_B0 K2
33078 #define GRC_REG_RSV_ATTN_ACCESS_DATA_1                                                               0x050044UL //Access:R    DataWidth:0x13  Holds the data regarding the last access that caused reserved address interrupt. Bits [3:0]: PF. Bits [11:4]: VF. Bit  [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s) 2 - HV: HyperVisor (Assigned to HV). 3 - UN: Un-restricted Access. Bits [18:16]: Protection. Contains the value set by the master. The decoding: 3 - 0: Takes the default protection defined by the slave RF block. 4: Over-ride the target slave address attribute to VN PROTECTION. 5: Over-ride the target slave address attribute to VM PROTECTION. 6: Over-ride the target slave address attribute to HV PROTECTION. 7: Over-ride the target slave address attribute to UA PROTECTION.  Chips: BB_A0 BB_B0 K2
33079 #define GRC_REG_RSV_ATTN_ACCESS_VALID                                                                0x050048UL //Access:RW   DataWidth:0x1   When asserted, = 1, indicates that the rsv_attn_access_data_0 and rsv_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.  Chips: BB_A0 BB_B0 K2
33080 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0                                                           0x05004cUL //Access:R    DataWidth:0x1c  Holds the data regarding the last access that caused timeout interrupt. Bits [22:0]:  Address (4 bytes resolution). Bit  [23]:    Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.  Chips: BB_A0 BB_B0 K2
33081 #define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1                                                           0x050050UL //Access:R    DataWidth:0x13  Holds the data regarding the last access that caused timeout interrupt. Bits [3:0]: PF. Bits [11:4]: VF. Bit  [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s) 2 - HV: HyperVisor (Assigned to HV). 3 - UN: Un-restricted Access. Bits [18:16]: Protection. Contains the value set by the master. The decoding: 3 - 0: Takes the default protection defined by the slave RF block. 4: Over-ride the target slave address attribute to VN PROTECTION. 5: Over-ride the target slave address attribute to VM PROTECTION. 6: Over-ride the target slave address attribute to HV PROTECTION. 7: Over-ride the target slave address attribute to UA PROTECTION.  Chips: BB_A0 BB_B0 K2
33082 #define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID                                                            0x050054UL //Access:RW   DataWidth:0x1   When asserted, = 1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.  Chips: BB_A0 BB_B0 K2
33083 #define GRC_REG_PATH_ISOLATION_ERROR_DATA_0                                                          0x050058UL //Access:R    DataWidth:0x1c  Holds the data regarding the last access that caused path isolation interrupt. Bits [22:0]:  Address (4 bytes resolution). Bit  [23]:    Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.  Chips: BB_A0 BB_B0 K2
33084 #define GRC_REG_PATH_ISOLATION_ERROR_DATA_1                                                          0x05005cUL //Access:R    DataWidth:0x13  Holds the data regarding the last access that caused path isolation interrupt. Bits [3:0]: PF. Bits [11:4]: VF. Bit  [13:12]: Port. Bits [15:14]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s) 2 - HV: HyperVisor (Assigned to HV). 3 - UN: Un-restricted Access. Bits [18:16]: Protection. Contains the value set by the master. The decoding: 3 - 0: Takes the default protection defined by the slave RF block. 4: Over-ride the target slave address attribute to VN PROTECTION. 5: Over-ride the target slave address attribute to VM PROTECTION. 6: Over-ride the target slave address attribute to HV PROTECTION. 7: Over-ride the target slave address attribute to UA PROTECTION.  Chips: BB_A0 BB_B0 K2
33085 #define GRC_REG_PATH_ISOLATION_ERROR_VALID                                                           0x050060UL //Access:RW   DataWidth:0x1   When asserted, = 1, indicates that the path_isolation_error_data_0 and path_isolation_error_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.  Chips: BB_A0 BB_B0 K2
33086 #define GRC_REG_TRACE_FIFO_VALID_DATA                                                                0x050064UL //Access:R    DataWidth:0x1   If = 1, indicates that the trace FIFO contains at least one valid data.                           If = 0, indicates that the trace FIFO doeasn't contain any valid data.                          This register should be read before reading the GRC_REGISTERS_TRACE_FIFO,                           and only if the read value is 1, one read from the GRC_REGISTERS_TRACE_FIFO can be done.  Chips: BB_A0 BB_B0 K2
33087 #define GRC_REG_TRACE_FIFO                                                                           0x050068UL //Access:WB_R DataWidth:0x34  Each row in the FIFO contains data regarding previous GRC rd/wr access. This FIFO conatins 32 rows. Before each read from this register, the register GRC_REGISTERS_TRACE_FIFO_VALID_DATA should be read, and only if the read value is 1, this FIFO has at least one valid data, and this register can be read once. The data: Bits [22:0]:  Address (4 bytes resolution). Bits [23]:    Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: PF. Bits [35:28]: VF. Bit  [37:36]: Port. Bits [39:38]: Privilege. The decoding: 0 - VN: Virtualized NIC (Used for VF access). 1 - PDA: Physical Device Assignment (Assigned to VM-s) 2 - HV: HyperVisor (Assigned to HV). 3 - UN: Un-restricted Access. Bits [42:40]: Protection. The decoding: 3 - 0: Takes the default protection defined by the slave RF block. 4: Over-ride the target slave address attribute to VN PROTECTION. 5: Over-ride the target slave address attribute to VM PROTECTION. 6: Over-ride the target slave address attribute to HV PROTECTION. 7: Over-ride the target slave address attribute to UA PROTECTION. Bits [46:43]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae. Bits [51:47]: Error type. The decoding: 0 = no error (access to the slave block ended successfully). 1 = timeout event. 2 = Reserved address that is acknowledged by the GRC block due to address which doesn't belong to any block address domain. 4 = slave block access to reserved address error or write to read only register which is set by the slave block that the access was targeted for. 8 = slave block privilege (protection) error which is set by the slave block that the access was targeted for.        16 = path isolation error.  Chips: BB_A0 BB_B0 K2
33088 #define GRC_REG_TRACE_FIFO_SIZE                                                                      2
33089 #define GRC_REG_TRACE_FIFO_ENABLE                                                                    0x050070UL //Access:RW   DataWidth:0x1   If = 1, the trace fifo feature is enabled and write of GRC wr/rd accesses to the FIFO is done based on the different trace FIFO configurtaions.                          If = 0, the trace fifo feature is disabled and no writes are done to the FIFO.                          It is recommended to disable this feature before reading from the GRC_REGISTERS_TRACE_FIFO.  Chips: BB_A0 BB_B0 K2
33090 #define GRC_REG_TRACE_FIFO_MASTERS_SEL                                                               0x050074UL //Access:RW   DataWidth:0xa   Selects the masters that their accesses are written to the trace FIFO. The range can be from one master to all masters, all combinations. If = 1, the master is enabled and its accesses are written to the trace FIFO. If = 0, the master is masked, and its accesses are not written to the trace FIFO. The fields: Bit [0]: pxp. Bit [1]: mcp. Bit [2]: msdm. Bit [3]: psdm. Bit [4]: ysdm. Bit [5]: usdm Bit [6]: tsdm. Bit [7]: xsdm. Bit [8]: dbu. Bit [9]: dmae.  Chips: BB_A0 BB_B0 K2
33091 #define GRC_REG_TRACE_FIFO_ERROR_TYPE_SEL                                                            0x050078UL //Access:RW   DataWidth:0x6   Selects the accesses with error types that are written to the trace FIFO. The range can be all combinations. If = 1 the error is enabled, access with applicable error is written to the trace FIFO. If = 0 the error is masked, access with applicable error is not written to the trace FIFO. The fields: Bit [0]: no error. Bit [1]: timeout event. Bit [2]: GRC reserved address. Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain. Bit [3]: slave block address error. Slave block address error (access to reserved address or write to read only register) which is set by the slave block that the access was targeted for. Bit [4]: slave block privilege (protection) error. Slave block privilege (protection) error which is set by the slave block that the access was targeted for. Bit [5]: path isolation error.  Chips: BB_A0 BB_B0 K2
33092 #define GRC_REG_TRACE_FIFO_WR_RD_SEL                                                                 0x05007cUL //Access:RW   DataWidth:0x2   Selects if wr/rd type accesses are written to the trace FIFO. One or both types can be enabled. If = 1 the wr/rd access is enabled, wr/rd access is written to the trace FIFO. If = 0 the wr/rd access is masked, wr/rd access is not written to the trace FIFO. The fields: Bit [0]: wr. Bit [1]: rd.  Chips: BB_A0 BB_B0 K2
33093 #define GRC_REG_TRACE_FIFO_PF_SEL                                                                    0x050080UL //Access:RW   DataWidth:0x10  Selects the PF for the accesses that are written to the trace FIFO. The range is from one PF to all PFs, all combinations. If = 1 the PF is enabled, access with the PF is written to the trace FIFO. If = 0 the PF is masked, access with the PF is not written to the trace FIFO. BB: only bits 0-7 are applicable. The fields: Bit [0]: PF #0. Bit [1]: PF #1.            Bit [2]: PF #2. Bit [3]: PF #3.  Bit [4]: PF #4. Bit [5]: PF #5.            Bit [6]: PF #6. Bit [7]: PF #7. Bit [8]: PF #8. Bit [9]: PF #9.            Bit [10]: PF #10. Bit [11]: PF #11. Bit [12]: PF #12. Bit [13]: PF #13.            Bit [14]: PF #14. Bit [15]: PF #15.  Chips: BB_A0 BB_B0 K2
33094 #define GRC_REG_TRACE_FIFO_VF_SEL                                                                    0x050084UL //Access:RW   DataWidth:0x1   If = 1, selects only the VF in GRC_REG_TRACE_FIFO_VF for the accesses that are written to the trace FIFO. If = 0, accesses with all VFs are written to the trace FIFO.  Chips: BB_A0 BB_B0 K2
33095 #define GRC_REG_TRACE_FIFO_VF                                                                        0x050088UL //Access:RW   DataWidth:0x8   The VF for the accesses that are written to the trace FIFO. Applicable only if GRC_REG_TRACE_FIFO_VF_SEL = 1. Value of all 1s is applicable and represents VF not valid. BB: only bits 0-6 are applicable.  Chips: BB_A0 BB_B0 K2
33096 #define GRC_REG_TRACE_FIFO_PORT_SEL                                                                  0x05008cUL //Access:RW   DataWidth:0x4   Selects the ports for the accesses that are written to the trace FIFO. The range is from one port to all ports, all combinations. If = 1 the port is enabled, access with the port is written to the trace FIFO. If = 0 the port is masked, access with the port is not written to the trace FIFO. BB: only bits 0-1 are applicable. The fields: Bit [0]: port #0. Bit [1]: port #1.            Bit [2]: port #2. Bit [3]: port #3.  Chips: BB_A0 BB_B0 K2
33097 #define GRC_REG_TRACE_FIFO_PRIVILEGE_SEL                                                             0x050090UL //Access:RW   DataWidth:0x4   Selects the privilege for the accesses that are written to the trace FIFO. The range is from one privilege to all privileges, all combinations. If = 1 the privilege is enabled, access with the privilege is written to the trace FIFO. If = 0 the privilege is masked, access with the privilege is not written to the trace FIFO. The fields: Bit [0]: VN (0). Bit [1]: PDA (1).            Bit [2]: HV (2). Bit [3]: UA (3).  Chips: BB_A0 BB_B0 K2
33098 #define GRC_REG_TRACE_FIFO_PRIVILEGE_OVERRIDE_SEL                                                    0x050094UL //Access:RW   DataWidth:0x8   Selects the privilege override for the accesses that are written to the trace FIFO. The range is from one privilege override to all privilege overrides, all combinations. If = 1 the privilege override is enabled, access with the privilege override is written to the trace FIFO. If = 0 the privilege override is masked, access with the privilege overrideis not written to the trace FIFO. The fields: Bit [0]: PRV_DEFAULT. Takes the default protection defined by RF block. Bit [1]: PRV_DEFAULT. Takes the default protection defined by RF block.           Bit [2]: PRV_DEFAULT. Takes the default protection defined by RF block. Bit [3]: PRV_DEFAULT. Takes the default protection defined by RF block. Bit [4]: VN_OV. Over-ride to VN PROTECTION. Bit [5]: PDA_OV. Over-ride to PDA PROTECTION. Bit [6]: HV_OV. Over-ride to HV PROTECTION. Bit [7]: UA_OV. Over-ride to UA PROTECTION.  Chips: BB_A0 BB_B0 K2
33099 #define GRC_REG_TRACE_FIFO_ADDRESS_SEL                                                               0x050098UL //Access:RW   DataWidth:0x17  Selects the address for the accesses that are written to the trace FIFO. Selects for each address bit if this bit is enforced. The register GRC_REG_TRACE_FIFO_ADDRESS selects the value for the address bit. This mechanism enables to select or a specific address, or a range of address by enforcing the msbits. In order to select all the addresses of a specific block, need to enforce its base address. In order to select all chip addresses, the required value for this regsiter is 0.  Chips: BB_A0 BB_B0 K2
33100 #define GRC_REG_TRACE_FIFO_ADDRESS                                                                   0x05009cUL //Access:RW   DataWidth:0x17  Selects the address for the accesses that are written to the trace FIFO. Selects the value for each address bit. The register GRC_REG_TRACE_FIFO_ADDRESS_SEL selects for each address bit if it is enforced the address bit. This mechanism enables to select or a specific address, or a range of address by enforcing the msbits. In order to select all the addresses of a specific block, need to enforce its base address.  Chips: BB_A0 BB_B0 K2
33101 #define GRC_REG_TRACE_FIFO_MODE                                                                      0x0500a0UL //Access:RW   DataWidth:0x1   Trace FIFO mode. If = 0, keeps the first 32 GRC accesses. When the FIFO is full new accesses are dropped. If = 1, keeps the last 32 GRC accesses. When the FIFO is full a new access overrides the first access.  Chips: BB_A0 BB_B0 K2
33102 #define GRC_REG_DBG_SELECT                                                                           0x0500a4UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
33103 #define GRC_REG_DBG_DWORD_ENABLE                                                                     0x0500a8UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
33104 #define GRC_REG_DBG_SHIFT                                                                            0x0500acUL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
33105 #define GRC_REG_DBG_FORCE_VALID                                                                      0x0500b0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
33106 #define GRC_REG_DBG_FORCE_FRAME                                                                      0x0500b4UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
33107 #define GRC_REG_DBG_OUT_DATA                                                                         0x0500c0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
33108 #define GRC_REG_DBG_OUT_DATA_SIZE                                                                    8
33109 #define GRC_REG_DBG_OUT_VALID                                                                        0x0500e0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
33110 #define GRC_REG_DBG_OUT_FRAME                                                                        0x0500e4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
33111 #define GRC_REG_DBGSYN_STATUS                                                                        0x0500e8UL //Access:R    DataWidth:0x5   Fill level of dbgmux fifo.  Chips: BB_B0 K2
33112 #define GRC_REG_DBGSYN_ALMOST_FULL_THR                                                               0x0500ecUL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO, it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: BB_B0 K2
33113 #define GRC_REG_INT_STS_0                                                                            0x050180UL //Access:R    DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33114     #define GRC_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
33115     #define GRC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
33116     #define GRC_REG_INT_STS_0_TIMEOUT_EVENT                                                          (0x1<<1) // Timeout event
33117     #define GRC_REG_INT_STS_0_TIMEOUT_EVENT_SHIFT                                                    1
33118     #define GRC_REG_INT_STS_0_GLOBAL_RESERVED_ADDRESS                                                (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
33119     #define GRC_REG_INT_STS_0_GLOBAL_RESERVED_ADDRESS_SHIFT                                          2
33120     #define GRC_REG_INT_STS_0_PATH_ISOLATION_ERROR                                                   (0x1<<3) // Path Isolation error.
33121     #define GRC_REG_INT_STS_0_PATH_ISOLATION_ERROR_SHIFT                                             3
33122     #define GRC_REG_INT_STS_0_TRACE_FIFO_VALID_DATA                                                  (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
33123     #define GRC_REG_INT_STS_0_TRACE_FIFO_VALID_DATA_SHIFT                                            4
33124 #define GRC_REG_INT_MASK_0                                                                           0x050184UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33125     #define GRC_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.ADDRESS_ERROR .
33126     #define GRC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
33127     #define GRC_REG_INT_MASK_0_TIMEOUT_EVENT                                                         (0x1<<1) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.TIMEOUT_EVENT .
33128     #define GRC_REG_INT_MASK_0_TIMEOUT_EVENT_SHIFT                                                   1
33129     #define GRC_REG_INT_MASK_0_GLOBAL_RESERVED_ADDRESS                                               (0x1<<2) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.GLOBAL_RESERVED_ADDRESS .
33130     #define GRC_REG_INT_MASK_0_GLOBAL_RESERVED_ADDRESS_SHIFT                                         2
33131     #define GRC_REG_INT_MASK_0_PATH_ISOLATION_ERROR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.PATH_ISOLATION_ERROR .
33132     #define GRC_REG_INT_MASK_0_PATH_ISOLATION_ERROR_SHIFT                                            3
33133     #define GRC_REG_INT_MASK_0_TRACE_FIFO_VALID_DATA                                                 (0x1<<4) // This bit masks, when set, the Interrupt bit: GRC_REG_INT_STS_0.TRACE_FIFO_VALID_DATA .
33134     #define GRC_REG_INT_MASK_0_TRACE_FIFO_VALID_DATA_SHIFT                                           4
33135 #define GRC_REG_INT_STS_WR_0                                                                         0x050188UL //Access:WR   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33136     #define GRC_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
33137     #define GRC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
33138     #define GRC_REG_INT_STS_WR_0_TIMEOUT_EVENT                                                       (0x1<<1) // Timeout event
33139     #define GRC_REG_INT_STS_WR_0_TIMEOUT_EVENT_SHIFT                                                 1
33140     #define GRC_REG_INT_STS_WR_0_GLOBAL_RESERVED_ADDRESS                                             (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
33141     #define GRC_REG_INT_STS_WR_0_GLOBAL_RESERVED_ADDRESS_SHIFT                                       2
33142     #define GRC_REG_INT_STS_WR_0_PATH_ISOLATION_ERROR                                                (0x1<<3) // Path Isolation error.
33143     #define GRC_REG_INT_STS_WR_0_PATH_ISOLATION_ERROR_SHIFT                                          3
33144     #define GRC_REG_INT_STS_WR_0_TRACE_FIFO_VALID_DATA                                               (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
33145     #define GRC_REG_INT_STS_WR_0_TRACE_FIFO_VALID_DATA_SHIFT                                         4
33146 #define GRC_REG_INT_STS_CLR_0                                                                        0x05018cUL //Access:RC   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33147     #define GRC_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
33148     #define GRC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
33149     #define GRC_REG_INT_STS_CLR_0_TIMEOUT_EVENT                                                      (0x1<<1) // Timeout event
33150     #define GRC_REG_INT_STS_CLR_0_TIMEOUT_EVENT_SHIFT                                                1
33151     #define GRC_REG_INT_STS_CLR_0_GLOBAL_RESERVED_ADDRESS                                            (0x1<<2) // Reserved address that is acknowledged by the GRC block due to address which doesnt belong to any block address domain.
33152     #define GRC_REG_INT_STS_CLR_0_GLOBAL_RESERVED_ADDRESS_SHIFT                                      2
33153     #define GRC_REG_INT_STS_CLR_0_PATH_ISOLATION_ERROR                                               (0x1<<3) // Path Isolation error.
33154     #define GRC_REG_INT_STS_CLR_0_PATH_ISOLATION_ERROR_SHIFT                                         3
33155     #define GRC_REG_INT_STS_CLR_0_TRACE_FIFO_VALID_DATA                                              (0x1<<4) // Trace FIFO contains at least one valid data (GRC rd/wr access).
33156     #define GRC_REG_INT_STS_CLR_0_TRACE_FIFO_VALID_DATA_SHIFT                                        4
33157 #define GRC_REG_PRTY_MASK_H_0                                                                        0x050204UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33158     #define GRC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
33159     #define GRC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            0
33160     #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0                                            (0x1<<0) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
33161     #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                      0
33162     #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
33163     #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                      1
33164     #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
33165     #define GRC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                         1
33166     #define GRC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: GRC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
33167     #define GRC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            1
33168 #define GRC_REG_MEM_ECC_EVENTS                                                                       0x050210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
33169 #define GRC_REG_MEM003_I_MEM_DFT_K2                                                                  0x050218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance grc.i_trace_fifo.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
33170 #define GRC_REG_MEM002_I_MEM_DFT_K2                                                                  0x05021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance grc.i_protection_override_window_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
33171 #define GRC_REG_MEM001_I_MEM_DFT_K2                                                                  0x050220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance grc.i_dbgsyn_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
33172 #define GRC_REG_TIMEOUT_VAL                                                                          0x050400UL //Access:RW   DataWidth:0x20  The count value for the timeout timer. The count is done in common main clock domain.  Chips: BB_A0 BB_B0 K2
33173 #define GRC_REG_TIMEOUT_EN                                                                           0x050404UL //Access:RW   DataWidth:0x1   Setting this bit enables a timer in the GRC block to timeout any access that does not finish within GRC_REGISTERS_TIMOUT_VAL.TIMEOUT_VAL cycles. When this bit is cleared the timeout is disabled.  Chips: BB_A0 BB_B0 K2
33174 #define GRC_REG_ECO_RESERVED                                                                         0x050408UL //Access:RW   DataWidth:0x8   For ECOs.  Chips: BB_A0 BB_B0 K2
33175 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW                                                         0x05040cUL //Access:RW   DataWidth:0x5   Number of valid windows in the GRC_REG_PROTECTION_OVERRIDE_WINDOW memory. The number can be from 0 (no valid window) to 20 (20 valid windows). The valid windows should be consecutive. Each valid window can be applicable for rd access, wr access, or both.  Chips: BB_A0 BB_B0 K2
33176 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW                                                           0x050500UL //Access:WB   DataWidth:0x37  A protection override window that enables to override the protection levels of a range of GRC addresses. There are 20 windows. Each valid window can be applicable for rd access, wr access, or both. Each window contains the following fields: Bits [22:0]:  Base address 4 bytes resolution). The GRC address which the window starts at. Bits [46:23]: Window size. The size of the window in the GRC space (for a window of one address needs to write value of 0x1). Bit  [47]: Rd access. If = 1, the window is applicable for rd access. If = 0, the window is not applicable for rd access. Bit  [48]: Wr access. If = 1, the window is applicable for wr access. If = 1, the window is not applicable for wr access. Bits [51:49]: Protection value rd access. The new protection value assigned to the range in rd access (if Rd access = 1). Bits [54:52]: Protection value wr access. The new protection value assigned to the range in wr access (if Wr access = 1).  Chips: BB_A0 BB_B0 K2
33177 #define GRC_REG_PROTECTION_OVERRIDE_WINDOW_SIZE                                                      40
33178 #define UMAC_REG_MIFG_K2                                                                             0x051004UL //Access:RW   DataWidth:0x8   Programmable field representing the minimum number of bits of IFG to enforce between frames.  A frame whose IFG is less than that programmed is dropped.  The default setting is 0x50 (80d).  Chips: K2
33179 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_A0                                                               0x051004UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0
33180 #define UMAC_REG_IPG_HD_BKP_CNTL_BB_B0                                                               0x051004UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_B0
33181     #define UMAC_REG_IPG_HD_BKP_CNTL_HD_FC_ENA                                                       (0x1<<0) // When set; enables back-pressure in half-duplex mode.
33182     #define UMAC_REG_IPG_HD_BKP_CNTL_HD_FC_ENA_SHIFT                                                 0
33183     #define UMAC_REG_IPG_HD_BKP_CNTL_HD_FC_BKOFF_OK                                                  (0x1<<1) // Register Bit 1 refers to the application of backoff algorithm during HD backpressure.
33184     #define UMAC_REG_IPG_HD_BKP_CNTL_HD_FC_BKOFF_OK_SHIFT                                            1
33185     #define UMAC_REG_IPG_HD_BKP_CNTL_IPG_CONFIG_RX                                                   (0x1f<<2) // The programmable Rx IPG below which the packets received are dropped graciously. The value is in Bytes for 1/2.5G and Nibbles for 10/100M.
33186     #define UMAC_REG_IPG_HD_BKP_CNTL_IPG_CONFIG_RX_SHIFT                                             2
33187 #define UMAC_REG_COMMAND_CONFIG                                                                      0x051008UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
33188     #define UMAC_REG_COMMAND_CONFIG_PORT_ENB_SYS                                                     (0x1<<0) // Enable/Disable MAC path for data packets.
33189     #define UMAC_REG_COMMAND_CONFIG_PORT_ENB_SYS_SHIFT                                               0
33190     #define UMAC_REG_COMMAND_CONFIG_PORT_SPEED                                                       (0x7<<2) // Set MAC speed. used to set the core mode of operation: 000: Enable 10Mbps  Ethernet mode (SGMII) 001: Enable 100Mbps Ethernet mode (SGMII) 010: Enable Gigabit Ethernet mode (SGMII) 101: Enable RMII mode
33191     #define UMAC_REG_COMMAND_CONFIG_PORT_SPEED_SHIFT                                                 2
33192     #define UMAC_REG_COMMAND_CONFIG_PCRCE                                                            (0x1<<5) // globally pad frame, and append CRC.
33193     #define UMAC_REG_COMMAND_CONFIG_PCRCE_SHIFT                                                      5
33194     #define UMAC_REG_COMMAND_CONFIG_CRCE                                                             (0x1<<6) // globally append CRC.
33195     #define UMAC_REG_COMMAND_CONFIG_CRCE_SHIFT                                                       6
33196     #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_TX                                                      (0x1<<16) // Transmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
33197     #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_TX_SHIFT                                                16
33198     #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_RX                                                      (0x1<<19) // When set, frames received by the PHY are transmitted. Received packet by the PHY are Transmitted by the PHY (remote  loopback); when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
33199     #define UMAC_REG_COMMAND_CONFIG_LOOPBACK_RX_SHIFT                                                19
33200     #define UMAC_REG_COMMAND_CONFIG_TX_ENA                                                           (0x1<<0) // Enable/Disable MAC transmit path for data packets & pause/pfc packets sent in the normal data path. Pause/pfc packets generated internally are allowed if ignore_tx_pause is not set. When set to '0' (Reset value); the MAC transmit function is disable. When set to '1'; the MAC transmit function is enabled.
33201     #define UMAC_REG_COMMAND_CONFIG_TX_ENA_SHIFT                                                     0
33202     #define UMAC_REG_COMMAND_CONFIG_RX_ENA                                                           (0x1<<1) // Enable/Disable MAC receive path. When set to '0' (Reset value); the MAC receive function is disable. When set to '1'; the MAC receive function is enabled.
33203     #define UMAC_REG_COMMAND_CONFIG_RX_ENA_SHIFT                                                     1
33204     #define UMAC_REG_COMMAND_CONFIG_ETH_SPEED                                                        (0x3<<2) // Set MAC speed. Ignored when the register bit ENA_EXT_CONFIG is set to '1'. When the Register bit ENA_EXT_CONFIG is set to '0'; used to set the core mode of operation: 00: Enable 10Mbps Ethernet mode 01: Enable 100Mbps Ethernet mode 10: Enable Gigabit Ethernet mode 11: Enable 2.5Gigabit Ethernet mode.
33205     #define UMAC_REG_COMMAND_CONFIG_ETH_SPEED_SHIFT                                                  2
33206     #define UMAC_REG_COMMAND_CONFIG_PROMIS_EN                                                        (0x1<<4) // Enable/Disable MAC promiscuous operation. When asserted (Set to '1'); all frames are received without Unicast address filtering.
33207     #define UMAC_REG_COMMAND_CONFIG_PROMIS_EN_SHIFT                                                  4
33208     #define UMAC_REG_COMMAND_CONFIG_PAD_EN                                                           (0x1<<5) // Enable/Disable Frame Padding. If enabled (Set to '1'); then padding is removed from the received frame before it is transmitted to the user application. If disabled (set to reset value '0'); then no padding is removed on receive by the MAC. This bit has no effect on Tx padding and hence Transmit always pad runts to guarantee a minimum frame size of 64 octets.
33209     #define UMAC_REG_COMMAND_CONFIG_PAD_EN_SHIFT                                                     5
33210     #define UMAC_REG_COMMAND_CONFIG_CRC_FWD                                                          (0x1<<6) // Terminate/Forward Received CRC. If enabled (1) the CRC field of received frames are transmitted to the user application. If disabled (Set to reset value '0') the CRC field is stripped from the frame. Note: If padding function (Bit PAD_EN set to '1') is enabled. CRC_FWD is ignored and the CRC field is checked and always terminated and removed.
33211     #define UMAC_REG_COMMAND_CONFIG_CRC_FWD_SHIFT                                                    6
33212     #define UMAC_REG_COMMAND_CONFIG_PAUSE_FWD                                                        (0x1<<7) // Terminate/Forward Pause Frames. If enabled (Set to '1') pause frames are forwarded to the user application. If disabled (Set to reset value '0'); pause frames are terminated and discarded in the MAC.
33213     #define UMAC_REG_COMMAND_CONFIG_PAUSE_FWD_SHIFT                                                  7
33214     #define UMAC_REG_COMMAND_CONFIG_PAUSE_IGNORE                                                     (0x1<<8) // Ignore Pause Frame Quanta. If enabled (Set to '1') received pause frames are ignored by the MAC. When disabled (Set to reset value '0') the transmit process is stopped for the amount of time specified in the pause quanta received within the pause frame.
33215     #define UMAC_REG_COMMAND_CONFIG_PAUSE_IGNORE_SHIFT                                               8
33216     #define UMAC_REG_COMMAND_CONFIG_TX_ADDR_INS                                                      (0x1<<9) // Set MAC address on transmit. If enabled (Set to '1') the MAC overwrites the source MAC address with the programmed MAC address in registers MAC_0 and MAC_1. If disabled (Set to reset value '0'); the source MAC address received from the transmit application transmitted is not modified by the MAC.
33217     #define UMAC_REG_COMMAND_CONFIG_TX_ADDR_INS_SHIFT                                                9
33218     #define UMAC_REG_COMMAND_CONFIG_HD_ENA                                                           (0x1<<10) // Half duplex enable. When set to '1'; enables half duplex mode; when set to '0'; the MAC operates in full duplex mode. Ignored at ethernet speeds 1G/2.5G or when the register ENA_EXT_CONFIG is set to '1'.
33219     #define UMAC_REG_COMMAND_CONFIG_HD_ENA_SHIFT                                                     10
33220     #define UMAC_REG_COMMAND_CONFIG_RX_LOW_LATENCY_EN                                                (0x1<<11) // This works only when runt filter is disabled. It reduces the receive latency by 48 MAC clock time.
33221     #define UMAC_REG_COMMAND_CONFIG_RX_LOW_LATENCY_EN_SHIFT                                          11
33222     #define UMAC_REG_COMMAND_CONFIG_OVERFLOW_EN                                                      (0x1<<12) // If set; enables Rx FIFO overflow logic. In this case; the RXFIFO_STAT[1] register bit is not operational (always set to 0). If cleared; disables RX FIFO overflow logic. In this case; the RXFIFO_STAT[1] register bit is operational (Sticky set when overrun occurs; clearable only by SW_Reset).
33223     #define UMAC_REG_COMMAND_CONFIG_OVERFLOW_EN_SHIFT                                                12
33224     #define UMAC_REG_COMMAND_CONFIG_SW_RESET                                                         (0x1<<13) // Software Reset Command. When asserted; the TX and RX are disabled. Config registers are not affected by sw reset. Write a 0 to de-assert the sw reset.
33225     #define UMAC_REG_COMMAND_CONFIG_SW_RESET_SHIFT                                                   13
33226     #define UMAC_REG_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN                                              (0x1<<14) // Corrupt Tx FCS; on underrun; when set to '1'; No FCS corruption when set to '0' (Reset value).
33227     #define UMAC_REG_COMMAND_CONFIG_FCS_CORRUPT_URUN_EN_SHIFT                                        14
33228     #define UMAC_REG_COMMAND_CONFIG_LOOP_ENA                                                         (0x1<<15) // Enable GMII/MII loopback when set to '1'; normal operation when set to '0' (Reset value).
33229     #define UMAC_REG_COMMAND_CONFIG_LOOP_ENA_SHIFT                                                   15
33230     #define UMAC_REG_COMMAND_CONFIG_MAC_LOOP_CON                                                     (0x1<<16) // Transmit packets to PHY while in MAC local loopback; when set to '1'; otherwise transmit to PHY is disabled (normal operation); when set to '0' (Reset value).
33231     #define UMAC_REG_COMMAND_CONFIG_MAC_LOOP_CON_SHIFT                                               16
33232     #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_TX                                                   (0x1<<17) // If set; enables the SW programmed Tx pause capability config bits to overwrite the auto negotiated Tx pause capabilities when ena_ext_config (autoconfig) is set. If cleared; and when ena_ext_config (autoconfig) is set; then SW programmed Tx pause capability config bits has no effect over auto negotiated capabilities.
33233     #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_TX_SHIFT                                             17
33234     #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_RX                                                   (0x1<<18) // If set; enables the SW programmed Rx pause capability config bits to overwrite the auto negotiated Rx pause capabilities when ena_ext_config (autoconfig) is set. If cleared; and when ena_ext_config (autoconfig) is set; then SW programmed Rx pause capability config bits has no effect over auto negotiated capabilities.
33235     #define UMAC_REG_COMMAND_CONFIG_SW_OVERRIDE_RX_SHIFT                                             18
33236     #define UMAC_REG_COMMAND_CONFIG_EN_INTERNAL_TX_CRS                                               (0x1<<21) // If enabled; then CRS input to Unimac is ORed with tds[8] (tx data valid output). This is helpful when TX CRS is disabled inside PHY.
33237     #define UMAC_REG_COMMAND_CONFIG_EN_INTERNAL_TX_CRS_SHIFT                                         21
33238     #define UMAC_REG_COMMAND_CONFIG_ENA_EXT_CONFIG                                                   (0x1<<22) // Enable Configuration with External Pins. When set to '0' (Reset value) the Core speed and Mode is programmed with the register bits ETH_SPEED(1:0) and HD_ENA. When set to '1'; the Core is configured with the pins set_speed(1:0) and set_duplex.
33239     #define UMAC_REG_COMMAND_CONFIG_ENA_EXT_CONFIG_SHIFT                                             22
33240     #define UMAC_REG_COMMAND_CONFIG_CNTL_FRM_ENA                                                     (0x1<<23) // MAC Control Frame Enable. When set to '1'; MAC Control frames with any Opcode other than 0x0001 are accepted and forward to the Client interface. When set to '0' (Reset value); MAC Control frames with any Opcode other than 0x0001 are silently discarded.
33241     #define UMAC_REG_COMMAND_CONFIG_CNTL_FRM_ENA_SHIFT                                               23
33242     #define UMAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK                                                    (0x1<<24) // Payload Length Check Disable. When set to '0'; the Core checks the frame's payload length with the Frame Length/Type field; when set to '1'(Reset value); the payload length check is disabled.
33243     #define UMAC_REG_COMMAND_CONFIG_NO_LGTH_CHECK_SHIFT                                              24
33244     #define UMAC_REG_COMMAND_CONFIG_LINE_LOOPBACK                                                    (0x1<<25) // Enable Line Loopback i.e. MAC FIFO side loopback; when set to '1'; normal operation when set to '0' (Reset value).
33245     #define UMAC_REG_COMMAND_CONFIG_LINE_LOOPBACK_SHIFT                                              25
33246     #define UMAC_REG_COMMAND_CONFIG_RX_ERR_DISC                                                      (0x1<<26) // Receive Errored Frame Discard Enable. When set to '1'; any frame received with an error is discarded in the Core and not forwarded to the Client interface. When set to '0'; errored Frames are forwarded to the Client interface with ff_rx_err asserted. It is recommended to set RX_ERR_DISC to '1' only when Store and Forward operation is enabled on the Core Receive FIFO Receive FIFO Section full threshold set to 0).
33247     #define UMAC_REG_COMMAND_CONFIG_RX_ERR_DISC_SHIFT                                                26
33248     #define UMAC_REG_COMMAND_CONFIG_PRBL_ENA                                                         (0x1<<27) // Reserved.
33249     #define UMAC_REG_COMMAND_CONFIG_PRBL_ENA_SHIFT                                                   27
33250     #define UMAC_REG_COMMAND_CONFIG_IGNORE_TX_PAUSE                                                  (0x1<<28) // Ignores the back pressure signaling from the system and hence no Tx pause generation; when set.
33251     #define UMAC_REG_COMMAND_CONFIG_IGNORE_TX_PAUSE_SHIFT                                            28
33252     #define UMAC_REG_COMMAND_CONFIG_OOB_EFC_EN                                                       (0x1<<29) // If set then out-of-band egress flow control is enabled. When this bit is set and input pin ext_tx_flow_control is enabled then data frame trasmission is stopped; whereas Pause & PFC frames are transmitted normally. This operation is similar to halting the transmit datapath due to the reception of a Pause Frame with non-zero timer value; and is used in applications where the flow control information is exchanged out of band. Enabling or disabling this bit has no effect on regular Rx_pause pkt based egress flow control.
33253     #define UMAC_REG_COMMAND_CONFIG_OOB_EFC_EN_SHIFT                                                 29
33254     #define UMAC_REG_COMMAND_CONFIG_RUNT_FILTER_DIS                                                  (0x1<<30) // When set; disable runt filtering.
33255     #define UMAC_REG_COMMAND_CONFIG_RUNT_FILTER_DIS_SHIFT                                            30
33256 #define UMAC_REG_MAC_ADDR0                                                                           0x05100cUL //Access:RW   DataWidth:0x20  Register Bit 0 refers to Bit 16 of the MAC address; Bit 1 refers to bit 17 of the MAC address etc.  Chips: BB_A0 BB_B0
33257 #define UMAC_REG_MAC_ADDR1                                                                           0x051010UL //Access:RW   DataWidth:0x10  Register Bit 0 refers to Bit 0 of the MAC address; Register Bit 1 refers to Bit 1 of the MAC address etc. Bits 16 to 31 are reserved.  Chips: BB_A0 BB_B0
33258 #define UMAC_REG_MAXF_K2                                                                             0x051014UL //Access:RW   DataWidth:0x10  Defines a 16-Bit maximum frame length used by the MAC receive logic to check frames.  Chips: K2
33259 #define UMAC_REG_MAXFR_BB_A0                                                                         0x051014UL //Access:RW   DataWidth:0xe   Defines a 14-Bit maximum frame length used by the MAC receive logic to check frames.  Chips: BB_A0
33260 #define UMAC_REG_MAXFR_BB_B0                                                                         0x051014UL //Access:RW   DataWidth:0xe   Defines a 14-Bit maximum frame length used by the MAC receive logic to check frames.  Chips: BB_B0
33261 #define UMAC_REG_STAD2                                                                               0x051018UL //Access:RW   DataWidth:0x10  16-Bit value; sets; in increment of 512 Ethernet bit times; the pause quanta used in each Pause Frame sent to the remote Ethernet device.  Chips: BB_A0 BB_B0
33262 #define UMAC_REG_SFD_OFFSET                                                                          0x051040UL //Access:RW   DataWidth:0x4   Defines the length of the EFM preamble between 5 and 15 Bytes. When set to 0; 1; 2; 3 or 4; the Preamble EFM length is set to 5 Bytes.  Chips: BB_A0 BB_B0
33263 #define UMAC_REG_MAC_MODE                                                                            0x051044UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33264     #define UMAC_REG_MAC_MODE_PAUSE_RX_EN                                                            (0x1<<3) // Rx Flow. Setting this bit will cause the receive MAC control to detect and act on PAUSE flow control frames. Clearing this bit causes the receive MAC control to ignore PAUSE flow control frames.
33265     #define UMAC_REG_MAC_MODE_PAUSE_RX_EN_SHIFT                                                      3
33266     #define UMAC_REG_MAC_MODE_PAUSE_TX_EN                                                            (0x1<<4) // Tx Flow. Setting this bit will allow the transmit MAC control to send PAUSE flow control frames when requested by the system. Clearing this bit prevents the transmit MAC control from sending flow control frames.
33267     #define UMAC_REG_MAC_MODE_PAUSE_TX_EN_SHIFT                                                      4
33268     #define UMAC_REG_MAC_MODE_MAC_SPEED                                                              (0x3<<0) // MAC Speed. 00: 10Mbps Ethernet Mode enabled 01: 100Mbps Ethernet Mode enabled 10: Gigabit Ethernet Mode enabled 11: 2.5Gigabit Ethernet Mode enabled.
33269     #define UMAC_REG_MAC_MODE_MAC_SPEED_SHIFT                                                        0
33270     #define UMAC_REG_MAC_MODE_MAC_DUPLEX                                                             (0x1<<2) // MAC Duplex. 0: Full Duplex Mode enabled 1: Half Duplex Mode enabled.
33271     #define UMAC_REG_MAC_MODE_MAC_DUPLEX_SHIFT                                                       2
33272     #define UMAC_REG_MAC_MODE_MAC_RX_PAUSE                                                           (0x1<<3) // MAC Pause Enabled in Receive. 0: MAC Pause Disabled in Receive 1: MAC Pause Enabled in Receive.
33273     #define UMAC_REG_MAC_MODE_MAC_RX_PAUSE_SHIFT                                                     3
33274     #define UMAC_REG_MAC_MODE_MAC_TX_PAUSE                                                           (0x1<<4) // MAC Pause Enabled in Transmit. 0: MAC Pause Disabled in Transmit 1: MAC Pause Enabled in Transmit.
33275     #define UMAC_REG_MAC_MODE_MAC_TX_PAUSE_SHIFT                                                     4
33276     #define UMAC_REG_MAC_MODE_LINK_STATUS                                                            (0x1<<5) // Link Status Indication. Set to '0'; when link_status input is low. Set to '1'; when link_status input is High.
33277     #define UMAC_REG_MAC_MODE_LINK_STATUS_SHIFT                                                      5
33278 #define UMAC_REG_TAG_0                                                                               0x051048UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0
33279     #define UMAC_REG_TAG_0_FRM_TAG_0                                                                 (0xffff<<0) // Outer tag of the programmable VLAN tag.
33280     #define UMAC_REG_TAG_0_FRM_TAG_0_SHIFT                                                           0
33281     #define UMAC_REG_TAG_0_CONFIG_OUTER_TPID_ENABLE                                                  (0x1<<16) // If cleared then disable outer TPID detection.
33282     #define UMAC_REG_TAG_0_CONFIG_OUTER_TPID_ENABLE_SHIFT                                            16
33283 #define UMAC_REG_TAG_1                                                                               0x05104cUL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0
33284     #define UMAC_REG_TAG_1_FRM_TAG_1                                                                 (0xffff<<0) // inner tag of the programmable VLAN tag.
33285     #define UMAC_REG_TAG_1_FRM_TAG_1_SHIFT                                                           0
33286     #define UMAC_REG_TAG_1_CONFIG_INNER_TPID_ENABLE                                                  (0x1<<16) // If cleared then disable inner TPID detection.
33287     #define UMAC_REG_TAG_1_CONFIG_INNER_TPID_ENABLE_SHIFT                                            16
33288 #define UMAC_REG_RX_PAUSE_QUANTA_SCALE                                                               0x051050UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0
33289     #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_VALUE                                               (0xffff<<0) // The pause timer is loaded with the value obtained after adding or subtracting the scale_value from the received pause quanta.
33290     #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_VALUE_SHIFT                                         0
33291     #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL                                             (0x1<<16) // If clear; then subtract the scale_value from the received pause quanta. If set; then add the scale_value from the received pause quanta.
33292     #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_CONTROL_SHIFT                                       16
33293     #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_FIX                                                 (0x1<<17) // If set; then receive pause quanta is ignored and a fixed quanta value programmed in SCALE_VALUE is loaded into the pause timer. If set; then SCALE_CONTROL is ignored. If cleared; then SCALE_CONTROL takes into effect.
33294     #define UMAC_REG_RX_PAUSE_QUANTA_SCALE_SCALE_FIX_SHIFT                                           17
33295 #define UMAC_REG_TX_PREAMBLE                                                                         0x051054UL //Access:RW   DataWidth:0x3   Set the transmit preamble excluding SFD to be programmable from min of 2 bytes to the max allowable of 7 bytes; with granularity of 1 byte.  Chips: BB_A0 BB_B0
33296 #define UMAC_REG_IPGT_K2                                                                             0x05105cUL //Access:RW   DataWidth:0x8   Programmable field representing the IPG between Back-to-Back packets. This is the IPG parameter used exclusively in Full-Duplex mode when two transmit packets are sent back-to-back. Set this field to the number of bits of IPG desired. The default setting of 0x60 (96d) represents the minimum IPG of 96 bits.  Chips: K2
33297 #define UMAC_REG_TX_IPG_LENGTH_BB_A0                                                                 0x05105cUL //Access:RW   DataWidth:0x7   Set the Transmit minimum IPG from 8 to 64 Byte-times. If a value below 8 or above 64 is programmed; the minimum IPG is set to 12 byte-times.  Chips: BB_A0
33298 #define UMAC_REG_TX_IPG_LENGTH_BB_B0                                                                 0x05105cUL //Access:RW   DataWidth:0x7   Set the Transmit minimum IPG from 8 to 64 Byte-times. If a value below 8 or above 64 is programmed; the minimum IPG is set to 12 byte-times.  Chips: BB_B0
33299 #define UMAC_REG_PFC_XOFF_TIMER                                                                      0x051060UL //Access:RW   DataWidth:0x10  Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).  Chips: BB_A0 BB_B0
33300 #define UMAC_REG_UMAC_EEE_CTRL                                                                       0x051064UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0
33301     #define UMAC_REG_UMAC_EEE_CTRL_EEE_EN                                                            (0x1<<3) // If set; the TX LPI policy control engine is enabled and the MAC inserts LPI_idle codes if the link is idle. The rx_lpi_detect assertion is independent of this configuration. Reset default depends on EEE_en_strap input; which if tied to 1; defaults to enabled; otherwise if tied to 0; defaults to disabled.
33302     #define UMAC_REG_UMAC_EEE_CTRL_EEE_EN_SHIFT                                                      3
33303     #define UMAC_REG_UMAC_EEE_CTRL_RX_FIFO_CHECK                                                     (0x1<<4) // If enabled; lpi_rx_detect is set whenever the LPI_IDLES are being received on the RX line and Unimac Rx FIFO is empty. By default; lpi_rx_detect is set only when whenever the LPI_IDLES are being received on the RX line.
33304     #define UMAC_REG_UMAC_EEE_CTRL_RX_FIFO_CHECK_SHIFT                                               4
33305     #define UMAC_REG_UMAC_EEE_CTRL_EEE_TXCLK_DIS                                                     (0x1<<5) // If enabled; UNIMAC will shut down TXCLK to PHY; when in LPI state.
33306     #define UMAC_REG_UMAC_EEE_CTRL_EEE_TXCLK_DIS_SHIFT                                               5
33307     #define UMAC_REG_UMAC_EEE_CTRL_DIS_EEE_10M                                                       (0x1<<6) // When this bit is set and link is established at 10Mbps; LPI is not supported (saving is achieved by reduced PHY's output swing). UNIMAC ignores EEE feature on both Tx & Rx in 10Mbps. When cleared; Unimac doesn't differentiate between speeds for EEE feature.
33308     #define UMAC_REG_UMAC_EEE_CTRL_DIS_EEE_10M_SHIFT                                                 6
33309     #define UMAC_REG_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE                                           (0x1<<7) // When set to 1; enables LP_IDLE Prediction. When set to 0; disables LP_IDLE Prediction.
33310     #define UMAC_REG_UMAC_EEE_CTRL_LP_IDLE_PREDICTION_MODE_SHIFT                                     7
33311 #define UMAC_REG_MII_EEE_LPI_TIMER                                                                   0x051068UL //Access:RW   DataWidth:0x20  This is the duration for which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register is meant for 10/100 Mbps speed.  Chips: BB_A0 BB_B0
33312 #define UMAC_REG_GMII_EEE_LPI_TIMER                                                                  0x05106cUL //Access:RW   DataWidth:0x20  This is the duration for which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI State. The decrement unit is 1 micro-second. This register is meant for 1000 Mbps speed.  Chips: BB_A0 BB_B0
33313 #define UMAC_REG_EEE_REF_COUNT                                                                       0x051070UL //Access:RW   DataWidth:0x10  This field controls clock divider used to generate ~1us reference pulses used by EEE timers. It specifies integer number of timer clock cycles contained within 1us. We may consider having 0.5us reference; as timeout values in 802.3az/D1.3 are not always integer number of 1us.  Chips: BB_A0 BB_B0
33314 #define UMAC_REG_RX_IPG_INVAL                                                                        0x051078UL //Access:RW   DataWidth:0x1   Debug status; set if MAC receives an IPG less than programmed RX IPG or less than four bytes. Sticky bit. Clears when SW writes 0 into the field or by sw_reset.  Chips: BB_A0 BB_B0
33315 #define UMAC_REG_THRESHOLD_VALUE                                                                     0x05107cUL //Access:RW   DataWidth:0x10  If LPI_Prediction is enabled then this register defines the number of IDLEs to be received by the UniMAC before allowing LP_IDLE to be sent to Link Partner.  Chips: BB_A0 BB_B0
33316 #define UMAC_REG_MII_EEE_WAKE_TIMER                                                                  0x051080UL //Access:RW   DataWidth:0x10  This is the duration for which MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmission. The decrement unit is 1 micro-second. This register is meant for 10/100 Mbps speed.  Chips: BB_A0 BB_B0
33317 #define UMAC_REG_GMII_EEE_WAKE_TIMER                                                                 0x051084UL //Access:RW   DataWidth:0x10  This is the duration for which MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmission. The decrement unit is 1 micro-second. This register is meant for 1000 Mbps speed.  Chips: BB_A0 BB_B0
33318 #define UMAC_REG_UMAC_REV_ID                                                                         0x051088UL //Access:RW   DataWidth:0x18  Multi Field Register.  Chips: BB_A0 BB_B0
33319     #define UMAC_REG_UMAC_REV_ID_PATCH                                                               (0xff<<0) // Unimac revision patch number.
33320     #define UMAC_REG_UMAC_REV_ID_PATCH_SHIFT                                                         0
33321     #define UMAC_REG_UMAC_REV_ID_REVISION_ID_MINOR                                                   (0xff<<8) // Unimac version id field after decimal.
33322     #define UMAC_REG_UMAC_REV_ID_REVISION_ID_MINOR_SHIFT                                             8
33323     #define UMAC_REG_UMAC_REV_ID_REVISION_ID_MAJOR                                                   (0xff<<16) // Unimac version id field before decimal.
33324     #define UMAC_REG_UMAC_REV_ID_REVISION_ID_MAJOR_SHIFT                                             16
33325 #define UMAC_REG_TX_IPG_LENGTH1                                                                      0x05108cUL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: K2
33326     #define UMAC_REG_TX_IPG_LENGTH1_IPGR1                                                            (0x7f<<16) // Non Back-to-Back Transmit IPG part 1 (carrier sense window).
33327     #define UMAC_REG_TX_IPG_LENGTH1_IPGR1_SHIFT                                                      16
33328     #define UMAC_REG_TX_IPG_LENGTH1_IPGR2                                                            (0x7f<<24) // Non Back-to-Back Transmit IPG part 2.
33329     #define UMAC_REG_TX_IPG_LENGTH1_IPGR2_SHIFT                                                      24
33330 #define UMAC_REG_ECO_RESERVED                                                                        0x051090UL //Access:RW   DataWidth:0x20  This is unused register for future ECOs.  Chips: K2
33331 #define UMAC_REG_DBG_SELECT                                                                          0x051094UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
33332 #define UMAC_REG_DBG_DWORD_ENABLE                                                                    0x051098UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
33333 #define UMAC_REG_DBG_SHIFT                                                                           0x05109cUL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
33334 #define UMAC_REG_DBG_FORCE_VALID                                                                     0x0510a0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
33335 #define UMAC_REG_DBG_FORCE_FRAME                                                                     0x0510a4UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
33336 #define UMAC_REG_DBG_OUT_DATA                                                                        0x0510c0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
33337 #define UMAC_REG_DBG_OUT_DATA_SIZE                                                                   8
33338 #define UMAC_REG_DBG_OUT_VALID                                                                       0x0510e0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
33339 #define UMAC_REG_DBG_OUT_FRAME                                                                       0x0510e4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
33340 #define UMAC_REG_INT_STS                                                                             0x051180UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: K2
33341     #define UMAC_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
33342     #define UMAC_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
33343     #define UMAC_REG_INT_STS_TX_OVERFLOW                                                             (0x1<<1) // TX fifo overflow
33344     #define UMAC_REG_INT_STS_TX_OVERFLOW_SHIFT                                                       1
33345 #define UMAC_REG_INT_MASK                                                                            0x051184UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: K2
33346     #define UMAC_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: UMAC_REG_INT_STS.ADDRESS_ERROR .
33347     #define UMAC_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
33348     #define UMAC_REG_INT_MASK_TX_OVERFLOW                                                            (0x1<<1) // This bit masks, when set, the Interrupt bit: UMAC_REG_INT_STS.TX_OVERFLOW .
33349     #define UMAC_REG_INT_MASK_TX_OVERFLOW_SHIFT                                                      1
33350 #define UMAC_REG_INT_STS_WR                                                                          0x051188UL //Access:WR   DataWidth:0x2   Multi Field Register.  Chips: K2
33351     #define UMAC_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
33352     #define UMAC_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
33353     #define UMAC_REG_INT_STS_WR_TX_OVERFLOW                                                          (0x1<<1) // TX fifo overflow
33354     #define UMAC_REG_INT_STS_WR_TX_OVERFLOW_SHIFT                                                    1
33355 #define UMAC_REG_INT_STS_CLR                                                                         0x05118cUL //Access:RC   DataWidth:0x2   Multi Field Register.  Chips: K2
33356     #define UMAC_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
33357     #define UMAC_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
33358     #define UMAC_REG_INT_STS_CLR_TX_OVERFLOW                                                         (0x1<<1) // TX fifo overflow
33359     #define UMAC_REG_INT_STS_CLR_TX_OVERFLOW_SHIFT                                                   1
33360 #define UMAC_REG_PAUSE_TYPE_K2                                                                       0x051300UL //Access:RW   DataWidth:0x10  Pause Type.  This value is inserted into the Type/Length field of the Pause frames generated by the MAC and used to validate Pause frames received by the MAC.  Chips: K2
33361 #define UMAC_REG_PFC_ETH_TYPE_BB_A0                                                                  0x051300UL //Access:RW   DataWidth:0x10  These 16 bits are for programmable ethertype in PFC. Since PFC is not standardized yet; the ethertype must be programmable to make sure that when it gets standardized; we can be standards compliant.  Chips: BB_A0
33362 #define UMAC_REG_PFC_ETH_TYPE_BB_B0                                                                  0x051300UL //Access:RW   DataWidth:0x10  These 16 bits are for programmable ethertype in PFC. Since PFC is not standardized yet; the ethertype must be programmable to make sure that when it gets standardized; we can be standards compliant.  Chips: BB_B0
33363 #define UMAC_REG_PAUSE_OPCODE_K2                                                                     0x051304UL //Access:RW   DataWidth:0x10  Pause Frame Opcode.  This value is inserted into the opcode field of the Pause frames generated by the MAC and used to validate Pause frames received by the MAC.  Note; the default value is for standard pause.  Chips: K2
33364 #define UMAC_REG_PFC_OPCODE_BB_A0                                                                    0x051304UL //Access:RW   DataWidth:0x10  These 16 bits are for opcode. Since PFC is not standardized yet; the opcode must be programmable to make sure that when it gets standardized; we can be standards compliant.  Chips: BB_A0
33365 #define UMAC_REG_PFC_OPCODE_BB_B0                                                                    0x051304UL //Access:RW   DataWidth:0x10  These 16 bits are for opcode. Since PFC is not standardized yet; the opcode must be programmable to make sure that when it gets standardized; we can be standards compliant.  Chips: BB_B0
33366 #define UMAC_REG_PAUSE_DEST_ADDR_LO_K2                                                               0x051308UL //Access:RW   DataWidth:0x20  Pause frame Destination address.  This field is inserted into the destination address field of the MAC generated pause frames and is used to compare against the destination address of received packets.  The remaining 16 bits are contained in the next register.  By default, it contains the reserved multicast address of the MAC control frame.  Chips: K2
33367 #define UMAC_REG_PFC_MACDA_0_BB_A0                                                                   0x051308UL //Access:RW   DataWidth:0x20  Lower 32 bits of programmable DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when it gets standardized; we can be standards compliant.  Chips: BB_A0
33368 #define UMAC_REG_PFC_MACDA_0_BB_B0                                                                   0x051308UL //Access:RW   DataWidth:0x20  Lower 32 bits of programmable DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when it gets standardized; we can be standards compliant.  Chips: BB_B0
33369 #define UMAC_REG_PAUSE_DEST_ADDR_HI_K2                                                               0x05130cUL //Access:RW   DataWidth:0x10  Pause frame Destination address.  This field is inserted into the destination address field of the MAC generated pause frames and is used to compare against the destination address of received packets.  The remaining 32 bits are contained in the previous register.  By default, it contains the reserved multicast address of the MAC control frame.  Chips: K2
33370 #define UMAC_REG_PFC_MACDA_1_BB_A0                                                                   0x05130cUL //Access:RW   DataWidth:0x10  Upper 16 bits of programmable DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when it gets standardized; we can be standards compliant.  Chips: BB_A0
33371 #define UMAC_REG_PFC_MACDA_1_BB_B0                                                                   0x05130cUL //Access:RW   DataWidth:0x10  Upper 16 bits of programmable DA for PPP. Since PPP is not standardized yet; the DA must be programmable to make sure that when it gets standardized; we can be standards compliant.  Chips: BB_B0
33372 #define UMAC_REG_PAUSE_DEST_ADDR_1_LO_K2                                                             0x051310UL //Access:RW   DataWidth:0x20  Pause frame Destination address.  This field is used to compare against the destination address of received packets.  The remaining 16 bits are contained in the next register.  By default, it contains the reserved multicast address of the MAC control frame.  Chips: K2
33373 #define UMAC_REG_MACSEC_PROG_TX_CRC_BB_A0                                                            0x051310UL //Access:RW   DataWidth:0x20  The transmitted CRC can be corrupted by replacing the FCS of the transmitted frame by the FCS programmed in this register. This is enabled and controlled by MACSEC_CNTRL register.  Chips: BB_A0
33374 #define UMAC_REG_MACSEC_PROG_TX_CRC_BB_B0                                                            0x051310UL //Access:RW   DataWidth:0x20  The transmitted CRC can be corrupted by replacing the FCS of the transmitted frame by the FCS programmed in this register. This is enabled and controlled by MACSEC_CNTRL register.  Chips: BB_B0
33375 #define UMAC_REG_PAUSE_DEST_ADDR_1_HI_K2                                                             0x051314UL //Access:RW   DataWidth:0x10  Pause frame Destination address.  This field is used to compare against the destination address of received packets.  The remaining 32 bits are contained in the previous register.  By default, it contains the reserved multicast address of the MAC control frame.  Chips: K2
33376 #define UMAC_REG_MACSEC_CNTRL_BB_A0                                                                  0x051314UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0
33377 #define UMAC_REG_MACSEC_CNTRL_BB_B0                                                                  0x051314UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_B0
33378     #define UMAC_REG_MACSEC_CNTRL_TX_LAUNCH_EN                                                       (0x1<<0) // Set the bit 0 (Tx_Launch_en) logic 0; if the tx_launch function is to be disabled. If set; then the launch_enable signal assertion/deassertion causes the packet transmit enabled/disabled. The launch_enable is per packet basis.
33379     #define UMAC_REG_MACSEC_CNTRL_TX_LAUNCH_EN_SHIFT                                                 0
33380     #define UMAC_REG_MACSEC_CNTRL_TX_CRC_CORUPT_EN                                                   (0x1<<1) // Setting this field enables the CRC corruption on the transmitted packets. The options of how to corrupt; depends on the field 2 of this register (TX_CRC_PROGRAM). The CRC corruption happens only on the frames for which TXCRCER is asserted by the system.
33381     #define UMAC_REG_MACSEC_CNTRL_TX_CRC_CORUPT_EN_SHIFT                                             1
33382     #define UMAC_REG_MACSEC_CNTRL_TX_CRC_PROGRAM                                                     (0x1<<2) // If CRC corruption feature in enabled (TX_CRC_CORUPT_EN set); then in case where this bit when set; replaces the transmitted FCS with the programmed FCS. When cleared; corrupts the CRC of the transmitted packet internally.
33383     #define UMAC_REG_MACSEC_CNTRL_TX_CRC_PROGRAM_SHIFT                                               2
33384     #define UMAC_REG_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG                                             (0x1<<3) // When this bit is 1; IPG between pause and data frame is as per the original design; i.e.; 13B or 12B; fixed. It should be noted; that as number of preamble bytes reduces from 7; the IPG also increases. When this bit is 0; IPG between pause and data frame is variable and equals programmed IPG or programmed IPG + 1.
33385     #define UMAC_REG_MACSEC_CNTRL_DIS_PAUSE_DATA_VAR_IPG_SHIFT                                       3
33386 #define UMAC_REG_PAUSE_SOURCE_ADDR_LO_K2                                                             0x051318UL //Access:RW   DataWidth:0x20  This register contains the bits [31:0] in the 48-bit MAC address.  The MAC address is used as the SA for automatically generated MAC control pause frames.  Chips: K2
33387 #define UMAC_REG_TS_STATUS_CNTRL_BB_A0                                                               0x051318UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0
33388 #define UMAC_REG_TS_STATUS_CNTRL_BB_B0                                                               0x051318UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0
33389     #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_FULL                                                 (0x1<<0) // Read-only field assertion shows that the transmit timestamp FIFO is full.
33390     #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_FULL_SHIFT                                           0
33391     #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY                                                (0x1<<1) // Read-only field assertion shows that the transmit timestamp FIFO is empty.
33392     #define UMAC_REG_TS_STATUS_CNTRL_TX_TS_FIFO_EMPTY_SHIFT                                          1
33393     #define UMAC_REG_TS_STATUS_CNTRL_WORD_AVAIL                                                      (0x7<<2) // Indicates number of cells filled in the TX timestamp FIFO.
33394     #define UMAC_REG_TS_STATUS_CNTRL_WORD_AVAIL_SHIFT                                                2
33395 #define UMAC_REG_PAUSE_SOURCE_ADDR_HI_K2                                                             0x05131cUL //Access:RW   DataWidth:0x10  This register contains the bits [47:32] in the 48-bit MAC address.  The MAC address is used as the SA for automatically generated MAC control pause frames.  Chips: K2
33396 #define UMAC_REG_TX_TS_DATA_BB_A0                                                                    0x05131cUL //Access:RW   DataWidth:0x20  Every read of this register will fetch out one timestamp value corresponding to the preceding seq_id read from the transmit FIFO. Every 49 bit; val_bit + seq_id + timestamp is read in two steps; i.e.; one read from 0x10f (val_bit + seq_id) followed by another read from 0x1c7 (timestamp). Timestamp read without a preceding seq_id read will fetch stale timestamp value.  Chips: BB_A0
33397 #define UMAC_REG_TX_TS_DATA_BB_B0                                                                    0x05131cUL //Access:RW   DataWidth:0x20  Every read of this register will fetch out one timestamp value corresponding to the preceding seq_id read from the transmit FIFO. Every 49 bit; val_bit + seq_id + timestamp is read in two steps; i.e.; one read from 0x10f (val_bit + seq_id) followed by another read from 0x1c7 (timestamp). Timestamp read without a preceding seq_id read will fetch stale timestamp value.  Chips: BB_B0
33398 #define UMAC_REG_PAUSE_CONTROL                                                                       0x051330UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
33399     #define UMAC_REG_PAUSE_CONTROL_PAUSE_TIME                                                        (0xffff<<0) // If set and a Pause frame is being forced, send a Pause frame with the Pause Time Field specified in rf_omac_pause_time.  If this bit is cleared send a Pause frame with the zero pause time.
33400     #define UMAC_REG_PAUSE_CONTROL_PAUSE_TIME_SHIFT                                                  0
33401     #define UMAC_REG_PAUSE_CONTROL_TIME_NRESUME                                                      (0x1<<17) // If set and a Pause frame is being forced, send a Pause frame with the Pause Time Field specified in rf_omac_pause_time.  If this bit is cleared send a Pause frame with the zero pause time.
33402     #define UMAC_REG_PAUSE_CONTROL_TIME_NRESUME_SHIFT                                                17
33403     #define UMAC_REG_PAUSE_CONTROL_PAUSE_MODE                                                        (0x1<<18) // Pause mode 0 = Standard Pause, 1 = PFC Pause.
33404     #define UMAC_REG_PAUSE_CONTROL_PAUSE_MODE_SHIFT                                                  18
33405     #define UMAC_REG_PAUSE_CONTROL_FORCE_STD_PAUSE                                                   (0x1<<23) // Force sending a Standard Pause Frame.  The value of the Pause time is defined by rf_omac_time_nresume.  If rf_omac_time_nresume is set, the chip should continue to send Standard Pause frames at periodic intervals until rf_omac_time_nresume  is cleared.  If rf_omac_time_nresume is cleared, after sending a single Standard Pause frame the internal timer should be cleared.
33406     #define UMAC_REG_PAUSE_CONTROL_FORCE_STD_PAUSE_SHIFT                                             23
33407     #define UMAC_REG_PAUSE_CONTROL_FORCE_PP_PAUSE                                                    (0xff<<24) // Force sending a Per Priority Pause Frame.  Each bit in this field corresponds to a priority that should be set in a Per Priority Pause frame.  Bit 2 is priority 0 and so on.  The value of the Pause time is defined by rf_omac_time_nresume .  If rf_omac_time_nresume is set, the chip should continue to send Per Priority Pause frames at periodic intervals until rf_omac_time_nresume is cleared.  If rf_omac_time_nresume is cleared, after sending a single Per Priority Pause frame the internal timers for the selected priorities should be cleared. Note:  After forcing a Pause on a 10G port, a Resume must be forced to return the chip to normal Pause/Resume behavior.
33408     #define UMAC_REG_PAUSE_CONTROL_FORCE_PP_PAUSE_SHIFT                                              24
33409     #define UMAC_REG_PAUSE_CONTROL_VALUE                                                             (0x1ffff<<0) // Each bit in this register represents 512 bit times independent of the port speed. Values of 0 and 1 are illegal.
33410     #define UMAC_REG_PAUSE_CONTROL_VALUE_SHIFT                                                       0
33411     #define UMAC_REG_PAUSE_CONTROL_ENABLE                                                            (0x1<<17) // Enable Extra Pause Frames.
33412     #define UMAC_REG_PAUSE_CONTROL_ENABLE_SHIFT                                                      17
33413 #define UMAC_REG_UMAC_RSV_ERR_MASK_K2                                                                0x051334UL //Access:RW   DataWidth:0x16  0 - skipped (unsupported) 1 - stackvlan (unsupported) 2 - carrerr (on by default) 3 - codeerr (on by default) 4 - crcerr (on by default) 5 - lenerr 6 - oversize (on by default) 7 - rxok 8 - mcast 9 - bcast 10 - dribble (on by default) 11 - control 12 - pause (on by default) 13 - unsupp_op 14 - vlan 15 - unicast 16 - truncate (on by default) 17 - runt (on by default) 18 - ppp (per priority pause) 19 - rxfifooflow (rx fifo overflow (on by default)) [21:20] - unused  Chips: K2
33414 #define UMAC_REG_FLUSH_BB_A0                                                                         0x051334UL //Access:RW   DataWidth:0x1   Flush enable bit to drop out all packets in Tx FIFO without egressing any packets when set.  Chips: BB_A0
33415 #define UMAC_REG_FLUSH_BB_B0                                                                         0x051334UL //Access:RW   DataWidth:0x1   Flush enable bit to drop out all packets in Tx FIFO without egressing any packets when set.  Chips: BB_B0
33416 #define UMAC_REG_PROBE_ADR_K2                                                                        0x051338UL //Access:RW   DataWidth:0x8   probe address bit 7 - U/L bit 6 - GMII/XMGII CLK bits [5:0] mux select  Chips: K2
33417 #define UMAC_REG_RXFIFO_STAT_BB_A0                                                                   0x051338UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0
33418 #define UMAC_REG_RXFIFO_STAT_BB_B0                                                                   0x051338UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_B0
33419     #define UMAC_REG_RXFIFO_STAT_RXFIFO_UNDERRUN                                                     (0x1<<0) // RXFIFO Underrun occurred. Cleared by only reset.
33420     #define UMAC_REG_RXFIFO_STAT_RXFIFO_UNDERRUN_SHIFT                                               0
33421     #define UMAC_REG_RXFIFO_STAT_RXFIFO_OVERRUN                                                      (0x1<<1) // RXFIFO Overrun occurred. Cleared by only reset.
33422     #define UMAC_REG_RXFIFO_STAT_RXFIFO_OVERRUN_SHIFT                                                1
33423 #define UMAC_REG_PROBE_DATA_K2                                                                       0x05133cUL //Access:R    DataWidth:0x20  probe data based on probe address  Chips: K2
33424 #define UMAC_REG_TXFIFO_STAT_BB_A0                                                                   0x05133cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0
33425 #define UMAC_REG_TXFIFO_STAT_BB_B0                                                                   0x05133cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_B0
33426     #define UMAC_REG_TXFIFO_STAT_TXFIFO_UNDERRUN                                                     (0x1<<0) // TXFIFO Underrun occurred. Cleared by only reset.
33427     #define UMAC_REG_TXFIFO_STAT_TXFIFO_UNDERRUN_SHIFT                                               0
33428     #define UMAC_REG_TXFIFO_STAT_TXFIFO_OVERRUN                                                      (0x1<<1) // TXFIFO Overrun occurred. Cleared by only reset.
33429     #define UMAC_REG_TXFIFO_STAT_TXFIFO_OVERRUN_SHIFT                                                1
33430 #define UMAC_REG_MAC_PFC_CTRL                                                                        0x051340UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0
33431     #define UMAC_REG_MAC_PFC_CTRL_PFC_TX_ENBL                                                        (0x1<<0) // Enables the PPP-Tx functionality.
33432     #define UMAC_REG_MAC_PFC_CTRL_PFC_TX_ENBL_SHIFT                                                  0
33433     #define UMAC_REG_MAC_PFC_CTRL_PFC_RX_ENBL                                                        (0x1<<1) // Enables the PPP-Rx functionality.
33434     #define UMAC_REG_MAC_PFC_CTRL_PFC_RX_ENBL_SHIFT                                                  1
33435     #define UMAC_REG_MAC_PFC_CTRL_FORCE_PFC_XON                                                      (0x1<<2) // Instructs MAC to send Xon message to all classes of service.
33436     #define UMAC_REG_MAC_PFC_CTRL_FORCE_PFC_XON_SHIFT                                                2
33437     #define UMAC_REG_MAC_PFC_CTRL_RX_PASS_PFC_FRM                                                    (0x1<<4) // When set; MAC pass PFC frame to the system. Otherwise; PFC frame is discarded.
33438     #define UMAC_REG_MAC_PFC_CTRL_RX_PASS_PFC_FRM_SHIFT                                              4
33439     #define UMAC_REG_MAC_PFC_CTRL_PFC_STATS_EN                                                       (0x1<<5) // When clear; none of PFC related counters should increment. Otherwise; PFC counters is in full function. Note: it is programming requirement to set this bit when PFC function is enable.
33440     #define UMAC_REG_MAC_PFC_CTRL_PFC_STATS_EN_SHIFT                                                 5
33441 #define UMAC_REG_MAC_PFC_REFRESH_CTRL                                                                0x051344UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
33442     #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN                                             (0x1<<0) // Enables the PPP refresh functionality on the Tx side. When enabled; the MAC sends Xoff message on refresh counter becoming 0.
33443     #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_EN_SHIFT                                       0
33444     #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_TIMER                                          (0xffff<<16) // PPP refresh counter value.
33445     #define UMAC_REG_MAC_PFC_REFRESH_CTRL_PFC_REFRESH_TIMER_SHIFT                                    16
33446 #define MCP2_REG_PRTY_MASK                                                                           0x052044UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33447     #define MCP2_REG_PRTY_MASK_ROM_PARITY                                                            (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS.ROM_PARITY .
33448     #define MCP2_REG_PRTY_MASK_ROM_PARITY_SHIFT                                                      0
33449 #define MCP2_REG_ECO_RESERVED                                                                        0x052200UL //Access:RW   DataWidth:0x8   Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
33450 #define MCP2_REG_PRTY_MASK_H_0                                                                       0x052208UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33451     #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
33452     #define MCP2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                         0
33453     #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
33454     #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_SHIFT                                       1
33455     #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT                                             (0x1<<2) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
33456     #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_SHIFT                                       2
33457     #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT                                             (0x1<<3) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_2_RF_INT .
33458     #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_2_RF_INT_SHIFT                                       3
33459     #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT                                             (0x1<<4) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM006_I_ECC_3_RF_INT .
33460     #define MCP2_REG_PRTY_MASK_H_0_MEM006_I_ECC_3_RF_INT_SHIFT                                       4
33461     #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT                                               (0x1<<5) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
33462     #define MCP2_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_SHIFT                                         5
33463     #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
33464     #define MCP2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           6
33465     #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
33466     #define MCP2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           7
33467     #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
33468     #define MCP2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           8
33469     #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<9) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
33470     #define MCP2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           9
33471     #define MCP2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<10) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
33472     #define MCP2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           10
33473     #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<11) // This bit masks, when set, the Parity bit: MCP2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
33474     #define MCP2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           11
33475 #define MCP2_REG_MEM_ECC_EVENTS                                                                      0x052230UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
33476 #define MCP2_REG_MEM001_I_MEM_DFT_K2                                                                 0x052238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_flsh.i_flsh_buffer.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33477 #define MCP2_REG_MEM004_I_MEM_DFT_K2                                                                 0x05223cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_mcp_bmb.i_mcp_bmb_ingress_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33478 #define MCP2_REG_MEM003_I_MEM_DFT_K2                                                                 0x052240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_mcp_bmb.i_mcp_bmb_egress_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33479 #define MCP2_REG_MEM006_I_MEM_DFT_K2                                                                 0x052244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_mcp_scratchpad_mem_0.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
33480 #define MCP2_REG_MEM007_I_MEM_DFT_K2                                                                 0x052248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_mcp_scratchpad_mem_1.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
33481 #define MCP2_REG_MEM002_I_MEM_DFT_K2                                                                 0x05224cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_m2p_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33482 #define MCP2_REG_MEM009_I_MEM_DFT_K2                                                                 0x052250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_p2m_hdr_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33483 #define MCP2_REG_MEM008_I_MEM_DFT_K2                                                                 0x052254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_p2m_data_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33484 #define MCP2_REG_MEM005_I_MEM_DFT_K2                                                                 0x052258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcp.i_mcp_cache_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
33485 #define MCP2_REG_DBG_SELECT                                                                          0x052400UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
33486 #define MCP2_REG_DBG_DWORD_ENABLE                                                                    0x052404UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
33487 #define MCP2_REG_DBG_SHIFT                                                                           0x052408UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
33488 #define MCP2_REG_DBG_OUT_DATA                                                                        0x052420UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
33489 #define MCP2_REG_DBG_OUT_DATA_SIZE                                                                   8
33490 #define MCP2_REG_DBG_FORCE_VALID                                                                     0x052440UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
33491 #define MCP2_REG_DBG_FORCE_FRAME                                                                     0x052444UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
33492 #define MCP2_REG_DBG_OUT_VALID                                                                       0x052448UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
33493 #define MCP2_REG_DBG_OUT_FRAME                                                                       0x05244cUL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
33494 #define OPTE_REG_PRTY_MASK_H_0                                                                       0x053004UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33495     #define OPTE_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
33496     #define OPTE_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           0
33497     #define OPTE_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
33498     #define OPTE_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                           1
33499     #define OPTE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
33500     #define OPTE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           2
33501     #define OPTE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
33502     #define OPTE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           3
33503     #define OPTE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
33504     #define OPTE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           4
33505     #define OPTE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
33506     #define OPTE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           5
33507     #define OPTE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
33508     #define OPTE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           6
33509     #define OPTE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
33510     #define OPTE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           7
33511     #define OPTE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
33512     #define OPTE_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           8
33513     #define OPTE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<9) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
33514     #define OPTE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           9
33515     #define OPTE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                 (0x1<<10) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
33516     #define OPTE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                           10
33517 #define OPTE_REG_MEM_ECC_EVENTS                                                                      0x053010UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
33518 #define OPTE_REG_MEM005_I_MEM_DFT_K2                                                                 0x053018UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_if0_btb_fifo_mem_e0.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33519 #define OPTE_REG_MEM006_I_MEM_DFT_K2                                                                 0x05301cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_if0_btb_fifo_mem_e1.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33520 #define OPTE_REG_MEM007_I_MEM_DFT_K2                                                                 0x053020UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_if1_btb_fifo_mem_e0.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33521 #define OPTE_REG_MEM008_I_MEM_DFT_K2                                                                 0x053024UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_if1_btb_fifo_mem_e1.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33522 #define OPTE_REG_MEM001_I_MEM_DFT_K2                                                                 0x053028UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_dbg_fifo_mem_e0.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33523 #define OPTE_REG_MEM002_I_MEM_DFT_K2                                                                 0x05302cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_dbg_fifo_mem_e1.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33524 #define OPTE_REG_MEM003_I_MEM_DFT_K2                                                                 0x053030UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_dorq_fifo_mem_e0.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33525 #define OPTE_REG_MEM004_I_MEM_DFT_K2                                                                 0x053034UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_dorq_fifo_mem_e1.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33526 #define OPTE_REG_MEM011_I_MEM_DFT_K2                                                                 0x053038UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance opte.i_opte_storm_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33527 #define OPTE_REG_ECO_RESERVED                                                                        0x053200UL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
33528 #define OPTE_REG_DORQ_FIFO_ALMOST_FULL_THR                                                           0x053204UL //Access:RW   DataWidth:0x5   This field defines number of 256 bits data entries in the DORQ FIFO. When the occupancy is more than that number, local edpm_en is de-asserted. It is than combined with edpm_en from NIG to create the global edpm_en  Chips: BB_B0 K2
33529 #define OPTE_REG_PRTY_MASK                                                                           0x05320cUL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
33530     #define OPTE_REG_PRTY_MASK_DATAPATH_PARITY_ERROR                                                 (0x1<<0) // This bit masks, when set, the Parity bit: OPTE_REG_PRTY_STS.DATAPATH_PARITY_ERROR .
33531     #define OPTE_REG_PRTY_MASK_DATAPATH_PARITY_ERROR_SHIFT                                           0
33532 #define PCIE_REG_PRTY_MASK_H_0                                                                       0x054004UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33533     #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_A0                                         (0x1<<4) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
33534     #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_A0_SHIFT                                   4
33535     #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_B0                                         (0x1<<4) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
33536     #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_BB_B0_SHIFT                                   4
33537     #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_K2                                            (0x1<<0) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
33538     #define PCIE_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_K2_SHIFT                                      0
33539     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
33540     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                         1
33541     #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                           (0x1<<7) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
33542     #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                     7
33543     #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0                                           (0x1<<7) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
33544     #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                     7
33545     #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                              (0x1<<2) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
33546     #define PCIE_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                        2
33547     #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
33548     #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           3
33549     #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
33550     #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           4
33551     #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                           (0x1<<16) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
33552     #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                     16
33553     #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                           (0x1<<16) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
33554     #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                     16
33555     #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                              (0x1<<5) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
33556     #define PCIE_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                        5
33557     #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
33558     #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           6
33559     #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0                                           (0x1<<6) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
33560     #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                     6
33561     #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0                                           (0x1<<6) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
33562     #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                     6
33563     #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                              (0x1<<7) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
33564     #define PCIE_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                        7
33565     #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
33566     #define PCIE_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                         0
33567     #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
33568     #define PCIE_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT                                         1
33569     #define PCIE_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT                                               (0x1<<2) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
33570     #define PCIE_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT                                         2
33571     #define PCIE_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT                                               (0x1<<3) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
33572     #define PCIE_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_SHIFT                                         3
33573     #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT                                               (0x1<<5) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
33574     #define PCIE_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_SHIFT                                         5
33575     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0                                               (0x1<<8) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
33576     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_SHIFT                                         8
33577     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1                                               (0x1<<9) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
33578     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_SHIFT                                         9
33579     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2                                               (0x1<<10) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_2 .
33580     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2_SHIFT                                         10
33581     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_3                                               (0x1<<11) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_3 .
33582     #define PCIE_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_3_SHIFT                                         11
33583     #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_1                                               (0x1<<12) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY_1 .
33584     #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_1_SHIFT                                         12
33585     #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_2                                               (0x1<<13) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY_2 .
33586     #define PCIE_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_2_SHIFT                                         13
33587     #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1                                               (0x1<<14) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
33588     #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_SHIFT                                         14
33589     #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2                                               (0x1<<15) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
33590     #define PCIE_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_SHIFT                                         15
33591 #define PCIE_REG_MEM_ECC_EVENTS                                                                      0x05401cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
33592 #define PCIE_REG_MEM003_I_MEM_DFT_K2                                                                 0x054024UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcie_top_wrapper.i_ram_1p_rbuf.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
33593 #define PCIE_REG_MEM004_I_MEM_DFT_K2                                                                 0x054028UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcie_top_wrapper.i_ram_2p_sotbuf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33594 #define PCIE_REG_MEM008_I_MEM_DFT_K2                                                                 0x05402cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcie_top_wrapper.i_ram_radm_qbuffer_hdr.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33595 #define PCIE_REG_MEM007_I_MEM_DFT_K2                                                                 0x054030UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcie_top_wrapper.i_ram_radm_qbuffer_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33596 #define PCIE_REG_MEM005_I_MEM_DFT_K2                                                                 0x054034UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcie_top_wrapper.i_ram_cdm_rasdes_ec_reg.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33597 #define PCIE_REG_MEM006_I_MEM_DFT_K2                                                                 0x054038UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcie_top_wrapper.i_ram_cdm_rasdes_tba_reg.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
33598 #define PCIE_REG_MEM001_I_MEM_DFT_K2                                                                 0x05403cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcie_top_wrapper.i_pcie_dbgsyn_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
33599 #define PCIE_REG_MEM002_I_MEM_DFT_K2                                                                 0x054040UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcie_top_wrapper.i_phy_pcie_dbgsyn_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
33600 #define PCIE_REG_ECO_RESERVED                                                                        0x054200UL //Access:RW   DataWidth:0x20  Eco reserved register.  Chips: BB_A0 BB_B0 K2
33601 #define PCIE_REG_PCIE_CONTROL_BITS                                                                   0x054204UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33602     #define PCIE_REG_PCIE_CONTROL_BITS_USER_L1_ENTER                                                 (0x1<<2) // Set to enter L1 state.
33603     #define PCIE_REG_PCIE_CONTROL_BITS_USER_L1_ENTER_SHIFT                                           2
33604     #define PCIE_REG_PCIE_CONTROL_BITS_USER_L23_REQ                                                  (0x1<<3) // Set to request entry to L23 state (app_ready_entr_l23).
33605     #define PCIE_REG_PCIE_CONTROL_BITS_USER_L23_REQ_SHIFT                                            3
33606     #define PCIE_REG_PCIE_CONTROL_BITS_USER_SEND_LTR1                                                (0x1<<4) // Set to send LTR1.
33607     #define PCIE_REG_PCIE_CONTROL_BITS_USER_SEND_LTR1_SHIFT                                          4
33608     #define PCIE_REG_PCIE_CONTROL_BITS_USER_RC_MODE                                                  (0x1<<0) // Set to enter Root Controller Mode.
33609     #define PCIE_REG_PCIE_CONTROL_BITS_USER_RC_MODE_SHIFT                                            0
33610     #define PCIE_REG_PCIE_CONTROL_BITS_USER_ALLOW_GEN3                                               (0x1<<1) // Set to allow Gen3 mode.
33611     #define PCIE_REG_PCIE_CONTROL_BITS_USER_ALLOW_GEN3_SHIFT                                         1
33612     #define PCIE_REG_PCIE_CONTROL_BITS_USER_STOP_L1SUB                                               (0x1<<5) // Stop L1Sub control bit.
33613     #define PCIE_REG_PCIE_CONTROL_BITS_USER_STOP_L1SUB_SHIFT                                         5
33614 #define PCIE_REG_PCIE_STATUS_BITS                                                                    0x054208UL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33615     #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L0                                                     (0x1<<1) // Link in L0 Status bit.
33616     #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L0_SHIFT                                               1
33617     #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L23                                                    (0x1<<4) // Link in L23 Status bit.
33618     #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L23_SHIFT                                              4
33619     #define PCIE_REG_PCIE_STATUS_BITS_PTM_ATTN                                                       (0x1<<0) // Timesynch Data is ready in PCIE FIFO.
33620     #define PCIE_REG_PCIE_STATUS_BITS_PTM_ATTN_SHIFT                                                 0
33621     #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L11                                                    (0x1<<2) // Link in L11 Status bit.
33622     #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L11_SHIFT                                              2
33623     #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L12                                                    (0x1<<3) // Link in L12 Status bit.
33624     #define PCIE_REG_PCIE_STATUS_BITS_LINK_IN_L12_SHIFT                                              3
33625     #define PCIE_REG_PCIE_STATUS_BITS_LNK_PHY_DEVICE_TYPE                                            (0x7<<5) // Phy Device Type.
33626     #define PCIE_REG_PCIE_STATUS_BITS_LNK_PHY_DEVICE_TYPE_SHIFT                                      5
33627     #define PCIE_REG_PCIE_STATUS_BITS_PHY_PLL_LOCK                                                   (0x1<<8) // PLL Lock status bit.
33628     #define PCIE_REG_PCIE_STATUS_BITS_PHY_PLL_LOCK_SHIFT                                             8
33629 #define PCIE_REG_PCIE_DEBUG_BITS                                                                     0x05420cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
33630     #define PCIE_REG_PCIE_DEBUG_BITS_SPLITTBL_TL_PERR                                                (0x1<<0) // Force Parity Error on Split Table memory.
33631     #define PCIE_REG_PCIE_DEBUG_BITS_SPLITTBL_TL_PERR_SHIFT                                          0
33632     #define PCIE_REG_PCIE_DEBUG_BITS_TIMERTBL_TL_PERR                                                (0x1<<1) // Force Parity Error on Timer Table memory.
33633     #define PCIE_REG_PCIE_DEBUG_BITS_TIMERTBL_TL_PERR_SHIFT                                          1
33634 #define PCIE_REG_SOFT_RESET_CONTROL                                                                  0x054210UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: K2
33635     #define PCIE_REG_SOFT_RESET_CONTROL_APP_INIT_RST                                                 (0x1<<0) //
33636     #define PCIE_REG_SOFT_RESET_CONTROL_APP_INIT_RST_SHIFT                                           0
33637     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_WAKE_REF_RST_N                                          (0x1<<1) //
33638     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_WAKE_REF_RST_N_SHIFT                                    1
33639     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_SQUELCH_RST_N                                           (0x1<<2) //
33640     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_SQUELCH_RST_N_SHIFT                                     2
33641     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_STICKY_RST_N                                            (0x1<<3) //
33642     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_STICKY_RST_N_SHIFT                                      3
33643     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_NON_STICKY_RST_N                                        (0x1<<4) //
33644     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_NON_STICKY_RST_N_SHIFT                                  4
33645     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_CORE_RST_N                                              (0x1<<5) //
33646     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_CORE_RST_N_SHIFT                                        5
33647     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_PIPE_RST_N                                              (0x1<<6) //
33648     #define PCIE_REG_SOFT_RESET_CONTROL_SOFT_PIPE_RST_N_SHIFT                                        6
33649 #define PCIE_REG_OBFF_CONTROL_1                                                                      0x054214UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: K2
33650     #define PCIE_REG_OBFF_CONTROL_1_RECEIVEDREQUEST                                                  (0x1<<0) //
33651     #define PCIE_REG_OBFF_CONTROL_1_RECEIVEDREQUEST_SHIFT                                            0
33652     #define PCIE_REG_OBFF_CONTROL_1_OBFFSIGNALENABLE                                                 (0x1<<1) // This bit is set by firmware when host system sets OBFF Enable to 2'b11. Firmware must clear this bit when the host changes OBFF Enable from 2'b11 to any other value
33653     #define PCIE_REG_OBFF_CONTROL_1_OBFFSIGNALENABLE_SHIFT                                           1
33654     #define PCIE_REG_OBFF_CONTROL_1_OBFFWAKEPOLARITY                                                 (0x1<<2) // Set to 1 to indicate that the pcore WakeIn input is active high. This bit should only be set in the event a workaround is required.
33655     #define PCIE_REG_OBFF_CONTROL_1_OBFFWAKEPOLARITY_SHIFT                                           2
33656     #define PCIE_REG_OBFF_CONTROL_1_DISABLECPUACTIVEFORCING                                          (0x1<<3) // Set to 1 to prevent incoming Request TLPs from forcing the OBFF state to CPU Active.
33657     #define PCIE_REG_OBFF_CONTROL_1_DISABLECPUACTIVEFORCING_SHIFT                                    3
33658     #define PCIE_REG_OBFF_CONTROL_1_MINIMUMWAKEFALLINGEDGEDELAY                                      (0xffff<<4) // Minimum Wake Falling Edge Delay(this reset value is a count value based on 2ns clock period, for a time value of 700ns)
33659     #define PCIE_REG_OBFF_CONTROL_1_MINIMUMWAKEFALLINGEDGEDELAY_SHIFT                                4
33660 #define PCIE_REG_OBFF_CONTROL_2                                                                      0x054218UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: K2
33661     #define PCIE_REG_OBFF_CONTROL_2_MINIMUMWAKEPULSEWIDTH                                            (0xffff<<0) // Minimum Wake Pulse Width (this reset value is a count value based on 2ns clock period, for a time value of 200ns)
33662     #define PCIE_REG_OBFF_CONTROL_2_MINIMUMWAKEPULSEWIDTH_SHIFT                                      0
33663     #define PCIE_REG_OBFF_CONTROL_2_MAXIMUMWAKEPULSEWIDTH                                            (0xffff<<16) // Maximum Wake Pulse Width (this reset value is a count value based on 2ns clock period, for a time value of 600ns)
33664     #define PCIE_REG_OBFF_CONTROL_2_MAXIMUMWAKEPULSEWIDTH_SHIFT                                      16
33665 #define PCIE_REG_OBFF_STATUS_1                                                                       0x05421cUL //Access:R    DataWidth:0x14  Multi Field Register.  Chips: K2
33666     #define PCIE_REG_OBFF_STATUS_1_RXOBFFUPDATE                                                      (0x1<<0) //
33667     #define PCIE_REG_OBFF_STATUS_1_RXOBFFUPDATE_SHIFT                                                0
33668     #define PCIE_REG_OBFF_STATUS_1_RXOBFFCODE                                                        (0xf<<1) //
33669     #define PCIE_REG_OBFF_STATUS_1_RXOBFFCODE_SHIFT                                                  1
33670     #define PCIE_REG_OBFF_STATUS_1_RXOBFFEXCEPTION                                                   (0x1<<5) //
33671     #define PCIE_REG_OBFF_STATUS_1_RXOBFFEXCEPTION_SHIFT                                             5
33672     #define PCIE_REG_OBFF_STATUS_1_WAKESAMPLESTATE                                                   (0x1f<<6) //
33673     #define PCIE_REG_OBFF_STATUS_1_WAKESAMPLESTATE_SHIFT                                             6
33674     #define PCIE_REG_OBFF_STATUS_1_MINIMUMWAKEFALLINGEDGEVALID                                       (0x1<<11) //
33675     #define PCIE_REG_OBFF_STATUS_1_MINIMUMWAKEFALLINGEDGEVALID_SHIFT                                 11
33676     #define PCIE_REG_OBFF_STATUS_1_MAXIMUMPULSEWIDTHEXPIRE                                           (0x1<<12) //
33677     #define PCIE_REG_OBFF_STATUS_1_MAXIMUMPULSEWIDTHEXPIRE_SHIFT                                     12
33678     #define PCIE_REG_OBFF_STATUS_1_MINIMUMPULSEWIDTHREADY                                            (0x1<<13) //
33679     #define PCIE_REG_OBFF_STATUS_1_MINIMUMPULSEWIDTHREADY_SHIFT                                      13
33680     #define PCIE_REG_OBFF_STATUS_1_RESTARTWAKEPULSEWIDTHTIMER                                        (0x1<<14) //
33681     #define PCIE_REG_OBFF_STATUS_1_RESTARTWAKEPULSEWIDTHTIMER_SHIFT                                  14
33682     #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGE                                                   (0x1<<15) //
33683     #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGE_SHIFT                                             15
33684     #define PCIE_REG_OBFF_STATUS_1_WAKERISINGEDGE                                                    (0x1<<16) //
33685     #define PCIE_REG_OBFF_STATUS_1_WAKERISINGEDGE_SHIFT                                              16
33686     #define PCIE_REG_OBFF_STATUS_1_WAKEINSYNC                                                        (0x1<<17) //
33687     #define PCIE_REG_OBFF_STATUS_1_WAKEINSYNC_SHIFT                                                  17
33688     #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGECOUNT                                              (0x3<<18) //
33689     #define PCIE_REG_OBFF_STATUS_1_WAKEFALLINGEDGECOUNT_SHIFT                                        18
33690 #define PCIE_REG_OBFF_STATUS_2                                                                       0x054220UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: K2
33691     #define PCIE_REG_OBFF_STATUS_2_WAKEFALLINGEDGETIMER                                              (0xffff<<0) //
33692     #define PCIE_REG_OBFF_STATUS_2_WAKEFALLINGEDGETIMER_SHIFT                                        0
33693     #define PCIE_REG_OBFF_STATUS_2_WAKEPULSEWIDTHTIMER                                               (0xffff<<16) //
33694     #define PCIE_REG_OBFF_STATUS_2_WAKEPULSEWIDTHTIMER_SHIFT                                         16
33695 #define PCIE_REG_APP_LTR_MSG_LATENCY_0                                                               0x054224UL //Access:RW   DataWidth:0x20  32 bit value to be sent in LTR message  Chips: K2
33696 #define PCIE_REG_APP_LTR_MSG_LATENCY_1                                                               0x054228UL //Access:RW   DataWidth:0x20  32 bit value to be sent in LTR message  Chips: K2
33697 #define PCIE_REG_APP_LTR_LATENCY                                                                     0x05422cUL //Access:R    DataWidth:0x20  LTR latency value being sent in LTR messages  Chips: K2
33698 #define PCIE_REG_APP_LTR_MSG_FUNC_NUM                                                                0x054230UL //Access:RW   DataWidth:0x4   Function number associated with the LTR message  Chips: K2
33699 #define PCIE_REG_APP_LTR_MSG_GRANT                                                                   0x054234UL //Access:R    DataWidth:0x1     Chips: K2
33700 #define PCIE_REG_SII_LANE_FLIP_CONTROL                                                               0x054238UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: K2
33701     #define PCIE_REG_SII_LANE_FLIP_CONTROL_RX_LANE_FLIP_EN                                           (0x1<<0) // Performs manual lane reversal for receive lanes.
33702     #define PCIE_REG_SII_LANE_FLIP_CONTROL_RX_LANE_FLIP_EN_SHIFT                                     0
33703     #define PCIE_REG_SII_LANE_FLIP_CONTROL_TX_LANE_FLIP_EN                                           (0x1<<1) // Performs manual lane reversal for transmit lanes.
33704     #define PCIE_REG_SII_LANE_FLIP_CONTROL_TX_LANE_FLIP_EN_SHIFT                                     1
33705 #define PCIE_REG_APP_LTSSM_ENABLE                                                                    0x05423cUL //Access:RW   DataWidth:0x1   Driven low by your application after cold, warm or hot reset to hold the LTSSM in the Detect state until your application is ready for the link training to begin. When your application has finished reprogramming the core configuration registers using the DBI, it asserts app_ltssm_enable to allow the LTSSM to continue link establishment. Can also be used to delay hot resetting of the core until you have read out any register status.  Chips: K2
33706 #define PCIE_REG_HW_INIT_CONFIG                                                                      0x054240UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: K2
33707     #define PCIE_REG_HW_INIT_CONFIG_APP_LTSSM_ENABLE_OVR                                             (0x1<<0) // When set to 0, HWInit controls app_ltssm_enable
33708     #define PCIE_REG_HW_INIT_CONFIG_APP_LTSSM_ENABLE_OVR_SHIFT                                       0
33709     #define PCIE_REG_HW_INIT_CONFIG_HOT_RESET_PRE_DELAY_ENABLE                                       (0x1<<1) // When set to 1, HW delay asserting internal reset to allow FW access to internal registers
33710     #define PCIE_REG_HW_INIT_CONFIG_HOT_RESET_PRE_DELAY_ENABLE_SHIFT                                 1
33711 #define PCIE_REG_APP_REQ_RETRY_EN                                                                    0x054244UL //Access:RW   DataWidth:0x1     Chips: K2
33712 #define PCIE_REG_CLK_RST_APM_CONTROL                                                                 0x054248UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: K2
33713     #define PCIE_REG_CLK_RST_APM_CONTROL_APP_CLK_REQ_N                                               (0x1<<0) // Indicates that the application logic is ready to have reference clock removed.
33714     #define PCIE_REG_CLK_RST_APM_CONTROL_APP_CLK_REQ_N_SHIFT                                         0
33715     #define PCIE_REG_CLK_RST_APM_CONTROL_PHY_CLK_REQ_N                                               (0x1<<1) // Acknowledge from the PHY that it is ready to have reference clock removed.
33716     #define PCIE_REG_CLK_RST_APM_CONTROL_PHY_CLK_REQ_N_SHIFT                                         1
33717     #define PCIE_REG_CLK_RST_APM_CONTROL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN                      (0x1<<2) // While in L1 enable AUX clock to switch from PCLK to free running external clock.
33718     #define PCIE_REG_CLK_RST_APM_CONTROL_CFG_L1_AUX_CLK_SWITCH_CORE_CLK_GATE_EN_SHIFT                2
33719 #define PCIE_REG_CLK_RST_APM_STATUS                                                                  0x05424cUL //Access:R    DataWidth:0xb   Multi Field Register.  Chips: K2
33720     #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_CLK_REQ_N                                            (0x1<<0) // Indicates to the PHY that MAC and application is ready to remove the clock. PHY can decide whether or not it will allow reference clock removal if it supports this feature
33721     #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_CLK_REQ_N_SHIFT                                      0
33722     #define PCIE_REG_CLK_RST_APM_STATUS_CLK_REQ_N                                                    (0x1<<1) // Clock Turnoff request. Allows your application clock generation module to turn off core_clk based the current power management state
33723     #define PCIE_REG_CLK_RST_APM_STATUS_CLK_REQ_N_SHIFT                                              1
33724     #define PCIE_REG_CLK_RST_APM_STATUS_LOCAL_REF_CLK_REQ_N                                          (0x1<<2) //
33725     #define PCIE_REG_CLK_RST_APM_STATUS_LOCAL_REF_CLK_REQ_N_SHIFT                                    2
33726     #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_RXSTANDBY                                            (0xff<<3) // Indicates whether the PHY RX is active when the PHY is in P0 or P0s.
33727     #define PCIE_REG_CLK_RST_APM_STATUS_MAC_PHY_RXSTANDBY_SHIFT                                      3
33728 #define PCIE_REG_PTM_CONTROL                                                                         0x054250UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: K2
33729     #define PCIE_REG_PTM_CONTROL_PTM_AUTO_UPDATE_SIGNAL                                              (0x1<<0) //
33730     #define PCIE_REG_PTM_CONTROL_PTM_AUTO_UPDATE_SIGNAL_SHIFT                                        0
33731     #define PCIE_REG_PTM_CONTROL_PTM_MANUAL_UPDATE_PULSE                                             (0x1<<1) //
33732     #define PCIE_REG_PTM_CONTROL_PTM_MANUAL_UPDATE_PULSE_SHIFT                                       1
33733 #define PCIE_REG_PTM_STATUS                                                                          0x054254UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: K2
33734     #define PCIE_REG_PTM_STATUS_PTM_CONTEXT_VALID                                                    (0x1<<0) //
33735     #define PCIE_REG_PTM_STATUS_PTM_CONTEXT_VALID_SHIFT                                              0
33736     #define PCIE_REG_PTM_STATUS_PTM_CLOCK_UPDATED                                                    (0x1<<1) //
33737     #define PCIE_REG_PTM_STATUS_PTM_CLOCK_UPDATED_SHIFT                                              1
33738 #define PCIE_REG_PTM_CLOCK_CORRECTION_0                                                              0x054258UL //Access:R    DataWidth:0x20    Chips: K2
33739 #define PCIE_REG_PTM_CLOCK_CORRECTION_1                                                              0x05425cUL //Access:R    DataWidth:0x20    Chips: K2
33740 #define PCIE_REG_PTM_LOCAL_CLOCK_0                                                                   0x054260UL //Access:R    DataWidth:0x20    Chips: K2
33741 #define PCIE_REG_PTM_LOCAL_CLOCK_1                                                                   0x054264UL //Access:R    DataWidth:0x20    Chips: K2
33742 #define PCIE_REG_PTM_LOCAL_CLOCK0_LATCHED                                                            0x054268UL //Access:R    DataWidth:0x20  Latched vlaue during nig_pxp_ptm_latch pulse  Chips: K2
33743 #define PCIE_REG_PTM_LOCAL_CLOCK1_LATCHED                                                            0x05426cUL //Access:R    DataWidth:0x20  Latched vlaue during nig_pxp_ptm_latch pulse  Chips: K2
33744 #define PCIE_REG_RESET_STATUS_1                                                                      0x054270UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
33745     #define PCIE_REG_RESET_STATUS_1_WAKE_REF_RST_N                                                   (0x1<<0) //
33746     #define PCIE_REG_RESET_STATUS_1_WAKE_REF_RST_N_SHIFT                                             0
33747     #define PCIE_REG_RESET_STATUS_1_SQUELCH_RST_N                                                    (0x1<<1) //
33748     #define PCIE_REG_RESET_STATUS_1_SQUELCH_RST_N_SHIFT                                              1
33749     #define PCIE_REG_RESET_STATUS_1_STICKY_RST_N                                                     (0x1<<2) //
33750     #define PCIE_REG_RESET_STATUS_1_STICKY_RST_N_SHIFT                                               2
33751     #define PCIE_REG_RESET_STATUS_1_NON_STICKY_RST_N                                                 (0x1<<3) //
33752     #define PCIE_REG_RESET_STATUS_1_NON_STICKY_RST_N_SHIFT                                           3
33753     #define PCIE_REG_RESET_STATUS_1_PIPE_RST_N                                                       (0x1<<4) //
33754     #define PCIE_REG_RESET_STATUS_1_PIPE_RST_N_SHIFT                                                 4
33755     #define PCIE_REG_RESET_STATUS_1_SMLH_REQ_RST_NOT                                                 (0x1<<5) // Early version of the link_req_rst_not signal. For more details, see the 'Warm and Hot Resets' section in the Architecture chapter of the Databook.
33756     #define PCIE_REG_RESET_STATUS_1_SMLH_REQ_RST_NOT_SHIFT                                           5
33757     #define PCIE_REG_RESET_STATUS_1_LINK_REQ_RST_NOT                                                 (0x1<<6) //
33758     #define PCIE_REG_RESET_STATUS_1_LINK_REQ_RST_NOT_SHIFT                                           6
33759     #define PCIE_REG_RESET_STATUS_1_TRAINING_RST_N                                                   (0x1<<7) //
33760     #define PCIE_REG_RESET_STATUS_1_TRAINING_RST_N_SHIFT                                             7
33761 #define PCIE_REG_LINK_DEBUG_STATUS                                                                   0x054274UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: K2
33762     #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LINK_UP                                                  (0x1<<0) //
33763     #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LINK_UP_SHIFT                                            0
33764     #define PCIE_REG_LINK_DEBUG_STATUS_RDLH_LINK_UP                                                  (0x1<<1) //
33765     #define PCIE_REG_LINK_DEBUG_STATUS_RDLH_LINK_UP_SHIFT                                            1
33766     #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE                                              (0x3f<<2) //
33767     #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE_SHIFT                                        2
33768     #define PCIE_REG_LINK_DEBUG_STATUS_RADM_Q_NOT_EMPTY                                              (0x1<<8) // Level indicating that the receive queues contain TLP header/data.There is a 1 bit indication for each virtual channel.
33769     #define PCIE_REG_LINK_DEBUG_STATUS_RADM_Q_NOT_EMPTY_SHIFT                                        8
33770     #define PCIE_REG_LINK_DEBUG_STATUS_CDM_RAS_DES_TBA_INFO_COMMON                                   (0x7f<<9) // Common event signal status bus used in RAS D.E.S. time based analysis
33771     #define PCIE_REG_LINK_DEBUG_STATUS_CDM_RAS_DES_TBA_INFO_COMMON_SHIFT                             9
33772     #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE_RCVRY_EQ                                     (0x1<<16) // This status signal is asserted during all Recovery Equalization states
33773     #define PCIE_REG_LINK_DEBUG_STATUS_SMLH_LTSSM_STATE_RCVRY_EQ_SHIFT                               16
33774     #define PCIE_REG_LINK_DEBUG_STATUS_CFG_HW_AUTO_SP_DIS                                            (0x1<<17) // Autonomous speed disable. Used in downstream ports only.
33775     #define PCIE_REG_LINK_DEBUG_STATUS_CFG_HW_AUTO_SP_DIS_SHIFT                                      17
33776 #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR                                                            0x054278UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: K2
33777     #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_CXPL_DEBUG_INFO_EI                                     (0xffff<<0) // State of selected internal signals in relation to electrical idle (EI) at the receiver
33778     #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_CXPL_DEBUG_INFO_EI_SHIFT                               0
33779     #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_MSG_UNLOCK                                        (0x1<<16) // One-cycle pulse that indicates that the core received an Unlock message
33780     #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_MSG_UNLOCK_SHIFT                                  16
33781     #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_PM_TURNOFF                                        (0x1<<17) // One-clock-cycle pulse that indicates that the core received a PME Turnoff message
33782     #define PCIE_REG_DEBUG_EI_PM_UNLOCK_ERROR_RADM_PM_TURNOFF_SHIFT                                  17
33783 #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL                                                             0x05427cUL //Access:RW   DataWidth:0x13  Multi Field Register.  Chips: K2
33784     #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_DIAG_CTRL_BUS                                           (0x7<<0) // Diagnostic Control Bus
33785     #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_DIAG_CTRL_BUS_SHIFT                                     0
33786     #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_OUTBAND_PWRUP_CMD                                       (0xffff<<3) // Wake Up. Used by application logic to wake up the PMC state machine from a D1, D2 or D3 power state. Upon wake-up, the core sends a PM_PME Message
33787     #define PCIE_REG_PCIE_DIAGNOSTIC_CONTROL_OUTBAND_PWRUP_CMD_SHIFT                                 3
33788 #define PCIE_REG_POWER_MGMT_STATUS                                                                   0x054280UL //Access:R    DataWidth:0x13  Multi Field Register.  Chips: K2
33789     #define PCIE_REG_POWER_MGMT_STATUS_PM_STATUS                                                     (0xffff<<0) // PME Status bit from the PMCSR. There is 1 bit of pm_status for each configured function
33790     #define PCIE_REG_POWER_MGMT_STATUS_PM_STATUS_SHIFT                                               0
33791     #define PCIE_REG_POWER_MGMT_STATUS_PM_CURNT_STATE                                                (0x7<<16) // Indicates the current power state
33792     #define PCIE_REG_POWER_MGMT_STATUS_PM_CURNT_STATE_SHIFT                                          16
33793 #define PCIE_REG_SII_TRANSMIT_CONTROL                                                                0x054284UL //Access:R    DataWidth:0x14  Multi Field Register.  Chips: K2
33794     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_XTLH_BLOCK_TLP                                          (0x1<<0) // Indicates that your application must stop generating new outgoing request TLPs due to the current power management state.
33795     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_XTLH_BLOCK_TLP_SHIFT                                    0
33796     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_PME_EN                                                  (0xffff<<1) // PME Enable bit in the PMCSR. There is 1 bit of pm_pme_en for each configured function.
33797     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_PME_EN_SHIFT                                            1
33798     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L0S                                           (0x1<<17) // Power management is in L0s state
33799     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L0S_SHIFT                                     17
33800     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L2                                            (0x1<<18) // Power management is in L2 state.
33801     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_IN_L2_SHIFT                                      18
33802     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_L2_EXIT                                          (0x1<<19) // Power management is exiting L2 state.
33803     #define PCIE_REG_SII_TRANSMIT_CONTROL_PM_LINKST_L2_EXIT_SHIFT                                    19
33804 #define PCIE_REG_SII_CONFIG_INFO                                                                     0x054288UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: K2
33805     #define PCIE_REG_SII_CONFIG_INFO_CFG_PM_NO_SOFT_RST                                              (0xffff<<0) // This is the value of the No Soft Reset bit in the Power Management Control and Status Register
33806     #define PCIE_REG_SII_CONFIG_INFO_CFG_PM_NO_SOFT_RST_SHIFT                                        0
33807     #define PCIE_REG_SII_CONFIG_INFO_CFG_LTR_M_EN                                                    (0x1<<16) // The LTR Mechanism Enable field of the Device Control 2 register of function 0
33808     #define PCIE_REG_SII_CONFIG_INFO_CFG_LTR_M_EN_SHIFT                                              16
33809 #define PCIE_REG_SII_INTERRUPT_PM_STATUS                                                             0x05428cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: K2
33810     #define PCIE_REG_SII_INTERRUPT_PM_STATUS_AUX_PM_EN                                               (0xffff<<0) // Auxiliary Power Enable bit in the Device Control register. There is 1 bit of aux_pm_en for each configured function.
33811     #define PCIE_REG_SII_INTERRUPT_PM_STATUS_AUX_PM_EN_SHIFT                                         0
33812     #define PCIE_REG_SII_INTERRUPT_PM_STATUS_CFG_INT_DISABLE                                         (0xffff<<16) // When high a functions ability to generate INTx messages is Disabled
33813     #define PCIE_REG_SII_INTERRUPT_PM_STATUS_CFG_INT_DISABLE_SHIFT                                   16
33814 #define PCIE_REG_APP_RAS_DES_TBA_CTRL                                                                0x054290UL //Access:RW   DataWidth:0x2   Controls the start/end of time based analysis. You must only set the pins to the required value for the duration of one clock cycle  Chips: K2
33815 #define PCIE_REG_CXPL_DEBUG_INFO_31_0                                                                0x054294UL //Access:R    DataWidth:0x20  State of selected internal signals, for debugging purposes only  Chips: K2
33816 #define PCIE_REG_CXPL_DEBUG_INFO_63_32                                                               0x054298UL //Access:R    DataWidth:0x20  State of selected internal signals, for debugging purposes only  Chips: K2
33817 #define PCIE_REG_CDM_RAS_DES_SD_INFO_COMMON_31_0                                                     0x05429cUL //Access:R    DataWidth:0x20  Common debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33818 #define PCIE_REG_CDM_RAS_DES_SD_INFO_COMMON_63_32                                                    0x0542a0UL //Access:R    DataWidth:0x20  Common debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33819 #define PCIE_REG_CDM_RAS_DES_SD_INFO_COMMON_74_64                                                    0x0542a4UL //Access:R    DataWidth:0xb   Common debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33820 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L0_31_0                                                         0x0542a8UL //Access:R    DataWidth:0x20  Lane0 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33821 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L0_63_32                                                        0x0542acUL //Access:R    DataWidth:0x20  Lane0 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33822 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L0_77_64                                                        0x0542b0UL //Access:R    DataWidth:0xe   Lane0 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33823 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L1_31_0                                                         0x0542b4UL //Access:R    DataWidth:0x20  Lane1 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33824 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L1_63_32                                                        0x0542b8UL //Access:R    DataWidth:0x20  Lane1 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33825 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L1_77_64                                                        0x0542bcUL //Access:R    DataWidth:0xe   Lane1 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33826 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L2_31_0                                                         0x0542c0UL //Access:R    DataWidth:0x20  Lane2 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33827 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L2_63_32                                                        0x0542c4UL //Access:R    DataWidth:0x20  Lane2 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33828 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L2_77_64                                                        0x0542c8UL //Access:R    DataWidth:0xe   Lane2 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33829 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L3_31_0                                                         0x0542ccUL //Access:R    DataWidth:0x20  Lane3 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33830 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L3_63_32                                                        0x0542d0UL //Access:R    DataWidth:0x20  Lane3 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33831 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L3_77_64                                                        0x0542d4UL //Access:R    DataWidth:0xe   Lane3 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33832 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L4_31_0                                                         0x0542d8UL //Access:R    DataWidth:0x20  Lane4 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33833 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L4_63_32                                                        0x0542dcUL //Access:R    DataWidth:0x20  Lane4 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33834 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L4_77_64                                                        0x0542e0UL //Access:R    DataWidth:0xe   Lane4 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33835 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L5_31_0                                                         0x0542e4UL //Access:R    DataWidth:0x20  Lane5 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33836 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L5_63_32                                                        0x0542e8UL //Access:R    DataWidth:0x20  Lane5 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33837 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L5_77_64                                                        0x0542ecUL //Access:R    DataWidth:0xe   Lane5 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33838 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L6_31_0                                                         0x0542f0UL //Access:R    DataWidth:0x20  Lane6 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33839 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L6_63_32                                                        0x0542f4UL //Access:R    DataWidth:0x20  Lane6 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33840 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L6_77_64                                                        0x0542f8UL //Access:R    DataWidth:0xe   Lane6 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33841 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L7_31_0                                                         0x0542fcUL //Access:R    DataWidth:0x20  Lane7 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33842 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L7_63_32                                                        0x054300UL //Access:R    DataWidth:0x20  Lane7 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33843 #define PCIE_REG_CDM_RAS_DES_SD_INFO_L7_77_64                                                        0x054304UL //Access:R    DataWidth:0xe   Lane7 debug signal bus that is used in RAS D.E.S. silicon debug  Chips: K2
33844 #define PCIE_REG_CDM_RAS_DES_SD_INFO_V0_31_0                                                         0x054308UL //Access:R    DataWidth:0x20  VC0 debug signal bus that is used in RAS D.E.S. silicon debug.  Chips: K2
33845 #define PCIE_REG_CDM_RAS_DES_SD_INFO_V0_63_32                                                        0x05430cUL //Access:R    DataWidth:0x20  VC0 debug signal bus that is used in RAS D.E.S. silicon debug.  Chips: K2
33846 #define PCIE_REG_CDM_RAS_DES_SD_INFO_V0_95_64                                                        0x054310UL //Access:R    DataWidth:0x20  VC0 debug signal bus that is used in RAS D.E.S. silicon debug.  Chips: K2
33847 #define PCIE_REG_CDM_RAS_DES_SD_INFO_V0_127_96                                                       0x054314UL //Access:R    DataWidth:0x20  VC0 debug signal bus that is used in RAS D.E.S. silicon debug.  Chips: K2
33848 #define PCIE_REG_CDM_RAS_DES_SD_INFO_V0_159_128                                                      0x054318UL //Access:R    DataWidth:0x20  VC0 debug signal bus that is used in RAS D.E.S. silicon debug.  Chips: K2
33849 #define PCIE_REG_CDM_RAS_DES_SD_INFO_V0_191_160                                                      0x05431cUL //Access:R    DataWidth:0x20  VC0 debug signal bus that is used in RAS D.E.S. silicon debug.  Chips: K2
33850 #define PCIE_REG_CDM_RAS_DES_SD_INFO_V0_223_192                                                      0x054320UL //Access:R    DataWidth:0x20  VC0 debug signal bus that is used in RAS D.E.S. silicon debug.  Chips: K2
33851 #define PCIE_REG_CDM_RAS_DES_SD_INFO_V0_239_224                                                      0x054324UL //Access:R    DataWidth:0x10  VC0 debug signal bus that is used in RAS D.E.S. silicon debug.  Chips: K2
33852 #define PCIE_REG_DIAG_STATUS_BUS_843_839                                                             0x054328UL //Access:R    DataWidth:0x5   pm_dev_num[4:0]- Device number  Chips: K2
33853 #define PCIE_REG_DIAG_STATUS_BUS_838_831                                                             0x05432cUL //Access:R    DataWidth:0x8   pm_bus_num[7:0]- Bus Number  Chips: K2
33854 #define PCIE_REG_PHY_CFG_STATUS                                                                      0x054330UL //Access:RW   DataWidth:0x20  SNPS core input bus that can optionally be used to read PHY status. The phy_cfg_status bus maps to the PHY Status register.  Chips: K2
33855 #define PCIE_REG_CFG_PHY_CONTROL                                                                     0x054334UL //Access:R    DataWidth:0x20  Output bus that can optionally be used for additional PHY control purposes. The cfg_phy_control bus maps to the PHY Control register  Chips: K2
33856 #define PCIE_REG_LTSSM_MATCH_STATE                                                                   0x054338UL //Access:RW   DataWidth:0x6   Target LTSSM state for the LTSSM State matched event  Chips: K2
33857 #define PCIE_REG_POWER_BUDGET_DATA_0                                                                 0x05433cUL //Access:RW   DataWidth:0x15  Power Budget Table entry 0  Chips: K2
33858 #define PCIE_REG_POWER_BUDGET_DATA_1                                                                 0x054340UL //Access:RW   DataWidth:0x15  Power Budget Table entry 1  Chips: K2
33859 #define PCIE_REG_POWER_BUDGET_DATA_2                                                                 0x054344UL //Access:RW   DataWidth:0x15  Power Budget Table entry 2  Chips: K2
33860 #define PCIE_REG_POWER_BUDGET_DATA_3                                                                 0x054348UL //Access:RW   DataWidth:0x15  Power Budget Table entry 3  Chips: K2
33861 #define PCIE_REG_POWER_BUDGET_DATA_4                                                                 0x05434cUL //Access:RW   DataWidth:0x15  Power Budget Table entry 4  Chips: K2
33862 #define PCIE_REG_POWER_BUDGET_DATA_5                                                                 0x054350UL //Access:RW   DataWidth:0x15  Power Budget Table entry 5  Chips: K2
33863 #define PCIE_REG_POWER_BUDGET_DATA_6                                                                 0x054354UL //Access:RW   DataWidth:0x15  Power Budget Table entry 6  Chips: K2
33864 #define PCIE_REG_POWER_BUDGET_DATA_7                                                                 0x054358UL //Access:RW   DataWidth:0x15  Power Budget Table entry 7  Chips: K2
33865 #define PCIE_REG_DBG_ALMOST_FULL_THRESHOLD                                                           0x05435cUL //Access:RW   DataWidth:0x4     Chips: K2
33866 #define PCIE_REG_DBG_SAMPLING_INTERVAL                                                               0x054360UL //Access:RW   DataWidth:0x14  Sampling interval * pclk, 2ns to 2ms.  Chips: K2
33867 #define PCIE_REG_DBG_REPEAT_THRESHOLD_COUNT                                                          0x054364UL //Access:RW   DataWidth:0x4   If 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.  Chips: K2
33868 #define PCIE_REG_DBG_POST_TRIGGER_LATENCY_COUNT                                                      0x054368UL //Access:RW   DataWidth:0x18  If greater than 0, delay trigger count value * pclk, 0 to 32ms  Chips: K2
33869 #define PCIE_REG_DBG_FW_TRIGGER_ENABLE                                                               0x05436cUL //Access:RW   DataWidth:0x1     Chips: K2
33870 #define PCIE_REG_DBG_LANE_MATCH_ENABLE                                                               0x054370UL //Access:RW   DataWidth:0x8     Chips: K2
33871 #define PCIE_REG_DBG_AUX_CORE_CLK_SWITCH_TRIGGER_ENABLE                                              0x054374UL //Access:RW   DataWidth:0x1     Chips: K2
33872 #define PCIE_REG_DBG_LTSSM_MATCH_TRIGGER_ENABLE                                                      0x054378UL //Access:RW   DataWidth:0x1     Chips: K2
33873 #define PCIE_REG_DBG_LTSSM_MATCH_VALUE                                                               0x05437cUL //Access:RW   DataWidth:0x6     Chips: K2
33874 #define PCIE_REG_DBG_RX_ALIGN_LOSS_TRIGGER_ENABLE                                                    0x054380UL //Access:RW   DataWidth:0x1     Chips: K2
33875 #define PCIE_REG_DBG_EI_ENTRY_TRIGGER_ENABLE                                                         0x054384UL //Access:RW   DataWidth:0x1     Chips: K2
33876 #define PCIE_REG_DBG_EI_EXIT_TRIGGER_ENABLE                                                          0x054388UL //Access:RW   DataWidth:0x1     Chips: K2
33877 #define PCIE_REG_DBG_RATE_CHANGE_TRIGGER_ENABLE                                                      0x05438cUL //Access:RW   DataWidth:0x1     Chips: K2
33878 #define PCIE_REG_DBG_LINK_WIDTH_CHANGE_TRIGGER_ENABLE                                                0x054390UL //Access:RW   DataWidth:0x1     Chips: K2
33879 #define PCIE_REG_DBG_CORRECTABLE_ERROR_TRIGGER_ENABLE                                                0x054394UL //Access:RW   DataWidth:0x1     Chips: K2
33880 #define PCIE_REG_DBG_COMMON_SELECT                                                                   0x054398UL //Access:RW   DataWidth:0x8     Chips: K2
33881 #define PCIE_REG_DBG_COMMON_DWORD_ENABLE                                                             0x05439cUL //Access:RW   DataWidth:0x4     Chips: K2
33882 #define PCIE_REG_DBG_COMMON_SHIFT                                                                    0x0543a0UL //Access:RW   DataWidth:0x2     Chips: K2
33883 #define PCIE_REG_DBG_COMMON_FORCE_VALID                                                              0x0543a4UL //Access:RW   DataWidth:0x4     Chips: K2
33884 #define PCIE_REG_DBG_COMMON_FORCE_FRAME                                                              0x0543a8UL //Access:RW   DataWidth:0x4     Chips: K2
33885 #define PCIE_REG_DBGSYN_STATUS                                                                       0x0543acUL //Access:R    DataWidth:0x5     Chips: K2
33886 #define PCIE_REG_MSIX_SYNCH_START                                                                    0x0543b0UL //Access:RW   DataWidth:0x1   Need to write on init to start MSIX synchronization.  Chips: K2
33887 #define PCIE_REG_MSIX_SYNCH_STICKY                                                                   0x0543b4UL //Access:RC   DataWidth:0x1   Is set to 1 if at least 1 MSIX synchronization was performed completely.  Chips: K2
33888 #define PCIE_REG_INT_STS                                                                             0x0547a0UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: K2
33889     #define PCIE_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
33890     #define PCIE_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
33891     #define PCIE_REG_INT_STS_LINK_DOWN_DETECT                                                        (0x1<<1) // Data Link Down detected.
33892     #define PCIE_REG_INT_STS_LINK_DOWN_DETECT_SHIFT                                                  1
33893     #define PCIE_REG_INT_STS_LINK_UP_DETECT                                                          (0x1<<2) // Data Link Up detected.
33894     #define PCIE_REG_INT_STS_LINK_UP_DETECT_SHIFT                                                    2
33895     #define PCIE_REG_INT_STS_CFG_LINK_EQ_REQ_INT                                                     (0x1<<3) // Link Equalization requested.
33896     #define PCIE_REG_INT_STS_CFG_LINK_EQ_REQ_INT_SHIFT                                               3
33897     #define PCIE_REG_INT_STS_PCIE_BANDWIDTH_CHANGE_DETECT                                            (0x1<<4) // PCIe Bandwidth changed.
33898     #define PCIE_REG_INT_STS_PCIE_BANDWIDTH_CHANGE_DETECT_SHIFT                                      4
33899     #define PCIE_REG_INT_STS_EARLY_HOT_RESET_DETECT                                                  (0x1<<5) // Early Hot Reset detected.
33900     #define PCIE_REG_INT_STS_EARLY_HOT_RESET_DETECT_SHIFT                                            5
33901     #define PCIE_REG_INT_STS_HOT_RESET_DETECT                                                        (0x1<<6) // Hot Reset detected.
33902     #define PCIE_REG_INT_STS_HOT_RESET_DETECT_SHIFT                                                  6
33903     #define PCIE_REG_INT_STS_L1_ENTRY_DETECT                                                         (0x1<<7) // L1 Entry detected.
33904     #define PCIE_REG_INT_STS_L1_ENTRY_DETECT_SHIFT                                                   7
33905     #define PCIE_REG_INT_STS_L1_EXIT_DETECT                                                          (0x1<<8) // L1 Exit detected.
33906     #define PCIE_REG_INT_STS_L1_EXIT_DETECT_SHIFT                                                    8
33907     #define PCIE_REG_INT_STS_LTSSM_STATE_MATCH_DETECT                                                (0x1<<9) // LTSSM State matched.
33908     #define PCIE_REG_INT_STS_LTSSM_STATE_MATCH_DETECT_SHIFT                                          9
33909     #define PCIE_REG_INT_STS_FC_TIMEOUT_DETECT                                                       (0x1<<10) // Flow Control timeout detected.
33910     #define PCIE_REG_INT_STS_FC_TIMEOUT_DETECT_SHIFT                                                 10
33911     #define PCIE_REG_INT_STS_PME_TURNOFF_MESSAGE_DETECT                                              (0x1<<11) // PME Turnoff Message received.
33912     #define PCIE_REG_INT_STS_PME_TURNOFF_MESSAGE_DETECT_SHIFT                                        11
33913     #define PCIE_REG_INT_STS_CFG_SEND_COR_ERR                                                        (0x1<<12) // Correctable Error Message sent.
33914     #define PCIE_REG_INT_STS_CFG_SEND_COR_ERR_SHIFT                                                  12
33915     #define PCIE_REG_INT_STS_CFG_SEND_NF_ERR                                                         (0x1<<13) // Non-Fatal Error Message sent.
33916     #define PCIE_REG_INT_STS_CFG_SEND_NF_ERR_SHIFT                                                   13
33917     #define PCIE_REG_INT_STS_CFG_SEND_F_ERR                                                          (0x1<<14) // Fatal Error Message sent.
33918     #define PCIE_REG_INT_STS_CFG_SEND_F_ERR_SHIFT                                                    14
33919     #define PCIE_REG_INT_STS_QOVERFLOW_DETECT                                                        (0x1<<15) // Queue Overflow detected.
33920     #define PCIE_REG_INT_STS_QOVERFLOW_DETECT_SHIFT                                                  15
33921     #define PCIE_REG_INT_STS_VDM_DETECT                                                              (0x1<<16) // Vendor-Defined Message received.
33922     #define PCIE_REG_INT_STS_VDM_DETECT_SHIFT                                                        16
33923 #define PCIE_REG_INT_MASK                                                                            0x0547a4UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: K2
33924     #define PCIE_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.ADDRESS_ERROR .
33925     #define PCIE_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
33926     #define PCIE_REG_INT_MASK_LINK_DOWN_DETECT                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LINK_DOWN_DETECT .
33927     #define PCIE_REG_INT_MASK_LINK_DOWN_DETECT_SHIFT                                                 1
33928     #define PCIE_REG_INT_MASK_LINK_UP_DETECT                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LINK_UP_DETECT .
33929     #define PCIE_REG_INT_MASK_LINK_UP_DETECT_SHIFT                                                   2
33930     #define PCIE_REG_INT_MASK_CFG_LINK_EQ_REQ_INT                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_LINK_EQ_REQ_INT .
33931     #define PCIE_REG_INT_MASK_CFG_LINK_EQ_REQ_INT_SHIFT                                              3
33932     #define PCIE_REG_INT_MASK_PCIE_BANDWIDTH_CHANGE_DETECT                                           (0x1<<4) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.PCIE_BANDWIDTH_CHANGE_DETECT .
33933     #define PCIE_REG_INT_MASK_PCIE_BANDWIDTH_CHANGE_DETECT_SHIFT                                     4
33934     #define PCIE_REG_INT_MASK_EARLY_HOT_RESET_DETECT                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.EARLY_HOT_RESET_DETECT .
33935     #define PCIE_REG_INT_MASK_EARLY_HOT_RESET_DETECT_SHIFT                                           5
33936     #define PCIE_REG_INT_MASK_HOT_RESET_DETECT                                                       (0x1<<6) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.HOT_RESET_DETECT .
33937     #define PCIE_REG_INT_MASK_HOT_RESET_DETECT_SHIFT                                                 6
33938     #define PCIE_REG_INT_MASK_L1_ENTRY_DETECT                                                        (0x1<<7) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.L1_ENTRY_DETECT .
33939     #define PCIE_REG_INT_MASK_L1_ENTRY_DETECT_SHIFT                                                  7
33940     #define PCIE_REG_INT_MASK_L1_EXIT_DETECT                                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.L1_EXIT_DETECT .
33941     #define PCIE_REG_INT_MASK_L1_EXIT_DETECT_SHIFT                                                   8
33942     #define PCIE_REG_INT_MASK_LTSSM_STATE_MATCH_DETECT                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.LTSSM_STATE_MATCH_DETECT .
33943     #define PCIE_REG_INT_MASK_LTSSM_STATE_MATCH_DETECT_SHIFT                                         9
33944     #define PCIE_REG_INT_MASK_FC_TIMEOUT_DETECT                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.FC_TIMEOUT_DETECT .
33945     #define PCIE_REG_INT_MASK_FC_TIMEOUT_DETECT_SHIFT                                                10
33946     #define PCIE_REG_INT_MASK_PME_TURNOFF_MESSAGE_DETECT                                             (0x1<<11) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.PME_TURNOFF_MESSAGE_DETECT .
33947     #define PCIE_REG_INT_MASK_PME_TURNOFF_MESSAGE_DETECT_SHIFT                                       11
33948     #define PCIE_REG_INT_MASK_CFG_SEND_COR_ERR                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_COR_ERR .
33949     #define PCIE_REG_INT_MASK_CFG_SEND_COR_ERR_SHIFT                                                 12
33950     #define PCIE_REG_INT_MASK_CFG_SEND_NF_ERR                                                        (0x1<<13) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_NF_ERR .
33951     #define PCIE_REG_INT_MASK_CFG_SEND_NF_ERR_SHIFT                                                  13
33952     #define PCIE_REG_INT_MASK_CFG_SEND_F_ERR                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.CFG_SEND_F_ERR .
33953     #define PCIE_REG_INT_MASK_CFG_SEND_F_ERR_SHIFT                                                   14
33954     #define PCIE_REG_INT_MASK_QOVERFLOW_DETECT                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.QOVERFLOW_DETECT .
33955     #define PCIE_REG_INT_MASK_QOVERFLOW_DETECT_SHIFT                                                 15
33956     #define PCIE_REG_INT_MASK_VDM_DETECT                                                             (0x1<<16) // This bit masks, when set, the Interrupt bit: PCIE_REG_INT_STS.VDM_DETECT .
33957     #define PCIE_REG_INT_MASK_VDM_DETECT_SHIFT                                                       16
33958 #define PCIE_REG_INT_STS_WR                                                                          0x0547a8UL //Access:WR   DataWidth:0x11  Multi Field Register.  Chips: K2
33959     #define PCIE_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
33960     #define PCIE_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
33961     #define PCIE_REG_INT_STS_WR_LINK_DOWN_DETECT                                                     (0x1<<1) // Data Link Down detected.
33962     #define PCIE_REG_INT_STS_WR_LINK_DOWN_DETECT_SHIFT                                               1
33963     #define PCIE_REG_INT_STS_WR_LINK_UP_DETECT                                                       (0x1<<2) // Data Link Up detected.
33964     #define PCIE_REG_INT_STS_WR_LINK_UP_DETECT_SHIFT                                                 2
33965     #define PCIE_REG_INT_STS_WR_CFG_LINK_EQ_REQ_INT                                                  (0x1<<3) // Link Equalization requested.
33966     #define PCIE_REG_INT_STS_WR_CFG_LINK_EQ_REQ_INT_SHIFT                                            3
33967     #define PCIE_REG_INT_STS_WR_PCIE_BANDWIDTH_CHANGE_DETECT                                         (0x1<<4) // PCIe Bandwidth changed.
33968     #define PCIE_REG_INT_STS_WR_PCIE_BANDWIDTH_CHANGE_DETECT_SHIFT                                   4
33969     #define PCIE_REG_INT_STS_WR_EARLY_HOT_RESET_DETECT                                               (0x1<<5) // Early Hot Reset detected.
33970     #define PCIE_REG_INT_STS_WR_EARLY_HOT_RESET_DETECT_SHIFT                                         5
33971     #define PCIE_REG_INT_STS_WR_HOT_RESET_DETECT                                                     (0x1<<6) // Hot Reset detected.
33972     #define PCIE_REG_INT_STS_WR_HOT_RESET_DETECT_SHIFT                                               6
33973     #define PCIE_REG_INT_STS_WR_L1_ENTRY_DETECT                                                      (0x1<<7) // L1 Entry detected.
33974     #define PCIE_REG_INT_STS_WR_L1_ENTRY_DETECT_SHIFT                                                7
33975     #define PCIE_REG_INT_STS_WR_L1_EXIT_DETECT                                                       (0x1<<8) // L1 Exit detected.
33976     #define PCIE_REG_INT_STS_WR_L1_EXIT_DETECT_SHIFT                                                 8
33977     #define PCIE_REG_INT_STS_WR_LTSSM_STATE_MATCH_DETECT                                             (0x1<<9) // LTSSM State matched.
33978     #define PCIE_REG_INT_STS_WR_LTSSM_STATE_MATCH_DETECT_SHIFT                                       9
33979     #define PCIE_REG_INT_STS_WR_FC_TIMEOUT_DETECT                                                    (0x1<<10) // Flow Control timeout detected.
33980     #define PCIE_REG_INT_STS_WR_FC_TIMEOUT_DETECT_SHIFT                                              10
33981     #define PCIE_REG_INT_STS_WR_PME_TURNOFF_MESSAGE_DETECT                                           (0x1<<11) // PME Turnoff Message received.
33982     #define PCIE_REG_INT_STS_WR_PME_TURNOFF_MESSAGE_DETECT_SHIFT                                     11
33983     #define PCIE_REG_INT_STS_WR_CFG_SEND_COR_ERR                                                     (0x1<<12) // Correctable Error Message sent.
33984     #define PCIE_REG_INT_STS_WR_CFG_SEND_COR_ERR_SHIFT                                               12
33985     #define PCIE_REG_INT_STS_WR_CFG_SEND_NF_ERR                                                      (0x1<<13) // Non-Fatal Error Message sent.
33986     #define PCIE_REG_INT_STS_WR_CFG_SEND_NF_ERR_SHIFT                                                13
33987     #define PCIE_REG_INT_STS_WR_CFG_SEND_F_ERR                                                       (0x1<<14) // Fatal Error Message sent.
33988     #define PCIE_REG_INT_STS_WR_CFG_SEND_F_ERR_SHIFT                                                 14
33989     #define PCIE_REG_INT_STS_WR_QOVERFLOW_DETECT                                                     (0x1<<15) // Queue Overflow detected.
33990     #define PCIE_REG_INT_STS_WR_QOVERFLOW_DETECT_SHIFT                                               15
33991     #define PCIE_REG_INT_STS_WR_VDM_DETECT                                                           (0x1<<16) // Vendor-Defined Message received.
33992     #define PCIE_REG_INT_STS_WR_VDM_DETECT_SHIFT                                                     16
33993 #define PCIE_REG_INT_STS_CLR                                                                         0x0547acUL //Access:RC   DataWidth:0x11  Multi Field Register.  Chips: K2
33994     #define PCIE_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
33995     #define PCIE_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
33996     #define PCIE_REG_INT_STS_CLR_LINK_DOWN_DETECT                                                    (0x1<<1) // Data Link Down detected.
33997     #define PCIE_REG_INT_STS_CLR_LINK_DOWN_DETECT_SHIFT                                              1
33998     #define PCIE_REG_INT_STS_CLR_LINK_UP_DETECT                                                      (0x1<<2) // Data Link Up detected.
33999     #define PCIE_REG_INT_STS_CLR_LINK_UP_DETECT_SHIFT                                                2
34000     #define PCIE_REG_INT_STS_CLR_CFG_LINK_EQ_REQ_INT                                                 (0x1<<3) // Link Equalization requested.
34001     #define PCIE_REG_INT_STS_CLR_CFG_LINK_EQ_REQ_INT_SHIFT                                           3
34002     #define PCIE_REG_INT_STS_CLR_PCIE_BANDWIDTH_CHANGE_DETECT                                        (0x1<<4) // PCIe Bandwidth changed.
34003     #define PCIE_REG_INT_STS_CLR_PCIE_BANDWIDTH_CHANGE_DETECT_SHIFT                                  4
34004     #define PCIE_REG_INT_STS_CLR_EARLY_HOT_RESET_DETECT                                              (0x1<<5) // Early Hot Reset detected.
34005     #define PCIE_REG_INT_STS_CLR_EARLY_HOT_RESET_DETECT_SHIFT                                        5
34006     #define PCIE_REG_INT_STS_CLR_HOT_RESET_DETECT                                                    (0x1<<6) // Hot Reset detected.
34007     #define PCIE_REG_INT_STS_CLR_HOT_RESET_DETECT_SHIFT                                              6
34008     #define PCIE_REG_INT_STS_CLR_L1_ENTRY_DETECT                                                     (0x1<<7) // L1 Entry detected.
34009     #define PCIE_REG_INT_STS_CLR_L1_ENTRY_DETECT_SHIFT                                               7
34010     #define PCIE_REG_INT_STS_CLR_L1_EXIT_DETECT                                                      (0x1<<8) // L1 Exit detected.
34011     #define PCIE_REG_INT_STS_CLR_L1_EXIT_DETECT_SHIFT                                                8
34012     #define PCIE_REG_INT_STS_CLR_LTSSM_STATE_MATCH_DETECT                                            (0x1<<9) // LTSSM State matched.
34013     #define PCIE_REG_INT_STS_CLR_LTSSM_STATE_MATCH_DETECT_SHIFT                                      9
34014     #define PCIE_REG_INT_STS_CLR_FC_TIMEOUT_DETECT                                                   (0x1<<10) // Flow Control timeout detected.
34015     #define PCIE_REG_INT_STS_CLR_FC_TIMEOUT_DETECT_SHIFT                                             10
34016     #define PCIE_REG_INT_STS_CLR_PME_TURNOFF_MESSAGE_DETECT                                          (0x1<<11) // PME Turnoff Message received.
34017     #define PCIE_REG_INT_STS_CLR_PME_TURNOFF_MESSAGE_DETECT_SHIFT                                    11
34018     #define PCIE_REG_INT_STS_CLR_CFG_SEND_COR_ERR                                                    (0x1<<12) // Correctable Error Message sent.
34019     #define PCIE_REG_INT_STS_CLR_CFG_SEND_COR_ERR_SHIFT                                              12
34020     #define PCIE_REG_INT_STS_CLR_CFG_SEND_NF_ERR                                                     (0x1<<13) // Non-Fatal Error Message sent.
34021     #define PCIE_REG_INT_STS_CLR_CFG_SEND_NF_ERR_SHIFT                                               13
34022     #define PCIE_REG_INT_STS_CLR_CFG_SEND_F_ERR                                                      (0x1<<14) // Fatal Error Message sent.
34023     #define PCIE_REG_INT_STS_CLR_CFG_SEND_F_ERR_SHIFT                                                14
34024     #define PCIE_REG_INT_STS_CLR_QOVERFLOW_DETECT                                                    (0x1<<15) // Queue Overflow detected.
34025     #define PCIE_REG_INT_STS_CLR_QOVERFLOW_DETECT_SHIFT                                              15
34026     #define PCIE_REG_INT_STS_CLR_VDM_DETECT                                                          (0x1<<16) // Vendor-Defined Message received.
34027     #define PCIE_REG_INT_STS_CLR_VDM_DETECT_SHIFT                                                    16
34028 #define PCIE_REG_PRTY_MASK                                                                           0x0547b4UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: K2
34029     #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_0                                                     (0x1<<0) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_0 .
34030     #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_0_SHIFT                                               0
34031     #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_1                                                     (0x1<<1) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_1 .
34032     #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_1_SHIFT                                               1
34033     #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_2                                                     (0x1<<2) // This bit masks, when set, the Parity bit: PCIE_REG_PRTY_STS.APP_PARITY_ERRS_2 .
34034     #define PCIE_REG_PRTY_MASK_APP_PARITY_ERRS_2_SHIFT                                               2
34035 #define PCIE_REG_DBG_OUT_DATA                                                                        0x0547c0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
34036 #define PCIE_REG_DBG_OUT_DATA_SIZE                                                                   8
34037 #define PCIE_REG_DBG_OUT_VALID                                                                       0x0547e0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
34038 #define PCIE_REG_DBG_OUT_FRAME                                                                       0x0547e4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
34039 #define PCIE_REG_DBG_SELECT                                                                          0x0547e8UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
34040 #define PCIE_REG_DBG_DWORD_ENABLE                                                                    0x0547ecUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
34041 #define PCIE_REG_DBG_SHIFT                                                                           0x0547f0UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
34042 #define PCIE_REG_DBG_FORCE_VALID                                                                     0x0547f4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
34043 #define PCIE_REG_DBG_FORCE_FRAME                                                                     0x0547f8UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
34044 #define PCIE_REG_RESET_STATUS_2                                                                      0x054800UL //Access:R    DataWidth:0x18  Multi Field Register.  Chips: K2
34045     #define PCIE_REG_RESET_STATUS_2_PWR_RST_2                                                        (0x1<<0) // Power-on reset occurred.
34046     #define PCIE_REG_RESET_STATUS_2_PWR_RST_2_SHIFT                                                  0
34047     #define PCIE_REG_RESET_STATUS_2_WAKE_REF_RST_2                                                   (0x1<<1) // Wake Ref reset occurred.
34048     #define PCIE_REG_RESET_STATUS_2_WAKE_REF_RST_2_SHIFT                                             1
34049     #define PCIE_REG_RESET_STATUS_2_PHY_RST_2                                                        (0x1<<2) // Phy reset occurred.
34050     #define PCIE_REG_RESET_STATUS_2_PHY_RST_2_SHIFT                                                  2
34051     #define PCIE_REG_RESET_STATUS_2_SQUELCH_RST_2                                                    (0x1<<3) // Squelch reset occurred.
34052     #define PCIE_REG_RESET_STATUS_2_SQUELCH_RST_2_SHIFT                                              3
34053     #define PCIE_REG_RESET_STATUS_2_STICKY_RST_2                                                     (0x1<<4) // Sticky register reset occurred.
34054     #define PCIE_REG_RESET_STATUS_2_STICKY_RST_2_SHIFT                                               4
34055     #define PCIE_REG_RESET_STATUS_2_NON_STICKY_RST_2                                                 (0x1<<5) // Non-sticky register reset occurred.
34056     #define PCIE_REG_RESET_STATUS_2_NON_STICKY_RST_2_SHIFT                                           5
34057     #define PCIE_REG_RESET_STATUS_2_CORE_RST_2                                                       (0x1<<6) // Core reset occurred.
34058     #define PCIE_REG_RESET_STATUS_2_CORE_RST_2_SHIFT                                                 6
34059     #define PCIE_REG_RESET_STATUS_2_PIPE_RST_2                                                       (0x1<<7) // PIPE reset occurred.
34060     #define PCIE_REG_RESET_STATUS_2_PIPE_RST_2_SHIFT                                                 7
34061     #define PCIE_REG_RESET_STATUS_2_PERST_2                                                          (0x1<<8) // PERST occurred.
34062     #define PCIE_REG_RESET_STATUS_2_PERST_2_SHIFT                                                    8
34063     #define PCIE_REG_RESET_STATUS_2_DATA_LINK_DOWN_2                                                 (0x1<<9) // Data Link Down occurred.
34064     #define PCIE_REG_RESET_STATUS_2_DATA_LINK_DOWN_2_SHIFT                                           9
34065     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_10_2                                      (0x1<<10) // Spare status bit
34066     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_10_2_SHIFT                                10
34067     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_11_2                                      (0x1<<11) // Spare status bit
34068     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_11_2_SHIFT                                11
34069     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_12_2                                      (0x1<<12) // Spare status bit
34070     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_12_2_SHIFT                                12
34071     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_13_2                                      (0x1<<13) // Spare status bit
34072     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_13_2_SHIFT                                13
34073     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_14_2                                      (0x1<<14) // Spare status bit
34074     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_14_2_SHIFT                                14
34075     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_15_2                                      (0x1<<15) // Spare status bit
34076     #define PCIE_REG_RESET_STATUS_2_RESET_STATUS_REG_SPARE_15_2_SHIFT                                15
34077     #define PCIE_REG_RESET_STATUS_2_SOFT_PWR_RST_2                                                   (0x1<<16) // Soft power-on reset occurred.
34078     #define PCIE_REG_RESET_STATUS_2_SOFT_PWR_RST_2_SHIFT                                             16
34079     #define PCIE_REG_RESET_STATUS_2_SOFT_WAKE_REF_RST_2                                              (0x1<<17) // Soft Wake Ref reset occurred.
34080     #define PCIE_REG_RESET_STATUS_2_SOFT_WAKE_REF_RST_2_SHIFT                                        17
34081     #define PCIE_REG_RESET_STATUS_2_SOFT_PHY_RST_2                                                   (0x1<<18) // Soft phy reset occurred.
34082     #define PCIE_REG_RESET_STATUS_2_SOFT_PHY_RST_2_SHIFT                                             18
34083     #define PCIE_REG_RESET_STATUS_2_SOFT_SQUELCH_RST_2                                               (0x1<<19) // Soft squelch reset occurred.
34084     #define PCIE_REG_RESET_STATUS_2_SOFT_SQUELCH_RST_2_SHIFT                                         19
34085     #define PCIE_REG_RESET_STATUS_2_SOFT_STICKY_RST_2                                                (0x1<<20) // Soft sticky register reset occurred.
34086     #define PCIE_REG_RESET_STATUS_2_SOFT_STICKY_RST_2_SHIFT                                          20
34087     #define PCIE_REG_RESET_STATUS_2_SOFT_NON_STICKY_RST_2                                            (0x1<<21) // Soft non-sticky register reset occurred.
34088     #define PCIE_REG_RESET_STATUS_2_SOFT_NON_STICKY_RST_2_SHIFT                                      21
34089     #define PCIE_REG_RESET_STATUS_2_SOFT_CORE_RST_2                                                  (0x1<<22) // Soft core reset occurred.
34090     #define PCIE_REG_RESET_STATUS_2_SOFT_CORE_RST_2_SHIFT                                            22
34091     #define PCIE_REG_RESET_STATUS_2_SOFT_PIPE_RST_2                                                  (0x1<<23) // Soft PIPE reset occurred.
34092     #define PCIE_REG_RESET_STATUS_2_SOFT_PIPE_RST_2_SHIFT                                            23
34093 #define PCIE_REG_RESET_STATUS_3                                                                      0x054804UL //Access:RW   DataWidth:0x18  Multi Field Register.  Chips: K2
34094     #define PCIE_REG_RESET_STATUS_3_PWR_RST_3                                                        (0x1<<0) // Power-on reset occurred. Status will be cleared on reading this register.
34095     #define PCIE_REG_RESET_STATUS_3_PWR_RST_3_SHIFT                                                  0
34096     #define PCIE_REG_RESET_STATUS_3_WAKE_REF_RST_3                                                   (0x1<<1) // Wake Ref reset occurred. Status will be cleared on reading this register.
34097     #define PCIE_REG_RESET_STATUS_3_WAKE_REF_RST_3_SHIFT                                             1
34098     #define PCIE_REG_RESET_STATUS_3_PHY_RST_3                                                        (0x1<<2) // Phy reset occurred. Status will be cleared on reading this register.
34099     #define PCIE_REG_RESET_STATUS_3_PHY_RST_3_SHIFT                                                  2
34100     #define PCIE_REG_RESET_STATUS_3_SQUELCH_RST_3                                                    (0x1<<3) // Squelch reset occurred. Status will be cleared on reading this register.
34101     #define PCIE_REG_RESET_STATUS_3_SQUELCH_RST_3_SHIFT                                              3
34102     #define PCIE_REG_RESET_STATUS_3_STICKY_RST_3                                                     (0x1<<4) // Sticky register reset occurred. Status will be cleared on reading this register.
34103     #define PCIE_REG_RESET_STATUS_3_STICKY_RST_3_SHIFT                                               4
34104     #define PCIE_REG_RESET_STATUS_3_NON_STICKY_RST_3                                                 (0x1<<5) // Non-sticky register reset occurred. Status will be cleared on reading this register.
34105     #define PCIE_REG_RESET_STATUS_3_NON_STICKY_RST_3_SHIFT                                           5
34106     #define PCIE_REG_RESET_STATUS_3_CORE_RST_3                                                       (0x1<<6) // Core reset occurred. Status will be cleared on reading this register.
34107     #define PCIE_REG_RESET_STATUS_3_CORE_RST_3_SHIFT                                                 6
34108     #define PCIE_REG_RESET_STATUS_3_PIPE_RST_3                                                       (0x1<<7) // PIPE reset occurred. Status will be cleared on reading this register.
34109     #define PCIE_REG_RESET_STATUS_3_PIPE_RST_3_SHIFT                                                 7
34110     #define PCIE_REG_RESET_STATUS_3_PERST_3                                                          (0x1<<8) // PERST occurred. Status will be cleared on reading this register.
34111     #define PCIE_REG_RESET_STATUS_3_PERST_3_SHIFT                                                    8
34112     #define PCIE_REG_RESET_STATUS_3_DATA_LINK_DOWN_3                                                 (0x1<<9) // Data Link Down occurred. Status will be cleared on reading this register.
34113     #define PCIE_REG_RESET_STATUS_3_DATA_LINK_DOWN_3_SHIFT                                           9
34114     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_10_3                                      (0x1<<10) // Spare read-to-clear bit
34115     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_10_3_SHIFT                                10
34116     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_11_3                                      (0x1<<11) // Spare read-to-clear bit
34117     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_11_3_SHIFT                                11
34118     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_12_3                                      (0x1<<12) // Spare read-to-clear bit
34119     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_12_3_SHIFT                                12
34120     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_13_3                                      (0x1<<13) // Spare read-to-clear bit
34121     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_13_3_SHIFT                                13
34122     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_14_3                                      (0x1<<14) // Spare read-to-clear bit
34123     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_14_3_SHIFT                                14
34124     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_15_3                                      (0x1<<15) // Spare read-to-clear bit
34125     #define PCIE_REG_RESET_STATUS_3_RESET_STATUS_REG_SPARE_15_3_SHIFT                                15
34126     #define PCIE_REG_RESET_STATUS_3_SOFT_PWR_RST_3                                                   (0x1<<16) // Soft power-on reset occurred. Status will be cleared on reading this register.
34127     #define PCIE_REG_RESET_STATUS_3_SOFT_PWR_RST_3_SHIFT                                             16
34128     #define PCIE_REG_RESET_STATUS_3_SOFT_WAKE_REF_RST_3                                              (0x1<<17) // Soft Wake Ref reset occurred. Status will be cleared on reading this register.
34129     #define PCIE_REG_RESET_STATUS_3_SOFT_WAKE_REF_RST_3_SHIFT                                        17
34130     #define PCIE_REG_RESET_STATUS_3_SOFT_PHY_RST_3                                                   (0x1<<18) // Soft phy reset occurred. Status will be cleared on reading this register.
34131     #define PCIE_REG_RESET_STATUS_3_SOFT_PHY_RST_3_SHIFT                                             18
34132     #define PCIE_REG_RESET_STATUS_3_SOFT_SQUELCH_RST_3                                               (0x1<<19) // Soft squelch reset occurred. Status will be cleared on reading this register.
34133     #define PCIE_REG_RESET_STATUS_3_SOFT_SQUELCH_RST_3_SHIFT                                         19
34134     #define PCIE_REG_RESET_STATUS_3_SOFT_STICKY_RST_3                                                (0x1<<20) // Soft sticky register reset occurred. Status will be cleared on reading this register.
34135     #define PCIE_REG_RESET_STATUS_3_SOFT_STICKY_RST_3_SHIFT                                          20
34136     #define PCIE_REG_RESET_STATUS_3_SOFT_NON_STICKY_RST_3                                            (0x1<<21) // Soft non-sticky register reset occurred. Status will be cleared on reading this register.
34137     #define PCIE_REG_RESET_STATUS_3_SOFT_NON_STICKY_RST_3_SHIFT                                      21
34138     #define PCIE_REG_RESET_STATUS_3_SOFT_CORE_RST_3                                                  (0x1<<22) // Soft core reset occurred. Status will be cleared on reading this register.
34139     #define PCIE_REG_RESET_STATUS_3_SOFT_CORE_RST_3_SHIFT                                            22
34140     #define PCIE_REG_RESET_STATUS_3_SOFT_PIPE_RST_3                                                  (0x1<<23) // Soft PIPE reset occurred. Status will be cleared on reading this register.
34141     #define PCIE_REG_RESET_STATUS_3_SOFT_PIPE_RST_3_SHIFT                                            23
34142 #define DORQ_REG_INIT                                                                                0x100000UL //Access:RW   DataWidth:0x1   Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.  Chips: BB_A0 BB_B0 K2
34143 #define DORQ_REG_IFEN                                                                                0x100040UL //Access:RW   DataWidth:0x1   Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
34144 #define DORQ_REG_INT_STS                                                                             0x100180UL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34145     #define DORQ_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
34146     #define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
34147     #define DORQ_REG_INT_STS_DB_DROP                                                                 (0x1<<1) // Doorbell drop.
34148     #define DORQ_REG_INT_STS_DB_DROP_SHIFT                                                           1
34149     #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR                                                      (0x1<<2) // DORQ FIFO overflow.
34150     #define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT                                                2
34151     #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL                                                         (0x1<<3) // DORQ FIFO almost full.
34152     #define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT                                                   3
34153     #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR                                                  (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
34154     #define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT                                            4
34155     #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR                                                         (0x1<<5) // CCFC load response returnes an error.
34156     #define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT                                                   5
34157     #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR                                                        (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
34158     #define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT                                                  6
34159     #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR                                                (0x1<<7) // CFC load request FIFO overflow
34160     #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT                                          7
34161     #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR                                               (0x1<<8) // CFC load request FIFO under-run
34162     #define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT                                         8
34163 #define DORQ_REG_INT_MASK                                                                            0x100184UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34164     #define DORQ_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.ADDRESS_ERROR .
34165     #define DORQ_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
34166     #define DORQ_REG_INT_MASK_DB_DROP                                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DB_DROP .
34167     #define DORQ_REG_INT_MASK_DB_DROP_SHIFT                                                          1
34168     #define DORQ_REG_INT_MASK_DORQ_FIFO_OVFL_ERR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DORQ_FIFO_OVFL_ERR .
34169     #define DORQ_REG_INT_MASK_DORQ_FIFO_OVFL_ERR_SHIFT                                               2
34170     #define DORQ_REG_INT_MASK_DORQ_FIFO_AFULL                                                        (0x1<<3) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.DORQ_FIFO_AFULL .
34171     #define DORQ_REG_INT_MASK_DORQ_FIFO_AFULL_SHIFT                                                  3
34172     #define DORQ_REG_INT_MASK_CFC_BYP_VALIDATION_ERR                                                 (0x1<<4) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_BYP_VALIDATION_ERR .
34173     #define DORQ_REG_INT_MASK_CFC_BYP_VALIDATION_ERR_SHIFT                                           4
34174     #define DORQ_REG_INT_MASK_CFC_LD_RESP_ERR                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_RESP_ERR .
34175     #define DORQ_REG_INT_MASK_CFC_LD_RESP_ERR_SHIFT                                                  5
34176     #define DORQ_REG_INT_MASK_XCM_DONE_CNT_ERR                                                       (0x1<<6) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.XCM_DONE_CNT_ERR .
34177     #define DORQ_REG_INT_MASK_XCM_DONE_CNT_ERR_SHIFT                                                 6
34178     #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_OVFL_ERR                                               (0x1<<7) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_REQ_FIFO_OVFL_ERR .
34179     #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT                                         7
34180     #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_UNDER_ERR                                              (0x1<<8) // This bit masks, when set, the Interrupt bit: DORQ_REG_INT_STS.CFC_LD_REQ_FIFO_UNDER_ERR .
34181     #define DORQ_REG_INT_MASK_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT                                        8
34182 #define DORQ_REG_INT_STS_WR                                                                          0x100188UL //Access:WR   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34183     #define DORQ_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
34184     #define DORQ_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
34185     #define DORQ_REG_INT_STS_WR_DB_DROP                                                              (0x1<<1) // Doorbell drop.
34186     #define DORQ_REG_INT_STS_WR_DB_DROP_SHIFT                                                        1
34187     #define DORQ_REG_INT_STS_WR_DORQ_FIFO_OVFL_ERR                                                   (0x1<<2) // DORQ FIFO overflow.
34188     #define DORQ_REG_INT_STS_WR_DORQ_FIFO_OVFL_ERR_SHIFT                                             2
34189     #define DORQ_REG_INT_STS_WR_DORQ_FIFO_AFULL                                                      (0x1<<3) // DORQ FIFO almost full.
34190     #define DORQ_REG_INT_STS_WR_DORQ_FIFO_AFULL_SHIFT                                                3
34191     #define DORQ_REG_INT_STS_WR_CFC_BYP_VALIDATION_ERR                                               (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
34192     #define DORQ_REG_INT_STS_WR_CFC_BYP_VALIDATION_ERR_SHIFT                                         4
34193     #define DORQ_REG_INT_STS_WR_CFC_LD_RESP_ERR                                                      (0x1<<5) // CCFC load response returnes an error.
34194     #define DORQ_REG_INT_STS_WR_CFC_LD_RESP_ERR_SHIFT                                                5
34195     #define DORQ_REG_INT_STS_WR_XCM_DONE_CNT_ERR                                                     (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
34196     #define DORQ_REG_INT_STS_WR_XCM_DONE_CNT_ERR_SHIFT                                               6
34197     #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_OVFL_ERR                                             (0x1<<7) // CFC load request FIFO overflow
34198     #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT                                       7
34199     #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_UNDER_ERR                                            (0x1<<8) // CFC load request FIFO under-run
34200     #define DORQ_REG_INT_STS_WR_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT                                      8
34201 #define DORQ_REG_INT_STS_CLR                                                                         0x10018cUL //Access:RC   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34202     #define DORQ_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
34203     #define DORQ_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
34204     #define DORQ_REG_INT_STS_CLR_DB_DROP                                                             (0x1<<1) // Doorbell drop.
34205     #define DORQ_REG_INT_STS_CLR_DB_DROP_SHIFT                                                       1
34206     #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_OVFL_ERR                                                  (0x1<<2) // DORQ FIFO overflow.
34207     #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_OVFL_ERR_SHIFT                                            2
34208     #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_AFULL                                                     (0x1<<3) // DORQ FIFO almost full.
34209     #define DORQ_REG_INT_STS_CLR_DORQ_FIFO_AFULL_SHIFT                                               3
34210     #define DORQ_REG_INT_STS_CLR_CFC_BYP_VALIDATION_ERR                                              (0x1<<4) // After cached LCID value was used for CM message, CCFC load response LCID does not match cached value.
34211     #define DORQ_REG_INT_STS_CLR_CFC_BYP_VALIDATION_ERR_SHIFT                                        4
34212     #define DORQ_REG_INT_STS_CLR_CFC_LD_RESP_ERR                                                     (0x1<<5) // CCFC load response returnes an error.
34213     #define DORQ_REG_INT_STS_CLR_CFC_LD_RESP_ERR_SHIFT                                               5
34214     #define DORQ_REG_INT_STS_CLR_XCM_DONE_CNT_ERR                                                    (0x1<<6) // XCM done counter is decremented (done appears), when it is 0.
34215     #define DORQ_REG_INT_STS_CLR_XCM_DONE_CNT_ERR_SHIFT                                              6
34216     #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_OVFL_ERR                                            (0x1<<7) // CFC load request FIFO overflow
34217     #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT                                      7
34218     #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_UNDER_ERR                                           (0x1<<8) // CFC load request FIFO under-run
34219     #define DORQ_REG_INT_STS_CLR_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT                                     8
34220 #define DORQ_REG_PRTY_MASK                                                                           0x100194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
34221     #define DORQ_REG_PRTY_MASK_DATAPATH_REGISTERS                                                    (0x1<<0) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS.DATAPATH_REGISTERS .
34222     #define DORQ_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                              0
34223 #define DORQ_REG_PRTY_MASK_H_0                                                                       0x100204UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34224     #define DORQ_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
34225     #define DORQ_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT                                         0
34226     #define DORQ_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
34227     #define DORQ_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           1
34228     #define DORQ_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
34229     #define DORQ_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           2
34230     #define DORQ_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
34231     #define DORQ_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           3
34232     #define DORQ_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
34233     #define DORQ_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           4
34234     #define DORQ_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: DORQ_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
34235     #define DORQ_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           5
34236 #define DORQ_REG_MEM_ECC_EVENTS                                                                      0x10021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
34237 #define DORQ_REG_MEM002_I_MEM_DFT_K2                                                                 0x100224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dorq.i_dorq_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
34238 #define DORQ_REG_MEM001_I_MEM_DFT_K2                                                                 0x100228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dorq.i_dorq_cfc_ld_req_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
34239 #define DORQ_REG_MEM003_I_MEM_DFT_K2                                                                 0x10022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dorq.i_dorq_wqe_buf0_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34240 #define DORQ_REG_MEM004_I_MEM_DFT_K2                                                                 0x100230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dorq.i_dorq_wqe_buf1_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34241 #define DORQ_REG_MEM005_I_MEM_DFT_K2                                                                 0x100234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dorq.i_dorq_wqe_buf2_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34242 #define DORQ_REG_MEM006_I_MEM_DFT_K2                                                                 0x100238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance dorq.i_dorq_wqe_buf3_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34243 #define DORQ_REG_PF_MIN_ADDR_REG1                                                                    0x100400UL //Access:RW   DataWidth:0x14  The offset in units of 4KB from the start of the doorbell space to the start of region 1 (PWM region). This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34244 #define DORQ_REG_VF_MIN_ADDR_REG1                                                                    0x100404UL //Access:RW   DataWidth:0x14  The offset in units of 4KB from the start of the doorbell space to the start of region 1 (PWM region). This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34245 #define DORQ_REG_PF_MAX_ICID_0                                                                       0x100408UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 0. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34246 #define DORQ_REG_PF_MAX_ICID_1                                                                       0x10040cUL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 1. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34247 #define DORQ_REG_PF_MAX_ICID_2                                                                       0x100410UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 2. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34248 #define DORQ_REG_PF_MAX_ICID_3                                                                       0x100414UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 3. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34249 #define DORQ_REG_PF_MAX_ICID_4                                                                       0x100418UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 4. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34250 #define DORQ_REG_PF_MAX_ICID_5                                                                       0x10041cUL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 5. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34251 #define DORQ_REG_PF_MAX_ICID_6                                                                       0x100420UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 6. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34252 #define DORQ_REG_PF_MAX_ICID_7                                                                       0x100424UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 7. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34253 #define DORQ_REG_VF_MAX_ICID_0                                                                       0x100428UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 0. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34254 #define DORQ_REG_VF_MAX_ICID_1                                                                       0x10042cUL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 1. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34255 #define DORQ_REG_VF_MAX_ICID_2                                                                       0x100430UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 2. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34256 #define DORQ_REG_VF_MAX_ICID_3                                                                       0x100434UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 3. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34257 #define DORQ_REG_VF_MAX_ICID_4                                                                       0x100438UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 4. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34258 #define DORQ_REG_VF_MAX_ICID_5                                                                       0x10043cUL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 5. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34259 #define DORQ_REG_VF_MAX_ICID_6                                                                       0x100440UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 6. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34260 #define DORQ_REG_VF_MAX_ICID_7                                                                       0x100444UL //Access:RW   DataWidth:0xc   The value in the register, when multiplied by 16, is equal to the maximum ICID plus 1 of connection type 7. This is per PF configuration.  Chips: BB_A0 BB_B0 K2
34261 #define DORQ_REG_PF_ICID_BIT_SHIFT_NORM                                                              0x100448UL //Access:RW   DataWidth:0x2   LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 means 1 DWord (4B) per connection, value of 1 means 2 DWords (8B) and so forth. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34262 #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM                                                              0x10044cUL //Access:RW   DataWidth:0x2   LOG2 of the size of per connection doorbell space footprint in DWORD-s. I.e. value of 0 means 1 DWord (4B) per connection, value of 1 means 2 DWords (8B) and so forth. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34263 #define DORQ_REG_PF_DPI_BIT_SHIFT                                                                    0x100450UL //Access:RW   DataWidth:0x5   Indicates the size of a page in PWM. This is the LOG2 of PWM page size in units of 4KB, i.e. 0 means 4KB page, 1 means 8KB pages and so forth. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34264 #define DORQ_REG_VF_DPI_BIT_SHIFT                                                                    0x100454UL //Access:RW   DataWidth:0x5   Indicates the size of a page in PWM. This is the LOG2 of PWM page size in units of 4KB, i.e. 0 means 4KB page, 1 means 8KB pages and so forth. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34265 #define DORQ_REG_PF_MIN_VAL_DPI                                                                      0x100458UL //Access:RW   DataWidth:0x4   Indicates the LOG2 of PWM pages at the start of PWM region which doesn't require DPI validation. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34266 #define DORQ_REG_VF_MIN_VAL_DPI                                                                      0x10045cUL //Access:RW   DataWidth:0x4   Indicates the LOG2 of PWM pages at the start of PWM region which doesn't require DPI validation. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34267 #define DORQ_REG_DEMS_TARGET_1                                                                       0x100460UL //Access:RW   DataWidth:0x2   Target value used in DEMS mode for DEMS = 1.  Chips: BB_A0 BB_B0 K2
34268 #define DORQ_REG_DEMS_AGG_VAL_SEL_1                                                                  0x100464UL //Access:RW   DataWidth:0x2   AggValSel used in DEMS mode for DEMS = 1. Bit 2 of AggValSel is always 1 in DEMS mode.  Chips: BB_A0 BB_B0 K2
34269 #define DORQ_REG_DEMS_AGG_CMD_1                                                                      0x100468UL //Access:RW   DataWidth:0x2   AggCmd used in DEMS mode for DEMS = 1. Reset value = SET_AG_CMD.  Chips: BB_A0 BB_B0 K2
34270 #define DORQ_REG_DEMS_TARGET_2                                                                       0x10046cUL //Access:RW   DataWidth:0x2   Target value used in DEMS mode for DEMS = 2.  Chips: BB_A0 BB_B0 K2
34271 #define DORQ_REG_DEMS_AGG_VAL_SEL_2                                                                  0x100470UL //Access:RW   DataWidth:0x2   AggValSel used in DEMS mode for DEMS = 2. Bit 2 of AggValSel is always 1 in DEMS mode.  Chips: BB_A0 BB_B0 K2
34272 #define DORQ_REG_DEMS_AGG_CMD_2                                                                      0x100474UL //Access:RW   DataWidth:0x2   AggCmd used in DEMS mode for DEMS = 2. Reset value = SET_AG_CMD.  Chips: BB_A0 BB_B0 K2
34273 #define DORQ_REG_DEMS_TARGET_3                                                                       0x100478UL //Access:RW   DataWidth:0x2   Target value used in DEMS mode for DEMS = 3.  Chips: BB_A0 BB_B0 K2
34274 #define DORQ_REG_DEMS_AGG_VAL_SEL_3                                                                  0x10047cUL //Access:RW   DataWidth:0x2   AggValSel used in DEMS mode for DEMS = 3. Bit 2 of AggValSel is always 1 in DEMS mode.  Chips: BB_A0 BB_B0 K2
34275 #define DORQ_REG_DEMS_AGG_CMD_3                                                                      0x100480UL //Access:RW   DataWidth:0x2   AggCmd used in DEMS mode for DEMS = 3. Reset value = SET_AG_CMD.  Chips: BB_A0 BB_B0 K2
34276 #define DORQ_REG_DEMS_TARGET_4                                                                       0x100484UL //Access:RW   DataWidth:0x2   Target value used in DEMS mode for DEMS = 4.  Chips: BB_A0 BB_B0 K2
34277 #define DORQ_REG_DEMS_AGG_VAL_SEL_4                                                                  0x100488UL //Access:RW   DataWidth:0x2   AggValSel used in DEMS mode for DEMS = 4. Bit 2 of AggValSel is always 1 in DEMS mode.  Chips: BB_A0 BB_B0 K2
34278 #define DORQ_REG_DEMS_AGG_CMD_4                                                                      0x10048cUL //Access:RW   DataWidth:0x2   AggCmd used in DEMS mode for DEMS = 4. Reset value = SET_AG_CMD.  Chips: BB_A0 BB_B0 K2
34279 #define DORQ_REG_DEMS_TARGET_5                                                                       0x100490UL //Access:RW   DataWidth:0x2   Target value used in DEMS mode for DEMS = 5.  Chips: BB_A0 BB_B0 K2
34280 #define DORQ_REG_DEMS_AGG_VAL_SEL_5                                                                  0x100494UL //Access:RW   DataWidth:0x2   AggValSel used in DEMS mode for DEMS = 5. Bit 2 of AggValSel is always 1 in DEMS mode.  Chips: BB_A0 BB_B0 K2
34281 #define DORQ_REG_DEMS_AGG_CMD_5                                                                      0x100498UL //Access:RW   DataWidth:0x2   AggCmd used in DEMS mode for DEMS = 5. Reset value = SET_AG_CMD.  Chips: BB_A0 BB_B0 K2
34282 #define DORQ_REG_DEMS_TARGET_6                                                                       0x10049cUL //Access:RW   DataWidth:0x2   Target value used in DEMS mode for DEMS = 6.  Chips: BB_A0 BB_B0 K2
34283 #define DORQ_REG_DEMS_AGG_VAL_SEL_6                                                                  0x1004a0UL //Access:RW   DataWidth:0x2   AggValSel used in DEMS mode for DEMS = 6. Bit 2 of AggValSel is always 1 in DEMS mode.  Chips: BB_A0 BB_B0 K2
34284 #define DORQ_REG_DEMS_AGG_CMD_6                                                                      0x1004a4UL //Access:RW   DataWidth:0x2   AggCmd used in DEMS mode for DEMS = 6. Reset value = SET_AG_CMD.  Chips: BB_A0 BB_B0 K2
34285 #define DORQ_REG_DEMS_TARGET_7                                                                       0x1004a8UL //Access:RW   DataWidth:0x2   Target value used in DEMS mode for DEMS = 7.  Chips: BB_A0 BB_B0 K2
34286 #define DORQ_REG_DEMS_AGG_VAL_SEL_7                                                                  0x1004acUL //Access:RW   DataWidth:0x2   AggValSel used in DEMS mode for DEMS = 7. Bit 2 of AggValSel is always 1 in DEMS mode.  Chips: BB_A0 BB_B0 K2
34287 #define DORQ_REG_DEMS_AGG_CMD_7                                                                      0x1004b0UL //Access:RW   DataWidth:0x2   AggCmd used in DEMS mode for DEMS = 7. Reset value = SET_AG_CMD.  Chips: BB_A0 BB_B0 K2
34288 #define DORQ_REG_QM_EN_BYP_MASK_0                                                                    0x1004b4UL //Access:RW   DataWidth:0x1   QM Bypass mode is enabled for XCM messages for connection type 0.  Chips: BB_A0 BB_B0 K2
34289 #define DORQ_REG_QM_EN_BYP_MASK_1                                                                    0x1004b8UL //Access:RW   DataWidth:0x1   QM Bypass mode is enabled for XCM messages for connection type 1.  Chips: BB_A0 BB_B0 K2
34290 #define DORQ_REG_QM_EN_BYP_MASK_2                                                                    0x1004bcUL //Access:RW   DataWidth:0x1   QM Bypass mode is enabled for XCM messages for connection type 2.  Chips: BB_A0 BB_B0 K2
34291 #define DORQ_REG_QM_EN_BYP_MASK_3                                                                    0x1004c0UL //Access:RW   DataWidth:0x1   QM Bypass mode is enabled for XCM messages for connection type 3.  Chips: BB_A0 BB_B0 K2
34292 #define DORQ_REG_QM_EN_BYP_MASK_4                                                                    0x1004c4UL //Access:RW   DataWidth:0x1   QM Bypass mode is enabled for XCM messages for connection type 4.  Chips: BB_A0 BB_B0 K2
34293 #define DORQ_REG_QM_EN_BYP_MASK_5                                                                    0x1004c8UL //Access:RW   DataWidth:0x1   QM Bypass mode is enabled for XCM messages for connection type 5.  Chips: BB_A0 BB_B0 K2
34294 #define DORQ_REG_QM_EN_BYP_MASK_6                                                                    0x1004ccUL //Access:RW   DataWidth:0x1   QM Bypass mode is enabled for XCM messages for connection type 6.  Chips: BB_A0 BB_B0 K2
34295 #define DORQ_REG_QM_EN_BYP_MASK_7                                                                    0x1004d0UL //Access:RW   DataWidth:0x1   QM Bypass mode is enabled for XCM messages for connection type 7.  Chips: BB_A0 BB_B0 K2
34296 #define DORQ_REG_DPI_VAL_SUP_0                                                                       0x1004d4UL //Access:RW   DataWidth:0x1   Indicates whether DPI validation is supported for connection type 0.  Chips: BB_A0 BB_B0 K2
34297 #define DORQ_REG_DPI_VAL_SUP_1                                                                       0x1004d8UL //Access:RW   DataWidth:0x1   Indicates whether DPI validation is supported for connection type 1.  Chips: BB_A0 BB_B0 K2
34298 #define DORQ_REG_DPI_VAL_SUP_2                                                                       0x1004dcUL //Access:RW   DataWidth:0x1   Indicates whether DPI validation is supported for connection type 2.  Chips: BB_A0 BB_B0 K2
34299 #define DORQ_REG_DPI_VAL_SUP_3                                                                       0x1004e0UL //Access:RW   DataWidth:0x1   Indicates whether DPI validation is supported for connection type 3.  Chips: BB_A0 BB_B0 K2
34300 #define DORQ_REG_DPI_VAL_SUP_4                                                                       0x1004e4UL //Access:RW   DataWidth:0x1   Indicates whether DPI validation is supported for connection type 4.  Chips: BB_A0 BB_B0 K2
34301 #define DORQ_REG_DPI_VAL_SUP_5                                                                       0x1004e8UL //Access:RW   DataWidth:0x1   Indicates whether DPI validation is supported for connection type 5.  Chips: BB_A0 BB_B0 K2
34302 #define DORQ_REG_DPI_VAL_SUP_6                                                                       0x1004ecUL //Access:RW   DataWidth:0x1   Indicates whether DPI validation is supported for connection type 6.  Chips: BB_A0 BB_B0 K2
34303 #define DORQ_REG_DPI_VAL_SUP_7                                                                       0x1004f0UL //Access:RW   DataWidth:0x1   Indicates whether DPI validation is supported for connection type 7.  Chips: BB_A0 BB_B0 K2
34304 #define DORQ_REG_PWM_AGG_CMD                                                                         0x1004f4UL //Access:RW   DataWidth:0x2   AGG command value in PWM non-DPM mode.  Chips: BB_A0 BB_B0 K2
34305 #define DORQ_REG_CM_AC_UPD                                                                           0x1004f8UL //Access:RW   DataWidth:0x8   Activity counter initial value.  Chips: BB_A0 BB_B0 K2
34306 #define DORQ_REG_WAKE_MISC_EN                                                                        0x1004fcUL //Access:RW   DataWidth:0x1   Enables sending early wakeup indication towards MISC. This is per port configuration.  Chips: BB_A0 BB_B0 K2
34307 #define DORQ_REG_PF_NET_PORT_ID                                                                      0x100500UL //Access:RW   DataWidth:0x2   Indicates network port ID that this PF belongs to. In 2 port mode it is equal to 0 for all PF-s. In 4 port mode, it is equal to 0 for even PF-s and to 1 for off PF-s.  Chips: BB_A0 BB_B0 K2
34308 #define DORQ_REG_PF_WAKE_ALL                                                                         0x100504UL //Access:RW   DataWidth:0x1   Indicates that a doorbell on this PF should send wakeup indication on all ports. This is a per PF per configuration. Should be set in case of coupled mode teaming. Otherwise should be clear.  Chips: BB_A0 BB_B0 K2
34309 #define DORQ_REG_PF_DB_ENABLE                                                                        0x100508UL //Access:RW   DataWidth:0x1   Enable doorbells for this PF. In case not set the doorbell is silently dropped. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34310 #define DORQ_REG_VF_DB_ENABLE                                                                        0x10050cUL //Access:RW   DataWidth:0x1   Enable doorbells for this VF. In case not set the doorbell is silently dropped. This is a per VF configuration.  Chips: BB_A0 BB_B0 K2
34311 #define DORQ_REG_PF_DPM_ENABLE                                                                       0x100510UL //Access:RW   DataWidth:0x1   Enable DPM doorbells for this PF. In case not set the DPM doorbell is aborted. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34312 #define DORQ_REG_VF_DPM_ENABLE                                                                       0x100514UL //Access:RW   DataWidth:0x1   Enable DPM doorbells for all this PF child VF-s. In case not set the DPM doorbell is aborted. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34313 #define DORQ_REG_DPM_L2_SUCC_CFLG_CMD                                                                0x100600UL //Access:RW   DataWidth:0x8   The value of the counter flag command for successful L2 EDPM.  Chips: BB_A0 BB_B0 K2
34314 #define DORQ_REG_DPM_L2_ABRT_CFLG_CMD                                                                0x100604UL //Access:RW   DataWidth:0x8   The value of the counter flag command for unsuccessful L2 EDPM.  Chips: BB_A0 BB_B0 K2
34315 #define DORQ_REG_DPM_L2_SUCC_AGG_CMD                                                                 0x100608UL //Access:RW   DataWidth:0x10  Aggregation value command in case of successful L2 EDPM.  Chips: BB_A0 BB_B0 K2
34316 #define DORQ_REG_DPM_LEG_ROCE_AGG_CMD                                                                0x10060cUL //Access:RW   DataWidth:0x10  Aggregation value command in case of legacy and RoCE EDPM for both abort and success.  Chips: BB_A0 BB_B0 K2
34317 #define DORQ_REG_DPM_L2_ABRT_AGG_CMD                                                                 0x100610UL //Access:RW   DataWidth:0x10  Aggregation value command in case of aborted L2 EDPM.  Chips: BB_A0 BB_B0 K2
34318 #define DORQ_REG_XCM_AGG_FLG_MASK_CONN_0                                                             0x100614UL //Access:RW   DataWidth:0x8   Enable for XCM counter flag command for connection 0.  Chips: BB_A0 BB_B0 K2
34319 #define DORQ_REG_XCM_AGG_FLG_MASK_CONN_1                                                             0x100618UL //Access:RW   DataWidth:0x8   Enable for XCM counter flag command for connection 1.  Chips: BB_A0 BB_B0 K2
34320 #define DORQ_REG_XCM_AGG_FLG_MASK_CONN_2                                                             0x10061cUL //Access:RW   DataWidth:0x8   Enable for XCM counter flag command for connection 2.  Chips: BB_A0 BB_B0 K2
34321 #define DORQ_REG_XCM_AGG_FLG_MASK_CONN_3                                                             0x100620UL //Access:RW   DataWidth:0x8   Enable for XCM counter flag command for connection 3.  Chips: BB_A0 BB_B0 K2
34322 #define DORQ_REG_XCM_AGG_FLG_MASK_CONN_4                                                             0x100624UL //Access:RW   DataWidth:0x8   Enable for XCM counter flag command for connection 4.  Chips: BB_A0 BB_B0 K2
34323 #define DORQ_REG_XCM_AGG_FLG_MASK_CONN_5                                                             0x100628UL //Access:RW   DataWidth:0x8   Enable for XCM counter flag command for connection 5.  Chips: BB_A0 BB_B0 K2
34324 #define DORQ_REG_XCM_AGG_FLG_MASK_CONN_6                                                             0x10062cUL //Access:RW   DataWidth:0x8   Enable for XCM counter flag command for connection 6.  Chips: BB_A0 BB_B0 K2
34325 #define DORQ_REG_XCM_AGG_FLG_MASK_CONN_7                                                             0x100630UL //Access:RW   DataWidth:0x8   Enable for XCM counter flag command for connection 7.  Chips: BB_A0 BB_B0 K2
34326 #define DORQ_REG_TCM_AGG_FLG_MASK_CONN_0                                                             0x100634UL //Access:RW   DataWidth:0x8   Enable for TCM counter flag command for connection 0.  Chips: BB_A0 BB_B0 K2
34327 #define DORQ_REG_TCM_AGG_FLG_MASK_CONN_1                                                             0x100638UL //Access:RW   DataWidth:0x8   Enable for TCM counter flag command for connection 1.  Chips: BB_A0 BB_B0 K2
34328 #define DORQ_REG_TCM_AGG_FLG_MASK_CONN_2                                                             0x10063cUL //Access:RW   DataWidth:0x8   Enable for TCM counter flag command for connection 2.  Chips: BB_A0 BB_B0 K2
34329 #define DORQ_REG_TCM_AGG_FLG_MASK_CONN_3                                                             0x100640UL //Access:RW   DataWidth:0x8   Enable for TCM counter flag command for connection 3.  Chips: BB_A0 BB_B0 K2
34330 #define DORQ_REG_TCM_AGG_FLG_MASK_CONN_4                                                             0x100644UL //Access:RW   DataWidth:0x8   Enable for TCM counter flag command for connection 4.  Chips: BB_A0 BB_B0 K2
34331 #define DORQ_REG_TCM_AGG_FLG_MASK_CONN_5                                                             0x100648UL //Access:RW   DataWidth:0x8   Enable for TCM counter flag command for connection 5.  Chips: BB_A0 BB_B0 K2
34332 #define DORQ_REG_TCM_AGG_FLG_MASK_CONN_6                                                             0x10064cUL //Access:RW   DataWidth:0x8   Enable for TCM counter flag command for connection 6.  Chips: BB_A0 BB_B0 K2
34333 #define DORQ_REG_TCM_AGG_FLG_MASK_CONN_7                                                             0x100650UL //Access:RW   DataWidth:0x8   Enable for TCM counter flag command for connection 7.  Chips: BB_A0 BB_B0 K2
34334 #define DORQ_REG_UCM_AGG_FLG_MASK_CONN_0                                                             0x100654UL //Access:RW   DataWidth:0x8   Enable for UCM counter flag command for connection 0.  Chips: BB_A0 BB_B0 K2
34335 #define DORQ_REG_UCM_AGG_FLG_MASK_CONN_1                                                             0x100658UL //Access:RW   DataWidth:0x8   Enable for UCM counter flag command for connection 1.  Chips: BB_A0 BB_B0 K2
34336 #define DORQ_REG_UCM_AGG_FLG_MASK_CONN_2                                                             0x10065cUL //Access:RW   DataWidth:0x8   Enable for UCM counter flag command for connection 2.  Chips: BB_A0 BB_B0 K2
34337 #define DORQ_REG_UCM_AGG_FLG_MASK_CONN_3                                                             0x100660UL //Access:RW   DataWidth:0x8   Enable for UCM counter flag command for connection 3.  Chips: BB_A0 BB_B0 K2
34338 #define DORQ_REG_UCM_AGG_FLG_MASK_CONN_4                                                             0x100664UL //Access:RW   DataWidth:0x8   Enable for UCM counter flag command for connection 4.  Chips: BB_A0 BB_B0 K2
34339 #define DORQ_REG_UCM_AGG_FLG_MASK_CONN_5                                                             0x100668UL //Access:RW   DataWidth:0x8   Enable for UCM counter flag command for connection 5.  Chips: BB_A0 BB_B0 K2
34340 #define DORQ_REG_UCM_AGG_FLG_MASK_CONN_6                                                             0x10066cUL //Access:RW   DataWidth:0x8   Enable for UCM counter flag command for connection 6.  Chips: BB_A0 BB_B0 K2
34341 #define DORQ_REG_UCM_AGG_FLG_MASK_CONN_7                                                             0x100670UL //Access:RW   DataWidth:0x8   Enable for UCM counter flag command for connection 7.  Chips: BB_A0 BB_B0 K2
34342 #define DORQ_REG_XCM_AGG_CMD_MASK_CONN_0                                                             0x100674UL //Access:RW   DataWidth:0x8   Enable for XCM aggregation value command for connection 0.  Chips: BB_A0 BB_B0 K2
34343 #define DORQ_REG_XCM_AGG_CMD_MASK_CONN_1                                                             0x100678UL //Access:RW   DataWidth:0x8   Enable for XCM aggregation value command for connection 1.  Chips: BB_A0 BB_B0 K2
34344 #define DORQ_REG_XCM_AGG_CMD_MASK_CONN_2                                                             0x10067cUL //Access:RW   DataWidth:0x8   Enable for XCM aggregation value command for connection 2.  Chips: BB_A0 BB_B0 K2
34345 #define DORQ_REG_XCM_AGG_CMD_MASK_CONN_3                                                             0x100680UL //Access:RW   DataWidth:0x8   Enable for XCM aggregation value command for connection 3.  Chips: BB_A0 BB_B0 K2
34346 #define DORQ_REG_XCM_AGG_CMD_MASK_CONN_4                                                             0x100684UL //Access:RW   DataWidth:0x8   Enable for XCM aggregation value command for connection 4.  Chips: BB_A0 BB_B0 K2
34347 #define DORQ_REG_XCM_AGG_CMD_MASK_CONN_5                                                             0x100688UL //Access:RW   DataWidth:0x8   Enable for XCM aggregation value command for connection 5.  Chips: BB_A0 BB_B0 K2
34348 #define DORQ_REG_XCM_AGG_CMD_MASK_CONN_6                                                             0x10068cUL //Access:RW   DataWidth:0x8   Enable for XCM aggregation value command for connection 6.  Chips: BB_A0 BB_B0 K2
34349 #define DORQ_REG_XCM_AGG_CMD_MASK_CONN_7                                                             0x100690UL //Access:RW   DataWidth:0x8   Enable for XCM aggregation value command for connection 7.  Chips: BB_A0 BB_B0 K2
34350 #define DORQ_REG_TCM_AGG_CMD_MASK_CONN_0                                                             0x100694UL //Access:RW   DataWidth:0x8   Enable for TCM aggregation value command for connection 0.  Chips: BB_A0 BB_B0 K2
34351 #define DORQ_REG_TCM_AGG_CMD_MASK_CONN_1                                                             0x100698UL //Access:RW   DataWidth:0x8   Enable for TCM aggregation value command for connection 1.  Chips: BB_A0 BB_B0 K2
34352 #define DORQ_REG_TCM_AGG_CMD_MASK_CONN_2                                                             0x10069cUL //Access:RW   DataWidth:0x8   Enable for TCM aggregation value command for connection 2.  Chips: BB_A0 BB_B0 K2
34353 #define DORQ_REG_TCM_AGG_CMD_MASK_CONN_3                                                             0x1006a0UL //Access:RW   DataWidth:0x8   Enable for TCM aggregation value command for connection 3.  Chips: BB_A0 BB_B0 K2
34354 #define DORQ_REG_TCM_AGG_CMD_MASK_CONN_4                                                             0x1006a4UL //Access:RW   DataWidth:0x8   Enable for TCM aggregation value command for connection 4.  Chips: BB_A0 BB_B0 K2
34355 #define DORQ_REG_TCM_AGG_CMD_MASK_CONN_5                                                             0x1006a8UL //Access:RW   DataWidth:0x8   Enable for TCM aggregation value command for connection 5.  Chips: BB_A0 BB_B0 K2
34356 #define DORQ_REG_TCM_AGG_CMD_MASK_CONN_6                                                             0x1006acUL //Access:RW   DataWidth:0x8   Enable for TCM aggregation value command for connection 6.  Chips: BB_A0 BB_B0 K2
34357 #define DORQ_REG_TCM_AGG_CMD_MASK_CONN_7                                                             0x1006b0UL //Access:RW   DataWidth:0x8   Enable for TCM aggregation value command for connection 7.  Chips: BB_A0 BB_B0 K2
34358 #define DORQ_REG_UCM_AGG_CMD_MASK_CONN_0                                                             0x1006b4UL //Access:RW   DataWidth:0x8   Enable for UCM aggregation value command for connection 0.  Chips: BB_A0 BB_B0 K2
34359 #define DORQ_REG_UCM_AGG_CMD_MASK_CONN_1                                                             0x1006b8UL //Access:RW   DataWidth:0x8   Enable for UCM aggregation value command for connection 1.  Chips: BB_A0 BB_B0 K2
34360 #define DORQ_REG_UCM_AGG_CMD_MASK_CONN_2                                                             0x1006bcUL //Access:RW   DataWidth:0x8   Enable for UCM aggregation value command for connection 2.  Chips: BB_A0 BB_B0 K2
34361 #define DORQ_REG_UCM_AGG_CMD_MASK_CONN_3                                                             0x1006c0UL //Access:RW   DataWidth:0x8   Enable for UCM aggregation value command for connection 3.  Chips: BB_A0 BB_B0 K2
34362 #define DORQ_REG_UCM_AGG_CMD_MASK_CONN_4                                                             0x1006c4UL //Access:RW   DataWidth:0x8   Enable for UCM aggregation value command for connection 4.  Chips: BB_A0 BB_B0 K2
34363 #define DORQ_REG_UCM_AGG_CMD_MASK_CONN_5                                                             0x1006c8UL //Access:RW   DataWidth:0x8   Enable for UCM aggregation value command for connection 5.  Chips: BB_A0 BB_B0 K2
34364 #define DORQ_REG_UCM_AGG_CMD_MASK_CONN_6                                                             0x1006ccUL //Access:RW   DataWidth:0x8   Enable for UCM aggregation value command for connection 6.  Chips: BB_A0 BB_B0 K2
34365 #define DORQ_REG_UCM_AGG_CMD_MASK_CONN_7                                                             0x1006d0UL //Access:RW   DataWidth:0x8   Enable for UCM aggregation value command for connection 7.  Chips: BB_A0 BB_B0 K2
34366 #define DORQ_REG_DPM_XCM_EVENT_ID_0                                                                  0x1006d4UL //Access:RW   DataWidth:0x8   Event ID in XCM message in DPM doorbell for connection type 0.  Chips: BB_A0 BB_B0 K2
34367 #define DORQ_REG_DPM_XCM_EVENT_ID_1                                                                  0x1006d8UL //Access:RW   DataWidth:0x8   Event ID in XCM message in DPM doorbell for connection type 1.  Chips: BB_A0 BB_B0 K2
34368 #define DORQ_REG_DPM_XCM_EVENT_ID_2                                                                  0x1006dcUL //Access:RW   DataWidth:0x8   Event ID in XCM message in DPM doorbell for connection type 2.  Chips: BB_A0 BB_B0 K2
34369 #define DORQ_REG_DPM_XCM_EVENT_ID_3                                                                  0x1006e0UL //Access:RW   DataWidth:0x8   Event ID in XCM message in DPM doorbell for connection type 3.  Chips: BB_A0 BB_B0 K2
34370 #define DORQ_REG_DPM_XCM_EVENT_ID_4                                                                  0x1006e4UL //Access:RW   DataWidth:0x8   Event ID in XCM message in DPM doorbell for connection type 4.  Chips: BB_A0 BB_B0 K2
34371 #define DORQ_REG_DPM_XCM_EVENT_ID_5                                                                  0x1006e8UL //Access:RW   DataWidth:0x8   Event ID in XCM message in DPM doorbell for connection type 5.  Chips: BB_A0 BB_B0 K2
34372 #define DORQ_REG_DPM_XCM_EVENT_ID_6                                                                  0x1006ecUL //Access:RW   DataWidth:0x8   Event ID in XCM message in DPM doorbell for connection type 6.  Chips: BB_A0 BB_B0 K2
34373 #define DORQ_REG_DPM_XCM_EVENT_ID_7                                                                  0x1006f0UL //Access:RW   DataWidth:0x8   Event ID in XCM message in DPM doorbell for connection type 7.  Chips: BB_A0 BB_B0 K2
34374 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE                                                                 0x1006f4UL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass.  Chips: BB_A0
34375 #define DORQ_REG_XCM_AGG_TYPE                                                                        0x1006f8UL //Access:RW   DataWidth:0x5   The value of AggDecType in CM header in XCM message in case of no ROCE/legacy DPM.  Chips: BB_A0 BB_B0 K2
34376 #define DORQ_REG_UCM_AGG_TYPE                                                                        0x1006fcUL //Access:RW   DataWidth:0x5   The value of AggDecType in CM header in UCM message.  Chips: BB_A0 BB_B0 K2
34377 #define DORQ_REG_TCM_AGG_TYPE                                                                        0x100700UL //Access:RW   DataWidth:0x5   The value of AggDecType in CM header in TCM message.  Chips: BB_A0 BB_B0 K2
34378 #define DORQ_REG_EDPM_AGG_TYPE                                                                       0x100704UL //Access:RW   DataWidth:0x5   The value of the AggDecType in the XCM message in case of legacy DPM and ROCE EDPM and QM bypass.  Chips: BB_A0 BB_B0 K2
34379 #define DORQ_REG_XCM_SM_CTX_LD_ST_FLG_DPM                                                            0x100708UL //Access:RW   DataWidth:0x1   The value of the SmCtxLdStFlg in XCM header in case of EDPM and legacy DPM.  Chips: BB_A0 BB_B0 K2
34380 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE_0                                                               0x10070cUL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 0.  Chips: BB_B0 K2
34381 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE_1                                                               0x100710UL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 1.  Chips: BB_B0 K2
34382 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE_2                                                               0x100714UL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 2.  Chips: BB_B0 K2
34383 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE_3                                                               0x100718UL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 3.  Chips: BB_B0 K2
34384 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE_4                                                               0x10071cUL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 4.  Chips: BB_B0 K2
34385 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE_5                                                               0x100720UL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 5.  Chips: BB_B0 K2
34386 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE_6                                                               0x100724UL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 6.  Chips: BB_B0 K2
34387 #define DORQ_REG_QM_BYP_AGG_CTX_SIZE_7                                                               0x100728UL //Access:RW   DataWidth:0x4   The size of the AGG context to be loaded to the XSTORM in case of RoCE or legacy EDPM or QM bypass. Per connection type 7.  Chips: BB_B0 K2
34388 #define DORQ_REG_XCM_CCFC_REGN                                                                       0x100800UL //Access:RW   DataWidth:0x8   The CCFC regions to be loaded on XCM doorbell which is non DPM and non QM bypass doorbells.  Chips: BB_A0 BB_B0 K2
34389 #define DORQ_REG_XCM_CCFC_REGN_BYP                                                                   0x100804UL //Access:RW   DataWidth:0x8   The CCFC regions to be loaded on XCM doorbell on bypass or DPM.  Chips: BB_A0 BB_B0 K2
34390 #define DORQ_REG_TCM_CCFC_REGN                                                                       0x100808UL //Access:RW   DataWidth:0x8   The CCFC regions to be loaded on TCM doorbell.  Chips: BB_A0 BB_B0 K2
34391 #define DORQ_REG_UCM_CCFC_REGN                                                                       0x10080cUL //Access:RW   DataWidth:0x8   The CCFC regions to be loaded on UCM doorbell.  Chips: BB_A0 BB_B0 K2
34392 #define DORQ_REG_CFC_LOAD_MINI_CACHE_EN                                                              0x100810UL //Access:RW   DataWidth:0x1   If set then CCFC mini-cache is enabled.  Chips: BB_A0 BB_B0 K2
34393 #define DORQ_REG_DQ_FIFO_AFULL_TH                                                                    0x100814UL //Access:RW   DataWidth:0xa   DORQ FIFO almost full threshold (in FIFO entries).  Chips: BB_A0 BB_B0 K2
34394 #define DORQ_REG_DPM_XCM_DB_ABRT_TH                                                                  0x100818UL //Access:RW   DataWidth:0xa   If XCM doorbell counter is above this threshold and first DPM doorbell appears it is truncated to one entry and aborted; non-first doorbell is dropped. (Measured in FIFO entries).  Chips: BB_A0 BB_B0 K2
34395 #define DORQ_REG_DQ_FIFO_OVFL_TH                                                                     0x10081cUL //Access:RW   DataWidth:0xa   DORQ FIFO overflow threshold. If DORQ FIFO fill level is above this threshold any doorbell is silently dropped. (Measured in FIFO entries).  Chips: BB_A0
34396 #define DORQ_REG_DPM_ENT_ABRT_TH                                                                     0x100820UL //Access:RW   DataWidth:0xa   If DORQ FIFO fill level is above this threshold and first DPM doorbell appears it is truncated to one entry and DpmAbort flag is set; non-first doorbell is silently dropped. Is calculated in entries.  Chips: BB_A0 BB_B0 K2
34397 #define DORQ_REG_MASK_XCM_EN                                                                         0x100824UL //Access:RW   DataWidth:0x1   If set, then XCM bypass enable bit will be masked (XCM bypass considered always asserted).  Chips: BB_A0 BB_B0 K2
34398 #define DORQ_REG_MASK_QM_EN                                                                          0x100828UL //Access:RW   DataWidth:0x1   If set, then QM bypass enable bit will be masked (considered always asserted).  Chips: BB_A0 BB_B0 K2
34399 #define DORQ_REG_MASK_PBF_ROCE_EN                                                                    0x10082cUL //Access:RW   DataWidth:0x1   If set, then PBF bypass enable bit will be masked (considered always asserted) for RoCE EDPM.  Chips: BB_A0 BB_B0 K2
34400 #define DORQ_REG_MASK_PBF_L2_EN                                                                      0x100830UL //Access:RW   DataWidth:0x1   If set, then QM bypass enable bit will be masked (considered always asserted) for L2 for L2 EDPM.  Chips: BB_A0 BB_B0 K2
34401 #define DORQ_REG_DPM_TIMEOUT                                                                         0x100834UL //Access:RW   DataWidth:0xc   Timeout (measured in main clock cycles) for DPM operation to complete.  Chips: BB_A0 BB_B0 K2
34402 #define DORQ_REG_EDPM_EXIST_IN_QM_EN                                                                 0x100838UL //Access:RW   DataWidth:0x4   Indicates which ExistInQm bits are taken into account in the EDPM check. If a bit equals 0 then the corresponding ExistInQm is not used (masked).  Chips: BB_A0 BB_B0 K2
34403 #define DORQ_REG_DQ_PXP_FULL_EN                                                                      0x10083cUL //Access:RW   DataWidth:0x1   If 1, then full is asserted towards PXP when DORQ FIFO fill level is equal or greater than dq_fifo_full_thr. If 0, then doorbell is discarded when DORQ FIFO is full.  Chips: BB_B0 K2
34404 #define DORQ_REG_DQ_FIFO_FULL_TH                                                                     0x100840UL //Access:RW   DataWidth:0xa   DORQ FIFO full threshold (in FIFO entries). If DORQ FIFO fill level is equal or greater than it and dq_pxp_full_en is 1, then full is asserted towards PXP. If DORQ FIFO fill level is equal or greater than it and dq_pxp_full_en is 0, then full is not asserted towards PXP and doorbell is dropped or truncated.  Chips: BB_B0 K2
34405 #define DORQ_REG_DQ_FULL_CYCLES                                                                      0x100844UL //Access:RW   DataWidth:0xe   Number of cycles in which full towards PXP is asserted if DORQ is in almost full state.  Chips: BB_B0 K2
34406 #define DORQ_REG_ROCE_ETHERTYPE                                                                      0x100880UL //Access:RW   DataWidth:0x10  RoCE Ethertype used for RoCE packet generation in EDPM mode.  Chips: BB_A0
34407 #define DORQ_REG_TAG1_ETHERTYPE                                                                      0x100884UL //Access:RW   DataWidth:0x10  Tag 1 Ethertype used for packet generation in RoCE EDPM mode. Default is set to SVLAN.  Chips: BB_A0 BB_B0 K2
34408 #define DORQ_REG_TAG2_ETHERTYPE                                                                      0x100888UL //Access:RW   DataWidth:0x10  Tag 2 Ethertype used for packet generation in RoCE EDPM mode. Default is set to CVLAN.  Chips: BB_A0 BB_B0 K2
34409 #define DORQ_REG_TAG3_ETHERTYPE                                                                      0x10088cUL //Access:RW   DataWidth:0x10  Tag 3 Ethertype used for packet generation in RoCE EDPM mode. Default is set to TTAG.  Chips: BB_A0 BB_B0 K2
34410 #define DORQ_REG_TAG4_ETHERTYPE                                                                      0x100890UL //Access:RW   DataWidth:0x10  Tag 4 Ethertype used for packet generation in RoCE EDPM mode. Default is set to CN.  Chips: BB_A0 BB_B0 K2
34411 #define DORQ_REG_TAG1_SIZE                                                                           0x100894UL //Access:RW   DataWidth:0x2   Size of the Tag 1 used for packet generation in RoCE EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - 6 bytes;  Chips: BB_A0 BB_B0 K2
34412 #define DORQ_REG_TAG2_SIZE                                                                           0x100898UL //Access:RW   DataWidth:0x2   Size of the Tag 2 used for packet generation in RoCE EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - 6 bytes;  Chips: BB_A0 BB_B0 K2
34413 #define DORQ_REG_TAG3_SIZE                                                                           0x10089cUL //Access:RW   DataWidth:0x2   Size of the Tag 3 used for packet generation in RoCE EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - 6 bytes;  Chips: BB_A0 BB_B0 K2
34414 #define DORQ_REG_TAG4_SIZE                                                                           0x1008a0UL //Access:RW   DataWidth:0x2   Size of the Tag 4 used for packet generation in RoCE EDPM mode not including Ethertype itself. 0 - Reserved; 1 - 2 bytes; 2 - 4 bytes; 3 - 6 bytes;  Chips: BB_A0 BB_B0 K2
34415 #define DORQ_REG_GRH_NXT_HEADER                                                                      0x1008a4UL //Access:RW   DataWidth:0x8   GRH Next Header used for packet generation in RoCE EDPM.  Chips: BB_A0 BB_B0 K2
34416 #define DORQ_REG_BTH_TVER                                                                            0x1008a8UL //Access:RW   DataWidth:0x4   TVER value in RoCE BTH header.  Chips: BB_A0 BB_B0 K2
34417 #define DORQ_REG_ROCE_OPCODE_EN                                                                      0x1008acUL //Access:RW   DataWidth:0x20  Enable bit per each RoCE Opcode 5 LSB-s. N-th bit set means corresponding opcode N is enabled, if reset the RoCE DPM with this opcode is aborted.  Chips: BB_A0 BB_B0 K2
34418 #define DORQ_REG_CRC32_BSWAP                                                                         0x1008b0UL //Access:RW   DataWidth:0x1   If 0 - the CRC-32 final calculation result isn't byte swapped; if 1 - the CRC-32 final calculation result is byte swapped (byte [7:0] goes to location [31:24];etc).  Chips: BB_A0 BB_B0 K2
34419 #define DORQ_REG_TAG1_OVRD_MODE                                                                      0x1008b4UL //Access:RW   DataWidth:0x2   Indicates which type of override of the TAG content read from the PCM context is required. The possible values are: 0 ? No override 1 ? Full override (external VLAN Id + PCP) 2 ? PCP (priority) only 3 ? reserved Note that this mode is relevant only if size of the TAG (not including the Ethertype) is 2 bytes. Otherwise there is no override.  Chips: BB_B0 K2
34420 #define DORQ_REG_TAG2_OVRD_MODE                                                                      0x1008b8UL //Access:RW   DataWidth:0x2   Indicates which type of override of the TAG content read from the PCM context is required. The possible values are: 0 ? No override 1 ? Full override (external VLAN Id + PCP) 2 ? PCP (priority) only 3 ? reserved Note that this mode is relevant only if size of the TAG (not including the Ethertype) is 2 bytes. Otherwise there is no override.  Chips: BB_B0 K2
34421 #define DORQ_REG_TAG3_OVRD_MODE                                                                      0x1008bcUL //Access:RW   DataWidth:0x2   Indicates which type of override of the TAG content read from the PCM context is required. The possible values are: 0 ? No override 1 ? Full override (external VLAN Id + PCP) 2 ? PCP (priority) only 3 ? reserved Note that this mode is relevant only if size of the TAG (not including the Ethertype) is 2 bytes. Otherwise there is no override.  Chips: BB_B0 K2
34422 #define DORQ_REG_TAG4_OVRD_MODE                                                                      0x1008c0UL //Access:RW   DataWidth:0x2   Indicates which type of override of the TAG content read from the PCM context is required. The possible values are: 0 ? No override 1 ? Full override (external VLAN Id + PCP) 2 ? PCP (priority) only 3 ? reserved Note that this mode is relevant only if size of the TAG (not including the Ethertype) is 2 bytes. Otherwise there is no override.  Chips: BB_B0 K2
34423 #define DORQ_REG_PF_PCP                                                                              0x1008c4UL //Access:RW   DataWidth:0x4   The priority value and DEI bit of RoCE frames per PF.  Chips: BB_B0 K2
34424 #define DORQ_REG_PF_EXT_VID                                                                          0x1008c8UL //Access:RW   DataWidth:0xc   The external VLAN ID per PF.  Chips: BB_B0 K2
34425 #define DORQ_REG_RROCE_DST_UDP_PORT                                                                  0x1008ccUL //Access:RW   DataWidth:0x10  The content of the destination UDP port of RROCE.  Chips: BB_B0 K2
34426 #define DORQ_REG_ROCE_ETHER_TYPE                                                                     0x1008d0UL //Access:RW   DataWidth:0x10  RoCE Ethertype used for RoCE packet generation in EDPM mode. 0 ? plain ROCE; 1 ? RROCE (ROCEv2) over IPV4;  2 ? RROCE (ROCEv2) over IPV6.  Chips: BB_B0 K2
34427 #define DORQ_REG_ROCE_ETHER_TYPE_SIZE                                                                3
34428 #define DORQ_REG_L2_EDPM_NUM_BD_THR                                                                  0x100900UL //Access:RW   DataWidth:0x10  L2 EDPM BDs threshold. If overcome, the L2 EDPM context check fails.  Chips: BB_A0 BB_B0 K2
34429 #define DORQ_REG_L2_EDPM_EXT_HDR_SIZE                                                                0x100904UL //Access:RW   DataWidth:0x8   Size in Words of header extracted by PBF and sent to PSTORM in L2.  Chips: BB_A0 BB_B0 K2
34430 #define DORQ_REG_L2_EDPM_EXT_HDR_OFFS                                                                0x100908UL //Access:RW   DataWidth:0x8   Offset in Words of header extracted by PBF and sent to PSTORM in L2.  Chips: BB_A0 BB_B0 K2
34431 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN                                                           0x10090cUL //Access:RW   DataWidth:0x1   Indicates whether Ethernet over GRE header is expected in packet payload.  Chips: BB_A0 BB_B0 K2
34432 #define DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN                                                            0x100910UL //Access:RW   DataWidth:0x1   Indicates whether IP over GRE header is expected in packet payload.  Chips: BB_A0 BB_B0 K2
34433 #define DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN                                                             0x100914UL //Access:RW   DataWidth:0x1   Indicates whether VXLAN header is expected in packet payload.  Chips: BB_A0 BB_B0 K2
34434 #define DORQ_REG_L2_EDPM_ST_HINT                                                                     0x100918UL //Access:RW   DataWidth:0x2   TPH Hint value in case of non-inline L2 EDPM.  Chips: BB_A0 BB_B0 K2
34435 #define DORQ_REG_L2_EDPM_ATC_FLAGS                                                                   0x10091cUL //Access:RW   DataWidth:0x3   ATC attribute value of non-inline L2 EDPM.  Chips: BB_A0 BB_B0 K2
34436 #define DORQ_REG_PCM_START_OFFS                                                                      0x100920UL //Access:RW   DataWidth:0x5   Start offset to read PCM STORM context. Measured in REGQ.  Chips: BB_A0 BB_B0 K2
34437 #define DORQ_REG_MAX_L2_EDPM_PKT_SIZE                                                                0x100924UL //Access:RW   DataWidth:0xe   Maximum non-inline L2 EDPM PktSize.  Chips: BB_A0 BB_B0 K2
34438 #define DORQ_REG_L2_EDPM_PKT_HDR_SIZE                                                                0x100928UL //Access:RW   DataWidth:0x8   The maximum number of WORD-s which the PBF may add to the L2 packet.  Chips: BB_A0 BB_B0 K2
34439 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN                                                            0x10092cUL //Access:RW   DataWidth:0x1   Set to 1 if IP over NGE header is expected in the packet payload.  Chips: K2
34440 #define DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN                                                           0x100930UL //Access:RW   DataWidth:0x1   Set to 1 if Ethernet over NGE header is expected in the packet payload.  Chips: K2
34441 #define DORQ_REG_XCM_MSG_INIT_CRD                                                                    0x100980UL //Access:RW   DataWidth:0x3   XCM message interface initial credit.  Chips: BB_A0 BB_B0 K2
34442 #define DORQ_REG_TCM_MSG_INIT_CRD                                                                    0x100984UL //Access:RW   DataWidth:0x3   TCM message interface initial credit.  Chips: BB_A0 BB_B0 K2
34443 #define DORQ_REG_UCM_MSG_INIT_CRD                                                                    0x100988UL //Access:RW   DataWidth:0x3   UCM message interface initial credit.  Chips: BB_A0 BB_B0 K2
34444 #define DORQ_REG_PBF_CMD_INIT_CRD                                                                    0x10098cUL //Access:RW   DataWidth:0x6   PBF command interface initial credit.  Chips: BB_A0 BB_B0 K2
34445 #define DORQ_REG_PF_USAGE_CNT                                                                        0x1009c0UL //Access:R    DataWidth:0xb   Counter of DORQ FIFO entries used by corresponding PF or any of its child VF-s.  Chips: BB_A0 BB_B0 K2
34446 #define DORQ_REG_VF_USAGE_CNT                                                                        0x1009c4UL //Access:R    DataWidth:0xb   Counter of DORQ FIFO entries used by corresponding VF.  Chips: BB_A0 BB_B0 K2
34447 #define DORQ_REG_PF_USAGE_CNT_LIM                                                                    0x1009c8UL //Access:RW   DataWidth:0xb   Maximum number of DORQ FIFO entries used by corresponding PF or any of its child VF-s. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34448 #define DORQ_REG_VF_USAGE_CNT_LIM                                                                    0x1009ccUL //Access:RW   DataWidth:0xb   Maximum number of DORQ FIFO entries used by a VF which is a child VF of corresponding PF. This is a per PF configuration.  Chips: BB_A0 BB_B0 K2
34449 #define DORQ_REG_PF_OVFL_STICKY                                                                      0x1009d0UL //Access:RW   DataWidth:0x1   If set, PF doorbell with corresponding PF is silently dropped at the entrance to DORQ FIFO. This is a per PF configuration. Is cleared by write of 0.  Chips: BB_A0 BB_B0 K2
34450 #define DORQ_REG_VF_OVFL_STICKY                                                                      0x1009d4UL //Access:RW   DataWidth:0x1   If set, VF doorbell with corresponding VF, is silently dropped at the entrance to DORQ FIFO. This is a per VF configuration. Is cleared by write of 0.  Chips: BB_A0 BB_B0 K2
34451 #define DORQ_REG_DPM_FORCE_ABORT                                                                     0x1009d8UL //Access:W    DataWidth:0x1   Aborts all the current DPM entries which are not FREE.  Chips: BB_A0 BB_B0 K2
34452 #define DORQ_REG_DB_DROP_REASON_MASK                                                                 0x1009dcUL //Access:RW   DataWidth:0x14  A bit mask per doorbell drop reason. If a bit is set (1), then corresponding drop reason will cause attention be set. If a bit is not set (0), then corresponding drop reason will not cause interrupt.  Chips: BB_A0 BB_B0 K2
34453 #define DORQ_REG_AUTO_FREEZE_EN                                                                      0x1009e0UL //Access:RW   DataWidth:0x1   If set, DORQ enters freeze mode on the first doorbell drop due to DORQ FIFO overflow. The freeze mode means that DORQ stops sending CFC load requests. The freeze mode will remain until auto_drop_rel (Write Only) register is set.  Chips: BB_A0 BB_B0 K2
34454 #define DORQ_REG_AUTO_FREEZE_ST                                                                      0x1009e4UL //Access:R    DataWidth:0x1   When set, auto freeze is active and doorbells are not being popped from the FIFO. Cleared when auto_freeze_rel is written.  Chips: BB_A0 BB_B0 K2
34455 #define DORQ_REG_AUTO_FREEZE_REL                                                                     0x1009e8UL //Access:W    DataWidth:0x1   Release the freeze mode set by auto_freeze_en. Write only.  Chips: BB_A0 BB_B0 K2
34456 #define DORQ_REG_AUTO_DROP_EN                                                                        0x1009ecUL //Access:RW   DataWidth:0x1   If set, DORQ enters auto drop mode on the first doorbell drop due to DORQ FIFO overflow. In this mode all incoming doorbells will be dropped even if the FIFO is not full anymore. The drop mode will remain until auto_drop_rel (Write Only) register is set.  Chips: BB_A0 BB_B0 K2
34457 #define DORQ_REG_AUTO_DROP_ST                                                                        0x1009f0UL //Access:R    DataWidth:0x1   When set, auto discard mode is active and all doorbells are dropped at the entrance to DORQ FIFO.  De-asserted when auto_discard_rel is written.  Chips: BB_A0 BB_B0 K2
34458 #define DORQ_REG_AUTO_DROP_REL                                                                       0x1009f4UL //Access:W    DataWidth:0x1   Releases the auto_drop mode. Write only.  Chips: BB_A0 BB_B0 K2
34459 #define DORQ_REG_PXP_TRANS_SIZE                                                                      0x1009f8UL //Access:RW   DataWidth:0x8   Size in bytes of the PXP transactions to be counted in the pxp_trans_cnt  register (including address cycle).  Chips: BB_A0 BB_B0 K2
34460 #define DORQ_REG_DB_INGRESS_CNT                                                                      0x1009fcUL //Access:R    DataWidth:0x20  Accounts for any non-DPM doorbell or first DPM doorbell, which are not silently dropped. Will rollover to 0 when incremented above all ones.  Chips: BB_A0 BB_B0 K2
34461 #define DORQ_REG_DB_EGRESS_CNT                                                                       0x100a00UL //Access:R    DataWidth:0x20  Incremented for each message sent to any one of CMs. Will rollover to 0 when incremented above all ones.  Chips: BB_A0 BB_B0 K2
34462 #define DORQ_REG_CFC_LD_MAX_OUTS_REQ                                                                 0x100a04UL //Access:RW   DataWidth:0x6   Maximum allowed number of outstanding CFC load requests.  Chips: BB_A0 BB_B0 K2
34463 #define DORQ_REG_CFC_LD_REQ_FIFO_FILL_LVL                                                            0x100a08UL //Access:R    DataWidth:0x6   CFC load request FIFO current fill level (in entries).  Chips: BB_A0 BB_B0 K2
34464 #define DORQ_REG_DORQ_FIFO_FILL_LVL                                                                  0x100a0cUL //Access:R    DataWidth:0xb   DORQ FIFO current fill level (in entries REGQ each).  Chips: BB_A0 BB_B0 K2
34465 #define DORQ_REG_DORQ_FIFO_FILL_LVL_ST                                                               0x100a10UL //Access:RC   DataWidth:0xb   DORQ FIFO sticky fill level (in entries REGQ each). Is cleared on read.  Chips: BB_A0 BB_B0 K2
34466 #define DORQ_REG_DORQ_FIFO_NXT_INF_UNIT                                                              0x100a14UL //Access:R    DataWidth:0x5   Debug only: read from DORQ FIFO: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
34467 #define DORQ_REG_DB_DROP_CNT                                                                         0x100a18UL //Access:R    DataWidth:0x20  Accounts for number of dropped doorbells. See db_drop_reason for drop reason.  Will rollover to 0 when incremented above all ones.  Chips: BB_A0 BB_B0 K2
34468 #define DORQ_REG_DB_DROP_DETAILS_ADDRESS                                                             0x100a1cUL //Access:R    DataWidth:0x20  Stores the details of the first dropped doorbell after logging was re-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell address (in  case of drops from DORQ FIFO DpmOffset is stored)..  Chips: BB_A0 BB_B0 K2
34469 #define DORQ_REG_DB_DROP_DETAILS_REASON                                                              0x100a20UL //Access:R    DataWidth:0x14  Stores the details of the first dropped doorbell after logging was re-armed by db_drop_details_rel. The following details of the transaction will be recorded: Doorbell drop reason: 0 - Size of the data is not equal to 4 or to a multiple of 8 bytes; 1 - 2 LSB-s of the address are not zeroes (no DWORD alignment); 2 - The size of the data in the transaction is a multiple of 8 bytes and the 3 LSB-s of the address are not zeroes (not QWORD aligned); 3 - ICID is out of maximum allowed range; 4 - PWM doorbell to reserved register; 5 - Size miss-match: 32b doorbell (non-DPM) written to 64b register (non-DPM or DPM). Will be distinguished as the write with (pxp_dorq_eop_bvalid=4) to 64b PWM register; 6 - DPI check is not supported for this connection/task type and DPI is not zero; 7 - Non-first DPM doorbell and FIFO fill level (in QREG-s) is above a threshold (dpm_ent_abrt_th). 8 - Non-first DPM doorbell and XCM doorbell counter is above the threshold (dpm_xcm_db_abrt_th); 9 - PF doorbell appears and its corresponding PF sticky overflow bit (pf_ovfl_sticky[pf]) is set; 10 - VF doorbell appears and its corresponding VF sticky overflow bit (vf_ovfl_sticky[vf]) is set or its corresponding parent PF sticky overflow bit (pf_ovfl_sticky[pf]) is set (or both); 11 - PF doorbell appears and its corresponding PF is disabled in pf_db_en; 12 - VF doorbell appears and its corresponding PF is disabled in vf_db_en; 13 - Global overflow; 14 - The first byte enable field is not equal to all ones; 15 - The length (in DWORD-s) of the transaction is more than 1 payload DWORD and the last byte enable is not equal to all ones 16 - Auto drop 17 - Non first DPM doorbell arrived and there is no matching DPM entry 18 - Non first DPM doorbell arrived and non-contigious offset in a DPM transaction 19 - Non first DPM doorbell arrived beyond the DPM size  Chips: BB_A0 BB_B0 K2
34470 #define DORQ_REG_DB_DROP_DETAILS                                                                     0x100a24UL //Access:R    DataWidth:0x17  Stores the details of the first dropped doorbell after logging was re-armed by db_drop_details_rel. The following details of the transaction will be recorded: bits[15:0]   Doorbell opaque FID; bits[22:16]  Doorbell size in in DWords (calculated according to "length");  Chips: BB_A0 BB_B0 K2
34471 #define DORQ_REG_DB_DROP_DETAILS_REL                                                                 0x100a28UL //Access:W    DataWidth:0x1   Clears db_drop_details and makes it ready for the next details capture. Write only.  Chips: BB_A0 BB_B0 K2
34472 #define DORQ_REG_DB_DROP_REASON                                                                      0x100a2cUL //Access:R    DataWidth:0x14  Sticky status of drop reason (a bit per reason). It is reset on write to db_drop_details_rel. 0 - Size of the data is not equal to 4 or to a multiple of 8 bytes; 1 - 2 LSB-s of the address are not zeroes (no DWORD alignment); 2 - The size of the data in the transaction is a multiple of 8 bytes and the 3 LSB-s of the address are not zeroes (not QWORD aligned); 3 - ICID is out of maximum allowed range; 4 - PWM doorbell to reserved register; 5 - Size miss-match: 32b doorbell (non-DPM) written to 64b register (non-DPM or DPM). Will be distinguished as the write with (pxp_dorq_eop_bvalid=4) to 64b PWM register; 6 - DPI check is not supported for this connection/task type and DPI is not zero; 7 - Non-first DPM doorbell and FIFO fill level (in QREG-s) is above a threshold (dpm_ent_abrt_th). 8 - Non-first DPM doorbell and XCM doorbell counter is above the threshold (dpm_xcm_db_abrt_th); 9 - PF doorbell appears and its corresponding PF sticky overflow bit (pf_ovfl_sticky[pf]) is set; 10 - VF doorbell appears and its corresponding VF sticky overflow bit (vf_ovfl_sticky[vf]) is set or its corresponding parent PF sticky overflow bit (pf_ovfl_sticky[pf]) is set (or both); 11 - PF doorbell appears and its corresponding PF is disabled in pf_db_en; 12 - VF doorbell appears and its corresponding PF is disabled in pf_db_en or its VF is disabled in vf_db_en; 13 - Global overflow; 14 - The first byte enable field is not equal to all ones; 15 - The length (in DWORD-s) of the transaction is more than 1 payload DWORD and the last byte enable is not equal to all ones 16 - Autodrop 17 - Non first DPM doorbell arrived and there is no matching DPM entry 18 - Non first DPM doorbell arrived and non-contigious offset in a DPM transaction 19 - Non first DPM doorbell arrived beyond the DPM size  Chips: BB_A0 BB_B0 K2
34473 #define DORQ_REG_DPM_ABORT_CNT                                                                       0x100a30UL //Access:R    DataWidth:0x20  Accounts for number of aborted doorbells. See dpm_abort_reason for abort reason. Will rollover to 0 when incremented above all ones.  Chips: BB_A0 BB_B0 K2
34474 #define DORQ_REG_DPM_ABORT_DETAILS_DB_VAL                                                            0x100a34UL //Access:R    DataWidth:0x10  Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: DbVal[15:0].  Chips: BB_A0 BB_B0 K2
34475 #define DORQ_REG_DPM_ABORT_DETAILS_WID                                                               0x100a38UL //Access:R    DataWidth:0x8   Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Doorbell WID;  Chips: BB_A0 BB_B0 K2
34476 #define DORQ_REG_DPM_ABORT_DETAILS_DPI                                                               0x100a3cUL //Access:R    DataWidth:0x10  Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: bits[15:0]    Doorbell DPI;  Chips: BB_A0 BB_B0 K2
34477 #define DORQ_REG_DPM_ABORT_DETAILS_CID                                                               0x100a40UL //Access:R    DataWidth:0x20  Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: Doorbell CID;  Chips: BB_A0 BB_B0 K2
34478 #define DORQ_REG_DPM_ABORT_DETAILS_REASON                                                            0x100a44UL //Access:R    DataWidth:0x12  Stores the details of the first aborted doorbell after this register was cleared. It is reset on write to db_abort_details_rel. The following details of the transaction will be recorded: 0 - DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - PF DPM doorbell and its corresponding PF is disabled in pf_dpm_en; 2 - VF DPM doorbell and its corresponding PF is disabled in vf_dpm_en; 3 - First DPM doorbell and FIFO fill level (in QREG-s) is above threshold (dpm_ent_abrt_th); 4 - First DPM doorbell and XCM doorbell counter is above threshold (dpm_xcm_db_abrt_th); 5 - First DPM doorbell and illegal DpmSize; 6 - First DPM doorbell and illegal WqeSize/PktSize; 7 - First DPM doorbell and illegal RoCEFlags/SgeNum; 8 - First RoCE EDPM doorbell and opcode[4:0] does not match allowed by roce_opcode_en; 9 - Non-DPM or first DPM doorbell with CID of not fully collected DPM doorbell in WQE buffer; 10 - First DPM doorbell with {fid,dpi,wid} of not fully collected DPM doorbell in WQE buffer; 11 - First DPM doorbell does not match DPM global start conditions; 12 - Non-first DPM doorbell with {fid,dpi,wid} of DPM doorbell in WQE buffer and matched doorbell offset is not contiguous; 13 - CFC load response with error; 14 - EDPM context check fails; 15 - DPM timer expired; 16 - Force abort; 17 - Size mis-match: 32b doorbell (normal region or PWM non-DPM) is written to DpmReg[0];  Chips: BB_A0 BB_B0 K2
34479 #define DORQ_REG_DPM_ABORT_DETAILS_REL                                                               0x100a48UL //Access:W    DataWidth:0x1   Clears db_abort_details and makes it ready for the next details capture. Write only.  Chips: BB_A0 BB_B0 K2
34480 #define DORQ_REG_DPM_ABORT_REASON                                                                    0x100a4cUL //Access:R    DataWidth:0x12  Sticky status of abort reason (a bit per reason). It is reset on write to db_abort_details_rel. 0 - DPM doorbell and rewind configuration of DPM timer (dpm_timeout) is 0; 1 - First DPM doorbell and PF DPM doorbell and its corresponding PF is disabled in pf_dpm_en; 2 - First DPM doorbell and VF DPM doorbell and its corresponding PF is disabled in vf_dpm_en; 3 - First DPM doorbell and FIFO fill level (in QREG-s) is above threshold (dpm_ent_abrt_th); 4 - First DPM doorbell and XCM doorbell counter is above threshold (dpm_xcm_db_abrt_th); 5 - First DPM doorbell and illegal DpmSize; 6 - First DPM doorbell and illegal WqeSize/PktSize; 7 - First DPM doorbell and illegal RoCEFlags/SgeNum; 8 - First RoCE EDPM doorbell and opcode[4:0] does not match allowed by roce_opcode_en; 9 - Non-DPM or first DPM doorbell with CID of not fully collected DPM doorbell in WQE buffer; 10 - First DPM doorbell with {fid,dpi,wid} of not fully collected DPM doorbell in WQE buffer; 11 - First DPM doorbell does not match DPM global start conditions; 12 - Non-first DPM doorbell with {fid,dpi,wid} of DPM doorbell in WQE buffer and matched doorbell offset is not contiguous; 13 - CFC load response with error; 14 - EDPM context check fails; 15 - DPM timer expired; 16 - Force abort; 17 - Size mis-match: 32b doorbell (normal region or PWM non-DPM) is written to DpmReg[0];  Chips: BB_A0 BB_B0 K2
34481 #define DORQ_REG_DB_EARLY_TRUNC_CNT                                                                  0x100a50UL //Access:RC   DataWidth:0x20  Truncation counter. It is reset on read.  Chips: BB_A0 BB_B0 K2
34482 #define DORQ_REG_DPM_EARLY_ABORT_CNT                                                                 0x100a54UL //Access:RC   DataWidth:0x20  DPM early abort counter. It is reset on read.  Chips: BB_A0 BB_B0 K2
34483 #define DORQ_REG_DPM_TIMER_EXPIR_ABORT_CNT                                                           0x100a58UL //Access:RC   DataWidth:0x20  DPM timer expiration abort counter. It is reset on read.  Chips: BB_A0 BB_B0 K2
34484 #define DORQ_REG_DPM_GLB_COND_ABORT_CNT                                                              0x100a5cUL //Access:RC   DataWidth:0x20  DPM global condition abort counter. It is reset on read.  Chips: BB_A0 BB_B0 K2
34485 #define DORQ_REG_DPM_CTX_CHECK_ABORT_CNT                                                             0x100a60UL //Access:RC   DataWidth:0x20  DPM context check failure abort counter. It is reset on read.  Chips: BB_A0 BB_B0 K2
34486 #define DORQ_REG_DPM_UNCOMPL_ABORT_CNT                                                               0x100a64UL //Access:RC   DataWidth:0x20  DPM uncompleted (arrival of first DPM first on a CID which already has a DPM entry pending for data) abort counter. It is reset on read.  Chips: BB_A0 BB_B0 K2
34487 #define DORQ_REG_DPM_ILLEG_SIZE_ABORT_CNT                                                            0x100a68UL //Access:RC   DataWidth:0x20  DPM Illegal value of DpmSize, WqeSize/PktSize or SgeNum abort counter. It is reset on read.  Chips: BB_A0 BB_B0 K2
34488 #define DORQ_REG_DPM_LEG_SUCCESS_CNT                                                                 0x100a6cUL //Access:RC   DataWidth:0x20  Number of successfull legacy DPM doorbells. It is reset on read.  Chips: BB_A0 BB_B0 K2
34489 #define DORQ_REG_DPM_ROCE_SUCCESS_CNT                                                                0x100a70UL //Access:RC   DataWidth:0x20  Number of successfull RoCE EDPM doorbells. It is reset on read.  Chips: BB_A0 BB_B0 K2
34490 #define DORQ_REG_DPM_L2_SUCCESS_CNT                                                                  0x100a74UL //Access:RC   DataWidth:0x20  Number of successfull L2 EDPM doorbells. It is reset on read.  Chips: BB_A0 BB_B0 K2
34491 #define DORQ_REG_DPM_DATA_CNT                                                                        0x100a78UL //Access:R    DataWidth:0x20  Counter for overall number of DPM doorbells data QWords. Will be calculated by accounting for any first DPM doorbell DpmSize indication.  Chips: BB_A0 BB_B0 K2
34492 #define DORQ_REG_DPM_EARLY_ABORT_DATA_CNT                                                            0x100a7cUL //Access:R    DataWidth:0x20  Counter for the number of DPM doorbells data QWords which were silently dropped or aborted due to early abort. Only first DPM doorbells, which are silently dropped or early aborted will be considered. The increment will be done at first cycle of first DPM doorbell by the size of DpmSize. No non-first DPM doorbells silent drops or aborts are considered.  Chips: BB_A0 BB_B0 K2
34493 #define DORQ_REG_DPM_FIFO_POP_ABORT_DATA_CNT                                                         0x100a80UL //Access:R    DataWidth:0x20  Counter for the number of DPM doorbells data QWords which were discarded or aborted on FIFO pop. Only silent drops and aborts that can be distinguished at the moment of DORQ FIFO pop will be considered and specifically only doorbell that is aborted due to DPM global start conditions.  Chips: BB_A0 BB_B0 K2
34494 #define DORQ_REG_PXP_TRANS_CNT                                                                       0x100a84UL //Access:RC   DataWidth:0x20  Number of PXP transaction of a selected size (including non DPM). The selected size can be a number which is a power of 2 which is between 4 to 256. It is reset on read.  Chips: BB_A0 BB_B0 K2
34495 #define DORQ_REG_DPM_TBL_FILL_LVL                                                                    0x100a88UL //Access:R    DataWidth:0x4   DPM Table fill level.  Chips: BB_A0 BB_B0 K2
34496 #define DORQ_REG_CFC_BYPASS_CNT                                                                      0x100a8cUL //Access:RC   DataWidth:0x20  Counts the number of times CFC bypass occurred.  Chips: BB_A0 BB_B0 K2
34497 #define DORQ_REG_MINI_CACHE_ENTRY                                                                    0x100a90UL //Access:WB_R DataWidth:0x32  Debug only: In case of LCID validation error or load error, the current value of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Region, 31:0 - CID  Chips: BB_A0 BB_B0 K2
34498 #define DORQ_REG_MINI_CACHE_ENTRY_SIZE                                                               2
34499 #define DORQ_REG_CFC_LCRES_ERR_DETAIL                                                                0x100a98UL //Access:WB_R DataWidth:0x25  Debug only: CFC Response error in case mini-cache was used. 36 - CDU Validation Error; 35 - CFC Load Cancel; 34 - CFC Load Error; 33 - CFC LCID validation error; 32 - Doorbell type (0 - non-DPM, 1 - DPM); 31:0 - CID.  Chips: BB_A0 BB_B0 K2
34500 #define DORQ_REG_CFC_LCRES_ERR_DETAIL_SIZE                                                           2
34501 #define DORQ_REG_CFC_LD_REQ_CNT                                                                      0x100aa0UL //Access:RC   DataWidth:0x20  The number of CCFC load requests sent (no bypass).  Chips: BB_A0 BB_B0 K2
34502 #define DORQ_REG_CFC_ERR_CNT                                                                         0x100aa4UL //Access:RC   DataWidth:0x8   Counts the number of CFC load errors.  Chips: BB_A0 BB_B0 K2
34503 #define DORQ_REG_ECO_RESERVED                                                                        0x100aa8UL //Access:RW   DataWidth:0x8   Chicken bits.  Chips: BB_A0 BB_B0 K2
34504 #define DORQ_REG_MEMCTRL_WR_RD_N                                                                     0x100ac0UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
34505 #define DORQ_REG_MEMCTRL_CMD                                                                         0x100ac4UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
34506 #define DORQ_REG_MEMCTRL_ADDRESS                                                                     0x100ac8UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
34507 #define DORQ_REG_MEMCTRL_STATUS                                                                      0x100accUL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0 K2
34508 #define DORQ_REG_DBG_SELECT                                                                          0x100ad0UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
34509 #define DORQ_REG_DBG_DWORD_ENABLE                                                                    0x100ad4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
34510 #define DORQ_REG_DBG_SHIFT                                                                           0x100ad8UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
34511 #define DORQ_REG_DBG_FORCE_VALID                                                                     0x100adcUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
34512 #define DORQ_REG_DBG_FORCE_FRAME                                                                     0x100ae0UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
34513 #define DORQ_REG_DBG_OUT_DATA                                                                        0x100b00UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
34514 #define DORQ_REG_DBG_OUT_DATA_SIZE                                                                   8
34515 #define DORQ_REG_DBG_OUT_VALID                                                                       0x100b20UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
34516 #define DORQ_REG_DBG_OUT_FRAME                                                                       0x100b24UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
34517 #define DORQ_REG_DPM_TBL                                                                             0x100c00UL //Access:WB_R DataWidth:0xa3  Read access to DPM Table. Fields mapping is: [162:159] - DPM FSM state [158:143] - ICID [142:127] - FID16 [126:118] - LCID [117:102] - DbVal[15:0] [101:94] - WID [93:78] - DPI [77] - DPI validation requested [76:71] - DpmCnt (number of received QWords) [70:65] - DpmSize [64] - Abort [63:62] - DPM Type [61:59] - Connection Type [58:51] - Opcode/Number of BDs [50:40] - WqeSize/PktSize [39:37] - RoCEF/g/NumSge [36] - CFC response happened [35] - DPM global start not fulfilled [34] - CFC CDU error [33] - CFC Cancel error [32] - CFC Load error [31:0]  - DpmReg0(Dw1)  Chips: BB_A0 BB_B0 K2
34518 #define DORQ_REG_DPM_TBL_SIZE                                                                        64
34519 #define DORQ_REG_WQE_BUF                                                                             0x101000UL //Access:R    DataWidth:0x20  1) Debug read access to WQE buffer. 2) Initialization write access: write all the addresses modulo 8, i.e. 0, 8, .., 632.  Chips: BB_A0 BB_B0 K2
34520 #define DORQ_REG_WQE_BUF_SIZE                                                                        640
34521 #define DORQ_REG_DORQ_FIFO                                                                           0x108000UL //Access:R    DataWidth:0x20  Debug only: Read access to DQ FIFO.  Chips: BB_A0 BB_B0 K2
34522 #define DORQ_REG_DORQ_FIFO_SIZE                                                                      4100
34523 #define IGU_REG_RESET_MEMORIES                                                                       0x180000UL //Access:RW   DataWidth:0x7   Write one for each bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. Bit 0 - mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and mask memories; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - number of messages sent statistics; Bit 6 - RL memories (variable 0, variable 1 and statistics).  Chips: BB_A0 BB_B0 K2
34524 #define IGU_REG_BLOCK_CONFIGURATION                                                                  0x180040UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34525     #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN                                         (0x1<<0) // If enabled the IGU forwards write/read requests to the TPH interface. 1 - enabled; 0 - disabled.
34526     #define IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN_SHIFT                                   0
34527     #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN                                                (0x1<<1) // If enabled the IGU allows to VF to send cleanup commands on the int ack address. 1 - enabled; 0 - disabled.
34528     #define IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN_SHIFT                                          1
34529     #define IGU_REG_BLOCK_CONFIGURATION_RL_BYPASS_EN                                                 (0x1<<2) // If enabled the IGU allows bypass mode of the rate limiter when the system is empty. 1 - enabled; 0 - disabled.
34530     #define IGU_REG_BLOCK_CONFIGURATION_RL_BYPASS_EN_SHIFT                                           2
34531 #define IGU_REG_PXP_REQUESTER_INITIAL_CREDIT                                                         0x180050UL //Access:RW   DataWidth:0x2   PXP req credit. The max number of outstanding messages to the PXP request. The value can be one or two only.  Chips: BB_A0 BB_B0 K2
34532 #define IGU_REG_CAM_BIST_EN                                                                          0x180060UL //Access:RW   DataWidth:0x1   Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.  Chips: BB_A0 BB_B0
34533 #define IGU_REG_CAM_BIST_SKIP_ERROR_CNT                                                              0x180064UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0
34534 #define IGU_REG_CAM_BIST_STATUS_SEL                                                                  0x180068UL //Access:RW   DataWidth:0x8   Used to select the BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.  Chips: BB_A0 BB_B0
34535 #define IGU_REG_CAM_BIST_STATUS                                                                      0x18006cUL //Access:R    DataWidth:0x20  Provides read-only access to the BIST status word selected by cam_bist_status_sel.  Chips: BB_A0 BB_B0
34536 #define IGU_REG_CAM_BIST_DBG_DATA                                                                    0x180070UL //Access:RW   DataWidth:0x20  For CAM bist usage.  Chips: BB_A0 BB_B0
34537 #define IGU_REG_CAM_BIST_DBG_DATA_VALID                                                              0x180074UL //Access:RW   DataWidth:0x1   For CAM bist usage.  Chips: BB_A0 BB_B0
34538 #define IGU_REG_CAM_BIST_DBG_COMPARE_EN                                                              0x180078UL //Access:RW   DataWidth:0x1   For CAM bist usage.  Chips: BB_A0 BB_B0
34539 #define IGU_REG_INT_STS                                                                              0x180180UL //Access:R    DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34540     #define IGU_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
34541     #define IGU_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
34542     #define IGU_REG_INT_STS_CTRL_FIFO_ERROR_ERR                                                      (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
34543     #define IGU_REG_INT_STS_CTRL_FIFO_ERROR_ERR_SHIFT                                                1
34544     #define IGU_REG_INT_STS_PXP_REQ_LENGTH_TOO_BIG                                                   (0x1<<2) // PXP write message length bigger then one.
34545     #define IGU_REG_INT_STS_PXP_REQ_LENGTH_TOO_BIG_SHIFT                                             2
34546     #define IGU_REG_INT_STS_HOST_TRIES2ACCESS_PROD_UPD                                               (0x1<<3) // Host write producer update command.
34547     #define IGU_REG_INT_STS_HOST_TRIES2ACCESS_PROD_UPD_SHIFT                                         3
34548     #define IGU_REG_INT_STS_VF_TRIES2ACC_ATTN_CMD                                                    (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
34549     #define IGU_REG_INT_STS_VF_TRIES2ACC_ATTN_CMD_SHIFT                                              4
34550     #define IGU_REG_INT_STS_MME_BIGGER_THEN_5                                                        (0x1<<5) // MME value in MSI control is bigger than 5.
34551     #define IGU_REG_INT_STS_MME_BIGGER_THEN_5_SHIFT                                                  5
34552     #define IGU_REG_INT_STS_SB_INDEX_IS_NOT_VALID                                                    (0x1<<6) // Prod / Cons update command to invalid SB index.
34553     #define IGU_REG_INT_STS_SB_INDEX_IS_NOT_VALID_SHIFT                                              6
34554     #define IGU_REG_INT_STS_DURIN_INT_READ_WITH_SIMD_DIS                                             (0x1<<7) // During interrupt read from function that is not in SIMD mode.
34555     #define IGU_REG_INT_STS_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT                                       7
34556     #define IGU_REG_INT_STS_CMD_FID_NOT_MATCH                                                        (0x1<<8) // Command FID not match mapping FID.
34557     #define IGU_REG_INT_STS_CMD_FID_NOT_MATCH_SHIFT                                                  8
34558     #define IGU_REG_INT_STS_SEGMENT_ACCESS_INVALID                                                   (0x1<<9) // Removed.
34559     #define IGU_REG_INT_STS_SEGMENT_ACCESS_INVALID_SHIFT                                             9
34560     #define IGU_REG_INT_STS_ATTN_PROD_ACC                                                            (0x1<<10) // Update producer command to attention producer.
34561     #define IGU_REG_INT_STS_ATTN_PROD_ACC_SHIFT                                                      10
34562 #define IGU_REG_INT_MASK                                                                             0x180184UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34563     #define IGU_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.ADDRESS_ERROR .
34564     #define IGU_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
34565     #define IGU_REG_INT_MASK_CTRL_FIFO_ERROR_ERR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.CTRL_FIFO_ERROR_ERR .
34566     #define IGU_REG_INT_MASK_CTRL_FIFO_ERROR_ERR_SHIFT                                               1
34567     #define IGU_REG_INT_MASK_PXP_REQ_LENGTH_TOO_BIG                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.PXP_REQ_LENGTH_TOO_BIG .
34568     #define IGU_REG_INT_MASK_PXP_REQ_LENGTH_TOO_BIG_SHIFT                                            2
34569     #define IGU_REG_INT_MASK_HOST_TRIES2ACCESS_PROD_UPD                                              (0x1<<3) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.HOST_TRIES2ACCESS_PROD_UPD .
34570     #define IGU_REG_INT_MASK_HOST_TRIES2ACCESS_PROD_UPD_SHIFT                                        3
34571     #define IGU_REG_INT_MASK_VF_TRIES2ACC_ATTN_CMD                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.VF_TRIES2ACC_ATTN_CMD .
34572     #define IGU_REG_INT_MASK_VF_TRIES2ACC_ATTN_CMD_SHIFT                                             4
34573     #define IGU_REG_INT_MASK_MME_BIGGER_THEN_5                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.MME_BIGGER_THEN_5 .
34574     #define IGU_REG_INT_MASK_MME_BIGGER_THEN_5_SHIFT                                                 5
34575     #define IGU_REG_INT_MASK_SB_INDEX_IS_NOT_VALID                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.SB_INDEX_IS_NOT_VALID .
34576     #define IGU_REG_INT_MASK_SB_INDEX_IS_NOT_VALID_SHIFT                                             6
34577     #define IGU_REG_INT_MASK_DURIN_INT_READ_WITH_SIMD_DIS                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.DURIN_INT_READ_WITH_SIMD_DIS .
34578     #define IGU_REG_INT_MASK_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT                                      7
34579     #define IGU_REG_INT_MASK_CMD_FID_NOT_MATCH                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.CMD_FID_NOT_MATCH .
34580     #define IGU_REG_INT_MASK_CMD_FID_NOT_MATCH_SHIFT                                                 8
34581     #define IGU_REG_INT_MASK_SEGMENT_ACCESS_INVALID                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.SEGMENT_ACCESS_INVALID .
34582     #define IGU_REG_INT_MASK_SEGMENT_ACCESS_INVALID_SHIFT                                            9
34583     #define IGU_REG_INT_MASK_ATTN_PROD_ACC                                                           (0x1<<10) // This bit masks, when set, the Interrupt bit: IGU_REG_INT_STS.ATTN_PROD_ACC .
34584     #define IGU_REG_INT_MASK_ATTN_PROD_ACC_SHIFT                                                     10
34585 #define IGU_REG_INT_STS_WR                                                                           0x180188UL //Access:WR   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34586     #define IGU_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
34587     #define IGU_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
34588     #define IGU_REG_INT_STS_WR_CTRL_FIFO_ERROR_ERR                                                   (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
34589     #define IGU_REG_INT_STS_WR_CTRL_FIFO_ERROR_ERR_SHIFT                                             1
34590     #define IGU_REG_INT_STS_WR_PXP_REQ_LENGTH_TOO_BIG                                                (0x1<<2) // PXP write message length bigger then one.
34591     #define IGU_REG_INT_STS_WR_PXP_REQ_LENGTH_TOO_BIG_SHIFT                                          2
34592     #define IGU_REG_INT_STS_WR_HOST_TRIES2ACCESS_PROD_UPD                                            (0x1<<3) // Host write producer update command.
34593     #define IGU_REG_INT_STS_WR_HOST_TRIES2ACCESS_PROD_UPD_SHIFT                                      3
34594     #define IGU_REG_INT_STS_WR_VF_TRIES2ACC_ATTN_CMD                                                 (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
34595     #define IGU_REG_INT_STS_WR_VF_TRIES2ACC_ATTN_CMD_SHIFT                                           4
34596     #define IGU_REG_INT_STS_WR_MME_BIGGER_THEN_5                                                     (0x1<<5) // MME value in MSI control is bigger than 5.
34597     #define IGU_REG_INT_STS_WR_MME_BIGGER_THEN_5_SHIFT                                               5
34598     #define IGU_REG_INT_STS_WR_SB_INDEX_IS_NOT_VALID                                                 (0x1<<6) // Prod / Cons update command to invalid SB index.
34599     #define IGU_REG_INT_STS_WR_SB_INDEX_IS_NOT_VALID_SHIFT                                           6
34600     #define IGU_REG_INT_STS_WR_DURIN_INT_READ_WITH_SIMD_DIS                                          (0x1<<7) // During interrupt read from function that is not in SIMD mode.
34601     #define IGU_REG_INT_STS_WR_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT                                    7
34602     #define IGU_REG_INT_STS_WR_CMD_FID_NOT_MATCH                                                     (0x1<<8) // Command FID not match mapping FID.
34603     #define IGU_REG_INT_STS_WR_CMD_FID_NOT_MATCH_SHIFT                                               8
34604     #define IGU_REG_INT_STS_WR_SEGMENT_ACCESS_INVALID                                                (0x1<<9) // Removed.
34605     #define IGU_REG_INT_STS_WR_SEGMENT_ACCESS_INVALID_SHIFT                                          9
34606     #define IGU_REG_INT_STS_WR_ATTN_PROD_ACC                                                         (0x1<<10) // Update producer command to attention producer.
34607     #define IGU_REG_INT_STS_WR_ATTN_PROD_ACC_SHIFT                                                   10
34608 #define IGU_REG_INT_STS_CLR                                                                          0x18018cUL //Access:RC   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34609     #define IGU_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
34610     #define IGU_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
34611     #define IGU_REG_INT_STS_CLR_CTRL_FIFO_ERROR_ERR                                                  (0x1<<1) // Debug FIFO error. Write to full FIFO or read from empty FIFO.
34612     #define IGU_REG_INT_STS_CLR_CTRL_FIFO_ERROR_ERR_SHIFT                                            1
34613     #define IGU_REG_INT_STS_CLR_PXP_REQ_LENGTH_TOO_BIG                                               (0x1<<2) // PXP write message length bigger then one.
34614     #define IGU_REG_INT_STS_CLR_PXP_REQ_LENGTH_TOO_BIG_SHIFT                                         2
34615     #define IGU_REG_INT_STS_CLR_HOST_TRIES2ACCESS_PROD_UPD                                           (0x1<<3) // Host write producer update command.
34616     #define IGU_REG_INT_STS_CLR_HOST_TRIES2ACCESS_PROD_UPD_SHIFT                                     3
34617     #define IGU_REG_INT_STS_CLR_VF_TRIES2ACC_ATTN_CMD                                                (0x1<<4) // VFID bit is set and the command is to attention bit set/clr/upd.
34618     #define IGU_REG_INT_STS_CLR_VF_TRIES2ACC_ATTN_CMD_SHIFT                                          4
34619     #define IGU_REG_INT_STS_CLR_MME_BIGGER_THEN_5                                                    (0x1<<5) // MME value in MSI control is bigger than 5.
34620     #define IGU_REG_INT_STS_CLR_MME_BIGGER_THEN_5_SHIFT                                              5
34621     #define IGU_REG_INT_STS_CLR_SB_INDEX_IS_NOT_VALID                                                (0x1<<6) // Prod / Cons update command to invalid SB index.
34622     #define IGU_REG_INT_STS_CLR_SB_INDEX_IS_NOT_VALID_SHIFT                                          6
34623     #define IGU_REG_INT_STS_CLR_DURIN_INT_READ_WITH_SIMD_DIS                                         (0x1<<7) // During interrupt read from function that is not in SIMD mode.
34624     #define IGU_REG_INT_STS_CLR_DURIN_INT_READ_WITH_SIMD_DIS_SHIFT                                   7
34625     #define IGU_REG_INT_STS_CLR_CMD_FID_NOT_MATCH                                                    (0x1<<8) // Command FID not match mapping FID.
34626     #define IGU_REG_INT_STS_CLR_CMD_FID_NOT_MATCH_SHIFT                                              8
34627     #define IGU_REG_INT_STS_CLR_SEGMENT_ACCESS_INVALID                                               (0x1<<9) // Removed.
34628     #define IGU_REG_INT_STS_CLR_SEGMENT_ACCESS_INVALID_SHIFT                                         9
34629     #define IGU_REG_INT_STS_CLR_ATTN_PROD_ACC                                                        (0x1<<10) // Update producer command to attention producer.
34630     #define IGU_REG_INT_STS_CLR_ATTN_PROD_ACC_SHIFT                                                  10
34631 #define IGU_REG_PRTY_MASK                                                                            0x180194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34632     #define IGU_REG_PRTY_MASK_CAM_PARITY                                                             (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS.CAM_PARITY .
34633     #define IGU_REG_PRTY_MASK_CAM_PARITY_SHIFT                                                       0
34634 #define IGU_REG_PRTY_MASK_H_0                                                                        0x180204UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
34635     #define IGU_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
34636     #define IGU_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_SHIFT                                          0
34637     #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
34638     #define IGU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_SHIFT                                            1
34639     #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0                                            (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
34640     #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                      1
34641     #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
34642     #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                      1
34643     #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                               (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
34644     #define IGU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                         2
34645     #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
34646     #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      2
34647     #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<2) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
34648     #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      2
34649     #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                               (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
34650     #define IGU_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                         3
34651     #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
34652     #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                      3
34653     #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
34654     #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                      3
34655     #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                               (0x1<<4) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
34656     #define IGU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                         4
34657     #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
34658     #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                      4
34659     #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
34660     #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      4
34661     #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
34662     #define IGU_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                         5
34663     #define IGU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
34664     #define IGU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            6
34665     #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0                                                (0x1<<7) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
34666     #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_SHIFT                                          7
34667     #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1                                                (0x1<<8) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
34668     #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_SHIFT                                          8
34669     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_A0                                          (0x1<<7) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
34670     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_A0_SHIFT                                    7
34671     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_B0                                          (0x1<<7) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
34672     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_BB_B0_SHIFT                                    7
34673     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_K2                                             (0x1<<9) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_0 .
34674     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_0_K2_SHIFT                                       9
34675     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB_A0                                          (0x1<<8) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
34676     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB_A0_SHIFT                                    8
34677     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB_B0                                          (0x1<<8) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
34678     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_BB_B0_SHIFT                                    8
34679     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_K2                                             (0x1<<10) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_1 .
34680     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_1_K2_SHIFT                                       10
34681     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2                                                (0x1<<11) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY_2 .
34682     #define IGU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_2_SHIFT                                          11
34683     #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
34684     #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            12
34685     #define IGU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
34686     #define IGU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                            13
34687     #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_0                                                (0x1<<14) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY_0 .
34688     #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_0_SHIFT                                          14
34689     #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_1                                                (0x1<<15) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY_1 .
34690     #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_1_SHIFT                                          15
34691     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_BB_A0                                          (0x1<<14) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_0 .
34692     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_BB_A0_SHIFT                                    14
34693     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_BB_B0                                          (0x1<<14) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_0 .
34694     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_BB_B0_SHIFT                                    14
34695     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_K2                                             (0x1<<16) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_0 .
34696     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_K2_SHIFT                                       16
34697     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_BB_A0                                          (0x1<<15) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_1 .
34698     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_BB_A0_SHIFT                                    15
34699     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_BB_B0                                          (0x1<<15) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_1 .
34700     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_BB_B0_SHIFT                                    15
34701     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_K2                                             (0x1<<17) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_1 .
34702     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_1_K2_SHIFT                                       17
34703     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_2                                                (0x1<<18) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_2 .
34704     #define IGU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_2_SHIFT                                          18
34705     #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
34706     #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                            19
34707     #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0                                                (0x1<<20) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 .
34708     #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_SHIFT                                          20
34709     #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_1                                                (0x1<<21) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_1 .
34710     #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_1_SHIFT                                          21
34711     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_BB_A0                                          (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_0 .
34712     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_BB_A0_SHIFT                                    26
34713     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_BB_B0                                          (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_0 .
34714     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_BB_B0_SHIFT                                    26
34715     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_K2                                             (0x1<<22) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_0 .
34716     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_0_K2_SHIFT                                       22
34717     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_BB_A0                                          (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
34718     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_BB_A0_SHIFT                                    27
34719     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_BB_B0                                          (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
34720     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_BB_B0_SHIFT                                    27
34721     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_K2                                             (0x1<<23) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_1 .
34722     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_1_K2_SHIFT                                       23
34723     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_BB_A0                                          (0x1<<28) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
34724     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_BB_A0_SHIFT                                    28
34725     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_BB_B0                                          (0x1<<28) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
34726     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_BB_B0_SHIFT                                    28
34727     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_K2                                             (0x1<<24) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY_2 .
34728     #define IGU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_2_K2_SHIFT                                       24
34729     #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                            (0x1<<29) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
34730     #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                      29
34731     #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                            (0x1<<29) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
34732     #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                      29
34733     #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                               (0x1<<25) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
34734     #define IGU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                         25
34735     #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
34736     #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                            26
34737     #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0                                            (0x1<<30) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
34738     #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0_SHIFT                                      30
34739     #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0                                            (0x1<<30) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
34740     #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0_SHIFT                                      30
34741     #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                               (0x1<<27) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
34742     #define IGU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                         27
34743     #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
34744     #define IGU_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_SHIFT                                            5
34745     #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0                                                (0x1<<9) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
34746     #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_SHIFT                                          9
34747     #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1                                                (0x1<<10) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
34748     #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_SHIFT                                          10
34749     #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_2                                                (0x1<<11) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_2 .
34750     #define IGU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_2_SHIFT                                          11
34751     #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
34752     #define IGU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            12
34753     #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0                                                (0x1<<16) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
34754     #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_SHIFT                                          16
34755     #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1                                                (0x1<<17) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
34756     #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_SHIFT                                          17
34757     #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2                                                (0x1<<18) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_2 .
34758     #define IGU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2_SHIFT                                          18
34759     #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
34760     #define IGU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                            19
34761     #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_2                                                (0x1<<22) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_2 .
34762     #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_2_SHIFT                                          22
34763     #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_3                                                (0x1<<23) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_3 .
34764     #define IGU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_3_SHIFT                                          23
34765     #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_0                                                (0x1<<24) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY_0 .
34766     #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_0_SHIFT                                          24
34767     #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_1                                                (0x1<<25) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY_1 .
34768     #define IGU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_1_SHIFT                                          25
34769 #define IGU_REG_PRTY_MASK_H_1_BB_A0                                                                  0x180214UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0
34770 #define IGU_REG_PRTY_MASK_H_1_BB_B0                                                                  0x180214UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0
34771     #define IGU_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: IGU_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
34772     #define IGU_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_SHIFT                                            0
34773 #define IGU_REG_MEM_ECC_EVENTS_BB_A0                                                                 0x18022cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0
34774 #define IGU_REG_MEM_ECC_EVENTS_BB_B0                                                                 0x18022cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_B0
34775 #define IGU_REG_MEM_ECC_EVENTS_K2                                                                    0x18021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
34776 #define IGU_REG_MEM020_I_CAM_DFT_K2                                                                  0x180224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.i_mapping_cam.i_cam of module ts_28hpc_tcam_111_hs_e_t_shlas_376x24_pbn_bist_wr. [2]=rme, [1:0]=t_strw.  Chips: K2
34777 #define IGU_REG_MEM015_I_MEM_DFT_K2                                                                  0x180228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.i_igu_err_dbg_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
34778 #define IGU_REG_MEM016_I_MEM_DFT_K2                                                                  0x18022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.i_igu_ips_last_served_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34779 #define IGU_REG_MEM017_I_MEM_DFT_K2                                                                  0x180230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.i_igu_ips_sts_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34780 #define IGU_REG_MEM018_I_MEM_DFT_K2                                                                  0x180234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.i_igu_ips_var0_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34781 #define IGU_REG_MEM019_I_MEM_DFT_K2                                                                  0x180238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.i_igu_ips_var1_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34782 #define IGU_REG_MEM001_I_MEM_DFT_K2                                                                  0x18023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_ATTN_16_PF_IF.i_igu_attn_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34783 #define IGU_REG_MEM002_I_MEM_DFT_K2                                                                  0x180240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_BEFORE_MASK_16_PF_IF.i_igu_before_mask_pf_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34784 #define IGU_REG_MEM004_I_MEM_DFT_K2                                                                  0x180244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_BEFORE_MASK_21_VF_HIGH_IF.i_igu_before_mask_vf_high_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34785 #define IGU_REG_MEM003_I_MEM_DFT_K2                                                                  0x180248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_BEFORE_MASK_192_VF_LOW_IF.i_igu_before_mask_vf_low_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34786 #define IGU_REG_MEM005_I_MEM_DFT_K2                                                                  0x18024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_CONS_368_SB_16_PF_IF.i_igu_cons_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34787 #define IGU_REG_MEM006_I_MEM_DFT_K2                                                                  0x180250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_MASK_16_PF_IF.i_igu_mask_pf_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34788 #define IGU_REG_MEM008_I_MEM_DFT_K2                                                                  0x180254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_MASK_21_VF_HIGH_IF.i_igu_mask_vf_high_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34789 #define IGU_REG_MEM007_I_MEM_DFT_K2                                                                  0x180258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_MASK_192_VF_LOW_IF.i_igu_mask_vf_low_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34790 #define IGU_REG_MEM009_I_MEM_DFT_K2                                                                  0x18025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_MSIX_368_SB_IF.i_igu_msix_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34791 #define IGU_REG_MEM010_I_MEM_DFT_K2                                                                  0x180260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_PBA_16_PF_IF.i_igu_pba_pf_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34792 #define IGU_REG_MEM012_I_MEM_DFT_K2                                                                  0x180264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_PBA_21_VF_HIGH_IF.i_igu_pba_vf_high_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34793 #define IGU_REG_MEM011_I_MEM_DFT_K2                                                                  0x180268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_PBA_192_VF_LOW_IF.i_igu_pba_vf_low_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34794 #define IGU_REG_MEM013_I_MEM_DFT_K2                                                                  0x18026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_PROD_368_SB_16_PF_IF.i_igu_prod_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34795 #define IGU_REG_MEM014_I_MEM_DFT_K2                                                                  0x180270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance igu.IGU_PXP_ARB_STS_192_VF_16_PF_IF.i_igu_pxp_arb_sts_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
34796 #define IGU_REG_STATISTIC_NUM_PF_MSG_SENT                                                            0x180400UL //Access:RW   DataWidth:0x14  Debug: Number of MSI/MSIX/ATTN messages sent for the PF: address 0 - number of MSI/MSIX messages; address 1 - number of ATTN messages.  Chips: BB_A0 BB_B0 K2
34797 #define IGU_REG_STATISTIC_NUM_PF_MSG_SENT_SIZE                                                       2
34798 #define IGU_REG_STATISTIC_NUM_VF_MSG_SENT                                                            0x180408UL //Access:RW   DataWidth:0x14  Debug: Number of MSI/MSIX messages sent for VF.  Chips: BB_A0 BB_B0 K2
34799 #define IGU_REG_PXP_REQUEST_COUNTER                                                                  0x18040cUL //Access:R    DataWidth:0x20  Debug: number of PXP messeges sent (attention, msi and msix).  Chips: BB_A0 BB_B0 K2
34800 #define IGU_REG_PXP_WRITE_DONE_COUNTER                                                               0x180410UL //Access:R    DataWidth:0x20  Debug: number of PXP write done received (attention, msi and msix).  Chips: BB_A0 BB_B0 K2
34801 #define IGU_REG_PXP_REQ_COUNTER_CTL                                                                  0x180414UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34802     #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM                                       (0x1ff<<0) // Debug: SB index for the counter.
34803     #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM_SHIFT                                 0
34804     #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM_MASK_EN                               (0x1<<9) // Debug: if set the counter is active.
34805     #define IGU_REG_PXP_REQ_COUNTER_CTL_PXP_REQ_COUNTER_SB_NUM_MASK_EN_SHIFT                         9
34806 #define IGU_REG_PXP_REQ_COUNTER                                                                      0x180418UL //Access:RC   DataWidth:0x20  Debug: count the number of PXP requests sent on behalf of a specific MSI/MSI-X vector on the SB index in pxp_req_counter_sb_num.  Chips: BB_A0 BB_B0 K2
34807 #define IGU_REG_PROD_UPD_COUNTER_CTL                                                                 0x18041cUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34808     #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM                                     (0x1ff<<0) // Debug: SB index for the counter.
34809     #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM_SHIFT                               0
34810     #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM_MASK_EN                             (0x1<<9) // Debug: if set the counter is active.
34811     #define IGU_REG_PROD_UPD_COUNTER_CTL_PROD_UPD_COUNTER_SB_NUM_MASK_EN_SHIFT                       9
34812 #define IGU_REG_PROD_UPD_COUNTER                                                                     0x180420UL //Access:RC   DataWidth:0x20  Debug: count the number of PROD update requests which arrived on a specific SB, on the SB index in prod_upd_counter_sb_num.                   If the SB number in the configuration is all ones the counter counts for all the SB indexes.  Chips: BB_A0 BB_B0 K2
34813 #define IGU_REG_CONS_UPD_COUNTER_CTL                                                                 0x180424UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34814     #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM                                     (0x1ff<<0) // Debug: SB index for the counter.
34815     #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM_SHIFT                               0
34816     #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM_MASK_EN                             (0x1<<9) // Debug: if set th counter is active.
34817     #define IGU_REG_CONS_UPD_COUNTER_CTL_CONS_UPD_COUNTER_SB_NUM_MASK_EN_SHIFT                       9
34818 #define IGU_REG_CONS_UPD_COUNTER                                                                     0x180428UL //Access:RC   DataWidth:0x20  Debug: count tnumber of CONS update requests which arrived on a specific SB, on the SB index in cons_upd_counter_sb_num. If the SB number in the configuration is all ones the counter counts for all the SB indexes.  Chips: BB_A0 BB_B0 K2
34819 #define IGU_REG_STATISTIC_NUM_OF_INTA_ASSERTED                                                       0x18042cUL //Access:RW   DataWidth:0x14  Number of interrupt assertion for the PF.  Chips: BB_A0 BB_B0 K2
34820 #define IGU_REG_RATE_LIMITER_STATISTICS                                                              0x180600UL //Access:RW   DataWidth:0x14  IPS statistics - number of messages sent for each group.  Chips: BB_A0 BB_B0 K2
34821 #define IGU_REG_RATE_LIMITER_STATISTICS_SIZE                                                         64
34822 #define IGU_REG_PF_CONFIGURATION                                                                     0x180800UL //Access:RW   DataWidth:0x6   b0 - function enable; b1 - MSI/MSIX enable; b2 - INT enable; b3 - attention enable; b4 - single ISR mode enable; b5 - simd all ones mode - If clear (reset value):If the result of SB_before_mask & MASK is 0xFFFF_FFFF then the read result will be 0x7FFF_FFFF and the mask will be also 0x7FFF_FFFF. Therefore the interrupt is not de-asserted (the MSB SB is asserted and unmasked). And on the next read from SIMD with mask the result will be 0x8000_0000 and only now the interrupt will be de-asserted. If set: If the result of SB_before_mask & MASK is 0xFFFF_FFFF then the read result will be 0x7FFF_FFFF but the mask will be 0xFFFF_FFFF. Therefore the interrupt is de-asserted. And on the next read from SIMD with mask the result will be 0x0.  Chips: BB_A0 BB_B0 K2
34823 #define IGU_REG_VF_CONFIGURATION                                                                     0x180804UL //Access:RW   DataWidth:0x9   d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d8:d5 parent PF (BB supports only 0-7 PF).  Chips: BB_A0 BB_B0 K2
34824 #define IGU_REG_MESSAGE_FIELDS                                                                       0x180808UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
34825     #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_VQID                                                     (0x1f<<0) // VQID for MSI and MSIX messages.
34826     #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_VQID_SHIFT                                               0
34827     #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_ATC                                                      (0x7<<5) // ATC for MSI and MSIX messages.
34828     #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_ATC_SHIFT                                                5
34829     #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_RO                                                       (0x1<<8) // RO for MSI and MSIX messages.
34830     #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_RO_SHIFT                                                 8
34831     #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_NS                                                       (0x1<<9) // NS for MSI and MSIX messages.
34832     #define IGU_REG_MESSAGE_FIELDS_MSI_MSIX_NS_SHIFT                                                 9
34833     #define IGU_REG_MESSAGE_FIELDS_MSIX_WRITE_DONE_TYPE                                              (0x1<<10) // Write done type for MSI and MSIX message.
34834     #define IGU_REG_MESSAGE_FIELDS_MSIX_WRITE_DONE_TYPE_SHIFT                                        10
34835     #define IGU_REG_MESSAGE_FIELDS_RESEVED                                                           (0xf<<11) // Reserved.
34836     #define IGU_REG_MESSAGE_FIELDS_RESEVED_SHIFT                                                     11
34837     #define IGU_REG_MESSAGE_FIELDS_ATTN_VQID                                                         (0x1f<<15) // VQID for attention messages.
34838     #define IGU_REG_MESSAGE_FIELDS_ATTN_VQID_SHIFT                                                   15
34839     #define IGU_REG_MESSAGE_FIELDS_ATTN_ATC                                                          (0x7<<20) // ATC for attention messages.
34840     #define IGU_REG_MESSAGE_FIELDS_ATTN_ATC_SHIFT                                                    20
34841     #define IGU_REG_MESSAGE_FIELDS_ATTN_RO                                                           (0x1<<23) // RO for attention messages.
34842     #define IGU_REG_MESSAGE_FIELDS_ATTN_RO_SHIFT                                                     23
34843     #define IGU_REG_MESSAGE_FIELDS_ATTN_NS                                                           (0x1<<24) // NS for attention messages.
34844     #define IGU_REG_MESSAGE_FIELDS_ATTN_NS_SHIFT                                                     24
34845     #define IGU_REG_MESSAGE_FIELDS_ATTN_WRITE_DONE_TYPE                                              (0x1<<25) // Write done type for attention message.
34846     #define IGU_REG_MESSAGE_FIELDS_ATTN_WRITE_DONE_TYPE_SHIFT                                        25
34847     #define IGU_REG_MESSAGE_FIELDS_ENDIANITY_MODE                                                    (0x3<<26) // Endianity mode in MSI/MSIX and attention message.
34848     #define IGU_REG_MESSAGE_FIELDS_ENDIANITY_MODE_SHIFT                                              26
34849 #define IGU_REG_PCI_PF_MSI_EN                                                                        0x18080cUL //Access:RW   DataWidth:0x1   PF MSI enable status. Shadow of PCI config register.  Chips: BB_A0 BB_B0
34850 #define IGU_REG_PCI_PF_MSIX_EN                                                                       0x180810UL //Access:RW   DataWidth:0x1   PF MSIX enable status. Shadow of PCI config register.  Chips: BB_A0 BB_B0
34851 #define IGU_REG_PCI_PF_MSIX_FUNC_MASK                                                                0x180814UL //Access:RW   DataWidth:0x1   PF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.  Chips: BB_A0 BB_B0
34852 #define IGU_REG_PCI_VF_MSIX_EN                                                                       0x180818UL //Access:RW   DataWidth:0x1   VF MSIX enable status. Shadow of PCI config register.  Chips: BB_A0 BB_B0
34853 #define IGU_REG_PCI_VF_MSIX_FUNC_MASK                                                                0x18081cUL //Access:RW   DataWidth:0x1   VF MSIX function mask status. Shadow of PCI config register. 0 - unmasked; 1 - masked.  Chips: BB_A0 BB_B0
34854 #define IGU_REG_ATTN_MSG_ADDR_L                                                                      0x180820UL //Access:RW   DataWidth:0x20  For attention message: Attention bit destination address 32 LSB. Two Lsbit must be zero.  Chips: BB_A0 BB_B0 K2
34855 #define IGU_REG_ATTN_MSG_ADDR_H                                                                      0x180824UL //Access:RW   DataWidth:0x20  For attention message: Attention bit destination address 32 MSB.  Chips: BB_A0 BB_B0 K2
34856 #define IGU_REG_ATTENTION_BIT_STATUS_INDEX                                                           0x180828UL //Access:RW   DataWidth:0x10  Value of attention bit status index (posted toward the driver as attention bit status index). This is the same value as in the attention message.  Chips: BB_A0 BB_B0 K2
34857 #define IGU_REG_LEADING_EDGE_LATCH                                                                   0x18082cUL //Access:RW   DataWidth:0x20  Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU.  Chips: BB_A0 BB_B0 K2
34858 #define IGU_REG_TRAILING_EDGE_LATCH                                                                  0x180830UL //Access:RW   DataWidth:0x20  Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU.  Chips: BB_A0 BB_B0 K2
34859 #define IGU_REG_ATTENTION_BITS                                                                       0x180834UL //Access:RW   DataWidth:0x20  32 bit register with the latched attention values. These are the same bits as in the attention message.  Chips: BB_A0 BB_B0 K2
34860 #define IGU_REG_ATTENTION_ACK_BITS                                                                   0x180838UL //Access:RW   DataWidth:0x20  32 bit register with the attention ACK values.These are the same bits as in the attention message.  Chips: BB_A0 BB_B0 K2
34861 #define IGU_REG_ATTENTION_ENABLE                                                                     0x18083cUL //Access:RW   DataWidth:0xc   Attention enable. Each PF attention vector is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. If the bit is set to 0, the corresponding bit in the attention vector is disabled.  Chips: BB_A0 BB_B0 K2
34862 #define IGU_REG_COMMAND_REG_32LSB_DATA                                                               0x180840UL //Access:RW   DataWidth:0x20  If the last command sent to the command_reg_ctrl was a read command, this register holds the 32LSB read value. If address is PBA: 32LSB of PBA register (one in each bit means PBA message wasnt sent due to mask). If address = SIMD with mask 64b/32LSB: 32 LSB of the during interrupt register (one in each bit means the appropriate SB is asserted. Every bit that is set will be masked in the mask bit register). If address = SIMD with mask 32MSB: this register will return zero. If address = SIMD without mask 64b: 32 LSB of the during interrupt register (one in each bit means the appropriate SB is asserted). If the command sent to the command_reg_ctrl is a write command the data in this register is used as follows:  If address = interrupt acknowledge register or producer update: same as Consumer & Producer update command.  If address = attention update: Attention ack new value = command_reg_32lsb_data. If address = attention set: Attention ack new value = attention ack old value | command_reg_32lsb_data. If address = attention clear: Attention ack new value = attention ack old value  & command_reg_32lsb_data.  Chips: BB_A0 BB_B0 K2
34863 #define IGU_REG_COMMAND_REG_32MSB_DATA                                                               0x180844UL //Access:RW   DataWidth:0x20  Read only register. If the last command sent to the command_reg_ctrl was a read command, this register holds the 32MSB read value. If address is PBA: 32 MSB of PBA register (one in each bit means PBA message wasnt sent due to mask).  If address = SIMD with mask 64b/32MSB: 32 MSB of the during interrupt register (one in each bit means the appropriate SB is asserted. Every bit that is set will be masked in the mask bit register). If address = SIMD with mask 32LSB: this register will return zero.  If address = SIMD without mask 64b: 32 MSB of the during interrupt register (one in each bit means the appropriate SB is asserted).  Chips: BB_A0 BB_B0 K2
34864 #define IGU_REG_COMMAND_REG_CTRL                                                                     0x180848UL //Access:W    DataWidth:0x20  [15:0] - function number: opaque fid. [27:16] - PXP BAR address; [30:28] - Reserved; [31] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: same as IGU BAR mapping. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0.  Chips: BB_A0 BB_B0 K2
34865 #define IGU_REG_STATISTIC_EN                                                                         0x18084cUL //Access:RW   DataWidth:0x1   Enable to collect data in the statistic_num_vf_msg_sent memory and statistic_num_pf_msg_sent memory.  Chips: BB_A0 BB_B0 K2
34866 #define IGU_REG_MSI_MEMORY                                                                           0x180850UL //Access:RW   DataWidth:0x20  Address 0 - MSI address low (two Lsbit are zero). Address 1 - MSI address high. Address 2 - [15:0] - MSI data; [18:16] MME; [31:19] Reserved.  Chips: BB_A0 BB_B0
34867 #define IGU_REG_MSI_MEMORY_SIZE                                                                      3
34868 #define IGU_REG_CAM_PARITY_SCRUBBING                                                                 0x180860UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34869     #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_HIT_EN                                            (0x1<<0) // IF = 1, hit scrubbing is enabled.                              When hit scrubbing is enabled, the match address of the hit response is used to perform a two-cycle                              read at the CAM hit location and (as usual) parity is checked during this read.
34870     #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_HIT_EN_SHIFT                                      0
34871     #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_MISS_EN                                           (0x1<<1) // IF = 1, miss scrubbing is enabled.                              When miss scrubbing is enabled, each time there is a search that results in a miss, a read of                               the entire CAM will be started (or re-started). This will end when the entire CAM has been read.                              Parity is checked during this read.
34872     #define IGU_REG_CAM_PARITY_SCRUBBING_CAM_SCRUB_MISS_EN_SHIFT                                     1
34873 #define IGU_REG_RATE_LIMITER_STATISTICS_EN                                                           0x180864UL //Access:RW   DataWidth:0x1   Enable the RL statistic. 0 - disabled; 1 - enabled.  Chips: BB_A0 BB_B0 K2
34874 #define IGU_REG_ECO_RESERVED                                                                         0x180868UL //Access:RW   DataWidth:0x8   Reserved for ECO if needed.  Chips: BB_A0 BB_B0 K2
34875 #define IGU_REG_PENDING_BITS_STATUS                                                                  0x180880UL //Access:R    DataWidth:0x20  Each bit represents the pending bits status for that SB. 0 = no pending; 1 = pending. Pendings means interrupt was asserted and write done was not received. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).  Chips: BB_A0 BB_B0 K2
34876 #define IGU_REG_PENDING_BITS_STATUS_SIZE                                                             12
34877 #define IGU_REG_WRITE_DONE_PENDING                                                                   0x180900UL //Access:R    DataWidth:0x20  Each bit represent write done pending bits status for that SB (MSI/MSIX message was sent and write done was not received yet). 0 = clear; 1 = set. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).  Chips: BB_A0 BB_B0 K2
34878 #define IGU_REG_WRITE_DONE_PENDING_SIZE                                                              12
34879 #define IGU_REG_CLEANUP_STATUS_0                                                                     0x180980UL //Access:R    DataWidth:0x20  Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in these registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).  Chips: BB_A0 BB_B0 K2
34880 #define IGU_REG_CLEANUP_STATUS_0_SIZE                                                                12
34881 #define IGU_REG_CLEANUP_STATUS_1                                                                     0x180a00UL //Access:R    DataWidth:0x20  Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).  Chips: BB_A0 BB_B0 K2
34882 #define IGU_REG_CLEANUP_STATUS_1_SIZE                                                                12
34883 #define IGU_REG_CLEANUP_STATUS_2                                                                     0x180a80UL //Access:R    DataWidth:0x20  Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).  Chips: BB_A0 BB_B0 K2
34884 #define IGU_REG_CLEANUP_STATUS_2_SIZE                                                                12
34885 #define IGU_REG_CLEANUP_STATUS_3                                                                     0x180b00UL //Access:R    DataWidth:0x20  Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).  Chips: BB_A0 BB_B0 K2
34886 #define IGU_REG_CLEANUP_STATUS_3_SIZE                                                                12
34887 #define IGU_REG_CLEANUP_STATUS_4                                                                     0x180b80UL //Access:R    DataWidth:0x20  Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).  Chips: BB_A0 BB_B0 K2
34888 #define IGU_REG_CLEANUP_STATUS_4_SIZE                                                                12
34889 #define IGU_REG_VF_WITH_MORE_16SB_0                                                                  0x180c00UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34890 #define IGU_REG_VF_WITH_MORE_16SB_1                                                                  0x180c04UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34891 #define IGU_REG_VF_WITH_MORE_16SB_2                                                                  0x180c08UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34892 #define IGU_REG_VF_WITH_MORE_16SB_3                                                                  0x180c0cUL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34893 #define IGU_REG_VF_WITH_MORE_16SB_4                                                                  0x180c10UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34894 #define IGU_REG_VF_WITH_MORE_16SB_5                                                                  0x180c14UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34895 #define IGU_REG_VF_WITH_MORE_16SB_6                                                                  0x180c18UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34896 #define IGU_REG_VF_WITH_MORE_16SB_7                                                                  0x180c1cUL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34897 #define IGU_REG_VF_WITH_MORE_16SB_8                                                                  0x180c20UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34898 #define IGU_REG_VF_WITH_MORE_16SB_9                                                                  0x180c24UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34899 #define IGU_REG_VF_WITH_MORE_16SB_10                                                                 0x180c28UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34900 #define IGU_REG_VF_WITH_MORE_16SB_11                                                                 0x180c2cUL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34901 #define IGU_REG_VF_WITH_MORE_16SB_12                                                                 0x180c30UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34902 #define IGU_REG_VF_WITH_MORE_16SB_13                                                                 0x180c34UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34903 #define IGU_REG_VF_WITH_MORE_16SB_14                                                                 0x180c38UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34904 #define IGU_REG_VF_WITH_MORE_16SB_15                                                                 0x180c3cUL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: BB_A0 BB_B0 K2
34905 #define IGU_REG_VF_WITH_MORE_16SB_16                                                                 0x180c40UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: K2
34906 #define IGU_REG_VF_WITH_MORE_16SB_17                                                                 0x180c44UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: K2
34907 #define IGU_REG_VF_WITH_MORE_16SB_18                                                                 0x180c48UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: K2
34908 #define IGU_REG_VF_WITH_MORE_16SB_19                                                                 0x180c4cUL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: K2
34909 #define IGU_REG_VF_WITH_MORE_16SB_20                                                                 0x180c50UL //Access:RW   DataWidth:0x9   The VF function numbers that has more than 16 SBs. [7:0] - VF number, [8] - valid bit.  Chips: K2
34910 #define IGU_REG_MSIX_CLEANUP_CMD                                                                     0x180c80UL //Access:W    DataWidth:0x9   Writing the absolute SB index to the register will clear the appropriate vector in the MSIX table (write zero to all fields except the mask bit that is set).  Chips: BB_A0 BB_B0 K2
34911 #define IGU_REG_INT_BEFORE_MASK_STS_PF                                                               0x180ca0UL //Access:RW   DataWidth:0x20  SB interrupt before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits order is according to the vector number of each SB in that function. Only 129b available.  Chips: BB_A0 BB_B0 K2
34912 #define IGU_REG_INT_BEFORE_MASK_STS_PF_SIZE                                                          5
34913 #define IGU_REG_INT_BEFORE_MASK_STS_VF_LSB                                                           0x180cc0UL //Access:RW   DataWidth:0x20  SB interrupt before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits order is according to the vector number of each SB in that function. Bits 31:16 are available for function that are configured in vf_with_more_16sb only.  Chips: BB_A0 BB_B0 K2
34914 #define IGU_REG_INT_BEFORE_MASK_STS_VF_MSB                                                           0x180cc4UL //Access:RW   DataWidth:0x20  SB interrupt before mask. 0 - prod equal cons. 1 - prod not equal cons or last command for this SB was prod update. The bits order is according to the vector number of each SB in that function. Availble for function that are configured in vf_with_more_16sb only.  Chips: BB_A0 BB_B0 K2
34915 #define IGU_REG_INT_MASK_STS_PF                                                                      0x180ce0UL //Access:RW   DataWidth:0x20  SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is according to the vector number of each SB in that function. Only 129b availble.  Chips: BB_A0 BB_B0 K2
34916 #define IGU_REG_INT_MASK_STS_PF_SIZE                                                                 5
34917 #define IGU_REG_INT_MASK_STS_VF_LSB                                                                  0x180d00UL //Access:RW   DataWidth:0x20  SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is according to the vector number of each SB in that function. Bits 31:16 are available for function that are configured in vf_with_more_16sb only.  Chips: BB_A0 BB_B0 K2
34918 #define IGU_REG_INT_MASK_STS_VF_MSB                                                                  0x180d04UL //Access:RW   DataWidth:0x20  SB interrupt mask. 0 - unmasked. 1 - masked. The bits order is according to the vector number of each SB in that function. Availble for function that are configured in vf_with_more_16sb only.  Chips: BB_A0 BB_B0 K2
34919 #define IGU_REG_PBA_STS_PF                                                                           0x180d20UL //Access:RW   DataWidth:0x20  PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or vector). The bits order is according to the vector number of each SB in that function. Only 129b availble.  Chips: BB_A0 BB_B0 K2
34920 #define IGU_REG_PBA_STS_PF_SIZE                                                                      5
34921 #define IGU_REG_PBA_STS_VF_LSB                                                                       0x180d40UL //Access:RW   DataWidth:0x20  PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or vector). The bits order is according to the vector number of each SB in that function. Bits 31:16 are available for function that are configured in vf_with_more_16sb only.  Chips: BB_A0 BB_B0 K2
34922 #define IGU_REG_PBA_STS_VF_MSB                                                                       0x180d44UL //Access:RW   DataWidth:0x20  PBA register. 0 - PBA clear, 1 - PBA set - the appropriate MSIX message was not set due to mask bit (function or vector). The bits order is according to the vector number of each SB in that function. Availble for function that are configured in vf_with_more_16sb only.  Chips: BB_A0 BB_B0 K2
34923 #define IGU_REG_GROUP_RL_VARIABLE0                                                                   0x180e00UL //Access:RW   DataWidth:0x18  [9:0] upper_bound - sets the max value that the rate_counter can reach; [19:10] tick_interval - define the max interrupt rate for the group; [23:20] timer mask value - define the negative value that the tick_value receives when receiving a timer mask command. 0 = 0; 1 = 1; 2 = 2; 3 = 4; 4 = 8; 5 = 16; 6 = 24; 7 = 32; 8 = 48; 9 = 64; 10 = 96; 11 = 128; 12 = 256; 13 = 512; 14 = 750; 15 = 1000.  Chips: BB_A0 BB_B0 K2
34924 #define IGU_REG_GROUP_RL_VARIABLE0_SIZE                                                              64
34925 #define IGU_REG_GROUP_RL_VARIABLE1                                                                   0x181000UL //Access:RW   DataWidth:0x15  [0:9] tick_value - receives the tick_interval value when reaching zero; or when writing to the tick_interval. The tick value is decreased every tick. [20:10] rate_counter - incremented by a one when tick_value reaches zero and decremented whenever a message from that group was sent or when a timer mask command arrived. When rate counter is zero/negative - no messages will be sent on that group. When the positive value reaches upper_bound it will not continue incrementing. Negative value is represented by 2s complement value.  Chips: BB_A0 BB_B0 K2
34926 #define IGU_REG_GROUP_RL_VARIABLE1_SIZE                                                              64
34927 #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0                                                            0x181200UL //Access:RW   DataWidth:0x18  Multi Field Register.  Chips: BB_A0 BB_B0 K2
34928     #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_UPPER_BOUND                                (0x3ff<<0) // Upper bound value of the global rate limiter. Sets the max value that the rate_counter can reach.
34929     #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_UPPER_BOUND_SHIFT                          0
34930     #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_TICK_INTERVAL                              (0x3ff<<10) // Tick interval of the global rate limiter. Define the max interrupt rate for the group.
34931     #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_TICK_INTERVAL_SHIFT                        10
34932     #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_INC_VALUE                                  (0xf<<20) // The value that the global rate will be increased on every interval. Zero is not a valid value.
34933     #define IGU_REG_GLOBAL_RATE_LIMITER_VARI0_GLOBAL_RATE_INC_VALUE_SHIFT                            20
34934 #define IGU_REG_GLOBAL_RATE_TICK_VALUE                                                               0x181204UL //Access:R    DataWidth:0xa   This field receives the tick_interval value when reaching zero. The tick value is decreased by one on every tick.  Chips: BB_A0 BB_B0 K2
34935 #define IGU_REG_GLOBAL_RATE_TICK_RATE_COUNTER                                                        0x181208UL //Access:RW   DataWidth:0xb   Rate counter - incremented by one when Tick_value reaches zero and decremented whenever a message from that group was sent. When rate counter is zero/negative - no messages will be sent on that group. Negative value is represented by 2s complement value. When the positive value reaches Upper_bound it will not continue incrementing.  Chips: BB_A0 BB_B0 K2
34936 #define IGU_REG_VF_FUNCTIONAL_CLEANUP                                                                0x18120cUL //Access:W    DataWidth:0x1   Writing 1 to this register will clear the VF statistics.  Chips: BB_A0 BB_B0 K2
34937 #define IGU_REG_PF_FUNCTIONAL_CLEANUP                                                                0x181210UL //Access:W    DataWidth:0x1   Writing 1 to this register will clear the PF statistics and clean also attn bit, attn ack and attn index registers.  Chips: BB_A0 BB_B0 K2
34938 #define IGU_REG_CLK25_COUNTER_SENSITIVITY                                                            0x181214UL //Access:RW   DataWidth:0x10  Number of clock 25 cycles that generate a tick in the IPS mechanism. The number of cycles multiply by clock 25 cycle time should give 1 usec.  Chips: BB_A0 BB_B0 K2
34939 #define IGU_REG_ATTN_TPH                                                                             0x181218UL //Access:RW   DataWidth:0x10  Tph field for attention message. Bits 8:0 - steering tag; bits 12:9 - reserved; bits 14:13 - st hint; bit 15 - tph valid.  Chips: BB_A0 BB_B0 K2
34940 #define IGU_REG_GROUP_RL_EN_0                                                                        0x18121cUL //Access:R    DataWidth:0x20  Rate Limiter group enable status bit for groups 0-31. For each bit: 0 - the rate limiter of the group is disabled. 1 - the rate limiter of the group is enabled.  Chips: BB_A0 BB_B0 K2
34941 #define IGU_REG_GROUP_RL_EN_1                                                                        0x181220UL //Access:R    DataWidth:0x20  Rate Limiter group enable status bit for groups 32-63. For each bit: 0 - the rate limiter of the group is disabled. 1 - the rate limiter of the group is enabled.  Chips: BB_A0 BB_B0 K2
34942 #define IGU_REG_GROUP_RL_CREDIT_0                                                                    0x181224UL //Access:R    DataWidth:0x20  Rate Limiter group credit status bit for groups 0-31. For each bit: 0 - the group has no credit. 1 - the group has credit.  Chips: BB_A0 BB_B0 K2
34943 #define IGU_REG_GROUP_RL_CREDIT_1                                                                    0x181228UL //Access:R    DataWidth:0x20  Rate Limiter group credit status bit for groups 32-63. For each bit: 0 - the group has no credit. 1 - the group has credit.  Chips: BB_A0 BB_B0 K2
34944 #define IGU_REG_GROUP_RL_PENDING_0                                                                   0x18122cUL //Access:R    DataWidth:0x20  Rate Limiter group pending status bit for groups 0-31. For each bit: 0 - there are no pending SB in that group. 1 - there are pending SB in that group.  Chips: BB_A0 BB_B0 K2
34945 #define IGU_REG_GROUP_RL_PENDING_1                                                                   0x181230UL //Access:R    DataWidth:0x20  Rate Limiter group pending status bit for groups 32-63. For each bit: 0 - there are no pending SB in that group. 1 - there are pending SB in that group.  Chips: BB_A0 BB_B0 K2
34946 #define IGU_REG_ATTENTION_SIGNAL_P0_STATUS                                                           0x181500UL //Access:R    DataWidth:0xc   Debug: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port0.  Chips: BB_A0 BB_B0 K2
34947 #define IGU_REG_ATTENTION_SIGNAL_P1_STATUS                                                           0x181504UL //Access:R    DataWidth:0xc   Debug: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port1.  Chips: BB_A0 BB_B0 K2
34948 #define IGU_REG_ATTENTION_SIGNAL_P2_STATUS                                                           0x181508UL //Access:R    DataWidth:0xc   Debug: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port2.  Chips: BB_A0 BB_B0 K2
34949 #define IGU_REG_ATTENTION_SIGNAL_P3_STATUS                                                           0x18150cUL //Access:R    DataWidth:0xc   Debug: attention signal status. Reflects the current value of the attention signals from the MISC-AEU port3.  Chips: BB_A0 BB_B0 K2
34950 #define IGU_REG_ATTN_MSG_PENDING                                                                     0x181510UL //Access:R    DataWidth:0x10  Debug: messages that wait to be sent; but were not sent yet. One bit for each PFID.  Chips: BB_A0 BB_B0 K2
34951 #define IGU_REG_ATTN_WRITE_DONE_PENDING                                                              0x181514UL //Access:R    DataWidth:0x5   Debug: [4] - attention write done message is pending (0-no pending; 1-pending). [3:0] = the PFID for the pending attention message. Pending means attention message was sent; but write done was not received.  Chips: BB_A0 BB_B0 K2
34952 #define IGU_REG_COMMAND_DEBUG                                                                        0x181518UL //Access:RW   DataWidth:0x1   Debug only: 0 - FIFO collects 64 first error messages; 1 - FIFO collects 64 last incoming command.  Chips: BB_A0 BB_B0 K2
34953 #define IGU_REG_INTERRUPT_STATUS                                                                     0x18151cUL //Access:R    DataWidth:0x10  Debug: Interrupt status (active high). BB: PF0 to PF7.  Chips: BB_A0 BB_B0 K2
34954 #define IGU_REG_ERROR_HANDLING_MEMORY                                                                0x181520UL //Access:WB_R DataWidth:0x41  Do not read from this memory if error_handling_data_valid register is zero. The data is collected in according to the command_debug value. If command_debug is clear it holds the first 64 error commands (commands that were dropped), else it stores the last 64 commands according to debug_record_mask registers: If the mask _*_en is clear it will collect all the data regardless of the mask_* value. if it is set it will collect the data that match to the value in the mask_* register. Masking can be done according to: debug_record_mask_source_idx, debug_record_mask_min_sb_idx, debug_record_mask_max_sb_idx, debug_record_mask_fid_num, debug_record_mask_fid_exclude, debug_record_mask_cmd_type_idx. The read data encoding is as follows: [8:0] - fid ([8] - if set - PF; else VF, [7:0] - FID). [12:9] - source (values 0-7 according to PXP sources, 8 - CAU, 9 - ATTN, 10 - GRC command register). [16:13] - error type (value: 0 - no error, 1 - length error, 2 - function disabled, 3 - VF sent command to attnetion address, 4 - host sent prod update command, 5 - read of during interrupt register while in MIMD mode, 6 - access to PXP BAR reserved address, 7 - producer update command to attention index, 9 - SB index not valid, 10 - SB relative index and FID not found, 11 - FID not match, 12 - command with error flag aserted (PCI error or CAU discard) 13 - VF sent cleanup and RF cleanup is disabled, 14 - cleanup command on type bigger than 4). [31:17] - Command address (15 LSBits). [32:32] - Command write or read. 0 - read, 1 - write. [64:33] - 32 LSB Wr data. In case of CAU command the mapping is: [56:33] - CAU command [23:0], [63:57] - reserved, [64] - CAU command [42] (CMD Type). In case of ATTENTION PRODUCER UPDATE command the mapping is: [56:33] - producer value, [64:57] - reserved.  Chips: BB_A0 BB_B0 K2
34955 #define IGU_REG_ERROR_HANDLING_MEMORY_SIZE                                                           4
34956 #define IGU_REG_ERROR_HANDLING_DATA_VALID                                                            0x181530UL //Access:R    DataWidth:0x1   Data available for error memory. If this bit is clear do not read from error_handling_memory.  Chips: BB_A0 BB_B0 K2
34957 #define IGU_REG_SILENT_DROP                                                                          0x181534UL //Access:RW   DataWidth:0x10  Number of command that were dropped.  Chips: BB_A0 BB_B0 K2
34958 #define IGU_REG_MAPPING_FSM                                                                          0x181538UL //Access:R    DataWidth:0x4   Debug: mapping_fsm.  Chips: BB_A0 BB_B0 K2
34959 #define IGU_REG_SB_CTRL_FSM                                                                          0x18153cUL //Access:R    DataWidth:0x4   Debug: sb_ctrl_fsm.  Chips: BB_A0 BB_B0 K2
34960 #define IGU_REG_INT_HANDLE_FSM                                                                       0x181540UL //Access:R    DataWidth:0x4   Debug: int_handle_fsm.  Chips: BB_A0 BB_B0 K2
34961 #define IGU_REG_ATTN_FSM                                                                             0x181544UL //Access:R    DataWidth:0x4   Debug: attn_fsm.  Chips: BB_A0 BB_B0 K2
34962 #define IGU_REG_PBA_FSM                                                                              0x181548UL //Access:R    DataWidth:0x4   Debug: pba_fsm.  Chips: BB_A0 BB_B0 K2
34963 #define IGU_REG_MSIX_MSG_BUILDER_FSM                                                                 0x18154cUL //Access:R    DataWidth:0x5   Debug: msix_msg_builder_fsm.  Chips: BB_A0 BB_B0 K2
34964 #define IGU_REG_MSIX_MEM_FSM                                                                         0x181550UL //Access:R    DataWidth:0x3   Debug: msix_mem_fsm.  Chips: BB_A0 BB_B0 K2
34965 #define IGU_REG_CTRL_FSM                                                                             0x181554UL //Access:R    DataWidth:0x5   Debug: ctrl_fsm.  Chips: BB_A0 BB_B0 K2
34966 #define IGU_REG_PXP_ARB_FSM                                                                          0x181558UL //Access:R    DataWidth:0x3   Debug: pxp_arb_fsm.  Chips: BB_A0 BB_B0 K2
34967 #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB                                                             0x18155cUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34968     #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_IDX                                                     (0x1ff<<0) // Debug: minimun SB index for the debug.
34969     #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_IDX_SHIFT                                               0
34970     #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_EN                                                      (0x1<<9) // Debug: if set the debug information is collected for SB index equal or above debug_record_mask_min_sb_idx. Applicable for PROD/CONS UPD, CLEANUP, and MSIX RD/WR commands. This field is ignored for error cases and for all other commands.
34971     #define IGU_REG_DEBUG_RECORD_MASK_MIN_SB_EN_SHIFT                                                9
34972 #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB                                                             0x181560UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34973     #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_IDX                                                     (0x1ff<<0) // Debug: maximum SB index for the debug.
34974     #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_IDX_SHIFT                                               0
34975     #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_EN                                                      (0x1<<9) // Debug: if set the debug information is collected for SB index equal or below debug_record_mask_max_sb_idx. Applicable for PROD/CONS UPD, CLEANUP, and MSIX RD/WR commands. This field is ignored for error cases and for all other commands.
34976     #define IGU_REG_DEBUG_RECORD_MASK_MAX_SB_EN_SHIFT                                                9
34977 #define IGU_REG_DEBUG_RECORD_MASK_FID                                                                0x181564UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34978     #define IGU_REG_DEBUG_RECORD_MASK_FID_NUM                                                        (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 0; [7:0] = VF number; if PF - [8] = 1; [7:4] = 0; [3:0] = PF number.
34979     #define IGU_REG_DEBUG_RECORD_MASK_FID_NUM_SHIFT                                                  0
34980     #define IGU_REG_DEBUG_RECORD_MASK_FID_EN                                                         (0x1<<9) // Debug: if set the debug information is collected for FID specified in debug_record_mask_fid_num according to debug_record_mask_fid_exclude field.
34981     #define IGU_REG_DEBUG_RECORD_MASK_FID_EN_SHIFT                                                   9
34982     #define IGU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE                                                    (0x1<<10) // Debug: if clear the debug information is collected for FID equal to debug_record_mask_fid_num. if set the debug information is collected for FID not equal to debug_record_mask_fid_num.
34983     #define IGU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE_SHIFT                                              10
34984 #define IGU_REG_DEBUG_RECORD_MASK_SOURCE                                                             0x181568UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34985     #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_IDX                                                     (0xf<<0) // Debug: source index for the debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM) 8 = CAU; 9 = internal (attention producer update); 10 = GRC.
34986     #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_IDX_SHIFT                                               0
34987     #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_EN                                                      (0x1<<4) // Debug: if set the debug information is collected for source equal to debug_record_mask_source_idx.
34988     #define IGU_REG_DEBUG_RECORD_MASK_SOURCE_EN_SHIFT                                                4
34989 #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE                                                           0x18156cUL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
34990     #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_IDX                                                   (0x3f<<0) // Debug: command type for the debug. Selects the command types to be collected. The fields: Bit [0] - MSIX read/write; Bit [1] - PBA read/write; Bit [2] - Producer update (or cleanup command through producer address space) read/write; Bit [3] - Interrupt acknowledgment - Consumer update (or cleanup command through consumer address space) read/write; Bit [4] - Attn command read/write; Bit [5] - Read during interrupt register read/write.
34991     #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_IDX_SHIFT                                             0
34992     #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN                                                    (0x1<<6) // Debug: if set the debug information is collected for the marked commands only according to debug_record_mask_cmd_type_idx.
34993     #define IGU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN_SHIFT                                              6
34994 #define IGU_REG_MISC_PORT_MODE                                                                       0x181570UL //Access:R    DataWidth:0x2   The misc port mode signal value. 0 = SPPE; 1 = DPPE; 2 = QPPE; 3 = reserved.  Chips: BB_A0 BB_B0 K2
34995 #define IGU_REG_CAU_DISCARD_STATUS                                                                   0x181574UL //Access:R    DataWidth:0x1   The discard signal status from the CAU.  Chips: BB_A0 BB_B0 K2
34996 #define IGU_REG_DBG_SELECT                                                                           0x181578UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
34997 #define IGU_REG_DBG_DWORD_ENABLE                                                                     0x18157cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
34998 #define IGU_REG_DBG_SHIFT                                                                            0x181580UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
34999 #define IGU_REG_DBG_FORCE_VALID                                                                      0x181584UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
35000 #define IGU_REG_DBG_FORCE_FRAME                                                                      0x181588UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
35001 #define IGU_REG_DBG_OUT_DATA                                                                         0x1815a0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
35002 #define IGU_REG_DBG_OUT_DATA_SIZE                                                                    8
35003 #define IGU_REG_DBG_OUT_VALID                                                                        0x1815c0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
35004 #define IGU_REG_DBG_OUT_FRAME                                                                        0x1815c4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
35005 #define IGU_REG_PRODUCER_MEMORY                                                                      0x182000UL //Access:RW   DataWidth:0x18  Producers only. address 0-287 match to the mapping memory; 288-296 - PF 0-7 attention producer.  Chips: BB_A0 BB_B0 K2
35006 #define IGU_REG_PRODUCER_MEMORY_SIZE                                                                 384
35007 #define IGU_REG_CONSUMER_MEM                                                                         0x183000UL //Access:RW   DataWidth:0x18  Consumers only. address 0-287 match to the mapping memory; 288-296 - PF0-7 attention consumer.  Chips: BB_A0 BB_B0 K2
35008 #define IGU_REG_CONSUMER_MEM_SIZE                                                                    384
35009 #define IGU_REG_MAPPING_MEMORY                                                                       0x184000UL //Access:RW   DataWidth:0x18  Mapping CAM. Fields: [0] - valid. [8:1] - vector number (0-128 for PF; 0-63 for VF). [17:9] - FID (if VF: [17] = 0; [16:9] = VF number (0-191); if PF: [17] = 1; [16:9] = PF number (0-15)).                           [23:18] - IPS group ID (0-63). Reset values (the CAM receives these values by writing one to bit zero in the reset_memories register: address 0-16 - PF 0 vectors 0-16; address 17-33 - PF 1 vectors 0-16; address 34-50 - PF 2 vectors 0-16; .. address 119-135 - PF 7 vectors 0-16; address 136 - VF 0 vector 0; address 137 - VF 1 vector 0; address 138 - VF 2 vector 0; .. address 255 - VF 119 vector 0; all other addresses are reserved. all the SB are associated to group 0 in the IRL mechanism.  Chips: BB_A0 BB_B0 K2
35010 #define IGU_REG_MAPPING_MEMORY_SIZE                                                                  368
35011 #define IGU_REG_MSIX_MEMORY                                                                          0x186000UL //Access:WB   DataWidth:0x61  [63:0] - MSIX message address (bit [1:0] are always zero); [95:64] - MSIX message data; [96] - MSIX mask bit (0 - unmasked; 1 - masked).Reset value (after reset_memories was set) is MSIX address = 0; MSIX data = 0; MSIX mask bit=1.  Chips: BB_A0 BB_B0 K2
35012 #define IGU_REG_MSIX_MEMORY_SIZE                                                                     1472
35013 #define CAU_REG_INT_STS                                                                              0x1c00d4UL //Access:R    DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35014     #define CAU_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
35015     #define CAU_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
35016     #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_RD_CMD                                                  (0x1<<1) // PXP read request arrived.
35017     #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_RD_CMD_SHIFT                                            1
35018     #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_LENGTH_CMD                                              (0x1<<2) // PXP write request without CQA and with length >1 arrived.
35019     #define CAU_REG_INT_STS_UNAUTHORIZED_PXP_LENGTH_CMD_SHIFT                                        2
35020     #define CAU_REG_INT_STS_PXP_SB_ADDRESS_ERROR                                                     (0x1<<3) // SB index > CAU_NUM_SB or  SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
35021     #define CAU_REG_INT_STS_PXP_SB_ADDRESS_ERROR_SHIFT                                               3
35022     #define CAU_REG_INT_STS_PXP_PI_NUMBER_ERROR                                                      (0x1<<4) // PI relative number > num_pi_per_sb.
35023     #define CAU_REG_INT_STS_PXP_PI_NUMBER_ERROR_SHIFT                                                4
35024     #define CAU_REG_INT_STS_CLEANUP_REG_SB_IDX_ERROR                                                 (0x1<<5) // SB index > CAU_SB_NUM or  SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
35025     #define CAU_REG_INT_STS_CLEANUP_REG_SB_IDX_ERROR_SHIFT                                           5
35026     #define CAU_REG_INT_STS_FSM_INVALID_LINE                                                         (0x1<<6) // The FSM arrived to an invalid line.
35027     #define CAU_REG_INT_STS_FSM_INVALID_LINE_SHIFT                                                   6
35028     #define CAU_REG_INT_STS_CQE_FIFO_ERR                                                             (0x1<<7) // Write to full  FIFO or read from empty  FIFO.
35029     #define CAU_REG_INT_STS_CQE_FIFO_ERR_SHIFT                                                       7
35030     #define CAU_REG_INT_STS_IGU_WDATA_FIFO_ERR                                                       (0x1<<8) // Write to full  FIFO or read from empty  FIFO.
35031     #define CAU_REG_INT_STS_IGU_WDATA_FIFO_ERR_SHIFT                                                 8
35032     #define CAU_REG_INT_STS_IGU_REQ_FIFO_ERR                                                         (0x1<<9) // Write to full  FIFO or read from empty  FIFO.
35033     #define CAU_REG_INT_STS_IGU_REQ_FIFO_ERR_SHIFT                                                   9
35034     #define CAU_REG_INT_STS_IGU_CMD_FIFO_ERR                                                         (0x1<<10) // Write to full  FIFO or read from empty  FIFO.
35035     #define CAU_REG_INT_STS_IGU_CMD_FIFO_ERR_SHIFT                                                   10
35036 #define CAU_REG_INT_STS_CLR                                                                          0x1c00d8UL //Access:RC   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35037     #define CAU_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
35038     #define CAU_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
35039     #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_RD_CMD                                              (0x1<<1) // PXP read request arrived.
35040     #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_RD_CMD_SHIFT                                        1
35041     #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_LENGTH_CMD                                          (0x1<<2) // PXP write request without CQA and with length >1 arrived.
35042     #define CAU_REG_INT_STS_CLR_UNAUTHORIZED_PXP_LENGTH_CMD_SHIFT                                    2
35043     #define CAU_REG_INT_STS_CLR_PXP_SB_ADDRESS_ERROR                                                 (0x1<<3) // SB index > CAU_NUM_SB or  SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
35044     #define CAU_REG_INT_STS_CLR_PXP_SB_ADDRESS_ERROR_SHIFT                                           3
35045     #define CAU_REG_INT_STS_CLR_PXP_PI_NUMBER_ERROR                                                  (0x1<<4) // PI relative number > num_pi_per_sb.
35046     #define CAU_REG_INT_STS_CLR_PXP_PI_NUMBER_ERROR_SHIFT                                            4
35047     #define CAU_REG_INT_STS_CLR_CLEANUP_REG_SB_IDX_ERROR                                             (0x1<<5) // SB index > CAU_SB_NUM or  SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
35048     #define CAU_REG_INT_STS_CLR_CLEANUP_REG_SB_IDX_ERROR_SHIFT                                       5
35049     #define CAU_REG_INT_STS_CLR_FSM_INVALID_LINE                                                     (0x1<<6) // The FSM arrived to an invalid line.
35050     #define CAU_REG_INT_STS_CLR_FSM_INVALID_LINE_SHIFT                                               6
35051     #define CAU_REG_INT_STS_CLR_CQE_FIFO_ERR                                                         (0x1<<7) // Write to full  FIFO or read from empty  FIFO.
35052     #define CAU_REG_INT_STS_CLR_CQE_FIFO_ERR_SHIFT                                                   7
35053     #define CAU_REG_INT_STS_CLR_IGU_WDATA_FIFO_ERR                                                   (0x1<<8) // Write to full  FIFO or read from empty  FIFO.
35054     #define CAU_REG_INT_STS_CLR_IGU_WDATA_FIFO_ERR_SHIFT                                             8
35055     #define CAU_REG_INT_STS_CLR_IGU_REQ_FIFO_ERR                                                     (0x1<<9) // Write to full  FIFO or read from empty  FIFO.
35056     #define CAU_REG_INT_STS_CLR_IGU_REQ_FIFO_ERR_SHIFT                                               9
35057     #define CAU_REG_INT_STS_CLR_IGU_CMD_FIFO_ERR                                                     (0x1<<10) // Write to full  FIFO or read from empty  FIFO.
35058     #define CAU_REG_INT_STS_CLR_IGU_CMD_FIFO_ERR_SHIFT                                               10
35059 #define CAU_REG_INT_STS_WR                                                                           0x1c00dcUL //Access:WR   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35060     #define CAU_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
35061     #define CAU_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
35062     #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_RD_CMD                                               (0x1<<1) // PXP read request arrived.
35063     #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_RD_CMD_SHIFT                                         1
35064     #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_LENGTH_CMD                                           (0x1<<2) // PXP write request without CQA and with length >1 arrived.
35065     #define CAU_REG_INT_STS_WR_UNAUTHORIZED_PXP_LENGTH_CMD_SHIFT                                     2
35066     #define CAU_REG_INT_STS_WR_PXP_SB_ADDRESS_ERROR                                                  (0x1<<3) // SB index > CAU_NUM_SB or  SB index > CAU_NUM_PI/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
35067     #define CAU_REG_INT_STS_WR_PXP_SB_ADDRESS_ERROR_SHIFT                                            3
35068     #define CAU_REG_INT_STS_WR_PXP_PI_NUMBER_ERROR                                                   (0x1<<4) // PI relative number > num_pi_per_sb.
35069     #define CAU_REG_INT_STS_WR_PXP_PI_NUMBER_ERROR_SHIFT                                             4
35070     #define CAU_REG_INT_STS_WR_CLEANUP_REG_SB_IDX_ERROR                                              (0x1<<5) // SB index > CAU_SB_NUM or  SB index > CAU_PI_NUM/num_pi_per_sb. CAU_SB_NUM is 288 in BB and 368 in K2. CAU_PI_NUM is 3456 in BB and 4416 in K2
35071     #define CAU_REG_INT_STS_WR_CLEANUP_REG_SB_IDX_ERROR_SHIFT                                        5
35072     #define CAU_REG_INT_STS_WR_FSM_INVALID_LINE                                                      (0x1<<6) // The FSM arrived to an invalid line.
35073     #define CAU_REG_INT_STS_WR_FSM_INVALID_LINE_SHIFT                                                6
35074     #define CAU_REG_INT_STS_WR_CQE_FIFO_ERR                                                          (0x1<<7) // Write to full  FIFO or read from empty  FIFO.
35075     #define CAU_REG_INT_STS_WR_CQE_FIFO_ERR_SHIFT                                                    7
35076     #define CAU_REG_INT_STS_WR_IGU_WDATA_FIFO_ERR                                                    (0x1<<8) // Write to full  FIFO or read from empty  FIFO.
35077     #define CAU_REG_INT_STS_WR_IGU_WDATA_FIFO_ERR_SHIFT                                              8
35078     #define CAU_REG_INT_STS_WR_IGU_REQ_FIFO_ERR                                                      (0x1<<9) // Write to full  FIFO or read from empty  FIFO.
35079     #define CAU_REG_INT_STS_WR_IGU_REQ_FIFO_ERR_SHIFT                                                9
35080     #define CAU_REG_INT_STS_WR_IGU_CMD_FIFO_ERR                                                      (0x1<<10) // Write to full  FIFO or read from empty  FIFO.
35081     #define CAU_REG_INT_STS_WR_IGU_CMD_FIFO_ERR_SHIFT                                                10
35082 #define CAU_REG_INT_MASK                                                                             0x1c00e0UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35083     #define CAU_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.ADDRESS_ERROR .
35084     #define CAU_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
35085     #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_RD_CMD                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.UNAUTHORIZED_PXP_RD_CMD .
35086     #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_RD_CMD_SHIFT                                           1
35087     #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_LENGTH_CMD                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.UNAUTHORIZED_PXP_LENGTH_CMD .
35088     #define CAU_REG_INT_MASK_UNAUTHORIZED_PXP_LENGTH_CMD_SHIFT                                       2
35089     #define CAU_REG_INT_MASK_PXP_SB_ADDRESS_ERROR                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.PXP_SB_ADDRESS_ERROR .
35090     #define CAU_REG_INT_MASK_PXP_SB_ADDRESS_ERROR_SHIFT                                              3
35091     #define CAU_REG_INT_MASK_PXP_PI_NUMBER_ERROR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.PXP_PI_NUMBER_ERROR .
35092     #define CAU_REG_INT_MASK_PXP_PI_NUMBER_ERROR_SHIFT                                               4
35093     #define CAU_REG_INT_MASK_CLEANUP_REG_SB_IDX_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.CLEANUP_REG_SB_IDX_ERROR .
35094     #define CAU_REG_INT_MASK_CLEANUP_REG_SB_IDX_ERROR_SHIFT                                          5
35095     #define CAU_REG_INT_MASK_FSM_INVALID_LINE                                                        (0x1<<6) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.FSM_INVALID_LINE .
35096     #define CAU_REG_INT_MASK_FSM_INVALID_LINE_SHIFT                                                  6
35097     #define CAU_REG_INT_MASK_CQE_FIFO_ERR                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.CQE_FIFO_ERR .
35098     #define CAU_REG_INT_MASK_CQE_FIFO_ERR_SHIFT                                                      7
35099     #define CAU_REG_INT_MASK_IGU_WDATA_FIFO_ERR                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_WDATA_FIFO_ERR .
35100     #define CAU_REG_INT_MASK_IGU_WDATA_FIFO_ERR_SHIFT                                                8
35101     #define CAU_REG_INT_MASK_IGU_REQ_FIFO_ERR                                                        (0x1<<9) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_REQ_FIFO_ERR .
35102     #define CAU_REG_INT_MASK_IGU_REQ_FIFO_ERR_SHIFT                                                  9
35103     #define CAU_REG_INT_MASK_IGU_CMD_FIFO_ERR                                                        (0x1<<10) // This bit masks, when set, the Interrupt bit: CAU_REG_INT_STS.IGU_CMD_FIFO_ERR .
35104     #define CAU_REG_INT_MASK_IGU_CMD_FIFO_ERR_SHIFT                                                  10
35105 #define CAU_REG_PRTY_MASK_H_0                                                                        0x1c0204UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35106     #define CAU_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
35107     #define CAU_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_SHIFT                                          0
35108     #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_0_RF_INT                                              (0x1<<1) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM001_I_ECC_0_RF_INT .
35109     #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_0_RF_INT_SHIFT                                        1
35110     #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_1_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM001_I_ECC_1_RF_INT .
35111     #define CAU_REG_PRTY_MASK_H_0_MEM001_I_ECC_1_RF_INT_SHIFT                                        2
35112     #define CAU_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
35113     #define CAU_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT                                          3
35114     #define CAU_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                                (0x1<<4) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
35115     #define CAU_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                          4
35116     #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
35117     #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0_SHIFT                                      3
35118     #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
35119     #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0_SHIFT                                      3
35120     #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
35121     #define CAU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                         5
35122     #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
35123     #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0_SHIFT                                      4
35124     #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
35125     #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0_SHIFT                                      4
35126     #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
35127     #define CAU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                         6
35128     #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                            (0x1<<5) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
35129     #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                      5
35130     #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0                                            (0x1<<5) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
35131     #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                      5
35132     #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
35133     #define CAU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                         7
35134     #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0                                            (0x1<<6) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
35135     #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0_SHIFT                                      6
35136     #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0                                            (0x1<<6) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
35137     #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0_SHIFT                                      6
35138     #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                               (0x1<<8) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
35139     #define CAU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                         8
35140     #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0                                            (0x1<<7) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
35141     #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0_SHIFT                                      7
35142     #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
35143     #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0_SHIFT                                      7
35144     #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
35145     #define CAU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT                                         9
35146     #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
35147     #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                      8
35148     #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                            (0x1<<8) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
35149     #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                      8
35150     #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
35151     #define CAU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                         10
35152     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_BB_A0                                          (0x1<<10) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
35153     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_BB_A0_SHIFT                                    10
35154     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_BB_B0                                          (0x1<<10) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
35155     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_BB_B0_SHIFT                                    10
35156     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_K2                                             (0x1<<11) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_0 .
35157     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_0_K2_SHIFT                                       11
35158     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_BB_A0                                          (0x1<<11) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
35159     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_BB_A0_SHIFT                                    11
35160     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_BB_B0                                          (0x1<<11) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
35161     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_BB_B0_SHIFT                                    11
35162     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_K2                                             (0x1<<12) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY_1 .
35163     #define CAU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_1_K2_SHIFT                                       12
35164     #define CAU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
35165     #define CAU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            9
35166     #define CAU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: CAU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
35167     #define CAU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            12
35168 #define CAU_REG_MEM_ECC_EVENTS                                                                       0x1c021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
35169 #define CAU_REG_MEM005_I_MEM_DFT_K2                                                                  0x1c0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.i_cau_agg_descriptor_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
35170 #define CAU_REG_MEM006_I_MEM_DFT_K2                                                                  0x1c0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.i_cau_agg_unit_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
35171 #define CAU_REG_MEM008_I_MEM_DFT_K2                                                                  0x1c022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.i_cau_cqe_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35172 #define CAU_REG_MEM009_I_MEM_DFT_K2                                                                  0x1c0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.i_cau_fsm_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
35173 #define CAU_REG_MEM010_I_MEM_DFT_K2                                                                  0x1c0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.i_cau_req_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35174 #define CAU_REG_MEM011_I_MEM_DFT_K2                                                                  0x1c0238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.i_cau_wdata_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35175 #define CAU_REG_MEM001_I_MEM_DFT_K2                                                                  0x1c023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.cau_pi_mem_368sb_IF.i_cau_pi_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
35176 #define CAU_REG_MEM002_I_MEM_DFT_K2                                                                  0x1c0240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.cau_sb_addr_mem_368sb_IF.i_cau_sb_addr_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
35177 #define CAU_REG_MEM003_I_MEM_DFT_K2                                                                  0x1c0244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.cau_sb_timers_mem_368sb_IF.i_cau_sb_timers_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
35178 #define CAU_REG_MEM004_I_MEM_DFT_K2                                                                  0x1c0248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cau.cau_sb_var_mem_368sb_IF.i_cau_sb_var_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
35179 #define CAU_REG_NUM_PI_PER_SB                                                                        0x1c0400UL //Access:RW   DataWidth:0x6   The number of Protocol Index per Status Block. Value can be even numbers only from 2 to 32. numbers above 12 will reduce the number of SB that are supported (3456/num_pi_per_sb).  Chips: BB_A0 BB_B0 K2
35180 #define CAU_REG_PXP_REQ_MSG_FIELDS                                                                   0x1c0404UL //Access:RW   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
35181     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_TPH_HINT                                           (0x3<<0) // The value of the TPH Hint field in the PXP request for SB DMA.
35182     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_TPH_HINT_SHIFT                                     0
35183     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_TPH_HINT                                          (0x3<<2) // The value of the TPH Hint field in the PXP request for CQE messages.
35184     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_TPH_HINT_SHIFT                                    2
35185     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_ENDIANITY                                             (0x3<<4) // The endianity mode in the PXP request.
35186     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_ENDIANITY_SHIFT                                       4
35187     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_RO                                                    (0x1<<6) // The value of the Relax Ordering field in the PXP request.
35188     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_RO_SHIFT                                              6
35189     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_NS                                                    (0x1<<7) // The value of the No Snoop field in the PXP request.
35190     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_NS_SHIFT                                              7
35191     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_VQID                                                  (0x1f<<8) // The value of the VQID field in the PXP request.
35192     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_VQID_SHIFT                                            8
35193     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_PAD2CACHE                                          (0x1<<13) // The value of the Pad to Cache Line field in the SB DMA PXP request.
35194     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_SB_PAD2CACHE_SHIFT                                    13
35195     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_PAD2CACHE                                         (0x1<<14) // The value of the Pad to Cache Line field in the CQE PXP request.
35196     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_CQE_PAD2CACHE_SHIFT                                   14
35197     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_ATC                                                   (0x7<<15) // The value of the ATC flags  in the PXP request.
35198     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_ATC_SHIFT                                             15
35199     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_DONE_TYPE                                             (0x1<<18) // The value of the done type in the PXP request.
35200     #define CAU_REG_PXP_REQ_MSG_FIELDS_PXP_REQ_DONE_TYPE_SHIFT                                       18
35201 #define CAU_REG_PI_BYP_GRAY2_EN                                                                      0x1c0408UL //Access:RW   DataWidth:0x1   Enabling pi value of command N+2/N+1 as part of sb_dma message of command N (Cont00065605 related) When set, bypass can be implemented (i.e. bug not fixed) When reset, bypass cannot be implemented (i.e. bug fixed)  Chips: BB_A0 BB_B0 K2
35202 #define CAU_REG_OUTSTANDING_WRITE                                                                    0x1c040cUL //Access:RW   DataWidth:0x8   The max number of outstanding write requests without receiving write done. Values 1-128. Zero is not a valid value.  Chips: BB_A0 BB_B0 K2
35203 #define CAU_REG_RESET_MEMORIES                                                                       0x1c0410UL //Access:RW   DataWidth:0x6   Write one to each bit will reset the whole memory. When the memory reset finished the appropriate bit will be clear. [0] - PI memory; [1] - SB var memory; [2]- SB address memory; [3] -Timers memory; [4] - fsm memory,[5] - aggregation memory.  Chips: BB_A0 BB_B0 K2
35204 #define CAU_REG_CLEANUP_COMMAND                                                                      0x1c0414UL //Access:W    DataWidth:0xd   Write to this register will perform cleanup on the written SB number. [8:0] - SB absolute index; [9] - Cleanup set/clr (0-clr; 1 - set); [12:10] Cleanup type (0-4).  Chips: BB_A0 BB_B0 K2
35205 #define CAU_REG_CLEANUP_COMMAND_DONE                                                                 0x1c0418UL //Access:R    DataWidth:0x1   When reading one from this register mean the cleanup was done. Reading it will clear its value.  Chips: BB_A0 BB_B0 K2
35206 #define CAU_REG_IN_ARB_PRIORITY                                                                      0x1c0500UL //Access:RW   DataWidth:0x6   Input arbiter (sp with anti starvation) priority for the input clients: bits 1:0 PXP input commands. bits 3:2 RBC cleanup. bits 5:4 Timer expiration priority. Priority values are from 0 (highest priority) to 2 (lowest).  Chips: BB_A0 BB_B0 K2
35207 #define CAU_REG_IN_ARB_TIMEOUT                                                                       0x1c0504UL //Access:RW   DataWidth:0x8   Input arbiter (sp with anti starvation) anti starvation timeout. value of 0 means the arbitration is constant rr.  Chips: BB_A0 BB_B0 K2
35208 #define CAU_REG_CQE_SIZE                                                                             0x1c0600UL //Access:RW   DataWidth:0x1   Indicate the size of the CQE. 0 - 32B; 1 - 64B.  Chips: BB_A0 BB_B0 K2
35209 #define CAU_REG_CQE_AGG_UNIT_SIZE                                                                    0x1c0604UL //Access:RW   DataWidth:0x2   Indicate the size of the AGG unit. 0 - 64B; 1 - 128B; 2 - 256B; 3 - illegal.  Chips: BB_A0 BB_B0 K2
35210 #define CAU_REG_CQE_FLUSH_ALL                                                                        0x1c0608UL //Access:RW   DataWidth:0x1   Flush all command - will flush all the CQE AGG unit that are in dirty state and free all AGG units.  Chips: BB_A0 BB_B0 K2
35211 #define CAU_REG_CQE_FLUSH_ALL_DONE                                                                   0x1c060cUL //Access:R    DataWidth:0x1   Read clear register. 1 means the the cqe_flush_all command was finished.  Chips: BB_A0 BB_B0 K2
35212 #define CAU_REG_AGG_RELEASE_TIMER                                                                    0x1c0610UL //Access:RW   DataWidth:0x10  The value of ReleaseTmr in system clock cycles (25MHz). Each expiration will generate an event that affect the FSM of each AGG unit that is in CLEAN state (will move to TIME WAIT state) and TIME WAIT state (will move to CLEAN).  Chips: BB_A0 BB_B0 K2
35213 #define CAU_REG_TICK_SIZE                                                                            0x1c0700UL //Access:RW   DataWidth:0x10  The number of cycles in each tick of the timer. Clock 25 MHz. value must be bigger than 2.  Chips: BB_A0 BB_B0 K2
35214 #define CAU_REG_SCAN_TICK                                                                            0x1c0704UL //Access:RW   DataWidth:0xc   The number of tick that will cause scan. Zero is not a valid number.  Chips: BB_A0 BB_B0 K2
35215 #define CAU_REG_LONG_TIMEOUT_THRESHOLD                                                               0x1c0708UL //Access:RW   DataWidth:0xa   Threshold in ticks for indicating far timeout to the MISC block.  Chips: BB_A0 BB_B0 K2
35216 #define CAU_REG_STOP_SCAN                                                                            0x1c070cUL //Access:RW   DataWidth:0x1   Setting this bit will disable the timer expiration mechanism. Should be used in close the gate only.  Chips: BB_A0 BB_B0 K2
35217 #define CAU_REG_RX_TIMER_STATUS                                                                      0x1c0780UL //Access:R    DataWidth:0x20  Rx timers status. 0 - inactive 1 - active.  Chips: BB_A0 BB_B0 K2
35218 #define CAU_REG_RX_TIMER_STATUS_SIZE                                                                 9
35219 #define CAU_REG_TX_TIMER_STATUS                                                                      0x1c0800UL //Access:R    DataWidth:0x20  Tx timers status. 0 - inactive 1 - active.  Chips: BB_A0 BB_B0 K2
35220 #define CAU_REG_TX_TIMER_STATUS_SIZE                                                                 9
35221 #define CAU_REG_WDATA_FIFO_AFULL_THR                                                                 0x1c0880UL //Access:RW   DataWidth:0x6   almost full threshold for wdata fifo  Chips: BB_A0 BB_B0 K2
35222 #define CAU_REG_CQE_FIFO_AFULL_THR                                                                   0x1c0884UL //Access:RW   DataWidth:0x5   almost full threshold for cqe fifo (within the input cmd arbiter)  Chips: BB_A0 BB_B0 K2
35223 #define CAU_REG_IGU_REQ_CREDIT_STATUS                                                                0x1c0980UL //Access:R    DataWidth:0x1   Debug:  IGU-CAU request interface credit.  In idle should be 1.  Chips: BB_A0 BB_B0 K2
35224 #define CAU_REG_IGU_CMD_CREDIT_STATUS                                                                0x1c0984UL //Access:R    DataWidth:0x1   Debug:  IGU-CAU command interface credit.  In idle should be 1.  Chips: BB_A0 BB_B0 K2
35225 #define CAU_REG_STAT_CTRL_SB_SELECT                                                                  0x1c0a80UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35226     #define CAU_REG_STAT_CTRL_SB_SELECT_IDX                                                          (0x1ff<<0) // Statistic: SB index to collect statistics on.
35227     #define CAU_REG_STAT_CTRL_SB_SELECT_IDX_SHIFT                                                    0
35228     #define CAU_REG_STAT_CTRL_SB_SELECT_EN                                                           (0x1<<9) // Statistic: enable SB index  statistics.
35229     #define CAU_REG_STAT_CTRL_SB_SELECT_EN_SHIFT                                                     9
35230 #define CAU_REG_STAT_CTRL_PROTOCOL                                                                   0x1c0a84UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35231     #define CAU_REG_STAT_CTRL_PROTOCOL_NUM                                                           (0x1f<<0) // Statistic: protocol number to collect statistics on.
35232     #define CAU_REG_STAT_CTRL_PROTOCOL_NUM_SHIFT                                                     0
35233     #define CAU_REG_STAT_CTRL_PROTOCOL_EN                                                            (0x1<<5) // Statistic: enable protocol  statistics.
35234     #define CAU_REG_STAT_CTRL_PROTOCOL_EN_SHIFT                                                      5
35235 #define CAU_REG_STAT_CTRL_CLIENT                                                                     0x1c0a88UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35236     #define CAU_REG_STAT_CTRL_CLIENT_IDX                                                             (0xf<<0) // Statistic: client index to collect statistics on. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8 =  GRC cleanup; 9 = Expiration.
35237     #define CAU_REG_STAT_CTRL_CLIENT_IDX_SHIFT                                                       0
35238     #define CAU_REG_STAT_CTRL_CLIENT_EN                                                              (0x1<<4) // Statistic: enable client  statistics.
35239     #define CAU_REG_STAT_CTRL_CLIENT_EN_SHIFT                                                        4
35240 #define CAU_REG_STAT_CTRL_FSM0_LINE                                                                  0x1c0a8cUL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35241     #define CAU_REG_STAT_CTRL_FSM0_LINE_SELECT                                                       (0xff<<0) // Statistic: Line number of FSM 0 to collect statistics on.
35242     #define CAU_REG_STAT_CTRL_FSM0_LINE_SELECT_SHIFT                                                 0
35243     #define CAU_REG_STAT_CTRL_FSM0_LINE_EN                                                           (0x1<<8) // Statistic: enable FSM 0 line  statistics.
35244     #define CAU_REG_STAT_CTRL_FSM0_LINE_EN_SHIFT                                                     8
35245 #define CAU_REG_STAT_CTRL_FSM1_LINE                                                                  0x1c0a90UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35246     #define CAU_REG_STAT_CTRL_FSM1_LINE_SELECT                                                       (0xff<<0) // Statistic: Line number of FSM 1 to collect statistics on.
35247     #define CAU_REG_STAT_CTRL_FSM1_LINE_SELECT_SHIFT                                                 0
35248     #define CAU_REG_STAT_CTRL_FSM1_LINE_EN                                                           (0x1<<8) // Statistic: enable FSM 1 line  statistics.
35249     #define CAU_REG_STAT_CTRL_FSM1_LINE_EN_SHIFT                                                     8
35250 #define CAU_REG_STAT_CTRL_TIMER_CMD_TYPE                                                             0x1c0a94UL //Access:RW   DataWidth:0x3   Statistic: enable timer command type. One bit for each timer command type: [0] - rewind; [1] - clear; [2] - rewind to shorter. When set the counter monitor these commands.  Chips: BB_A0 BB_B0 K2
35251 #define CAU_REG_STAT_COUNTER_SB_GEN                                                                  0x1c0b80UL //Access:RW   DataWidth:0x20  The number of times that SB was generated (written) for the selected SB (according to stat_ctrl_sb_select_idx).  Chips: BB_A0 BB_B0 K2
35252 #define CAU_REG_STAT_COUNTER_FSM0_TIMER_CMD                                                          0x1c0b84UL //Access:RW   DataWidth:0x20  The number of times that the timer was rewind for the selected SB (according to stat_ctrl_sb_select_idx) and timer command (according to stat_ctrl_timer_cmd_type) on FSM0.  Chips: BB_A0 BB_B0 K2
35253 #define CAU_REG_STAT_COUNTER_FSM1_TIMER_CMD                                                          0x1c0b88UL //Access:RW   DataWidth:0x20  The number of times that the timer was rewind for the selected SB (according to stat_ctrl_sb_select_idx) and timer command (according to stat_ctrl_timer_cmd_type) on FSM1.  Chips: BB_A0 BB_B0 K2
35254 #define CAU_REG_STAT_COUNTER_FSM0_EXP                                                                0x1c0b8cUL //Access:RW   DataWidth:0x20  The number of times that the timer has expired for FSM0 of the selected SB (according to stat_ctrl_sb_select_idx) .  Chips: BB_A0 BB_B0 K2
35255 #define CAU_REG_STAT_COUNTER_FSM1_EXP                                                                0x1c0b90UL //Access:RW   DataWidth:0x20  The number of times that the timer has expired for FSM1 of the selected SB (according to stat_ctrl_sb_select_idx) .  Chips: BB_A0 BB_B0 K2
35256 #define CAU_REG_STAT_COUNTER_PROTOCOL_TIMER_CMD                                                      0x1c0b94UL //Access:RW   DataWidth:0x20  The number of times that the timer was rewind for the selected SB (according to stat_ctrl_sb_select_idx); selected PI (according to stat_ctrl_protocol_num) and timer command (according to stat_ctrl_timer_cmd_type).  Chips: BB_A0 BB_B0 K2
35257 #define CAU_REG_STAT_COUNTER_PI_INCOME_CMD                                                           0x1c0b98UL //Access:RW   DataWidth:0x20  The number of incoming producer update commands for the selected PI (according to stat_ctrl_protocol_num) and SB (according to stat_ctrl_sb_idx).  Chips: BB_A0 BB_B0 K2
35258 #define CAU_REG_STAT_COUNTER_CLIENT_INCOME_CMD                                                       0x1c0b9cUL //Access:RW   DataWidth:0x20  The number of incoming commands from the selected client (according to stat_ctrl_client_idx).  Chips: BB_A0 BB_B0 K2
35259 #define CAU_REG_STAT_COUNTER_FSM0_LINE                                                               0x1c0ba0UL //Access:RW   DataWidth:0x20  The number of times the FSM reached a specific line (stat_ctrl_fsm0_line_select) for the selected protocol (stat_ctrl_protocol_idx) within the selected SB (stat_ctrl_sb_select_idx).  Chips: BB_A0 BB_B0 K2
35260 #define CAU_REG_STAT_COUNTER_FSM1_LINE                                                               0x1c0ba4UL //Access:RW   DataWidth:0x20  The number of times the FSM reached a specific line (stat_ctrl_fsm1_line_select) for the selected protocol (stat_ctrl_protocol_idx) within the selected SB (stat_ctrl_sb_select_idx).  Chips: BB_A0 BB_B0 K2
35261 #define CAU_REG_STAT_COUNTER_CQE_MSG_SENT                                                            0x1c0ba8UL //Access:RW   DataWidth:0x20  The number of CQE messages that where sent to the PXP.  Chips: BB_A0 BB_B0 K2
35262 #define CAU_REG_STAT_COUNTER_CQE_DMA_QWORD                                                           0x1c0bacUL //Access:RW   DataWidth:0x20  The amount of CQE data that was sent in QWORD.  Chips: BB_A0 BB_B0 K2
35263 #define CAU_REG_STAT_COUNTER_CQE_CACHE_HIT                                                           0x1c0bb0UL //Access:RW   DataWidth:0x20  The number of CQE command that there was a match in the aggregation memory.  Chips: BB_A0 BB_B0 K2
35264 #define CAU_REG_STAT_COUNTER_CQE_CACHE_MISS_NEW_AGG                                                  0x1c0bb4UL //Access:RW   DataWidth:0x20  The number of CQE command that there was no match in the aggregation memory but there was a free unit found.  Chips: BB_A0 BB_B0 K2
35265 #define CAU_REG_STAT_COUNTER_CQE_CACHE_MISS_NO_FREE                                                  0x1c0bb8UL //Access:RW   DataWidth:0x20  The number of CQE command that there was no match in the aggregation memory and no free unit was found.  Chips: BB_A0 BB_B0 K2
35266 #define CAU_REG_STAT_COUNTER_CQE_FULL_CACHE                                                          0x1c0bbcUL //Access:RW   DataWidth:0x20  The nuber of CQE dmae with full cache (DMA size = cqe_agg_unit_size).  Chips: BB_A0 BB_B0 K2
35267 #define CAU_REG_STAT_COUNTER_CQE_PARTIAL_CACHE                                                       0x1c0bc0UL //Access:RW   DataWidth:0x20  The nuber of CQE dmae with partial cache (DMA size < cqe_agg_unit_size).  Chips: BB_A0 BB_B0 K2
35268 #define CAU_REG_DEBUG_FIFO_STATUS                                                                    0x1c0c80UL //Access:R    DataWidth:0x6   Debug: all the FIFO status. 0 - FIFO empty; 1 - FIFO not empty. [0] - PXP command FIFO; [1] - CQE FIFO; [2] - timers expiration FIFO;  [3] - IGU req FIFO; [4] - IGU wdata FIFO; [5] - IGU command FIFO.  Chips: BB_A0 BB_B0 K2
35269 #define CAU_REG_ERROR_PXP_REQ                                                                        0x1c0c84UL //Access:R    DataWidth:0x15  Debug; debug information if an error command arrived to the CAU from the PXP: [20:18] - error typ (1- read request; 2 - CqeType disabled and length >1 or CQE enable and length not match cqe_siz; 3 - sb_index >= CAU_NUM_SB or SB index >  CAU_NUM_PI/num_pi_per_sb; 4 - pi_relative_number > num_pi_per_sb);  [17:14] - source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM)); [13:5] - SB abs index; [4:0] - pi_relative_number. If error type = 1 ignore bits [13:0].  Chips: BB_A0 BB_B0 K2
35270 #define CAU_REG_ERROR_FSM_LINE                                                                       0x1c0c88UL //Access:R    DataWidth:0x1d  Debug; debug information if the FSM arived to an invalid line:  [3:0] - source (0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8=GRC cleanup; 9=timer expiration); [12:4] - SB abs index; [13] -  reserved; [14] otherFSM (if set the commad was due to other FSM); [15] - FSM_sel;  [20:16] - PI relative number; [24:21] - event ID; [28:25] - state;.  Chips: BB_A0 BB_B0 K2
35271 #define CAU_REG_ERROR_FSM_LINE_PRE                                                                   0x1c0c8cUL //Access:R    DataWidth:0xa   Debug; [9] if set data valid; [8] previous FSM_sel; [7:4] - previous state; [3:0] - previous event ID;.  Chips: BB_A0 BB_B0 K2
35272 #define CAU_REG_PARITY_LATCH_STATUS                                                                  0x1c0c90UL //Access:R    DataWidth:0x1   Debug: If set a parity occurd and the CAU assert discard flag to the IGU from now on (until hard reset).  Chips: BB_A0 BB_B0 K2
35273 #define CAU_REG_ERROR_CLEANUP_CMD_REG                                                                0x1c0c94UL //Access:R    DataWidth:0x19  comment="Debug: [15:0] The PF that caused the error- one bit per PF; [24:16] - SB index.  Chips: BB_A0 BB_B0 K2
35274 #define CAU_REG_AGG_UNITS_STATE_READ_EN                                                              0x1c0c98UL //Access:W    DataWidth:0x1   Debug: write only. Writing to this register will copy the aggregation unit status to the agg_unit_state registers.  Chips: BB_A0 BB_B0 K2
35275 #define CAU_REG_AGG_UNITS_0TO15_STATE                                                                0x1c0c9cUL //Access:R    DataWidth:0x20  Debug: Each 2 bits reflect the aggregation unit state of unit [i] when there was writing to agg_units_state_read_en register. (i =0-15). 0 - free; 1 - dirty; 2 - clean; 3 - time wait.  Chips: BB_A0 BB_B0 K2
35276 #define CAU_REG_AGG_UNITS_16TO31_STATE                                                               0x1c0ca0UL //Access:R    DataWidth:0x20  Debug: Each 2 bits reflect the aggregation unit state of unit [i] when there was writing to agg_units_state_read_en register. (i = 16-31). 0 - free; 1 - dirty; 2 - clean; 3 - time wait.  Chips: BB_A0 BB_B0 K2
35277 #define CAU_REG_AGG_UNITS_32TO47_STATE                                                               0x1c0ca4UL //Access:R    DataWidth:0x20  Debug: Each 2 bits reflect the aggregation unit state of unit [i] when there was writing to agg_units_state_read_en register. (i = 32-47). 0 - free; 1 - dirty; 2 - clean; 3 - time wait.  Chips: BB_A0 BB_B0 K2
35278 #define CAU_REG_AGG_UNITS_48TO63_STATE                                                               0x1c0ca8UL //Access:R    DataWidth:0x20  Debug: Each 2 bits reflect the aggregation unit state of unit [i] when there was writing to agg_units_state_read_en register. (i = 48-63). 0 - free; 1 - dirty; 2 - clean; 3 - time wait.  Chips: BB_A0 BB_B0 K2
35279 #define CAU_REG_ECO_RESERVED                                                                         0x1c0cacUL //Access:RW   DataWidth:0x8   Reserved for ECO if needed.  Chips: BB_A0 BB_B0 K2
35280 #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB                                                             0x1c0d80UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35281     #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_IDX                                                     (0x1ff<<0) // Debug: minimun SB index for the debug.
35282     #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_IDX_SHIFT                                               0
35283     #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_EN                                                      (0x1<<9) // Debug: if set the debug information will be collected for SB index equal or above debug_record_mask_min_sb_idx.
35284     #define CAU_REG_DEBUG_RECORD_MASK_MIN_SB_EN_SHIFT                                                9
35285 #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB                                                             0x1c0d84UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35286     #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_IDX                                                     (0x1ff<<0) // Debug: maximum SB index for the debug.
35287     #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_IDX_SHIFT                                               0
35288     #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_EN                                                      (0x1<<9) // Debug: if set the debug information will be collected for SB index equal or below debug_record_mask_min_sb_idx.
35289     #define CAU_REG_DEBUG_RECORD_MASK_MAX_SB_EN_SHIFT                                                9
35290 #define CAU_REG_DEBUG_RECORD_MASK_FID                                                                0x1c0d88UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35291     #define CAU_REG_DEBUG_RECORD_MASK_FID_NUM                                                        (0x1ff<<0) // Debug: FID number for debug . if VF - [8] = 1; [7:0] = VF number; if PF - [8] = 0; [7:4] = 0; [3:0] = PF number.
35292     #define CAU_REG_DEBUG_RECORD_MASK_FID_NUM_SHIFT                                                  0
35293     #define CAU_REG_DEBUG_RECORD_MASK_FID_EN                                                         (0x1<<9) // Debug: if set the debug information will be collected for FID specified in debug_record_mask_fid_num.
35294     #define CAU_REG_DEBUG_RECORD_MASK_FID_EN_SHIFT                                                   9
35295     #define CAU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE                                                    (0x1<<10) // Debug: if clear the debug information will be collected for FID equal to debug_record_mask_fid_num. if set he debug information will be collected for FID not equal to debug_record_mask_fid_num.
35296     #define CAU_REG_DEBUG_RECORD_MASK_FID_EXCLUDE_SHIFT                                              10
35297 #define CAU_REG_DEBUG_RECORD_MASK_SOURCE                                                             0x1c0d8cUL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35298     #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_IDX                                                     (0xf<<0) // Debug: source index for the debug. 0=TSTORM; 1=MSTORM; 2=USTORM; 3=XSTORM; 4=YSTORM; 5=PSTORM; 6=PCIe; 7=other (PBF/NIG/QM); 8 =  GRC cleanup; 9 = expiration.
35299     #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_IDX_SHIFT                                               0
35300     #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_EN                                                      (0x1<<4) // Debug: if set the debug information will be collected for source equal to debug_record_mask_source_idx.
35301     #define CAU_REG_DEBUG_RECORD_MASK_SOURCE_EN_SHIFT                                                4
35302 #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE                                                           0x1c0d90UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35303     #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_IDX                                                   (0x7<<0) // Debug: command type for the debug. [0] - PI producer update; [1] - cleanup; [2] - expiration.
35304     #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_IDX_SHIFT                                             0
35305     #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN                                                    (0x1<<3) // Debug: if set the debug information will be collected for the marked commands only according to debug_record_mask_cmd_type_idx.
35306     #define CAU_REG_DEBUG_RECORD_MASK_CMD_TYPE_EN_SHIFT                                              3
35307 #define CAU_REG_REQ_COUNTER                                                                          0x1c0e00UL //Access:R    DataWidth:0x8   Debug:  the number of request that were sent to the IGU.  Chips: BB_A0 BB_B0 K2
35308 #define CAU_REG_ACK_COUNTER                                                                          0x1c0e04UL //Access:R    DataWidth:0x8   Debug:  the number of ack that were received from the IGU on the recuest interface.  Chips: BB_A0 BB_B0 K2
35309 #define CAU_REG_WDONE_COUNTER                                                                        0x1c0e08UL //Access:R    DataWidth:0x8   Debug:  the number of write done that were received from the IGU.  Chips: BB_A0 BB_B0 K2
35310 #define CAU_REG_DBG_OUT_DATA                                                                         0x1c0e80UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
35311 #define CAU_REG_DBG_OUT_DATA_SIZE                                                                    8
35312 #define CAU_REG_DBG_OUT_VALID                                                                        0x1c0ea0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
35313 #define CAU_REG_DBG_OUT_FRAME                                                                        0x1c0ea4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
35314 #define CAU_REG_DBG_SELECT                                                                           0x1c0ea8UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
35315 #define CAU_REG_DBG_DWORD_ENABLE                                                                     0x1c0eacUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
35316 #define CAU_REG_DBG_SHIFT                                                                            0x1c0eb0UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
35317 #define CAU_REG_DBG_FORCE_VALID                                                                      0x1c0eb4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
35318 #define CAU_REG_DBG_FORCE_FRAME                                                                      0x1c0eb8UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
35319 #define CAU_REG_MAIN_FSM_STATUS                                                                      0x1c0f00UL //Access:R    DataWidth:0x4   Debug:  FSM state for debug.  Chips: BB_A0 BB_B0 K2
35320 #define CAU_REG_VAR_READ_FSM_STATUS                                                                  0x1c0f04UL //Access:R    DataWidth:0x2   Debug:  FSM state for debug.  Chips: BB_A0 BB_B0 K2
35321 #define CAU_REG_IGU_DMA_FSM_STATUS                                                                   0x1c0f08UL //Access:R    DataWidth:0x3   Debug:  FSM state for debug.  Chips: BB_A0 BB_B0 K2
35322 #define CAU_REG_IGU_CQE_CMD_FSM_STATUS                                                               0x1c0f0cUL //Access:R    DataWidth:0x5   Debug:  FSM state for debug.Idle state value are 0-2  Chips: BB_A0 BB_B0 K2
35323 #define CAU_REG_IGU_CQE_AGG_FSM_STATUS                                                               0x1c0f10UL //Access:R    DataWidth:0x4   Debug:  FSM state for debug.  Chips: BB_A0 BB_B0 K2
35324 #define CAU_REG_CQE_FIFO                                                                             0x1c2000UL //Access:WB_R DataWidth:0x80  Debug: Provides read-only access of the CQE input command FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
35325 #define CAU_REG_CQE_FIFO_SIZE                                                                        120
35326 #define CAU_REG_IGU_CMD_FIFO                                                                         0x1c2200UL //Access:WB_R DataWidth:0x35  Debug: Provides read-only access of the IGU command FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
35327 #define CAU_REG_IGU_CMD_FIFO_SIZE                                                                    16
35328 #define CAU_REG_PXP_REQ_FIFO                                                                         0x1c2300UL //Access:WB_R DataWidth:0x62  Debug: Provides read-only access of the PXP reques FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
35329 #define CAU_REG_PXP_REQ_FIFO_SIZE                                                                    32
35330 #define CAU_REG_PXP_WDATA_FIFO                                                                       0x1c2400UL //Access:WB_R DataWidth:0x84  Debug: Provides read-only access of the PXP write-data FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
35331 #define CAU_REG_PXP_WDATA_FIFO_SIZE                                                                  256
35332 #define CAU_REG_AGG_UNIT_CAM                                                                         0x1c4000UL //Access:R    DataWidth:0xf   Debug: The SB index and PI relative number of each aggregation unit. [0] - valid; [9:1] - absolute SB index; [14:10] - relative PI number.  Chips: BB_A0 BB_B0 K2
35333 #define CAU_REG_AGG_UNIT_CAM_SIZE                                                                    64
35334 #define CAU_REG_FSM_TABLE                                                                            0x1c4400UL //Access:RW   DataWidth:0x10  The FSM table is a truth table. The inputs to the truth table are the address of the RAM and the outputs is the data in the RAM. The bits [7:4] of the address are the current_state and bits [3:0] are the event_id. The data is :[3:0] - next state; [5:4] - timer cmd (0 - None; 1 - Rewind; 2 - Clear; 3 - Rewind to shorter); [6] - SB producer increment (If set the SB segment index (PROD) is incremented by 1); [7] - SB write cmd (If set the entire SB segment is written over the PXP to host memory); [8] IGU cmd (If set then generate an IGU PROD update command); [12:9] - event ID to other FSM (The event ID value to generate to the other FSM); [14:13] - update timer cmd (0 - NONE; 1 - Set to new; 2 - Set to max (new/old); 3 - Set to min (new/old)); [15] - valid line (If set then this line is a valid line).  Chips: BB_A0 BB_B0 K2
35335 #define CAU_REG_FSM_TABLE_SIZE                                                                       256
35336 #define CAU_REG_SB_VAR_MEMORY                                                                        0x1c6000UL //Access:WB   DataWidth:0x40  Status Block variable: [23:0] producer index; [27:24] state0 (RX); [31:28] state1 (TX); [38:32] SbTimeSet0 (Indicates the RX TimeSet that this SB is associated with); [45:39] SbTimeSet1 (Indicates the TX TimeSet that this SB is associated with); [47:46] TimerRes0 (This value will determine the RX FSM timer resolution in ticks. Valid values are 0-2 only); [49:48] TimerRes1 (This value will determine the TX FSM timer resolution in ticks. Valid values are 0-2 only); [62:50] FID ([12:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)); [63] TPH valid (If set then indicates that the TPH STAG is equal to the SB number. Otherwise the STAG will be equal to all ones);  the memory will receive  the following reset values after writing to the appropriate bit in the reset memory register: All fields will be zero; excluding the FID; each PF will receive  17 SB; 0-16 PF0; 17-33 PF1 .. 119-135 PF7. All the SB above 136 reset value is zero therefore thy are allocated to PF 0 also.  Chips: BB_A0 BB_B0 K2
35337 #define CAU_REG_SB_VAR_MEMORY_SIZE                                                                   736
35338 #define CAU_REG_SB_ADDR_MEMORY                                                                       0x1c8000UL //Access:WB   DataWidth:0x40  Address of the Status Block DMA message.  Chips: BB_A0 BB_B0 K2
35339 #define CAU_REG_SB_ADDR_MEMORY_SIZE                                                                  736
35340 #define CAU_REG_PI_MEMORY                                                                            0x1d0000UL //Access:RW   DataWidth:0x18  Protocol Index memory.[15:0] - protocol producer; [22:16] - PiTimeSet (This value determines the TimeSet that the PI is associated with); [23] - FsmSel (0-RX; 1 - TX).  Chips: BB_A0 BB_B0 K2
35341 #define CAU_REG_PI_MEMORY_SIZE                                                                       4416
35342 #define CAU_REG_AGG_UNIT_DATA_MEMORY                                                                 0x1d8000UL //Access:WB   DataWidth:0x80  Debug: the CQE aggregated data. Each aggergation unit size occupies N addresses. N: If (cqe_agg_unit_size = 0), then N = 4  addresses If (cqe_agg_unit_size = 1), then N = 8  addresses If (cqe_agg_unit_size = 2), then N = 16 addresses Address calculation: If (AggUnitSizeLog = 2 and CqeSizeLog = 0), then Address = {slot number[2:0], line_couner[0], agg_unit_index[4:0]}; Else If (AggUnitSizeLog = 2 and CqeSizeLog = 1), then  Address = {slot number[1:0], line_couner [1:0], agg_unit_index[4:0]}; Else If (AggUnitSizeLog = 1 and CqeSizeLog = 1), then Address = {slot number[0], line_couner [1:0], agg_unit_index[5:0]}; Else Address = {slot number[1:0], line_couner [0], agg_unit_index[5:0]};                          Note that line_couner is running index in the slot;  Chips: BB_A0 BB_B0 K2
35343 #define CAU_REG_AGG_UNIT_DATA_MEMORY_SIZE                                                            3584
35344 #define CAU_REG_AGG_UNIT_DESCRIPTOR                                                                  0x1dc000UL //Access:WB_R DataWidth:0x56  Debug: the aggregation data of each unit. [63:0] - address; [71:64] - valid slots; [84:72] - FID ([13:9] - PF number (in case of VF the parent PF); [8] - VF valid (1 - VF; 0 - PF); [7:0] - VF number (if VF valid = 0 -must be zero)). [85] - TPH valid bit.  Chips: BB_A0 BB_B0 K2
35345 #define CAU_REG_AGG_UNIT_DESCRIPTOR_SIZE                                                             256
35346 #define CAU_REG_SB_TIMERS_MEMORY                                                                     0x1dd000UL //Access:R    DataWidth:0x18  The SB timers. For each SB there are two timers: [11:0] - RX timer; [23:12] - TX timer.  Chips: BB_A0 BB_B0 K2
35347 #define CAU_REG_SB_TIMERS_MEMORY_SIZE                                                                368
35348 #define PRS_REG_SOFT_RST                                                                             0x1f0000UL //Access:RW   DataWidth:0x1   Soft reset - reset all FSM.  Chips: BB_A0 BB_B0 K2
35349 #define PRS_REG_MAC_VLAN_CACHE_INIT                                                                  0x1f0004UL //Access:W    DataWidth:0x1   Any write to this register triggers MAC-VLAN Cache initialization.  Chips: BB_A0 BB_B0 K2
35350 #define PRS_REG_MAC_VLAN_CACHE_INIT_DONE                                                             0x1f0008UL //Access:R    DataWidth:0x1   Set when the cache initialization is complete.  Chips: BB_A0 BB_B0 K2
35351 #define PRS_REG_CAM_SCRUB_HIT_EN                                                                     0x1f000cUL //Access:RW   DataWidth:0x1   When set to 1 the cam hit parity scrubbing feature is enabled in the MAC/VLAN cache CAM.  Chips: BB_A0 BB_B0 K2
35352 #define PRS_REG_CAM_SCRUB_MISS_EN                                                                    0x1f0010UL //Access:RW   DataWidth:0x1   When set to 1 the cam miss parity scrubbing feature is enabled in the MAC/VLAN cache CAM.  Chips: BB_A0 BB_B0 K2
35353 #define PRS_REG_INT_STS_0                                                                            0x1f0040UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35354     #define PRS_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
35355     #define PRS_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
35356     #define PRS_REG_INT_STS_0_LCID_VALIDATION_ERR                                                    (0x1<<1) // Load Request Mini-cache validation error
35357     #define PRS_REG_INT_STS_0_LCID_VALIDATION_ERR_SHIFT                                              1
35358 #define PRS_REG_INT_MASK_0                                                                           0x1f0044UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35359     #define PRS_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: PRS_REG_INT_STS_0.ADDRESS_ERROR .
35360     #define PRS_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
35361     #define PRS_REG_INT_MASK_0_LCID_VALIDATION_ERR                                                   (0x1<<1) // This bit masks, when set, the Interrupt bit: PRS_REG_INT_STS_0.LCID_VALIDATION_ERR .
35362     #define PRS_REG_INT_MASK_0_LCID_VALIDATION_ERR_SHIFT                                             1
35363 #define PRS_REG_INT_STS_WR_0                                                                         0x1f0048UL //Access:WR   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35364     #define PRS_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
35365     #define PRS_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
35366     #define PRS_REG_INT_STS_WR_0_LCID_VALIDATION_ERR                                                 (0x1<<1) // Load Request Mini-cache validation error
35367     #define PRS_REG_INT_STS_WR_0_LCID_VALIDATION_ERR_SHIFT                                           1
35368 #define PRS_REG_INT_STS_CLR_0                                                                        0x1f004cUL //Access:RC   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35369     #define PRS_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
35370     #define PRS_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
35371     #define PRS_REG_INT_STS_CLR_0_LCID_VALIDATION_ERR                                                (0x1<<1) // Load Request Mini-cache validation error
35372     #define PRS_REG_INT_STS_CLR_0_LCID_VALIDATION_ERR_SHIFT                                          1
35373 #define PRS_REG_PRTY_MASK                                                                            0x1f0054UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35374     #define PRS_REG_PRTY_MASK_CAM_PARITY                                                             (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS.CAM_PARITY .
35375     #define PRS_REG_PRTY_MASK_CAM_PARITY_SHIFT                                                       0
35376     #define PRS_REG_PRTY_MASK_GFT_CAM_PARITY                                                         (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS.GFT_CAM_PARITY .
35377     #define PRS_REG_PRTY_MASK_GFT_CAM_PARITY_SHIFT                                                   1
35378 #define PRS_REG_PACKET_REGION_0                                                                      0x1f0100UL //Access:RW   DataWidth:0x8   Context region for received Ethernet packet with a match and packet type 0. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35379 #define PRS_REG_PACKET_REGION_1                                                                      0x1f0104UL //Access:RW   DataWidth:0x8   Context region for received Ethernet packet with a match and packet type 1. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35380 #define PRS_REG_PACKET_REGION_2                                                                      0x1f0108UL //Access:RW   DataWidth:0x8   Context region for received Ethernet packet with a match and packet type 2. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35381 #define PRS_REG_PACKET_REGION_3                                                                      0x1f010cUL //Access:RW   DataWidth:0x8   Context region for received Ethernet packet with a match and packet type 3. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35382 #define PRS_REG_PACKET_REGION_4                                                                      0x1f0110UL //Access:RW   DataWidth:0x8   Context region for received Ethernet packet with a match and packet type 4. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35383 #define PRS_REG_PACKET_REGION_5                                                                      0x1f0114UL //Access:RW   DataWidth:0x8   Context region for received Ethernet packet with a match and packet type 5. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35384 #define PRS_REG_PACKET_REGION_6                                                                      0x1f0118UL //Access:RW   DataWidth:0x8   Context region for received Ethernet packet with a match and packet type 6. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35385 #define PRS_REG_PACKET_REGION_7                                                                      0x1f011cUL //Access:RW   DataWidth:0x8   Context region for received Ethernet packet with a match and packet type 7. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35386 #define PRS_REG_PURE_REGION_0                                                                        0x1f0120UL //Access:RW   DataWidth:0x8   Context region for pure acknowledge packets with connection type 0. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35387 #define PRS_REG_PURE_REGION_1                                                                        0x1f0124UL //Access:RW   DataWidth:0x8   Context region for pure acknowledge packets with connection type 1. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35388 #define PRS_REG_PURE_REGION_2                                                                        0x1f0128UL //Access:RW   DataWidth:0x8   Context region for pure acknowledge packets with connection type 2. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35389 #define PRS_REG_PURE_REGION_3                                                                        0x1f012cUL //Access:RW   DataWidth:0x8   Context region for pure acknowledge packets with connection type 3. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35390 #define PRS_REG_PURE_REGION_4                                                                        0x1f0130UL //Access:RW   DataWidth:0x8   Context region for pure acknowledge packets with connection type 4. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35391 #define PRS_REG_PURE_REGION_5                                                                        0x1f0134UL //Access:RW   DataWidth:0x8   Context region for pure acknowledge packets with connection type 5. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35392 #define PRS_REG_PURE_REGION_6                                                                        0x1f0138UL //Access:RW   DataWidth:0x8   Context region for pure acknowledge packets with connection type 6. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35393 #define PRS_REG_PURE_REGION_7                                                                        0x1f013cUL //Access:RW   DataWidth:0x8   Context region for pure acknowledge packets with connection type 7. Used in CFC load request message.  Chips: BB_A0 BB_B0 K2
35394 #define PRS_REG_TASK_INC_VALUE                                                                       0x1f0140UL //Access:RW   DataWidth:0x8   The increment value to send in the TCFC load request message.  Chips: BB_A0 BB_B0 K2
35395 #define PRS_REG_CON_INC_VALUE_0                                                                      0x1f0144UL //Access:RW   DataWidth:0x8   The increment value to send in the CCFC load request message for connection type 0.  Chips: BB_A0 BB_B0 K2
35396 #define PRS_REG_CON_INC_VALUE_1                                                                      0x1f0148UL //Access:RW   DataWidth:0x8   The increment value to send in the CCFC load request message for connection type 1.  Chips: BB_A0 BB_B0 K2
35397 #define PRS_REG_CON_INC_VALUE_2                                                                      0x1f014cUL //Access:RW   DataWidth:0x8   The increment value to send in the CCFC load request message for connection type 2.  Chips: BB_A0 BB_B0 K2
35398 #define PRS_REG_CON_INC_VALUE_3                                                                      0x1f0150UL //Access:RW   DataWidth:0x8   The increment value to send in the CCFC load request message for connection type 3.  Chips: BB_A0 BB_B0 K2
35399 #define PRS_REG_CON_INC_VALUE_4                                                                      0x1f0154UL //Access:RW   DataWidth:0x8   The increment value to send in the CCFC load request message for connection type 4.  Chips: BB_A0 BB_B0 K2
35400 #define PRS_REG_CON_INC_VALUE_5                                                                      0x1f0158UL //Access:RW   DataWidth:0x8   The increment value to send in the CCFC load request message for connection type 5.  Chips: BB_A0 BB_B0 K2
35401 #define PRS_REG_CON_INC_VALUE_6                                                                      0x1f015cUL //Access:RW   DataWidth:0x8   The increment value to send in the CCFC load request message for connection type 6.  Chips: BB_A0 BB_B0 K2
35402 #define PRS_REG_CON_INC_VALUE_7                                                                      0x1f0160UL //Access:RW   DataWidth:0x8   The increment value to send in the CCFC load request message for connection type 7.  Chips: BB_A0 BB_B0 K2
35403 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE                                                           0x1f0164UL //Access:RW   DataWidth:0x4   Search response connection type for an FCoE initiator connection.  Chips: BB_A0 BB_B0 K2
35404 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF                                                             0x1f0168UL //Access:RW   DataWidth:0x10  Per-PF: If OX_ID exceeds this value on a PF packet, task-id-not-in-range is set.  Chips: BB_A0 BB_B0 K2
35405 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF                                                             0x1f016cUL //Access:RW   DataWidth:0x10  Per-PF: If OX_ID exceeds this value on a VF packet, task-id-not-in-range is set.  Chips: BB_A0 BB_B0 K2
35406 #define PRS_REG_TASK_ID_MAX_TARGET_PF                                                                0x1f0170UL //Access:RW   DataWidth:0x10  Per-PF: If RX_ID exceeds this value on a PF packet, task-id-not-in-range is set.  Chips: BB_A0 BB_B0 K2
35407 #define PRS_REG_TASK_ID_MAX_TARGET_VF                                                                0x1f0174UL //Access:RW   DataWidth:0x10  Per-PF: If RX_ID exceeds this value on a VF packet, task-id-not-in-range is set.  Chips: BB_A0 BB_B0 K2
35408 #define PRS_REG_TASK_ID_SEGMENT                                                                      0x1f0178UL //Access:RW   DataWidth:0x2   Part of the task_ID calculation for FCoE.  Chips: BB_A0 BB_B0 K2
35409 #define PRS_REG_TASK_REGIONS_INITIATOR                                                               0x1f017cUL //Access:RW   DataWidth:0x8   Context region used in TCFC load requests for initiator mode.  Chips: BB_A0 BB_B0 K2
35410 #define PRS_REG_TASK_REGIONS_TARGET                                                                  0x1f0180UL //Access:RW   DataWidth:0x8   Context region used in TCFC load requests for target mode.  Chips: BB_A0 BB_B0 K2
35411 #define PRS_REG_TASK_TYPE_INITIATOR                                                                  0x1f0184UL //Access:RW   DataWidth:0x4   Connection type used in TCFC load requests for initiator mode.  Chips: BB_A0 BB_B0 K2
35412 #define PRS_REG_TASK_TYPE_TARGET                                                                     0x1f0188UL //Access:RW   DataWidth:0x4   Connection type used in TCFC load requests for target mode.  Chips: BB_A0 BB_B0 K2
35413 #define PRS_REG_ROCE_CON_TYPE                                                                        0x1f018cUL //Access:RW   DataWidth:0x4   Connection type to be used in RoCE load requests.  Chips: BB_A0 BB_B0 K2
35414 #define PRS_REG_ROCE_SEPARATE_RX_TX_CID_FLG                                                          0x1f0190UL //Access:RW   DataWidth:0x1   Per-PF: If set, override of the CID LSb is enabled for RoCE packets.  Chips: BB_A0 BB_B0 K2
35415 #define PRS_REG_ROCE_OPCODE_REQ_RES                                                                  0x1f0194UL //Access:RW   DataWidth:0x20  Per-opcode requester/responder bit to be used in the CID of RoCE pkts (if enabled in roce_separate_rx_tx_cid_flg).  Chips: BB_A0 BB_B0 K2
35416 #define PRS_REG_LOAD_L2_FILTER                                                                       0x1f0198UL //Access:RW   DataWidth:0x1   Per-PF: If set, a load request is sent for TCP, UDP, and RoCE packets receiving a search response result code of match L2 filter.  Chips: BB_A0 BB_B0 K2
35417 #define PRS_REG_CFC_LOAD_MINI_CACHE_EN                                                               0x1f019cUL //Access:RW   DataWidth:0x1   If set, CFC load mini-cache is enabled.  Chips: BB_A0 BB_B0 K2
35418 #define PRS_REG_TARGET_INITIATOR_SELECT                                                              0x1f01a0UL //Access:RW   DataWidth:0x1   0-search response initiator type,1-Exchange Context  Chips: BB_B0 K2
35419 #define PRS_REG_FCOE_SEARCH_WITH_EXCHANGE_CONTEXT                                                    0x1f01a4UL //Access:RW   DataWidth:0x1   0-Exchange Context field in the fcoe search req is zero. 1-Exchange context field in the FCoE search request is taken from the F_CTL field of the FC header.  Chips: BB_B0 K2
35420 #define PRS_REG_ECO_RESERVED                                                                         0x1f0200UL //Access:RW   DataWidth:0x20  Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
35421 #define PRS_REG_PRTY_MASK_H_0                                                                        0x1f0208UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
35422     #define PRS_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
35423     #define PRS_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_SHIFT                                          0
35424     #define PRS_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
35425     #define PRS_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_SHIFT                                          1
35426     #define PRS_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT                                                (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
35427     #define PRS_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_SHIFT                                          2
35428     #define PRS_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
35429     #define PRS_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_SHIFT                                          3
35430     #define PRS_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT                                                (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
35431     #define PRS_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_SHIFT                                          4
35432     #define PRS_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
35433     #define PRS_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_SHIFT                                          5
35434     #define PRS_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT                                                (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
35435     #define PRS_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_SHIFT                                          6
35436     #define PRS_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT                                                (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM027_I_ECC_RF_INT .
35437     #define PRS_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_SHIFT                                          7
35438     #define PRS_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
35439     #define PRS_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_SHIFT                                            8
35440     #define PRS_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
35441     #define PRS_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_SHIFT                                            9
35442     #define PRS_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
35443     #define PRS_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_SHIFT                                            10
35444     #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
35445     #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_A0_SHIFT                                      4
35446     #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
35447     #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_B0_SHIFT                                      4
35448     #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
35449     #define PRS_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2_SHIFT                                         11
35450     #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_A0                                            (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
35451     #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_A0_SHIFT                                      26
35452     #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_B0                                            (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
35453     #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_B0_SHIFT                                      25
35454     #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
35455     #define PRS_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2_SHIFT                                         12
35456     #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
35457     #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_A0_SHIFT                                      17
35458     #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
35459     #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_B0_SHIFT                                      16
35460     #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
35461     #define PRS_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2_SHIFT                                         13
35462     #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
35463     #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_A0_SHIFT                                      18
35464     #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
35465     #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_B0_SHIFT                                      17
35466     #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
35467     #define PRS_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT                                         14
35468     #define PRS_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
35469     #define PRS_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_SHIFT                                            15
35470     #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0                                            (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
35471     #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0_SHIFT                                      30
35472     #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0                                            (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
35473     #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0_SHIFT                                      29
35474     #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
35475     #define PRS_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                         16
35476     #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0                                            (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
35477     #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0_SHIFT                                      30
35478     #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
35479     #define PRS_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                         17
35480     #define PRS_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
35481     #define PRS_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_SHIFT                                            18
35482     #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_A0                                            (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
35483     #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_A0_SHIFT                                      25
35484     #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_B0                                            (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
35485     #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_B0_SHIFT                                      24
35486     #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
35487     #define PRS_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2_SHIFT                                         19
35488     #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
35489     #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0_SHIFT                                      19
35490     #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0                                            (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
35491     #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0_SHIFT                                      18
35492     #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                               (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
35493     #define PRS_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                         20
35494     #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0                                            (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
35495     #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0_SHIFT                                      29
35496     #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0                                            (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
35497     #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0_SHIFT                                      28
35498     #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                               (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
35499     #define PRS_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                         21
35500     #define PRS_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
35501     #define PRS_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_SHIFT                                            22
35502     #define PRS_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
35503     #define PRS_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_SHIFT                                            23
35504     #define PRS_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
35505     #define PRS_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_SHIFT                                            24
35506     #define PRS_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
35507     #define PRS_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_SHIFT                                            25
35508     #define PRS_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
35509     #define PRS_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_SHIFT                                            26
35510     #define PRS_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
35511     #define PRS_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_SHIFT                                            27
35512     #define PRS_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
35513     #define PRS_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_SHIFT                                            28
35514     #define PRS_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
35515     #define PRS_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_SHIFT                                            29
35516     #define PRS_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
35517     #define PRS_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                            30
35518     #define PRS_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
35519     #define PRS_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_SHIFT                                          0
35520     #define PRS_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
35521     #define PRS_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT                                          1
35522     #define PRS_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT                                                (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
35523     #define PRS_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_SHIFT                                          2
35524     #define PRS_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
35525     #define PRS_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT                                          3
35526     #define PRS_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
35527     #define PRS_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT                                            5
35528     #define PRS_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
35529     #define PRS_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_SHIFT                                            6
35530     #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
35531     #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_A0_SHIFT                                      8
35532     #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
35533     #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_B0_SHIFT                                      7
35534     #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
35535     #define PRS_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                         7
35536     #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
35537     #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                      9
35538     #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
35539     #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      8
35540     #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                               (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
35541     #define PRS_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                         8
35542     #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
35543     #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      10
35544     #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
35545     #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      9
35546     #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
35547     #define PRS_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                         9
35548     #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
35549     #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      11
35550     #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
35551     #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      10
35552     #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
35553     #define PRS_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                         10
35554     #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
35555     #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                      12
35556     #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
35557     #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                      11
35558     #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
35559     #define PRS_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                         11
35560     #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
35561     #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0_SHIFT                                      13
35562     #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
35563     #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0_SHIFT                                      12
35564     #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
35565     #define PRS_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                         12
35566     #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
35567     #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                      14
35568     #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
35569     #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                      13
35570     #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
35571     #define PRS_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                         13
35572     #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_A0                                            (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
35573     #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_A0_SHIFT                                      15
35574     #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
35575     #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_B0_SHIFT                                      14
35576     #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
35577     #define PRS_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                         14
35578     #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
35579     #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_A0_SHIFT                                      16
35580     #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
35581     #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_B0_SHIFT                                      15
35582     #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
35583     #define PRS_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                         15
35584     #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
35585     #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                      20
35586     #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0                                            (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
35587     #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                      19
35588     #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
35589     #define PRS_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                         19
35590     #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0                                            (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
35591     #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0_SHIFT                                      21
35592     #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0                                            (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
35593     #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0_SHIFT                                      20
35594     #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                               (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
35595     #define PRS_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                         20
35596     #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0                                            (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
35597     #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0_SHIFT                                      22
35598     #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0                                            (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
35599     #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0_SHIFT                                      21
35600     #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                               (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
35601     #define PRS_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                         21
35602     #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                            (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
35603     #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                      23
35604     #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                            (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
35605     #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                      22
35606     #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                               (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
35607     #define PRS_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                         22
35608     #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
35609     #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                      24
35610     #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                            (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
35611     #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                      23
35612     #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                               (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
35613     #define PRS_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                         23
35614     #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0                                            (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
35615     #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0_SHIFT                                      27
35616     #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0                                            (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
35617     #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0_SHIFT                                      26
35618     #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                               (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
35619     #define PRS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                         26
35620     #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0                                            (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
35621     #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0_SHIFT                                      28
35622     #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0                                            (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
35623     #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0_SHIFT                                      27
35624     #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                               (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
35625     #define PRS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                         27
35626     #define PRS_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
35627     #define PRS_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_SHIFT                                            7
35628 #define PRS_REG_PRTY_MASK_H_1                                                                        0x1f0218UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
35629     #define PRS_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
35630     #define PRS_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_SHIFT                                            0
35631     #define PRS_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
35632     #define PRS_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_SHIFT                                            1
35633     #define PRS_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
35634     #define PRS_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_SHIFT                                            2
35635     #define PRS_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
35636     #define PRS_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_SHIFT                                            3
35637     #define PRS_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
35638     #define PRS_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_SHIFT                                            4
35639     #define PRS_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
35640     #define PRS_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_SHIFT                                            5
35641     #define PRS_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
35642     #define PRS_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_SHIFT                                            6
35643     #define PRS_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
35644     #define PRS_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_SHIFT                                            7
35645     #define PRS_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
35646     #define PRS_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_SHIFT                                            8
35647     #define PRS_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
35648     #define PRS_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_SHIFT                                            9
35649     #define PRS_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
35650     #define PRS_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_SHIFT                                            10
35651     #define PRS_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
35652     #define PRS_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_SHIFT                                            11
35653     #define PRS_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
35654     #define PRS_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_SHIFT                                            12
35655     #define PRS_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
35656     #define PRS_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_SHIFT                                            13
35657     #define PRS_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
35658     #define PRS_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_SHIFT                                            14
35659     #define PRS_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
35660     #define PRS_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_SHIFT                                            15
35661     #define PRS_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
35662     #define PRS_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_SHIFT                                            16
35663     #define PRS_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
35664     #define PRS_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_SHIFT                                            17
35665     #define PRS_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
35666     #define PRS_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_SHIFT                                            18
35667     #define PRS_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
35668     #define PRS_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_SHIFT                                            19
35669     #define PRS_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
35670     #define PRS_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_SHIFT                                            20
35671     #define PRS_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
35672     #define PRS_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_SHIFT                                            21
35673     #define PRS_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
35674     #define PRS_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_SHIFT                                            22
35675     #define PRS_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
35676     #define PRS_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_SHIFT                                            23
35677     #define PRS_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
35678     #define PRS_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_SHIFT                                            24
35679     #define PRS_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
35680     #define PRS_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_SHIFT                                            25
35681     #define PRS_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
35682     #define PRS_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_SHIFT                                            26
35683     #define PRS_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
35684     #define PRS_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_SHIFT                                            27
35685     #define PRS_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
35686     #define PRS_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_SHIFT                                            28
35687     #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
35688     #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                      3
35689     #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
35690     #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                      3
35691     #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                               (0x1<<29) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
35692     #define PRS_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                         29
35693     #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
35694     #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_A0_SHIFT                                      4
35695     #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
35696     #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                      4
35697     #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                               (0x1<<30) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
35698     #define PRS_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                         30
35699     #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_A0                                            (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
35700     #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_A0_SHIFT                                      1
35701     #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_B0                                            (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
35702     #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_B0_SHIFT                                      0
35703     #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_K2                                               (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
35704     #define PRS_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_K2_SHIFT                                         0
35705     #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_A0                                            (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
35706     #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_A0_SHIFT                                      2
35707     #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
35708     #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_B0_SHIFT                                      1
35709     #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
35710     #define PRS_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2_SHIFT                                         1
35711     #define PRS_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
35712     #define PRS_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_SHIFT                                            2
35713     #define PRS_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: PRS_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
35714     #define PRS_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_SHIFT                                            0
35715 #define PRS_REG_MEM_ECC_EVENTS                                                                       0x1f0230UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
35716 #define PRS_REG_MEM064_I_MEM_DFT_K2                                                                  0x1f023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_prsu.i_prs_prsu_hdr_fifo.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35717 #define PRS_REG_MEM063_I_ESILICON_TCAM_DFT_K2                                                        0x1f0240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_prsu.i_prs_prmsg.i_prs_gft.i_prs_gft_cam_wrapper.i_esilicon_tcam of module ts_28hpc_tcam_111_hs_e_t_shlas_32x14_pbn_bist_wr. [2]=rme, [1:0]=t_strw.  Chips: K2
35718 #define PRS_REG_MEM044_I_MEM_DFT_K2                                                                  0x1f0244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_cfcu.i_prs_cfcu_search_req_fifo.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35719 #define PRS_REG_MEM043_I_MEM_DFT_K2                                                                  0x1f0248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_cfcu.i_prs_cfcu_ccfc_search_resp_fifo.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35720 #define PRS_REG_MEM033_I_MEM_DFT_K2                                                                  0x1f024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_brbu.i_eopreq_fifo_0.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35721 #define PRS_REG_MEM034_I_MEM_DFT_K2                                                                  0x1f0250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_brbu.i_eopreq_fifo_1.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35722 #define PRS_REG_MEM035_I_MEM_DFT_K2                                                                  0x1f0254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_brbu.i_eopreq_fifo_2.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35723 #define PRS_REG_MEM036_I_MEM_DFT_K2                                                                  0x1f0258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_brbu.i_eopreq_fifo_3.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35724 #define PRS_REG_MEM038_I_ESILICON_TCAM_H_DFT_K2                                                      0x1f025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_cam.i_cam.i_esilicon_tcam_h of module ts_28hpc_tcam_111_hs_e_t_shlas_64x74_pbn_bist_wr. [2]=rme, [1:0]=t_strw.  Chips: K2
35725 #define PRS_REG_MEM039_I_MEM_DFT_K2                                                                  0x1f0260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_ccfc_ldresp_fifo_0.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35726 #define PRS_REG_MEM040_I_MEM_DFT_K2                                                                  0x1f0264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_ccfc_ldresp_fifo_1.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35727 #define PRS_REG_MEM058_I_MEM_DFT_K2                                                                  0x1f0268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_msgb_tcfc_ldresp_fifo_0.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35728 #define PRS_REG_MEM059_I_MEM_DFT_K2                                                                  0x1f026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_msgb_tcfc_ldresp_fifo_1.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35729 #define PRS_REG_MEM041_I_MEM_DFT_K2                                                                  0x1f0270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_ccfc_ldresp_fifo_2.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35730 #define PRS_REG_MEM042_I_MEM_DFT_K2                                                                  0x1f0274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_ccfc_ldresp_fifo_3.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35731 #define PRS_REG_MEM060_I_MEM_DFT_K2                                                                  0x1f0278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_msgb_tcfc_ldresp_fifo_2.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35732 #define PRS_REG_MEM061_I_MEM_DFT_K2                                                                  0x1f027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_msgb_tcfc_ldresp_fifo_3.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35733 #define PRS_REG_MEM011_I_MEM_DFT_K2                                                                  0x1f0280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if0_main_fifoa.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35734 #define PRS_REG_MEM012_I_MEM_DFT_K2                                                                  0x1f0284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if0_main_fifob.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35735 #define PRS_REG_MEM016_I_MEM_DFT_K2                                                                  0x1f0288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if1_main_fifoa.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35736 #define PRS_REG_MEM017_I_MEM_DFT_K2                                                                  0x1f028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if1_main_fifob.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35737 #define PRS_REG_MEM021_I_MEM_DFT_K2                                                                  0x1f0290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if2_main_fifoa.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35738 #define PRS_REG_MEM022_I_MEM_DFT_K2                                                                  0x1f0294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if2_main_fifob.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35739 #define PRS_REG_MEM026_I_MEM_DFT_K2                                                                  0x1f0298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if3_main_fifoa.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35740 #define PRS_REG_MEM027_I_MEM_DFT_K2                                                                  0x1f029cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if3_main_fifob.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35741 #define PRS_REG_MEM009_I_MEM_DFT_K2                                                                  0x1f02a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if0_local_hdr_fifoa.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35742 #define PRS_REG_MEM010_I_MEM_DFT_K2                                                                  0x1f02a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if0_local_hdr_fifob.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35743 #define PRS_REG_MEM014_I_MEM_DFT_K2                                                                  0x1f02a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if1_local_hdr_fifoa.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35744 #define PRS_REG_MEM015_I_MEM_DFT_K2                                                                  0x1f02acUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if1_local_hdr_fifob.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35745 #define PRS_REG_MEM019_I_MEM_DFT_K2                                                                  0x1f02b0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if2_local_hdr_fifoa.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35746 #define PRS_REG_MEM020_I_MEM_DFT_K2                                                                  0x1f02b4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if2_local_hdr_fifob.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35747 #define PRS_REG_MEM024_I_MEM_DFT_K2                                                                  0x1f02b8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if3_local_hdr_fifoa.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35748 #define PRS_REG_MEM025_I_MEM_DFT_K2                                                                  0x1f02bcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if3_local_hdr_fifob.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35749 #define PRS_REG_MEM008_I_MEM_DFT_K2                                                                  0x1f02c0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if0_eop_desc.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35750 #define PRS_REG_MEM013_I_MEM_DFT_K2                                                                  0x1f02c4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if1_eop_desc.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35751 #define PRS_REG_MEM018_I_MEM_DFT_K2                                                                  0x1f02c8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if2_eop_desc.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35752 #define PRS_REG_MEM023_I_MEM_DFT_K2                                                                  0x1f02ccUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_msgb_if3_eop_desc.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35753 #define PRS_REG_MEM054_I_MEM_DFT_K2                                                                  0x1f02d0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_msgb_search_resp_fifo_0.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35754 #define PRS_REG_MEM055_I_MEM_DFT                                                                     0x1f02d4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_msgb_search_resp_fifo_1.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35755 #define PRS_REG_MEM056_I_MEM_DFT                                                                     0x1f02d8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_msgb_search_resp_fifo_2.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35756 #define PRS_REG_MEM057_I_MEM_DFT                                                                     0x1f02dcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_msgb_search_resp_fifo_3.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35757 #define PRS_REG_MEM003_I_MEM_DFT                                                                     0x1f02e0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_iarb_if0_credit_adj.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35758 #define PRS_REG_MEM004_I_MEM_DFT                                                                     0x1f02e4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_iarb_if1_credit_adj.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35759 #define PRS_REG_MEM005_I_MEM_DFT                                                                     0x1f02e8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_iarb_if2_credit_adj.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35760 #define PRS_REG_MEM006_I_MEM_DFT                                                                     0x1f02ecUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_iarb_if3_credit_adj.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35761 #define PRS_REG_MEM062_I_MEM_DFT                                                                     0x1f02f0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_pkt_list_fifo.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35762 #define PRS_REG_MEM045_I_MEM_DFT                                                                     0x1f02f4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prs.i_prs_gft_profile_mask_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
35763 #define PRS_REG_SEARCH_TCP                                                                           0x1f0400UL //Access:RW   DataWidth:0x1   Per-PF: Flag enabling searches for tcp protocol.  Chips: BB_A0 BB_B0 K2
35764 #define PRS_REG_SEARCH_UDP                                                                           0x1f0404UL //Access:RW   DataWidth:0x1   Per-PF: Flag enabling searches for udp protocol.  Chips: BB_A0 BB_B0 K2
35765 #define PRS_REG_SEARCH_FCOE                                                                          0x1f0408UL //Access:RW   DataWidth:0x1   Per-PF: Flag enabling searches for fcoe protocol.  Chips: BB_A0 BB_B0 K2
35766 #define PRS_REG_SEARCH_ROCE                                                                          0x1f040cUL //Access:RW   DataWidth:0x1   Per-PF: Flag enabling searches for roce protocol.  Chips: BB_A0 BB_B0 K2
35767 #define PRS_REG_SEARCH_TCP_FIRST_FRAG                                                                0x1f0410UL //Access:RW   DataWidth:0x1   Enables sending messages to CFC on received first TCP fragmented packets.  Chips: BB_A0 BB_B0 K2
35768 #define PRS_REG_TCP_SEARCH_KEY_MASK                                                                  0x1f0414UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35769     #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4                                         (0x1<<0) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the TCP search request.
35770     #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4_SHIFT                                   0
35771     #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6                                         (0x1<<1) // If this bit is 0, the dest_ip_address_ipv6 field will be masked in the TCP search request.
35772     #define PRS_REG_TCP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6_SHIFT                                   1
35773     #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4                                       (0x1<<2) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the TCP search request.
35774     #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4_SHIFT                                 2
35775     #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6                                       (0x1<<3) // If this bit is 0, the source_ip_address_ipv6 field will be masked in the TCP search request.
35776     #define PRS_REG_TCP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6_SHIFT                                 3
35777     #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_DEST_PORT                                                (0x1<<4) // If this bit is 0, the tcp_dest_port field will be masked in the TCP search request.
35778     #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_DEST_PORT_SHIFT                                          4
35779     #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_SOURCE_PORT                                              (0x1<<5) // If this bit is 0, the tcp_source_port field will be masked in the TCP search request.
35780     #define PRS_REG_TCP_SEARCH_KEY_MASK_TCP_SOURCE_PORT_SHIFT                                        5
35781     #define PRS_REG_TCP_SEARCH_KEY_MASK_IP_VERSION                                                   (0x1<<6) // If this bit is 0, the ip_version field will be masked in the TCP search request.
35782     #define PRS_REG_TCP_SEARCH_KEY_MASK_IP_VERSION_SHIFT                                             6
35783 #define PRS_REG_UDP_SEARCH_KEY_MASK                                                                  0x1f0418UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
35784     #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4                                         (0x1<<0) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the UDP search request.
35785     #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4_SHIFT                                   0
35786     #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6                                         (0x1<<1) // If this bit is 0, the dest_ip_address_ipv6 field will be masked in the UDP search request.
35787     #define PRS_REG_UDP_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV6_SHIFT                                   1
35788     #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4                                       (0x1<<2) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the UDP search request.
35789     #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4_SHIFT                                 2
35790     #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6                                       (0x1<<3) // If this bit is 0, the source_ip_address_ipv6 field will be masked in the UDP search request.
35791     #define PRS_REG_UDP_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV6_SHIFT                                 3
35792     #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_DEST_PORT                                                (0x1<<4) // If this bit is 0, the udp_dest_port field will be masked in the UDP search request.
35793     #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_DEST_PORT_SHIFT                                          4
35794     #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_SOURCE_PORT                                              (0x1<<5) // If this bit is 0, the udp_source_port field will be masked in the UDP search request.
35795     #define PRS_REG_UDP_SEARCH_KEY_MASK_UDP_SOURCE_PORT_SHIFT                                        5
35796     #define PRS_REG_UDP_SEARCH_KEY_MASK_IP_VERSION                                                   (0x1<<6) // If this bit is 0, the ip_version field will be masked in the UDP search request.
35797     #define PRS_REG_UDP_SEARCH_KEY_MASK_IP_VERSION_SHIFT                                             6
35798 #define PRS_REG_SEARCH_FCOE_W_SRC_MAC                                                                0x1f041cUL //Access:RW   DataWidth:0x1   Per-PF: If set, search requests on FCoE packets are only sent if source MAC address compare matches.  Chips: BB_A0 BB_B0 K2
35799 #define PRS_REG_SEARCH_FCOE_W_VFT                                                                    0x1f0420UL //Access:RW   DataWidth:0x1   Per-PF: Enables VF_ID (if it exists) to be sent in search requests for FCoE packets.  Chips: BB_A0 BB_B0 K2
35800 #define PRS_REG_ROCE_BUILD_CID_WO_SEARCH                                                             0x1f0424UL //Access:RW   DataWidth:0x1   Per-PF: Enables load request for RoCE pkts to be sent even though a search request was not sent  Chips: BB_A0 BB_B0 K2
35801 #define PRS_REG_ROCE_SPCL_QP_VAL                                                                     0x1f0428UL //Access:RW   DataWidth:0x18  Search is enabled if destination QP equals this value.  Chips: BB_A0 BB_B0 K2
35802 #define PRS_REG_ROCE_DEST_QP_MAX_VF                                                                  0x1f042cUL //Access:RW   DataWidth:0x10  Per-PF: Max value for temp_qpid used in RoCE CID equation for VF pkts.  Chips: BB_A0 BB_B0 K2
35803 #define PRS_REG_ROCE_DEST_QP_MAX_PF                                                                  0x1f0430UL //Access:RW   DataWidth:0x10  Per-PF: Max value for temp_qpid used in RoCE CID equation for PF pkts.  Chips: BB_A0 BB_B0 K2
35804 #define PRS_REG_SEARCH_OPENFLOW                                                                      0x1f0434UL //Access:RW   DataWidth:0x1   Per-PF: Enables openflow search for all packet types.  Chips: BB_A0 BB_B0 K2
35805 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW                                                            0x1f0438UL //Access:RW   DataWidth:0x1   Per-PF: Enables openflow search for non-IP packets. Only valid if search_openflow is also set.  Chips: BB_A0 BB_B0 K2
35806 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP                                                  0x1f043cUL //Access:RW   DataWidth:0x1   Per-PF: If this field is 1, Over-IPv4-protocol field of Openflow search is only valid for SCTP, TCP, and UDP headers.  Chips: BB_A0 BB_B0 K2
35807 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK                                                             0x1f0440UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
35808     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_SOURCE_PORT                                         (0x1<<0) // If this bit is 0, the tcp_source_port field will be masked in the Openflow search request.
35809     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_SOURCE_PORT_SHIFT                                   0
35810     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_SOURCE_PORT                                         (0x1<<1) // If this bit is 0, the udp_source_port field will be masked in the Openflow search request.
35811     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_SOURCE_PORT_SHIFT                                   1
35812     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_SOURCE_PORT                                        (0x1<<2) // If this bit is 0, the sctp_source_port field will be masked in the Openflow search request.
35813     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_SOURCE_PORT_SHIFT                                  2
35814     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_TYPE                                               (0x1<<3) // If this bit is 0, the icmp_type field will be masked in the Openflow search request.
35815     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_TYPE_SHIFT                                         3
35816     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_DEST_PORT                                           (0x1<<4) // If this bit is 0, the tcp_dest_port field will be masked in the Openflow search request.
35817     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_TCP_DEST_PORT_SHIFT                                     4
35818     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_DEST_PORT                                           (0x1<<5) // If this bit is 0, the udp_dest_port field will be masked in the Openflow search request.
35819     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_UDP_DEST_PORT_SHIFT                                     5
35820     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_DEST_PORT                                          (0x1<<6) // If this bit is 0, the sctp_dest_port field will be masked in the Openflow search request.
35821     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SCTP_DEST_PORT_SHIFT                                    6
35822     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_CODE                                               (0x1<<7) // If this bit is 0, the icmp_code field will be masked in the Openflow search request.
35823     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ICMP_CODE_SHIFT                                         7
35824     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_PRIORITY                                                (0x1<<8) // If this bit is 0, the priority field will be masked in the Openflow search request.
35825     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_PRIORITY_SHIFT                                          8
35826     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_FRAG_TYPE                                          (0x1<<9) // If this bit is 0, the ipv4_frag_type field will be masked in the Openflow search request.
35827     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_FRAG_TYPE_SHIFT                                    9
35828     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_MAC_ADDRESS                                        (0x1<<10) // If this bit is 0, the dest_mac_address field will be masked in the Openflow search request.
35829     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_MAC_ADDRESS_SHIFT                                  10
35830     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_OVER_IPV4_PROTOCOL                                      (0x1<<11) // If this bit is 0, the over_ipv4_protocol field will be masked in the Openflow search request.
35831     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_OVER_IPV4_PROTOCOL_SHIFT                                11
35832     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ARP_OPCODE                                              (0x1<<12) // If this bit is 0, the arp_opcode field will be masked in the Openflow search request.
35833     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ARP_OPCODE_SHIFT                                        12
35834     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_DSCP                                               (0x1<<13) // If this bit is 0, the ipv4_dscp field will be masked in the Openflow search request.
35835     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_IPV4_DSCP_SHIFT                                         13
35836     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_MAC_ADDRESS                                      (0x1<<14) // If this bit is 0, the source_mac_address field will be masked in the Openflow search request.
35837     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_MAC_ADDRESS_SHIFT                                14
35838     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4                                  (0x1<<15) // If this bit is 0, the source_ip_address_ipv4 field will be masked in the Openflow search request.
35839     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_IPV4_SHIFT                            15
35840     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_ARP                                   (0x1<<16) // If this bit is 0, the source_ip_address_arp field will be masked in the Openflow search request.
35841     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_SOURCE_IP_ADDRESS_ARP_SHIFT                             16
35842     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4                                    (0x1<<17) // If this bit is 0, the dest_ip_address_ipv4 field will be masked in the Openflow search request.
35843     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_IPV4_SHIFT                              17
35844     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_ARP                                     (0x1<<18) // If this bit is 0, the dest_ip_address_arp field will be masked in the Openflow search request.
35845     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_DEST_IP_ADDRESS_ARP_SHIFT                               18
35846     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ETHERTYPE                                               (0x1<<19) // If this bit is 0, the ethertype field will be masked in the Openflow search request.
35847     #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_ETHERTYPE_SHIFT                                         19
35848 #define PRS_REG_SEARCH_TAG1                                                                          0x1f0444UL //Access:RW   DataWidth:0x5   Per-PF: Indicates whether to include the Inner VLAN in the search for each protocol. 0 - TCP, 1 - UDP, 2 - FCoE, 3 - RoCE, 4 - Openflow- if a bit is set in search_outer_tag it cannot be set here.  Chips: BB_A0 BB_B0 K2
35849 #define PRS_REG_SEARCH_OUTER_TAG                                                                     0x1f0448UL //Access:RW   DataWidth:0x5   Per-PF: Indicates whether to include the Outer TAG in the search for each protocol. 0 - TCP, 1 - UDP, 2 - FCoE, 3 - RoCE, 4 - Openflow - if a bit is set in search_tag1 it cannot be set here.  Chips: BB_A0 BB_B0 K2
35850 #define PRS_REG_SEARCH_TENANT_ID                                                                     0x1f044cUL //Access:RW   DataWidth:0x6   Per-PF: Indicates whether to include Tenant ID (if it exists) in the search for each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE  Chips: BB_A0 BB_B0 K2
35851 #define PRS_REG_TENANT_ID_DEFAULT_VAL_ENABLE                                                         0x1f0450UL //Access:RW   DataWidth:0x6   Enables Tenant ID Exists bit in the search request to be 0 if the ID matches the default value.  0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE  Chips: BB_A0 BB_B0 K2
35852 #define PRS_REG_TENANT_ID_MASK_ETH_GRE                                                               0x1f0454UL //Access:RW   DataWidth:0x20  Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated Ethernet over GRE packet. A zero in this register will mask the corresponding tenant ID bit to 0.  Chips: BB_A0 BB_B0 K2
35853 #define PRS_REG_TENANT_ID_MASK_IP_GRE                                                                0x1f0458UL //Access:RW   DataWidth:0x20  Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated IP over GRE packet.. A zero in this register will mask the corresponding tenant ID bit to 0.  Chips: BB_A0 BB_B0 K2
35854 #define PRS_REG_TENANT_ID_MASK_VXLAN                                                                 0x1f045cUL //Access:RW   DataWidth:0x20  Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated VXLAN packet.. A zero in this register will mask the corresponding tenant ID bit to 0.  Chips: BB_A0 BB_B0 K2
35855 #define PRS_REG_TENANT_ID_MASK_TTAG                                                                  0x1f0460UL //Access:RW   DataWidth:0x20  Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated T-tag packet.. A zero in this register will mask the corresponding tenant ID bit to 0.  Chips: BB_A0 BB_B0 K2
35856 #define PRS_REG_TENANT_ID_DEFAULT_VAL_ETH_GRE                                                        0x1f0464UL //Access:RW   DataWidth:0x20  If the Tenant ID exists in the encapsulated Ethernet over GRE packet  and does not match this value the Tenant ID exists bit is set.  Chips: BB_A0 BB_B0 K2
35857 #define PRS_REG_TENANT_ID_DEFAULT_VAL_IP_GRE                                                         0x1f0468UL //Access:RW   DataWidth:0x20  If the Tenant ID exists in the encapsulated IP over GRE packet  and does not match this value the Tenant ID exists bit is set.  Chips: BB_A0 BB_B0 K2
35858 #define PRS_REG_TENANT_ID_DEFAULT_VAL_VXLAN                                                          0x1f046cUL //Access:RW   DataWidth:0x20  If the Tenant ID exists in the encapsulated VXLAN packet and does not match this value the Tenant ID exists bit is set.  Chips: BB_A0 BB_B0 K2
35859 #define PRS_REG_TENANT_ID_DEFAULT_VAL_TTAG                                                           0x1f0470UL //Access:RW   DataWidth:0x20  If the Tenant ID exists in the encapsulated T-Tag packet and does not match this value the Tenant ID exists bit is set.  Chips: BB_A0 BB_B0 K2
35860 #define PRS_REG_T_TAG_TAGNUM                                                                         0x1f0474UL //Access:RW   DataWidth:0x3   Per-Port: Specifies the flexible L2 tag to be used for T-tag. The T-tag bit of encapsulation_type_en enables T-tag recognition.  Chips: BB_A0 BB_B0 K2
35861 #define PRS_REG_TENANT_ID_MASK_ETH_NGE                                                               0x1f0478UL //Access:RW   DataWidth:0x20  Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated nge packet.. A zero in this register will mask the corresponding tenant ID bit to 0.  Chips: BB_B0 K2
35862 #define PRS_REG_TENANT_ID_MASK_IP_NGE                                                                0x1f047cUL //Access:RW   DataWidth:0x20  Bit masks Tenant ID used in the search request if Tenant ID exists in the encapsulated nge packet.. A zero in this register will mask the corresponding tenant ID bit to 0.  Chips: BB_B0 K2
35863 #define PRS_REG_TENANT_ID_DEFAULT_VAL_ETH_NGE                                                        0x1f0480UL //Access:RW   DataWidth:0x20  If the Tenant ID exists in the encapsulated ETH NGE packet and does not match this value the Tenant ID exists bit is set.  Chips: BB_B0 K2
35864 #define PRS_REG_TENANT_ID_DEFAULT_VAL_IP_NGE                                                         0x1f0484UL //Access:RW   DataWidth:0x20  If the Tenant ID exists in the encapsulated IP NGE packet and does not match this value the Tenant ID exists bit is set.  Chips: BB_B0 K2
35865 #define PRS_REG_PORTS_ARB_SCHEME                                                                     0x1f0500UL //Access:RW   DataWidth:0x1   MAC port arbitration guarantees fairness at byte-level (0) or packet-level (1).  Chips: BB_A0 BB_B0 K2
35866 #define PRS_REG_MAIN_LB_ARB_SCHEME                                                                   0x1f0504UL //Access:RW   DataWidth:0x1   Main/LB arbitration guarantees fairness at byte-level (0) or packet-level (1).  Chips: BB_A0 BB_B0 K2
35867 #define PRS_REG_INITIAL_HEADER_SIZE                                                                  0x1f0508UL //Access:RW   DataWidth:0xa   Initial header size to read from the BRB for received packets.  Chips: BB_A0 BB_B0 K2
35868 #define PRS_REG_MAX_PACKET_SIZE                                                                      0x1f050cUL //Access:RW   DataWidth:0xe   Maximum packet size used for ETS Arbiter fairness calculation.  Chips: BB_A0 BB_B0 K2
35869 #define PRS_REG_ETS_PACKET_ADDITIONAL_NETWORK_SIZE                                                   0x1f0510UL //Access:RW   DataWidth:0x8   Size of inter-packet gap and FCS used for ETS Arbiter fairness calculation.  Chips: BB_A0 BB_B0 K2
35870 #define PRS_REG_ETS_ARB_CLIENT_IS_STRICT                                                             0x1f0514UL //Access:RW   DataWidth:0x9   Specify whether the client competes directly in the strict priority arbiter.  The bits are mapped according to client ID  (client IDs are defined in *_arb_priority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 traffic; 6-TC6 traffic; 7-TC7 traffic; 8-TC8 traffic.  Default value is set to enable strict priorities for all clients.  Chips: BB_A0 BB_B0 K2
35871 #define PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ                                                        0x1f0518UL //Access:RW   DataWidth:0x9   Specify whether the client is subject to WFQ credit blocking.  The bits are mapped according to client ID (client IDs are defined in *_arb_priority_client): 0-TC0 traffic; 1-TC1 traffic; 2-TC2 traffic; 3-TC3 traffic; 4-TC4 traffic; 5-TC5 traffic; 6-TC6 traffic; 7-TC7 traffic; 8-TC8 traffic.  Default value is 0 for not using WFQ credit blocking.  Chips: BB_A0 BB_B0 K2
35872 #define PRS_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS                                                         0x1f051cUL //Access:RW   DataWidth:0xc   Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation.  A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter.  Chips: BB_A0 BB_B0 K2
35873 #define PRS_REG_ETS_ARB_PRIORITY_CLIENT_0                                                            0x1f0520UL //Access:RW   DataWidth:0x20  Specify the client number to be assigned to each priority of the strict priority arbiter.  Priority 0 is the highest priority.  Bits [3:0] are for priority 0 client; upper bits are for priority 8 client.  The clients are assigned the IDs corresponding to their TC # (0-8)  Chips: BB_A0 BB_B0 K2
35874 #define PRS_REG_ETS_ARB_PRIORITY_CLIENT_1                                                            0x1f0524UL //Access:RW   DataWidth:0x4   Specify the client number to be assigned to each priority of the strict priority arbiter.  Priority 0 is the highest priority.  Bits [3:0] are for priority 0 client; upper bits are for priority 8 client.  The clients are assigned the IDs corresponding to their TC # (0-8)  Chips: BB_A0 BB_B0 K2
35875 #define PRS_REG_ETS_ARB_CLIENT_BURSTMODE                                                             0x1f0528UL //Access:RW   DataWidth:0x2   Burst mode enables.  Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the next one.  Bit 0 is for the main round-robin arbiter.  Bit 1 is for the round-robin arbiter within the strict priority with anti-starvation feature.  Chips: BB_A0 BB_B0 K2
35876 #define PRS_REG_ETS_ARB_PSEUDO_RR_EN                                                                 0x1f052cUL //Access:RW   DataWidth:0x1   Enables pseudo-random round robin arbitration.  Chips: BB_A0 BB_B0 K2
35877 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0                                                         0x1f0530UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 0 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35878 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_0                                                              0x1f0534UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 0 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35879 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_0                                                             0x1f0538UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 0.  Chips: BB_A0 BB_B0 K2
35880 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1                                                         0x1f053cUL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 1 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35881 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_1                                                              0x1f0540UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 1 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35882 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_1                                                             0x1f0544UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 1.  Chips: BB_A0 BB_B0 K2
35883 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_2                                                         0x1f0548UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 2 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35884 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_2                                                              0x1f054cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 2 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35885 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_2                                                             0x1f0550UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 2.  Chips: BB_A0 BB_B0 K2
35886 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_3                                                         0x1f0554UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 3 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35887 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_3                                                              0x1f0558UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 3 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35888 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_3                                                             0x1f055cUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 3.  Chips: BB_A0 BB_B0 K2
35889 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_4                                                         0x1f0560UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 4 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35890 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_4                                                              0x1f0564UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 4 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35891 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_4                                                             0x1f0568UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 4.  Chips: BB_A0 BB_B0 K2
35892 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_5                                                         0x1f056cUL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 5 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35893 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_5                                                              0x1f0570UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 5 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35894 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_5                                                             0x1f0574UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 5.  Chips: BB_A0 BB_B0 K2
35895 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_6                                                         0x1f0578UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 6 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35896 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_6                                                              0x1f057cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 6 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35897 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_6                                                             0x1f0580UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 6.  Chips: BB_A0 BB_B0 K2
35898 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_7                                                         0x1f0584UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 7 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35899 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_7                                                              0x1f0588UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 7 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35900 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_7                                                             0x1f058cUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 7.  Chips: BB_A0 BB_B0 K2
35901 #define PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_8                                                         0x1f0590UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 8 is allowed to reach.  Chips: BB_A0 BB_B0 K2
35902 #define PRS_REG_ETS_ARB_CREDIT_WEIGHT_8                                                              0x1f0594UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 8 when it is time to increment.  Chips: BB_A0 BB_B0 K2
35903 #define PRS_REG_ETS_ARB_CURRENT_CREDIT_8                                                             0x1f0598UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 8.  Chips: BB_A0 BB_B0 K2
35904 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_0                                                    0x1f059cUL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for main traffic on TC 0 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35905 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_0                                                         0x1f05a0UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for main traffic on TC 0 when it is time to increment during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35906 #define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_0                                                        0x1f05a4UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 0 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35907 #define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_0                                                      0x1f05a8UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 0 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35908 #define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_0                                                           0x1f05acUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 0 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35909 #define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_0                                                          0x1f05b0UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 0 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35910 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_1                                                    0x1f05b4UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for main traffic on TC 1 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35911 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_1                                                         0x1f05b8UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for main traffic on TC 1 when it is time to increment during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35912 #define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_1                                                        0x1f05bcUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 1 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35913 #define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_1                                                      0x1f05c0UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 1 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35914 #define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_1                                                           0x1f05c4UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 1 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35915 #define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_1                                                          0x1f05c8UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 1 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35916 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_2                                                    0x1f05ccUL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for main traffic on TC 2 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35917 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_2                                                         0x1f05d0UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for main traffic on TC 2 when it is time to increment during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35918 #define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_2                                                        0x1f05d4UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 2 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35919 #define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_2                                                      0x1f05d8UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 2 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35920 #define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_2                                                           0x1f05dcUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 2 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35921 #define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_2                                                          0x1f05e0UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 2 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35922 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_3                                                    0x1f05e4UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for main traffic on TC 3 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35923 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_3                                                         0x1f05e8UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for main traffic on TC 3 when it is time to increment during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35924 #define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_3                                                        0x1f05ecUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 3 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35925 #define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_3                                                      0x1f05f0UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 3 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35926 #define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_3                                                           0x1f05f4UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 3 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35927 #define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_3                                                          0x1f05f8UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 3 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35928 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_4                                                    0x1f05fcUL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for main traffic on TC 4 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35929 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_4                                                         0x1f0600UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for main traffic on TC 4 when it is time to increment during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35930 #define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_4                                                        0x1f0604UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 4 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35931 #define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_4                                                      0x1f0608UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 4 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35932 #define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_4                                                           0x1f060cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 4 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35933 #define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_4                                                          0x1f0610UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 4 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35934 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_5                                                    0x1f0614UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for main traffic on TC 5 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35935 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_5                                                         0x1f0618UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for main traffic on TC 5 when it is time to increment during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35936 #define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_5                                                        0x1f061cUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 5 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35937 #define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_5                                                      0x1f0620UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 5 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35938 #define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_5                                                           0x1f0624UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 5 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35939 #define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_5                                                          0x1f0628UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 5 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35940 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_6                                                    0x1f062cUL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for main traffic on TC 6 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35941 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_6                                                         0x1f0630UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for main traffic on TC 6 when it is time to increment during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35942 #define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_6                                                        0x1f0634UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 6 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35943 #define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_6                                                      0x1f0638UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 6 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35944 #define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_6                                                           0x1f063cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 6 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35945 #define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_6                                                          0x1f0640UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 6 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35946 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_UPPER_BOUND_7                                                    0x1f0644UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for main traffic on TC 7 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35947 #define PRS_REG_WFQ_MAIN_ARB_CREDIT_WEIGHT_7                                                         0x1f0648UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for main traffic on TC 7 when it is time to increment during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35948 #define PRS_REG_WFQ_MAIN_ARB_CURRENT_CREDIT_7                                                        0x1f064cUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for main traffic on TC 7 during WFQ Main/Loopback arbitration.  Chips: BB_A0 BB_B0 K2
35949 #define PRS_REG_WFQ_LB_ARB_CREDIT_UPPER_BOUND_7                                                      0x1f0650UL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for loopback traffic on TC 7 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35950 #define PRS_REG_WFQ_LB_ARB_CREDIT_WEIGHT_7                                                           0x1f0654UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for loopback traffic on TC 7 when it is time to increment during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35951 #define PRS_REG_WFQ_LB_ARB_CURRENT_CREDIT_7                                                          0x1f0658UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register for loopback traffic on TC 7 during WFQ Main/Loopback arbitration. Note: TC 8 arbitration is not required for this stage  Chips: BB_A0 BB_B0 K2
35952 #define PRS_REG_WFQ_PORT_ARB_CREDIT_UPPER_BOUND                                                      0x1f065cUL //Access:RW   DataWidth:0x20  Specify the upper bound that the credit register is allowed to reach for each port during WFQ Port Arbitration.  Chips: BB_A0 BB_B0 K2
35953 #define PRS_REG_WFQ_PORT_ARB_CREDIT_WEIGHT                                                           0x1f0660UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to the credit register for each port when it is time to increment during WFQ Port arbitration.  Chips: BB_A0 BB_B0 K2
35954 #define PRS_REG_WFQ_PORT_ARB_CURRENT_CREDIT                                                          0x1f0664UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in the credit register for each port during WFQ Port arbitration.  Chips: BB_A0 BB_B0 K2
35955 #define PRS_REG_PROP_HDR_SIZE                                                                        0x1f0700UL //Access:RW   DataWidth:0x4   Per-port: Size of the proprietary header for this port (in 4B increments). If proprietary header is disabled this value should be 0.  Legal values for this field are from 0 (disabled) to 8 (32B).  Chips: BB_A0 BB_B0 K2
35956 #define PRS_REG_LLC_TYPE_THRESHOLD                                                                   0x1f0704UL //Access:RW   DataWidth:0x10  Upper value of LLC Ethertype range.  Chips: BB_A0 BB_B0 K2
35957 #define PRS_REG_LLC_JUMBO_TYPE                                                                       0x1f0708UL //Access:RW   DataWidth:0x10  Jumbo value of LLC Ethertype.  Chips: BB_A0 BB_B0 K2
35958 #define PRS_REG_GRE_ETH_TYPE                                                                         0x1f070cUL //Access:RW   DataWidth:0x10  Ethertype for encapsulated ethernet used in GRE header parsing.  Chips: BB_A0 BB_B0 K2
35959 #define PRS_REG_IPV4_TYPE                                                                            0x1f0710UL //Access:RW   DataWidth:0x10  IPv4 Ethertype.  Chips: BB_A0 BB_B0 K2
35960 #define PRS_REG_IPV6_TYPE                                                                            0x1f0714UL //Access:RW   DataWidth:0x10  IPv6 Ethertype.  Chips: BB_A0 BB_B0 K2
35961 #define PRS_REG_ROCE_TYPE                                                                            0x1f0718UL //Access:RW   DataWidth:0x10  RoCE Ethertype.  Chips: BB_A0 BB_B0 K2
35962 #define PRS_REG_ARP_TYPE                                                                             0x1f071cUL //Access:RW   DataWidth:0x10  ARP Ethertype.  Chips: BB_A0 BB_B0 K2
35963 #define PRS_REG_TCP_PROTOCOL                                                                         0x1f0720UL //Access:RW   DataWidth:0x8   Value used to designate TCP in the IPv4 Protocol and IPv6 Next Header fields.  Chips: BB_A0 BB_B0 K2
35964 #define PRS_REG_UDP_PROTOCOL                                                                         0x1f0724UL //Access:RW   DataWidth:0x8   Value used to designate UDP in the IPv4 Protocol and IPv6 Next Header fields.  Chips: BB_A0 BB_B0 K2
35965 #define PRS_REG_SCTP_PROTOCOL                                                                        0x1f0728UL //Access:RW   DataWidth:0x8   Value used to designate SCTP in the IPv4 Protocol and IPv6 Next Header fields.  Matching can only occur when sctp_enable is set.  Chips: BB_A0 BB_B0 K2
35966 #define PRS_REG_ICMPV4_PROTOCOL                                                                      0x1f072cUL //Access:RW   DataWidth:0x8   Value used to designate ICMP in the IPv4 Protocol field. Matching can only occur when icmp_enable is set.  Chips: BB_A0 BB_B0 K2
35967 #define PRS_REG_ENCAPSULATION_TYPE_EN                                                                0x1f0730UL //Access:RW   DataWidth:0x6   Per-port:  Flag enabling each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE  Chips: BB_A0 BB_B0 K2
35968 #define PRS_REG_GRE_PROTOCOL                                                                         0x1f0734UL //Access:RW   DataWidth:0x8   Value used to designate GRE in the IPv4 Protocol and IPv6 Next Header fields.  Chips: BB_A0 BB_B0 K2
35969 #define PRS_REG_VXLAN_PORT                                                                           0x1f0738UL //Access:RW   DataWidth:0x10  Dest port value used to designate a VXLAN header following the UDP header.  Chips: BB_A0 BB_B0 K2
35970 #define PRS_REG_ROCE_ICID_BASE_PF                                                                    0x1f073cUL //Access:RW   DataWidth:0x10  Per-PF: Base value used in the TID calc during RoCE parsing for PF pkts.  Chips: BB_A0 BB_B0 K2
35971 #define PRS_REG_ROCE_ICID_BASE_VF                                                                    0x1f0740UL //Access:RW   DataWidth:0x10  Per-PF: Base value used in the TID calc during RoCE parsing for VF pkts.  Chips: BB_A0 BB_B0 K2
35972 #define PRS_REG_FCOE_TYPE                                                                            0x1f0744UL //Access:RW   DataWidth:0x10  The Ethernet type value for first FCoE type.  Chips: BB_A0 BB_B0 K2
35973 #define PRS_REG_FIP_TYPE                                                                             0x1f0748UL //Access:RW   DataWidth:0x10  The Ethernet type value for FIP type.  Chips: BB_A0 BB_B0 K2
35974 #define PRS_REG_TAG_ETHERTYPE_0                                                                      0x1f074cUL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 0.  Chips: BB_A0 BB_B0 K2
35975 #define PRS_REG_TAG_ETHERTYPE_1                                                                      0x1f0750UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 1.  Chips: BB_A0 BB_B0 K2
35976 #define PRS_REG_TAG_ETHERTYPE_2                                                                      0x1f0754UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 2.  Chips: BB_A0 BB_B0 K2
35977 #define PRS_REG_TAG_ETHERTYPE_3                                                                      0x1f0758UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 3.  Chips: BB_A0 BB_B0 K2
35978 #define PRS_REG_TAG_ETHERTYPE_4                                                                      0x1f075cUL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 4.  Chips: BB_A0 BB_B0 K2
35979 #define PRS_REG_TAG_ETHERTYPE_5                                                                      0x1f0760UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 5.  Chips: BB_A0 BB_B0 K2
35980 #define PRS_REG_TAG_LEN_0                                                                            0x1f0764UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 0.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
35981 #define PRS_REG_TAG_LEN_1                                                                            0x1f0768UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 1.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
35982 #define PRS_REG_TAG_LEN_2                                                                            0x1f076cUL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 2.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
35983 #define PRS_REG_TAG_LEN_3                                                                            0x1f0770UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 3.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
35984 #define PRS_REG_TAG_LEN_4                                                                            0x1f0774UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 4.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
35985 #define PRS_REG_TAG_LEN_5                                                                            0x1f0778UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 5.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
35986 #define PRS_REG_FIRST_HDR_HDRS_AFTER_BASIC                                                           0x1f077cUL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
35987 #define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_0                                                           0x1f0780UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
35988 #define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_1                                                           0x1f0784UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
35989 #define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_2                                                           0x1f0788UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
35990 #define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_3                                                           0x1f078cUL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
35991 #define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_4                                                           0x1f0790UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
35992 #define PRS_REG_FIRST_HDR_HDRS_AFTER_TAG_5                                                           0x1f0794UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
35993 #define PRS_REG_FIRST_HDR_MUST_HAVE_HDRS                                                             0x1f0798UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which headers must appear in the packet on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
35994 #define PRS_REG_INNER_HDR_HDRS_AFTER_BASIC                                                           0x1f079cUL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
35995 #define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_0                                                           0x1f07a0UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
35996 #define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_1                                                           0x1f07a4UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
35997 #define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_2                                                           0x1f07a8UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
35998 #define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_3                                                           0x1f07acUL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
35999 #define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_4                                                           0x1f07b0UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
36000 #define PRS_REG_INNER_HDR_HDRS_AFTER_TAG_5                                                           0x1f07b4UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
36001 #define PRS_REG_INNER_HDR_MUST_HAVE_HDRS                                                             0x1f07b8UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which headers must appear in the packet on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
36002 #define PRS_REG_DST_MAC_GLOBAL_0                                                                     0x1f07bcUL //Access:RW   DataWidth:0x20  Global destination address match value.  Chips: BB_A0 BB_B0 K2
36003 #define PRS_REG_DST_MAC_GLOBAL_1                                                                     0x1f07c0UL //Access:RW   DataWidth:0x10  Global destination address match value.  Chips: BB_A0 BB_B0 K2
36004 #define PRS_REG_DST_MAC_GLOBAL_MASK_0                                                                0x1f07c4UL //Access:RW   DataWidth:0x20  Mask for global destination address match value. A zero in this                 register will cause the corresponding bit to not be included in the match.  Chips: BB_A0 BB_B0 K2
36005 #define PRS_REG_DST_MAC_GLOBAL_MASK_1                                                                0x1f07c8UL //Access:RW   DataWidth:0x10  Mask for global destination address match value. A zero in this                 register will cause the corresponding bit to not be included in the match.  Chips: BB_A0 BB_B0 K2
36006 #define PRS_REG_FIRST_HDR_DST_MAC_0                                                                  0x1f07ccUL //Access:RW   DataWidth:0x20  Per-PF/Per-port: Destination address match value.  Chips: BB_A0 BB_B0 K2
36007 #define PRS_REG_FIRST_HDR_DST_MAC_1                                                                  0x1f07d0UL //Access:RW   DataWidth:0x10  Per-PF/Per-port: Destination address match value.  Chips: BB_A0 BB_B0 K2
36008 #define PRS_REG_FIRST_HDR_DST_IP_0                                                                   0x1f07d4UL //Access:RW   DataWidth:0x20  Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.  Chips: BB_A0 BB_B0 K2
36009 #define PRS_REG_FIRST_HDR_DST_IP_1                                                                   0x1f07d8UL //Access:RW   DataWidth:0x20  Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.  Chips: BB_A0 BB_B0 K2
36010 #define PRS_REG_FIRST_HDR_DST_IP_2                                                                   0x1f07dcUL //Access:RW   DataWidth:0x20  Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.  Chips: BB_A0 BB_B0 K2
36011 #define PRS_REG_FIRST_HDR_DST_IP_3                                                                   0x1f07e0UL //Access:RW   DataWidth:0x20  Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.  Chips: BB_A0 BB_B0 K2
36012 #define PRS_REG_FIRST_HDR_DST_IP_4                                                                   0x1f07e4UL //Access:RW   DataWidth:0x2   Per-PF:  Destination IP address match value - bit 129 indicates validity, bit 128 indicates an IPv6 address.  Chips: BB_A0 BB_B0 K2
36013 #define PRS_REG_SRC_MAC_0_0                                                                          0x1f07e8UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36014 #define PRS_REG_SRC_MAC_0_1                                                                          0x1f07ecUL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36015 #define PRS_REG_SRC_MAC_1_0                                                                          0x1f07f0UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36016 #define PRS_REG_SRC_MAC_1_1                                                                          0x1f07f4UL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36017 #define PRS_REG_SRC_MAC_2_0                                                                          0x1f07f8UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36018 #define PRS_REG_SRC_MAC_2_1                                                                          0x1f07fcUL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36019 #define PRS_REG_SRC_MAC_3_0                                                                          0x1f0800UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36020 #define PRS_REG_SRC_MAC_3_1                                                                          0x1f0804UL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36021 #define PRS_REG_SRC_MAC_4_0                                                                          0x1f0808UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36022 #define PRS_REG_SRC_MAC_4_1                                                                          0x1f080cUL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36023 #define PRS_REG_SRC_MAC_5_0                                                                          0x1f0810UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36024 #define PRS_REG_SRC_MAC_5_1                                                                          0x1f0814UL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36025 #define PRS_REG_SRC_MAC_6_0                                                                          0x1f0818UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36026 #define PRS_REG_SRC_MAC_6_1                                                                          0x1f081cUL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36027 #define PRS_REG_SRC_MAC_7_0                                                                          0x1f0820UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36028 #define PRS_REG_SRC_MAC_7_1                                                                          0x1f0824UL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36029 #define PRS_REG_SRC_MAC_8_0                                                                          0x1f0828UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36030 #define PRS_REG_SRC_MAC_8_1                                                                          0x1f082cUL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36031 #define PRS_REG_SRC_MAC_9_0                                                                          0x1f0830UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36032 #define PRS_REG_SRC_MAC_9_1                                                                          0x1f0834UL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36033 #define PRS_REG_SRC_MAC_10_0                                                                         0x1f0838UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36034 #define PRS_REG_SRC_MAC_10_1                                                                         0x1f083cUL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36035 #define PRS_REG_SRC_MAC_11_0                                                                         0x1f0840UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36036 #define PRS_REG_SRC_MAC_11_1                                                                         0x1f0844UL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36037 #define PRS_REG_SRC_MAC_12_0                                                                         0x1f0848UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36038 #define PRS_REG_SRC_MAC_12_1                                                                         0x1f084cUL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36039 #define PRS_REG_SRC_MAC_13_0                                                                         0x1f0850UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36040 #define PRS_REG_SRC_MAC_13_1                                                                         0x1f0854UL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36041 #define PRS_REG_SRC_MAC_14_0                                                                         0x1f0858UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36042 #define PRS_REG_SRC_MAC_14_1                                                                         0x1f085cUL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36043 #define PRS_REG_SRC_MAC_15_0                                                                         0x1f0860UL //Access:RW   DataWidth:0x20  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36044 #define PRS_REG_SRC_MAC_15_1                                                                         0x1f0864UL //Access:RW   DataWidth:0x10  Per-port: Source address match values for this port.  Chips: BB_A0 BB_B0 K2
36045 #define PRS_REG_NGE_ETH_TYPE                                                                         0x1f0868UL //Access:RW   DataWidth:0x10  Ethertype for encapsulated ethernet used in NGE header parsing.  Chips: BB_B0 K2
36046 #define PRS_REG_NGE_PORT                                                                             0x1f086cUL //Access:RW   DataWidth:0x10  Dest port value used to designate a NGE header following the UDP header.  Chips: BB_B0 K2
36047 #define PRS_REG_RROCE_PORT                                                                           0x1f0870UL //Access:RW   DataWidth:0x10  Dest port value used to designate a RROCE header following the UDP header.  Chips: BB_B0 K2
36048 #define PRS_REG_RROCE_ENABLE                                                                         0x1f0874UL //Access:RW   DataWidth:0x1   Per-port:  Flag enabling RRoCE.  Chips: BB_B0 K2
36049 #define PRS_REG_NGE_COMP_VER                                                                         0x1f0878UL //Access:RW   DataWidth:0x1   Per-port:  Flag to compare the value of nge version to 2'b00.  Chips: BB_B0 K2
36050 #define PRS_REG_L2_IRREG_CASES                                                                       0x1f0900UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36051     #define PRS_REG_L2_IRREG_CASES_EVENT_ID                                                          (0xff<<0) // Event ID for irregular or errored packets
36052     #define PRS_REG_L2_IRREG_CASES_EVENT_ID_SHIFT                                                    0
36053     #define PRS_REG_L2_IRREG_CASES_CM_HDR                                                            (0x3ff<<8) // The CM header for irregular or errored packets. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36054     #define PRS_REG_L2_IRREG_CASES_CM_HDR_SHIFT                                                      8
36055 #define PRS_REG_L2_TUNNELING                                                                         0x1f0904UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36056     #define PRS_REG_L2_TUNNELING_EVENT_ID                                                            (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
36057     #define PRS_REG_L2_TUNNELING_EVENT_ID_SHIFT                                                      0
36058     #define PRS_REG_L2_TUNNELING_CM_HDR                                                              (0x3ff<<8) // The CM header for tunneled packets with no match in the mac-vlan cache. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36059     #define PRS_REG_L2_TUNNELING_CM_HDR_SHIFT                                                        8
36060 #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN                                                         0x1f0908UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36061     #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_EVENT_ID                                            (0xff<<0) // Event ID for tunneled packets with no match in the mac-vlan cache
36062     #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_EVENT_ID_SHIFT                                      0
36063     #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_CM_HDR                                              (0x3ff<<8) // The CM header for tunneled packets with no match in the mac-vlan cache. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36064     #define PRS_REG_L2_TUNNELING_CACHED_MAC_VLAN_CM_HDR_SHIFT                                        8
36065 #define PRS_REG_L2_CACHED_MAC_VLAN                                                                   0x1f090cUL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36066     #define PRS_REG_L2_CACHED_MAC_VLAN_EVENT_ID                                                      (0xff<<0) // Event ID for packets that hit in the MAC/VLAN cache
36067     #define PRS_REG_L2_CACHED_MAC_VLAN_EVENT_ID_SHIFT                                                0
36068     #define PRS_REG_L2_CACHED_MAC_VLAN_CM_HDR                                                        (0x3ff<<8) // The CM header for packets that hit in the MAC/VLAN cache. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36069     #define PRS_REG_L2_CACHED_MAC_VLAN_CM_HDR_SHIFT                                                  8
36070 #define PRS_REG_LIGHT_L2                                                                             0x1f0910UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36071     #define PRS_REG_LIGHT_L2_EVENT_ID                                                                (0xff<<0) // Event ID for light L2
36072     #define PRS_REG_LIGHT_L2_EVENT_ID_SHIFT                                                          0
36073     #define PRS_REG_LIGHT_L2_CM_HDR                                                                  (0x3ff<<8) // The CM header for light L2. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36074     #define PRS_REG_LIGHT_L2_CM_HDR_SHIFT                                                            8
36075 #define PRS_REG_CM_HDR_EVENT_ID_0                                                                    0x1f0914UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36076     #define PRS_REG_CM_HDR_EVENT_ID_0_EVENT_ID                                                       (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 0
36077     #define PRS_REG_CM_HDR_EVENT_ID_0_EVENT_ID_SHIFT                                                 0
36078     #define PRS_REG_CM_HDR_EVENT_ID_0_CM_HDR                                                         (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 0. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36079     #define PRS_REG_CM_HDR_EVENT_ID_0_CM_HDR_SHIFT                                                   8
36080 #define PRS_REG_CM_HDR_EVENT_ID_1                                                                    0x1f0918UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36081     #define PRS_REG_CM_HDR_EVENT_ID_1_EVENT_ID                                                       (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 1
36082     #define PRS_REG_CM_HDR_EVENT_ID_1_EVENT_ID_SHIFT                                                 0
36083     #define PRS_REG_CM_HDR_EVENT_ID_1_CM_HDR                                                         (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 1. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36084     #define PRS_REG_CM_HDR_EVENT_ID_1_CM_HDR_SHIFT                                                   8
36085 #define PRS_REG_CM_HDR_EVENT_ID_2                                                                    0x1f091cUL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36086     #define PRS_REG_CM_HDR_EVENT_ID_2_EVENT_ID                                                       (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 2
36087     #define PRS_REG_CM_HDR_EVENT_ID_2_EVENT_ID_SHIFT                                                 0
36088     #define PRS_REG_CM_HDR_EVENT_ID_2_CM_HDR                                                         (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 2. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36089     #define PRS_REG_CM_HDR_EVENT_ID_2_CM_HDR_SHIFT                                                   8
36090 #define PRS_REG_CM_HDR_EVENT_ID_3                                                                    0x1f0920UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36091     #define PRS_REG_CM_HDR_EVENT_ID_3_EVENT_ID                                                       (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 3
36092     #define PRS_REG_CM_HDR_EVENT_ID_3_EVENT_ID_SHIFT                                                 0
36093     #define PRS_REG_CM_HDR_EVENT_ID_3_CM_HDR                                                         (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 3. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36094     #define PRS_REG_CM_HDR_EVENT_ID_3_CM_HDR_SHIFT                                                   8
36095 #define PRS_REG_CM_HDR_EVENT_ID_4                                                                    0x1f0924UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36096     #define PRS_REG_CM_HDR_EVENT_ID_4_EVENT_ID                                                       (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 4
36097     #define PRS_REG_CM_HDR_EVENT_ID_4_EVENT_ID_SHIFT                                                 0
36098     #define PRS_REG_CM_HDR_EVENT_ID_4_CM_HDR                                                         (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 4. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36099     #define PRS_REG_CM_HDR_EVENT_ID_4_CM_HDR_SHIFT                                                   8
36100 #define PRS_REG_CM_HDR_EVENT_ID_5                                                                    0x1f0928UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36101     #define PRS_REG_CM_HDR_EVENT_ID_5_EVENT_ID                                                       (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 5
36102     #define PRS_REG_CM_HDR_EVENT_ID_5_EVENT_ID_SHIFT                                                 0
36103     #define PRS_REG_CM_HDR_EVENT_ID_5_CM_HDR                                                         (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 5. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36104     #define PRS_REG_CM_HDR_EVENT_ID_5_CM_HDR_SHIFT                                                   8
36105 #define PRS_REG_CM_HDR_EVENT_ID_6                                                                    0x1f092cUL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36106     #define PRS_REG_CM_HDR_EVENT_ID_6_EVENT_ID                                                       (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 6
36107     #define PRS_REG_CM_HDR_EVENT_ID_6_EVENT_ID_SHIFT                                                 0
36108     #define PRS_REG_CM_HDR_EVENT_ID_6_CM_HDR                                                         (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 6. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36109     #define PRS_REG_CM_HDR_EVENT_ID_6_CM_HDR_SHIFT                                                   8
36110 #define PRS_REG_CM_HDR_EVENT_ID_7                                                                    0x1f0930UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36111     #define PRS_REG_CM_HDR_EVENT_ID_7_EVENT_ID                                                       (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and connection type 7
36112     #define PRS_REG_CM_HDR_EVENT_ID_7_EVENT_ID_SHIFT                                                 0
36113     #define PRS_REG_CM_HDR_EVENT_ID_7_CM_HDR                                                         (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and connection type 7. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36114     #define PRS_REG_CM_HDR_EVENT_ID_7_CM_HDR_SHIFT                                                   8
36115 #define PRS_REG_L2_REGULAR_PKT                                                                       0x1f0934UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36116     #define PRS_REG_L2_REGULAR_PKT_EVENT_ID                                                          (0xff<<0) // Event ID for regular packets
36117     #define PRS_REG_L2_REGULAR_PKT_EVENT_ID_SHIFT                                                    0
36118     #define PRS_REG_L2_REGULAR_PKT_CM_HDR                                                            (0x3ff<<8) // The CM header for regular packets. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36119     #define PRS_REG_L2_REGULAR_PKT_CM_HDR_SHIFT                                                      8
36120 #define PRS_REG_TASK_CM_HDR                                                                          0x1f0938UL //Access:RW   DataWidth:0xa   The CM header for an FCoE packet. Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.  Chips: BB_A0 BB_B0 K2
36121 #define PRS_REG_DEF_L2_CON_TYPE                                                                      0x1f093cUL //Access:RW   DataWidth:0x4   Connection type for no-match packets.  Chips: BB_A0 BB_B0 K2
36122 #define PRS_REG_NO_MATCH_PFID                                                                        0x1f0940UL //Access:RW   DataWidth:0x4   Per-port: PFID for no-match packets.  Chips: BB_A0 BB_B0 K2
36123 #define PRS_REG_OVERRIDE_PFID_IF_NO_MATCH                                                            0x1f0944UL //Access:RW   DataWidth:0x1   Per-PF: If set, the PFID may be overridden for no-match packets.  Chips: BB_A0 BB_B0 K2
36124 #define PRS_REG_NO_MATCH_CID                                                                         0x1f0948UL //Access:RW   DataWidth:0x20  Per-PF: CID for no-match packets.  Chips: BB_A0 BB_B0 K2
36125 #define PRS_REG_NO_MATCH_LCID                                                                        0x1f094cUL //Access:RW   DataWidth:0x9   Per-PF: LCID for no-match packets.  Chips: BB_A0 BB_B0 K2
36126 #define PRS_REG_LIGHT_L2_ETHERTYPE_0                                                                 0x1f0950UL //Access:RW   DataWidth:0x10  If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.  Chips: BB_A0 BB_B0 K2
36127 #define PRS_REG_LIGHT_L2_ETHERTYPE_1                                                                 0x1f0954UL //Access:RW   DataWidth:0x10  If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.  Chips: BB_A0 BB_B0 K2
36128 #define PRS_REG_LIGHT_L2_ETHERTYPE_2                                                                 0x1f0958UL //Access:RW   DataWidth:0x10  If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.  Chips: BB_A0 BB_B0 K2
36129 #define PRS_REG_LIGHT_L2_ETHERTYPE_3                                                                 0x1f095cUL //Access:RW   DataWidth:0x10  If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.  Chips: BB_A0 BB_B0 K2
36130 #define PRS_REG_LIGHT_L2_ETHERTYPE_4                                                                 0x1f0960UL //Access:RW   DataWidth:0x10  If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.  Chips: BB_A0 BB_B0 K2
36131 #define PRS_REG_LIGHT_L2_ETHERTYPE_5                                                                 0x1f0964UL //Access:RW   DataWidth:0x10  If one of these Ethertypes matches the last L2 ethertype, light_l2_cm_hdr_event_id can be used for the cm_hdr and eventid values.  Chips: BB_A0 BB_B0 K2
36132 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN                                                                0x1f0968UL //Access:RW   DataWidth:0x6   Enables for each of the light_l2_ethertypes.  Chips: BB_A0 BB_B0 K2
36133 #define PRS_REG_USE_LIGHT_L2                                                                         0x1f096cUL //Access:RW   DataWidth:0x1   Per-PF: If set, and PF classification succeeds, use  light_l2_tbit_eventid  Chips: BB_A0 BB_B0 K2
36134 #define PRS_REG_DST_MAC_SELECT                                                                       0x1f0970UL //Access:RW   DataWidth:0x3   Selects whether to use the dest MAC address of the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE  Chips: BB_A0 BB_B0 K2
36135 #define PRS_REG_SRC_MAC_SELECT                                                                       0x1f0974UL //Access:RW   DataWidth:0x3   Selects whether to use the source MAC address of the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN 2 - NGE  Chips: BB_A0 BB_B0 K2
36136 #define PRS_REG_VLAN_TAG_SELECT                                                                      0x1f0978UL //Access:RW   DataWidth:0x3   Selects whether to use the 8021q tag of the first (0) or encapsulated (1) header in the output message for each encapsulation type. 0 - L2 GRE, 1 - VXLAN, 2 - NGE  Chips: BB_A0 BB_B0 K2
36137 #define PRS_REG_OUTPUT_FORMAT_0_0                                                                    0x1f097cUL //Access:RW   DataWidth:0x20  Ordered list of building blocks in TSTORM message for connection type 0. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36138 #define PRS_REG_OUTPUT_FORMAT_0_1                                                                    0x1f0980UL //Access:RW   DataWidth:0x10  Ordered list of building blocks in TSTORM message for connection type 0. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36139 #define PRS_REG_OUTPUT_FORMAT_1_0                                                                    0x1f0984UL //Access:RW   DataWidth:0x20  Ordered list of building blocks in TSTORM message for connection type 1. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36140 #define PRS_REG_OUTPUT_FORMAT_1_1                                                                    0x1f0988UL //Access:RW   DataWidth:0x10  Ordered list of building blocks in TSTORM message for connection type 1. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36141 #define PRS_REG_OUTPUT_FORMAT_2_0                                                                    0x1f098cUL //Access:RW   DataWidth:0x20  Ordered list of building blocks in TSTORM message for connection type 2. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36142 #define PRS_REG_OUTPUT_FORMAT_2_1                                                                    0x1f0990UL //Access:RW   DataWidth:0x10  Ordered list of building blocks in TSTORM message for connection type 2. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36143 #define PRS_REG_OUTPUT_FORMAT_3_0                                                                    0x1f0994UL //Access:RW   DataWidth:0x20  Ordered list of building blocks in TSTORM message for connection type 3. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36144 #define PRS_REG_OUTPUT_FORMAT_3_1                                                                    0x1f0998UL //Access:RW   DataWidth:0x10  Ordered list of building blocks in TSTORM message for connection type 3. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36145 #define PRS_REG_OUTPUT_FORMAT_4_0                                                                    0x1f099cUL //Access:RW   DataWidth:0x20  Ordered list of building blocks in TSTORM message for connection type 4. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36146 #define PRS_REG_OUTPUT_FORMAT_4_1                                                                    0x1f09a0UL //Access:RW   DataWidth:0x10  Ordered list of building blocks in TSTORM message for connection type 4. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36147 #define PRS_REG_OUTPUT_FORMAT_5_0                                                                    0x1f09a4UL //Access:RW   DataWidth:0x20  Ordered list of building blocks in TSTORM message for connection type 5. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36148 #define PRS_REG_OUTPUT_FORMAT_5_1                                                                    0x1f09a8UL //Access:RW   DataWidth:0x10  Ordered list of building blocks in TSTORM message for connection type 5. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36149 #define PRS_REG_OUTPUT_FORMAT_6_0                                                                    0x1f09acUL //Access:RW   DataWidth:0x20  Ordered list of building blocks in TSTORM message for connection type 6. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36150 #define PRS_REG_OUTPUT_FORMAT_6_1                                                                    0x1f09b0UL //Access:RW   DataWidth:0x10  Ordered list of building blocks in TSTORM message for connection type 6. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36151 #define PRS_REG_OUTPUT_FORMAT_7_0                                                                    0x1f09b4UL //Access:RW   DataWidth:0x20  Ordered list of building blocks in TSTORM message for connection type 7. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36152 #define PRS_REG_OUTPUT_FORMAT_7_1                                                                    0x1f09b8UL //Access:RW   DataWidth:0x10  Ordered list of building blocks in TSTORM message for connection type 7. Unused blocks must be set to 0xf.  Chips: BB_A0 BB_B0 K2
36153 #define PRS_REG_MAC_VLAN_CACHE_USE_TENANT_ID                                                         0x1f09bcUL //Access:RW   DataWidth:0x6   Per-PF: Indicates whether to include Tenant ID (if it exists) in the MAC VLAN Cache entry for each encapsulation type. 0 - L2 GRE, 1 - IP GRE, 2 - VXLAN, 3 - T-Tag, 4 - L2 NGE, 5 - IP NGE  Chips: BB_A0 BB_B0 K2
36154 #define PRS_REG_MAC_VLAN_FLEX_UPPER                                                                  0x1f09c0UL //Access:RW   DataWidth:0xe   Building block information used to build the MAC-VLAN Cache Flexible Field.  If two blocks are used, this block is used for the upper bytes. 13:11 - number of bytes, 10:4 - byte offset, 3:0 - block id.  Chips: BB_A0 BB_B0 K2
36155 #define PRS_REG_MAC_VLAN_FLEX_LOWER                                                                  0x1f09c4UL //Access:RW   DataWidth:0xe   Building block information used to build the MAC-VLAN Cache Flexible Field.  This block is only used if the number of bytes in mac_vlan_flex_upper is less than 6.13:11 - number of bytes, 10:4 - byte offset, 3:0 - block id.  Chips: BB_A0 BB_B0 K2
36156 #define PRS_REG_MAC_VLAN_FLEX_BITMASK_0                                                              0x1f09c8UL //Access:RW   DataWidth:0x20  Used to bitmask the flexible field formed from the building block information in mac_vlan_flex_upper and/or mac_vlan_flex_lower.  A zero in this register will mask the corresponding bit in the flexible field to 0.  Chips: BB_A0 BB_B0 K2
36157 #define PRS_REG_MAC_VLAN_FLEX_BITMASK_1                                                              0x1f09ccUL //Access:RW   DataWidth:0x10  Used to bitmask the flexible field formed from the building block information in mac_vlan_flex_upper and/or mac_vlan_flex_lower.  A zero in this register will mask the corresponding bit in the flexible field to 0.  Chips: BB_A0 BB_B0 K2
36158 #define PRS_REG_SORT_SACK                                                                            0x1f09d0UL //Access:RW   DataWidth:0x1   Per-PF: If set, the SACK blocks will be sorted and various compares performed.  Chips: BB_A0 BB_B0 K2
36159 #define PRS_REG_SACK_BLK_OVERRIDE                                                                    0x1f09d4UL //Access:RW   DataWidth:0x1   If set, RoCE building block data is FIFOed on all non-FCoE packets. This allows Over-L2-Raw Part2 to be available on non-RoCE packets. The RoCE specific bits of this block will still show default values on non-RoCE packets.  Chips: BB_A0 BB_B0 K2
36160 #define PRS_REG_RDMA_SYN_MASK                                                                        0x1f09d8UL //Access:RW   DataWidth:0x20  Per-PF: Mask used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36161 #define PRS_REG_RDMA_SYN_SEED_0                                                                      0x1f09dcUL //Access:RW   DataWidth:0x20  Seeds used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36162 #define PRS_REG_RDMA_SYN_SEED_1                                                                      0x1f09e0UL //Access:RW   DataWidth:0x20  Seeds used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36163 #define PRS_REG_RDMA_SYN_SEED_2                                                                      0x1f09e4UL //Access:RW   DataWidth:0x20  Seeds used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36164 #define PRS_REG_RDMA_SYN_SEED_3                                                                      0x1f09e8UL //Access:RW   DataWidth:0x20  Seeds used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36165 #define PRS_REG_RDMA_SYN_SEED_4                                                                      0x1f09ecUL //Access:RW   DataWidth:0x20  Seeds used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36166 #define PRS_REG_RDMA_SYN_SEED_5                                                                      0x1f09f0UL //Access:RW   DataWidth:0x20  Seeds used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36167 #define PRS_REG_RDMA_SYN_SEED_6                                                                      0x1f09f4UL //Access:RW   DataWidth:0x20  Seeds used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36168 #define PRS_REG_RDMA_SYN_SEED_7                                                                      0x1f09f8UL //Access:RW   DataWidth:0x20  Seeds used in RDMA SYN cookie calculation.  Chips: BB_A0 BB_B0 K2
36169 #define PRS_REG_RDMA_SYN_COOKIE_EN                                                                   0x1f09fcUL //Access:RW   DataWidth:0x1   Per-PF: Enables SYN cookie hash function.  Chips: BB_A0 BB_B0 K2
36170 #define PRS_REG_IWARP_EN                                                                             0x1f0a00UL //Access:RW   DataWidth:0x1   Per-PF: If set, enables iWarp.  Chips: BB_A0 BB_B0 K2
36171 #define PRS_REG_PKT_LEN_STAT_ADD_CRC                                                                 0x1f0a04UL //Access:RW   DataWidth:0x1   Per-PF: If set, 4B for Ethernet CRC is included in Packet Length for Statistics field. For pkts where classification failed,  the per-port version of this register is used.  Chips: BB_A0 BB_B0 K2
36172 #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_INNER                                                  0x1f0a08UL //Access:RW   DataWidth:0x8   Per-PF: For each bit set, the length of the corresponding tag in the inner header will be subtracted from Packet Length for Statistics Field.  For pkts where classification failed,  the per-port version of this register is used.  Chips: BB_A0 BB_B0 K2
36173 #define PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST                                                  0x1f0a0cUL //Access:RW   DataWidth:0x9   Per-PF: For each bit set, the length of the corresponding tag in the first header will be subtracted from Packet Length for Statistics Field.  The upper bit is for proprietary header. For pkts where classification failed,  the per-port version of this register is used.  Chips: BB_A0 BB_B0 K2
36174 #define PRS_REG_CLASSIFY_FAILED_PKT_LEN_STAT_ADD_CRC                                                 0x1f0a10UL //Access:RW   DataWidth:0x1   Per-Port: If set and classification failed, 4B for Ethernet CRC is included in Packet Length for Statistics field.  Chips: BB_A0 BB_B0 K2
36175 #define PRS_REG_CLASSIFY_FAILED_PKT_LEN_STAT_TAGS_NOT_COUNTED_INNER                                  0x1f0a14UL //Access:RW   DataWidth:0x8   Per-Port: If classification failed, for each bit set, the length of the corresponding tag in the inner header will be subtracted from Packet Length for Statistics Field  Chips: BB_A0 BB_B0 K2
36176 #define PRS_REG_CLASSIFY_FAILED_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST                                  0x1f0a18UL //Access:RW   DataWidth:0x9   Per-Port: If classification failed, for each bit set, the length of the corresponding tag in the first header will be subtracted from Packet Length for Statistics Field.  The upper bit is for proprietary header.  Chips: BB_A0 BB_B0 K2
36177 #define PRS_REG_MSG_INFO                                                                             0x1f0a1cUL //Access:RW   DataWidth:0x20  Per-PF: This value is passed to the per-PF configuration field in the output message.  Chips: BB_A0 BB_B0 K2
36178 #define PRS_REG_NIG_CLASSIFY_FAILED                                                                  0x1f0a20UL //Access:RW   DataWidth:0x2   Per-Port: This value goes in the NIG Classify Failed field of the output message when classification fails.  Chips: BB_A0 BB_B0 K2
36179 #define PRS_REG_MSG_CT_MAIN_0                                                                        0x1f0a24UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the main port for TC 0. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36180 #define PRS_REG_MSG_CT_LB_0                                                                          0x1f0a28UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 0. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36181 #define PRS_REG_MSG_CT_MAIN_1                                                                        0x1f0a2cUL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the main port for TC 1. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36182 #define PRS_REG_MSG_CT_LB_1                                                                          0x1f0a30UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 1. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36183 #define PRS_REG_MSG_CT_MAIN_2                                                                        0x1f0a34UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the main port for TC 2. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36184 #define PRS_REG_MSG_CT_LB_2                                                                          0x1f0a38UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 2. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36185 #define PRS_REG_MSG_CT_MAIN_3                                                                        0x1f0a3cUL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the main port for TC 3. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36186 #define PRS_REG_MSG_CT_LB_3                                                                          0x1f0a40UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 3. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36187 #define PRS_REG_MSG_CT_MAIN_4                                                                        0x1f0a44UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the main port for TC 4. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36188 #define PRS_REG_MSG_CT_LB_4                                                                          0x1f0a48UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 4. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36189 #define PRS_REG_MSG_CT_MAIN_5                                                                        0x1f0a4cUL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the main port for TC 5. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36190 #define PRS_REG_MSG_CT_LB_5                                                                          0x1f0a50UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 5. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36191 #define PRS_REG_MSG_CT_MAIN_6                                                                        0x1f0a54UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the main port for TC 6. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36192 #define PRS_REG_MSG_CT_LB_6                                                                          0x1f0a58UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 6. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36193 #define PRS_REG_MSG_CT_MAIN_7                                                                        0x1f0a5cUL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the main port for TC 7. In 4-port mode, only TCs 0-3 are valid.  Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36194 #define PRS_REG_MSG_CT_LB_7                                                                          0x1f0a60UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 7. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36195 #define PRS_REG_MSG_CT_LB_8                                                                          0x1f0a64UL //Access:R    DataWidth:0x18  (per-port) Number of messages sent to TCM on the LB port for TC 8. In 4-port mode, only TCs 0-3 and 8 are valid. Counter loops to 0.  Chips: BB_A0 BB_B0 K2
36196 #define PRS_REG_IGNORE_UDP_ZERO_CHECKSUM                                                             0x1f0a68UL //Access:RW   DataWidth:0x3   bit 0 - ignore for VXLAN, bit 1 - ignore for NGE, bit 2 - ignore for RRoCE  Chips: BB_B0 K2
36197 #define PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES                                                            0x1f0b00UL //Access:RC   DataWidth:0x18  The number of input CFC flush packets.  Chips: BB_A0 BB_B0 K2
36198 #define PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES                                                    0x1f0b04UL //Access:RC   DataWidth:0x18  The number of input transparent flush packets.  Chips: BB_A0 BB_B0 K2
36199 #define PRS_REG_NUM_OF_PACKETS_0                                                                     0x1f0b08UL //Access:RC   DataWidth:0x18  The number of processed packets for TC 0.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36200 #define PRS_REG_NUM_OF_PACKETS_1                                                                     0x1f0b0cUL //Access:RC   DataWidth:0x18  The number of processed packets for TC 1.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36201 #define PRS_REG_NUM_OF_PACKETS_2                                                                     0x1f0b10UL //Access:RC   DataWidth:0x18  The number of processed packets for TC 2.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36202 #define PRS_REG_NUM_OF_PACKETS_3                                                                     0x1f0b14UL //Access:RC   DataWidth:0x18  The number of processed packets for TC 3.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36203 #define PRS_REG_NUM_OF_PACKETS_4                                                                     0x1f0b18UL //Access:RC   DataWidth:0x18  The number of processed packets for TC 4.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36204 #define PRS_REG_NUM_OF_PACKETS_5                                                                     0x1f0b1cUL //Access:RC   DataWidth:0x18  The number of processed packets for TC 5.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36205 #define PRS_REG_NUM_OF_PACKETS_6                                                                     0x1f0b20UL //Access:RC   DataWidth:0x18  The number of processed packets for TC 6.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36206 #define PRS_REG_NUM_OF_PACKETS_7                                                                     0x1f0b24UL //Access:RC   DataWidth:0x18  The number of processed packets for TC 7.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36207 #define PRS_REG_NUM_OF_PACKETS_8                                                                     0x1f0b28UL //Access:RC   DataWidth:0x18  The number of process packets for TC 8.  Counts packets as                             they are chosen for processing.  Chips: BB_A0 BB_B0 K2
36208 #define PRS_REG_FIFO_EMPTY_FLAGS                                                                     0x1f0b30UL //Access:WB_R DataWidth:0x80  Debug only: Empty_flag for each FIFO.  Chips: BB_A0 BB_B0 K2
36209 #define PRS_REG_FIFO_EMPTY_FLAGS_SIZE                                                                4
36210 #define PRS_REG_FIFO_FULL_FLAGS                                                                      0x1f0b40UL //Access:WB_R DataWidth:0x80  Debug only: Full_flag for each FIFO.  Chips: BB_A0 BB_B0 K2
36211 #define PRS_REG_FIFO_FULL_FLAGS_SIZE                                                                 4
36212 #define PRS_REG_PRS_PKT_CT                                                                           0x1f0b50UL //Access:R    DataWidth:0x6   Debug only: Parser pipeline packet count.  This is the value of the counter in the Input Arbiter that keeps track of the number of packets that have been selected to be processed but have not yet resulted in a message to TCM.  Chips: BB_A0 BB_B0 K2
36213 #define PRS_REG_QUEUE_PKT_AVAIL_STATUS                                                               0x1f0b54UL //Access:R    DataWidth:0x11  Debug only (per-port): Packet available status of the main and loopback queues of each traffic class, before being back pressured by the STORMs. 16:8 - Loopback, 7:0 - main  Chips: BB_A0 BB_B0 K2
36214 #define PRS_REG_STORM_BKPRS_STATUS                                                                   0x1f0b58UL //Access:R    DataWidth:0x18  Debug only (per-port): STORM backpressure status (blocked priorities) Each set bit represents a blocked TC (7-0) from MSDM, TSDM, and USDM, respectively.  Chips: BB_A0 BB_B0 K2
36215 #define PRS_REG_STOP_PARSING_STATUS                                                                  0x1f0b5cUL //Access:R    DataWidth:0x1   Debug only:  BRB has asserted Stop Parsing indication to PRS.  Chips: BB_A0 BB_B0 K2
36216 #define PRS_REG_MINI_CACHE_ENTRY                                                                     0x1f0b60UL //Access:WB_R DataWidth:0x32  Debug only: In case of LCID validation error, the current value of the single entry in the CID load mini-cache is captured. 49: Valid, 48:40 - LCID, 39:32 - Region, 31:0 - CID  Chips: BB_A0 BB_B0 K2
36217 #define PRS_REG_MINI_CACHE_ENTRY_SIZE                                                                2
36218 #define PRS_REG_MINI_CACHE_FAILED_RESPONSE                                                           0x1f0b68UL //Access:R    DataWidth:0xd   Debug only:  In the case of a mini-cache LCID validation error, the load response with the mismatched LCID is captured here.  Chips: BB_A0 BB_B0 K2
36219 #define PRS_REG_DBG_SELECT                                                                           0x1f0b6cUL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
36220 #define PRS_REG_DBG_DWORD_ENABLE                                                                     0x1f0b70UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
36221 #define PRS_REG_DBG_SHIFT                                                                            0x1f0b74UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
36222 #define PRS_REG_DBG_OUT_DATA                                                                         0x1f0b80UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
36223 #define PRS_REG_DBG_OUT_DATA_SIZE                                                                    8
36224 #define PRS_REG_DBG_FORCE_VALID                                                                      0x1f0ba0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
36225 #define PRS_REG_DBG_FORCE_FRAME                                                                      0x1f0ba4UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
36226 #define PRS_REG_DBG_OUT_VALID                                                                        0x1f0ba8UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
36227 #define PRS_REG_DBG_OUT_FRAME                                                                        0x1f0bacUL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
36228 #define PRS_REG_FC_DBG_SELECT                                                                        0x1f0bb0UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
36229 #define PRS_REG_FC_DBG_DWORD_ENABLE                                                                  0x1f0bb4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
36230 #define PRS_REG_FC_DBG_SHIFT                                                                         0x1f0bb8UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
36231 #define PRS_REG_FC_DBG_OUT_DATA                                                                      0x1f0bc0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
36232 #define PRS_REG_FC_DBG_OUT_DATA_SIZE                                                                 8
36233 #define PRS_REG_FC_DBG_FORCE_VALID                                                                   0x1f0be0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
36234 #define PRS_REG_FC_DBG_FORCE_FRAME                                                                   0x1f0be4UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
36235 #define PRS_REG_FC_DBG_OUT_VALID                                                                     0x1f0be8UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
36236 #define PRS_REG_FC_DBG_OUT_FRAME                                                                     0x1f0becUL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
36237 #define PRS_REG_LAST_PKT_LIST                                                                        0x1f0c00UL //Access:R    DataWidth:0x20  Debug only : Read access to a FIFO containing information from the last 32 pkts sent to TCM: Reserved - 127:66, Parsing and Error flags - 65:50, Start block - 49:37, Priority - 36:34, Port - 33:32, CID - 31:0. To allow this register to be read during traffic, the full entry value is latched when the lowest 4B are read. If the upper bytes of the same entry are read next, the latched value is used.  If another entry is read or the lower 4B are read again, a fresh value is returned from the FIFO. For flush packets, the CID comes from the flush message.  Chips: BB_A0 BB_B0 K2
36238 #define PRS_REG_LAST_PKT_LIST_SIZE                                                                   128
36239 #define PRS_REG_TCM_INITIAL_CREDIT                                                                   0x1f0f00UL //Access:RW   DataWidth:0x8   The initial credit in the packet start message to the TCM interface (message to STORM). Credit is cycle based.  Chips: BB_A0 BB_B0 K2
36240 #define PRS_REG_CCFC_SEARCH_INITIAL_CREDIT                                                           0x1f0f04UL //Access:RW   DataWidth:0x8   The initial credit for the search message to the CCFC interface. Credit is transaction based.  Chips: BB_A0 BB_B0 K2
36241 #define PRS_REG_TCFC_SEARCH_INITIAL_CREDIT                                                           0x1f0f08UL //Access:RW   DataWidth:0x2   The initial credit for the search message to the TCFC interface. Credit is transaction based.  Chips: BB_A0 BB_B0 K2
36242 #define PRS_REG_TCM_CURRENT_CREDIT                                                                   0x1f0f0cUL //Access:R    DataWidth:0x8   Debug only: TCM current credit. Transaction based. This is a count of the requests                        that have not received an ACK.  Chips: BB_A0 BB_B0 K2
36243 #define PRS_REG_CCFC_SEARCH_CURRENT_CREDIT                                                           0x1f0f10UL //Access:R    DataWidth:0x8   Debug only: CCFC search request current credit. Transaction based. This is a count of the requests that have not received an ACK.  Chips: BB_A0 BB_B0 K2
36244 #define PRS_REG_TCFC_SEARCH_CURRENT_CREDIT                                                           0x1f0f14UL //Access:R    DataWidth:0x8   Debug only: TCFC search request current credit. Transaction based. This is a count of the requests that have not received an ACK.  Chips: BB_A0 BB_B0 K2
36245 #define PRS_REG_CCFC_LOAD_CURRENT_CREDIT                                                             0x1f0f18UL //Access:R    DataWidth:0x1   Debug only: CCFC load request current credit. Transaction based. Since the credit limit on this interface is 1, if this bit is high there is a request that has not received an ACK.  Chips: BB_A0 BB_B0 K2
36246 #define PRS_REG_TCFC_LOAD_CURRENT_CREDIT                                                             0x1f0f1cUL //Access:R    DataWidth:0x1   Debug only: TCFC load request current credit. Transaction based.  Since the credit limit on this interface is 1, if this bit is high there is a request that has not received an ACK.  Chips: BB_A0 BB_B0 K2
36247 #define PRS_REG_CCFC_SEARCH_REQ_CT                                                                   0x1f0f20UL //Access:R    DataWidth:0x5   Debug only: The number of outstanding CCFC search requests. This is a count of the requests that have not received a response.  Chips: BB_A0 BB_B0 K2
36248 #define PRS_REG_TCFC_SEARCH_REQ_CT                                                                   0x1f0f24UL //Access:R    DataWidth:0x5   Debug only: The number of outstanding TCFC search requests This is a count of the requests that have not received a response.  Chips: BB_A0 BB_B0 K2
36249 #define PRS_REG_CCFC_LOAD_REQ_CT                                                                     0x1f0f28UL //Access:R    DataWidth:0x5   Debug only: The number of outstanding CCFC load requests  Chips: BB_A0 BB_B0 K2
36250 #define PRS_REG_TCFC_LOAD_REQ_CT                                                                     0x1f0f2cUL //Access:R    DataWidth:0x5   Debug only: The number of outstanding TCFC load requests  Chips: BB_A0 BB_B0 K2
36251 #define PRS_REG_SOP_REQ_CT                                                                           0x1f0f30UL //Access:R    DataWidth:0x3   Debug only: Outstanding SOP request count.  The value of the counter in the BRB Interface Unit that keeps track of the number of SOP requests sent to the BRB.  Chips: BB_A0 BB_B0 K2
36252 #define PRS_REG_EOP_REQ_CT                                                                           0x1f0f34UL //Access:R    DataWidth:0x3   Debug only (per-port): Outstanding EOP request count.  The value of the counter in the BRB Interface Unit that keeps track of the number of EOP requests sent to the BRB.  Chips: BB_A0 BB_B0 K2
36253 #define PRS_REG_CAM_BIST_EN                                                                          0x1f0f80UL //Access:RW   DataWidth:0x1   Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.  Chips: BB_A0 BB_B0
36254 #define PRS_REG_CAM_BIST_SKIP_ERROR_CNT                                                              0x1f0f84UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0
36255 #define PRS_REG_CAM_BIST_STATUS_SEL                                                                  0x1f0f88UL //Access:RW   DataWidth:0x8   Used to select the BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.  Chips: BB_A0 BB_B0
36256 #define PRS_REG_CAM_BIST_STATUS                                                                      0x1f0f8cUL //Access:R    DataWidth:0x20  Provides read-only access to the BIST status word selected by cam_bist_status_sel.  Chips: BB_A0 BB_B0
36257 #define PRS_REG_CAM_BIST_DBG_DATA                                                                    0x1f0f90UL //Access:RW   DataWidth:0x20  For CAM bist usage.  Chips: BB_A0 BB_B0
36258 #define PRS_REG_CAM_BIST_DBG_DATA_VALID                                                              0x1f0f94UL //Access:RW   DataWidth:0x1   For CAM bist usage.  Chips: BB_A0 BB_B0
36259 #define PRS_REG_CAM_BIST_DBG_COMPARE_EN                                                              0x1f0f98UL //Access:RW   DataWidth:0x1   For CAM bist usage.  Chips: BB_A0 BB_B0
36260 #define PRS_REG_GFT_PROFILE_MASK_RAM                                                                 0x1f1000UL //Access:WB   DataWidth:0x2a  Used to set the values of the GFT profile mask ram. line #31 must be configured before enabling the GFT since #31 is the default profile. 41.  Tenant ID Inner header(used also for non-encasulated packet): 40.Source MAC 39.Destination MAC 38.VLAN (12b) ) ? Tag 1 37.Provider VLAN (12b) ) ? Tag 0 36.Priority taken from CVLAN tag or the SVLAN tag based on GFTInnerVlanSelect global configuration 35.Source IP 34.Destination IP 33.Over IP protocol 32.DSCP (extracted form IP TOS) 31.Source port or ICMP type 30.Destination port or ICMP code 29.TCP flag - NS 28.TCP flag - CWR 27.TCP flag - ECE 26.TCP flag - URG 25.TCP flag - ACK 24.TCP flag - PSH 23.TCP flag - RST 22.TCP flag - SYN 21.TCP flag - FIN 20.reserved 19.Ethertype 18.Ttl 17.TtlEqualOne Tunnel header fields(not used for non-encasulated packet): 16.Source MAC 15.Destination MAC 14.VLAN ? Tag 1 13.Provider VLAN ? Tag 0 12.Priority taken from CVLAN tag or the SVLAN tag based on GFTTunnelVlanSelect global 11.Source IP 10.Destination IP 9.Over IP protocol 8.DSCP 7.Source port or ICMP type 6.Destination port or ICMP code 5.Ethertype 4.Ttl 3.TtlEqualOne 2.Entrophy : GENEVE, VXLAN ? source UDP port number,  NVGRE ? FlowID (key 8LBS bits)  1:0 vlan select 0: inner Provider VLAN 1: inner VLAN 2: outer Provider VLAN 3: outer  VLAN  Chips: BB_B0 K2
36261 #define PRS_REG_GFT_PROFILE_MASK_RAM_SIZE                                                            64
36262 #define PRS_REG_GFT_CAM                                                                              0x1f1100UL //Access:RW   DataWidth:0x1d  Used to set the values of the GFT profile cam: 0 ?valid, zero at reset 1-14 data 14-11 PF ID (3bit BB 4bit K2) 10-7 Tunnel type (4b) 0000-no tunnel 0001-vxlan 0010-GRE MAC / NVGRE 0011-GRE IP 0100-Genve MAC 0101-Genve IP 1000-1111 ? reserved   6-3 upper protocol type (4b):  -  by priority 0 is highest  0000 ? RoCE 0001 ? RoCE v2 0010 ? FCoE 0011 ? ICMP 0100 ? ARP 0101 ? User TCP Source Port 1(inner) 0110 ? User TCP Destination Port 1(inner) 0111 ? TCP 1000 ? User UDP Destination Port 1(inner) 1001 ? User UDP Destination Port 2(outer) 1010 ? UDP 1011 ? User IP Protocol 1(inner) 1100 ? User IP Protocol 2(outer) 1101 ? User ETH Type 1 (inner) 1110 ? User ETH Type 2 (outer) 1111 ? RAW   - by priority  2 Tunnel IP version  0-v4 1-v6 1 IP version  0-v4 1-v6 15-28 mask of bits 1-14 resepectively , ?1?- compare, ?0?-don?t compare. All the CAM should be initialized in order to prevent false parity error while doing scrubbing. the init value: bits[28-1] - Don't care bit[0](valid) - 1'b0  Chips: BB_B0 K2
36263 #define PRS_REG_GFT_CAM_SIZE                                                                         31
36264 #define PRS_REG_GFT_HASH_KEY_0                                                                       0x1f1180UL //Access:RW   DataWidth:0x20    Chips: BB_B0 K2
36265 #define PRS_REG_GFT_HASH_KEY_1                                                                       0x1f1184UL //Access:RW   DataWidth:0x20    Chips: BB_B0 K2
36266 #define PRS_REG_GFT_HASH_KEY_2                                                                       0x1f1188UL //Access:RW   DataWidth:0x20    Chips: BB_B0 K2
36267 #define PRS_REG_GFT_HASH_KEY_3                                                                       0x1f118cUL //Access:RW   DataWidth:0x20    Chips: BB_B0 K2
36268 #define PRS_REG_GFT_HASH_KEY_4                                                                       0x1f1190UL //Access:RW   DataWidth:0x20    Chips: BB_B0 K2
36269 #define PRS_REG_GFT_TCP_SOURCE_PORT_1                                                                0x1f1194UL //Access:RW   DataWidth:0x10  tcp source port for the gft profile key upper protocol type  Chips: BB_B0 K2
36270 #define PRS_REG_GFT_TCP_DESTINATION_PORT_1                                                           0x1f1198UL //Access:RW   DataWidth:0x10  tcp inner destination port for the gft profile key upper protocol type  Chips: BB_B0 K2
36271 #define PRS_REG_GFT_UDP_DESTINATION_PORT_1                                                           0x1f119cUL //Access:RW   DataWidth:0x10  udp inner destination port for the gft profile key upper protocol type  Chips: BB_B0 K2
36272 #define PRS_REG_GFT_UDP_DESTINATION_PORT_2                                                           0x1f11a0UL //Access:RW   DataWidth:0x10  udp outer destination port for the gft profile key upper protocol type  Chips: BB_B0 K2
36273 #define PRS_REG_GFT_IP_PROTOCOL_1                                                                    0x1f11a4UL //Access:RW   DataWidth:0x8   inner ip protocol for the gft profile key upper protocol type  Chips: BB_B0 K2
36274 #define PRS_REG_GFT_IP_PROTOCOL_2                                                                    0x1f11a8UL //Access:RW   DataWidth:0x8   outer ip protocol for the gft profile key upper protocol type  Chips: BB_B0 K2
36275 #define PRS_REG_GFT_ETH_TYPE_1                                                                       0x1f11acUL //Access:RW   DataWidth:0x10  inner ethernet type for the gft profile key upper protocol type  Chips: BB_B0 K2
36276 #define PRS_REG_GFT_ETH_TYPE_2                                                                       0x1f11b0UL //Access:RW   DataWidth:0x10  outer ethernet type for the gft profile key upper protocol type  Chips: BB_B0 K2
36277 #define PRS_REG_GFT_INNER_VLAN_SELECT                                                                0x1f11b4UL //Access:RW   DataWidth:0x1   used to build the priority field in the GFT used frame fields inner header 0- use CVLAN priority 1- use SVLAN priority  Chips: BB_B0 K2
36278 #define PRS_REG_GFT_TUNNEL_VLAN_SELECT                                                               0x1f11b8UL //Access:RW   DataWidth:0x1   used to build the priority field in the GFT used frame fields tunnel header 0- use CVLAN priority 1- use SVLAN priority  Chips: BB_B0 K2
36279 #define PRS_REG_SEARCH_GFT                                                                           0x1f11bcUL //Access:RW   DataWidth:0x1   Per-PF: Enables gft search for all packet types.  Chips: BB_B0 K2
36280 #define PRS_REG_SEARCH_NON_IP_AS_GFT                                                                 0x1f11c0UL //Access:RW   DataWidth:0x1   Per-PF: Enables gft search for non-IP packets. Only valid if search_gft is also set.  Chips: BB_B0 K2
36281 #define PRS_REG_GFT_CONNECTION_TYPE                                                                  0x1f11c4UL //Access:RW   DataWidth:0x4   connection type for gft, if the connection type returned in the search response equal to this value, use the CM_HDR_GFT intead of CM_HDR_EVENT_ID_X in the CM header. is also set.  Chips: BB_B0 K2
36282 #define PRS_REG_CM_HDR_GFT                                                                           0x1f11c8UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_B0 K2
36283     #define PRS_REG_CM_HDR_GFT_EVENT_ID                                                              (0xff<<0) // Event ID for Match Offload/ Match L2 filter packets and gft connection type
36284     #define PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT                                                        0
36285     #define PRS_REG_CM_HDR_GFT_CM_HDR                                                                (0x3ff<<8) // The CM header for Match Offload/ Match L2 filter packets and gft connection type . Used in packet start message to TCM.  9 - UseStateFlg; 8 - SmCtxLdStFlg; 7 - AggCtxLdStFlg; 6:4 - XXLockCmd, 3:0 - AggCtxPartSize.
36286     #define PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT                                                          8
36287 #define PRS_REG_GFT_CAM_SCRUB_HIT_EN                                                                 0x1f11ccUL //Access:RW   DataWidth:0x1   When set to 1 the gft cam hit parity scrubbing feature is enabled.  Chips: BB_B0 K2
36288 #define PRS_REG_GFT_CAM_SCRUB_MISS_EN                                                                0x1f11d0UL //Access:RW   DataWidth:0x1   When set to 1 the gft cam miss parity scrubbing feature is enabled.  Chips: BB_B0 K2
36289 #define XMAC_REG_CTRL                                                                                0x210000UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36290     #define XMAC_REG_CTRL_TX_EN                                                                      (0x1<<0) // Transmit enable.
36291     #define XMAC_REG_CTRL_TX_EN_SHIFT                                                                0
36292     #define XMAC_REG_CTRL_RX_EN                                                                      (0x1<<1) // Receive enable.
36293     #define XMAC_REG_CTRL_RX_EN_SHIFT                                                                1
36294     #define XMAC_REG_CTRL_LINE_LOCAL_LPBK                                                            (0x1<<2) // Local loopback from TX to RX. This loopback is on the line side after clock domain crossing - from the last TX pipeline stage to the first RX pipeline stage.
36295     #define XMAC_REG_CTRL_LINE_LOCAL_LPBK_SHIFT                                                      2
36296     #define XMAC_REG_CTRL_CORE_LOCAL_LPBK                                                            (0x1<<3) // Local loopback from TX to RX. This loopback is on the core side before clock domain crossing - from the first TX pipeline stage to the last RX pipeline stage.
36297     #define XMAC_REG_CTRL_CORE_LOCAL_LPBK_SHIFT                                                      3
36298     #define XMAC_REG_CTRL_LINE_REMOTE_LPBK                                                           (0x1<<4) // Remote loopback from RX to TX. This loopback is on the line side before clock domain crossing - from the first RX pipeline stage to the last TX pipeline stage.
36299     #define XMAC_REG_CTRL_LINE_REMOTE_LPBK_SHIFT                                                     4
36300     #define XMAC_REG_CTRL_CORE_REMOTE_LPBK                                                           (0x1<<5) // Remote loopback from RX to TX. This loopback is on the core side after clock domain crossing - from the last RX pipeline stage to the first TX pipeline stage.
36301     #define XMAC_REG_CTRL_CORE_REMOTE_LPBK_SHIFT                                                     5
36302     #define XMAC_REG_CTRL_SOFT_RESET                                                                 (0x1<<6) // Resets the MAC logic annd status registers only.
36303     #define XMAC_REG_CTRL_SOFT_RESET_SHIFT                                                           6
36304     #define XMAC_REG_CTRL_XLGMII_ALIGN_ENB                                                           (0x1<<7) // Enables SOP; SOM & Sequence alignment to 8 byte boundaries; as defined in 40G mode.
36305     #define XMAC_REG_CTRL_XLGMII_ALIGN_ENB_SHIFT                                                     7
36306     #define XMAC_REG_CTRL_LOCAL_LPBK_LEAK_ENB                                                        (0x1<<8) // If set; during either of the local loopback modes; the transmit packets are also sent to the TX Warpcore interface; apart from the loopback operation.
36307     #define XMAC_REG_CTRL_LOCAL_LPBK_LEAK_ENB_SHIFT                                                  8
36308     #define XMAC_REG_CTRL_REMOTE_LPBK_LEAK_ENB                                                       (0x1<<9) // If set; during either of the remote loopback modes; the received packets are also sent to the RX Port interface; apart from the loopback operation.
36309     #define XMAC_REG_CTRL_REMOTE_LPBK_LEAK_ENB_SHIFT                                                 9
36310     #define XMAC_REG_CTRL_RS_SOFT_RESET                                                              (0x1<<10) // Resets the RS layer functionality - fault handling.
36311     #define XMAC_REG_CTRL_RS_SOFT_RESET_SHIFT                                                        10
36312     #define XMAC_REG_CTRL_XGMII_IPG_CHECK_DISABLE                                                    (0x1<<11) // If set; this will override the one column idle/sequence ordered set check before SOP in XGMII mode - effectively supporting 1 byte IPG in XGMII mode.
36313     #define XMAC_REG_CTRL_XGMII_IPG_CHECK_DISABLE_SHIFT                                              11
36314     #define XMAC_REG_CTRL_SW_LINK_STATUS                                                             (0x1<<12) // Link status indication from Software. If set; indicates that link is active. When this transitions from 0 to 1; EEE FSM waits for 1 second before it starts its operation.
36315     #define XMAC_REG_CTRL_SW_LINK_STATUS_SHIFT                                                       12
36316     #define XMAC_REG_CTRL_LINK_STATUS_SELECT                                                         (0x1<<13) // This is the link status mux select signal to choose between link status indication from software or the link status indication from the strap pin. If reset; it selects the software link status which is also the default value.
36317     #define XMAC_REG_CTRL_LINK_STATUS_SELECT_SHIFT                                                   13
36318 #define XMAC_REG_MODE                                                                                0x210008UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36319     #define XMAC_REG_MODE_HDR_MODE                                                                   (0x7<<0) // Packet Header mode.
36320     #define XMAC_REG_MODE_HDR_MODE_SHIFT                                                             0
36321     #define XMAC_REG_MODE_NO_SOP_FOR_CRC_HG                                                          (0x1<<3) // If set; exclude the SOP byte for CRC calculation in HG modes.
36322     #define XMAC_REG_MODE_NO_SOP_FOR_CRC_HG_SHIFT                                                    3
36323     #define XMAC_REG_MODE_SPEED_MODE                                                                 (0x7<<4) // Port Speed.
36324     #define XMAC_REG_MODE_SPEED_MODE_SHIFT                                                           4
36325 #define XMAC_REG_XMAC_SPARE0                                                                         0x210010UL //Access:RW   DataWidth:0x20  SPARE REGISTERS 0.  Chips: BB_A0 BB_B0 K2
36326 #define XMAC_REG_XMAC_SPARE1                                                                         0x210018UL //Access:RW   DataWidth:0x2   SPARE REGISTERS 0.  Chips: BB_A0 BB_B0 K2
36327 #define XMAC_REG_TX_CTRL_LO                                                                          0x210020UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36328     #define XMAC_REG_TX_CTRL_LO_CRC_MODE                                                             (0x3<<0) // CRC mode for Transmit Side.
36329     #define XMAC_REG_TX_CTRL_LO_CRC_MODE_SHIFT                                                       0
36330     #define XMAC_REG_TX_CTRL_LO_DISCARD                                                              (0x1<<2) // Accept packets from the host but do not transmit.
36331     #define XMAC_REG_TX_CTRL_LO_DISCARD_SHIFT                                                        2
36332     #define XMAC_REG_TX_CTRL_LO_TX_ANY_START                                                         (0x1<<3) // Don't force the first byte of a packet to be /Start.
36333     #define XMAC_REG_TX_CTRL_LO_TX_ANY_START_SHIFT                                                   3
36334     #define XMAC_REG_TX_CTRL_LO_PAD_EN                                                               (0x1<<4) // Enable XMAC to pad runt packets on the Tx.
36335     #define XMAC_REG_TX_CTRL_LO_PAD_EN_SHIFT                                                         4
36336     #define XMAC_REG_TX_CTRL_LO_PAD_THRESHOLD                                                        (0x7f<<5) // If padding is enabled; packets less than this size are padded to get to this size.
36337     #define XMAC_REG_TX_CTRL_LO_PAD_THRESHOLD_SHIFT                                                  5
36338     #define XMAC_REG_TX_CTRL_LO_AVERAGE_IPG                                                          (0x7f<<12) // Average interpacket gap. Must be >=8.
36339     #define XMAC_REG_TX_CTRL_LO_AVERAGE_IPG_SHIFT                                                    12
36340     #define XMAC_REG_TX_CTRL_LO_THROT_NUM                                                            (0x3f<<19) // Number of bytes of extra IPG added whenever txThrotDemon bytes have been transmitted.
36341     #define XMAC_REG_TX_CTRL_LO_THROT_NUM_SHIFT                                                      19
36342     #define XMAC_REG_TX_CTRL_LO_THROT_DENOM_LO                                                       (0x7f<<25) // Lower 8 bits of throt_denom register. Number of bytes to transmite before adding txThrotNumer bytes to the IPG.
36343     #define XMAC_REG_TX_CTRL_LO_THROT_DENOM_LO_SHIFT                                                 25
36344 #define XMAC_REG_TX_CTRL_HI                                                                          0x210024UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36345     #define XMAC_REG_TX_CTRL_HI_THROT_DENOM_HI                                                       (0x1<<0) // Upper 8 bits of throt_denom register. Number of bytes to transmite before adding txThrotNumer bytes to the IPG.
36346     #define XMAC_REG_TX_CTRL_HI_THROT_DENOM_HI_SHIFT                                                 0
36347     #define XMAC_REG_TX_CTRL_HI_TX_PREAMBLE_LENGTH                                                   (0xf<<1) // Number of preamble bytes for transmit IEEE packets; this value should include the K.SOP & SFD character as well.
36348     #define XMAC_REG_TX_CTRL_HI_TX_PREAMBLE_LENGTH_SHIFT                                             1
36349     #define XMAC_REG_TX_CTRL_HI_TX_64BYTE_BUFFER_EN                                                  (0x1<<5) // If enabled; XMAC buffers 64 bytes per packet; before starting transmission of the packet on the line side; helps to prevent underflow issues.
36350     #define XMAC_REG_TX_CTRL_HI_TX_64BYTE_BUFFER_EN_SHIFT                                            5
36351 #define XMAC_REG_CTRL_SA_LO                                                                          0x210028UL //Access:RW   DataWidth:0x20  Lower 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets transmitted by the MAC.  Chips: BB_A0 BB_B0 K2
36352 #define XMAC_REG_CTRL_SA_HI                                                                          0x21002cUL //Access:RW   DataWidth:0x10  Upper 48 bits of ctrl_sa register. Used as the SA in PAUSE/PFC packets transmitted by the MAC.  Chips: BB_A0 BB_B0 K2
36353 #define XMAC_REG_RX_CTRL                                                                             0x210030UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36354     #define XMAC_REG_RX_CTRL_RX_PASS_CTRL                                                            (0x1<<0) // Mac Control packets are passed to the system.
36355     #define XMAC_REG_RX_CTRL_RX_PASS_CTRL_SHIFT                                                      0
36356     #define XMAC_REG_RX_CTRL_RX_ANY_START                                                            (0x1<<1) // True to allow any non-Idle character to start a packet.
36357     #define XMAC_REG_RX_CTRL_RX_ANY_START_SHIFT                                                      1
36358     #define XMAC_REG_RX_CTRL_STRIP_CRC                                                               (0x1<<2) // CRC is checked; then stripped from the received packet.
36359     #define XMAC_REG_RX_CTRL_STRIP_CRC_SHIFT                                                         2
36360     #define XMAC_REG_RX_CTRL_STRICT_PREAMBLE                                                         (0x1<<3) // If set; the MAC checks for IEEE Ethernet format premable - K.SOP + 5 '55' premable bytes + 'D5' SFD character - if this sequence is missing it is treated as an errored packet.
36361     #define XMAC_REG_RX_CTRL_STRICT_PREAMBLE_SHIFT                                                   3
36362     #define XMAC_REG_RX_CTRL_RUNT_THRESHOLD                                                          (0x7f<<4) // The runt threshold; below which the packets are discarded.
36363     #define XMAC_REG_RX_CTRL_RUNT_THRESHOLD_SHIFT                                                    4
36364     #define XMAC_REG_RX_CTRL_RECEIVE_18_BYTE_PKTS                                                    (0x1<<11) // If set; the minimum receive packet size is reduced to 18 bytes from the default 33 bytes - Should be used in MACSEC chips with IEEE mode only.
36365     #define XMAC_REG_RX_CTRL_RECEIVE_18_BYTE_PKTS_SHIFT                                              11
36366     #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE                                               (0x1<<12) // If set; the MAC parses the frame from K.SOP onwards to look for the SFD character and then processes the packet. If disabled; treats the first 8 bytes of packet as preamble.
36367     #define XMAC_REG_RX_CTRL_PROCESS_VARIABLE_PREAMBLE_SHIFT                                         12
36368 #define XMAC_REG_RX_SA_LO                                                                            0x210038UL //Access:RW   DataWidth:0x20  Lower 48 bits of rx_sa register. SA recognized for MAC control packets in addition to the standard 0x0180C2000001.  Chips: BB_A0 BB_B0 K2
36369 #define XMAC_REG_RX_SA_HI                                                                            0x21003cUL //Access:RW   DataWidth:0x10  Upper 48 bits of rx_sa register. SA recognized for MAC control packets in addition to the standard 0x0180C2000001.  Chips: BB_A0 BB_B0 K2
36370 #define XMAC_REG_RX_MAX_SIZE                                                                         0x210040UL //Access:RW   DataWidth:0xe   Maximum packet size in receive direction; exclusive of preamble & CRC in strip mode.  Chips: BB_A0 BB_B0 K2
36371 #define XMAC_REG_RX_VLAN_TAG_LO                                                                      0x210048UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36372     #define XMAC_REG_RX_VLAN_TAG_LO_INNER_VLAN_TAG                                                   (0xffff<<0) // Type field for Inner VLAN tag.
36373     #define XMAC_REG_RX_VLAN_TAG_LO_INNER_VLAN_TAG_SHIFT                                             0
36374     #define XMAC_REG_RX_VLAN_TAG_LO_OUTER_VLAN_TAG                                                   (0xffff<<16) // Type field for Outer VLAN tag.
36375     #define XMAC_REG_RX_VLAN_TAG_LO_OUTER_VLAN_TAG_SHIFT                                             16
36376 #define XMAC_REG_RX_VLAN_TAG_HI                                                                      0x21004cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36377     #define XMAC_REG_RX_VLAN_TAG_HI_INNER_VLAN_TAG_ENABLE                                            (0x1<<0) // Enables VLAN tag detection using the INNER_VLAN_TAG.
36378     #define XMAC_REG_RX_VLAN_TAG_HI_INNER_VLAN_TAG_ENABLE_SHIFT                                      0
36379     #define XMAC_REG_RX_VLAN_TAG_HI_OUTER_VLAN_TAG_ENABLE                                            (0x1<<1) // Enables VLAN tag detection using the OUTER_VLAN_TAG.
36380     #define XMAC_REG_RX_VLAN_TAG_HI_OUTER_VLAN_TAG_ENABLE_SHIFT                                      1
36381 #define XMAC_REG_RX_LSS_CTRL                                                                         0x210050UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36382     #define XMAC_REG_RX_LSS_CTRL_LOCAL_FAULT_DISABLE                                                 (0x1<<0) // True to disable enable processing of LSS message type: Local Fault. When clear and a local fault LSS message is received; a continuous stream of 'Remote Fault' LSS messages will be transmitted to the link partner.
36383     #define XMAC_REG_RX_LSS_CTRL_LOCAL_FAULT_DISABLE_SHIFT                                           0
36384     #define XMAC_REG_RX_LSS_CTRL_REMOTE_FAULT_DISABLE                                                (0x1<<1) // True to disable processing of LSS message type: Remote Fault. When clear and a remote fault LSS message is received; a continuous stream of IDLES will be transmitted to the link partner.
36385     #define XMAC_REG_RX_LSS_CTRL_REMOTE_FAULT_DISABLE_SHIFT                                          1
36386     #define XMAC_REG_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX                                          (0x1<<2) // If set; the TX faults inputs are used to send out fault sequences - else receive faults are used -- used by MACSEC PHY chips.
36387     #define XMAC_REG_RX_LSS_CTRL_USE_EXTERNAL_FAULTS_FOR_TX_SHIFT                                    2
36388     #define XMAC_REG_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE                                           (0x1<<3) // True to disable processing of LSS message type: Link Interruption. When clear and a Link Interruption LSS message is received; a continuous stream of IDLES will be transmitted to the link partner.
36389     #define XMAC_REG_RX_LSS_CTRL_LINK_INTERRUPTION_DISABLE_SHIFT                                     3
36390     #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT                                         (0x1<<4) // If set; the transmit data is dropped on detection of local fault on the receive side. If reset; transmit data is stalled on detection of local fault.
36391     #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LOCAL_FAULT_SHIFT                                   4
36392     #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT                                        (0x1<<5) // If set; the transmit data is dropped on detection of remote fault on the receive side. If reset; transmit data is stalled on detection of remote fault.
36393     #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_REMOTE_FAULT_SHIFT                                  5
36394     #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT                                      (0x1<<6) // If set; the transmit data is dropped on detection of link interruption on the receive side. If reset; transmit data is stalled on detection of link interruption.
36395     #define XMAC_REG_RX_LSS_CTRL_DROP_TX_DATA_ON_LINK_INTERRUPT_SHIFT                                6
36396     #define XMAC_REG_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN                              (0x1<<7) // If set; the Receive LPause; PFC & LLFC timers are reset whenever the link status is down; or we receive local or remote faults.
36397     #define XMAC_REG_RX_LSS_CTRL_RESET_FLOW_CONTROL_TIMERS_ON_LINK_DOWN_SHIFT                        7
36398 #define XMAC_REG_RX_LSS_STATUS                                                                       0x210058UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36399     #define XMAC_REG_RX_LSS_STATUS_LOCAL_FAULT_STATUS                                                (0x1<<0) // True while 'local fault' LSS messages are being received.
36400     #define XMAC_REG_RX_LSS_STATUS_LOCAL_FAULT_STATUS_SHIFT                                          0
36401     #define XMAC_REG_RX_LSS_STATUS_REMOTE_FAULT_STATUS                                               (0x1<<1) // True while 'remote fault' LSS messages are being received.
36402     #define XMAC_REG_RX_LSS_STATUS_REMOTE_FAULT_STATUS_SHIFT                                         1
36403     #define XMAC_REG_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS                                          (0x1<<2) // True while 'Link Interruption' LSS messages are being received.
36404     #define XMAC_REG_RX_LSS_STATUS_LINK_INTERRUPTION_STATUS_SHIFT                                    2
36405 #define XMAC_REG_CLEAR_RX_LSS_STATUS                                                                 0x210060UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36406     #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS                                    (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky LOCAL_FAULT_STATUS bit.
36407     #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LOCAL_FAULT_STATUS_SHIFT                              0
36408     #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS                                   (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky REMOTE_FAULT_STATUS bit.
36409     #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_REMOTE_FAULT_STATUS_SHIFT                             1
36410     #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS                              (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky LINK_INTERRUPTION_STATUS bit.
36411     #define XMAC_REG_CLEAR_RX_LSS_STATUS_CLEAR_LINK_INTERRUPTION_STATUS_SHIFT                        2
36412 #define XMAC_REG_PAUSE_CTRL_LO                                                                       0x210068UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36413     #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_TIMER                                               (0xffff<<0) // This field is Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
36414     #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_TIMER_SHIFT                                         0
36415     #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_EN                                                  (0x1<<16) // If set; enables the pause regen functionality.
36416     #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_REFRESH_EN_SHIFT                                            16
36417     #define XMAC_REG_PAUSE_CTRL_LO_TX_PAUSE_EN                                                       (0x1<<17) // Send PAUSE packets whenever TxPause input is true.
36418     #define XMAC_REG_PAUSE_CTRL_LO_TX_PAUSE_EN_SHIFT                                                 17
36419     #define XMAC_REG_PAUSE_CTRL_LO_RX_PAUSE_EN                                                       (0x1<<18) // Process PAUSE Frames in the receive direction.
36420     #define XMAC_REG_PAUSE_CTRL_LO_RX_PAUSE_EN_SHIFT                                                 18
36421     #define XMAC_REG_PAUSE_CTRL_LO_RX_PASS_PAUSE                                                     (0x1<<19) // Send PAUSE frames to the system side.
36422     #define XMAC_REG_PAUSE_CTRL_LO_RX_PASS_PAUSE_SHIFT                                               19
36423     #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_GMII_ON_TX_LINE_SIDE                                        (0x1<<20) // If set; the recive pause is used to stop the frame transmission in the GMII convertor block; to reduce the Pause commencement latency.
36424     #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_GMII_ON_TX_LINE_SIDE_SHIFT                                  20
36425     #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_XOFF_TIMER_LO                                               (0x7ff<<21) // Lower 16 bits of pause_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).
36426     #define XMAC_REG_PAUSE_CTRL_LO_PAUSE_XOFF_TIMER_LO_SHIFT                                         21
36427 #define XMAC_REG_PAUSE_XOFF_TIMER_HI                                                                 0x21006cUL //Access:RW   DataWidth:0x5   Upper 16 bits of pause_xoff_timer register. Time value sent in the Timer Field for XOFF state (Unit is 512 bit-times).  Chips: BB_A0 BB_B0 K2
36428 #define XMAC_REG_PFC_CTRL_LO                                                                         0x210070UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36429     #define XMAC_REG_PFC_CTRL_LO_PFC_REFRESH_TIMER                                                   (0xffff<<0) // Threshold for pause timer to cause XOFF to be resent (Unit is 512 bit-times).
36430     #define XMAC_REG_PFC_CTRL_LO_PFC_REFRESH_TIMER_SHIFT                                             0
36431     #define XMAC_REG_PFC_CTRL_LO_PFC_XOFF_TIMER                                                      (0xffff<<16) // Time value sent in the Timer Field for classes in XOFF state (Unit is 512 bit-times).
36432     #define XMAC_REG_PFC_CTRL_LO_PFC_XOFF_TIMER_SHIFT                                                16
36433 #define XMAC_REG_PFC_CTRL_HI                                                                         0x210074UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36434     #define XMAC_REG_PFC_CTRL_HI_PFC_REFRESH_EN                                                      (0x1<<0) // Enable automatic re-send of PFC packet after a period time determined by PFC_REFRESH_TIMER.
36435     #define XMAC_REG_PFC_CTRL_HI_PFC_REFRESH_EN_SHIFT                                                0
36436     #define XMAC_REG_PFC_CTRL_HI_FORCE_PFC_XON                                                       (0x1<<1) // Instructs the MAC to send XON for all Classes of Service.
36437     #define XMAC_REG_PFC_CTRL_HI_FORCE_PFC_XON_SHIFT                                                 1
36438     #define XMAC_REG_PFC_CTRL_HI_RX_PASS_PFC                                                         (0x1<<2) // Set to pass RX PFC frame to core I/F.
36439     #define XMAC_REG_PFC_CTRL_HI_RX_PASS_PFC_SHIFT                                                   2
36440     #define XMAC_REG_PFC_CTRL_HI_PFC_STATS_EN                                                        (0x1<<3) // Set to enable incrementing IRXPP and ITXPP.
36441     #define XMAC_REG_PFC_CTRL_HI_PFC_STATS_EN_SHIFT                                                  3
36442     #define XMAC_REG_PFC_CTRL_HI_RX_PFC_EN                                                           (0x1<<4) // PFC RX enable.
36443     #define XMAC_REG_PFC_CTRL_HI_RX_PFC_EN_SHIFT                                                     4
36444     #define XMAC_REG_PFC_CTRL_HI_TX_PFC_EN                                                           (0x1<<5) // PFC TX enable.
36445     #define XMAC_REG_PFC_CTRL_HI_TX_PFC_EN_SHIFT                                                     5
36446 #define XMAC_REG_PFC_ETH_TYPE                                                                        0x210078UL //Access:RW   DataWidth:0x10  The PFC packet generation and detection uses this Ethertype value.  Chips: BB_A0 BB_B0 K2
36447 #define XMAC_REG_PFC_OPCODE                                                                          0x210080UL //Access:RW   DataWidth:0x10  The PFC packet generation and detection uses this Ethertype value.  Chips: BB_A0 BB_B0 K2
36448 #define XMAC_REG_PFC_MACDA_LO                                                                        0x210088UL //Access:RW   DataWidth:0x20  Lower 48 bits of pfc_macda register. Used as the DA in PFC packets transmitted by the MAC.  Chips: BB_A0 BB_B0 K2
36449 #define XMAC_REG_PFC_MACDA_HI                                                                        0x21008cUL //Access:RW   DataWidth:0x10  Upper 48 bits of pfc_macda register. Used as the DA in PFC packets transmitted by the MAC.  Chips: BB_A0 BB_B0 K2
36450 #define XMAC_REG_LLFC_CTRL                                                                           0x210090UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36451     #define XMAC_REG_LLFC_CTRL_TX_LLFC_EN                                                            (0x1<<0) // This bit enables llfc for Tx path in XMAC; works with llfc_en in xport.
36452     #define XMAC_REG_LLFC_CTRL_TX_LLFC_EN_SHIFT                                                      0
36453     #define XMAC_REG_LLFC_CTRL_RX_LLFC_EN                                                            (0x1<<1) // This bit enables llfc for Rx path in XMAC; works with llfc_en in xport.
36454     #define XMAC_REG_LLFC_CTRL_RX_LLFC_EN_SHIFT                                                      1
36455     #define XMAC_REG_LLFC_CTRL_LLFC_IN_IPG_ONLY                                                      (0x1<<2) // When set; LLFC is inserted only during IPG.
36456     #define XMAC_REG_LLFC_CTRL_LLFC_IN_IPG_ONLY_SHIFT                                                2
36457     #define XMAC_REG_LLFC_CTRL_LLFC_CUT_THROUGH_MODE                                                 (0x1<<3) // When set and llfc_in_ipg_only =0; GXPORT operates in cut-through mode.
36458     #define XMAC_REG_LLFC_CTRL_LLFC_CUT_THROUGH_MODE_SHIFT                                           3
36459     #define XMAC_REG_LLFC_CTRL_LLFC_CRC_IGNORE                                                       (0x1<<4) // This bit if set to 1; disables the crc check for incoming llfc messages.
36460     #define XMAC_REG_LLFC_CTRL_LLFC_CRC_IGNORE_SHIFT                                                 4
36461     #define XMAC_REG_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC                                                   (0x1<<5) // When set; LLFC crc calculation does not involve SOM.
36462     #define XMAC_REG_LLFC_CTRL_NO_SOM_FOR_CRC_LLFC_SHIFT                                             5
36463     #define XMAC_REG_LLFC_CTRL_LLFC_IMG                                                              (0xff<<6) // The minimum Inter Message gap that must be observed between 2 HG2 Messages.
36464     #define XMAC_REG_LLFC_CTRL_LLFC_IMG_SHIFT                                                        6
36465 #define XMAC_REG_TX_LLFC_MSG_FIELDS                                                                  0x210098UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36466     #define XMAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL                                     (0xff<<0) // Value used for dw0_byte1 of outgoing LLFC message.
36467     #define XMAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_MSG_TYPE_LOGICAL_SHIFT                               0
36468     #define XMAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL                                       (0xf<<8) // Value used for dw1_byte0 of outgoing LLFC message.
36469     #define XMAC_REG_TX_LLFC_MSG_FIELDS_TX_LLFC_FC_OBJ_LOGICAL_SHIFT                                 8
36470     #define XMAC_REG_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME                                               (0xffff<<12) // Value used for DW2_byte2 and DW2_byte3 of the outgoing LLFC messages.
36471     #define XMAC_REG_TX_LLFC_MSG_FIELDS_LLFC_XOFF_TIME_SHIFT                                         12
36472 #define XMAC_REG_RX_LLFC_MSG_FIELDS                                                                  0x2100a0UL //Access:RW   DataWidth:0x18  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36473     #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL                                     (0xff<<0) // Value used to decode dw0_byte1 of incoming LLFC message.
36474     #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_LOGICAL_SHIFT                               0
36475     #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL                                       (0xf<<8) // Value used to decode dw1_byte0 of incoming LLFC message.
36476     #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_LOGICAL_SHIFT                                 8
36477     #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL                                    (0xff<<12) // Value used to decode dw0_byte1 of incoming PLFC message.
36478     #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_MSG_TYPE_PHYSICAL_SHIFT                              12
36479     #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL                                      (0xf<<20) // Value used to decode dw1_byte0 of incoming PLFC message.
36480     #define XMAC_REG_RX_LLFC_MSG_FIELDS_RX_LLFC_FC_OBJ_PHYSICAL_SHIFT                                20
36481 #define XMAC_REG_HCFC_CTRL                                                                           0x2100a8UL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36482     #define XMAC_REG_HCFC_CTRL_TX_HCFC_EN                                                            (0x1<<0) // This bit enables HCFC for Tx path in XMAC.
36483     #define XMAC_REG_HCFC_CTRL_TX_HCFC_EN_SHIFT                                                      0
36484     #define XMAC_REG_HCFC_CTRL_RX_HCFC_EN                                                            (0x1<<1) // This bit enables HCFC for Rx path in XMAC.
36485     #define XMAC_REG_HCFC_CTRL_RX_HCFC_EN_SHIFT                                                      1
36486     #define XMAC_REG_HCFC_CTRL_HCFC_CRC_IGNORE                                                       (0x1<<2) // The crc check for HCFC messages is ignored if this bit is set.
36487     #define XMAC_REG_HCFC_CTRL_HCFC_CRC_IGNORE_SHIFT                                                 2
36488     #define XMAC_REG_HCFC_CTRL_NO_SOM_FOR_CRC_HCFC                                                   (0x1<<3) // When set; HCFC CRC calculation does not involve SOM.
36489     #define XMAC_REG_HCFC_CTRL_NO_SOM_FOR_CRC_HCFC_SHIFT                                             3
36490     #define XMAC_REG_HCFC_CTRL_HCFC_IN_IPG_ONLY                                                      (0x1<<4) // If 1; the HCFC packets are sent during IPG; else sent preemptively.
36491     #define XMAC_REG_HCFC_CTRL_HCFC_IN_IPG_ONLY_SHIFT                                                4
36492     #define XMAC_REG_HCFC_CTRL_HCFC_SOM                                                              (0xff<<5) // Sets the new value for the SOM of the HCFC messages.
36493     #define XMAC_REG_HCFC_CTRL_HCFC_SOM_SHIFT                                                        5
36494     #define XMAC_REG_HCFC_CTRL_HCFC_IMG                                                              (0xff<<13) // The minimum Inter Message gap between 2 HCFC Messages.
36495     #define XMAC_REG_HCFC_CTRL_HCFC_IMG_SHIFT                                                        13
36496 #define XMAC_REG_FIFO_STATUS                                                                         0x2100c0UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36497     #define XMAC_REG_FIFO_STATUS_RX_PKT_OVERFLOW                                                     (0x1<<0) // Indicates rx packet fifo overflow.
36498     #define XMAC_REG_FIFO_STATUS_RX_PKT_OVERFLOW_SHIFT                                               0
36499     #define XMAC_REG_FIFO_STATUS_RX_MSG_OVERFLOW                                                     (0x1<<1) // Indicates rx message fifo overflow.
36500     #define XMAC_REG_FIFO_STATUS_RX_MSG_OVERFLOW_SHIFT                                               1
36501     #define XMAC_REG_FIFO_STATUS_TX_PKT_UNDERFLOW                                                    (0x1<<2) // Indicates tx packet fifo underflow.
36502     #define XMAC_REG_FIFO_STATUS_TX_PKT_UNDERFLOW_SHIFT                                              2
36503     #define XMAC_REG_FIFO_STATUS_TX_PKT_OVERFLOW                                                     (0x1<<3) // Indicates tx packet fifo overflow.
36504     #define XMAC_REG_FIFO_STATUS_TX_PKT_OVERFLOW_SHIFT                                               3
36505     #define XMAC_REG_FIFO_STATUS_TX_HCFC_MSG_OVERFLOW                                                (0x1<<4) // Indicates tx HCFC message fifo overflow.
36506     #define XMAC_REG_FIFO_STATUS_TX_HCFC_MSG_OVERFLOW_SHIFT                                          4
36507     #define XMAC_REG_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW                                                (0x1<<5) // Indicates tx LLFC message fifo overflow.
36508     #define XMAC_REG_FIFO_STATUS_TX_LLFC_MSG_OVERFLOW_SHIFT                                          5
36509     #define XMAC_REG_FIFO_STATUS_LINK_STATUS                                                         (0x1<<7) // This bit indicates the link status used by XMAC EEE. This is continuously updated. If set; indicates that link is active.
36510     #define XMAC_REG_FIFO_STATUS_LINK_STATUS_SHIFT                                                   7
36511 #define XMAC_REG_CLEAR_FIFO_STATUS                                                                   0x2100c8UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36512     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW                                         (0x1<<0) // A rising edge on this register bit (0->1); clears the sticky RX_PKT_OVERFLOW status bit.
36513     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_PKT_OVERFLOW_SHIFT                                   0
36514     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW                                         (0x1<<1) // A rising edge on this register bit (0->1); clears the sticky RX_MSG_OVERFLOW status bit.
36515     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_RX_MSG_OVERFLOW_SHIFT                                   1
36516     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW                                        (0x1<<2) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_UNDERFLOW status bit.
36517     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_UNDERFLOW_SHIFT                                  2
36518     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW                                         (0x1<<3) // A rising edge on this register bit (0->1); clears the sticky TX_PKT_OVERFLOW status bit.
36519     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_PKT_OVERFLOW_SHIFT                                   3
36520     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_HCFC_MSG_OVERFLOW                                    (0x1<<4) // A rising edge on this register bit (0->1); clears the sticky TX_HCFC_MSG_OVERFLOW status bit.
36521     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_HCFC_MSG_OVERFLOW_SHIFT                              4
36522     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW                                    (0x1<<5) // A rising edge on this register bit (0->1); clears the sticky TX_LLFC_MSG_OVERFLOW status bit.
36523     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_LLFC_MSG_OVERFLOW_SHIFT                              5
36524     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW                                     (0x1<<6) // A rising edge on this register bit (0->1); clears the sticky TX_TS_FIFO_OVERFLOW status bit.
36525     #define XMAC_REG_CLEAR_FIFO_STATUS_CLEAR_TX_TS_FIFO_OVERFLOW_SHIFT                               6
36526 #define XMAC_REG_TX_FIFO_CREDITS                                                                     0x2100d0UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36527     #define XMAC_REG_TX_FIFO_CREDITS_QUAD_PORT_TX_CREDITS                                            (0x3f<<0) // Credits for TX FIFO; used by Ports 0/1/2/3 in quad port mode.
36528     #define XMAC_REG_TX_FIFO_CREDITS_QUAD_PORT_TX_CREDITS_SHIFT                                      0
36529     #define XMAC_REG_TX_FIFO_CREDITS_DUAL_PORT_TX_CREDITS                                            (0x3f<<6) // Credits for TX FIFO; used by Port 0 & 2 in dual port mode.
36530     #define XMAC_REG_TX_FIFO_CREDITS_DUAL_PORT_TX_CREDITS_SHIFT                                      6
36531     #define XMAC_REG_TX_FIFO_CREDITS_SINGLE_PORT_TX_CREDITS                                          (0x3f<<12) // Credits for TX FIFO; used by Port 0 in single port mode.
36532     #define XMAC_REG_TX_FIFO_CREDITS_SINGLE_PORT_TX_CREDITS_SHIFT                                    12
36533 #define XMAC_REG_EEE_CTRL                                                                            0x2100d8UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36534     #define XMAC_REG_EEE_CTRL_EEE_EN                                                                 (0x1<<0) // EEE Enable.
36535     #define XMAC_REG_EEE_CTRL_EEE_EN_SHIFT                                                           0
36536     #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PAUSE_XOFF                                              (0x1<<1) // If set; EEE FSM can go to EMPTY state even when transmit path is in XOFF state and Refresh Pause frame generation is enabled.
36537     #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PAUSE_XOFF_SHIFT                                        1
36538     #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PFC_XOFF                                                (0x1<<2) // If set; EEE FSM can go to EMPTY state even when transmit path is in XOFF state per PFC implementation and Refresh PFC frame generation is enabled.
36539     #define XMAC_REG_EEE_CTRL_EEE_DISABLE_TX_PFC_XOFF_SHIFT                                          2
36540     #define XMAC_REG_EEE_CTRL_EEE_DISABLE_RX_PAUSE_ACTIVE                                            (0x1<<3) // If set; EEE FSM can go to EMPTY state even when Receive Pause is active.
36541     #define XMAC_REG_EEE_CTRL_EEE_DISABLE_RX_PAUSE_ACTIVE_SHIFT                                      3
36542 #define XMAC_REG_EEE_DELAY_ENTRY_TIMER                                                               0x2100e0UL //Access:RW   DataWidth:0x20  This is the duration for which condition to move to LPI state must be satisfied; at the end of which MAC transitions to LPI State. This is in terms of micro seconds.  Chips: BB_A0 BB_B0 K2
36543 #define XMAC_REG_EEE_TIMERS_HI                                                                       0x2100e4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36544     #define XMAC_REG_EEE_TIMERS_HI_EEE_WAKE_TIMER                                                    (0xffff<<0) // This is the duration for which MAC must wait to go back to ACTIVE state from LPI state when it receives packet for transmission. This is in terms of micro seconds.
36545     #define XMAC_REG_EEE_TIMERS_HI_EEE_WAKE_TIMER_SHIFT                                              0
36546     #define XMAC_REG_EEE_TIMERS_HI_EEE_REF_COUNT                                                     (0xffff<<16) // This field controls clock divider used to generate ~1us reference pulses used by EEE timers. It specifies integer number of timer clock cycles for 1us using XLGMII txclk.
36547     #define XMAC_REG_EEE_TIMERS_HI_EEE_REF_COUNT_SHIFT                                               16
36548 #define XMAC_REG_ONE_SECOND_TIMER                                                                    0x2100e8UL //Access:RW   DataWidth:0x18  This is the duration for which EEE FSM must wait when Link status becomes active before transitioning to ACTIVE state. This is in terms of micro seconds. Default value is set to 1 second.  Chips: BB_A0 BB_B0 K2
36549 #define XMAC_REG_GMII_EEE_CTRL                                                                       0x210118UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36550     #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD                                        (0xffff<<0) // If LPI_Prediction is enabled then this register defines the number of IDLEs to be received by GMII interface before allowing LP_IDLE to be sent to Link Partner.
36551     #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_THRESHOLD_SHIFT                                  0
36552     #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN                                          (0x1<<16) // When set to 1; enables LP_IDLE Prediction. When set to 0; disables LP_IDLE Prediction.
36553     #define XMAC_REG_GMII_EEE_CTRL_GMII_LPI_PREDICT_MODE_EN_SHIFT                                    16
36554     #define XMAC_REG_GMII_EEE_CTRL_GMII_TXCLK_DIS                                                    (0x1<<17) // When set to 1; GMII interface will shut down TXCLK to PHY; when in LPI state.
36555     #define XMAC_REG_GMII_EEE_CTRL_GMII_TXCLK_DIS_SHIFT                                              17
36556 #define XMAC_REG_MACSEC_CTRL_LO                                                                      0x210128UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
36557     #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_LAUNCH_EN                                              (0x1<<0) // If set; each data frame is transmitted only after the corresponding launch_en signal is asserted.
36558     #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_LAUNCH_EN_SHIFT                                        0
36559     #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPT_EN                                         (0x1<<1) // Setting this field enables the CRC corruption on the transmitted packets.
36560     #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPT_EN_SHIFT                                   1
36561     #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPTION_MODE                                    (0x1<<2) // In CRC corruption mode; if this bit is set; replaces computed CRC with XXX; else computed CRC is inverted.
36562     #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_TX_CRC_CORRUPTION_MODE_SHIFT                              2
36563     #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_PROG_TX_CRC_LO                                            (0x1fffffff<<3) // Lower 32 bits of macsec_prog_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used in MACSEC. The computed CRC is replaced by this programmed CRC value.
36564     #define XMAC_REG_MACSEC_CTRL_LO_MACSEC_PROG_TX_CRC_LO_SHIFT                                      3
36565 #define XMAC_REG_MACSEC_PROG_TX_CRC_HI                                                               0x21012cUL //Access:RW   DataWidth:0x3   Upper 32 bits of macsec_prog_tx_crc register. Programmable CRC value to corrupt the Tx CRC to be used in MACSEC. The computed CRC is replaced by this programmed CRC value.  Chips: BB_A0 BB_B0 K2
36566 #define XMAC_REG_XMAC_VERSION                                                                        0x210130UL //Access:RW   DataWidth:0x10  XMAC IP Version ID - corresponds to RTL/DV label.  Chips: BB_A0 BB_B0 K2
36567 #define XMAC_REG_WB_TX_CTRL                                                                          0x210420UL //Access:WB   DataWidth:0x26  This is a WB access for version of the register at XMAC TX_CTRL. The register can be access in either this loation or at XMAC TX_CTRL; but normal WB access methods mus be used at this location. The fields within this WB register are: 1:0=XMAC CRC_MODE; 2:2=XMAC DISCARD; 3:3=XMAC TX_ANY_START; 4:4=XMAC PAD_EN; 11:5=XMAC PAD_THRESHOLD; 18:12=XMAC AVERAGE_IPG; 24:19=XMAC THROT_NUM; 31:25=XMAC THROT_DENOM_LO; 32:32=XMAC THROT_DENOM_HI; 36:33=XMAC TX_PREAMBLE_LENGTH; 37:37=XMAC TX_64BYTE_BUFFER_EN; 63:38=XMAC RESERVED.  Chips: BB_A0 BB_B0 K2
36568 #define XMAC_REG_WB_TX_CTRL_SIZE                                                                     2
36569 #define XMAC_REG_WB_TX_MAC_SA                                                                        0x210428UL //Access:WB   DataWidth:0x30  This is a WB access for version of the register at XMAC TX_MAC_SA. The register can be access in either this loation or at XMAC TX_MAC_SA; but normal WB access methods mus be used at this location. The fields within this WB register are: 31:0=XMAC CTRL_SA_LO; 47:32=XMAC CTRL_SA_HI; 63:48=XMAC RESERVED.  Chips: BB_A0 BB_B0 K2
36570 #define XMAC_REG_WB_TX_MAC_SA_SIZE                                                                   2
36571 #define XMAC_REG_WB_RX_MAC_SA                                                                        0x210438UL //Access:WB   DataWidth:0x30  This is a WB access for version of the register at XMAC RX_MAC_SA. The register can be access in either this loation or at XMAC RX_MAC_SA; but normal WB access methods mus be used at this location. The fields within this WB register are: 31:0=XMAC RX_SA_LO; 47:32=XMAC RX_SA_HI; 63:48=XMAC RESERVED.  Chips: BB_A0 BB_B0 K2
36572 #define XMAC_REG_WB_RX_MAC_SA_SIZE                                                                   2
36573 #define XMAC_REG_WB_PAUSE_CTRL                                                                       0x210468UL //Access:WB   DataWidth:0x25  This is a WB access for version of the register at XMAC PAUSE_CTRL. The register can be access in either this loation or at XMAC PAUSE_CTRL; but normal WB access methods mus be used at this location. The fields within this WB register are: 15:0=XMAC PAUSE_REFRESH_TIMER; 16:16=XMAC PAUSE_REFRESH_EN; 17:17=XMAC TX_PAUSE_EN; 18:18=XMAC RX_PAUSE_EN; 19:19=XMAC RX_PASS_PAUSE; 20:20=XMAC PAUSE_GMII_ON_TX_LINE_SIDE; 31:21=XMAC PAUSE_XOFF_TIMER_LO; 36:32=XMAC PAUSE_XOFF_TIMER_HI; 63:37=XMAC RESERVED.  Chips: BB_A0 BB_B0 K2
36574 #define XMAC_REG_WB_PAUSE_CTRL_SIZE                                                                  2
36575 #define XMAC_REG_WB_PFC_DA                                                                           0x210488UL //Access:WB   DataWidth:0x30  This is a WB access for version of the register at XMAC PFC_DA. The register can be access in either this loation or at XMAC PFC_DA; but normal WB access methods mus be used at this location. The fields within this WB register are: 31:0=XMAC PFC_MACDA_LO; 47:32=XMAC PFC_MACDA_HI; 63:48=XMAC RESERVED.  Chips: BB_A0 BB_B0 K2
36576 #define XMAC_REG_WB_PFC_DA_SIZE                                                                      2
36577 #define XMAC_REG_WB_MACSEC_CTRL                                                                      0x210528UL //Access:WB   DataWidth:0x23  This is a WB access for version of the register at XMAC MACSEC_CTRL. The register can be access in either this loation or at XMAC MACSEC_CTRL; but normal WB access methods mus be used at this location. The fields within this WB register are: 0:0=XMAC MACSEC_TX_LAUNCH_EN; 1:1=XMAC MACSEC_TX_CRC_CORRUPT_EN; 2:2=XMAC MACSEC_TX_CRC_CORRUPTION_MODE; 31:3=XMAC MACSEC_PROG_TX_CRC_LO; 34:32=XMAC MACSEC_PROG_TX_CRC_HI; 63:35=XMAC RESERVED.  Chips: BB_A0 BB_B0 K2
36578 #define XMAC_REG_WB_MACSEC_CTRL_SIZE                                                                 2
36579 #define XMAC_REG_XMAC1                                                                               0x210800UL //Access:RW   DataWidth:0x20  This is the XMAC for port 1.  Chips: BB_A0 BB_B0 K2
36580 #define XMAC_REG_XMAC1_SIZE                                                                          512
36581 #define XMAC_REG_MSTAT0                                                                              0x211000UL //Access:RW   DataWidth:0x20  This is the MSTAT block.  Chips: BB_A0 BB_B0 K2
36582 #define XMAC_REG_MSTAT0_SIZE                                                                         1024
36583 #define CNIG_REG_NIG_PORT0_CONF_K2                                                                   0x218200UL //Access:RW   DataWidth:0xf   Multi Field Register.  Chips: K2
36584     #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0                                                (0x1<<0) // 0: NIG port inactive 1: NIG prot active
36585     #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_ENABLE_0_SHIFT                                          0
36586     #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0                                          (0x3<<1) // 00: Map to NWM  port 0 01: Map to NWM  port 1 10: Map to NWM  port 2 11: Map to NWM  port 3
36587     #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_NWM_PORT_MAP_0_SHIFT                                    1
36588     #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0                                                  (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
36589     #define CNIG_REG_NIG_PORT0_CONF_NIG_PORT_RATE_0_SHIFT                                            3
36590     #define CNIG_REG_NIG_PORT0_CONF_CRC_REMOVE_EN_0                                                  (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
36591     #define CNIG_REG_NIG_PORT0_CONF_CRC_REMOVE_EN_0_SHIFT                                            6
36592     #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_EN_0                                                  (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet.
36593     #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_EN_0_SHIFT                                            7
36594     #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_EN_0                                          (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
36595     #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_EN_0_SHIFT                                    8
36596     #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_ON_ERROR_0                                    (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
36597     #define CNIG_REG_NIG_PORT0_CONF_CRC_APPEND_CORRUPT_ON_ERROR_0_SHIFT                              9
36598     #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ENABLE_0                                            (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
36599     #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ENABLE_0_SHIFT                                      10
36600     #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ACTIVE_CYCLES_0                                     (0xf<<11) // This 4 bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels, how many cycles backpressure will be deasserted.  Active cycles vlaue = field value + 1.
36601     #define CNIG_REG_NIG_PORT0_CONF_RATE_LIMITER_ACTIVE_CYCLES_0_SHIFT                               11
36602 #define CNIG_REG_NW_PORT_MODE_BB_A0                                                                  0x218200UL //Access:RW   DataWidth:0x4   This register sets the Port Mode for the Network interface. 0 : 2x40G (BB), NA (K2) 1 : 2x50G (BB), 2x20G (K2) 2 : 1x100G (BB), 1x40G (K2) 3 : 4x10G_F (BB) (10G with 4x25 SERDES) NA (K2) 4 : 4x10G_E (BB/K2) (10G with 4x10 SERDES) 5 : 4x20G (BB), NA (K2) 6 : 1x40G + 2x10G (BB), NA (K2) 7 : 1x40G + 2x20G (BB), NA (K2) Others: Unused  Chips: BB_A0
36603 #define CNIG_REG_NW_PORT_MODE_BB_B0                                                                  0x218200UL //Access:RW   DataWidth:0x4   This register sets the Port Mode for the Network interface. 0 : 2x40G (BB), NA (K2) 1 : 2x50G (BB), 2x20G (K2) 2 : 1x100G (BB), 1x40G (K2) 3 : 4x10G_F (BB) (10G with 4x25 SERDES) NA (K2) 4 : 4x10G_E (BB/K2) (10G with 4x10 SERDES) 5 : 4x20G (BB), NA (K2) 6 : 1x40G + 2x10G (BB), NA (K2) 7 : 1x40G + 2x20G (BB), NA (K2) Others: Unused  Chips: BB_B0
36604 #define CNIG_REG_NIG_PORT1_CONF_K2                                                                   0x218204UL //Access:RW   DataWidth:0xf   Multi Field Register.  Chips: K2
36605     #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_ENABLE_1                                                (0x1<<0) // 0: NIG port inactive 1: NIG prot active
36606     #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_ENABLE_1_SHIFT                                          0
36607     #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_NWM_PORT_MAP_1                                          (0x3<<1) // 00: Map to NWM  port 0 01: Map to NWM  port 1 10: Map to NWM  port 2 11: Map to NWM  port 3
36608     #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_NWM_PORT_MAP_1_SHIFT                                    1
36609     #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_RATE_1                                                  (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
36610     #define CNIG_REG_NIG_PORT1_CONF_NIG_PORT_RATE_1_SHIFT                                            3
36611     #define CNIG_REG_NIG_PORT1_CONF_CRC_REMOVE_EN_1                                                  (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
36612     #define CNIG_REG_NIG_PORT1_CONF_CRC_REMOVE_EN_1_SHIFT                                            6
36613     #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_EN_1                                                  (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet.
36614     #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_EN_1_SHIFT                                            7
36615     #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_EN_1                                          (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
36616     #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_EN_1_SHIFT                                    8
36617     #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_ON_ERROR_1                                    (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
36618     #define CNIG_REG_NIG_PORT1_CONF_CRC_APPEND_CORRUPT_ON_ERROR_1_SHIFT                              9
36619     #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ENABLE_1                                            (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
36620     #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ENABLE_1_SHIFT                                      10
36621     #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ACTIVE_CYCLES_1                                     (0xf<<11) // This 4 bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels, how many cycles backpressure will be deasserted.  Active cycles vlaue = field value + 1.
36622     #define CNIG_REG_NIG_PORT1_CONF_RATE_LIMITER_ACTIVE_CYCLES_1_SHIFT                               11
36623 #define CNIG_REG_NW_SERDES_SWAP_BB_A0                                                                0x218204UL //Access:RW   DataWidth:0x1   This register allows swapping the SERDES instances 0 : 4x25 SERDES connects to Engine 0 and 4x10 SERDES connects to Engine 1 1 : 4x25 SERDES connects to Engine 1 and 4x10 SERDES connects to Engine 0  Chips: BB_A0
36624 #define CNIG_REG_NW_SERDES_SWAP_BB_B0                                                                0x218204UL //Access:RW   DataWidth:0x1   This register allows swapping the SERDES instances 0 : 4x25 SERDES connects to Engine 0 and 4x10 SERDES connects to Engine 1 1 : 4x25 SERDES connects to Engine 1 and 4x10 SERDES connects to Engine 0  Chips: BB_B0
36625 #define CNIG_REG_NIG_PORT2_CONF_K2                                                                   0x218208UL //Access:RW   DataWidth:0xf   Multi Field Register.  Chips: K2
36626     #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_ENABLE_2                                                (0x1<<0) // 0: NIG port inactive 1: NIG prot active
36627     #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_ENABLE_2_SHIFT                                          0
36628     #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_NWM_PORT_MAP_2                                          (0x3<<1) // 00: Map to NWM  port 0 01: Map to NWM  port 1 10: Map to NWM  port 2 11: Map to NWM  port 3
36629     #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_NWM_PORT_MAP_2_SHIFT                                    1
36630     #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_RATE_2                                                  (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
36631     #define CNIG_REG_NIG_PORT2_CONF_NIG_PORT_RATE_2_SHIFT                                            3
36632     #define CNIG_REG_NIG_PORT2_CONF_CRC_REMOVE_EN_2                                                  (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
36633     #define CNIG_REG_NIG_PORT2_CONF_CRC_REMOVE_EN_2_SHIFT                                            6
36634     #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_EN_2                                                  (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet.
36635     #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_EN_2_SHIFT                                            7
36636     #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_EN_2                                          (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
36637     #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_EN_2_SHIFT                                    8
36638     #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_ON_ERROR_2                                    (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
36639     #define CNIG_REG_NIG_PORT2_CONF_CRC_APPEND_CORRUPT_ON_ERROR_2_SHIFT                              9
36640     #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ENABLE_2                                            (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
36641     #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ENABLE_2_SHIFT                                      10
36642     #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ACTIVE_CYCLES_2                                     (0xf<<11) // This 4 bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels, how many cycles backpressure will be deasserted.  Active cycles vlaue = field value + 1.
36643     #define CNIG_REG_NIG_PORT2_CONF_RATE_LIMITER_ACTIVE_CYCLES_2_SHIFT                               11
36644 #define CNIG_REG_PMFC_IF_CMD_BB_A0                                                                   0x218208UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0
36645 #define CNIG_REG_PMFC_IF_CMD_BB_B0                                                                   0x218208UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_B0
36646     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_TYPE                                                        (0x1<<0) // 1 : Memory Access 0 : Register Access
36647     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_TYPE_SHIFT                                                  0
36648     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC                                               (0x1<<1) // Setting this bit to 1 tells the interface logic auto increment the address based on the programmed byte count.
36649     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC_SHIFT                                         1
36650     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_UNUSED                                                      (0x3<<2) //
36651     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_UNUSED_SHIFT                                                2
36652     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC_SIZE                                          (0xf<<4) // In Port Macro the register addresses are index addresses, a 64bit register is considered a single register, the next 64 bit register will be at addr+1. This register allows HW to automatically increment to a programmable index. Normally the value will be just 1.
36653     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_ADDR_AUTO_INC_SIZE_SHIFT                                    4
36654     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_BYTE_COUNT                                                  (0xff<<8) // Byte Count of the transaction. Limit to 32bytes.
36655     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_BYTE_COUNT_SHIFT                                            8
36656     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_RESET_FSM                                                   (0x1<<16) // Reset the Register interface state machine
36657     #define CNIG_REG_PMFC_IF_CMD_PMFC_IF_RESET_FSM_SHIFT                                             16
36658 #define CNIG_REG_NIG_PORT3_CONF_K2                                                                   0x21820cUL //Access:RW   DataWidth:0xf   Multi Field Register.  Chips: K2
36659     #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_ENABLE_3                                                (0x1<<0) // 0: NIG port inactive 1: NIG prot active
36660     #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_ENABLE_3_SHIFT                                          0
36661     #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_NWM_PORT_MAP_3                                          (0x3<<1) // 00: Map to NWM  port 0 01: Map to NWM  port 1 10: Map to NWM  port 2 11: Map to NWM  port 3
36662     #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_NWM_PORT_MAP_3_SHIFT                                    1
36663     #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_RATE_3                                                  (0x7<<3) // 000: 1G/10G 001: 25G 010: 40G 011: 50G 111-100: reserved
36664     #define CNIG_REG_NIG_PORT3_CONF_NIG_PORT_RATE_3_SHIFT                                            3
36665     #define CNIG_REG_NIG_PORT3_CONF_CRC_REMOVE_EN_3                                                  (0x1<<6) // This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness.
36666     #define CNIG_REG_NIG_PORT3_CONF_CRC_REMOVE_EN_3_SHIFT                                            6
36667     #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_EN_3                                                  (0x1<<7) // This bit controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet.
36668     #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_EN_3_SHIFT                                            7
36669     #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_EN_3                                          (0x1<<8) // This bit controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
36670     #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_EN_3_SHIFT                                    8
36671     #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_ON_ERROR_3                                    (0x1<<9) // This bit controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration.
36672     #define CNIG_REG_NIG_PORT3_CONF_CRC_APPEND_CORRUPT_ON_ERROR_3_SHIFT                              9
36673     #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ENABLE_3                                            (0x1<<10) // This bit controls the option for enabling rate limitation on the CNIG TX data path via controlling the NIGs backpressure mechanism. When this bit is set, the port's TX datapath is limited to 256xactive_cycles/16[bit/cycle]. This mode is intended to be used on loopback mode but can also be active on when loopback mode is disabled.
36674     #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ENABLE_3_SHIFT                                      10
36675     #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ACTIVE_CYCLES_3                                     (0xf<<11) // This 4 bit field sets the value of active cycles within a window of 16 cycles. i.e - from each 16 cycels, how many cycles backpressure will be deasserted.  Active cycles vlaue = field value + 1.
36676     #define CNIG_REG_NIG_PORT3_CONF_RATE_LIMITER_ACTIVE_CYCLES_3_SHIFT                               11
36677 #define CNIG_REG_PMFC_IF_STATUS_BB_A0                                                                0x21820cUL //Access:R    DataWidth:0x3   Multi Field Register.  Chips: BB_A0
36678 #define CNIG_REG_PMFC_IF_STATUS_BB_B0                                                                0x21820cUL //Access:R    DataWidth:0x3   Multi Field Register.  Chips: BB_B0
36679     #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_BUSY                                                     (0x1<<0) // 1 : State Machine is busy
36680     #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_BUSY_SHIFT                                               0
36681     #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_DONE                                                     (0x1<<1) // 1 : State Machine has completed operation.
36682     #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_DONE_SHIFT                                               1
36683     #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_ERROR                                                    (0x1<<2) // 1 : Last transaction resulted in an error
36684     #define CNIG_REG_PMFC_IF_STATUS_PMFC_IF_ERROR_SHIFT                                              2
36685 #define CNIG_REG_LOOPBACK_MODE_K2                                                                    0x218210UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: K2
36686     #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_ENABLE                                                   (0x1<<0) // This regiseter enables loopback mode (used for debug) 0 - loopback inactive 1 - loopback active
36687     #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_ENABLE_SHIFT                                             0
36688     #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_MODE                                                     (0x1<<1) // 0: mode0 is used with the following loopback mapping: NIG TX port 0 => NIG RX port 0 NIG TX port 1 => NIG RX port 1 NIG TX port 2 => NIG RX port 2 NIG TX port 3 => NIG RX port 3 1: mode1 is used with the following loopback mapping: NIG TX port 0 => NIG RX port 1 NIG TX port 1 => NIG RX port 0 NIG TX port 2 => NIG RX port 3 NIG TX port 3 => NIG RX port 2
36689     #define CNIG_REG_LOOPBACK_MODE_LOOPBACK_MODE_SHIFT                                               1
36690 #define CNIG_REG_PMFC_IF_ADDR_BB_A0                                                                  0x218210UL //Access:RW   DataWidth:0x20  Address of PM IF transaction. For Register Access 31:26 : Stage ID 25:25 : Register Type 1 = Generic Register, 0 = Per Port 24:08 : Register Offset 07:00 : Port Number For Memory Access 31:26 : Stage ID 25:00 : Memory Index  Chips: BB_A0
36691 #define CNIG_REG_PMFC_IF_ADDR_BB_B0                                                                  0x218210UL //Access:RW   DataWidth:0x20  Address of PM IF transaction. For Register Access 31:26 : Stage ID 25:25 : Register Type 1 = Generic Register, 0 = Per Port 24:08 : Register Offset 07:00 : Port Number For Memory Access 31:26 : Stage ID 25:00 : Memory Index  Chips: BB_B0
36692 #define CNIG_REG_NWM_ERROR_MASK_K2                                                                   0x218214UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
36693     #define CNIG_REG_NWM_ERROR_MASK_LENGTH                                                           (0x1<<0) // Set to 1 for masking invlaid legth fram error.
36694     #define CNIG_REG_NWM_ERROR_MASK_LENGTH_SHIFT                                                     0
36695     #define CNIG_REG_NWM_ERROR_MASK_CRC                                                              (0x1<<1) // Set to 1 for masking crc error.
36696     #define CNIG_REG_NWM_ERROR_MASK_CRC_SHIFT                                                        1
36697     #define CNIG_REG_NWM_ERROR_MASK_DEC                                                              (0x1<<2) // Set to 1 for masking decoding error.
36698     #define CNIG_REG_NWM_ERROR_MASK_DEC_SHIFT                                                        2
36699     #define CNIG_REG_NWM_ERROR_MASK_SHORT_FRAME                                                      (0x1<<3) // Set to 1 for masking fifo overflow error.
36700     #define CNIG_REG_NWM_ERROR_MASK_SHORT_FRAME_SHIFT                                                3
36701     #define CNIG_REG_NWM_ERROR_MASK_REMOTE                                                           (0x1<<4) // Set to 1 for masking remote error.
36702     #define CNIG_REG_NWM_ERROR_MASK_REMOTE_SHIFT                                                     4
36703     #define CNIG_REG_NWM_ERROR_MASK_VLAN_TAG                                                         (0x1<<5) // Set to 1 for masking vlan tag error.
36704     #define CNIG_REG_NWM_ERROR_MASK_VLAN_TAG_SHIFT                                                   5
36705     #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_TRASMIT                                                (0x1<<6) // Set to 1 for masking vlan transmit error.
36706     #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_TRASMIT_SHIFT                                          6
36707     #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_VLAN                                                   (0x1<<7) // Set to 1 for masking vlan error.
36708     #define CNIG_REG_NWM_ERROR_MASK_NWM_ERROR_VLAN_SHIFT                                             7
36709 #define CNIG_REG_PMFC_IF_WRDATA_BB_A0                                                                0x218214UL //Access:RW   DataWidth:0x20  Write Data. This should be the last item written for a transaction. Writing to this register will kick off a transaction  Chips: BB_A0
36710 #define CNIG_REG_PMFC_IF_WRDATA_BB_B0                                                                0x218214UL //Access:RW   DataWidth:0x20  Write Data. This should be the last item written for a transaction. Writing to this register will kick off a transaction  Chips: BB_B0
36711 #define CNIG_REG_INT_STS_BB_A0                                                                       0x2182e8UL //Access:R    DataWidth:0x4   Multi Field Register.  Chips: BB_A0
36712 #define CNIG_REG_INT_STS_BB_B0                                                                       0x2182e8UL //Access:R    DataWidth:0x6   Multi Field Register.  Chips: BB_B0
36713 #define CNIG_REG_INT_STS_K2                                                                          0x218218UL //Access:R    DataWidth:0x7   Multi Field Register.  Chips: K2
36714     #define CNIG_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
36715     #define CNIG_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
36716     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_BB_B0                                              (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
36717     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_BB_B0_SHIFT                                        4
36718     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_K2                                                 (0x1<<1) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36719     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT0_K2_SHIFT                                           1
36720     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT1                                                    (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36721     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT1_SHIFT                                              2
36722     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_BB_B0                                              (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
36723     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_BB_B0_SHIFT                                        5
36724     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_K2                                                 (0x1<<3) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36725     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT2_K2_SHIFT                                           3
36726     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT3                                                    (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36727     #define CNIG_REG_INT_STS_TX_ILLEGAL_SOP_PORT3_SHIFT                                              4
36728     #define CNIG_REG_INT_STS_TDM_LANE_0_BANDWITH_EXCEED                                              (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
36729     #define CNIG_REG_INT_STS_TDM_LANE_0_BANDWITH_EXCEED_SHIFT                                        5
36730     #define CNIG_REG_INT_STS_TDM_LANE_1_BANDWITH_EXCEED                                              (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
36731     #define CNIG_REG_INT_STS_TDM_LANE_1_BANDWITH_EXCEED_SHIFT                                        6
36732     #define CNIG_REG_INT_STS_PMEG_INTR                                                               (0x1<<1) // Interrupt from PMEG.
36733     #define CNIG_REG_INT_STS_PMEG_INTR_SHIFT                                                         1
36734     #define CNIG_REG_INT_STS_PMFC_INTR                                                               (0x1<<2) // Interrupt from PMFC.
36735     #define CNIG_REG_INT_STS_PMFC_INTR_SHIFT                                                         2
36736     #define CNIG_REG_INT_STS_FIFO_ERROR                                                              (0x1<<3) // Error from an Interface FIFO.
36737     #define CNIG_REG_INT_STS_FIFO_ERROR_SHIFT                                                        3
36738 #define CNIG_REG_PMFC_IF_RDDATA_BB_A0                                                                0x218218UL //Access:R    DataWidth:0x20  Read Data  Chips: BB_A0
36739 #define CNIG_REG_PMFC_IF_RDDATA_BB_B0                                                                0x218218UL //Access:R    DataWidth:0x20  Read Data  Chips: BB_B0
36740 #define CNIG_REG_INT_MASK_BB_A0                                                                      0x2182ecUL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0
36741 #define CNIG_REG_INT_MASK_BB_B0                                                                      0x2182ecUL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_B0
36742 #define CNIG_REG_INT_MASK_K2                                                                         0x21821cUL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: K2
36743     #define CNIG_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.ADDRESS_ERROR .
36744     #define CNIG_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
36745     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_BB_B0                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT0 .
36746     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_BB_B0_SHIFT                                       4
36747     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_K2                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT0 .
36748     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT0_K2_SHIFT                                          1
36749     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT1                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT1 .
36750     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT1_SHIFT                                             2
36751     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_BB_B0                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT2 .
36752     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_BB_B0_SHIFT                                       5
36753     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_K2                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT2 .
36754     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT2_K2_SHIFT                                          3
36755     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT3                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TX_ILLEGAL_SOP_PORT3 .
36756     #define CNIG_REG_INT_MASK_TX_ILLEGAL_SOP_PORT3_SHIFT                                             4
36757     #define CNIG_REG_INT_MASK_TDM_LANE_0_BANDWITH_EXCEED                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TDM_LANE_0_BANDWITH_EXCEED .
36758     #define CNIG_REG_INT_MASK_TDM_LANE_0_BANDWITH_EXCEED_SHIFT                                       5
36759     #define CNIG_REG_INT_MASK_TDM_LANE_1_BANDWITH_EXCEED                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.TDM_LANE_1_BANDWITH_EXCEED .
36760     #define CNIG_REG_INT_MASK_TDM_LANE_1_BANDWITH_EXCEED_SHIFT                                       6
36761     #define CNIG_REG_INT_MASK_PMEG_INTR                                                              (0x1<<1) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.PMEG_INTR .
36762     #define CNIG_REG_INT_MASK_PMEG_INTR_SHIFT                                                        1
36763     #define CNIG_REG_INT_MASK_PMFC_INTR                                                              (0x1<<2) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.PMFC_INTR .
36764     #define CNIG_REG_INT_MASK_PMFC_INTR_SHIFT                                                        2
36765     #define CNIG_REG_INT_MASK_FIFO_ERROR                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: CNIG_REG_INT_STS.FIFO_ERROR .
36766     #define CNIG_REG_INT_MASK_FIFO_ERROR_SHIFT                                                       3
36767 #define CNIG_REG_PMEG_IF_CMD_BB_A0                                                                   0x21821cUL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0
36768 #define CNIG_REG_PMEG_IF_CMD_BB_B0                                                                   0x21821cUL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_B0
36769     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_TYPE                                                        (0x1<<0) // 1 : Memory Access 0 : Register Access
36770     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_TYPE_SHIFT                                                  0
36771     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC                                               (0x1<<1) // Setting this bit to 1 tells the interface logic auto increment the address based on the programmed byte count.
36772     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC_SHIFT                                         1
36773     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_UNUSED                                                      (0x3<<2) //
36774     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_UNUSED_SHIFT                                                2
36775     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC_SIZE                                          (0xf<<4) // In Port Macro the register addresses are index addresses, a 64bit register is considered a single register, the next 64 bit register will be at addr+1. This register allows HW to automatically increment to a programmable index. Normally the value will be just 1.
36776     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_ADDR_AUTO_INC_SIZE_SHIFT                                    4
36777     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_BYTE_COUNT                                                  (0xff<<8) // Byte Count of the transaction. Limit to 32bytes.
36778     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_BYTE_COUNT_SHIFT                                            8
36779     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_RESET_FSM                                                   (0x1<<16) // Reset the Register interface state machine
36780     #define CNIG_REG_PMEG_IF_CMD_PMEG_IF_RESET_FSM_SHIFT                                             16
36781 #define CNIG_REG_INT_STS_WR_BB_A0                                                                    0x2182f0UL //Access:WR   DataWidth:0x4   Multi Field Register.  Chips: BB_A0
36782 #define CNIG_REG_INT_STS_WR_BB_B0                                                                    0x2182f0UL //Access:WR   DataWidth:0x6   Multi Field Register.  Chips: BB_B0
36783 #define CNIG_REG_INT_STS_WR_K2                                                                       0x218220UL //Access:WR   DataWidth:0x7   Multi Field Register.  Chips: K2
36784     #define CNIG_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
36785     #define CNIG_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
36786     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_BB_B0                                           (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
36787     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_BB_B0_SHIFT                                     4
36788     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_K2                                              (0x1<<1) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36789     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT0_K2_SHIFT                                        1
36790     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT1                                                 (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36791     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT1_SHIFT                                           2
36792     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_BB_B0                                           (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
36793     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_BB_B0_SHIFT                                     5
36794     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_K2                                              (0x1<<3) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36795     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT2_K2_SHIFT                                        3
36796     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT3                                                 (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36797     #define CNIG_REG_INT_STS_WR_TX_ILLEGAL_SOP_PORT3_SHIFT                                           4
36798     #define CNIG_REG_INT_STS_WR_TDM_LANE_0_BANDWITH_EXCEED                                           (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
36799     #define CNIG_REG_INT_STS_WR_TDM_LANE_0_BANDWITH_EXCEED_SHIFT                                     5
36800     #define CNIG_REG_INT_STS_WR_TDM_LANE_1_BANDWITH_EXCEED                                           (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
36801     #define CNIG_REG_INT_STS_WR_TDM_LANE_1_BANDWITH_EXCEED_SHIFT                                     6
36802     #define CNIG_REG_INT_STS_WR_PMEG_INTR                                                            (0x1<<1) // Interrupt from PMEG.
36803     #define CNIG_REG_INT_STS_WR_PMEG_INTR_SHIFT                                                      1
36804     #define CNIG_REG_INT_STS_WR_PMFC_INTR                                                            (0x1<<2) // Interrupt from PMFC.
36805     #define CNIG_REG_INT_STS_WR_PMFC_INTR_SHIFT                                                      2
36806     #define CNIG_REG_INT_STS_WR_FIFO_ERROR                                                           (0x1<<3) // Error from an Interface FIFO.
36807     #define CNIG_REG_INT_STS_WR_FIFO_ERROR_SHIFT                                                     3
36808 #define CNIG_REG_PMEG_IF_STATUS_BB_A0                                                                0x218220UL //Access:R    DataWidth:0x3   Multi Field Register.  Chips: BB_A0
36809 #define CNIG_REG_PMEG_IF_STATUS_BB_B0                                                                0x218220UL //Access:R    DataWidth:0x3   Multi Field Register.  Chips: BB_B0
36810     #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_BUSY                                                     (0x1<<0) // 1 : State Machine is busy
36811     #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_BUSY_SHIFT                                               0
36812     #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_DONE                                                     (0x1<<1) // 1 : State Machine has completed operation.
36813     #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_DONE_SHIFT                                               1
36814     #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_ERROR                                                    (0x1<<2) // 1 : Last transaction resulted in an error
36815     #define CNIG_REG_PMEG_IF_STATUS_PMEG_IF_ERROR_SHIFT                                              2
36816 #define CNIG_REG_INT_STS_CLR_BB_A0                                                                   0x2182f4UL //Access:RC   DataWidth:0x4   Multi Field Register.  Chips: BB_A0
36817 #define CNIG_REG_INT_STS_CLR_BB_B0                                                                   0x2182f4UL //Access:RC   DataWidth:0x6   Multi Field Register.  Chips: BB_B0
36818 #define CNIG_REG_INT_STS_CLR_K2                                                                      0x218224UL //Access:RC   DataWidth:0x7   Multi Field Register.  Chips: K2
36819     #define CNIG_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
36820     #define CNIG_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
36821     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_BB_B0                                          (0x1<<4) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
36822     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_BB_B0_SHIFT                                    4
36823     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_K2                                             (0x1<<1) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36824     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT0_K2_SHIFT                                       1
36825     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT1                                                (0x1<<2) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36826     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT1_SHIFT                                          2
36827     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_BB_B0                                          (0x1<<5) // This interrupt is asserted when a violation of the ADD CRC PORT  STM occurs. It can result if a packet size is less than 256bit is sent by NIG (which is illegal).
36828     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_BB_B0_SHIFT                                    5
36829     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_K2                                             (0x1<<3) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36830     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT2_K2_SHIFT                                       3
36831     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT3                                                (0x1<<4) // This interrupt is asserted when a violation of the append CRC STM occurs. It can result if NIG sends SOP indication the next transaction after sending "EOP +  Byte Valid > 28" without inserting an "empty" transaction in between.
36832     #define CNIG_REG_INT_STS_CLR_TX_ILLEGAL_SOP_PORT3_SHIFT                                          4
36833     #define CNIG_REG_INT_STS_CLR_TDM_LANE_0_BANDWITH_EXCEED                                          (0x1<<5) // This interrupt is asserted when a violation of the allocated TDM lane0 bandwith is detected
36834     #define CNIG_REG_INT_STS_CLR_TDM_LANE_0_BANDWITH_EXCEED_SHIFT                                    5
36835     #define CNIG_REG_INT_STS_CLR_TDM_LANE_1_BANDWITH_EXCEED                                          (0x1<<6) // This interrupt is asserted when a violation of the allocated TDM lane1 bandwith is detected
36836     #define CNIG_REG_INT_STS_CLR_TDM_LANE_1_BANDWITH_EXCEED_SHIFT                                    6
36837     #define CNIG_REG_INT_STS_CLR_PMEG_INTR                                                           (0x1<<1) // Interrupt from PMEG.
36838     #define CNIG_REG_INT_STS_CLR_PMEG_INTR_SHIFT                                                     1
36839     #define CNIG_REG_INT_STS_CLR_PMFC_INTR                                                           (0x1<<2) // Interrupt from PMFC.
36840     #define CNIG_REG_INT_STS_CLR_PMFC_INTR_SHIFT                                                     2
36841     #define CNIG_REG_INT_STS_CLR_FIFO_ERROR                                                          (0x1<<3) // Error from an Interface FIFO.
36842     #define CNIG_REG_INT_STS_CLR_FIFO_ERROR_SHIFT                                                    3
36843 #define CNIG_REG_PMEG_IF_ADDR_BB_A0                                                                  0x218224UL //Access:RW   DataWidth:0x20  Address of PM IF transaction. For Register Access 31:26 : Stage ID 25:25 : Register Type 1 = Generic Register, 0 = Per Port 24:08 : Register Offset 07:00 : Port Number For Memory Access 31:26 : Stage ID 25:00 : Memory Index  Chips: BB_A0
36844 #define CNIG_REG_PMEG_IF_ADDR_BB_B0                                                                  0x218224UL //Access:RW   DataWidth:0x20  Address of PM IF transaction. For Register Access 31:26 : Stage ID 25:25 : Register Type 1 = Generic Register, 0 = Per Port 24:08 : Register Offset 07:00 : Port Number For Memory Access 31:26 : Stage ID 25:00 : Memory Index  Chips: BB_B0
36845 #define CNIG_REG_NWM_LPI_DEFUALT_VALUE_K2                                                            0x218228UL //Access:RW   DataWidth:0x1   This register is used to set the value of NWM lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the NWM NIG mapping.  Chips: K2
36846 #define CNIG_REG_PMEG_IF_WRDATA_BB_A0                                                                0x218228UL //Access:RW   DataWidth:0x20  Write Data. This should be the last item written for a transaction. Writing to this register will kick off a transaction  Chips: BB_A0
36847 #define CNIG_REG_PMEG_IF_WRDATA_BB_B0                                                                0x218228UL //Access:RW   DataWidth:0x20  Write Data. This should be the last item written for a transaction. Writing to this register will kick off a transaction  Chips: BB_B0
36848 #define CNIG_REG_PMEG_IF_RDDATA_BB_A0                                                                0x21822cUL //Access:R    DataWidth:0x20  Read Data  Chips: BB_A0
36849 #define CNIG_REG_PMEG_IF_RDDATA_BB_B0                                                                0x21822cUL //Access:R    DataWidth:0x20  Read Data  Chips: BB_B0
36850 #define CNIG_REG_PRTY_MASK_BB_B0                                                                     0x21834cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_B0
36851 #define CNIG_REG_PRTY_MASK_K2                                                                        0x218230UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: K2
36852     #define CNIG_REG_PRTY_MASK_DATAPATH_TX                                                           (0x1<<1) // This bit masks, when set, the Parity bit: CNIG_REG_PRTY_STS.DATAPATH_TX .
36853     #define CNIG_REG_PRTY_MASK_DATAPATH_TX_SHIFT                                                     1
36854     #define CNIG_REG_PRTY_MASK_DATAPATH_RX                                                           (0x1<<0) // This bit masks, when set, the Parity bit: CNIG_REG_PRTY_STS.DATAPATH_RX .
36855     #define CNIG_REG_PRTY_MASK_DATAPATH_RX_SHIFT                                                     0
36856 #define CNIG_REG_MDIO_SW_ARB_BB_A0                                                                   0x218230UL //Access:RW   DataWidth:0x10    Chips: BB_A0
36857 #define CNIG_REG_MDIO_SW_ARB_BB_B0                                                                   0x218230UL //Access:RW   DataWidth:0x10    Chips: BB_B0
36858 #define CNIG_REG_LED_CONTROL                                                                         0x21823cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0
36859     #define CNIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC                                                    (0x1<<0) // If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC And LED_CONTROL_BLINK_TRAFFIC
36860     #define CNIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_SHIFT                                              0
36861     #define CNIG_REG_LED_CONTROL_TRAFFIC                                                             (0x1<<4) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TRAFFIC bit bit is also set; the LED will blink with blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
36862     #define CNIG_REG_LED_CONTROL_TRAFFIC_SHIFT                                                       4
36863     #define CNIG_REG_LED_CONTROL_BLINK_TRAFFIC                                                       (0x1<<8) // Port0: If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; the Traffic LED will blink with the blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
36864     #define CNIG_REG_LED_CONTROL_BLINK_TRAFFIC_SHIFT                                                 8
36865     #define CNIG_REG_LED_CONTROL_BLINK_RATE_ENA                                                      (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field defined below. If this bit is cleared; then the blink rate will be about 16Hz.
36866     #define CNIG_REG_LED_CONTROL_BLINK_RATE_ENA_SHIFT                                                12
36867     #define CNIG_REG_LED_CONTROL_BLINK_RATE                                                          (0xfff<<20) // Specifies the period of each blink cycle (on + off) for Traffic LED in milliseconds. Must be a non-zero value. This 12-bit field is reset to 0x162; giving a default blink period of approximately 16Hz for the 375Mhz clock (used in 10G/40G modes). For 425Mhz clock (used in 50G/100G modes), the value of 0xb9f should be used for a 16Hz rate.
36868     #define CNIG_REG_LED_CONTROL_BLINK_RATE_SHIFT                                                    20
36869 #define CNIG_REG_COSMAP_TX_SET_K2                                                                    0x218240UL //Access:RW   DataWidth:0x8   This register enable to read and write the cosmap 8 bit value for each NWM port.  Chips: K2
36870 #define CNIG_REG_LED_MODE_BB_A0                                                                      0x218240UL //Access:RW   DataWidth:0x4   Led mode: 0     -> MAC; 1-3   -> PHY1; 4     -> MAC2; 5-7   -> PHY4; 8     -> MAC3; 9     -> 11PHY7; 12    -> MAC4; 13-15 -> PHY10;  Chips: BB_A0
36871 #define CNIG_REG_LED_MODE_BB_B0                                                                      0x218240UL //Access:RW   DataWidth:0x4   Led mode: 0     -> MAC; 1-3   -> PHY1; 4     -> MAC2; 5-7   -> PHY4; 8     -> MAC3; 9     -> 11PHY7; 12    -> MAC4; 13-15 -> PHY10;  Chips: BB_B0
36872 #define CNIG_REG_LED_PORT_SPD0_EN                                                                    0x218244UL //Access:RW   DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A '1' to each bit location will enable the corresponding speed to activate the LED.  Chips: BB_A0 BB_B0
36873 #define CNIG_REG_LED_PORT_SPD1_EN                                                                    0x218248UL //Access:RW   DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A '1' to each bit location will enable the corresponding speed to activate the LED.  Chips: BB_A0 BB_B0
36874 #define CNIG_REG_LED_PORT_SPD2_EN                                                                    0x21824cUL //Access:RW   DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused A '1' to each bit location will enable the corresponding speed to activate the LED.  Chips: BB_A0 BB_B0
36875 #define CNIG_REG_ECO_RESERVED_BB_A0                                                                  0x218238UL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0
36876 #define CNIG_REG_ECO_RESERVED_BB_B0                                                                  0x218238UL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_B0
36877 #define CNIG_REG_ECO_RESERVED_K2                                                                     0x218250UL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: K2
36878 #define CNIG_REG_MAC_LED_SPEED_BB_A0                                                                 0x218250UL //Access:RW   DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused This register allows the MAC (Driver/FW) to set the link speed of the particular port. This combined with the mask for each LED will activate the corresponding LED. For ex. if the link speed is 10G, then SW will set bit[1] of this register. If 10G is enabled on LED SPD1, then SPD1 will light up, SPD0 and SPD2 will not.  Chips: BB_A0
36879 #define CNIG_REG_MAC_LED_SPEED_BB_B0                                                                 0x218250UL //Access:RW   DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused This register allows the MAC (Driver/FW) to set the link speed of the particular port. This combined with the mask for each LED will activate the corresponding LED. For ex. if the link speed is 10G, then SW will set bit[1] of this register. If 10G is enabled on LED SPD1, then SPD1 will light up, SPD0 and SPD2 will not.  Chips: BB_B0
36880 #define CNIG_REG_DBG_SELECT_K2                                                                       0x218254UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
36881 #define CNIG_REG_MAC_LED_SWAP_BB_A0                                                                  0x218254UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_A0
36882 #define CNIG_REG_MAC_LED_SWAP_BB_B0                                                                  0x218254UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_B0
36883     #define CNIG_REG_MAC_LED_SWAP_P0                                                                 (0x3<<0) // Device Drivers view of a physical port is through the PCIE physical function that was enumerated. In a typical setup, Physical function 0 is connected to Network Port 0, PF1 to NW1 and so on. However, there are cases when the PF and NW conenctions are swapped. This register sets up which PF is connected to which Network Port. For a multiport/multifunction configuration, appropriate settings should be chosen. For ex. in a two port device, only two sets of the the bits below are valid. a Four port device has all four sets of bits valid. These bits makes the connection of Network Port 0 to the corresponding Physical function. 0  -> NW0 connects to PF0 1  -> NW0 connects to PF1 2  -> NW0 connects to PF2 3  -> NW0 connects to PF3
36884     #define CNIG_REG_MAC_LED_SWAP_P0_SHIFT                                                           0
36885     #define CNIG_REG_MAC_LED_SWAP_P1                                                                 (0x3<<4) // These bits makes the connection of Network Port 1 to the corresponding Physical function. 0  -> NW1 connects to PF0 1  -> NW1 connects to PF1 2  -> NW1 connects to PF2 3  -> NW1 connects to PF3
36886     #define CNIG_REG_MAC_LED_SWAP_P1_SHIFT                                                           4
36887     #define CNIG_REG_MAC_LED_SWAP_P2                                                                 (0x3<<8) // These bits makes the connection of Network Port 2 to the corresponding Physical function. 0  -> NW2 connects to PF0 1  -> NW2 connects to PF1 2  -> NW2 connects to PF2 3  -> NW2 connects to PF3
36888     #define CNIG_REG_MAC_LED_SWAP_P2_SHIFT                                                           8
36889     #define CNIG_REG_MAC_LED_SWAP_P3                                                                 (0x3<<12) // These bits makes the connection of Network Port 2 to the corresponding Physical function. 0  -> NW3 connects to PF0 1  -> NW3 connects to PF1 2  -> NW3 connects to PF2 3  -> NW3 connects to PF3
36890     #define CNIG_REG_MAC_LED_SWAP_P3_SHIFT                                                           12
36891 #define CNIG_REG_DBG_DWORD_ENABLE_K2                                                                 0x218258UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
36892 #define CNIG_REG_PMFC_RAW_SPEED_LN0_BB_A0                                                            0x218258UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_A0
36893 #define CNIG_REG_PMFC_RAW_SPEED_LN0_BB_B0                                                            0x218258UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_B0
36894 #define CNIG_REG_DBG_SHIFT_K2                                                                        0x21825cUL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
36895 #define CNIG_REG_PMFC_RAW_SPEED_LN1_BB_A0                                                            0x21825cUL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_A0
36896 #define CNIG_REG_PMFC_RAW_SPEED_LN1_BB_B0                                                            0x21825cUL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_B0
36897 #define CNIG_REG_DBG_FORCE_VALID_K2                                                                  0x218260UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
36898 #define CNIG_REG_PMFC_RAW_SPEED_LN2_BB_A0                                                            0x218260UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_A0
36899 #define CNIG_REG_PMFC_RAW_SPEED_LN2_BB_B0                                                            0x218260UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_B0
36900 #define CNIG_REG_DBG_FORCE_FRAME_K2                                                                  0x218264UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
36901 #define CNIG_REG_PMFC_RAW_SPEED_LN3_BB_A0                                                            0x218264UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_A0
36902 #define CNIG_REG_PMFC_RAW_SPEED_LN3_BB_B0                                                            0x218264UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_B0
36903 #define CNIG_REG_PMEG_RAW_SPEED_LN0                                                                  0x218268UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_A0 BB_B0
36904 #define CNIG_REG_PMEG_RAW_SPEED_LN1                                                                  0x21826cUL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_A0 BB_B0
36905 #define CNIG_REG_PMEG_RAW_SPEED_LN2                                                                  0x218270UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_A0 BB_B0
36906 #define CNIG_REG_PMEG_RAW_SPEED_LN3                                                                  0x218274UL //Access:R    DataWidth:0x8   LED decode [0] -> 1G or lower [1] -> 10G [2] -> 20G [3] -> 25G [4] -> 40G [5] -> 50G [6] -> 100G [7] -> unused RAW version of the LED from the SERDES..  Chips: BB_A0 BB_B0
36907 #define CNIG_REG_PMIF_OVERRIDE_ENABLE                                                                0x218278UL //Access:RW   DataWidth:0x1   When set, PMIF block uses values in following registers to configure NIG - PM interface  Chips: BB_A0 BB_B0
36908 #define CNIG_REG_PMIF_OVERRIDE_PORT_IS_PMEG                                                          0x21827cUL //Access:RW   DataWidth:0x4   These bits are used to set which NIG Ports are used with the PM4x10. A 1'b0 in these bits indicates that NIG Port is assigned to the PM4x25.  Chips: BB_A0 BB_B0
36909 #define CNIG_REG_DBG_OUT_DATA_K2                                                                     0x218280UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
36910 #define CNIG_REG_PMIF_OVERRIDE_PMEG_NIG_PORT_BB_A0                                                   0x218280UL //Access:RW   DataWidth:0x8   These bits are used to define which NIG port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Port 2 [7:6] -- PMEG Port 3  Chips: BB_A0
36911 #define CNIG_REG_PMIF_OVERRIDE_PMEG_NIG_PORT_BB_B0                                                   0x218280UL //Access:RW   DataWidth:0x8   These bits are used to define which NIG port is assigned to each PMEG Port. [1:0] -- PMEG Port 0 [3:2] -- PMEG Port 1 [5:4] -- PMEG Port 2 [7:6] -- PMEG Port 3  Chips: BB_B0
36912 #define CNIG_REG_PMIF_OVERRIDE_PMFC_NIG_PORT                                                         0x218284UL //Access:RW   DataWidth:0x8   These bits are used to define which NIG port is assigned to each PMFC Port. [1:0] -- PMFC Port 0 [3:2] -- PMFC Port 1 [5:4] -- PMFC Port 2 [7:6] -- PMFC Port 3  Chips: BB_A0 BB_B0
36913 #define CNIG_REG_PMIF_OVERRIDE_PMEG_PORTID                                                           0x218288UL //Access:RW   DataWidth:0x2   These bits are used to set the number of active ports on PMEG. The value in this register is added to the PMEG Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are used 2 -- Only Ports 0 and 2 are used  Chips: BB_A0 BB_B0
36914 #define CNIG_REG_PMIF_OVERRIDE_PMFC_PORTID                                                           0x21828cUL //Access:RW   DataWidth:0x2   These bits are used to set the number of active ports on PMFC. The value in this register is added to the PMFC Port ID every cycle. Valid values are: 0 -- Only Port 0 is used 1 -- All Ports (0-3) are used 2 -- Only Ports 0 and 2 are used  Chips: BB_A0 BB_B0
36915 #define CNIG_REG_CNIG_DBG_NIGTX_FIFO_AFULL_THRESH                                                    0x218290UL //Access:RW   DataWidth:0x3   This register sets the Almost Full Threshold for the NIG Tx FIFOs. When this threshold is reached, the backpressure signal will be sent to NIG to stop transmitting data.  Chips: BB_A0 BB_B0
36916 #define CNIG_REG_CNIG_DBG_PMEG_TXFIFO_THRESH                                                         0x218294UL //Access:RW   DataWidth:0x6   This register sets the Threshold level for Tx Credits from the 4x10 PM. Data will not be sent to the PM unless the current number of credits is greater than the number in this register.  This allows extra levels of registers between the PM and CNIG blocks without overflow.  Chips: BB_A0 BB_B0
36917 #define CNIG_REG_CNIG_DBG_PMFC_TXFIFO_THRESH                                                         0x218298UL //Access:RW   DataWidth:0x6   This register sets the Threshold level for Tx Credits from the 1x40 PM. Data will not be sent to the PM unless the current number of credits is greater than the number in this register.  This allows extra levels of registers between the PM and CNIG blocks without overflow.  Chips: BB_A0 BB_B0
36918 #define CNIG_REG_CNIG_DBG_FIFO_ERROR                                                                 0x21829cUL //Access:R    DataWidth:0x5   This register latches the FIFO Error bits from the PMFC Rx FIFO (bit [4]) and the NIG Tx FIFOs (bits [3:0]).  To clear these bits, the NIG block must be reset.  Chips: BB_A0 BB_B0
36919 #define CNIG_REG_DBG_OUT_VALID_K2                                                                    0x2182a0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
36920 #define CNIG_REG_CNIG_DBG_PMEG_CNIG_PORT_MODE_BB_A0                                                  0x2182a0UL //Access:R    DataWidth:0x3     Chips: BB_A0
36921 #define CNIG_REG_CNIG_DBG_PMEG_CNIG_PORT_MODE_BB_B0                                                  0x2182a0UL //Access:R    DataWidth:0x3     Chips: BB_B0
36922 #define CNIG_REG_DBG_OUT_FRAME_K2                                                                    0x2182a4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
36923 #define CNIG_REG_CNIG_DBG_PMFC_CNIG_PORT_MODE_BB_A0                                                  0x2182a4UL //Access:R    DataWidth:0x4     Chips: BB_A0
36924 #define CNIG_REG_CNIG_DBG_PMFC_CNIG_PORT_MODE_BB_B0                                                  0x2182a4UL //Access:R    DataWidth:0x4     Chips: BB_B0
36925 #define CNIG_REG_CNIG_DBG_PMEG_CNIG_TSFIFO_NOT_EMPTY                                                 0x2182a8UL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36926 #define CNIG_REG_CNIG_DBG_PMFC_CNIG_TSFIFO_NOT_EMPTY                                                 0x2182acUL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36927 #define CNIG_REG_CNIG_DBG_PMEG_CNIG_TS                                                               0x2182b0UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0
36928 #define CNIG_REG_CNIG_DBG_PMFC_CNIG_TS                                                               0x2182b4UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0
36929 #define CNIG_REG_CNIG_DBG_PMEG_LINK_STATUS                                                           0x2182b8UL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36930 #define CNIG_REG_CNIG_DBG_PMFC_LINK_STATUS                                                           0x2182bcUL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36931 #define CNIG_REG_CNIG_DBG_PMEG_STATUS                                                                0x2182c0UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0
36932     #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE0_STATUS                                          (0x7<<0) //
36933     #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE0_STATUS_SHIFT                                    0
36934     #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE1_STATUS                                          (0x7<<3) //
36935     #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE1_STATUS_SHIFT                                    3
36936     #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE2_STATUS                                          (0x7<<6) //
36937     #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE2_STATUS_SHIFT                                    6
36938     #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE3_STATUS                                          (0x7<<9) //
36939     #define CNIG_REG_CNIG_DBG_PMEG_STATUS_PMEG_LANE3_STATUS_SHIFT                                    9
36940 #define CNIG_REG_CNIG_DBG_PMFC_STATUS                                                                0x2182c4UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0
36941     #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE0_STATUS                                          (0x7<<0) //
36942     #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE0_STATUS_SHIFT                                    0
36943     #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE1_STATUS                                          (0x7<<3) //
36944     #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE1_STATUS_SHIFT                                    3
36945     #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE2_STATUS                                          (0x7<<6) //
36946     #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE2_STATUS_SHIFT                                    6
36947     #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE3_STATUS                                          (0x7<<9) //
36948     #define CNIG_REG_CNIG_DBG_PMFC_STATUS_PMFC_LANE3_STATUS_SHIFT                                    9
36949 #define CNIG_REG_CNIG_DBG_PMEG_EXT_LPI_INDICATE                                                      0x2182c8UL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36950 #define CNIG_REG_CNIG_DBG_PMEG_EXT_LPI_DETECT                                                        0x2182ccUL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36951 #define CNIG_REG_CNIG_DBG_PMFC_EXT_LPI_INDICATE                                                      0x2182d0UL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36952 #define CNIG_REG_CNIG_DBG_PMFC_EXT_LPI_DETECT                                                        0x2182d4UL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36953 #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT                                                              0x2182d8UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0
36954     #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_LINK_INTERRUPTION                                (0xf<<0) //
36955     #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_LINK_INTERRUPTION_SHIFT                          0
36956     #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_LOCAL_FAULT                                      (0xf<<4) //
36957     #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_LOCAL_FAULT_SHIFT                                4
36958     #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_REMOTE_FAULT                                     (0xf<<8) //
36959     #define CNIG_REG_CNIG_DBG_PMEG_RX_FAULT_PMEG_RX_REMOTE_FAULT_SHIFT                               8
36960 #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT                                                              0x2182dcUL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0
36961     #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_LINK_INTERRUPTION                                (0xf<<0) //
36962     #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_LINK_INTERRUPTION_SHIFT                          0
36963     #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_LOCAL_FAULT                                      (0xf<<4) //
36964     #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_LOCAL_FAULT_SHIFT                                4
36965     #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_REMOTE_FAULT                                     (0xf<<8) //
36966     #define CNIG_REG_CNIG_DBG_PMFC_RX_FAULT_PMFC_RX_REMOTE_FAULT_SHIFT                               8
36967 #define CNIG_REG_CNIG_DBG_IFMUX_SIGDET                                                               0x2182e0UL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36968 #define CNIG_REG_CNIG_DBG_IFMUX_PHY_LASI_B                                                           0x2182e4UL //Access:R    DataWidth:0x4     Chips: BB_A0 BB_B0
36969 #define CNIG_REG_CNIG_DBG_NIGTX_FIFO_AFULL_THRESH_LARGE                                              0x2182f8UL //Access:RW   DataWidth:0x4   This register controls the almost full indication of TX FIFO of port 0 and 2. Note: the register value represent the number of FIFO entries before almost full indication is transferred to NIG.  Chips: BB_B0
36970 #define CNIG_REG_PMEG_TX_CREDITS                                                                     0x218300UL //Access:RW   DataWidth:0x6   Per Eagle port credit RD/WR: Writing to this register will initialize the port's credit with the written value. Reading from this register will return the port's current credit value.  Chips: BB_B0
36971 #define CNIG_REG_PMEG_TX_CREDITS_SIZE                                                                4
36972 #define CNIG_REG_PMFC_TX_CREDITS                                                                     0x218310UL //Access:RW   DataWidth:0x6   Per Falcon port credit RD/WR: Writing to this register will initialize the port's credit with the written value. Reading from this register will return the port's current credit value.  Chips: BB_B0
36973 #define CNIG_REG_PMFC_TX_CREDITS_SIZE                                                                4
36974 #define CNIG_REG_PMEG_SIGN_EXT                                                                       0x218320UL //Access:RW   DataWidth:0x1   This register is used to set the value of cnig_pmeg_sign_ext output signal.  Chips: BB_B0
36975 #define CNIG_REG_PMFC_SIGN_EXT                                                                       0x218324UL //Access:RW   DataWidth:0x1   This register is used to set the value of cnig_pmfc_sign_ext output signal.  Chips: BB_B0
36976 #define CNIG_REG_PMFC_LPI_DEFUALT_VALUE                                                              0x218328UL //Access:RW   DataWidth:0x1   This register is used to set the value of PMFC lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the Port Macro NIG mapping.  Chips: BB_B0
36977 #define CNIG_REG_PMEG_LPI_DEFUALT_VALUE                                                              0x21832cUL //Access:RW   DataWidth:0x1   This register is used to set the value of PMEG lpi_indicate default value. The lpi value will be overwriten by cpmu vlaue accordigly to the Port Macro NIG mapping.  Chips: BB_B0
36978 #define CNIG_REG_PMEG_TS_RESET_N                                                                     0x218330UL //Access:RW   DataWidth:0x1   PMEG timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is out of reset.  Chips: BB_B0
36979 #define CNIG_REG_PMFC_TS_RESET_N                                                                     0x218334UL //Access:RW   DataWidth:0x1   PMFC timestamp local counter reset. If = 0, the timers is reset. If = 1, the timer is out of reset.  Chips: BB_B0
36980 #define CNIG_REG_PMFC_CRC_RX_EN                                                                      0x218338UL //Access:RW   DataWidth:0x2   This register controls the option for calculating CRC in CNIG RX datapath, remove CRC field from packet and assert Error indication accordingly to CRC correctness. Note: this mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 CRC enable.  Chips: BB_B0
36981 #define CNIG_REG_PMFC_CRC_TX_EN                                                                      0x21833cUL //Access:RW   DataWidth:0x2   This register controls the option for calculating CRC in CNIG TX datapath, and append  CRC field at the end of the packet. Note: this mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. Bit 0 - port0 CRC enable. Bit 1 - port2 CRC enable.  Chips: BB_B0
36982 #define CNIG_REG_PMFC_CRC_TX_CORRUPT_EN                                                              0x218340UL //Access:RW   DataWidth:0x2   This register controls the option for corrupting the calculated CRC value in TX path when Parity or error  indication is received from NIG. Note: a. This mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. b. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - port2 CRC corrupte enable.  Chips: BB_B0
36983 #define CNIG_REG_PMFC_CRC_TX_CORRUPT_ON_ERROR                                                        0x218344UL //Access:RW   DataWidth:0x2   This register controls the option for corrupting the calculated CRC value in TX path when error indication is received from NIG. Note: a. This mode can be active only for PMFC ports 0,2 and should be used for 100G or 2x50G NW modes. b. As result of parity error on TX datapath, CRC filed will be corrupted independently from this register configuration. Bit 0 - port0 CRC corrupt enable. Bit 1 - port2 CRC corrupte enable.  Chips: BB_B0
36984 #define PRM_REG_DISABLE_PRM                                                                          0x230000UL //Access:RW   DataWidth:0x1   Used to disable the PRM from processing any new commands.  Chips: BB_A0 BB_B0 K2
36985 #define PRM_REG_BRB_DATA_IN_EN                                                                       0x230004UL //Access:RW   DataWidth:0x1   Enables data to be received on the BRB data interface.  Chips: BB_A0 BB_B0 K2
36986 #define PRM_REG_BRB_FULL_OUT_EN                                                                      0x230008UL //Access:RW   DataWidth:0x1   Enables the BRB full output to be asserted by the PRM.  Chips: BB_A0 BB_B0 K2
36987 #define PRM_REG_PXP_ACK_IN_EN                                                                        0x23000cUL //Access:RW   DataWidth:0x1   Enables the PXP request acknowledge to be received by the PRM.  Chips: BB_A0 BB_B0 K2
36988 #define PRM_REG_DISABLE_INPUTS                                                                       0x230010UL //Access:RW   DataWidth:0x1   Used to disable all PRM block inputs for test purposes.  Chips: BB_A0 BB_B0 K2
36989 #define PRM_REG_DISABLE_OUTPUTS                                                                      0x230014UL //Access:RW   DataWidth:0x1   Used to disable all PRM block outputs for test purposes.  Chips: BB_A0 BB_B0 K2
36990 #define PRM_REG_INT_STS                                                                              0x230040UL //Access:R    DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
36991     #define PRM_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
36992     #define PRM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
36993     #define PRM_REG_INT_STS_IFIFO_ERROR                                                              (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
36994     #define PRM_REG_INT_STS_IFIFO_ERROR_SHIFT                                                        1
36995     #define PRM_REG_INT_STS_IMMED_FIFO_ERROR                                                         (0x1<<2) // Overrun/underrun error for the immediate FIFO.
36996     #define PRM_REG_INT_STS_IMMED_FIFO_ERROR_SHIFT                                                   2
36997     #define PRM_REG_INT_STS_OFST_PEND_ERROR                                                          (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
36998     #define PRM_REG_INT_STS_OFST_PEND_ERROR_SHIFT                                                    3
36999     #define PRM_REG_INT_STS_PAD_PEND_ERROR                                                           (0x1<<4) // Overrun/underrun error for pad pending FIFO.
37000     #define PRM_REG_INT_STS_PAD_PEND_ERROR_SHIFT                                                     4
37001     #define PRM_REG_INT_STS_PBINP_PEND_ERROR                                                         (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
37002     #define PRM_REG_INT_STS_PBINP_PEND_ERROR_SHIFT                                                   5
37003     #define PRM_REG_INT_STS_TAG_PEND_ERROR                                                           (0x1<<6) // Overrun/underrun error for tag pending FIFO.
37004     #define PRM_REG_INT_STS_TAG_PEND_ERROR_SHIFT                                                     6
37005     #define PRM_REG_INT_STS_MSTORM_EOP_ERR                                                           (0x1<<7) // End of packet error on M-Storm command interface.
37006     #define PRM_REG_INT_STS_MSTORM_EOP_ERR_SHIFT                                                     7
37007     #define PRM_REG_INT_STS_USTORM_EOP_ERR                                                           (0x1<<8) // End of packet error on U-Storm command interface.
37008     #define PRM_REG_INT_STS_USTORM_EOP_ERR_SHIFT                                                     8
37009     #define PRM_REG_INT_STS_MSTORM_QUE_ERR                                                           (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
37010     #define PRM_REG_INT_STS_MSTORM_QUE_ERR_SHIFT                                                     9
37011     #define PRM_REG_INT_STS_USTORM_QUE_ERR                                                           (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
37012     #define PRM_REG_INT_STS_USTORM_QUE_ERR_SHIFT                                                     10
37013 #define PRM_REG_INT_MASK                                                                             0x230044UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37014     #define PRM_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.ADDRESS_ERROR .
37015     #define PRM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
37016     #define PRM_REG_INT_MASK_IFIFO_ERROR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.IFIFO_ERROR .
37017     #define PRM_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                       1
37018     #define PRM_REG_INT_MASK_IMMED_FIFO_ERROR                                                        (0x1<<2) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.IMMED_FIFO_ERROR .
37019     #define PRM_REG_INT_MASK_IMMED_FIFO_ERROR_SHIFT                                                  2
37020     #define PRM_REG_INT_MASK_OFST_PEND_ERROR                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.OFST_PEND_ERROR .
37021     #define PRM_REG_INT_MASK_OFST_PEND_ERROR_SHIFT                                                   3
37022     #define PRM_REG_INT_MASK_PAD_PEND_ERROR                                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.PAD_PEND_ERROR .
37023     #define PRM_REG_INT_MASK_PAD_PEND_ERROR_SHIFT                                                    4
37024     #define PRM_REG_INT_MASK_PBINP_PEND_ERROR                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.PBINP_PEND_ERROR .
37025     #define PRM_REG_INT_MASK_PBINP_PEND_ERROR_SHIFT                                                  5
37026     #define PRM_REG_INT_MASK_TAG_PEND_ERROR                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.TAG_PEND_ERROR .
37027     #define PRM_REG_INT_MASK_TAG_PEND_ERROR_SHIFT                                                    6
37028     #define PRM_REG_INT_MASK_MSTORM_EOP_ERR                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.MSTORM_EOP_ERR .
37029     #define PRM_REG_INT_MASK_MSTORM_EOP_ERR_SHIFT                                                    7
37030     #define PRM_REG_INT_MASK_USTORM_EOP_ERR                                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.USTORM_EOP_ERR .
37031     #define PRM_REG_INT_MASK_USTORM_EOP_ERR_SHIFT                                                    8
37032     #define PRM_REG_INT_MASK_MSTORM_QUE_ERR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.MSTORM_QUE_ERR .
37033     #define PRM_REG_INT_MASK_MSTORM_QUE_ERR_SHIFT                                                    9
37034     #define PRM_REG_INT_MASK_USTORM_QUE_ERR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: PRM_REG_INT_STS.USTORM_QUE_ERR .
37035     #define PRM_REG_INT_MASK_USTORM_QUE_ERR_SHIFT                                                    10
37036 #define PRM_REG_INT_STS_WR                                                                           0x230048UL //Access:WR   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37037     #define PRM_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
37038     #define PRM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
37039     #define PRM_REG_INT_STS_WR_IFIFO_ERROR                                                           (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
37040     #define PRM_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                     1
37041     #define PRM_REG_INT_STS_WR_IMMED_FIFO_ERROR                                                      (0x1<<2) // Overrun/underrun error for the immediate FIFO.
37042     #define PRM_REG_INT_STS_WR_IMMED_FIFO_ERROR_SHIFT                                                2
37043     #define PRM_REG_INT_STS_WR_OFST_PEND_ERROR                                                       (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
37044     #define PRM_REG_INT_STS_WR_OFST_PEND_ERROR_SHIFT                                                 3
37045     #define PRM_REG_INT_STS_WR_PAD_PEND_ERROR                                                        (0x1<<4) // Overrun/underrun error for pad pending FIFO.
37046     #define PRM_REG_INT_STS_WR_PAD_PEND_ERROR_SHIFT                                                  4
37047     #define PRM_REG_INT_STS_WR_PBINP_PEND_ERROR                                                      (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
37048     #define PRM_REG_INT_STS_WR_PBINP_PEND_ERROR_SHIFT                                                5
37049     #define PRM_REG_INT_STS_WR_TAG_PEND_ERROR                                                        (0x1<<6) // Overrun/underrun error for tag pending FIFO.
37050     #define PRM_REG_INT_STS_WR_TAG_PEND_ERROR_SHIFT                                                  6
37051     #define PRM_REG_INT_STS_WR_MSTORM_EOP_ERR                                                        (0x1<<7) // End of packet error on M-Storm command interface.
37052     #define PRM_REG_INT_STS_WR_MSTORM_EOP_ERR_SHIFT                                                  7
37053     #define PRM_REG_INT_STS_WR_USTORM_EOP_ERR                                                        (0x1<<8) // End of packet error on U-Storm command interface.
37054     #define PRM_REG_INT_STS_WR_USTORM_EOP_ERR_SHIFT                                                  8
37055     #define PRM_REG_INT_STS_WR_MSTORM_QUE_ERR                                                        (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
37056     #define PRM_REG_INT_STS_WR_MSTORM_QUE_ERR_SHIFT                                                  9
37057     #define PRM_REG_INT_STS_WR_USTORM_QUE_ERR                                                        (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
37058     #define PRM_REG_INT_STS_WR_USTORM_QUE_ERR_SHIFT                                                  10
37059 #define PRM_REG_INT_STS_CLR                                                                          0x23004cUL //Access:RC   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37060     #define PRM_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
37061     #define PRM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
37062     #define PRM_REG_INT_STS_CLR_IFIFO_ERROR                                                          (0x1<<1) // Overrun/underrun error for the BRB input FIFO.
37063     #define PRM_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                    1
37064     #define PRM_REG_INT_STS_CLR_IMMED_FIFO_ERROR                                                     (0x1<<2) // Overrun/underrun error for the immediate FIFO.
37065     #define PRM_REG_INT_STS_CLR_IMMED_FIFO_ERROR_SHIFT                                               2
37066     #define PRM_REG_INT_STS_CLR_OFST_PEND_ERROR                                                      (0x1<<3) // Overrun/underrun error for BRB offset pending FIFO.
37067     #define PRM_REG_INT_STS_CLR_OFST_PEND_ERROR_SHIFT                                                3
37068     #define PRM_REG_INT_STS_CLR_PAD_PEND_ERROR                                                       (0x1<<4) // Overrun/underrun error for pad pending FIFO.
37069     #define PRM_REG_INT_STS_CLR_PAD_PEND_ERROR_SHIFT                                                 4
37070     #define PRM_REG_INT_STS_CLR_PBINP_PEND_ERROR                                                     (0x1<<5) // Overrun/underrun error for PB input pending FIFO.
37071     #define PRM_REG_INT_STS_CLR_PBINP_PEND_ERROR_SHIFT                                               5
37072     #define PRM_REG_INT_STS_CLR_TAG_PEND_ERROR                                                       (0x1<<6) // Overrun/underrun error for tag pending FIFO.
37073     #define PRM_REG_INT_STS_CLR_TAG_PEND_ERROR_SHIFT                                                 6
37074     #define PRM_REG_INT_STS_CLR_MSTORM_EOP_ERR                                                       (0x1<<7) // End of packet error on M-Storm command interface.
37075     #define PRM_REG_INT_STS_CLR_MSTORM_EOP_ERR_SHIFT                                                 7
37076     #define PRM_REG_INT_STS_CLR_USTORM_EOP_ERR                                                       (0x1<<8) // End of packet error on U-Storm command interface.
37077     #define PRM_REG_INT_STS_CLR_USTORM_EOP_ERR_SHIFT                                                 8
37078     #define PRM_REG_INT_STS_CLR_MSTORM_QUE_ERR                                                       (0x1<<9) // FIFO overflow/underflow error on M-Storm command interface.
37079     #define PRM_REG_INT_STS_CLR_MSTORM_QUE_ERR_SHIFT                                                 9
37080     #define PRM_REG_INT_STS_CLR_USTORM_QUE_ERR                                                       (0x1<<10) // FIFO overflow/underflow error on U-Storm command interface.
37081     #define PRM_REG_INT_STS_CLR_USTORM_QUE_ERR_SHIFT                                                 10
37082 #define PRM_REG_PRTY_MASK                                                                            0x230054UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
37083     #define PRM_REG_PRTY_MASK_DATAPATH_REGISTERS                                                     (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS.DATAPATH_REGISTERS .
37084     #define PRM_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                               0
37085 #define PRM_REG_PRTY_MASK_H_0                                                                        0x230204UL //Access:RW   DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
37086     #define PRM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
37087     #define PRM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_SHIFT                                          0
37088     #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_A0                                          (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
37089     #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_A0_SHIFT                                    0
37090     #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_B0                                          (0x1<<0) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
37091     #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_BB_B0_SHIFT                                    0
37092     #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_K2                                             (0x1<<1) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
37093     #define PRM_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_K2_SHIFT                                       1
37094     #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_A0                                          (0x1<<1) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
37095     #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_A0_SHIFT                                    1
37096     #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_B0                                          (0x1<<1) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
37097     #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_BB_B0_SHIFT                                    1
37098     #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_K2                                             (0x1<<2) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
37099     #define PRM_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_K2_SHIFT                                       2
37100     #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT .
37101     #define PRM_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_SHIFT                                          3
37102     #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
37103     #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0_SHIFT                                      13
37104     #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
37105     #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0_SHIFT                                      13
37106     #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                               (0x1<<4) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
37107     #define PRM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                         4
37108     #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
37109     #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_A0_SHIFT                                      16
37110     #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
37111     #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_B0_SHIFT                                      16
37112     #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
37113     #define PRM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                         5
37114     #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
37115     #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                      11
37116     #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
37117     #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                      11
37118     #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
37119     #define PRM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                         6
37120     #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<6) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
37121     #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      6
37122     #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<6) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
37123     #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      6
37124     #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
37125     #define PRM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                         7
37126     #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
37127     #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                      18
37128     #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0                                            (0x1<<18) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
37129     #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                      18
37130     #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                               (0x1<<8) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
37131     #define PRM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                         8
37132     #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
37133     #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0_SHIFT                                      8
37134     #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0                                            (0x1<<8) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
37135     #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0_SHIFT                                      8
37136     #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
37137     #define PRM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                         9
37138     #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
37139     #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0_SHIFT                                      9
37140     #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
37141     #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0_SHIFT                                      9
37142     #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
37143     #define PRM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT                                         10
37144     #define PRM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
37145     #define PRM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_SHIFT                                            11
37146     #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                            (0x1<<10) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
37147     #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                      10
37148     #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
37149     #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                      10
37150     #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
37151     #define PRM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                         12
37152     #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37153     #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0_SHIFT                                      14
37154     #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37155     #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0_SHIFT                                      14
37156     #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37157     #define PRM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                         13
37158     #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
37159     #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                      20
37160     #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0                                            (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
37161     #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                      20
37162     #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
37163     #define PRM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                         14
37164     #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
37165     #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0_SHIFT                                      4
37166     #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
37167     #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0_SHIFT                                      4
37168     #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
37169     #define PRM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                         15
37170     #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_A0                                            (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
37171     #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_A0_SHIFT                                      21
37172     #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_B0                                            (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
37173     #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_B0_SHIFT                                      21
37174     #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
37175     #define PRM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                         16
37176     #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                            (0x1<<15) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
37177     #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                      15
37178     #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
37179     #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                      15
37180     #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
37181     #define PRM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                         17
37182     #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
37183     #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0_SHIFT                                      17
37184     #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
37185     #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0_SHIFT                                      17
37186     #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
37187     #define PRM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                         18
37188     #define PRM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
37189     #define PRM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            19
37190     #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_A0                                            (0x1<<23) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
37191     #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_A0_SHIFT                                      23
37192     #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_B0                                            (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
37193     #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_B0_SHIFT                                      22
37194     #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2                                               (0x1<<20) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
37195     #define PRM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT                                         20
37196     #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
37197     #define PRM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                            21
37198     #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
37199     #define PRM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_SHIFT                                            22
37200     #define PRM_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT                                                (0x1<<2) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
37201     #define PRM_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT                                          2
37202     #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
37203     #define PRM_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_SHIFT                                          3
37204     #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
37205     #define PRM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_SHIFT                                            5
37206     #define PRM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
37207     #define PRM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_SHIFT                                            7
37208     #define PRM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
37209     #define PRM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                            12
37210     #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
37211     #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      24
37212     #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<23) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
37213     #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      23
37214     #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                               (0x1<<23) // This bit masks, when set, the Parity bit: PRM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
37215     #define PRM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                         23
37216 #define PRM_REG_MEM_ECC_EVENTS                                                                       0x230228UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
37217 #define PRM_REG_MEM004_I_MEM_DFT_K2                                                                  0x230230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_mstorm_cque_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37218 #define PRM_REG_MEM024_I_MEM_DFT_K2                                                                  0x230234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_ustorm_cque_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37219 #define PRM_REG_MEM008_I_MEM_DFT_K2                                                                  0x230238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_dp.i_rdif.i_rdif_cmd_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37220 #define PRM_REG_MEM009_I_MEM_DFT_K2                                                                  0x23023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_dp.i_rdif.i_rdif_data_in_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37221 #define PRM_REG_MEM010_I_MEM_DFT_K2                                                                  0x230240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_dp.i_rdif.i_rdif_dix_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37222 #define PRM_REG_MEM012_I_MEM_DFT_K2                                                                  0x230244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector0_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37223 #define PRM_REG_MEM013_I_MEM_DFT_K2                                                                  0x230248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector1_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37224 #define PRM_REG_MEM014_I_MEM_DFT_K2                                                                  0x23024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector2_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37225 #define PRM_REG_MEM015_I_MEM_DFT_K2                                                                  0x230250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_dp.i_rdif.i_rdif_l1_sector3_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37226 #define PRM_REG_MEM011_I_MEM_DFT_K2                                                                  0x230254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_dp.i_rdif.i_rdif_err_debug_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37227 #define PRM_REG_MEM003_I_MEM_DFT_K2                                                                  0x230258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_inp_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37228 #define PRM_REG_MEM002_I_MEM_DFT_K2                                                                  0x23025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_immed_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37229 #define PRM_REG_MEM023_I_MEM_DFT_K2                                                                  0x230260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_tag_pend_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37230 #define PRM_REG_MEM006_I_MEM_DFT_K2                                                                  0x230264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_pad_pend_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37231 #define PRM_REG_MEM007_I_MEM_DFT_K2                                                                  0x230268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_pbinp_pend_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37232 #define PRM_REG_MEM001_I_MEM_DFT_K2                                                                  0x23026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_cmp_msg_queue.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37233 #define PRM_REG_MEM018_I_MEM_DFT_K2                                                                  0x230270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_rpb_data_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37234 #define PRM_REG_MEM020_I_MEM_DFT_K2                                                                  0x230274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_rpb_l1_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37235 #define PRM_REG_MEM021_I_MEM_DFT_K2                                                                  0x230278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_rpb_lo_task_que.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37236 #define PRM_REG_MEM019_I_MEM_DFT_K2                                                                  0x23027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance prm.i_prm_rpb_hi_task_que.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37237 #define PRM_REG_TAG_SZ                                                                               0x230400UL //Access:RW   DataWidth:0x4   Array of registers provides a size (in units of two bytes) for each of the possible seven configurable L2 tags to remove, where the direct register index corresponds with the tag ID. The actual value to remove in bytes will be defined by the following: size (bytes) = (tag_sz+1)*2. Note: there is no tag_sz register for tag ID = 0x7 because this is the LLC/Snap tag ID and is not configurable.  Chips: BB_A0 BB_B0 K2
37238 #define PRM_REG_TAG_SZ_SIZE                                                                          7
37239 #define PRM_REG_PAD_DATA                                                                             0x230420UL //Access:RW   DataWidth:0x10  Provides the value of the 16-bit pad that will be inserted into the PXP data stream when pad insertion is enabled.  Chips: BB_A0 BB_B0 K2
37240 #define PRM_REG_PAD_FROM_DBG                                                                         0x230424UL //Access:RW   DataWidth:0x1   When set, this bit enables the pad insertion logic to use BRB debug field from the PRM command to define the value of the inserted pad; otherwise the pad_data configuration is used.  Chips: BB_A0 BB_B0 K2
37241 #define PRM_REG_INIT_CREDIT_PXP                                                                      0x230428UL //Access:RW   DataWidth:0x3   Initial credit to be used on the PXP request interface. This value defines the maximum number of outstanding requests allowed.  Chips: BB_A0 BB_B0 K2
37242 #define PRM_REG_INIT_CREDIT_RDIF_CMD                                                                 0x23042cUL //Access:RW   DataWidth:0x4   Initial credit to be used on the RDIF command interface for regular (non-pass-through) requests. This value defines the maximum number of outstanding regular commands allowed.  Chips: BB_A0 BB_B0 K2
37243 #define PRM_REG_INIT_CREDIT_RDIF_PTH                                                                 0x230430UL //Access:RW   DataWidth:0x6   Initial credit to be used on the RDIF command interface for pass-through requests. This value defines the maximum number of outstanding pass-through commands allowed.  Chips: BB_A0 BB_B0 K2
37244 #define PRM_REG_RPB_DB_FULL_THR                                                                      0x230500UL //Access:RW   DataWidth:0x6   Defines the number of occupied entries required in the RPB data buffer before the full signal will be asserted.  Chips: BB_A0 BB_B0 K2
37245 #define PRM_REG_RPB_TQ_FULL_THR                                                                      0x230504UL //Access:RW   DataWidth:0x7   Defines the number of occupied entries required in the RPB task queue before the full signal will be asserted.  Chips: BB_A0 BB_B0 K2
37246 #define PRM_REG_IFIFO_FULL_THR                                                                       0x230508UL //Access:RW   DataWidth:0x5   Defines the number of occupied entries required in the BRB input FIFO before the full signal will be asserted.  Chips: BB_A0 BB_B0 K2
37247 #define PRM_REG_ECO_RESERVED                                                                         0x23050cUL //Access:RW   DataWidth:0x20  This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: BB_A0 BB_B0 K2
37248 #define PRM_REG_PXP_RESP_FULL_THR                                                                    0x230510UL //Access:RW   DataWidth:0x6   Defines the number of occupied entries required in the PXP read-response FIFO before the full signal will be asserted.  Chips: BB_A0 BB_B0 K2
37249 #define PRM_REG_NUM_OF_MSTORM_CMD                                                                    0x230600UL //Access:RC   DataWidth:0x18  Statistics counter provides a count of the number of M-Storm comands that have been received by the PRM.  Chips: BB_A0 BB_B0 K2
37250 #define PRM_REG_NUM_OF_USTORM_CMD                                                                    0x230604UL //Access:RC   DataWidth:0x18  Statistics counter provides a count of the number of U-Storm comands that have been received by the PRM.  Chips: BB_A0 BB_B0 K2
37251 #define PRM_REG_DBG_OUT_DATA                                                                         0x230680UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
37252 #define PRM_REG_DBG_OUT_DATA_SIZE                                                                    8
37253 #define PRM_REG_DBG_OUT_VALID                                                                        0x2306a0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
37254 #define PRM_REG_DBG_OUT_FRAME                                                                        0x2306a4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
37255 #define PRM_REG_DBG_SELECT                                                                           0x2306a8UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
37256 #define PRM_REG_DBG_DWORD_ENABLE                                                                     0x2306acUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
37257 #define PRM_REG_DBG_SHIFT                                                                            0x2306b0UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
37258 #define PRM_REG_DBG_FORCE_VALID                                                                      0x2306b4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37259 #define PRM_REG_DBG_FORCE_FRAME                                                                      0x2306b8UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37260 #define PRM_REG_MSTORM_CMD_QUE                                                                       0x232000UL //Access:WB_R DataWidth:0x80  Provides read-only access of the M-Storm command queue. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37261 #define PRM_REG_MSTORM_CMD_QUE_SIZE                                                                  132
37262 #define PRM_REG_USTORM_CMD_QUE                                                                       0x232400UL //Access:WB_R DataWidth:0x80  Provides read-only access of the U-Storm command queue. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37263 #define PRM_REG_USTORM_CMD_QUE_SIZE                                                                  132
37264 #define PRM_REG_BRB_INP_FIFO                                                                         0x232800UL //Access:WB_R DataWidth:0x108 Provides read-only access of the BRB input FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37265 #define PRM_REG_BRB_INP_FIFO_SIZE                                                                    144
37266 #define PRM_REG_OFST_PEND_FIFO                                                                       0x232c00UL //Access:R    DataWidth:0x7   Provides read-only access of the BRB ofset pending request FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37267 #define PRM_REG_OFST_PEND_FIFO_SIZE                                                                  49
37268 #define PRM_REG_TAG_PEND_FIFO                                                                        0x233000UL //Access:WB_R DataWidth:0x2c  Provides read-only access of the tag removal pending request FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37269 #define PRM_REG_TAG_PEND_FIFO_SIZE                                                                   98
37270 #define PRM_REG_PAD_PEND_FIFO                                                                        0x233400UL //Access:R    DataWidth:0x11  Provides read-only access of the pad insertion pending request FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37271 #define PRM_REG_PAD_PEND_FIFO_SIZE                                                                   49
37272 #define PRM_REG_PBINP_PEND_FIFO                                                                      0x233600UL //Access:R    DataWidth:0xb   Provides read-only access of the PB input pending request FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37273 #define PRM_REG_PBINP_PEND_FIFO_SIZE                                                                 49
37274 #define PRM_REG_IMMED_FIFO                                                                           0x233800UL //Access:WB_R DataWidth:0x100 Provides read-only access of the PRM immediate data FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37275 #define PRM_REG_IMMED_FIFO_SIZE                                                                      72
37276 #define PRM_REG_WDONE_FIFO                                                                           0x233c00UL //Access:R    DataWidth:0x8   Provides read-only access of the PXP write-done response FIFO. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37277 #define PRM_REG_WDONE_FIFO_SIZE                                                                      54
37278 #define PRM_REG_DIR_MSG_BUF                                                                          0x234000UL //Access:WB   DataWidth:0x80  Provides read/write access to the PRM completion message queue. Intended for test/debug purposes.  Chips: BB_A0 BB_B0 K2
37279 #define PRM_REG_DIR_MSG_BUF_SIZE                                                                     1272
37280 #define PRM_REG_NOP_WITHOUT_COMPLETION_FIX_DISABLE                                                   0x236000UL //Access:RW   DataWidth:0x1   Chicken Bit for the NOP without completion fix  Chips: K2
37281 #define SRC_REG_CTRL                                                                                 0x238040UL //Access:RW   DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
37282     #define SRC_REG_CTRL_NUM_CONCURRENT_PROCESSES                                                    (0xff<<0) // Number of Concurrent Processes (State Machines); Values can be 1 to 25.
37283     #define SRC_REG_CTRL_NUM_CONCURRENT_PROCESSES_SHIFT                                              0
37284     #define SRC_REG_CTRL_MAXNUMHOPS                                                                  (0xff<<8) // The maximum allowed HOP to search.
37285     #define SRC_REG_CTRL_MAXNUMHOPS_SHIFT                                                            8
37286     #define SRC_REG_CTRL_VLAN_HASH_ENABLE                                                            (0x1<<16) // Enable for VLAN in Hash Address. !!! NOTE : vlan_hash_enable == 1 and vlan_match_disable == 1 is illegal !!!
37287     #define SRC_REG_CTRL_VLAN_HASH_ENABLE_SHIFT                                                      16
37288     #define SRC_REG_CTRL_VLAN_MATCH_DISABLE                                                          (0x1<<17) // Disable VLAN and VLAN Promiscuous Mode (vpf) matching logic.!!! NOTE : vlan_hash_enable == 1 and vlan_match_disable == 1 is illegal !!!
37289     #define SRC_REG_CTRL_VLAN_MATCH_DISABLE_SHIFT                                                    17
37290     #define SRC_REG_CTRL_STRING_MATCH_DISABLE                                                        (0x1<<18) // Disable String Matching Logic.
37291     #define SRC_REG_CTRL_STRING_MATCH_DISABLE_SHIFT                                                  18
37292     #define SRC_REG_CTRL_ALLOWSHORTCUT                                                               (0x1<<19) // If set; same search shortcut is allowed.
37293     #define SRC_REG_CTRL_ALLOWSHORTCUT_SHIFT                                                         19
37294     #define SRC_REG_CTRL_ALLOWEMPTYSHORTCUT                                                          (0x1<<20) // If set; search return no match on empty shortcut is allowed.
37295     #define SRC_REG_CTRL_ALLOWEMPTYSHORTCUT_SHIFT                                                    20
37296     #define SRC_REG_CTRL_TENANT_ID_DISABLE                                                           (0x1<<21) // Disable Tenant ID Matching Logic.NOTE : tenant_id_in_hash_en == 1 and tenant_id_disable == 1 is illegal !!!
37297     #define SRC_REG_CTRL_TENANT_ID_DISABLE_SHIFT                                                     21
37298     #define SRC_REG_CTRL_TENANT_ID_IN_HASH_EN                                                        (0x1<<22) // Enables the use of the tenant_id value in Hash address calculation.!!! NOTE : tenant_id_in_hash_en == 1 and tenant_id_disable == 1 is illegal !!!
37299     #define SRC_REG_CTRL_TENANT_ID_IN_HASH_EN_SHIFT                                                  22
37300 #define SRC_REG_INT_STS                                                                              0x2381d8UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37301     #define SRC_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
37302     #define SRC_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
37303 #define SRC_REG_INT_STS_CLR                                                                          0x2381dcUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37304     #define SRC_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
37305     #define SRC_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
37306 #define SRC_REG_INT_STS_WR                                                                           0x2381e0UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37307     #define SRC_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
37308     #define SRC_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
37309 #define SRC_REG_INT_MASK                                                                             0x2381e4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37310     #define SRC_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: SRC_REG_INT_STS.ADDRESS_ERROR .
37311     #define SRC_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
37312 #define SRC_REG_KEYSEARCH_0                                                                          0x238400UL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37313 #define SRC_REG_KEYSEARCH_1                                                                          0x238404UL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37314 #define SRC_REG_KEYSEARCH_2                                                                          0x238408UL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37315 #define SRC_REG_KEYSEARCH_3                                                                          0x23840cUL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37316 #define SRC_REG_KEYSEARCH_4                                                                          0x238410UL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37317 #define SRC_REG_KEYSEARCH_5                                                                          0x238414UL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37318 #define SRC_REG_KEYSEARCH_6                                                                          0x238418UL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37319 #define SRC_REG_KEYSEARCH_7                                                                          0x23841cUL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37320 #define SRC_REG_KEYSEARCH_8                                                                          0x238420UL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37321 #define SRC_REG_KEYSEARCH_9                                                                          0x238424UL //Access:RW   DataWidth:0x20  Key for searcher hash function.  Chips: BB_A0 BB_B0 K2
37322 #define SRC_REG_KEYSEARCH_VLAN                                                                       0x238428UL //Access:RW   DataWidth:0xc   Key for searcher hash function vlan field. HAS NO EFFECT IN E4 B0!!!  Chips: BB_A0 BB_B0 K2
37323 #define SRC_REG_IF_STAT_PF_CONFIG                                                                    0x238480UL //Access:RW   DataWidth:0x10  Per-PF Bitmask for inclusion in Ingress Flow Statistics counters.  Chips: BB_A0 BB_B0 K2
37324 #define SRC_REG_IF_STAT_STRTYPE_CONFIG                                                               0x238484UL //Access:RW   DataWidth:0x8   Per-StringType Bitmask for inclusion in Ingress Flow Statistics counters.  Chips: BB_A0 BB_B0 K2
37325 #define SRC_REG_IF_STAT_ENABLED                                                                      0x238488UL //Access:RW   DataWidth:0x1   IF Stats Enable Bit.  IF Stat Counters only count when this bit is set.     This bit is cleared when any IF Stat Counter is read to ensure coherency.     Setting this bit clears all IF Stat Counters.  Chips: BB_A0 BB_B0 K2
37326 #define SRC_REG_IF_STAT_SEARCH_COUNTER                                                               0x23848cUL //Access:R    DataWidth:0x20  IF Stat Search Counter.  This register counts all Search Requests received.  Chips: BB_A0 BB_B0 K2
37327 #define SRC_REG_IF_STAT_HIT_COUNTER                                                                  0x238490UL //Access:R    DataWidth:0x20  IF Stat Hit Counter.  This register counts all Search Hits on both Table 1 and Table 2.  Chips: BB_A0 BB_B0 K2
37328 #define SRC_REG_IF_STAT_T1_HIT_COUNTER                                                               0x238494UL //Access:R    DataWidth:0x20  IF Stat T1 Hit Counter.  This register counts all Search Hits on Table 1 only.  Chips: BB_A0 BB_B0 K2
37329 #define SRC_REG_IF_STAT_NO_READ_COUNTER                                                              0x238498UL //Access:R    DataWidth:0x20  IF Stat No Read Counter.  This register counts all Search requests which did not generate a Table     Access.  This is caused when there is an outstanding request for the same string.  Chips: BB_A0 BB_B0 K2
37330 #define SRC_REG_NUMIPV4CONN                                                                          0x23849cUL //Access:R    DataWidth:0x1a  Number of Ipv4 connections (statistics).  Chips: BB_A0 BB_B0 K2
37331 #define SRC_REG_NUMIPV6CONN                                                                          0x2384a0UL //Access:R    DataWidth:0x1a  Number of Ipv6 connections (statistics).  Chips: BB_A0 BB_B0 K2
37332 #define SRC_REG_FIRSTFREE                                                                            0x238500UL //Access:WB   DataWidth:0x40  First free element in the free list of T2 entries  Chips: BB_A0 BB_B0 K2
37333 #define SRC_REG_FIRSTFREE_SIZE                                                                       2
37334 #define SRC_REG_LASTFREE                                                                             0x238520UL //Access:WB   DataWidth:0x40  Last free element in the free list of T2 entries  Chips: BB_A0 BB_B0 K2
37335 #define SRC_REG_LASTFREE_SIZE                                                                        2
37336 #define SRC_REG_COUNTFREE                                                                            0x238540UL //Access:RW   DataWidth:0x16  Number of free element in the free list of T2 entries  Chips: BB_A0 BB_B0 K2
37337 #define SRC_REG_PXP_CTRL                                                                             0x238600UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37338     #define SRC_REG_PXP_CTRL_PXP_ATC_T1                                                              (0x7<<0) // Controls PXP Request ATC Field for Table1.
37339     #define SRC_REG_PXP_CTRL_PXP_ATC_T1_SHIFT                                                        0
37340     #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T1                                                         (0x1<<3) // Controls PXP Request TPH Valid field for Table1.
37341     #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T1_SHIFT                                                   3
37342     #define SRC_REG_PXP_CTRL_PXP_ATC_T2                                                              (0x7<<4) // Controls PXP Request ATC Field for Table2.
37343     #define SRC_REG_PXP_CTRL_PXP_ATC_T2_SHIFT                                                        4
37344     #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T2                                                         (0x1<<7) // Controls PXP Request TPH Valid field for Table2.
37345     #define SRC_REG_PXP_CTRL_PXP_TPHVALID_T2_SHIFT                                                   7
37346     #define SRC_REG_PXP_CTRL_PXP_DONETYPE                                                            (0x1<<8) // Controls PXP Request DonType Field.
37347     #define SRC_REG_PXP_CTRL_PXP_DONETYPE_SHIFT                                                      8
37348 #define SRC_REG_NUMBER_HASH_BITS                                                                     0x238604UL //Access:RW   DataWidth:0x5   The number of hash bits used for the search (h); Values can be 8 to 24.  Chips: BB_A0 BB_B0 K2
37349 #define SRC_REG_EMPTY_PF                                                                             0x238620UL //Access:RW   DataWidth:0x20  Empty bit per bin 256 bins per PF.  Chips: BB_A0 BB_B0 K2
37350 #define SRC_REG_EMPTY_PF_SIZE                                                                        8
37351 #define SRC_REG_DBG_SELECT                                                                           0x238700UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
37352 #define SRC_REG_DBG_DWORD_ENABLE                                                                     0x238704UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
37353 #define SRC_REG_DBG_SHIFT                                                                            0x238708UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
37354 #define SRC_REG_DBG_FORCE_VALID                                                                      0x23870cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37355 #define SRC_REG_DBG_FORCE_FRAME                                                                      0x238710UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37356 #define SRC_REG_DBG_OUT_DATA                                                                         0x238720UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
37357 #define SRC_REG_DBG_OUT_DATA_SIZE                                                                    8
37358 #define SRC_REG_DBG_OUT_VALID                                                                        0x238740UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
37359 #define SRC_REG_DBG_OUT_FRAME                                                                        0x238744UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
37360 #define SRC_REG_ECO_RESERVED                                                                         0x238748UL //Access:RW   DataWidth:0x8   ECO reserved.  Chips: BB_A0 BB_B0 K2
37361 #define SRC_REG_SOFT_RST                                                                             0x23874cUL //Access:RW   DataWidth:0x19  Reset internal state machines.  Chips: BB_A0 BB_B0 K2
37362 #define RSS_REG_RSS_INIT_EN                                                                          0x238804UL //Access:RW   DataWidth:0x1   Write to this register will initialize all rows of RSS memory to zeros.It will be be set to 0 when init will be finished.  Chips: BB_A0 BB_B0 K2
37363 #define RSS_REG_RSS_INIT_DONE                                                                        0x238808UL //Access:R    DataWidth:0x1   This register will be set when init procedure of RSS memory is finished.  Chips: BB_A0 BB_B0 K2
37364 #define RSS_REG_IF_ENABLE                                                                            0x23880cUL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37365     #define RSS_REG_IF_ENABLE_TMLD_INP_EN                                                            (0x1<<0) // TM loader input interface enable register.
37366     #define RSS_REG_IF_ENABLE_TMLD_INP_EN_SHIFT                                                      0
37367     #define RSS_REG_IF_ENABLE_TSEM_INP_EN                                                            (0x1<<1) // TSEM input interface enable register.
37368     #define RSS_REG_IF_ENABLE_TSEM_INP_EN_SHIFT                                                      1
37369     #define RSS_REG_IF_ENABLE_TMLD_OUT_EN                                                            (0x1<<2) // TM loader output interface enable register.
37370     #define RSS_REG_IF_ENABLE_TMLD_OUT_EN_SHIFT                                                      2
37371     #define RSS_REG_IF_ENABLE_TSEM_OUT_EN                                                            (0x1<<3) // TSEM output interface enable register.
37372     #define RSS_REG_IF_ENABLE_TSEM_OUT_EN_SHIFT                                                      3
37373 #define RSS_REG_INT_STS                                                                              0x238980UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37374     #define RSS_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
37375     #define RSS_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
37376     #define RSS_REG_INT_STS_MSG_INP_CNT_ERROR                                                        (0x1<<1) // Number of cycles in CM message from TSEM is 63.
37377     #define RSS_REG_INT_STS_MSG_INP_CNT_ERROR_SHIFT                                                  1
37378     #define RSS_REG_INT_STS_MSG_OUT_CNT_ERROR                                                        (0x1<<2) // Number of cycles in CM message to TM loader is 63.
37379     #define RSS_REG_INT_STS_MSG_OUT_CNT_ERROR_SHIFT                                                  2
37380     #define RSS_REG_INT_STS_INP_STATE_ERROR                                                          (0x1<<3) // Input state machine reached error state.
37381     #define RSS_REG_INT_STS_INP_STATE_ERROR_SHIFT                                                    3
37382     #define RSS_REG_INT_STS_OUT_STATE_ERROR                                                          (0x1<<4) // Output state machine reached error state.
37383     #define RSS_REG_INT_STS_OUT_STATE_ERROR_SHIFT                                                    4
37384     #define RSS_REG_INT_STS_MAIN_STATE_ERROR                                                         (0x1<<5) // Main state machine in RSS calculation block reached error state.
37385     #define RSS_REG_INT_STS_MAIN_STATE_ERROR_SHIFT                                                   5
37386     #define RSS_REG_INT_STS_CALC_STATE_ERROR                                                         (0x1<<6) // CALC state machine in RSS calculation block reached error state.
37387     #define RSS_REG_INT_STS_CALC_STATE_ERROR_SHIFT                                                   6
37388     #define RSS_REG_INT_STS_INP_FIFO_ERROR                                                           (0x1<<7) // Input FIFO overflow or underflow.
37389     #define RSS_REG_INT_STS_INP_FIFO_ERROR_SHIFT                                                     7
37390     #define RSS_REG_INT_STS_CMD_FIFO_ERROR                                                           (0x1<<8) // RSS command FIFO overflow or underflow.
37391     #define RSS_REG_INT_STS_CMD_FIFO_ERROR_SHIFT                                                     8
37392     #define RSS_REG_INT_STS_MSG_FIFO_ERROR                                                           (0x1<<9) // Message FIFO overflow or underflow.
37393     #define RSS_REG_INT_STS_MSG_FIFO_ERROR_SHIFT                                                     9
37394     #define RSS_REG_INT_STS_RSP_FIFO_ERROR                                                           (0x1<<10) // Response FIFO overflow or underflow.
37395     #define RSS_REG_INT_STS_RSP_FIFO_ERROR_SHIFT                                                     10
37396     #define RSS_REG_INT_STS_HDR_FIFO_ERROR                                                           (0x1<<11) // Header FIFO overflow or underflow.
37397     #define RSS_REG_INT_STS_HDR_FIFO_ERROR_SHIFT                                                     11
37398 #define RSS_REG_INT_MASK                                                                             0x238984UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37399     #define RSS_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.ADDRESS_ERROR .
37400     #define RSS_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
37401     #define RSS_REG_INT_MASK_MSG_INP_CNT_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_INP_CNT_ERROR .
37402     #define RSS_REG_INT_MASK_MSG_INP_CNT_ERROR_SHIFT                                                 1
37403     #define RSS_REG_INT_MASK_MSG_OUT_CNT_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_OUT_CNT_ERROR .
37404     #define RSS_REG_INT_MASK_MSG_OUT_CNT_ERROR_SHIFT                                                 2
37405     #define RSS_REG_INT_MASK_INP_STATE_ERROR                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.INP_STATE_ERROR .
37406     #define RSS_REG_INT_MASK_INP_STATE_ERROR_SHIFT                                                   3
37407     #define RSS_REG_INT_MASK_OUT_STATE_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.OUT_STATE_ERROR .
37408     #define RSS_REG_INT_MASK_OUT_STATE_ERROR_SHIFT                                                   4
37409     #define RSS_REG_INT_MASK_MAIN_STATE_ERROR                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MAIN_STATE_ERROR .
37410     #define RSS_REG_INT_MASK_MAIN_STATE_ERROR_SHIFT                                                  5
37411     #define RSS_REG_INT_MASK_CALC_STATE_ERROR                                                        (0x1<<6) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.CALC_STATE_ERROR .
37412     #define RSS_REG_INT_MASK_CALC_STATE_ERROR_SHIFT                                                  6
37413     #define RSS_REG_INT_MASK_INP_FIFO_ERROR                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.INP_FIFO_ERROR .
37414     #define RSS_REG_INT_MASK_INP_FIFO_ERROR_SHIFT                                                    7
37415     #define RSS_REG_INT_MASK_CMD_FIFO_ERROR                                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.CMD_FIFO_ERROR .
37416     #define RSS_REG_INT_MASK_CMD_FIFO_ERROR_SHIFT                                                    8
37417     #define RSS_REG_INT_MASK_MSG_FIFO_ERROR                                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.MSG_FIFO_ERROR .
37418     #define RSS_REG_INT_MASK_MSG_FIFO_ERROR_SHIFT                                                    9
37419     #define RSS_REG_INT_MASK_RSP_FIFO_ERROR                                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.RSP_FIFO_ERROR .
37420     #define RSS_REG_INT_MASK_RSP_FIFO_ERROR_SHIFT                                                    10
37421     #define RSS_REG_INT_MASK_HDR_FIFO_ERROR                                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: RSS_REG_INT_STS.HDR_FIFO_ERROR .
37422     #define RSS_REG_INT_MASK_HDR_FIFO_ERROR_SHIFT                                                    11
37423 #define RSS_REG_INT_STS_WR                                                                           0x238988UL //Access:WR   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37424     #define RSS_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
37425     #define RSS_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
37426     #define RSS_REG_INT_STS_WR_MSG_INP_CNT_ERROR                                                     (0x1<<1) // Number of cycles in CM message from TSEM is 63.
37427     #define RSS_REG_INT_STS_WR_MSG_INP_CNT_ERROR_SHIFT                                               1
37428     #define RSS_REG_INT_STS_WR_MSG_OUT_CNT_ERROR                                                     (0x1<<2) // Number of cycles in CM message to TM loader is 63.
37429     #define RSS_REG_INT_STS_WR_MSG_OUT_CNT_ERROR_SHIFT                                               2
37430     #define RSS_REG_INT_STS_WR_INP_STATE_ERROR                                                       (0x1<<3) // Input state machine reached error state.
37431     #define RSS_REG_INT_STS_WR_INP_STATE_ERROR_SHIFT                                                 3
37432     #define RSS_REG_INT_STS_WR_OUT_STATE_ERROR                                                       (0x1<<4) // Output state machine reached error state.
37433     #define RSS_REG_INT_STS_WR_OUT_STATE_ERROR_SHIFT                                                 4
37434     #define RSS_REG_INT_STS_WR_MAIN_STATE_ERROR                                                      (0x1<<5) // Main state machine in RSS calculation block reached error state.
37435     #define RSS_REG_INT_STS_WR_MAIN_STATE_ERROR_SHIFT                                                5
37436     #define RSS_REG_INT_STS_WR_CALC_STATE_ERROR                                                      (0x1<<6) // CALC state machine in RSS calculation block reached error state.
37437     #define RSS_REG_INT_STS_WR_CALC_STATE_ERROR_SHIFT                                                6
37438     #define RSS_REG_INT_STS_WR_INP_FIFO_ERROR                                                        (0x1<<7) // Input FIFO overflow or underflow.
37439     #define RSS_REG_INT_STS_WR_INP_FIFO_ERROR_SHIFT                                                  7
37440     #define RSS_REG_INT_STS_WR_CMD_FIFO_ERROR                                                        (0x1<<8) // RSS command FIFO overflow or underflow.
37441     #define RSS_REG_INT_STS_WR_CMD_FIFO_ERROR_SHIFT                                                  8
37442     #define RSS_REG_INT_STS_WR_MSG_FIFO_ERROR                                                        (0x1<<9) // Message FIFO overflow or underflow.
37443     #define RSS_REG_INT_STS_WR_MSG_FIFO_ERROR_SHIFT                                                  9
37444     #define RSS_REG_INT_STS_WR_RSP_FIFO_ERROR                                                        (0x1<<10) // Response FIFO overflow or underflow.
37445     #define RSS_REG_INT_STS_WR_RSP_FIFO_ERROR_SHIFT                                                  10
37446     #define RSS_REG_INT_STS_WR_HDR_FIFO_ERROR                                                        (0x1<<11) // Header FIFO overflow or underflow.
37447     #define RSS_REG_INT_STS_WR_HDR_FIFO_ERROR_SHIFT                                                  11
37448 #define RSS_REG_INT_STS_CLR                                                                          0x23898cUL //Access:RC   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37449     #define RSS_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
37450     #define RSS_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
37451     #define RSS_REG_INT_STS_CLR_MSG_INP_CNT_ERROR                                                    (0x1<<1) // Number of cycles in CM message from TSEM is 63.
37452     #define RSS_REG_INT_STS_CLR_MSG_INP_CNT_ERROR_SHIFT                                              1
37453     #define RSS_REG_INT_STS_CLR_MSG_OUT_CNT_ERROR                                                    (0x1<<2) // Number of cycles in CM message to TM loader is 63.
37454     #define RSS_REG_INT_STS_CLR_MSG_OUT_CNT_ERROR_SHIFT                                              2
37455     #define RSS_REG_INT_STS_CLR_INP_STATE_ERROR                                                      (0x1<<3) // Input state machine reached error state.
37456     #define RSS_REG_INT_STS_CLR_INP_STATE_ERROR_SHIFT                                                3
37457     #define RSS_REG_INT_STS_CLR_OUT_STATE_ERROR                                                      (0x1<<4) // Output state machine reached error state.
37458     #define RSS_REG_INT_STS_CLR_OUT_STATE_ERROR_SHIFT                                                4
37459     #define RSS_REG_INT_STS_CLR_MAIN_STATE_ERROR                                                     (0x1<<5) // Main state machine in RSS calculation block reached error state.
37460     #define RSS_REG_INT_STS_CLR_MAIN_STATE_ERROR_SHIFT                                               5
37461     #define RSS_REG_INT_STS_CLR_CALC_STATE_ERROR                                                     (0x1<<6) // CALC state machine in RSS calculation block reached error state.
37462     #define RSS_REG_INT_STS_CLR_CALC_STATE_ERROR_SHIFT                                               6
37463     #define RSS_REG_INT_STS_CLR_INP_FIFO_ERROR                                                       (0x1<<7) // Input FIFO overflow or underflow.
37464     #define RSS_REG_INT_STS_CLR_INP_FIFO_ERROR_SHIFT                                                 7
37465     #define RSS_REG_INT_STS_CLR_CMD_FIFO_ERROR                                                       (0x1<<8) // RSS command FIFO overflow or underflow.
37466     #define RSS_REG_INT_STS_CLR_CMD_FIFO_ERROR_SHIFT                                                 8
37467     #define RSS_REG_INT_STS_CLR_MSG_FIFO_ERROR                                                       (0x1<<9) // Message FIFO overflow or underflow.
37468     #define RSS_REG_INT_STS_CLR_MSG_FIFO_ERROR_SHIFT                                                 9
37469     #define RSS_REG_INT_STS_CLR_RSP_FIFO_ERROR                                                       (0x1<<10) // Response FIFO overflow or underflow.
37470     #define RSS_REG_INT_STS_CLR_RSP_FIFO_ERROR_SHIFT                                                 10
37471     #define RSS_REG_INT_STS_CLR_HDR_FIFO_ERROR                                                       (0x1<<11) // Header FIFO overflow or underflow.
37472     #define RSS_REG_INT_STS_CLR_HDR_FIFO_ERROR_SHIFT                                                 11
37473 #define RSS_REG_PRTY_MASK_H_0                                                                        0x238a04UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37474     #define RSS_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
37475     #define RSS_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT                                          0
37476     #define RSS_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
37477     #define RSS_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                          1
37478     #define RSS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37479     #define RSS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            2
37480     #define RSS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: RSS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
37481     #define RSS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            3
37482 #define RSS_REG_MEM_ECC_EVENTS                                                                       0x238a1cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
37483 #define RSS_REG_MEM003_I_MEM_DFT_K2                                                                  0x238a24UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance rss.i_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37484 #define RSS_REG_MEM004_I_MEM_DFT_K2                                                                  0x238a28UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance rss.i_msg_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37485 #define RSS_REG_MEM002_I_MEM_DFT_K2                                                                  0x238a2cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance rss.RSS_MEM_K2_GEN_IF.i_rss_mem_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37486 #define RSS_REG_MEM001_I_MEM_DFT_K2                                                                  0x238a30UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance rss.RSS_IND_K2_GEN_IF.i_rss_ind_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37487 #define RSS_REG_KEY_RSS_EXT5                                                                         0x238c00UL //Access:RW   DataWidth:0x8   Key extension for 5th tuple.  Chips: BB_A0 BB_B0 K2
37488 #define RSS_REG_TMLD_CREDIT                                                                          0x238c04UL //Access:RW   DataWidth:0x6   Number of credits on RSS interface to TMLD. Maaximal supported value is 62.  Chips: BB_A0 BB_B0 K2
37489 #define RSS_REG_RSS_RAM_MASK                                                                         0x238c10UL //Access:WB   DataWidth:0x80  RSS RAM bit enable. It will be used for write operation from RBC. If it equals to 1 then rss_ram_data for appropriate location will be written. Other way data will stay in this place without change.  Chips: BB_A0 BB_B0 K2
37490 #define RSS_REG_RSS_RAM_MASK_SIZE                                                                    4
37491 #define RSS_REG_RSS_RAM_DATA                                                                         0x238c20UL //Access:WB   DataWidth:0x80  RSS RAM data. Read or write to this register will generate read or write transaction to RSS memory. Write data in this register will stay till next read command. After read was done to this register then vaue of this register will be changed to read data from RSS memory.  Chips: BB_A0 BB_B0 K2
37492 #define RSS_REG_RSS_RAM_DATA_SIZE                                                                    4
37493 #define RSS_REG_RSS_RAM_ADDR                                                                         0x238c30UL //Access:RW   DataWidth:0xd   RSS RAM address. If bit 12 is 0 then access is done to RSS memory according to 12 LSB bits. If bit 12 is 1 then access is done to RSS indirection memory according to 12 LSB bits : If bits 11:10 is 0 then bits 9:0 is address to RSS CID table; If bits 11:10 is 1 then bits 9:0 is address to RSS KEY MSB table; If bits 11:10 is 2 then bits 9:0 is address to RSS KEY LSB table; If bits 11:10 is 3 then bits 9:0 is address to RSS INFO table.  Chips: BB_A0 BB_B0 K2
37494 #define RSS_REG_RBC_STATUS                                                                           0x238c34UL //Access:R    DataWidth:0x2   B0 is asserted when RSS got request from RBC that is still not done; B1 is asserted when RSS executed read or write request from RBC and next request still wasn't received.  Chips: BB_A0 BB_B0 K2
37495 #define RSS_REG_EMPTY_STATUS                                                                         0x238c38UL //Access:R    DataWidth:0x5   Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP FIFO; b4- RSS header FIFO}.  Chips: BB_A0 BB_B0 K2
37496 #define RSS_REG_FULL_STATUS                                                                          0x238c3cUL //Access:R    DataWidth:0x5   Debug register. FIFO empty status: {b0 - MSG FIFO; b1- RSS CMD FIFO; b2- INPUT FIFO; b3 - RSP FIFO; b4- RSS header FIFO}.  Chips: BB_A0 BB_B0 K2
37497 #define RSS_REG_COUNTERS_STATUS                                                                      0x238c40UL //Access:R    DataWidth:0x20  Debug register. FIFO empty status: {b15:8 - inp_fifo_counter; b7:6- cmd_fifo_couter; b5:0 - msg_fifo_counter}.  Chips: BB_A0 BB_B0 K2
37498 #define RSS_REG_STATE_MACHINES                                                                       0x238c44UL //Access:R    DataWidth:0x10  Debug register. State of each state machine {b15:12 - calc_cur_state; b11:8 - main_cur_state;b7:4 - msg_cur_state; b3:0 - inp_cur_state}.  Chips: BB_A0 BB_B0 K2
37499 #define RSS_REG_ECO_RESERVED                                                                         0x238c48UL //Access:RW   DataWidth:0x20  This is unused register for future ECOs.  Chips: BB_A0 BB_B0 K2
37500 #define RSS_REG_DBG_SELECT                                                                           0x238c4cUL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
37501 #define RSS_REG_DBG_DWORD_ENABLE                                                                     0x238c50UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
37502 #define RSS_REG_DBG_SHIFT                                                                            0x238c54UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
37503 #define RSS_REG_DBG_FORCE_VALID                                                                      0x238c58UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37504 #define RSS_REG_DBG_FORCE_FRAME                                                                      0x238c5cUL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37505 #define RSS_REG_DBG_OUT_DATA                                                                         0x238c60UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
37506 #define RSS_REG_DBG_OUT_DATA_SIZE                                                                    8
37507 #define RSS_REG_DBG_OUT_VALID                                                                        0x238c80UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
37508 #define RSS_REG_DBG_OUT_FRAME                                                                        0x238c84UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
37509 #define RSS_REG_MEMCTRL_WR_RD_N                                                                      0x238c88UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
37510 #define RSS_REG_MEMCTRL_CMD                                                                          0x238c8cUL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
37511 #define RSS_REG_MEMCTRL_ADDRESS                                                                      0x238c90UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
37512 #define RSS_REG_MEMCTRL_STATUS                                                                       0x238c94UL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0
37513 #define RPB_REG_INT_STS                                                                              0x23c040UL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37514     #define RPB_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
37515     #define RPB_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
37516     #define RPB_REG_INT_STS_EOP_ERROR                                                                (0x1<<1) // EOP check error.
37517     #define RPB_REG_INT_STS_EOP_ERROR_SHIFT                                                          1
37518     #define RPB_REG_INT_STS_IFIFO_ERROR                                                              (0x1<<2) // Instruction FIFO error.
37519     #define RPB_REG_INT_STS_IFIFO_ERROR_SHIFT                                                        2
37520     #define RPB_REG_INT_STS_PFIFO_ERROR                                                              (0x1<<3) // Parameter FIFO error.
37521     #define RPB_REG_INT_STS_PFIFO_ERROR_SHIFT                                                        3
37522     #define RPB_REG_INT_STS_DB_BUF_ERROR                                                             (0x1<<4) // DB FIFO error.
37523     #define RPB_REG_INT_STS_DB_BUF_ERROR_SHIFT                                                       4
37524     #define RPB_REG_INT_STS_TH_EXEC_ERROR                                                            (0x1<<5) //
37525     #define RPB_REG_INT_STS_TH_EXEC_ERROR_SHIFT                                                      5
37526     #define RPB_REG_INT_STS_TQ_ERROR_WR                                                              (0x1<<6) // TQ write overflow.
37527     #define RPB_REG_INT_STS_TQ_ERROR_WR_SHIFT                                                        6
37528     #define RPB_REG_INT_STS_TQ_ERROR_RD_TH                                                           (0x1<<7) // TQ read underflow by task handler.
37529     #define RPB_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT                                                     7
37530     #define RPB_REG_INT_STS_TQ_ERROR_RD_IH                                                           (0x1<<8) // TQ read underflow by instruction handler.
37531     #define RPB_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT                                                     8
37532 #define RPB_REG_INT_MASK                                                                             0x23c044UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37533     #define RPB_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
37534     #define RPB_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
37535     #define RPB_REG_INT_MASK_EOP_ERROR                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
37536     #define RPB_REG_INT_MASK_EOP_ERROR_SHIFT                                                         1
37537     #define RPB_REG_INT_MASK_IFIFO_ERROR                                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
37538     #define RPB_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                       2
37539     #define RPB_REG_INT_MASK_PFIFO_ERROR                                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
37540     #define RPB_REG_INT_MASK_PFIFO_ERROR_SHIFT                                                       3
37541     #define RPB_REG_INT_MASK_DB_BUF_ERROR                                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
37542     #define RPB_REG_INT_MASK_DB_BUF_ERROR_SHIFT                                                      4
37543     #define RPB_REG_INT_MASK_TH_EXEC_ERROR                                                           (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
37544     #define RPB_REG_INT_MASK_TH_EXEC_ERROR_SHIFT                                                     5
37545     #define RPB_REG_INT_MASK_TQ_ERROR_WR                                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
37546     #define RPB_REG_INT_MASK_TQ_ERROR_WR_SHIFT                                                       6
37547     #define RPB_REG_INT_MASK_TQ_ERROR_RD_TH                                                          (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
37548     #define RPB_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT                                                    7
37549     #define RPB_REG_INT_MASK_TQ_ERROR_RD_IH                                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
37550     #define RPB_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT                                                    8
37551 #define RPB_REG_INT_STS_WR                                                                           0x23c048UL //Access:WR   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37552     #define RPB_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
37553     #define RPB_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
37554     #define RPB_REG_INT_STS_WR_EOP_ERROR                                                             (0x1<<1) // EOP check error.
37555     #define RPB_REG_INT_STS_WR_EOP_ERROR_SHIFT                                                       1
37556     #define RPB_REG_INT_STS_WR_IFIFO_ERROR                                                           (0x1<<2) // Instruction FIFO error.
37557     #define RPB_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                     2
37558     #define RPB_REG_INT_STS_WR_PFIFO_ERROR                                                           (0x1<<3) // Parameter FIFO error.
37559     #define RPB_REG_INT_STS_WR_PFIFO_ERROR_SHIFT                                                     3
37560     #define RPB_REG_INT_STS_WR_DB_BUF_ERROR                                                          (0x1<<4) // DB FIFO error.
37561     #define RPB_REG_INT_STS_WR_DB_BUF_ERROR_SHIFT                                                    4
37562     #define RPB_REG_INT_STS_WR_TH_EXEC_ERROR                                                         (0x1<<5) //
37563     #define RPB_REG_INT_STS_WR_TH_EXEC_ERROR_SHIFT                                                   5
37564     #define RPB_REG_INT_STS_WR_TQ_ERROR_WR                                                           (0x1<<6) // TQ write overflow.
37565     #define RPB_REG_INT_STS_WR_TQ_ERROR_WR_SHIFT                                                     6
37566     #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_TH                                                        (0x1<<7) // TQ read underflow by task handler.
37567     #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT                                                  7
37568     #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_IH                                                        (0x1<<8) // TQ read underflow by instruction handler.
37569     #define RPB_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT                                                  8
37570 #define RPB_REG_INT_STS_CLR                                                                          0x23c04cUL //Access:RC   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37571     #define RPB_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
37572     #define RPB_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
37573     #define RPB_REG_INT_STS_CLR_EOP_ERROR                                                            (0x1<<1) // EOP check error.
37574     #define RPB_REG_INT_STS_CLR_EOP_ERROR_SHIFT                                                      1
37575     #define RPB_REG_INT_STS_CLR_IFIFO_ERROR                                                          (0x1<<2) // Instruction FIFO error.
37576     #define RPB_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                    2
37577     #define RPB_REG_INT_STS_CLR_PFIFO_ERROR                                                          (0x1<<3) // Parameter FIFO error.
37578     #define RPB_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT                                                    3
37579     #define RPB_REG_INT_STS_CLR_DB_BUF_ERROR                                                         (0x1<<4) // DB FIFO error.
37580     #define RPB_REG_INT_STS_CLR_DB_BUF_ERROR_SHIFT                                                   4
37581     #define RPB_REG_INT_STS_CLR_TH_EXEC_ERROR                                                        (0x1<<5) //
37582     #define RPB_REG_INT_STS_CLR_TH_EXEC_ERROR_SHIFT                                                  5
37583     #define RPB_REG_INT_STS_CLR_TQ_ERROR_WR                                                          (0x1<<6) // TQ write overflow.
37584     #define RPB_REG_INT_STS_CLR_TQ_ERROR_WR_SHIFT                                                    6
37585     #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_TH                                                       (0x1<<7) // TQ read underflow by task handler.
37586     #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT                                                 7
37587     #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_IH                                                       (0x1<<8) // TQ read underflow by instruction handler.
37588     #define RPB_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT                                                 8
37589 #define RPB_REG_PRTY_MASK                                                                            0x23c054UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
37590     #define RPB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                     (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
37591     #define RPB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                               0
37592 #define RPB_REG_CONTROL                                                                              0x23c400UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37593     #define RPB_REG_CONTROL_BYTE_ORDER_SWITCH                                                        (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
37594     #define RPB_REG_CONTROL_BYTE_ORDER_SWITCH_SHIFT                                                  0
37595     #define RPB_REG_CONTROL_DB_IGNORE_ERROR                                                          (0x1<<1) // Indicates if to ignore the input error indication.
37596     #define RPB_REG_CONTROL_DB_IGNORE_ERROR_SHIFT                                                    1
37597     #define RPB_REG_CONTROL_DONT_PASS_ERROR                                                          (0x1<<2) // Masks error on output of pb.
37598     #define RPB_REG_CONTROL_DONT_PASS_ERROR_SHIFT                                                    2
37599     #define RPB_REG_CONTROL_EOP_CHECK_DISABLE                                                        (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
37600     #define RPB_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT                                                  3
37601     #define RPB_REG_CONTROL_CRC_COMPARE_DISABLE                                                      (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
37602     #define RPB_REG_CONTROL_CRC_COMPARE_DISABLE_SHIFT                                                4
37603     #define RPB_REG_CONTROL_EN_INPUTS                                                                (0x1<<5) // Enable inputs.
37604     #define RPB_REG_CONTROL_EN_INPUTS_SHIFT                                                          5
37605     #define RPB_REG_CONTROL_DISABLE_PB                                                               (0x1<<6) // Debug only: Disable PB.
37606     #define RPB_REG_CONTROL_DISABLE_PB_SHIFT                                                         6
37607     #define RPB_REG_CONTROL_DEBUG_SELECT                                                             (0xf<<7) // Obsolete.
37608     #define RPB_REG_CONTROL_DEBUG_SELECT_SHIFT                                                       7
37609     #define RPB_REG_CONTROL_RELAX_TH                                                                 (0x1<<11) // Dbug only.
37610     #define RPB_REG_CONTROL_RELAX_TH_SHIFT                                                           11
37611     #define RPB_REG_CONTROL_DUMMY_ERR_ALLOW                                                          (0x1<<12) // Dummy ingress error allow.  When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
37612     #define RPB_REG_CONTROL_DUMMY_ERR_ALLOW_SHIFT                                                    12
37613 #define RPB_REG_CRC_MASK_1_0                                                                         0x23c404UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37614 #define RPB_REG_CRC_MASK_1_1                                                                         0x23c408UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37615 #define RPB_REG_CRC_MASK_1_2                                                                         0x23c40cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37616 #define RPB_REG_CRC_MASK_1_3                                                                         0x23c410UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37617 #define RPB_REG_CRC_MASK_2_0                                                                         0x23c414UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37618 #define RPB_REG_CRC_MASK_2_1                                                                         0x23c418UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37619 #define RPB_REG_CRC_MASK_2_2                                                                         0x23c41cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37620 #define RPB_REG_CRC_MASK_2_3                                                                         0x23c420UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37621 #define RPB_REG_CRC_MASK_3_0                                                                         0x23c424UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37622 #define RPB_REG_CRC_MASK_3_1                                                                         0x23c428UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37623 #define RPB_REG_CRC_MASK_3_2                                                                         0x23c42cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37624 #define RPB_REG_CRC_MASK_3_3                                                                         0x23c430UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
37625 #define RPB_REG_DB_EMPTY                                                                             0x23c500UL //Access:R    DataWidth:0x1   Data Buffer empty status.  Chips: BB_A0 BB_B0 K2
37626 #define RPB_REG_DB_FULL                                                                              0x23c504UL //Access:R    DataWidth:0x1   Data Buffer full status.  Chips: BB_A0 BB_B0 K2
37627 #define RPB_REG_TQ_EMPTY                                                                             0x23c508UL //Access:R    DataWidth:0x1   Task Queue empty status.  Chips: BB_A0 BB_B0 K2
37628 #define RPB_REG_TQ_FULL                                                                              0x23c50cUL //Access:R    DataWidth:0x1   Task Queue full status.  Chips: BB_A0 BB_B0 K2
37629 #define RPB_REG_IFIFO_EMPTY                                                                          0x23c510UL //Access:R    DataWidth:0x1   Instruction FIFO empty status.  Chips: BB_A0 BB_B0 K2
37630 #define RPB_REG_IFIFO_FULL                                                                           0x23c514UL //Access:R    DataWidth:0x1   Instruction FIFO full status.  Chips: BB_A0 BB_B0 K2
37631 #define RPB_REG_PFIFO_EMPTY                                                                          0x23c518UL //Access:R    DataWidth:0x1   Parameter FIFO empty status.  Chips: BB_A0 BB_B0 K2
37632 #define RPB_REG_PFIFO_FULL                                                                           0x23c51cUL //Access:R    DataWidth:0x1   Parameter FIFO full status.  Chips: BB_A0 BB_B0 K2
37633 #define RPB_REG_TQ_TH_EMPTY                                                                          0x23c520UL //Access:R    DataWidth:0x1   Task Queue empty status for task handler.  Chips: BB_A0 BB_B0 K2
37634 #define RPB_REG_ERRORED_CRC                                                                          0x23c600UL //Access:R    DataWidth:0x20  CRC mismatch debug register.  This register stores the calculated CRC value that resulted in the most recent CRC error event.  Chips: BB_A0 BB_B0 K2
37635 #define RPB_REG_ERRORED_INSTR                                                                        0x23c604UL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the instruction being executed at the time EOP error is detected. The instruction is aligned with the least significant bit of this register.  Bits 31:29 provide additional information about the instruction.  Bit 31 indicates whether the instruction is valid.  Bit 30 indicates if the instruction is the first instruction in the task.  Bit 29 indicates whether the instruction is the last instruction in the task.  Chips: BB_A0 BB_B0 K2
37636 #define RPB_REG_ERRORED_HDR_LOW                                                                      0x23c608UL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the lower 32 bits of the task header being executed at the time EOP error is detected.  The instruction length is not kept and is read as 0.  Chips: BB_A0 BB_B0 K2
37637 #define RPB_REG_ERRORED_HDR_HIGH                                                                     0x23c60cUL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the upper 32 bits of the task header being executed at the time EOP error is detected.  The task passthrough bit is not kept and is read as 0.  Chips: BB_A0 BB_B0 K2
37638 #define RPB_REG_ERRORED_LENGTH                                                                       0x23c610UL //Access:R    DataWidth:0x10  EOP mismatch debug register.  This register provides the number of data bytes remaining to be read from DB at the time of EOP error detection.  Chips: BB_A0 BB_B0 K2
37639 #define RPB_REG_ECO_RESERVED                                                                         0x23c614UL //Access:RW   DataWidth:0x8   For future eco.  Chips: BB_A0 BB_B0 K2
37640 #define RPB_REG_DBG_OUT_DATA                                                                         0x23c700UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
37641 #define RPB_REG_DBG_OUT_DATA_SIZE                                                                    8
37642 #define RPB_REG_DBG_OUT_VALID                                                                        0x23c720UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
37643 #define RPB_REG_DBG_OUT_FRAME                                                                        0x23c724UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
37644 #define RPB_REG_DBG_SELECT                                                                           0x23c728UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
37645 #define RPB_REG_DBG_DWORD_ENABLE                                                                     0x23c72cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
37646 #define RPB_REG_DBG_SHIFT                                                                            0x23c730UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
37647 #define RPB_REG_DBG_FORCE_VALID                                                                      0x23c734UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37648 #define RPB_REG_DBG_FORCE_FRAME                                                                      0x23c738UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37649 #define RPB_REG_DB_FIFO                                                                              0x23e000UL //Access:WB_R DataWidth:0x108 Provides read-only access of the data buffer FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
37650 #define RPB_REG_DB_FIFO_SIZE                                                                         512
37651 #define RPB_REG_L1                                                                                   0x23f000UL //Access:WB   DataWidth:0x40  L1 CRC memory access.  Chips: BB_A0 BB_B0 K2
37652 #define RPB_REG_L1_SIZE                                                                              640
37653 #define PSWRQ2_REG_RBC_DONE                                                                          0x240000UL //Access:RW   DataWidth:0x1   Driver should write 1 to this register in order to signal the PSWRQ block to start initializing internal memories.  Chips: BB_A0 BB_B0 K2
37654 #define PSWRQ2_REG_CFG_DONE                                                                          0x240004UL //Access:R    DataWidth:0x1   PSWRQ internal memories initialization is done. Driver should check this register is 1 some time after writing 1 to rbc_done register.  Chips: BB_A0 BB_B0 K2
37655 #define PSWRQ2_REG_RESET_STT                                                                         0x240008UL //Access:RW   DataWidth:0x1   MCP writes '1' to this bit to indicate PSWRQ to initialize Steering Tag Table with zeros. PSWRQ clears this bit when the initialization is done. MCP can use this register the same as it uses IGU reset_memories register.  Chips: BB_A0 BB_B0 K2
37656 #define PSWRQ2_REG_CDUT_P_SIZE                                                                       0x24000cUL //Access:RW   DataWidth:0x4   Page size in L2P table for CDU-Task module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37657 #define PSWRQ2_REG_CDUC_P_SIZE                                                                       0x240010UL //Access:RW   DataWidth:0x4   Page size in L2P table for CDU module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37658 #define PSWRQ2_REG_TM_P_SIZE                                                                         0x240014UL //Access:RW   DataWidth:0x4   Page size in L2P table for TM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37659 #define PSWRQ2_REG_QM_P_SIZE                                                                         0x240018UL //Access:RW   DataWidth:0x4   Page size in L2P table for QM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37660 #define PSWRQ2_REG_SRC_P_SIZE                                                                        0x24001cUL //Access:RW   DataWidth:0x4   Page size in L2P table for SRC module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37661 #define PSWRQ2_REG_DBG_P_SIZE                                                                        0x240020UL //Access:RW   DataWidth:0x4   Page size in L2P table for DBG module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37662 #define PSWRQ2_REG_XSDM_P_SIZE                                                                       0x240024UL //Access:RW   DataWidth:0x4   Page size in L2P table for XSDM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37663 #define PSWRQ2_REG_TSDM_P_SIZE                                                                       0x240028UL //Access:RW   DataWidth:0x4   Page size in L2P table for TSDM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37664 #define PSWRQ2_REG_USDM_P_SIZE                                                                       0x24002cUL //Access:RW   DataWidth:0x4   Page size in L2P table for USDM module;0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
37665 #define PSWRQ2_REG_TM_FIRST_ILT                                                                      0x240030UL //Access:RW   DataWidth:0xe   First memory address base for tm in ILT.  Chips: BB_A0 BB_B0 K2
37666 #define PSWRQ2_REG_TM_LAST_ILT                                                                       0x240034UL //Access:RW   DataWidth:0xe   Last memory address base for tm in ILT.  Chips: BB_A0 BB_B0 K2
37667 #define PSWRQ2_REG_QM_FIRST_ILT                                                                      0x240038UL //Access:RW   DataWidth:0xe   First memory address base for qm in ILT.  Chips: BB_A0 BB_B0 K2
37668 #define PSWRQ2_REG_QM_LAST_ILT                                                                       0x24003cUL //Access:RW   DataWidth:0xe   Last memory address base for qm in ILT.  Chips: BB_A0 BB_B0 K2
37669 #define PSWRQ2_REG_SRC_FIRST_ILT                                                                     0x240040UL //Access:RW   DataWidth:0xe   First memory address base for src in ILT.  Chips: BB_A0 BB_B0 K2
37670 #define PSWRQ2_REG_SRC_LAST_ILT                                                                      0x240044UL //Access:RW   DataWidth:0xe   Last memory address base for src in ILT.  Chips: BB_A0 BB_B0 K2
37671 #define PSWRQ2_REG_CDUC_FIRST_ILT                                                                    0x240048UL //Access:RW   DataWidth:0xe   First memory address base for cdu-connection in ILT.  Chips: BB_A0 BB_B0 K2
37672 #define PSWRQ2_REG_CDUC_LAST_ILT                                                                     0x24004cUL //Access:RW   DataWidth:0xe   Last memory address base for cdu-connection in ILT.  Chips: BB_A0 BB_B0 K2
37673 #define PSWRQ2_REG_CDUT_FIRST_ILT                                                                    0x240050UL //Access:RW   DataWidth:0xe   First memory address base for cdu-task in ILT.  Chips: BB_A0 BB_B0 K2
37674 #define PSWRQ2_REG_CDUT_LAST_ILT                                                                     0x240054UL //Access:RW   DataWidth:0xe   Last memory address base for cdu-task in ILT.  Chips: BB_A0 BB_B0 K2
37675 #define PSWRQ2_REG_XSDM_FIRST_ILT                                                                    0x240058UL //Access:RW   DataWidth:0xe   First memory address base for xsdm in ILT.  Chips: BB_A0 BB_B0 K2
37676 #define PSWRQ2_REG_XSDM_LAST_ILT                                                                     0x24005cUL //Access:RW   DataWidth:0xe   Last memory address base for xsdm in ILT.  Chips: BB_A0 BB_B0 K2
37677 #define PSWRQ2_REG_TSDM_FIRST_ILT                                                                    0x240060UL //Access:RW   DataWidth:0xe   First memory address base for tsdm in ILT.  Chips: BB_A0 BB_B0 K2
37678 #define PSWRQ2_REG_TSDM_LAST_ILT                                                                     0x240064UL //Access:RW   DataWidth:0xe   Last memory address base for tsdm in ILT.  Chips: BB_A0 BB_B0 K2
37679 #define PSWRQ2_REG_USDM_FIRST_ILT                                                                    0x240068UL //Access:RW   DataWidth:0xe   First memory address base for usdm in ILT.  Chips: BB_A0 BB_B0 K2
37680 #define PSWRQ2_REG_USDM_LAST_ILT                                                                     0x24006cUL //Access:RW   DataWidth:0xe   Last memory address base for usdm in ILT.  Chips: BB_A0 BB_B0 K2
37681 #define PSWRQ2_REG_DBG_FIRST_ILT                                                                     0x240070UL //Access:RW   DataWidth:0xe   First memory address base for dbg in ILT.  Chips: BB_A0 BB_B0 K2
37682 #define PSWRQ2_REG_DBG_LAST_ILT                                                                      0x240074UL //Access:RW   DataWidth:0xe   Last memory address base for dbg in ILT.  Chips: BB_A0 BB_B0 K2
37683 #define PSWRQ2_REG_ENDIANITY_00                                                                      0x240078UL //Access:RW   DataWidth:0x2   Requests from all SDM's and DMAE with endian mode 0 will receive the endian mode indicated here.  Chips: BB_A0 BB_B0 K2
37684 #define PSWRQ2_REG_ENDIANITY_01                                                                      0x24007cUL //Access:RW   DataWidth:0x2   Requests from all SDM's and DMAE with endian mode 1 will receive the endian mode indicated here.  Chips: BB_A0 BB_B0 K2
37685 #define PSWRQ2_REG_ENDIANITY_02                                                                      0x240080UL //Access:RW   DataWidth:0x2   Requests from all SDM's and DMAE with endian mode 2 will receive the endian mode indicated here.  Chips: BB_A0 BB_B0 K2
37686 #define PSWRQ2_REG_ENDIANITY_03                                                                      0x240084UL //Access:RW   DataWidth:0x2   Requests from all SDM's and DMAE with endian mode 3 will receive the endian mode indicated here.  Chips: BB_A0 BB_B0 K2
37687 #define PSWRQ2_REG_PTU_ENDIAN_M                                                                      0x240088UL //Access:RW   DataWidth:0x2   Endian mode for ptu.  Chips: BB_A0 BB_B0 K2
37688 #define PSWRQ2_REG_M2P_ENDIAN_M                                                                      0x24008cUL //Access:RW   DataWidth:0x2   Endian mode for m2p.  Chips: BB_A0 BB_B0 K2
37689 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS                                                            0x240090UL //Access:RW   DataWidth:0x10  Number of ILT PF blocks.  Chips: BB_A0 BB_B0 K2
37690 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS                                                          0x240094UL //Access:RW   DataWidth:0x10  Number of ILT PF blocks.  Chips: BB_A0 BB_B0 K2
37691 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS                                                          0x240098UL //Access:RW   DataWidth:0x10  Number of ILT PF blocks.  Chips: BB_A0 BB_B0 K2
37692 #define PSWRQ2_REG_TM_VF_BLOCKS                                                                      0x24009cUL //Access:RW   DataWidth:0x8   Number of ILT VF blocks.  Chips: BB_A0 BB_B0 K2
37693 #define PSWRQ2_REG_CDUT_VF_BLOCKS                                                                    0x2400a0UL //Access:RW   DataWidth:0x8   Number of ILT VF blocks.  Chips: BB_A0 BB_B0 K2
37694 #define PSWRQ2_REG_CDUC_VF_BLOCKS                                                                    0x2400a4UL //Access:RW   DataWidth:0x8   Number of ILT VF blocks.  Chips: BB_A0 BB_B0 K2
37695 #define PSWRQ2_REG_TM_BLOCKS_FACTOR                                                                  0x2400a8UL //Access:RW   DataWidth:0x4   ILT blocks factor.  Chips: BB_A0 BB_B0 K2
37696 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR                                                                0x2400acUL //Access:RW   DataWidth:0x4   ILT blocks factor.  Chips: BB_A0 BB_B0 K2
37697 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR                                                                0x2400b0UL //Access:RW   DataWidth:0x4   ILT blocks factor.  Chips: BB_A0 BB_B0 K2
37698 #define PSWRQ2_REG_VF_BASE                                                                           0x2400b4UL //Access:RW   DataWidth:0x8   First VF assigned to this PF. Used for ILT for VFs calculations.  Chips: BB_A0 BB_B0 K2
37699 #define PSWRQ2_REG_VF_LAST_ILT                                                                       0x2400b8UL //Access:RW   DataWidth:0x8   VF LAST  Chips: BB_B0 K2
37700 #define PSWRQ2_REG_DBG_OUT_DATA                                                                      0x2400e0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
37701 #define PSWRQ2_REG_DBG_OUT_DATA_SIZE                                                                 8
37702 #define PSWRQ2_REG_DBG_SELECT                                                                        0x240100UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
37703 #define PSWRQ2_REG_DBG_DWORD_ENABLE                                                                  0x240104UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
37704 #define PSWRQ2_REG_DBG_SHIFT                                                                         0x240108UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
37705 #define PSWRQ2_REG_DBG_FORCE_VALID                                                                   0x24010cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37706 #define PSWRQ2_REG_DBG_FORCE_FRAME                                                                   0x240110UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
37707 #define PSWRQ2_REG_DBG_OUT_VALID                                                                     0x240114UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
37708 #define PSWRQ2_REG_DBG_OUT_FRAME                                                                     0x240118UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
37709 #define PSWRQ2_REG_INT_STS                                                                           0x240180UL //Access:R    DataWidth:0xf   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37710     #define PSWRQ2_REG_INT_STS_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
37711     #define PSWRQ2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                   0
37712     #define PSWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW                                                     (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
37713     #define PSWRQ2_REG_INT_STS_L2P_FIFO_OVERFLOW_SHIFT                                               1
37714     #define PSWRQ2_REG_INT_STS_WDFIFO_OVERFLOW                                                       (0x1<<2) // Overflow in src write done fifo.
37715     #define PSWRQ2_REG_INT_STS_WDFIFO_OVERFLOW_SHIFT                                                 2
37716     #define PSWRQ2_REG_INT_STS_PHYADDR_FIFO_OF                                                       (0x1<<3) // Overflow of phy addr fifo - removed in E4.
37717     #define PSWRQ2_REG_INT_STS_PHYADDR_FIFO_OF_SHIFT                                                 3
37718     #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_1                                                       (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
37719     #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_1_SHIFT                                                 4
37720     #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_2                                                       (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
37721     #define PSWRQ2_REG_INT_STS_L2P_VIOLATION_2_SHIFT                                                 5
37722     #define PSWRQ2_REG_INT_STS_FREE_LIST_EMPTY                                                       (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
37723     #define PSWRQ2_REG_INT_STS_FREE_LIST_EMPTY_SHIFT                                                 6
37724     #define PSWRQ2_REG_INT_STS_ELT_ADDR                                                              (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
37725     #define PSWRQ2_REG_INT_STS_ELT_ADDR_SHIFT                                                        7
37726     #define PSWRQ2_REG_INT_STS_L2P_VF_ERR                                                            (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
37727     #define PSWRQ2_REG_INT_STS_L2P_VF_ERR_SHIFT                                                      8
37728     #define PSWRQ2_REG_INT_STS_CORE_WDONE_OVERFLOW                                                   (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
37729     #define PSWRQ2_REG_INT_STS_CORE_WDONE_OVERFLOW_SHIFT                                             9
37730     #define PSWRQ2_REG_INT_STS_TREQ_FIFO_UNDERFLOW                                                   (0x1<<10) // Underflwoing the treq fifo.
37731     #define PSWRQ2_REG_INT_STS_TREQ_FIFO_UNDERFLOW_SHIFT                                             10
37732     #define PSWRQ2_REG_INT_STS_TREQ_FIFO_OVERFLOW                                                    (0x1<<11) // Overflwoing the treq fifo.
37733     #define PSWRQ2_REG_INT_STS_TREQ_FIFO_OVERFLOW_SHIFT                                              11
37734     #define PSWRQ2_REG_INT_STS_ICPL_FIFO_UNDERFLOW                                                   (0x1<<12) // Underflwoing the icpl fifo.
37735     #define PSWRQ2_REG_INT_STS_ICPL_FIFO_UNDERFLOW_SHIFT                                             12
37736     #define PSWRQ2_REG_INT_STS_ICPL_FIFO_OVERFLOW                                                    (0x1<<13) // Overflwoing the icpl fifo.
37737     #define PSWRQ2_REG_INT_STS_ICPL_FIFO_OVERFLOW_SHIFT                                              13
37738     #define PSWRQ2_REG_INT_STS_BACK2BACK_ATC_RESPONSE                                                (0x1<<14) // 2 consecutive atc responses are not allowed.
37739     #define PSWRQ2_REG_INT_STS_BACK2BACK_ATC_RESPONSE_SHIFT                                          14
37740 #define PSWRQ2_REG_INT_MASK                                                                          0x240184UL //Access:RW   DataWidth:0xf   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37741     #define PSWRQ2_REG_INT_MASK_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ADDRESS_ERROR .
37742     #define PSWRQ2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                  0
37743     #define PSWRQ2_REG_INT_MASK_L2P_FIFO_OVERFLOW                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_FIFO_OVERFLOW .
37744     #define PSWRQ2_REG_INT_MASK_L2P_FIFO_OVERFLOW_SHIFT                                              1
37745     #define PSWRQ2_REG_INT_MASK_WDFIFO_OVERFLOW                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.WDFIFO_OVERFLOW .
37746     #define PSWRQ2_REG_INT_MASK_WDFIFO_OVERFLOW_SHIFT                                                2
37747     #define PSWRQ2_REG_INT_MASK_PHYADDR_FIFO_OF                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.PHYADDR_FIFO_OF .
37748     #define PSWRQ2_REG_INT_MASK_PHYADDR_FIFO_OF_SHIFT                                                3
37749     #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_1                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VIOLATION_1 .
37750     #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_1_SHIFT                                                4
37751     #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_2                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VIOLATION_2 .
37752     #define PSWRQ2_REG_INT_MASK_L2P_VIOLATION_2_SHIFT                                                5
37753     #define PSWRQ2_REG_INT_MASK_FREE_LIST_EMPTY                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.FREE_LIST_EMPTY .
37754     #define PSWRQ2_REG_INT_MASK_FREE_LIST_EMPTY_SHIFT                                                6
37755     #define PSWRQ2_REG_INT_MASK_ELT_ADDR                                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ELT_ADDR .
37756     #define PSWRQ2_REG_INT_MASK_ELT_ADDR_SHIFT                                                       7
37757     #define PSWRQ2_REG_INT_MASK_L2P_VF_ERR                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.L2P_VF_ERR .
37758     #define PSWRQ2_REG_INT_MASK_L2P_VF_ERR_SHIFT                                                     8
37759     #define PSWRQ2_REG_INT_MASK_CORE_WDONE_OVERFLOW                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.CORE_WDONE_OVERFLOW .
37760     #define PSWRQ2_REG_INT_MASK_CORE_WDONE_OVERFLOW_SHIFT                                            9
37761     #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_UNDERFLOW                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.TREQ_FIFO_UNDERFLOW .
37762     #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_UNDERFLOW_SHIFT                                            10
37763     #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_OVERFLOW                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.TREQ_FIFO_OVERFLOW .
37764     #define PSWRQ2_REG_INT_MASK_TREQ_FIFO_OVERFLOW_SHIFT                                             11
37765     #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_UNDERFLOW                                                  (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ICPL_FIFO_UNDERFLOW .
37766     #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_UNDERFLOW_SHIFT                                            12
37767     #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_OVERFLOW                                                   (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.ICPL_FIFO_OVERFLOW .
37768     #define PSWRQ2_REG_INT_MASK_ICPL_FIFO_OVERFLOW_SHIFT                                             13
37769     #define PSWRQ2_REG_INT_MASK_BACK2BACK_ATC_RESPONSE                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWRQ2_REG_INT_STS.BACK2BACK_ATC_RESPONSE .
37770     #define PSWRQ2_REG_INT_MASK_BACK2BACK_ATC_RESPONSE_SHIFT                                         14
37771 #define PSWRQ2_REG_INT_STS_WR                                                                        0x240188UL //Access:WR   DataWidth:0xf   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37772     #define PSWRQ2_REG_INT_STS_WR_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
37773     #define PSWRQ2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                0
37774     #define PSWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW                                                  (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
37775     #define PSWRQ2_REG_INT_STS_WR_L2P_FIFO_OVERFLOW_SHIFT                                            1
37776     #define PSWRQ2_REG_INT_STS_WR_WDFIFO_OVERFLOW                                                    (0x1<<2) // Overflow in src write done fifo.
37777     #define PSWRQ2_REG_INT_STS_WR_WDFIFO_OVERFLOW_SHIFT                                              2
37778     #define PSWRQ2_REG_INT_STS_WR_PHYADDR_FIFO_OF                                                    (0x1<<3) // Overflow of phy addr fifo - removed in E4.
37779     #define PSWRQ2_REG_INT_STS_WR_PHYADDR_FIFO_OF_SHIFT                                              3
37780     #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_1                                                    (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
37781     #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_1_SHIFT                                              4
37782     #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_2                                                    (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
37783     #define PSWRQ2_REG_INT_STS_WR_L2P_VIOLATION_2_SHIFT                                              5
37784     #define PSWRQ2_REG_INT_STS_WR_FREE_LIST_EMPTY                                                    (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
37785     #define PSWRQ2_REG_INT_STS_WR_FREE_LIST_EMPTY_SHIFT                                              6
37786     #define PSWRQ2_REG_INT_STS_WR_ELT_ADDR                                                           (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
37787     #define PSWRQ2_REG_INT_STS_WR_ELT_ADDR_SHIFT                                                     7
37788     #define PSWRQ2_REG_INT_STS_WR_L2P_VF_ERR                                                         (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
37789     #define PSWRQ2_REG_INT_STS_WR_L2P_VF_ERR_SHIFT                                                   8
37790     #define PSWRQ2_REG_INT_STS_WR_CORE_WDONE_OVERFLOW                                                (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
37791     #define PSWRQ2_REG_INT_STS_WR_CORE_WDONE_OVERFLOW_SHIFT                                          9
37792     #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_UNDERFLOW                                                (0x1<<10) // Underflwoing the treq fifo.
37793     #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_UNDERFLOW_SHIFT                                          10
37794     #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_OVERFLOW                                                 (0x1<<11) // Overflwoing the treq fifo.
37795     #define PSWRQ2_REG_INT_STS_WR_TREQ_FIFO_OVERFLOW_SHIFT                                           11
37796     #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_UNDERFLOW                                                (0x1<<12) // Underflwoing the icpl fifo.
37797     #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_UNDERFLOW_SHIFT                                          12
37798     #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_OVERFLOW                                                 (0x1<<13) // Overflwoing the icpl fifo.
37799     #define PSWRQ2_REG_INT_STS_WR_ICPL_FIFO_OVERFLOW_SHIFT                                           13
37800     #define PSWRQ2_REG_INT_STS_WR_BACK2BACK_ATC_RESPONSE                                             (0x1<<14) // 2 consecutive atc responses are not allowed.
37801     #define PSWRQ2_REG_INT_STS_WR_BACK2BACK_ATC_RESPONSE_SHIFT                                       14
37802 #define PSWRQ2_REG_INT_STS_CLR                                                                       0x24018cUL //Access:RC   DataWidth:0xf   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37803     #define PSWRQ2_REG_INT_STS_CLR_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
37804     #define PSWRQ2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                               0
37805     #define PSWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW                                                 (0x1<<1) // Overflow in l2p input fifo - hard wired to 0 in E4.
37806     #define PSWRQ2_REG_INT_STS_CLR_L2P_FIFO_OVERFLOW_SHIFT                                           1
37807     #define PSWRQ2_REG_INT_STS_CLR_WDFIFO_OVERFLOW                                                   (0x1<<2) // Overflow in src write done fifo.
37808     #define PSWRQ2_REG_INT_STS_CLR_WDFIFO_OVERFLOW_SHIFT                                             2
37809     #define PSWRQ2_REG_INT_STS_CLR_PHYADDR_FIFO_OF                                                   (0x1<<3) // Overflow of phy addr fifo - removed in E4.
37810     #define PSWRQ2_REG_INT_STS_CLR_PHYADDR_FIFO_OF_SHIFT                                             3
37811     #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_1                                                   (0x1<<4) // Translation page pointer is bigger than 15 - hard wired to 0 in E4.
37812     #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_1_SHIFT                                             4
37813     #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_2                                                   (0x1<<5) // Vah+elt_first_index is bigger than page size - hard wired to 0 in E4.
37814     #define PSWRQ2_REG_INT_STS_CLR_L2P_VIOLATION_2_SHIFT                                             5
37815     #define PSWRQ2_REG_INT_STS_CLR_FREE_LIST_EMPTY                                                   (0x1<<6) // If this interrupt occurs then an entry in the cxr_ram was overwritten and a linked list is corrupted; it is a fatal bug; can be fixed only by reset.
37816     #define PSWRQ2_REG_INT_STS_CLR_FREE_LIST_EMPTY_SHIFT                                             6
37817     #define PSWRQ2_REG_INT_STS_CLR_ELT_ADDR                                                          (0x1<<7) // Indicates that onchip translation did not succeed in ILT mode (in ILT mode all onchip translation MUST succeed).
37818     #define PSWRQ2_REG_INT_STS_CLR_ELT_ADDR_SHIFT                                                    7
37819     #define PSWRQ2_REG_INT_STS_CLR_L2P_VF_ERR                                                        (0x1<<8) // E4: Indicates a request with: 1. Logical address. 2. Function is a VF. 3. Client is NOT (TM;CDU).
37820     #define PSWRQ2_REG_INT_STS_CLR_L2P_VF_ERR_SHIFT                                                  8
37821     #define PSWRQ2_REG_INT_STS_CLR_CORE_WDONE_OVERFLOW                                               (0x1<<9) // Overflow in the wdone fifo for wdone responses coming from the glue.
37822     #define PSWRQ2_REG_INT_STS_CLR_CORE_WDONE_OVERFLOW_SHIFT                                         9
37823     #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_UNDERFLOW                                               (0x1<<10) // Underflwoing the treq fifo.
37824     #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_UNDERFLOW_SHIFT                                         10
37825     #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_OVERFLOW                                                (0x1<<11) // Overflwoing the treq fifo.
37826     #define PSWRQ2_REG_INT_STS_CLR_TREQ_FIFO_OVERFLOW_SHIFT                                          11
37827     #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_UNDERFLOW                                               (0x1<<12) // Underflwoing the icpl fifo.
37828     #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_UNDERFLOW_SHIFT                                         12
37829     #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_OVERFLOW                                                (0x1<<13) // Overflwoing the icpl fifo.
37830     #define PSWRQ2_REG_INT_STS_CLR_ICPL_FIFO_OVERFLOW_SHIFT                                          13
37831     #define PSWRQ2_REG_INT_STS_CLR_BACK2BACK_ATC_RESPONSE                                            (0x1<<14) // 2 consecutive atc responses are not allowed.
37832     #define PSWRQ2_REG_INT_STS_CLR_BACK2BACK_ATC_RESPONSE_SHIFT                                      14
37833 #define PSWRQ2_REG_PRTY_MASK_H_0                                                                     0x240204UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37834     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
37835     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                       0
37836     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
37837     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT                                       1
37838     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_A0                                       (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
37839     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_A0_SHIFT                                 1
37840     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_B0                                       (0x1<<1) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
37841     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_BB_B0_SHIFT                                 1
37842     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_K2                                          (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
37843     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_K2_SHIFT                                    2
37844     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                         (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
37845     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                   8
37846     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                         (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
37847     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                   8
37848     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                            (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
37849     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                      3
37850     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                               (0x1<<4) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
37851     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                         4
37852     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0                                         (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
37853     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0_SHIFT                                   7
37854     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0                                         (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
37855     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0_SHIFT                                   7
37856     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                            (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
37857     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                      5
37858     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0                                         (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37859     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0_SHIFT                                   5
37860     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0                                         (0x1<<5) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37861     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0_SHIFT                                   5
37862     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                            (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
37863     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                      6
37864     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0                                         (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
37865     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                   6
37866     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0                                         (0x1<<6) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
37867     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                   6
37868     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                            (0x1<<7) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
37869     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                      7
37870     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                               (0x1<<8) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
37871     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                         8
37872     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0                                         (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
37873     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0_SHIFT                                   3
37874     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0                                         (0x1<<3) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
37875     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0_SHIFT                                   3
37876     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                            (0x1<<9) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
37877     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                      9
37878     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                               (0x1<<2) // This bit masks, when set, the Parity bit: PSWRQ2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
37879     #define PSWRQ2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                         2
37880 #define PSWRQ2_REG_MEM_ECC_EVENTS_BB_A0                                                              0x240220UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0
37881 #define PSWRQ2_REG_MEM_ECC_EVENTS_BB_B0                                                              0x240220UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_B0
37882 #define PSWRQ2_REG_MEM_ECC_EVENTS_K2                                                                 0x240224UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
37883 #define PSWRQ2_REG_MEM004_I_MEM_DFT_K2                                                               0x24022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrq.i_l2p_table.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37884 #define PSWRQ2_REG_MEM005_I_MEM_DFT_K2                                                               0x240230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrq.i_l2p_table_high.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37885 #define PSWRQ2_REG_MEM008_I_MEM_DFT_K2                                                               0x240234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrq.i_stt_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
37886 #define PSWRQ2_REG_MEM009_I_MEM_DFT_K2                                                               0x240238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrq.i_treq_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37887 #define PSWRQ2_REG_MEM002_I_MEM_DFT_K2                                                               0x24023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrq.i_hoq_ram0.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37888 #define PSWRQ2_REG_MEM001_I_MEM_DFT_K2                                                               0x240240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrq.i_cxr_ram1.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37889 #define PSWRQ2_REG_MEM010_I_MEM_DFT_K2                                                               0x240244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrq.i_wdone_dc_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
37890 #define PSWRQ2_REG_MEM007_I_MEM_DFT_K2                                                               0x240248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrq.i_pswrq_mem_hoq1_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
37891 #define PSWRQ2_REG_WR_MBS0                                                                           0x240400UL //Access:RW   DataWidth:0x3   Max burst size filed for write requests port 0; 000 - 128B; 001:256B; 010: 512B;.  Chips: BB_A0 BB_B0 K2
37892 #define PSWRQ2_REG_RD_MBS0                                                                           0x240404UL //Access:RW   DataWidth:0x3   Max burst size filed for read requests port 0; 000 - 128B; 001:256B; 010: 512B;011:1K:100:2K;101:4K.  Chips: BB_A0 BB_B0 K2
37893 #define PSWRQ2_REG_CDU_ENDIAN_M                                                                      0x240408UL //Access:RW   DataWidth:0x2   Endian mode for cdu.  Chips: BB_A0 BB_B0 K2
37894 #define PSWRQ2_REG_DISABLE_INPUTS                                                                    0x24040cUL //Access:RW   DataWidth:0x1   When '1'; requests will enter input buffers but wont get out towards the glue.  Chips: BB_A0 BB_B0 K2
37895 #define PSWRQ2_REG_DRAM_ALIGN_WR                                                                     0x240410UL //Access:RW   DataWidth:0x4   Determines alignment of write SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B aligned. 4 - 512B aligned.  Chips: BB_A0 BB_B0 K2
37896 #define PSWRQ2_REG_DRAM_ALIGN_RD                                                                     0x240414UL //Access:RW   DataWidth:0x4   Determines alignment of read SRs when a request is split into several SRs. 0 - 8B aligned. 1 - 64B aligned. 2 - 128B aligned. 3 - 256B aligned. 4 - 512B aligned.  Chips: BB_A0 BB_B0 K2
37897 #define PSWRQ2_REG_USDM_ENTRY_TH                                                                     0x240418UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to usdm in the queues.  Chips: BB_A0 BB_B0 K2
37898 #define PSWRQ2_REG_PRM_ENTRY_TH                                                                      0x24041cUL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to prm in the queues.  Chips: BB_A0 BB_B0 K2
37899 #define PSWRQ2_REG_TSDM_ENTRY_TH                                                                     0x240420UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to tsdm in the queues.  Chips: BB_A0 BB_B0 K2
37900 #define PSWRQ2_REG_XSDM_ENTRY_TH                                                                     0x240424UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to xsdm in the queues.  Chips: BB_A0 BB_B0 K2
37901 #define PSWRQ2_REG_DMAE_ENTRY_TH                                                                     0x240428UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to rwh in the queues.  Chips: BB_A0 BB_B0 K2
37902 #define PSWRQ2_REG_CDUWR_ENTRY_TH                                                                    0x24042cUL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to cduwr in the queues.  Chips: BB_A0 BB_B0 K2
37903 #define PSWRQ2_REG_CDURD_ENTRY_TH                                                                    0x240430UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to cdurd in the queues.  Chips: BB_A0 BB_B0 K2
37904 #define PSWRQ2_REG_PBF_ENTRY_TH                                                                      0x240434UL //Access:RW   DataWidth:0x7   This number indicates how many entries are guaranteed to pbf in the queues.  Chips: BB_A0 BB_B0 K2
37905 #define PSWRQ2_REG_QM_ENTRY_TH                                                                       0x240438UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to qm in the queues.  Chips: BB_A0 BB_B0 K2
37906 #define PSWRQ2_REG_TM_ENTRY_TH                                                                       0x24043cUL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to tm in the queues.  Chips: BB_A0 BB_B0 K2
37907 #define PSWRQ2_REG_SRC_ENTRY_TH                                                                      0x240440UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to src in the queues.  Chips: BB_A0 BB_B0 K2
37908 #define PSWRQ2_REG_DBG_ENTRY_TH                                                                      0x240444UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to debug in the queues.  Chips: BB_A0 BB_B0 K2
37909 #define PSWRQ2_REG_HC_ENTRY_TH                                                                       0x240448UL //Access:RW   DataWidth:0x2   This number indicates how many entries are guaranteed to hc in the queues.  Chips: BB_A0 BB_B0 K2
37910 #define PSWRQ2_REG_GC_INIT_VAL                                                                       0x24044cUL //Access:RW   DataWidth:0x8   Initial value of global counter; This value MUST be 256 - sum of all clients thresholds.  Chips: BB_A0 BB_B0 K2
37911 #define PSWRQ2_REG_UFIFO                                                                             0x240450UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37912     #define PSWRQ2_REG_UFIFO_UFIFO_LOW_TH                                                            (0xf<<0) // Low threshold of update fifo; not used.
37913     #define PSWRQ2_REG_UFIFO_UFIFO_LOW_TH_SHIFT                                                      0
37914     #define PSWRQ2_REG_UFIFO_UFIFO_HIGH_TH                                                           (0xf<<4) // High threshold of update fifo; not used.
37915     #define PSWRQ2_REG_UFIFO_UFIFO_HIGH_TH_SHIFT                                                     4
37916 #define PSWRQ2_REG_VQ0_ENTRY_CNT                                                                     0x240454UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 0 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37917 #define PSWRQ2_REG_VQ1_ENTRY_CNT                                                                     0x240458UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 1 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37918 #define PSWRQ2_REG_VQ2_ENTRY_CNT                                                                     0x24045cUL //Access:R    DataWidth:0x8   Number of entries occupied by vq 2 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37919 #define PSWRQ2_REG_VQ3_ENTRY_CNT                                                                     0x240460UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 3 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37920 #define PSWRQ2_REG_VQ4_ENTRY_CNT                                                                     0x240464UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 4  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37921 #define PSWRQ2_REG_VQ5_ENTRY_CNT                                                                     0x240468UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 5  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37922 #define PSWRQ2_REG_VQ6_ENTRY_CNT                                                                     0x24046cUL //Access:R    DataWidth:0x8   Number of entries occupied by vq 6 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37923 #define PSWRQ2_REG_VQ7_ENTRY_CNT                                                                     0x240470UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 7 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37924 #define PSWRQ2_REG_VQ8_ENTRY_CNT                                                                     0x240474UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 8  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37925 #define PSWRQ2_REG_VQ9_ENTRY_CNT                                                                     0x240478UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 9 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37926 #define PSWRQ2_REG_VQ10_ENTRY_CNT                                                                    0x24047cUL //Access:R    DataWidth:0x8   Number of entries occupied by vq 10 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37927 #define PSWRQ2_REG_VQ11_ENTRY_CNT                                                                    0x240480UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 11 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37928 #define PSWRQ2_REG_VQ12_ENTRY_CNT                                                                    0x240484UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 12 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37929 #define PSWRQ2_REG_VQ13_ENTRY_CNT                                                                    0x240488UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 13 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37930 #define PSWRQ2_REG_VQ14_ENTRY_CNT                                                                    0x24048cUL //Access:R    DataWidth:0x8   Number of entries occupied by vq 14  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37931 #define PSWRQ2_REG_VQ15_ENTRY_CNT                                                                    0x240490UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 15  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37932 #define PSWRQ2_REG_VQ16_ENTRY_CNT                                                                    0x240494UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 16 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37933 #define PSWRQ2_REG_VQ17_ENTRY_CNT                                                                    0x240498UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 17 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37934 #define PSWRQ2_REG_VQ18_ENTRY_CNT                                                                    0x24049cUL //Access:R    DataWidth:0x8   Number of entries occupied by vq 18  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37935 #define PSWRQ2_REG_VQ19_ENTRY_CNT                                                                    0x2404a0UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 19 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37936 #define PSWRQ2_REG_VQ20_ENTRY_CNT                                                                    0x2404a4UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 20  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37937 #define PSWRQ2_REG_VQ21_ENTRY_CNT                                                                    0x2404a8UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 21 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37938 #define PSWRQ2_REG_VQ22_ENTRY_CNT                                                                    0x2404acUL //Access:R    DataWidth:0x8   Number of entries occupied by vq 22 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37939 #define PSWRQ2_REG_VQ23_ENTRY_CNT                                                                    0x2404b0UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 23 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37940 #define PSWRQ2_REG_VQ24_ENTRY_CNT                                                                    0x2404b4UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 24  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37941 #define PSWRQ2_REG_VQ25_ENTRY_CNT                                                                    0x2404b8UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 25  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37942 #define PSWRQ2_REG_VQ26_ENTRY_CNT                                                                    0x2404bcUL //Access:R    DataWidth:0x8   Number of entries occupied by vq 26 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37943 #define PSWRQ2_REG_VQ27_ENTRY_CNT                                                                    0x2404c0UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 27 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37944 #define PSWRQ2_REG_VQ28_ENTRY_CNT                                                                    0x2404c4UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 28  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37945 #define PSWRQ2_REG_VQ29_ENTRY_CNT                                                                    0x2404c8UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 29 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37946 #define PSWRQ2_REG_VQ30_ENTRY_CNT                                                                    0x2404ccUL //Access:R    DataWidth:0x8   Number of entries occupied by vq 30  in pswrq memory.  Chips: BB_A0 BB_B0 K2
37947 #define PSWRQ2_REG_VQ31_ENTRY_CNT                                                                    0x2404d0UL //Access:R    DataWidth:0x8   Number of entries occupied by vq 31 in pswrq memory.  Chips: BB_A0 BB_B0 K2
37948 #define PSWRQ2_REG_VQ0_MAX_ENTRY_CNT                                                                 0x2404d4UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 0.  Chips: BB_A0 BB_B0 K2
37949 #define PSWRQ2_REG_VQ1_MAX_ENTRY_CNT                                                                 0x2404d8UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 1.  Chips: BB_A0 BB_B0 K2
37950 #define PSWRQ2_REG_VQ2_MAX_ENTRY_CNT                                                                 0x2404dcUL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 2.  Chips: BB_A0 BB_B0 K2
37951 #define PSWRQ2_REG_VQ3_MAX_ENTRY_CNT                                                                 0x2404e0UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 3.  Chips: BB_A0 BB_B0 K2
37952 #define PSWRQ2_REG_VQ4_MAX_ENTRY_CNT                                                                 0x2404e4UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 4.  Chips: BB_A0 BB_B0 K2
37953 #define PSWRQ2_REG_VQ5_MAX_ENTRY_CNT                                                                 0x2404e8UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 5.  Chips: BB_A0 BB_B0 K2
37954 #define PSWRQ2_REG_VQ6_MAX_ENTRY_CNT                                                                 0x2404ecUL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 6.  Chips: BB_A0 BB_B0 K2
37955 #define PSWRQ2_REG_VQ7_MAX_ENTRY_CNT                                                                 0x2404f0UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 7.  Chips: BB_A0 BB_B0 K2
37956 #define PSWRQ2_REG_VQ8_MAX_ENTRY_CNT                                                                 0x2404f4UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 8.  Chips: BB_A0 BB_B0 K2
37957 #define PSWRQ2_REG_VQ9_MAX_ENTRY_CNT                                                                 0x2404f8UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 9.  Chips: BB_A0 BB_B0 K2
37958 #define PSWRQ2_REG_VQ10_MAX_ENTRY_CNT                                                                0x2404fcUL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 10.  Chips: BB_A0 BB_B0 K2
37959 #define PSWRQ2_REG_VQ11_MAX_ENTRY_CNT                                                                0x240500UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 11.  Chips: BB_A0 BB_B0 K2
37960 #define PSWRQ2_REG_VQ12_MAX_ENTRY_CNT                                                                0x240504UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 12.  Chips: BB_A0 BB_B0 K2
37961 #define PSWRQ2_REG_VQ13_MAX_ENTRY_CNT                                                                0x240508UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 13.  Chips: BB_A0 BB_B0 K2
37962 #define PSWRQ2_REG_VQ14_MAX_ENTRY_CNT                                                                0x24050cUL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 14.  Chips: BB_A0 BB_B0 K2
37963 #define PSWRQ2_REG_VQ15_MAX_ENTRY_CNT                                                                0x240510UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 15.  Chips: BB_A0 BB_B0 K2
37964 #define PSWRQ2_REG_VQ16_MAX_ENTRY_CNT                                                                0x240514UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 16.  Chips: BB_A0 BB_B0 K2
37965 #define PSWRQ2_REG_VQ17_MAX_ENTRY_CNT                                                                0x240518UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 17.  Chips: BB_A0 BB_B0 K2
37966 #define PSWRQ2_REG_VQ18_MAX_ENTRY_CNT                                                                0x24051cUL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 18.  Chips: BB_A0 BB_B0 K2
37967 #define PSWRQ2_REG_VQ19_MAX_ENTRY_CNT                                                                0x240520UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 19.  Chips: BB_A0 BB_B0 K2
37968 #define PSWRQ2_REG_VQ20_MAX_ENTRY_CNT                                                                0x240524UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 20.  Chips: BB_A0 BB_B0 K2
37969 #define PSWRQ2_REG_VQ21_MAX_ENTRY_CNT                                                                0x240528UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 21.  Chips: BB_A0 BB_B0 K2
37970 #define PSWRQ2_REG_VQ22_MAX_ENTRY_CNT                                                                0x24052cUL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 22.  Chips: BB_A0 BB_B0 K2
37971 #define PSWRQ2_REG_VQ23_MAX_ENTRY_CNT                                                                0x240530UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 23.  Chips: BB_A0 BB_B0 K2
37972 #define PSWRQ2_REG_VQ24_MAX_ENTRY_CNT                                                                0x240534UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 24.  Chips: BB_A0 BB_B0 K2
37973 #define PSWRQ2_REG_VQ25_MAX_ENTRY_CNT                                                                0x240538UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 25.  Chips: BB_A0 BB_B0 K2
37974 #define PSWRQ2_REG_VQ26_MAX_ENTRY_CNT                                                                0x24053cUL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 26.  Chips: BB_A0 BB_B0 K2
37975 #define PSWRQ2_REG_VQ27_MAX_ENTRY_CNT                                                                0x240540UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 27.  Chips: BB_A0 BB_B0 K2
37976 #define PSWRQ2_REG_VQ28_MAX_ENTRY_CNT                                                                0x240544UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 28.  Chips: BB_A0 BB_B0 K2
37977 #define PSWRQ2_REG_VQ29_MAX_ENTRY_CNT                                                                0x240548UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 29.  Chips: BB_A0 BB_B0 K2
37978 #define PSWRQ2_REG_VQ30_MAX_ENTRY_CNT                                                                0x24054cUL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 30.  Chips: BB_A0 BB_B0 K2
37979 #define PSWRQ2_REG_VQ31_MAX_ENTRY_CNT                                                                0x240550UL //Access:R    DataWidth:0x8   Maximum Number of entries occupied by vq 31.  Chips: BB_A0 BB_B0 K2
37980 #define PSWRQ2_REG_UFIFO_NUM_OF_ENTRY                                                                0x240554UL //Access:R    DataWidth:0x5   Number of entries in the ufifo;This fifo has l2p completions.  Chips: BB_A0 BB_B0 K2
37981 #define PSWRQ2_REG_QM_PCI_ATTR                                                                       0x240558UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37982     #define PSWRQ2_REG_QM_PCI_ATTR_QM_RELAXED                                                        (0x1<<0) // Relaxed oredering attribute for qm.
37983     #define PSWRQ2_REG_QM_PCI_ATTR_QM_RELAXED_SHIFT                                                  0
37984     #define PSWRQ2_REG_QM_PCI_ATTR_QM_NOSNOOP                                                        (0x1<<1) // Nosnoop attribute for qm.
37985     #define PSWRQ2_REG_QM_PCI_ATTR_QM_NOSNOOP_SHIFT                                                  1
37986 #define PSWRQ2_REG_TM_PCI_ATTR                                                                       0x24055cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37987     #define PSWRQ2_REG_TM_PCI_ATTR_TM_RELAXED                                                        (0x1<<0) // Relaxed oredering attribute for tm.
37988     #define PSWRQ2_REG_TM_PCI_ATTR_TM_RELAXED_SHIFT                                                  0
37989     #define PSWRQ2_REG_TM_PCI_ATTR_TM_NOSNOOP                                                        (0x1<<1) // Nosnoop attribute for tm.
37990     #define PSWRQ2_REG_TM_PCI_ATTR_TM_NOSNOOP_SHIFT                                                  1
37991 #define PSWRQ2_REG_SRC_PCI_ATTR                                                                      0x240560UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37992     #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_RELAXED                                                      (0x1<<0) // Relaxed oredering attribute for src.
37993     #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_RELAXED_SHIFT                                                0
37994     #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_NOSNOOP                                                      (0x1<<1) // Nosnoop attribute for src.
37995     #define PSWRQ2_REG_SRC_PCI_ATTR_SRC_NOSNOOP_SHIFT                                                1
37996 #define PSWRQ2_REG_CDU_PCI_ATTR                                                                      0x240564UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
37997     #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_RELAXED                                                      (0x1<<0) // Relaxed oredering attribute for cdu. Removed in E4B0, PXP request flag is used.
37998     #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_RELAXED_SHIFT                                                0
37999     #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_NOSNOOP                                                      (0x1<<1) // Nosnoop attribute for cdu. Removed in E4B0, PXP request flag is used.
38000     #define PSWRQ2_REG_CDU_PCI_ATTR_CDU_NOSNOOP_SHIFT                                                1
38001 #define PSWRQ2_REG_DBG_PCI_ATTR                                                                      0x240568UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
38002     #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_RELAXED                                                      (0x1<<0) // Relaxed oredering attribute for dbg.
38003     #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_RELAXED_SHIFT                                                0
38004     #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_NOSNOOP                                                      (0x1<<1) // Nosnoop attribute for dbg.
38005     #define PSWRQ2_REG_DBG_PCI_ATTR_DBG_NOSNOOP_SHIFT                                                1
38006 #define PSWRQ2_REG_HC_PCI_ATTR                                                                       0x24056cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
38007     #define PSWRQ2_REG_HC_PCI_ATTR_HC_RELAXED                                                        (0x1<<0) // Relaxed oredering attribute for hc.
38008     #define PSWRQ2_REG_HC_PCI_ATTR_HC_RELAXED_SHIFT                                                  0
38009     #define PSWRQ2_REG_HC_PCI_ATTR_HC_NOSNOOP                                                        (0x1<<1) // Nosnoop attribute for hc.
38010     #define PSWRQ2_REG_HC_PCI_ATTR_HC_NOSNOOP_SHIFT                                                  1
38011 #define PSWRQ2_REG_DMAE_PCI_ATTR                                                                     0x240570UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
38012     #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_RELAXED                                                    (0x1<<0) // Relaxed oredering attribute for dmae.
38013     #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_RELAXED_SHIFT                                              0
38014     #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_NOSNOOP                                                    (0x1<<1) // Nosnoop attribute for dmae.
38015     #define PSWRQ2_REG_DMAE_PCI_ATTR_DMAE_NOSNOOP_SHIFT                                              1
38016 #define PSWRQ2_REG_QM_ENDIAN_M                                                                       0x240574UL //Access:RW   DataWidth:0x2   Endian mode for qm.  Chips: BB_A0 BB_B0 K2
38017 #define PSWRQ2_REG_TM_ENDIAN_M                                                                       0x240578UL //Access:RW   DataWidth:0x2   Endian mode for tm.  Chips: BB_A0 BB_B0 K2
38018 #define PSWRQ2_REG_SRC_ENDIAN_M                                                                      0x24057cUL //Access:RW   DataWidth:0x2   Endian mode for src.  Chips: BB_A0 BB_B0 K2
38019 #define PSWRQ2_REG_DBG_ENDIAN_M                                                                      0x240580UL //Access:RW   DataWidth:0x2   Endian mode for debug.  Chips: BB_A0 BB_B0 K2
38020 #define PSWRQ2_REG_PBF_ENDIAN_M                                                                      0x240584UL //Access:RW   DataWidth:0x2   Endian mode for pbf.  Chips: BB_A0 BB_B0 K2
38021 #define PSWRQ2_REG_DONE_FIFO_TH                                                                      0x240588UL //Access:RW   DataWidth:0x5   Write Done fifo threshold; this fifo has write done indications;this threshold would not be reached unless there is a bug.  Chips: BB_A0 BB_B0 K2
38022 #define PSWRQ2_REG_BW_RD_ADD0                                                                        0x24058cUL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ0 write requests.  Chips: BB_A0 BB_B0 K2
38023 #define PSWRQ2_REG_BW_ADD1                                                                           0x240590UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38024     #define PSWRQ2_REG_BW_ADD1_BW_RD_ADD1                                                            (0x3ff<<0) // Bandwidth addition to VQ1 read requests.
38025     #define PSWRQ2_REG_BW_ADD1_BW_RD_ADD1_SHIFT                                                      0
38026     #define PSWRQ2_REG_BW_ADD1_BW_WR_ADD1                                                            (0x3ff<<10) // Bandwidth addition to VQ1 write requests.
38027     #define PSWRQ2_REG_BW_ADD1_BW_WR_ADD1_SHIFT                                                      10
38028 #define PSWRQ2_REG_BW_ADD2                                                                           0x240594UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38029     #define PSWRQ2_REG_BW_ADD2_BW_RD_ADD2                                                            (0x3ff<<0) // Bandwidth addition to VQ2 read requests.
38030     #define PSWRQ2_REG_BW_ADD2_BW_RD_ADD2_SHIFT                                                      0
38031     #define PSWRQ2_REG_BW_ADD2_BW_WR_ADD2                                                            (0x3ff<<10) // Bandwidth addition to VQ2 write requests.
38032     #define PSWRQ2_REG_BW_ADD2_BW_WR_ADD2_SHIFT                                                      10
38033 #define PSWRQ2_REG_BW_ADD3                                                                           0x240598UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38034     #define PSWRQ2_REG_BW_ADD3_BW_RD_ADD3                                                            (0x3ff<<0) // Bandwidth addition to VQ3 read requests.
38035     #define PSWRQ2_REG_BW_ADD3_BW_RD_ADD3_SHIFT                                                      0
38036     #define PSWRQ2_REG_BW_ADD3_BW_WR_ADD3                                                            (0x3ff<<10) // Bandwidth addition to VQ3 write requests.
38037     #define PSWRQ2_REG_BW_ADD3_BW_WR_ADD3_SHIFT                                                      10
38038 #define PSWRQ2_REG_BW_RD_ADD4                                                                        0x24059cUL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ4 read requests.  Chips: BB_A0 BB_B0 K2
38039 #define PSWRQ2_REG_BW_RD_ADD5                                                                        0x2405a0UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ5 read requests.  Chips: BB_A0 BB_B0 K2
38040 #define PSWRQ2_REG_BW_ADD6                                                                           0x2405a4UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38041     #define PSWRQ2_REG_BW_ADD6_BW_RD_ADD6                                                            (0x3ff<<0) // Bandwidth addition to VQ6 read requests.
38042     #define PSWRQ2_REG_BW_ADD6_BW_RD_ADD6_SHIFT                                                      0
38043     #define PSWRQ2_REG_BW_ADD6_BW_WR_ADD6                                                            (0x3ff<<10) // Bandwidth addition to VQ6 write requests.
38044     #define PSWRQ2_REG_BW_ADD6_BW_WR_ADD6_SHIFT                                                      10
38045 #define PSWRQ2_REG_BW_ADD7                                                                           0x2405a8UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38046     #define PSWRQ2_REG_BW_ADD7_BW_RD_ADD7                                                            (0x3ff<<0) // Bandwidth addition to VQ7 read requests.
38047     #define PSWRQ2_REG_BW_ADD7_BW_RD_ADD7_SHIFT                                                      0
38048     #define PSWRQ2_REG_BW_ADD7_BW_WR_ADD7                                                            (0x3ff<<10) // Bandwidth addition to VQ7 write requests.
38049     #define PSWRQ2_REG_BW_ADD7_BW_WR_ADD7_SHIFT                                                      10
38050 #define PSWRQ2_REG_BW_ADD8                                                                           0x2405acUL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38051     #define PSWRQ2_REG_BW_ADD8_BW_RD_ADD8                                                            (0x3ff<<0) // Bandwidth addition to VQ8 read requests.
38052     #define PSWRQ2_REG_BW_ADD8_BW_RD_ADD8_SHIFT                                                      0
38053     #define PSWRQ2_REG_BW_ADD8_BW_WR_ADD8                                                            (0x3ff<<10) // Bandwidth addition to VQ8 write requests.
38054     #define PSWRQ2_REG_BW_ADD8_BW_WR_ADD8_SHIFT                                                      10
38055 #define PSWRQ2_REG_BW_ADD9                                                                           0x2405b0UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38056     #define PSWRQ2_REG_BW_ADD9_BW_RD_ADD9                                                            (0x3ff<<0) // Bandwidth addition to VQ9 read requests.
38057     #define PSWRQ2_REG_BW_ADD9_BW_RD_ADD9_SHIFT                                                      0
38058     #define PSWRQ2_REG_BW_ADD9_BW_WR_ADD9                                                            (0x3ff<<10) // Bandwidth addition to VQ9 write requests.
38059     #define PSWRQ2_REG_BW_ADD9_BW_WR_ADD9_SHIFT                                                      10
38060 #define PSWRQ2_REG_BW_ADD10                                                                          0x2405b4UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38061     #define PSWRQ2_REG_BW_ADD10_BW_RD_ADD10                                                          (0x3ff<<0) // Bandwidth addition to VQ10 read requests.
38062     #define PSWRQ2_REG_BW_ADD10_BW_RD_ADD10_SHIFT                                                    0
38063     #define PSWRQ2_REG_BW_ADD10_BW_WR_ADD10                                                          (0x3ff<<10) // Bandwidth addition to VQ10 write requests.
38064     #define PSWRQ2_REG_BW_ADD10_BW_WR_ADD10_SHIFT                                                    10
38065 #define PSWRQ2_REG_BW_ADD11                                                                          0x2405b8UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38066     #define PSWRQ2_REG_BW_ADD11_BW_RD_ADD11                                                          (0x3ff<<0) // Bandwidth addition to VQ11 read requests.
38067     #define PSWRQ2_REG_BW_ADD11_BW_RD_ADD11_SHIFT                                                    0
38068     #define PSWRQ2_REG_BW_ADD11_BW_WR_ADD11                                                          (0x3ff<<10) // Bandwidth addition to VQ11 write requests.
38069     #define PSWRQ2_REG_BW_ADD11_BW_WR_ADD11_SHIFT                                                    10
38070 #define PSWRQ2_REG_BW_RD_ADD12                                                                       0x2405bcUL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ12 read requests.  Chips: BB_A0 BB_B0 K2
38071 #define PSWRQ2_REG_BW_RD_ADD13                                                                       0x2405c0UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ13 read requests.  Chips: BB_A0 BB_B0 K2
38072 #define PSWRQ2_REG_BW_ADD14                                                                          0x2405c4UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38073     #define PSWRQ2_REG_BW_ADD14_BW_RD_ADD14                                                          (0x3ff<<0) // Bandwidth addition to VQ14 read requests.
38074     #define PSWRQ2_REG_BW_ADD14_BW_RD_ADD14_SHIFT                                                    0
38075     #define PSWRQ2_REG_BW_ADD14_BW_WR_ADD14                                                          (0x3ff<<10) // Bandwidth addition to VQ14 write requests.
38076     #define PSWRQ2_REG_BW_ADD14_BW_WR_ADD14_SHIFT                                                    10
38077 #define PSWRQ2_REG_BW_RD_ADD15                                                                       0x2405c8UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ15 read requests.  Chips: BB_A0 BB_B0 K2
38078 #define PSWRQ2_REG_BW_RD_ADD16                                                                       0x2405ccUL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ16 read requests.  Chips: BB_A0 BB_B0 K2
38079 #define PSWRQ2_REG_BW_RD_ADD17                                                                       0x2405d0UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ17 read requests.  Chips: BB_A0 BB_B0 K2
38080 #define PSWRQ2_REG_BW_RD_ADD18                                                                       0x2405d4UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ18 read requests.  Chips: BB_A0 BB_B0 K2
38081 #define PSWRQ2_REG_BW_RD_ADD19                                                                       0x2405d8UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ19 read requests.  Chips: BB_A0 BB_B0 K2
38082 #define PSWRQ2_REG_BW_RD_ADD20                                                                       0x2405dcUL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ20 read requests.  Chips: BB_A0 BB_B0 K2
38083 #define PSWRQ2_REG_BW_WR_ADD21                                                                       0x2405e0UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ21 write requests.  Chips: BB_A0 BB_B0 K2
38084 #define PSWRQ2_REG_BW_RD_ADD22                                                                       0x2405e4UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ22 read requests.  Chips: BB_A0 BB_B0 K2
38085 #define PSWRQ2_REG_BW_RD_ADD23                                                                       0x2405e8UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ23 read requests.  Chips: BB_A0 BB_B0 K2
38086 #define PSWRQ2_REG_BW_RD_ADD24                                                                       0x2405ecUL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ24 read requests.  Chips: BB_A0 BB_B0 K2
38087 #define PSWRQ2_REG_BW_RD_ADD25                                                                       0x2405f0UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ25 read requests.  Chips: BB_A0 BB_B0 K2
38088 #define PSWRQ2_REG_BW_RD_ADD26                                                                       0x2405f4UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ26 read requests.  Chips: BB_A0 BB_B0 K2
38089 #define PSWRQ2_REG_BW_RD_ADD27                                                                       0x2405f8UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ27 read requests.  Chips: BB_A0 BB_B0 K2
38090 #define PSWRQ2_REG_BW_ADD28                                                                          0x2405fcUL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38091     #define PSWRQ2_REG_BW_ADD28_BW_RD_ADD28                                                          (0x3ff<<0) // Bandwidth addition to VQ28 read requests.
38092     #define PSWRQ2_REG_BW_ADD28_BW_RD_ADD28_SHIFT                                                    0
38093     #define PSWRQ2_REG_BW_ADD28_BW_WR_ADD28                                                          (0x3ff<<10) // Bandwidth addition to VQ28 write requests.
38094     #define PSWRQ2_REG_BW_ADD28_BW_WR_ADD28_SHIFT                                                    10
38095 #define PSWRQ2_REG_BW_WR_ADD29                                                                       0x240600UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ29 write requests.  Chips: BB_A0 BB_B0 K2
38096 #define PSWRQ2_REG_BW_WR_ADD30                                                                       0x240604UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ30 write requests.  Chips: BB_A0 BB_B0 K2
38097 #define PSWRQ2_REG_BW_ADD31                                                                          0x240608UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38098     #define PSWRQ2_REG_BW_ADD31_BW_RD_ADD31                                                          (0x3ff<<0) // Bandwidth addition to VQ31 read requests.
38099     #define PSWRQ2_REG_BW_ADD31_BW_RD_ADD31_SHIFT                                                    0
38100     #define PSWRQ2_REG_BW_ADD31_BW_WR_ADD31                                                          (0x3ff<<10) // Bandwidth addition to VQ31 write requests.
38101     #define PSWRQ2_REG_BW_ADD31_BW_WR_ADD31_SHIFT                                                    10
38102 #define PSWRQ2_REG_BW_RD_UBOUND0                                                                     0x24060cUL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ0 read requests.  Chips: BB_A0 BB_B0 K2
38103 #define PSWRQ2_REG_BW_UB1                                                                            0x240610UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38104     #define PSWRQ2_REG_BW_UB1_BW_RD_UBOUND1                                                          (0x1ff<<0) // Bandwidth upper bound for VQ1 read requests.
38105     #define PSWRQ2_REG_BW_UB1_BW_RD_UBOUND1_SHIFT                                                    0
38106     #define PSWRQ2_REG_BW_UB1_BW_WR_UBOUND1                                                          (0x1ff<<9) // Bandwidth upper bound for VQ1 write requests.
38107     #define PSWRQ2_REG_BW_UB1_BW_WR_UBOUND1_SHIFT                                                    9
38108 #define PSWRQ2_REG_BW_UB2                                                                            0x240614UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38109     #define PSWRQ2_REG_BW_UB2_BW_RD_UBOUND2                                                          (0x1ff<<0) // Bandwidth upper bound for VQ2 read requests.
38110     #define PSWRQ2_REG_BW_UB2_BW_RD_UBOUND2_SHIFT                                                    0
38111     #define PSWRQ2_REG_BW_UB2_BW_WR_UBOUND2                                                          (0x1ff<<9) // Bandwidth upper bound for VQ2 read requests.
38112     #define PSWRQ2_REG_BW_UB2_BW_WR_UBOUND2_SHIFT                                                    9
38113 #define PSWRQ2_REG_BW_UB3                                                                            0x240618UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38114     #define PSWRQ2_REG_BW_UB3_BW_RD_UBOUND3                                                          (0x1ff<<0) // Bandwidth upper bound for VQ3 read requests.
38115     #define PSWRQ2_REG_BW_UB3_BW_RD_UBOUND3_SHIFT                                                    0
38116     #define PSWRQ2_REG_BW_UB3_BW_WR_UBOUND3                                                          (0x1ff<<9) // Bandwidth upper bound for VQ3 write requests.
38117     #define PSWRQ2_REG_BW_UB3_BW_WR_UBOUND3_SHIFT                                                    9
38118 #define PSWRQ2_REG_BW_RD_UBOUND4                                                                     0x24061cUL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ4 read requests.  Chips: BB_A0 BB_B0 K2
38119 #define PSWRQ2_REG_BW_RD_UBOUND5                                                                     0x240620UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ5 read requests.  Chips: BB_A0 BB_B0 K2
38120 #define PSWRQ2_REG_BW_UB6                                                                            0x240624UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38121     #define PSWRQ2_REG_BW_UB6_BW_RD_UBOUND6                                                          (0x1ff<<0) // Bandwidth upper bound for VQ6 read requests.
38122     #define PSWRQ2_REG_BW_UB6_BW_RD_UBOUND6_SHIFT                                                    0
38123     #define PSWRQ2_REG_BW_UB6_BW_WR_UBOUND6                                                          (0x1ff<<9) // Bandwidth upper bound for VQ6 write requests.
38124     #define PSWRQ2_REG_BW_UB6_BW_WR_UBOUND6_SHIFT                                                    9
38125 #define PSWRQ2_REG_BW_UB7                                                                            0x240628UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38126     #define PSWRQ2_REG_BW_UB7_BW_RD_UBOUND7                                                          (0x1ff<<0) // Bandwidth upper bound for VQ7 read requests.
38127     #define PSWRQ2_REG_BW_UB7_BW_RD_UBOUND7_SHIFT                                                    0
38128     #define PSWRQ2_REG_BW_UB7_BW_WR_UBOUND7                                                          (0x1ff<<9) // Bandwidth upper bound for VQ7 write requests.
38129     #define PSWRQ2_REG_BW_UB7_BW_WR_UBOUND7_SHIFT                                                    9
38130 #define PSWRQ2_REG_BW_UB8                                                                            0x24062cUL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38131     #define PSWRQ2_REG_BW_UB8_BW_RD_UBOUND8                                                          (0x1ff<<0) // Bandwidth upper bound for VQ8 read requests.
38132     #define PSWRQ2_REG_BW_UB8_BW_RD_UBOUND8_SHIFT                                                    0
38133     #define PSWRQ2_REG_BW_UB8_BW_WR_UBOUND8                                                          (0x1ff<<9) // Bandwidth upper bound for VQ8 write requests.
38134     #define PSWRQ2_REG_BW_UB8_BW_WR_UBOUND8_SHIFT                                                    9
38135 #define PSWRQ2_REG_BW_UB9                                                                            0x240630UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38136     #define PSWRQ2_REG_BW_UB9_BW_RD_UBOUND9                                                          (0x1ff<<0) // Bandwidth upper bound for VQ9 read requests.
38137     #define PSWRQ2_REG_BW_UB9_BW_RD_UBOUND9_SHIFT                                                    0
38138     #define PSWRQ2_REG_BW_UB9_BW_WR_UBOUND9                                                          (0x1ff<<9) // Bandwidth upper bound for VQ9 write requests.
38139     #define PSWRQ2_REG_BW_UB9_BW_WR_UBOUND9_SHIFT                                                    9
38140 #define PSWRQ2_REG_BW_UB10                                                                           0x240634UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38141     #define PSWRQ2_REG_BW_UB10_BW_RD_UBOUND10                                                        (0x1ff<<0) // Bandwidth upper bound for VQ10 read requests.
38142     #define PSWRQ2_REG_BW_UB10_BW_RD_UBOUND10_SHIFT                                                  0
38143     #define PSWRQ2_REG_BW_UB10_BW_WR_UBOUND10                                                        (0x1ff<<9) // Bandwidth upper bound for VQ10 write requests.
38144     #define PSWRQ2_REG_BW_UB10_BW_WR_UBOUND10_SHIFT                                                  9
38145 #define PSWRQ2_REG_BW_UB11                                                                           0x240638UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38146     #define PSWRQ2_REG_BW_UB11_BW_RD_UBOUND11                                                        (0x1ff<<0) // Bandwidth upper bound for VQ11 read requests.
38147     #define PSWRQ2_REG_BW_UB11_BW_RD_UBOUND11_SHIFT                                                  0
38148     #define PSWRQ2_REG_BW_UB11_BW_WR_UBOUND11                                                        (0x1ff<<9) // Bandwidth upper bound for VQ11 write requests.
38149     #define PSWRQ2_REG_BW_UB11_BW_WR_UBOUND11_SHIFT                                                  9
38150 #define PSWRQ2_REG_BW_RD_UBOUND12                                                                    0x24063cUL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ12 read requests.  Chips: BB_A0 BB_B0 K2
38151 #define PSWRQ2_REG_BW_RD_UBOUND13                                                                    0x240640UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ13 read requests.  Chips: BB_A0 BB_B0 K2
38152 #define PSWRQ2_REG_BW_UB14                                                                           0x240644UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38153     #define PSWRQ2_REG_BW_UB14_BW_RD_UBOUND14                                                        (0x1ff<<0) // Bandwidth upper bound for VQ14 read requests.
38154     #define PSWRQ2_REG_BW_UB14_BW_RD_UBOUND14_SHIFT                                                  0
38155     #define PSWRQ2_REG_BW_UB14_BW_WR_UBOUND14                                                        (0x1ff<<9) // Bandwidth upper bound for VQ14 write requests.
38156     #define PSWRQ2_REG_BW_UB14_BW_WR_UBOUND14_SHIFT                                                  9
38157 #define PSWRQ2_REG_BW_RD_UBOUND15                                                                    0x240648UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ15 read requests.  Chips: BB_A0 BB_B0 K2
38158 #define PSWRQ2_REG_BW_RD_UBOUND16                                                                    0x24064cUL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ16 read requests.  Chips: BB_A0 BB_B0 K2
38159 #define PSWRQ2_REG_BW_RD_UBOUND17                                                                    0x240650UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ17 read requests.  Chips: BB_A0 BB_B0 K2
38160 #define PSWRQ2_REG_BW_RD_UBOUND18                                                                    0x240654UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ18 read requests.  Chips: BB_A0 BB_B0 K2
38161 #define PSWRQ2_REG_BW_RD_UBOUND19                                                                    0x240658UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ19 read requests.  Chips: BB_A0 BB_B0 K2
38162 #define PSWRQ2_REG_BW_RD_UBOUND20                                                                    0x24065cUL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ20 read requests.  Chips: BB_A0 BB_B0 K2
38163 #define PSWRQ2_REG_BW_WR_UBOUND21                                                                    0x240660UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ21 write requests.  Chips: BB_A0 BB_B0 K2
38164 #define PSWRQ2_REG_BW_RD_UBOUND22                                                                    0x240664UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ22 read requests.  Chips: BB_A0 BB_B0 K2
38165 #define PSWRQ2_REG_BW_RD_UBOUND23                                                                    0x240668UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ23 read requests.  Chips: BB_A0 BB_B0 K2
38166 #define PSWRQ2_REG_BW_RD_UBOUND24                                                                    0x24066cUL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ24 read requests.  Chips: BB_A0 BB_B0 K2
38167 #define PSWRQ2_REG_BW_RD_UBOUND25                                                                    0x240670UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ25 read requests.  Chips: BB_A0 BB_B0 K2
38168 #define PSWRQ2_REG_BW_RD_UBOUND26                                                                    0x240674UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ26 read requests.  Chips: BB_A0 BB_B0 K2
38169 #define PSWRQ2_REG_BW_RD_UBOUND27                                                                    0x240678UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ27 read requests.  Chips: BB_A0 BB_B0 K2
38170 #define PSWRQ2_REG_BW_UB28                                                                           0x24067cUL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38171     #define PSWRQ2_REG_BW_UB28_BW_RD_UBOUND28                                                        (0x1ff<<0) // Bandwidth upper bound for VQ28 read requests.
38172     #define PSWRQ2_REG_BW_UB28_BW_RD_UBOUND28_SHIFT                                                  0
38173     #define PSWRQ2_REG_BW_UB28_BW_WR_UBOUND28                                                        (0x1ff<<9) // Bandwidth upper bound for VQ28.
38174     #define PSWRQ2_REG_BW_UB28_BW_WR_UBOUND28_SHIFT                                                  9
38175 #define PSWRQ2_REG_BW_WR_UBOUND29                                                                    0x240680UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ29.  Chips: BB_A0 BB_B0 K2
38176 #define PSWRQ2_REG_BW_WR_UBOUND30                                                                    0x240684UL //Access:RW   DataWidth:0x9   Bandwidth upper bound for VQ30.  Chips: BB_A0 BB_B0 K2
38177 #define PSWRQ2_REG_BW_UB31                                                                           0x240688UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38178     #define PSWRQ2_REG_BW_UB31_BW_RD_UBOUND31                                                        (0x1ff<<0) // Bandwidth upper bound for VQ31 read requests.
38179     #define PSWRQ2_REG_BW_UB31_BW_RD_UBOUND31_SHIFT                                                  0
38180     #define PSWRQ2_REG_BW_UB31_BW_WR_UBOUND31                                                        (0x1ff<<9) // Bandwidth upper bound for VQ31 write requests.
38181     #define PSWRQ2_REG_BW_UB31_BW_WR_UBOUND31_SHIFT                                                  9
38182 #define PSWRQ2_REG_BW_RD_L0                                                                          0x24068cUL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ0 Read requests.  Chips: BB_A0 BB_B0 K2
38183 #define PSWRQ2_REG_BW_L1                                                                             0x240690UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38184     #define PSWRQ2_REG_BW_L1_BW_WR_L1                                                                (0x1ff<<0) // Bandwidth Typical L for VQ1 Write requests.
38185     #define PSWRQ2_REG_BW_L1_BW_WR_L1_SHIFT                                                          0
38186     #define PSWRQ2_REG_BW_L1_BW_RD_L1                                                                (0x1ff<<9) // Bandwidth Typical L for VQ1 Read requests.
38187     #define PSWRQ2_REG_BW_L1_BW_RD_L1_SHIFT                                                          9
38188 #define PSWRQ2_REG_BW_L2                                                                             0x240694UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38189     #define PSWRQ2_REG_BW_L2_BW_WR_L2                                                                (0x1ff<<0) // Bandwidth Typical L for VQ2 Write requests.
38190     #define PSWRQ2_REG_BW_L2_BW_WR_L2_SHIFT                                                          0
38191     #define PSWRQ2_REG_BW_L2_BW_RD_L2                                                                (0x1ff<<9) // Bandwidth Typical L for VQ2 Read requests.
38192     #define PSWRQ2_REG_BW_L2_BW_RD_L2_SHIFT                                                          9
38193 #define PSWRQ2_REG_BW_L3                                                                             0x240698UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38194     #define PSWRQ2_REG_BW_L3_BW_WR_L3                                                                (0x1ff<<0) // Bandwidth Typical L for VQ3 Write requests.
38195     #define PSWRQ2_REG_BW_L3_BW_WR_L3_SHIFT                                                          0
38196     #define PSWRQ2_REG_BW_L3_BW_RD_L3                                                                (0x1ff<<9) // Bandwidth Typical L for VQ3 Read requests.
38197     #define PSWRQ2_REG_BW_L3_BW_RD_L3_SHIFT                                                          9
38198 #define PSWRQ2_REG_BW_RD_L4                                                                          0x24069cUL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ4 Read requests.  Chips: BB_A0 BB_B0 K2
38199 #define PSWRQ2_REG_BW_RD_L5                                                                          0x2406a0UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ5 Read- currently not used.  Chips: BB_A0 BB_B0 K2
38200 #define PSWRQ2_REG_BW_L6                                                                             0x2406a4UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38201     #define PSWRQ2_REG_BW_L6_BW_RD_L6                                                                (0x1ff<<0) // Bandwidth Typical L for VQ6 Read requests.
38202     #define PSWRQ2_REG_BW_L6_BW_RD_L6_SHIFT                                                          0
38203     #define PSWRQ2_REG_BW_L6_BW_WR_L6                                                                (0x1ff<<9) // Bandwidth Typical L for VQ6 Write requests.
38204     #define PSWRQ2_REG_BW_L6_BW_WR_L6_SHIFT                                                          9
38205 #define PSWRQ2_REG_BW_L7                                                                             0x2406a8UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38206     #define PSWRQ2_REG_BW_L7_BW_RD_L7                                                                (0x1ff<<0) // Bandwidth Typical L for VQ7 Read requests.
38207     #define PSWRQ2_REG_BW_L7_BW_RD_L7_SHIFT                                                          0
38208     #define PSWRQ2_REG_BW_L7_BW_WR_L7                                                                (0x1ff<<9) // Bandwidth Typical L for VQ7 Write requests.
38209     #define PSWRQ2_REG_BW_L7_BW_WR_L7_SHIFT                                                          9
38210 #define PSWRQ2_REG_BW_L8                                                                             0x2406acUL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38211     #define PSWRQ2_REG_BW_L8_BW_RD_L8                                                                (0x1ff<<0) // Bandwidth Typical L for VQ8 Read requests.
38212     #define PSWRQ2_REG_BW_L8_BW_RD_L8_SHIFT                                                          0
38213     #define PSWRQ2_REG_BW_L8_BW_WR_L8                                                                (0x1ff<<9) // Bandwidth Typical L for VQ8 Write requests.
38214     #define PSWRQ2_REG_BW_L8_BW_WR_L8_SHIFT                                                          9
38215 #define PSWRQ2_REG_BW_L9                                                                             0x2406b0UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38216     #define PSWRQ2_REG_BW_L9_BW_RD_L9                                                                (0x1ff<<0) // Bandwidth Typical L for VQ9 Read requests.
38217     #define PSWRQ2_REG_BW_L9_BW_RD_L9_SHIFT                                                          0
38218     #define PSWRQ2_REG_BW_L9_BW_WR_L9                                                                (0x1ff<<9) // Bandwidth Typical L for VQ9 Write requests.
38219     #define PSWRQ2_REG_BW_L9_BW_WR_L9_SHIFT                                                          9
38220 #define PSWRQ2_REG_BW_L10                                                                            0x2406b4UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38221     #define PSWRQ2_REG_BW_L10_BW_RD_L10                                                              (0x1ff<<0) // Bandwidth Typical L for VQ10 Read requests.
38222     #define PSWRQ2_REG_BW_L10_BW_RD_L10_SHIFT                                                        0
38223     #define PSWRQ2_REG_BW_L10_BW_WR_L10                                                              (0x1ff<<9) // Bandwidth Typical L for VQ10 Write requests.
38224     #define PSWRQ2_REG_BW_L10_BW_WR_L10_SHIFT                                                        9
38225 #define PSWRQ2_REG_BW_L11                                                                            0x2406b8UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38226     #define PSWRQ2_REG_BW_L11_BW_RD_L11                                                              (0x1ff<<0) // Bandwidth Typical L for VQ11 Read requests.
38227     #define PSWRQ2_REG_BW_L11_BW_RD_L11_SHIFT                                                        0
38228     #define PSWRQ2_REG_BW_L11_BW_WR_L11                                                              (0x1ff<<9) // Bandwidth Typical L for VQ11 Write requests.
38229     #define PSWRQ2_REG_BW_L11_BW_WR_L11_SHIFT                                                        9
38230 #define PSWRQ2_REG_BW_RD_L12                                                                         0x2406bcUL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ12 Read requests.  Chips: BB_A0 BB_B0 K2
38231 #define PSWRQ2_REG_BW_RD_L13                                                                         0x2406c0UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ13 Read requests.  Chips: BB_A0 BB_B0 K2
38232 #define PSWRQ2_REG_BW_L14                                                                            0x2406c4UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38233     #define PSWRQ2_REG_BW_L14_BW_RD_L14                                                              (0x1ff<<0) // Bandwidth Typical L for VQ14 Read requests.
38234     #define PSWRQ2_REG_BW_L14_BW_RD_L14_SHIFT                                                        0
38235     #define PSWRQ2_REG_BW_L14_BW_WR_L14                                                              (0x1ff<<9) // Bandwidth Typical L for VQ14 Write requests.
38236     #define PSWRQ2_REG_BW_L14_BW_WR_L14_SHIFT                                                        9
38237 #define PSWRQ2_REG_BW_RD_L15                                                                         0x2406c8UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ15 Read requests.  Chips: BB_A0 BB_B0 K2
38238 #define PSWRQ2_REG_BW_RD_L16                                                                         0x2406ccUL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ16 Read requests.  Chips: BB_A0 BB_B0 K2
38239 #define PSWRQ2_REG_BW_RD_L17                                                                         0x2406d0UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ17 Read requests.  Chips: BB_A0 BB_B0 K2
38240 #define PSWRQ2_REG_BW_RD_L18                                                                         0x2406d4UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ18 Read requests.  Chips: BB_A0 BB_B0 K2
38241 #define PSWRQ2_REG_BW_RD_L19                                                                         0x2406d8UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ19 Read requests.  Chips: BB_A0 BB_B0 K2
38242 #define PSWRQ2_REG_BW_RD_L20                                                                         0x2406dcUL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ20 Read requests.  Chips: BB_A0 BB_B0 K2
38243 #define PSWRQ2_REG_BW_WR_L21                                                                         0x2406e0UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ21 Write requests.  Chips: BB_A0 BB_B0 K2
38244 #define PSWRQ2_REG_BW_RD_L22                                                                         0x2406e4UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ22 Read requests.  Chips: BB_A0 BB_B0 K2
38245 #define PSWRQ2_REG_BW_RD_L23                                                                         0x2406e8UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ23 Read requests.  Chips: BB_A0 BB_B0 K2
38246 #define PSWRQ2_REG_BW_RD_L24                                                                         0x2406ecUL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ24 Read requests.  Chips: BB_A0 BB_B0 K2
38247 #define PSWRQ2_REG_BW_RD_L25                                                                         0x2406f0UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ25 Read requests.  Chips: BB_A0 BB_B0 K2
38248 #define PSWRQ2_REG_BW_RD_L26                                                                         0x2406f4UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ26 Read requests.  Chips: BB_A0 BB_B0 K2
38249 #define PSWRQ2_REG_BW_RD_L27                                                                         0x2406f8UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ27 Read requests.  Chips: BB_A0 BB_B0 K2
38250 #define PSWRQ2_REG_BW_L28                                                                            0x2406fcUL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38251     #define PSWRQ2_REG_BW_L28_BW_RD_L28                                                              (0x1ff<<0) // Bandwidth Typical L for VQ28 Read requests.
38252     #define PSWRQ2_REG_BW_L28_BW_RD_L28_SHIFT                                                        0
38253     #define PSWRQ2_REG_BW_L28_BW_WR_L28                                                              (0x1ff<<9) // Bandwidth Typical L for VQ28 Write requests.
38254     #define PSWRQ2_REG_BW_L28_BW_WR_L28_SHIFT                                                        9
38255 #define PSWRQ2_REG_BW_WR_L29                                                                         0x240700UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ29 Write requests.  Chips: BB_A0 BB_B0 K2
38256 #define PSWRQ2_REG_BW_WR_L30                                                                         0x240704UL //Access:RW   DataWidth:0x9   Bandwidth Typical L for VQ30 Write requests.  Chips: BB_A0 BB_B0 K2
38257 #define PSWRQ2_REG_BW_L31                                                                            0x240708UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38258     #define PSWRQ2_REG_BW_L31_BW_RD_L31                                                              (0x1ff<<0) // Bandwidth Typical L for VQ31 Read requests.
38259     #define PSWRQ2_REG_BW_L31_BW_RD_L31_SHIFT                                                        0
38260     #define PSWRQ2_REG_BW_L31_BW_WR_L31                                                              (0x1ff<<9) // Bandwidth Typical L for VQ31 Write requests.
38261     #define PSWRQ2_REG_BW_L31_BW_WR_L31_SHIFT                                                        9
38262 #define PSWRQ2_REG_BW_RD                                                                             0x24070cUL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38263     #define PSWRQ2_REG_BW_RD_RD_BW_ADD                                                               (0x3ff<<0) // Bandwidth addition for read requests in the read write arbiter.
38264     #define PSWRQ2_REG_BW_RD_RD_BW_ADD_SHIFT                                                         0
38265     #define PSWRQ2_REG_BW_RD_RD_BW_UBOUND                                                            (0x1ff<<10) // Bandwidth upperbound for read requests in the read write arbiter.
38266     #define PSWRQ2_REG_BW_RD_RD_BW_UBOUND_SHIFT                                                      10
38267     #define PSWRQ2_REG_BW_RD_RD_BW_L                                                                 (0x1ff<<19) // Bandwidth Typical L for read requests in the read write arbiter.
38268     #define PSWRQ2_REG_BW_RD_RD_BW_L_SHIFT                                                           19
38269 #define PSWRQ2_REG_BW_WR                                                                             0x240710UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38270     #define PSWRQ2_REG_BW_WR_WR_BW_ADD                                                               (0x3ff<<0) // Bandwidth addition for write requests in the read write arbiter.
38271     #define PSWRQ2_REG_BW_WR_WR_BW_ADD_SHIFT                                                         0
38272     #define PSWRQ2_REG_BW_WR_WR_BW_UBOUND                                                            (0x1ff<<10) // Bandwidth upperbound for write requests in the read write arbiter.
38273     #define PSWRQ2_REG_BW_WR_WR_BW_UBOUND_SHIFT                                                      10
38274     #define PSWRQ2_REG_BW_WR_WR_BW_L                                                                 (0x1ff<<19) // Bandwidth Typical L for write requests in the read write arbiter.
38275     #define PSWRQ2_REG_BW_WR_WR_BW_L_SHIFT                                                           19
38276 #define PSWRQ2_REG_BW_CREDIT                                                                         0x240714UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
38277     #define PSWRQ2_REG_BW_CREDIT_READ_CREDIT                                                         (0xf<<0) // Indicates the number of credits for read sub-requests in th requester glue interface.
38278     #define PSWRQ2_REG_BW_CREDIT_READ_CREDIT_SHIFT                                                   0
38279     #define PSWRQ2_REG_BW_CREDIT_WRITE_CREDIT                                                        (0xf<<4) // Indicates the number of credits for write sub-requests in th requester glue interface.
38280     #define PSWRQ2_REG_BW_CREDIT_WRITE_CREDIT_SHIFT                                                  4
38281 #define PSWRQ2_REG_L2P_TM                                                                            0x240718UL //Access:RW   DataWidth:0x5   Tm input for l2p memory.  Chips: BB_A0 BB_B0 K2
38282 #define PSWRQ2_REG_SLOW_TH                                                                           0x24071cUL //Access:RW   DataWidth:0x8   When number of free entries in the context ram will be lower than this;the input clients arbiter will work in a slower pace.  Chips: BB_A0 BB_B0 K2
38283 #define PSWRQ2_REG_PDR_LIMIT                                                                         0x240720UL //Access:RW   DataWidth:0xe   Pending read limiter threshold; in Dwords.  Chips: BB_A0 BB_B0 K2
38284 #define PSWRQ2_REG_DBG_HEAD_MUX_SEL                                                                  0x240724UL //Access:RW   DataWidth:0x5   Sets which vq head pointer to see out of queues 0-31.  Chips: BB_A0 BB_B0 K2
38285 #define PSWRQ2_REG_DBG_TAIL_MUX_SEL                                                                  0x240728UL //Access:RW   DataWidth:0x5   Sets which vq tail pointer to see out of queues 0-31.  Chips: BB_A0 BB_B0 K2
38286 #define PSWRQ2_REG_L2P_MODE                                                                          0x24072cUL //Access:RW   DataWidth:0x1   Will determine how the logical address is calculated; 0: as in E1; 1:with new algorithm.  Chips: BB_A0 BB_B0 K2
38287 #define PSWRQ2_REG_DRAM_ALIGN_SEL                                                                    0x240730UL //Access:RW   DataWidth:0x1   When set the new alignment method (E2) will be applied; when reset the original alignment method (E1 E1H) will be applied.  Chips: BB_A0 BB_B0 K2
38288 #define PSWRQ2_REG_CXR_RAM0_TM                                                                       0x240734UL //Access:RW   DataWidth:0x8   TM bits for cxr ram0.  Chips: BB_A0 BB_B0 K2
38289 #define PSWRQ2_REG_CXR_RAM1_TM                                                                       0x240738UL //Access:RW   DataWidth:0x8   TM bits for cxr ram1.  Chips: BB_A0 BB_B0 K2
38290 #define PSWRQ2_REG_VQ_RD_DISABLE                                                                     0x24073cUL //Access:R    DataWidth:0xc   Vq read disable as wdone was not received yet for the wr request that was sent {vq1 ; vq2 ; vq3 ; vq6 ; vq7 ; vq8 ; vq9 ; vq10 ; vq11 ; vq14; vq28; vq31}.  Chips: BB_A0 BB_B0 K2
38291 #define PSWRQ2_REG_QC_REG1                                                                           0x240740UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38292 #define PSWRQ2_REG_QC_REG2                                                                           0x240744UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38293 #define PSWRQ2_REG_QC_VIQ_1ENTRY                                                                     0x240748UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38294 #define PSWRQ2_REG_QC_HOQ_IS_LOGICAL                                                                 0x24074cUL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38295 #define PSWRQ2_REG_QC_VIQ_TAIL_V                                                                     0x240750UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38296 #define PSWRQ2_REG_QC_VIQ_HEAD_V                                                                     0x240754UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38297 #define PSWRQ2_REG_QC_VIQ_31_28_TAIL                                                                 0x240758UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38298 #define PSWRQ2_REG_QC_VIQ_27_24_TAIL                                                                 0x24075cUL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38299 #define PSWRQ2_REG_QC_VIQ_23_20_TAIL                                                                 0x240760UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38300 #define PSWRQ2_REG_QC_VIQ_19_16_TAIL                                                                 0x240764UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38301 #define PSWRQ2_REG_QC_VIQ_15_12_TAIL                                                                 0x240768UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38302 #define PSWRQ2_REG_QC_VIQ_11_8_TAIL                                                                  0x24076cUL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38303 #define PSWRQ2_REG_QC_VIQ_7_4_TAIL                                                                   0x240770UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38304 #define PSWRQ2_REG_QC_VIQ_3_0_TAIL                                                                   0x240774UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38305 #define PSWRQ2_REG_QC_VIQ_31_28_HEAD                                                                 0x240778UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38306 #define PSWRQ2_REG_QC_VIQ_27_24_HEAD                                                                 0x24077cUL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38307 #define PSWRQ2_REG_QC_VIQ_23_20_HEAD                                                                 0x240780UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38308 #define PSWRQ2_REG_QC_VIQ_19_16_HEAD                                                                 0x240784UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38309 #define PSWRQ2_REG_QC_VIQ_15_12_HEAD                                                                 0x240788UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38310 #define PSWRQ2_REG_QC_VIQ_11_8_HEAD                                                                  0x24078cUL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38311 #define PSWRQ2_REG_QC_VIQ_7_4_HEAD                                                                   0x240790UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38312 #define PSWRQ2_REG_QC_VIQ_3_0_HEAD                                                                   0x240794UL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
38313 #define PSWRQ2_REG_BW_RD_ADD_TREQ                                                                    0x240798UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ TREQ read requests.  Chips: BB_A0 BB_B0 K2
38314 #define PSWRQ2_REG_BW_RD_UBOUND_TREQ                                                                 0x24079cUL //Access:RW   DataWidth:0x9   Bandwidth upper bound to VQ TREQ read requests.  Chips: BB_A0 BB_B0 K2
38315 #define PSWRQ2_REG_BW_RD_L_TREQ                                                                      0x2407a0UL //Access:RW   DataWidth:0x9   Bandwidth Typical L to VQ TREQ read requests.  Chips: BB_A0 BB_B0 K2
38316 #define PSWRQ2_REG_BW_WR_ADD_ICPL                                                                    0x2407a4UL //Access:RW   DataWidth:0xa   Bandwidth addition to VQ ICPL write requests.  Chips: BB_A0 BB_B0 K2
38317 #define PSWRQ2_REG_BW_WR_UBOUND_ICPL                                                                 0x2407a8UL //Access:RW   DataWidth:0x9   Bandwidth upper bound to VQ ICPL write requests.  Chips: BB_A0 BB_B0 K2
38318 #define PSWRQ2_REG_BW_WR_L_ICPL                                                                      0x2407acUL //Access:RW   DataWidth:0x9   Bandwidth Typical L to VQ ICPL write requests.  Chips: BB_A0 BB_B0 K2
38319 #define PSWRQ2_REG_ATC_USDM_FLAGS                                                                    0x2407b0UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38320 #define PSWRQ2_REG_ATC_USDMDP_FLAGS                                                                  0x2407b4UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38321 #define PSWRQ2_REG_ATC_TSDM_FLAGS                                                                    0x2407b8UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38322 #define PSWRQ2_REG_ATC_XSDM_FLAGS                                                                    0x2407bcUL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38323 #define PSWRQ2_REG_ATC_DMAE_FLAGS                                                                    0x2407c0UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38324 #define PSWRQ2_REG_ATC_CDUWR_FLAGS                                                                   0x2407c4UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38325 #define PSWRQ2_REG_ATC_CDURD_FLAGS                                                                   0x2407c8UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38326 #define PSWRQ2_REG_ATC_PBF_FLAGS                                                                     0x2407ccUL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38327 #define PSWRQ2_REG_ATC_QM_FLAGS                                                                      0x2407d0UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38328 #define PSWRQ2_REG_ATC_TM_FLAGS                                                                      0x2407d4UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38329 #define PSWRQ2_REG_ATC_SRC_FLAGS                                                                     0x2407d8UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38330 #define PSWRQ2_REG_ATC_DBG_FLAGS                                                                     0x2407dcUL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38331 #define PSWRQ2_REG_ATC_M2P_FLAGS                                                                     0x2407e0UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38332 #define PSWRQ2_REG_ATC_PTU_FLAGS                                                                     0x2407e4UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38333 #define PSWRQ2_REG_ATC_HC_FLAGS                                                                      0x2407e8UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38334 #define PSWRQ2_REG_ATC_VQ_ENABLE                                                                     0x2407ecUL //Access:RW   DataWidth:0x20  ATC VQ enable bits. When set - SR from the VQ can send ATC lookup request to the ATC (assuming all other conditions are met). When reset - all SR-s from the VQ will NOT go through the ATC. b0 - VQ0; b1 - VQ1; b30 - VQ30; b31 - reserved (should be filled with zeroes).  Chips: BB_A0 BB_B0 K2
38335 #define PSWRQ2_REG_ATC_INTERNAL_ATS_ENABLE                                                           0x2407f0UL //Access:RW   DataWidth:0x2   ATC enable values per PF as follows: b0 - PF enable; b1 - VF enable; PF enable bit is relevant when VF_Valid (in the request) bit is 0; VF enable bit is relevant when VF_Valid bit is 1.  Chips: BB_A0 BB_B0 K2
38336 #define PSWRQ2_REG_ATC_INTERNAL_ATS_ENABLE_ALL                                                       0x2407f4UL //Access:R    DataWidth:0x20  Concatenated values of rq_atc_internal_ats_enable as follows: b0 - PF0; b1 - VF0; b2 - PF1; b3 - VF1; b30 - PF15 ; b31 - VF15;.  Chips: BB_A0 BB_B0 K2
38337 #define PSWRQ2_REG_ATC_VQ_GO_TRANSLATED                                                              0x2407f8UL //Access:RW   DataWidth:0x20  DEBUG ONLY. bit per VQ. go translated set means that SR of the matched VQ will be always sent to the GLUE with the at_valid=1 indication (see atc_code in PSWRQ-PGLUE interface for more details). In that case the address will be delivered by the chip (and not by the ATC). This mode will be used mainly for debug and the other configurations must make sure that ATC will never be used for that VQ while the go_translated bit for that VQ is set. when reset means that the at_valid indication will be determined according to the ATC.  Chips: BB_A0 BB_B0 K2
38338 #define PSWRQ2_REG_ATC_GLOBAL_ENABLE                                                                 0x2407fcUL //Access:RW   DataWidth:0x1   Global ATC enable bit. when reset all ATC logic is disabled within the PSWRQ. The value of this register must be the same as RD_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.  Chips: BB_A0 BB_B0 K2
38339 #define PSWRQ2_REG_CLOSE_GATE_VQ_LSB_EN                                                              0x240800UL //Access:RW   DataWidth:0x20  VQ-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU TREQ & ICPL requests to be chosen in such scenario.  Chips: BB_A0 BB_B0 K2
38340 #define PSWRQ2_REG_CLOSE_GATE_VQ_MSB_EN                                                              0x240804UL //Access:RW   DataWidth:0x2   VQ-s that are enabled (i.e. can be chosen by the GARB) in close the gates scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU TREQ & ICPL requests to be chosen in such scenario.  Chips: BB_A0 BB_B0 K2
38341 #define PSWRQ2_REG_STALL_MEM_VQ_LSB_EN                                                               0x240808UL //Access:RW   DataWidth:0x20  VQ-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU requests to be chosen in such scenario.  Chips: BB_A0 BB_B0 K2
38342 #define PSWRQ2_REG_STALL_MEM_VQ_MSB_EN                                                               0x24080cUL //Access:RW   DataWidth:0x2   VQ-s that are enabled (i.e. can be chosen by the GARB) in stall mem scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow IGU requests to be chosen in such scenario.  Chips: BB_A0 BB_B0 K2
38343 #define PSWRQ2_REG_STALL_INT_VQ_LSB_EN                                                               0x240810UL //Access:RW   DataWidth:0x20  VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow non-IGU requests to be chosen in such scenario.  Chips: BB_A0 BB_B0 K2
38344 #define PSWRQ2_REG_STALL_INT_VQ_MSB_EN                                                               0x240814UL //Access:RW   DataWidth:0x2   VQ-s that are enabled (i.e. can be chosen by the GARB) in stall int scenario; VQ32 = TREQ; VQ33 = ICPL; the original E4 plan is to allow non-IGU requests to be chosen in such scenario.  Chips: BB_A0 BB_B0 K2
38345 #define PSWRQ2_REG_TREQ_FIFO_FILL_LVL                                                                0x240818UL //Access:R    DataWidth:0x6   The fill level of the TREQ fifo.  Chips: BB_A0 BB_B0 K2
38346 #define PSWRQ2_REG_ICPL_FIFO_FILL_LVL                                                                0x24081cUL //Access:R    DataWidth:0x3   The fill level of the ICPL fifo.  Chips: BB_A0 BB_B0 K2
38347 #define PSWRQ2_REG_ATC_TREQ_FIFO_TM                                                                  0x240820UL //Access:RW   DataWidth:0x2   NOT USED.  Chips: BB_A0 BB_B0 K2
38348 #define PSWRQ2_REG_ASSERT_IF_ILT_FAIL                                                                0x240824UL //Access:RW   DataWidth:0x1   When set - assert ilt fail interrupt (rq_elt_addr) in case working in ilt mode and onchip translation fail due to overflow on vah_plus_1st signal (Cont00041628). If reset - interrupt will not assert.  Chips: BB_A0 BB_B0 K2
38349 #define PSWRQ2_REG_HOQ_RAM_RD_REQ                                                                    0x240828UL //Access:RW   DataWidth:0x5   FOR DBG: read request from the hoq ram; the write data represents the address which is the vqid; in order to read from the hoq ram the read enable register should be set as well (rq_hoq_ram_rd_en); upon read completion (rq_hoq_ram_rd_status =1) data_rd_0 data_rd_1 data_rd_2 and data_rd_3 are ready with the valid values.  Chips: BB_A0 BB_B0 K2
38350 #define PSWRQ2_REG_HOQ_RAM_RD_EN                                                                     0x24082cUL //Access:RW   DataWidth:0x1   FOR DBG: enable reading from the hoq ram; when set hoq rbc read is enabled; when reset hoq rbc read is disabled (i.e. rq_hoq_ram_rd_req will not have any affect).  Chips: BB_A0 BB_B0 K2
38351 #define PSWRQ2_REG_HOQ_RAM_RD_STATUS                                                                 0x240830UL //Access:R    DataWidth:0x1   FOR DBG: when set - data rd from hoq ram is completed (i.e. data is ready in data_rd_0 data_rd_1 data_rd2 and data_rd_3); when reset - still waiting for hoq ram read request to be completed).  Chips: BB_A0 BB_B0 K2
38352 #define PSWRQ2_REG_HOQ_RAM_DATA_RD_0                                                                 0x240834UL //Access:R    DataWidth:0x20  FOR DBG: bits 15:0 length; bits 31:16 request id.  Chips: BB_A0 BB_B0 K2
38353 #define PSWRQ2_REG_HOQ_RAM_DATA_RD_1                                                                 0x240838UL //Access:R    DataWidth:0x20  FOR DBG: address (32 lsb).  Chips: BB_A0 BB_B0 K2
38354 #define PSWRQ2_REG_HOQ_RAM_DATA_RD_2                                                                 0x24083cUL //Access:R    DataWidth:0x20  FOR DBG: address (32 msb).  Chips: BB_A0 BB_B0 K2
38355 #define PSWRQ2_REG_HOQ_RAM_DATA_RD_3                                                                 0x240840UL //Access:R    DataWidth:0x20  FOR DBG: bit 0 relaxed ordering; bit 1 no-snoop; bits 5:2 client id; bit 6 done type; bit 7 resevred; bit 10:8 pfid; bit 11 vf_valid; bit 17:12 vfid; bits 20:18 atc flags; bits 31:21 reserved.  Chips: BB_A0 BB_B0 K2
38356 #define PSWRQ2_REG_SR_CNT_WR_CNT                                                                     0x240844UL //Access:R    DataWidth:0x20  The total number of WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.  Chips: BB_A0 BB_B0 K2
38357 #define PSWRQ2_REG_SR_CNT_RD_CNT                                                                     0x240848UL //Access:R    DataWidth:0x20  The total number of RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.  Chips: BB_A0 BB_B0 K2
38358 #define PSWRQ2_REG_SR_CNT_PBF_CNT                                                                    0x24084cUL //Access:R    DataWidth:0x20  The number of PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.  Chips: BB_A0 BB_B0 K2
38359 #define PSWRQ2_REG_SR_CNT_USDMDP_CNT                                                                 0x240850UL //Access:R    DataWidth:0x20  The number of USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.  Chips: BB_A0 BB_B0 K2
38360 #define PSWRQ2_REG_SR_CNT_TREQ_CNT                                                                   0x240854UL //Access:R    DataWidth:0x20  The number of TREQ SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.  Chips: BB_A0 BB_B0 K2
38361 #define PSWRQ2_REG_SR_CNT_ICPL_CNT                                                                   0x240858UL //Access:R    DataWidth:0x20  The number of ICPL SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done.  Chips: BB_A0 BB_B0 K2
38362 #define PSWRQ2_REG_SR_CNT_WR_BYTE_LSB                                                                0x24085cUL //Access:R    DataWidth:0x20  The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value.  Chips: BB_A0 BB_B0 K2
38363 #define PSWRQ2_REG_SR_CNT_WR_BYTE_MSB                                                                0x240860UL //Access:R    DataWidth:0x9   The total number of bytes for WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value.  Chips: BB_A0 BB_B0 K2
38364 #define PSWRQ2_REG_SR_CNT_RD_BYTE_LSB                                                                0x240864UL //Access:R    DataWidth:0x20  The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value.  Chips: BB_A0 BB_B0 K2
38365 #define PSWRQ2_REG_SR_CNT_RD_BYTE_MSB                                                                0x240868UL //Access:R    DataWidth:0xc   The total number of bytes for RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value.  Chips: BB_A0 BB_B0 K2
38366 #define PSWRQ2_REG_SR_CNT_PBF_BYTE_LSB                                                               0x24086cUL //Access:R    DataWidth:0x20  The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value.  Chips: BB_A0 BB_B0 K2
38367 #define PSWRQ2_REG_SR_CNT_PBF_BYTE_MSB                                                               0x240870UL //Access:R    DataWidth:0xc   The number of bytes for PBF RD SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value.  Chips: BB_A0 BB_B0 K2
38368 #define PSWRQ2_REG_SR_CNT_USDMDP_BYTE_LSB                                                            0x240874UL //Access:R    DataWidth:0x20  The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - lsb value.  Chips: BB_A0 BB_B0 K2
38369 #define PSWRQ2_REG_SR_CNT_USDMDP_BYTE_MSB                                                            0x240878UL //Access:R    DataWidth:0x9   The number of bytes for USDM-DP WR SR-s that were sent to the PGLUE. Valid when Sr_cnt_status is done - msb value.  Chips: BB_A0 BB_B0 K2
38370 #define PSWRQ2_REG_SR_CNT_WINDOW_MODE                                                                0x24087cUL //Access:RW   DataWidth:0x1   Counting window mode. 0 - manual window: counting is manually being initiated & stopped by the user through GRC. 1 - configured window: counting occurs according to configured window size.  Chips: BB_A0 BB_B0 K2
38371 #define PSWRQ2_REG_SR_CNT_WINDOW_SIZE                                                                0x240880UL //Access:RW   DataWidth:0x20  Determines the size of the counting window. Valid when working in predefined window mode (i.e. Sr_cnt_window_mode = 1).  Granularity of sr_cnt_clk_tickxclk_pci cycles.  Chips: BB_A0 BB_B0 K2
38372 #define PSWRQ2_REG_SR_CNT_WINDOW_VALUE                                                               0x240884UL //Access:R    DataWidth:0x20  Global window counter for the current value of the recorded window. Represents the number of sr_cnt_clk_tickxclk_pci cycles from the beginning of counting. NOTE: beginning of counting is determined according to Sr_cnt_start_mode.  Chips: BB_A0 BB_B0 K2
38373 #define PSWRQ2_REG_SR_CNT_MANUAL_CMD                                                                 0x240888UL //Access:W    DataWidth:0x1   Write Only register. The manual window command sent by the user. Valid when working in manual window mode (i.e. Sr_cnt_window_mode = 0). 0 - stop counting. 1 - start counting.  Chips: BB_A0 BB_B0 K2
38374 #define PSWRQ2_REG_SR_CNT_RST                                                                        0x24088cUL //Access:W    DataWidth:0x1   Write Only register. RBC write command to this reg (any value) will reset the SR counters & the global window counter. In addition it'll move the Sr_cnt_status to idle state.  Chips: BB_A0 BB_B0 K2
38375 #define PSWRQ2_REG_SR_CNT_START_MODE                                                                 0x240890UL //Access:RW   DataWidth:0x1   Determines the trigger for start counting (for both SR counters & global window counter). 0 - start counting upon any first SR that is sent to the PGLUE. 1 - start counting upon first PBF/USDM-DP SR that is sent to the PGLUE.  Chips: BB_A0 BB_B0 K2
38376 #define PSWRQ2_REG_SR_CNT_ENABLE                                                                     0x240894UL //Access:RW   DataWidth:0x1   Enables the SR counting mechanism.  Chips: BB_A0 BB_B0 K2
38377 #define PSWRQ2_REG_SR_CNT_CLK_TICK                                                                   0x240898UL //Access:RW   DataWidth:0x3   The number of clk_pci ticks minus 1 between each increment of the global window counter (i.e. 0 is for 1 clk_pci cycle; 1 is for 2 clk_pci cycles; 7 is for 8 clk_pci cycles).  Chips: BB_A0 BB_B0 K2
38378 #define PSWRQ2_REG_SR_CNT_STATUS                                                                     0x24089cUL //Access:R    DataWidth:0x2   The status of the SR count mechanism: 0 - idle: ready to start new counting. 1 - ongoing: counting is currently ongoing. 2 - done: counting is completed. SR counters & global window counter are valid.  Chips: BB_A0 BB_B0 K2
38379 #define PSWRQ2_REG_LAST_RD_SR_LOG_0                                                                  0x2408a0UL //Access:R    DataWidth:0x20  SR address - 32 lsb.  Chips: BB_A0 BB_B0 K2
38380 #define PSWRQ2_REG_LAST_RD_SR_LOG_1                                                                  0x2408a4UL //Access:R    DataWidth:0x20  SR address - 32 msb.  Chips: BB_A0 BB_B0 K2
38381 #define PSWRQ2_REG_LAST_RD_SR_LOG_2                                                                  0x2408a8UL //Access:R    DataWidth:0x20  B15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes.  Chips: BB_A0 BB_B0 K2
38382 #define PSWRQ2_REG_LAST_RD_SR_LOG_3                                                                  0x2408acUL //Access:R    DataWidth:0x20  B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client id; b24-20: vq; b31-25: srid.  Chips: BB_A0 BB_B0 K2
38383 #define PSWRQ2_REG_LAST_RD_SR_LOG_4                                                                  0x2408b0UL //Access:R    DataWidth:0x9   b1-0: atc code; b3-2: endianity. b8-4: Treq otb entry.  Chips: BB_A0 BB_B0 K2
38384 #define PSWRQ2_REG_LAST_WR_SR_LOG_0                                                                  0x2408b4UL //Access:R    DataWidth:0x20  SR address - 32 lsb.  Chips: BB_A0 BB_B0 K2
38385 #define PSWRQ2_REG_LAST_WR_SR_LOG_1                                                                  0x2408b8UL //Access:R    DataWidth:0x20  SR address - 32 msb.  Chips: BB_A0 BB_B0 K2
38386 #define PSWRQ2_REG_LAST_WR_SR_LOG_2                                                                  0x2408bcUL //Access:R    DataWidth:0x20  B15-0: reqid; b28-16: SR length; b29 - reserved; b31-30: attributes.  Chips: BB_A0 BB_B0 K2
38387 #define PSWRQ2_REG_LAST_WR_SR_LOG_3                                                                  0x2408c0UL //Access:R    DataWidth:0x20  B3-0: PFID; b4: vf_valid; b12-b5: VFID; b13: first SR; b14: last SR; b19-15: client id; b24-20: vq; b30-25: start offset; b31: usdm err.  Chips: BB_A0 BB_B0 K2
38388 #define PSWRQ2_REG_LAST_WR_SR_LOG_4                                                                  0x2408c4UL //Access:R    DataWidth:0xa   b1-0: atc code; b2: wdone type; b4-3: endianity; b9-5: Icpl itag index.  Chips: BB_A0 BB_B0 K2
38389 #define PSWRQ2_REG_MSDM_ENTRY_TH                                                                     0x2408c8UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to msdm in the queues.  Chips: BB_A0 BB_B0 K2
38390 #define PSWRQ2_REG_YSDM_ENTRY_TH                                                                     0x2408ccUL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to ysdm in the queues.  Chips: BB_A0 BB_B0 K2
38391 #define PSWRQ2_REG_PSDM_ENTRY_TH                                                                     0x2408d0UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to psdm in the queues.  Chips: BB_A0 BB_B0 K2
38392 #define PSWRQ2_REG_MULD_ENTRY_TH                                                                     0x2408d4UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to muld in the queues.  Chips: BB_A0 BB_B0 K2
38393 #define PSWRQ2_REG_PTU_ENTRY_TH                                                                      0x2408d8UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to ptu in the queues.  Chips: BB_A0 BB_B0 K2
38394 #define PSWRQ2_REG_PTU_PCI_ATTR                                                                      0x2408dcUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
38395     #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_RELAXED                                                      (0x1<<0) // Relaxed oredering attribute for ptu.
38396     #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_RELAXED_SHIFT                                                0
38397     #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_NOSNOOP                                                      (0x1<<1) // Nosnoop attribute for ptu.
38398     #define PSWRQ2_REG_PTU_PCI_ATTR_PTU_NOSNOOP_SHIFT                                                1
38399 #define PSWRQ2_REG_M2P_ENTRY_TH                                                                      0x2408e0UL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to m2p in the queues.  Chips: BB_A0 BB_B0 K2
38400 #define PSWRQ2_REG_M2P_PCI_ATTR                                                                      0x2408e4UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
38401     #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_RELAXED                                                      (0x1<<0) // Relaxed oredering attribute for m2p.
38402     #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_RELAXED_SHIFT                                                0
38403     #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_NOSNOOP                                                      (0x1<<1) // Nosnoop attribute for m2p.
38404     #define PSWRQ2_REG_M2P_PCI_ATTR_M2P_NOSNOOP_SHIFT                                                1
38405 #define PSWRQ2_REG_MULD_PCI_ATTR                                                                     0x2408e8UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
38406     #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_RELAXED                                                    (0x1<<0) // Relaxed oredering attribute for muld.
38407     #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_RELAXED_SHIFT                                              0
38408     #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_NOSNOOP                                                    (0x1<<1) // Nosnoop attribute for muld.
38409     #define PSWRQ2_REG_MULD_PCI_ATTR_MULD_NOSNOOP_SHIFT                                              1
38410 #define PSWRQ2_REG_XYLD_ENTRY_TH                                                                     0x2408ecUL //Access:RW   DataWidth:0x3   This number indicates how many entries are guaranteed to xyld in the queues.  Chips: BB_A0 BB_B0 K2
38411 #define PSWRQ2_REG_XYLD_PCI_ATTR                                                                     0x2408f0UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
38412     #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_RELAXED                                                    (0x1<<0) // Relaxed oredering attribute for xyld.
38413     #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_RELAXED_SHIFT                                              0
38414     #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_NOSNOOP                                                    (0x1<<1) // Nosnoop attribute for xyld.
38415     #define PSWRQ2_REG_XYLD_PCI_ATTR_XYLD_NOSNOOP_SHIFT                                              1
38416 #define PSWRQ2_REG_ATC_MSDM_FLAGS                                                                    0x2408f4UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38417 #define PSWRQ2_REG_ATC_YSDM_FLAGS                                                                    0x2408f8UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38418 #define PSWRQ2_REG_ATC_PSDM_FLAGS                                                                    0x2408fcUL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38419 #define PSWRQ2_REG_ATC_MULD_FLAGS                                                                    0x240900UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38420 #define PSWRQ2_REG_ATC_XYLD_FLAGS                                                                    0x240904UL //Access:RW   DataWidth:0x4   ATC flags for that client as follows: b2-b0: atc flags; b3 - if set use this configuration (b2-b0) otherwise use the atc flags from the request.  Chips: BB_A0 BB_B0 K2
38421 #define PSWRQ2_REG_RMM_ENABLE                                                                        0x240908UL //Access:RW   DataWidth:0x1   Debug only. Writing this register from 0 to 1 enables the roundtrip measurement mechanism and resets the registers latest_rtt ,max_hold_rtt, min_hold_rtt, num_of_measurements.  Chips: BB_A0 BB_B0 K2
38422 #define PSWRQ2_REG_LATEST_RTT                                                                        0x24090cUL //Access:R    DataWidth:0x20  Debug only. Round trip measurement of latest request that was measured. Measured in clk_pci cycles (375 MHz).  Chips: BB_A0 BB_B0 K2
38423 #define PSWRQ2_REG_MAX_HOLD_RTT                                                                      0x240910UL //Access:R    DataWidth:0x20  Debug only. Maximal round trip measurement value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 MHz).  Chips: BB_A0 BB_B0 K2
38424 #define PSWRQ2_REG_MIN_HOLD_RTT                                                                      0x240914UL //Access:R    DataWidth:0x20  Debug only. Minimal round trip measurement value from the time rmm_enable register was written with '1'. Measured in clk_pci cycles (375 MHz).  Chips: BB_A0 BB_B0 K2
38425 #define PSWRQ2_REG_NUM_OF_MEASUREMENTS                                                               0x240918UL //Access:R    DataWidth:0x20  Debug only. Number of round trip measurements done from the time rmm_enable register was written with '1'. When the register reaches its maximal value of 0xffff_ffff it remains there.  Chips: BB_A0 BB_B0 K2
38426 #define PSWRQ2_REG_CLIENT_RTT                                                                        0x24091cUL //Access:RW   DataWidth:0x5   Debug only. Indicates the client for which PSWRQ measures roundtrip. 0x1f means 'all clients'. This register should be modified when rmm_enable is 0.  Chips: BB_A0 BB_B0 K2
38427 #define PSWRQ2_REG_VQ_RTT                                                                            0x240920UL //Access:RW   DataWidth:0x6   Debug only. Indicates the VQ for which PSWRQ measures roundtrip. 0x3f means 'all clients'. This register should be modified when rmm_enable is 0.  Chips: BB_A0 BB_B0 K2
38428 #define PSWRQ2_REG_L2P_SUPRESS_ERR                                                                   0x240924UL //Access:RW   DataWidth:0x2   In case this register is set, requests belongs to VFs/PF with logic address, will be silently dropped instead of causing close_the_gate_scenario.  Chips: BB_A0 BB_B0 K2
38429 #define PSWRQ2_REG_L2P_ERR_ADD_31_0                                                                  0x240928UL //Access:R    DataWidth:0x20  Address [31:0] of first request that triggered rq_l2p_vf_err  or rq_elt_addr interrupt.  Chips: BB_A0 BB_B0 K2
38430 #define PSWRQ2_REG_L2P_ERR_ADD_63_32                                                                 0x24092cUL //Access:R    DataWidth:0x20  Address [63:32] of first request that triggered rq_l2p_vf_err  or rq_elt_addr interrupt.  Chips: BB_A0 BB_B0 K2
38431 #define PSWRQ2_REG_L2P_ERR_DETAILS                                                                   0x240930UL //Access:R    DataWidth:0x1a  Details of first request that triggered rq_l2p_vf_err  or rq_elt_addr interrupt.  [12:0] - Length in bytes. [16:13] - PFID. [17] - VF_VALID. [25:18] - VFID.  Chips: BB_A0 BB_B0 K2
38432 #define PSWRQ2_REG_L2P_ERR_DETAILS2                                                                  0x240934UL //Access:R    DataWidth:0x1d  Details of first request that triggered rq_l2p_vf_err  or rq_elt_addr interrupt. [15:0] Request ID. [20:16] client ID. [21] - Error type - 0 - rq_l2p_vf_err; 1 - rq_elt_addr. [22] - w_nr - 0 - read; 1 - write.[27:23]VQID. [28] valid - indicates if there was a request not submitted due to error since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
38433 #define PSWRQ2_REG_L2P_ERR_DETAILS_CLR                                                               0x240938UL //Access:W    DataWidth:0x1   Writing to this register clears rq_l2p_err registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
38434 #define PSWRQ2_REG_SR_NUM_CFG                                                                        0x24093cUL //Access:RW   DataWidth:0x7   Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed.  Chips: BB_A0 BB_B0 K2
38435 #define PSWRQ2_REG_BLK_NUM_CFG                                                                       0x240940UL //Access:RW   DataWidth:0x9   Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed.  Chips: BB_A0 BB_B0 K2
38436 #define PSWRQ2_REG_MAX_BLKS_VQ0                                                                      0x240944UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38437 #define PSWRQ2_REG_MAX_BLKS_VQ1                                                                      0x240948UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38438 #define PSWRQ2_REG_MAX_BLKS_VQ2                                                                      0x24094cUL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38439 #define PSWRQ2_REG_MAX_BLKS_VQ3                                                                      0x240950UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38440 #define PSWRQ2_REG_MAX_BLKS_VQ4                                                                      0x240954UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38441 #define PSWRQ2_REG_MAX_BLKS_VQ5                                                                      0x240958UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38442 #define PSWRQ2_REG_MAX_BLKS_VQ6                                                                      0x24095cUL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38443 #define PSWRQ2_REG_MAX_BLKS_VQ7                                                                      0x240960UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38444 #define PSWRQ2_REG_MAX_BLKS_VQ8                                                                      0x240964UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38445 #define PSWRQ2_REG_MAX_BLKS_VQ9                                                                      0x240968UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38446 #define PSWRQ2_REG_MAX_BLKS_VQ10                                                                     0x24096cUL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38447 #define PSWRQ2_REG_MAX_BLKS_VQ11                                                                     0x240970UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38448 #define PSWRQ2_REG_MAX_BLKS_VQ12                                                                     0x240974UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38449 #define PSWRQ2_REG_MAX_BLKS_VQ13                                                                     0x240978UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38450 #define PSWRQ2_REG_MAX_BLKS_VQ14                                                                     0x24097cUL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38451 #define PSWRQ2_REG_MAX_BLKS_VQ15                                                                     0x240980UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38452 #define PSWRQ2_REG_MAX_BLKS_VQ16                                                                     0x240984UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38453 #define PSWRQ2_REG_MAX_BLKS_VQ17                                                                     0x240988UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38454 #define PSWRQ2_REG_MAX_BLKS_VQ18                                                                     0x24098cUL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38455 #define PSWRQ2_REG_MAX_BLKS_VQ19                                                                     0x240990UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38456 #define PSWRQ2_REG_MAX_BLKS_VQ20                                                                     0x240994UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38457 #define PSWRQ2_REG_MAX_BLKS_VQ21                                                                     0x240998UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38458 #define PSWRQ2_REG_MAX_BLKS_VQ22                                                                     0x24099cUL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38459 #define PSWRQ2_REG_MAX_BLKS_VQ23                                                                     0x2409a0UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38460 #define PSWRQ2_REG_MAX_BLKS_VQ24                                                                     0x2409a4UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38461 #define PSWRQ2_REG_MAX_BLKS_VQ25                                                                     0x2409a8UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38462 #define PSWRQ2_REG_MAX_BLKS_VQ26                                                                     0x2409acUL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38463 #define PSWRQ2_REG_MAX_BLKS_VQ27                                                                     0x2409b0UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38464 #define PSWRQ2_REG_MAX_BLKS_VQ28                                                                     0x2409b4UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38465 #define PSWRQ2_REG_MAX_BLKS_VQ29                                                                     0x2409b8UL //Access:RW   DataWidth:0x9   Not used. VQ29 is not used for read.  Chips: BB_A0 BB_B0 K2
38466 #define PSWRQ2_REG_MAX_BLKS_VQ30                                                                     0x2409bcUL //Access:RW   DataWidth:0x9   Not used. VQ30 is not used for read.  Chips: BB_A0 BB_B0 K2
38467 #define PSWRQ2_REG_MAX_BLKS_VQ31                                                                     0x2409c0UL //Access:RW   DataWidth:0x9   The maximum number of blocks in Tetris Buffer that can be allocated for this vq. Field and register name used to be rd. need to update reset value for phase3 - TBD.  Chips: BB_A0 BB_B0 K2
38468 #define PSWRQ2_REG_SR_CNT                                                                            0x2409c4UL //Access:R    DataWidth:0x7   Debug only: The SR counter - number of unused sub request ids. Field and register name used to be rd.  Chips: BB_A0 BB_B0 K2
38469 #define PSWRQ2_REG_SR_CNT_PER_VQ_0                                                                   0x2409c8UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38470 #define PSWRQ2_REG_SR_CNT_PER_VQ_1                                                                   0x2409ccUL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38471 #define PSWRQ2_REG_SR_CNT_PER_VQ_2                                                                   0x2409d0UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38472 #define PSWRQ2_REG_SR_CNT_PER_VQ_3                                                                   0x2409d4UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38473 #define PSWRQ2_REG_SR_CNT_PER_VQ_4                                                                   0x2409d8UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38474 #define PSWRQ2_REG_SR_CNT_PER_VQ_5                                                                   0x2409dcUL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38475 #define PSWRQ2_REG_SR_CNT_PER_VQ_6                                                                   0x2409e0UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38476 #define PSWRQ2_REG_SR_CNT_PER_VQ_7                                                                   0x2409e4UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38477 #define PSWRQ2_REG_SR_CNT_PER_VQ_8                                                                   0x2409e8UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38478 #define PSWRQ2_REG_SR_CNT_PER_VQ_9                                                                   0x2409ecUL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38479 #define PSWRQ2_REG_SR_CNT_PER_VQ_10                                                                  0x2409f0UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38480 #define PSWRQ2_REG_SR_CNT_PER_VQ_11                                                                  0x2409f4UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38481 #define PSWRQ2_REG_SR_CNT_PER_VQ_12                                                                  0x2409f8UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38482 #define PSWRQ2_REG_SR_CNT_PER_VQ_13                                                                  0x2409fcUL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38483 #define PSWRQ2_REG_SR_CNT_PER_VQ_14                                                                  0x240a00UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38484 #define PSWRQ2_REG_SR_CNT_PER_VQ_15                                                                  0x240a04UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38485 #define PSWRQ2_REG_SR_CNT_PER_VQ_16                                                                  0x240a08UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38486 #define PSWRQ2_REG_SR_CNT_PER_VQ_17                                                                  0x240a0cUL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38487 #define PSWRQ2_REG_SR_CNT_PER_VQ_18                                                                  0x240a10UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38488 #define PSWRQ2_REG_SR_CNT_PER_VQ_19                                                                  0x240a14UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38489 #define PSWRQ2_REG_SR_CNT_PER_VQ_20                                                                  0x240a18UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38490 #define PSWRQ2_REG_SR_CNT_PER_VQ_21                                                                  0x240a1cUL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38491 #define PSWRQ2_REG_SR_CNT_PER_VQ_22                                                                  0x240a20UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38492 #define PSWRQ2_REG_SR_CNT_PER_VQ_23                                                                  0x240a24UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38493 #define PSWRQ2_REG_SR_CNT_PER_VQ_24                                                                  0x240a28UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38494 #define PSWRQ2_REG_SR_CNT_PER_VQ_25                                                                  0x240a2cUL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38495 #define PSWRQ2_REG_SR_CNT_PER_VQ_26                                                                  0x240a30UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38496 #define PSWRQ2_REG_SR_CNT_PER_VQ_27                                                                  0x240a34UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38497 #define PSWRQ2_REG_SR_CNT_PER_VQ_28                                                                  0x240a38UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38498 #define PSWRQ2_REG_SR_CNT_PER_VQ_29                                                                  0x240a3cUL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38499 #define PSWRQ2_REG_SR_CNT_PER_VQ_30                                                                  0x240a40UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38500 #define PSWRQ2_REG_SR_CNT_PER_VQ_31                                                                  0x240a44UL //Access:R    DataWidth:0x7   Debug only: The SR counter per vq.  Chips: BB_A0 BB_B0 K2
38501 #define PSWRQ2_REG_BLK_CNT                                                                           0x240a48UL //Access:R    DataWidth:0x9   Debug only: The blocks counter - number of unused block ids. Field and register name used to be rd.  Chips: BB_A0 BB_B0 K2
38502 #define PSWRQ2_REG_BLK_CNT_PER_VQ_0                                                                  0x240a4cUL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38503 #define PSWRQ2_REG_BLK_CNT_PER_VQ_1                                                                  0x240a50UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38504 #define PSWRQ2_REG_BLK_CNT_PER_VQ_2                                                                  0x240a54UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38505 #define PSWRQ2_REG_BLK_CNT_PER_VQ_3                                                                  0x240a58UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38506 #define PSWRQ2_REG_BLK_CNT_PER_VQ_4                                                                  0x240a5cUL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38507 #define PSWRQ2_REG_BLK_CNT_PER_VQ_5                                                                  0x240a60UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38508 #define PSWRQ2_REG_BLK_CNT_PER_VQ_6                                                                  0x240a64UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38509 #define PSWRQ2_REG_BLK_CNT_PER_VQ_7                                                                  0x240a68UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38510 #define PSWRQ2_REG_BLK_CNT_PER_VQ_8                                                                  0x240a6cUL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38511 #define PSWRQ2_REG_BLK_CNT_PER_VQ_9                                                                  0x240a70UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38512 #define PSWRQ2_REG_BLK_CNT_PER_VQ_10                                                                 0x240a74UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38513 #define PSWRQ2_REG_BLK_CNT_PER_VQ_11                                                                 0x240a78UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38514 #define PSWRQ2_REG_BLK_CNT_PER_VQ_12                                                                 0x240a7cUL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38515 #define PSWRQ2_REG_BLK_CNT_PER_VQ_13                                                                 0x240a80UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38516 #define PSWRQ2_REG_BLK_CNT_PER_VQ_14                                                                 0x240a84UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38517 #define PSWRQ2_REG_BLK_CNT_PER_VQ_15                                                                 0x240a88UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38518 #define PSWRQ2_REG_BLK_CNT_PER_VQ_16                                                                 0x240a8cUL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38519 #define PSWRQ2_REG_BLK_CNT_PER_VQ_17                                                                 0x240a90UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38520 #define PSWRQ2_REG_BLK_CNT_PER_VQ_18                                                                 0x240a94UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38521 #define PSWRQ2_REG_BLK_CNT_PER_VQ_19                                                                 0x240a98UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38522 #define PSWRQ2_REG_BLK_CNT_PER_VQ_20                                                                 0x240a9cUL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38523 #define PSWRQ2_REG_BLK_CNT_PER_VQ_21                                                                 0x240aa0UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38524 #define PSWRQ2_REG_BLK_CNT_PER_VQ_22                                                                 0x240aa4UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38525 #define PSWRQ2_REG_BLK_CNT_PER_VQ_23                                                                 0x240aa8UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38526 #define PSWRQ2_REG_BLK_CNT_PER_VQ_24                                                                 0x240aacUL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38527 #define PSWRQ2_REG_BLK_CNT_PER_VQ_25                                                                 0x240ab0UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38528 #define PSWRQ2_REG_BLK_CNT_PER_VQ_26                                                                 0x240ab4UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38529 #define PSWRQ2_REG_BLK_CNT_PER_VQ_27                                                                 0x240ab8UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38530 #define PSWRQ2_REG_BLK_CNT_PER_VQ_28                                                                 0x240abcUL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38531 #define PSWRQ2_REG_BLK_CNT_PER_VQ_29                                                                 0x240ac0UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38532 #define PSWRQ2_REG_BLK_CNT_PER_VQ_30                                                                 0x240ac4UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38533 #define PSWRQ2_REG_BLK_CNT_PER_VQ_31                                                                 0x240ac8UL //Access:R    DataWidth:0x9   Debug only: The blocks counter per vq.  Chips: BB_A0 BB_B0 K2
38534 #define PSWRQ2_REG_CNT_BYTE_0                                                                        0x240accUL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38535 #define PSWRQ2_REG_CNT_BYTE_1                                                                        0x240ad0UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38536 #define PSWRQ2_REG_CNT_BYTE_2                                                                        0x240ad4UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38537 #define PSWRQ2_REG_CNT_BYTE_3                                                                        0x240ad8UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38538 #define PSWRQ2_REG_CNT_BYTE_4                                                                        0x240adcUL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38539 #define PSWRQ2_REG_CNT_BYTE_5                                                                        0x240ae0UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38540 #define PSWRQ2_REG_CNT_BYTE_6                                                                        0x240ae4UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38541 #define PSWRQ2_REG_CNT_BYTE_7                                                                        0x240ae8UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38542 #define PSWRQ2_REG_CNT_BYTE_8                                                                        0x240aecUL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38543 #define PSWRQ2_REG_CNT_BYTE_9                                                                        0x240af0UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38544 #define PSWRQ2_REG_CNT_BYTE_10                                                                       0x240af4UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38545 #define PSWRQ2_REG_CNT_BYTE_11                                                                       0x240af8UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38546 #define PSWRQ2_REG_CNT_BYTE_12                                                                       0x240afcUL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38547 #define PSWRQ2_REG_CNT_BYTE_13                                                                       0x240b00UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38548 #define PSWRQ2_REG_CNT_BYTE_14                                                                       0x240b04UL //Access:R    DataWidth:0xe   Debug only: byte counter per wr client. Describes the number of bytes that are stored in the pswwr client fifo for the last request of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38549 #define PSWRQ2_REG_CNT_EOP_0                                                                         0x240b08UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38550 #define PSWRQ2_REG_CNT_EOP_1                                                                         0x240b0cUL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38551 #define PSWRQ2_REG_CNT_EOP_2                                                                         0x240b10UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38552 #define PSWRQ2_REG_CNT_EOP_3                                                                         0x240b14UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38553 #define PSWRQ2_REG_CNT_EOP_4                                                                         0x240b18UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38554 #define PSWRQ2_REG_CNT_EOP_5                                                                         0x240b1cUL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38555 #define PSWRQ2_REG_CNT_EOP_6                                                                         0x240b20UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38556 #define PSWRQ2_REG_CNT_EOP_7                                                                         0x240b24UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38557 #define PSWRQ2_REG_CNT_EOP_8                                                                         0x240b28UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38558 #define PSWRQ2_REG_CNT_EOP_9                                                                         0x240b2cUL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38559 #define PSWRQ2_REG_CNT_EOP_10                                                                        0x240b30UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38560 #define PSWRQ2_REG_CNT_EOP_11                                                                        0x240b34UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38561 #define PSWRQ2_REG_CNT_EOP_12                                                                        0x240b38UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38562 #define PSWRQ2_REG_CNT_EOP_13                                                                        0x240b3cUL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38563 #define PSWRQ2_REG_CNT_EOP_14                                                                        0x240b40UL //Access:R    DataWidth:0x8   Debug only: eop counter per wr client. Describes the number of packets that are stored in the pswwr client fifo of the client. Wr_client decoding: TSDM 0; MSDM 1; USDM 2; XSDM 3; YSDM 4; PSDM 5; QM 6; TM 7; SRC 8; DMAE 9; PRM 10; HC 11; CDUWR 12; DBG 13; M2P 14.  Chips: BB_A0 BB_B0 K2
38564 #define PSWRQ2_REG_MAX_SRS_VQ0                                                                       0x240b44UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38565 #define PSWRQ2_REG_MAX_SRS_VQ1                                                                       0x240b48UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38566 #define PSWRQ2_REG_MAX_SRS_VQ2                                                                       0x240b4cUL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38567 #define PSWRQ2_REG_MAX_SRS_VQ3                                                                       0x240b50UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38568 #define PSWRQ2_REG_MAX_SRS_VQ4                                                                       0x240b54UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38569 #define PSWRQ2_REG_MAX_SRS_VQ5                                                                       0x240b58UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38570 #define PSWRQ2_REG_MAX_SRS_VQ6                                                                       0x240b5cUL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38571 #define PSWRQ2_REG_MAX_SRS_VQ7                                                                       0x240b60UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38572 #define PSWRQ2_REG_MAX_SRS_VQ8                                                                       0x240b64UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38573 #define PSWRQ2_REG_MAX_SRS_VQ9                                                                       0x240b68UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38574 #define PSWRQ2_REG_MAX_SRS_VQ10                                                                      0x240b6cUL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38575 #define PSWRQ2_REG_MAX_SRS_VQ11                                                                      0x240b70UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38576 #define PSWRQ2_REG_MAX_SRS_VQ12                                                                      0x240b74UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38577 #define PSWRQ2_REG_MAX_SRS_VQ13                                                                      0x240b78UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38578 #define PSWRQ2_REG_MAX_SRS_VQ14                                                                      0x240b7cUL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38579 #define PSWRQ2_REG_MAX_SRS_VQ15                                                                      0x240b80UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38580 #define PSWRQ2_REG_MAX_SRS_VQ16                                                                      0x240b84UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38581 #define PSWRQ2_REG_MAX_SRS_VQ17                                                                      0x240b88UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38582 #define PSWRQ2_REG_MAX_SRS_VQ18                                                                      0x240b8cUL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38583 #define PSWRQ2_REG_MAX_SRS_VQ19                                                                      0x240b90UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38584 #define PSWRQ2_REG_MAX_SRS_VQ20                                                                      0x240b94UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38585 #define PSWRQ2_REG_MAX_SRS_VQ21                                                                      0x240b98UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38586 #define PSWRQ2_REG_MAX_SRS_VQ22                                                                      0x240b9cUL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38587 #define PSWRQ2_REG_MAX_SRS_VQ23                                                                      0x240ba0UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38588 #define PSWRQ2_REG_MAX_SRS_VQ24                                                                      0x240ba4UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38589 #define PSWRQ2_REG_MAX_SRS_VQ25                                                                      0x240ba8UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38590 #define PSWRQ2_REG_MAX_SRS_VQ26                                                                      0x240bacUL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38591 #define PSWRQ2_REG_MAX_SRS_VQ27                                                                      0x240bb0UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38592 #define PSWRQ2_REG_MAX_SRS_VQ28                                                                      0x240bb4UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38593 #define PSWRQ2_REG_MAX_SRS_VQ29                                                                      0x240bb8UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38594 #define PSWRQ2_REG_MAX_SRS_VQ30                                                                      0x240bbcUL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38595 #define PSWRQ2_REG_MAX_SRS_VQ31                                                                      0x240bc0UL //Access:RW   DataWidth:0x7   The maximum number of sub-requests that can be allocated for this vq.  Chips: BB_A0 BB_B0 K2
38596 #define PSWRQ2_REG_REQIF_DEL_DELAY                                                                   0x240bc4UL //Access:RW   DataWidth:0x3   Number of delay cycles on the reqif del indication.  Chips: BB_A0 BB_B0 K2
38597 #define PSWRQ2_REG_L2P_CLOSE_GATE_STS                                                                0x240bc8UL //Access:RW   DataWidth:0x1   L2P error close the gate status register.  Chips: BB_A0 BB_B0 K2
38598 #define PSWRQ2_REG_MISC_CLOSE_GATE_STS                                                               0x240bccUL //Access:R    DataWidth:0x1   MISC close the gate status register. 1 indicates the gates are closed.  Chips: BB_A0 BB_B0 K2
38599 #define PSWRQ2_REG_MISC_STALL_MEM_STS                                                                0x240bd0UL //Access:R    DataWidth:0x1   MISC stall mem status register. 1 indicates stall mem is active.  Chips: BB_A0 BB_B0 K2
38600 #define PSWRQ2_REG_GARB_STRICT_PRIORITY_FOR_READS                                                    0x240bd4UL //Access:RW   DataWidth:0x1   GARB config: 1 indicates read SRs have strict priority over write SRs in RW arbiter.  Chips: BB_A0 BB_B0 K2
38601 #define PSWRQ2_REG_GARB_NEGATIVE_BWC_MODE                                                            0x240bd8UL //Access:RW   DataWidth:0x1   GARB config: 1 indicates BWCs can become negative. Clients with negative BWCs are not chosen. Default value: 1.  Chips: BB_A0 BB_B0 K2
38602 #define PSWRQ2_REG_GARB_GNT_ABOVE_LIMIT_ONLY_MODE                                                    0x240bdcUL //Access:RW   DataWidth:0x1   GARB config: 1 indicates that only clients with BWC greater or equal to Li are chosen. 0 indicates that clients with BWC greater or equal to 0 can be chosen if no BWC is greater or equal to Li. Default value: 0. This is a chicken bit in case there are problems/bugs when choosing clients with BWC less than Li.  Chips: BB_A0 BB_B0 K2
38603 #define PSWRQ2_REG_GARB_VQ_2_STRICT_LSB                                                              0x240be0UL //Access:RW   DataWidth:0x20  GARB config: mapping of VQ to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters);  1 - the VQ has strict priority; VQ32 = TREQ; VQ33 = ICPL; NOTE: the VQ-s associated with strict priority slot should match the configuration in garb_strict0_2_vq or garb_strict1_2_vq;.  Chips: BB_A0 BB_B0 K2
38604 #define PSWRQ2_REG_GARB_VQ_2_STRICT_MSB                                                              0x240be4UL //Access:RW   DataWidth:0x2   GARB config: mapping of VQ to strict priority: 0 - the VQ is not associated with any strict priority (i.e. the VQ is associated wth the BW counters);  1 - the VQ has strict priority; VQ32 = TREQ; VQ33 = ICPL; NOTE: the VQ-s associated with strict priority slot should match the configuration in garb_strict0_2_vq or garb_strict1_2_vq;.  Chips: BB_A0 BB_B0 K2
38605 #define PSWRQ2_REG_GARB_STRICT0_2_VQ_0                                                               0x240be8UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38606 #define PSWRQ2_REG_GARB_STRICT0_2_VQ_1                                                               0x240becUL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38607 #define PSWRQ2_REG_GARB_STRICT0_2_VQ_2                                                               0x240bf0UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38608 #define PSWRQ2_REG_GARB_STRICT0_2_VQ_3                                                               0x240bf4UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38609 #define PSWRQ2_REG_GARB_STRICT0_2_VQ_4                                                               0x240bf8UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38610 #define PSWRQ2_REG_GARB_STRICT0_2_VQ_5                                                               0x240bfcUL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38611 #define PSWRQ2_REG_GARB_STRICT0_2_VQ_6                                                               0x240c00UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38612 #define PSWRQ2_REG_GARB_STRICT0_2_VQ_7                                                               0x240c04UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 0 (high priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 0 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38613 #define PSWRQ2_REG_GARB_STRICT1_2_VQ_0                                                               0x240c08UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38614 #define PSWRQ2_REG_GARB_STRICT1_2_VQ_1                                                               0x240c0cUL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38615 #define PSWRQ2_REG_GARB_STRICT1_2_VQ_2                                                               0x240c10UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38616 #define PSWRQ2_REG_GARB_STRICT1_2_VQ_3                                                               0x240c14UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38617 #define PSWRQ2_REG_GARB_STRICT1_2_VQ_4                                                               0x240c18UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38618 #define PSWRQ2_REG_GARB_STRICT1_2_VQ_5                                                               0x240c1cUL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38619 #define PSWRQ2_REG_GARB_STRICT1_2_VQ_6                                                               0x240c20UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38620 #define PSWRQ2_REG_GARB_STRICT1_2_VQ_7                                                               0x240c24UL //Access:RW   DataWidth:0x7   GARB config: mapping of strict priority 1 (low priority) to VQ: bits 5:0 - the VQ id; bit6 - validates the VQ association; VQ32 = TREQ; VQ33 = ICPL; NOTE: (a) the VQ-s associated with strict priority 1 should match the values in garb_vq_2_strict; (b) VQ can be associated with up to single priority (i.e. cannot be associated with both priority0 and priority1).  Chips: BB_A0 BB_B0 K2
38621 #define PSWRQ2_REG_CREDIT_WR_STS                                                                     0x240c28UL //Access:R    DataWidth:0x1   The status of the PSWRQ-PGLUE request interface write credit; 0 - no more credit for wr SR-s (i.e. write SR-s cannot be sent to the PGLUE); 1 - credit is greater than 0 for wr SR-s (i.e. more write SR-s can be sent to the PGLUE).  Chips: BB_A0 BB_B0 K2
38622 #define PSWRQ2_REG_CREDIT_RD_STS                                                                     0x240c2cUL //Access:R    DataWidth:0x1   The status of the PSWRQ-PGLUE request interface read credit; 0 - no more credit for rd SR-s (i.e. read SR-s cannot be sent to the PGLUE); 1 - credit is greater than 0 for rd SR-s (i.e. more read SR-s can be sent to the PGLUE).  Chips: BB_A0 BB_B0 K2
38623 #define PSWRQ2_REG_WAIT_FOR_EOP                                                                      0x240c30UL //Access:RW   DataWidth:0xf   Per client store_and_forward configuration. When set it will only enable to submit a write request when eop arrived. This can be a workaround for possible bugs in the byte counters. Id-s are based on wr client id-s (taken from pswrq_funcs.v).  Chips: BB_A0 BB_B0 K2
38624 #define PSWRQ2_REG_ADD2Q_2_DELHOQ0_DELAY                                                             0x240c34UL //Access:RW   DataWidth:0x3   LSI purpose: the number of [cycles-1] between qc_cmg_add_2_q (indication that new request is written into hoq0) and cmg_qc_del_head (delete request sent by the cmg towards hoq0). This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between qc_cmg_add_2_q and cmg_qc_del_head.  Chips: BB_A0 BB_B0 K2
38625 #define PSWRQ2_REG_DELHOQ0_2_DELHOQ0_DELAY_0                                                         0x240c38UL //Access:RW   DataWidth:0x4   LSI purpose: the minimum allowed number of [cycles-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_head for the same VQ. This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between 2 adjacent requests.  Chips: BB_A0 BB_B0 K2
38626 #define PSWRQ2_REG_DELHOQ0_2_DELHOQ0_DELAY_1                                                         0x240c3cUL //Access:RW   DataWidth:0x4   LSI purpose: the minimum allowed number of [cycles-1] between cmg_qc_del_head (delete request sent by the cmg towards hoq0) and the next cmg_qc_del_head for different VQ. This register should be touched unless there is non-expected HW limitation within the QC. value of N means that there are N dead cycles between 2 adjacent requests.  Chips: BB_A0 BB_B0 K2
38627 #define PSWRQ2_REG_PDR_CNT                                                                           0x240c40UL //Access:R    DataWidth:0xe   For debug and Idle-check use. The value of the PDR counter.  Chips: BB_A0 BB_B0 K2
38628 #define PSWRQ2_REG_CHECK_RESOURCES_FOR_THE_ENTIRE_REQ                                                0x240c44UL //Access:RW   DataWidth:0x6   Will be used for OOO clients deadlock prevention. indicating if to submit the first SR of a request only when there are enough SRIDs and blocks for the entire request. bit0: TSDM; bit1: MSDM; bit2: USDM; bit3: XSDM; bit4: YSDM; bit5: PSDM.  Chips: BB_A0 BB_B0 K2
38629 #define PSWRQ2_REG_RW_ORDERING_DISABLE_WR_THR                                                        0x240c48UL //Access:RW   DataWidth:0x6   LSI purpose: the threshold for the max number of pending wr requests sent to the PGLUE (i.e. sent to the PGLUE and did not receive write done for them from the PGLUE). Upon reaching the threshold no more wr SR-s will be sent by the PSWRQ to the PGLUE until receiving write done for the previous requests.  Chips: BB_A0 BB_B0 K2
38630 #define PSWRQ2_REG_ECO_RESERVED                                                                      0x240c4cUL //Access:RW   DataWidth:0x6   Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
38631 #define PSWRQ2_REG_L2P_VALIDATE_VFID                                                                 0x240c50UL //Access:RW   DataWidth:0x1   Enables VFID validate check  Chips: BB_A0 BB_B0 K2
38632 #define PSWRQ2_REG_STEERING_TAG_TABLE                                                                0x241000UL //Access:RW   DataWidth:0x8   Steering Tag Table. Used for TPH.  Chips: BB_A0 BB_B0 K2
38633 #define PSWRQ2_REG_STEERING_TAG_TABLE_SIZE                                                           368
38634 #define PSWRQ2_REG_ILT_MEMORY                                                                        0x260000UL //Access:WB   DataWidth:0x35  Internal lookup table for logical to physical address translation. Re-instantiated in E4 due to size increase.  Chips: BB_A0 BB_B0 K2
38635 #define PSWRQ2_REG_ILT_MEMORY_SIZE                                                                   22000
38636 #define PSWRQ_REG_DBG_OUT_DATA                                                                       0x280000UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
38637 #define PSWRQ_REG_DBG_OUT_DATA_SIZE                                                                  8
38638 #define PSWRQ_REG_DBG_SELECT                                                                         0x280020UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
38639 #define PSWRQ_REG_DBG_DWORD_ENABLE                                                                   0x280024UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
38640 #define PSWRQ_REG_DBG_SHIFT                                                                          0x280028UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
38641 #define PSWRQ_REG_DBG_FORCE_VALID                                                                    0x28002cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
38642 #define PSWRQ_REG_DBG_FORCE_FRAME                                                                    0x280030UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
38643 #define PSWRQ_REG_DBG_OUT_VALID                                                                      0x280034UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
38644 #define PSWRQ_REG_DBG_OUT_FRAME                                                                      0x280038UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
38645 #define PSWRQ_REG_ECO_RESERVED                                                                       0x280060UL //Access:RW   DataWidth:0x6   Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
38646 #define PSWRQ_REG_INT_STS                                                                            0x280180UL //Access:R    DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38647     #define PSWRQ_REG_INT_STS_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
38648     #define PSWRQ_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                    0
38649     #define PSWRQ_REG_INT_STS_PBF_FIFO_OVERFLOW                                                      (0x1<<1) // Overflow in pbf request input fifo.
38650     #define PSWRQ_REG_INT_STS_PBF_FIFO_OVERFLOW_SHIFT                                                1
38651     #define PSWRQ_REG_INT_STS_SRC_FIFO_OVERFLOW                                                      (0x1<<2) // Overflow in src request input fifo.
38652     #define PSWRQ_REG_INT_STS_SRC_FIFO_OVERFLOW_SHIFT                                                2
38653     #define PSWRQ_REG_INT_STS_QM_FIFO_OVERFLOW                                                       (0x1<<3) // Overflow in qm request input fifo.
38654     #define PSWRQ_REG_INT_STS_QM_FIFO_OVERFLOW_SHIFT                                                 3
38655     #define PSWRQ_REG_INT_STS_TM_FIFO_OVERFLOW                                                       (0x1<<4) // Overflow in tm request fifo.
38656     #define PSWRQ_REG_INT_STS_TM_FIFO_OVERFLOW_SHIFT                                                 4
38657     #define PSWRQ_REG_INT_STS_USDM_FIFO_OVERFLOW                                                     (0x1<<5) // Overflow in usdm request input fifo.
38658     #define PSWRQ_REG_INT_STS_USDM_FIFO_OVERFLOW_SHIFT                                               5
38659     #define PSWRQ_REG_INT_STS_M2P_FIFO_OVERFLOW                                                      (0x1<<6) // Overflow in m2p request input fifo.
38660     #define PSWRQ_REG_INT_STS_M2P_FIFO_OVERFLOW_SHIFT                                                6
38661     #define PSWRQ_REG_INT_STS_XSDM_FIFO_OVERFLOW                                                     (0x1<<7) // Overflow in xsdm request input fifo.
38662     #define PSWRQ_REG_INT_STS_XSDM_FIFO_OVERFLOW_SHIFT                                               7
38663     #define PSWRQ_REG_INT_STS_TSDM_FIFO_OVERFLOW                                                     (0x1<<8) // Overflow in tsdm request input fifo.
38664     #define PSWRQ_REG_INT_STS_TSDM_FIFO_OVERFLOW_SHIFT                                               8
38665     #define PSWRQ_REG_INT_STS_PTU_FIFO_OVERFLOW                                                      (0x1<<9) // Overflow in ptu request input fifo.
38666     #define PSWRQ_REG_INT_STS_PTU_FIFO_OVERFLOW_SHIFT                                                9
38667     #define PSWRQ_REG_INT_STS_CDUWR_FIFO_OVERFLOW                                                    (0x1<<10) // Overflow in cduwr request input fifo.
38668     #define PSWRQ_REG_INT_STS_CDUWR_FIFO_OVERFLOW_SHIFT                                              10
38669     #define PSWRQ_REG_INT_STS_CDURD_FIFO_OVERFLOW                                                    (0x1<<11) // Overflow in cdurd request input fifo.
38670     #define PSWRQ_REG_INT_STS_CDURD_FIFO_OVERFLOW_SHIFT                                              11
38671     #define PSWRQ_REG_INT_STS_DMAE_FIFO_OVERFLOW                                                     (0x1<<12) // Overflow in dmae request input fifo.
38672     #define PSWRQ_REG_INT_STS_DMAE_FIFO_OVERFLOW_SHIFT                                               12
38673     #define PSWRQ_REG_INT_STS_HC_FIFO_OVERFLOW                                                       (0x1<<13) // Overflow in hc request input fifo.
38674     #define PSWRQ_REG_INT_STS_HC_FIFO_OVERFLOW_SHIFT                                                 13
38675     #define PSWRQ_REG_INT_STS_DBG_FIFO_OVERFLOW                                                      (0x1<<14) // Overflow in dbg request input fifo.
38676     #define PSWRQ_REG_INT_STS_DBG_FIFO_OVERFLOW_SHIFT                                                14
38677     #define PSWRQ_REG_INT_STS_MSDM_FIFO_OVERFLOW                                                     (0x1<<15) // Overflow in msdm request input fifo.
38678     #define PSWRQ_REG_INT_STS_MSDM_FIFO_OVERFLOW_SHIFT                                               15
38679     #define PSWRQ_REG_INT_STS_YSDM_FIFO_OVERFLOW                                                     (0x1<<16) // Overflow in ysdm request input fifo.
38680     #define PSWRQ_REG_INT_STS_YSDM_FIFO_OVERFLOW_SHIFT                                               16
38681     #define PSWRQ_REG_INT_STS_PSDM_FIFO_OVERFLOW                                                     (0x1<<17) // Overflow in psdm request input fifo.
38682     #define PSWRQ_REG_INT_STS_PSDM_FIFO_OVERFLOW_SHIFT                                               17
38683     #define PSWRQ_REG_INT_STS_PRM_FIFO_OVERFLOW                                                      (0x1<<18) // Overflow in prm request input fifo.
38684     #define PSWRQ_REG_INT_STS_PRM_FIFO_OVERFLOW_SHIFT                                                18
38685     #define PSWRQ_REG_INT_STS_MULD_FIFO_OVERFLOW                                                     (0x1<<19) // Overflow in muld request input fifo.
38686     #define PSWRQ_REG_INT_STS_MULD_FIFO_OVERFLOW_SHIFT                                               19
38687     #define PSWRQ_REG_INT_STS_XYLD_FIFO_OVERFLOW                                                     (0x1<<20) // Overflow in muld request input fifo.
38688     #define PSWRQ_REG_INT_STS_XYLD_FIFO_OVERFLOW_SHIFT                                               20
38689 #define PSWRQ_REG_INT_MASK                                                                           0x280184UL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38690     #define PSWRQ_REG_INT_MASK_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.ADDRESS_ERROR .
38691     #define PSWRQ_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                   0
38692     #define PSWRQ_REG_INT_MASK_PBF_FIFO_OVERFLOW                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PBF_FIFO_OVERFLOW .
38693     #define PSWRQ_REG_INT_MASK_PBF_FIFO_OVERFLOW_SHIFT                                               1
38694     #define PSWRQ_REG_INT_MASK_SRC_FIFO_OVERFLOW                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.SRC_FIFO_OVERFLOW .
38695     #define PSWRQ_REG_INT_MASK_SRC_FIFO_OVERFLOW_SHIFT                                               2
38696     #define PSWRQ_REG_INT_MASK_QM_FIFO_OVERFLOW                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.QM_FIFO_OVERFLOW .
38697     #define PSWRQ_REG_INT_MASK_QM_FIFO_OVERFLOW_SHIFT                                                3
38698     #define PSWRQ_REG_INT_MASK_TM_FIFO_OVERFLOW                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.TM_FIFO_OVERFLOW .
38699     #define PSWRQ_REG_INT_MASK_TM_FIFO_OVERFLOW_SHIFT                                                4
38700     #define PSWRQ_REG_INT_MASK_USDM_FIFO_OVERFLOW                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.USDM_FIFO_OVERFLOW .
38701     #define PSWRQ_REG_INT_MASK_USDM_FIFO_OVERFLOW_SHIFT                                              5
38702     #define PSWRQ_REG_INT_MASK_M2P_FIFO_OVERFLOW                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.M2P_FIFO_OVERFLOW .
38703     #define PSWRQ_REG_INT_MASK_M2P_FIFO_OVERFLOW_SHIFT                                               6
38704     #define PSWRQ_REG_INT_MASK_XSDM_FIFO_OVERFLOW                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.XSDM_FIFO_OVERFLOW .
38705     #define PSWRQ_REG_INT_MASK_XSDM_FIFO_OVERFLOW_SHIFT                                              7
38706     #define PSWRQ_REG_INT_MASK_TSDM_FIFO_OVERFLOW                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.TSDM_FIFO_OVERFLOW .
38707     #define PSWRQ_REG_INT_MASK_TSDM_FIFO_OVERFLOW_SHIFT                                              8
38708     #define PSWRQ_REG_INT_MASK_PTU_FIFO_OVERFLOW                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PTU_FIFO_OVERFLOW .
38709     #define PSWRQ_REG_INT_MASK_PTU_FIFO_OVERFLOW_SHIFT                                               9
38710     #define PSWRQ_REG_INT_MASK_CDUWR_FIFO_OVERFLOW                                                   (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.CDUWR_FIFO_OVERFLOW .
38711     #define PSWRQ_REG_INT_MASK_CDUWR_FIFO_OVERFLOW_SHIFT                                             10
38712     #define PSWRQ_REG_INT_MASK_CDURD_FIFO_OVERFLOW                                                   (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.CDURD_FIFO_OVERFLOW .
38713     #define PSWRQ_REG_INT_MASK_CDURD_FIFO_OVERFLOW_SHIFT                                             11
38714     #define PSWRQ_REG_INT_MASK_DMAE_FIFO_OVERFLOW                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.DMAE_FIFO_OVERFLOW .
38715     #define PSWRQ_REG_INT_MASK_DMAE_FIFO_OVERFLOW_SHIFT                                              12
38716     #define PSWRQ_REG_INT_MASK_HC_FIFO_OVERFLOW                                                      (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.HC_FIFO_OVERFLOW .
38717     #define PSWRQ_REG_INT_MASK_HC_FIFO_OVERFLOW_SHIFT                                                13
38718     #define PSWRQ_REG_INT_MASK_DBG_FIFO_OVERFLOW                                                     (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.DBG_FIFO_OVERFLOW .
38719     #define PSWRQ_REG_INT_MASK_DBG_FIFO_OVERFLOW_SHIFT                                               14
38720     #define PSWRQ_REG_INT_MASK_MSDM_FIFO_OVERFLOW                                                    (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.MSDM_FIFO_OVERFLOW .
38721     #define PSWRQ_REG_INT_MASK_MSDM_FIFO_OVERFLOW_SHIFT                                              15
38722     #define PSWRQ_REG_INT_MASK_YSDM_FIFO_OVERFLOW                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.YSDM_FIFO_OVERFLOW .
38723     #define PSWRQ_REG_INT_MASK_YSDM_FIFO_OVERFLOW_SHIFT                                              16
38724     #define PSWRQ_REG_INT_MASK_PSDM_FIFO_OVERFLOW                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PSDM_FIFO_OVERFLOW .
38725     #define PSWRQ_REG_INT_MASK_PSDM_FIFO_OVERFLOW_SHIFT                                              17
38726     #define PSWRQ_REG_INT_MASK_PRM_FIFO_OVERFLOW                                                     (0x1<<18) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.PRM_FIFO_OVERFLOW .
38727     #define PSWRQ_REG_INT_MASK_PRM_FIFO_OVERFLOW_SHIFT                                               18
38728     #define PSWRQ_REG_INT_MASK_MULD_FIFO_OVERFLOW                                                    (0x1<<19) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.MULD_FIFO_OVERFLOW .
38729     #define PSWRQ_REG_INT_MASK_MULD_FIFO_OVERFLOW_SHIFT                                              19
38730     #define PSWRQ_REG_INT_MASK_XYLD_FIFO_OVERFLOW                                                    (0x1<<20) // This bit masks, when set, the Interrupt bit: PSWRQ_REG_INT_STS.XYLD_FIFO_OVERFLOW .
38731     #define PSWRQ_REG_INT_MASK_XYLD_FIFO_OVERFLOW_SHIFT                                              20
38732 #define PSWRQ_REG_INT_STS_WR                                                                         0x280188UL //Access:WR   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38733     #define PSWRQ_REG_INT_STS_WR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
38734     #define PSWRQ_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                 0
38735     #define PSWRQ_REG_INT_STS_WR_PBF_FIFO_OVERFLOW                                                   (0x1<<1) // Overflow in pbf request input fifo.
38736     #define PSWRQ_REG_INT_STS_WR_PBF_FIFO_OVERFLOW_SHIFT                                             1
38737     #define PSWRQ_REG_INT_STS_WR_SRC_FIFO_OVERFLOW                                                   (0x1<<2) // Overflow in src request input fifo.
38738     #define PSWRQ_REG_INT_STS_WR_SRC_FIFO_OVERFLOW_SHIFT                                             2
38739     #define PSWRQ_REG_INT_STS_WR_QM_FIFO_OVERFLOW                                                    (0x1<<3) // Overflow in qm request input fifo.
38740     #define PSWRQ_REG_INT_STS_WR_QM_FIFO_OVERFLOW_SHIFT                                              3
38741     #define PSWRQ_REG_INT_STS_WR_TM_FIFO_OVERFLOW                                                    (0x1<<4) // Overflow in tm request fifo.
38742     #define PSWRQ_REG_INT_STS_WR_TM_FIFO_OVERFLOW_SHIFT                                              4
38743     #define PSWRQ_REG_INT_STS_WR_USDM_FIFO_OVERFLOW                                                  (0x1<<5) // Overflow in usdm request input fifo.
38744     #define PSWRQ_REG_INT_STS_WR_USDM_FIFO_OVERFLOW_SHIFT                                            5
38745     #define PSWRQ_REG_INT_STS_WR_M2P_FIFO_OVERFLOW                                                   (0x1<<6) // Overflow in m2p request input fifo.
38746     #define PSWRQ_REG_INT_STS_WR_M2P_FIFO_OVERFLOW_SHIFT                                             6
38747     #define PSWRQ_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW                                                  (0x1<<7) // Overflow in xsdm request input fifo.
38748     #define PSWRQ_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW_SHIFT                                            7
38749     #define PSWRQ_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW                                                  (0x1<<8) // Overflow in tsdm request input fifo.
38750     #define PSWRQ_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW_SHIFT                                            8
38751     #define PSWRQ_REG_INT_STS_WR_PTU_FIFO_OVERFLOW                                                   (0x1<<9) // Overflow in ptu request input fifo.
38752     #define PSWRQ_REG_INT_STS_WR_PTU_FIFO_OVERFLOW_SHIFT                                             9
38753     #define PSWRQ_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW                                                 (0x1<<10) // Overflow in cduwr request input fifo.
38754     #define PSWRQ_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW_SHIFT                                           10
38755     #define PSWRQ_REG_INT_STS_WR_CDURD_FIFO_OVERFLOW                                                 (0x1<<11) // Overflow in cdurd request input fifo.
38756     #define PSWRQ_REG_INT_STS_WR_CDURD_FIFO_OVERFLOW_SHIFT                                           11
38757     #define PSWRQ_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW                                                  (0x1<<12) // Overflow in dmae request input fifo.
38758     #define PSWRQ_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW_SHIFT                                            12
38759     #define PSWRQ_REG_INT_STS_WR_HC_FIFO_OVERFLOW                                                    (0x1<<13) // Overflow in hc request input fifo.
38760     #define PSWRQ_REG_INT_STS_WR_HC_FIFO_OVERFLOW_SHIFT                                              13
38761     #define PSWRQ_REG_INT_STS_WR_DBG_FIFO_OVERFLOW                                                   (0x1<<14) // Overflow in dbg request input fifo.
38762     #define PSWRQ_REG_INT_STS_WR_DBG_FIFO_OVERFLOW_SHIFT                                             14
38763     #define PSWRQ_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW                                                  (0x1<<15) // Overflow in msdm request input fifo.
38764     #define PSWRQ_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW_SHIFT                                            15
38765     #define PSWRQ_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW                                                  (0x1<<16) // Overflow in ysdm request input fifo.
38766     #define PSWRQ_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW_SHIFT                                            16
38767     #define PSWRQ_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW                                                  (0x1<<17) // Overflow in psdm request input fifo.
38768     #define PSWRQ_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW_SHIFT                                            17
38769     #define PSWRQ_REG_INT_STS_WR_PRM_FIFO_OVERFLOW                                                   (0x1<<18) // Overflow in prm request input fifo.
38770     #define PSWRQ_REG_INT_STS_WR_PRM_FIFO_OVERFLOW_SHIFT                                             18
38771     #define PSWRQ_REG_INT_STS_WR_MULD_FIFO_OVERFLOW                                                  (0x1<<19) // Overflow in muld request input fifo.
38772     #define PSWRQ_REG_INT_STS_WR_MULD_FIFO_OVERFLOW_SHIFT                                            19
38773     #define PSWRQ_REG_INT_STS_WR_XYLD_FIFO_OVERFLOW                                                  (0x1<<20) // Overflow in muld request input fifo.
38774     #define PSWRQ_REG_INT_STS_WR_XYLD_FIFO_OVERFLOW_SHIFT                                            20
38775 #define PSWRQ_REG_INT_STS_CLR                                                                        0x28018cUL //Access:RC   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38776     #define PSWRQ_REG_INT_STS_CLR_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
38777     #define PSWRQ_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                0
38778     #define PSWRQ_REG_INT_STS_CLR_PBF_FIFO_OVERFLOW                                                  (0x1<<1) // Overflow in pbf request input fifo.
38779     #define PSWRQ_REG_INT_STS_CLR_PBF_FIFO_OVERFLOW_SHIFT                                            1
38780     #define PSWRQ_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW                                                  (0x1<<2) // Overflow in src request input fifo.
38781     #define PSWRQ_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW_SHIFT                                            2
38782     #define PSWRQ_REG_INT_STS_CLR_QM_FIFO_OVERFLOW                                                   (0x1<<3) // Overflow in qm request input fifo.
38783     #define PSWRQ_REG_INT_STS_CLR_QM_FIFO_OVERFLOW_SHIFT                                             3
38784     #define PSWRQ_REG_INT_STS_CLR_TM_FIFO_OVERFLOW                                                   (0x1<<4) // Overflow in tm request fifo.
38785     #define PSWRQ_REG_INT_STS_CLR_TM_FIFO_OVERFLOW_SHIFT                                             4
38786     #define PSWRQ_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW                                                 (0x1<<5) // Overflow in usdm request input fifo.
38787     #define PSWRQ_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW_SHIFT                                           5
38788     #define PSWRQ_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW                                                  (0x1<<6) // Overflow in m2p request input fifo.
38789     #define PSWRQ_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW_SHIFT                                            6
38790     #define PSWRQ_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW                                                 (0x1<<7) // Overflow in xsdm request input fifo.
38791     #define PSWRQ_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW_SHIFT                                           7
38792     #define PSWRQ_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW                                                 (0x1<<8) // Overflow in tsdm request input fifo.
38793     #define PSWRQ_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW_SHIFT                                           8
38794     #define PSWRQ_REG_INT_STS_CLR_PTU_FIFO_OVERFLOW                                                  (0x1<<9) // Overflow in ptu request input fifo.
38795     #define PSWRQ_REG_INT_STS_CLR_PTU_FIFO_OVERFLOW_SHIFT                                            9
38796     #define PSWRQ_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW                                                (0x1<<10) // Overflow in cduwr request input fifo.
38797     #define PSWRQ_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW_SHIFT                                          10
38798     #define PSWRQ_REG_INT_STS_CLR_CDURD_FIFO_OVERFLOW                                                (0x1<<11) // Overflow in cdurd request input fifo.
38799     #define PSWRQ_REG_INT_STS_CLR_CDURD_FIFO_OVERFLOW_SHIFT                                          11
38800     #define PSWRQ_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW                                                 (0x1<<12) // Overflow in dmae request input fifo.
38801     #define PSWRQ_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW_SHIFT                                           12
38802     #define PSWRQ_REG_INT_STS_CLR_HC_FIFO_OVERFLOW                                                   (0x1<<13) // Overflow in hc request input fifo.
38803     #define PSWRQ_REG_INT_STS_CLR_HC_FIFO_OVERFLOW_SHIFT                                             13
38804     #define PSWRQ_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW                                                  (0x1<<14) // Overflow in dbg request input fifo.
38805     #define PSWRQ_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW_SHIFT                                            14
38806     #define PSWRQ_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW                                                 (0x1<<15) // Overflow in msdm request input fifo.
38807     #define PSWRQ_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW_SHIFT                                           15
38808     #define PSWRQ_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW                                                 (0x1<<16) // Overflow in ysdm request input fifo.
38809     #define PSWRQ_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW_SHIFT                                           16
38810     #define PSWRQ_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW                                                 (0x1<<17) // Overflow in psdm request input fifo.
38811     #define PSWRQ_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW_SHIFT                                           17
38812     #define PSWRQ_REG_INT_STS_CLR_PRM_FIFO_OVERFLOW                                                  (0x1<<18) // Overflow in prm request input fifo.
38813     #define PSWRQ_REG_INT_STS_CLR_PRM_FIFO_OVERFLOW_SHIFT                                            18
38814     #define PSWRQ_REG_INT_STS_CLR_MULD_FIFO_OVERFLOW                                                 (0x1<<19) // Overflow in muld request input fifo.
38815     #define PSWRQ_REG_INT_STS_CLR_MULD_FIFO_OVERFLOW_SHIFT                                           19
38816     #define PSWRQ_REG_INT_STS_CLR_XYLD_FIFO_OVERFLOW                                                 (0x1<<20) // Overflow in muld request input fifo.
38817     #define PSWRQ_REG_INT_STS_CLR_XYLD_FIFO_OVERFLOW_SHIFT                                           20
38818 #define PSWRQ_REG_PRTY_MASK                                                                          0x280194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
38819     #define PSWRQ_REG_PRTY_MASK_PXP_BUSIP_PARITY                                                     (0x1<<0) // This bit masks, when set, the Parity bit: PSWRQ_REG_PRTY_STS.PXP_BUSIP_PARITY .
38820     #define PSWRQ_REG_PRTY_MASK_PXP_BUSIP_PARITY_SHIFT                                               0
38821 #define PSWWR_REG_USDM_FULL_TH                                                                       0x29a040UL //Access:RW   DataWidth:0x4   If number of entries in the usdm fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38822 #define PSWWR_REG_MSDM_FULL_TH                                                                       0x29a044UL //Access:RW   DataWidth:0x4   If number of entries in the msdm fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38823 #define PSWWR_REG_YSDM_FULL_TH                                                                       0x29a048UL //Access:RW   DataWidth:0x4   If number of entries in the ysdm fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38824 #define PSWWR_REG_PSDM_FULL_TH                                                                       0x29a04cUL //Access:RW   DataWidth:0x4   If number of entries in the psdm fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38825 #define PSWWR_REG_XSDM_FULL_TH                                                                       0x29a050UL //Access:RW   DataWidth:0x4   If number of entries in the xsdm fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38826 #define PSWWR_REG_TSDM_FULL_TH                                                                       0x29a054UL //Access:RW   DataWidth:0x4   If number of entries in the tsdm fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38827 #define PSWWR_REG_M2P_FULL_TH                                                                        0x29a058UL //Access:RW   DataWidth:0x4   If number of entries in M2P fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38828 #define PSWWR_REG_QM_FULL_TH                                                                         0x29a05cUL //Access:RW   DataWidth:0x3   If number of entries in the qm fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38829 #define PSWWR_REG_TM_FULL_TH                                                                         0x29a060UL //Access:RW   DataWidth:0x4   If number of entries in the tm fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38830 #define PSWWR_REG_SRC_FULL_TH                                                                        0x29a064UL //Access:RW   DataWidth:0x4   If number of entries in the src fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38831 #define PSWWR_REG_DBG_FULL_TH                                                                        0x29a068UL //Access:RW   DataWidth:0x4   If number of entries in the dbg fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38832 #define PSWWR_REG_HC_FULL_TH                                                                         0x29a06cUL //Access:RW   DataWidth:0x4   If number of entries in the hc fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38833 #define PSWWR_REG_DMAE_FULL_TH                                                                       0x29a070UL //Access:RW   DataWidth:0x4   If number of entries in the dmae input fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38834 #define PSWWR_REG_CDU_FULL_TH                                                                        0x29a074UL //Access:RW   DataWidth:0x4   If number of entries in the cdu input fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38835 #define PSWWR_REG_USDMDP_FULL_TH                                                                     0x29a078UL //Access:RW   DataWidth:0x4   If number of entries in the usdmdp input fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38836 #define PSWWR_REG_FIFO_FULL_STATUS                                                                   0x29a07cUL //Access:R    DataWidth:0xf   Each bit indicates if full is asserted towards the client. The clients order is according to the incrementing client IDs of write clients: 0 - TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - PRM (RDIF); 11 - HC; 12 - CDU; 13 - DBG; 14- M2P.  Chips: BB_A0 BB_B0 K2
38837 #define PSWWR_REG_FIFO_FULL_STICKY                                                                   0x29a080UL //Access:R    DataWidth:0xf   Each bit indicates if full was asserted since reset towards the client. The clients order is according to the incrementing client IDs of write clients: 0 - TSDM; 1 - MSDM; 2 - USDM; 3 - XSDM; 4 - YSDM; 5 - PSDM; 6 - QM; 7 - TM; 8 - SRC; 9 - DMAE; 10 - PRM (RDIF); 11 - HC; 12 - CDU; 13 - DBG; 14 - M2P.  Chips: BB_A0 BB_B0 K2
38838 #define PSWWR_REG_DBG_SELECT                                                                         0x29a084UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
38839 #define PSWWR_REG_DBG_DWORD_ENABLE                                                                   0x29a088UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
38840 #define PSWWR_REG_DBG_SHIFT                                                                          0x29a08cUL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
38841 #define PSWWR_REG_DBG_FORCE_VALID                                                                    0x29a090UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
38842 #define PSWWR_REG_DBG_FORCE_FRAME                                                                    0x29a094UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
38843 #define PSWWR_REG_DBG_OUT_DATA                                                                       0x29a0a0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
38844 #define PSWWR_REG_DBG_OUT_DATA_SIZE                                                                  8
38845 #define PSWWR_REG_DBG_OUT_VALID                                                                      0x29a0c0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
38846 #define PSWWR_REG_DBG_OUT_FRAME                                                                      0x29a0c4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
38847 #define PSWWR_REG_ECO_RESERVED                                                                       0x29a0c8UL //Access:RW   DataWidth:0x6   Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
38848 #define PSWWR_REG_INT_STS                                                                            0x29a180UL //Access:R    DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38849     #define PSWWR_REG_INT_STS_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
38850     #define PSWWR_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                    0
38851     #define PSWWR_REG_INT_STS_SRC_FIFO_OVERFLOW                                                      (0x1<<1) // Overflow in src input fifo.
38852     #define PSWWR_REG_INT_STS_SRC_FIFO_OVERFLOW_SHIFT                                                1
38853     #define PSWWR_REG_INT_STS_QM_FIFO_OVERFLOW                                                       (0x1<<2) // Overflow in qm input fifo.
38854     #define PSWWR_REG_INT_STS_QM_FIFO_OVERFLOW_SHIFT                                                 2
38855     #define PSWWR_REG_INT_STS_TM_FIFO_OVERFLOW                                                       (0x1<<3) // Overflow in tm fifo.
38856     #define PSWWR_REG_INT_STS_TM_FIFO_OVERFLOW_SHIFT                                                 3
38857     #define PSWWR_REG_INT_STS_USDM_FIFO_OVERFLOW                                                     (0x1<<4) // Overflow in usdm input fifo.
38858     #define PSWWR_REG_INT_STS_USDM_FIFO_OVERFLOW_SHIFT                                               4
38859     #define PSWWR_REG_INT_STS_USDMDP_FIFO_OVERFLOW                                                   (0x1<<5) // Overflow in usdmdp input fifo.
38860     #define PSWWR_REG_INT_STS_USDMDP_FIFO_OVERFLOW_SHIFT                                             5
38861     #define PSWWR_REG_INT_STS_XSDM_FIFO_OVERFLOW                                                     (0x1<<6) // Overflow in xsdm input fifo.
38862     #define PSWWR_REG_INT_STS_XSDM_FIFO_OVERFLOW_SHIFT                                               6
38863     #define PSWWR_REG_INT_STS_TSDM_FIFO_OVERFLOW                                                     (0x1<<7) // Overflow in tsdm input fifo.
38864     #define PSWWR_REG_INT_STS_TSDM_FIFO_OVERFLOW_SHIFT                                               7
38865     #define PSWWR_REG_INT_STS_CDUWR_FIFO_OVERFLOW                                                    (0x1<<8) // Overflow in cduwr input fifo.
38866     #define PSWWR_REG_INT_STS_CDUWR_FIFO_OVERFLOW_SHIFT                                              8
38867     #define PSWWR_REG_INT_STS_DBG_FIFO_OVERFLOW                                                      (0x1<<9) // Overflow in dbg input fifo.
38868     #define PSWWR_REG_INT_STS_DBG_FIFO_OVERFLOW_SHIFT                                                9
38869     #define PSWWR_REG_INT_STS_DMAE_FIFO_OVERFLOW                                                     (0x1<<10) // Overflow in dmae input fifo.
38870     #define PSWWR_REG_INT_STS_DMAE_FIFO_OVERFLOW_SHIFT                                               10
38871     #define PSWWR_REG_INT_STS_HC_FIFO_OVERFLOW                                                       (0x1<<11) // Overflow in hc input fifo.
38872     #define PSWWR_REG_INT_STS_HC_FIFO_OVERFLOW_SHIFT                                                 11
38873     #define PSWWR_REG_INT_STS_MSDM_FIFO_OVERFLOW                                                     (0x1<<12) // Overflow in msdm write input fifo.
38874     #define PSWWR_REG_INT_STS_MSDM_FIFO_OVERFLOW_SHIFT                                               12
38875     #define PSWWR_REG_INT_STS_YSDM_FIFO_OVERFLOW                                                     (0x1<<13) // Overflow in ysdm write input fifo.
38876     #define PSWWR_REG_INT_STS_YSDM_FIFO_OVERFLOW_SHIFT                                               13
38877     #define PSWWR_REG_INT_STS_PSDM_FIFO_OVERFLOW                                                     (0x1<<14) // Overflow in psdm write input fifo.
38878     #define PSWWR_REG_INT_STS_PSDM_FIFO_OVERFLOW_SHIFT                                               14
38879     #define PSWWR_REG_INT_STS_M2P_FIFO_OVERFLOW                                                      (0x1<<15) // Overflow in M2P input fifo.
38880     #define PSWWR_REG_INT_STS_M2P_FIFO_OVERFLOW_SHIFT                                                15
38881 #define PSWWR_REG_INT_MASK                                                                           0x29a184UL //Access:RW   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38882     #define PSWWR_REG_INT_MASK_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.ADDRESS_ERROR .
38883     #define PSWWR_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                   0
38884     #define PSWWR_REG_INT_MASK_SRC_FIFO_OVERFLOW                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.SRC_FIFO_OVERFLOW .
38885     #define PSWWR_REG_INT_MASK_SRC_FIFO_OVERFLOW_SHIFT                                               1
38886     #define PSWWR_REG_INT_MASK_QM_FIFO_OVERFLOW                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.QM_FIFO_OVERFLOW .
38887     #define PSWWR_REG_INT_MASK_QM_FIFO_OVERFLOW_SHIFT                                                2
38888     #define PSWWR_REG_INT_MASK_TM_FIFO_OVERFLOW                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.TM_FIFO_OVERFLOW .
38889     #define PSWWR_REG_INT_MASK_TM_FIFO_OVERFLOW_SHIFT                                                3
38890     #define PSWWR_REG_INT_MASK_USDM_FIFO_OVERFLOW                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.USDM_FIFO_OVERFLOW .
38891     #define PSWWR_REG_INT_MASK_USDM_FIFO_OVERFLOW_SHIFT                                              4
38892     #define PSWWR_REG_INT_MASK_USDMDP_FIFO_OVERFLOW                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.USDMDP_FIFO_OVERFLOW .
38893     #define PSWWR_REG_INT_MASK_USDMDP_FIFO_OVERFLOW_SHIFT                                            5
38894     #define PSWWR_REG_INT_MASK_XSDM_FIFO_OVERFLOW                                                    (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.XSDM_FIFO_OVERFLOW .
38895     #define PSWWR_REG_INT_MASK_XSDM_FIFO_OVERFLOW_SHIFT                                              6
38896     #define PSWWR_REG_INT_MASK_TSDM_FIFO_OVERFLOW                                                    (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.TSDM_FIFO_OVERFLOW .
38897     #define PSWWR_REG_INT_MASK_TSDM_FIFO_OVERFLOW_SHIFT                                              7
38898     #define PSWWR_REG_INT_MASK_CDUWR_FIFO_OVERFLOW                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.CDUWR_FIFO_OVERFLOW .
38899     #define PSWWR_REG_INT_MASK_CDUWR_FIFO_OVERFLOW_SHIFT                                             8
38900     #define PSWWR_REG_INT_MASK_DBG_FIFO_OVERFLOW                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.DBG_FIFO_OVERFLOW .
38901     #define PSWWR_REG_INT_MASK_DBG_FIFO_OVERFLOW_SHIFT                                               9
38902     #define PSWWR_REG_INT_MASK_DMAE_FIFO_OVERFLOW                                                    (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.DMAE_FIFO_OVERFLOW .
38903     #define PSWWR_REG_INT_MASK_DMAE_FIFO_OVERFLOW_SHIFT                                              10
38904     #define PSWWR_REG_INT_MASK_HC_FIFO_OVERFLOW                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.HC_FIFO_OVERFLOW .
38905     #define PSWWR_REG_INT_MASK_HC_FIFO_OVERFLOW_SHIFT                                                11
38906     #define PSWWR_REG_INT_MASK_MSDM_FIFO_OVERFLOW                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.MSDM_FIFO_OVERFLOW .
38907     #define PSWWR_REG_INT_MASK_MSDM_FIFO_OVERFLOW_SHIFT                                              12
38908     #define PSWWR_REG_INT_MASK_YSDM_FIFO_OVERFLOW                                                    (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.YSDM_FIFO_OVERFLOW .
38909     #define PSWWR_REG_INT_MASK_YSDM_FIFO_OVERFLOW_SHIFT                                              13
38910     #define PSWWR_REG_INT_MASK_PSDM_FIFO_OVERFLOW                                                    (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.PSDM_FIFO_OVERFLOW .
38911     #define PSWWR_REG_INT_MASK_PSDM_FIFO_OVERFLOW_SHIFT                                              14
38912     #define PSWWR_REG_INT_MASK_M2P_FIFO_OVERFLOW                                                     (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWWR_REG_INT_STS.M2P_FIFO_OVERFLOW .
38913     #define PSWWR_REG_INT_MASK_M2P_FIFO_OVERFLOW_SHIFT                                               15
38914 #define PSWWR_REG_INT_STS_WR                                                                         0x29a188UL //Access:WR   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38915     #define PSWWR_REG_INT_STS_WR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
38916     #define PSWWR_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                 0
38917     #define PSWWR_REG_INT_STS_WR_SRC_FIFO_OVERFLOW                                                   (0x1<<1) // Overflow in src input fifo.
38918     #define PSWWR_REG_INT_STS_WR_SRC_FIFO_OVERFLOW_SHIFT                                             1
38919     #define PSWWR_REG_INT_STS_WR_QM_FIFO_OVERFLOW                                                    (0x1<<2) // Overflow in qm input fifo.
38920     #define PSWWR_REG_INT_STS_WR_QM_FIFO_OVERFLOW_SHIFT                                              2
38921     #define PSWWR_REG_INT_STS_WR_TM_FIFO_OVERFLOW                                                    (0x1<<3) // Overflow in tm fifo.
38922     #define PSWWR_REG_INT_STS_WR_TM_FIFO_OVERFLOW_SHIFT                                              3
38923     #define PSWWR_REG_INT_STS_WR_USDM_FIFO_OVERFLOW                                                  (0x1<<4) // Overflow in usdm input fifo.
38924     #define PSWWR_REG_INT_STS_WR_USDM_FIFO_OVERFLOW_SHIFT                                            4
38925     #define PSWWR_REG_INT_STS_WR_USDMDP_FIFO_OVERFLOW                                                (0x1<<5) // Overflow in usdmdp input fifo.
38926     #define PSWWR_REG_INT_STS_WR_USDMDP_FIFO_OVERFLOW_SHIFT                                          5
38927     #define PSWWR_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW                                                  (0x1<<6) // Overflow in xsdm input fifo.
38928     #define PSWWR_REG_INT_STS_WR_XSDM_FIFO_OVERFLOW_SHIFT                                            6
38929     #define PSWWR_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW                                                  (0x1<<7) // Overflow in tsdm input fifo.
38930     #define PSWWR_REG_INT_STS_WR_TSDM_FIFO_OVERFLOW_SHIFT                                            7
38931     #define PSWWR_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW                                                 (0x1<<8) // Overflow in cduwr input fifo.
38932     #define PSWWR_REG_INT_STS_WR_CDUWR_FIFO_OVERFLOW_SHIFT                                           8
38933     #define PSWWR_REG_INT_STS_WR_DBG_FIFO_OVERFLOW                                                   (0x1<<9) // Overflow in dbg input fifo.
38934     #define PSWWR_REG_INT_STS_WR_DBG_FIFO_OVERFLOW_SHIFT                                             9
38935     #define PSWWR_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW                                                  (0x1<<10) // Overflow in dmae input fifo.
38936     #define PSWWR_REG_INT_STS_WR_DMAE_FIFO_OVERFLOW_SHIFT                                            10
38937     #define PSWWR_REG_INT_STS_WR_HC_FIFO_OVERFLOW                                                    (0x1<<11) // Overflow in hc input fifo.
38938     #define PSWWR_REG_INT_STS_WR_HC_FIFO_OVERFLOW_SHIFT                                              11
38939     #define PSWWR_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW                                                  (0x1<<12) // Overflow in msdm write input fifo.
38940     #define PSWWR_REG_INT_STS_WR_MSDM_FIFO_OVERFLOW_SHIFT                                            12
38941     #define PSWWR_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW                                                  (0x1<<13) // Overflow in ysdm write input fifo.
38942     #define PSWWR_REG_INT_STS_WR_YSDM_FIFO_OVERFLOW_SHIFT                                            13
38943     #define PSWWR_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW                                                  (0x1<<14) // Overflow in psdm write input fifo.
38944     #define PSWWR_REG_INT_STS_WR_PSDM_FIFO_OVERFLOW_SHIFT                                            14
38945     #define PSWWR_REG_INT_STS_WR_M2P_FIFO_OVERFLOW                                                   (0x1<<15) // Overflow in M2P input fifo.
38946     #define PSWWR_REG_INT_STS_WR_M2P_FIFO_OVERFLOW_SHIFT                                             15
38947 #define PSWWR_REG_INT_STS_CLR                                                                        0x29a18cUL //Access:RC   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38948     #define PSWWR_REG_INT_STS_CLR_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
38949     #define PSWWR_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                0
38950     #define PSWWR_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW                                                  (0x1<<1) // Overflow in src input fifo.
38951     #define PSWWR_REG_INT_STS_CLR_SRC_FIFO_OVERFLOW_SHIFT                                            1
38952     #define PSWWR_REG_INT_STS_CLR_QM_FIFO_OVERFLOW                                                   (0x1<<2) // Overflow in qm input fifo.
38953     #define PSWWR_REG_INT_STS_CLR_QM_FIFO_OVERFLOW_SHIFT                                             2
38954     #define PSWWR_REG_INT_STS_CLR_TM_FIFO_OVERFLOW                                                   (0x1<<3) // Overflow in tm fifo.
38955     #define PSWWR_REG_INT_STS_CLR_TM_FIFO_OVERFLOW_SHIFT                                             3
38956     #define PSWWR_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW                                                 (0x1<<4) // Overflow in usdm input fifo.
38957     #define PSWWR_REG_INT_STS_CLR_USDM_FIFO_OVERFLOW_SHIFT                                           4
38958     #define PSWWR_REG_INT_STS_CLR_USDMDP_FIFO_OVERFLOW                                               (0x1<<5) // Overflow in usdmdp input fifo.
38959     #define PSWWR_REG_INT_STS_CLR_USDMDP_FIFO_OVERFLOW_SHIFT                                         5
38960     #define PSWWR_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW                                                 (0x1<<6) // Overflow in xsdm input fifo.
38961     #define PSWWR_REG_INT_STS_CLR_XSDM_FIFO_OVERFLOW_SHIFT                                           6
38962     #define PSWWR_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW                                                 (0x1<<7) // Overflow in tsdm input fifo.
38963     #define PSWWR_REG_INT_STS_CLR_TSDM_FIFO_OVERFLOW_SHIFT                                           7
38964     #define PSWWR_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW                                                (0x1<<8) // Overflow in cduwr input fifo.
38965     #define PSWWR_REG_INT_STS_CLR_CDUWR_FIFO_OVERFLOW_SHIFT                                          8
38966     #define PSWWR_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW                                                  (0x1<<9) // Overflow in dbg input fifo.
38967     #define PSWWR_REG_INT_STS_CLR_DBG_FIFO_OVERFLOW_SHIFT                                            9
38968     #define PSWWR_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW                                                 (0x1<<10) // Overflow in dmae input fifo.
38969     #define PSWWR_REG_INT_STS_CLR_DMAE_FIFO_OVERFLOW_SHIFT                                           10
38970     #define PSWWR_REG_INT_STS_CLR_HC_FIFO_OVERFLOW                                                   (0x1<<11) // Overflow in hc input fifo.
38971     #define PSWWR_REG_INT_STS_CLR_HC_FIFO_OVERFLOW_SHIFT                                             11
38972     #define PSWWR_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW                                                 (0x1<<12) // Overflow in msdm write input fifo.
38973     #define PSWWR_REG_INT_STS_CLR_MSDM_FIFO_OVERFLOW_SHIFT                                           12
38974     #define PSWWR_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW                                                 (0x1<<13) // Overflow in ysdm write input fifo.
38975     #define PSWWR_REG_INT_STS_CLR_YSDM_FIFO_OVERFLOW_SHIFT                                           13
38976     #define PSWWR_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW                                                 (0x1<<14) // Overflow in psdm write input fifo.
38977     #define PSWWR_REG_INT_STS_CLR_PSDM_FIFO_OVERFLOW_SHIFT                                           14
38978     #define PSWWR_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW                                                  (0x1<<15) // Overflow in M2P input fifo.
38979     #define PSWWR_REG_INT_STS_CLR_M2P_FIFO_OVERFLOW_SHIFT                                            15
38980 #define PSWWR_REG_PRTY_MASK                                                                          0x29a194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
38981     #define PSWWR_REG_PRTY_MASK_DATAPATH_REGISTERS                                                   (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR_REG_PRTY_STS.DATAPATH_REGISTERS .
38982     #define PSWWR_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                             0
38983 #define PSWWR2_REG_CDU_FULL_TH2                                                                      0x29b040UL //Access:RW   DataWidth:0x6   If Number of entries in the cdu internal fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38984 #define PSWWR2_REG_USDMDP_FULL_TH2                                                                   0x29b044UL //Access:RW   DataWidth:0x9   If Number of entries in the usdmdp internal fifo is bigger than this number than full will be asserted.  Chips: BB_A0 BB_B0 K2
38985 #define PSWWR2_REG_PGLUE_EOP_ERR_DETAILS                                                             0x29b048UL //Access:R    DataWidth:0xf   Details of first request that triggered any of the 3 EOP interrupts: [4:0] - client ID. [7:5] - (sum1[5:3] + 1) or (sum1[5:4] + 1) according to the definition in the spec. [10:8] - number_of_valid_64bit_words[2:0] or number_of_valid_128bit_words[1:0] according to the definition in the spec. [13:11] - The type of interrupt the logging corresponds to: [11] - pglue_eop_error; [12] - pglue_lsr_error; [13] - pglue_eop_error_in_line. [14] - valid - indicates if there was a request that triggered EOP interrupt since this register was cleared.  Chips: BB_A0 BB_B0 K2
38986 #define PSWWR2_REG_PGLUE_EOP_ERR_DETAILS_CLR                                                         0x29b04cUL //Access:W    DataWidth:0x1   Writing to this register clears pglue_eop_err_details and enables logging new error details.  Chips: BB_A0 BB_B0 K2
38987 #define PSWWR2_REG_PRM_CURR_FILL_LEVEL                                                               0x29b050UL //Access:R    DataWidth:0x8   Current internal PRM fill level in 64B lines.  Chips: BB_A0 BB_B0 K2
38988 #define PSWWR2_REG_PRM_MAX_FILL_LEVEL                                                                0x29b054UL //Access:R    DataWidth:0x8   Maximum internal PRM fill level since reset in 64B lines.  Chips: BB_A0 BB_B0 K2
38989 #define PSWWR2_REG_CDU_CURR_FILL_LEVEL                                                               0x29b058UL //Access:R    DataWidth:0x6   Current internal CDU fill level in 64B lines.  Chips: BB_A0 BB_B0 K2
38990 #define PSWWR2_REG_CDU_MAX_FILL_LEVEL                                                                0x29b05cUL //Access:R    DataWidth:0x6   Maximum internal CDU fill level since reset in 64B lines.  Chips: BB_A0 BB_B0 K2
38991 #define PSWWR2_REG_PRM_ERR_FIFO_FULL_TH                                                              0x29b060UL //Access:RW   DataWidth:0x7   If Number of entries in the PRM error fifo is bigger than this number than full will be asserted. PRM error FIFO contains 64 entries.  Chips: BB_A0 BB_B0 K2
38992 #define PSWWR2_REG_ECO_RESERVED                                                                      0x29b064UL //Access:RW   DataWidth:0x6   Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
38993 #define PSWWR2_REG_INT_STS                                                                           0x29b180UL //Access:R    DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
38994     #define PSWWR2_REG_INT_STS_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
38995     #define PSWWR2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                   0
38996     #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR                                                       (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
38997     #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR_SHIFT                                                 1
38998     #define PSWWR2_REG_INT_STS_PGLUE_LSR_ERROR                                                       (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
38999     #define PSWWR2_REG_INT_STS_PGLUE_LSR_ERROR_SHIFT                                                 2
39000     #define PSWWR2_REG_INT_STS_TM_UNDERFLOW                                                          (0x1<<3) // Underflow in the tm fifo.
39001     #define PSWWR2_REG_INT_STS_TM_UNDERFLOW_SHIFT                                                    3
39002     #define PSWWR2_REG_INT_STS_QM_UNDERFLOW                                                          (0x1<<4) // Underflow in the qm fifo.
39003     #define PSWWR2_REG_INT_STS_QM_UNDERFLOW_SHIFT                                                    4
39004     #define PSWWR2_REG_INT_STS_SRC_UNDERFLOW                                                         (0x1<<5) // Underflow in the src fifo.
39005     #define PSWWR2_REG_INT_STS_SRC_UNDERFLOW_SHIFT                                                   5
39006     #define PSWWR2_REG_INT_STS_USDM_UNDERFLOW                                                        (0x1<<6) // Underflow in the usdm fifo.
39007     #define PSWWR2_REG_INT_STS_USDM_UNDERFLOW_SHIFT                                                  6
39008     #define PSWWR2_REG_INT_STS_TSDM_UNDERFLOW                                                        (0x1<<7) // Underflow in the tsdm fifo.
39009     #define PSWWR2_REG_INT_STS_TSDM_UNDERFLOW_SHIFT                                                  7
39010     #define PSWWR2_REG_INT_STS_XSDM_UNDERFLOW                                                        (0x1<<8) // Underflow in the xsdm fifo.
39011     #define PSWWR2_REG_INT_STS_XSDM_UNDERFLOW_SHIFT                                                  8
39012     #define PSWWR2_REG_INT_STS_USDMDP_UNDERFLOW                                                      (0x1<<9) // Underflow in the usdmdp fifo.
39013     #define PSWWR2_REG_INT_STS_USDMDP_UNDERFLOW_SHIFT                                                9
39014     #define PSWWR2_REG_INT_STS_CDU_UNDERFLOW                                                         (0x1<<10) // Underflow in the cdu fifo.
39015     #define PSWWR2_REG_INT_STS_CDU_UNDERFLOW_SHIFT                                                   10
39016     #define PSWWR2_REG_INT_STS_DBG_UNDERFLOW                                                         (0x1<<11) // Underflow in the dbg fifo.
39017     #define PSWWR2_REG_INT_STS_DBG_UNDERFLOW_SHIFT                                                   11
39018     #define PSWWR2_REG_INT_STS_DMAE_UNDERFLOW                                                        (0x1<<12) // Underflow in the dmae fifo.
39019     #define PSWWR2_REG_INT_STS_DMAE_UNDERFLOW_SHIFT                                                  12
39020     #define PSWWR2_REG_INT_STS_HC_UNDERFLOW                                                          (0x1<<13) // Underflow in the hc fifo.
39021     #define PSWWR2_REG_INT_STS_HC_UNDERFLOW_SHIFT                                                    13
39022     #define PSWWR2_REG_INT_STS_MSDM_UNDERFLOW                                                        (0x1<<14) // Underflow in the msdm fifo.
39023     #define PSWWR2_REG_INT_STS_MSDM_UNDERFLOW_SHIFT                                                  14
39024     #define PSWWR2_REG_INT_STS_YSDM_UNDERFLOW                                                        (0x1<<15) // Underflow in the ysdm fifo.
39025     #define PSWWR2_REG_INT_STS_YSDM_UNDERFLOW_SHIFT                                                  15
39026     #define PSWWR2_REG_INT_STS_PSDM_UNDERFLOW                                                        (0x1<<16) // Underflow in the psdm fifo.
39027     #define PSWWR2_REG_INT_STS_PSDM_UNDERFLOW_SHIFT                                                  16
39028     #define PSWWR2_REG_INT_STS_M2P_UNDERFLOW                                                         (0x1<<17) // Underflow in the M2P fifo.
39029     #define PSWWR2_REG_INT_STS_M2P_UNDERFLOW_SHIFT                                                   17
39030     #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR_IN_LINE                                               (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
39031     #define PSWWR2_REG_INT_STS_PGLUE_EOP_ERROR_IN_LINE_SHIFT                                         18
39032 #define PSWWR2_REG_INT_MASK                                                                          0x29b184UL //Access:RW   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39033     #define PSWWR2_REG_INT_MASK_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.ADDRESS_ERROR .
39034     #define PSWWR2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                  0
39035     #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_EOP_ERROR .
39036     #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR_SHIFT                                                1
39037     #define PSWWR2_REG_INT_MASK_PGLUE_LSR_ERROR                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_LSR_ERROR .
39038     #define PSWWR2_REG_INT_MASK_PGLUE_LSR_ERROR_SHIFT                                                2
39039     #define PSWWR2_REG_INT_MASK_TM_UNDERFLOW                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.TM_UNDERFLOW .
39040     #define PSWWR2_REG_INT_MASK_TM_UNDERFLOW_SHIFT                                                   3
39041     #define PSWWR2_REG_INT_MASK_QM_UNDERFLOW                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.QM_UNDERFLOW .
39042     #define PSWWR2_REG_INT_MASK_QM_UNDERFLOW_SHIFT                                                   4
39043     #define PSWWR2_REG_INT_MASK_SRC_UNDERFLOW                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.SRC_UNDERFLOW .
39044     #define PSWWR2_REG_INT_MASK_SRC_UNDERFLOW_SHIFT                                                  5
39045     #define PSWWR2_REG_INT_MASK_USDM_UNDERFLOW                                                       (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.USDM_UNDERFLOW .
39046     #define PSWWR2_REG_INT_MASK_USDM_UNDERFLOW_SHIFT                                                 6
39047     #define PSWWR2_REG_INT_MASK_TSDM_UNDERFLOW                                                       (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.TSDM_UNDERFLOW .
39048     #define PSWWR2_REG_INT_MASK_TSDM_UNDERFLOW_SHIFT                                                 7
39049     #define PSWWR2_REG_INT_MASK_XSDM_UNDERFLOW                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.XSDM_UNDERFLOW .
39050     #define PSWWR2_REG_INT_MASK_XSDM_UNDERFLOW_SHIFT                                                 8
39051     #define PSWWR2_REG_INT_MASK_USDMDP_UNDERFLOW                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.USDMDP_UNDERFLOW .
39052     #define PSWWR2_REG_INT_MASK_USDMDP_UNDERFLOW_SHIFT                                               9
39053     #define PSWWR2_REG_INT_MASK_CDU_UNDERFLOW                                                        (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.CDU_UNDERFLOW .
39054     #define PSWWR2_REG_INT_MASK_CDU_UNDERFLOW_SHIFT                                                  10
39055     #define PSWWR2_REG_INT_MASK_DBG_UNDERFLOW                                                        (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.DBG_UNDERFLOW .
39056     #define PSWWR2_REG_INT_MASK_DBG_UNDERFLOW_SHIFT                                                  11
39057     #define PSWWR2_REG_INT_MASK_DMAE_UNDERFLOW                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.DMAE_UNDERFLOW .
39058     #define PSWWR2_REG_INT_MASK_DMAE_UNDERFLOW_SHIFT                                                 12
39059     #define PSWWR2_REG_INT_MASK_HC_UNDERFLOW                                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.HC_UNDERFLOW .
39060     #define PSWWR2_REG_INT_MASK_HC_UNDERFLOW_SHIFT                                                   13
39061     #define PSWWR2_REG_INT_MASK_MSDM_UNDERFLOW                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.MSDM_UNDERFLOW .
39062     #define PSWWR2_REG_INT_MASK_MSDM_UNDERFLOW_SHIFT                                                 14
39063     #define PSWWR2_REG_INT_MASK_YSDM_UNDERFLOW                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.YSDM_UNDERFLOW .
39064     #define PSWWR2_REG_INT_MASK_YSDM_UNDERFLOW_SHIFT                                                 15
39065     #define PSWWR2_REG_INT_MASK_PSDM_UNDERFLOW                                                       (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PSDM_UNDERFLOW .
39066     #define PSWWR2_REG_INT_MASK_PSDM_UNDERFLOW_SHIFT                                                 16
39067     #define PSWWR2_REG_INT_MASK_M2P_UNDERFLOW                                                        (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.M2P_UNDERFLOW .
39068     #define PSWWR2_REG_INT_MASK_M2P_UNDERFLOW_SHIFT                                                  17
39069     #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR_IN_LINE                                              (0x1<<18) // This bit masks, when set, the Interrupt bit: PSWWR2_REG_INT_STS.PGLUE_EOP_ERROR_IN_LINE .
39070     #define PSWWR2_REG_INT_MASK_PGLUE_EOP_ERROR_IN_LINE_SHIFT                                        18
39071 #define PSWWR2_REG_INT_STS_WR                                                                        0x29b188UL //Access:WR   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39072     #define PSWWR2_REG_INT_STS_WR_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
39073     #define PSWWR2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                0
39074     #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR                                                    (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
39075     #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR_SHIFT                                              1
39076     #define PSWWR2_REG_INT_STS_WR_PGLUE_LSR_ERROR                                                    (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
39077     #define PSWWR2_REG_INT_STS_WR_PGLUE_LSR_ERROR_SHIFT                                              2
39078     #define PSWWR2_REG_INT_STS_WR_TM_UNDERFLOW                                                       (0x1<<3) // Underflow in the tm fifo.
39079     #define PSWWR2_REG_INT_STS_WR_TM_UNDERFLOW_SHIFT                                                 3
39080     #define PSWWR2_REG_INT_STS_WR_QM_UNDERFLOW                                                       (0x1<<4) // Underflow in the qm fifo.
39081     #define PSWWR2_REG_INT_STS_WR_QM_UNDERFLOW_SHIFT                                                 4
39082     #define PSWWR2_REG_INT_STS_WR_SRC_UNDERFLOW                                                      (0x1<<5) // Underflow in the src fifo.
39083     #define PSWWR2_REG_INT_STS_WR_SRC_UNDERFLOW_SHIFT                                                5
39084     #define PSWWR2_REG_INT_STS_WR_USDM_UNDERFLOW                                                     (0x1<<6) // Underflow in the usdm fifo.
39085     #define PSWWR2_REG_INT_STS_WR_USDM_UNDERFLOW_SHIFT                                               6
39086     #define PSWWR2_REG_INT_STS_WR_TSDM_UNDERFLOW                                                     (0x1<<7) // Underflow in the tsdm fifo.
39087     #define PSWWR2_REG_INT_STS_WR_TSDM_UNDERFLOW_SHIFT                                               7
39088     #define PSWWR2_REG_INT_STS_WR_XSDM_UNDERFLOW                                                     (0x1<<8) // Underflow in the xsdm fifo.
39089     #define PSWWR2_REG_INT_STS_WR_XSDM_UNDERFLOW_SHIFT                                               8
39090     #define PSWWR2_REG_INT_STS_WR_USDMDP_UNDERFLOW                                                   (0x1<<9) // Underflow in the usdmdp fifo.
39091     #define PSWWR2_REG_INT_STS_WR_USDMDP_UNDERFLOW_SHIFT                                             9
39092     #define PSWWR2_REG_INT_STS_WR_CDU_UNDERFLOW                                                      (0x1<<10) // Underflow in the cdu fifo.
39093     #define PSWWR2_REG_INT_STS_WR_CDU_UNDERFLOW_SHIFT                                                10
39094     #define PSWWR2_REG_INT_STS_WR_DBG_UNDERFLOW                                                      (0x1<<11) // Underflow in the dbg fifo.
39095     #define PSWWR2_REG_INT_STS_WR_DBG_UNDERFLOW_SHIFT                                                11
39096     #define PSWWR2_REG_INT_STS_WR_DMAE_UNDERFLOW                                                     (0x1<<12) // Underflow in the dmae fifo.
39097     #define PSWWR2_REG_INT_STS_WR_DMAE_UNDERFLOW_SHIFT                                               12
39098     #define PSWWR2_REG_INT_STS_WR_HC_UNDERFLOW                                                       (0x1<<13) // Underflow in the hc fifo.
39099     #define PSWWR2_REG_INT_STS_WR_HC_UNDERFLOW_SHIFT                                                 13
39100     #define PSWWR2_REG_INT_STS_WR_MSDM_UNDERFLOW                                                     (0x1<<14) // Underflow in the msdm fifo.
39101     #define PSWWR2_REG_INT_STS_WR_MSDM_UNDERFLOW_SHIFT                                               14
39102     #define PSWWR2_REG_INT_STS_WR_YSDM_UNDERFLOW                                                     (0x1<<15) // Underflow in the ysdm fifo.
39103     #define PSWWR2_REG_INT_STS_WR_YSDM_UNDERFLOW_SHIFT                                               15
39104     #define PSWWR2_REG_INT_STS_WR_PSDM_UNDERFLOW                                                     (0x1<<16) // Underflow in the psdm fifo.
39105     #define PSWWR2_REG_INT_STS_WR_PSDM_UNDERFLOW_SHIFT                                               16
39106     #define PSWWR2_REG_INT_STS_WR_M2P_UNDERFLOW                                                      (0x1<<17) // Underflow in the M2P fifo.
39107     #define PSWWR2_REG_INT_STS_WR_M2P_UNDERFLOW_SHIFT                                                17
39108     #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR_IN_LINE                                            (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
39109     #define PSWWR2_REG_INT_STS_WR_PGLUE_EOP_ERROR_IN_LINE_SHIFT                                      18
39110 #define PSWWR2_REG_INT_STS_CLR                                                                       0x29b18cUL //Access:RC   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39111     #define PSWWR2_REG_INT_STS_CLR_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
39112     #define PSWWR2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                               0
39113     #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR                                                   (0x1<<1) // Indicates that there was not 'eop' in the last read request from the glue block.
39114     #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR_SHIFT                                             1
39115     #define PSWWR2_REG_INT_STS_CLR_PGLUE_LSR_ERROR                                                   (0x1<<2) // Indicates that there was 'eop' not in the last read request from the glue block.
39116     #define PSWWR2_REG_INT_STS_CLR_PGLUE_LSR_ERROR_SHIFT                                             2
39117     #define PSWWR2_REG_INT_STS_CLR_TM_UNDERFLOW                                                      (0x1<<3) // Underflow in the tm fifo.
39118     #define PSWWR2_REG_INT_STS_CLR_TM_UNDERFLOW_SHIFT                                                3
39119     #define PSWWR2_REG_INT_STS_CLR_QM_UNDERFLOW                                                      (0x1<<4) // Underflow in the qm fifo.
39120     #define PSWWR2_REG_INT_STS_CLR_QM_UNDERFLOW_SHIFT                                                4
39121     #define PSWWR2_REG_INT_STS_CLR_SRC_UNDERFLOW                                                     (0x1<<5) // Underflow in the src fifo.
39122     #define PSWWR2_REG_INT_STS_CLR_SRC_UNDERFLOW_SHIFT                                               5
39123     #define PSWWR2_REG_INT_STS_CLR_USDM_UNDERFLOW                                                    (0x1<<6) // Underflow in the usdm fifo.
39124     #define PSWWR2_REG_INT_STS_CLR_USDM_UNDERFLOW_SHIFT                                              6
39125     #define PSWWR2_REG_INT_STS_CLR_TSDM_UNDERFLOW                                                    (0x1<<7) // Underflow in the tsdm fifo.
39126     #define PSWWR2_REG_INT_STS_CLR_TSDM_UNDERFLOW_SHIFT                                              7
39127     #define PSWWR2_REG_INT_STS_CLR_XSDM_UNDERFLOW                                                    (0x1<<8) // Underflow in the xsdm fifo.
39128     #define PSWWR2_REG_INT_STS_CLR_XSDM_UNDERFLOW_SHIFT                                              8
39129     #define PSWWR2_REG_INT_STS_CLR_USDMDP_UNDERFLOW                                                  (0x1<<9) // Underflow in the usdmdp fifo.
39130     #define PSWWR2_REG_INT_STS_CLR_USDMDP_UNDERFLOW_SHIFT                                            9
39131     #define PSWWR2_REG_INT_STS_CLR_CDU_UNDERFLOW                                                     (0x1<<10) // Underflow in the cdu fifo.
39132     #define PSWWR2_REG_INT_STS_CLR_CDU_UNDERFLOW_SHIFT                                               10
39133     #define PSWWR2_REG_INT_STS_CLR_DBG_UNDERFLOW                                                     (0x1<<11) // Underflow in the dbg fifo.
39134     #define PSWWR2_REG_INT_STS_CLR_DBG_UNDERFLOW_SHIFT                                               11
39135     #define PSWWR2_REG_INT_STS_CLR_DMAE_UNDERFLOW                                                    (0x1<<12) // Underflow in the dmae fifo.
39136     #define PSWWR2_REG_INT_STS_CLR_DMAE_UNDERFLOW_SHIFT                                              12
39137     #define PSWWR2_REG_INT_STS_CLR_HC_UNDERFLOW                                                      (0x1<<13) // Underflow in the hc fifo.
39138     #define PSWWR2_REG_INT_STS_CLR_HC_UNDERFLOW_SHIFT                                                13
39139     #define PSWWR2_REG_INT_STS_CLR_MSDM_UNDERFLOW                                                    (0x1<<14) // Underflow in the msdm fifo.
39140     #define PSWWR2_REG_INT_STS_CLR_MSDM_UNDERFLOW_SHIFT                                              14
39141     #define PSWWR2_REG_INT_STS_CLR_YSDM_UNDERFLOW                                                    (0x1<<15) // Underflow in the ysdm fifo.
39142     #define PSWWR2_REG_INT_STS_CLR_YSDM_UNDERFLOW_SHIFT                                              15
39143     #define PSWWR2_REG_INT_STS_CLR_PSDM_UNDERFLOW                                                    (0x1<<16) // Underflow in the psdm fifo.
39144     #define PSWWR2_REG_INT_STS_CLR_PSDM_UNDERFLOW_SHIFT                                              16
39145     #define PSWWR2_REG_INT_STS_CLR_M2P_UNDERFLOW                                                     (0x1<<17) // Underflow in the M2P fifo.
39146     #define PSWWR2_REG_INT_STS_CLR_M2P_UNDERFLOW_SHIFT                                               17
39147     #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR_IN_LINE                                           (0x1<<18) // Indicates that there was 'eop' in the last read request from the glue block; but the number of valid 128-bit or 64-bit words in the memory line did not match the PGLUE indication of the request length.
39148     #define PSWWR2_REG_INT_STS_CLR_PGLUE_EOP_ERROR_IN_LINE_SHIFT                                     18
39149 #define PSWWR2_REG_PRTY_MASK                                                                         0x29b194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
39150     #define PSWWR2_REG_PRTY_MASK_DATAPATH_REGISTERS                                                  (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS.DATAPATH_REGISTERS .
39151     #define PSWWR2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                            0
39152 #define PSWWR2_REG_PRTY_MASK_H_0                                                                     0x29b204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39153     #define PSWWR2_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
39154     #define PSWWR2_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT                                       0
39155     #define PSWWR2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                               (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
39156     #define PSWWR2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                         1
39157     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_0                                             (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_0 .
39158     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_0_SHIFT                                       2
39159     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_1                                             (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_1 .
39160     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_1_SHIFT                                       3
39161     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_2                                             (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_2 .
39162     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_2_SHIFT                                       4
39163     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_3                                             (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_3 .
39164     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_3_SHIFT                                       5
39165     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_4                                             (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_4 .
39166     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_4_SHIFT                                       6
39167     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_5                                             (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_5 .
39168     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_5_SHIFT                                       7
39169     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_6                                             (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_6 .
39170     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_6_SHIFT                                       8
39171     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_7                                             (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_7 .
39172     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_7_SHIFT                                       9
39173     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_8                                             (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY_8 .
39174     #define PSWWR2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_8_SHIFT                                       10
39175     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0                                             (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_0 .
39176     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_0_SHIFT                                       11
39177     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1                                             (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_1 .
39178     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_1_SHIFT                                       12
39179     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_2                                             (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_2 .
39180     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_2_SHIFT                                       13
39181     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_3                                             (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_3 .
39182     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_3_SHIFT                                       14
39183     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_4                                             (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_4 .
39184     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_4_SHIFT                                       15
39185     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_5                                             (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_5 .
39186     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_5_SHIFT                                       16
39187     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_6                                             (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_6 .
39188     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_6_SHIFT                                       17
39189     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_7                                             (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_7 .
39190     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_7_SHIFT                                       18
39191     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_8                                             (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY_8 .
39192     #define PSWWR2_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_8_SHIFT                                       19
39193     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0                                             (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
39194     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_SHIFT                                       20
39195     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1                                             (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
39196     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_SHIFT                                       21
39197     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2                                             (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_2 .
39198     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_2_SHIFT                                       22
39199     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_3                                             (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_3 .
39200     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_3_SHIFT                                       23
39201     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_4                                             (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_4 .
39202     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_4_SHIFT                                       24
39203     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_5                                             (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_5 .
39204     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_5_SHIFT                                       25
39205     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_6                                             (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_6 .
39206     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_6_SHIFT                                       26
39207     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_7                                             (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_7 .
39208     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_7_SHIFT                                       27
39209     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_8                                             (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_8 .
39210     #define PSWWR2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_8_SHIFT                                       28
39211     #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_0                                             (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_0 .
39212     #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_0_SHIFT                                       29
39213     #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_1                                             (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY_1 .
39214     #define PSWWR2_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_1_SHIFT                                       30
39215 #define PSWWR2_REG_PRTY_MASK_H_1                                                                     0x29b214UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39216     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_2                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_2 .
39217     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_2_SHIFT                                       0
39218     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_3                                             (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_3 .
39219     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_3_SHIFT                                       1
39220     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_4                                             (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_4 .
39221     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_4_SHIFT                                       2
39222     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_5                                             (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_5 .
39223     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_5_SHIFT                                       3
39224     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_6                                             (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_6 .
39225     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_6_SHIFT                                       4
39226     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_7                                             (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_7 .
39227     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_7_SHIFT                                       5
39228     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_8                                             (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY_8 .
39229     #define PSWWR2_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_8_SHIFT                                       6
39230     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_0                                             (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_0 .
39231     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_0_SHIFT                                       7
39232     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_1                                             (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_1 .
39233     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_1_SHIFT                                       8
39234     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_2                                             (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_2 .
39235     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_2_SHIFT                                       9
39236     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_3                                             (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_3 .
39237     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_3_SHIFT                                       10
39238     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_4                                             (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_4 .
39239     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_4_SHIFT                                       11
39240     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_5                                             (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_5 .
39241     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_5_SHIFT                                       12
39242     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_6                                             (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_6 .
39243     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_6_SHIFT                                       13
39244     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_7                                             (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_7 .
39245     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_7_SHIFT                                       14
39246     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_8                                             (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY_8 .
39247     #define PSWWR2_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_8_SHIFT                                       15
39248     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_0                                             (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_0 .
39249     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_0_SHIFT                                       16
39250     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_1                                             (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_1 .
39251     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_1_SHIFT                                       17
39252     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_2                                             (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_2 .
39253     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_2_SHIFT                                       18
39254     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_3                                             (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_3 .
39255     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_3_SHIFT                                       19
39256     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_4                                             (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_4 .
39257     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_4_SHIFT                                       20
39258     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_5                                             (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_5 .
39259     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_5_SHIFT                                       21
39260     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_6                                             (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_6 .
39261     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_6_SHIFT                                       22
39262     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_7                                             (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_7 .
39263     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_7_SHIFT                                       23
39264     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_8                                             (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY_8 .
39265     #define PSWWR2_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_8_SHIFT                                       24
39266     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_0                                             (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_0 .
39267     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_0_SHIFT                                       25
39268     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_1                                             (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_1 .
39269     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_1_SHIFT                                       26
39270     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_2                                             (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_2 .
39271     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_2_SHIFT                                       27
39272     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_3                                             (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_3 .
39273     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_3_SHIFT                                       28
39274     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_4                                             (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_4 .
39275     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_4_SHIFT                                       29
39276     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_5                                             (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY_5 .
39277     #define PSWWR2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_5_SHIFT                                       30
39278 #define PSWWR2_REG_PRTY_MASK_H_2                                                                     0x29b224UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39279     #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_6                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_6 .
39280     #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_6_SHIFT                                       0
39281     #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_7                                             (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_7 .
39282     #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_7_SHIFT                                       1
39283     #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_8                                             (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM006_I_MEM_PRTY_8 .
39284     #define PSWWR2_REG_PRTY_MASK_H_2_MEM006_I_MEM_PRTY_8_SHIFT                                       2
39285     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_0                                             (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_0 .
39286     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_0_SHIFT                                       3
39287     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_1                                             (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_1 .
39288     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_1_SHIFT                                       4
39289     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_2                                             (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_2 .
39290     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_2_SHIFT                                       5
39291     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_3                                             (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_3 .
39292     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_3_SHIFT                                       6
39293     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_4                                             (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_4 .
39294     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_4_SHIFT                                       7
39295     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_5                                             (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_5 .
39296     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_5_SHIFT                                       8
39297     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_6                                             (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_6 .
39298     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_6_SHIFT                                       9
39299     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_7                                             (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_7 .
39300     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_7_SHIFT                                       10
39301     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_8                                             (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY_8 .
39302     #define PSWWR2_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_8_SHIFT                                       11
39303     #define PSWWR2_REG_PRTY_MASK_H_2_MEM012_I_MEM_PRTY                                               (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM012_I_MEM_PRTY .
39304     #define PSWWR2_REG_PRTY_MASK_H_2_MEM012_I_MEM_PRTY_SHIFT                                         12
39305     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_0                                             (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_0 .
39306     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_0_SHIFT                                       13
39307     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_1                                             (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_1 .
39308     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_1_SHIFT                                       14
39309     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_2                                             (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_2 .
39310     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_2_SHIFT                                       15
39311     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_3                                             (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_3 .
39312     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_3_SHIFT                                       16
39313     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_4                                             (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_4 .
39314     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_4_SHIFT                                       17
39315     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_5                                             (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_5 .
39316     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_5_SHIFT                                       18
39317     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_6                                             (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_6 .
39318     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_6_SHIFT                                       19
39319     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_7                                             (0x1<<20) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_7 .
39320     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_7_SHIFT                                       20
39321     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_8                                             (0x1<<21) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM011_I_MEM_PRTY_8 .
39322     #define PSWWR2_REG_PRTY_MASK_H_2_MEM011_I_MEM_PRTY_8_SHIFT                                       21
39323     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_0                                             (0x1<<22) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_0 .
39324     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_0_SHIFT                                       22
39325     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_1                                             (0x1<<23) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_1 .
39326     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_1_SHIFT                                       23
39327     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_2                                             (0x1<<24) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_2 .
39328     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_2_SHIFT                                       24
39329     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_3                                             (0x1<<25) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_3 .
39330     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_3_SHIFT                                       25
39331     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_4                                             (0x1<<26) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_4 .
39332     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_4_SHIFT                                       26
39333     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_5                                             (0x1<<27) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_5 .
39334     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_5_SHIFT                                       27
39335     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_6                                             (0x1<<28) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_6 .
39336     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_6_SHIFT                                       28
39337     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_7                                             (0x1<<29) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_7 .
39338     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_7_SHIFT                                       29
39339     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_8                                             (0x1<<30) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_2.MEM004_I_MEM_PRTY_8 .
39340     #define PSWWR2_REG_PRTY_MASK_H_2_MEM004_I_MEM_PRTY_8_SHIFT                                       30
39341 #define PSWWR2_REG_PRTY_MASK_H_3                                                                     0x29b234UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39342     #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_0                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_0 .
39343     #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_0_SHIFT                                       0
39344     #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_1                                             (0x1<<1) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_1 .
39345     #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_1_SHIFT                                       1
39346     #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_2                                             (0x1<<2) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM015_I_MEM_PRTY_2 .
39347     #define PSWWR2_REG_PRTY_MASK_H_3_MEM015_I_MEM_PRTY_2_SHIFT                                       2
39348     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_0                                             (0x1<<3) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_0 .
39349     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_0_SHIFT                                       3
39350     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_1                                             (0x1<<4) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_1 .
39351     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_1_SHIFT                                       4
39352     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_2                                             (0x1<<5) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_2 .
39353     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_2_SHIFT                                       5
39354     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_3                                             (0x1<<6) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_3 .
39355     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_3_SHIFT                                       6
39356     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_4                                             (0x1<<7) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_4 .
39357     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_4_SHIFT                                       7
39358     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_5                                             (0x1<<8) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_5 .
39359     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_5_SHIFT                                       8
39360     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_6                                             (0x1<<9) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_6 .
39361     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_6_SHIFT                                       9
39362     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_7                                             (0x1<<10) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_7 .
39363     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_7_SHIFT                                       10
39364     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_8                                             (0x1<<11) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY_8 .
39365     #define PSWWR2_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_8_SHIFT                                       11
39366     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_0                                             (0x1<<12) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_0 .
39367     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_0_SHIFT                                       12
39368     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_1                                             (0x1<<13) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_1 .
39369     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_1_SHIFT                                       13
39370     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_2                                             (0x1<<14) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_2 .
39371     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_2_SHIFT                                       14
39372     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_3                                             (0x1<<15) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_3 .
39373     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_3_SHIFT                                       15
39374     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_4                                             (0x1<<16) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY_4 .
39375     #define PSWWR2_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_4_SHIFT                                       16
39376     #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_0                                             (0x1<<17) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_0 .
39377     #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_0_SHIFT                                       17
39378     #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_1                                             (0x1<<18) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_1 .
39379     #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_1_SHIFT                                       18
39380     #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_2                                             (0x1<<19) // This bit masks, when set, the Parity bit: PSWWR2_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY_2 .
39381     #define PSWWR2_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_2_SHIFT                                       19
39382 #define PSWWR2_REG_MEM_ECC_EVENTS                                                                    0x29b250UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
39383 #define PSWWR2_REG_MEM001_I_MEM_DFT_K2                                                               0x29b264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_cdu_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39384 #define PSWWR2_REG_MEM008_I_MEM_DFT_K2                                                               0x29b268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_prm_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39385 #define PSWWR2_REG_MEM014_I_MEM_DFT_K2                                                               0x29b26cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_usdm_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39386 #define PSWWR2_REG_MEM016_I_MEM_DFT_K2                                                               0x29b270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_xsdm_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39387 #define PSWWR2_REG_MEM007_I_MEM_DFT_K2                                                               0x29b274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_msdm_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39388 #define PSWWR2_REG_MEM017_I_MEM_DFT_K2                                                               0x29b278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_ysdm_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39389 #define PSWWR2_REG_MEM009_I_MEM_DFT_K2                                                               0x29b27cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_psdm_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39390 #define PSWWR2_REG_MEM013_I_MEM_DFT_K2                                                               0x29b280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_tsdm_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39391 #define PSWWR2_REG_MEM006_I_MEM_DFT_K2                                                               0x29b284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_m2p_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39392 #define PSWWR2_REG_MEM010_I_MEM_DFT_K2                                                               0x29b288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_qm_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39393 #define PSWWR2_REG_MEM012_I_MEM_DFT_K2                                                               0x29b28cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_tm_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39394 #define PSWWR2_REG_MEM011_I_MEM_DFT_K2                                                               0x29b290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_src_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39395 #define PSWWR2_REG_MEM004_I_MEM_DFT_K2                                                               0x29b294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_dmae_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39396 #define PSWWR2_REG_MEM015_I_MEM_DFT_K2                                                               0x29b298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_usdmdp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39397 #define PSWWR2_REG_MEM005_I_MEM_DFT_K2                                                               0x29b29cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_hc_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39398 #define PSWWR2_REG_MEM002_I_MEM_DFT_K2                                                               0x29b2a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_cdu_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39399 #define PSWWR2_REG_MEM003_I_MEM_DFT_K2                                                               0x29b2a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswwr.i_dbg_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39400 #define PSWRD_REG_DBG_SELECT                                                                         0x29c040UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
39401 #define PSWRD_REG_DBG_DWORD_ENABLE                                                                   0x29c044UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
39402 #define PSWRD_REG_DBG_SHIFT                                                                          0x29c048UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
39403 #define PSWRD_REG_DBG_FORCE_VALID                                                                    0x29c04cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
39404 #define PSWRD_REG_DBG_FORCE_FRAME                                                                    0x29c050UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
39405 #define PSWRD_REG_DBG_OUT_DATA                                                                       0x29c060UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
39406 #define PSWRD_REG_DBG_OUT_DATA_SIZE                                                                  8
39407 #define PSWRD_REG_DBG_OUT_VALID                                                                      0x29c080UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
39408 #define PSWRD_REG_DBG_OUT_FRAME                                                                      0x29c084UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
39409 #define PSWRD_REG_ECO_RESERVED                                                                       0x29c0a0UL //Access:RW   DataWidth:0xa   Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
39410 #define PSWRD_REG_FIFO_FULL_STATUS                                                                   0x29c0a4UL //Access:R    DataWidth:0x10  Each bit indicates if full is asserted by the client. The clients order is according to the incrementing client IDs of read clients.  Chips: BB_A0 BB_B0 K2
39411 #define PSWRD_REG_FIFO_FULL_STICKY                                                                   0x29c0a8UL //Access:R    DataWidth:0x10  Each bit indicates if full was asserted since reset by the client. The clients order is according to the incrementing client IDs of read clients:.  Chips: BB_A0 BB_B0 K2
39412 #define PSWRD_REG_INT_STS                                                                            0x29c180UL //Access:R    DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39413     #define PSWRD_REG_INT_STS_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
39414     #define PSWRD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                    0
39415     #define PSWRD_REG_INT_STS_POP_ERROR                                                              (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
39416     #define PSWRD_REG_INT_STS_POP_ERROR_SHIFT                                                        1
39417     #define PSWRD_REG_INT_STS_POP_PBF_ERROR                                                          (0x1<<2) // An error in the PBF FIFO pop interface.
39418     #define PSWRD_REG_INT_STS_POP_PBF_ERROR_SHIFT                                                    2
39419 #define PSWRD_REG_INT_MASK                                                                           0x29c184UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39420     #define PSWRD_REG_INT_MASK_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.ADDRESS_ERROR .
39421     #define PSWRD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                   0
39422     #define PSWRD_REG_INT_MASK_POP_ERROR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.POP_ERROR .
39423     #define PSWRD_REG_INT_MASK_POP_ERROR_SHIFT                                                       1
39424     #define PSWRD_REG_INT_MASK_POP_PBF_ERROR                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRD_REG_INT_STS.POP_PBF_ERROR .
39425     #define PSWRD_REG_INT_MASK_POP_PBF_ERROR_SHIFT                                                   2
39426 #define PSWRD_REG_INT_STS_WR                                                                         0x29c188UL //Access:WR   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39427     #define PSWRD_REG_INT_STS_WR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
39428     #define PSWRD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                 0
39429     #define PSWRD_REG_INT_STS_WR_POP_ERROR                                                           (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
39430     #define PSWRD_REG_INT_STS_WR_POP_ERROR_SHIFT                                                     1
39431     #define PSWRD_REG_INT_STS_WR_POP_PBF_ERROR                                                       (0x1<<2) // An error in the PBF FIFO pop interface.
39432     #define PSWRD_REG_INT_STS_WR_POP_PBF_ERROR_SHIFT                                                 2
39433 #define PSWRD_REG_INT_STS_CLR                                                                        0x29c18cUL //Access:RC   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39434     #define PSWRD_REG_INT_STS_CLR_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
39435     #define PSWRD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                0
39436     #define PSWRD_REG_INT_STS_CLR_POP_ERROR                                                          (0x1<<1) // An error in one of the clients' (except PBF) FIFOs pop interface.
39437     #define PSWRD_REG_INT_STS_CLR_POP_ERROR_SHIFT                                                    1
39438     #define PSWRD_REG_INT_STS_CLR_POP_PBF_ERROR                                                      (0x1<<2) // An error in the PBF FIFO pop interface.
39439     #define PSWRD_REG_INT_STS_CLR_POP_PBF_ERROR_SHIFT                                                2
39440 #define PSWRD_REG_PRTY_MASK                                                                          0x29c194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
39441     #define PSWRD_REG_PRTY_MASK_DATAPATH_REGISTERS                                                   (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD_REG_PRTY_STS.DATAPATH_REGISTERS .
39442     #define PSWRD_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                             0
39443 #define PSWRD2_REG_START_INIT                                                                        0x29d000UL //Access:RW   DataWidth:0x1   Driver should write 1 to this register in order to signal the PSWRD block to start initializing internal memories.  Chips: BB_A0 BB_B0 K2
39444 #define PSWRD2_REG_INIT_DONE                                                                         0x29d004UL //Access:R    DataWidth:0x1   PSWRD internal memories initialization is done. Driver should check this register is 1 some time after writing 1 to start_init register.  Chips: BB_A0 BB_B0 K2
39445 #define PSWRD2_REG_FIRST_SR_NODES                                                                    0x29d040UL //Access:R    DataWidth:0x1c  Debug only and read only: Each entry provides the first sub request ID in 4 VQs. SR ID of 0x7f is NULL and means there is no sub request in this VQ in PSWRD. The reset value is the one expected in idle check except for the Timers VQ (VQ3).  Chips: BB_A0 BB_B0 K2
39446 #define PSWRD2_REG_FIRST_SR_NODES_SIZE                                                               8
39447 #define PSWRD2_REG_MASK_ERROR_TO_CLIENTS                                                             0x29d060UL //Access:RW   DataWidth:0x10  Debug only: '1' indicates that error indication is masked towards the corresponding client.  Chips: BB_A0 BB_B0 K2
39448 #define PSWRD2_REG_CONF11                                                                            0x29d064UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39449     #define PSWRD2_REG_CONF11_ERROR_PATTERN                                                          (0xffff<<0) // Data pattern that should override the data in case of an error. Duplicated 4 times to create 64 bit data. Can be deaddeaddeaddead for example.
39450     #define PSWRD2_REG_CONF11_ERROR_PATTERN_SHIFT                                                    0
39451     #define PSWRD2_REG_CONF11_OVERRIDE_DATA_WHEN_ERROR                                               (0x1<<16) // 1 indicates to override the data to the client in case of an error and use the error pattern. 0 indicates not to override the data. Arrowhead: The reset value of 1 should not be changed. It can cause Xs on the outputs - CQ79817.
39452     #define PSWRD2_REG_CONF11_OVERRIDE_DATA_WHEN_ERROR_SHIFT                                         16
39453     #define PSWRD2_REG_CONF11_OVERRIDE_LAST_CYCLE_ONLY                                               (0x1<<17) // Meaningful only when override_data_when_error is 1. 1 indicates to override the data to the client in case of an error only in the last request cycle. 0 indicates to override the data from the time the error indication arrives to delivery sub-block until end of packet. Note that the override may start a few cycles before or after the last data cycle that arrived from PGLUE. Arrowhead: The reset value of 0 should not be changed. It can cause Xs on the outputs - CQ79817.
39454     #define PSWRD2_REG_CONF11_OVERRIDE_LAST_CYCLE_ONLY_SHIFT                                         17
39455 #define PSWRD2_REG_CPL_ERR_DETAILS                                                                   0x29d068UL //Access:R    DataWidth:0x1f  Details of first request with error on receive side: [15:0] - Echo ID. [28:16] - sub-request length minus 1. [29] - first SR. [30] - last SR.  Chips: BB_A0 BB_B0 K2
39456 #define PSWRD2_REG_CPL_ERR_DETAILS2                                                                  0x29d06cUL //Access:R    DataWidth:0xb   Details of first request with error on receive side: [4:0] - VQ ID. [9:5] - client ID. [10] - valid - indicates if there was a completion error since the last time this register was read.  Chips: BB_A0 BB_B0 K2
39457 #define PSWRD2_REG_CPL_ERR_DETAILS_CLR                                                               0x29d070UL //Access:W    DataWidth:0x1   Writing to this register clears cpl_err_details and cpl_err_details2 and enables logging new error details.  Chips: BB_A0 BB_B0 K2
39458 #define PSWRD2_REG_ARB_DELAY                                                                         0x29d074UL //Access:RW   DataWidth:0x4   Debug only: The arbiter delay. The delivery port waits ARB_DELAY cycles before asserting 'port_is_idle'. This value is based on implementation and should not be changed.  Chips: BB_A0 BB_B0 K2
39459 #define PSWRD2_REG_PBF_IN_SEPARATE_VQ                                                                0x29d078UL //Access:RW   DataWidth:0x1   1' indicates that the PBF has a separate VQ and uses VQ4. '0' indicates it shares VQ9 with SDM clients. This field should be consistent with PBF_REGISTERS_PCI_VOQ_ID.PCI_VOQ_ID .  Chips: BB_A0 BB_B0 K2
39460 #define PSWRD2_REG_PORT_IS_IDLE_0                                                                    0x29d07cUL //Access:R    DataWidth:0x1   Debug only: Indication if delivery ports are idle.  Chips: BB_A0 BB_B0 K2
39461 #define PSWRD2_REG_PORT_IS_IDLE_1                                                                    0x29d080UL //Access:R    DataWidth:0x1   Debug only: Indication if delivery ports are idle.  Chips: BB_A0 BB_B0 K2
39462 #define PSWRD2_REG_ECO_RESERVED                                                                      0x29d084UL //Access:RW   DataWidth:0x14  Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
39463 #define PSWRD2_REG_PBF_SWAP_MODE                                                                     0x29d0c0UL //Access:RW   DataWidth:0x2   PBF byte swapping mode configuration for master read requests.  Chips: BB_A0 BB_B0 K2
39464 #define PSWRD2_REG_QM_SWAP_MODE                                                                      0x29d0c4UL //Access:RW   DataWidth:0x2   QM byte swapping mode configuration for master read requests.  Chips: BB_A0 BB_B0 K2
39465 #define PSWRD2_REG_TM_SWAP_MODE                                                                      0x29d0c8UL //Access:RW   DataWidth:0x2   TM byte swapping mode configuration for master read requests.  Chips: BB_A0 BB_B0 K2
39466 #define PSWRD2_REG_SRC_SWAP_MODE                                                                     0x29d0ccUL //Access:RW   DataWidth:0x2   SRC byte swapping mode configuration for master read requests.  Chips: BB_A0 BB_B0 K2
39467 #define PSWRD2_REG_CDURD_SWAP_MODE                                                                   0x29d0d0UL //Access:RW   DataWidth:0x2   CDU byte swapping mode configuration for master read requests.  Chips: BB_A0 BB_B0 K2
39468 #define PSWRD2_REG_PTU_SWAP_MODE                                                                     0x29d0d4UL //Access:RW   DataWidth:0x2   PTU byte swapping mode configuration for master read requests.  Chips: BB_A0 BB_B0 K2
39469 #define PSWRD2_REG_ALMOST_FULL_0                                                                     0x29d0e0UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39470 #define PSWRD2_REG_ALMOST_FULL_1                                                                     0x29d0e4UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39471 #define PSWRD2_REG_ALMOST_FULL_2                                                                     0x29d0e8UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39472 #define PSWRD2_REG_ALMOST_FULL_3                                                                     0x29d0ecUL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39473 #define PSWRD2_REG_ALMOST_FULL_4                                                                     0x29d0f0UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39474 #define PSWRD2_REG_ALMOST_FULL_5                                                                     0x29d0f4UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39475 #define PSWRD2_REG_ALMOST_FULL_6                                                                     0x29d0f8UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39476 #define PSWRD2_REG_ALMOST_FULL_7                                                                     0x29d0fcUL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39477 #define PSWRD2_REG_ALMOST_FULL_8                                                                     0x29d100UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39478 #define PSWRD2_REG_ALMOST_FULL_9                                                                     0x29d104UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39479 #define PSWRD2_REG_ALMOST_FULL_10                                                                    0x29d108UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39480 #define PSWRD2_REG_ALMOST_FULL_11                                                                    0x29d10cUL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39481 #define PSWRD2_REG_ALMOST_FULL_12                                                                    0x29d110UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39482 #define PSWRD2_REG_ALMOST_FULL_13                                                                    0x29d114UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39483 #define PSWRD2_REG_ALMOST_FULL_14                                                                    0x29d118UL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39484 #define PSWRD2_REG_ALMOST_FULL_15                                                                    0x29d11cUL //Access:R    DataWidth:0x1   Debug only: The 'almost full' indication from each fifo (gives indication about backpressure).  Chips: BB_A0 BB_B0 K2
39485 #define PSWRD2_REG_ALMOST_FULL_THR_HIGH                                                              0x29d120UL //Access:RW   DataWidth:0x5   Debug only: If more than this Number of entries are used in the clock synchronization FIFO; it asserts the 'almost full' bit. This number is common to all clock synchronization FIFOs except PBF, CDU and PRM. This value is based on implementation and should not be changed.  Chips: BB_A0 BB_B0 K2
39486 #define PSWRD2_REG_ALMOST_FULL_THR_LOW                                                               0x29d124UL //Access:RW   DataWidth:0x5   Debug only: If less or equal than this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for all clients except PBF, CDU and PRM. It should be equal or smaller to the almost full high consiguration.  Chips: BB_A0 BB_B0 K2
39487 #define PSWRD2_REG_ALMOST_FULL_THR_HIGH_CDU                                                          0x29d128UL //Access:RW   DataWidth:0x5   Debug only: If more than this Number of entries are used in the CDU clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost full high configuration for CDU.  Chips: BB_A0 BB_B0 K2
39488 #define PSWRD2_REG_ALMOST_FULL_THR_LOW_CDU                                                           0x29d12cUL //Access:RW   DataWidth:0x5   Debug only: If less or equal than this Number of entries are used in the CDU clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for CDU. It should be equal or smaller to the almost full high consiguration.  Chips: BB_A0 BB_B0 K2
39489 #define PSWRD2_REG_ALMOST_FULL_THR_HIGH_PBF                                                          0x29d130UL //Access:RW   DataWidth:0x7   Debug only: If more than this Number of entries are used in the PBF clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost full high configuration for PBF.  Chips: BB_A0 BB_B0 K2
39490 #define PSWRD2_REG_ALMOST_FULL_THR_LOW_PBF                                                           0x29d134UL //Access:RW   DataWidth:0x7   Debug only: If less or equal than this Number of entries are used in the PBF clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for PBF It should be equal or smaller to the almost full high consiguration.  Chips: BB_A0 BB_B0 K2
39491 #define PSWRD2_REG_ALMOST_FULL_THR_HIGH_PRM                                                          0x29d138UL //Access:RW   DataWidth:0x3   Debug only: If more than this Number of entries are used in the PRM clock synchronization FIFO; it asserts the 'almost full' bit. This is the almost full high configuration for PRM.  Chips: BB_A0 BB_B0 K2
39492 #define PSWRD2_REG_ALMOST_FULL_THR_LOW_PRM                                                           0x29d13cUL //Access:RW   DataWidth:0x3   Debug only: If less or equal than this Number of entries are used in the clock synchronization FIFO; it de-asserts the 'almost full' bit. This is the almost full low configuration for PRM. It should be equal or smaller to the almost full high consiguration.  Chips: BB_A0 BB_B0 K2
39493 #define PSWRD2_REG_FIFO_ALMOST_FULL_STICKY                                                           0x29d140UL //Access:R    DataWidth:0x10  Each bit indicates if 'almost full' was asserted since reset from the FIFO towards the delivery module. The clients order is according to the incrementing client IDs of read clients: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF (TDIF); 7 QM; 8 TM; 9 SRC; 10 CDURD; 11 DMAE; 12 MULD (Rfetcher); 13 XYLD; 14 PTU; 15 PRM.  Chips: BB_A0 BB_B0 K2
39494 #define PSWRD2_REG_MAX_FILL_LEVEL1                                                                   0x29d144UL //Access:R    DataWidth:0x20  Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 TSDM; 15:8 MSDM; 23:16 USDM; 31:24 XSDM.  Chips: BB_A0 BB_B0 K2
39495 #define PSWRD2_REG_MAX_FILL_LEVEL2                                                                   0x29d148UL //Access:R    DataWidth:0x20  Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 YSDM; 15:8 PSDM; 23:16 QM; 31:24 TM.  Chips: BB_A0 BB_B0 K2
39496 #define PSWRD2_REG_MAX_FILL_LEVEL3                                                                   0x29d14cUL //Access:R    DataWidth:0x20  Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 SRC; 15:8 CDU; 23:16 DMAE; 31:24 MULD.  Chips: BB_A0 BB_B0 K2
39497 #define PSWRD2_REG_MAX_FILL_LEVEL4                                                                   0x29d150UL //Access:R    DataWidth:0x18  Per-client maximum sync FIFO fill level since reset in 16B lines. 7:0 XYLD. 15:8 PTU. 23:16 PRM.  Chips: BB_A0 BB_B0 K2
39498 #define PSWRD2_REG_MAX_FILL_LEVEL_PBF                                                                0x29d154UL //Access:R    DataWidth:0x8   PBF maximum sync FIFO fill level since reset in 16B lines.  Chips: BB_A0 BB_B0 K2
39499 #define PSWRD2_REG_INT_STS                                                                           0x29d180UL //Access:R    DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39500     #define PSWRD2_REG_INT_STS_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
39501     #define PSWRD2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                   0
39502     #define PSWRD2_REG_INT_STS_SR_FIFO_ERROR                                                         (0x1<<1) // An error in the SR free list FIFO.
39503     #define PSWRD2_REG_INT_STS_SR_FIFO_ERROR_SHIFT                                                   1
39504     #define PSWRD2_REG_INT_STS_BLK_FIFO_ERROR                                                        (0x1<<2) // An error in the blocks free list FIFO.
39505     #define PSWRD2_REG_INT_STS_BLK_FIFO_ERROR_SHIFT                                                  2
39506     #define PSWRD2_REG_INT_STS_PUSH_ERROR                                                            (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
39507     #define PSWRD2_REG_INT_STS_PUSH_ERROR_SHIFT                                                      3
39508     #define PSWRD2_REG_INT_STS_PUSH_PBF_ERROR                                                        (0x1<<4) // An error in the PBF FIFO push interface.
39509     #define PSWRD2_REG_INT_STS_PUSH_PBF_ERROR_SHIFT                                                  4
39510 #define PSWRD2_REG_INT_MASK                                                                          0x29d184UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39511     #define PSWRD2_REG_INT_MASK_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.ADDRESS_ERROR .
39512     #define PSWRD2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                  0
39513     #define PSWRD2_REG_INT_MASK_SR_FIFO_ERROR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.SR_FIFO_ERROR .
39514     #define PSWRD2_REG_INT_MASK_SR_FIFO_ERROR_SHIFT                                                  1
39515     #define PSWRD2_REG_INT_MASK_BLK_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.BLK_FIFO_ERROR .
39516     #define PSWRD2_REG_INT_MASK_BLK_FIFO_ERROR_SHIFT                                                 2
39517     #define PSWRD2_REG_INT_MASK_PUSH_ERROR                                                           (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.PUSH_ERROR .
39518     #define PSWRD2_REG_INT_MASK_PUSH_ERROR_SHIFT                                                     3
39519     #define PSWRD2_REG_INT_MASK_PUSH_PBF_ERROR                                                       (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWRD2_REG_INT_STS.PUSH_PBF_ERROR .
39520     #define PSWRD2_REG_INT_MASK_PUSH_PBF_ERROR_SHIFT                                                 4
39521 #define PSWRD2_REG_INT_STS_WR                                                                        0x29d188UL //Access:WR   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39522     #define PSWRD2_REG_INT_STS_WR_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
39523     #define PSWRD2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                0
39524     #define PSWRD2_REG_INT_STS_WR_SR_FIFO_ERROR                                                      (0x1<<1) // An error in the SR free list FIFO.
39525     #define PSWRD2_REG_INT_STS_WR_SR_FIFO_ERROR_SHIFT                                                1
39526     #define PSWRD2_REG_INT_STS_WR_BLK_FIFO_ERROR                                                     (0x1<<2) // An error in the blocks free list FIFO.
39527     #define PSWRD2_REG_INT_STS_WR_BLK_FIFO_ERROR_SHIFT                                               2
39528     #define PSWRD2_REG_INT_STS_WR_PUSH_ERROR                                                         (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
39529     #define PSWRD2_REG_INT_STS_WR_PUSH_ERROR_SHIFT                                                   3
39530     #define PSWRD2_REG_INT_STS_WR_PUSH_PBF_ERROR                                                     (0x1<<4) // An error in the PBF FIFO push interface.
39531     #define PSWRD2_REG_INT_STS_WR_PUSH_PBF_ERROR_SHIFT                                               4
39532 #define PSWRD2_REG_INT_STS_CLR                                                                       0x29d18cUL //Access:RC   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39533     #define PSWRD2_REG_INT_STS_CLR_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
39534     #define PSWRD2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                               0
39535     #define PSWRD2_REG_INT_STS_CLR_SR_FIFO_ERROR                                                     (0x1<<1) // An error in the SR free list FIFO.
39536     #define PSWRD2_REG_INT_STS_CLR_SR_FIFO_ERROR_SHIFT                                               1
39537     #define PSWRD2_REG_INT_STS_CLR_BLK_FIFO_ERROR                                                    (0x1<<2) // An error in the blocks free list FIFO.
39538     #define PSWRD2_REG_INT_STS_CLR_BLK_FIFO_ERROR_SHIFT                                              2
39539     #define PSWRD2_REG_INT_STS_CLR_PUSH_ERROR                                                        (0x1<<3) // An error in one of the clients' (except PBF) FIFOs push interface.
39540     #define PSWRD2_REG_INT_STS_CLR_PUSH_ERROR_SHIFT                                                  3
39541     #define PSWRD2_REG_INT_STS_CLR_PUSH_PBF_ERROR                                                    (0x1<<4) // An error in the PBF FIFO push interface.
39542     #define PSWRD2_REG_INT_STS_CLR_PUSH_PBF_ERROR_SHIFT                                              4
39543 #define PSWRD2_REG_PRTY_MASK                                                                         0x29d194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
39544     #define PSWRD2_REG_PRTY_MASK_DATAPATH_REGISTERS                                                  (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS.DATAPATH_REGISTERS .
39545     #define PSWRD2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                            0
39546 #define PSWRD2_REG_PRTY_MASK_H_0                                                                     0x29d204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39547     #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
39548     #define PSWRD2_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_SHIFT                                       0
39549     #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT .
39550     #define PSWRD2_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_SHIFT                                       1
39551     #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT                                             (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM019_I_ECC_RF_INT .
39552     #define PSWRD2_REG_PRTY_MASK_H_0_MEM019_I_ECC_RF_INT_SHIFT                                       2
39553     #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT                                             (0x1<<3) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM020_I_ECC_RF_INT .
39554     #define PSWRD2_REG_PRTY_MASK_H_0_MEM020_I_ECC_RF_INT_SHIFT                                       3
39555     #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT                                             (0x1<<4) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM021_I_ECC_RF_INT .
39556     #define PSWRD2_REG_PRTY_MASK_H_0_MEM021_I_ECC_RF_INT_SHIFT                                       4
39557     #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT                                             (0x1<<5) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
39558     #define PSWRD2_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_SHIFT                                       5
39559     #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT                                             (0x1<<6) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT .
39560     #define PSWRD2_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_SHIFT                                       6
39561     #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT                                             (0x1<<7) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT .
39562     #define PSWRD2_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_SHIFT                                       7
39563     #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT                                             (0x1<<8) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
39564     #define PSWRD2_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_SHIFT                                       8
39565     #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT                                             (0x1<<9) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
39566     #define PSWRD2_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT                                       9
39567     #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_A0                                         (0x1<<9) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
39568     #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_A0_SHIFT                                   9
39569     #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_B0                                         (0x1<<10) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
39570     #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_B0_SHIFT                                   10
39571     #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2                                            (0x1<<10) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
39572     #define PSWRD2_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2_SHIFT                                      10
39573     #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_A0                                         (0x1<<10) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
39574     #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_A0_SHIFT                                   10
39575     #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_B0                                         (0x1<<11) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
39576     #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_B0_SHIFT                                   11
39577     #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2                                            (0x1<<11) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
39578     #define PSWRD2_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2_SHIFT                                      11
39579     #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0                                         (0x1<<11) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
39580     #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0_SHIFT                                   11
39581     #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0                                         (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
39582     #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0_SHIFT                                   12
39583     #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                            (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
39584     #define PSWRD2_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                      12
39585     #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_A0                                         (0x1<<12) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
39586     #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_A0_SHIFT                                   12
39587     #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_B0                                         (0x1<<13) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
39588     #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_B0_SHIFT                                   13
39589     #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2                                            (0x1<<13) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
39590     #define PSWRD2_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2_SHIFT                                      13
39591     #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_A0                                         (0x1<<13) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
39592     #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_A0_SHIFT                                   13
39593     #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0                                         (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
39594     #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0_SHIFT                                   14
39595     #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                            (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
39596     #define PSWRD2_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                      14
39597     #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0                                         (0x1<<14) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
39598     #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0_SHIFT                                   14
39599     #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0                                         (0x1<<15) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
39600     #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0_SHIFT                                   15
39601     #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                            (0x1<<15) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
39602     #define PSWRD2_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                      15
39603     #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_A0                                         (0x1<<15) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
39604     #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_A0_SHIFT                                   15
39605     #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_B0                                         (0x1<<16) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
39606     #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_B0_SHIFT                                   16
39607     #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2                                            (0x1<<16) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
39608     #define PSWRD2_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_SHIFT                                      16
39609     #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0                                         (0x1<<16) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
39610     #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0_SHIFT                                   16
39611     #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0                                         (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
39612     #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0_SHIFT                                   17
39613     #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                            (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
39614     #define PSWRD2_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                      17
39615     #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_A0                                         (0x1<<17) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
39616     #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_A0_SHIFT                                   17
39617     #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_B0                                         (0x1<<18) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
39618     #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_B0_SHIFT                                   18
39619     #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2                                            (0x1<<18) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
39620     #define PSWRD2_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_SHIFT                                      18
39621     #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_A0                                         (0x1<<18) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
39622     #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_A0_SHIFT                                   18
39623     #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_B0                                         (0x1<<19) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
39624     #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                   19
39625     #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2                                            (0x1<<19) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
39626     #define PSWRD2_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_SHIFT                                      19
39627     #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0                                         (0x1<<19) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
39628     #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0_SHIFT                                   19
39629     #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0                                         (0x1<<20) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
39630     #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0_SHIFT                                   20
39631     #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                            (0x1<<20) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
39632     #define PSWRD2_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                      20
39633     #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                         (0x1<<20) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
39634     #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                   20
39635     #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0                                         (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
39636     #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                   21
39637     #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                            (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
39638     #define PSWRD2_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                      21
39639     #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0                                         (0x1<<21) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
39640     #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0_SHIFT                                   21
39641     #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0                                         (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
39642     #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0_SHIFT                                   22
39643     #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                            (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
39644     #define PSWRD2_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                      22
39645     #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0                                         (0x1<<22) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
39646     #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0_SHIFT                                   22
39647     #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0                                         (0x1<<23) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
39648     #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0_SHIFT                                   23
39649     #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2                                            (0x1<<23) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
39650     #define PSWRD2_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT                                      23
39651     #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                         (0x1<<23) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
39652     #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                   23
39653     #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                         (0x1<<24) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
39654     #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                   24
39655     #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                            (0x1<<24) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
39656     #define PSWRD2_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                      24
39657     #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0                                         (0x1<<24) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
39658     #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0_SHIFT                                   24
39659     #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0                                         (0x1<<25) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
39660     #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0_SHIFT                                   25
39661     #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                            (0x1<<25) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
39662     #define PSWRD2_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                      25
39663     #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0                                         (0x1<<25) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
39664     #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0_SHIFT                                   25
39665     #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0                                         (0x1<<26) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
39666     #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0_SHIFT                                   26
39667     #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                            (0x1<<26) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
39668     #define PSWRD2_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                      26
39669     #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0                                         (0x1<<26) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
39670     #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0_SHIFT                                   26
39671     #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0                                         (0x1<<27) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
39672     #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0_SHIFT                                   27
39673     #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                            (0x1<<27) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
39674     #define PSWRD2_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                      27
39675     #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0                                         (0x1<<27) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
39676     #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                   27
39677     #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0                                         (0x1<<28) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
39678     #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                   28
39679     #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                            (0x1<<28) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
39680     #define PSWRD2_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                      28
39681     #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0                                         (0x1<<28) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
39682     #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0_SHIFT                                   28
39683     #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0                                         (0x1<<29) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
39684     #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0_SHIFT                                   29
39685     #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                            (0x1<<29) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
39686     #define PSWRD2_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                      29
39687     #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0                                         (0x1<<29) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
39688     #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0_SHIFT                                   29
39689     #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0                                         (0x1<<30) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
39690     #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0_SHIFT                                   30
39691     #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                            (0x1<<30) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
39692     #define PSWRD2_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                      30
39693     #define PSWRD2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                               (0x1<<30) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
39694     #define PSWRD2_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                         30
39695 #define PSWRD2_REG_PRTY_MASK_H_1                                                                     0x29d214UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39696     #define PSWRD2_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY                                               (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
39697     #define PSWRD2_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_SHIFT                                         0
39698     #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_A0                                         (0x1<<0) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
39699     #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                   0
39700     #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_B0                                         (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
39701     #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                   1
39702     #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_K2                                            (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
39703     #define PSWRD2_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_K2_SHIFT                                      1
39704     #define PSWRD2_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY                                               (0x1<<2) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
39705     #define PSWRD2_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_SHIFT                                         2
39706     #define PSWRD2_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY                                               (0x1<<1) // This bit masks, when set, the Parity bit: PSWRD2_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
39707     #define PSWRD2_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_SHIFT                                         1
39708 #define PSWRD2_REG_MEM_ECC_EVENTS                                                                    0x29d248UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
39709 #define PSWRD2_REG_MEM034_I_MEM_DFT_K2                                                               0x29d250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_vq_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39710 #define PSWRD2_REG_MEM032_I_MEM_DFT_K2                                                               0x29d254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_sr_memc.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39711 #define PSWRD2_REG_MEM028_I_MEM_DFT_K2                                                               0x29d258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_completion_context_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39712 #define PSWRD2_REG_MEM033_I_MEM_DFT_K2                                                               0x29d25cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_sr_memd.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
39713 #define PSWRD2_REG_MEM030_I_MEM_DFT_K2                                                               0x29d260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_next_blk_ptr_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39714 #define PSWRD2_REG_MEM029_I_MEM_DFT_K2                                                               0x29d264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_first_blk_ptr_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39715 #define PSWRD2_REG_MEM031_I_MEM_DFT_K2                                                               0x29d268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_sr_free_list_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39716 #define PSWRD2_REG_MEM027_I_MEM_DFT_K2                                                               0x29d26cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_block_free_list_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39717 #define PSWRD2_REG_MEM026_I_MEM_DFT_K2                                                               0x29d270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.i_atc_entryid_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39718 #define PSWRD2_REG_MEM017_I_MEM_DFT_K2                                                               0x29d274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_32_GEN_FOR[0].i_tetris_32b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39719 #define PSWRD2_REG_MEM018_I_MEM_DFT_K2                                                               0x29d278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_32_GEN_FOR[1].i_tetris_32b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39720 #define PSWRD2_REG_MEM019_I_MEM_DFT_K2                                                               0x29d27cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_64_GEN_FOR[0].i_tetris_64b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39721 #define PSWRD2_REG_MEM020_I_MEM_DFT_K2                                                               0x29d280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_64_GEN_FOR[1].i_tetris_64b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39722 #define PSWRD2_REG_MEM021_I_MEM_DFT_K2                                                               0x29d284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_64_GEN_FOR[2].i_tetris_64b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39723 #define PSWRD2_REG_MEM022_I_MEM_DFT_K2                                                               0x29d288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_64_GEN_FOR[3].i_tetris_64b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39724 #define PSWRD2_REG_MEM023_I_MEM_DFT_K2                                                               0x29d28cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_64_GEN_FOR[4].i_tetris_64b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39725 #define PSWRD2_REG_MEM024_I_MEM_DFT_K2                                                               0x29d290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_64_GEN_FOR[5].i_tetris_64b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39726 #define PSWRD2_REG_MEM025_I_MEM_DFT_K2                                                               0x29d294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.TETRIS_64_GEN_FOR[6].i_tetris_64b.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
39727 #define PSWRD2_REG_MEM001_I_MEM_DFT_K2                                                               0x29d298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[0].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39728 #define PSWRD2_REG_MEM007_I_MEM_DFT_K2                                                               0x29d29cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[1].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39729 #define PSWRD2_REG_MEM008_I_MEM_DFT_K2                                                               0x29d2a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[2].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39730 #define PSWRD2_REG_MEM009_I_MEM_DFT_K2                                                               0x29d2a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[3].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39731 #define PSWRD2_REG_MEM010_I_MEM_DFT_K2                                                               0x29d2a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[4].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39732 #define PSWRD2_REG_MEM011_I_MEM_DFT_K2                                                               0x29d2acUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[5].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39733 #define PSWRD2_REG_MEM012_I_MEM_DFT_K2                                                               0x29d2b0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[7].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39734 #define PSWRD2_REG_MEM013_I_MEM_DFT_K2                                                               0x29d2b4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[8].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39735 #define PSWRD2_REG_MEM014_I_MEM_DFT_K2                                                               0x29d2b8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[9].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39736 #define PSWRD2_REG_MEM002_I_MEM_DFT_K2                                                               0x29d2bcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[10].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39737 #define PSWRD2_REG_MEM003_I_MEM_DFT_K2                                                               0x29d2c0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[11].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39738 #define PSWRD2_REG_MEM004_I_MEM_DFT_K2                                                               0x29d2c4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[12].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39739 #define PSWRD2_REG_MEM005_I_MEM_DFT_K2                                                               0x29d2c8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[13].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39740 #define PSWRD2_REG_MEM006_I_MEM_DFT_K2                                                               0x29d2ccUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_FOR[14].SYNC_FIFO_GEN_REGULAR_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39741 #define PSWRD2_REG_MEM015_I_MEM_DFT_K2                                                               0x29d2d0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_PBF_FOR[6].SYNC_FIFO_GEN_PBF_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39742 #define PSWRD2_REG_MEM016_I_MEM_DFT_K2                                                               0x29d2d4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswrd.SYNC_FIFO_GEN_PRM_FOR[15].SYNC_FIFO_GEN_PRM_IF.i_m_1w1r_2clks_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
39743 #define PSWRD2_REG_DBG_SELECT                                                                        0x29d400UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
39744 #define PSWRD2_REG_DBG_DWORD_ENABLE                                                                  0x29d404UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
39745 #define PSWRD2_REG_DBG_SHIFT                                                                         0x29d408UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
39746 #define PSWRD2_REG_DBG_FORCE_VALID                                                                   0x29d40cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
39747 #define PSWRD2_REG_DBG_FORCE_FRAME                                                                   0x29d410UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
39748 #define PSWRD2_REG_DBG_OUT_DATA                                                                      0x29d420UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
39749 #define PSWRD2_REG_DBG_OUT_DATA_SIZE                                                                 8
39750 #define PSWRD2_REG_DBG_OUT_VALID                                                                     0x29d440UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
39751 #define PSWRD2_REG_DBG_OUT_FRAME                                                                     0x29d444UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
39752 #define PSWRD2_REG_DISABLE_INPUTS                                                                    0x29d460UL //Access:RW   DataWidth:0x1   When '1'; inputs to the PSWRD block are ignored.  Chips: BB_A0 BB_B0 K2
39753 #define PSWRD2_REG_SR_NUM_CFG                                                                        0x29d464UL //Access:RW   DataWidth:0x7   Debug only: Total number of available PCI read sub-requests. Must be bigger than 1. Normally should not be changed. Should have identical value to rq_sr_num_cfg.  Chips: BB_A0 BB_B0 K2
39754 #define PSWRD2_REG_BLK_NUM_CFG                                                                       0x29d468UL //Access:RW   DataWidth:0x9   Debug only: Total number of available blocks in Tetris Buffer. Must be bigger than 6. Normally should not be changed. Should have identical value to rq_blk_num_cfg.  Chips: BB_A0 BB_B0 K2
39755 #define PSWRD2_REG_ATC_GLOBAL_ENABLE                                                                 0x29d46cUL //Access:RW   DataWidth:0x1   Global ATC enable bit. When reset all ATC logic is disabled within the PSWRD. 'ATC entry ID' interface from PSWRQ is ignored and 'ATC RCPL Done' interface to ATC is not generated. The value of this register must be the same as PSWRQ_ATC_GLOBAL_ENABLE. This value must be '1' when ATC capability is enabled in PCIe core.  Chips: BB_A0 BB_B0 K2
39756 #define PSWRD2_REG_CONTINUE_SERVING_PBF                                                              0x29d470UL //Access:RW   DataWidth:0x1   This register defines the delivery port behavior when finishing delivering a request to the PBF and the data for the next request is already in the Tetris buffer. 0 - The delivery port continues delivering the next PBF request only if the second delivery port is idle. This is the behavior in E1 E1H and E2. 1 - The delivery port always continues delivering the next PBF request. This is more efficient since about 11 arbitration cycles are not wasted.  Chips: BB_A0 BB_B0 K2
39757 #define PSWRD2_REG_USDM_ADDITIONAL_REQUESTS                                                          0x29d474UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to deliver to the client without doing arbitration again. This configuration is for all clients except PBF (for PBF the number of additional requests to deliver is unlimited). This feature can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39758 #define PSWRD2_REG_XSDM_ADDITIONAL_REQUESTS                                                          0x29d478UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39759 #define PSWRD2_REG_MSDM_ADDITIONAL_REQUESTS                                                          0x29d47cUL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39760 #define PSWRD2_REG_YSDM_ADDITIONAL_REQUESTS                                                          0x29d480UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39761 #define PSWRD2_REG_PSDM_ADDITIONAL_REQUESTS                                                          0x29d484UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39762 #define PSWRD2_REG_TSDM_ADDITIONAL_REQUESTS                                                          0x29d488UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39763 #define PSWRD2_REG_QM_ADDITIONAL_REQUESTS                                                            0x29d48cUL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39764 #define PSWRD2_REG_TM_ADDITIONAL_REQUESTS                                                            0x29d490UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39765 #define PSWRD2_REG_SRC_ADDITIONAL_REQUESTS                                                           0x29d494UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39766 #define PSWRD2_REG_CDU_ADDITIONAL_REQUESTS                                                           0x29d498UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39767 #define PSWRD2_REG_DMAE_ADDITIONAL_REQUESTS                                                          0x29d49cUL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39768 #define PSWRD2_REG_MULD_ADDITIONAL_REQUESTS                                                          0x29d4a0UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39769 #define PSWRD2_REG_XYLD_ADDITIONAL_REQUESTS                                                          0x29d4a4UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39770 #define PSWRD2_REG_PTU_ADDITIONAL_REQUESTS                                                           0x29d4a8UL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39771 #define PSWRD2_REG_PRM_ADDITIONAL_REQUESTS                                                           0x29d4acUL //Access:RW   DataWidth:0x2   When finishing delivering a request to this client; this register determines the number of additional requests to serve in this port without doing arbitration again. This can save arbitration overhead.  Chips: BB_A0 BB_B0 K2
39772 #define PSWHST2_REG_HEADER_FIFO_STATUS                                                               0x29e040UL //Access:R    DataWidth:0x7   Debug only: Number of used entries in the header FIFO.  Chips: BB_A0 BB_B0 K2
39773 #define PSWHST2_REG_DATA_FIFO_STATUS                                                                 0x29e044UL //Access:R    DataWidth:0x7   Debug only: Number of used entries in the data FIFO.  Chips: BB_A0 BB_B0 K2
39774 #define PSWHST2_REG_HEADER_FIFO_MAX_ENTRIES                                                          0x29e048UL //Access:R    DataWidth:0x7   Debug only: Maximum number of entries that were used in the header FIFO.  Chips: BB_A0 BB_B0 K2
39775 #define PSWHST2_REG_DATA_FIFO_MAX_ENTRIES                                                            0x29e04cUL //Access:R    DataWidth:0x7   Debug only: Maximum number of entries that were used in the data FIFO.  Chips: BB_A0 BB_B0 K2
39776 #define PSWHST2_REG_DBGSYN_ALMOST_FULL_THR                                                           0x29e050UL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed. This value is an output from PSWHST to pxp_dbgsyn.  Chips: BB_A0 BB_B0 K2
39777 #define PSWHST2_REG_ECO_RESERVED                                                                     0x29e054UL //Access:RW   DataWidth:0x5   Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
39778 #define PSWHST2_REG_DBG_SELECT                                                                       0x29e058UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
39779 #define PSWHST2_REG_DBG_DWORD_ENABLE                                                                 0x29e05cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
39780 #define PSWHST2_REG_DBG_SHIFT                                                                        0x29e060UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
39781 #define PSWHST2_REG_DBG_FORCE_VALID                                                                  0x29e064UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
39782 #define PSWHST2_REG_DBG_FORCE_FRAME                                                                  0x29e068UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
39783 #define PSWHST2_REG_DBG_OUT_DATA                                                                     0x29e080UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
39784 #define PSWHST2_REG_DBG_OUT_DATA_SIZE                                                                8
39785 #define PSWHST2_REG_DBG_OUT_VALID                                                                    0x29e0a0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
39786 #define PSWHST2_REG_DBG_OUT_FRAME                                                                    0x29e0a4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
39787 #define PSWHST2_REG_INT_STS                                                                          0x29e180UL //Access:R    DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39788     #define PSWHST2_REG_INT_STS_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
39789     #define PSWHST2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                  0
39790     #define PSWHST2_REG_INT_STS_HST_HEADER_FIFO_ERR                                                  (0x1<<1) // An error in the header clock sync  FIFO.
39791     #define PSWHST2_REG_INT_STS_HST_HEADER_FIFO_ERR_SHIFT                                            1
39792     #define PSWHST2_REG_INT_STS_HST_DATA_FIFO_ERR                                                    (0x1<<2) // An error in the data clock sync  FIFO.
39793     #define PSWHST2_REG_INT_STS_HST_DATA_FIFO_ERR_SHIFT                                              2
39794     #define PSWHST2_REG_INT_STS_HST_CPL_FIFO_ERR                                                     (0x1<<3) // An error in the completion clock sync  FIFO.
39795     #define PSWHST2_REG_INT_STS_HST_CPL_FIFO_ERR_SHIFT                                               3
39796     #define PSWHST2_REG_INT_STS_HST_IREQ_FIFO_ERR                                                    (0x1<<4) // An error in the ireq clock sync  FIFO.
39797     #define PSWHST2_REG_INT_STS_HST_IREQ_FIFO_ERR_SHIFT                                              4
39798 #define PSWHST2_REG_INT_MASK                                                                         0x29e184UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39799     #define PSWHST2_REG_INT_MASK_ADDRESS_ERROR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.ADDRESS_ERROR .
39800     #define PSWHST2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                 0
39801     #define PSWHST2_REG_INT_MASK_HST_HEADER_FIFO_ERR                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_HEADER_FIFO_ERR .
39802     #define PSWHST2_REG_INT_MASK_HST_HEADER_FIFO_ERR_SHIFT                                           1
39803     #define PSWHST2_REG_INT_MASK_HST_DATA_FIFO_ERR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_DATA_FIFO_ERR .
39804     #define PSWHST2_REG_INT_MASK_HST_DATA_FIFO_ERR_SHIFT                                             2
39805     #define PSWHST2_REG_INT_MASK_HST_CPL_FIFO_ERR                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_CPL_FIFO_ERR .
39806     #define PSWHST2_REG_INT_MASK_HST_CPL_FIFO_ERR_SHIFT                                              3
39807     #define PSWHST2_REG_INT_MASK_HST_IREQ_FIFO_ERR                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWHST2_REG_INT_STS.HST_IREQ_FIFO_ERR .
39808     #define PSWHST2_REG_INT_MASK_HST_IREQ_FIFO_ERR_SHIFT                                             4
39809 #define PSWHST2_REG_INT_STS_WR                                                                       0x29e188UL //Access:WR   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39810     #define PSWHST2_REG_INT_STS_WR_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
39811     #define PSWHST2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                               0
39812     #define PSWHST2_REG_INT_STS_WR_HST_HEADER_FIFO_ERR                                               (0x1<<1) // An error in the header clock sync  FIFO.
39813     #define PSWHST2_REG_INT_STS_WR_HST_HEADER_FIFO_ERR_SHIFT                                         1
39814     #define PSWHST2_REG_INT_STS_WR_HST_DATA_FIFO_ERR                                                 (0x1<<2) // An error in the data clock sync  FIFO.
39815     #define PSWHST2_REG_INT_STS_WR_HST_DATA_FIFO_ERR_SHIFT                                           2
39816     #define PSWHST2_REG_INT_STS_WR_HST_CPL_FIFO_ERR                                                  (0x1<<3) // An error in the completion clock sync  FIFO.
39817     #define PSWHST2_REG_INT_STS_WR_HST_CPL_FIFO_ERR_SHIFT                                            3
39818     #define PSWHST2_REG_INT_STS_WR_HST_IREQ_FIFO_ERR                                                 (0x1<<4) // An error in the ireq clock sync  FIFO.
39819     #define PSWHST2_REG_INT_STS_WR_HST_IREQ_FIFO_ERR_SHIFT                                           4
39820 #define PSWHST2_REG_INT_STS_CLR                                                                      0x29e18cUL //Access:RC   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
39821     #define PSWHST2_REG_INT_STS_CLR_ADDRESS_ERROR                                                    (0x1<<0) // Signals an unknown address to the rf module.
39822     #define PSWHST2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                              0
39823     #define PSWHST2_REG_INT_STS_CLR_HST_HEADER_FIFO_ERR                                              (0x1<<1) // An error in the header clock sync  FIFO.
39824     #define PSWHST2_REG_INT_STS_CLR_HST_HEADER_FIFO_ERR_SHIFT                                        1
39825     #define PSWHST2_REG_INT_STS_CLR_HST_DATA_FIFO_ERR                                                (0x1<<2) // An error in the data clock sync  FIFO.
39826     #define PSWHST2_REG_INT_STS_CLR_HST_DATA_FIFO_ERR_SHIFT                                          2
39827     #define PSWHST2_REG_INT_STS_CLR_HST_CPL_FIFO_ERR                                                 (0x1<<3) // An error in the completion clock sync  FIFO.
39828     #define PSWHST2_REG_INT_STS_CLR_HST_CPL_FIFO_ERR_SHIFT                                           3
39829     #define PSWHST2_REG_INT_STS_CLR_HST_IREQ_FIFO_ERR                                                (0x1<<4) // An error in the ireq clock sync  FIFO.
39830     #define PSWHST2_REG_INT_STS_CLR_HST_IREQ_FIFO_ERR_SHIFT                                          4
39831 #define PSWHST2_REG_PRTY_MASK                                                                        0x29e194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
39832     #define PSWHST2_REG_PRTY_MASK_DATAPATH_REGISTERS                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST2_REG_PRTY_STS.DATAPATH_REGISTERS .
39833     #define PSWHST2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                           0
39834 #define PSWHST_REG_ZONE_PERM_TABLE_INIT                                                              0x2a0000UL //Access:RW   DataWidth:0x1   Start the Init sequence for the zone permission table.  Chips: BB_A0 BB_B0 K2
39835 #define PSWHST_REG_ZONE_PERM_TABLE_INIT_DONE                                                         0x2a0004UL //Access:RC   DataWidth:0x1   Done indication for the permission table's init sequence. Driver should check the value of this register is 1 some time after it wrote 1 to zone_perm_table_init.  Chips: BB_A0 BB_B0 K2
39836 #define PSWHST_REG_DISCARD_INTERNAL_WRITES                                                           0x2a0040UL //Access:RW   DataWidth:0x1   When 1; new internal writes arriving to the block are discarded. Should be used for close the gates.  Chips: BB_A0 BB_B0 K2
39837 #define PSWHST_REG_DISCARD_DOORBELLS                                                                 0x2a0044UL //Access:RW   DataWidth:0x1   When 1; doorbells are discarded and not passed to doorbell queue block. Should be used for close the gates.  Chips: BB_A0 BB_B0 K2
39838 #define PSWHST_REG_DISCARD_P2M                                                                       0x2a0048UL //Access:RW   DataWidth:0x1   When 1; p2m are discarded and not passed to p2m queue block. Should be used for close the gates.  Chips: BB_A0 BB_B0 K2
39839 #define PSWHST_REG_DISCARD_INTERNAL_WRITES_STATUS                                                    0x2a004cUL //Access:R    DataWidth:0x9   Debug only: A bit mask for all PSWHST internal write clients. '1' means this PSWHST is discarding inputs from this client. Each bit should update accoring to 'hst_discard_internal_writes' register when the state machine is idle.  Chips: BB_A0 BB_B0 K2
39840 #define PSWHST_REG_DISCARD_DOORBELLS_STATUS                                                          0x2a0050UL //Access:R    DataWidth:0x1   Debug only: '1' means this PSWHST is discarding doorbells. This bit should update accoring to 'hst_discard_doorbells' register when the state machine is idle.  Chips: BB_A0 BB_B0 K2
39841 #define PSWHST_REG_DISCARD_P2M_STATUS                                                                0x2a0054UL //Access:R    DataWidth:0x1   Debug only: '1' means this PSWHST is discarding p2m. This bit should update accoring to 'hst_discard_p2m' register when the state machine is idle.  Chips: BB_A0 BB_B0 K2
39842 #define PSWHST_REG_ARB_IS_IDLE                                                                       0x2a0058UL //Access:R    DataWidth:0x2   Debug only: A bit per arbiter-engine indicating if the engine is idle. Idle means the engine is not sending request (and therefore no credits from the target means the arbiter-engine is idle which is different than E3).  Chips: BB_A0 BB_B0 K2
39843 #define PSWHST_REG_VF_DISABLED_ERROR_DATA                                                            0x2a005cUL //Access:R    DataWidth:0x12  The FID of the first access to a disabled VF; the format is [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.  Chips: BB_A0 BB_B0 K2
39844 #define PSWHST_REG_VF_DISABLED_ERROR_VALID                                                           0x2a0060UL //Access:R    DataWidth:0x1   1 - An error request is logged.  Chips: BB_A0 BB_B0 K2
39845 #define PSWHST_REG_VF_DISABLED_ERROR_ADDRESS                                                         0x2a0064UL //Access:R    DataWidth:0x20  The address of the first access to a disabled VF.  Chips: BB_A0 BB_B0 K2
39846 #define PSWHST_REG_INCORRECT_ACCESS_DATA                                                             0x2a0068UL //Access:R    DataWidth:0x20  The data of the first incorrect access. the format is: [31:26] - RSV [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.  Chips: BB_A0 BB_B0 K2
39847 #define PSWHST_REG_INCORRECT_ACCESS_LENGTH                                                           0x2a006cUL //Access:R    DataWidth:0x7   The data of the first incorrect access. the format is: [6:0] - length in DWs. The data is written only when the valid bit is reset. and it is stays stable until it is reset by the read from interrupt_clr register.  Chips: BB_A0 BB_B0 K2
39848 #define PSWHST_REG_INCORRECT_ACCESS_VALID                                                            0x2a0070UL //Access:R    DataWidth:0x1   1 - An incorrect access is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1).  Chips: BB_A0 BB_B0 K2
39849 #define PSWHST_REG_INCORRECT_ACCESS_ADDRESS                                                          0x2a0074UL //Access:R    DataWidth:0x20  The address of the first incorrect access (length and alignement combination).  Chips: BB_A0 BB_B0 K2
39850 #define PSWHST_REG_PER_VIOLATION_VALID                                                               0x2a0078UL //Access:R    DataWidth:0x1   1- permission violation data is logged. The valid bit is reset when the relevant interrupt register is read.  Chips: BB_A0 BB_B0 K2
39851 #define PSWHST_REG_PER_VIOLATION_DATA                                                                0x2a007cUL //Access:R    DataWidth:0x11  Log of the permission violation: {QID[8:0];VFID[7:0]}.  Chips: BB_A0 BB_B0 K2
39852 #define PSWHST_REG_SOURCE_SDM_CREDITS                                                                0x2a0080UL //Access:RW   DataWidth:0x2   Number of credits for source SDM in internal write interface (common to all SDMs except USDM). PSWHST issues an attention if more credits are consumed.  Chips: BB_A0 BB_B0 K2
39853 #define PSWHST_REG_SOURCE_PBF_CREDITS                                                                0x2a0084UL //Access:RW   DataWidth:0x2   Number of credits for source SDM in internal write interface. PSWHST issues an attention if more credits are consumed.  Chips: BB_A0 BB_B0 K2
39854 #define PSWHST_REG_SOURCE_QM_CREDITS                                                                 0x2a0088UL //Access:RW   DataWidth:0x3   Number of credits for source SDM in internal write interface. PSWHST issues an attention if more credits are consumed.  Chips: BB_A0 BB_B0 K2
39855 #define PSWHST_REG_SOURCE_CREDITS_AVAIL                                                              0x2a008cUL //Access:R    DataWidth:0x13  Number of available credits for source in internal write interface: [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm; [11:10] tsdm; [13:12] pbf; [16:14] qm; [18:17] nig.  Chips: BB_A0 BB_B0 K2
39856 #define PSWHST_REG_SOURCE_CREDIT_VIOL_DATA                                                           0x2a0090UL //Access:R    DataWidth:0x4   The data of the first internal write source that consumed more than its allowed credits. the format is: [3:0] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF; 7 QM; 8 NIG).  Chips: BB_A0 BB_B0 K2
39857 #define PSWHST_REG_SOURCE_CREDIT_VIOL_VALID                                                          0x2a0094UL //Access:R    DataWidth:0x1   1 - A source credit violation is logged. The valid bit is reset when the relevant interrupt register is read (PXP_REG_INT_STS_CLR_1).  Chips: BB_A0 BB_B0 K2
39858 #define PSWHST_REG_DEST_SDM_CREDITS                                                                  0x2a0098UL //Access:RW   DataWidth:0x2   Number of credits for destination SDM in target write interface (common to all SDMs).  Chips: BB_A0 BB_B0 K2
39859 #define PSWHST_REG_DEST_IGU_CREDITS                                                                  0x2a009cUL //Access:RW   DataWidth:0x2   Number of credits for destination IGU in target write interface.  Chips: BB_A0 BB_B0 K2
39860 #define PSWHST_REG_DEST_CAU_CREDITS                                                                  0x2a00a0UL //Access:RW   DataWidth:0x2   Number of credits for destination IGU in target write interface.  Chips: BB_A0 BB_B0 K2
39861 #define PSWHST_REG_DEST_CREDITS_AVAIL                                                                0x2a00a4UL //Access:R    DataWidth:0x10  Number of available credits for destination in internal write interface. [1:0] usdm; [3:2] xsdm; [5:4] msdm; [7:6] ysdm; [9:8] psdm; [11:10] tsdm; [13:12] igu; [15:14] cau.  Chips: BB_A0 BB_B0 K2
39862 #define PSWHST_REG_TIMEOUT                                                                           0x2a00a8UL //Access:RW   DataWidth:0x1e  Number of cycles to wait before entering drain mode.  Chips: BB_A0 BB_B0 K2
39863 #define PSWHST_REG_IS_IN_DRAIN_MODE                                                                  0x2a00acUL //Access:R    DataWidth:0x1   1 - PSWHST is in drain mode.  Chips: BB_A0 BB_B0 K2
39864 #define PSWHST_REG_EXIT_DRAIN_MODE                                                                   0x2a00b0UL //Access:W    DataWidth:0x1   Writing 1 to this register indicates PSWHST to exit drain mode.  Chips: BB_A0 BB_B0 K2
39865 #define PSWHST_REG_TIMEOUT_DATA                                                                      0x2a00b4UL //Access:R    DataWidth:0x20  The data of the request that hst_timeout happened while it was processed. the format is (for non P2M): [31:26] - length in DWs; [25:18] - byte enable; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 HC; 7 GRC; 8 DQ; 9 ATC; 10 RESERVED SPACE); [0] - w_nr(0-read req; 1- write req). for p2m: [24:18] VDM length; [17:14] - pfid; [13:6] - vfid; [5] - vf_valid; [4:1] - client (P2M); [0] - w_nr(0-read req; 1- write req). The data is written only when the valid bit is reset. and it is stays stable until exiting drain mode.  Chips: BB_A0 BB_B0 K2
39866 #define PSWHST_REG_TIMEOUT_VALID                                                                     0x2a00b8UL //Access:R    DataWidth:0x1   1 - An hst timeout data is logged. The valid bit is reset when exiting drain mode (writing to hst_exit_drain_mode).  Chips: BB_A0 BB_B0 K2
39867 #define PSWHST_REG_TIMEOUT_ADDRESS                                                                   0x2a00bcUL //Access:R    DataWidth:0x20  The address of the first incorrect access (length and alignement combination). not relevant for P2M logging  Chips: BB_A0 BB_B0 K2
39868 #define PSWHST_REG_SOURCE_USDM_CREDITS                                                               0x2a00c0UL //Access:RW   DataWidth:0x2   Number of credits for source USDM in internal write interface. PSWHST issues an attention if more credits are consumed. Added in BB-B0 due to pipeline.  Chips: BB_B0 K2
39869 #define PSWHST_REG_HOST_STRICT_PRIORITY                                                              0x2a00c8UL //Access:RW   DataWidth:0x1   When 1; host requests have strict priority on internal write requests; as in A0. When 0; arbiter alternately chooses host requests and internal write requests.  Chips: BB_A0 BB_B0 K2
39870 #define PSWHST_REG_SDM_MAX_LENGTH                                                                    0x2a00ccUL //Access:RW   DataWidth:0x6   Maximum write transaction data in DWs that is sent to SDMs and IGU. Write requests with bigger length are discarded in PSWHST.  Chips: BB_A0 BB_B0 K2
39871 #define PSWHST_REG_ECO_RESERVED                                                                      0x2a00d0UL //Access:RW   DataWidth:0xa   Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
39872 #define PSWHST_REG_USDM_SWAP_MODE                                                                    0x2a00d4UL //Access:RW   DataWidth:0x2   USDM byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39873 #define PSWHST_REG_XSDM_SWAP_MODE                                                                    0x2a00d8UL //Access:RW   DataWidth:0x2   XSDM byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39874 #define PSWHST_REG_TSDM_SWAP_MODE                                                                    0x2a00dcUL //Access:RW   DataWidth:0x2   TSDM byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39875 #define PSWHST_REG_HC_SWAP_MODE                                                                      0x2a00e0UL //Access:RW   DataWidth:0x2   HC byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39876 #define PSWHST_REG_GRC_SWAP_MODE                                                                     0x2a00e4UL //Access:RW   DataWidth:0x2   GRC byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39877 #define PSWHST_REG_DQ_SWAP_MODE                                                                      0x2a00e8UL //Access:RW   DataWidth:0x2   DORQ byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39878 #define PSWHST_REG_P2M_SWAP_MODE                                                                     0x2a00ecUL //Access:RW   DataWidth:0x2   P2M byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39879 #define PSWHST_REG_MSDM_SWAP_MODE                                                                    0x2a00f0UL //Access:RW   DataWidth:0x2   MSDM byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39880 #define PSWHST_REG_YSDM_SWAP_MODE                                                                    0x2a00f4UL //Access:RW   DataWidth:0x2   YSDM byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39881 #define PSWHST_REG_PSDM_SWAP_MODE                                                                    0x2a00f8UL //Access:RW   DataWidth:0x2   PSDM byte swapping mode configuration for host read and write requests.  Chips: BB_A0 BB_B0 K2
39882 #define PSWHST_REG_DBG_SELECT                                                                        0x2a0100UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
39883 #define PSWHST_REG_DBG_DWORD_ENABLE                                                                  0x2a0104UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
39884 #define PSWHST_REG_DBG_SHIFT                                                                         0x2a0108UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
39885 #define PSWHST_REG_DBG_FORCE_VALID                                                                   0x2a010cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
39886 #define PSWHST_REG_DBG_FORCE_FRAME                                                                   0x2a0110UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
39887 #define PSWHST_REG_DBG_OUT_DATA                                                                      0x2a0120UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
39888 #define PSWHST_REG_DBG_OUT_DATA_SIZE                                                                 8
39889 #define PSWHST_REG_DBG_OUT_VALID                                                                     0x2a0140UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
39890 #define PSWHST_REG_DBG_OUT_FRAME                                                                     0x2a0144UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
39891 #define PSWHST_REG_CLIENTS_WAITING_TO_SOURCE_ARB                                                     0x2a0160UL //Access:R    DataWidth:0xb   Debug only: Each entry contains a bit mask for PSWHST source arbiter clients. '1' means this client is waiting for the arbiter. Each entry refers to a different source arbiter. Entry decoding: (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 IGU; 7 CAU). Bit mask decoding: (0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM; 6 PBF; 7 QM; 8 NIG; 9 HOST WR; 10 HOST RD).  Chips: BB_A0 BB_B0 K2
39892 #define PSWHST_REG_CLIENTS_WAITING_TO_SOURCE_ARB_SIZE                                                8
39893 #define PSWHST_REG_INT_STS                                                                           0x2a0180UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39894     #define PSWHST_REG_INT_STS_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
39895     #define PSWHST_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                   0
39896     #define PSWHST_REG_INT_STS_HST_SRC_FIFO1_ERR                                                     (0x1<<1) // An error in write source FIFO 1.
39897     #define PSWHST_REG_INT_STS_HST_SRC_FIFO1_ERR_SHIFT                                               1
39898     #define PSWHST_REG_INT_STS_HST_SRC_FIFO2_ERR                                                     (0x1<<2) // An error in write source FIFO 2.
39899     #define PSWHST_REG_INT_STS_HST_SRC_FIFO2_ERR_SHIFT                                               2
39900     #define PSWHST_REG_INT_STS_HST_SRC_FIFO3_ERR                                                     (0x1<<3) // An error in write source FIFO 3.
39901     #define PSWHST_REG_INT_STS_HST_SRC_FIFO3_ERR_SHIFT                                               3
39902     #define PSWHST_REG_INT_STS_HST_SRC_FIFO4_ERR                                                     (0x1<<4) // An error in write source FIFO 4.
39903     #define PSWHST_REG_INT_STS_HST_SRC_FIFO4_ERR_SHIFT                                               4
39904     #define PSWHST_REG_INT_STS_HST_SRC_FIFO5_ERR                                                     (0x1<<5) // An error in write source FIFO 5.
39905     #define PSWHST_REG_INT_STS_HST_SRC_FIFO5_ERR_SHIFT                                               5
39906     #define PSWHST_REG_INT_STS_HST_HDR_SYNC_FIFO_ERR                                                 (0x1<<6) // An error in header clock sync FIFO.
39907     #define PSWHST_REG_INT_STS_HST_HDR_SYNC_FIFO_ERR_SHIFT                                           6
39908     #define PSWHST_REG_INT_STS_HST_DATA_SYNC_FIFO_ERR                                                (0x1<<7) // An error in data clock sync FIFO.
39909     #define PSWHST_REG_INT_STS_HST_DATA_SYNC_FIFO_ERR_SHIFT                                          7
39910     #define PSWHST_REG_INT_STS_HST_CPL_SYNC_FIFO_ERR                                                 (0x1<<8) // An error in completion clock sync FIFO.
39911     #define PSWHST_REG_INT_STS_HST_CPL_SYNC_FIFO_ERR_SHIFT                                           8
39912     #define PSWHST_REG_INT_STS_HST_VF_DISABLED_ACCESS                                                (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
39913     #define PSWHST_REG_INT_STS_HST_VF_DISABLED_ACCESS_SHIFT                                          9
39914     #define PSWHST_REG_INT_STS_HST_PERMISSION_VIOLATION                                              (0x1<<10) // Indicates Zone permission violation.  The relevant data is stored in hst_per_violation_data.
39915     #define PSWHST_REG_INT_STS_HST_PERMISSION_VIOLATION_SHIFT                                        10
39916     #define PSWHST_REG_INT_STS_HST_INCORRECT_ACCESS                                                  (0x1<<11) // Indicates there was an access to any of the clients  with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
39917     #define PSWHST_REG_INT_STS_HST_INCORRECT_ACCESS_SHIFT                                            11
39918     #define PSWHST_REG_INT_STS_HST_SRC_FIFO6_ERR                                                     (0x1<<12) // An error in write source FIFO 6.
39919     #define PSWHST_REG_INT_STS_HST_SRC_FIFO6_ERR_SHIFT                                               12
39920     #define PSWHST_REG_INT_STS_HST_SRC_FIFO7_ERR                                                     (0x1<<13) // An error in write source FIFO 7.
39921     #define PSWHST_REG_INT_STS_HST_SRC_FIFO7_ERR_SHIFT                                               13
39922     #define PSWHST_REG_INT_STS_HST_SRC_FIFO8_ERR                                                     (0x1<<14) // An error in write source FIFO 8.
39923     #define PSWHST_REG_INT_STS_HST_SRC_FIFO8_ERR_SHIFT                                               14
39924     #define PSWHST_REG_INT_STS_HST_SRC_FIFO9_ERR                                                     (0x1<<15) // An error in write source FIFO 9 (PBF).
39925     #define PSWHST_REG_INT_STS_HST_SRC_FIFO9_ERR_SHIFT                                               15
39926     #define PSWHST_REG_INT_STS_HST_SOURCE_CREDIT_VIOLATION                                           (0x1<<16) // Indicates an internal write source credit violation.  The relevant data is stored in hst_source_credit_viol_data.
39927     #define PSWHST_REG_INT_STS_HST_SOURCE_CREDIT_VIOLATION_SHIFT                                     16
39928     #define PSWHST_REG_INT_STS_HST_TIMEOUT                                                           (0x1<<17) // Indicates hst_timeout occurred.
39929     #define PSWHST_REG_INT_STS_HST_TIMEOUT_SHIFT                                                     17
39930 #define PSWHST_REG_INT_MASK                                                                          0x2a0184UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39931     #define PSWHST_REG_INT_MASK_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.ADDRESS_ERROR .
39932     #define PSWHST_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                  0
39933     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO1_ERR                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO1_ERR .
39934     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO1_ERR_SHIFT                                              1
39935     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO2_ERR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO2_ERR .
39936     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO2_ERR_SHIFT                                              2
39937     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO3_ERR                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO3_ERR .
39938     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO3_ERR_SHIFT                                              3
39939     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO4_ERR                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO4_ERR .
39940     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO4_ERR_SHIFT                                              4
39941     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO5_ERR                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO5_ERR .
39942     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO5_ERR_SHIFT                                              5
39943     #define PSWHST_REG_INT_MASK_HST_HDR_SYNC_FIFO_ERR                                                (0x1<<6) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_HDR_SYNC_FIFO_ERR .
39944     #define PSWHST_REG_INT_MASK_HST_HDR_SYNC_FIFO_ERR_SHIFT                                          6
39945     #define PSWHST_REG_INT_MASK_HST_DATA_SYNC_FIFO_ERR                                               (0x1<<7) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_DATA_SYNC_FIFO_ERR .
39946     #define PSWHST_REG_INT_MASK_HST_DATA_SYNC_FIFO_ERR_SHIFT                                         7
39947     #define PSWHST_REG_INT_MASK_HST_CPL_SYNC_FIFO_ERR                                                (0x1<<8) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_CPL_SYNC_FIFO_ERR .
39948     #define PSWHST_REG_INT_MASK_HST_CPL_SYNC_FIFO_ERR_SHIFT                                          8
39949     #define PSWHST_REG_INT_MASK_HST_VF_DISABLED_ACCESS                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_VF_DISABLED_ACCESS .
39950     #define PSWHST_REG_INT_MASK_HST_VF_DISABLED_ACCESS_SHIFT                                         9
39951     #define PSWHST_REG_INT_MASK_HST_PERMISSION_VIOLATION                                             (0x1<<10) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_PERMISSION_VIOLATION .
39952     #define PSWHST_REG_INT_MASK_HST_PERMISSION_VIOLATION_SHIFT                                       10
39953     #define PSWHST_REG_INT_MASK_HST_INCORRECT_ACCESS                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_INCORRECT_ACCESS .
39954     #define PSWHST_REG_INT_MASK_HST_INCORRECT_ACCESS_SHIFT                                           11
39955     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO6_ERR                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO6_ERR .
39956     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO6_ERR_SHIFT                                              12
39957     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO7_ERR                                                    (0x1<<13) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO7_ERR .
39958     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO7_ERR_SHIFT                                              13
39959     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO8_ERR                                                    (0x1<<14) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO8_ERR .
39960     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO8_ERR_SHIFT                                              14
39961     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO9_ERR                                                    (0x1<<15) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SRC_FIFO9_ERR .
39962     #define PSWHST_REG_INT_MASK_HST_SRC_FIFO9_ERR_SHIFT                                              15
39963     #define PSWHST_REG_INT_MASK_HST_SOURCE_CREDIT_VIOLATION                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_SOURCE_CREDIT_VIOLATION .
39964     #define PSWHST_REG_INT_MASK_HST_SOURCE_CREDIT_VIOLATION_SHIFT                                    16
39965     #define PSWHST_REG_INT_MASK_HST_TIMEOUT                                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: PSWHST_REG_INT_STS.HST_TIMEOUT .
39966     #define PSWHST_REG_INT_MASK_HST_TIMEOUT_SHIFT                                                    17
39967 #define PSWHST_REG_INT_STS_WR                                                                        0x2a0188UL //Access:WR   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
39968     #define PSWHST_REG_INT_STS_WR_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
39969     #define PSWHST_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                0
39970     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO1_ERR                                                  (0x1<<1) // An error in write source FIFO 1.
39971     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO1_ERR_SHIFT                                            1
39972     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO2_ERR                                                  (0x1<<2) // An error in write source FIFO 2.
39973     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO2_ERR_SHIFT                                            2
39974     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO3_ERR                                                  (0x1<<3) // An error in write source FIFO 3.
39975     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO3_ERR_SHIFT                                            3
39976     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO4_ERR                                                  (0x1<<4) // An error in write source FIFO 4.
39977     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO4_ERR_SHIFT                                            4
39978     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO5_ERR                                                  (0x1<<5) // An error in write source FIFO 5.
39979     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO5_ERR_SHIFT                                            5
39980     #define PSWHST_REG_INT_STS_WR_HST_HDR_SYNC_FIFO_ERR                                              (0x1<<6) // An error in header clock sync FIFO.
39981     #define PSWHST_REG_INT_STS_WR_HST_HDR_SYNC_FIFO_ERR_SHIFT                                        6
39982     #define PSWHST_REG_INT_STS_WR_HST_DATA_SYNC_FIFO_ERR                                             (0x1<<7) // An error in data clock sync FIFO.
39983     #define PSWHST_REG_INT_STS_WR_HST_DATA_SYNC_FIFO_ERR_SHIFT                                       7
39984     #define PSWHST_REG_INT_STS_WR_HST_CPL_SYNC_FIFO_ERR                                              (0x1<<8) // An error in completion clock sync FIFO.
39985     #define PSWHST_REG_INT_STS_WR_HST_CPL_SYNC_FIFO_ERR_SHIFT                                        8
39986     #define PSWHST_REG_INT_STS_WR_HST_VF_DISABLED_ACCESS                                             (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
39987     #define PSWHST_REG_INT_STS_WR_HST_VF_DISABLED_ACCESS_SHIFT                                       9
39988     #define PSWHST_REG_INT_STS_WR_HST_PERMISSION_VIOLATION                                           (0x1<<10) // Indicates Zone permission violation.  The relevant data is stored in hst_per_violation_data.
39989     #define PSWHST_REG_INT_STS_WR_HST_PERMISSION_VIOLATION_SHIFT                                     10
39990     #define PSWHST_REG_INT_STS_WR_HST_INCORRECT_ACCESS                                               (0x1<<11) // Indicates there was an access to any of the clients  with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
39991     #define PSWHST_REG_INT_STS_WR_HST_INCORRECT_ACCESS_SHIFT                                         11
39992     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO6_ERR                                                  (0x1<<12) // An error in write source FIFO 6.
39993     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO6_ERR_SHIFT                                            12
39994     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO7_ERR                                                  (0x1<<13) // An error in write source FIFO 7.
39995     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO7_ERR_SHIFT                                            13
39996     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO8_ERR                                                  (0x1<<14) // An error in write source FIFO 8.
39997     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO8_ERR_SHIFT                                            14
39998     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO9_ERR                                                  (0x1<<15) // An error in write source FIFO 9 (PBF).
39999     #define PSWHST_REG_INT_STS_WR_HST_SRC_FIFO9_ERR_SHIFT                                            15
40000     #define PSWHST_REG_INT_STS_WR_HST_SOURCE_CREDIT_VIOLATION                                        (0x1<<16) // Indicates an internal write source credit violation.  The relevant data is stored in hst_source_credit_viol_data.
40001     #define PSWHST_REG_INT_STS_WR_HST_SOURCE_CREDIT_VIOLATION_SHIFT                                  16
40002     #define PSWHST_REG_INT_STS_WR_HST_TIMEOUT                                                        (0x1<<17) // Indicates hst_timeout occurred.
40003     #define PSWHST_REG_INT_STS_WR_HST_TIMEOUT_SHIFT                                                  17
40004 #define PSWHST_REG_INT_STS_CLR                                                                       0x2a018cUL //Access:RC   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40005     #define PSWHST_REG_INT_STS_CLR_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
40006     #define PSWHST_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                               0
40007     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO1_ERR                                                 (0x1<<1) // An error in write source FIFO 1.
40008     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO1_ERR_SHIFT                                           1
40009     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO2_ERR                                                 (0x1<<2) // An error in write source FIFO 2.
40010     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO2_ERR_SHIFT                                           2
40011     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO3_ERR                                                 (0x1<<3) // An error in write source FIFO 3.
40012     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO3_ERR_SHIFT                                           3
40013     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO4_ERR                                                 (0x1<<4) // An error in write source FIFO 4.
40014     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO4_ERR_SHIFT                                           4
40015     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO5_ERR                                                 (0x1<<5) // An error in write source FIFO 5.
40016     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO5_ERR_SHIFT                                           5
40017     #define PSWHST_REG_INT_STS_CLR_HST_HDR_SYNC_FIFO_ERR                                             (0x1<<6) // An error in header clock sync FIFO.
40018     #define PSWHST_REG_INT_STS_CLR_HST_HDR_SYNC_FIFO_ERR_SHIFT                                       6
40019     #define PSWHST_REG_INT_STS_CLR_HST_DATA_SYNC_FIFO_ERR                                            (0x1<<7) // An error in data clock sync FIFO.
40020     #define PSWHST_REG_INT_STS_CLR_HST_DATA_SYNC_FIFO_ERR_SHIFT                                      7
40021     #define PSWHST_REG_INT_STS_CLR_HST_CPL_SYNC_FIFO_ERR                                             (0x1<<8) // An error in completion clock sync FIFO.
40022     #define PSWHST_REG_INT_STS_CLR_HST_CPL_SYNC_FIFO_ERR_SHIFT                                       8
40023     #define PSWHST_REG_INT_STS_CLR_HST_VF_DISABLED_ACCESS                                            (0x1<<9) // Indicates there was an access to a disabled VF when client is not IGU or ATC (so access is dropped). The disabled vf registers are valid when it is set and reset when the interrupt clr is read.
40024     #define PSWHST_REG_INT_STS_CLR_HST_VF_DISABLED_ACCESS_SHIFT                                      9
40025     #define PSWHST_REG_INT_STS_CLR_HST_PERMISSION_VIOLATION                                          (0x1<<10) // Indicates Zone permission violation.  The relevant data is stored in hst_per_violation_data.
40026     #define PSWHST_REG_INT_STS_CLR_HST_PERMISSION_VIOLATION_SHIFT                                    10
40027     #define PSWHST_REG_INT_STS_CLR_HST_INCORRECT_ACCESS                                              (0x1<<11) // Indicates there was an access to any of the clients  with incorrect length and alignement. Details are logged in incorrect access registers. The incorrect access registers are valid when it is set and reset when the interrupt clr is read.
40028     #define PSWHST_REG_INT_STS_CLR_HST_INCORRECT_ACCESS_SHIFT                                        11
40029     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO6_ERR                                                 (0x1<<12) // An error in write source FIFO 6.
40030     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO6_ERR_SHIFT                                           12
40031     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO7_ERR                                                 (0x1<<13) // An error in write source FIFO 7.
40032     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO7_ERR_SHIFT                                           13
40033     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO8_ERR                                                 (0x1<<14) // An error in write source FIFO 8.
40034     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO8_ERR_SHIFT                                           14
40035     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO9_ERR                                                 (0x1<<15) // An error in write source FIFO 9 (PBF).
40036     #define PSWHST_REG_INT_STS_CLR_HST_SRC_FIFO9_ERR_SHIFT                                           15
40037     #define PSWHST_REG_INT_STS_CLR_HST_SOURCE_CREDIT_VIOLATION                                       (0x1<<16) // Indicates an internal write source credit violation.  The relevant data is stored in hst_source_credit_viol_data.
40038     #define PSWHST_REG_INT_STS_CLR_HST_SOURCE_CREDIT_VIOLATION_SHIFT                                 16
40039     #define PSWHST_REG_INT_STS_CLR_HST_TIMEOUT                                                       (0x1<<17) // Indicates hst_timeout occurred.
40040     #define PSWHST_REG_INT_STS_CLR_HST_TIMEOUT_SHIFT                                                 17
40041 #define PSWHST_REG_PRTY_MASK                                                                         0x2a0194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
40042     #define PSWHST_REG_PRTY_MASK_DATAPATH_REGISTERS                                                  (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS.DATAPATH_REGISTERS .
40043     #define PSWHST_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                            0
40044 #define PSWHST_REG_PRTY_MASK_H_0                                                                     0x2a0204UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40045     #define PSWHST_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                               (0x1<<0) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
40046     #define PSWHST_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                         0
40047     #define PSWHST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                               (0x1<<1) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
40048     #define PSWHST_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                         1
40049     #define PSWHST_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                               (0x1<<2) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
40050     #define PSWHST_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                         2
40051     #define PSWHST_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                               (0x1<<3) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
40052     #define PSWHST_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                         3
40053     #define PSWHST_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                               (0x1<<4) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
40054     #define PSWHST_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                         4
40055     #define PSWHST_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                               (0x1<<5) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
40056     #define PSWHST_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                         5
40057     #define PSWHST_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                               (0x1<<6) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
40058     #define PSWHST_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                         6
40059     #define PSWHST_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                               (0x1<<7) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
40060     #define PSWHST_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                         7
40061     #define PSWHST_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                               (0x1<<8) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
40062     #define PSWHST_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                         8
40063     #define PSWHST_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                               (0x1<<9) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
40064     #define PSWHST_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                         9
40065     #define PSWHST_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY                                               (0x1<<10) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
40066     #define PSWHST_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_SHIFT                                         10
40067     #define PSWHST_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                               (0x1<<11) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
40068     #define PSWHST_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                         11
40069     #define PSWHST_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                               (0x1<<12) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
40070     #define PSWHST_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                         12
40071     #define PSWHST_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY                                               (0x1<<13) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
40072     #define PSWHST_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT                                         13
40073     #define PSWHST_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY                                               (0x1<<14) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
40074     #define PSWHST_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_SHIFT                                         14
40075     #define PSWHST_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                               (0x1<<15) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
40076     #define PSWHST_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                         15
40077     #define PSWHST_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY                                               (0x1<<16) // This bit masks, when set, the Parity bit: PSWHST_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
40078     #define PSWHST_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_SHIFT                                         16
40079 #define PSWHST_REG_MEM_ECC_EVENTS                                                                    0x2a0210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
40080 #define PSWHST_REG_MEM006_I_MEM_DFT_K2                                                               0x2a0218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_pswhst_wr_src_fifos_top.usdm_fifo.genblk1.i_wr_src_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40081 #define PSWHST_REG_MEM007_I_MEM_DFT_K2                                                               0x2a021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_pswhst_wr_src_fifos_top.xsdm_fifo.genblk1.i_wr_src_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40082 #define PSWHST_REG_MEM005_I_MEM_DFT_K2                                                               0x2a0220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_pswhst_wr_src_fifos_top.tsdm_fifo.genblk1.i_wr_src_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40083 #define PSWHST_REG_MEM002_I_MEM_DFT_K2                                                               0x2a0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_pswhst_wr_src_fifos_top.nig_fifo.genblk1.i_wr_src_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40084 #define PSWHST_REG_MEM003_I_MEM_DFT_K2                                                               0x2a0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_pswhst_wr_src_fifos_top.pbf_fifo.genblk1.i_wr_src_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40085 #define PSWHST_REG_MEM001_I_MEM_DFT_K2                                                               0x2a022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_pswhst_wr_src_fifos_top.msdm_fifo.genblk1.i_wr_src_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40086 #define PSWHST_REG_MEM008_I_MEM_DFT_K2                                                               0x2a0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_pswhst_wr_src_fifos_top.ysdm_fifo.genblk1.i_wr_src_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40087 #define PSWHST_REG_MEM004_I_MEM_DFT_K2                                                               0x2a0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_pswhst_wr_src_fifos_top.psdm_fifo.genblk1.i_wr_src_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40088 #define PSWHST_REG_MEM009_I_MEM_DFT_K2                                                               0x2a0238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_rw_handler.i_inbnd_int_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40089 #define PSWHST_REG_MEM010_I_MEM_DFT_K2                                                               0x2a023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_clk_domain.i_rw_handler.i_per_table_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40090 #define PSWHST_REG_MEM016_I_MEM_DFT_K2                                                               0x2a0240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_dc_domain.i_hdr_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40091 #define PSWHST_REG_MEM012_I_MEM_DFT_K2                                                               0x2a0244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_dc_domain.i_data_mem_lsb_0.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40092 #define PSWHST_REG_MEM013_I_MEM_DFT_K2                                                               0x2a0248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_dc_domain.i_data_mem_lsb_1.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40093 #define PSWHST_REG_MEM014_I_MEM_DFT_K2                                                               0x2a024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_dc_domain.i_data_mem_msb_0.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40094 #define PSWHST_REG_MEM015_I_MEM_DFT_K2                                                               0x2a0250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_dc_domain.i_data_mem_msb_1.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40095 #define PSWHST_REG_MEM011_I_MEM_DFT_K2                                                               0x2a0254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_dc_domain.i_cpl_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40096 #define PSWHST_REG_MEM017_I_MEM_DFT_K2                                                               0x2a0258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pswhst.i_pswhst_no_rf.i_pswhst_dc_domain.i_ireq_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40097 #define PSWHST_REG_INBOUND_INT                                                                       0x2a0400UL //Access:RW   DataWidth:0x20  Used for initialization of the inbound interrupts memory. E4 entry structure: [15:0] - CompParams. [23:16] - EventID. [24] - T. [28:25] - Trig.  Chips: BB_A0 BB_B0 K2
40098 #define PSWHST_REG_INBOUND_INT_SIZE                                                                  72
40099 #define PSWHST_REG_ZONE_PERMISSION_TABLE                                                             0x2a0800UL //Access:RW   DataWidth:0x9   Indirect access to the permission table. The fields are : {Valid; VFID[7:0]}.  Chips: BB_A0 BB_B0 K2
40100 #define PSWHST_REG_ZONE_PERMISSION_TABLE_SIZE                                                        320
40101 #define PGLUE_B_REG_START_INIT_INB_INT_MEM                                                           0x2a8000UL //Access:W    DataWidth:0x1   Writing 1 to this register signals the PGLUE block to start initializing inbound interrupt memories for PF zone B. Memories are initialized such that all interrupts are disabled: start_address = 1; end_address = 0.  Chips: BB_A0 BB_B0 K2
40102 #define PGLUE_B_REG_INIT_DONE_INB_INT_MEM                                                            0x2a8004UL //Access:R    DataWidth:0x2   Initializing inbound interrupt memories for PF zone B is done. Driver should make sure the corresponding bit is 1 some time after writing to start_init_inb_int_mem. Bit 0 is for path 0 and bit 1 is for path 1.  Chips: BB_A0 BB_B0 K2
40103 #define PGLUE_B_REG_START_INIT_PTT_GTT                                                               0x2a8008UL //Access:W    DataWidth:0x1   Writing 1 to this register signals the PGLUE block to start initializing PTT and GTT. Offsets should map to reserved space, pretend should map to the same PF. This register should be initialized by MCP.  Chips: BB_A0 BB_B0 K2
40104 #define PGLUE_B_REG_INIT_DONE_PTT_GTT                                                                0x2a800cUL //Access:R    DataWidth:0x1   PTT and GTT initialization is done. MCP should make sure this bit is 1 some time after writing to start_init_ptt_gtt.  Chips: BB_A0 BB_B0 K2
40105 #define PGLUE_B_REG_START_INIT_ZONE_A                                                                0x2a8010UL //Access:W    DataWidth:0x1   Writing 1 to this register signals the PGLUE block to start calculating the start address of each SDM zone A in VF BAR according to the sdm_queue_zone_size configurations.  Chips: BB_A0 BB_B0 K2
40106 #define PGLUE_B_REG_INIT_DONE_ZONE_A                                                                 0x2a8014UL //Access:R    DataWidth:0x2   Calculation of SDMs zone A start address in VF BAR  is done. Driver should make sure the corresponding bit is 1 some time after writing to start_init_zone_a. Bit 0 is for path 0 and bit 1 is for path 1.  Chips: BB_A0 BB_B0 K2
40107 #define PGLUE_B_REG_INT_STS                                                                          0x2a8180UL //Access:R    DataWidth:0x18  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40108     #define PGLUE_B_REG_INT_STS_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
40109     #define PGLUE_B_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                  0
40110     #define PGLUE_B_REG_INT_STS_INCORRECT_RCV_BEHAVIOR                                               (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
40111     #define PGLUE_B_REG_INT_STS_INCORRECT_RCV_BEHAVIOR_SHIFT                                         1
40112     #define PGLUE_B_REG_INT_STS_WAS_ERROR_ATTN                                                       (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
40113     #define PGLUE_B_REG_INT_STS_WAS_ERROR_ATTN_SHIFT                                                 2
40114     #define PGLUE_B_REG_INT_STS_VF_LENGTH_VIOLATION_ATTN                                             (0x1<<3) // Indicates a  VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
40115     #define PGLUE_B_REG_INT_STS_VF_LENGTH_VIOLATION_ATTN_SHIFT                                       3
40116     #define PGLUE_B_REG_INT_STS_VF_GRC_SPACE_VIOLATION_ATTN                                          (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
40117     #define PGLUE_B_REG_INT_STS_VF_GRC_SPACE_VIOLATION_ATTN_SHIFT                                    4
40118     #define PGLUE_B_REG_INT_STS_TCPL_ERROR_ATTN                                                      (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
40119     #define PGLUE_B_REG_INT_STS_TCPL_ERROR_ATTN_SHIFT                                                5
40120     #define PGLUE_B_REG_INT_STS_TCPL_IN_TWO_RCBS_ATTN                                                (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
40121     #define PGLUE_B_REG_INT_STS_TCPL_IN_TWO_RCBS_ATTN_SHIFT                                          6
40122     #define PGLUE_B_REG_INT_STS_CSSNOOP_FIFO_OVERFLOW                                                (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
40123     #define PGLUE_B_REG_INT_STS_CSSNOOP_FIFO_OVERFLOW_SHIFT                                          7
40124     #define PGLUE_B_REG_INT_STS_TCPL_TRANSLATION_SIZE_DIFFERENT                                      (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
40125     #define PGLUE_B_REG_INT_STS_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT                                8
40126     #define PGLUE_B_REG_INT_STS_PCIE_RX_L0S_TIMEOUT                                                  (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly.  If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
40127     #define PGLUE_B_REG_INT_STS_PCIE_RX_L0S_TIMEOUT_SHIFT                                            9
40128     #define PGLUE_B_REG_INT_STS_MASTER_ZLR_ATTN                                                      (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
40129     #define PGLUE_B_REG_INT_STS_MASTER_ZLR_ATTN_SHIFT                                                10
40130     #define PGLUE_B_REG_INT_STS_ADMIN_WINDOW_VIOLATION_ATTN                                          (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
40131     #define PGLUE_B_REG_INT_STS_ADMIN_WINDOW_VIOLATION_ATTN_SHIFT                                    11
40132     #define PGLUE_B_REG_INT_STS_OUT_OF_RANGE_FUNCTION_IN_PRETEND                                     (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
40133     #define PGLUE_B_REG_INT_STS_OUT_OF_RANGE_FUNCTION_IN_PRETEND_SHIFT                               12
40134     #define PGLUE_B_REG_INT_STS_ILLEGAL_ADDRESS                                                      (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
40135     #define PGLUE_B_REG_INT_STS_ILLEGAL_ADDRESS_SHIFT                                                13
40136     #define PGLUE_B_REG_INT_STS_PGL_CPL_ERR                                                          (0x1<<14) // Completion error received from core.
40137     #define PGLUE_B_REG_INT_STS_PGL_CPL_ERR_SHIFT                                                    14
40138     #define PGLUE_B_REG_INT_STS_PGL_TXW_OF                                                           (0x1<<15) // Overflow of tx write queue.
40139     #define PGLUE_B_REG_INT_STS_PGL_TXW_OF_SHIFT                                                     15
40140     #define PGLUE_B_REG_INT_STS_PGL_CPL_AFT                                                          (0x1<<16) // Overflow of cpl queue.
40141     #define PGLUE_B_REG_INT_STS_PGL_CPL_AFT_SHIFT                                                    16
40142     #define PGLUE_B_REG_INT_STS_PGL_CPL_OF                                                           (0x1<<17) // Overflow error on completion or target write.
40143     #define PGLUE_B_REG_INT_STS_PGL_CPL_OF_SHIFT                                                     17
40144     #define PGLUE_B_REG_INT_STS_PGL_CPL_ECRC                                                         (0x1<<18) // Ecrc error on completion or target write.
40145     #define PGLUE_B_REG_INT_STS_PGL_CPL_ECRC_SHIFT                                                   18
40146     #define PGLUE_B_REG_INT_STS_PGL_PCIE_ATTN                                                        (0x1<<19) // Pcie core raised an attention.
40147     #define PGLUE_B_REG_INT_STS_PGL_PCIE_ATTN_SHIFT                                                  19
40148     #define PGLUE_B_REG_INT_STS_PGL_READ_BLOCKED                                                     (0x1<<20) // Read was blocked due to master_en.
40149     #define PGLUE_B_REG_INT_STS_PGL_READ_BLOCKED_SHIFT                                               20
40150     #define PGLUE_B_REG_INT_STS_PGL_WRITE_BLOCKED                                                    (0x1<<21) // Write was blocked due to master_en.
40151     #define PGLUE_B_REG_INT_STS_PGL_WRITE_BLOCKED_SHIFT                                              21
40152     #define PGLUE_B_REG_INT_STS_VF_ILT_ERR                                                           (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
40153     #define PGLUE_B_REG_INT_STS_VF_ILT_ERR_SHIFT                                                     22
40154     #define PGLUE_B_REG_INT_STS_RXOBFFEXCEPTION_ATTN                                                 (0x1<<23) // Indicate rxobffexception_attn is asseted
40155     #define PGLUE_B_REG_INT_STS_RXOBFFEXCEPTION_ATTN_SHIFT                                           23
40156 #define PGLUE_B_REG_INT_MASK                                                                         0x2a8184UL //Access:RW   DataWidth:0x18  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40157     #define PGLUE_B_REG_INT_MASK_ADDRESS_ERROR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ADDRESS_ERROR .
40158     #define PGLUE_B_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                 0
40159     #define PGLUE_B_REG_INT_MASK_INCORRECT_RCV_BEHAVIOR                                              (0x1<<1) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.INCORRECT_RCV_BEHAVIOR .
40160     #define PGLUE_B_REG_INT_MASK_INCORRECT_RCV_BEHAVIOR_SHIFT                                        1
40161     #define PGLUE_B_REG_INT_MASK_WAS_ERROR_ATTN                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.WAS_ERROR_ATTN .
40162     #define PGLUE_B_REG_INT_MASK_WAS_ERROR_ATTN_SHIFT                                                2
40163     #define PGLUE_B_REG_INT_MASK_VF_LENGTH_VIOLATION_ATTN                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_LENGTH_VIOLATION_ATTN .
40164     #define PGLUE_B_REG_INT_MASK_VF_LENGTH_VIOLATION_ATTN_SHIFT                                      3
40165     #define PGLUE_B_REG_INT_MASK_VF_GRC_SPACE_VIOLATION_ATTN                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_GRC_SPACE_VIOLATION_ATTN .
40166     #define PGLUE_B_REG_INT_MASK_VF_GRC_SPACE_VIOLATION_ATTN_SHIFT                                   4
40167     #define PGLUE_B_REG_INT_MASK_TCPL_ERROR_ATTN                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_ERROR_ATTN .
40168     #define PGLUE_B_REG_INT_MASK_TCPL_ERROR_ATTN_SHIFT                                               5
40169     #define PGLUE_B_REG_INT_MASK_TCPL_IN_TWO_RCBS_ATTN                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_IN_TWO_RCBS_ATTN .
40170     #define PGLUE_B_REG_INT_MASK_TCPL_IN_TWO_RCBS_ATTN_SHIFT                                         6
40171     #define PGLUE_B_REG_INT_MASK_CSSNOOP_FIFO_OVERFLOW                                               (0x1<<7) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.CSSNOOP_FIFO_OVERFLOW .
40172     #define PGLUE_B_REG_INT_MASK_CSSNOOP_FIFO_OVERFLOW_SHIFT                                         7
40173     #define PGLUE_B_REG_INT_MASK_TCPL_TRANSLATION_SIZE_DIFFERENT                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.TCPL_TRANSLATION_SIZE_DIFFERENT .
40174     #define PGLUE_B_REG_INT_MASK_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT                               8
40175     #define PGLUE_B_REG_INT_MASK_PCIE_RX_L0S_TIMEOUT                                                 (0x1<<9) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PCIE_RX_L0S_TIMEOUT .
40176     #define PGLUE_B_REG_INT_MASK_PCIE_RX_L0S_TIMEOUT_SHIFT                                           9
40177     #define PGLUE_B_REG_INT_MASK_MASTER_ZLR_ATTN                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.MASTER_ZLR_ATTN .
40178     #define PGLUE_B_REG_INT_MASK_MASTER_ZLR_ATTN_SHIFT                                               10
40179     #define PGLUE_B_REG_INT_MASK_ADMIN_WINDOW_VIOLATION_ATTN                                         (0x1<<11) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ADMIN_WINDOW_VIOLATION_ATTN .
40180     #define PGLUE_B_REG_INT_MASK_ADMIN_WINDOW_VIOLATION_ATTN_SHIFT                                   11
40181     #define PGLUE_B_REG_INT_MASK_OUT_OF_RANGE_FUNCTION_IN_PRETEND                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.OUT_OF_RANGE_FUNCTION_IN_PRETEND .
40182     #define PGLUE_B_REG_INT_MASK_OUT_OF_RANGE_FUNCTION_IN_PRETEND_SHIFT                              12
40183     #define PGLUE_B_REG_INT_MASK_ILLEGAL_ADDRESS                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.ILLEGAL_ADDRESS .
40184     #define PGLUE_B_REG_INT_MASK_ILLEGAL_ADDRESS_SHIFT                                               13
40185     #define PGLUE_B_REG_INT_MASK_PGL_CPL_ERR                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_ERR .
40186     #define PGLUE_B_REG_INT_MASK_PGL_CPL_ERR_SHIFT                                                   14
40187     #define PGLUE_B_REG_INT_MASK_PGL_TXW_OF                                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_TXW_OF .
40188     #define PGLUE_B_REG_INT_MASK_PGL_TXW_OF_SHIFT                                                    15
40189     #define PGLUE_B_REG_INT_MASK_PGL_CPL_AFT                                                         (0x1<<16) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_AFT .
40190     #define PGLUE_B_REG_INT_MASK_PGL_CPL_AFT_SHIFT                                                   16
40191     #define PGLUE_B_REG_INT_MASK_PGL_CPL_OF                                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_OF .
40192     #define PGLUE_B_REG_INT_MASK_PGL_CPL_OF_SHIFT                                                    17
40193     #define PGLUE_B_REG_INT_MASK_PGL_CPL_ECRC                                                        (0x1<<18) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_CPL_ECRC .
40194     #define PGLUE_B_REG_INT_MASK_PGL_CPL_ECRC_SHIFT                                                  18
40195     #define PGLUE_B_REG_INT_MASK_PGL_PCIE_ATTN                                                       (0x1<<19) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_PCIE_ATTN .
40196     #define PGLUE_B_REG_INT_MASK_PGL_PCIE_ATTN_SHIFT                                                 19
40197     #define PGLUE_B_REG_INT_MASK_PGL_READ_BLOCKED                                                    (0x1<<20) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_READ_BLOCKED .
40198     #define PGLUE_B_REG_INT_MASK_PGL_READ_BLOCKED_SHIFT                                              20
40199     #define PGLUE_B_REG_INT_MASK_PGL_WRITE_BLOCKED                                                   (0x1<<21) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.PGL_WRITE_BLOCKED .
40200     #define PGLUE_B_REG_INT_MASK_PGL_WRITE_BLOCKED_SHIFT                                             21
40201     #define PGLUE_B_REG_INT_MASK_VF_ILT_ERR                                                          (0x1<<22) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.VF_ILT_ERR .
40202     #define PGLUE_B_REG_INT_MASK_VF_ILT_ERR_SHIFT                                                    22
40203     #define PGLUE_B_REG_INT_MASK_RXOBFFEXCEPTION_ATTN                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: PGLUE_B_REG_INT_STS.RXOBFFEXCEPTION_ATTN .
40204     #define PGLUE_B_REG_INT_MASK_RXOBFFEXCEPTION_ATTN_SHIFT                                          23
40205 #define PGLUE_B_REG_INT_STS_WR                                                                       0x2a8188UL //Access:WR   DataWidth:0x18  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40206     #define PGLUE_B_REG_INT_STS_WR_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
40207     #define PGLUE_B_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                               0
40208     #define PGLUE_B_REG_INT_STS_WR_INCORRECT_RCV_BEHAVIOR                                            (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
40209     #define PGLUE_B_REG_INT_STS_WR_INCORRECT_RCV_BEHAVIOR_SHIFT                                      1
40210     #define PGLUE_B_REG_INT_STS_WR_WAS_ERROR_ATTN                                                    (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
40211     #define PGLUE_B_REG_INT_STS_WR_WAS_ERROR_ATTN_SHIFT                                              2
40212     #define PGLUE_B_REG_INT_STS_WR_VF_LENGTH_VIOLATION_ATTN                                          (0x1<<3) // Indicates a  VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
40213     #define PGLUE_B_REG_INT_STS_WR_VF_LENGTH_VIOLATION_ATTN_SHIFT                                    3
40214     #define PGLUE_B_REG_INT_STS_WR_VF_GRC_SPACE_VIOLATION_ATTN                                       (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
40215     #define PGLUE_B_REG_INT_STS_WR_VF_GRC_SPACE_VIOLATION_ATTN_SHIFT                                 4
40216     #define PGLUE_B_REG_INT_STS_WR_TCPL_ERROR_ATTN                                                   (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
40217     #define PGLUE_B_REG_INT_STS_WR_TCPL_ERROR_ATTN_SHIFT                                             5
40218     #define PGLUE_B_REG_INT_STS_WR_TCPL_IN_TWO_RCBS_ATTN                                             (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
40219     #define PGLUE_B_REG_INT_STS_WR_TCPL_IN_TWO_RCBS_ATTN_SHIFT                                       6
40220     #define PGLUE_B_REG_INT_STS_WR_CSSNOOP_FIFO_OVERFLOW                                             (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
40221     #define PGLUE_B_REG_INT_STS_WR_CSSNOOP_FIFO_OVERFLOW_SHIFT                                       7
40222     #define PGLUE_B_REG_INT_STS_WR_TCPL_TRANSLATION_SIZE_DIFFERENT                                   (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
40223     #define PGLUE_B_REG_INT_STS_WR_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT                             8
40224     #define PGLUE_B_REG_INT_STS_WR_PCIE_RX_L0S_TIMEOUT                                               (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly.  If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
40225     #define PGLUE_B_REG_INT_STS_WR_PCIE_RX_L0S_TIMEOUT_SHIFT                                         9
40226     #define PGLUE_B_REG_INT_STS_WR_MASTER_ZLR_ATTN                                                   (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
40227     #define PGLUE_B_REG_INT_STS_WR_MASTER_ZLR_ATTN_SHIFT                                             10
40228     #define PGLUE_B_REG_INT_STS_WR_ADMIN_WINDOW_VIOLATION_ATTN                                       (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
40229     #define PGLUE_B_REG_INT_STS_WR_ADMIN_WINDOW_VIOLATION_ATTN_SHIFT                                 11
40230     #define PGLUE_B_REG_INT_STS_WR_OUT_OF_RANGE_FUNCTION_IN_PRETEND                                  (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
40231     #define PGLUE_B_REG_INT_STS_WR_OUT_OF_RANGE_FUNCTION_IN_PRETEND_SHIFT                            12
40232     #define PGLUE_B_REG_INT_STS_WR_ILLEGAL_ADDRESS                                                   (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
40233     #define PGLUE_B_REG_INT_STS_WR_ILLEGAL_ADDRESS_SHIFT                                             13
40234     #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ERR                                                       (0x1<<14) // Completion error received from core.
40235     #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ERR_SHIFT                                                 14
40236     #define PGLUE_B_REG_INT_STS_WR_PGL_TXW_OF                                                        (0x1<<15) // Overflow of tx write queue.
40237     #define PGLUE_B_REG_INT_STS_WR_PGL_TXW_OF_SHIFT                                                  15
40238     #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_AFT                                                       (0x1<<16) // Overflow of cpl queue.
40239     #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_AFT_SHIFT                                                 16
40240     #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_OF                                                        (0x1<<17) // Overflow error on completion or target write.
40241     #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_OF_SHIFT                                                  17
40242     #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ECRC                                                      (0x1<<18) // Ecrc error on completion or target write.
40243     #define PGLUE_B_REG_INT_STS_WR_PGL_CPL_ECRC_SHIFT                                                18
40244     #define PGLUE_B_REG_INT_STS_WR_PGL_PCIE_ATTN                                                     (0x1<<19) // Pcie core raised an attention.
40245     #define PGLUE_B_REG_INT_STS_WR_PGL_PCIE_ATTN_SHIFT                                               19
40246     #define PGLUE_B_REG_INT_STS_WR_PGL_READ_BLOCKED                                                  (0x1<<20) // Read was blocked due to master_en.
40247     #define PGLUE_B_REG_INT_STS_WR_PGL_READ_BLOCKED_SHIFT                                            20
40248     #define PGLUE_B_REG_INT_STS_WR_PGL_WRITE_BLOCKED                                                 (0x1<<21) // Write was blocked due to master_en.
40249     #define PGLUE_B_REG_INT_STS_WR_PGL_WRITE_BLOCKED_SHIFT                                           21
40250     #define PGLUE_B_REG_INT_STS_WR_VF_ILT_ERR                                                        (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
40251     #define PGLUE_B_REG_INT_STS_WR_VF_ILT_ERR_SHIFT                                                  22
40252     #define PGLUE_B_REG_INT_STS_WR_RXOBFFEXCEPTION_ATTN                                              (0x1<<23) // Indicate rxobffexception_attn is asseted
40253     #define PGLUE_B_REG_INT_STS_WR_RXOBFFEXCEPTION_ATTN_SHIFT                                        23
40254 #define PGLUE_B_REG_INT_STS_CLR                                                                      0x2a818cUL //Access:RC   DataWidth:0x18  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40255     #define PGLUE_B_REG_INT_STS_CLR_ADDRESS_ERROR                                                    (0x1<<0) // Signals an unknown address to the rf module.
40256     #define PGLUE_B_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                              0
40257     #define PGLUE_B_REG_INT_STS_CLR_INCORRECT_RCV_BEHAVIOR                                           (0x1<<1) // Target RW or completion not according to PCIe core spec. See incorrect_rcv_details.
40258     #define PGLUE_B_REG_INT_STS_CLR_INCORRECT_RCV_BEHAVIOR_SHIFT                                     1
40259     #define PGLUE_B_REG_INT_STS_CLR_WAS_ERROR_ATTN                                                   (0x1<<2) // Indicates a memory read completion was received with an uncorrectable error. Was_error dirty bits provide the function on which the completion was received.
40260     #define PGLUE_B_REG_INT_STS_CLR_WAS_ERROR_ATTN_SHIFT                                             2
40261     #define PGLUE_B_REG_INT_STS_CLR_VF_LENGTH_VIOLATION_ATTN                                         (0x1<<3) // Indicates a  VF BAR0 length violation: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW. Details are stored in vf_length_violation_details register.
40262     #define PGLUE_B_REG_INT_STS_CLR_VF_LENGTH_VIOLATION_ATTN_SHIFT                                   3
40263     #define PGLUE_B_REG_INT_STS_CLR_VF_GRC_SPACE_VIOLATION_ATTN                                      (0x1<<4) // Indicates target VF request accessing VF GRC space that failed permission check. Permission checks are: function permission; RW permission; address range permission. Details are stored in vf_grc_space_violation_details register.
40264     #define PGLUE_B_REG_INT_STS_CLR_VF_GRC_SPACE_VIOLATION_ATTN_SHIFT                                4
40265     #define PGLUE_B_REG_INT_STS_CLR_TCPL_ERROR_ATTN                                                  (0x1<<5) // Indicates an ATS translation completion was received with an uncorrectable error.
40266     #define PGLUE_B_REG_INT_STS_CLR_TCPL_ERROR_ATTN_SHIFT                                            5
40267     #define PGLUE_B_REG_INT_STS_CLR_TCPL_IN_TWO_RCBS_ATTN                                            (0x1<<6) // Indicates ATS Translation Completion received in two rcbs (packets). Details are stored in tcpl_in_two_rcbs_details register.
40268     #define PGLUE_B_REG_INT_STS_CLR_TCPL_IN_TWO_RCBS_ATTN_SHIFT                                      6
40269     #define PGLUE_B_REG_INT_STS_CLR_CSSNOOP_FIFO_OVERFLOW                                            (0x1<<7) // Indicates an overflow in CSSNOOP sync fifo.
40270     #define PGLUE_B_REG_INT_STS_CLR_CSSNOOP_FIFO_OVERFLOW_SHIFT                                      7
40271     #define PGLUE_B_REG_INT_STS_CLR_TCPL_TRANSLATION_SIZE_DIFFERENT                                  (0x1<<8) // Indicates a function received a Translation Completion with a Translation Size field different than the Function programmed STU value. Note that the disable_tcpl_translation_size_check configuration does not affect this interrupt.
40272     #define PGLUE_B_REG_INT_STS_CLR_TCPL_TRANSLATION_SIZE_DIFFERENT_SHIFT                            8
40273     #define PGLUE_B_REG_INT_STS_CLR_PCIE_RX_L0S_TIMEOUT                                              (0x1<<9) // A PCIe IP debug signal indicating a failure to exit Rx_L0s correctly.  If this occurs "too frequently", this means that the N_FTS is too low and needs to be adjusted.
40274     #define PGLUE_B_REG_INT_STS_CLR_PCIE_RX_L0S_TIMEOUT_SHIFT                                        9
40275     #define PGLUE_B_REG_INT_STS_CLR_MASTER_ZLR_ATTN                                                  (0x1<<10) // Indicates a zero length read arrived from PSWRQ. Should not normally happen, but might happen with physical device assignement flow.
40276     #define PGLUE_B_REG_INT_STS_CLR_MASTER_ZLR_ATTN_SHIFT                                            10
40277     #define PGLUE_B_REG_INT_STS_CLR_ADMIN_WINDOW_VIOLATION_ATTN                                      (0x1<<11) // Indicates Read/Write accesses to the admin window that have a length bigger than 1DW or first byte enable != 0xf.
40278     #define PGLUE_B_REG_INT_STS_CLR_ADMIN_WINDOW_VIOLATION_ATTN_SHIFT                                11
40279     #define PGLUE_B_REG_INT_STS_CLR_OUT_OF_RANGE_FUNCTION_IN_PRETEND                                 (0x1<<12) // Indicates Target R/W where pretend register contains an out of range function. Relevant when number of PFs or VFs is not a power of two. In E4, it indicates VFID bigger than 95.
40280     #define PGLUE_B_REG_INT_STS_CLR_OUT_OF_RANGE_FUNCTION_IN_PRETEND_SHIFT                           12
40281     #define PGLUE_B_REG_INT_STS_CLR_ILLEGAL_ADDRESS                                                  (0x1<<13) // Indicates an illegal address event - address smaller than minimal_address_log or bigger than maximal_address_log. Details are stored in illegal_address_add and illegal_address_details registers.
40282     #define PGLUE_B_REG_INT_STS_CLR_ILLEGAL_ADDRESS_SHIFT                                            13
40283     #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ERR                                                      (0x1<<14) // Completion error received from core.
40284     #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ERR_SHIFT                                                14
40285     #define PGLUE_B_REG_INT_STS_CLR_PGL_TXW_OF                                                       (0x1<<15) // Overflow of tx write queue.
40286     #define PGLUE_B_REG_INT_STS_CLR_PGL_TXW_OF_SHIFT                                                 15
40287     #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_AFT                                                      (0x1<<16) // Overflow of cpl queue.
40288     #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_AFT_SHIFT                                                16
40289     #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_OF                                                       (0x1<<17) // Overflow error on completion or target write.
40290     #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_OF_SHIFT                                                 17
40291     #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ECRC                                                     (0x1<<18) // Ecrc error on completion or target write.
40292     #define PGLUE_B_REG_INT_STS_CLR_PGL_CPL_ECRC_SHIFT                                               18
40293     #define PGLUE_B_REG_INT_STS_CLR_PGL_PCIE_ATTN                                                    (0x1<<19) // Pcie core raised an attention.
40294     #define PGLUE_B_REG_INT_STS_CLR_PGL_PCIE_ATTN_SHIFT                                              19
40295     #define PGLUE_B_REG_INT_STS_CLR_PGL_READ_BLOCKED                                                 (0x1<<20) // Read was blocked due to master_en.
40296     #define PGLUE_B_REG_INT_STS_CLR_PGL_READ_BLOCKED_SHIFT                                           20
40297     #define PGLUE_B_REG_INT_STS_CLR_PGL_WRITE_BLOCKED                                                (0x1<<21) // Write was blocked due to master_en.
40298     #define PGLUE_B_REG_INT_STS_CLR_PGL_WRITE_BLOCKED_SHIFT                                          21
40299     #define PGLUE_B_REG_INT_STS_CLR_VF_ILT_ERR                                                       (0x1<<22) // Indicates a request received with VF ILT error indication from PSWRQ. The request was dropped. Details are stored in vf_ilt_err_add and vf_ilt_err_details registers.
40300     #define PGLUE_B_REG_INT_STS_CLR_VF_ILT_ERR_SHIFT                                                 22
40301     #define PGLUE_B_REG_INT_STS_CLR_RXOBFFEXCEPTION_ATTN                                             (0x1<<23) // Indicate rxobffexception_attn is asseted
40302     #define PGLUE_B_REG_INT_STS_CLR_RXOBFFEXCEPTION_ATTN_SHIFT                                       23
40303 #define PGLUE_B_REG_PRTY_MASK                                                                        0x2a8194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
40304     #define PGLUE_B_REG_PRTY_MASK_DATAPATH_REGISTERS                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS.DATAPATH_REGISTERS .
40305     #define PGLUE_B_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                           0
40306 #define PGLUE_B_REG_PRTY_MASK_H_0                                                                    0x2a8204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40307     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY                                              (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
40308     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_SHIFT                                        0
40309     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0                                        (0x1<<4) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
40310     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0_SHIFT                                  4
40311     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0                                        (0x1<<4) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
40312     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0_SHIFT                                  4
40313     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                           (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
40314     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                     1
40315     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                              (0x1<<2) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
40316     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                        2
40317     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                              (0x1<<3) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
40318     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                        3
40319     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                        (0x1<<5) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
40320     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                  5
40321     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0                                        (0x1<<5) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
40322     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                  5
40323     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                           (0x1<<4) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
40324     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                     4
40325     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY                                              (0x1<<5) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
40326     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_SHIFT                                        5
40327     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY                                              (0x1<<6) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
40328     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_SHIFT                                        6
40329     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                              (0x1<<7) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
40330     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                        7
40331     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY                                              (0x1<<8) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
40332     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_SHIFT                                        8
40333     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0                                        (0x1<<10) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
40334     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0_SHIFT                                  10
40335     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0                                        (0x1<<10) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
40336     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0_SHIFT                                  10
40337     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                           (0x1<<9) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
40338     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                     9
40339     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0                                        (0x1<<11) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
40340     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0_SHIFT                                  11
40341     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0                                        (0x1<<11) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
40342     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0_SHIFT                                  11
40343     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                           (0x1<<10) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
40344     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                     10
40345     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                        (0x1<<6) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
40346     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                  6
40347     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                        (0x1<<6) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
40348     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                  6
40349     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                           (0x1<<11) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
40350     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                     11
40351     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY                                              (0x1<<12) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
40352     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_SHIFT                                        12
40353     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY                                              (0x1<<13) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
40354     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_SHIFT                                        13
40355     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0                                        (0x1<<7) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
40356     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0_SHIFT                                  7
40357     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0                                        (0x1<<7) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
40358     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0_SHIFT                                  7
40359     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                           (0x1<<14) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
40360     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                     14
40361     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0                                        (0x1<<8) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
40362     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0_SHIFT                                  8
40363     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0                                        (0x1<<8) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
40364     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0_SHIFT                                  8
40365     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                           (0x1<<15) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
40366     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                     15
40367     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0                                        (0x1<<9) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
40368     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0_SHIFT                                  9
40369     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0                                        (0x1<<9) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
40370     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0_SHIFT                                  9
40371     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                           (0x1<<16) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
40372     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                     16
40373     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0                                        (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
40374     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0_SHIFT                                  0
40375     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0                                        (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
40376     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0_SHIFT                                  0
40377     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                           (0x1<<17) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
40378     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                     17
40379     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY                                              (0x1<<18) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
40380     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_SHIFT                                        18
40381     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY                                              (0x1<<19) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
40382     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_SHIFT                                        19
40383     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                              (0x1<<20) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
40384     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                        20
40385     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY                                              (0x1<<21) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
40386     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_SHIFT                                        21
40387     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY                                              (0x1<<22) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
40388     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT                                        22
40389     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                        (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
40390     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                  1
40391     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                        (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
40392     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                  1
40393     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                           (0x1<<23) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
40394     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                     23
40395     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0                                        (0x1<<12) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
40396     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0_SHIFT                                  12
40397     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0                                        (0x1<<12) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
40398     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0_SHIFT                                  12
40399     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                           (0x1<<24) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
40400     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                     24
40401     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_BB_A0                                      (0x1<<13) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
40402     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_BB_A0_SHIFT                                13
40403     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_BB_B0                                      (0x1<<13) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
40404     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_BB_B0_SHIFT                                13
40405     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_K2                                         (0x1<<25) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_0 .
40406     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_0_K2_SHIFT                                   25
40407     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_BB_A0                                      (0x1<<14) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
40408     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_BB_A0_SHIFT                                14
40409     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_BB_B0                                      (0x1<<14) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
40410     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_BB_B0_SHIFT                                14
40411     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_K2                                         (0x1<<26) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_1 .
40412     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_1_K2_SHIFT                                   26
40413     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_BB_A0                                      (0x1<<15) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_2 .
40414     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_BB_A0_SHIFT                                15
40415     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_BB_B0                                      (0x1<<15) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_2 .
40416     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_BB_B0_SHIFT                                15
40417     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_K2                                         (0x1<<27) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_2 .
40418     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_2_K2_SHIFT                                   27
40419     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_BB_A0                                      (0x1<<16) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_3 .
40420     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_BB_A0_SHIFT                                16
40421     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_BB_B0                                      (0x1<<16) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_3 .
40422     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_BB_B0_SHIFT                                16
40423     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_K2                                         (0x1<<28) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_3 .
40424     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_3_K2_SHIFT                                   28
40425     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_BB_A0                                      (0x1<<17) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_4 .
40426     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_BB_A0_SHIFT                                17
40427     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_BB_B0                                      (0x1<<17) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_4 .
40428     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_BB_B0_SHIFT                                17
40429     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_K2                                         (0x1<<29) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_4 .
40430     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_4_K2_SHIFT                                   29
40431     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_BB_A0                                      (0x1<<18) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_5 .
40432     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_BB_A0_SHIFT                                18
40433     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_BB_B0                                      (0x1<<18) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_5 .
40434     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_BB_B0_SHIFT                                18
40435     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_K2                                         (0x1<<30) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_5 .
40436     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_5_K2_SHIFT                                   30
40437     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_6                                            (0x1<<19) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_6 .
40438     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_6_SHIFT                                      19
40439     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_7                                            (0x1<<20) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY_7 .
40440     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_7_SHIFT                                      20
40441     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                              (0x1<<21) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
40442     #define PGLUE_B_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                        21
40443 #define PGLUE_B_REG_PRTY_MASK_H_1_K2                                                                 0x2a8214UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: K2
40444     #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_6                                            (0x1<<0) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY_6 .
40445     #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_6_SHIFT                                      0
40446     #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_7                                            (0x1<<1) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY_7 .
40447     #define PGLUE_B_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_7_SHIFT                                      1
40448     #define PGLUE_B_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY                                              (0x1<<2) // This bit masks, when set, the Parity bit: PGLUE_B_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
40449     #define PGLUE_B_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_SHIFT                                        2
40450 #define PGLUE_B_REG_MEM_ECC_EVENTS_BB_A0                                                             0x2a8210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0
40451 #define PGLUE_B_REG_MEM_ECC_EVENTS_BB_B0                                                             0x2a8210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_B0
40452 #define PGLUE_B_REG_MEM_ECC_EVENTS_K2                                                                0x2a8220UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
40453 #define PGLUE_B_REG_MEM027_I_MEM_DFT_K2                                                              0x2a822cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_txw_dp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40454 #define PGLUE_B_REG_MEM007_I_MEM_DFT_K2                                                              0x2a8230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_cpl_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40455 #define PGLUE_B_REG_MEM009_I_MEM_DFT_K2                                                              0x2a8234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_dbgsyn_mem_e0.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40456 #define PGLUE_B_REG_MEM010_I_MEM_DFT_K2                                                              0x2a8238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_dbgsyn_mem_e1.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40457 #define PGLUE_B_REG_MEM008_I_MEM_DFT_K2                                                              0x2a823cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_dbgcoresyn_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40458 #define PGLUE_B_REG_MEM022_I_MEM_DFT_K2                                                              0x2a8240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_ptt_part1_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
40459 #define PGLUE_B_REG_MEM023_I_MEM_DFT_K2                                                              0x2a8244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_ptt_part2_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
40460 #define PGLUE_B_REG_MEM025_I_MEM_DFT_K2                                                              0x2a8248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_ptt_part4_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
40461 #define PGLUE_B_REG_MEM011_I_MEM_DFT_K2                                                              0x2a824cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_credit_syncfifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40462 #define PGLUE_B_REG_MEM016_I_MEM_DFT_K2                                                              0x2a8250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_rx_h_syncfifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40463 #define PGLUE_B_REG_MEM017_I_MEM_DFT_K2                                                              0x2a8254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_rx_hd_syncfifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40464 #define PGLUE_B_REG_MEM012_I_MEM_DFT_K2                                                              0x2a8258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_rx_d_syncfifo_e0.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40465 #define PGLUE_B_REG_MEM013_I_MEM_DFT_K2                                                              0x2a825cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_rx_d_syncfifo_e1.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40466 #define PGLUE_B_REG_MEM014_I_MEM_DFT_K2                                                              0x2a8260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_rx_d_syncfifo_e2.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40467 #define PGLUE_B_REG_MEM015_I_MEM_DFT_K2                                                              0x2a8264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_rx_d_syncfifo_e3.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40468 #define PGLUE_B_REG_MEM018_I_MEM_DFT_K2                                                              0x2a8268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_txcpl_h_syncfifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40469 #define PGLUE_B_REG_MEM020_I_MEM_DFT                                                                 0x2a826cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_txw_d_syncfifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40470 #define PGLUE_B_REG_MEM021_I_MEM_DFT                                                                 0x2a8270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_txw_h_syncfifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40471 #define PGLUE_B_REG_MEM019_I_MEM_DFT                                                                 0x2a8274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_pci_core_txr_h_syncfifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
40472 #define PGLUE_B_REG_MEM026_I_MEM_DFT                                                                 0x2a8278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.pgl_tag_for_flr.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40473 #define PGLUE_B_REG_MEM003_I_MEM_DFT                                                                 0x2a827cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.TAG_DB_128_GEN_IF.pgl_tag_database.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
40474 #define PGLUE_B_REG_MEM002_I_MEM_DFT                                                                 0x2a8280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.INB_MEM_1_ENGINE_GEN_IF.pgl_inb_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
40475 #define PGLUE_B_REG_MEM001_I_MEM_DFT                                                                 0x2a8284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pgl.i_pgl_memory_wrappers.GTT_1_ENGINE_GEN_IF.pgl_gtt_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
40476 #define PGLUE_B_REG_DBG_SELECT                                                                       0x2a8400UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
40477 #define PGLUE_B_REG_DBG_DWORD_ENABLE                                                                 0x2a8404UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
40478 #define PGLUE_B_REG_DBG_SHIFT                                                                        0x2a8408UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
40479 #define PGLUE_B_REG_DBG_FORCE_VALID                                                                  0x2a840cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
40480 #define PGLUE_B_REG_DBG_FORCE_FRAME                                                                  0x2a8410UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
40481 #define PGLUE_B_REG_DBG_OUT_DATA                                                                     0x2a8420UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
40482 #define PGLUE_B_REG_DBG_OUT_DATA_SIZE                                                                8
40483 #define PGLUE_B_REG_DBG_OUT_VALID                                                                    0x2a8440UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
40484 #define PGLUE_B_REG_DBG_OUT_FRAME                                                                    0x2a8444UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
40485 #define PGLUE_B_REG_PGL_ECO_RESERVED                                                                 0x2a8460UL //Access:RW   DataWidth:0x20  Debug only: Reserved bits for ECO. Bit 0 - for Atomic Op / MRD handling of NPH credits. 0 - Can send both if there is one NPH credit and this may cause HOL blocking on user TX interface and theoretically cause deadlock between RC and device. 1 - Each waits for 2 NPH credits to be sent.  Chips: BB_A0 BB_B0 K2
40486 #define PGLUE_B_REG_PGL_ECO_RESERVED2                                                                0x2a8464UL //Access:RW   DataWidth:0x20  Debug only: Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
40487 #define PGLUE_B_REG_DBGSYN_ALMOST_FULL_THR                                                           0x2a8468UL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: BB_A0 BB_B0 K2
40488 #define PGLUE_B_REG_DBGBUS_PATH_SELECT                                                               0x2a846cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40489     #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E0                                     (0x1<<0) // 0 - Debug bus is not output to RBCN_e0. 1 - Debug bus is output to RBCN_e0.
40490     #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E0_SHIFT                               0
40491     #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E1                                     (0x1<<1) // 0 - Debug bus is not output to RBCN_e1. 1 - Debug bus is output to RBCN_e1.
40492     #define PGLUE_B_REG_DBGBUS_PATH_SELECT_DBGBUS_PATH_SELECT_E1_SHIFT                               1
40493 #define PGLUE_B_REG_PGL_DEBUG                                                                        0x2a8470UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40494     #define PGLUE_B_REG_PGL_DEBUG_PGL_TXR_RELAX                                                      (0x1<<0) // Debug only.
40495     #define PGLUE_B_REG_PGL_DEBUG_PGL_TXR_RELAX_SHIFT                                                0
40496     #define PGLUE_B_REG_PGL_DEBUG_PGL_TXW_RELAX                                                      (0x1<<1) // Debug only.
40497     #define PGLUE_B_REG_PGL_DEBUG_PGL_TXW_RELAX_SHIFT                                                1
40498     #define PGLUE_B_REG_PGL_DEBUG_PGL_DISABLE                                                        (0x1<<2) // Debug only.
40499     #define PGLUE_B_REG_PGL_DEBUG_PGL_DISABLE_SHIFT                                                  2
40500 #define PGLUE_B_REG_PGL_MOT                                                                          0x2a8474UL //Access:R    DataWidth:0x6   Debug only.  Chips: BB_A0 BB_B0 K2
40501 #define PGLUE_B_REG_PGL_CORE_DEBUG                                                                   0x2a8478UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40502     #define PGLUE_B_REG_PGL_CORE_DEBUG_SEL_1                                                         (0xf<<0) // Pcie core debug mux select 1. this field controls the output of the debug bus of the pcie_core.
40503     #define PGLUE_B_REG_PGL_CORE_DEBUG_SEL_1_SHIFT                                                   0
40504     #define PGLUE_B_REG_PGL_CORE_DEBUG_SEL_2                                                         (0xf<<4) // Pcie core debug mux select 2.
40505     #define PGLUE_B_REG_PGL_CORE_DEBUG_SEL_2_SHIFT                                                   4
40506     #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_PARITY_MODE                                               (0x1<<8) // This bit forces a parity error in the replay buffer.
40507     #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_PARITY_MODE_SHIFT                                         8
40508     #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_TXARB_SP                                                  (0x1<<9) // This bit give strict priority to read over write on the PGL read-write arbiter.
40509     #define PGLUE_B_REG_PGL_CORE_DEBUG_PGL_TXARB_SP_SHIFT                                            9
40510 #define PGLUE_B_REG_PGL_PM_STATUS                                                                    0x2a847cUL //Access:R    DataWidth:0x10  Contains pcie_func_hidden vector.  Chips: BB_A0 BB_B0 K2
40511 #define PGLUE_B_REG_PGL_WRITE_BLOCKED                                                                0x2a8480UL //Access:R    DataWidth:0x2   Bit 0: This bit indicates that a write request was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that currently a write request is blocked due to any of the blocking conditions.  Chips: BB_A0 BB_B0 K2
40512 #define PGLUE_B_REG_PGL_READ_BLOCKED                                                                 0x2a8484UL //Access:R    DataWidth:0x2   Bit 0: This bit indicates that a read request was blocked because of bus_master_en was deasserted. Bit 1: Added in BigBear-B0. Indicates that currently a read request is blocked due to any of the blocking conditions.  Chips: BB_A0 BB_B0 K2
40513 #define PGLUE_B_REG_READ_FIFO_OCCUPANCY_LEVEL                                                        0x2a8488UL //Access:R    DataWidth:0x4   Debug only: Occupancy level in PGLUE master read FIFO. This is the driver counter.  Chips: BB_A0 BB_B0 K2
40514 #define PGLUE_B_REG_WRITE_FIFO_MAX_OCCUPANCY_LEVEL                                                   0x2a848cUL //Access:R    DataWidth:0x5   Debug only: Maximal occupancy level in PGLUE master write FIFO.  Chips: BB_A0 BB_B0 K2
40515 #define PGLUE_B_REG_READ_FIFO_MAX_OCCUPANCY_LEVEL                                                    0x2a8490UL //Access:R    DataWidth:0x4   Debug only: Maximal occupancy level in PGLUE master read FIFO.  Chips: BB_A0 BB_B0 K2
40516 #define PGLUE_B_REG_WRITE_FIFO_WRITE_PTR                                                             0x2a8494UL //Access:R    DataWidth:0x5   Debug only: Write pointer in PGLUE master write FIFO.  Chips: BB_A0 BB_B0 K2
40517 #define PGLUE_B_REG_WRITE_FIFO_DRIVER_READ_PTR                                                       0x2a8498UL //Access:R    DataWidth:0x5   Debug only: Driver read pointer in PGLUE master write FIFO.  Chips: BB_A0 BB_B0 K2
40518 #define PGLUE_B_REG_WRITE_FIFO_FILLER_READ_PTR                                                       0x2a849cUL //Access:R    DataWidth:0x5   Debug only: Filler read pointer in PGLUE master write FIFO.  Chips: BB_A0 BB_B0 K2
40519 #define PGLUE_B_REG_READ_FIFO_WRITE_PTR                                                              0x2a84a0UL //Access:R    DataWidth:0x4   Debug only: Write pointer in PGLUE master read FIFO.  Chips: BB_A0 BB_B0 K2
40520 #define PGLUE_B_REG_READ_FIFO_DRIVER_READ_PTR                                                        0x2a84a4UL //Access:R    DataWidth:0x4   Debug only: Driver read pointer in PGLUE master read FIFO.  Chips: BB_A0 BB_B0 K2
40521 #define PGLUE_B_REG_MAX_USED_TAGS                                                                    0x2a84a8UL //Access:R    DataWidth:0x9   Debug only: Maximal number of used tags at a given time since reset.  Chips: BB_A0 BB_B0 K2
40522 #define PGLUE_B_REG_RX_LEGACY_ERRORS                                                                 0x2a84acUL //Access:R    DataWidth:0x8   Each bit indicates a type of legacy error that was received in user RX interface since last reset. Note that such errors are legitimate. Bit 0 - Target memory read arrived with a correctable error. Bit 1 - Target memory read arrived with an uncorrectable error. Bit 2 - Configuration RW arrived with a correctable error. Bit 3 - Configuration RW arrived with an uncorrectable error. Bit 4 - Target memory write or MSGD arrived with a correctable error. Bit 5 - Target memory write or MSGD arrived with an uncorrectable error. Bit 6 - Master completion arrived with a correctable error. Bit 7 - Master completion arrived with an uncorrectable error.  Chips: BB_A0 BB_B0 K2
40523 #define PGLUE_B_REG_PCIE_DBGSYN_ALMOST_FULL_THR                                                      0x2a84b0UL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the PCIe dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: BB_A0 BB_B0 K2
40524 #define PGLUE_B_REG_PCIE_DBGSYN_ENABLE                                                               0x2a84b4UL //Access:RW   DataWidth:0x1   Debug only: When 1, PCIe dbgsyn clock synchronization FIFO is enabled and frame, valid, data are output from it to the debug block. When 0, PCIe dbgsyn clock synchronization FIFO is disabled and pcie_top_wrapper should output 0 in frame, valid and data outputs.  Chips: BB_A0 BB_B0 K2
40525 #define PGLUE_B_REG_DISABLE_HIGHER_BW                                                                0x2a84b8UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40526     #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_HIGHER_BW_WAW                                      (0x1<<0) // Debug only. Used to disable an E2 optimization of having less dead cycles between adjacent write request (write after write) from PGLUE to PCIe core. When disable_two_pending_wr_requests is 0; this bit must be 0 as well.
40527     #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_HIGHER_BW_WAW_SHIFT                                0
40528     #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_REQUESTS                               (0x1<<1) // Debug only. Used to disable an E2 optimization of sending two pending requests from PGLUE to PCIe core. The two pending requests are of different types (master write; master read; target completion).
40529     #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_REQUESTS_SHIFT                         1
40530     #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_WR_REQUESTS                            (0x1<<2) // Debug only. Used to disable an E2 optimization of sending two pending write requests from PGLUE to PCIe core. When this bit is 0; disable_higher_bw_waw must be 0 as well.
40531     #define PGLUE_B_REG_DISABLE_HIGHER_BW_DISABLE_TWO_PENDING_WR_REQUESTS_SHIFT                      2
40532 #define PGLUE_B_REG_MEMCTRL_WR_RD_N                                                                  0x2a84bcUL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
40533 #define PGLUE_B_REG_MEMCTRL_CMD                                                                      0x2a84c0UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
40534 #define PGLUE_B_REG_MEMCTRL_ADDRESS                                                                  0x2a84c4UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
40535 #define PGLUE_B_REG_MEMCTRL_STATUS                                                                   0x2a84c8UL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0 K2
40536 #define PGLUE_B_REG_PCIE_CHECKSUM_ERROR                                                              0x2a84ccUL //Access:R    DataWidth:0x1   Indicates there was an error in PCIe checksum in data from PCIe core.  Chips: BB_B0 K2
40537 #define PGLUE_B_REG_REMOVE_PCIE_CHECKSUM                                                             0x2a84d0UL //Access:RW   DataWidth:0x1   Debug only: 0 - PCIe checksum is generated towards PCIe core. 1 - PCIe checksum is not generated towards PCIe core. This is a chicken bit in case that the extra sample added for checksum calculation needs to be bypassed.  Chips: BB_B0 K2
40538 #define PGLUE_B_REG_TC_PER_VQ                                                                        0x2a84d4UL //Access:RW   DataWidth:0x20  A bit per VQ that indicates the TC to use.  Chips: BB_B0 K2
40539 #define PGLUE_B_REG_PSEUDO_VF_MASTER_ENABLE                                                          0x2a84d8UL //Access:RW   DataWidth:0x1   Enable for pseudo VF master mode.  Chips: BB_B0 K2
40540 #define PGLUE_B_REG_PSEUDO_VF_TARGET_ENABLE                                                          0x2a84dcUL //Access:RW   DataWidth:0x1   Enable for pseudo VF target mode.  Chips: BB_B0 K2
40541 #define PGLUE_B_REG_LOG2_F_DB_WND                                                                    0x2a84e0UL //Access:RW   DataWidth:0x5   Pseudo VF target mode configuration that controls the size of each pseudo-VF in the BAR.  Chips: BB_B0 K2
40542 #define PGLUE_B_REG_VF_BASE                                                                          0x2a84e4UL //Access:RW   DataWidth:0x5   Pseudo VF target mode configuration that defines first VF divided by 8 for each PF.  Chips: BB_B0 K2
40543 #define PGLUE_B_REG_PGL_CONTROL0                                                                     0x2a8520UL //Access:RW   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40544     #define PGLUE_B_REG_PGL_CONTROL0_PGL_CPL_AFT                                                     (0x7f<<0) // Almost full threshold for completion interface (debug purposes).
40545     #define PGLUE_B_REG_PGL_CONTROL0_PGL_CPL_AFT_SHIFT                                               0
40546     #define PGLUE_B_REG_PGL_CONTROL0_PGL_DISABLE_INPUTS                                              (0x1<<7) // Debug only: disable inputs to pgl.
40547     #define PGLUE_B_REG_PGL_CONTROL0_PGL_DISABLE_INPUTS_SHIFT                                        7
40548     #define PGLUE_B_REG_PGL_CONTROL0_PGL_TXW_CC_THRESH                                               (0x1f<<8) // The fullness threshold of the txw data fifo after which transaction may start.
40549     #define PGLUE_B_REG_PGL_CONTROL0_PGL_TXW_CC_THRESH_SHIFT                                         8
40550     #define PGLUE_B_REG_PGL_CONTROL0_PGL_TXW_DP_AFT                                                  (0x3f<<13) // The fullnes threshold of the txw data fifo after which the block stops reading from pswwr.
40551     #define PGLUE_B_REG_PGL_CONTROL0_PGL_TXW_DP_AFT_SHIFT                                            13
40552 #define PGLUE_B_REG_CSSNOOP_ALMOST_FULL_THR                                                          0x2a8524UL //Access:RW   DataWidth:0x2   Debug only: If more than this Number of entries are occupied in the cssnoop clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: BB_A0 BB_B0 K2
40553 #define PGLUE_B_REG_TXW_H_SYNCFIFO_ALMOSTFULL_TH                                                     0x2a8528UL //Access:RW   DataWidth:0x5   Debug only: If more than this Number of entries are occupied in the TXW header clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: K2
40554 #define PGLUE_B_REG_TXW_D_SYNCFIFO_ALMOSTFULL_TH                                                     0x2a852cUL //Access:RW   DataWidth:0x5   Debug only: If more than this Number of entries are occupied in the TXW data clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: K2
40555 #define PGLUE_B_REG_TXR_H_SYNCFIFO_ALMOSTFULL_TH                                                     0x2a8530UL //Access:RW   DataWidth:0x5   Debug only: If more than this Number of entries are occupied in the TXR header clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: K2
40556 #define PGLUE_B_REG_PGL_TXR_CDTS                                                                     0x2a8560UL //Access:R    DataWidth:0x9   Debug only.  Chips: BB_A0 BB_B0 K2
40557 #define PGLUE_B_REG_PGL_TXW_CDTS                                                                     0x2a8564UL //Access:R    DataWidth:0x15  Debug only.  Chips: BB_A0 BB_B0 K2
40558 #define PGLUE_B_REG_ADMIN_PER_PF_REGION                                                              0x2a9000UL //Access:RW   DataWidth:0x20  This register maps the Admin per-PF region. Addresses 0x0 - 0x5c: 12 per-PF PF windows. Each PF window contains two 32-bit values. The low address (0, 2, and on) contains the 22-bit offset register. The high address (1, 3 and on) contains the pretend registers. Addresses 0x60-0x1ec: reserved. Address 0x1f0: Global pretend register. Address 0x1f4 - reserved. Address 0x1f8 - ME opaque register. Address 0x1fc - ME concrete register. E4: split16. Note that the reset values of the read only addresses is not X. The reset value of the reserved addresses is 0.  Chips: BB_A0 BB_B0 K2
40559 #define PGLUE_B_REG_ADMIN_PER_PF_REGION_SIZE                                                         128
40560 #define PGLUE_B_REG_ADMIN_GLOBAL_REGION                                                              0x2a9200UL //Access:RW   DataWidth:0x20  This register maps the Admin global region. 0x0 - 0x3c8 (0x200 - 0x5c8) -  243 global windows. Each entry is the 12-bit window offset. Addresses 0x3cc - 0xe08 (0x5cc - 0xffc) - reserved (reset value 0).  Chips: BB_A0 BB_B0 K2
40561 #define PGLUE_B_REG_ADMIN_GLOBAL_REGION_SIZE                                                         896
40562 #define PGLUE_B_REG_CFG_SPACE_A_ADDRESS                                                              0x2aa000UL //Access:RW   DataWidth:0x6   Address[12:7] in PCI configuration space of the first register on which config space A attention is generated. Note that this register is in 128-byte units.  Chips: BB_A0 BB_B0 K2
40563 #define PGLUE_B_REG_CFG_SPACE_A_ENABLE                                                               0x2aa004UL //Access:RW   DataWidth:0x20  Indicates which of the 32 registers starting in address cfg_space_a_address generates an attention. If bit N is set - a CSSNOOP cycle with address {cfg_space_a_address; 7b0}+4*N will generate a config space A attention.  Chips: BB_A0 BB_B0 K2
40564 #define PGLUE_B_REG_CFG_SPACE_B_ADDRESS                                                              0x2aa008UL //Access:RW   DataWidth:0x6   Address[12:7] in PCI configuration space of the first register on which config space B attention is generated. Note that this register is in 128-byte units.  Chips: BB_A0 BB_B0 K2
40565 #define PGLUE_B_REG_CFG_SPACE_B_ENABLE                                                               0x2aa00cUL //Access:RW   DataWidth:0x20  Indicates which of the 32 registers starting in address cfg_space_b_address generates an attention. If bit N is set - a CSSNOOP cycle with address {cfg_space_b_address; 7b0}+4*N will generate a config space B attention.  Chips: BB_A0 BB_B0 K2
40566 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST                                                              0x2aa010UL //Access:R    DataWidth:0x10  Config space A attention dirty bits. Each bit indicates that the corresponding PF generates config space A attention. Set by PXP. Reset by MCP writing 1 to icfg_space_a_request_clr. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40567 #define PGLUE_B_REG_CFG_SPACE_A_REQUEST_CLR                                                          0x2aa014UL //Access:W    DataWidth:0x10  Config space A attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in cfg_space_a_request register. Note: register contains bits from both paths. Note: Need to re-read the enabled registers after clearing the dirty bit and then check the dirty bit is still clear since they may have been written again during the scan.  Chips: BB_A0 BB_B0 K2
40568 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST                                                              0x2aa018UL //Access:R    DataWidth:0x10  Config space B attention dirty bits. Each bit indicates that the corresponding PF generates config space B attention. Set by PXP. Reset by MCP writing 1 to icfg_space_b_request_clr. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40569 #define PGLUE_B_REG_CFG_SPACE_B_REQUEST_CLR                                                          0x2aa01cUL //Access:W    DataWidth:0x10  Config space B attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in cfg_space_b_request register. Note: register contains bits from both paths. Note: Need to re-read the enabled registers after clearing the dirty bit and then check the dirty bit is still clear since they may have been written again during the scan.  Chips: BB_A0 BB_B0 K2
40570 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0                                                              0x2aa020UL //Access:R    DataWidth:0x20  FLR request attention dirty bits for VFs 0 to 31. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_31_0_clr.  Chips: BB_A0 BB_B0 K2
40571 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32                                                             0x2aa024UL //Access:R    DataWidth:0x20  FLR request attention dirty bits for VFs 32 to 63. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_63_32_clr.  Chips: BB_A0 BB_B0 K2
40572 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64                                                             0x2aa028UL //Access:R    DataWidth:0x20  FLR request attention dirty bits for VFs 64 to 95. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_95_64_clr.  Chips: BB_A0 BB_B0 K2
40573 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96                                                            0x2aa02cUL //Access:R    DataWidth:0x20  FLR request attention dirty bits for VFs 96 to 127. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_127_96_clr.  Chips: BB_A0 BB_B0 K2
40574 #define PGLUE_B_REG_FLR_REQUEST_VF_159_128                                                           0x2aa030UL //Access:R    DataWidth:0x20  FLR request attention dirty bits for VFs 128 to 159. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_159_128_clr.  Chips: BB_A0 BB_B0 K2
40575 #define PGLUE_B_REG_FLR_REQUEST_VF_191_160                                                           0x2aa034UL //Access:R    DataWidth:0x20  FLR request attention dirty bits for VFs 160 to 191. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_191_160_clr.  Chips: BB_A0 BB_B0 K2
40576 #define PGLUE_B_REG_FLR_REQUEST_VF_223_192                                                           0x2aa038UL //Access:R    DataWidth:0x20  FLR request attention dirty bits for VFs 192 to 223. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_223_192_clr.  Chips: BB_A0 BB_B0 K2
40577 #define PGLUE_B_REG_FLR_REQUEST_VF_255_224                                                           0x2aa03cUL //Access:R    DataWidth:0x20  FLR request attention dirty bits for VFs 224 to 255. Each bit indicates that the FLR register of the corresponding VF was set. Set by PXP. Reset by MCP writing 1 to flr_request_vf_255_224_clr.  Chips: BB_A0 BB_B0 K2
40578 #define PGLUE_B_REG_FLR_REQUEST_PF_31_0                                                              0x2aa040UL //Access:R    DataWidth:0x10  FLR request attention dirty bits for all PFs. Each bit indicates that the FLR register of the corresponding PF was set. Set by PXP. Reset by MCP writing 1 to flr_request_pf_31_0_clr. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40579 #define PGLUE_B_REG_FLR_REQUEST_VF_31_0_CLR                                                          0x2aa044UL //Access:W    DataWidth:0x20  FLR request attention dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_31_0 register.  Chips: BB_A0 BB_B0 K2
40580 #define PGLUE_B_REG_FLR_REQUEST_VF_63_32_CLR                                                         0x2aa048UL //Access:W    DataWidth:0x20  FLR request attention dirty bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_63_32 register.  Chips: BB_A0 BB_B0 K2
40581 #define PGLUE_B_REG_FLR_REQUEST_VF_95_64_CLR                                                         0x2aa04cUL //Access:W    DataWidth:0x20  FLR request attention dirty bits clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_95_64 register.  Chips: BB_A0 BB_B0 K2
40582 #define PGLUE_B_REG_FLR_REQUEST_VF_127_96_CLR                                                        0x2aa050UL //Access:W    DataWidth:0x20  FLR request attention dirty bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_127_96 register.  Chips: BB_A0 BB_B0 K2
40583 #define PGLUE_B_REG_FLR_REQUEST_VF_159_128_CLR                                                       0x2aa054UL //Access:W    DataWidth:0x20  FLR request attention dirty bits clear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_159_128 register.  Chips: BB_A0 BB_B0 K2
40584 #define PGLUE_B_REG_FLR_REQUEST_VF_191_160_CLR                                                       0x2aa058UL //Access:W    DataWidth:0x20  FLR request attention dirty bits clear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_191_160 register.  Chips: BB_A0 BB_B0 K2
40585 #define PGLUE_B_REG_FLR_REQUEST_VF_223_192_CLR                                                       0x2aa05cUL //Access:W    DataWidth:0x20  FLR request attention dirty bits clear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_223_192 register.  Chips: BB_A0 BB_B0 K2
40586 #define PGLUE_B_REG_FLR_REQUEST_VF_255_224_CLR                                                       0x2aa060UL //Access:W    DataWidth:0x20  FLR request attention dirty bits clear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_vf_255_224 register.  Chips: BB_A0 BB_B0 K2
40587 #define PGLUE_B_REG_FLR_REQUEST_PF_31_0_CLR                                                          0x2aa064UL //Access:W    DataWidth:0x10  FLR request attention dirty bits clear for all PFs.  MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40588 #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED                                                       0x2aa068UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40589     #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_FLR_REQUEST                               (0x1<<0) // Debug only: When 1 flr request is not generated by PGLUE.
40590     #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_FLR_REQUEST_SHIFT                         0
40591     #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_SRIOV_DISABLED_REQUEST                    (0x1<<1) // Debug only: When 1 SR-IOV disbaled request is not generated by PGLUE.
40592     #define PGLUE_B_REG_DISABLE_FLR_SRIOV_DISABLED_DISABLE_SRIOV_DISABLED_REQUEST_SHIFT              1
40593 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST                                                          0x2aa06cUL //Access:R    DataWidth:0x10  SR IOV disabled attention dirty bits. Each bit indicates that the VF enable register of the corresponding PF is written to 0 and was previously 1. Set by PXP. Reset by MCP writing 1 to sr_iov_disabled_request_clr. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40594 #define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR                                                      0x2aa070UL //Access:W    DataWidth:0x10  SR IOV disabled attention dirty bits clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in sr_iov_disabled_request register. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40595 #define PGLUE_B_REG_SHADOW_BME_VF_31_0                                                               0x2aa074UL //Access:R    DataWidth:0x20  Shadow BME register for VFs 0 to 31. Each bit indicates if the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40596 #define PGLUE_B_REG_SHADOW_BME_VF_63_32                                                              0x2aa078UL //Access:R    DataWidth:0x20  Shadow BME register for VFs 32 to 63. Each bit indicates if the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40597 #define PGLUE_B_REG_SHADOW_BME_VF_95_64                                                              0x2aa07cUL //Access:R    DataWidth:0x20  Shadow BME register for VFs 64 to 95. Each bit indicates if the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40598 #define PGLUE_B_REG_SHADOW_BME_VF_127_96                                                             0x2aa080UL //Access:R    DataWidth:0x20  Shadow BME register for VFs 96 to 127. Each bit indicates if the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40599 #define PGLUE_B_REG_SHADOW_BME_VF_159_128                                                            0x2aa084UL //Access:R    DataWidth:0x20  Shadow BME register for VFs 128 to 159. Each bit indicates if the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40600 #define PGLUE_B_REG_SHADOW_BME_VF_191_160                                                            0x2aa088UL //Access:R    DataWidth:0x20  Shadow BME register for VFs 160 to 191. Each bit indicates if the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40601 #define PGLUE_B_REG_SHADOW_BME_VF_223_192                                                            0x2aa08cUL //Access:R    DataWidth:0x20  Shadow BME register for VFs 192 to 223. Each bit indicates if the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40602 #define PGLUE_B_REG_SHADOW_BME_VF_255_224                                                            0x2aa090UL //Access:R    DataWidth:0x20  Shadow BME register for VFs 224 to 255. Each bit indicates if the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40603 #define PGLUE_B_REG_SHADOW_BME_PF_31_0                                                               0x2aa094UL //Access:R    DataWidth:0x10  Shadow BME register for all PFs. Each bit indicates if the corresponding PF is enabled. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40604 #define PGLUE_B_REG_SHADOW_VF_31_0_CLR                                                               0x2aa098UL //Access:W    DataWidth:0x20  Shadow bits clear for VFs 0 to 31.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.  Chips: BB_A0 BB_B0 K2
40605 #define PGLUE_B_REG_SHADOW_VF_63_32_CLR                                                              0x2aa09cUL //Access:W    DataWidth:0x20  Shadow bits clear for VFs 32 to 63.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.  Chips: BB_A0 BB_B0 K2
40606 #define PGLUE_B_REG_SHADOW_VF_95_64_CLR                                                              0x2aa0a0UL //Access:W    DataWidth:0x20  Shadow bits clear for VFs 64 to 95.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.  Chips: BB_A0 BB_B0 K2
40607 #define PGLUE_B_REG_SHADOW_VF_127_96_CLR                                                             0x2aa0a4UL //Access:W    DataWidth:0x20  Shadow bits clear for VFs 96 to 127.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40608 #define PGLUE_B_REG_SHADOW_VF_159_128_CLR                                                            0x2aa0a8UL //Access:W    DataWidth:0x20  Shadow bits clear for VFs 128 to 159.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.  Chips: BB_A0 BB_B0 K2
40609 #define PGLUE_B_REG_SHADOW_VF_191_160_CLR                                                            0x2aa0acUL //Access:W    DataWidth:0x20  Shadow bits clear for VFs 160 to 191.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.  Chips: BB_A0 BB_B0 K2
40610 #define PGLUE_B_REG_SHADOW_VF_223_192_CLR                                                            0x2aa0b0UL //Access:W    DataWidth:0x20  Shadow bits clear for VFs 192 to 223.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.  Chips: BB_A0 BB_B0 K2
40611 #define PGLUE_B_REG_SHADOW_VF_255_224_CLR                                                            0x2aa0b4UL //Access:W    DataWidth:0x20  Shadow bits clear for VFs 224 to 255.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should do this in PF-FLR and SR-IOV-disabled events.  Chips: BB_A0 BB_B0 K2
40612 #define PGLUE_B_REG_SHADOW_PF_31_0_CLR                                                               0x2aa0b8UL //Access:W    DataWidth:0x10  Debug only - Shadow bits clear for PFs 0 to 31.  MCP writes 1 to a bit in this register in order to reset the corresponding VF BME, ATS_enable, TPH_requester_enable, ST_mode_select fields. MCP should never use this unless a work-around is needed. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40613 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_31_0                                                        0x2aa0bcUL //Access:R    DataWidth:0x20  Shadow ats_enable register for VFs 0 to 31. Each bit indicates if ATS for the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40614 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_63_32                                                       0x2aa0c0UL //Access:R    DataWidth:0x20  Shadow ats_enable register for VFs 32 to 63. Each bit indicates if ATS for the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40615 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_95_64                                                       0x2aa0c4UL //Access:R    DataWidth:0x20  Shadow ats_enable register for VFs 64 to 95. Each bit indicates if ATS for the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40616 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_127_96                                                      0x2aa0c8UL //Access:R    DataWidth:0x20  Shadow ats_enable register for VFs 96 to 127. Each bit indicates if ATS for the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40617 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_159_128                                                     0x2aa0ccUL //Access:R    DataWidth:0x20  Shadow ats_enable register for VFs 128 to 159. Each bit indicates if ATS for the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40618 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_191_160                                                     0x2aa0d0UL //Access:R    DataWidth:0x20  Shadow ats_enable register for VFs 160 to 191. Each bit indicates if ATS for the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40619 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_223_192                                                     0x2aa0d4UL //Access:R    DataWidth:0x20  Shadow ats_enable register for VFs 192 to 223. Each bit indicates if ATS for the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40620 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_VF_255_224                                                     0x2aa0d8UL //Access:R    DataWidth:0x20  Shadow ats_enable register for VFs 224 to 255. Each bit indicates if ATS for the corresponding VF is enabled.  Chips: BB_A0 BB_B0 K2
40621 #define PGLUE_B_REG_SHADOW_ATS_ENABLE_PF_31_0                                                        0x2aa0dcUL //Access:R    DataWidth:0x10  Shadow ats_enable register for all PFs. Each bit indicates if ATS for the corresponding PF is enabled. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40622 #define PGLUE_B_REG_SHADOW_VF_ENABLE_PF_31_0                                                         0x2aa0e0UL //Access:R    DataWidth:0x10  Shadow vf_enable register for all PFs. Each bit indicates if SR-IOV for the corresponding PF is enabled. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40623 #define PGLUE_B_REG_SHADOW_ATS_STU                                                                   0x2aa0e4UL //Access:R    DataWidth:0x5   Read only. Shadow ATS_STU register. (2^ATS_STU)*4KB is ATC translation address granularity. E4: split16.  Chips: BB_A0 BB_B0 K2
40624 #define PGLUE_B_REG_SHADOW_IDO_BITS                                                                  0x2aa0e8UL //Access:R    DataWidth:0x20  Shadow ido bits register for PFs 0 to 15. [15:0] : Each bit indicates if IDO_REQ_ENABLE bit for the corresponding PF is set. [31:16] : Each bit indicates if IDO_CPL_ENABLE bit for the corresponding PF is set. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40625 #define PGLUE_B_REG_DISABLE_ATS_EN_CLEARING                                                          0x2aa0ecUL //Access:RW   DataWidth:0x1   Debug only: PGLUE automatically clears ATC enable for a function if a TCPL arrived for that function with Unsupported Request error. Setting this register to 1 disables this automatic clearing.  Chips: BB_A0 BB_B0 K2
40626 #define PGLUE_B_REG_INCORRECT_RCV_DETAILS                                                            0x2aa0f0UL //Access:R    DataWidth:0x8   Each bit indicates an incorrect behavior in user RX interface. Bit 0 - Reserved. Bit 1 - Reserved. Bit 2 - Reserved. Bit 3 - Reserved. Bit 4 - Completion with Configuration Request Retry Status. Bit 5 - Expansion ROM access received with a write request. Bit 6 - Completion with pcie_rx_err of 0000; CMPL_STATUS of non-zero; and pcie_rx_last not asserted. Bit 7 - Completion with pcie_rx_err of 1010; and pcie_rx_last not asserted.  Chips: BB_A0 BB_B0 K2
40627 #define PGLUE_B_REG_WAS_ERROR_VF_31_0                                                                0x2aa0f4UL //Access:R    DataWidth:0x20  Was_error indication dirty bits for VFs 0 to 31.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_31_0_clr.  Chips: BB_A0 BB_B0 K2
40628 #define PGLUE_B_REG_WAS_ERROR_VF_63_32                                                               0x2aa0f8UL //Access:R    DataWidth:0x20  Was_error indication dirty bits for VFs 32 to 63.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_63_32_clr.  Chips: BB_A0 BB_B0 K2
40629 #define PGLUE_B_REG_WAS_ERROR_VF_95_64                                                               0x2aa0fcUL //Access:R    DataWidth:0x20  Was_error indication dirty bits for VFs 64 to 95.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_95_64_clr.  Chips: BB_A0 BB_B0 K2
40630 #define PGLUE_B_REG_WAS_ERROR_VF_127_96                                                              0x2aa100UL //Access:R    DataWidth:0x20  Was_error indication dirty bits for VFs 96 to 127.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_127_96_clr.  Chips: BB_A0 BB_B0 K2
40631 #define PGLUE_B_REG_WAS_ERROR_VF_159_128                                                             0x2aa104UL //Access:R    DataWidth:0x20  Was_error indication dirty bits for VFs 128 to 159.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_159_128_clr.  Chips: BB_A0 BB_B0 K2
40632 #define PGLUE_B_REG_WAS_ERROR_VF_191_160                                                             0x2aa108UL //Access:R    DataWidth:0x20  Was_error indication dirty bits for VFs 160 to 191.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_191_160_clr.  Chips: BB_A0 BB_B0 K2
40633 #define PGLUE_B_REG_WAS_ERROR_VF_223_192                                                             0x2aa10cUL //Access:R    DataWidth:0x20  Was_error indication dirty bits for VFs 192 to 223.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_223_192_clr.  Chips: BB_A0 BB_B0 K2
40634 #define PGLUE_B_REG_WAS_ERROR_VF_255_224                                                             0x2aa110UL //Access:R    DataWidth:0x20  Was_error indication dirty bits for VFs 224 to 255.  Each bit indicates that there was a completion with uncorrectable error for the corresponding VF. Set by PXP. Reset by MCP writing 1 to was_error_vf_255_224_clr.  Chips: BB_A0 BB_B0 K2
40635 #define PGLUE_B_REG_WAS_ERROR_PF_31_0                                                                0x2aa114UL //Access:R    DataWidth:0x10  Was_error indication dirty bits for PFs 0 to 7.  Each bit indicates that there was a completion with uncorrectable error for the corresponding PF. Set by PXP. Reset by MCP writing 1 to was_error_pf_31_0_clr.  Chips: BB_A0 BB_B0 K2
40636 #define PGLUE_B_REG_WAS_ERROR_VF_31_0_CLR                                                            0x2aa118UL //Access:W    DataWidth:0x20  Was_error indication dirty bits clear for VFs 0 to 31. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_31_0 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.  Chips: BB_A0 BB_B0 K2
40637 #define PGLUE_B_REG_WAS_ERROR_VF_63_32_CLR                                                           0x2aa11cUL //Access:W    DataWidth:0x20  Was_error indication dirty bits clear for VFs 32 to 63. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_63_32 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.  Chips: BB_A0 BB_B0 K2
40638 #define PGLUE_B_REG_WAS_ERROR_VF_95_64_CLR                                                           0x2aa120UL //Access:W    DataWidth:0x20  Was_error indication dirty bits clear for VFs 64 to 95. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_95_64 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.  Chips: BB_A0 BB_B0 K2
40639 #define PGLUE_B_REG_WAS_ERROR_VF_127_96_CLR                                                          0x2aa124UL //Access:W    DataWidth:0x20  Was_error indication dirty bits clear for VFs 96 to 127. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_127_96 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.  Chips: BB_A0 BB_B0 K2
40640 #define PGLUE_B_REG_WAS_ERROR_VF_159_128_CLR                                                         0x2aa128UL //Access:W    DataWidth:0x20  Was_error indication dirty bits clear for VFs 128 to 159. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_159_128 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.  Chips: BB_A0 BB_B0 K2
40641 #define PGLUE_B_REG_WAS_ERROR_VF_191_160_CLR                                                         0x2aa12cUL //Access:W    DataWidth:0x20  Was_error indication dirty bits clear for VFs 160 to 191. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_191_160 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.  Chips: BB_A0 BB_B0 K2
40642 #define PGLUE_B_REG_WAS_ERROR_VF_223_192_CLR                                                         0x2aa130UL //Access:W    DataWidth:0x20  Was_error indication dirty bits clear for VFs 192 to 223. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_223_192 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.  Chips: BB_A0 BB_B0 K2
40643 #define PGLUE_B_REG_WAS_ERROR_VF_255_224_CLR                                                         0x2aa134UL //Access:W    DataWidth:0x20  Was_error indication dirty bits clear for VFs 224 to 255. MCP writes 1 to a bit in this register in order to clear the corresponding bit in was_error_vf_255_224 register. The register is split per path but VFID is global. Each path can reset only the VFs belong to it.  Chips: BB_A0 BB_B0 K2
40644 #define PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR                                                            0x2aa138UL //Access:W    DataWidth:0x10  Was_error indication dirty bits clear for PFs 0 to 7.  MCP writes 1 to a bit in this register in order to clear the corresponding bit in flr_request_pf_31_0 register. The register is split per path but PFID is global. Each path can reset only the PFs belong to it.  Chips: BB_A0 BB_B0 K2
40645 #define PGLUE_B_REG_RX_ERR_DETAILS                                                                   0x2aa13cUL //Access:R    DataWidth:0x10  Details of first request received with error. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - completer abort. 3 - Illegal value for this field. [15] valid - indicates if there was a completion error since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40646 #define PGLUE_B_REG_RX_TCPL_ERR_DETAILS                                                              0x2aa140UL //Access:R    DataWidth:0x15  Details of first ATS Translation Completion request received with error. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [14:13] - Error Code - 0 - Indicates Completion Timeout of a User Tx non-posted request. 1 - unsupported request. 2 - completer abort. 3 - Illegal value for this field. [19:15] - ATC OTB EntryID. [20] valid - indicates if there was a completion error since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40647 #define PGLUE_B_REG_TX_ERR_WR_ADD_31_0                                                               0x2aa144UL //Access:R    DataWidth:0x20  Address [31:0] of first write request not submitted due to error.  Chips: BB_A0 BB_B0 K2
40648 #define PGLUE_B_REG_TX_ERR_WR_ADD_63_32                                                              0x2aa148UL //Access:R    DataWidth:0x20  Address [63:32] of first write request not submitted due to error.  Chips: BB_A0 BB_B0 K2
40649 #define PGLUE_B_REG_TX_ERR_WR_DETAILS                                                                0x2aa14cUL //Access:R    DataWidth:0x20  Details of first write request not submitted due to error. [4:0] VQID. [17:5] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.  Chips: BB_A0 BB_B0 K2
40650 #define PGLUE_B_REG_TX_ERR_WR_DETAILS2                                                               0x2aa150UL //Access:R    DataWidth:0x1e  Details of first write request not submitted due to error. [15:0] Request ID. [20:16] client ID. [24:21] - Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set; [25] - Indicates AtomicOp Requester Enable was cleared for Atomic Operation; [26] - last SR. [28:27] - Atomic - 0 - Regular request (not Atomic). 1 - CAS. 2 - FetchAdd. 3 - Swap. [29] - valid - indicates if there was a request not submitted due to error since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40651 #define PGLUE_B_REG_TX_ERR_RD_ADD_31_0                                                               0x2aa154UL //Access:R    DataWidth:0x20  Address [31:0] of first read request not submitted due to error.  Chips: BB_A0 BB_B0 K2
40652 #define PGLUE_B_REG_TX_ERR_RD_ADD_63_32                                                              0x2aa158UL //Access:R    DataWidth:0x20  Address [63:32] of first read request not submitted due to error.  Chips: BB_A0 BB_B0 K2
40653 #define PGLUE_B_REG_TX_ERR_RD_DETAILS                                                                0x2aa15cUL //Access:R    DataWidth:0x20  Details of first read request not submitted due to error. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [18:6] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.  Chips: BB_A0 BB_B0 K2
40654 #define PGLUE_B_REG_TX_ERR_RD_DETAILS2                                                               0x2aa160UL //Access:R    DataWidth:0x1c  Details of first read request not submitted due to error. [15:0] Request ID. [20:16] client ID. [24:21] - Error type - [21] - Indicates was_error was set; [22] - Indicates BME was cleared; [23] - Indicates FID_enable was cleared; [24] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set. [25] - last SR. [26] valid - indicates if there was a request not submitted due to error since the last time this register was cleared. [27] dstate_0 and write discard  Chips: BB_A0 BB_B0 K2
40655 #define PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL                                                           0x2aa164UL //Access:R    DataWidth:0x18  Details of first Invalidation Completion or MCTP message submitted during a TX error condition. [3:0] - PFID. [11:4] - VFID. [12] - VF_VALID. [17:13] - ITAG Index.  [21:18] - Error type - [18] - Indicates was_error was set; [19] - Indicates BME was cleared; [20] - Indicates FID_enable was cleared; [21] - Indicates VF with parent PF FLR_request or IOV_disable_request dirty bit is set. [22] - 0 indicates ICPL; 1 indicates MCTP. [23] valid - indicates if there was an Invalidation Completion message submitted during a TX error condition since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40656 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE                                                             0x2aa168UL //Access:RW   DataWidth:0x1   Internal FID_enable configuration per-VF for master and target transactions. E4: split240.  Chips: BB_A0 BB_B0 K2
40657 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER                                                      0x2aa16cUL //Access:RW   DataWidth:0x1   Internal FID_enable configuration per-PF for master transactions. E4: split16.  Chips: BB_A0 BB_B0 K2
40658 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_WRITE                                                0x2aa170UL //Access:RW   DataWidth:0x1   Internal FID_enable configuration per-PF for target write transactions. E4: split16.  Chips: BB_A0 BB_B0 K2
40659 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ                                                 0x2aa174UL //Access:RW   DataWidth:0x1   Internal FID_enable configuration per-PF for target read transactions. E4: split16.  Chips: BB_A0 BB_B0 K2
40660 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE_31_0_VALUE                                                  0x2aa178UL //Access:R    DataWidth:0x20  A global view of internal_vfid_enable register for VFs 0 to 31.  Chips: BB_A0 BB_B0 K2
40661 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE_63_32_VALUE                                                 0x2aa17cUL //Access:R    DataWidth:0x20  A global view of internal_vfid_enable register for VFs 32 to 63.  Chips: BB_A0 BB_B0 K2
40662 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE_95_64_VALUE                                                 0x2aa180UL //Access:R    DataWidth:0x20  A global view of internal_vfid_enable register for VFs 64 to 95.  Chips: BB_A0 BB_B0 K2
40663 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE_127_96_VALUE                                                0x2aa184UL //Access:R    DataWidth:0x20  A global view of internal_vfid_enable register for VFs 96 to 127.  Chips: BB_A0 BB_B0 K2
40664 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE_159_128_VALUE                                               0x2aa188UL //Access:R    DataWidth:0x20  A global view of internal_vfid_enable register for VFs 128 to 159.  Chips: BB_A0 BB_B0 K2
40665 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE_191_160_VALUE                                               0x2aa18cUL //Access:R    DataWidth:0x20  A global view of internal_vfid_enable register for VFs 224 to 191.  Chips: BB_A0 BB_B0 K2
40666 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE_223_192_VALUE                                               0x2aa190UL //Access:R    DataWidth:0x20  A global view of internal_vfid_enable register for VFs 192 to 223.  Chips: BB_A0 BB_B0 K2
40667 #define PGLUE_B_REG_INTERNAL_VFID_ENABLE_255_224_VALUE                                               0x2aa194UL //Access:R    DataWidth:0x20  A global view of internal_vfid_enable register for VFs 224 to 255.  Chips: BB_A0 BB_B0 K2
40668 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_VALUE                                                       0x2aa198UL //Access:R    DataWidth:0x20  A global view of internal_pfid_enable registers for target flow. Bits [15:0] - internal_pfid_enable_target_write; Bits [31:16] - internal_pfid_enable_target_read.  Chips: BB_A0 BB_B0 K2
40669 #define PGLUE_B_REG_INTERNAL_PFID_ENABLE_VALUE_MASTER                                                0x2aa19cUL //Access:R    DataWidth:0x10  A global view of internal_pfid_enable registers for master flow. Bits [15:0] - internal_pfid_enable_master.  Chips: BB_A0 BB_B0 K2
40670 #define PGLUE_B_REG_TSDM_START_OFFSET_A                                                              0x2aa1a0UL //Access:RW   DataWidth:0x13  Start offset of TSDM zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40671 #define PGLUE_B_REG_TSDM_OFFSET_MASK_A                                                               0x2aa1a4UL //Access:RW   DataWidth:0x5   Offset mask of TSDM zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40672 #define PGLUE_B_REG_TSDM_START_OFFSET_B                                                              0x2aa1a8UL //Access:RW   DataWidth:0x13  Start offset of TSDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40673 #define PGLUE_B_REG_TSDM_OFFSET_MASK_B                                                               0x2aa1acUL //Access:RW   DataWidth:0x9   Offset mask of TSDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40674 #define PGLUE_B_REG_TSDM_VF_SHIFT_B                                                                  0x2aa1b0UL //Access:RW   DataWidth:0x5   VF Shift of TSDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40675 #define PGLUE_B_REG_MSDM_START_OFFSET_A                                                              0x2aa1b4UL //Access:RW   DataWidth:0x13  Start offset of msdm zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40676 #define PGLUE_B_REG_MSDM_OFFSET_MASK_A                                                               0x2aa1b8UL //Access:RW   DataWidth:0x5   Offset mask of msdm zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40677 #define PGLUE_B_REG_MSDM_START_OFFSET_B                                                              0x2aa1bcUL //Access:RW   DataWidth:0x13  Start offset of msdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40678 #define PGLUE_B_REG_MSDM_OFFSET_MASK_B                                                               0x2aa1c0UL //Access:RW   DataWidth:0x9   Offset mask of msdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40679 #define PGLUE_B_REG_MSDM_VF_SHIFT_B                                                                  0x2aa1c4UL //Access:RW   DataWidth:0x5   VF Shift of msdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40680 #define PGLUE_B_REG_USDM_START_OFFSET_A                                                              0x2aa1c8UL //Access:RW   DataWidth:0x13  Start offset of USDM zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40681 #define PGLUE_B_REG_USDM_OFFSET_MASK_A                                                               0x2aa1ccUL //Access:RW   DataWidth:0x5   Offset mask of USDM zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40682 #define PGLUE_B_REG_USDM_START_OFFSET_B                                                              0x2aa1d0UL //Access:RW   DataWidth:0x13  Start offset of USDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40683 #define PGLUE_B_REG_USDM_OFFSET_MASK_B                                                               0x2aa1d4UL //Access:RW   DataWidth:0x9   Offset mask of USDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40684 #define PGLUE_B_REG_USDM_VF_SHIFT_B                                                                  0x2aa1d8UL //Access:RW   DataWidth:0x5   VF Shift of USDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40685 #define PGLUE_B_REG_XSDM_START_OFFSET_A                                                              0x2aa1dcUL //Access:RW   DataWidth:0x13  Start offset of XSDM zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40686 #define PGLUE_B_REG_XSDM_OFFSET_MASK_A                                                               0x2aa1e0UL //Access:RW   DataWidth:0x5   Offset mask of XSDM zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40687 #define PGLUE_B_REG_XSDM_START_OFFSET_B                                                              0x2aa1e4UL //Access:RW   DataWidth:0x13  Start offset of XSDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40688 #define PGLUE_B_REG_XSDM_OFFSET_MASK_B                                                               0x2aa1e8UL //Access:RW   DataWidth:0x9   Offset mask of XSDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40689 #define PGLUE_B_REG_XSDM_VF_SHIFT_B                                                                  0x2aa1ecUL //Access:RW   DataWidth:0x5   VF Shift of XSDM zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40690 #define PGLUE_B_REG_YSDM_START_OFFSET_A                                                              0x2aa1f0UL //Access:RW   DataWidth:0x13  Start offset of ysdm zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40691 #define PGLUE_B_REG_YSDM_OFFSET_MASK_A                                                               0x2aa1f4UL //Access:RW   DataWidth:0x5   Offset mask of ysdm zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40692 #define PGLUE_B_REG_YSDM_START_OFFSET_B                                                              0x2aa1f8UL //Access:RW   DataWidth:0x13  Start offset of ysdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40693 #define PGLUE_B_REG_YSDM_OFFSET_MASK_B                                                               0x2aa1fcUL //Access:RW   DataWidth:0x9   Offset mask of ysdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40694 #define PGLUE_B_REG_YSDM_VF_SHIFT_B                                                                  0x2aa200UL //Access:RW   DataWidth:0x5   VF Shift of ysdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40695 #define PGLUE_B_REG_PSDM_START_OFFSET_A                                                              0x2aa204UL //Access:RW   DataWidth:0x13  Start offset of psdm zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40696 #define PGLUE_B_REG_PSDM_OFFSET_MASK_A                                                               0x2aa208UL //Access:RW   DataWidth:0x5   Offset mask of psdm zone A (queue zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40697 #define PGLUE_B_REG_PSDM_START_OFFSET_B                                                              0x2aa20cUL //Access:RW   DataWidth:0x13  Start offset of psdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40698 #define PGLUE_B_REG_PSDM_OFFSET_MASK_B                                                               0x2aa210UL //Access:RW   DataWidth:0x9   Offset mask of psdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40699 #define PGLUE_B_REG_PSDM_VF_SHIFT_B                                                                  0x2aa214UL //Access:RW   DataWidth:0x5   VF Shift of psdm zone B (legacy zone) in the internal RAM.  Chips: BB_A0 BB_B0 K2
40700 #define PGLUE_B_REG_TSDM_INB_INT_A_0                                                                 0x2aa218UL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40701 #define PGLUE_B_REG_TSDM_INB_INT_A_1                                                                 0x2aa21cUL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40702 #define PGLUE_B_REG_TSDM_INB_INT_B_VF_0                                                              0x2aa220UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40703 #define PGLUE_B_REG_TSDM_INB_INT_B_VF_1                                                              0x2aa224UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40704 #define PGLUE_B_REG_MSDM_INB_INT_A_0                                                                 0x2aa228UL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40705 #define PGLUE_B_REG_MSDM_INB_INT_A_1                                                                 0x2aa22cUL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40706 #define PGLUE_B_REG_MSDM_INB_INT_B_VF_0                                                              0x2aa230UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40707 #define PGLUE_B_REG_MSDM_INB_INT_B_VF_1                                                              0x2aa234UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40708 #define PGLUE_B_REG_USDM_INB_INT_A_0                                                                 0x2aa238UL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40709 #define PGLUE_B_REG_USDM_INB_INT_A_1                                                                 0x2aa23cUL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40710 #define PGLUE_B_REG_USDM_INB_INT_B_VF_0                                                              0x2aa240UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40711 #define PGLUE_B_REG_USDM_INB_INT_B_VF_1                                                              0x2aa244UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40712 #define PGLUE_B_REG_XSDM_INB_INT_A_0                                                                 0x2aa248UL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40713 #define PGLUE_B_REG_XSDM_INB_INT_A_1                                                                 0x2aa24cUL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40714 #define PGLUE_B_REG_XSDM_INB_INT_B_VF_0                                                              0x2aa250UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40715 #define PGLUE_B_REG_XSDM_INB_INT_B_VF_1                                                              0x2aa254UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40716 #define PGLUE_B_REG_YSDM_INB_INT_A_0                                                                 0x2aa258UL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40717 #define PGLUE_B_REG_YSDM_INB_INT_A_1                                                                 0x2aa25cUL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40718 #define PGLUE_B_REG_YSDM_INB_INT_B_VF_0                                                              0x2aa260UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40719 #define PGLUE_B_REG_YSDM_INB_INT_B_VF_1                                                              0x2aa264UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40720 #define PGLUE_B_REG_PSDM_INB_INT_A_0                                                                 0x2aa268UL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40721 #define PGLUE_B_REG_PSDM_INB_INT_A_1                                                                 0x2aa26cUL //Access:RW   DataWidth:0xb   Type A PF/VF inbound interrupt table for SDM: bit[10]-enable for VF. 0 indicates the specific interrupt is enabled for PF only. 1 indicates it is enabled for PF and VF. bits[9:5]-end address in byte resolution;bits[4:0]-start address in byte resolution (relative to start_offset_a).  Chips: BB_A0 BB_B0 K2
40722 #define PGLUE_B_REG_PSDM_INB_INT_B_VF_0                                                              0x2aa270UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40723 #define PGLUE_B_REG_PSDM_INB_INT_B_VF_1                                                              0x2aa274UL //Access:RW   DataWidth:0xc   Type B VF inbound interrupt table for SDM: bits[11:6]-end address in 8B resolution;bits[5:0]-start address in 8B resolution (bits 8:3 of the address).  Chips: BB_A0 BB_B0 K2
40724 #define PGLUE_B_REG_TSDM_ZONE_A_SIZE_PF                                                              0x2aa318UL //Access:RW   DataWidth:0x1   0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.  Chips: BB_A0 BB_B0 K2
40725 #define PGLUE_B_REG_MSDM_ZONE_A_SIZE_PF                                                              0x2aa31cUL //Access:RW   DataWidth:0x1   0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.  Chips: BB_A0 BB_B0 K2
40726 #define PGLUE_B_REG_USDM_ZONE_A_SIZE_PF                                                              0x2aa320UL //Access:RW   DataWidth:0x1   0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.  Chips: BB_A0 BB_B0 K2
40727 #define PGLUE_B_REG_XSDM_ZONE_A_SIZE_PF                                                              0x2aa324UL //Access:RW   DataWidth:0x1   0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.  Chips: BB_A0 BB_B0 K2
40728 #define PGLUE_B_REG_YSDM_ZONE_A_SIZE_PF                                                              0x2aa328UL //Access:RW   DataWidth:0x1   0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.  Chips: BB_A0 BB_B0 K2
40729 #define PGLUE_B_REG_PSDM_ZONE_A_SIZE_PF                                                              0x2aa32cUL //Access:RW   DataWidth:0x1   0 - Zone A PF has NumQueues queues. 1 - Zone A PF has NumSBs queues. NumQueues is 256 for BB and 320 for K2. NumSBs is 288 for BB and 368 for K2.  Chips: BB_A0 BB_B0 K2
40730 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_0                                                            0x2aa330UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40731 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_0                                                            0x2aa334UL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40732 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_1                                                            0x2aa338UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40733 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_1                                                            0x2aa33cUL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40734 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_2                                                            0x2aa340UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40735 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_2                                                            0x2aa344UL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40736 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_3                                                            0x2aa348UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40737 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_3                                                            0x2aa34cUL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40738 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_4                                                            0x2aa350UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40739 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_4                                                            0x2aa354UL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40740 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_5                                                            0x2aa358UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40741 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_5                                                            0x2aa35cUL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40742 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_6                                                            0x2aa360UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40743 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_6                                                            0x2aa364UL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40744 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_7                                                            0x2aa368UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40745 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_7                                                            0x2aa36cUL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40746 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_8                                                            0x2aa370UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40747 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_8                                                            0x2aa374UL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40748 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_9                                                            0x2aa378UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40749 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_9                                                            0x2aa37cUL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40750 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_10                                                           0x2aa380UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40751 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_10                                                           0x2aa384UL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40752 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_11                                                           0x2aa388UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40753 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_11                                                           0x2aa38cUL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40754 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_12                                                           0x2aa390UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40755 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_12                                                           0x2aa394UL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40756 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_13                                                           0x2aa398UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40757 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_13                                                           0x2aa39cUL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40758 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_14                                                           0x2aa3a0UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40759 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_14                                                           0x2aa3a4UL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40760 #define PGLUE_B_REG_VF_GRC_ACCESS_PART1_15                                                           0x2aa3a8UL //Access:RW   DataWidth:0x19  Part1 of VF GRC access register. Bits [24:22] - GRC range. The GRC range in DWORDS that is allowed to be accessed (starting from GRC base).  0 means that only the GRC base can be accessed. Bits [21:0] - GRC base. The GRC base address that this packet is accessing (in DWORS).  Chips: BB_A0 BB_B0 K2
40761 #define PGLUE_B_REG_VF_GRC_ACCESS_PART2_15                                                           0x2aa3acUL //Access:RW   DataWidth:0x17  Part2 of VF GRC access register. Bits [22:19] - Function offset. This fields allows different functions to access GRC locations in distance 2^Func_offset from GRC_base. Bits [18] - Absolute func index. 0 - Path-relative func index should be used (a number between 0 and 119). 1 - Absolute func index should be used (a number between 0 and 239). Bits [17] - Add func index. 1 - Function index should be added to the GRC address. In E4; path-relative func index should always be used (a number between 0 and 119). Bits [16] - GRC func. 1 - Access will be with the parent PFID. 0 - Access will be with the VFID. Bits [15:4] - Allowed func ID. [15:12] - PFID. [11:4] - VFID. Bits [3] - R/W. 0 - Read only access; 1 - read and write access. Bits [2:0] - Permission. 0 - no one. 1 - all VFs. 2 - All VFs within path. 3 - All VFs within PF. 4 - Specific VF.  Chips: BB_A0 BB_B0 K2
40762 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS                                                      0x2aa3b0UL //Access:R    DataWidth:0x1b  Details of first target VF request with length violation (too many DWs) accessing BAR0. [12:0] Address in DWs (bits [14:2] of byte address). [14:13] BAR. [22:15] VFID. [26:23] - PFID.  Chips: BB_A0 BB_B0 K2
40763 #define PGLUE_B_REG_VF_LENGTH_VIOLATION_DETAILS2                                                     0x2aa3b4UL //Access:R    DataWidth:0x7   Details of first target VF request with length violation (too many DWs) accessing BAR0. [5:0] - Length in DWs.  [6] valid - indicates if there was a request with length violation since the last time this register was cleared. Length violations: length of more than 2DWs; length of 2DWs and address not QW aligned; window is GRC and length is more than 1 DW.  Chips: BB_A0 BB_B0 K2
40764 #define PGLUE_B_REG_VF_GRC_SPACE_VIOLATION_DETAILS                                                   0x2aa3b8UL //Access:R    DataWidth:0x1d  Details of first target VF request accessing VF GRC space that failed permission check. [14:0] Address. [15] w_nr: 0 - Read; 1 - Write. [23:16] VFID. [27:24] - PFID. [28] valid - indicates if there was a request accessing VF GRC space that failed permission check since the last time this register was cleared. Permission checks are: function permission; R/W permission; address range permission.  Chips: BB_A0 BB_B0 K2
40765 #define PGLUE_B_REG_LATCHED_ERRORS_CLR                                                               0x2aa3bcUL //Access:W    DataWidth:0x11  Writing 1 to each bit in this register clears a corresponding error details register and enables logging new error details. Bit 0 - clears INCORRECT_RCV_DETAILS; Bit 1 - clears RX_ERR_DETAILS; Bit 2 - clears TX_ERR_WR_ADD_31_0 TX_ERR_WR_ADD_63_32 TX_ERR_WR_DETAILS TX_ERR_WR_DETAILS2 TX_ERR_RD_ADD_31_0 TX_ERR_RD_ADD_63_32 TX_ERR_RD_DETAILS TX_ERR_RD_DETAILS2 TX_ERR_WR_DETAILS_ICPL MASTER_ZLR_ERR_ADD_31_0 MASTER_ZLR_ERR_ADD_63_32 MASTER_ZLR_ERR_DETAILS VF_ILT_ERR_ADD_31_0 VF_ILT_ERR_ADD_63_32 VF_ILT_ERR_DETAILS VF_ILT_ERR_DETAILS2; Bit 3 - clears VF_LENGTH_VIOLATION_DETAILS. Bit 4 - clears VF_GRC_SPACE_VIOLATION_DETAILS. Bit 5 - clears RX_TCPL_ERR_DETAILS. Bit 6 - clears TCPL_IN_TWO_RCBS_DETAILS. Bit 7 - clears ADMIN_WINDOW_VIOLATION_DETAILS. Bit 8 - clears OUT_OF_RANGE_FUNCTION_IN_PRETEND_DETAILS OUT_OF_RANGE_FUNCTION_IN_PRETEND_ADDRESS. Bit 9 - clears ILLEGAL_ADDRESS (DETAILS and ADDRESS registers). Bit 10 - clears TPH (DETAILS and ADDRESS registers) although this logging does not relate to error. Bit 12 - DBI error log clr. Bit 13 - MCT Error log clr Bit 14 - TLP Abort error log clr Bit 15 - ECRC Abort error log clr Bit 16 - Poison error log clr  Chips: BB_A0 BB_B0 K2
40766 #define PGLUE_B_REG_IDO_ENABLE_MASTER_RW                                                             0x2aa3c0UL //Access:RW   DataWidth:0x20  Each bit when set indicates that IDO bit towards PGLUE should be set for this VQ.  Chips: BB_A0 BB_B0 K2
40767 #define PGLUE_B_REG_IDO_ENABLE_MASTER_RW2                                                            0x2aa3c4UL //Access:RW   DataWidth:0x1   Bit 0 - when set indicates that IDO bit towards PGLUE should be set for Translation Requests.  Chips: BB_A0 BB_B0 K2
40768 #define PGLUE_B_REG_IDO_ENABLE_TARGET_CPL                                                            0x2aa3c8UL //Access:RW   DataWidth:0x1   Bit 0 - when set indicates that IDO bit towards PGLUE should be set for Target Completions.  Chips: BB_A0 BB_B0 K2
40769 #define PGLUE_B_REG_IGU_BYPASS_ON_ERR                                                                0x2aa3ccUL //Access:RW   DataWidth:0x1   1 - Do not discard IGU master transactions for PF when the corresponding was_error bit is set.  Chips: BB_A0 BB_B0 K2
40770 #define PGLUE_B_REG_ALLOW_MSIX_ACCESS_IN_BAR0                                                        0x2aa3d0UL //Access:RW   DataWidth:0x1   0 - Accesses to the first 8KB of IGU in BAR0 (MSIX table and PBA) are not allowed. When this value is configured; BAR2 size for PFs and VFs should be configured to 8KB to allow ONLY MSIX table and PBA access. 1 - All IGU space in BAR 0 is accessible; including the first 8KB. When this value is configured; BAR2 size for PFs can be configured to 64KB and for VFs to 16KB to allow all IGU space to be accessed in BAR2 as well.  Chips: BB_A0 BB_B0 K2
40771 #define PGLUE_B_REG_TCPL_IN_TWO_RCBS_DETAILS                                                         0x2aa3d4UL //Access:R    DataWidth:0x13  Details of first ATS Translation Completion received in two rcbs (packets). Logging is triggered by a Translation Completion with length different than 2 DWs. Such a case is unsupported and the Translation completion is considered erroneous. [3:0] - PFID. [4] - VF_VALID. [12:5] - VFID. [17:13] - OTB EntryID. [18] valid - indicates if there was a Translation Completion received in two rcbs since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40772 #define PGLUE_B_REG_PCIE_ERR_STATUS                                                                  0x2aa3d8UL //Access:R    DataWidth:0x4   Details of PCIe core error status. Valid when pgl_pcie_attn in pxp2 is set. 0 - Unsupported Request or Completer Abort on User RX Interface. 1 - Reception of a poisoned TLP on RX Lanes. 2 - Completion timeout. 3 - Unexpected Completion on RX Lanes. 4 - Detected Unsupported Request on RX Lanes. 5 - ECRC error on RX Lanes. 6 - Reserved. 7 - Reserved. 8 - Illegal operation size on User TX Interface. 9 - Detected Unsupported Request on User TX Interface (Bridge Forwarding Error). 10 - Unsupported header type on User TX Interface. 11 - Reserved. 12 - NP TAG value on User TX Interface already in use. 13 - Completion RTAG value on User TX Interface unexpected. 14 - User TX Interface Overflow Error (Too many req wo/ack). 15 - reserved.  Chips: BB_A0 BB_B0 K2
40773 #define PGLUE_B_REG_CPU_MBIST_MEMCTRL_0_CNTRL_CMD                                                    0x2aa3dcUL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0 K2
40774 #define PGLUE_B_REG_CPU_MBIST_MEMCTRL_1_CNTRL_CMD                                                    0x2aa3e0UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0 K2
40775 #define PGLUE_B_REG_DISABLE_TCPL_TRANSLATION_SIZE_CHECK                                              0x2aa3ecUL //Access:RW   DataWidth:0x1   Debug only: 0 - Enable the fix for CQ45220. If a Function receives a Translation Completion with a Translation Size field smaller than the Function programmed STU value; clear the ATS_en shadow bit and send UR to the ATC. 1 - Disable the fix for CQ45220.  Chips: BB_A0 BB_B0 K2
40776 #define PGLUE_B_REG_CPU_MBIST_MEMCTRL_2_CNTRL_CMD                                                    0x2aa3f0UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0 K2
40777 #define PGLUE_B_REG_CPU_MBIST_MEMCTRL_3_CNTRL_CMD                                                    0x2aa3f4UL //Access:RW   DataWidth:0x5   Bit 0 - bist_override; Bit 1 - mbist_en; Bit 2 - mbist_async_reset; Bits 4:3 - bist_setup[1:0];.  Chips: BB_A0 BB_B0 K2
40778 #define PGLUE_B_REG_PGL_TGTWR_MLENGTH                                                                0x2aa400UL //Access:RW   DataWidth:0xa   Maximal length allowed for target writes (dwords). Target writes with bigger length are discarded. Configuration value must be at least 16 DWORDs, so the discarded packetstarget writes have at least two cycles.  Chips: BB_A0 BB_B0 K2
40779 #define PGLUE_B_REG_PGL_ADDR_88_F0                                                                   0x2aa404UL //Access:RW   DataWidth:0x20  GRC address for configuration access to PCIE config address 0x88. any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.  Chips: BB_A0 BB_B0
40780 #define PGLUE_B_REG_PGL_ADDR_8C_F0                                                                   0x2aa408UL //Access:RW   DataWidth:0x20  GRC address for configuration access to PCIE config address 0x8c.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.  Chips: BB_A0 BB_B0
40781 #define PGLUE_B_REG_PGL_ADDR_90_F0                                                                   0x2aa40cUL //Access:RW   DataWidth:0x20  GRC address for configuration access to PCIE config address 0x90.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.  Chips: BB_A0 BB_B0
40782 #define PGLUE_B_REG_PGL_ADDR_94_F0                                                                   0x2aa410UL //Access:RW   DataWidth:0x20  GRC address for configuration access to PCIE config address 0x94.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.  Chips: BB_A0 BB_B0
40783 #define PGLUE_B_REG_PGL_EXP_ROM_ADDR                                                                 0x2aa414UL //Access:R    DataWidth:0x19  The address to be read from expansion rom (address is in bytes according to read packet from host).  Chips: BB_A0 BB_B0 K2
40784 #define PGLUE_B_REG_PGL_EXP_ROM_FUNC                                                                 0x2aa418UL //Access:R    DataWidth:0x4   The function number of the expansion rom that is being accessed.  Chips: BB_A0 BB_B0 K2
40785 #define PGLUE_B_REG_PGL_EXP_ROM_SIZE                                                                 0x2aa41cUL //Access:R    DataWidth:0x2   The size in dwords to be read from expansion rom (according to read packet from host).  Chips: BB_A0 BB_B0 K2
40786 #define PGLUE_B_REG_PGL_EXP_ROM0                                                                     0x2aa420UL //Access:RW   DataWidth:0x20  First dword data of expansion rom request. When this register is written a completion is sent to the pcie core. When the expansion rom request contains more than one dword this register should be written last. Writing to this register when there is not pending expansion rom request should not be done!.  Chips: BB_A0 BB_B0 K2
40787 #define PGLUE_B_REG_PGL_EXP_ROM1                                                                     0x2aa424UL //Access:RW   DataWidth:0x20  Second dword data of expansion rom request.  Chips: BB_A0 BB_B0 K2
40788 #define PGLUE_B_REG_PGL_EXP_ROM2                                                                     0x2aa428UL //Access:RW   DataWidth:0x20  Third dword data of expansion rom request.  Chips: BB_A0 BB_B0 K2
40789 #define PGLUE_B_REG_PGL_TAGS_LIMIT                                                                   0x2aa42cUL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40790     #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS                                                  (0xff<<0) // This field sets the maximal number of outstanding tags.
40791     #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS_SHIFT                                            0
40792     #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS_DISABLE                                          (0x1<<8) // This field disables the outstadnging tags limit mechanism.
40793     #define PGLUE_B_REG_PGL_TAGS_LIMIT_PGL_MAX_TAGS_DISABLE_SHIFT                                    8
40794 #define PGLUE_B_REG_SDM_INB_INT_B_PF_0                                                               0x2aa440UL //Access:RW   DataWidth:0x1a  8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).  Chips: BB_A0 BB_B0 K2
40795 #define PGLUE_B_REG_SDM_INB_INT_B_PF_0_SIZE                                                          6
40796 #define PGLUE_B_REG_SDM_INB_INT_B_PF_1                                                               0x2aa460UL //Access:RW   DataWidth:0x1a  8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).  Chips: BB_A0 BB_B0 K2
40797 #define PGLUE_B_REG_SDM_INB_INT_B_PF_1_SIZE                                                          6
40798 #define PGLUE_B_REG_SDM_INB_INT_B_PF_2                                                               0x2aa480UL //Access:RW   DataWidth:0x1a  8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).  Chips: BB_A0 BB_B0 K2
40799 #define PGLUE_B_REG_SDM_INB_INT_B_PF_2_SIZE                                                          6
40800 #define PGLUE_B_REG_SDM_INB_INT_B_PF_3                                                               0x2aa4a0UL //Access:RW   DataWidth:0x1a  8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).  Chips: BB_A0 BB_B0 K2
40801 #define PGLUE_B_REG_SDM_INB_INT_B_PF_3_SIZE                                                          6
40802 #define PGLUE_B_REG_SDM_INB_INT_B_PF_4                                                               0x2aa4c0UL //Access:RW   DataWidth:0x1a  8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).  Chips: BB_A0 BB_B0 K2
40803 #define PGLUE_B_REG_SDM_INB_INT_B_PF_4_SIZE                                                          6
40804 #define PGLUE_B_REG_SDM_INB_INT_B_PF_5                                                               0x2aa4e0UL //Access:RW   DataWidth:0x1a  8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).  Chips: BB_A0 BB_B0 K2
40805 #define PGLUE_B_REG_SDM_INB_INT_B_PF_5_SIZE                                                          6
40806 #define PGLUE_B_REG_SDM_INB_INT_B_PF_6                                                               0x2aa500UL //Access:RW   DataWidth:0x1a  8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).  Chips: BB_A0 BB_B0 K2
40807 #define PGLUE_B_REG_SDM_INB_INT_B_PF_6_SIZE                                                          6
40808 #define PGLUE_B_REG_SDM_INB_INT_B_PF_7                                                               0x2aa520UL //Access:RW   DataWidth:0x1a  8 memories; each corresponds to a different legacy (type B) PF inbound interrupt index. In every memory there are 6 lines: 0 TSDM; 1 MSDM; 2 USDM; 3 XSDM; 4 YSDM; 5 PSDM. The content of each entry: bits[25:13]-end address in 64B resolution;bits[12:0]-start address in 64B resolution (bits 15:6).  Chips: BB_A0 BB_B0 K2
40809 #define PGLUE_B_REG_SDM_INB_INT_B_PF_7_SIZE                                                          6
40810 #define PGLUE_B_REG_PF_TRUSTED                                                                       0x2aa540UL //Access:RW   DataWidth:0x1   Each bit in this read-only register reflects the value of the corresponding 'PF trusted' config bit on the external configuration space (on PCI address 0x7C bit0). It is used for physical device assignment flow. 0 - PF is untranted. 1 - PF is trusted.  Chips: BB_A0 BB_B0 K2
40811 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0                                                          0x2aa544UL //Access:R    DataWidth:0x20  Address [31:0] of first read request with length = 0.  Chips: BB_A0 BB_B0 K2
40812 #define PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32                                                         0x2aa548UL //Access:R    DataWidth:0x20  Address [63:32] of first read request with length = 0.  Chips: BB_A0 BB_B0 K2
40813 #define PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS                                                           0x2aa54cUL //Access:R    DataWidth:0x1a  Details of first read request with length = 0. [4:0] VQID. [5] TREQ. 1 - Indicates the request is a Translation Request. [9:6] - PFID. [10] - VF_VALID. [18:11] - VFID. [23:19] client ID. [24] - last SR. [25] valid - indicates if there was a request with length = 0 since the last time this register was cleared. This error should not normally happen, but may happen with physical device assignement flow. The register is cleared with latched_errors_clr bit 2.  Chips: BB_A0 BB_B0 K2
40814 #define PGLUE_B_REG_DISABLE_TPH_NONALIGNED                                                           0x2aa550UL //Access:RW   DataWidth:0x1   Relevant for read request with tph_valid = '1' and with either address not DW aligned or length not a multiple of DWs. 0 - PGLUE will submit the request with TPH info. PXP will take care of aligning it correctly when sending the response to the client (already done in E3). 1 - PGLUE should handle the request as it as if it arrived with TPH_Valid = '0'.  Chips: BB_A0 BB_B0 K2
40815 #define PGLUE_B_REG_ADMIN_WINDOW_VIOLATION_DETAILS                                                   0x2aa554UL //Access:R    DataWidth:0x1d  Details of first target Read/Write access to the admin window that have a length bigger than 1DW or first byte enable != 0xf . [9:0] Address in DWs (bits [11:2] of byte address). [13:10] BE first. [17:14] BE last. [21:18] - PFID. [27:22] - Length in DWs. [28] valid - indicates if there was a request with admin window violation since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40816 #define PGLUE_B_REG_OUT_OF_RANGE_FUNCTION_IN_PRETEND_DETAILS                                         0x2aa558UL //Access:R    DataWidth:0x16  Details of first target Read/Write access where pretend register contains an out of range function. [3:0] - original PFID. [7:4] Pretend PFID. [15:8] Pretend VFID. [16] Pretend vf_valid. [20:17] Pretend register: 0-11 - One of the PF windows pretend. 12 - global pretend register. [21] valid - indicates there was a GRC access where pretend containe dout of range function since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40817 #define PGLUE_B_REG_OUT_OF_RANGE_FUNCTION_IN_PRETEND_ADDRESS                                         0x2aa55cUL //Access:R    DataWidth:0x19  Address of first target Read/Write access where pretend register contains an out of range function.  Chips: BB_A0 BB_B0 K2
40818 #define PGLUE_B_REG_DISABLE_EXTERNAL_BAR0                                                            0x2aa560UL //Access:RW   DataWidth:0x1   0 - Work with external BAR0 mechanism as defined in E4 spec. 1 - Disable external BAR0 mechanism. Access will be directly to the internal BAR, except accesses to the Admin Window which will still be executed.  Chips: BB_A0 BB_B0 K2
40819 #define PGLUE_B_REG_TSDM_QUEUE_ZONE_SIZE                                                             0x2aa564UL //Access:RW   DataWidth:0x6   Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.  Chips: BB_A0 BB_B0 K2
40820 #define PGLUE_B_REG_MSDM_QUEUE_ZONE_SIZE                                                             0x2aa568UL //Access:RW   DataWidth:0x6   Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.  Chips: BB_A0 BB_B0 K2
40821 #define PGLUE_B_REG_USDM_QUEUE_ZONE_SIZE                                                             0x2aa56cUL //Access:RW   DataWidth:0x6   Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.  Chips: BB_A0 BB_B0 K2
40822 #define PGLUE_B_REG_XSDM_QUEUE_ZONE_SIZE                                                             0x2aa570UL //Access:RW   DataWidth:0x6   Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.  Chips: BB_A0 BB_B0 K2
40823 #define PGLUE_B_REG_YSDM_QUEUE_ZONE_SIZE                                                             0x2aa574UL //Access:RW   DataWidth:0x6   Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.  Chips: BB_A0 BB_B0 K2
40824 #define PGLUE_B_REG_PSDM_QUEUE_ZONE_SIZE                                                             0x2aa578UL //Access:RW   DataWidth:0x6   Queue size for SDM zone A. Possible values: 0B; 8B; 16B; 32B.  Chips: BB_A0 BB_B0 K2
40825 #define PGLUE_B_REG_FID_CHANNEL_ENABLE                                                               0x2aa57cUL //Access:RW   DataWidth:0x1   FID channel enable configuration per-VF.  Controls Target read/write access to specific locations in ZoneB of each SDM window in the VF BAR. E4: split240.  Chips: BB_A0 BB_B0 K2
40826 #define PGLUE_B_REG_SDM_CHANNEL_ENABLE                                                               0x2aa580UL //Access:RW   DataWidth:0x6   Defines if the PF to VF channel is enabled for that SDM. One bit per SDM. Bit 0 - TSDM. Bit 1 - MSDM. Bit 2 - USDM. Bit 3 - XSDM. Bit 4 - YSDM. Bit 5 - PSDM.  Chips: BB_A0 BB_B0 K2
40827 #define PGLUE_B_REG_PFVF_WINDOW_SIZE                                                                 0x2aa584UL //Access:RW   DataWidth:0x3   Window size for VF to PF channel. 0 - NA; 1 - 8B; 2 - 16B; 3 - 32B; 4 - 64B; 5 - 128B; 6 - 256B; 7 - 512B.  Chips: BB_A0 BB_B0 K2
40828 #define PGLUE_B_REG_PFVF_WINDOW_START_OFFSET                                                         0x2aa588UL //Access:RW   DataWidth:0x6   Defines the start offset of the VF to PF window within VF ZoneB in 8B granularity.  Chips: BB_A0 BB_B0 K2
40829 #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK                                                            0x2aa58cUL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40830     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_BME                                  (0x1<<0) // Decision bit for PF master requests when BME is cleared: 0 - block; 1 - discard.
40831     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_BME_SHIFT                            0
40832     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_FID_ENABLE                           (0x1<<1) // Decision bit for PF master requests when fid_enable is cleared: 0 - block; 1 - discard.
40833     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_FID_ENABLE_SHIFT                     1
40834     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_WAS_ERROR                            (0x1<<2) // Decision bit for PF master requests when was_error is set: 0 - block; 1 - discard.
40835     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_PF_WAS_ERROR_SHIFT                      2
40836     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_BME                                  (0x1<<3) // Decision bit for VF master requests when BME is cleared: 0 - block; 1 - discard.
40837     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_BME_SHIFT                            3
40838     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_FID_ENABLE                           (0x1<<4) // Decision bit for VF master requests when fid_enable is cleared: 0 - block; 1 - discard.
40839     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_FID_ENABLE_SHIFT                     4
40840     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_WAS_ERROR                            (0x1<<5) // Decision bit for VF master requests when was_error is set: 0 - block; 1 - discard.
40841     #define PGLUE_B_REG_MASTER_DISCARD_NBLOCK_DISCARD_NBLOCK_VF_WAS_ERROR_SHIFT                      5
40842 #define PGLUE_B_REG_MASTER_ATTENTION_SETTING                                                         0x2aa590UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40843     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_BME                            (0x3<<0) // Attention setting configuration for PF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
40844     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_BME_SHIFT                      0
40845     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_FID_ENABLE                     (0x3<<2) // Attention setting configuration for PF master requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
40846     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_FID_ENABLE_SHIFT               2
40847     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_WAS_ERROR                      (0x3<<4) // Attention setting configuration for PF master requests when was_error is set: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
40848     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_PF_WAS_ERROR_SHIFT                4
40849     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_BME                            (0x3<<6) // Attention setting configuration for VF master requests when BME is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
40850     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_BME_SHIFT                      6
40851     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_FID_ENABLE                     (0x3<<8) // Attention setting configuration for VF master requests when fid_enabled is cleared: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
40852     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_FID_ENABLE_SHIFT               8
40853     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_WAS_ERROR                      (0x3<<10) // Attention setting configuration for VF master requests when was_error is set: 0 - Always set (and log error details); 1 - never set attention; 2 - set attention (and log error details) only if FLR is not in progress and mask_block_discard_attn is cleared.
40854     #define PGLUE_B_REG_MASTER_ATTENTION_SETTING_ATTENTION_SETTING_VF_WAS_ERROR_SHIFT                10
40855 #define PGLUE_B_REG_MASK_BLOCK_DISCARD_ATTN_PF                                                       0x2aa594UL //Access:RW   DataWidth:0x1   When this bit is set and attntion setting configuration is 2 any block or discard event for that function will not generate an attention. This bit will allow SW to extend the period in which attention is masked beyond the FLR_in_progress period. E4: split16.  Chips: BB_A0 BB_B0 K2
40856 #define PGLUE_B_REG_MASK_BLOCK_DISCARD_ATTN_VF                                                       0x2aa598UL //Access:RW   DataWidth:0x1   When this bit is set and attntion setting configuration is 2 any block or discard event for that function will not generate an attention. This bit will allow SW to extend the period in which attention is masked beyond the FLR_in_progress period. E4: split240.  Chips: BB_A0 BB_B0 K2
40857 #define PGLUE_B_REG_WRITE_FIFO_QUEUE                                                                 0x2aa800UL //Access:WB_R DataWidth:0xfb  Debug only and read only: Each entry provides the content of the corresponding entry in PGLUE master write FIFO. The structure of every entry appears in TBD.  Chips: BB_A0 BB_B0 K2
40858 #define PGLUE_B_REG_WRITE_FIFO_QUEUE_SIZE                                                            176
40859 #define PGLUE_B_REG_READ_FIFO_QUEUE                                                                  0x2aac00UL //Access:WB_R DataWidth:0xae  Debug only and read only: Each entry provides the content of the corresponding entry in PGLUE master read FIFO. The structure of every entry appears in TBD.  Chips: BB_A0 BB_B0 K2
40860 #define PGLUE_B_REG_READ_FIFO_QUEUE_SIZE                                                             112
40861 #define PGLUE_B_REG_WRITE_FIFO_OCCUPANCY_LEVEL                                                       0x2aae00UL //Access:R    DataWidth:0x5   Debug only: Occupancy level in PGLUE master write FIFO. This is the maximum between driver counter and filler counter.  Chips: BB_A0 BB_B0 K2
40862 #define PGLUE_B_REG_USE_CLIENTID_IN_TAG                                                              0x2aae04UL //Access:RW   DataWidth:0x1   A value of '1' instructs PGLUE to use the client ID value in the 'tag' field of non-TPH master write packets. This can be used for debug purposes.  Chips: BB_A0 BB_B0 K2
40863 #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_EN                                                        0x2aae08UL //Access:RW   DataWidth:0x1   This field is an enable bit for 'detection of out-of-range requests' debug feature. It should be initialized to '0' in systems with IOMMU enabled.  Chips: BB_A0 BB_B0 K2
40864 #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS                                                           0x2aae0cUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40865     #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_MINIMAL_ADDRESS_LOG                                   (0x1f<<0) // This field is (the log of ) the minimal legal address value. It is used in the 'detection of out-of-range requests' debug feature.
40866     #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_MINIMAL_ADDRESS_LOG_SHIFT                             0
40867     #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_MAXIMAL_ADDRESS_LOG                                   (0x1f<<5) // This field plus 48 is (the log of ) the maximal legal address value. It is used in the 'detection of out-of-range requests' debug feature.
40868     #define PGLUE_B_REG_DETECT_ILLEGAL_ADDRESS_MAXIMAL_ADDRESS_LOG_SHIFT                             5
40869 #define PGLUE_B_REG_ILLEGAL_ADDRESS_ADD_31_0                                                         0x2aae10UL //Access:R    DataWidth:0x20  Address [31:0] of first request with illegal address.  Chips: BB_A0 BB_B0 K2
40870 #define PGLUE_B_REG_ILLEGAL_ADDRESS_ADD_63_32                                                        0x2aae14UL //Access:R    DataWidth:0x20  Address [63:32] of first request with illegal address.  Chips: BB_A0 BB_B0 K2
40871 #define PGLUE_B_REG_ILLEGAL_ADDRESS_DETAILS                                                          0x2aae18UL //Access:R    DataWidth:0x20  Details of first request with illegal address. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.  Chips: BB_A0 BB_B0 K2
40872 #define PGLUE_B_REG_ILLEGAL_ADDRESS_DETAILS2                                                         0x2aae1cUL //Access:R    DataWidth:0x19  Details of first request with illegal address. [15:0] Request ID. [20:16] client ID. [21] Illegal address cause: 0 - address was smaller than minimal_address_log;  1 - address was bigger than maximal_address_log. [22] - write_n_read: 0 - read; 1 - write. [23] - last SR.  [24] valid - indicates if there was a request submitted with illegal address since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40873 #define PGLUE_B_REG_TPH_ADD_31_0                                                                     0x2aae20UL //Access:R    DataWidth:0x20  Address [31:0] of first request sent with TPH information.  Chips: BB_A0 BB_B0 K2
40874 #define PGLUE_B_REG_TPH_ADD_63_32                                                                    0x2aae24UL //Access:R    DataWidth:0x20  Address [63:32] of first request sent with TPH information.  Chips: BB_A0 BB_B0 K2
40875 #define PGLUE_B_REG_TPH_DETAILS                                                                      0x2aae28UL //Access:R    DataWidth:0x20  Details of first request sent with TPH information. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.  Chips: BB_A0 BB_B0 K2
40876 #define PGLUE_B_REG_TPH_DETAILS2                                                                     0x2aae2cUL //Access:R    DataWidth:0x12  Details of first request sent with TPH information. [4:0] client ID. [6:5] PH. [14:7] Steering Tag. [15] - write_n_read: 0 - read; 1 - write.  [16] - last SR. [17] valid - indicates if there was a request submitted with TPH informationsince the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40877 #define PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE                                                          0x2aae30UL //Access:RW   DataWidth:0x1   0 - never pad write sub-requests with zeros. 1 - Pad write sub-requests with zeros and align them to cache line according to the sub-request configuration.  Chips: BB_A0 BB_B0 K2
40878 #define PGLUE_B_REG_CACHE_LINE_SIZE                                                                  0x2aae34UL //Access:RW   DataWidth:0x3   Cache line size for padding. 0 - 32B. 1 - 64B. 2 - 128B. 3 - 256B.  Chips: BB_A0 BB_B0 K2
40879 #define PGLUE_B_REG_TAGS_31_0                                                                        0x2aae38UL //Access:R    DataWidth:0x20  Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.  Chips: BB_A0 BB_B0 K2
40880 #define PGLUE_B_REG_TAGS_63_32                                                                       0x2aae3cUL //Access:R    DataWidth:0x20  Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.  Chips: BB_A0 BB_B0 K2
40881 #define PGLUE_B_REG_TAGS_95_64                                                                       0x2aae40UL //Access:R    DataWidth:0x20  Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.  Chips: BB_A0 BB_B0 K2
40882 #define PGLUE_B_REG_TAGS_127_96                                                                      0x2aae44UL //Access:R    DataWidth:0x20  Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.  Chips: BB_A0 BB_B0 K2
40883 #define PGLUE_B_REG_TAGS_159_128                                                                     0x2aae48UL //Access:R    DataWidth:0x20  Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.  Chips: BB_A0 BB_B0 K2
40884 #define PGLUE_B_REG_TAGS_191_160                                                                     0x2aae4cUL //Access:R    DataWidth:0x20  Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.  Chips: BB_A0 BB_B0 K2
40885 #define PGLUE_B_REG_TAGS_223_192                                                                     0x2aae50UL //Access:R    DataWidth:0x20  Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.  Chips: BB_A0 BB_B0 K2
40886 #define PGLUE_B_REG_TAGS_255_224                                                                     0x2aae54UL //Access:R    DataWidth:0x20  Indicates the status of tags. 0 - tags is used - read completion did not return yet. 1 - tag is unused.  Chips: BB_A0 BB_B0 K2
40887 #define PGLUE_B_REG_PCIE_LTR_STATE                                                                   0x2aae58UL //Access:R    DataWidth:0x2   LTR state indication from PCIe core.  Chips: BB_A0 BB_B0 K2
40888 #define PGLUE_B_REG_CONFIG_REG_78                                                                    0x2aae5cUL //Access:RW   DataWidth:0x20  This register is used for backdoor rbc access to PCI config space register 0x78. There are certain flows (like FLR) where 0x78 should be written but writing it from config space generates Kernel warning. For these cases only it should be written using this rbc register.  Chips: BB_A0 BB_B0 K2
40889 #define PGLUE_B_REG_PF_BAR0_SIZE                                                                     0x2aae60UL //Access:RW   DataWidth:0x4   For Coupled Mode Teaming. The driver should read BAR1_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_CONFIG_2) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G.  Chips: BB_A0 BB_B0 K2
40890 #define PGLUE_B_REG_PF_BAR1_SIZE                                                                     0x2aae64UL //Access:RW   DataWidth:0x4   For Coupled Mode Teaming. The driver should read BAR2_SIZE from PCIe IP config space (bits 3:0 in PCIE_REG_PCIER_REG_BAR2_CONFIG) and configure to this register. Decoding: 0 disabled; 1 64K; 2 128K; up to 15 1G. When using resizable BAR, the driver should read the value from BAR_SIZE (bits 12:8 in PCIE_REG_PCIER_RBAR_CTRL) and adjust the decoding. Adjusting is done by adding 5, since in RBAR 0 represents 1M while in regular decoding 5 represents 1M.  Chips: BB_A0 BB_B0 K2
40891 #define PGLUE_B_REG_VF_BAR1_SIZE                                                                     0x2aae68UL //Access:RW   DataWidth:0x4   For Coupled Mode Teaming. The driver should read BAR2_SIZE_OF_VF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 disabled; 1 4K; 2 8K; up to 15 64M.  Chips: BB_A0 BB_B0 K2
40892 #define PGLUE_B_REG_MCTP_ATTN_CLR                                                                    0x2aae6cUL //Access:W    DataWidth:0x1   Indication to clear MCTP attention that was genertaed due to bus number change detected by PCIe IP. MCP writes 1 to this register in order to clear the level attention.  Chips: BB_A0 BB_B0 K2
40893 #define PGLUE_B_REG_MCTP_TC                                                                          0x2aae70UL //Access:RW   DataWidth:0x3   MCTP TC field. Normally should not be changed.  Chips: BB_A0 BB_B0 K2
40894 #define PGLUE_B_REG_VF_ILT_ERR_ADD_31_0                                                              0x2aae74UL //Access:R    DataWidth:0x20  Address [31:0] of first request with vf ilt error indication.  Chips: BB_A0 BB_B0 K2
40895 #define PGLUE_B_REG_VF_ILT_ERR_ADD_63_32                                                             0x2aae78UL //Access:R    DataWidth:0x20  Address [63:32] of first request with vf ilt error indication.  Chips: BB_A0 BB_B0 K2
40896 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS                                                               0x2aae7cUL //Access:R    DataWidth:0x20  Details of first request with vf ilt error indication. [4:0] VQID. [5] - first SR. [18:6] - Length in bytes. [19] - VF_VALID. [23:20] - PFID. [31:24] - VFID.  Chips: BB_A0 BB_B0 K2
40897 #define PGLUE_B_REG_VF_ILT_ERR_DETAILS2                                                              0x2aae80UL //Access:R    DataWidth:0x18  Details of first request with vf ilt error indication. [15:0] Request ID. [20:16] client ID. [21] - write_n_read: 0 - read; 1 - write. [22] - last SR.  [23] valid - indicates if there was a request submitted with illegal address since the last time this register was cleared.  Chips: BB_A0 BB_B0 K2
40898 #define PGLUE_B_REG_ATOMIC_OP_REQUESTER_ENABLE_PF                                                    0x2aae84UL //Access:R    DataWidth:0x10  Atomic Op requester enable register for all PFs. Each bit indicates if Atomic Operation Requester for the corresponding PF is enabled. Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40899 #define PGLUE_B_REG_EXPANSION_ROM_ATTN                                                               0x2aae88UL //Access:R    DataWidth:0x2   Expansion ROM attention dirty bits. Bit 0 is for engine 0 and bit 1 for engine 1. Set by PXP. Reset by MCP writing 1 to the corresponding bit in expansion_rom_attn_clr.  Chips: BB_A0 BB_B0 K2
40900 #define PGLUE_B_REG_EXPANSION_ROM_ATTN_CLR                                                           0x2aae8cUL //Access:W    DataWidth:0x2   Expansion ROM attention dirty bits clear. Bit 0 is for engine 0 and bit 1 for engine 1. MCP writes 1 to a bit in this register in order to clear the corresponding bit in expansion_rom_attn register.  Chips: BB_A0 BB_B0 K2
40901 #define PGLUE_B_REG_MPS_ATTN                                                                         0x2aae90UL //Access:R    DataWidth:0x10  MPS attention dirty bit. Set by PXP. Reset by MCP writing 1 to the corresponding bit in mps_attn_clr.  Chips: BB_A0 BB_B0 K2
40902 #define PGLUE_B_REG_MPS_ATTN_CLR                                                                     0x2aae94UL //Access:W    DataWidth:0x10  MPS attention dirty bit clear. MCP writes 1 to a bit in this register in order to clear the corresponding bit in mps_attn register.  Chips: BB_A0 BB_B0 K2
40903 #define PGLUE_B_REG_VPD_REQUEST_PF_31_0                                                              0x2aae98UL //Access:R    DataWidth:0x10  VPD request attention dirty bits for all PFs. Each bit indicates that the VPD register of the corresponding PF was set. Set by PXP. Reset by MCP according to VPD flow (write to 0x2430). Note: register contains bits from both paths.  Chips: BB_A0 BB_B0 K2
40904 #define PGLUE_B_REG_PATH_IN_D3_MASK                                                                  0x2aae9cUL //Access:RW   DataWidth:0x10  This register controls the path_in_d3 output to CPMU. Each bit corresponds to a PF in the path. A value of 0 indicates the power state of this PF is not taken into account when determining path_in_d3 output.  A value of 1 indicates the power state of this PF is taken into account  Chips: BB_A0 BB_B0 K2
40905 #define PGLUE_B_REG_VF_BAR_PRIVILEGE                                                                 0x2aaea0UL //Access:RW   DataWidth:0x2   This register determines the GRC privilege level for VF BAR accesses.  Chips: BB_A0 BB_B0 K2
40906 #define PGLUE_B_REG_PF_BAR_PRIVILEGE                                                                 0x2aaea4UL //Access:RW   DataWidth:0x2   This register determines the GRC privilege level for PF BAR accesses.  Chips: BB_A0 BB_B0 K2
40907 #define PGLUE_B_REG_PCI_CONFIG_PRIVILEGE                                                             0x2aaea8UL //Access:RW   DataWidth:0x2   This register determines the GRC privilege level for PCI config space accesses.  Chips: BB_A0 BB_B0 K2
40908 #define PGLUE_B_REG_STICKY_MASTER_ERROR_EN                                                           0x2aaeacUL //Access:RW   DataWidth:0x1   Value of 1 indicates that was_error should be set when BME or fid_enabled bits are cleared for master request.  Chips: BB_A0 BB_B0 K2
40909 #define PGLUE_B_REG_CFG_NO_L1_ON_INT                                                                 0x2aaeb0UL //Access:RW   DataWidth:0x1   Chicken bit to disable app_xfer_pending.  Chips: K2
40910 #define PGLUE_B_REG_VF_BAR0_SIZE                                                                     0x2aaeb4UL //Access:RW   DataWidth:0x4   For Coupled Mode Teaming. The driver should read BAR2_SIZE_OF_VF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 2K; 1 4K; 2 8K; up to 15 64M  Chips: K2
40911 #define PGLUE_B_REG_PF_ROM_SIZE                                                                      0x2aaeb8UL //Access:RW   DataWidth:0x4   For Coupled Mode Teaming. The driver should read ROM_SIZE_OF_PF from PCIe IP config space (bits 11:8 in PCIE_REG_PCIER_REG_VF_BAR_REG) and configure to this register. Decoding: 0 2k; 1 4K; 2 8K; up to 15 64M  Chips: K2
40912 #define PGLUE_B_REG_MCTP_MAX_LENGTH                                                                  0x2aaebcUL //Access:RW   DataWidth:0xa   MCTP MAX lENGTH register If the packet is larger than MAX LENGTH Then the packet will be discard.  Chips: K2
40913 #define PGLUE_B_REG_MCTP_REQID                                                                       0x2aaec0UL //Access:RW   DataWidth:0x10  Request id register for MCTP  Chips: K2
40914 #define PGLUE_B_REG_CFG_VPD_END                                                                      0x2aaec4UL //Access:W    DataWidth:0x10  VPD END Register  Chips: K2
40915 #define PGLUE_B_REG_PBUS_NUM                                                                         0x2aaec8UL //Access:R    DataWidth:0x8   PBUS number  Chips: K2
40916 #define PGLUE_B_REG_PBUS_DEV_NUM                                                                     0x2aaeccUL //Access:R    DataWidth:0x5   PBUS DEV NUM set for MCTP check  Chips: K2
40917 #define PGLUE_B_REG_POISON_DISCARD_MCMPL                                                             0x2aaed0UL //Access:RW   DataWidth:0x1   Discard when poisoned for MCTP packet  Chips: K2
40918 #define PGLUE_B_REG_BUS_CHECK_ENABLE                                                                 0x2aaed4UL //Access:RW   DataWidth:0x1   PBUS bus_check_enable Its for MCTP  Chips: K2
40919 #define PGLUE_B_REG_DEVICE_CHECK_ENABLE                                                              0x2aaed8UL //Access:RW   DataWidth:0x1   PBUS device check enable Its for MCTP packet  Chips: K2
40920 #define PGLUE_B_REG_MCTP_TD_NOT_DROP                                                                 0x2aaedcUL //Access:RW   DataWidth:0x1   enable drop packet when TD is 1  Chips: K2
40921 #define PGLUE_B_REG_MCTP_REQID_FLREN                                                                 0x2aaee0UL //Access:RW   DataWidth:0x2   enable MCTP REQID reuest enable  Chips: K2
40922 #define PGLUE_B_REG_TXR_B2B_DISABLE                                                                  0x2aaee4UL //Access:RW   DataWidth:0x1   Disable master read back 2 back transition IT's checken bit for perfomance improvement If this register is set then b2b transfer will be disable like BB  Chips: K2
40923 #define PGLUE_B_REG_MRRS_ATTN                                                                        0x2aaee8UL //Access:R    DataWidth:0x10  mrrs attn register It's the indicator for MRRS attn  Chips: K2
40924 #define PGLUE_B_REG_MRRS_ATTN_CLR                                                                    0x2aaeecUL //Access:W    DataWidth:0x10  mrrs attn clear set register if these bits set, then we will clear MRRS attn  Chips: K2
40925 #define PGLUE_B_REG_TXW_B2B_DISABLE                                                                  0x2aaef0UL //Access:RW   DataWidth:0x1   Disable master write back 2 back transition  Chips: K2
40926 #define PGLUE_B_REG_ERROR_REG                                                                        0x2aaef4UL //Access:R    DataWidth:0xc   Error log for dllp abort bit8 to 11 pfid bit0 to 7  tag  Chips: K2
40927 #define PGLUE_B_REG_FLR_INVALIDATE_DISABLE                                                           0x2aaef8UL //Access:RW   DataWidth:0x1   Disable FLR Invalidate process  Chips: K2
40928 #define PGLUE_B_REG_INVALIDATE_TAGS_EN                                                               0x2aaefcUL //Access:RW   DataWidth:0x1   Enable invalidate tag  Chips: K2
40929 #define PGLUE_B_REG_DBI_ERR                                                                          0x2aaf00UL //Access:R    DataWidth:0x20  Indicates there was an error in DBI Dbi_error_attn                    Bit0 Dbi_wr                            Bit4 to Bit1 pcie_pgl_dbi_addr                 Bit17 to Bit5 Dbi_func_num                      Bit21 to Bit18 Dbi_vfunc_active                  Bit22 Dbi_vfunc_num                     Bit30 to Bit23  Chips: K2
40930 #define PGLUE_B_REG_DBI_ERR_DATA                                                                     0x2aaf04UL //Access:R    DataWidth:0x20  DBI Error data information  Chips: K2
40931 #define PGLUE_B_REG_DISABLE_POWER_STATE_CHECK                                                        0x2aaf08UL //Access:RW   DataWidth:0x1   Power state check disable register If its 0 Then we will do power state check  Chips: K2
40932 #define PGLUE_B_REG_PGL_PM_DSTATE_31_0                                                               0x2aaf0cUL //Access:R    DataWidth:0x20  DBI Error data information  Chips: K2
40933 #define PGLUE_B_REG_PGL_PM_DSTATE_47_32                                                              0x2aaf10UL //Access:R    DataWidth:0x10  pm_dstate 47-032  Chips: K2
40934 #define PGLUE_B_REG_CHECK_TC_ON_ERR                                                                  0x2aaf5cUL //Access:RW   DataWidth:0x1   check tc on error Its config register if check tc on error = 0 Then we will not check TC If check tc on error =1. we need check if TC = x000  Chips: K2
40935 #define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_31_0                                               0x2aaf60UL //Access:R    DataWidth:0x20  FLR Invalidate in progress vf 31-0  Chips: K2
40936 #define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_63_32                                              0x2aaf64UL //Access:R    DataWidth:0x20  FLR Invalidate in progress vf 63 -32  Chips: K2
40937 #define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_95_64                                              0x2aaf68UL //Access:R    DataWidth:0x20  FLR Invalidate in progress vf 95 - 64  Chips: K2
40938 #define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_127_96                                             0x2aaf6cUL //Access:R    DataWidth:0x20  FLR Invalidate in progress vf 127 - 96  Chips: K2
40939 #define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_159_128                                            0x2aaf70UL //Access:R    DataWidth:0x20  FLR Invalidate in progress vf 159-128  Chips: K2
40940 #define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_VF_191_160                                            0x2aaf74UL //Access:R    DataWidth:0x20  FLR Invalidate in progress vf 191 to 160  Chips: K2
40941 #define PGLUE_B_REG_FLR_INVALIDATE_IN_PROGRESS_PF_31_0                                               0x2aaf78UL //Access:R    DataWidth:0x10  FLR Invalidate in progress pf 31 to 0  Chips: K2
40942 #define PGLUE_B_REG_EXT_TAG_MODE                                                                     0x2aaf7cUL //Access:RW   DataWidth:0x2   Extand tag mode 00 default mode 01 BB mode 10 Read mode  Chips: K2
40943 #define PGLUE_B_REG_MCTP_ERR1                                                                        0x2aaf80UL //Access:R    DataWidth:0x20  Indicates there was an error in MCTP BIt 21-30 Message code Bit 7-22  Vender ID Bit 3-6   TAG Bit 0-2   TC  Chips: K2
40944 #define PGLUE_B_REG_MCTP_ERR2                                                                        0x2aaf84UL //Access:R    DataWidth:0x20  Indicates there was an error in MCTP Bit 21-30 Length Bit 5-20  PCIE REQ ID Bit 0-4   TYPE  Chips: K2
40945 #define PGLUE_B_REG_ERROR_ECRC_REG                                                                   0x2aaf88UL //Access:R    DataWidth:0xc   Error log for ecrc abort bit8 to 11 pfid bit0 to 7  tag  Chips: K2
40946 #define PGLUE_B_REG_ERROR_TLP_REG                                                                    0x2aaf8cUL //Access:R    DataWidth:0xc   Error log for tlp abort bit8 to 11 pfid bit0 to 7  tag  Chips: K2
40947 #define PGLUE_B_REG_ERROR_POISON_REG                                                                 0x2aaf90UL //Access:R    DataWidth:0xc   Error log for poison bit8 to 11 pfid bit0 to 7  tag  Chips: K2
40948 #define PGLUE_B_REG_MCTP_VENDERID_CHK_DISABLE                                                        0x2aaf94UL //Access:RW   DataWidth:0x1   Disable vendorid check in MCTP  Chips: K2
40949 #define PGLUE_B_REG_PGL_ADDR_E8_F0                                                                   0x2aaf98UL //Access:RW   DataWidth:0x20  GRC address for configuration access to PCIE config address 0xe8. any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.  Chips: K2
40950 #define PGLUE_B_REG_PGL_ADDR_EC_F0                                                                   0x2aaf9cUL //Access:RW   DataWidth:0x20  GRC address for configuration access to PCIE config address 0xec.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.  Chips: K2
40951 #define PGLUE_B_REG_PGL_ADDR_F0_F0                                                                   0x2aafa0UL //Access:RW   DataWidth:0x20  GRC address for configuration access to PCIE config address 0xf0.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.  Chips: K2
40952 #define PGLUE_B_REG_PGL_ADDR_F4_F0                                                                   0x2aafa4UL //Access:RW   DataWidth:0x20  GRC address for configuration access to PCIE config address 0xf4.  any write to this PCIE address will cause a GRC write access to the address that's in t this register. E4: split16.  Chips: K2
40953 #define PGLUE_B_REG_EXT_TAG_EN_PF_31_0                                                               0x2aafa8UL //Access:R    DataWidth:0x20  Extended tag enable per PF  Chips: K2
40954 #define PGLUE_B_REG_NO_SNOOP_EN_PF_31_0                                                              0x2aafacUL //Access:R    DataWidth:0x10  No snoop enable per PF  Chips: K2
40955 #define PGLUE_B_REG_RELAXED_ORDERING_EN_PF_31_0                                                      0x2aafb0UL //Access:R    DataWidth:0x10  Relaxed ordering enable per PF  Chips: K2
40956 #define PGLUE_B_REG_DISCARD_HEADER_UNKNOWN                                                           0x2aafb4UL //Access:RW   DataWidth:0x1   0 - Don't discard target request with unknown header type 1 - Discard target request with unknown header type  Chips: K2
40957 #define PGLUE_B_REG_COMPARE_CPL_FUNCTION                                                             0x2aafb8UL //Access:RW   DataWidth:0x1   0 - Don't compare the function received in the completion to the original MRD function. 1 - Compare the function received in the completion to the original MRD function. Discard the completion if the comparison fails.  Chips: K2
40958 #define PGLUE_B_REG_DISABLE_B2B                                                                      0x2aafbcUL //Access:RW   DataWidth:0x1   0 - Enable b2b pop from sync fifos in pgl_pci_core_rx. 1 - Disable b2b pop from sync fifos in pgl_pci_core_rx (chicken bit).  Chips: K2
40959 #define PGLUE_B_REG_DISCARD_MASTER_REQUEST_IN_FLR                                                    0x2aafc0UL //Access:RW   DataWidth:0x1   0 - Don't discard master request during FLR 1 - Discard master request during FLR  Chips: K2
40960 #define TM_REG_MEMORY_SELF_INIT_START                                                                0x2c0000UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
40961     #define TM_REG_MEMORY_SELF_INIT_START_CONTEXT_MEM_SELF_INIT_START                                (0x1<<0) // Reset the context memory. When set, the context memory self init starts.
40962     #define TM_REG_MEMORY_SELF_INIT_START_CONTEXT_MEM_SELF_INIT_START_SHIFT                          0
40963     #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_CONN_MEM_SELF_INIT_START                            (0x1<<1) // Reset the config conn memory. When set, the config conn memory self init starts.
40964     #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_CONN_MEM_SELF_INIT_START_SHIFT                      1
40965     #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_TASK_MEM_SELF_INIT_START                            (0x1<<2) // Reset the config task memory. When set, the config task memory self init starts.
40966     #define TM_REG_MEMORY_SELF_INIT_START_CONFIG_TASK_MEM_SELF_INIT_START_SHIFT                      2
40967     #define TM_REG_MEMORY_SELF_INIT_START_PRE_SCAN_MEM_SELF_INIT_START                               (0x1<<3) // Reset the pre scan memory. When set, the pre scan memory self init starts.
40968     #define TM_REG_MEMORY_SELF_INIT_START_PRE_SCAN_MEM_SELF_INIT_START_SHIFT                         3
40969 #define TM_REG_CONTEXT_MEM_SELF_INIT_DONE                                                            0x2c0004UL //Access:R    DataWidth:0x1   When set, the self init for the context memory is done. TBD - need to change to read, all the bits.  Chips: BB_A0 BB_B0 K2
40970 #define TM_REG_CONFIG_CONN_MEM_SELF_INIT_DONE                                                        0x2c0008UL //Access:R    DataWidth:0x1   When set, the self init for the config conn memory is done.  Chips: BB_A0 BB_B0 K2
40971 #define TM_REG_CONFIG_TASK_MEM_SELF_INIT_DONE                                                        0x2c000cUL //Access:R    DataWidth:0x1   When set, the self init for the config task memory is done.  Chips: BB_A0 BB_B0 K2
40972 #define TM_REG_PRE_SCAN_MEM_SELF_INIT_DONE                                                           0x2c0010UL //Access:R    DataWidth:0x1   When set, the self init for the pre scan memory is done.  Chips: BB_A0 BB_B0 K2
40973 #define TM_REG_PXP_READ_DATA_FIFO_INIT                                                               0x2c0014UL //Access:RW   DataWidth:0x1   When set init the PXP READ DATA FIFO.  Chips: BB_A0 BB_B0 K2
40974 #define TM_REG_PXP_READ_CTRL_FIFO_INIT                                                               0x2c0018UL //Access:RW   DataWidth:0x1   When set init the PXP READ CTRL FIFO.  Chips: BB_A0 BB_B0 K2
40975 #define TM_REG_CFC_LOAD_COMMAND_FIFO_INIT                                                            0x2c001cUL //Access:RW   DataWidth:0x1   When set init the CFC LOAD COMMAND FIFO.  Chips: BB_A0 BB_B0 K2
40976 #define TM_REG_CFC_LOAD_ECHO_FIFO_INIT                                                               0x2c0020UL //Access:RW   DataWidth:0x1   When set init the CFC LOAD ECHO FIFO.  Chips: BB_A0 BB_B0 K2
40977 #define TM_REG_CLIENT_OUT_FIFO_INIT                                                                  0x2c0024UL //Access:RW   DataWidth:0x1   When set init the CLIENT OUT FIFO.  Chips: BB_A0 BB_B0 K2
40978 #define TM_REG_CLIENT_IN_PBF_FIFO_INIT                                                               0x2c0028UL //Access:RW   DataWidth:0x1   When set init the CLIENT IN PBF FIFO.  Chips: BB_A0 BB_B0 K2
40979 #define TM_REG_CLIENT_IN_XCM_FIFO_INIT                                                               0x2c002cUL //Access:RW   DataWidth:0x1   When set init the CLIENT IN XCM FIFO.  Chips: BB_A0 BB_B0 K2
40980 #define TM_REG_CLIENT_IN_TCM_FIFO_INIT                                                               0x2c0030UL //Access:RW   DataWidth:0x1   When set init the CLIENT IN TCM FIFO.  Chips: BB_A0 BB_B0 K2
40981 #define TM_REG_CLIENT_IN_UCM_FIFO_INIT                                                               0x2c0034UL //Access:RW   DataWidth:0x1   When set init the CLIENT IN UCM FIFO.  Chips: BB_A0 BB_B0 K2
40982 #define TM_REG_EXPIRATION_CMD_FIFO_INIT                                                              0x2c0038UL //Access:RW   DataWidth:0x1   When set init the EXPIRATION COMMAND FIFO.  Chips: BB_A0 BB_B0 K2
40983 #define TM_REG_AC_COMMAND_FIFO_INIT                                                                  0x2c003cUL //Access:RW   DataWidth:0x1   When set init the AC COMMAND FIFO.  Chips: BB_A0 BB_B0 K2
40984 #define TM_REG_PXP_INTERFACE_ENABLE                                                                  0x2c0060UL //Access:RW   DataWidth:0x1   Enable pxp request, wr and rd interfaces.  Chips: BB_A0 BB_B0 K2
40985 #define TM_REG_CFC_INTERFACE_ENABLE                                                                  0x2c0064UL //Access:RW   DataWidth:0x1   Enable cfc load request and load response interfaces.  Chips: BB_A0 BB_B0 K2
40986 #define TM_REG_CLIENT_OUT_INTERFACE_ENABLE                                                           0x2c0068UL //Access:RW   DataWidth:0x1   Enable client out interfaces (XCM, UCM, TCM).  Chips: BB_A0 BB_B0 K2
40987 #define TM_REG_CLIENT_IN_INTERFACE_ENABLE                                                            0x2c006cUL //Access:RW   DataWidth:0x1   Enable client in interfaces (XCM, UCM, TCM, PBF).  Chips: BB_A0 BB_B0 K2
40988 #define TM_REG_PXP_REQUEST_CREDIT                                                                    0x2c0078UL //Access:RW   DataWidth:0x2   Credit for the PXP request interface.  Chips: BB_A0 BB_B0 K2
40989 #define TM_REG_CLIENT_OUT_XCM_REQ_CREDIT                                                             0x2c007cUL //Access:RW   DataWidth:0x3   Credit for the XCM client out request interface.  Chips: BB_A0 BB_B0 K2
40990 #define TM_REG_CLIENT_OUT_TCM_REQ_CREDIT                                                             0x2c0080UL //Access:RW   DataWidth:0x3   Credit for the TCM client out request interface.  Chips: BB_A0 BB_B0 K2
40991 #define TM_REG_CLIENT_OUT_UCM_REQ_CREDIT                                                             0x2c0084UL //Access:RW   DataWidth:0x3   Credit for the UCM client out request interface.  Chips: BB_A0 BB_B0 K2
40992 #define TM_REG_LOAD_REQUEST_CREDIT                                                                   0x2c0088UL //Access:RW   DataWidth:0x4   Credit for the CFC load requests. Common for both tasks and connections and equal to the Expiration FIFO row size.                          The number of allowed CFC load requests since they are sent to the CCFC/TCFC till they are read from the Expiration FIFO                           (after CFC load request is received) is less or equal to this credit.                          Value of 0: this credit is disabled.  Chips: BB_A0 BB_B0 K2
40993 #define TM_REG_INT_STS_0                                                                             0x2c0180UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
40994     #define TM_REG_INT_STS_0_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
40995     #define TM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                     0
40996     #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_OV                                                   (0x1<<1) // PXP READ DATA FIFO Overflow.
40997     #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_OV_SHIFT                                             1
40998     #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_UN                                                   (0x1<<2) // PXP READ DATA FIFO Underrun.
40999     #define TM_REG_INT_STS_0_PXP_READ_DATA_FIFO_UN_SHIFT                                             2
41000     #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_OV                                                   (0x1<<3) // PXP READ CTRL FIFO Overflow.
41001     #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_OV_SHIFT                                             3
41002     #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_UN                                                   (0x1<<4) // PXP READ CTRL FIFO Underrun.
41003     #define TM_REG_INT_STS_0_PXP_READ_CTRL_FIFO_UN_SHIFT                                             4
41004     #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_OV                                                (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
41005     #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_OV_SHIFT                                          5
41006     #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_UN                                                (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
41007     #define TM_REG_INT_STS_0_CFC_LOAD_COMMAND_FIFO_UN_SHIFT                                          6
41008     #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_OV                                                   (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
41009     #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT                                             7
41010     #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_UN                                                   (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
41011     #define TM_REG_INT_STS_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT                                             8
41012     #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_OV                                                      (0x1<<9) // CLIENT OUT FIFO Overflow.
41013     #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_OV_SHIFT                                                9
41014     #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_UN                                                      (0x1<<10) // CLIENT OUT FIFO Underrun.
41015     #define TM_REG_INT_STS_0_CLIENT_OUT_FIFO_UN_SHIFT                                                10
41016     #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_OV                                                      (0x1<<11) // AC COMMAND FIFO Overflow.
41017     #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_OV_SHIFT                                                11
41018     #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_UN                                                      (0x1<<12) // AC COMMAND FIFO Underrun.
41019     #define TM_REG_INT_STS_0_AC_COMMAND_FIFO_UN_SHIFT                                                12
41020     #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_OV                                                   (0x1<<13) // CLIENT IN PBF FIFO Overflow.
41021     #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_OV_SHIFT                                             13
41022     #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_UN                                                   (0x1<<14) // CLIENT IN PBF FIFO Underrun.
41023     #define TM_REG_INT_STS_0_CLIENT_IN_PBF_FIFO_UN_SHIFT                                             14
41024     #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_OV                                                   (0x1<<15) // CLIENT IN UCM FIFO Overflow.
41025     #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_OV_SHIFT                                             15
41026     #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_UN                                                   (0x1<<16) // CLIENT IN UCM FIFO Underun.
41027     #define TM_REG_INT_STS_0_CLIENT_IN_UCM_FIFO_UN_SHIFT                                             16
41028     #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_OV                                                   (0x1<<17) // CLIENT IN TCM FIFO Overflow.
41029     #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_OV_SHIFT                                             17
41030     #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_UN                                                   (0x1<<18) // CLIENT IN TCM FIFO Underrun.
41031     #define TM_REG_INT_STS_0_CLIENT_IN_TCM_FIFO_UN_SHIFT                                             18
41032     #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_OV                                                   (0x1<<19) // CLIENT IN XCM FIFO Overflow.
41033     #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_OV_SHIFT                                             19
41034     #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_UN                                                   (0x1<<20) // CLIENT IN XCM FIFO Underrun.
41035     #define TM_REG_INT_STS_0_CLIENT_IN_XCM_FIFO_UN_SHIFT                                             20
41036     #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_OV                                                  (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
41037     #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_OV_SHIFT                                            21
41038     #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_UN                                                  (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
41039     #define TM_REG_INT_STS_0_EXPIRATION_CMD_FIFO_UN_SHIFT                                            22
41040     #define TM_REG_INT_STS_0_STOP_ALL_LC_INVALID                                                     (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
41041     #define TM_REG_INT_STS_0_STOP_ALL_LC_INVALID_SHIFT                                               23
41042     #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_0                                                    (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
41043     #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_0_SHIFT                                              24
41044     #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_1                                                    (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
41045     #define TM_REG_INT_STS_0_COMMAND_LC_INVALID_1_SHIFT                                              25
41046     #define TM_REG_INT_STS_0_INIT_COMMAND_LC_VALID                                                   (0x1<<26) // INIT command and the logical client valid bit is asserted.
41047     #define TM_REG_INT_STS_0_INIT_COMMAND_LC_VALID_SHIFT                                             26
41048     #define TM_REG_INT_STS_0_STOP_ALL_EXP_LC_VALID                                                   (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
41049     #define TM_REG_INT_STS_0_STOP_ALL_EXP_LC_VALID_SHIFT                                             27
41050     #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_0                                                   (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
41051     #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_0_SHIFT                                             28
41052     #define TM_REG_INT_STS_0_RESERVED_COMMAND                                                        (0x1<<29) // RESERVED command.
41053     #define TM_REG_INT_STS_0_RESERVED_COMMAND_SHIFT                                                  29
41054     #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_1                                                   (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
41055     #define TM_REG_INT_STS_0_COMMAND_CID_INVALID_1_SHIFT                                             30
41056     #define TM_REG_INT_STS_0_CLOAD_RES_LOADERR_CONN                                                  (0x1<<31) // Connections Load response with Load Error.
41057     #define TM_REG_INT_STS_0_CLOAD_RES_LOADERR_CONN_SHIFT                                            31
41058 #define TM_REG_INT_MASK_0                                                                            0x2c0184UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
41059     #define TM_REG_INT_MASK_0_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.ADDRESS_ERROR .
41060     #define TM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                    0
41061     #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_OV                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_DATA_FIFO_OV .
41062     #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_OV_SHIFT                                            1
41063     #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_UN                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_DATA_FIFO_UN .
41064     #define TM_REG_INT_MASK_0_PXP_READ_DATA_FIFO_UN_SHIFT                                            2
41065     #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_OV                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_CTRL_FIFO_OV .
41066     #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_OV_SHIFT                                            3
41067     #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_UN                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.PXP_READ_CTRL_FIFO_UN .
41068     #define TM_REG_INT_MASK_0_PXP_READ_CTRL_FIFO_UN_SHIFT                                            4
41069     #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_OV                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_COMMAND_FIFO_OV .
41070     #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_OV_SHIFT                                         5
41071     #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_UN                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_COMMAND_FIFO_UN .
41072     #define TM_REG_INT_MASK_0_CFC_LOAD_COMMAND_FIFO_UN_SHIFT                                         6
41073     #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_OV                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_ECHO_FIFO_OV .
41074     #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT                                            7
41075     #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_UN                                                  (0x1<<8) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CFC_LOAD_ECHO_FIFO_UN .
41076     #define TM_REG_INT_MASK_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT                                            8
41077     #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_OV                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_OUT_FIFO_OV .
41078     #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_OV_SHIFT                                               9
41079     #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_UN                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_OUT_FIFO_UN .
41080     #define TM_REG_INT_MASK_0_CLIENT_OUT_FIFO_UN_SHIFT                                               10
41081     #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_OV                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.AC_COMMAND_FIFO_OV .
41082     #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_OV_SHIFT                                               11
41083     #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_UN                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.AC_COMMAND_FIFO_UN .
41084     #define TM_REG_INT_MASK_0_AC_COMMAND_FIFO_UN_SHIFT                                               12
41085     #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_OV                                                  (0x1<<13) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_PBF_FIFO_OV .
41086     #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_OV_SHIFT                                            13
41087     #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_UN                                                  (0x1<<14) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_PBF_FIFO_UN .
41088     #define TM_REG_INT_MASK_0_CLIENT_IN_PBF_FIFO_UN_SHIFT                                            14
41089     #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_OV                                                  (0x1<<15) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_UCM_FIFO_OV .
41090     #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_OV_SHIFT                                            15
41091     #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_UN                                                  (0x1<<16) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_UCM_FIFO_UN .
41092     #define TM_REG_INT_MASK_0_CLIENT_IN_UCM_FIFO_UN_SHIFT                                            16
41093     #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_OV                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_TCM_FIFO_OV .
41094     #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_OV_SHIFT                                            17
41095     #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_UN                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_TCM_FIFO_UN .
41096     #define TM_REG_INT_MASK_0_CLIENT_IN_TCM_FIFO_UN_SHIFT                                            18
41097     #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_OV                                                  (0x1<<19) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_XCM_FIFO_OV .
41098     #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_OV_SHIFT                                            19
41099     #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_UN                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLIENT_IN_XCM_FIFO_UN .
41100     #define TM_REG_INT_MASK_0_CLIENT_IN_XCM_FIFO_UN_SHIFT                                            20
41101     #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_OV                                                 (0x1<<21) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.EXPIRATION_CMD_FIFO_OV .
41102     #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_OV_SHIFT                                           21
41103     #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_UN                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.EXPIRATION_CMD_FIFO_UN .
41104     #define TM_REG_INT_MASK_0_EXPIRATION_CMD_FIFO_UN_SHIFT                                           22
41105     #define TM_REG_INT_MASK_0_STOP_ALL_LC_INVALID                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.STOP_ALL_LC_INVALID .
41106     #define TM_REG_INT_MASK_0_STOP_ALL_LC_INVALID_SHIFT                                              23
41107     #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_0                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_LC_INVALID_0 .
41108     #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_0_SHIFT                                             24
41109     #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_1                                                   (0x1<<25) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_LC_INVALID_1 .
41110     #define TM_REG_INT_MASK_0_COMMAND_LC_INVALID_1_SHIFT                                             25
41111     #define TM_REG_INT_MASK_0_INIT_COMMAND_LC_VALID                                                  (0x1<<26) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.INIT_COMMAND_LC_VALID .
41112     #define TM_REG_INT_MASK_0_INIT_COMMAND_LC_VALID_SHIFT                                            26
41113     #define TM_REG_INT_MASK_0_STOP_ALL_EXP_LC_VALID                                                  (0x1<<27) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.STOP_ALL_EXP_LC_VALID .
41114     #define TM_REG_INT_MASK_0_STOP_ALL_EXP_LC_VALID_SHIFT                                            27
41115     #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_0                                                  (0x1<<28) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_CID_INVALID_0 .
41116     #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_0_SHIFT                                            28
41117     #define TM_REG_INT_MASK_0_RESERVED_COMMAND                                                       (0x1<<29) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.RESERVED_COMMAND .
41118     #define TM_REG_INT_MASK_0_RESERVED_COMMAND_SHIFT                                                 29
41119     #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_1                                                  (0x1<<30) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.COMMAND_CID_INVALID_1 .
41120     #define TM_REG_INT_MASK_0_COMMAND_CID_INVALID_1_SHIFT                                            30
41121     #define TM_REG_INT_MASK_0_CLOAD_RES_LOADERR_CONN                                                 (0x1<<31) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_0.CLOAD_RES_LOADERR_CONN .
41122     #define TM_REG_INT_MASK_0_CLOAD_RES_LOADERR_CONN_SHIFT                                           31
41123 #define TM_REG_INT_STS_WR_0                                                                          0x2c0188UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
41124     #define TM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
41125     #define TM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                  0
41126     #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_OV                                                (0x1<<1) // PXP READ DATA FIFO Overflow.
41127     #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_OV_SHIFT                                          1
41128     #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_UN                                                (0x1<<2) // PXP READ DATA FIFO Underrun.
41129     #define TM_REG_INT_STS_WR_0_PXP_READ_DATA_FIFO_UN_SHIFT                                          2
41130     #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_OV                                                (0x1<<3) // PXP READ CTRL FIFO Overflow.
41131     #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_OV_SHIFT                                          3
41132     #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_UN                                                (0x1<<4) // PXP READ CTRL FIFO Underrun.
41133     #define TM_REG_INT_STS_WR_0_PXP_READ_CTRL_FIFO_UN_SHIFT                                          4
41134     #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_OV                                             (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
41135     #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_OV_SHIFT                                       5
41136     #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_UN                                             (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
41137     #define TM_REG_INT_STS_WR_0_CFC_LOAD_COMMAND_FIFO_UN_SHIFT                                       6
41138     #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_OV                                                (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
41139     #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT                                          7
41140     #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_UN                                                (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
41141     #define TM_REG_INT_STS_WR_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT                                          8
41142     #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_OV                                                   (0x1<<9) // CLIENT OUT FIFO Overflow.
41143     #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_OV_SHIFT                                             9
41144     #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_UN                                                   (0x1<<10) // CLIENT OUT FIFO Underrun.
41145     #define TM_REG_INT_STS_WR_0_CLIENT_OUT_FIFO_UN_SHIFT                                             10
41146     #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_OV                                                   (0x1<<11) // AC COMMAND FIFO Overflow.
41147     #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_OV_SHIFT                                             11
41148     #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_UN                                                   (0x1<<12) // AC COMMAND FIFO Underrun.
41149     #define TM_REG_INT_STS_WR_0_AC_COMMAND_FIFO_UN_SHIFT                                             12
41150     #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_OV                                                (0x1<<13) // CLIENT IN PBF FIFO Overflow.
41151     #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_OV_SHIFT                                          13
41152     #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_UN                                                (0x1<<14) // CLIENT IN PBF FIFO Underrun.
41153     #define TM_REG_INT_STS_WR_0_CLIENT_IN_PBF_FIFO_UN_SHIFT                                          14
41154     #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_OV                                                (0x1<<15) // CLIENT IN UCM FIFO Overflow.
41155     #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_OV_SHIFT                                          15
41156     #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_UN                                                (0x1<<16) // CLIENT IN UCM FIFO Underun.
41157     #define TM_REG_INT_STS_WR_0_CLIENT_IN_UCM_FIFO_UN_SHIFT                                          16
41158     #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_OV                                                (0x1<<17) // CLIENT IN TCM FIFO Overflow.
41159     #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_OV_SHIFT                                          17
41160     #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_UN                                                (0x1<<18) // CLIENT IN TCM FIFO Underrun.
41161     #define TM_REG_INT_STS_WR_0_CLIENT_IN_TCM_FIFO_UN_SHIFT                                          18
41162     #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_OV                                                (0x1<<19) // CLIENT IN XCM FIFO Overflow.
41163     #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_OV_SHIFT                                          19
41164     #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_UN                                                (0x1<<20) // CLIENT IN XCM FIFO Underrun.
41165     #define TM_REG_INT_STS_WR_0_CLIENT_IN_XCM_FIFO_UN_SHIFT                                          20
41166     #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_OV                                               (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
41167     #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_OV_SHIFT                                         21
41168     #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_UN                                               (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
41169     #define TM_REG_INT_STS_WR_0_EXPIRATION_CMD_FIFO_UN_SHIFT                                         22
41170     #define TM_REG_INT_STS_WR_0_STOP_ALL_LC_INVALID                                                  (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
41171     #define TM_REG_INT_STS_WR_0_STOP_ALL_LC_INVALID_SHIFT                                            23
41172     #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_0                                                 (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
41173     #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_0_SHIFT                                           24
41174     #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_1                                                 (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
41175     #define TM_REG_INT_STS_WR_0_COMMAND_LC_INVALID_1_SHIFT                                           25
41176     #define TM_REG_INT_STS_WR_0_INIT_COMMAND_LC_VALID                                                (0x1<<26) // INIT command and the logical client valid bit is asserted.
41177     #define TM_REG_INT_STS_WR_0_INIT_COMMAND_LC_VALID_SHIFT                                          26
41178     #define TM_REG_INT_STS_WR_0_STOP_ALL_EXP_LC_VALID                                                (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
41179     #define TM_REG_INT_STS_WR_0_STOP_ALL_EXP_LC_VALID_SHIFT                                          27
41180     #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_0                                                (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
41181     #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_0_SHIFT                                          28
41182     #define TM_REG_INT_STS_WR_0_RESERVED_COMMAND                                                     (0x1<<29) // RESERVED command.
41183     #define TM_REG_INT_STS_WR_0_RESERVED_COMMAND_SHIFT                                               29
41184     #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_1                                                (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
41185     #define TM_REG_INT_STS_WR_0_COMMAND_CID_INVALID_1_SHIFT                                          30
41186     #define TM_REG_INT_STS_WR_0_CLOAD_RES_LOADERR_CONN                                               (0x1<<31) // Connections Load response with Load Error.
41187     #define TM_REG_INT_STS_WR_0_CLOAD_RES_LOADERR_CONN_SHIFT                                         31
41188 #define TM_REG_INT_STS_CLR_0                                                                         0x2c018cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
41189     #define TM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
41190     #define TM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                 0
41191     #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_OV                                               (0x1<<1) // PXP READ DATA FIFO Overflow.
41192     #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_OV_SHIFT                                         1
41193     #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_UN                                               (0x1<<2) // PXP READ DATA FIFO Underrun.
41194     #define TM_REG_INT_STS_CLR_0_PXP_READ_DATA_FIFO_UN_SHIFT                                         2
41195     #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_OV                                               (0x1<<3) // PXP READ CTRL FIFO Overflow.
41196     #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_OV_SHIFT                                         3
41197     #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_UN                                               (0x1<<4) // PXP READ CTRL FIFO Underrun.
41198     #define TM_REG_INT_STS_CLR_0_PXP_READ_CTRL_FIFO_UN_SHIFT                                         4
41199     #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_OV                                            (0x1<<5) // CFC LOAD COMMAND FIFO Overflow.
41200     #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_OV_SHIFT                                      5
41201     #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_UN                                            (0x1<<6) // CFC LOAD COMMAND FIFO Underrun.
41202     #define TM_REG_INT_STS_CLR_0_CFC_LOAD_COMMAND_FIFO_UN_SHIFT                                      6
41203     #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_OV                                               (0x1<<7) // CFC LOAD ECHO FIFO Overflow.
41204     #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_OV_SHIFT                                         7
41205     #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_UN                                               (0x1<<8) // CFC LOAD ECHO FIFO Underrun.
41206     #define TM_REG_INT_STS_CLR_0_CFC_LOAD_ECHO_FIFO_UN_SHIFT                                         8
41207     #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_OV                                                  (0x1<<9) // CLIENT OUT FIFO Overflow.
41208     #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_OV_SHIFT                                            9
41209     #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_UN                                                  (0x1<<10) // CLIENT OUT FIFO Underrun.
41210     #define TM_REG_INT_STS_CLR_0_CLIENT_OUT_FIFO_UN_SHIFT                                            10
41211     #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_OV                                                  (0x1<<11) // AC COMMAND FIFO Overflow.
41212     #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_OV_SHIFT                                            11
41213     #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_UN                                                  (0x1<<12) // AC COMMAND FIFO Underrun.
41214     #define TM_REG_INT_STS_CLR_0_AC_COMMAND_FIFO_UN_SHIFT                                            12
41215     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_OV                                               (0x1<<13) // CLIENT IN PBF FIFO Overflow.
41216     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_OV_SHIFT                                         13
41217     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_UN                                               (0x1<<14) // CLIENT IN PBF FIFO Underrun.
41218     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_PBF_FIFO_UN_SHIFT                                         14
41219     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_OV                                               (0x1<<15) // CLIENT IN UCM FIFO Overflow.
41220     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_OV_SHIFT                                         15
41221     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_UN                                               (0x1<<16) // CLIENT IN UCM FIFO Underun.
41222     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_UCM_FIFO_UN_SHIFT                                         16
41223     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_OV                                               (0x1<<17) // CLIENT IN TCM FIFO Overflow.
41224     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_OV_SHIFT                                         17
41225     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_UN                                               (0x1<<18) // CLIENT IN TCM FIFO Underrun.
41226     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_TCM_FIFO_UN_SHIFT                                         18
41227     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_OV                                               (0x1<<19) // CLIENT IN XCM FIFO Overflow.
41228     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_OV_SHIFT                                         19
41229     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_UN                                               (0x1<<20) // CLIENT IN XCM FIFO Underrun.
41230     #define TM_REG_INT_STS_CLR_0_CLIENT_IN_XCM_FIFO_UN_SHIFT                                         20
41231     #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_OV                                              (0x1<<21) // EXPIRATION COMMAND FIFO Overflow.
41232     #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_OV_SHIFT                                        21
41233     #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_UN                                              (0x1<<22) // EXPIRATION COMMAND FIFO Underrun.
41234     #define TM_REG_INT_STS_CLR_0_EXPIRATION_CMD_FIFO_UN_SHIFT                                        22
41235     #define TM_REG_INT_STS_CLR_0_STOP_ALL_LC_INVALID                                                 (0x1<<23) // STOP_ALL_TIMERS command and the logical client is invalid.
41236     #define TM_REG_INT_STS_CLR_0_STOP_ALL_LC_INVALID_SHIFT                                           23
41237     #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_0                                                (0x1<<24) // SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical clients is valid.
41238     #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_0_SHIFT                                          24
41239     #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_1                                                (0x1<<25) // SET/CLEAR/FORCE CLEAR command and the logical client is invalid and the other logical clients are also invalid.
41240     #define TM_REG_INT_STS_CLR_0_COMMAND_LC_INVALID_1_SHIFT                                          25
41241     #define TM_REG_INT_STS_CLR_0_INIT_COMMAND_LC_VALID                                               (0x1<<26) // INIT command and the logical client valid bit is asserted.
41242     #define TM_REG_INT_STS_CLR_0_INIT_COMMAND_LC_VALID_SHIFT                                         26
41243     #define TM_REG_INT_STS_CLR_0_STOP_ALL_EXP_LC_VALID                                               (0x1<<27) // Stop all expiration and the valid of one of the logical clients is asserted.
41244     #define TM_REG_INT_STS_CLR_0_STOP_ALL_EXP_LC_VALID_SHIFT                                         27
41245     #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_0                                               (0x1<<28) // Command with C/TID > 64K or VF TID segment not zero.
41246     #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_0_SHIFT                                         28
41247     #define TM_REG_INT_STS_CLR_0_RESERVED_COMMAND                                                    (0x1<<29) // RESERVED command.
41248     #define TM_REG_INT_STS_CLR_0_RESERVED_COMMAND_SHIFT                                              29
41249     #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_1                                               (0x1<<30) // Command arrived to the host handler unit with CID/TID > Num_of_timers for that function.
41250     #define TM_REG_INT_STS_CLR_0_COMMAND_CID_INVALID_1_SHIFT                                         30
41251     #define TM_REG_INT_STS_CLR_0_CLOAD_RES_LOADERR_CONN                                              (0x1<<31) // Connections Load response with Load Error.
41252     #define TM_REG_INT_STS_CLR_0_CLOAD_RES_LOADERR_CONN_SHIFT                                        31
41253 #define TM_REG_INT_STS_1                                                                             0x2c0190UL //Access:R    DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41254     #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_CONN                                               (0x1<<0) // Connections Load response with Load Cancel Error.
41255     #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_CONN_SHIFT                                         0
41256     #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_CONN                                                 (0x1<<1) // Connections Load response with Validation Error.
41257     #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_CONN_SHIFT                                           1
41258     #define TM_REG_INT_STS_1_CONTEXT_RD_LAST                                                         (0x1<<2) // Context Read with Last indication de-asserted.
41259     #define TM_REG_INT_STS_1_CONTEXT_RD_LAST_SHIFT                                                   2
41260     #define TM_REG_INT_STS_1_CONTEXT_WR_LAST                                                         (0x1<<3) // Context Write with Last indication de-asserted.
41261     #define TM_REG_INT_STS_1_CONTEXT_WR_LAST_SHIFT                                                   3
41262     #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_BVALID                                                  (0x1<<4) // PXP Read Data EOP with BVALID != 0.
41263     #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_BVALID_SHIFT                                            4
41264     #define TM_REG_INT_STS_1_PEND_CONN_SCAN                                                          (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
41265     #define TM_REG_INT_STS_1_PEND_CONN_SCAN_SHIFT                                                    5
41266     #define TM_REG_INT_STS_1_PEND_TASK_SCAN                                                          (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
41267     #define TM_REG_INT_STS_1_PEND_TASK_SCAN_SHIFT                                                    6
41268     #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_ERROR                                                   (0x1<<7) // PXP Read Data EOP with ERROR.
41269     #define TM_REG_INT_STS_1_PXP_RD_DATA_EOP_ERROR_SHIFT                                             7
41270     #define TM_REG_INT_STS_1_CLOAD_RES_LOADERR_TASK                                                  (0x1<<8) // Tasks Load response with Load Error
41271     #define TM_REG_INT_STS_1_CLOAD_RES_LOADERR_TASK_SHIFT                                            8
41272     #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_TASK                                               (0x1<<9) // Tasks Load response with Load Cancel Error.
41273     #define TM_REG_INT_STS_1_CLOAD_RES_LOADCANCEL_TASK_SHIFT                                         9
41274     #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_TASK                                                 (0x1<<10) // Tasks Load response with Validation Error.
41275     #define TM_REG_INT_STS_1_CLOAD_RES_VALIDERR_TASK_SHIFT                                           10
41276 #define TM_REG_INT_MASK_1                                                                            0x2c0194UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41277     #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_CONN                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADCANCEL_CONN .
41278     #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_CONN_SHIFT                                        0
41279     #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_CONN                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_VALIDERR_CONN .
41280     #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_CONN_SHIFT                                          1
41281     #define TM_REG_INT_MASK_1_CONTEXT_RD_LAST                                                        (0x1<<2) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CONTEXT_RD_LAST .
41282     #define TM_REG_INT_MASK_1_CONTEXT_RD_LAST_SHIFT                                                  2
41283     #define TM_REG_INT_MASK_1_CONTEXT_WR_LAST                                                        (0x1<<3) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CONTEXT_WR_LAST .
41284     #define TM_REG_INT_MASK_1_CONTEXT_WR_LAST_SHIFT                                                  3
41285     #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_BVALID                                                 (0x1<<4) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PXP_RD_DATA_EOP_BVALID .
41286     #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_BVALID_SHIFT                                           4
41287     #define TM_REG_INT_MASK_1_PEND_CONN_SCAN                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PEND_CONN_SCAN .
41288     #define TM_REG_INT_MASK_1_PEND_CONN_SCAN_SHIFT                                                   5
41289     #define TM_REG_INT_MASK_1_PEND_TASK_SCAN                                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PEND_TASK_SCAN .
41290     #define TM_REG_INT_MASK_1_PEND_TASK_SCAN_SHIFT                                                   6
41291     #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_ERROR                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.PXP_RD_DATA_EOP_ERROR .
41292     #define TM_REG_INT_MASK_1_PXP_RD_DATA_EOP_ERROR_SHIFT                                            7
41293     #define TM_REG_INT_MASK_1_CLOAD_RES_LOADERR_TASK                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADERR_TASK .
41294     #define TM_REG_INT_MASK_1_CLOAD_RES_LOADERR_TASK_SHIFT                                           8
41295     #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_TASK                                              (0x1<<9) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_LOADCANCEL_TASK .
41296     #define TM_REG_INT_MASK_1_CLOAD_RES_LOADCANCEL_TASK_SHIFT                                        9
41297     #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_TASK                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: TM_REG_INT_STS_1.CLOAD_RES_VALIDERR_TASK .
41298     #define TM_REG_INT_MASK_1_CLOAD_RES_VALIDERR_TASK_SHIFT                                          10
41299 #define TM_REG_INT_STS_WR_1                                                                          0x2c0198UL //Access:WR   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41300     #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_CONN                                            (0x1<<0) // Connections Load response with Load Cancel Error.
41301     #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_CONN_SHIFT                                      0
41302     #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_CONN                                              (0x1<<1) // Connections Load response with Validation Error.
41303     #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_CONN_SHIFT                                        1
41304     #define TM_REG_INT_STS_WR_1_CONTEXT_RD_LAST                                                      (0x1<<2) // Context Read with Last indication de-asserted.
41305     #define TM_REG_INT_STS_WR_1_CONTEXT_RD_LAST_SHIFT                                                2
41306     #define TM_REG_INT_STS_WR_1_CONTEXT_WR_LAST                                                      (0x1<<3) // Context Write with Last indication de-asserted.
41307     #define TM_REG_INT_STS_WR_1_CONTEXT_WR_LAST_SHIFT                                                3
41308     #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_BVALID                                               (0x1<<4) // PXP Read Data EOP with BVALID != 0.
41309     #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_BVALID_SHIFT                                         4
41310     #define TM_REG_INT_STS_WR_1_PEND_CONN_SCAN                                                       (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
41311     #define TM_REG_INT_STS_WR_1_PEND_CONN_SCAN_SHIFT                                                 5
41312     #define TM_REG_INT_STS_WR_1_PEND_TASK_SCAN                                                       (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
41313     #define TM_REG_INT_STS_WR_1_PEND_TASK_SCAN_SHIFT                                                 6
41314     #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_ERROR                                                (0x1<<7) // PXP Read Data EOP with ERROR.
41315     #define TM_REG_INT_STS_WR_1_PXP_RD_DATA_EOP_ERROR_SHIFT                                          7
41316     #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADERR_TASK                                               (0x1<<8) // Tasks Load response with Load Error
41317     #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADERR_TASK_SHIFT                                         8
41318     #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_TASK                                            (0x1<<9) // Tasks Load response with Load Cancel Error.
41319     #define TM_REG_INT_STS_WR_1_CLOAD_RES_LOADCANCEL_TASK_SHIFT                                      9
41320     #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_TASK                                              (0x1<<10) // Tasks Load response with Validation Error.
41321     #define TM_REG_INT_STS_WR_1_CLOAD_RES_VALIDERR_TASK_SHIFT                                        10
41322 #define TM_REG_INT_STS_CLR_1                                                                         0x2c019cUL //Access:RC   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41323     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_CONN                                           (0x1<<0) // Connections Load response with Load Cancel Error.
41324     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_CONN_SHIFT                                     0
41325     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_CONN                                             (0x1<<1) // Connections Load response with Validation Error.
41326     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_CONN_SHIFT                                       1
41327     #define TM_REG_INT_STS_CLR_1_CONTEXT_RD_LAST                                                     (0x1<<2) // Context Read with Last indication de-asserted.
41328     #define TM_REG_INT_STS_CLR_1_CONTEXT_RD_LAST_SHIFT                                               2
41329     #define TM_REG_INT_STS_CLR_1_CONTEXT_WR_LAST                                                     (0x1<<3) // Context Write with Last indication de-asserted.
41330     #define TM_REG_INT_STS_CLR_1_CONTEXT_WR_LAST_SHIFT                                               3
41331     #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_BVALID                                              (0x1<<4) // PXP Read Data EOP with BVALID != 0.
41332     #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_BVALID_SHIFT                                        4
41333     #define TM_REG_INT_STS_CLR_1_PEND_CONN_SCAN                                                      (0x1<<5) // Pending connection scan (the previous connection scan is still ongoing while there is a new connection scan pulse).
41334     #define TM_REG_INT_STS_CLR_1_PEND_CONN_SCAN_SHIFT                                                5
41335     #define TM_REG_INT_STS_CLR_1_PEND_TASK_SCAN                                                      (0x1<<6) // Pending task scan (the previous task scan is still ongoing while there is a new task scan pulse).
41336     #define TM_REG_INT_STS_CLR_1_PEND_TASK_SCAN_SHIFT                                                6
41337     #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_ERROR                                               (0x1<<7) // PXP Read Data EOP with ERROR.
41338     #define TM_REG_INT_STS_CLR_1_PXP_RD_DATA_EOP_ERROR_SHIFT                                         7
41339     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADERR_TASK                                              (0x1<<8) // Tasks Load response with Load Error
41340     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADERR_TASK_SHIFT                                        8
41341     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_TASK                                           (0x1<<9) // Tasks Load response with Load Cancel Error.
41342     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_LOADCANCEL_TASK_SHIFT                                     9
41343     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_TASK                                             (0x1<<10) // Tasks Load response with Validation Error.
41344     #define TM_REG_INT_STS_CLR_1_CLOAD_RES_VALIDERR_TASK_SHIFT                                       10
41345 #define TM_REG_PRTY_MASK_H_0                                                                         0x2c0204UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
41346     #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM012_I_ECC_0_RF_INT .
41347     #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_SHIFT                                         0
41348     #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM012_I_ECC_1_RF_INT .
41349     #define TM_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_SHIFT                                         1
41350     #define TM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT                                                 (0x1<<2) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
41351     #define TM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT                                           2
41352     #define TM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY                                                   (0x1<<3) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
41353     #define TM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_SHIFT                                             3
41354     #define TM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                   (0x1<<4) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
41355     #define TM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                             4
41356     #define TM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                   (0x1<<5) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
41357     #define TM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                             5
41358     #define TM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                   (0x1<<6) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
41359     #define TM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                             6
41360     #define TM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                   (0x1<<7) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
41361     #define TM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                             7
41362     #define TM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                                   (0x1<<8) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
41363     #define TM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                             8
41364     #define TM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY                                                   (0x1<<9) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
41365     #define TM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_SHIFT                                             9
41366     #define TM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY                                                   (0x1<<10) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
41367     #define TM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT                                             10
41368     #define TM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                   (0x1<<11) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
41369     #define TM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                             11
41370     #define TM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                   (0x1<<12) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
41371     #define TM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                             12
41372     #define TM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                   (0x1<<13) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
41373     #define TM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                             13
41374     #define TM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                   (0x1<<14) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
41375     #define TM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                             14
41376     #define TM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                   (0x1<<15) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
41377     #define TM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                             15
41378     #define TM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                   (0x1<<16) // This bit masks, when set, the Parity bit: TM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
41379     #define TM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                             16
41380 #define TM_REG_MEM_ECC_EVENTS                                                                        0x2c021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
41381 #define TM_REG_MEM012_I_MEM_DFT_K2                                                                   0x2c0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tm.i_tm_context_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
41382 #define TM_REG_MEM016_I_MEM_DFT_K2                                                                   0x2c0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tm.i_tm_tick_timer_val_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
41383 #define TM_REG_MEM015_I_MEM_DFT_K2                                                                   0x2c022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tm.i_tm_pxp_read_data_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
41384 #define TM_REG_MEM005_I_MEM_DFT_K2                                                                   0x2c0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tm.i_tm_cfc_load_command_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
41385 #define TM_REG_MEM006_I_MEM_DFT_K2                                                                   0x2c0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tm.i_tm_cfc_load_echo_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
41386 #define TM_REG_MEM001_I_MEM_DFT_K2                                                                   0x2c0238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tm.TM_CONFIG_CONN_208_IF.i_tm_config_conn_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
41387 #define TM_REG_MEM002_I_MEM_DFT_K2                                                                   0x2c023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tm.TM_CONFIG_TASK_256_IF.i_tm_config_task_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
41388 #define TM_REG_MEM003_I_MEM_DFT_K2                                                                   0x2c0240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tm.TM_PRE_SCAN_2048_ROWS_IF.i_tm_pre_scan_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
41389 #define TM_REG_PXP_READ_DATA_FIFO_A_F_THR                                                            0x2c0400UL //Access:RW   DataWidth:0x6   Almost full threshold for the PXP READ DATA FIFO, which its size is 48 rows.  Chips: BB_A0 BB_B0 K2
41390 #define TM_REG_PXP_READ_CTRL_FIFO_A_F_THR                                                            0x2c0404UL //Access:RW   DataWidth:0x4   Almost full threshold for the PXP READ CTRL FIFO, which its size is 8 rows.  Chips: BB_A0 BB_B0 K2
41391 #define TM_REG_CFC_LOAD_COMMAND_FIFO_A_F_THR                                                         0x2c0408UL //Access:RW   DataWidth:0x5   Almost full threshold for the CFC LOAD COMMAND FIFO, which its size is 16 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41392 #define TM_REG_CLIENT_OUT_FIFO_A_F_THR                                                               0x2c040cUL //Access:RW   DataWidth:0x4   Almost full threshold for the CLIENT OUT FIFO, which its size is 4 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41393 #define TM_REG_CLIENT_IN_PBF_FIFO_A_F_THR                                                            0x2c0410UL //Access:RW   DataWidth:0x3   Almost full threshold for the CLIENT IN PBF FIFO, which its size is 4 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41394 #define TM_REG_CLIENT_IN_XCM_FIFO_A_F_THR                                                            0x2c0414UL //Access:RW   DataWidth:0x3   Almost full threshold for the CLIENT IN XCM FIFO, which its size is 4 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41395 #define TM_REG_CLIENT_IN_TCM_FIFO_A_F_THR                                                            0x2c0418UL //Access:RW   DataWidth:0x3   Almost full threshold for the CLIENT IN TCM FIFO, which its size is 4 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41396 #define TM_REG_CLIENT_IN_UCM_FIFO_A_F_THR                                                            0x2c041cUL //Access:RW   DataWidth:0x3   Almost full threshold for the CLIENT IN UCM FIFO, which its size is 4 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41397 #define TM_REG_EXPIRATION_CMD_FIFO_A_F_THR                                                           0x2c0420UL //Access:RW   DataWidth:0x4   Almost full threshold for the EXPIRATION COMMAND FIFO, which its size is 8 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41398 #define TM_REG_CFC_LOAD_ECHO_FIFO_A_F_THR                                                            0x2c0424UL //Access:RW   DataWidth:0x5   Almost full threshold for the CFC LOAD ECHO FIFO, which its size is 16 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41399 #define TM_REG_AC_COMMAND_FIFO_A_F_THR                                                               0x2c0428UL //Access:RW   DataWidth:0x4   Almost full threshold for the AC COMMAND FIFO, which its size is 12 rows. For Debug only.  Chips: BB_A0 BB_B0 K2
41400 #define TM_REG_VF_ENABLE_CONN                                                                        0x2c0438UL //Access:RW   DataWidth:0x1   Enable the VF functions for the connections. This configuration is applicable only to scan operation.  Was: en_linear0_timer.  Chips: BB_A0 BB_B0 K2
41401 #define TM_REG_PF_ENABLE_CONN                                                                        0x2c043cUL //Access:RW   DataWidth:0x1   Enable the PF functions for the connections. This configuration is applicable only to scan opeartion.  Chips: BB_A0 BB_B0 K2
41402 #define TM_REG_VF_ENABLE_TASK                                                                        0x2c0440UL //Access:RW   DataWidth:0x1   Enable the VF functions for the tasks. This configuration is applicable only to scan operation.  Was: en_linear1_timer.  Chips: BB_A0 BB_B0 K2
41403 #define TM_REG_PF_ENABLE_TASK                                                                        0x2c0444UL //Access:RW   DataWidth:0x4   Enable the PF functions for the tasks. This configuration is applicable only to scan opeartion. Bit 0: segment 0, bit 1: segment 1, bit 2: segment 2, bit 3: segment 3. Was: en_linear1_timer.  Chips: BB_A0 BB_B0 K2
41404 #define TM_REG_TICK_TIMER_VAL                                                                        0x2c0448UL //Access:RW   DataWidth:0x12  The number of clock cycles (25MHz clock) for each timer tick. Previous name: timer_tick_size.  Chips: BB_A0 BB_B0 K2
41405 #define TM_REG_TICK_TIMER_ENABLE                                                                     0x2c044cUL //Access:RW   DataWidth:0x1   When set, enable the tick_timer.  Chips: BB_A0 BB_B0 K2
41406 #define TM_REG_CONNECTIONS_SCAN_TIMER_VAL                                                            0x2c0450UL //Access:RW   DataWidth:0x14  The count value for the connections scan timer, which counts number of ticks (tick_timer) that generate a connection scan pulse, an indication to scan the connections timers. The minimum value is 2.  Chips: BB_A0 BB_B0 K2
41407 #define TM_REG_CONNECTIONS_SCAN_TIMER_ENABLE                                                         0x2c0454UL //Access:RW   DataWidth:0x1   When set, enable the connections scan timer.  Chips: BB_A0 BB_B0 K2
41408 #define TM_REG_TASKS_SCAN_TIMER_VAL                                                                  0x2c0458UL //Access:RW   DataWidth:0x14  The count value for the tasks scan timer, which counts number of ticks (tick_timer) that generate a tasks scan pulse, an indication to scan the tasks timers. The minimum value is 2.  Chips: BB_A0 BB_B0 K2
41409 #define TM_REG_TASKS_SCAN_TIMER_ENABLE                                                               0x2c045cUL //Access:RW   DataWidth:0x1   When set, enable the tasks scan timer.  Chips: BB_A0 BB_B0 K2
41410 #define TM_REG_CONTEXT_REGION_CONN                                                                   0x2c0460UL //Access:RW   DataWidth:0x8   The Context Region for the connections CFC context load command.  Chips: BB_A0 BB_B0 K2
41411 #define TM_REG_CONTEXT_REGION_TASK                                                                   0x2c0464UL //Access:RW   DataWidth:0x8   The Context Region for the tasks CFC context load command.  Chips: BB_A0 BB_B0 K2
41412 #define TM_REG_PCI_VQ_ID                                                                             0x2c0468UL //Access:RW   DataWidth:0x5   Pci VQ ID.  Chips: BB_A0 BB_B0 K2
41413 #define TM_REG_PCI_TPH_VALID                                                                         0x2c046cUL //Access:RW   DataWidth:0x1   Pci TPH valid.  Chips: BB_A0 BB_B0 K2
41414 #define TM_REG_PCI_TPH_ST_HINT                                                                       0x2c0470UL //Access:RW   DataWidth:0x2   Pci TPH ST hint.  Chips: BB_A0 BB_B0 K2
41415 #define TM_REG_PCI_TPH_STT_IDX                                                                       0x2c0474UL //Access:RW   DataWidth:0x9   Pci TPH STT IDX.  Chips: BB_A0 BB_B0 K2
41416 #define TM_REG_PCI_REQUEST_DONE_TYPE                                                                 0x2c0478UL //Access:RW   DataWidth:0x1   Pci request done type.  Chips: BB_A0 BB_B0 K2
41417 #define TM_REG_PCI_USE_PARENT_PF                                                                     0x2c047cUL //Access:RW   DataWidth:0x1   Pci use parent PF.  Chips: BB_A0 BB_B0 K2
41418 #define TM_REG_PCI_NUMBER_READ_REQUESTS                                                              0x2c0480UL //Access:RW   DataWidth:0x3   The maximum number for the pci outstanding read requests, generated by the scan engine. The applicable values are 1 to 4.  Chips: BB_A0 BB_B0 K2
41419 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN                                                            0x2c0484UL //Access:RW   DataWidth:0x2   Number of timers per connection group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 11 - 16 timers.  Chips: BB_A0 BB_B0 K2
41420 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK                                                            0x2c0488UL //Access:RW   DataWidth:0x2   Number of timers per task group: 00 - 128 timers, 01 - 64 timers, 10 - 32 timers, 11 - 16 timers.  Chips: BB_A0 BB_B0 K2
41421 #define TM_REG_PRE_SCAN_RANGE_CONN                                                                   0x2c048cUL //Access:RW   DataWidth:0x2   Selection when to scan a connection group: 00 - the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each group is selected to be scanned based on its nearest timer, every 1,2,4 scan pulses.  10 - each group is selected to be scanned based on its nearest timer, every 1,4,16 scan pulses.  11 - each group is selected to be scanned based on its nearest timer, every 1,8,64 scan pulses.  Chips: BB_A0 BB_B0 K2
41422 #define TM_REG_PRE_SCAN_RANGE_TASK                                                                   0x2c0490UL //Access:RW   DataWidth:0x2   Selection when to scan a task group: 00 - the pre scan feature is disabled, i.e. every scan pulse all the groups are scanned. 01 - each group is selected to be scanned based on its nearest timer, every 1,2,4 scan pulses.  10 - each group is selected to be scanned based on its nearest timer, every 1,4,16 scan pulses.  11 - each group is selected to be scanned based on its nearest timer, every 1,8,64 scan pulses.  Chips: BB_A0 BB_B0 K2
41423 #define TM_REG_PRE_SCAN_MEM_BYPASS                                                                   0x2c0494UL //Access:RW   DataWidth:0x1   When set, the pre scan memory is bypassed. This configuration is applicable only if PreScanRange register is set to 0. TBD = name of the other register.  Chips: BB_A0 BB_B0 K2
41424 #define TM_REG_ECO_RESERVED                                                                          0x2c0498UL //Access:RW   DataWidth:0x8   For ECOs.  Chips: BB_A0 BB_B0 K2
41425 #define TM_REG_PCI_ATC_RD_FIRST_BLOCK                                                                0x2c049cUL //Access:RW   DataWidth:0x3   ATC flag for reading first block in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search only, 10 - search & cache, 11 - search & release. Was: pci_atc_rd_first_block.  Chips: BB_A0 BB_B0 K2
41426 #define TM_REG_PCI_ATC_RD_LAST_BLOCK                                                                 0x2c04a0UL //Access:RW   DataWidth:0x3   ATC flag for reading last block in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search only, 10 - search & cache, 11 - search & release. Was: atc_page_las_bnk_rd.  Chips: BB_A0 BB_B0 K2
41427 #define TM_REG_PCI_ATC_RD_MIDDLE_BLOCK                                                               0x2c04a4UL //Access:RW   DataWidth:0x3   ATC flag for reading middle blockss in a page; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search only, 10 - search & cache, 11 - search & release. Was atc_page_mid_bnk_rd.  Chips: BB_A0 BB_B0 K2
41428 #define TM_REG_PCI_ATC_WR                                                                            0x2c04a8UL //Access:RW   DataWidth:0x3   ATC field for writes; bit2: 0 - low priority, 1 - high priority; bit[1:0]: 00 - do nothing, 01 - search only, 10 - search & cache, 11 - search & release.  Chips: BB_A0 BB_B0 K2
41429 #define TM_REG_LOGICAL_0_CLIENT_EXP_CONN                                                             0x2c04acUL //Access:RW   DataWidth:0x10  For logical client 0, per each connection type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.  Chips: BB_A0 BB_B0 K2
41430 #define TM_REG_LOGICAL_1_CLIENT_EXP_CONN                                                             0x2c04b0UL //Access:RW   DataWidth:0x10  For logical client 1, per each connection type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.  Chips: BB_A0 BB_B0 K2
41431 #define TM_REG_LOGICAL_2_CLIENT_EXP_CONN                                                             0x2c04b4UL //Access:RW   DataWidth:0x10  For logical client 2, per each connection type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.  Chips: BB_A0 BB_B0 K2
41432 #define TM_REG_LOGICAL_0_CLIENT_EXP_TASK                                                             0x2c04b8UL //Access:RW   DataWidth:0x10  For logical client 0, per each task type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.  Chips: BB_A0 BB_B0 K2
41433 #define TM_REG_LOGICAL_1_CLIENT_EXP_TASK                                                             0x2c04bcUL //Access:RW   DataWidth:0x10  For logical client 1, per each task type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.  Chips: BB_A0 BB_B0 K2
41434 #define TM_REG_LOGICAL_2_CLIENT_EXP_TASK                                                             0x2c04c0UL //Access:RW   DataWidth:0x10  For logical client 2, per each task type (8 types), configuration of the applicable client out interface that the expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.  Chips: BB_A0 BB_B0 K2
41435 #define TM_REG_CLIENT_STOP_ALL_EXP_CONN                                                              0x2c04c4UL //Access:RW   DataWidth:0x10  For stop all expiration, per each connection type (8 types), configuration of the applicable client out interface that the stop all expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.  Chips: BB_A0 BB_B0 K2
41436 #define TM_REG_CLIENT_STOP_ALL_EXP_TASK                                                              0x2c04c8UL //Access:RW   DataWidth:0x10  For stop all expiration, per each task type (8 types), configuration of the applicable client out interface that the stop all expiration command is sent to. The client out decoding is : 00 - XCM, 01 - TCM, 10 - UCM, 11 - reserved. Bits [1:0] - client out for type 0, Bits [3:2] - client out for type 1, Bits [5:4] - client out for type 2, Bits [7:6] - client out for type 3, Bits [9:8] - client out for type 4, Bits [11:10] - client out for type 5, Bits [13:12] - client out for type 6, Bits [15:14] - client out for type 7.  Chips: BB_A0 BB_B0 K2
41437 #define TM_REG_LOGICAL_0_CONN_THRESH_SEL                                                             0x2c04ccUL //Access:RW   DataWidth:0x10  For logical client 0, per each connection type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.  Chips: BB_A0 BB_B0 K2
41438 #define TM_REG_LOGICAL_1_CONN_THRESH_SEL                                                             0x2c04d0UL //Access:RW   DataWidth:0x10  For logical client 1, per each connection type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.  Chips: BB_A0 BB_B0 K2
41439 #define TM_REG_LOGICAL_2_CONN_THRESH_SEL                                                             0x2c04d4UL //Access:RW   DataWidth:0x10  For logical client 2, per each connection type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.  Chips: BB_A0 BB_B0 K2
41440 #define TM_REG_LOGICAL_0_TASK_THRESH_SEL                                                             0x2c04d8UL //Access:RW   DataWidth:0x10  For logical client 0, per each task type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.  Chips: BB_A0 BB_B0 K2
41441 #define TM_REG_LOGICAL_1_TASK_THRESH_SEL                                                             0x2c04dcUL //Access:RW   DataWidth:0x10  For logical client 1, per each task type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.  Chips: BB_A0 BB_B0 K2
41442 #define TM_REG_LOGICAL_2_TASK_THRESH_SEL                                                             0x2c04e0UL //Access:RW   DataWidth:0x10  For logical client 2, per each task type (8 types), configuration of the threshold on the nearest expiration for sending write command to host. The threshold decoding is : 00 - No threshold; Command to the host is set without checking threshold, 01 - Threshold according to global configuration conn_timer_threshold_0, 10 - Threshold according to global configuration conn_timer_threshold_1, 11 - Threshold according to global configuration conn_timer_threshold_2. Bits [1:0] - threshold selection for  type 0, Bits [3:2] - threshold selection for  type 1, Bits [5:4] - threshold selection for  type 2, Bits [7:6] - threshold selection for  type 3, Bits [9:8] - threshold selection for  type 4, Bits [11:10] - threshold selection for  type 5, Bits [13:12] - threshold selection for  type 6, Bits [15:14] - threshold selection for  type 7.  Chips: BB_A0 BB_B0 K2
41443 #define TM_REG_CONN_TIMER_THRESHOLD_0                                                                0x2c04e4UL //Access:RW   DataWidth:0x1a  A threshold value, 0 , for connections, which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_conn_thresh_sel, logical_1_conn_thresh_sel and logical_1_conn_thresh_sel registers.  Chips: BB_A0 BB_B0 K2
41444 #define TM_REG_CONN_TIMER_THRESHOLD_1                                                                0x2c04e8UL //Access:RW   DataWidth:0x1a  A threshold value, 1 , for connections, which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_conn_thresh_sel, logical_1_conn_thresh_sel and logical_1_conn_thresh_sel registers.  Chips: BB_A0 BB_B0 K2
41445 #define TM_REG_CONN_TIMER_THRESHOLD_2                                                                0x2c04ecUL //Access:RW   DataWidth:0x1a  A threshold value, 2 , for connections, which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_conn_thresh_sel, logical_1_conn_thresh_sel and logical_1_conn_thresh_sel registers.  Chips: BB_A0 BB_B0 K2
41446 #define TM_REG_TASK_TIMER_THRESHOLD_0                                                                0x2c04f0UL //Access:RW   DataWidth:0x1a  A threshold value, 0 , for tasks, which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_task_thresh_sel, logical_1_task_thresh_sel and logical_1_task_thresh_sel registers.  Chips: BB_A0 BB_B0 K2
41447 #define TM_REG_TASK_TIMER_THRESHOLD_1                                                                0x2c04f4UL //Access:RW   DataWidth:0x1a  A threshold value, 1 , for tasks which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_task_thresh_sel, logical_1_task_thresh_sel and logical_1_task_thresh_sel registers.  Chips: BB_A0 BB_B0 K2
41448 #define TM_REG_TASK_TIMER_THRESHOLD_2                                                                0x2c04f8UL //Access:RW   DataWidth:0x1a  A threshold value, 2 , for taskss which is used on decision on whether to send a write command to the host or postpone the write command to later stage. This threshold is selected by the logical_0_task_thresh_sel, logical_1_task_thresh_sel and logical_1_task_thresh_sel registers.  Chips: BB_A0 BB_B0 K2
41449 #define TM_REG_PF_SCAN_ACTIVE_CONN                                                                   0x2c04fcUL //Access:R    DataWidth:0x1   Indicates if the PF connection is active, ie if it is during the scan process. When =1, the PF connection is active. When =0, the PF connection is not active.  Chips: BB_A0 BB_B0 K2
41450 #define TM_REG_PF_SCAN_ACTIVE_TASK                                                                   0x2c0500UL //Access:R    DataWidth:0x4   Indicates if the PF task is active, ie if it is during the scan process. Bit 0 is for segment 0, bit 1 is for segment 1, bit 2 is for segment 2 and bit 3 is for segment 3. When =1, the PF task segment is active. When =0, the PF task segment is not active.  Chips: BB_A0 BB_B0 K2
41451 #define TM_REG_VF_SCAN_ACTIVE_CONN                                                                   0x2c0504UL //Access:R    DataWidth:0x1   Indicates if the VF connection is active, ie if it is during the scan process. When =1, the VF connection is active. When =0, the VF connection is not active.  Chips: BB_A0 BB_B0 K2
41452 #define TM_REG_VF_SCAN_ACTIVE_TASK                                                                   0x2c0508UL //Access:R    DataWidth:0x1   Indicates if the VF task is active, ie if it is during the scan process. When =1, the VF task is active. When =0, the VF task is not active.  Chips: BB_A0 BB_B0 K2
41453 #define TM_REG_DURING_SCAN_CONN                                                                      0x2c050cUL //Access:R    DataWidth:0x1   Indicates if the block is during the connections scan process. When =1, the block is during the connections scan process. When =0, the block is not during the connections scan process.  Chips: BB_A0 BB_B0 K2
41454 #define TM_REG_DURING_SCAN_TASK                                                                      0x2c0510UL //Access:R    DataWidth:0x1   Indicates if the block is during the tasks scan process. When =1, the block is during the tasks scan process. When =0, the block is not during the tasks scan process.  Chips: BB_A0 BB_B0 K2
41455 #define TM_REG_DURING_SCAN                                                                           0x2c0514UL //Access:R    DataWidth:0x1   Indicates if the block is during the tasks or connections scan process. When =1, the block is during the tasks or connections scan process. When =0, the block is not during the tasks or connections scan process.  Chips: BB_A0 BB_B0 K2
41456 #define TM_REG_COMPLETED_SCANS                                                                       0x2c0600UL //Access:R    DataWidth:0x20  Number of completed scans. Incremented if connection scan is completed or if task scan is completed. The counter wraparound, and is not reset when read.  Chips: BB_A0 BB_B0 K2
41457 #define TM_REG_SCAN_PULSE_PRIOR_SCAN_COMPLETED                                                       0x2c0604UL //Access:RC   DataWidth:0x20  Number of scan pulses that arrived before the compatible scan was completed or even started.                          Incremented if task pulse arrived before the previous task scan was completed or even started or                           if connection pulse arrived before the previous connection scan was completed or even started.  Chips: BB_A0 BB_B0 K2
41458 #define TM_REG_SET_COMMANDS_RCV_ON_PBF                                                               0x2c0608UL //Access:R    DataWidth:0x20  Number of SET commands received on the client in PBF interface.  Chips: BB_A0 BB_B0 K2
41459 #define TM_REG_CLEAR_COMMANDS_RCV_ON_PBF                                                             0x2c060cUL //Access:R    DataWidth:0x20  Number of CLEAR commands received on the client in PBF interface.  Chips: BB_A0 BB_B0 K2
41460 #define TM_REG_FORCE_CLEAR_COMMANDS_RCV_ON_PBF                                                       0x2c0610UL //Access:R    DataWidth:0x20  Number of FORCE CLEAR commands received on the client in PBF interface.  Chips: BB_A0 BB_B0 K2
41461 #define TM_REG_INIT_COMMANDS_RCV_ON_PBF                                                              0x2c0614UL //Access:R    DataWidth:0x20  Number of INIT commands received on the client in PBF interface.  Chips: BB_A0 BB_B0 K2
41462 #define TM_REG_STOP_ALL_COMMANDS_RCV_ON_PBF                                                          0x2c0618UL //Access:R    DataWidth:0x20  Number of STOP ALL commands received on the client in PBF interface.  Chips: BB_A0 BB_B0 K2
41463 #define TM_REG_SET_COMMANDS_RCV_ON_TCM                                                               0x2c061cUL //Access:R    DataWidth:0x20  Number of SET commands received on the client in TCM interface.  Chips: BB_A0 BB_B0 K2
41464 #define TM_REG_CLEAR_COMMANDS_RCV_ON_TCM                                                             0x2c0620UL //Access:R    DataWidth:0x20  Number of CLEAR commands received on the client in TCM interface.  Chips: BB_A0 BB_B0 K2
41465 #define TM_REG_FORCE_CLEAR_COMMANDS_RCV_ON_TCM                                                       0x2c0624UL //Access:R    DataWidth:0x20  Number of FORCE CLEAR commands received on the client in TCM interface.  Chips: BB_A0 BB_B0 K2
41466 #define TM_REG_INIT_COMMANDS_RCV_ON_TCM                                                              0x2c0628UL //Access:R    DataWidth:0x20  Number of INIT commands received on the client in TCM interface.  Chips: BB_A0 BB_B0 K2
41467 #define TM_REG_STOP_ALL_COMMANDS_RCV_ON_TCM                                                          0x2c062cUL //Access:R    DataWidth:0x20  Number of STOP ALL commands received on the client in TCM interface.  Chips: BB_A0 BB_B0 K2
41468 #define TM_REG_SET_COMMANDS_RCV_ON_UCM                                                               0x2c0630UL //Access:R    DataWidth:0x20  Number of SET commands received on the client in UCM interface.  Chips: BB_A0 BB_B0 K2
41469 #define TM_REG_CLEAR_COMMANDS_RCV_ON_UCM                                                             0x2c0634UL //Access:R    DataWidth:0x20  Number of CLEAR commands received on the client in UCM interface.  Chips: BB_A0 BB_B0 K2
41470 #define TM_REG_FORCE_CLEAR_COMMANDS_RCV_ON_UCM                                                       0x2c0638UL //Access:R    DataWidth:0x20  Number of FORCE CLEAR commands received on the client in UCM interface.  Chips: BB_A0 BB_B0 K2
41471 #define TM_REG_INIT_COMMANDS_RCV_ON_UCM                                                              0x2c063cUL //Access:R    DataWidth:0x20  Number of INIT commands received on the client in UCM interface.  Chips: BB_A0 BB_B0 K2
41472 #define TM_REG_STOP_ALL_COMMANDS_RCV_ON_UCM                                                          0x2c0640UL //Access:R    DataWidth:0x20  Number of STOP ALL commands received on the client in UCM interface.  Chips: BB_A0 BB_B0 K2
41473 #define TM_REG_SET_COMMANDS_RCV_ON_XCM                                                               0x2c0644UL //Access:R    DataWidth:0x20  Number of SET commands received on the client in XCM interface.  Chips: BB_A0 BB_B0 K2
41474 #define TM_REG_CLEAR_COMMANDS_RCV_ON_XCM                                                             0x2c0648UL //Access:R    DataWidth:0x20  Number of CLEAR commands received on the client in XCM interface.  Chips: BB_A0 BB_B0 K2
41475 #define TM_REG_FORCE_CLEAR_COMMANDS_RCV_ON_XCM                                                       0x2c064cUL //Access:R    DataWidth:0x20  Number of FORCE CLEAR commands received on the client in XCM interface.  Chips: BB_A0 BB_B0 K2
41476 #define TM_REG_INIT_COMMANDS_RCV_ON_XCM                                                              0x2c0650UL //Access:R    DataWidth:0x20  Number of INIT commands received on the client in XCM interface.  Chips: BB_A0 BB_B0 K2
41477 #define TM_REG_STOP_ALL_COMMANDS_RCV_ON_XCM                                                          0x2c0654UL //Access:R    DataWidth:0x20  Number of STOP ALL commands received on the client in XCM interface.  Chips: BB_A0 BB_B0 K2
41478 #define TM_REG_FALSE_EXPIRATIONS                                                                     0x2c0658UL //Access:RC   DataWidth:0x20  Number of false expirations.  Chips: BB_A0 BB_B0 K2
41479 #define TM_REG_EXPIRATIONS                                                                           0x2c065cUL //Access:RC   DataWidth:0x20  Number of expirations (including stop all expirations).  Chips: BB_A0 BB_B0 K2
41480 #define TM_REG_COMMANDS_SENT_TO_HOST                                                                 0x2c0660UL //Access:RC   DataWidth:0x20  Number of commands (write requests) sent to host (set, clear, stop all)  Chips: BB_A0 BB_B0 K2
41481 #define TM_REG_LOAD_RESP_LOADERR_CONN                                                                0x2c0664UL //Access:RC   DataWidth:0x10  Number of load responses with loaderr asserted on the CCFC interface (connections).  Chips: BB_A0 BB_B0 K2
41482 #define TM_REG_LOAD_RESP_LOADCANCEL_CONN                                                             0x2c0668UL //Access:RC   DataWidth:0x10  Number of load responses with loadcancel asserted on the CCFC interface (connections).  Chips: BB_A0 BB_B0 K2
41483 #define TM_REG_LOAD_RESP_LOADERR_TASK                                                                0x2c066cUL //Access:RC   DataWidth:0x10  Number of load responses with loaderr asserted on the CCFC interface (tasks).  Chips: BB_A0 BB_B0 K2
41484 #define TM_REG_LOAD_RESP_LOADCANCEL_TASK                                                             0x2c0670UL //Access:RC   DataWidth:0x10  Number of load responses with loadcancel asserted on the CCFC interface (tasks).  Chips: BB_A0 BB_B0 K2
41485 #define TM_REG_RD_REQUESTS_SENT_TO_HOST                                                              0x2c0674UL //Access:RC   DataWidth:0x20  Number of read requests (scan) sent to host.  Chips: BB_A0 BB_B0 K2
41486 #define TM_REG_PXP_READ_DATA_ERROR                                                                   0x2c0678UL //Access:RC   DataWidth:0x8   Number of PXP read data packets received with ERROR (on the EOP cycle)  Chips: BB_A0 BB_B0 K2
41487 #define TM_REG_CURRENT_TIME                                                                          0x2c0700UL //Access:R    DataWidth:0x1c  The real time clock, incremented every ticks (tick_timer).  Chips: BB_A0 BB_B0 K2
41488 #define TM_REG_CONNECTIONS_SCAN_TIMER                                                                0x2c0704UL //Access:R    DataWidth:0x14  Connections scan timer, counts number of ticks (tick_timer) that generates a connection scan pulse, an indication to scan the connections timers.  Chips: BB_A0 BB_B0 K2
41489 #define TM_REG_TASKS_SCAN_TIMER                                                                      0x2c0708UL //Access:R    DataWidth:0x14  Tasks scan timer, counts number of ticks (tick_timer) that generates a task scan pulse, an indication to scan the tasks timers.  Chips: BB_A0 BB_B0 K2
41490 #define TM_REG_PXP_READ_DATA_FIFO_FULL                                                               0x2c070cUL //Access:R    DataWidth:0x1   When set indicates that the PXP READ DATA FIFO is full.  Chips: BB_A0 BB_B0 K2
41491 #define TM_REG_PXP_READ_DATA_FIFO_STATUS                                                             0x2c0710UL //Access:R    DataWidth:0x6   Indicates the status of the PXP READ DATA FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41492 #define TM_REG_PXP_READ_CTRL_FIFO_FULL                                                               0x2c0714UL //Access:R    DataWidth:0x1   When set indicates that the PXP READ CTRL FIFO is full.  Chips: BB_A0 BB_B0 K2
41493 #define TM_REG_PXP_READ_CTRL_FIFO_STATUS                                                             0x2c0718UL //Access:R    DataWidth:0x4   Indicates the status of the PXP READ CTRL FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41494 #define TM_REG_CFC_LOAD_COMMAND_FIFO_STATUS                                                          0x2c071cUL //Access:R    DataWidth:0x5   Indicates the status of the CFC LOAD COMMAND FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41495 #define TM_REG_CFC_LOAD_ECHO_FIFO_STATUS                                                             0x2c0720UL //Access:R    DataWidth:0x5   Indicates the status of the CFC LOAD ECHO FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41496 #define TM_REG_CLIENT_OUT_FIFO_STATUS                                                                0x2c0724UL //Access:R    DataWidth:0x4   Indicates the status of the CLIENT IN PBF FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41497 #define TM_REG_CLIENT_IN_PBF_FIFO_STATUS                                                             0x2c0728UL //Access:R    DataWidth:0x3   Indicates the status of the CLIENT In PBF FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41498 #define TM_REG_CLIENT_IN_XCM_FIFO_STATUS                                                             0x2c072cUL //Access:R    DataWidth:0x3   Indicates the status of the CLIENT IN XCM FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41499 #define TM_REG_CLIENT_IN_TCM_FIFO_STATUS                                                             0x2c0730UL //Access:R    DataWidth:0x3   Indicates the status of the CLIENT IN TCM FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41500 #define TM_REG_CLIENT_IN_UCM_FIFO_STATUS                                                             0x2c0734UL //Access:R    DataWidth:0x3   Indicates the status of the CLIENT IN UCM FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41501 #define TM_REG_EXPIRATION_CMD_FIFO_STATUS                                                            0x2c0738UL //Access:R    DataWidth:0x4   Indicates the status of the EXPIRATION COMMAND FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41502 #define TM_REG_AC_COMMAND_FIFO_STATUS                                                                0x2c073cUL //Access:R    DataWidth:0x4   Indicates the status of the AC COMMAND FIFO, number of rows filled with data.  Chips: BB_A0 BB_B0 K2
41503 #define TM_REG_DEBUG_0_ERROR_TYPE_EN                                                                 0x2c0740UL //Access:RW   DataWidth:0x8   If the error type is enabled, if the error took place, the errored command data is kept in the debug_0 registers: Bit [0]: if = 1,  the following error is enabled: STOP_ALL_TIMERS command and the logical client is invalid, Bit [1]: if = 1,  the following error is enabled: SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical client is valid, Bit [2]: if = 1,  the following error is enabled: SET/CLEAR/FORCE CLEAR command and the logical client invalid and the other logical client are also invalid, Bit [3]: if = 1,  the following error is enabled: INIT command and the logical client valid bit is asserted, Bit [4]: if = 1,  the following error is enabled: stop all expiration and the valid of one of the logical clients is asserted, Bit [5]: if = 1,  the following error is enabled: command with C/TID > 64K or VF TID segment not zero, Bit [6]: if = 1,  the following error is enabled: RESERVED command, Bit [7]: if = 1,  the following error is enabled: command arrived to the host handler unit with CID/TID > Num_of_timers for that function.  Chips: BB_A0 BB_B0 K2
41504 #define TM_REG_DEBUG_0_FID_EN                                                                        0x2c0744UL //Access:RW   DataWidth:0x1   If enabled, if the error took place, only a command with error for the fid in the register debug_0_fid_mask is kept in the debug_0 registers.  Chips: BB_A0 BB_B0 K2
41505 #define TM_REG_DEBUG_0_FID_MASK                                                                      0x2c0748UL //Access:RW   DataWidth:0x10  If debug_0_fid_en is enabled, if the error took place, only a command with error for the fid identical to this regsiter is kept in the debug_0 registers. The fid structure is the opaque fid.  Chips: BB_A0 BB_B0 K2
41506 #define TM_REG_DEBUG_0_SOURCE_EN                                                                     0x2c074cUL //Access:RW   DataWidth:0x1   If enabled, if the error took place, only a command with error from the source in the register debug_0_source_mask is kept in the debug_0 registers.  Chips: BB_A0 BB_B0 K2
41507 #define TM_REG_DEBUG_0_SOURCE_MASK                                                                   0x2c0750UL //Access:RW   DataWidth:0x3   If debug_0_source_en is enabled, if the error took place, only a command with error for the source identical to this regsiter is kept in the debug_0 registers. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved, 6 - reserved, 7 - reserved.  Chips: BB_A0 BB_B0 K2
41508 #define TM_REG_DEBUG_0_ERROR_VALID                                                                   0x2c0754UL //Access:RW   DataWidth:0x1   When asserted, = 1, indicates that the debug_0 registers contain valid data. Asserted by the hardware, de-asserted by the SW.  Chips: BB_A0 BB_B0 K2
41509 #define TM_REG_DEBUG_0_CID                                                                           0x2c0758UL //Access:R    DataWidth:0x20  The CID for the errored command.  Chips: BB_A0 BB_B0 K2
41510 #define TM_REG_DEBUG_0_LCID                                                                          0x2c075cUL //Access:R    DataWidth:0x9   The LCID for the errored command.  Chips: BB_A0 BB_B0 K2
41511 #define TM_REG_DEBUG_0_DONT_DEC_AC                                                                   0x2c0760UL //Access:R    DataWidth:0x1   The Dont Dec AC field for the errored command.  Chips: BB_A0 BB_B0 K2
41512 #define TM_REG_DEBUG_0_COMMAND                                                                       0x2c0764UL //Access:R    DataWidth:0x3   The Command field for the errored command: 0 - SET TIMER, 1 - CLEAR TIMER, 2 - STOP ALL TIMERS, 3 - INIT, 4 - FORCE CLEAR TIMER,  5 - reserved, 6 - reservd, 7 -reservd, 1 - EXPIRATION (if SOURCE = EXPIRATION), 2 - STOP ALL EXPIRATION (if SOURCE = EXPIRATION).  Chips: BB_A0 BB_B0 K2
41513 #define TM_REG_DEBUG_0_LOG_CLIENT_NUM                                                                0x2c0768UL //Access:R    DataWidth:0x2   The Logical Client for the errored command.  Chips: BB_A0 BB_B0 K2
41514 #define TM_REG_DEBUG_0_TYPE                                                                          0x2c076cUL //Access:R    DataWidth:0x3   The TYPE field for the errored command.  Chips: BB_A0 BB_B0 K2
41515 #define TM_REG_DEBUG_0_LEADER_TYPE                                                                   0x2c0770UL //Access:R    DataWidth:0x1   The Leader Type field for the errored command: 0 - connection, 1 - task.  Chips: BB_A0 BB_B0 K2
41516 #define TM_REG_DEBUG_0_SOURCE                                                                        0x2c0774UL //Access:R    DataWidth:0x3   The Source for the errored command. The source: 0 - PBF, 1 -TCM, 2- UCM, 3 - XCM, 4 - expiration, 5 - reserved, 6 - reserved, 7 - reserved.  Chips: BB_A0 BB_B0 K2
41517 #define TM_REG_DEBUG_0_CONTEXT_STATUS                                                                0x2c0778UL //Access:R    DataWidth:0x6   The Context Status for the errored command: Bit 0: logical client 0 valid bit, Bit 1: logical client 0 active bit, Bit 2: logical client 1 valid bit, Bit 3: logical client 1 active bit, Bit 4: logical client 2 valid bit, Bit 5: logical client 2 active bit. This status information doesnt exist for the error: command arrived to the host handler unit with CID/TID > Num_of_timers for that function.  Chips: BB_A0 BB_B0 K2
41518 #define TM_REG_DEBUG_0_ERROR_TYPE                                                                    0x2c077cUL //Access:R    DataWidth:0x8   The error type: Bit [0]: if = 1,  the following error happened: STOP_ALL_TIMERS command and the logical client is invalid, Bit [1]: if = 1,  the following error happened: SET/CLEAR/FORCE CLEAR command and the logical client invalid and one of the other logical client is valid, Bit [2]: if = 1,  the following error is happened: SET/CLEAR/FORCE CLEAR command and the logical client invalid and the other logical client are also invalid, Bit [3]: if = 1,  the following error happened: INIT command and the logical client valid bit is asserted, Bit [4]: if = 1,  the following error happened: stop all expiration and the valid of one of the logical clients is asserted, Bit [5]: if = 1,  the following error happened: command with C/TID > 64K or VF TID segment not zero, Bit [6]: if = 1,  the following error happened: RESERVED command, Bit [7]: if = 1,  the following error happened: command arrived to the host handler unit with CID/TID > Num_of_timers for that function.  Chips: BB_A0 BB_B0 K2
41519 #define TM_REG_DEBUG_1_ERROR_VALID                                                                   0x2c0780UL //Access:RW   DataWidth:0x1   When asserted, = 1, indicates that the debug_1 registers contain valid data. Asserted by the hardware, de-asserted by the SW.  Chips: BB_A0 BB_B0 K2
41520 #define TM_REG_DEBUG_1_CID                                                                           0x2c0784UL //Access:R    DataWidth:0x20  The CID for the errored load response.  Chips: BB_A0 BB_B0 K2
41521 #define TM_REG_DEBUG_1                                                                               0x2c0788UL //Access:R    DataWidth:0x13  The load response with error fields: Bits 8-0: LCID, Bit 9: scan type (0 - connection, 1 - task), Bits 12-10: type, Bit 13: Load Error Task, Bit 14: Load Cancel Task, Bit 15: Valid Error Task, Bit 16: Load Error Connection, Bit 17: Load Cancel Connection, Bit 15: Valid Error Connection.  Chips: BB_A0 BB_B0 K2
41522 #define TM_REG_DEBUG_2_ERROR_VALID                                                                   0x2c078cUL //Access:RW   DataWidth:0x1   When asserted, = 1, indicates that the debug_2 registers contain valid data. Asserted by the hardware, de-asserted by the SW.  Chips: BB_A0 BB_B0 K2
41523 #define TM_REG_DEBUG_2                                                                               0x2c0790UL //Access:R    DataWidth:0xb   The CDU context read with last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 10: asserted if Last indication is de-asserted.  Chips: BB_A0 BB_B0 K2
41524 #define TM_REG_DEBUG_3_ERROR_VALID                                                                   0x2c0794UL //Access:RW   DataWidth:0x1   When asserted, = 1, indicates that the debug_3 registers contain valid data. Asserted by the hardware, de-asserted by the SW.  Chips: BB_A0 BB_B0 K2
41525 #define TM_REG_DEBUG_3                                                                               0x2c0798UL //Access:R    DataWidth:0xd   The CDU context write with last indication de-asserted fields: Bits 8-0: LCID, Bit 9: Type (0 - connection, 1 - task), Bit 11-10: Qward Valid, Bit 12: asserted if Last indication is de-asserted.  Chips: BB_A0 BB_B0 K2
41526 #define TM_REG_FSMS_STATES                                                                           0x2c079cUL //Access:R    DataWidth:0x1b  The current states of the block FSMs:                          Bits 2-0: cmd_handler.                          Bit 3: reserved.                          Bits 7-4: write_timer.                          Bits 9-8: read_fifo.                          Bits 11-10: reserved.                          Bits 14-12: scan.                          Bits 15: reserved.                          Bits 19-16: rd_scan_rate.                          Bits 22-20: expiration.                          Bits 23: reserved.                          Bits 26-24: update_prescan_mem.  Chips: BB_A0 BB_B0 K2
41527 #define TM_REG_DEBUG_4_ERROR_VALID                                                                   0x2c07a0UL //Access:RW   DataWidth:0x1   When asserted, = 1, indicates that the debug_4 registers contain valid data. Asserted by the hardware, de-asserted by the SW.  Chips: BB_A0 BB_B0 K2
41528 #define TM_REG_DEBUG_4                                                                               0x2c07a4UL //Access:R    DataWidth:0x16  The PXP read data is received with an error or with bvalid != 0. The parameters for the errored data:                    Bits 7-0: function # (0-119 VFs, 120 and above PFs / segments) . Bit 8: type (0 - connection, 1 - task). Bits 12-9: group. Bit 21-13: relative row (16 groups in a row).  Chips: BB_A0 BB_B0 K2
41529 #define TM_REG_DBG_SELECT                                                                            0x2c07a8UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
41530 #define TM_REG_DBG_DWORD_ENABLE                                                                      0x2c07acUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
41531 #define TM_REG_DBG_SHIFT                                                                             0x2c07b0UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
41532 #define TM_REG_DBG_FORCE_VALID                                                                       0x2c07b4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
41533 #define TM_REG_DBG_FORCE_FRAME                                                                       0x2c07b8UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
41534 #define TM_REG_DBG_OUT_DATA                                                                          0x2c07c0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
41535 #define TM_REG_DBG_OUT_DATA_SIZE                                                                     8
41536 #define TM_REG_DBG_OUT_VALID                                                                         0x2c07e0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
41537 #define TM_REG_DBG_OUT_FRAME                                                                         0x2c07e4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
41538 #define TM_REG_CONFIG_CONN_MEM                                                                       0x2c1000UL //Access:WB   DataWidth:0x27  Configuration memory for the connections. Each row contains the configuration for the compatible function. Rows 0 to 191 are for VFs 0 to 191: row 0 for VF 0, row 1 for VF1, row 2 for VF 2, etc. Rows 192 to 207 are for the PFs: row 192 for PF 0, row 193 for PF 1, row 194 for PF 2, etc. The fields are: bits [15:0] - number of connections, the value should be multiplies of group_size_resolution_conn register (for example, if group_size_resolution_conn = 0, 128 timers, the number of connections can be 128, 256, 384, etc.), bits [25:16] - the start offset in the pre-scan memory,for BB only 9 bits are applicable. bits [29:26] - the parent PF (applicable if VF, NA if PF), for BB only 3 bits are applicable. bits [38:30] - number of rows allocated for the function in the pre-scan memory. If = 0, all the timers that belong to the function are scanned.  Chips: BB_A0 BB_B0 K2
41539 #define TM_REG_CONFIG_CONN_MEM_SIZE                                                                  416
41540 #define TM_REG_CONFIG_TASK_MEM                                                                       0x2c2000UL //Access:WB   DataWidth:0x3a  Configuration memory for the tasks. Each row contains the configuration for the compatible function. Rows 0 to 191 are for VFs 0 to 191: row 0 for VF 0, row 1 for VF1, row 2 for VF 2, etc. Rows 192 to 255 are for the PFs segments: row 192 for PF 0 segment 0, row 193 for PF 0 segment 1, row 194 for PF 0 segment 2, row 195 for PF 0 segment 3, row 196 for PF1 segment 0, row 197 for PF1 segment 1, etc. The fields are: bits [15:0] - number of tasks, the value should be multiplies of group_size_resolution_task register (for example, if group_size_resolution_task = 0, 128 timers, the number of tasks can be 128, 256, 384, etc.), bits [25:16] - the start offset in the pre-scan memory, for BB only 9 bits are applicable. bits [29:26] - the parent PF (applicable if VF, NA if PF), for BB only 3 bits are applicable. bits [48:30] - the pci base offset address in 32 bits resolution (all 19 bits are applicable if PF, only the first 17 bits are applicable if VF). bits [57:49] - number of rows allocated for the function in the pre-scan memory. If = 0, all the timers that belong to the function are scanned.  Chips: BB_A0 BB_B0 K2
41541 #define TM_REG_CONFIG_TASK_MEM_SIZE                                                                  512
41542 #define TM_REG_PRE_SCAN_MEM                                                                          0x2c4000UL //Access:RW   DataWidth:0x20  Pre scan memory which contains the scan rate fields for each group. Each row contains scan rate field (2 bits) per group, for 16 groups. The first 512 rows contain the scan rate fields for connections, the last 512 rows contain the scan rate fields for tasks. TBD - describe the fields.  Chips: BB_A0 BB_B0 K2
41543 #define TM_REG_PRE_SCAN_MEM_SIZE                                                                     2048
41544 #define TM_REG_CONTEXT_MEM                                                                           0x2c8000UL //Access:WB   DataWidth:0x77  Context memory for connections and tasks. 320 LCIDs for connections and 320 LTIDs for tasks. The addresses are interleaved between connections and tasks. If address [0] = 0, it is LCID (connections), if address [0] = 1, it is LTID (tasks). Previous name: context_ram0.  Chips: BB_A0 BB_B0 K2
41545 #define TM_REG_CONTEXT_MEM_SIZE                                                                      2560
41546 #define TCFC_REG_INIT_REG                                                                            0x2d0000UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41547     #define TCFC_REG_INIT_REG_AC_INIT                                                                (0x1<<0) // When set activity counter ram will be initialized to zeros. when this operation is completed CFC_REGISTERS_AC_INITDONE.AC_INIT_DONE will be set.
41548     #define TCFC_REG_INIT_REG_AC_INIT_SHIFT                                                          0
41549     #define TCFC_REG_INIT_REG_LL_INIT_LAST_LCID                                                      (0x1ff<<1) // This field is only relevant when setting CFC_REGISTERS_INIT_REG.LL_INIT . indicates the last lcid to be used by the CFC. this field can strict the CFC to work will less than 320 LCIDs.
41550     #define TCFC_REG_INIT_REG_LL_INIT_LAST_LCID_SHIFT                                                1
41551     #define TCFC_REG_INIT_REG_LL_INIT                                                                (0x1<<10) // When set link list ram will be initialized - all LCIDs will be located in the empty link list. when this operation completes CFC_REGISTERS_LL_INITDONE.LL_INIT_DONE will be set.
41552     #define TCFC_REG_INIT_REG_LL_INIT_SHIFT                                                          10
41553     #define TCFC_REG_INIT_REG_CAM_INIT                                                               (0x1<<11) // When set the CFC CAMs will be initialized to zeros. When this operation completes CFC_REGISTERS_CAM_INITDONE.CAM_INIT_DONE will be set.
41554     #define TCFC_REG_INIT_REG_CAM_INIT_SHIFT                                                         11
41555     #define TCFC_REG_INIT_REG_TIDRAM_INIT                                                            (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be idle or the request will be ignored. When this operation completes CFC_REGISTERS_TIDRAM_INITDONE.TIDRAM_INIT_DONE will be set.
41556     #define TCFC_REG_INIT_REG_TIDRAM_INIT_SHIFT                                                      12
41557 #define TCFC_REG_LL_INIT_DONE                                                                        0x2d0004UL //Access:R    DataWidth:0x1   Indication the initializing the link list by the hardware was done.  Chips: BB_A0 BB_B0 K2
41558 #define TCFC_REG_AC_INIT_DONE                                                                        0x2d0008UL //Access:R    DataWidth:0x1   Indication the initializing the activity counter by the hardware was done.  Chips: BB_A0 BB_B0 K2
41559 #define TCFC_REG_CAM_INIT_DONE                                                                       0x2d000cUL //Access:R    DataWidth:0x1   Indication that initializing the cams by the hardware was done.  Chips: BB_A0 BB_B0 K2
41560 #define TCFC_REG_TIDRAM_INIT_DONE                                                                    0x2d0010UL //Access:R    DataWidth:0x1   Indication that initializing the TID Lock RAM by the hardware was done.  Chips: BB_A0 BB_B0 K2
41561 #define TCFC_REG_INT_STS_0                                                                           0x2d0180UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41562     #define TCFC_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
41563     #define TCFC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
41564     #define TCFC_REG_INT_STS_0_EXE_ERROR                                                             (0x1<<1) // Interrupt indicating that an execution error has occurred.
41565     #define TCFC_REG_INT_STS_0_EXE_ERROR_SHIFT                                                       1
41566 #define TCFC_REG_INT_MASK_0                                                                          0x2d0184UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41567     #define TCFC_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: TCFC_REG_INT_STS_0.ADDRESS_ERROR .
41568     #define TCFC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
41569     #define TCFC_REG_INT_MASK_0_EXE_ERROR                                                            (0x1<<1) // This bit masks, when set, the Interrupt bit: TCFC_REG_INT_STS_0.EXE_ERROR .
41570     #define TCFC_REG_INT_MASK_0_EXE_ERROR_SHIFT                                                      1
41571 #define TCFC_REG_INT_STS_WR_0                                                                        0x2d0188UL //Access:WR   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41572     #define TCFC_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
41573     #define TCFC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
41574     #define TCFC_REG_INT_STS_WR_0_EXE_ERROR                                                          (0x1<<1) // Interrupt indicating that an execution error has occurred.
41575     #define TCFC_REG_INT_STS_WR_0_EXE_ERROR_SHIFT                                                    1
41576 #define TCFC_REG_INT_STS_CLR_0                                                                       0x2d018cUL //Access:RC   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41577     #define TCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
41578     #define TCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
41579     #define TCFC_REG_INT_STS_CLR_0_EXE_ERROR                                                         (0x1<<1) // Interrupt indicating that an execution error has occurred.
41580     #define TCFC_REG_INT_STS_CLR_0_EXE_ERROR_SHIFT                                                   1
41581 #define TCFC_REG_PRTY_MASK_H_0                                                                       0x2d0204UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41582     #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0                                           (0x1<<2) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
41583     #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                     2
41584     #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0                                           (0x1<<0) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
41585     #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                     0
41586     #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                              (0x1<<0) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
41587     #define TCFC_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                        0
41588     #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_A0                                           (0x1<<3) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
41589     #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_A0_SHIFT                                     3
41590     #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_B0                                           (0x1<<1) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
41591     #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                     1
41592     #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2                                              (0x1<<1) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
41593     #define TCFC_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_SHIFT                                        1
41594     #define TCFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
41595     #define TCFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           0
41596     #define TCFC_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
41597     #define TCFC_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           1
41598 #define TCFC_REG_MEM_ECC_EVENTS                                                                      0x2d0210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
41599 #define TCFC_REG_MEM003_I_ESILICON_TCAM_DFT_K2                                                       0x2d0218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcfc.i_cfc_core.i_cfc_cid_cam.i_cam.i_esilicon_tcam of module ts_28hpc_tcam_111_hs_e_t_shlas_320x33_pbn_bist_wr. [2]=rme, [1:0]=t_strw.  Chips: K2
41600 #define TCFC_REG_MEM004_I_MEM_DFT_K2                                                                 0x2d021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcfc.i_cfc_core.i_lc_que_ram.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
41601 #define TCFC_REG_MEM002_I_MEM_DFT_K2                                                                 0x2d0220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcfc.i_cfc_core.i_ac_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
41602 #define TCFC_REG_MEM001_I_MEM_DFT_K2                                                                 0x2d0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcfc.i_cfc_core.TCFC_LTID_LOCK_GEN_IF.u_cfc_tid_lock_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
41603 #define TCFC_REG_LC_BLOCKED                                                                          0x2d0400UL //Access:RC   DataWidth:0x20  Statistics register that counts cycles in which load context requests were blocked.  Chips: BB_A0 BB_B0 K2
41604 #define TCFC_REG_TID_LOCK_INC_STAT                                                                   0x2d0404UL //Access:RC   DataWidth:0x20  This statistic counts the number of cycles in which a Primary Lock condition exists when it was caused by an Increment command on a previously locked LTID. Note that this counts the number of cycles in which this condition exists, not the number of times it occurred.  Chips: BB_A0 BB_B0 K2
41605 #define TCFC_REG_TID_LOCK_LOCK_STAT                                                                  0x2d0408UL //Access:RC   DataWidth:0x20  This statistic counts the number of cycles in which a Primary Lock condition exists when it was caused by an Lock command on a previously locked LTID. Note that this counts the number of cycles in which this condition exists, not the number of times it occurred.  Chips: BB_A0 BB_B0 K2
41606 #define TCFC_REG_RFE_TASK_COUNTER                                                                    0x2d040cUL //Access:RC   DataWidth:0x20  Counts number of tasks executed by the RFE controller.  Chips: BB_A0 BB_B0 K2
41607 #define TCFC_REG_LC_STAT_MASK                                                                        0x2d0410UL //Access:RW   DataWidth:0xe   Used to mask the various load client queues for LC task statistics.  Chips: BB_A0 BB_B0 K2
41608 #define TCFC_REG_LC_TASK_COUNTER                                                                     0x2d0414UL //Access:RC   DataWidth:0x20  Counts number of tasks executed by the load client controller.  Chips: BB_A0 BB_B0 K2
41609 #define TCFC_REG_MISC_TASK_COUNTER                                                                   0x2d0418UL //Access:RC   DataWidth:0x20  Counts number of tasks executed by the miscellaneous controller.  Chips: BB_A0 BB_B0 K2
41610 #define TCFC_REG_LOAD_CONTEXT_HITS                                                                   0x2d041cUL //Access:RC   DataWidth:0x20  Counts the number of load context hits for the load clients selected by lc_stat_mask.  Chips: BB_A0 BB_B0 K2
41611 #define TCFC_REG_LOAD_CONTEXT_MISSES                                                                 0x2d0420UL //Access:RC   DataWidth:0x20  Counts the number of load context misses for the load clients selected by lc_stat_mask.  Chips: BB_A0 BB_B0 K2
41612 #define TCFC_REG_RFE_SEARCH_HITS                                                                     0x2d0424UL //Access:RC   DataWidth:0x20  Counts the number of RFE serach hits.  Chips: BB_A0 BB_B0 K2
41613 #define TCFC_REG_RFE_SEARCH_MISSES                                                                   0x2d0428UL //Access:RC   DataWidth:0x20  Counts the number of RFE serach misses.  Chips: BB_A0 BB_B0 K2
41614 #define TCFC_REG_CDU_WRITE_BACKS                                                                     0x2d042cUL //Access:RC   DataWidth:0x20  Counts the number of CDU write backs submitted by CFC.  Chips: BB_A0 BB_B0 K2
41615 #define TCFC_REG_DBG_SELECT                                                                          0x2d0500UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
41616 #define TCFC_REG_DBG_DWORD_ENABLE                                                                    0x2d0504UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
41617 #define TCFC_REG_DBG_SHIFT                                                                           0x2d0508UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
41618 #define TCFC_REG_DBG_FORCE_VALID                                                                     0x2d050cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
41619 #define TCFC_REG_DBG_FORCE_FRAME                                                                     0x2d0510UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
41620 #define TCFC_REG_DBG_OUT_DATA                                                                        0x2d0520UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
41621 #define TCFC_REG_DBG_OUT_DATA_SIZE                                                                   8
41622 #define TCFC_REG_DBG_OUT_VALID                                                                       0x2d0540UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
41623 #define TCFC_REG_DBG_OUT_FRAME                                                                       0x2d0544UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
41624 #define TCFC_REG_ECO_RESERVED                                                                        0x2d0548UL //Access:RW   DataWidth:0x8   Eco reserved.  bit0: Chicken bit for CQ73536 fix. When '0' takes into account LCIDs in the pipe. When '1' behaces as A0.  Chips: BB_A0 BB_B0 K2
41625 #define TCFC_REG_ERROR_VECTOR                                                                        0x2d054cUL //Access:R    DataWidth:0x11  CFC error vector. when the CFC detects an internal error it will set one of these bits. the bit description can be found in CFC specifications.  Chips: BB_A0 BB_B0 K2
41626 #define TCFC_REG_ERROR_MASK                                                                          0x2d0550UL //Access:RW   DataWidth:0x11  Masking for error logging. if a bit in this field is set then the corresponding bit in CFC_REGISTERS_CFC_ERROR_VECTOR.ERROR_VECTOR will not be set.  Chips: BB_A0 BB_B0 K2
41627 #define TCFC_REG_DISABLE_ON_ERROR                                                                    0x2d0554UL //Access:RW   DataWidth:0x11  Indicates per error (in CFC_REGISTERS_CFC_ERROR_VECTOR.CFC_ERROR vector) whether the cfc should be disabled upon it.  Chips: BB_A0 BB_B0 K2
41628 #define TCFC_REG_ERROR_DATA1                                                                         0x2d0558UL //Access:R    DataWidth:0x20  When the CFC detects an internal error it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Note that the Error ID starts counting at 0x1 so that there will always be a bit set in the ID.  This means it is always 1 greater than the bit in the error_vector register which caused the error.  See the CFC EAS document for more details.  Chips: BB_A0 BB_B0 K2
41629 #define TCFC_REG_ERROR_DATA2                                                                         0x2d055cUL //Access:R    DataWidth:0x20  When the CFC detects an internal error it updates these fields. [31:00] -- CID  Chips: BB_A0 BB_B0 K2
41630 #define TCFC_REG_ERROR_DATA3                                                                         0x2d0560UL //Access:R    DataWidth:0x20  When the CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active LCID  Chips: BB_A0 BB_B0 K2
41631 #define TCFC_REG_ERROR_DATA4                                                                         0x2d0564UL //Access:R    DataWidth:0x20  When the CFC detects an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00] -- AC LCID  Chips: BB_A0 BB_B0 K2
41632 #define TCFC_REG_ARBITERS_REG                                                                        0x2d0568UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41633     #define TCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB                                                     (0x1<<0) // When set CFC arbiter1 will work in strict priority.
41634     #define TCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB_SHIFT                                               0
41635     #define TCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB                                                      (0x1<<1) // When set load context arbiter will work in strict priority.
41636     #define TCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB_SHIFT                                                1
41637     #define TCFC_REG_ARBITERS_REG_SP_LC_INP_ARB                                                      (0x1<<2) // When set CFC arbiter2 will work in strict priority.
41638     #define TCFC_REG_ARBITERS_REG_SP_LC_INP_ARB_SHIFT                                                2
41639     #define TCFC_REG_ARBITERS_REG_SP_MISC_ARB                                                        (0x1<<3) // When set CFC arbiter3 will work in strict priority.
41640     #define TCFC_REG_ARBITERS_REG_SP_MISC_ARB_SHIFT                                                  3
41641     #define TCFC_REG_ARBITERS_REG_SP_AC_DEC                                                          (0x1<<4) // When set activity counter decrement arbiter will work in strict priority.
41642     #define TCFC_REG_ARBITERS_REG_SP_AC_DEC_SHIFT                                                    4
41643     #define TCFC_REG_ARBITERS_REG_SP_AC_INC                                                          (0x1<<5) // When set activity counter increment arbiter will work in strict priority.
41644     #define TCFC_REG_ARBITERS_REG_SP_AC_INC_SHIFT                                                    5
41645 #define TCFC_REG_LCREQ_WEIGHTS                                                                       0x2d0580UL //Access:RW   DataWidth:0x3   This field allows changing the priorities of the weighted-round-robin arbiter which selects which CFC load client should be served next.  Chips: BB_A0 BB_B0 K2
41646 #define TCFC_REG_LCREQ_WEIGHTS_SIZE                                                                  14
41647 #define TCFC_REG_DEBUG0                                                                              0x2d05c0UL //Access:RW   DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
41648     #define TCFC_REG_DEBUG0_DISABLE_INPUTS                                                           (0x1<<0) // This bit disables the inputs on the CFC.
41649     #define TCFC_REG_DEBUG0_DISABLE_INPUTS_SHIFT                                                     0
41650     #define TCFC_REG_DEBUG0_DISABLE_OUTPUTS                                                          (0x1<<1) // This bit disables the outputs of the CFC.
41651     #define TCFC_REG_DEBUG0_DISABLE_OUTPUTS_SHIFT                                                    1
41652     #define TCFC_REG_DEBUG0_AC_COUNTER_ZERO                                                          (0xff<<2) // Debug only.
41653     #define TCFC_REG_DEBUG0_AC_COUNTER_ZERO_SHIFT                                                    2
41654     #define TCFC_REG_DEBUG0_AC_GRANT_PERIOD                                                          (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep its address.
41655     #define TCFC_REG_DEBUG0_AC_GRANT_PERIOD_SHIFT                                                    10
41656     #define TCFC_REG_DEBUG0_E_THRESHOLD                                                              (0x7<<14) // Debug only.
41657     #define TCFC_REG_DEBUG0_E_THRESHOLD_SHIFT                                                        14
41658     #define TCFC_REG_DEBUG0_INA_THRESHOLD                                                            (0x7<<17) // Debug only.
41659     #define TCFC_REG_DEBUG0_INA_THRESHOLD_SHIFT                                                      17
41660     #define TCFC_REG_DEBUG0_IO_THRESHOLD                                                             (0x7<<20) // Debug only.
41661     #define TCFC_REG_DEBUG0_IO_THRESHOLD_SHIFT                                                       20
41662 #define TCFC_REG_DEBUG1                                                                              0x2d05c4UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41663     #define TCFC_REG_DEBUG1_MARB_THRESHOLD                                                           (0xf<<0) // Debug only.
41664     #define TCFC_REG_DEBUG1_MARB_THRESHOLD_SHIFT                                                     0
41665     #define TCFC_REG_DEBUG1_WRITE_AC                                                                 (0x1<<4) // Debug only.
41666     #define TCFC_REG_DEBUG1_WRITE_AC_SHIFT                                                           4
41667     #define TCFC_REG_DEBUG1_MY_VAL_AC                                                                (0x1<<5) // Debug only.
41668     #define TCFC_REG_DEBUG1_MY_VAL_AC_SHIFT                                                          5
41669     #define TCFC_REG_DEBUG1_WVAL_AC                                                                  (0x3<<6) // Debug only.
41670     #define TCFC_REG_DEBUG1_WVAL_AC_SHIFT                                                            6
41671     #define TCFC_REG_DEBUG1_TYPE_FROM_REQ                                                            (0x1<<8) // Debug only.
41672     #define TCFC_REG_DEBUG1_TYPE_FROM_REQ_SHIFT                                                      8
41673     #define TCFC_REG_DEBUG1_CHECK_DEL_STATE                                                          (0x1<<9) // Debug only.
41674     #define TCFC_REG_DEBUG1_CHECK_DEL_STATE_SHIFT                                                    9
41675     #define TCFC_REG_DEBUG1_SW_RESET                                                                 (0x1<<10) // Debug only.
41676     #define TCFC_REG_DEBUG1_SW_RESET_SHIFT                                                           10
41677     #define TCFC_REG_DEBUG1_EN_ON_INT_CLR                                                            (0x1<<11) // Debug only.
41678     #define TCFC_REG_DEBUG1_EN_ON_INT_CLR_SHIFT                                                      11
41679     #define TCFC_REG_DEBUG1_UPD_CANCEL_DIS                                                           (0x1<<12) // Debug only.
41680     #define TCFC_REG_DEBUG1_UPD_CANCEL_DIS_SHIFT                                                     12
41681 #define TCFC_REG_OPERATION_MASK                                                                      0x2d05c8UL //Access:RW   DataWidth:0x7   Used to mask all various types of requests.  Chips: BB_A0 BB_B0 K2
41682 #define TCFC_REG_CDU_CV_ERR_MASK                                                                     0x2d05ccUL //Access:RW   DataWidth:0x3   Error Masking Bits for CDU Context Validation Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.  Chips: BB_A0 BB_B0 K2
41683 #define TCFC_REG_CDU_AV_ERR_MASK                                                                     0x2d05d0UL //Access:RW   DataWidth:0x3   Error Masking Bits for CDU Active Validation Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.  Chips: BB_A0 BB_B0 K2
41684 #define TCFC_REG_CDU_PCIE_ERR_MASK                                                                   0x2d05d4UL //Access:RW   DataWidth:0x3   Error Masking Bits for CDU PCIE Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.  Chips: BB_A0 BB_B0 K2
41685 #define TCFC_REG_ROBUSTWB_PF                                                                         0x2d05d8UL //Access:RW   DataWidth:0x1   Disable Robust WB change: When an inactivate request is processed do not move the LCID to Inactive state if any of the regions are in error state.  Chips: BB_A0 BB_B0 K2
41686 #define TCFC_REG_SREQ_FULL_STICKY                                                                    0x2d05dcUL //Access:RW   DataWidth:0x1   The Interface to Searcher Request Queue has reached the maximum value (4).  Chips: BB_A0 BB_B0 K2
41687 #define TCFC_REG_PRSRESP_FULL_STICKY                                                                 0x2d05e0UL //Access:RW   DataWidth:0x1   The Interface to Parser Response Queue has reached the maximum value (6).  Chips: BB_A0 BB_B0 K2
41688 #define TCFC_REG_PRTY_MASK                                                                           0x2d05e8UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41689     #define TCFC_REG_PRTY_MASK_CCAM_PAR_ERR                                                          (0x1<<0) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.CCAM_PAR_ERR .
41690     #define TCFC_REG_PRTY_MASK_CCAM_PAR_ERR_SHIFT                                                    0
41691     #define TCFC_REG_PRTY_MASK_SCAM_PAR_ERR                                                          (0x1<<1) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.SCAM_PAR_ERR .
41692     #define TCFC_REG_PRTY_MASK_SCAM_PAR_ERR_SHIFT                                                    1
41693     #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR                                          (0x1<<2) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_LSB_PAR_ERR .
41694     #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR_SHIFT                                    2
41695     #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR                                          (0x1<<3) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_MSB_PAR_ERR .
41696     #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR_SHIFT                                    3
41697     #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR                                          (0x1<<4) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_LSB_PAR_ERR .
41698     #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR_SHIFT                                    4
41699     #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR                                          (0x1<<5) // This bit masks, when set, the Parity bit: TCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_MSB_PAR_ERR .
41700     #define TCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR_SHIFT                                    5
41701 #define TCFC_REG_NUM_LCIDS_EMPTY                                                                     0x2d0600UL //Access:R    DataWidth:0x9   Number of Empty LCIDs in Link List Block (not allocated).  Chips: BB_A0 BB_B0 K2
41702 #define TCFC_REG_NUM_LCIDS_INA                                                                       0x2d0604UL //Access:R    DataWidth:0x9   Number of Inside not active LCIDs in Link List Block.  Chips: BB_A0 BB_B0 K2
41703 #define TCFC_REG_NUM_LCIDS_IO                                                                        0x2d0608UL //Access:R    DataWidth:0x9   Number of inside/outside LCIDs in Link List Block.  Chips: BB_A0 BB_B0 K2
41704 #define TCFC_REG_LSTATE_EMPTY                                                                        0x2d060cUL //Access:R    DataWidth:0x9   Number of LCIDs in the EMPTY state.  Chips: BB_A0 BB_B0 K2
41705 #define TCFC_REG_LSTATE_ARRIVING                                                                     0x2d0610UL //Access:R    DataWidth:0x9   Number of LCIDs in the ARRIVING state.  Chips: BB_A0 BB_B0 K2
41706 #define TCFC_REG_LSTATE_INSIDE                                                                       0x2d0614UL //Access:R    DataWidth:0x9   Number of LCIDs in the INSIDE state.  Chips: BB_A0 BB_B0 K2
41707 #define TCFC_REG_LSTATE_INSIDE_NA                                                                    0x2d0618UL //Access:R    DataWidth:0x9   Number of LCIDs in the INSIDE_NA state.  Chips: BB_A0 BB_B0 K2
41708 #define TCFC_REG_LSTATE_LEAVING                                                                      0x2d061cUL //Access:R    DataWidth:0x9   Number of LCIDs in the LEAVING state.  Chips: BB_A0 BB_B0 K2
41709 #define TCFC_REG_LSTATE_I_AND_O                                                                      0x2d0620UL //Access:R    DataWidth:0x9   Number of LCIDs in the I_AND_O state.  Chips: BB_A0 BB_B0 K2
41710 #define TCFC_REG_LSTATE_BDELETED                                                                     0x2d0624UL //Access:R    DataWidth:0x9   Number of LCIDs in the BDELETED state.  Chips: BB_A0 BB_B0 K2
41711 #define TCFC_REG_MAX_INSIDE                                                                          0x2d0628UL //Access:R    DataWidth:0x9   Reflects the maximum value seen on the lstate_inside counter.  Chips: BB_A0 BB_B0 K2
41712 #define TCFC_REG_WEAK_ENABLE_PF                                                                      0x2d0700UL //Access:RW   DataWidth:0x1   This bit when clear will cause a load-cancel response to a load request for PF and set an execution error. Set processes load requests normally.  Chips: BB_A0 BB_B0 K2
41713 #define TCFC_REG_WEAK_ENABLE_VF                                                                      0x2d0704UL //Access:RW   DataWidth:0x1   This bit when clear will cause a load-cancel response to a load request for VF and set an execution error. Set processes load requests normally.  Chips: BB_A0 BB_B0 K2
41714 #define TCFC_REG_STRONG_ENABLE_PF                                                                    0x2d0708UL //Access:RW   DataWidth:0x1   This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for PF. The PFID that caused the execution error will be stored (exec_error_pf).  Chips: BB_A0 BB_B0 K2
41715 #define TCFC_REG_STRONG_ENABLE_VF                                                                    0x2d070cUL //Access:RW   DataWidth:0x1   This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for VF. The VFID that caused the execution error will be stored (exec_error_pf).  Chips: BB_A0 BB_B0 K2
41716 #define TCFC_REG_LOADRETRY_TYPES                                                                     0x2d0710UL //Access:RW   DataWidth:0x10  LoadRetry Enable Vector, Per Type.  Chips: BB_A0 BB_B0 K2
41717 #define TCFC_REG_MINICACHE_CONTROL                                                                   0x2d0714UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41718     #define TCFC_REG_MINICACHE_CONTROL_EMPTYTHRESHMINICACHE                                          (0x3ff<<0) // The Threshold of EmptyLCIDs which must be in the Empty State to enable the MiniCache in the Load Clients.  If there are less Empty LCIDs than this threshold, the Invalidate MiniCache signal will be asserted to the clients.
41719     #define TCFC_REG_MINICACHE_CONTROL_EMPTYTHRESHMINICACHE_SHIFT                                    0
41720     #define TCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE                                     (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit will prevent the CFC from setting an Attention or hanging when the AC Counter underflows, as long as the Invalidate Minicache for that LC Client is currently asserted.
41721     #define TCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE_SHIFT                               10
41722 #define TCFC_REG_PF_MINICACHE_ENABLE                                                                 0x2d0718UL //Access:RW   DataWidth:0x1   Enables MiniCache in Load Clients.  Chips: BB_A0 BB_B0 K2
41723 #define TCFC_REG_CONTROL0                                                                            0x2d071cUL //Access:RW   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
41724     #define TCFC_REG_CONTROL0_WB_THRESHOLD                                                           (0x1ff<<0) // The threshold of number of free entries for WB. If there are less free entries than the threshold a WB will be initiated.
41725     #define TCFC_REG_CONTROL0_WB_THRESHOLD_SHIFT                                                     0
41726     #define TCFC_REG_CONTROL0_STRING_CAM_DISABLE                                                     (0x1<<9) // When set to 1 the search string caching mechanism is disabled.
41727     #define TCFC_REG_CONTROL0_STRING_CAM_DISABLE_SHIFT                                               9
41728     #define TCFC_REG_CONTROL0_CID_CAM_DISABLE                                                        (0x1<<10) // When set to 1 the cid cam is disabled.
41729     #define TCFC_REG_CONTROL0_CID_CAM_DISABLE_SHIFT                                                  10
41730     #define TCFC_REG_CONTROL0_NLOE                                                                   (0x1<<11) // New Load On Error. if this bit is set and there is a load request region that is in error state then a new load request for that region will be submitted; otherwise an immediate response will be sent to the client with error.
41731     #define TCFC_REG_CONTROL0_NLOE_SHIFT                                                             11
41732     #define TCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN                                                      (0x1<<12) // When set to 1 the string cam hit parity scrubbing feature is enabled.
41733     #define TCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN_SHIFT                                                12
41734     #define TCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN                                                     (0x1<<13) // When set to 1 the string cam miss parity scrubbing feature is enabled.
41735     #define TCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN_SHIFT                                               13
41736     #define TCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN                                                      (0x1<<14) // When set to 1 the cid cam hit parity scrubbing feature is enabled.
41737     #define TCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN_SHIFT                                                14
41738     #define TCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN                                                     (0x1<<15) // When set to 1 the cid cam miss parity scrubbing feature is enabled.
41739     #define TCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN_SHIFT                                               15
41740 #define TCFC_REG_LCREQ_CREDIT                                                                        0x2d0740UL //Access:RW   DataWidth:0x6   Set the initial credit for each of the load clients if less than the max is desired.  Chips: BB_A0 BB_B0 K2
41741 #define TCFC_REG_LCREQ_CREDIT_SIZE                                                                   14
41742 #define TCFC_REG_PRSRESP_CREDIT                                                                      0x2d0780UL //Access:RW   DataWidth:0x5   Set the initial credit for the parser response interface if less than the max is desired.  Chips: BB_A0 BB_B0 K2
41743 #define TCFC_REG_SEARCH_CREDIT                                                                       0x2d0784UL //Access:RW   DataWidth:0x5   Set the initial credit for the searcher interface if less than the max is desired.  Chips: BB_A0 BB_B0 K2
41744 #define TCFC_REG_CDULD_CREDIT                                                                        0x2d0788UL //Access:RW   DataWidth:0x6   Set the initial credit for the CDU load interface if less than the max is desired.  Chips: BB_A0 BB_B0 K2
41745 #define TCFC_REG_CDUWB_CREDIT                                                                        0x2d078cUL //Access:RW   DataWidth:0x6   Set the initial credit for the CDU write-back interface if less than the max is desired.  Chips: BB_A0 BB_B0 K2
41746 #define TCFC_REG_FLOAD_RGN_MSK                                                                       0x2d07a0UL //Access:RW   DataWidth:0x8   Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC.  Chips: BB_A0 BB_B0 K2
41747 #define TCFC_REG_FLOAD_RGN_MSK_SIZE                                                                  8
41748 #define TCFC_REG_LL_POLICY_CFG                                                                       0x2d0800UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41749     #define TCFC_REG_LL_POLICY_CFG_LL_POLICY_IO                                                      (0x3<<0) // This register is used to set the usage policy for the I/O Link List: 00: Pop LCIDs from the Head of the List (FIFO) 01: Pop LCIDs from the Tail of the List (Stack) 10: Alternate between Head and Tail of the List 11: Reserved
41750     #define TCFC_REG_LL_POLICY_CFG_LL_POLICY_IO_SHIFT                                                0
41751     #define TCFC_REG_LL_POLICY_CFG_LL_POLICY_INA                                                     (0x3<<2) // This register is used to set the usage policy for the INA Link List: 00: Pop LCIDs from the Head of the List (FIFO) 01: Pop LCIDs from the Tail of the List (Stack) 10: Alternate between Head and Tail of the List 11: Reserved
41752     #define TCFC_REG_LL_POLICY_CFG_LL_POLICY_INA_SHIFT                                               2
41753 #define TCFC_REG_EMPTY_HEAD                                                                          0x2d0804UL //Access:R    DataWidth:0x9   Reserved:  This register is no longer needed in E4 B0.  Chips: BB_A0 BB_B0 K2
41754 #define TCFC_REG_EMPTY_TAIL                                                                          0x2d0808UL //Access:R    DataWidth:0x9   Reserved:  This register is no longer needed in E4 b0.  Chips: BB_A0 BB_B0 K2
41755 #define TCFC_REG_EMPTY_SIZE                                                                          0x2d080cUL //Access:RW   DataWidth:0x9   The size of the empty Link List is set accordingly.  Chips: BB_A0 BB_B0 K2
41756 #define TCFC_REG_LC_CLIENT_0_LCID_THRESHOLD                                                          0x2d0900UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 0 (YULD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41757 #define TCFC_REG_LC_CLIENT_1_LCID_THRESHOLD                                                          0x2d0904UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 1 (XYLD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41758 #define TCFC_REG_LC_CLIENT_2_LCID_THRESHOLD                                                          0x2d0908UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 2 (TMLD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41759 #define TCFC_REG_LC_CLIENT_3_LCID_THRESHOLD                                                          0x2d090cUL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 3 (MULD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41760 #define TCFC_REG_LC_CLIENT_4_LCID_THRESHOLD                                                          0x2d0910UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 4 (YSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41761 #define TCFC_REG_LC_CLIENT_5_LCID_THRESHOLD                                                          0x2d0914UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 5 (XSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41762 #define TCFC_REG_LC_CLIENT_6_LCID_THRESHOLD                                                          0x2d0918UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 6 (USDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41763 #define TCFC_REG_LC_CLIENT_7_LCID_THRESHOLD                                                          0x2d091cUL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 7 (TSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41764 #define TCFC_REG_LC_CLIENT_8_LCID_THRESHOLD                                                          0x2d0920UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 8 (PSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41765 #define TCFC_REG_LC_CLIENT_9_LCID_THRESHOLD                                                          0x2d0924UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 9 (MSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41766 #define TCFC_REG_LC_CLIENT_10_LCID_THRESHOLD                                                         0x2d0928UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 10 (Timers). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41767 #define TCFC_REG_LC_CLIENT_11_LCID_THRESHOLD                                                         0x2d092cUL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 11 (QM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41768 #define TCFC_REG_LC_CLIENT_12_LCID_THRESHOLD                                                         0x2d0930UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 12 (Parser). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41769 #define TCFC_REG_LC_CLIENT_13_LCID_THRESHOLD                                                         0x2d0934UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 13 (DORQ). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
41770 #define TCFC_REG_DORQ_NODIRECT_MSG_THRESH                                                            0x2d0938UL //Access:RW   DataWidth:0x9   This is threshold register to disable Direct messages in the DORQ. When the number of Active LCIDs is above this value, CFC will drive a signal to DORQ to prevent it from sending direct messages to XCM.  Chips: BB_A0 BB_B0 K2
41771 #define TCFC_REG_WAVE_SM_RESTART                                                                     0x2d093cUL //Access:RW   DataWidth:0x3   This is the Restart register for the LCID Limit Waveform Generators. Each bit corresponds to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Timer in each Generator. At this time, the output of the Generator will be set to the value of the Polarity bit in the corresponding Config register. Reading this register will always return 0.  Chips: BB_A0 BB_B0 K2
41772 #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG                                                            0x2d0940UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41773     #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED                                      (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #0.
41774     #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED_SHIFT                                0
41775     #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY                                     (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform will always output this value when the Restart bit is set.
41776     #define TCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY_SHIFT                               1
41777 #define TCFC_REG_WAVE_SM_0_CLIENT_MASK                                                               0x2d0944UL //Access:RW   DataWidth:0xe   This is the list of LC Clients that will be affected by Waveform Generator #0.  Chips: BB_A0 BB_B0 K2
41778 #define TCFC_REG_WAVE_SM_0_ACTIVE_THRESH                                                             0x2d0948UL //Access:RW   DataWidth:0x9   This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #0.  Chips: BB_A0 BB_B0 K2
41779 #define TCFC_REG_WAVE_SM_0_ZERO_COUNT                                                                0x2d094cUL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #0 will output a ZERO value.  Chips: BB_A0 BB_B0 K2
41780 #define TCFC_REG_WAVE_SM_0_ONE_COUNT                                                                 0x2d0950UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #0 will output a ONE value.  Chips: BB_A0 BB_B0 K2
41781 #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG                                                            0x2d0954UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41782     #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED                                      (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #1.
41783     #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED_SHIFT                                0
41784     #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY                                     (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform will always output this value when the Restart bit is set.
41785     #define TCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY_SHIFT                               1
41786 #define TCFC_REG_WAVE_SM_1_CLIENT_MASK                                                               0x2d0958UL //Access:RW   DataWidth:0xe   This is the list of LC Clients that will be affected by Waveform Generator #1.  Chips: BB_A0 BB_B0 K2
41787 #define TCFC_REG_WAVE_SM_1_ACTIVE_THRESH                                                             0x2d095cUL //Access:RW   DataWidth:0x9   This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #1.  Chips: BB_A0 BB_B0 K2
41788 #define TCFC_REG_WAVE_SM_1_ZERO_COUNT                                                                0x2d0960UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #1 will output a ZERO value.  Chips: BB_A0 BB_B0 K2
41789 #define TCFC_REG_WAVE_SM_1_ONE_COUNT                                                                 0x2d0964UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #1 will output a ONE value.  Chips: BB_A0 BB_B0 K2
41790 #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG                                                            0x2d0968UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41791     #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED                                      (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #2.
41792     #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED_SHIFT                                0
41793     #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY                                     (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform will always output this value when the Restart bit is set.
41794     #define TCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY_SHIFT                               1
41795 #define TCFC_REG_WAVE_SM_2_CLIENT_MASK                                                               0x2d096cUL //Access:RW   DataWidth:0xe   This is the list of LC Clients that will be affected by Waveform Generator #2.  Chips: BB_A0 BB_B0 K2
41796 #define TCFC_REG_WAVE_SM_2_ACTIVE_THRESH                                                             0x2d0970UL //Access:RW   DataWidth:0x9   This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #2.  Chips: BB_A0 BB_B0 K2
41797 #define TCFC_REG_WAVE_SM_2_ZERO_COUNT                                                                0x2d0974UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #2 will output a ZERO value.  Chips: BB_A0 BB_B0 K2
41798 #define TCFC_REG_WAVE_SM_2_ONE_COUNT                                                                 0x2d0978UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #2 will output a ONE value.  Chips: BB_A0 BB_B0 K2
41799 #define TCFC_REG_CACHE_STRING_TYPE                                                                   0x2d0a00UL //Access:RW   DataWidth:0x8   Mask vector for enabling caching on various string types. Each bit in this register matches the corresponding String Type. Bit[0]   = TCP Bit[1]   = UDP Bit[2]   = RoCE Multicast Bit[3]   = RoCE Unicast Bit[4]   = FCoE Bit[5]   = OpenFlow Bit[6]   = GFT Bit[7]   = Reserved  Chips: BB_A0 BB_B0 K2
41800 #define TCFC_REG_SCAM_CACHE_ENABLES                                                                  0x2d0a04UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41801     #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING                                      (0x1<<0) // When set, the String CAM will be used to cache results from the Searcher that did not match an entry in the external tables.
41802     #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING_SHIFT                                0
41803     #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING                                            (0x1<<1) // When set, the String CAM will be used to cache results from the Searcher that Matched on an L2 Filter.
41804     #define TCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING_SHIFT                                      1
41805 #define TCFC_REG_CCAM_MASK_VECTOR                                                                    0x2d0a08UL //Access:RW   DataWidth:0x20  CID CAM Mask.  This mask is used for Searches and Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a bit to 0 will clear that bit on a write.  Chips: BB_A0 BB_B0 K2
41806 #define TCFC_REG_CCAM_SEARCH                                                                         0x2d0a0cUL //Access:RW   DataWidth:0x1   When this bit is set writing to the ccam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_CID_CAM.CID_CAM interface. the write can be to any address).  Chips: BB_A0 BB_B0 K2
41807 #define TCFC_REG_SCAM_HASH_KEY0                                                                      0x2d0a10UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[31:0].  Chips: BB_A0 BB_B0 K2
41808 #define TCFC_REG_SCAM_HASH_KEY1                                                                      0x2d0a14UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[63:32].  Chips: BB_A0 BB_B0 K2
41809 #define TCFC_REG_SCAM_HASH_KEY2                                                                      0x2d0a18UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[95:64].  Chips: BB_A0 BB_B0 K2
41810 #define TCFC_REG_SCAM_HASH_KEY3                                                                      0x2d0a1cUL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[127:96].  Chips: BB_A0 BB_B0 K2
41811 #define TCFC_REG_SCAM_HASH_KEY4                                                                      0x2d0a20UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[159:128].  Chips: BB_A0 BB_B0 K2
41812 #define TCFC_REG_SCAM_HASH_KEY5                                                                      0x2d0a24UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[191:160].  Chips: BB_A0 BB_B0 K2
41813 #define TCFC_REG_SCAM_HASH_KEY6                                                                      0x2d0a28UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[223:192].  Chips: BB_A0 BB_B0 K2
41814 #define TCFC_REG_SCAM_HASH_KEY7                                                                      0x2d0a2cUL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[255:224].  Chips: BB_A0 BB_B0 K2
41815 #define TCFC_REG_SCAM_HASH_KEY8                                                                      0x2d0a30UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[287:256].  Chips: BB_A0 BB_B0 K2
41816 #define TCFC_REG_SCAM_HASH_KEY9                                                                      0x2d0a34UL //Access:RW   DataWidth:0x18  Key for String Cam Hash Algorithm, Bits[311:288].  Chips: BB_A0 BB_B0 K2
41817 #define TCFC_REG_SCAM_SEARCH                                                                         0x2d0a38UL //Access:RW   DataWidth:0x1   When this bit is set writing to the scam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_STRING_CAM.STRING_CAM interface. the write can be to any address).  Chips: BB_A0 BB_B0 K2
41818 #define TCFC_REG_SEARCH_RESULT                                                                       0x2d0a3cUL //Access:R    DataWidth:0xa   {HIT;LCID}. HIT - if set then previous CAM seach item (either CCAM or SCAM) was found. LCID contains the result in case CAM search item (either CCAM or SCAM) was found.  Chips: BB_A0 BB_B0 K2
41819 #define TCFC_REG_INCLUDE_TID_IN_HASH                                                                 0x2d0a40UL //Access:RW   DataWidth:0x1   Added in E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by XORing TID[32:16] and TID[15:0] to the hash result. In this case, TID mask bit should be zero.  Chips: BB_B0 K2
41820 #define TCFC_REG_INCLUDE_VLAN_IN_HASH                                                                0x2d0a44UL //Access:RW   DataWidth:0x1   Added in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation by XORing VLAN [11:0] to the hash result. In this case, promiscuous VLAN bit should be zero.  Chips: BB_B0 K2
41821 #define TCFC_REG_CID_CAM_BIST_EN                                                                     0x2d0b00UL //Access:RW   DataWidth:0x1   Used to enable/disable BIST mode on the CID CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.  Chips: BB_A0 BB_B0 K2
41822 #define TCFC_REG_CID_CAM_BIST_SKIP_ERROR_CNT                                                         0x2d0b04UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of CID CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0 K2
41823 #define TCFC_REG_CID_CAM_BIST_STATUS_SEL                                                             0x2d0b08UL //Access:RW   DataWidth:0x8   Used to select the CID CAM BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.  Chips: BB_A0 BB_B0 K2
41824 #define TCFC_REG_CID_CAM_BIST_STATUS                                                                 0x2d0b0cUL //Access:R    DataWidth:0x20  Provides read-only access to the CID CAM BIST status word selected by cid_cam_bist_status_sel.  Chips: BB_A0 BB_B0 K2
41825 #define TCFC_REG_STRING_CAM_BIST_EN                                                                  0x2d0b10UL //Access:RW   DataWidth:0x1   Used to enable/disable BIST mode on the STRING CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.  Chips: BB_A0 BB_B0 K2
41826 #define TCFC_REG_STRING_CAM_BIST_SKIP_ERROR_CNT                                                      0x2d0b14UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of STRING CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0 K2
41827 #define TCFC_REG_STRING_CAM_BIST_STATUS_SEL                                                          0x2d0b18UL //Access:RW   DataWidth:0x8   Used to select the STRING CAM BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.  Chips: BB_A0 BB_B0 K2
41828 #define TCFC_REG_STRING_CAM_BIST_STATUS                                                              0x2d0b1cUL //Access:R    DataWidth:0x20  Provides read-only access to the STRING CAM BIST status word selected by string_cam_bist_status_sel.  Chips: BB_A0 BB_B0 K2
41829 #define TCFC_REG_LC_QUE                                                                              0x2d8000UL //Access:WB   DataWidth:0x36  Load client queue ram access.  Chips: BB_A0 BB_B0 K2
41830 #define TCFC_REG_LC_QUE_SIZE                                                                         324
41831 #define TCFC_REG_ACTIVITY_COUNTER                                                                    0x2d8800UL //Access:RW   DataWidth:0x10  Activity counter ram access.  Chips: BB_A0 BB_B0 K2
41832 #define TCFC_REG_ACTIVITY_COUNTER_SIZE                                                               320
41833 #define TCFC_REG_INFO_STATE                                                                          0x2d9000UL //Access:R    DataWidth:0x13  Info store state machines = {lcid_curr_state;region_states}.  Chips: BB_A0 BB_B0 K2
41834 #define TCFC_REG_INFO_STATE_SIZE                                                                     320
41835 #define TCFC_REG_INFO_REG                                                                            0x2d9800UL //Access:R    DataWidth:0xe   Info store register = {fid;type;cvld;ofl}.  Chips: BB_A0 BB_B0 K2
41836 #define TCFC_REG_INFO_REG_SIZE                                                                       320
41837 #define TCFC_REG_LINK_LIST                                                                           0x2da000UL //Access:RW   DataWidth:0x12  Link List ram access; data = {prev_pfid;prev_lcid;next_pfid;next_lcid}.  Chips: BB_A0 BB_B0 K2
41838 #define TCFC_REG_LINK_LIST_SIZE                                                                      320
41839 #define TCFC_REG_CID_CAM                                                                             0x2db000UL //Access:WB   DataWidth:0x21  CID cam  access (Valid - 32;31:0 - Data).  Chips: BB_A0 BB_B0 K2
41840 #define TCFC_REG_CID_CAM_SIZE                                                                        640
41841 #define TCFC_REG_STRING_CAM                                                                          0x2dc000UL //Access:WB   DataWidth:0x18  String CAM Access Register (Hash[23:0])  Chips: BB_A0 BB_B0 K2
41842 #define TCFC_REG_STRING_CAM_SIZE                                                                     8
41843 #define TCFC_REG_TID_LOCK_RAM                                                                        0x2dc800UL //Access:RW   DataWidth:0xc   TID Lock RAM Access Register [11]      = Locked [10]      = In Use [09:00]   = Usage Counter Value  Chips: BB_A0 BB_B0 K2
41844 #define TCFC_REG_TID_LOCK_RAM_SIZE                                                                   320
41845 #define TCFC_REG_VPF1_LSTATE_SEL                                                                     0x2dd000UL //Access:RW   DataWidth:0x7   State select vector for VF/PF LCID state counter 1 .  Chips: BB_A0 BB_B0 K2
41846 #define TCFC_REG_VPF2_LSTATE_SEL                                                                     0x2dd004UL //Access:RW   DataWidth:0x7   State select vector for VF/PF LCID state counter 2 .  Chips: BB_A0 BB_B0 K2
41847 #define TCFC_REG_VF_LSTATE_CNT1                                                                      0x2dd008UL //Access:R    DataWidth:0x9   VF port to VF/PF LCID state counter 1 .  Chips: BB_A0 BB_B0 K2
41848 #define TCFC_REG_PF_LSTATE_CNT1                                                                      0x2dd00cUL //Access:R    DataWidth:0x9   PF port to VF/PF LCID state counter 1 .  Chips: BB_A0 BB_B0 K2
41849 #define TCFC_REG_VF_LSTATE_CNT2                                                                      0x2dd010UL //Access:R    DataWidth:0x9   VF port to VF/PF LCID state counter 2 .  Chips: BB_A0 BB_B0 K2
41850 #define TCFC_REG_PF_LSTATE_CNT2                                                                      0x2dd014UL //Access:R    DataWidth:0x9   PF port to VF/PF LCID state counter 2 .  Chips: BB_A0 BB_B0 K2
41851 #define CCFC_REG_INIT_REG                                                                            0x2e0000UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41852     #define CCFC_REG_INIT_REG_AC_INIT                                                                (0x1<<0) // When set activity counter ram will be initialized to zeros. when this operation is completed CFC_REGISTERS_AC_INITDONE.AC_INIT_DONE will be set.
41853     #define CCFC_REG_INIT_REG_AC_INIT_SHIFT                                                          0
41854     #define CCFC_REG_INIT_REG_LL_INIT_LAST_LCID                                                      (0x1ff<<1) // This field is only relevant when setting CFC_REGISTERS_INIT_REG.LL_INIT . indicates the last lcid to be used by the CFC. this field can strict the CFC to work will less than 320 LCIDs.
41855     #define CCFC_REG_INIT_REG_LL_INIT_LAST_LCID_SHIFT                                                1
41856     #define CCFC_REG_INIT_REG_LL_INIT                                                                (0x1<<10) // When set link list ram will be initialized - all LCIDs will be located in the empty link list. when this operation completes CFC_REGISTERS_LL_INITDONE.LL_INIT_DONE will be set.
41857     #define CCFC_REG_INIT_REG_LL_INIT_SHIFT                                                          10
41858     #define CCFC_REG_INIT_REG_CAM_INIT                                                               (0x1<<11) // When set the CFC CAMs will be initialized to zeros. When this operation completes CFC_REGISTERS_CAM_INITDONE.CAM_INIT_DONE will be set.
41859     #define CCFC_REG_INIT_REG_CAM_INIT_SHIFT                                                         11
41860     #define CCFC_REG_INIT_REG_TIDRAM_INIT                                                            (0x1<<12) // Setting this bit causes the TID Lock RAM to be initialized. This cannot be set during normal operation -- the block must be idle or the request will be ignored. When this operation completes CFC_REGISTERS_TIDRAM_INITDONE.TIDRAM_INIT_DONE will be set.
41861     #define CCFC_REG_INIT_REG_TIDRAM_INIT_SHIFT                                                      12
41862 #define CCFC_REG_LL_INIT_DONE                                                                        0x2e0004UL //Access:R    DataWidth:0x1   Indication the initializing the link list by the hardware was done.  Chips: BB_A0 BB_B0 K2
41863 #define CCFC_REG_AC_INIT_DONE                                                                        0x2e0008UL //Access:R    DataWidth:0x1   Indication the initializing the activity counter by the hardware was done.  Chips: BB_A0 BB_B0 K2
41864 #define CCFC_REG_CAM_INIT_DONE                                                                       0x2e000cUL //Access:R    DataWidth:0x1   Indication that initializing the cams by the hardware was done.  Chips: BB_A0 BB_B0 K2
41865 #define CCFC_REG_TIDRAM_INIT_DONE                                                                    0x2e0010UL //Access:R    DataWidth:0x1   This bit does not exist for CCFC and will always read '1'.  Chips: BB_A0 BB_B0 K2
41866 #define CCFC_REG_INT_STS_0                                                                           0x2e0180UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41867     #define CCFC_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
41868     #define CCFC_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
41869     #define CCFC_REG_INT_STS_0_EXE_ERROR                                                             (0x1<<1) // Interrupt indicating that an execution error has occurred.
41870     #define CCFC_REG_INT_STS_0_EXE_ERROR_SHIFT                                                       1
41871 #define CCFC_REG_INT_MASK_0                                                                          0x2e0184UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41872     #define CCFC_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: CCFC_REG_INT_STS_0.ADDRESS_ERROR .
41873     #define CCFC_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
41874     #define CCFC_REG_INT_MASK_0_EXE_ERROR                                                            (0x1<<1) // This bit masks, when set, the Interrupt bit: CCFC_REG_INT_STS_0.EXE_ERROR .
41875     #define CCFC_REG_INT_MASK_0_EXE_ERROR_SHIFT                                                      1
41876 #define CCFC_REG_INT_STS_WR_0                                                                        0x2e0188UL //Access:WR   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41877     #define CCFC_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
41878     #define CCFC_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
41879     #define CCFC_REG_INT_STS_WR_0_EXE_ERROR                                                          (0x1<<1) // Interrupt indicating that an execution error has occurred.
41880     #define CCFC_REG_INT_STS_WR_0_EXE_ERROR_SHIFT                                                    1
41881 #define CCFC_REG_INT_STS_CLR_0                                                                       0x2e018cUL //Access:RC   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41882     #define CCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
41883     #define CCFC_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
41884     #define CCFC_REG_INT_STS_CLR_0_EXE_ERROR                                                         (0x1<<1) // Interrupt indicating that an execution error has occurred.
41885     #define CCFC_REG_INT_STS_CLR_0_EXE_ERROR_SHIFT                                                   1
41886 #define CCFC_REG_PRTY_MASK_H_0                                                                       0x2e0204UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41887     #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
41888     #define CCFC_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                         0
41889     #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0                                           (0x1<<3) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
41890     #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0_SHIFT                                     3
41891     #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0                                           (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
41892     #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0_SHIFT                                     1
41893     #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                              (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
41894     #define CCFC_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                        1
41895     #define CCFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
41896     #define CCFC_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           1
41897     #define CCFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
41898     #define CCFC_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           2
41899 #define CCFC_REG_MEM_ECC_EVENTS                                                                      0x2e021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
41900 #define CCFC_REG_MEM004_I_ESILICON_TCAM_DFT_K2                                                       0x2e0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ccfc.i_cfc_core.i_cfc_cid_cam.i_cam.i_esilicon_tcam of module ts_28hpc_tcam_111_hs_e_t_shlas_320x33_pbn_bist_wr. [2]=rme, [1:0]=t_strw.  Chips: K2
41901 #define CCFC_REG_MEM005_I_MEM_DFT_K2                                                                 0x2e0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ccfc.i_cfc_core.i_lc_que_ram.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
41902 #define CCFC_REG_MEM003_I_MEM_DFT_K2                                                                 0x2e022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ccfc.i_cfc_core.i_ac_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
41903 #define CCFC_REG_MEM002_I_ESILICON_TCAM_DFT_K2                                                       0x2e0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_string_cam.i_cam.i_esilicon_tcam of module ts_28hpc_tcam_111_hs_e_t_shlas_512x25_pbn_bist_wr. [2]=rme, [1:0]=t_strw.  Chips: K2
41904 #define CCFC_REG_MEM001_I_MEM_DFT_K2                                                                 0x2e0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ccfc.i_cfc_core.CCFC_STR_CAM_GEN_IF.i_cfc_sinfo_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
41905 #define CCFC_REG_LC_BLOCKED                                                                          0x2e0400UL //Access:RC   DataWidth:0x20  Statistics register that counts cycles in which load context requests were blocked.  Chips: BB_A0 BB_B0 K2
41906 #define CCFC_REG_TID_LOCK_INC_STAT                                                                   0x2e0404UL //Access:RC   DataWidth:0x20  This statistic counts the number of cycles in which a Primary Lock condition exists when it was caused by an Increment command on a previously locked LTID. Note that this counts the number of cycles in which this condition exists, not the number of times it occurred.  Chips: BB_A0 BB_B0 K2
41907 #define CCFC_REG_TID_LOCK_LOCK_STAT                                                                  0x2e0408UL //Access:RC   DataWidth:0x20  This statistic counts the number of cycles in which a Primary Lock condition exists when it was caused by an Lock command on a previously locked LTID. Note that this counts the number of cycles in which this condition exists, not the number of times it occurred.  Chips: BB_A0 BB_B0 K2
41908 #define CCFC_REG_RFE_TASK_COUNTER                                                                    0x2e040cUL //Access:RC   DataWidth:0x20  Counts number of tasks executed by the RFE controller.  Chips: BB_A0 BB_B0 K2
41909 #define CCFC_REG_LC_STAT_MASK                                                                        0x2e0410UL //Access:RW   DataWidth:0xe   Used to mask the various load client queues for LC task statistics.  Chips: BB_A0 BB_B0 K2
41910 #define CCFC_REG_LC_TASK_COUNTER                                                                     0x2e0414UL //Access:RC   DataWidth:0x20  Counts number of tasks executed by the load client controller.  Chips: BB_A0 BB_B0 K2
41911 #define CCFC_REG_MISC_TASK_COUNTER                                                                   0x2e0418UL //Access:RC   DataWidth:0x20  Counts number of tasks executed by the miscellaneous controller.  Chips: BB_A0 BB_B0 K2
41912 #define CCFC_REG_LOAD_CONTEXT_HITS                                                                   0x2e041cUL //Access:RC   DataWidth:0x20  Counts the number of load context hits for the load clients selected by lc_stat_mask.  Chips: BB_A0 BB_B0 K2
41913 #define CCFC_REG_LOAD_CONTEXT_MISSES                                                                 0x2e0420UL //Access:RC   DataWidth:0x20  Counts the number of load context misses for the load clients selected by lc_stat_mask.  Chips: BB_A0 BB_B0 K2
41914 #define CCFC_REG_RFE_SEARCH_HITS                                                                     0x2e0424UL //Access:RC   DataWidth:0x20  Counts the number of RFE serach hits.  Chips: BB_A0 BB_B0 K2
41915 #define CCFC_REG_RFE_SEARCH_MISSES                                                                   0x2e0428UL //Access:RC   DataWidth:0x20  Counts the number of RFE serach misses.  Chips: BB_A0 BB_B0 K2
41916 #define CCFC_REG_CDU_WRITE_BACKS                                                                     0x2e042cUL //Access:RC   DataWidth:0x20  Counts the number of CDU write backs submitted by CFC.  Chips: BB_A0 BB_B0 K2
41917 #define CCFC_REG_DBG_SELECT                                                                          0x2e0500UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
41918 #define CCFC_REG_DBG_DWORD_ENABLE                                                                    0x2e0504UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
41919 #define CCFC_REG_DBG_SHIFT                                                                           0x2e0508UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
41920 #define CCFC_REG_DBG_FORCE_VALID                                                                     0x2e050cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
41921 #define CCFC_REG_DBG_FORCE_FRAME                                                                     0x2e0510UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
41922 #define CCFC_REG_DBG_OUT_DATA                                                                        0x2e0520UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
41923 #define CCFC_REG_DBG_OUT_DATA_SIZE                                                                   8
41924 #define CCFC_REG_DBG_OUT_VALID                                                                       0x2e0540UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
41925 #define CCFC_REG_DBG_OUT_FRAME                                                                       0x2e0544UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
41926 #define CCFC_REG_ECO_RESERVED                                                                        0x2e0548UL //Access:RW   DataWidth:0x8   Eco reserved.  bit0: Chicken bit for CQ73536 fix. When '0' takes into account LCIDs in the pipe. When '1' behaces as A0.  Chips: BB_A0 BB_B0 K2
41927 #define CCFC_REG_ERROR_VECTOR                                                                        0x2e054cUL //Access:R    DataWidth:0x11  CFC error vector. when the CFC detects an internal error it will set one of these bits. the bit description can be found in CFC specifications.  Chips: BB_A0 BB_B0 K2
41928 #define CCFC_REG_ERROR_MASK                                                                          0x2e0550UL //Access:RW   DataWidth:0x11  Masking for error logging. if a bit in this field is set then the corresponding bit in CFC_REGISTERS_CFC_ERROR_VECTOR.ERROR_VECTOR will not be set.  Chips: BB_A0 BB_B0 K2
41929 #define CCFC_REG_DISABLE_ON_ERROR                                                                    0x2e0554UL //Access:RW   DataWidth:0x11  Indicates per error (in CFC_REGISTERS_CFC_ERROR_VECTOR.CFC_ERROR vector) whether the cfc should be disabled upon it.  Chips: BB_A0 BB_B0 K2
41930 #define CCFC_REG_ERROR_DATA1                                                                         0x2e0558UL //Access:R    DataWidth:0x20  When the CFC detects an internal error it updates these fields. [31:28] -- CFC Controller ID [20:16] -- CFC Client ID [15:08] -- Requested Regions [04:00] -- Error ID Note that the Error ID starts counting at 0x1 so that there will always be a bit set in the ID.  This means it is always 1 greater than the bit in the error_vector register which caused the error.  See the CFC EAS document for more details.  Chips: BB_A0 BB_B0 K2
41931 #define CCFC_REG_ERROR_DATA2                                                                         0x2e055cUL //Access:R    DataWidth:0x20  When the CFC detects an internal error it updates these fields. [31:00] -- CID  Chips: BB_A0 BB_B0 K2
41932 #define CCFC_REG_ERROR_DATA3                                                                         0x2e0560UL //Access:R    DataWidth:0x20  When the CFC detects an internal error it updates these fields. [24:16] -- Request LCID [08:00] -- Active LCID  Chips: BB_A0 BB_B0 K2
41933 #define CCFC_REG_ERROR_DATA4                                                                         0x2e0564UL //Access:R    DataWidth:0x20  When the CFC detects an internal error it updates these fields. [23:16] -- Increment Value [15:12] -- Type Field [08:00] -- AC LCID  Chips: BB_A0 BB_B0 K2
41934 #define CCFC_REG_ARBITERS_REG                                                                        0x2e0568UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41935     #define CCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB                                                     (0x1<<0) // When set CFC arbiter1 will work in strict priority.
41936     #define CCFC_REG_ARBITERS_REG_SP_LC_DONE_ARB_SHIFT                                               0
41937     #define CCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB                                                      (0x1<<1) // When set load context arbiter will work in strict priority.
41938     #define CCFC_REG_ARBITERS_REG_SP_LC_REQ_ARB_SHIFT                                                1
41939     #define CCFC_REG_ARBITERS_REG_SP_LC_INP_ARB                                                      (0x1<<2) // When set CFC arbiter2 will work in strict priority.
41940     #define CCFC_REG_ARBITERS_REG_SP_LC_INP_ARB_SHIFT                                                2
41941     #define CCFC_REG_ARBITERS_REG_SP_MISC_ARB                                                        (0x1<<3) // When set CFC arbiter3 will work in strict priority.
41942     #define CCFC_REG_ARBITERS_REG_SP_MISC_ARB_SHIFT                                                  3
41943     #define CCFC_REG_ARBITERS_REG_SP_AC_DEC                                                          (0x1<<4) // When set activity counter decrement arbiter will work in strict priority.
41944     #define CCFC_REG_ARBITERS_REG_SP_AC_DEC_SHIFT                                                    4
41945     #define CCFC_REG_ARBITERS_REG_SP_AC_INC                                                          (0x1<<5) // When set activity counter increment arbiter will work in strict priority.
41946     #define CCFC_REG_ARBITERS_REG_SP_AC_INC_SHIFT                                                    5
41947 #define CCFC_REG_LCREQ_WEIGHTS                                                                       0x2e0580UL //Access:RW   DataWidth:0x3   This field allows changing the priorities of the weighted-round-robin arbiter which selects which CFC load client should be served next.  Chips: BB_A0 BB_B0 K2
41948 #define CCFC_REG_LCREQ_WEIGHTS_SIZE                                                                  14
41949 #define CCFC_REG_DEBUG0                                                                              0x2e05c0UL //Access:RW   DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
41950     #define CCFC_REG_DEBUG0_DISABLE_INPUTS                                                           (0x1<<0) // This bit disables the inputs on the CFC.
41951     #define CCFC_REG_DEBUG0_DISABLE_INPUTS_SHIFT                                                     0
41952     #define CCFC_REG_DEBUG0_DISABLE_OUTPUTS                                                          (0x1<<1) // This bit disables the outputs of the CFC.
41953     #define CCFC_REG_DEBUG0_DISABLE_OUTPUTS_SHIFT                                                    1
41954     #define CCFC_REG_DEBUG0_AC_COUNTER_ZERO                                                          (0xff<<2) // Debug only.
41955     #define CCFC_REG_DEBUG0_AC_COUNTER_ZERO_SHIFT                                                    2
41956     #define CCFC_REG_DEBUG0_AC_GRANT_PERIOD                                                          (0xf<<10) // This register is not used in BB-B0. Reduced width to 1 bit to keep its address.
41957     #define CCFC_REG_DEBUG0_AC_GRANT_PERIOD_SHIFT                                                    10
41958     #define CCFC_REG_DEBUG0_E_THRESHOLD                                                              (0x7<<14) // Debug only.
41959     #define CCFC_REG_DEBUG0_E_THRESHOLD_SHIFT                                                        14
41960     #define CCFC_REG_DEBUG0_INA_THRESHOLD                                                            (0x7<<17) // Debug only.
41961     #define CCFC_REG_DEBUG0_INA_THRESHOLD_SHIFT                                                      17
41962     #define CCFC_REG_DEBUG0_IO_THRESHOLD                                                             (0x7<<20) // Debug only.
41963     #define CCFC_REG_DEBUG0_IO_THRESHOLD_SHIFT                                                       20
41964 #define CCFC_REG_DEBUG1                                                                              0x2e05c4UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41965     #define CCFC_REG_DEBUG1_MARB_THRESHOLD                                                           (0xf<<0) // Debug only.
41966     #define CCFC_REG_DEBUG1_MARB_THRESHOLD_SHIFT                                                     0
41967     #define CCFC_REG_DEBUG1_WRITE_AC                                                                 (0x1<<4) // Debug only.
41968     #define CCFC_REG_DEBUG1_WRITE_AC_SHIFT                                                           4
41969     #define CCFC_REG_DEBUG1_MY_VAL_AC                                                                (0x1<<5) // Debug only.
41970     #define CCFC_REG_DEBUG1_MY_VAL_AC_SHIFT                                                          5
41971     #define CCFC_REG_DEBUG1_WVAL_AC                                                                  (0x3<<6) // Debug only.
41972     #define CCFC_REG_DEBUG1_WVAL_AC_SHIFT                                                            6
41973     #define CCFC_REG_DEBUG1_TYPE_FROM_REQ                                                            (0x1<<8) // Debug only.
41974     #define CCFC_REG_DEBUG1_TYPE_FROM_REQ_SHIFT                                                      8
41975     #define CCFC_REG_DEBUG1_CHECK_DEL_STATE                                                          (0x1<<9) // Debug only.
41976     #define CCFC_REG_DEBUG1_CHECK_DEL_STATE_SHIFT                                                    9
41977     #define CCFC_REG_DEBUG1_SW_RESET                                                                 (0x1<<10) // Debug only.
41978     #define CCFC_REG_DEBUG1_SW_RESET_SHIFT                                                           10
41979     #define CCFC_REG_DEBUG1_EN_ON_INT_CLR                                                            (0x1<<11) // Debug only.
41980     #define CCFC_REG_DEBUG1_EN_ON_INT_CLR_SHIFT                                                      11
41981     #define CCFC_REG_DEBUG1_UPD_CANCEL_DIS                                                           (0x1<<12) // Debug only.
41982     #define CCFC_REG_DEBUG1_UPD_CANCEL_DIS_SHIFT                                                     12
41983 #define CCFC_REG_OPERATION_MASK                                                                      0x2e05c8UL //Access:RW   DataWidth:0x7   Used to mask all various types of requests.  Chips: BB_A0 BB_B0 K2
41984 #define CCFC_REG_CDU_CV_ERR_MASK                                                                     0x2e05ccUL //Access:RW   DataWidth:0x3   Error Masking Bits for CDU Context Validation Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.  Chips: BB_A0 BB_B0 K2
41985 #define CCFC_REG_CDU_AV_ERR_MASK                                                                     0x2e05d0UL //Access:RW   DataWidth:0x3   Error Masking Bits for CDU Active Validation Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.  Chips: BB_A0 BB_B0 K2
41986 #define CCFC_REG_CDU_PCIE_ERR_MASK                                                                   0x2e05d4UL //Access:RW   DataWidth:0x3   Error Masking Bits for CDU PCIE Error. This is independent of the cfc_error_mask register. [2] Mask Error For DORQ Client on Virtual Functions. [1] Mask Error For DORQ Client on Physical Functions. [0] Mask Error For non-DORQ Clients.  Chips: BB_A0 BB_B0 K2
41987 #define CCFC_REG_ROBUSTWB_PF                                                                         0x2e05d8UL //Access:RW   DataWidth:0x1   Disable Robust WB change: When an inactivate request is processed do not move the LCID to Inactive state if any of the regions are in error state.  Chips: BB_A0 BB_B0 K2
41988 #define CCFC_REG_SREQ_FULL_STICKY                                                                    0x2e05dcUL //Access:RW   DataWidth:0x1   The Interface to Searcher Request Queue has reached the maximum value (4).  Chips: BB_A0 BB_B0 K2
41989 #define CCFC_REG_PRSRESP_FULL_STICKY                                                                 0x2e05e0UL //Access:RW   DataWidth:0x1   The Interface to Parser Response Queue has reached the maximum value (6).  Chips: BB_A0 BB_B0 K2
41990 #define CCFC_REG_PRTY_MASK                                                                           0x2e05e8UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
41991     #define CCFC_REG_PRTY_MASK_CCAM_PAR_ERR                                                          (0x1<<0) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.CCAM_PAR_ERR .
41992     #define CCFC_REG_PRTY_MASK_CCAM_PAR_ERR_SHIFT                                                    0
41993     #define CCFC_REG_PRTY_MASK_SCAM_PAR_ERR                                                          (0x1<<1) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.SCAM_PAR_ERR .
41994     #define CCFC_REG_PRTY_MASK_SCAM_PAR_ERR_SHIFT                                                    1
41995     #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR                                          (0x1<<2) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_LSB_PAR_ERR .
41996     #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_LSB_PAR_ERR_SHIFT                                    2
41997     #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR                                          (0x1<<3) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTA_MSB_PAR_ERR .
41998     #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTA_MSB_PAR_ERR_SHIFT                                    3
41999     #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR                                          (0x1<<4) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_LSB_PAR_ERR .
42000     #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_LSB_PAR_ERR_SHIFT                                    4
42001     #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR                                          (0x1<<5) // This bit masks, when set, the Parity bit: CCFC_REG_PRTY_STS.LC_QUE_RAM_PORTB_MSB_PAR_ERR .
42002     #define CCFC_REG_PRTY_MASK_LC_QUE_RAM_PORTB_MSB_PAR_ERR_SHIFT                                    5
42003 #define CCFC_REG_NUM_LCIDS_EMPTY                                                                     0x2e0600UL //Access:R    DataWidth:0x9   Number of Empty LCIDs in Link List Block (not allocated).  Chips: BB_A0 BB_B0 K2
42004 #define CCFC_REG_NUM_LCIDS_INA                                                                       0x2e0604UL //Access:R    DataWidth:0x9   Number of Inside not active LCIDs in Link List Block.  Chips: BB_A0 BB_B0 K2
42005 #define CCFC_REG_NUM_LCIDS_IO                                                                        0x2e0608UL //Access:R    DataWidth:0x9   Number of inside/outside LCIDs in Link List Block.  Chips: BB_A0 BB_B0 K2
42006 #define CCFC_REG_LSTATE_EMPTY                                                                        0x2e060cUL //Access:R    DataWidth:0x9   Number of LCIDs in the EMPTY state.  Chips: BB_A0 BB_B0 K2
42007 #define CCFC_REG_LSTATE_ARRIVING                                                                     0x2e0610UL //Access:R    DataWidth:0x9   Number of LCIDs in the ARRIVING state.  Chips: BB_A0 BB_B0 K2
42008 #define CCFC_REG_LSTATE_INSIDE                                                                       0x2e0614UL //Access:R    DataWidth:0x9   Number of LCIDs in the INSIDE state.  Chips: BB_A0 BB_B0 K2
42009 #define CCFC_REG_LSTATE_INSIDE_NA                                                                    0x2e0618UL //Access:R    DataWidth:0x9   Number of LCIDs in the INSIDE_NA state.  Chips: BB_A0 BB_B0 K2
42010 #define CCFC_REG_LSTATE_LEAVING                                                                      0x2e061cUL //Access:R    DataWidth:0x9   Number of LCIDs in the LEAVING state.  Chips: BB_A0 BB_B0 K2
42011 #define CCFC_REG_LSTATE_I_AND_O                                                                      0x2e0620UL //Access:R    DataWidth:0x9   Number of LCIDs in the I_AND_O state.  Chips: BB_A0 BB_B0 K2
42012 #define CCFC_REG_LSTATE_BDELETED                                                                     0x2e0624UL //Access:R    DataWidth:0x9   Number of LCIDs in the BDELETED state.  Chips: BB_A0 BB_B0 K2
42013 #define CCFC_REG_MAX_INSIDE                                                                          0x2e0628UL //Access:R    DataWidth:0x9   Reflects the maximum value seen on the lstate_inside counter.  Chips: BB_A0 BB_B0 K2
42014 #define CCFC_REG_WEAK_ENABLE_PF                                                                      0x2e0700UL //Access:RW   DataWidth:0x1   This bit when clear will cause a load-cancel response to a load request for PF and set an execution error. Set processes load requests normally.  Chips: BB_A0 BB_B0 K2
42015 #define CCFC_REG_WEAK_ENABLE_VF                                                                      0x2e0704UL //Access:RW   DataWidth:0x1   This bit when clear will cause a load-cancel response to a load request for VF and set an execution error. Set processes load requests normally.  Chips: BB_A0 BB_B0 K2
42016 #define CCFC_REG_STRONG_ENABLE_PF                                                                    0x2e0708UL //Access:RW   DataWidth:0x1   This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for PF. The PFID that caused the execution error will be stored (exec_error_pf).  Chips: BB_A0 BB_B0 K2
42017 #define CCFC_REG_STRONG_ENABLE_VF                                                                    0x2e070cUL //Access:RW   DataWidth:0x1   This bit when clear will cause a CFC execution error (weak_enable will override to force load-cancel) to a search or load request for VF. The VFID that caused the execution error will be stored (exec_error_pf).  Chips: BB_A0 BB_B0 K2
42018 #define CCFC_REG_LOADRETRY_TYPES                                                                     0x2e0710UL //Access:RW   DataWidth:0x10  LoadRetry Enable Vector, Per Type.  Chips: BB_A0 BB_B0 K2
42019 #define CCFC_REG_MINICACHE_CONTROL                                                                   0x2e0714UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
42020     #define CCFC_REG_MINICACHE_CONTROL_EMPTYTHRESHMINICACHE                                          (0x3ff<<0) // The Threshold of EmptyLCIDs which must be in the Empty State to enable the MiniCache in the Load Clients.  If there are less Empty LCIDs than this threshold, the Invalidate MiniCache signal will be asserted to the clients.
42021     #define CCFC_REG_MINICACHE_CONTROL_EMPTYTHRESHMINICACHE_SHIFT                                    0
42022     #define CCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE                                     (0x1<<10) // This field is not used in BB-B0. When set, this configuration bit will prevent the CFC from setting an Attention or hanging when the AC Counter underflows, as long as the Invalidate Minicache for that LC Client is currently asserted.
42023     #define CCFC_REG_MINICACHE_CONTROL_DISABLEATTENTIONMINICACHE_SHIFT                               10
42024 #define CCFC_REG_PF_MINICACHE_ENABLE                                                                 0x2e0718UL //Access:RW   DataWidth:0x1   Enables MiniCache in Load Clients.  Chips: BB_A0 BB_B0 K2
42025 #define CCFC_REG_CONTROL0                                                                            0x2e071cUL //Access:RW   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
42026     #define CCFC_REG_CONTROL0_WB_THRESHOLD                                                           (0x1ff<<0) // The threshold of number of free entries for WB. If there are less free entries than the threshold a WB will be initiated.
42027     #define CCFC_REG_CONTROL0_WB_THRESHOLD_SHIFT                                                     0
42028     #define CCFC_REG_CONTROL0_STRING_CAM_DISABLE                                                     (0x1<<9) // When set to 1 the search string caching mechanism is disabled.
42029     #define CCFC_REG_CONTROL0_STRING_CAM_DISABLE_SHIFT                                               9
42030     #define CCFC_REG_CONTROL0_CID_CAM_DISABLE                                                        (0x1<<10) // When set to 1 the cid cam is disabled.
42031     #define CCFC_REG_CONTROL0_CID_CAM_DISABLE_SHIFT                                                  10
42032     #define CCFC_REG_CONTROL0_NLOE                                                                   (0x1<<11) // New Load On Error. if this bit is set and there is a load request region that is in error state then a new load request for that region will be submitted; otherwise an immediate response will be sent to the client with error.
42033     #define CCFC_REG_CONTROL0_NLOE_SHIFT                                                             11
42034     #define CCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN                                                      (0x1<<12) // When set to 1 the string cam hit parity scrubbing feature is enabled.
42035     #define CCFC_REG_CONTROL0_SCAM_SCRUB_HIT_EN_SHIFT                                                12
42036     #define CCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN                                                     (0x1<<13) // When set to 1 the string cam miss parity scrubbing feature is enabled.
42037     #define CCFC_REG_CONTROL0_SCAM_SCRUB_MISS_EN_SHIFT                                               13
42038     #define CCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN                                                      (0x1<<14) // When set to 1 the cid cam hit parity scrubbing feature is enabled.
42039     #define CCFC_REG_CONTROL0_CCAM_SCRUB_HIT_EN_SHIFT                                                14
42040     #define CCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN                                                     (0x1<<15) // When set to 1 the cid cam miss parity scrubbing feature is enabled.
42041     #define CCFC_REG_CONTROL0_CCAM_SCRUB_MISS_EN_SHIFT                                               15
42042 #define CCFC_REG_LCREQ_CREDIT                                                                        0x2e0740UL //Access:RW   DataWidth:0x6   Set the initial credit for each of the load clients if less than the max is desired.  Chips: BB_A0 BB_B0 K2
42043 #define CCFC_REG_LCREQ_CREDIT_SIZE                                                                   14
42044 #define CCFC_REG_PRSRESP_CREDIT                                                                      0x2e0780UL //Access:RW   DataWidth:0x5   Set the initial credit for the parser response interface if less than the max is desired.  Chips: BB_A0 BB_B0 K2
42045 #define CCFC_REG_SEARCH_CREDIT                                                                       0x2e0784UL //Access:RW   DataWidth:0x5   Set the initial credit for the searcher interface if less than the max is desired.  Chips: BB_A0 BB_B0 K2
42046 #define CCFC_REG_CDULD_CREDIT                                                                        0x2e0788UL //Access:RW   DataWidth:0x6   Set the initial credit for the CDU load interface if less than the max is desired.  Chips: BB_A0 BB_B0 K2
42047 #define CCFC_REG_CDUWB_CREDIT                                                                        0x2e078cUL //Access:RW   DataWidth:0x6   Set the initial credit for the CDU write-back interface if less than the max is desired.  Chips: BB_A0 BB_B0 K2
42048 #define CCFC_REG_FLOAD_RGN_MSK                                                                       0x2e07a0UL //Access:RW   DataWidth:0x8   Array of indirect registers defines the forced load regions per type. Applicable only in the TCFC.  Chips: BB_A0 BB_B0 K2
42049 #define CCFC_REG_FLOAD_RGN_MSK_SIZE                                                                  8
42050 #define CCFC_REG_LL_POLICY_CFG                                                                       0x2e0800UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
42051     #define CCFC_REG_LL_POLICY_CFG_LL_POLICY_IO                                                      (0x3<<0) // This register is used to set the usage policy for the I/O Link List: 00: Pop LCIDs from the Head of the List (FIFO) 01: Pop LCIDs from the Tail of the List (Stack) 10: Alternate between Head and Tail of the List 11: Reserved
42052     #define CCFC_REG_LL_POLICY_CFG_LL_POLICY_IO_SHIFT                                                0
42053     #define CCFC_REG_LL_POLICY_CFG_LL_POLICY_INA                                                     (0x3<<2) // This register is used to set the usage policy for the INA Link List: 00: Pop LCIDs from the Head of the List (FIFO) 01: Pop LCIDs from the Tail of the List (Stack) 10: Alternate between Head and Tail of the List 11: Reserved
42054     #define CCFC_REG_LL_POLICY_CFG_LL_POLICY_INA_SHIFT                                               2
42055 #define CCFC_REG_EMPTY_HEAD                                                                          0x2e0804UL //Access:R    DataWidth:0x9   Reserved:  This register is no longer needed in E4 B0.  Chips: BB_A0 BB_B0 K2
42056 #define CCFC_REG_EMPTY_TAIL                                                                          0x2e0808UL //Access:R    DataWidth:0x9   Reserved:  This register is no longer needed in E4 b0.  Chips: BB_A0 BB_B0 K2
42057 #define CCFC_REG_EMPTY_SIZE                                                                          0x2e080cUL //Access:RW   DataWidth:0x9   The size of the empty Link List is set accordingly.  Chips: BB_A0 BB_B0 K2
42058 #define CCFC_REG_LC_CLIENT_0_LCID_THRESHOLD                                                          0x2e0900UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 0 (YULD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42059 #define CCFC_REG_LC_CLIENT_1_LCID_THRESHOLD                                                          0x2e0904UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 1 (XYLD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42060 #define CCFC_REG_LC_CLIENT_2_LCID_THRESHOLD                                                          0x2e0908UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 2 (TMLD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42061 #define CCFC_REG_LC_CLIENT_3_LCID_THRESHOLD                                                          0x2e090cUL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 3 (MULD). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42062 #define CCFC_REG_LC_CLIENT_4_LCID_THRESHOLD                                                          0x2e0910UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 4 (YSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42063 #define CCFC_REG_LC_CLIENT_5_LCID_THRESHOLD                                                          0x2e0914UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 5 (XSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42064 #define CCFC_REG_LC_CLIENT_6_LCID_THRESHOLD                                                          0x2e0918UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 6 (USDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42065 #define CCFC_REG_LC_CLIENT_7_LCID_THRESHOLD                                                          0x2e091cUL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 7 (TSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42066 #define CCFC_REG_LC_CLIENT_8_LCID_THRESHOLD                                                          0x2e0920UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 8 (PSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42067 #define CCFC_REG_LC_CLIENT_9_LCID_THRESHOLD                                                          0x2e0924UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 9 (MSDM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42068 #define CCFC_REG_LC_CLIENT_10_LCID_THRESHOLD                                                         0x2e0928UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 10 (Timers). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42069 #define CCFC_REG_LC_CLIENT_11_LCID_THRESHOLD                                                         0x2e092cUL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 11 (QM). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42070 #define CCFC_REG_LC_CLIENT_12_LCID_THRESHOLD                                                         0x2e0930UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 12 (Parser). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42071 #define CCFC_REG_LC_CLIENT_13_LCID_THRESHOLD                                                         0x2e0934UL //Access:RW   DataWidth:0x9   This is the LCID Threshold for LC CLient 13 (DORQ). When the number of Active LCIDs is equal to or greater than this value, this client will no longer be serviced for Load Requests.  Chips: BB_A0 BB_B0 K2
42072 #define CCFC_REG_DORQ_NODIRECT_MSG_THRESH                                                            0x2e0938UL //Access:RW   DataWidth:0x9   This is threshold register to disable Direct messages in the DORQ. When the number of Active LCIDs is above this value, CFC will drive a signal to DORQ to prevent it from sending direct messages to XCM.  Chips: BB_A0 BB_B0 K2
42073 #define CCFC_REG_WAVE_SM_RESTART                                                                     0x2e093cUL //Access:RW   DataWidth:0x3   This is the Restart register for the LCID Limit Waveform Generators. Each bit corresponds to one of the state machines [2:0]. Writing the bits to 1'b1 will restart the Timer in each Generator. At this time, the output of the Generator will be set to the value of the Polarity bit in the corresponding Config register. Reading this register will always return 0.  Chips: BB_A0 BB_B0 K2
42074 #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG                                                            0x2e0940UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
42075     #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED                                      (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #0.
42076     #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_ENABLED_SHIFT                                0
42077     #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY                                     (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #0. The Waveform will always output this value when the Restart bit is set.
42078     #define CCFC_REG_LCID_LIMIT_WAVE_SM_0_CFG_WAVE_SM_0_POLARITY_SHIFT                               1
42079 #define CCFC_REG_WAVE_SM_0_CLIENT_MASK                                                               0x2e0944UL //Access:RW   DataWidth:0xe   This is the list of LC Clients that will be affected by Waveform Generator #0.  Chips: BB_A0 BB_B0 K2
42080 #define CCFC_REG_WAVE_SM_0_ACTIVE_THRESH                                                             0x2e0948UL //Access:RW   DataWidth:0x9   This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #0.  Chips: BB_A0 BB_B0 K2
42081 #define CCFC_REG_WAVE_SM_0_ZERO_COUNT                                                                0x2e094cUL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #0 will output a ZERO value.  Chips: BB_A0 BB_B0 K2
42082 #define CCFC_REG_WAVE_SM_0_ONE_COUNT                                                                 0x2e0950UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #0 will output a ONE value.  Chips: BB_A0 BB_B0 K2
42083 #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG                                                            0x2e0954UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
42084     #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED                                      (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #1.
42085     #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_ENABLED_SHIFT                                0
42086     #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY                                     (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #1. The Waveform will always output this value when the Restart bit is set.
42087     #define CCFC_REG_LCID_LIMIT_WAVE_SM_1_CFG_WAVE_SM_1_POLARITY_SHIFT                               1
42088 #define CCFC_REG_WAVE_SM_1_CLIENT_MASK                                                               0x2e0958UL //Access:RW   DataWidth:0xe   This is the list of LC Clients that will be affected by Waveform Generator #1.  Chips: BB_A0 BB_B0 K2
42089 #define CCFC_REG_WAVE_SM_1_ACTIVE_THRESH                                                             0x2e095cUL //Access:RW   DataWidth:0x9   This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #1.  Chips: BB_A0 BB_B0 K2
42090 #define CCFC_REG_WAVE_SM_1_ZERO_COUNT                                                                0x2e0960UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #1 will output a ZERO value.  Chips: BB_A0 BB_B0 K2
42091 #define CCFC_REG_WAVE_SM_1_ONE_COUNT                                                                 0x2e0964UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #1 will output a ONE value.  Chips: BB_A0 BB_B0 K2
42092 #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG                                                            0x2e0968UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
42093     #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED                                      (0x1<<0) // This is the Enable bit for the LCID Limiting Waveform Generator #2.
42094     #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_ENABLED_SHIFT                                0
42095     #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY                                     (0x1<<1) // This is the Polarity bit for the LCID Limiting Waveform Generator #2. The Waveform will always output this value when the Restart bit is set.
42096     #define CCFC_REG_LCID_LIMIT_WAVE_SM_2_CFG_WAVE_SM_2_POLARITY_SHIFT                               1
42097 #define CCFC_REG_WAVE_SM_2_CLIENT_MASK                                                               0x2e096cUL //Access:RW   DataWidth:0xe   This is the list of LC Clients that will be affected by Waveform Generator #2.  Chips: BB_A0 BB_B0 K2
42098 #define CCFC_REG_WAVE_SM_2_ACTIVE_THRESH                                                             0x2e0970UL //Access:RW   DataWidth:0x9   This is the Threshold value of active LCIDs that triggers masking by Waveform Generator #2.  Chips: BB_A0 BB_B0 K2
42099 #define CCFC_REG_WAVE_SM_2_ZERO_COUNT                                                                0x2e0974UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #2 will output a ZERO value.  Chips: BB_A0 BB_B0 K2
42100 #define CCFC_REG_WAVE_SM_2_ONE_COUNT                                                                 0x2e0978UL //Access:RW   DataWidth:0x10  This is the count of cycles that Waveform Generator #2 will output a ONE value.  Chips: BB_A0 BB_B0 K2
42101 #define CCFC_REG_CACHE_STRING_TYPE                                                                   0x2e0a00UL //Access:RW   DataWidth:0x8   Mask vector for enabling caching on various string types. Each bit in this register matches the corresponding String Type. Bit[0]   = TCP Bit[1]   = UDP Bit[2]   = RoCE Multicast Bit[3]   = RoCE Unicast Bit[4]   = FCoE Bit[5]   = OpenFlow Bit[6]   = GFT Bit[7]   = Reserved  Chips: BB_A0 BB_B0 K2
42102 #define CCFC_REG_SCAM_CACHE_ENABLES                                                                  0x2e0a04UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_A0 BB_B0 K2
42103     #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING                                      (0x1<<0) // When set, the String CAM will be used to cache results from the Searcher that did not match an entry in the external tables.
42104     #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_NO_MATCH_CACHING_SHIFT                                0
42105     #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING                                            (0x1<<1) // When set, the String CAM will be used to cache results from the Searcher that Matched on an L2 Filter.
42106     #define CCFC_REG_SCAM_CACHE_ENABLES_ENABLE_L2_CACHING_SHIFT                                      1
42107 #define CCFC_REG_CCAM_MASK_VECTOR                                                                    0x2e0a08UL //Access:RW   DataWidth:0x20  CID CAM Mask.  This mask is used for Searches and Writes to the CID CAM. Setting a bit to 0 will ignore that bit in a search. Setting a bit to 0 will clear that bit on a write.  Chips: BB_A0 BB_B0 K2
42108 #define CCFC_REG_CCAM_SEARCH                                                                         0x2e0a0cUL //Access:RW   DataWidth:0x1   When this bit is set writing to the ccam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_CID_CAM.CID_CAM interface. the write can be to any address).  Chips: BB_A0 BB_B0 K2
42109 #define CCFC_REG_SCAM_HASH_KEY0                                                                      0x2e0a10UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[31:0].  Chips: BB_A0 BB_B0 K2
42110 #define CCFC_REG_SCAM_HASH_KEY1                                                                      0x2e0a14UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[63:32].  Chips: BB_A0 BB_B0 K2
42111 #define CCFC_REG_SCAM_HASH_KEY2                                                                      0x2e0a18UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[95:64].  Chips: BB_A0 BB_B0 K2
42112 #define CCFC_REG_SCAM_HASH_KEY3                                                                      0x2e0a1cUL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[127:96].  Chips: BB_A0 BB_B0 K2
42113 #define CCFC_REG_SCAM_HASH_KEY4                                                                      0x2e0a20UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[159:128].  Chips: BB_A0 BB_B0 K2
42114 #define CCFC_REG_SCAM_HASH_KEY5                                                                      0x2e0a24UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[191:160].  Chips: BB_A0 BB_B0 K2
42115 #define CCFC_REG_SCAM_HASH_KEY6                                                                      0x2e0a28UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[223:192].  Chips: BB_A0 BB_B0 K2
42116 #define CCFC_REG_SCAM_HASH_KEY7                                                                      0x2e0a2cUL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[255:224].  Chips: BB_A0 BB_B0 K2
42117 #define CCFC_REG_SCAM_HASH_KEY8                                                                      0x2e0a30UL //Access:RW   DataWidth:0x20  Key for String Cam Hash Algorithm, Bits[287:256].  Chips: BB_A0 BB_B0 K2
42118 #define CCFC_REG_SCAM_HASH_KEY9                                                                      0x2e0a34UL //Access:RW   DataWidth:0x18  Key for String Cam Hash Algorithm, Bits[311:288].  Chips: BB_A0 BB_B0 K2
42119 #define CCFC_REG_SCAM_SEARCH                                                                         0x2e0a38UL //Access:RW   DataWidth:0x1   When this bit is set writing to the scam will cause a search operation on the written item (written using CFC_REGISTERS_LCID_STRING_CAM.STRING_CAM interface. the write can be to any address).  Chips: BB_A0 BB_B0 K2
42120 #define CCFC_REG_SEARCH_RESULT                                                                       0x2e0a3cUL //Access:R    DataWidth:0xa   {HIT;LCID}. HIT - if set then previous CAM seach item (either CCAM or SCAM) was found. LCID contains the result in case CAM search item (either CCAM or SCAM) was found.  Chips: BB_A0 BB_B0 K2
42121 #define CCFC_REG_INCLUDE_TID_IN_HASH                                                                 0x2e0a40UL //Access:RW   DataWidth:0x1   Added in E4B0. 0 - tid is not included in hash calculation (like in A0). 1 - tid is included in hash calculation by XORing TID[32:16] and TID[15:0] to the hash result. In this case, TID mask bit should be zero.  Chips: BB_B0 K2
42122 #define CCFC_REG_INCLUDE_VLAN_IN_HASH                                                                0x2e0a44UL //Access:RW   DataWidth:0x1   Added in E4B0. 0 - vlan is not included in hash calculation (like in A0). 1 - vlan is included in hash calculation by XORing VLAN [11:0] to the hash result. In this case, promiscuous VLAN bit should be zero.  Chips: BB_B0 K2
42123 #define CCFC_REG_CID_CAM_BIST_EN                                                                     0x2e0b00UL //Access:RW   DataWidth:0x1   Used to enable/disable BIST mode on the CID CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.  Chips: BB_A0 BB_B0 K2
42124 #define CCFC_REG_CID_CAM_BIST_SKIP_ERROR_CNT                                                         0x2e0b04UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of CID CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0 K2
42125 #define CCFC_REG_CID_CAM_BIST_STATUS_SEL                                                             0x2e0b08UL //Access:RW   DataWidth:0x8   Used to select the CID CAM BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.  Chips: BB_A0 BB_B0 K2
42126 #define CCFC_REG_CID_CAM_BIST_STATUS                                                                 0x2e0b0cUL //Access:R    DataWidth:0x20  Provides read-only access to the CID CAM BIST status word selected by cid_cam_bist_status_sel.  Chips: BB_A0 BB_B0 K2
42127 #define CCFC_REG_STRING_CAM_BIST_EN                                                                  0x2e0b10UL //Access:RW   DataWidth:0x1   Used to enable/disable BIST mode on the STRING CAM. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.  Chips: BB_A0 BB_B0 K2
42128 #define CCFC_REG_STRING_CAM_BIST_SKIP_ERROR_CNT                                                      0x2e0b14UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of STRING CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0 K2
42129 #define CCFC_REG_STRING_CAM_BIST_STATUS_SEL                                                          0x2e0b18UL //Access:RW   DataWidth:0x8   Used to select the STRING CAM BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.  Chips: BB_A0 BB_B0 K2
42130 #define CCFC_REG_STRING_CAM_BIST_STATUS                                                              0x2e0b1cUL //Access:R    DataWidth:0x20  Provides read-only access to the STRING CAM BIST status word selected by string_cam_bist_status_sel.  Chips: BB_A0 BB_B0 K2
42131 #define CCFC_REG_LC_QUE                                                                              0x2e8000UL //Access:WB   DataWidth:0x36  Load client queue ram access.  Chips: BB_A0 BB_B0 K2
42132 #define CCFC_REG_LC_QUE_SIZE                                                                         430
42133 #define CCFC_REG_ACTIVITY_COUNTER                                                                    0x2e8800UL //Access:RW   DataWidth:0x10  Activity counter ram access.  Chips: BB_A0 BB_B0 K2
42134 #define CCFC_REG_ACTIVITY_COUNTER_SIZE                                                               320
42135 #define CCFC_REG_INFO_STATE                                                                          0x2e9000UL //Access:R    DataWidth:0x13  Info store state machines = {lcid_curr_state;region_states}.  Chips: BB_A0 BB_B0 K2
42136 #define CCFC_REG_INFO_STATE_SIZE                                                                     320
42137 #define CCFC_REG_INFO_REG                                                                            0x2e9800UL //Access:R    DataWidth:0xe   Info store register = {fid;type;cvld;ofl}.  Chips: BB_A0 BB_B0 K2
42138 #define CCFC_REG_INFO_REG_SIZE                                                                       320
42139 #define CCFC_REG_LINK_LIST                                                                           0x2ea000UL //Access:RW   DataWidth:0x12  Link List ram access; data = {prev_pfid;prev_lcid;next_pfid;next_lcid}.  Chips: BB_A0 BB_B0 K2
42140 #define CCFC_REG_LINK_LIST_SIZE                                                                      320
42141 #define CCFC_REG_CID_CAM                                                                             0x2eb000UL //Access:WB   DataWidth:0x21  CID cam  access (Valid - 32;31:0 - Data).  Chips: BB_A0 BB_B0 K2
42142 #define CCFC_REG_CID_CAM_SIZE                                                                        640
42143 #define CCFC_REG_STRING_CAM                                                                          0x2ec000UL //Access:WB   DataWidth:0x18  String CAM Access Register (Hash[23:0])  Chips: BB_A0 BB_B0 K2
42144 #define CCFC_REG_STRING_CAM_SIZE                                                                     512
42145 #define CCFC_REG_TID_LOCK_RAM                                                                        0x2ec800UL //Access:RW   DataWidth:0xc   TID Lock RAM Access Register [11]      = Locked [10]      = In Use [09:00]   = Usage Counter Value  Chips: BB_A0 BB_B0 K2
42146 #define CCFC_REG_TID_LOCK_RAM_SIZE                                                                   320
42147 #define CCFC_REG_VPF1_LSTATE_SEL                                                                     0x2ed000UL //Access:RW   DataWidth:0x7   State select vector for VF/PF LCID state counter 1 .  Chips: BB_A0 BB_B0 K2
42148 #define CCFC_REG_VPF2_LSTATE_SEL                                                                     0x2ed004UL //Access:RW   DataWidth:0x7   State select vector for VF/PF LCID state counter 2 .  Chips: BB_A0 BB_B0 K2
42149 #define CCFC_REG_VF_LSTATE_CNT1                                                                      0x2ed008UL //Access:R    DataWidth:0x9   VF port to VF/PF LCID state counter 1 .  Chips: BB_A0 BB_B0 K2
42150 #define CCFC_REG_PF_LSTATE_CNT1                                                                      0x2ed00cUL //Access:R    DataWidth:0x9   PF port to VF/PF LCID state counter 1 .  Chips: BB_A0 BB_B0 K2
42151 #define CCFC_REG_VF_LSTATE_CNT2                                                                      0x2ed010UL //Access:R    DataWidth:0x9   VF port to VF/PF LCID state counter 2 .  Chips: BB_A0 BB_B0 K2
42152 #define CCFC_REG_PF_LSTATE_CNT2                                                                      0x2ed014UL //Access:R    DataWidth:0x9   PF port to VF/PF LCID state counter 2 .  Chips: BB_A0 BB_B0 K2
42153 #define QM_REG_INT_STS                                                                               0x2f0180UL //Access:R    DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
42154     #define QM_REG_INT_STS_ADDRESS_ERROR                                                             (0x1<<0) // Signals an unknown address to the rf module.
42155     #define QM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                       0
42156     #define QM_REG_INT_STS_OVF_ERR_TX                                                                (0x1<<1) // Over flow occurs on the TX Queue.
42157     #define QM_REG_INT_STS_OVF_ERR_TX_SHIFT                                                          1
42158     #define QM_REG_INT_STS_OVF_ERR_OTHER                                                             (0x1<<2) // Over flow occurs on the Other Queue.
42159     #define QM_REG_INT_STS_OVF_ERR_OTHER_SHIFT                                                       2
42160     #define QM_REG_INT_STS_PF_USG_CNT_ERR                                                            (0x1<<3) // Overflow of pf usage counter.
42161     #define QM_REG_INT_STS_PF_USG_CNT_ERR_SHIFT                                                      3
42162     #define QM_REG_INT_STS_VF_USG_CNT_ERR                                                            (0x1<<4) // Overflow of vf usage counter.
42163     #define QM_REG_INT_STS_VF_USG_CNT_ERR_SHIFT                                                      4
42164     #define QM_REG_INT_STS_VOQ_CRD_INC_ERR                                                           (0x1<<5) // Increment overflow on VOQ counter.
42165     #define QM_REG_INT_STS_VOQ_CRD_INC_ERR_SHIFT                                                     5
42166     #define QM_REG_INT_STS_VOQ_CRD_DEC_ERR                                                           (0x1<<6) // Decrement underflow on VOQ counter.
42167     #define QM_REG_INT_STS_VOQ_CRD_DEC_ERR_SHIFT                                                     6
42168     #define QM_REG_INT_STS_BYTE_CRD_INC_ERR                                                          (0x1<<7) // Increment overflow on byte credit counter.
42169     #define QM_REG_INT_STS_BYTE_CRD_INC_ERR_SHIFT                                                    7
42170     #define QM_REG_INT_STS_BYTE_CRD_DEC_ERR                                                          (0x1<<8) // Decrement underflow on byte credit counter.
42171     #define QM_REG_INT_STS_BYTE_CRD_DEC_ERR_SHIFT                                                    8
42172     #define QM_REG_INT_STS_ERR_INCDEC_RLGLBLCRD                                                      (0x1<<9) // Increment or Decrement error for the RL Global counters.
42173     #define QM_REG_INT_STS_ERR_INCDEC_RLGLBLCRD_SHIFT                                                9
42174     #define QM_REG_INT_STS_ERR_INCDEC_RLPFCRD                                                        (0x1<<10) // Increment or Decrement error for the RL PF counters.
42175     #define QM_REG_INT_STS_ERR_INCDEC_RLPFCRD_SHIFT                                                  10
42176     #define QM_REG_INT_STS_ERR_INCDEC_WFQPFCRD                                                       (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
42177     #define QM_REG_INT_STS_ERR_INCDEC_WFQPFCRD_SHIFT                                                 11
42178     #define QM_REG_INT_STS_ERR_INCDEC_WFQVPCRD                                                       (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
42179     #define QM_REG_INT_STS_ERR_INCDEC_WFQVPCRD_SHIFT                                                 12
42180     #define QM_REG_INT_STS_ERR_INCDEC_VOQLINECRD                                                     (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
42181     #define QM_REG_INT_STS_ERR_INCDEC_VOQLINECRD_SHIFT                                               13
42182     #define QM_REG_INT_STS_ERR_INCDEC_VOQBYTECRD                                                     (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
42183     #define QM_REG_INT_STS_ERR_INCDEC_VOQBYTECRD_SHIFT                                               14
42184     #define QM_REG_INT_STS_FIFOS_ERROR                                                               (0x1<<15) // Overflow or underflow error in one of FIFOs.
42185     #define QM_REG_INT_STS_FIFOS_ERROR_SHIFT                                                         15
42186     #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR                                       (0x1<<16) // EXP PF controller pop FIFO error.
42187     #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR_SHIFT                                 16
42188     #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR                                      (0x1<<17) // EXP PF controller push FIFO error.
42189     #define QM_REG_INT_STS_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR_SHIFT                                17
42190     #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR                                       (0x1<<18) // REQ controller pop FIFO error.
42191     #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR_SHIFT                                 18
42192     #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR                                      (0x1<<19) // REQ controller push FIFO error.
42193     #define QM_REG_INT_STS_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR_SHIFT                                19
42194     #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR                                       (0x1<<20) // RES controller pop FIFO error.
42195     #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR_SHIFT                                 20
42196     #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR                                      (0x1<<21) // RES controller push FIFO error.
42197     #define QM_REG_INT_STS_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR_SHIFT                                21
42198 #define QM_REG_INT_MASK                                                                              0x2f0184UL //Access:RW   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
42199     #define QM_REG_INT_MASK_ADDRESS_ERROR                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ADDRESS_ERROR .
42200     #define QM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                      0
42201     #define QM_REG_INT_MASK_OVF_ERR_TX                                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.OVF_ERR_TX .
42202     #define QM_REG_INT_MASK_OVF_ERR_TX_SHIFT                                                         1
42203     #define QM_REG_INT_MASK_OVF_ERR_OTHER                                                            (0x1<<2) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.OVF_ERR_OTHER .
42204     #define QM_REG_INT_MASK_OVF_ERR_OTHER_SHIFT                                                      2
42205     #define QM_REG_INT_MASK_PF_USG_CNT_ERR                                                           (0x1<<3) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.PF_USG_CNT_ERR .
42206     #define QM_REG_INT_MASK_PF_USG_CNT_ERR_SHIFT                                                     3
42207     #define QM_REG_INT_MASK_VF_USG_CNT_ERR                                                           (0x1<<4) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VF_USG_CNT_ERR .
42208     #define QM_REG_INT_MASK_VF_USG_CNT_ERR_SHIFT                                                     4
42209     #define QM_REG_INT_MASK_VOQ_CRD_INC_ERR                                                          (0x1<<5) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VOQ_CRD_INC_ERR .
42210     #define QM_REG_INT_MASK_VOQ_CRD_INC_ERR_SHIFT                                                    5
42211     #define QM_REG_INT_MASK_VOQ_CRD_DEC_ERR                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.VOQ_CRD_DEC_ERR .
42212     #define QM_REG_INT_MASK_VOQ_CRD_DEC_ERR_SHIFT                                                    6
42213     #define QM_REG_INT_MASK_BYTE_CRD_INC_ERR                                                         (0x1<<7) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.BYTE_CRD_INC_ERR .
42214     #define QM_REG_INT_MASK_BYTE_CRD_INC_ERR_SHIFT                                                   7
42215     #define QM_REG_INT_MASK_BYTE_CRD_DEC_ERR                                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.BYTE_CRD_DEC_ERR .
42216     #define QM_REG_INT_MASK_BYTE_CRD_DEC_ERR_SHIFT                                                   8
42217     #define QM_REG_INT_MASK_ERR_INCDEC_RLGLBLCRD                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_RLGLBLCRD .
42218     #define QM_REG_INT_MASK_ERR_INCDEC_RLGLBLCRD_SHIFT                                               9
42219     #define QM_REG_INT_MASK_ERR_INCDEC_RLPFCRD                                                       (0x1<<10) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_RLPFCRD .
42220     #define QM_REG_INT_MASK_ERR_INCDEC_RLPFCRD_SHIFT                                                 10
42221     #define QM_REG_INT_MASK_ERR_INCDEC_WFQPFCRD                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_WFQPFCRD .
42222     #define QM_REG_INT_MASK_ERR_INCDEC_WFQPFCRD_SHIFT                                                11
42223     #define QM_REG_INT_MASK_ERR_INCDEC_WFQVPCRD                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_WFQVPCRD .
42224     #define QM_REG_INT_MASK_ERR_INCDEC_WFQVPCRD_SHIFT                                                12
42225     #define QM_REG_INT_MASK_ERR_INCDEC_VOQLINECRD                                                    (0x1<<13) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_VOQLINECRD .
42226     #define QM_REG_INT_MASK_ERR_INCDEC_VOQLINECRD_SHIFT                                              13
42227     #define QM_REG_INT_MASK_ERR_INCDEC_VOQBYTECRD                                                    (0x1<<14) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.ERR_INCDEC_VOQBYTECRD .
42228     #define QM_REG_INT_MASK_ERR_INCDEC_VOQBYTECRD_SHIFT                                              14
42229     #define QM_REG_INT_MASK_FIFOS_ERROR                                                              (0x1<<15) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.FIFOS_ERROR .
42230     #define QM_REG_INT_MASK_FIFOS_ERROR_SHIFT                                                        15
42231     #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR                                      (0x1<<16) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR .
42232     #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR_SHIFT                                16
42233     #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR                                     (0x1<<17) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR .
42234     #define QM_REG_INT_MASK_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR_SHIFT                               17
42235     #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR                                      (0x1<<18) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR .
42236     #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR_SHIFT                                18
42237     #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR                                     (0x1<<19) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR .
42238     #define QM_REG_INT_MASK_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR_SHIFT                               19
42239     #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR                                      (0x1<<20) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_RES_CONTROLER_POP_ERROR .
42240     #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR_SHIFT                                20
42241     #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR                                     (0x1<<21) // This bit masks, when set, the Interrupt bit: QM_REG_INT_STS.QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR .
42242     #define QM_REG_INT_MASK_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR_SHIFT                               21
42243 #define QM_REG_INT_STS_WR                                                                            0x2f0188UL //Access:WR   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
42244     #define QM_REG_INT_STS_WR_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
42245     #define QM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                    0
42246     #define QM_REG_INT_STS_WR_OVF_ERR_TX                                                             (0x1<<1) // Over flow occurs on the TX Queue.
42247     #define QM_REG_INT_STS_WR_OVF_ERR_TX_SHIFT                                                       1
42248     #define QM_REG_INT_STS_WR_OVF_ERR_OTHER                                                          (0x1<<2) // Over flow occurs on the Other Queue.
42249     #define QM_REG_INT_STS_WR_OVF_ERR_OTHER_SHIFT                                                    2
42250     #define QM_REG_INT_STS_WR_PF_USG_CNT_ERR                                                         (0x1<<3) // Overflow of pf usage counter.
42251     #define QM_REG_INT_STS_WR_PF_USG_CNT_ERR_SHIFT                                                   3
42252     #define QM_REG_INT_STS_WR_VF_USG_CNT_ERR                                                         (0x1<<4) // Overflow of vf usage counter.
42253     #define QM_REG_INT_STS_WR_VF_USG_CNT_ERR_SHIFT                                                   4
42254     #define QM_REG_INT_STS_WR_VOQ_CRD_INC_ERR                                                        (0x1<<5) // Increment overflow on VOQ counter.
42255     #define QM_REG_INT_STS_WR_VOQ_CRD_INC_ERR_SHIFT                                                  5
42256     #define QM_REG_INT_STS_WR_VOQ_CRD_DEC_ERR                                                        (0x1<<6) // Decrement underflow on VOQ counter.
42257     #define QM_REG_INT_STS_WR_VOQ_CRD_DEC_ERR_SHIFT                                                  6
42258     #define QM_REG_INT_STS_WR_BYTE_CRD_INC_ERR                                                       (0x1<<7) // Increment overflow on byte credit counter.
42259     #define QM_REG_INT_STS_WR_BYTE_CRD_INC_ERR_SHIFT                                                 7
42260     #define QM_REG_INT_STS_WR_BYTE_CRD_DEC_ERR                                                       (0x1<<8) // Decrement underflow on byte credit counter.
42261     #define QM_REG_INT_STS_WR_BYTE_CRD_DEC_ERR_SHIFT                                                 8
42262     #define QM_REG_INT_STS_WR_ERR_INCDEC_RLGLBLCRD                                                   (0x1<<9) // Increment or Decrement error for the RL Global counters.
42263     #define QM_REG_INT_STS_WR_ERR_INCDEC_RLGLBLCRD_SHIFT                                             9
42264     #define QM_REG_INT_STS_WR_ERR_INCDEC_RLPFCRD                                                     (0x1<<10) // Increment or Decrement error for the RL PF counters.
42265     #define QM_REG_INT_STS_WR_ERR_INCDEC_RLPFCRD_SHIFT                                               10
42266     #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQPFCRD                                                    (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
42267     #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQPFCRD_SHIFT                                              11
42268     #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQVPCRD                                                    (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
42269     #define QM_REG_INT_STS_WR_ERR_INCDEC_WFQVPCRD_SHIFT                                              12
42270     #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQLINECRD                                                  (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
42271     #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQLINECRD_SHIFT                                            13
42272     #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQBYTECRD                                                  (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
42273     #define QM_REG_INT_STS_WR_ERR_INCDEC_VOQBYTECRD_SHIFT                                            14
42274     #define QM_REG_INT_STS_WR_FIFOS_ERROR                                                            (0x1<<15) // Overflow or underflow error in one of FIFOs.
42275     #define QM_REG_INT_STS_WR_FIFOS_ERROR_SHIFT                                                      15
42276     #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR                                    (0x1<<16) // EXP PF controller pop FIFO error.
42277     #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR_SHIFT                              16
42278     #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR                                   (0x1<<17) // EXP PF controller push FIFO error.
42279     #define QM_REG_INT_STS_WR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR_SHIFT                             17
42280     #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR                                    (0x1<<18) // REQ controller pop FIFO error.
42281     #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR_SHIFT                              18
42282     #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR                                   (0x1<<19) // REQ controller push FIFO error.
42283     #define QM_REG_INT_STS_WR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR_SHIFT                             19
42284     #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR                                    (0x1<<20) // RES controller pop FIFO error.
42285     #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR_SHIFT                              20
42286     #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR                                   (0x1<<21) // RES controller push FIFO error.
42287     #define QM_REG_INT_STS_WR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR_SHIFT                             21
42288 #define QM_REG_INT_STS_CLR                                                                           0x2f018cUL //Access:RC   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
42289     #define QM_REG_INT_STS_CLR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
42290     #define QM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                   0
42291     #define QM_REG_INT_STS_CLR_OVF_ERR_TX                                                            (0x1<<1) // Over flow occurs on the TX Queue.
42292     #define QM_REG_INT_STS_CLR_OVF_ERR_TX_SHIFT                                                      1
42293     #define QM_REG_INT_STS_CLR_OVF_ERR_OTHER                                                         (0x1<<2) // Over flow occurs on the Other Queue.
42294     #define QM_REG_INT_STS_CLR_OVF_ERR_OTHER_SHIFT                                                   2
42295     #define QM_REG_INT_STS_CLR_PF_USG_CNT_ERR                                                        (0x1<<3) // Overflow of pf usage counter.
42296     #define QM_REG_INT_STS_CLR_PF_USG_CNT_ERR_SHIFT                                                  3
42297     #define QM_REG_INT_STS_CLR_VF_USG_CNT_ERR                                                        (0x1<<4) // Overflow of vf usage counter.
42298     #define QM_REG_INT_STS_CLR_VF_USG_CNT_ERR_SHIFT                                                  4
42299     #define QM_REG_INT_STS_CLR_VOQ_CRD_INC_ERR                                                       (0x1<<5) // Increment overflow on VOQ counter.
42300     #define QM_REG_INT_STS_CLR_VOQ_CRD_INC_ERR_SHIFT                                                 5
42301     #define QM_REG_INT_STS_CLR_VOQ_CRD_DEC_ERR                                                       (0x1<<6) // Decrement underflow on VOQ counter.
42302     #define QM_REG_INT_STS_CLR_VOQ_CRD_DEC_ERR_SHIFT                                                 6
42303     #define QM_REG_INT_STS_CLR_BYTE_CRD_INC_ERR                                                      (0x1<<7) // Increment overflow on byte credit counter.
42304     #define QM_REG_INT_STS_CLR_BYTE_CRD_INC_ERR_SHIFT                                                7
42305     #define QM_REG_INT_STS_CLR_BYTE_CRD_DEC_ERR                                                      (0x1<<8) // Decrement underflow on byte credit counter.
42306     #define QM_REG_INT_STS_CLR_BYTE_CRD_DEC_ERR_SHIFT                                                8
42307     #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLGLBLCRD                                                  (0x1<<9) // Increment or Decrement error for the RL Global counters.
42308     #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLGLBLCRD_SHIFT                                            9
42309     #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLPFCRD                                                    (0x1<<10) // Increment or Decrement error for the RL PF counters.
42310     #define QM_REG_INT_STS_CLR_ERR_INCDEC_RLPFCRD_SHIFT                                              10
42311     #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQPFCRD                                                   (0x1<<11) // Increment or Decrement error for the WFQ PF counters.
42312     #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQPFCRD_SHIFT                                             11
42313     #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQVPCRD                                                   (0x1<<12) // Increment or Decrement error for the WFQ VP counters.
42314     #define QM_REG_INT_STS_CLR_ERR_INCDEC_WFQVPCRD_SHIFT                                             12
42315     #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQLINECRD                                                 (0x1<<13) // Increment or Decrement error for the VOQ Line counters.
42316     #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQLINECRD_SHIFT                                           13
42317     #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQBYTECRD                                                 (0x1<<14) // Increment or Decrement error for the VOQ Byte counters.
42318     #define QM_REG_INT_STS_CLR_ERR_INCDEC_VOQBYTECRD_SHIFT                                           14
42319     #define QM_REG_INT_STS_CLR_FIFOS_ERROR                                                           (0x1<<15) // Overflow or underflow error in one of FIFOs.
42320     #define QM_REG_INT_STS_CLR_FIFOS_ERROR_SHIFT                                                     15
42321     #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR                                   (0x1<<16) // EXP PF controller pop FIFO error.
42322     #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_POP_ERROR_SHIFT                             16
42323     #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR                                  (0x1<<17) // EXP PF controller push FIFO error.
42324     #define QM_REG_INT_STS_CLR_QM_RL_DC_EXP_PF_CONTROLER_PUSH_ERROR_SHIFT                            17
42325     #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR                                   (0x1<<18) // REQ controller pop FIFO error.
42326     #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_POP_ERROR_SHIFT                             18
42327     #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR                                  (0x1<<19) // REQ controller push FIFO error.
42328     #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_REQ_CONTROLER_PUSH_ERROR_SHIFT                            19
42329     #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR                                   (0x1<<20) // RES controller pop FIFO error.
42330     #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_POP_ERROR_SHIFT                             20
42331     #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR                                  (0x1<<21) // RES controller push FIFO error.
42332     #define QM_REG_INT_STS_CLR_QM_RL_DC_RF_RES_CONTROLER_PUSH_ERROR_SHIFT                            21
42333 #define QM_REG_PRTY_MASK                                                                             0x2f0194UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
42334     #define QM_REG_PRTY_MASK_XCM_WRC_FIFO                                                            (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.XCM_WRC_FIFO .
42335     #define QM_REG_PRTY_MASK_XCM_WRC_FIFO_SHIFT                                                      0
42336     #define QM_REG_PRTY_MASK_UCM_WRC_FIFO                                                            (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.UCM_WRC_FIFO .
42337     #define QM_REG_PRTY_MASK_UCM_WRC_FIFO_SHIFT                                                      1
42338     #define QM_REG_PRTY_MASK_TCM_WRC_FIFO                                                            (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.TCM_WRC_FIFO .
42339     #define QM_REG_PRTY_MASK_TCM_WRC_FIFO_SHIFT                                                      2
42340     #define QM_REG_PRTY_MASK_CCM_WRC_FIFO                                                            (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.CCM_WRC_FIFO .
42341     #define QM_REG_PRTY_MASK_CCM_WRC_FIFO_SHIFT                                                      3
42342     #define QM_REG_PRTY_MASK_BIGRAMHIGH                                                              (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMHIGH .
42343     #define QM_REG_PRTY_MASK_BIGRAMHIGH_SHIFT                                                        4
42344     #define QM_REG_PRTY_MASK_BIGRAMLOW                                                               (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMLOW .
42345     #define QM_REG_PRTY_MASK_BIGRAMLOW_SHIFT                                                         5
42346     #define QM_REG_PRTY_MASK_BASE_ADDRESS                                                            (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BASE_ADDRESS .
42347     #define QM_REG_PRTY_MASK_BASE_ADDRESS_SHIFT                                                      6
42348     #define QM_REG_PRTY_MASK_WRBUFF                                                                  (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.WRBUFF .
42349     #define QM_REG_PRTY_MASK_WRBUFF_SHIFT                                                            7
42350     #define QM_REG_PRTY_MASK_BIGRAMHIGH_EXT_A                                                        (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMHIGH_EXT_A .
42351     #define QM_REG_PRTY_MASK_BIGRAMHIGH_EXT_A_SHIFT                                                  8
42352     #define QM_REG_PRTY_MASK_BIGRAMLOW_EXT_A                                                         (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BIGRAMLOW_EXT_A .
42353     #define QM_REG_PRTY_MASK_BIGRAMLOW_EXT_A_SHIFT                                                   9
42354     #define QM_REG_PRTY_MASK_BASE_ADDRESS_EXT_A                                                      (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS.BASE_ADDRESS_EXT_A .
42355     #define QM_REG_PRTY_MASK_BASE_ADDRESS_EXT_A_SHIFT                                                10
42356 #define QM_REG_PRTY_MASK_H_0                                                                         0x2f0204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
42357     #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
42358     #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_SHIFT                                         0
42359     #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
42360     #define QM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_SHIFT                                         1
42361     #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT                                               (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
42362     #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT                                         2
42363     #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT                                               (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
42364     #define QM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT                                         3
42365     #define QM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT                                                 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
42366     #define QM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_SHIFT                                           4
42367     #define QM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY                                                   (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
42368     #define QM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_SHIFT                                             5
42369     #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_A0                                             (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
42370     #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_A0_SHIFT                                       23
42371     #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_B0                                             (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
42372     #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_B0_SHIFT                                       6
42373     #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_K2                                                (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
42374     #define QM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_K2_SHIFT                                          6
42375     #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY                                                   (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
42376     #define QM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_SHIFT                                             7
42377     #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY                                                   (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
42378     #define QM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_SHIFT                                             8
42379     #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY                                                   (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
42380     #define QM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_SHIFT                                             9
42381     #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY                                                   (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
42382     #define QM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_SHIFT                                             10
42383     #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY                                                   (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
42384     #define QM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_SHIFT                                             11
42385     #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY                                                   (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
42386     #define QM_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_SHIFT                                             12
42387     #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY                                                   (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
42388     #define QM_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_SHIFT                                             13
42389     #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY                                                   (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
42390     #define QM_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_SHIFT                                             14
42391     #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY                                                   (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
42392     #define QM_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_SHIFT                                             15
42393     #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY                                                   (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
42394     #define QM_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_SHIFT                                             16
42395     #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY                                                   (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
42396     #define QM_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_SHIFT                                             17
42397     #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY                                                   (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
42398     #define QM_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_SHIFT                                             18
42399     #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY                                                   (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
42400     #define QM_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_SHIFT                                             19
42401     #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY                                                   (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
42402     #define QM_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_SHIFT                                             20
42403     #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY                                                   (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
42404     #define QM_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_SHIFT                                             21
42405     #define QM_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY                                                   (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
42406     #define QM_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_SHIFT                                             22
42407     #define QM_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY                                                   (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
42408     #define QM_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_SHIFT                                             23
42409     #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_A0                                             (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
42410     #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_A0_SHIFT                                       19
42411     #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_B0                                             (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
42412     #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_BB_B0_SHIFT                                       24
42413     #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2                                                (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
42414     #define QM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_K2_SHIFT                                          24
42415     #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_A0                                             (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
42416     #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_A0_SHIFT                                       21
42417     #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_B0                                             (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
42418     #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_BB_B0_SHIFT                                       25
42419     #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2                                                (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
42420     #define QM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_K2_SHIFT                                          25
42421     #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_A0                                             (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
42422     #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_A0_SHIFT                                       17
42423     #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0                                             (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
42424     #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0_SHIFT                                       26
42425     #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                                (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
42426     #define QM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                          26
42427     #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_A0                                             (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
42428     #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_A0_SHIFT                                       20
42429     #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_B0                                             (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
42430     #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_B0_SHIFT                                       27
42431     #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2                                                (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
42432     #define QM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_SHIFT                                          27
42433     #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_A0                                             (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
42434     #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_A0_SHIFT                                       18
42435     #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_B0                                             (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
42436     #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_BB_B0_SHIFT                                       28
42437     #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2                                                (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
42438     #define QM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_K2_SHIFT                                          28
42439     #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_A0                                             (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
42440     #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_A0_SHIFT                                       22
42441     #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_B0                                             (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
42442     #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_B0_SHIFT                                       29
42443     #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2                                                (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
42444     #define QM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT                                          29
42445     #define QM_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY                                                   (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
42446     #define QM_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_SHIFT                                             30
42447     #define QM_REG_PRTY_MASK_H_0_MEM042_I_ECC_0_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM042_I_ECC_0_RF_INT .
42448     #define QM_REG_PRTY_MASK_H_0_MEM042_I_ECC_0_RF_INT_SHIFT                                         0
42449     #define QM_REG_PRTY_MASK_H_0_MEM042_I_ECC_1_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM042_I_ECC_1_RF_INT .
42450     #define QM_REG_PRTY_MASK_H_0_MEM042_I_ECC_1_RF_INT_SHIFT                                         1
42451     #define QM_REG_PRTY_MASK_H_0_MEM041_I_ECC_0_RF_INT                                               (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM041_I_ECC_0_RF_INT .
42452     #define QM_REG_PRTY_MASK_H_0_MEM041_I_ECC_0_RF_INT_SHIFT                                         2
42453     #define QM_REG_PRTY_MASK_H_0_MEM041_I_ECC_1_RF_INT                                               (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM041_I_ECC_1_RF_INT .
42454     #define QM_REG_PRTY_MASK_H_0_MEM041_I_ECC_1_RF_INT_SHIFT                                         3
42455     #define QM_REG_PRTY_MASK_H_0_MEM048_I_ECC_RF_INT                                                 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM048_I_ECC_RF_INT .
42456     #define QM_REG_PRTY_MASK_H_0_MEM048_I_ECC_RF_INT_SHIFT                                           4
42457     #define QM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                   (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
42458     #define QM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                             5
42459     #define QM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                   (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
42460     #define QM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                             6
42461     #define QM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                   (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
42462     #define QM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                             7
42463     #define QM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                   (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
42464     #define QM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                             8
42465     #define QM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                                   (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
42466     #define QM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                             9
42467     #define QM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY                                                   (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
42468     #define QM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT                                             10
42469     #define QM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                                   (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
42470     #define QM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                             11
42471     #define QM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY                                                   (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
42472     #define QM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_SHIFT                                             12
42473     #define QM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY                                                   (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
42474     #define QM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_SHIFT                                             13
42475     #define QM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY                                                   (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
42476     #define QM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_SHIFT                                             14
42477     #define QM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY                                                   (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
42478     #define QM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT                                             15
42479     #define QM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY                                                   (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
42480     #define QM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_SHIFT                                             16
42481     #define QM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                   (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
42482     #define QM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                             24
42483     #define QM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                   (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
42484     #define QM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                             25
42485     #define QM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                   (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
42486     #define QM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                             26
42487     #define QM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                   (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
42488     #define QM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                             27
42489     #define QM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                   (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
42490     #define QM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                             28
42491     #define QM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                   (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
42492     #define QM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                             29
42493     #define QM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY                                                   (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
42494     #define QM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_SHIFT                                             30
42495 #define QM_REG_PRTY_MASK_H_1                                                                         0x2f0214UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
42496     #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_BB_A0                                             (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
42497     #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_BB_A0_SHIFT                                       12
42498     #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_BB_B0                                             (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
42499     #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_BB_B0_SHIFT                                       0
42500     #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2                                                (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
42501     #define QM_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_K2_SHIFT                                          0
42502     #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_A0                                             (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
42503     #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_A0_SHIFT                                       15
42504     #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_B0                                             (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
42505     #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_BB_B0_SHIFT                                       1
42506     #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2                                                (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
42507     #define QM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_K2_SHIFT                                          1
42508     #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY                                                   (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
42509     #define QM_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_SHIFT                                             2
42510     #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_A0                                             (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
42511     #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_A0_SHIFT                                       14
42512     #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_B0                                             (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
42513     #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_B0_SHIFT                                       3
42514     #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2                                                (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
42515     #define QM_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2_SHIFT                                          3
42516     #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_A0                                             (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
42517     #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_A0_SHIFT                                       21
42518     #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_B0                                             (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
42519     #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_BB_B0_SHIFT                                       4
42520     #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2                                                (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
42521     #define QM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_K2_SHIFT                                          4
42522     #define QM_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY                                                   (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
42523     #define QM_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_SHIFT                                             5
42524     #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY                                                   (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
42525     #define QM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_SHIFT                                             6
42526     #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY                                                   (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY .
42527     #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_SHIFT                                             7
42528     #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_A0                                             (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
42529     #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_A0_SHIFT                                       27
42530     #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_B0                                             (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
42531     #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_BB_B0_SHIFT                                       8
42532     #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2                                                (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
42533     #define QM_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_K2_SHIFT                                          8
42534     #define QM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY                                                   (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
42535     #define QM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_SHIFT                                             9
42536     #define QM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY                                                   (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
42537     #define QM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_SHIFT                                             10
42538     #define QM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY                                                   (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
42539     #define QM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_SHIFT                                             11
42540     #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY                                                   (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
42541     #define QM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_SHIFT                                             12
42542     #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_A0                                             (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
42543     #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                       5
42544     #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_B0                                             (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
42545     #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                       13
42546     #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_K2                                                (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
42547     #define QM_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_K2_SHIFT                                          13
42548     #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_A0                                             (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
42549     #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                       8
42550     #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_B0                                             (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
42551     #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                       14
42552     #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2                                                (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
42553     #define QM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_K2_SHIFT                                          14
42554     #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY                                                   (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
42555     #define QM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_SHIFT                                             15
42556     #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_A0                                             (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
42557     #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_A0_SHIFT                                       1
42558     #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_B0                                             (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
42559     #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_B0_SHIFT                                       16
42560     #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_K2                                                (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
42561     #define QM_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_K2_SHIFT                                          16
42562     #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_A0                                             (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
42563     #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_A0_SHIFT                                       3
42564     #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_B0                                             (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
42565     #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_BB_B0_SHIFT                                       17
42566     #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_K2                                                (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
42567     #define QM_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_K2_SHIFT                                          17
42568     #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_A0                                             (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
42569     #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                       0
42570     #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_B0                                             (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
42571     #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                       18
42572     #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2                                                (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
42573     #define QM_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2_SHIFT                                          18
42574     #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_A0                                             (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
42575     #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                       6
42576     #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_B0                                             (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
42577     #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                       19
42578     #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2                                                (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
42579     #define QM_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2_SHIFT                                          19
42580     #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_A0                                             (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
42581     #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_A0_SHIFT                                       7
42582     #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_B0                                             (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
42583     #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_BB_B0_SHIFT                                       20
42584     #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_K2                                                (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
42585     #define QM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_K2_SHIFT                                          20
42586     #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY                                                   (0x1<<21) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
42587     #define QM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_SHIFT                                             21
42588     #define QM_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY                                                   (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
42589     #define QM_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_SHIFT                                             22
42590     #define QM_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY                                                   (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
42591     #define QM_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_SHIFT                                             23
42592     #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_A0                                             (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
42593     #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_A0_SHIFT                                       4
42594     #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_B0                                             (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
42595     #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_B0_SHIFT                                       24
42596     #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_K2                                                (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
42597     #define QM_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_K2_SHIFT                                          24
42598     #define QM_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY                                                   (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
42599     #define QM_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_SHIFT                                             25
42600     #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_A0                                             (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
42601     #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                       2
42602     #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_B0                                             (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
42603     #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                       26
42604     #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_K2                                                (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
42605     #define QM_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_K2_SHIFT                                          26
42606     #define QM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY                                                   (0x1<<27) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
42607     #define QM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_SHIFT                                             27
42608     #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_0                                                 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_0 .
42609     #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_0_SHIFT                                           28
42610     #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_1                                                 (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_1 .
42611     #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_1_SHIFT                                           29
42612     #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_2                                                 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY_2 .
42613     #define QM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_2_SHIFT                                           30
42614     #define QM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY                                                   (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
42615     #define QM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_SHIFT                                             9
42616     #define QM_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY                                                   (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM040_I_MEM_PRTY .
42617     #define QM_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_SHIFT                                             10
42618     #define QM_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY                                                   (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM039_I_MEM_PRTY .
42619     #define QM_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_SHIFT                                             11
42620     #define QM_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY                                                   (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
42621     #define QM_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_SHIFT                                             13
42622     #define QM_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY                                                   (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
42623     #define QM_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_SHIFT                                             16
42624     #define QM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY                                                   (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
42625     #define QM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_SHIFT                                             17
42626     #define QM_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY                                                   (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
42627     #define QM_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_SHIFT                                             18
42628     #define QM_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY                                                   (0x1<<19) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
42629     #define QM_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_SHIFT                                             19
42630     #define QM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY                                                   (0x1<<20) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
42631     #define QM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_SHIFT                                             20
42632     #define QM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY                                                   (0x1<<22) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
42633     #define QM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_SHIFT                                             22
42634     #define QM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY                                                   (0x1<<23) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
42635     #define QM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_SHIFT                                             23
42636     #define QM_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY                                                   (0x1<<24) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
42637     #define QM_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_SHIFT                                             24
42638     #define QM_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY                                                   (0x1<<25) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
42639     #define QM_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_SHIFT                                             25
42640     #define QM_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY                                                   (0x1<<26) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
42641     #define QM_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_SHIFT                                             26
42642     #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_0                                                 (0x1<<28) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY_0 .
42643     #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_0_SHIFT                                           28
42644     #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_1                                                 (0x1<<29) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY_1 .
42645     #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_1_SHIFT                                           29
42646     #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_2                                                 (0x1<<30) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY_2 .
42647     #define QM_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_2_SHIFT                                           30
42648 #define QM_REG_PRTY_MASK_H_2                                                                         0x2f0224UL //Access:RW   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
42649     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_3                                                 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_3 .
42650     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_3_SHIFT                                           0
42651     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_4                                                 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_4 .
42652     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_4_SHIFT                                           1
42653     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_5                                                 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_5 .
42654     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_5_SHIFT                                           2
42655     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_6                                                 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_6 .
42656     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_6_SHIFT                                           3
42657     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_7                                                 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_7 .
42658     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_7_SHIFT                                           4
42659     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_8                                                 (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_8 .
42660     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_8_SHIFT                                           5
42661     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_9                                                 (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_9 .
42662     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_9_SHIFT                                           6
42663     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_10                                                (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_10 .
42664     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_10_SHIFT                                          7
42665     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_11                                                (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_11 .
42666     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_11_SHIFT                                          8
42667     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_12                                                (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_12 .
42668     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_12_SHIFT                                          9
42669     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_13                                                (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_13 .
42670     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_13_SHIFT                                          10
42671     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_14                                                (0x1<<11) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_14 .
42672     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_14_SHIFT                                          11
42673     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_15                                                (0x1<<12) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY_15 .
42674     #define QM_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_15_SHIFT                                          12
42675     #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB_B0                                             (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY .
42676     #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_BB_B0_SHIFT                                       5
42677     #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_K2                                                (0x1<<13) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY .
42678     #define QM_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_K2_SHIFT                                          13
42679     #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY_BB_B0                                             (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM001_I_MEM_PRTY .
42680     #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                       6
42681     #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY_K2                                                (0x1<<14) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM001_I_MEM_PRTY .
42682     #define QM_REG_PRTY_MASK_H_2_MEM001_I_MEM_PRTY_K2_SHIFT                                          14
42683     #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB_B0                                             (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY .
42684     #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_BB_B0_SHIFT                                       7
42685     #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_K2                                                (0x1<<15) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY .
42686     #define QM_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_K2_SHIFT                                          15
42687     #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_BB_B0                                             (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM002_I_MEM_PRTY .
42688     #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                       8
42689     #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_K2                                                (0x1<<16) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM002_I_MEM_PRTY .
42690     #define QM_REG_PRTY_MASK_H_2_MEM002_I_MEM_PRTY_K2_SHIFT                                          16
42691     #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_BB_B0                                             (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY .
42692     #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_BB_B0_SHIFT                                       9
42693     #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_K2                                                (0x1<<17) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY .
42694     #define QM_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_K2_SHIFT                                          17
42695     #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_BB_B0                                             (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM009_I_MEM_PRTY .
42696     #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_BB_B0_SHIFT                                       10
42697     #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_K2                                                (0x1<<18) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM009_I_MEM_PRTY .
42698     #define QM_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_K2_SHIFT                                          18
42699     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_3                                                 (0x1<<0) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM043_I_MEM_PRTY_3 .
42700     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_3_SHIFT                                           0
42701     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_4                                                 (0x1<<1) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM043_I_MEM_PRTY_4 .
42702     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_4_SHIFT                                           1
42703     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_5                                                 (0x1<<2) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM043_I_MEM_PRTY_5 .
42704     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_5_SHIFT                                           2
42705     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_6                                                 (0x1<<3) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM043_I_MEM_PRTY_6 .
42706     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_6_SHIFT                                           3
42707     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_7                                                 (0x1<<4) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM043_I_MEM_PRTY_7 .
42708     #define QM_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_7_SHIFT                                           4
42709     #define QM_REG_PRTY_MASK_H_2_MEM063_I_MEM_PRTY                                                   (0x1<<5) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM063_I_MEM_PRTY .
42710     #define QM_REG_PRTY_MASK_H_2_MEM063_I_MEM_PRTY_SHIFT                                             5
42711     #define QM_REG_PRTY_MASK_H_2_MEM037_I_MEM_PRTY                                                   (0x1<<6) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM037_I_MEM_PRTY .
42712     #define QM_REG_PRTY_MASK_H_2_MEM037_I_MEM_PRTY_SHIFT                                             6
42713     #define QM_REG_PRTY_MASK_H_2_MEM064_I_MEM_PRTY                                                   (0x1<<7) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM064_I_MEM_PRTY .
42714     #define QM_REG_PRTY_MASK_H_2_MEM064_I_MEM_PRTY_SHIFT                                             7
42715     #define QM_REG_PRTY_MASK_H_2_MEM038_I_MEM_PRTY                                                   (0x1<<8) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM038_I_MEM_PRTY .
42716     #define QM_REG_PRTY_MASK_H_2_MEM038_I_MEM_PRTY_SHIFT                                             8
42717     #define QM_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY                                                   (0x1<<9) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM046_I_MEM_PRTY .
42718     #define QM_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_SHIFT                                             9
42719     #define QM_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY                                                   (0x1<<10) // This bit masks, when set, the Parity bit: QM_REG_PRTY_STS_H_2.MEM045_I_MEM_PRTY .
42720     #define QM_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_SHIFT                                             10
42721 #define QM_REG_MEM_ECC_EVENTS                                                                        0x2f023cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
42722 #define QM_REG_MEM039_I_MEM_DFT_K2                                                                   0x2f024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_pxp_wdata_fifo_tx.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42723 #define QM_REG_MEM038_I_MEM_DFT_K2                                                                   0x2f0250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_pxp_wdata_fifo_other.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42724 #define QM_REG_MEM040_I_MEM_DFT_K2                                                                   0x2f0254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_rl_glbl_crd.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42725 #define QM_REG_MEM042_I_MEM_DFT_K2                                                                   0x2f0258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_rl_glbl_ubound.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42726 #define QM_REG_MEM041_I_MEM_DFT_K2                                                                   0x2f025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_rl_glbl_inc_val.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42727 #define QM_REG_MEM051_I_MEM_DFT_K2                                                                   0x2f0260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_wrc_fifo_xcm_tx.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42728 #define QM_REG_MEM047_I_MEM_DFT_K2                                                                   0x2f0264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_wrc_fifo_mcm_other.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42729 #define QM_REG_MEM049_I_MEM_DFT_K2                                                                   0x2f0268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_wrc_fifo_ucm_other.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42730 #define QM_REG_MEM048_I_MEM_DFT_K2                                                                   0x2f026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_wrc_fifo_tcm_other.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42731 #define QM_REG_MEM052_I_MEM_DFT_K2                                                                   0x2f0270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_wrc_fifo_ycm_other.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42732 #define QM_REG_MEM050_I_MEM_DFT_K2                                                                   0x2f0274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_wrc_fifo_xcm_other.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42733 #define QM_REG_MEM045_I_MEM_DFT_K2                                                                   0x2f0278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_sync_rl_rf_req.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
42734 #define QM_REG_MEM046_I_MEM_DFT_K2                                                                   0x2f027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_sync_rl_rf_res.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
42735 #define QM_REG_MEM043_I_MEM_DFT_K2                                                                   0x2f0280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_sync_rl_glbl_exp.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
42736 #define QM_REG_MEM044_I_MEM_DFT_K2                                                                   0x2f0284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.i_qm_mem_sync_rl_pf_exp.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
42737 #define QM_REG_MEM004_I_MEM_DFT_K2                                                                   0x2f0288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_BASE_ADDR_TX_PQ_512PQTX_IF.i_qm_mem_base_addr_tx_pq.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42738 #define QM_REG_MEM003_I_MEM_DFT_K2                                                                   0x2f028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_BASE_ADDR_OTHER_PQ_128PQOTHER_IF.i_qm_mem_base_addr_other_pq.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42739 #define QM_REG_MEM006_I_MEM_DFT_K2                                                                   0x2f0290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_BIGRAM_TX_512PQTX_IF.i_qm_mem_bigram_tx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
42740 #define QM_REG_MEM005_I_MEM_DFT_K2                                                                   0x2f0294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_BIGRAM_OTHER_128PQOTHER_IF.i_qm_mem_bigram_other.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
42741 #define QM_REG_MEM012_I_MEM_DFT_K2                                                                   0x2f0298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_PTR_TBL_TX_PQ_512PQTX_IF.i_qm_mem_ptr_tbl_tx_pq.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42742 #define QM_REG_MEM011_I_MEM_DFT_K2                                                                   0x2f029cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_PTR_TBL_OTHER_PQ_128PQOTHER_IF.i_qm_mem_ptr_tbl_other_pq.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42743 #define QM_REG_MEM013_I_MEM_DFT_K2                                                                   0x2f02a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_RL_PF_CRD_16PF_IF.i_qm_mem_rl_pf_crd.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42744 #define QM_REG_MEM021_I_MEM_DFT_K2                                                                   0x2f02a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_WFQ_PF_CRD_16PF_IF.i_qm_mem_wfq_pf_crd.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42745 #define QM_REG_MEM024_I_MEM_DFT_K2                                                                   0x2f02a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_WFQ_VP_CRD_512PQTX_IF.i_qm_mem_wfq_vp_crd.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42746 #define QM_REG_MEM015_I_MEM_DFT_K2                                                                   0x2f02acUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_RL_PF_UBOUND_16PF_IF.i_qm_mem_rl_pf_ubound.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42747 #define QM_REG_MEM026_I_MEM_DFT_K2                                                                   0x2f02b0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_WFQ_VP_WEIGHT_512PQTX_IF.i_qm_mem_wfq_vp_weight.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42748 #define QM_REG_MEM022_I_MEM_DFT_K2                                                                   0x2f02b4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_WFQ_PF_UBOUND_16PF_IF.i_qm_mem_wfq_pf_ubound.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42749 #define QM_REG_MEM025_I_MEM_DFT_K2                                                                   0x2f02b8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_WFQ_VP_UBOUND_512PQTX_IF.i_qm_mem_wfq_vp_ubound.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42750 #define QM_REG_MEM020_I_MEM_DFT_K2                                                                   0x2f02bcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_VP_ARB_LAST_GNT_16PF_20VOQ_IF.i_qm_mem_vp_arb_last_gnt.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
42751 #define QM_REG_MEM008_I_MEM_DFT_K2                                                                   0x2f02c0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_PQ_ARB_LAST_GNT_512PQ_TX_IF.i_qm_mem_pq_arb_last_gnt_tx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
42752 #define QM_REG_MEM007_I_MEM_DFT_K2                                                                   0x2f02c4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_CM_INT_Q_MASK_128PQOTHER_IF.i_qm_mem_cm_int_q_mask.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42753 #define QM_REG_MEM028_I_MEM_DFT_K2                                                                   0x2f02c8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.TX_QM_MEM_VF_USG_CNT_192VF_IF.i_qm_mem_usg_cnt_vf_tx.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42754 #define QM_REG_MEM002_I_MEM_DFT_K2                                                                   0x2f02ccUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.OTHER_QM_MEM_VF_USG_CNT_192VF_IF.i_qm_mem_usg_cnt_vf_other.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42755 #define QM_REG_MEM010_I_MEM_DFT_K2                                                                   0x2f02d0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_PQ_FILL_LVL_TX_PQ_512PQTX_IF.i_qm_mem_pq_fill_lvl_tx_pq_512pqtx.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42756 #define QM_REG_MEM009_I_MEM_DFT                                                                      0x2f02d4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance qm.QM_MEM_PQ_FILL_LVL_OTHER_PQ_128PQOTHER_IF.i_qm_mem_pq_fill_lvl_other_pq_128pqother.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
42757 #define QM_REG_WRC_DROP_CNT_0                                                                        0x2f0400UL //Access:R    DataWidth:0x8   drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42758 #define QM_REG_WRC_DROP_CNT_1                                                                        0x2f0404UL //Access:R    DataWidth:0x8   drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42759 #define QM_REG_WRC_DROP_CNT_2                                                                        0x2f0408UL //Access:R    DataWidth:0x8   drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42760 #define QM_REG_WRC_DROP_CNT_3                                                                        0x2f040cUL //Access:R    DataWidth:0x8   drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42761 #define QM_REG_WRC_DROP_CNT_4                                                                        0x2f0410UL //Access:R    DataWidth:0x8   drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42762 #define QM_REG_WRC_DROP_CNT_5                                                                        0x2f0414UL //Access:R    DataWidth:0x8   drop counter per write client fifo i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42763 #define QM_REG_WRC_FIFOLVL_0                                                                         0x2f0418UL //Access:R    DataWidth:0x5   Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42764 #define QM_REG_WRC_FIFOLVL_1                                                                         0x2f041cUL //Access:R    DataWidth:0x5   Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42765 #define QM_REG_WRC_FIFOLVL_2                                                                         0x2f0420UL //Access:R    DataWidth:0x5   Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42766 #define QM_REG_WRC_FIFOLVL_3                                                                         0x2f0424UL //Access:R    DataWidth:0x5   Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42767 #define QM_REG_WRC_FIFOLVL_4                                                                         0x2f0428UL //Access:R    DataWidth:0x5   Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42768 #define QM_REG_WRC_FIFOLVL_5                                                                         0x2f042cUL //Access:R    DataWidth:0x5   Keep the fill level of the fifo from write client. i: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42769 #define QM_REG_CM_PUSH_INT_EN                                                                        0x2f0430UL //Access:RW   DataWidth:0x6   Enable the write client. Bit: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X (other); 5 = X (tx).  Chips: BB_A0 BB_B0 K2
42770 #define QM_REG_MAXPQSIZE_0                                                                           0x2f0434UL //Access:RW   DataWidth:0x10  The number of connections divided by 256 minus 1 which dictates the size of the queues which belong to the function for TX queues. There are 2 different values per fucntion and each PQ that belongs to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN  Chips: BB_A0 BB_B0 K2
42771 #define QM_REG_MAXPQSIZE_1                                                                           0x2f0438UL //Access:RW   DataWidth:0x10  The number of connections divided by 256 minus 1 which dictates the size of the queues which belong to the function for TX queues. There are 2 different values per fucntion and each PQ that belongs to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN  Chips: BB_A0 BB_B0 K2
42772 #define QM_REG_MAXPQSIZE_2                                                                           0x2f043cUL //Access:RW   DataWidth:0x10  The number of connections divided by 256 minus 1 which dictates the size of the queues which belong to the function for Other queues. There is single values per fucntion and each PQ that belongs to the function can be associated with one of the values. values: 0: 256; 1: 512; ...; N-1: 256xN  Chips: BB_A0 BB_B0 K2
42773 #define QM_REG_MAXPQSIZETXSEL_0                                                                      0x2f0440UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42774 #define QM_REG_MAXPQSIZETXSEL_1                                                                      0x2f0444UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42775 #define QM_REG_MAXPQSIZETXSEL_2                                                                      0x2f0448UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42776 #define QM_REG_MAXPQSIZETXSEL_3                                                                      0x2f044cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42777 #define QM_REG_MAXPQSIZETXSEL_4                                                                      0x2f0450UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42778 #define QM_REG_MAXPQSIZETXSEL_5                                                                      0x2f0454UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42779 #define QM_REG_MAXPQSIZETXSEL_6                                                                      0x2f0458UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42780 #define QM_REG_MAXPQSIZETXSEL_7                                                                      0x2f045cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42781 #define QM_REG_MAXPQSIZETXSEL_8                                                                      0x2f0460UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42782 #define QM_REG_MAXPQSIZETXSEL_9                                                                      0x2f0464UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42783 #define QM_REG_MAXPQSIZETXSEL_10                                                                     0x2f0468UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42784 #define QM_REG_MAXPQSIZETXSEL_11                                                                     0x2f046cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42785 #define QM_REG_MAXPQSIZETXSEL_12                                                                     0x2f0470UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42786 #define QM_REG_MAXPQSIZETXSEL_13                                                                     0x2f0474UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_A0 BB_B0 K2
42787 #define QM_REG_MAXPQSIZETXSEL_14                                                                     0x2f0478UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42788 #define QM_REG_MAXPQSIZETXSEL_15                                                                     0x2f047cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42789 #define QM_REG_MAXPQSIZETXSEL_16                                                                     0x2f0480UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42790 #define QM_REG_MAXPQSIZETXSEL_17                                                                     0x2f0484UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42791 #define QM_REG_MAXPQSIZETXSEL_18                                                                     0x2f0488UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42792 #define QM_REG_MAXPQSIZETXSEL_19                                                                     0x2f048cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42793 #define QM_REG_MAXPQSIZETXSEL_20                                                                     0x2f0490UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42794 #define QM_REG_MAXPQSIZETXSEL_21                                                                     0x2f0494UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42795 #define QM_REG_MAXPQSIZETXSEL_22                                                                     0x2f0498UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42796 #define QM_REG_MAXPQSIZETXSEL_23                                                                     0x2f049cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42797 #define QM_REG_MAXPQSIZETXSEL_24                                                                     0x2f04a0UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42798 #define QM_REG_MAXPQSIZETXSEL_25                                                                     0x2f04a4UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42799 #define QM_REG_MAXPQSIZETXSEL_26                                                                     0x2f04a8UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42800 #define QM_REG_MAXPQSIZETXSEL_27                                                                     0x2f04acUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42801 #define QM_REG_MAXPQSIZETXSEL_28                                                                     0x2f04b0UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42802 #define QM_REG_MAXPQSIZETXSEL_29                                                                     0x2f04b4UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42803 #define QM_REG_MAXPQSIZETXSEL_30                                                                     0x2f04b8UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42804 #define QM_REG_MAXPQSIZETXSEL_31                                                                     0x2f04bcUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42805 #define QM_REG_MAXPQSIZETXSEL_32                                                                     0x2f04c0UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42806 #define QM_REG_MAXPQSIZETXSEL_33                                                                     0x2f04c4UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42807 #define QM_REG_MAXPQSIZETXSEL_34                                                                     0x2f04c8UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42808 #define QM_REG_MAXPQSIZETXSEL_35                                                                     0x2f04ccUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42809 #define QM_REG_MAXPQSIZETXSEL_36                                                                     0x2f04d0UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42810 #define QM_REG_MAXPQSIZETXSEL_37                                                                     0x2f04d4UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42811 #define QM_REG_MAXPQSIZETXSEL_38                                                                     0x2f04d8UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42812 #define QM_REG_MAXPQSIZETXSEL_39                                                                     0x2f04dcUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42813 #define QM_REG_MAXPQSIZETXSEL_40                                                                     0x2f04e0UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42814 #define QM_REG_MAXPQSIZETXSEL_41                                                                     0x2f04e4UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42815 #define QM_REG_MAXPQSIZETXSEL_42                                                                     0x2f04e8UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42816 #define QM_REG_MAXPQSIZETXSEL_43                                                                     0x2f04ecUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42817 #define QM_REG_MAXPQSIZETXSEL_44                                                                     0x2f04f0UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42818 #define QM_REG_MAXPQSIZETXSEL_45                                                                     0x2f04f4UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42819 #define QM_REG_MAXPQSIZETXSEL_46                                                                     0x2f04f8UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42820 #define QM_REG_MAXPQSIZETXSEL_47                                                                     0x2f04fcUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42821 #define QM_REG_MAXPQSIZETXSEL_48                                                                     0x2f0500UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42822 #define QM_REG_MAXPQSIZETXSEL_49                                                                     0x2f0504UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42823 #define QM_REG_MAXPQSIZETXSEL_50                                                                     0x2f0508UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42824 #define QM_REG_MAXPQSIZETXSEL_51                                                                     0x2f050cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42825 #define QM_REG_MAXPQSIZETXSEL_52                                                                     0x2f0510UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42826 #define QM_REG_MAXPQSIZETXSEL_53                                                                     0x2f0514UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42827 #define QM_REG_MAXPQSIZETXSEL_54                                                                     0x2f0518UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42828 #define QM_REG_MAXPQSIZETXSEL_55                                                                     0x2f051cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: BB_B0 K2
42829 #define QM_REG_MAXPQSIZETXSEL_56                                                                     0x2f0520UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: K2
42830 #define QM_REG_MAXPQSIZETXSEL_57                                                                     0x2f0524UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: K2
42831 #define QM_REG_MAXPQSIZETXSEL_58                                                                     0x2f0528UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: K2
42832 #define QM_REG_MAXPQSIZETXSEL_59                                                                     0x2f052cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: K2
42833 #define QM_REG_MAXPQSIZETXSEL_60                                                                     0x2f0530UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: K2
42834 #define QM_REG_MAXPQSIZETXSEL_61                                                                     0x2f0534UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: K2
42835 #define QM_REG_MAXPQSIZETXSEL_62                                                                     0x2f0538UL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: K2
42836 #define QM_REG_MAXPQSIZETXSEL_63                                                                     0x2f053cUL //Access:RW   DataWidth:0x8   Selection of the max PQ size based on the 2 possibilities of each PF (based on MaxPqSize 0 & 1). Per each TX PQ configuration. i=0: PQ-s 7-0 (bit0 for PQ0; bit1 for PQ1; etc); i=1: PQ-s 15-8 (bit0 for PQ8; bit1 for PQ9); etc.  Chips: K2
42837 #define QM_REG_BASEADDROTHERPQ                                                                       0x2f0600UL //Access:RW   DataWidth:0x14  The base logical address (in 4096 bytes) of each physical queue. The index I represents the physical queue number.  Chips: BB_A0 BB_B0 K2
42838 #define QM_REG_BASEADDROTHERPQ_SIZE                                                                  128
42839 #define QM_REG_OUTLDREQSIZECONNTX                                                                    0x2f0800UL //Access:RW   DataWidth:0x5   The max buffer size of the load request buffer within the RC response unit for the TX connection requests (goes to the CCFC). NOTE: The max size should be based on the actual buffer size.  Chips: BB_A0 BB_B0 K2
42840 #define QM_REG_OUTLDREQSIZECONNOTHER                                                                 0x2f0804UL //Access:RW   DataWidth:0x5   The max buffer size of the load request buffer within the RC response unit for the Other connection requests (goes to the CCFC). NOTE: The max size should be based on the actual buffer size.  Chips: BB_A0 BB_B0 K2
42841 #define QM_REG_OUTLDREQCRDCONNTX                                                                     0x2f0808UL //Access:R    DataWidth:0x5   The credit of the connection load request TX buffer. Describes the number of outstanding read requests (outstanding means sent by the RC request unit & didn't get CCFC load response yet). Each time the RC request unit sends a TX queue pop request towards the UQE this counter is decremented. Each time the CCFC sends load response this counter is incremented.  Chips: BB_A0 BB_B0 K2
42842 #define QM_REG_OUTLDREQCRDCONNOTHER                                                                  0x2f080cUL //Access:R    DataWidth:0x5   The credit of the connection load request Other buffer. Describes the number of outstanding read requests (outstanding means sent by the RC request unit & didn't get CCFC load response yet). Each time the RC request unit sends an Other queue pop request towards the UQE this counter is decremented. Each time the CCFC sends load response this counter is incremented.  Chips: BB_A0 BB_B0 K2
42843 #define QM_REG_PTRTBLOTHER                                                                           0x2f0c00UL //Access:WB   DataWidth:0x36  Pointer Table Memory for Other queues 63-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;.  Chips: BB_A0 BB_B0 K2
42844 #define QM_REG_PTRTBLOTHER_SIZE                                                                      256
42845 #define QM_REG_BIGRAMTXADDR                                                                          0x2f1000UL //Access:RW   DataWidth:0xd   The address of the TX BigRam to access. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamTxAddr; (b) writing the data BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data BigRamTxData (for rd cmd only).  Chips: BB_A0 BB_B0 K2
42846 #define QM_REG_BIGRAMTXDATA                                                                          0x2f1008UL //Access:WB   DataWidth:0x3c  The data of the TX bigRam to access (rd/wr). Accessing the BigRam should be implemented as follows: (a) writing the address BigRamTxAddr; (b) writing the data BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data BigRamTxData (for rd cmd only).  Chips: BB_A0 BB_B0 K2
42847 #define QM_REG_BIGRAMTXDATA_SIZE                                                                     2
42848 #define QM_REG_BIGRAMTXCMD                                                                           0x2f1010UL //Access:W    DataWidth:0x1   The mem access cmd (0 - rd; 1 - wr) sent towards of the TX bigRam. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamTxAddr; (b) writing the data BigRamTxData (for wr cmd only); (c) writing the cmd type BigRamTxCmd; (d) accessing the rd data BigRamTxData (for rd cmd only).  Chips: BB_A0 BB_B0 K2
42849 #define QM_REG_BIGRAMOTHERADDR                                                                       0x2f1014UL //Access:RW   DataWidth:0xb   The address of the Other BigRam to access. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamOtherAddr; (b) writing the data BigRamOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data BigRamOtherData (for rd cmd only).  Chips: BB_A0 BB_B0 K2
42850 #define QM_REG_BIGRAMOTHERDATA                                                                       0x2f1020UL //Access:WB   DataWidth:0x6c  The data of the Other bigRam to access (rd/wr). Accessing the BigRam should be implemented as follows: (a) writing the address BigRamOtherAddr; (b) writing the data BigRamOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data BigRamOtherData (for rd cmd only).  Chips: BB_A0 BB_B0 K2
42851 #define QM_REG_BIGRAMOTHERDATA_SIZE                                                                  4
42852 #define QM_REG_BIGRAMOTHERCMD                                                                        0x2f1030UL //Access:W    DataWidth:0x1   The mem access cmd (0 - rd; 1 - wr) sent towards of the Other bigRam. Accessing the BigRam should be implemented as follows: (a) writing the address BigRamOtherAddr; (b) writing the data BigRamOtherData (for wr cmd only); (c) writing the cmd type BigRamOtherCmd; (d) accessing the rd data BigRamOtherData (for rd cmd only).  Chips: BB_A0 BB_B0 K2
42853 #define QM_REG_QSTATUSTX_0                                                                           0x2f1040UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42854 #define QM_REG_QSTATUSTX_1                                                                           0x2f1044UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42855 #define QM_REG_QSTATUSTX_2                                                                           0x2f1048UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42856 #define QM_REG_QSTATUSTX_3                                                                           0x2f104cUL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42857 #define QM_REG_QSTATUSTX_4                                                                           0x2f1050UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42858 #define QM_REG_QSTATUSTX_5                                                                           0x2f1054UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42859 #define QM_REG_QSTATUSTX_6                                                                           0x2f1058UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42860 #define QM_REG_QSTATUSTX_7                                                                           0x2f105cUL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42861 #define QM_REG_QSTATUSTX_8                                                                           0x2f1060UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42862 #define QM_REG_QSTATUSTX_9                                                                           0x2f1064UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42863 #define QM_REG_QSTATUSTX_10                                                                          0x2f1068UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42864 #define QM_REG_QSTATUSTX_11                                                                          0x2f106cUL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42865 #define QM_REG_QSTATUSTX_12                                                                          0x2f1070UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42866 #define QM_REG_QSTATUSTX_13                                                                          0x2f1074UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: BB_A0 BB_B0 K2
42867 #define QM_REG_QSTATUSTX_14                                                                          0x2f1078UL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: K2
42868 #define QM_REG_QSTATUSTX_15                                                                          0x2f107cUL //Access:R    DataWidth:0x20  Current TX queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1; .. ; queues 416-447 in n=13; queues 448-479 in n14; queues 480-511 in n15;  Chips: K2
42869 #define QM_REG_QSTATUSOTHER_0                                                                        0x2f10c0UL //Access:R    DataWidth:0x20  Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3.  Chips: BB_A0 BB_B0 K2
42870 #define QM_REG_QSTATUSOTHER_1                                                                        0x2f10c4UL //Access:R    DataWidth:0x20  Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3.  Chips: BB_A0 BB_B0 K2
42871 #define QM_REG_QSTATUSOTHER_2                                                                        0x2f10c8UL //Access:R    DataWidth:0x20  Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3.  Chips: K2
42872 #define QM_REG_QSTATUSOTHER_3                                                                        0x2f10ccUL //Access:R    DataWidth:0x20  Current Other queues in pipeline: Queues 0-31 in n=0; Queues 32-63 in n=1;Queues 64-95 in n=2;Queues 96-127 in n=3.  Chips: K2
42873 #define QM_REG_CTXREGCCFC_0                                                                          0x2f1120UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42874 #define QM_REG_CTXREGCCFC_1                                                                          0x2f1124UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42875 #define QM_REG_CTXREGCCFC_2                                                                          0x2f1128UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42876 #define QM_REG_CTXREGCCFC_3                                                                          0x2f112cUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42877 #define QM_REG_CTXREGCCFC_4                                                                          0x2f1130UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42878 #define QM_REG_CTXREGCCFC_5                                                                          0x2f1134UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42879 #define QM_REG_CTXREGCCFC_6                                                                          0x2f1138UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42880 #define QM_REG_CTXREGCCFC_7                                                                          0x2f113cUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42881 #define QM_REG_CTXREGCCFC_8                                                                          0x2f1140UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42882 #define QM_REG_CTXREGCCFC_9                                                                          0x2f1144UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42883 #define QM_REG_CTXREGCCFC_10                                                                         0x2f1148UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42884 #define QM_REG_CTXREGCCFC_11                                                                         0x2f114cUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42885 #define QM_REG_CTXREGCCFC_12                                                                         0x2f1150UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42886 #define QM_REG_CTXREGCCFC_13                                                                         0x2f1154UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42887 #define QM_REG_CTXREGCCFC_14                                                                         0x2f1158UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42888 #define QM_REG_CTXREGCCFC_15                                                                         0x2f115cUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42889 #define QM_REG_CTXREGCCFC_16                                                                         0x2f1160UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42890 #define QM_REG_CTXREGCCFC_17                                                                         0x2f1164UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42891 #define QM_REG_CTXREGCCFC_18                                                                         0x2f1168UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42892 #define QM_REG_CTXREGCCFC_19                                                                         0x2f116cUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42893 #define QM_REG_CTXREGCCFC_20                                                                         0x2f1170UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42894 #define QM_REG_CTXREGCCFC_21                                                                         0x2f1174UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42895 #define QM_REG_CTXREGCCFC_22                                                                         0x2f1178UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42896 #define QM_REG_CTXREGCCFC_23                                                                         0x2f117cUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42897 #define QM_REG_CTXREGCCFC_24                                                                         0x2f1180UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42898 #define QM_REG_CTXREGCCFC_25                                                                         0x2f1184UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42899 #define QM_REG_CTXREGCCFC_26                                                                         0x2f1188UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42900 #define QM_REG_CTXREGCCFC_27                                                                         0x2f118cUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42901 #define QM_REG_CTXREGCCFC_28                                                                         0x2f1190UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42902 #define QM_REG_CTXREGCCFC_29                                                                         0x2f1194UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42903 #define QM_REG_CTXREGCCFC_30                                                                         0x2f1198UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42904 #define QM_REG_CTXREGCCFC_31                                                                         0x2f119cUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42905 #define QM_REG_CTXREGCCFC_32                                                                         0x2f11a0UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42906 #define QM_REG_CTXREGCCFC_33                                                                         0x2f11a4UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42907 #define QM_REG_CTXREGCCFC_34                                                                         0x2f11a8UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42908 #define QM_REG_CTXREGCCFC_35                                                                         0x2f11acUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42909 #define QM_REG_CTXREGCCFC_36                                                                         0x2f11b0UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42910 #define QM_REG_CTXREGCCFC_37                                                                         0x2f11b4UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42911 #define QM_REG_CTXREGCCFC_38                                                                         0x2f11b8UL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42912 #define QM_REG_CTXREGCCFC_39                                                                         0x2f11bcUL //Access:RW   DataWidth:0x8   The context regions sent in the CCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42913 #define QM_REG_CTXREGTCFC_0                                                                          0x2f1220UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42914 #define QM_REG_CTXREGTCFC_1                                                                          0x2f1224UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42915 #define QM_REG_CTXREGTCFC_2                                                                          0x2f1228UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42916 #define QM_REG_CTXREGTCFC_3                                                                          0x2f122cUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42917 #define QM_REG_CTXREGTCFC_4                                                                          0x2f1230UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42918 #define QM_REG_CTXREGTCFC_5                                                                          0x2f1234UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42919 #define QM_REG_CTXREGTCFC_6                                                                          0x2f1238UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42920 #define QM_REG_CTXREGTCFC_7                                                                          0x2f123cUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42921 #define QM_REG_CTXREGTCFC_8                                                                          0x2f1240UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42922 #define QM_REG_CTXREGTCFC_9                                                                          0x2f1244UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42923 #define QM_REG_CTXREGTCFC_10                                                                         0x2f1248UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42924 #define QM_REG_CTXREGTCFC_11                                                                         0x2f124cUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42925 #define QM_REG_CTXREGTCFC_12                                                                         0x2f1250UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42926 #define QM_REG_CTXREGTCFC_13                                                                         0x2f1254UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42927 #define QM_REG_CTXREGTCFC_14                                                                         0x2f1258UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42928 #define QM_REG_CTXREGTCFC_15                                                                         0x2f125cUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42929 #define QM_REG_CTXREGTCFC_16                                                                         0x2f1260UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42930 #define QM_REG_CTXREGTCFC_17                                                                         0x2f1264UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42931 #define QM_REG_CTXREGTCFC_18                                                                         0x2f1268UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42932 #define QM_REG_CTXREGTCFC_19                                                                         0x2f126cUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42933 #define QM_REG_CTXREGTCFC_20                                                                         0x2f1270UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42934 #define QM_REG_CTXREGTCFC_21                                                                         0x2f1274UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42935 #define QM_REG_CTXREGTCFC_22                                                                         0x2f1278UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42936 #define QM_REG_CTXREGTCFC_23                                                                         0x2f127cUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42937 #define QM_REG_CTXREGTCFC_24                                                                         0x2f1280UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42938 #define QM_REG_CTXREGTCFC_25                                                                         0x2f1284UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42939 #define QM_REG_CTXREGTCFC_26                                                                         0x2f1288UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42940 #define QM_REG_CTXREGTCFC_27                                                                         0x2f128cUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42941 #define QM_REG_CTXREGTCFC_28                                                                         0x2f1290UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42942 #define QM_REG_CTXREGTCFC_29                                                                         0x2f1294UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42943 #define QM_REG_CTXREGTCFC_30                                                                         0x2f1298UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42944 #define QM_REG_CTXREGTCFC_31                                                                         0x2f129cUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42945 #define QM_REG_CTXREGTCFC_32                                                                         0x2f12a0UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42946 #define QM_REG_CTXREGTCFC_33                                                                         0x2f12a4UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42947 #define QM_REG_CTXREGTCFC_34                                                                         0x2f12a8UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42948 #define QM_REG_CTXREGTCFC_35                                                                         0x2f12acUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42949 #define QM_REG_CTXREGTCFC_36                                                                         0x2f12b0UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42950 #define QM_REG_CTXREGTCFC_37                                                                         0x2f12b4UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42951 #define QM_REG_CTXREGTCFC_38                                                                         0x2f12b8UL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42952 #define QM_REG_CTXREGTCFC_39                                                                         0x2f12bcUL //Access:RW   DataWidth:0x8   The context regions sent in the TCFC load request;  CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42953 #define QM_REG_ACTCTRINITVALCCFC_0                                                                   0x2f1320UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42954 #define QM_REG_ACTCTRINITVALCCFC_1                                                                   0x2f1324UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42955 #define QM_REG_ACTCTRINITVALCCFC_2                                                                   0x2f1328UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42956 #define QM_REG_ACTCTRINITVALCCFC_3                                                                   0x2f132cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42957 #define QM_REG_ACTCTRINITVALCCFC_4                                                                   0x2f1330UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42958 #define QM_REG_ACTCTRINITVALCCFC_5                                                                   0x2f1334UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42959 #define QM_REG_ACTCTRINITVALCCFC_6                                                                   0x2f1338UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42960 #define QM_REG_ACTCTRINITVALCCFC_7                                                                   0x2f133cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42961 #define QM_REG_ACTCTRINITVALCCFC_8                                                                   0x2f1340UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42962 #define QM_REG_ACTCTRINITVALCCFC_9                                                                   0x2f1344UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42963 #define QM_REG_ACTCTRINITVALCCFC_10                                                                  0x2f1348UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42964 #define QM_REG_ACTCTRINITVALCCFC_11                                                                  0x2f134cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42965 #define QM_REG_ACTCTRINITVALCCFC_12                                                                  0x2f1350UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42966 #define QM_REG_ACTCTRINITVALCCFC_13                                                                  0x2f1354UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42967 #define QM_REG_ACTCTRINITVALCCFC_14                                                                  0x2f1358UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42968 #define QM_REG_ACTCTRINITVALCCFC_15                                                                  0x2f135cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42969 #define QM_REG_ACTCTRINITVALCCFC_16                                                                  0x2f1360UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42970 #define QM_REG_ACTCTRINITVALCCFC_17                                                                  0x2f1364UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42971 #define QM_REG_ACTCTRINITVALCCFC_18                                                                  0x2f1368UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42972 #define QM_REG_ACTCTRINITVALCCFC_19                                                                  0x2f136cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42973 #define QM_REG_ACTCTRINITVALCCFC_20                                                                  0x2f1370UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42974 #define QM_REG_ACTCTRINITVALCCFC_21                                                                  0x2f1374UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42975 #define QM_REG_ACTCTRINITVALCCFC_22                                                                  0x2f1378UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42976 #define QM_REG_ACTCTRINITVALCCFC_23                                                                  0x2f137cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42977 #define QM_REG_ACTCTRINITVALCCFC_24                                                                  0x2f1380UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42978 #define QM_REG_ACTCTRINITVALCCFC_25                                                                  0x2f1384UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42979 #define QM_REG_ACTCTRINITVALCCFC_26                                                                  0x2f1388UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42980 #define QM_REG_ACTCTRINITVALCCFC_27                                                                  0x2f138cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42981 #define QM_REG_ACTCTRINITVALCCFC_28                                                                  0x2f1390UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42982 #define QM_REG_ACTCTRINITVALCCFC_29                                                                  0x2f1394UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42983 #define QM_REG_ACTCTRINITVALCCFC_30                                                                  0x2f1398UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42984 #define QM_REG_ACTCTRINITVALCCFC_31                                                                  0x2f139cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42985 #define QM_REG_ACTCTRINITVALCCFC_32                                                                  0x2f13a0UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42986 #define QM_REG_ACTCTRINITVALCCFC_33                                                                  0x2f13a4UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42987 #define QM_REG_ACTCTRINITVALCCFC_34                                                                  0x2f13a8UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42988 #define QM_REG_ACTCTRINITVALCCFC_35                                                                  0x2f13acUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42989 #define QM_REG_ACTCTRINITVALCCFC_36                                                                  0x2f13b0UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42990 #define QM_REG_ACTCTRINITVALCCFC_37                                                                  0x2f13b4UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42991 #define QM_REG_ACTCTRINITVALCCFC_38                                                                  0x2f13b8UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42992 #define QM_REG_ACTCTRINITVALCCFC_39                                                                  0x2f13bcUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, ConnType} (i: bits 2:0 = ConnType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42993 #define QM_REG_ACTCTRINITVALTCFC_0                                                                   0x2f1420UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42994 #define QM_REG_ACTCTRINITVALTCFC_1                                                                   0x2f1424UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42995 #define QM_REG_ACTCTRINITVALTCFC_2                                                                   0x2f1428UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42996 #define QM_REG_ACTCTRINITVALTCFC_3                                                                   0x2f142cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42997 #define QM_REG_ACTCTRINITVALTCFC_4                                                                   0x2f1430UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42998 #define QM_REG_ACTCTRINITVALTCFC_5                                                                   0x2f1434UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
42999 #define QM_REG_ACTCTRINITVALTCFC_6                                                                   0x2f1438UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43000 #define QM_REG_ACTCTRINITVALTCFC_7                                                                   0x2f143cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43001 #define QM_REG_ACTCTRINITVALTCFC_8                                                                   0x2f1440UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43002 #define QM_REG_ACTCTRINITVALTCFC_9                                                                   0x2f1444UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43003 #define QM_REG_ACTCTRINITVALTCFC_10                                                                  0x2f1448UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43004 #define QM_REG_ACTCTRINITVALTCFC_11                                                                  0x2f144cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43005 #define QM_REG_ACTCTRINITVALTCFC_12                                                                  0x2f1450UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43006 #define QM_REG_ACTCTRINITVALTCFC_13                                                                  0x2f1454UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43007 #define QM_REG_ACTCTRINITVALTCFC_14                                                                  0x2f1458UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43008 #define QM_REG_ACTCTRINITVALTCFC_15                                                                  0x2f145cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43009 #define QM_REG_ACTCTRINITVALTCFC_16                                                                  0x2f1460UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43010 #define QM_REG_ACTCTRINITVALTCFC_17                                                                  0x2f1464UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43011 #define QM_REG_ACTCTRINITVALTCFC_18                                                                  0x2f1468UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43012 #define QM_REG_ACTCTRINITVALTCFC_19                                                                  0x2f146cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43013 #define QM_REG_ACTCTRINITVALTCFC_20                                                                  0x2f1470UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43014 #define QM_REG_ACTCTRINITVALTCFC_21                                                                  0x2f1474UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43015 #define QM_REG_ACTCTRINITVALTCFC_22                                                                  0x2f1478UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43016 #define QM_REG_ACTCTRINITVALTCFC_23                                                                  0x2f147cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43017 #define QM_REG_ACTCTRINITVALTCFC_24                                                                  0x2f1480UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43018 #define QM_REG_ACTCTRINITVALTCFC_25                                                                  0x2f1484UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43019 #define QM_REG_ACTCTRINITVALTCFC_26                                                                  0x2f1488UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43020 #define QM_REG_ACTCTRINITVALTCFC_27                                                                  0x2f148cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43021 #define QM_REG_ACTCTRINITVALTCFC_28                                                                  0x2f1490UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43022 #define QM_REG_ACTCTRINITVALTCFC_29                                                                  0x2f1494UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43023 #define QM_REG_ACTCTRINITVALTCFC_30                                                                  0x2f1498UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43024 #define QM_REG_ACTCTRINITVALTCFC_31                                                                  0x2f149cUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43025 #define QM_REG_ACTCTRINITVALTCFC_32                                                                  0x2f14a0UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43026 #define QM_REG_ACTCTRINITVALTCFC_33                                                                  0x2f14a4UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43027 #define QM_REG_ACTCTRINITVALTCFC_34                                                                  0x2f14a8UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43028 #define QM_REG_ACTCTRINITVALTCFC_35                                                                  0x2f14acUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43029 #define QM_REG_ACTCTRINITVALTCFC_36                                                                  0x2f14b0UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43030 #define QM_REG_ACTCTRINITVALTCFC_37                                                                  0x2f14b4UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43031 #define QM_REG_ACTCTRINITVALTCFC_38                                                                  0x2f14b8UL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43032 #define QM_REG_ACTCTRINITVALTCFC_39                                                                  0x2f14bcUL //Access:RW   DataWidth:0x8   The activity counter initial increment value sent in the load request; CM_ID: 0 = M; 1 = U; 2 = T; 3 = Y; 4 = X. i = {CM_ID, TaskType} (i: bits 2:0 = TaskType, bits 5:3 = CM_ID)  Chips: BB_A0 BB_B0 K2
43033 #define QM_REG_PCIREQQID                                                                             0x2f1520UL //Access:RW   DataWidth:0x5   The virtual Queue ID used in the PCI request.  Chips: BB_A0 BB_B0 K2
43034 #define QM_REG_PCIREQAT                                                                              0x2f1524UL //Access:RW   DataWidth:0x2   The PCI attributes field used in the PCI request.  Chips: BB_A0 BB_B0 K2
43035 #define QM_REG_PCIREQATC                                                                             0x2f1528UL //Access:RW   DataWidth:0x18  The PCI ATC flags used in the PCI request. b2-b0: rd first bank in page; b3: reserved (zero); b6-b4: wr first bank in page; b7: reserved (zero); b10-b8: rd middle bank in page; b11: reserved (zero); b14-b12: wr middle bank in page; b15: reserved (zero); b18-b16: rd last bank in page; b19: reserved (zero); b22-b20: wr last bank in page; b23: reserved (zero);.  Chips: BB_A0 BB_B0 K2
43036 #define QM_REG_QMPAGESIZE                                                                            0x2f152cUL //Access:RW   DataWidth:0x5   The STU size; this should be configured according to the minimal STU within the PXP (there is STU per PF). 0-4k;1-8k;2-16k;3-32k;4-64k;5-128k;6-256k;7-512k;8-1M;9-2M;10-4M.  Chips: BB_A0 BB_B0 K2
43037 #define QM_REG_PCIREQTPH                                                                             0x2f1530UL //Access:RW   DataWidth:0x10  The PCI TPH field used in the PCI request. Per PF value. bits: 8-0 TPH Steering Tag Index; 12-9 reserved; 14-13 TPH ST hint; 15 TPH Valid.  Chips: BB_A0 BB_B0 K2
43038 #define QM_REG_PCIREQPADTOCACHELINE                                                                  0x2f1534UL //Access:RW   DataWidth:0x1   pad to cache line field as part of PXP write request  Chips: BB_A0 BB_B0 K2
43039 #define QM_REG_OVFQNUMTX                                                                             0x2f1538UL //Access:RC   DataWidth:0x9   The Q were the qverflow occurs.  Chips: BB_A0 BB_B0 K2
43040 #define QM_REG_OVFERRORTX                                                                            0x2f153cUL //Access:RC   DataWidth:0x1   A flag to indicate that overflow error occurred in one of the queues.  Chips: BB_A0 BB_B0 K2
43041 #define QM_REG_OVFQNUMOTHER                                                                          0x2f1540UL //Access:RC   DataWidth:0x6   The Q were the qverflow occurs.  Chips: BB_A0 BB_B0 K2
43042 #define QM_REG_OVFERROROTHER                                                                         0x2f1544UL //Access:RC   DataWidth:0x1   A flag to indicate that overflow error occurred in one of the queues.  Chips: BB_A0 BB_B0 K2
43043 #define QM_REG_VOQCRDLINE                                                                            0x2f1580UL //Access:RW   DataWidth:0x10  The actual line credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdline. Granularity of 16B.  Chips: BB_A0 BB_B0 K2
43044 #define QM_REG_VOQCRDLINE_SIZE                                                                       20
43045 #define QM_REG_VOQCRDLINEFULL                                                                        0x2f1600UL //Access:R    DataWidth:0x14  When set, inidicates that the VOQ line credit counter is equal to the VOQ line init value. There is a bit per VOQ.  Chips: BB_A0 BB_B0 K2
43046 #define QM_REG_VOQINITCRDLINE                                                                        0x2f1680UL //Access:RW   DataWidth:0x10  The init and maximum line credit for each VOQ. The max allowed init value is 2^15-1-2^9. Granularity of 16B.  Chips: BB_A0 BB_B0 K2
43047 #define QM_REG_VOQINITCRDLINE_SIZE                                                                   20
43048 #define QM_REG_TASKLINECRDCOST                                                                       0x2f1700UL //Access:RW   DataWidth:0x8   The lineVOQ credit cost per every task in the QM.  must be smaller or equal to the matched Voq line credit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ). Granularity of 16B.  Chips: BB_A0 BB_B0 K2
43049 #define QM_REG_VOQCRDBYTE                                                                            0x2f1780UL //Access:RW   DataWidth:0x18  The actual byte credit for each VOQ. Should be read only access in non-init mode. In init mode should be written with the same value of voqinitcrdbyte.  Chips: BB_A0 BB_B0 K2
43050 #define QM_REG_VOQCRDBYTE_SIZE                                                                       20
43051 #define QM_REG_VOQCRDBYTEFULL                                                                        0x2f1800UL //Access:R    DataWidth:0x14  When set, inidicates that the VOQ byte credit counter is equal to the VOQ byte init value. There is a bit per VOQ.  Chips: BB_A0 BB_B0 K2
43052 #define QM_REG_VOQINITCRDBYTE                                                                        0x2f1880UL //Access:RW   DataWidth:0x18  The init and maximum byte credit for each VOQ. The max allowed init value is 2^23-1-2^16.  Chips: BB_A0 BB_B0 K2
43053 #define QM_REG_VOQINITCRDBYTE_SIZE                                                                   20
43054 #define QM_REG_TASKBYTECRDCOST_0                                                                     0x2f1900UL //Access:RW   DataWidth:0x10  The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).  Chips: BB_A0 BB_B0 K2
43055 #define QM_REG_TASKBYTECRDCOST_1                                                                     0x2f1904UL //Access:RW   DataWidth:0x10  The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).  Chips: BB_A0 BB_B0 K2
43056 #define QM_REG_TASKBYTECRDCOST_2                                                                     0x2f1908UL //Access:RW   DataWidth:0x10  The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).  Chips: BB_A0 BB_B0 K2
43057 #define QM_REG_TASKBYTECRDCOST_3                                                                     0x2f190cUL //Access:RW   DataWidth:0x10  The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).  Chips: BB_A0 BB_B0 K2
43058 #define QM_REG_TASKBYTECRDCOST_4                                                                     0x2f1910UL //Access:RW   DataWidth:0x10  The byte credit cost per every task in the QM that will be used for charging the different byte credit resources. i: 0 - VOQ byte; 1 - PF RL; 2 - Global VP/QCN RL; 3 - PF WFQ; 4 - VP WFQ; NOTE: 3. In the common functional mode all byte credits will have the same value. must be smaller or equal to the matched Voq byte redit (relevant only for VOQs that are being used - or in other words VOQs that have at least single PQ that is associated with the VOQ).  Chips: BB_A0 BB_B0 K2
43059 #define QM_REG_AFULLQMBYPTHRLINEVOQMASK                                                              0x2f1914UL //Access:RW   DataWidth:0x14  VOQ line credit almost full threshold mask for the QM bypass feature (per VOQ id bit). When 1 the VOQ line credit counter should be equal to the VOQ line init value to enable bypass. When 0 - the VOQ line credit counter is don't care, and bypass can be implemented regardless of the VOQ line counter value.  Chips: BB_A0 BB_B0 K2
43060 #define QM_REG_AFULLQMBYPTHRPFWFQ                                                                    0x2f1918UL //Access:RW   DataWidth:0x20  PF WFQ byte credit almost full threshold for the qm bypass operation.  Chips: BB_A0 BB_B0 K2
43061 #define QM_REG_AFULLQMBYPTHRVPWFQ                                                                    0x2f191cUL //Access:RW   DataWidth:0x20  VP WFQ byte credit almost full threshold for the qm bypass operation.  Chips: BB_A0 BB_B0 K2
43062 #define QM_REG_AFULLQMBYPTHRPFRL                                                                     0x2f1920UL //Access:RW   DataWidth:0x20  PF RL byte credit almost full threshold for the qm bypass operation.  Chips: BB_A0 BB_B0 K2
43063 #define QM_REG_AFULLQMBYPTHRGLBLRL                                                                   0x2f1924UL //Access:RW   DataWidth:0x20  Global VP/QCN RL byte credit almost full threshold for the qm bypass operation.  Chips: BB_A0 BB_B0 K2
43064 #define QM_REG_AFULLQMBYPMASK                                                                        0x2f1928UL //Access:RW   DataWidth:0x7   Mask bit per credit resource for the qm bypass. 1 - resource is required to be more than the almost full threshold. 0 - resource value is do not care; 0 - line VOQ; 1 - reserved; 2 - PF WFQ; 3 - VP WFQ; 4 - PF RL; 5 - global VP-QCN RL; 6 - FW stop;  Chips: BB_A0 BB_B0 K2
43065 #define QM_REG_AFULLOPRTNSTCTHRLINEVOQ                                                               0x2f192cUL //Access:RW   DataWidth:0x10  VOQ line credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskLineCrdCost  Chips: BB_A0 BB_B0 K2
43066 #define QM_REG_AFULLOPRTNSTCTHRBYTEVOQ                                                               0x2f1930UL //Access:RW   DataWidth:0x18  VOQ byte credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskByteCrdCost_0  Chips: BB_A0 BB_B0 K2
43067 #define QM_REG_AFULLOPRTNSTCTHRPFWFQ                                                                 0x2f1934UL //Access:RW   DataWidth:0x20  PF WFQ byte credit almost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_3  Chips: BB_A0 BB_B0 K2
43068 #define QM_REG_AFULLOPRTNSTCTHRVPWFQ                                                                 0x2f1938UL //Access:RW   DataWidth:0x20  VP WFQ byte credit almost full threshold for the opportunistic credit flow operation. reset value: -1 x TaskByteCrdCost_4  Chips: BB_A0 BB_B0 K2
43069 #define QM_REG_AFULLOPRTNSTCTHRPFRL                                                                  0x2f193cUL //Access:RW   DataWidth:0x20  PF RL byte credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskByteCrdCost_1  Chips: BB_A0 BB_B0 K2
43070 #define QM_REG_AFULLOPRTNSTCTHRGLBLRL                                                                0x2f1940UL //Access:RW   DataWidth:0x20  Global VP/QCN RL byte credit almost full threshold for the opportunistic credit flow operation. reset value: +2 x TaskByteCrdCost_2  Chips: BB_A0 BB_B0 K2
43071 #define QM_REG_AFULLOPRTNSTCCRDMASK                                                                  0x2f1944UL //Access:RW   DataWidth:0x9   Mask bit per credit resource for the opportunistic credit. 1 - resource is required to be more than the almost full threshold. 0 - resource value is do not care; 0 - line VOQ; 1 - byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF RL; 5 - global VP-QCN RL; 6 - FW stop; 7 - reserved; 8 - PQ Empty.  Chips: BB_A0 BB_B0 K2
43072 #define QM_REG_QMBYPENABLE                                                                           0x2f1948UL //Access:RW   DataWidth:0x1   Allows the QM to work in qm bypass mode. i.e. sending the bypass indication when conditions are met and open the XCM bypass request interface from the XCM.  Chips: BB_A0 BB_B0 K2
43073 #define QM_REG_OPRTNSTCCRDENABLE                                                                     0x2f194cUL //Access:RW   DataWidth:0x1   Allows the QM to answer and handle opportunistic bypass requests (i.e. which PQ credit info?) from the Xstorm. otherwise return null on the GPI interface.  Chips: BB_A0 BB_B0 K2
43074 #define QM_REG_QMBYPGLBLCNT_0                                                                        0x2f1950UL //Access:R    DataWidth:0xa   Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.  Chips: BB_A0 BB_B0 K2
43075 #define QM_REG_QMBYPGLBLCNT_1                                                                        0x2f1954UL //Access:R    DataWidth:0xa   Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.  Chips: BB_A0 BB_B0 K2
43076 #define QM_REG_QMBYPGLBLCNT_2                                                                        0x2f1958UL //Access:R    DataWidth:0xa   Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.  Chips: BB_A0 BB_B0 K2
43077 #define QM_REG_QMBYPGLBLCNT_3                                                                        0x2f195cUL //Access:R    DataWidth:0xa   Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.  Chips: BB_A0 BB_B0 K2
43078 #define QM_REG_QMBYPGLBLCNT_4                                                                        0x2f1960UL //Access:R    DataWidth:0xa   Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.  Chips: BB_A0 BB_B0 K2
43079 #define QM_REG_QMBYPGLBLCNT_5                                                                        0x2f1964UL //Access:R    DataWidth:0xa   Global per type counter that counts the number of counters of the same type that are above the almost full threshold. i: 0 - Line VOQ; 1 - Byte VOQ; 2 - PF WFQ; 3 - VP WFQ; 4 - PF R; 5 - Global VP/QCN RL.  Chips: BB_A0 BB_B0 K2
43080 #define QM_REG_WRROTHERPQGRP_0                                                                       0x2f1968UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: BB_A0 BB_B0 K2
43081 #define QM_REG_WRROTHERPQGRP_1                                                                       0x2f196cUL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: BB_A0 BB_B0 K2
43082 #define QM_REG_WRROTHERPQGRP_2                                                                       0x2f1970UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: BB_A0 BB_B0 K2
43083 #define QM_REG_WRROTHERPQGRP_3                                                                       0x2f1974UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: BB_A0 BB_B0 K2
43084 #define QM_REG_WRROTHERPQGRP_4                                                                       0x2f1978UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: BB_A0 BB_B0 K2
43085 #define QM_REG_WRROTHERPQGRP_5                                                                       0x2f197cUL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: BB_A0 BB_B0 K2
43086 #define QM_REG_WRROTHERPQGRP_6                                                                       0x2f1980UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: BB_A0 BB_B0 K2
43087 #define QM_REG_WRROTHERPQGRP_7                                                                       0x2f1984UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: BB_A0 BB_B0 K2
43088 #define QM_REG_WRROTHERPQGRP_8                                                                       0x2f1988UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: K2
43089 #define QM_REG_WRROTHERPQGRP_9                                                                       0x2f198cUL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: K2
43090 #define QM_REG_WRROTHERPQGRP_10                                                                      0x2f1990UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: K2
43091 #define QM_REG_WRROTHERPQGRP_11                                                                      0x2f1994UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: K2
43092 #define QM_REG_WRROTHERPQGRP_12                                                                      0x2f1998UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: K2
43093 #define QM_REG_WRROTHERPQGRP_13                                                                      0x2f199cUL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: K2
43094 #define QM_REG_WRROTHERPQGRP_14                                                                      0x2f19a0UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: K2
43095 #define QM_REG_WRROTHERPQGRP_15                                                                      0x2f19a4UL //Access:RW   DataWidth:0x20  The WRR group for Other queue which will indicate the WRR weight of the other queue. 4 bits per PQ - for i=0: bits 3:0 - PQ0; bits 7:4 - PQ1; bits 31:28 - PQ7; for i=1: bits 3:0 - PQ8; bits 7:4 - PQ9; bits 31:28 - PQ15; Valid groups values are: 0x0: the WRR weight of the PQ is 0 (eligible for single gnt as part of the full wrr circles round); 0x1: the WRR weight of the PQ is WrrOtherGrpWeight_0; 0x3: the WRR weight of the PQ is WrrOtherGrpWeight_1; 0x7: the WRR weight of the PQ is WrrOtherGrpWeight_2; 0xf: the WRR weight of the PQ is WrrOtherGrpWeight_3. This is based on WrrGrpWeight NOTE: weight update is allowed only to queues which are either empty or paused.  Chips: K2
43096 #define QM_REG_WRROTHERGRPWEIGHT_0                                                                   0x2f19e8UL //Access:RW   DataWidth:0x8   The actual WRR weight that is used by Other PQ-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrOtherGrpWeight (3-0) are = 0 --> RR (b) if all WrrOtherGrpWeight (3-0) are > 0 --> WRR in that case the WrrOtherGrpWeight should be ordered. WrrOtherGrpWeight_0 should be configured with the smallest value. WrrOtherGrpWeight_1 should be next (and bigger than WrrOtherGrpWeight_0). WrrOtherGrpWeight_2 should be next (and bigger than WrrOtherGrpWeight_1). WrrOtherGrpWeight_3 should be configured with the max value (bigger than WrrOtherGrpWeight_2). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.  Chips: BB_A0 BB_B0 K2
43097 #define QM_REG_WRROTHERGRPWEIGHT_1                                                                   0x2f19ecUL //Access:RW   DataWidth:0x8   The actual WRR weight that is used by Other PQ-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrOtherGrpWeight (3-0) are = 0 --> RR (b) if all WrrOtherGrpWeight (3-0) are > 0 --> WRR in that case the WrrOtherGrpWeight should be ordered. WrrOtherGrpWeight_0 should be configured with the smallest value. WrrOtherGrpWeight_1 should be next (and bigger than WrrOtherGrpWeight_0). WrrOtherGrpWeight_2 should be next (and bigger than WrrOtherGrpWeight_1). WrrOtherGrpWeight_3 should be configured with the max value (bigger than WrrOtherGrpWeight_2). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.  Chips: BB_A0 BB_B0 K2
43098 #define QM_REG_WRROTHERGRPWEIGHT_2                                                                   0x2f19f0UL //Access:RW   DataWidth:0x8   The actual WRR weight that is used by Other PQ-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrOtherGrpWeight (3-0) are = 0 --> RR (b) if all WrrOtherGrpWeight (3-0) are > 0 --> WRR in that case the WrrOtherGrpWeight should be ordered. WrrOtherGrpWeight_0 should be configured with the smallest value. WrrOtherGrpWeight_1 should be next (and bigger than WrrOtherGrpWeight_0). WrrOtherGrpWeight_2 should be next (and bigger than WrrOtherGrpWeight_1). WrrOtherGrpWeight_3 should be configured with the max value (bigger than WrrOtherGrpWeight_2). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.  Chips: BB_A0 BB_B0 K2
43099 #define QM_REG_WRROTHERGRPWEIGHT_3                                                                   0x2f19f4UL //Access:RW   DataWidth:0x8   The actual WRR weight that is used by Other PQ-s that belong to WrrGroup_i (i=0..3). NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrOtherGrpWeight (3-0) are = 0 --> RR (b) if all WrrOtherGrpWeight (3-0) are > 0 --> WRR in that case the WrrOtherGrpWeight should be ordered. WrrOtherGrpWeight_0 should be configured with the smallest value. WrrOtherGrpWeight_1 should be next (and bigger than WrrOtherGrpWeight_0). WrrOtherGrpWeight_2 should be next (and bigger than WrrOtherGrpWeight_1). WrrOtherGrpWeight_3 should be configured with the max value (bigger than WrrOtherGrpWeight_2). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.  Chips: BB_A0 BB_B0 K2
43100 #define QM_REG_WRRTXGRPWEIGHT_0                                                                      0x2f1a08UL //Access:RW   DataWidth:0x8   The actual WRR weight that is used by TX PQ-s that belong to TxPqMap[WrrWeightGrpRng]==2'b01. NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrTxGrpWeight (1-0) are = 0 --> RR (b) if all WrrTxGrpWeight (1-0) are > 0 --> WRR in that case the WrrTxGrpWeight should be ordered. WrrTxGrpWeight_0 should be configured with the smallest value. WrrTxGrpWeight_1 should be configured with the max value (bigger than WrrTxGrpWeight_0). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.  Chips: BB_A0 BB_B0 K2
43101 #define QM_REG_WRRTXGRPWEIGHT_1                                                                      0x2f1a0cUL //Access:RW   DataWidth:0x8   The actual WRR weight that is used by TX PQ-s that belong to TxPqMap[WrrWeightGrpRng]==2'b11. NOTE: weight update is allowed only to queues which are either empty or paused. NOTE: (a) if all WrrTxGrpWeight (1-0) are = 0 --> RR (b) if all WrrTxGrpWeight (1-0) are > 0 --> WRR in that case the WrrTxGrpWeight should be ordered. WrrTxGrpWeight_0 should be configured with the smallest value. WrrTxGrpWeight_1 should be configured with the max value (bigger than WrrTxGrpWeight_0). (c) either (a) or (b) are allowed. Weight=0 for some and weight>0 for others is not legal.  Chips: BB_A0 BB_B0 K2
43102 #define QM_REG_CMINITCRD_0                                                                           0x2f1a10UL //Access:RW   DataWidth:0x4   The initial credit for interface; MCM Secondary.  Chips: BB_A0 BB_B0 K2
43103 #define QM_REG_CMINITCRD_1                                                                           0x2f1a14UL //Access:RW   DataWidth:0x4   The initial credit for interface; MCM Primary.  Chips: BB_A0 BB_B0 K2
43104 #define QM_REG_CMINITCRD_2                                                                           0x2f1a18UL //Access:RW   DataWidth:0x4   The initial credit for interface; UCM Secondary.  Chips: BB_A0 BB_B0 K2
43105 #define QM_REG_CMINITCRD_3                                                                           0x2f1a1cUL //Access:RW   DataWidth:0x4   The initial credit for interface; UCM Primary.  Chips: BB_A0 BB_B0 K2
43106 #define QM_REG_CMINITCRD_4                                                                           0x2f1a20UL //Access:RW   DataWidth:0x4   The initial credit for interface; TCM Secondary.  Chips: BB_A0 BB_B0 K2
43107 #define QM_REG_CMINITCRD_5                                                                           0x2f1a24UL //Access:RW   DataWidth:0x4   The initial credit for interface; TCM Primary.  Chips: BB_A0 BB_B0 K2
43108 #define QM_REG_CMINITCRD_6                                                                           0x2f1a28UL //Access:RW   DataWidth:0x4   The initial credit for interface; YCM Secondary.  Chips: BB_A0 BB_B0 K2
43109 #define QM_REG_CMINITCRD_7                                                                           0x2f1a2cUL //Access:RW   DataWidth:0x4   The initial credit for interface; YCM Primary.  Chips: BB_A0 BB_B0 K2
43110 #define QM_REG_CMINITCRD_8                                                                           0x2f1a30UL //Access:RW   DataWidth:0x4   The initial credit for interface; XCM Secondary.  Chips: BB_A0 BB_B0 K2
43111 #define QM_REG_CMINITCRD_9                                                                           0x2f1a34UL //Access:RW   DataWidth:0x4   The initial credit for interface; XCM Primary.  Chips: BB_A0 BB_B0 K2
43112 #define QM_REG_CMCRD_0                                                                               0x2f1a38UL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43113 #define QM_REG_CMCRD_1                                                                               0x2f1a3cUL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43114 #define QM_REG_CMCRD_2                                                                               0x2f1a40UL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43115 #define QM_REG_CMCRD_3                                                                               0x2f1a44UL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43116 #define QM_REG_CMCRD_4                                                                               0x2f1a48UL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43117 #define QM_REG_CMCRD_5                                                                               0x2f1a4cUL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43118 #define QM_REG_CMCRD_6                                                                               0x2f1a50UL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43119 #define QM_REG_CMCRD_7                                                                               0x2f1a54UL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43120 #define QM_REG_CMCRD_8                                                                               0x2f1a58UL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43121 #define QM_REG_CMCRD_9                                                                               0x2f1a5cUL //Access:R    DataWidth:0x4   The actual credit for the interface; i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43122 #define QM_REG_CMINTEN                                                                               0x2f1a60UL //Access:RW   DataWidth:0xa   A mask bit per CM interface. If this bit is 0 then this interface is masked.  i: 0 - MCM sec; 1 - MCM pri; 2 - UCM sec; 3 - UCM pri; 4 - TCM sec; 5 - TCM pri; 6 - YCM sec; 7 - YCM pri; 8 - XCM sec; 9 - XCM pri;.  Chips: BB_A0 BB_B0 K2
43123 #define QM_REG_CMINTQMASK                                                                            0x2f1c00UL //Access:RW   DataWidth:0x8   A bit vector per CM interface which indicates which one of the Other queues are tied to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pri; 71-64 XCM sec; for addr[2:0]=0 Other queues 7-0; for addr[2:0]=1 Other queues 15-8; for addr[2:0]=7 Other queues 63-56.  Chips: BB_A0 BB_B0 K2
43124 #define QM_REG_CMINTQMASK_SIZE                                                                       72
43125 #define QM_REG_VOQBYTECRDENABLE                                                                      0x2f1e00UL //Access:RW   DataWidth:0x1   Enables the VOQ byte credit logic.  Chips: BB_A0 BB_B0 K2
43126 #define QM_REG_SDMCMDADDR                                                                            0x2f1e04UL //Access:RW   DataWidth:0x8   SDM command address. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.  Chips: BB_A0 BB_B0 K2
43127 #define QM_REG_SDMCMDDATALSB                                                                         0x2f1e08UL //Access:RW   DataWidth:0x20  SDM command data lsb. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.  Chips: BB_A0 BB_B0 K2
43128 #define QM_REG_SDMCMDDATAMSB                                                                         0x2f1e0cUL //Access:RW   DataWidth:0x20  SDM command data msb. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.  Chips: BB_A0 BB_B0 K2
43129 #define QM_REG_SDMCMDREADY                                                                           0x2f1e10UL //Access:R    DataWidth:0x1   SDM command Ready. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: (1) wr value=1; and then (2) wr value=0.  Chips: BB_A0 BB_B0 K2
43130 #define QM_REG_SDMCMDGO                                                                              0x2f1e14UL //Access:RW   DataWidth:0x1   SDM command Ready. This reg is used for sending SDM command through the RBC. See command description in the QM EAS section SDM memory map. Required flow: (a) Poll on the SdmCmdReady bit (i.e. SdmCmdReady=1). (b) Write SdmCmdAddr, SdmCmdDataLsb and SdmCmdDataMsb (c) Send SdmCmdGo command: wr value=1.  Chips: BB_A0 BB_B0 K2
43131 #define QM_REG_PQFILLLVLOTHER                                                                        0x2f2000UL //Access:RW   DataWidth:0x18  The number of tasks queued for each Other queue. Should be read only access.  Chips: BB_A0 BB_B0 K2
43132 #define QM_REG_PQFILLLVLOTHER_SIZE                                                                   128
43133 #define QM_REG_MHQTXNUMSEL                                                                           0x2f2400UL //Access:RW   DataWidth:0x9   The physical queue number for the MAX hold TX queue fill level statistics.  Chips: BB_A0 BB_B0 K2
43134 #define QM_REG_QTXLEVELMHVAL                                                                         0x2f2404UL //Access:RC   DataWidth:0x18  The MAX hold value of the fill level of the TX physical queue.  Chips: BB_A0 BB_B0 K2
43135 #define QM_REG_MHQOTHERNUMSEL                                                                        0x2f2408UL //Access:RW   DataWidth:0x7   The physical queue number for the MAX hold Other queue fill level statistics.  Chips: BB_A0 BB_B0 K2
43136 #define QM_REG_QOTHERLEVELMHVAL                                                                      0x2f240cUL //Access:RC   DataWidth:0x18  The MAX hold value of the fill level of the Other physical queue.  Chips: BB_A0 BB_B0 K2
43137 #define QM_REG_PQSTSOTHER                                                                            0x2f2800UL //Access:R    DataWidth:0x1   The status of the Other PQ-s: bit0 - PQ paused. Should be read only access.  Chips: BB_A0 BB_B0 K2
43138 #define QM_REG_PQSTSOTHER_SIZE                                                                       128
43139 #define QM_REG_SOFT_RESET                                                                            0x2f2c00UL //Access:RW   DataWidth:0x1   Initialization bit command.  Chips: BB_A0 BB_B0 K2
43140 #define QM_REG_PQTX2PF_0                                                                             0x2f2c04UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43141 #define QM_REG_PQTX2PF_1                                                                             0x2f2c08UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43142 #define QM_REG_PQTX2PF_2                                                                             0x2f2c0cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43143 #define QM_REG_PQTX2PF_3                                                                             0x2f2c10UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43144 #define QM_REG_PQTX2PF_4                                                                             0x2f2c14UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43145 #define QM_REG_PQTX2PF_5                                                                             0x2f2c18UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43146 #define QM_REG_PQTX2PF_6                                                                             0x2f2c1cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43147 #define QM_REG_PQTX2PF_7                                                                             0x2f2c20UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43148 #define QM_REG_PQTX2PF_8                                                                             0x2f2c24UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43149 #define QM_REG_PQTX2PF_9                                                                             0x2f2c28UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43150 #define QM_REG_PQTX2PF_10                                                                            0x2f2c2cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43151 #define QM_REG_PQTX2PF_11                                                                            0x2f2c30UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43152 #define QM_REG_PQTX2PF_12                                                                            0x2f2c34UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43153 #define QM_REG_PQTX2PF_13                                                                            0x2f2c38UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43154 #define QM_REG_PQTX2PF_14                                                                            0x2f2c3cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43155 #define QM_REG_PQTX2PF_15                                                                            0x2f2c40UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43156 #define QM_REG_PQTX2PF_16                                                                            0x2f2c44UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43157 #define QM_REG_PQTX2PF_17                                                                            0x2f2c48UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43158 #define QM_REG_PQTX2PF_18                                                                            0x2f2c4cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43159 #define QM_REG_PQTX2PF_19                                                                            0x2f2c50UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43160 #define QM_REG_PQTX2PF_20                                                                            0x2f2c54UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43161 #define QM_REG_PQTX2PF_21                                                                            0x2f2c58UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43162 #define QM_REG_PQTX2PF_22                                                                            0x2f2c5cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43163 #define QM_REG_PQTX2PF_23                                                                            0x2f2c60UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43164 #define QM_REG_PQTX2PF_24                                                                            0x2f2c64UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43165 #define QM_REG_PQTX2PF_25                                                                            0x2f2c68UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43166 #define QM_REG_PQTX2PF_26                                                                            0x2f2c6cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43167 #define QM_REG_PQTX2PF_27                                                                            0x2f2c70UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43168 #define QM_REG_PQTX2PF_28                                                                            0x2f2c74UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43169 #define QM_REG_PQTX2PF_29                                                                            0x2f2c78UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43170 #define QM_REG_PQTX2PF_30                                                                            0x2f2c7cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43171 #define QM_REG_PQTX2PF_31                                                                            0x2f2c80UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43172 #define QM_REG_PQTX2PF_32                                                                            0x2f2c84UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43173 #define QM_REG_PQTX2PF_33                                                                            0x2f2c88UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43174 #define QM_REG_PQTX2PF_34                                                                            0x2f2c8cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43175 #define QM_REG_PQTX2PF_35                                                                            0x2f2c90UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43176 #define QM_REG_PQTX2PF_36                                                                            0x2f2c94UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43177 #define QM_REG_PQTX2PF_37                                                                            0x2f2c98UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43178 #define QM_REG_PQTX2PF_38                                                                            0x2f2c9cUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43179 #define QM_REG_PQTX2PF_39                                                                            0x2f2ca0UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43180 #define QM_REG_PQTX2PF_40                                                                            0x2f2ca4UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43181 #define QM_REG_PQTX2PF_41                                                                            0x2f2ca8UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43182 #define QM_REG_PQTX2PF_42                                                                            0x2f2cacUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43183 #define QM_REG_PQTX2PF_43                                                                            0x2f2cb0UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43184 #define QM_REG_PQTX2PF_44                                                                            0x2f2cb4UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43185 #define QM_REG_PQTX2PF_45                                                                            0x2f2cb8UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43186 #define QM_REG_PQTX2PF_46                                                                            0x2f2cbcUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43187 #define QM_REG_PQTX2PF_47                                                                            0x2f2cc0UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43188 #define QM_REG_PQTX2PF_48                                                                            0x2f2cc4UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43189 #define QM_REG_PQTX2PF_49                                                                            0x2f2cc8UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43190 #define QM_REG_PQTX2PF_50                                                                            0x2f2cccUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43191 #define QM_REG_PQTX2PF_51                                                                            0x2f2cd0UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43192 #define QM_REG_PQTX2PF_52                                                                            0x2f2cd4UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43193 #define QM_REG_PQTX2PF_53                                                                            0x2f2cd8UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43194 #define QM_REG_PQTX2PF_54                                                                            0x2f2cdcUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43195 #define QM_REG_PQTX2PF_55                                                                            0x2f2ce0UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: BB_A0 BB_B0 K2
43196 #define QM_REG_PQTX2PF_56                                                                            0x2f2ce4UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: K2
43197 #define QM_REG_PQTX2PF_57                                                                            0x2f2ce8UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: K2
43198 #define QM_REG_PQTX2PF_58                                                                            0x2f2cecUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: K2
43199 #define QM_REG_PQTX2PF_59                                                                            0x2f2cf0UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: K2
43200 #define QM_REG_PQTX2PF_60                                                                            0x2f2cf4UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: K2
43201 #define QM_REG_PQTX2PF_61                                                                            0x2f2cf8UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: K2
43202 #define QM_REG_PQTX2PF_62                                                                            0x2f2cfcUL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: K2
43203 #define QM_REG_PQTX2PF_63                                                                            0x2f2d00UL //Access:RW   DataWidth:0x4   Describes the PF of each TX queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 440-447: Group55 PFID (i=55); ... PQ 504-511: Group63 PFID (i=63);  Chips: K2
43204 #define QM_REG_PQOTHER2PF_0                                                                          0x2f2e04UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: BB_A0 BB_B0 K2
43205 #define QM_REG_PQOTHER2PF_1                                                                          0x2f2e08UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: BB_A0 BB_B0 K2
43206 #define QM_REG_PQOTHER2PF_2                                                                          0x2f2e0cUL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: BB_A0 BB_B0 K2
43207 #define QM_REG_PQOTHER2PF_3                                                                          0x2f2e10UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: BB_A0 BB_B0 K2
43208 #define QM_REG_PQOTHER2PF_4                                                                          0x2f2e14UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: BB_A0 BB_B0 K2
43209 #define QM_REG_PQOTHER2PF_5                                                                          0x2f2e18UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: BB_A0 BB_B0 K2
43210 #define QM_REG_PQOTHER2PF_6                                                                          0x2f2e1cUL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: BB_A0 BB_B0 K2
43211 #define QM_REG_PQOTHER2PF_7                                                                          0x2f2e20UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: BB_A0 BB_B0 K2
43212 #define QM_REG_PQOTHER2PF_8                                                                          0x2f2e24UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: K2
43213 #define QM_REG_PQOTHER2PF_9                                                                          0x2f2e28UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: K2
43214 #define QM_REG_PQOTHER2PF_10                                                                         0x2f2e2cUL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: K2
43215 #define QM_REG_PQOTHER2PF_11                                                                         0x2f2e30UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: K2
43216 #define QM_REG_PQOTHER2PF_12                                                                         0x2f2e34UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: K2
43217 #define QM_REG_PQOTHER2PF_13                                                                         0x2f2e38UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: K2
43218 #define QM_REG_PQOTHER2PF_14                                                                         0x2f2e3cUL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: K2
43219 #define QM_REG_PQOTHER2PF_15                                                                         0x2f2e40UL //Access:RW   DataWidth:0x4   Describes the PF of each OTHER queue. the mapping is based on 8 PQ groups as follows: PQ 0-7: Group0 PFID (i=0); PQ 8-15: Group1 PFID (i=1); ... PQ 56-63: Group7 PFID (i=7); ... PQ 120-127: Group15 PFID (i=15);  Chips: K2
43220 #define QM_REG_ARB_TX_EN                                                                             0x2f2e64UL //Access:RW   DataWidth:0x1   Enabling the TX PQ arbiter.  Chips: BB_A0 BB_B0 K2
43221 #define QM_REG_ARB_OTHER_EN                                                                          0x2f2e68UL //Access:RW   DataWidth:0x1   Enabling the Other PQ arbiter.  Chips: BB_A0 BB_B0 K2
43222 #define QM_REG_PXP_REQ_CRD_INIT                                                                      0x2f2e6cUL //Access:RW   DataWidth:0x2   Init credit for the pxp request interface.  Chips: BB_A0 BB_B0 K2
43223 #define QM_REG_PXP_REQ_CRD                                                                           0x2f2e70UL //Access:R    DataWidth:0x2   Actual credit for the pxp request interface.  Chips: BB_A0 BB_B0 K2
43224 #define QM_REG_DBG_SELECT                                                                            0x2f2e74UL //Access:RW   DataWidth:0x8   Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for selecting a line to output to the DBG block.  Chips: BB_A0 BB_B0 K2
43225 #define QM_REG_DBG_DWORD_ENABLE                                                                      0x2f2e78UL //Access:RW   DataWidth:0x4   Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for enabling dwords in the selected line (after the select before the shift).  Chips: BB_A0 BB_B0 K2
43226 #define QM_REG_DBG_SHIFT                                                                             0x2f2e7cUL //Access:RW   DataWidth:0x2   Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - for circular right shifting of the selected line (after the enabling).  Chips: BB_A0 BB_B0 K2
43227 #define QM_REG_DBG_FORCE_VALID                                                                       0x2f2e80UL //Access:RW   DataWidth:0x4   Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing valid.  Chips: BB_A0 BB_B0 K2
43228 #define QM_REG_DBG_FORCE_FRAME                                                                       0x2f2e84UL //Access:RW   DataWidth:0x4   Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - forcing frame.  Chips: BB_A0 BB_B0 K2
43229 #define QM_REG_DBG_OUT_DATA_LSB                                                                      0x2f2e88UL //Access:R    DataWidth:0x20  Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 lsb data that goes to the DBG block.  Chips: BB_A0 BB_B0 K2
43230 #define QM_REG_DBG_OUT_DATA_MSB                                                                      0x2f2e8cUL //Access:R    DataWidth:0x20  Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 32 msb data that goes to the DBG block.  Chips: BB_A0 BB_B0 K2
43231 #define QM_REG_DBG_OUT_FRAME                                                                         0x2f2e90UL //Access:R    DataWidth:0x4   Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 frame bits that goes to the DBG block. Bit0 is the frame of data byte0; Bit1 is the frame of  data byte1; Bit2 is the frame of data byte2; Bit3 is the frame of  data byte4.  Chips: BB_A0 BB_B0 K2
43232 #define QM_REG_DBG_OUT_VALID                                                                         0x2f2e94UL //Access:R    DataWidth:0x4   Debug only: For dbgmux usage (debug data that goes from QM to the DBG block) - The 4 valid bits that goes to the DBG block. Bit0 validtes data byte0; Bit1 validates data byte1; Bit2 validates data byte2; Bit3 validates data byte4.  Chips: BB_A0 BB_B0 K2
43233 #define QM_REG_ECO_RESERVED                                                                          0x2f2e98UL //Access:RW   DataWidth:0x8   Eco reserved register.  Chips: BB_A0 BB_B0 K2
43234 #define QM_REG_TXPQMAP_MASKACCESS                                                                    0x2f2e9cUL //Access:RW   DataWidth:0x1   Selects between the Mem Array (0) and the Mask Array (1) when accessing the TxPqMap CAM.  Chips: BB_A0 BB_B0 K2
43235 #define QM_REG_PCI_RD_ERR                                                                            0x2f2ea0UL //Access:RW   DataWidth:0x1   PCI rd error indication. The QM sets this reg upon PXP rdata with error. The driver can clear this bit (through RBC) based on the functional flows (e.g. FLR). It is also possible to set this bit by the RBC but this is used for debug.  Chips: BB_A0 BB_B0 K2
43236 #define QM_REG_PF_EN                                                                                 0x2f2ea4UL //Access:RW   DataWidth:0x1   PF enable vector. Bit per PF. If set the PF is enabled.  Chips: BB_A0 BB_B0 K2
43237 #define QM_REG_VF_EN                                                                                 0x2f2ea8UL //Access:RW   DataWidth:0x1   VF enable vector. Bit per VF. If set the VF is enabled.  Chips: BB_A0 BB_B0 K2
43238 #define QM_REG_USG_CNT_PF_TX                                                                         0x2f2eacUL //Access:RW   DataWidth:0x18  PF Usage counters for TX tasks.  Chips: BB_A0 BB_B0 K2
43239 #define QM_REG_USG_CNT_PF_OTHER                                                                      0x2f2eb0UL //Access:RW   DataWidth:0x18  PF Usage counters for Other tasks.  Chips: BB_A0 BB_B0 K2
43240 #define QM_REG_USG_CNT_VF_TX                                                                         0x2f2eb4UL //Access:RW   DataWidth:0x18  VF Usage counters for TX tasks.  Chips: BB_A0 BB_B0 K2
43241 #define QM_REG_USG_CNT_VF_OTHER                                                                      0x2f2eb8UL //Access:RW   DataWidth:0x18  VF Usage counters for Other tasks.  Chips: BB_A0 BB_B0 K2
43242 #define QM_REG_XSDM_FIFO_FULL_THR                                                                    0x2f2ebcUL //Access:RW   DataWidth:0x4   almost full threshold for the xsdm fifo. the value refer fifo size of 8. if the fifo size is different (for different flow control resources) then the rtl should use this value and compensate for the difference.  Chips: BB_A0 BB_B0 K2
43243 #define QM_REG_YSDM_FIFO_FULL_THR                                                                    0x2f2ec0UL //Access:RW   DataWidth:0x4   almost full threshold for the ysdm fifo. the value refer fifo size of 8. if the fifo size is different (for different flow control resources) then the rtl should use this value and compensate for the difference.  Chips: BB_A0 BB_B0 K2
43244 #define QM_REG_PSDM_FIFO_FULL_THR                                                                    0x2f2ec4UL //Access:RW   DataWidth:0x4   almost full threshold for the psdm fifo. the value refer fifo size of 8. if the fifo size is different (for different flow control resources) then the rtl should use this value and compensate for the difference.  Chips: BB_A0 BB_B0 K2
43245 #define QM_REG_RLGLBLPERIOD_0                                                                        0x2f2ec8UL //Access:RW   DataWidth:0x20  The RL timeout period in 25Mhz clock cycles for the global. VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Global VP/QCN RL Timeout1. NOTE: ck25 domain. sync should be implemented.  Chips: BB_A0 BB_B0 K2
43246 #define QM_REG_RLGLBLPERIOD_1                                                                        0x2f2eccUL //Access:RW   DataWidth:0x20  The RL timeout period in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Global VP/QCN RL Timeout1. NOTE: ck25 domain. sync should be implemented.  Chips: BB_A0 BB_B0 K2
43247 #define QM_REG_RLGLBLPERIODTIMER_0                                                                   0x2f2ed0UL //Access:RW   DataWidth:0x20  The RL timeout period counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. Upon init should be set with value of RlGlblPeriod_0 by the GRC. 1 - Global VP/QCN RL Timeout1. NOTE: ck25 domain. sync should be implemented.  Chips: BB_A0 BB_B0 K2
43248 #define QM_REG_RLGLBLPERIODTIMER_1                                                                   0x2f2ed4UL //Access:RW   DataWidth:0x20  The RL timeout period counter in 25Mhz clock cycles for the global VP/QCN RL-s. 0 - Global VP/QCN RL Timeout0. 1 - Global VP/QCN RL Timeout1. Upon init should be set with value of RlGlblPeriod_1 by the GRC. NOTE: ck25 domain. sync should be implemented.  Chips: BB_A0 BB_B0 K2
43249 #define QM_REG_RLGLBLPERIODSEL_0                                                                     0x2f2ed8UL //Access:RW   DataWidth:0x20  The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224  Chips: BB_A0 BB_B0 K2
43250 #define QM_REG_RLGLBLPERIODSEL_1                                                                     0x2f2edcUL //Access:RW   DataWidth:0x20  The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224  Chips: BB_A0 BB_B0 K2
43251 #define QM_REG_RLGLBLPERIODSEL_2                                                                     0x2f2ee0UL //Access:RW   DataWidth:0x20  The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224  Chips: BB_A0 BB_B0 K2
43252 #define QM_REG_RLGLBLPERIODSEL_3                                                                     0x2f2ee4UL //Access:RW   DataWidth:0x20  The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224  Chips: BB_A0 BB_B0 K2
43253 #define QM_REG_RLGLBLPERIODSEL_4                                                                     0x2f2ee8UL //Access:RW   DataWidth:0x20  The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224  Chips: BB_A0 BB_B0 K2
43254 #define QM_REG_RLGLBLPERIODSEL_5                                                                     0x2f2eecUL //Access:RW   DataWidth:0x20  The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224  Chips: BB_A0 BB_B0 K2
43255 #define QM_REG_RLGLBLPERIODSEL_6                                                                     0x2f2ef0UL //Access:RW   DataWidth:0x20  The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224  Chips: BB_A0 BB_B0 K2
43256 #define QM_REG_RLGLBLPERIODSEL_7                                                                     0x2f2ef4UL //Access:RW   DataWidth:0x20  The RL timeout period that should be selected for the global VP/QCN RL counter per RL Global counter: 0 - use Timeout0; 1 - use Timeout1; Array mapping: 0 - RL-s 31:0; 1 - RL-s 63:32; ... 7 - RL-s 255:224  Chips: BB_A0 BB_B0 K2
43257 #define QM_REG_RLGLBLINCVAL                                                                          0x2f3400UL //Access:RW   DataWidth:0x1f  The RL increment value for the global VP/QCN RL counters.  Chips: BB_A0 BB_B0 K2
43258 #define QM_REG_RLGLBLINCVAL_SIZE                                                                     256
43259 #define QM_REG_RLGLBLUPPERBOUND                                                                      0x2f3c00UL //Access:RW   DataWidth:0x20  The RL upper bound for the global VP/QCN RL counters. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation  Chips: BB_A0 BB_B0 K2
43260 #define QM_REG_RLGLBLUPPERBOUND_SIZE                                                                 256
43261 #define QM_REG_RLGLBLCRD                                                                             0x2f4400UL //Access:RW   DataWidth:0x20  The actual RL credit for the global VP/QCN RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlGlblUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation  Chips: BB_A0 BB_B0 K2
43262 #define QM_REG_RLGLBLCRD_SIZE                                                                        256
43263 #define QM_REG_RLGLBLENABLE                                                                          0x2f4c00UL //Access:RW   DataWidth:0x1   Enabling the global VP/QCN RL mechanism.  Chips: BB_A0 BB_B0 K2
43264 #define QM_REG_RLGLBL_CNT_NUM                                                                        0x2f4c04UL //Access:RW   DataWidth:0x9   number of active RL counters (between 1 to QM_NUM_OF_RL)  Chips: BB_A0 BB_B0 K2
43265 #define QM_REG_RLGLBLCRD_FORCE_STS_UPDATE                                                            0x2f4c08UL //Access:RW   DataWidth:0x1   when 1 - force cam search and update sts_rlglbl_pq_blocked vector even when the rlglblcrd did not change from XON->XOFF or XOFF->XON NOTE: this is valid only for rf_qm_ind_rlglblcrd* command (i.e. access the global RL through the RBC)  Chips: BB_A0 BB_B0 K2
43266 #define QM_REG_ERR_INC0_RLGLBLCRD                                                                    0x2f4c0cUL //Access:RC   DataWidth:0x10  Increment error type0 for the global RL (inc above max allowed value (i.e. overflow the RL credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - periodic timer);  Chips: BB_A0 BB_B0 K2
43267 #define QM_REG_ERR_DEC0_RLGLBLCRD                                                                    0x2f4c10UL //Access:RC   DataWidth:0x10  Decrement error type0 for the global RL (dec below the most neg value (i.e. underflow the RL credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - tx_arb);  Chips: BB_A0 BB_B0 K2
43268 #define QM_REG_ERR_DEC1_RLGLBLCRD                                                                    0x2f4c14UL //Access:RC   DataWidth:0x10  Decrement error type1 for the global RL (dec when the credit counter is already below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b11-b4: rl id; b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - tx_arb);  Chips: BB_A0 BB_B0 K2
43269 #define QM_REG_ERR_MASK_RLGLBLCRD                                                                    0x2f4c18UL //Access:RW   DataWidth:0x4   per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlGlblCrd; b1 - reserved. b2 - Err_Dec0_RlGlblCrd; b3 - Err_Dec1_RlGlblCrd;  Chips: BB_A0 BB_B0 K2
43270 #define QM_REG_RLPFPERIOD                                                                            0x2f4c1cUL //Access:RW   DataWidth:0x20  The RL timeout period in 25Mhz clock cycles for the PF RL-s. NOTE: ck25 domain. sync should be implemented.  Chips: BB_A0 BB_B0 K2
43271 #define QM_REG_RLPFPERIODTIMER                                                                       0x2f4c20UL //Access:RW   DataWidth:0x20  The RL timeout period counter in 25Mhz clock cycles for the PF RL-s. Upon init should be set with value of RlPfPeriod by the GRC. NOTE: ck25 domain. sync should be implemented.  Chips: BB_A0 BB_B0 K2
43272 #define QM_REG_RLPFINCVAL                                                                            0x2f4c80UL //Access:RW   DataWidth:0x1f  The RL increment value for the PF RL counters.  Chips: BB_A0 BB_B0 K2
43273 #define QM_REG_RLPFINCVAL_SIZE                                                                       16
43274 #define QM_REG_RLPFUPPERBOUND                                                                        0x2f4d00UL //Access:RW   DataWidth:0x20  The RL upper bound for the PF RL counters. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation  Chips: BB_A0 BB_B0 K2
43275 #define QM_REG_RLPFUPPERBOUND_SIZE                                                                   16
43276 #define QM_REG_RLPFCRD                                                                               0x2f4d80UL //Access:RW   DataWidth:0x20  The actual RL credit for the PF RL counters. Should be read only access in non-init mode. In init mode should be written with the same value of RlPfUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation  Chips: BB_A0 BB_B0 K2
43277 #define QM_REG_RLPFCRD_SIZE                                                                          16
43278 #define QM_REG_RLPFENABLE                                                                            0x2f4e00UL //Access:RW   DataWidth:0x1   Enabling the PF RL mechanism.  Chips: BB_A0 BB_B0 K2
43279 #define QM_REG_RLPFVOQENABLE                                                                         0x2f4e04UL //Access:RW   DataWidth:0x14  Enabling the PF RL mechanism per VOQ.  Chips: BB_A0 BB_B0 K2
43280 #define QM_REG_ERR_INC0_RLPFCRD                                                                      0x2f4e08UL //Access:RC   DataWidth:0xc   Increment error type0 for the PF RL (inc above max allowed value (i.e. overflow the RL credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: client id (b8 - xsdm; b9 - ysdm; b10 - psdm; b11 - periodic timer);  Chips: BB_A0 BB_B0 K2
43281 #define QM_REG_ERR_DEC0_RLPFCRD                                                                      0x2f4e0cUL //Access:RC   DataWidth:0xc   Decrement error type0 for the PF RL (dec below the most neg value (i.e. underflow the RL credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: client id (b8 - xsdm; b9 - ysdm; b10 - psdm; b11 - tx_arb);  Chips: BB_A0 BB_B0 K2
43282 #define QM_REG_ERR_DEC1_RLPFCRD                                                                      0x2f4e10UL //Access:RC   DataWidth:0xc   Decrement error type1 for the PF RL (dec when the credit counter is already below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b11-b8: client id (b8 - xsdm; b9 - ysdm; b10 - psdm; b11 - tx_arb);  Chips: BB_A0 BB_B0 K2
43283 #define QM_REG_ERR_MASK_RLPFCRD                                                                      0x2f4e14UL //Access:RW   DataWidth:0x4   per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_RlPfCrd; b1 - reserved. b2 - Err_Dec0_RlPfCrd; b3 - Err_Dec1_RlPfCrd;  Chips: BB_A0 BB_B0 K2
43284 #define QM_REG_WFQPFWEIGHT                                                                           0x2f4e80UL //Access:RW   DataWidth:0x1f  The WFQ weight (increment value) for the PF WFQ counters.  Chips: BB_A0 BB_B0 K2
43285 #define QM_REG_WFQPFWEIGHT_SIZE                                                                      16
43286 #define QM_REG_WFQPFUPPERBOUND                                                                       0x2f4f00UL //Access:RW   DataWidth:0x20  The WFQ upper bound for the PF WFQ counters. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation  Chips: BB_A0 BB_B0 K2
43287 #define QM_REG_WFQPFUPPERBOUND_SIZE                                                                  16
43288 #define QM_REG_WFQPFCRD                                                                              0x2f5400UL //Access:RW   DataWidth:0x20  The actual WFQ credit for the PF WFQ counters. Should be read only access in non-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation. Mapping: Counters 0-7 are associated with VOQ0. Counters 8-15 are associated with VOQ1. ... Counters 136-143 are associated with VOQ17. Counters 144-151 are associated with VOQ18 in K2. Counters 152-159 are associated with VOQ19 in K2.  Chips: BB_A0 BB_B0 K2
43289 #define QM_REG_WFQPFCRD_SIZE                                                                         160
43290 #define QM_REG_WFQPFENABLE                                                                           0x2f5c00UL //Access:RW   DataWidth:0x1   Enabling the PF WFQ mechanism.  Chips: BB_A0 BB_B0 K2
43291 #define QM_REG_ERR_INC0_WFQPFCRD                                                                     0x2f5c04UL //Access:RC   DataWidth:0x10  Increment error type0 for the PF WFQ (inc above max allowed value (i.e. overflow the WFQ credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b6-b4: pf id; b11-b8: voq id;  b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - periodic timer);  Chips: BB_A0 BB_B0 K2
43292 #define QM_REG_ERR_DEC0_WFQPFCRD                                                                     0x2f5c08UL //Access:RC   DataWidth:0x10  Decrement error type0 for the PF WFQ (dec below the most neg value (i.e. underflow the WFQ credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b6-b4: pf id; b11-b8: voq id;  b15-b12: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - tx_arb);  Chips: BB_A0 BB_B0 K2
43293 #define QM_REG_ERR_DEC1_WFQPFCRD                                                                     0x2f5c0cUL //Access:RC   DataWidth:0x11  Decrement error type1 for the PF WFQ (dec when the credit counter is already below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b7-b4: pf id; b12-b8: voq id;  b16-b13: client id (b12 - xsdm; b13 - ysdm; b14 - psdm; b15 - tx_arb);  Chips: BB_A0 BB_B0 K2
43294 #define QM_REG_ERR_MASK_WFQPFCRD                                                                     0x2f5c10UL //Access:RW   DataWidth:0x4   per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqPfCrd; b1 - reserved. b2 - Err_Dec0_WfqPfCrd; b3 - Err_Dec1_WfqPfCrd;  Chips: BB_A0 BB_B0 K2
43295 #define QM_REG_WFQVPENABLE                                                                           0x2f5c14UL //Access:RW   DataWidth:0x1   Enabling the VP WFQ mechanism.  Chips: BB_A0 BB_B0 K2
43296 #define QM_REG_WFQVPCRD_FORCE_STS_UPDATE                                                             0x2f5c18UL //Access:RW   DataWidth:0x1   when 1 - force cam search and update sts_wfqvp_pq_blocked vector even when the wfqvpcrd did not change from XON->XOFF or XOFF->XON NOTE: this is valid only for rf_qm_ind_wfqvpcrd* command (i.e. access the global RL through the RBC)  Chips: BB_A0 BB_B0 K2
43297 #define QM_REG_ERR_INC0_WFQVPCRD                                                                     0x2f5c1cUL //Access:RC   DataWidth:0x14  Increment error type0 for the VP WFQ (inc above max allowed value (i.e. overflow the WFQ credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (should be filled with zeroes); b19-b16: client id (b16 - xsdm; b17 - ysdm; b18 - psdm; b19 - periodic timer);  Chips: BB_A0 BB_B0 K2
43298 #define QM_REG_ERR_DEC0_WFQVPCRD                                                                     0x2f5c20UL //Access:RC   DataWidth:0x14  Decrement error type0 for the VP WFQ (dec below the most neg value (i.e. underflow the WFQ credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (should be filled with zeroes); b19-b16: client id (b16 - xsdm; b17 - ysdm; b18 - psdm; b19 - tx_arb);  Chips: BB_A0 BB_B0 K2
43299 #define QM_REG_ERR_DEC1_WFQVPCRD                                                                     0x2f5c24UL //Access:RC   DataWidth:0x14  Decrement error type1 for the VP WFQ (dec when the credit counter is already below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b12-b4: vp id; b15-b13: reserved (should be filled with zeroes); b19-b16: client id (b16 - xsdm; b17 - ysdm; b18 - psdm; b19 - tx_arb);  Chips: BB_A0 BB_B0 K2
43300 #define QM_REG_ERR_MASK_WFQVPCRD                                                                     0x2f5c28UL //Access:RW   DataWidth:0x4   per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_WfqVpCrd; b1 - reserved. b2 - Err_Dec0_WfqVpCrd; b3 - Err_Dec1_WfqVpCrd;  Chips: BB_A0 BB_B0 K2
43301 #define QM_REG_VOQ_ARB_GRP0_WEIGHT_0                                                                 0x2f5c2cUL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43302 #define QM_REG_VOQ_ARB_GRP0_WEIGHT_1                                                                 0x2f5c30UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43303 #define QM_REG_VOQ_ARB_GRP0_WEIGHT_2                                                                 0x2f5c34UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43304 #define QM_REG_VOQ_ARB_GRP0_WEIGHT_3                                                                 0x2f5c38UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43305 #define QM_REG_VOQ_ARB_GRP0_WEIGHT_4                                                                 0x2f5c3cUL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43306 #define QM_REG_VOQ_ARB_GRP0_WEIGHT_5                                                                 0x2f5c40UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43307 #define QM_REG_VOQ_ARB_GRP0_WEIGHT_6                                                                 0x2f5c44UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43308 #define QM_REG_VOQ_ARB_GRP0_WEIGHT_7                                                                 0x2f5c48UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43309 #define QM_REG_VOQ_ARB_GRP1_WEIGHT_0                                                                 0x2f5cacUL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43310 #define QM_REG_VOQ_ARB_GRP1_WEIGHT_1                                                                 0x2f5cb0UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43311 #define QM_REG_VOQ_ARB_GRP1_WEIGHT_2                                                                 0x2f5cb4UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43312 #define QM_REG_VOQ_ARB_GRP1_WEIGHT_3                                                                 0x2f5cb8UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43313 #define QM_REG_VOQ_ARB_GRP1_WEIGHT_4                                                                 0x2f5cbcUL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43314 #define QM_REG_VOQ_ARB_GRP1_WEIGHT_5                                                                 0x2f5cc0UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43315 #define QM_REG_VOQ_ARB_GRP1_WEIGHT_6                                                                 0x2f5cc4UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43316 #define QM_REG_VOQ_ARB_GRP1_WEIGHT_7                                                                 0x2f5cc8UL //Access:RW   DataWidth:0x3   VOQ arbiter strict priority weights. Weight0 - highest priority;...;  Weight7 - lowest priority; Within group of VOQ-s (up to 8 VOQ-s) the priority should be unique for each VOQ. NOTES: (a) The group of VOQ-s depends on the chip port mode. (b) Grp0 represent VOQ-s 7-0 (c) Grp1 represent VOQ-s 15-8 (d) The values to configure are the VOQ id-s.  Chips: BB_A0 BB_B0 K2
43317 #define QM_REG_VOQ_ARB_TIMEOUT                                                                       0x2f5d2cUL //Access:RW   DataWidth:0xc   The number of arbitration cycles between 2 adjacent RR rounds. For anti starvation purpose. Value of 0 will give regular RR arbitration.  Chips: BB_A0 BB_B0 K2
43318 #define QM_REG_TX_ARB_GO_MODE                                                                        0x2f5d30UL //Access:RW   DataWidth:0x1   Represent the TX arbiter GO working mode. Whenever TX arbitration has completed (i.e. chose the PQ and completed updating all the relevant counters and state bits), new TX arbitration will start. When the new TX arbitration cannot start as no PQ can be chosen, the arbiter enters idle state. Moving to non-idle state, trying to start new TX arbitration depends on the GO mode as follows: 0 - start new TX arbitration whenever one of the state bits (VOQ blocked, PF WFQ blocked, VP WFQ blocked, PF RL blocked, VP/QCN RL blocked, Q active, Q paused) changes its state (either XON or XOFF). 1 - start new TX arbitration whenever Tx_Arb_Go_Cycle_Period of cycles has passed from since the last time TX arbitration has started.  Chips: BB_A0 BB_B0 K2
43319 #define QM_REG_TX_ARB_GO_CYCLE_PERIOD                                                                0x2f5d34UL //Access:RW   DataWidth:0xa   The number of cycles between 2 adjacent TX arbitrations. Valid only when Tx_Arb_Go_Mode==1  Chips: BB_A0 BB_B0 K2
43320 #define QM_REG_PQ_ACTIVE_ENABLE                                                                      0x2f5d38UL //Access:RW   DataWidth:0x1   Enable the active state mechanism logic.  Chips: BB_A0 BB_B0 K2
43321 #define QM_REG_ERR_INC0_VOQLINECRD                                                                   0x2f5d3cUL //Access:RC   DataWidth:0xd   Increment error type0 for the VOQ Line (inc above max allowed value (i.e. overflow the VOQ Line credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b8-b4: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - pbf)  Chips: BB_A0 BB_B0 K2
43322 #define QM_REG_ERR_INC1_VOQLINECRD                                                                   0x2f5d40UL //Access:RC   DataWidth:0xd   Increment error type1 for the VOQ Line (inc above init value. b0 - error valid; b3-b1: reserved (should be filled with zeroes); b8-b4: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - pbf)  Chips: BB_A0 BB_B0 K2
43323 #define QM_REG_ERR_DEC0_VOQLINECRD                                                                   0x2f5d44UL //Access:RC   DataWidth:0xd   Decrement error type0 for the VOQ Line (dec below the most neg value (i.e. underflow the VOQ Line credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b8-b4: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - tx_arb)  Chips: BB_A0 BB_B0 K2
43324 #define QM_REG_ERR_DEC1_VOQLINECRD                                                                   0x2f5d48UL //Access:RC   DataWidth:0xd   Decrement error type1 for the VOQ Line (dec when the credit counter is below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b8-b4: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - tx_arb)  Chips: BB_A0 BB_B0 K2
43325 #define QM_REG_ERR_MASK_VOQLINECRD                                                                   0x2f5d4cUL //Access:RW   DataWidth:0x4   per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqLineCrd; b1 - Err_Inc1_VoqLineCrd. b2 - Err_Dec0_VoqLineCrd; b3 - Err_Dec1_VoqLineCrd;  Chips: BB_A0 BB_B0 K2
43326 #define QM_REG_ERR_INC0_VOQBYTECRD                                                                   0x2f5d50UL //Access:RC   DataWidth:0xd   Increment error type0 for the VOQ Byte (inc above max allowed value (i.e. overflow the VOQ Byte credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b8-b4: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - btb)  Chips: BB_A0 BB_B0 K2
43327 #define QM_REG_ERR_INC1_VOQBYTECRD                                                                   0x2f5d54UL //Access:RC   DataWidth:0xd   Increment error type1 for the VOQ Byte (inc above init value. b0 - error valid; b3-b1: reserved (should be filled with zeroes); b8-b4: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - btb)  Chips: BB_A0 BB_B0 K2
43328 #define QM_REG_ERR_DEC0_VOQBYTECRD                                                                   0x2f5d58UL //Access:RC   DataWidth:0xd   Decrement error type0 for the VOQ Byte (dec below the most neg value (i.e. underflow the VOQ Byte credit counter)) b0 - error valid; b3-b1: reserved (should be filled with zeroes); b8-b4: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - tx_arb)  Chips: BB_A0 BB_B0 K2
43329 #define QM_REG_ERR_DEC1_VOQBYTECRD                                                                   0x2f5d5cUL //Access:RC   DataWidth:0xd   Decrement error type1 for the VOQ Byte (dec when the credit counter is below zero). b0 - error valid; b3-b1: reserved (should be filled with zeroes); b8-b4: voq id;  b12-b9: client id (b9 - xsdm; b10 - ysdm; b11 - psdm; b12 - tx_arb)  Chips: BB_A0 BB_B0 K2
43330 #define QM_REG_ERR_MASK_VOQBYTECRD                                                                   0x2f5d60UL //Access:RW   DataWidth:0x4   per error type bit mask vector. when 1 - error should be logged. when 0 - error is not logged. b0 - Err_Inc0_VoqByteCrd; b1 - Err_Inc1_VoqByteCrd. b2 - Err_Dec0_VoqByteCrd; b3 - Err_Dec1_VoqByteCrd;  Chips: BB_A0 BB_B0 K2
43331 #define QM_REG_FIFO_EMPTY0                                                                           0x2f5d64UL //Access:R    DataWidth:0x20  Empty indication for all FIFOs.  Chips: BB_A0 BB_B0 K2
43332 #define QM_REG_FIFO_EMPTY1                                                                           0x2f5d68UL //Access:R    DataWidth:0x20  Empty indication for all FIFOs.  Chips: BB_A0 BB_B0 K2
43333 #define QM_REG_FIFO_FULL0                                                                            0x2f5d6cUL //Access:R    DataWidth:0x20  Full indication for all FIFOs.  Chips: BB_A0 BB_B0 K2
43334 #define QM_REG_FIFO_FULL1                                                                            0x2f5d70UL //Access:R    DataWidth:0x20  Full indication for all FIFOs.  Chips: BB_A0 BB_B0 K2
43335 #define QM_REG_FIFO_ERROR0                                                                           0x2f5d74UL //Access:R    DataWidth:0x20  Error indication for all FIFOs.  Chips: BB_A0 BB_B0 K2
43336 #define QM_REG_FIFO_ERROR1                                                                           0x2f5d78UL //Access:R    DataWidth:0x20  Error indication for all FIFOs.  Chips: BB_A0 BB_B0 K2
43337 #define QM_REG_MEM_INIT_GO                                                                           0x2f5d7cUL //Access:RW   DataWidth:0x1   Init go command. Upon Wr value of 1, the enabled mems (Mem_Init_Mask_0/1) will be initialized with value of Mem_Init_Value_0/1. NOTES: (a) Go command can be sent only when the mem init unit is ready (Mem_Init_Ready=1). the user is responsible to verify that prior to sending go command. (b) Go command can be sent only in init mode (i.e. no functional traffic is allowed). (c) Upon Go command and until the init is done (Mem_Init_Ready), RBC access to the mems that are being initialized (Mem_Init_Mask_0/1) is not allowed.  Chips: BB_A0 BB_B0 K2
43338 #define QM_REG_MEM_INIT_READY                                                                        0x2f5d80UL //Access:R    DataWidth:0x1   When set indicates that the mem init unit is ready to accept mem init command (Mem_Init_Go)  Chips: BB_A0 BB_B0 K2
43339 #define QM_REG_MEM_INIT_MASK_0                                                                       0x2f5d84UL //Access:RW   DataWidth:0x20  Indicates which mem to init upon Mem_Init_Go command. When set the mem is initiazlied. when reset the mem in not initiazlied. There is mask bit per mem, the following are mems 31-0: b0: qm_mem_bigram_tx b1: qm_mem_bigram_other b2: qm_mem_pq_fill_lvl_tx b3: qm_mem_pq_fill_lvl_other b4: qm_mem_voq_init_crd_line b5: qm_mem_voq_init_crd_byte b6: qm_mem_voq_crd_line b7: qm_mem_voq_crd_byte b8: qm_mem_rl_glbl_inc_val b9: qm_mem_rl_glbl_ubound b10: qm_mem_rl_glbl_crd b11: qm_mem_rl_pf_inc_val b12: qm_mem_rl_pf_ubound b13: qm_mem_rl_pf_crd b14: qm_mem_wfq_pf_weight b15: qm_mem_wfq_pf_ubound b16: qm_mem_wfq_pf_crd b17: qm_mem_wfq_vp_weight b18: qm_mem_wfq_vp_ubound b19: qm_mem_wfq_vp_crd b20: qm_mem_base_addr_tx b21: qm_mem_base_addr_other b22: qm_mem_ptr_tbl_tx b23: qm_mem_ptr_tbl_other b24: qm_mem_pf_usg_cnt b25: qm_mem_vf_usg_cnt b26: qm_mem_wrc_fifo_xcm_tx b27: qm_mem_wrc_fifo_xcm_other b28: qm_mem_wrc_fifo_ycm_other b29: qm_mem_wrc_fifo_tcm_other b30: qm_mem_wrc_fifo_mcm_other b31: qm_mem_wrc_fifo_ucm_other  Chips: BB_A0 BB_B0 K2
43340 #define QM_REG_MEM_INIT_MASK_1                                                                       0x2f5d88UL //Access:RW   DataWidth:0x20  Indicates which mem to init upon Mem_Init_Go command. When set the mem is initiazlied. when reset the mem in not initiazlied. There is mask bit per mem, the following are mems 63-32: b32: qm_mem_cfc_ldreq_buffer_ccfc_tx b33: qm_mem_cfc_ldreq_buffer_ccfc_other b34: qm_mem_cfc_ldreq_buffer_tcfc_other b35: qm_mem_pxp_req_fifo_tx b36: qm_mem_pxp_req_fifo_other b37: qm_mem_pxp_wdata_fifo_tx b38: qm_mem_pxp_wdata_fifo_other b39: qm_mem_xsdm_voq_line b40: qm_mem_ysdm_voq_line b41: qm_mem_psdm_voq_line b42: qm_mem_xsdm_voq_byte b43: qm_mem_ysdm_voq_byte b44: qm_mem_psdm_voq_byte b45: qm_mem_xsdm_rl_glbl b46: qm_mem_ysdm_rl_glbl b47: qm_mem_psdm_rl_glbl b48: qm_mem_xsdm_rl_pf b49: qm_mem_ysdm_rl_pf b50: qm_mem_psdm_rl_pf b51: qm_mem_xsdm_wfq_pf b52: qm_mem_ysdm_wfq_pf b53: qm_mem_psdm_wfq_pf b54: qm_mem_xsdm_wfq_vp b55: qm_mem_ysdm_wfq_vp b56: qm_mem_psdm_wfq_vp b57: qm_mem_cm_int_q_mask b58: qm_mem_sync_rl_rf_req b59: qm_mem_sync_rl_rf_res b60: qm_mem_sync_rl_glbl_exp b61: qm_mem_sync_rl_pf_exp b62: qm_mem_vp_arb_last_gnt b63: qm_mem_pq_arb_last_gnt  Chips: BB_A0 BB_B0 K2
43341 #define QM_REG_MEM_INIT_VALUE_0                                                                      0x2f5d8cUL //Access:RW   DataWidth:0x20  Indicates the init value to write upon Mem_Init_Go command When set the mem is initialized with all ones. when reset the mem in initialized with all zeroes. There is bit per mem, the following are mems 31-0: b0: qm_mem_bigram_tx b1: qm_mem_bigram_other b2: qm_mem_pq_fill_lvl_tx b3: qm_mem_pq_fill_lvl_other b4: qm_mem_voq_init_crd_line b5: qm_mem_voq_init_crd_byte b6: qm_mem_voq_crd_line b7: qm_mem_voq_crd_byte b8: qm_mem_rl_glbl_inc_val b9: qm_mem_rl_glbl_ubound b10: qm_mem_rl_glbl_crd b11: qm_mem_rl_pf_inc_val b12: qm_mem_rl_pf_ubound b13: qm_mem_rl_pf_crd b14: qm_mem_wfq_pf_weight b15: qm_mem_wfq_pf_ubound b16: qm_mem_wfq_pf_crd b17: qm_mem_wfq_vp_weight_ b18: qm_mem_wfq_vp_ubound_ b19: qm_mem_wfq_vp_crd b20: qm_mem_base_addr_tx b21: qm_mem_base_addr_other b22: qm_mem_ptr_tbl_tx b23: qm_mem_ptr_tbl_other b24: qm_mem_pf_usg_cnt b25: qm_mem_vf_usg_cnt b26: qm_mem_wrc_fifo_xcm_tx b27: qm_mem_wrc_fifo_xcm_other b28: qm_mem_wrc_fifo_ycm_other b29: qm_mem_wrc_fifo_tcm_other b30: qm_mem_wrc_fifo_mcm_other b31: qm_mem_wrc_fifo_ucm_other  Chips: BB_A0 BB_B0 K2
43342 #define QM_REG_MEM_INIT_VALUE_1                                                                      0x2f5d90UL //Access:RW   DataWidth:0x20  Indicates the init value to write upon Mem_Init_Go command When set the mem is initialized with all ones. when reset the mem in initialized with all zeroes. There is bit per mem, the following are mems 63-32: b32: qm_mem_cfc_ldreq_buffer_ccfc_tx b33: qm_mem_cfc_ldreq_buffer_ccfc_other b34: qm_mem_cfc_ldreq_buffer_tcfc_other b35: qm_mem_pxp_req_fifo_tx b36: qm_mem_pxp_req_fifo_other b37: qm_mem_pxp_wdata_fifo_tx b38: qm_mem_pxp_wdata_fifo_other b39: qm_mem_xsdm_voq_line b40: qm_mem_ysdm_voq_line b41: qm_mem_psdm_voq_line b42: qm_mem_xsdm_voq_byte b43: qm_mem_ysdm_voq_byte b44: qm_mem_psdm_voq_byte b45: qm_mem_xsdm_rl_glbl b46: qm_mem_ysdm_rl_glbl b47: qm_mem_psdm_rl_glbl b48: qm_mem_xsdm_rl_pf b49: qm_mem_ysdm_rl_pf b50: qm_mem_psdm_rl_pf b51: qm_mem_xsdm_wfq_pf b52: qm_mem_ysdm_wfq_pf b53: qm_mem_psdm_wfq_pf b54: qm_mem_xsdm_wfq_vp b55: qm_mem_ysdm_wfq_vp b56: qm_mem_psdm_wfq_vp b57: qm_mem_cm_int_q_mask b58: qm_mem_sync_rl_rf_req b59: qm_mem_sync_rl_rf_res b60: qm_mem_sync_rl_glbl_exp b61: qm_mem_sync_rl_pf_exp b62: qm_mem_vp_arb_last_gnt b63: qm_mem_pq_arb_last_gnt  Chips: BB_A0 BB_B0 K2
43343 #define QM_REG_MEM_INIT_STS_0                                                                        0x2f5d94UL //Access:R    DataWidth:0x20  Describes the status of the mem. When set indicates that the mem is not currently being initialized. When set indicates that the mem is currently being initialized. There is status bit per mem, the following are mems 31-0: b0: qm_mem_bigram_tx b1: qm_mem_bigram_other b2: qm_mem_pq_fill_lvl_tx b3: qm_mem_pq_fill_lvl_other b4: qm_mem_voq_init_crd_line b5: qm_mem_voq_init_crd_byte b6: qm_mem_voq_crd_line b7: qm_mem_voq_crd_byte b8: qm_mem_rl_glbl_inc_val b9: qm_mem_rl_glbl_ubound b10: qm_mem_rl_glbl_crd b11: qm_mem_rl_pf_inc_val b12: qm_mem_rl_pf_ubound b13: qm_mem_rl_pf_crd b14: qm_mem_wfq_pf_weight b15: qm_mem_wfq_pf_ubound b16: qm_mem_wfq_pf_crd b17: qm_mem_wfq_vp_weight_ b18: qm_mem_wfq_vp_ubound_ b19: qm_mem_wfq_vp_crd b20: qm_mem_base_addr_tx b21: qm_mem_base_addr_other b22: qm_mem_ptr_tbl_tx b23: qm_mem_ptr_tbl_other b24: qm_mem_pf_usg_cnt b25: qm_mem_vf_usg_cnt b26: qm_mem_wrc_fifo_xcm_tx b27: qm_mem_wrc_fifo_xcm_other b28: qm_mem_wrc_fifo_ycm_other b29: qm_mem_wrc_fifo_tcm_other b30: qm_mem_wrc_fifo_mcm_other b31: qm_mem_wrc_fifo_ucm_other  Chips: BB_A0 BB_B0 K2
43344 #define QM_REG_MEM_INIT_STS_1                                                                        0x2f5d98UL //Access:R    DataWidth:0x20  Describes the status of the mem. When set indicates that the mem is not currently being initialized. When set indicates that the mem is currently being initialized. There is status bit per mem, the following are mems 63-32: b32: qm_mem_cfc_ldreq_buffer_ccfc_tx b33: qm_mem_cfc_ldreq_buffer_ccfc_other b34: qm_mem_cfc_ldreq_buffer_tcfc_other b35: qm_mem_pxp_req_fifo_tx b36: qm_mem_pxp_req_fifo_other b37: qm_mem_pxp_wdata_fifo_tx b38: qm_mem_pxp_wdata_fifo_other b39: qm_mem_xsdm_voq_line b40: qm_mem_ysdm_voq_line b41: qm_mem_psdm_voq_line b42: qm_mem_xsdm_voq_byte b43: qm_mem_ysdm_voq_byte b44: qm_mem_psdm_voq_byte b45: qm_mem_xsdm_rl_glbl b46: qm_mem_ysdm_rl_glbl b47: qm_mem_psdm_rl_glbl b48: qm_mem_xsdm_rl_pf b49: qm_mem_ysdm_rl_pf b50: qm_mem_psdm_rl_pf b51: qm_mem_xsdm_wfq_pf b52: qm_mem_ysdm_wfq_pf b53: qm_mem_psdm_wfq_pf b54: qm_mem_xsdm_wfq_vp b55: qm_mem_ysdm_wfq_vp b56: qm_mem_psdm_wfq_vp b57: qm_mem_cm_int_q_mask b58: qm_mem_sync_rl_rf_req b59: qm_mem_sync_rl_rf_res b60: qm_mem_sync_rl_glbl_exp b61: qm_mem_sync_rl_pf_exp b62: qm_mem_vp_arb_last_gnt b63: qm_mem_pq_arb_last_gnt  Chips: BB_A0 BB_B0 K2
43345 #define QM_REG_CAM_BIST_EN                                                                           0x2f5d9cUL //Access:RW   DataWidth:0x1   Used to enable/disable BIST mode. When set, BIST testing will be performed and the results will be posted upon completion. When cleared CAM access will be enabled through the CAM BIST mechanism instead.  Chips: BB_A0 BB_B0 K2
43346 #define QM_REG_CAM_BIST_SKIP_ERROR_CNT                                                               0x2f5da0UL //Access:RW   DataWidth:0x8   Provides a threshold for the number of CAM BIST errors that are acceptable before reporting CAM BIST failure status.  Chips: BB_A0 BB_B0 K2
43347 #define QM_REG_CAM_BIST_STATUS_SEL                                                                   0x2f5da4UL //Access:RW   DataWidth:0x8   Used to select the BIST status word to read following the completion of a BIST test. Also used to select the data slice when writing data directly to the CAM using the CAM BIST mechanism.  Chips: BB_A0 BB_B0 K2
43348 #define QM_REG_CAM_BIST_STATUS                                                                       0x2f5da8UL //Access:R    DataWidth:0x16  Provides read-only access to the BIST status word selected by cam_bist_status_sel.  Chips: BB_A0 BB_B0 K2
43349 #define QM_REG_BASEADDRTXPQ                                                                          0x2f6000UL //Access:RW   DataWidth:0x14  The base logical address (in 4096 bytes) of each physical queue. The index I represents the physical queue number.  Chips: BB_A0 BB_B0 K2
43350 #define QM_REG_BASEADDRTXPQ_SIZE                                                                     512
43351 #define QM_REG_PQFILLLVLTX                                                                           0x2f7000UL //Access:RW   DataWidth:0x18  The number of tasks queued for each TX queue. Should be read only access.  Chips: BB_A0 BB_B0 K2
43352 #define QM_REG_PQFILLLVLTX_SIZE                                                                      512
43353 #define QM_REG_PQSTSTX                                                                               0x2f8000UL //Access:R    DataWidth:0x4   The status of the TX PQ-s: bit0 - PQ global VP/QCN RL block; bit1 - PQ active; bit2 - PQ paused; bit3 - PQ VP WFQ blocked. Should be read only access.  Chips: BB_A0 BB_B0 K2
43354 #define QM_REG_PQSTSTX_SIZE                                                                          512
43355 #define QM_REG_TXPQMAP                                                                               0x2f9000UL //Access:RW   DataWidth:0x20  (1) Mem Array: Maps between TX PQ and its resources as follows: bit  0     - PQ valid; bits 8:1   - RL id; bits 17:9  - VP id (value of all ones is reserved for pure-LB VOQ VP-s. no WFQ is implemented for such VP-s); bits 22:18 - Voq id; bits 24:23 - WRR weight group (allowed values: 2'b00 (associated with weight=0); 2'b01 (associated with weight=WrrTxGrpWeight_0); 2'b11 (associated with weight=WrrTxGrpWeight_1)); bit  25    - RL valid;  NOTE: the reserved bits must be written with zeroes. (2) Mask Array: Should be written with the same value as the mem array. (3) NOTES: (a) The Mask array exist as the TxPqMap struct is implemented with. (b) TxPqMap_MaskAccess selects if writing to the mask array (set) or the mem array (reset).  Chips: BB_A0 BB_B0 K2
43356 #define QM_REG_TXPQMAP_SIZE                                                                          512
43357 #define QM_REG_WFQVPWEIGHT                                                                           0x2fa000UL //Access:RW   DataWidth:0x1f  The WFQ weight (increment value) for the VP WFQ counters.  Chips: BB_A0 BB_B0 K2
43358 #define QM_REG_WFQVPWEIGHT_SIZE                                                                      512
43359 #define QM_REG_WFQVPUPPERBOUND                                                                       0x2fb000UL //Access:RW   DataWidth:0x20  The WFQ upper bound for the VP WFQ counters. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation  Chips: BB_A0 BB_B0 K2
43360 #define QM_REG_WFQVPUPPERBOUND_SIZE                                                                  512
43361 #define QM_REG_WFQVPCRD                                                                              0x2fc000UL //Access:RW   DataWidth:0x20  The actual WFQ credit for the VP WFQ counters. Should be read only access in non-init mode. In init mode should be written with the same value of WfqVpUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation  Chips: BB_A0 BB_B0 K2
43362 #define QM_REG_WFQVPCRD_SIZE                                                                         512
43363 #define QM_REG_WFQVPMAP                                                                              0x2fd000UL //Access:RW   DataWidth:0x9   (1) Mem Array: Maps between VP WFQ counter and its resources as follows: bit  4:0   - Voq id; bit  7:5   - Pf id; (2) NOTE: valud of 0xff indicates the Wfq Vp counter is not associated with any Voq and Pf  Chips: BB_A0 BB_B0 K2
43364 #define QM_REG_WFQVPMAP_SIZE                                                                         512
43365 #define QM_REG_PTRTBLTX                                                                              0x2fe000UL //Access:WB   DataWidth:0x36  Pointer Table Memory for TX queues 447-0; The mapping is as follow: ptrtbl[53:30] read pointer; ptrtbl[29:6] write pointer; ptrtbl[5:4] read bank0; ptrtbl[3:2] read bank 1; ptrtbl[1:0] write bank;.  Chips: BB_A0 BB_B0 K2
43366 #define QM_REG_PTRTBLTX_SIZE                                                                         1024
43367 #define QM_REG_CMINTQMASK_MSB                                                                        0x2ff000UL //Access:RW   DataWidth:0x8   An MSB bit vector per CM interface which indicates which one of the Other queues are tied to the matched CM interface. address: 7-0 MCM sec; 15-8 MCM pri; 23-16 UCM sec; 31-24 UCM pri; 39-32 TCM sec; 47-40 TCM pri; 55-48 YCM sec; 63-56 YCM pri; 71-64 XCM sec; for addr[2:0]=0 Other queues 7-0; for addr[2:0]=1 Other queues 15-8; for addr[2:0]=7 Other queues 63-56.  Chips: K2
43368 #define QM_REG_CMINTQMASK_MSB_SIZE                                                                   72
43369 #define QM_REG_WFQPFCRD_MSB                                                                          0x2ff400UL //Access:RW   DataWidth:0x20  The actual WFQ credit for the PF WFQ counters. Should be read only access in non-init mode. In init mode should be written with the same value of WfqPfUpperBound. Sign: the msb is used for sign as follows: 1 - positive number or zero. 0 - negative number the rest of the bits (msb-1) to 0 are in 2s complement representation. Mapping: Counters 0-7 are associated with 8 MSB PF of VOQ0 in K2. Counters 8-15 are associated with  8 MSB PF of VOQ1 in K2. ... Counters 136-143 are associated with 8 MSB PF of VOQ17 in K2. Counters 144-151 are associated with 8 MSB PF of VOQ18 in K2. Counters 152-159 are associated with 8 MSB PF of VOQ19 in K2.  Chips: K2
43370 #define QM_REG_WFQPFCRD_MSB_SIZE                                                                     160
43371 #define RDIF_REG_RESET_MEMORIES                                                                      0x300000UL //Access:W    DataWidth:0x1   Write one to this register will write zero to all L1 entries. When the command is complete zero will be indicated in this register.  Chips: BB_A0 BB_B0 K2
43372 #define RDIF_REG_STOP_ON_ERROR                                                                       0x300040UL //Access:RW   DataWidth:0x1   If set and DIF block found error; the DIF block will be stuck - hard reset is needed.  Chips: BB_A0 BB_B0 K2
43373 #define RDIF_REG_BYPASS_MODE_EN                                                                      0x300044UL //Access:RW   DataWidth:0x1   If set allow bypass the pipline on pass through commands and in an empty system.  Chips: BB_A0 BB_B0 K2
43374 #define RDIF_REG_ECO_RESERVED                                                                        0x300048UL //Access:RW   DataWidth:0x8   ECO reserved.  Chips: BB_A0 BB_B0 K2
43375 #define RDIF_REG_MIN_EOB2WF_L1_RD_DEL                                                                0x30004cUL //Access:RW   DataWidth:0x6   If the L1 of an LTID is not updated since EOB within the configured number of cycles the dirty_l1 register will be set. Configuring 0 is the same as 1.  Chips: BB_B0 K2
43376 #define RDIF_REG_DIRTY_L1                                                                            0x300054UL //Access:R    DataWidth:0x1   Indicates that there is a pending L1 WB. Set only if this is the case for at least min_eob2wf_l1_rd_del cycles.  Chips: BB_B0 K2
43377 #define RDIF_REG_DEBUG_BUFER_0_READ_EN                                                               0x300058UL //Access:W    DataWidth:0x1   Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_0_data_0..8.  Chips: BB_A0 BB_B0 K2
43378 #define RDIF_REG_DEBUG_BUFER_0_READ_EN_SIZE                                                          2
43379 #define RDIF_REG_DEBUG_BUFER_1_READ_EN                                                               0x300068UL //Access:W    DataWidth:0x1   Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_1_data_0..8.  Chips: BB_A0 BB_B0 K2
43380 #define RDIF_REG_DEBUG_BUFER_1_READ_EN_SIZE                                                          2
43381 #define RDIF_REG_DEBUG_COMMAND_FIFO_EMPTY                                                            0x300070UL //Access:R    DataWidth:0x1   Debug: 1 =  fifo is empty.  Chips: BB_A0 BB_B0 K2
43382 #define RDIF_REG_DEBUG_ORDER_FIFO_EMPTY                                                              0x300074UL //Access:R    DataWidth:0x1   Debug: 1 =  fifo is empty.  Chips: BB_A0 BB_B0 K2
43383 #define RDIF_REG_DEBUG_RDATA_FIFO_EMPTY                                                              0x300078UL //Access:R    DataWidth:0x1   Debug: 1 =  fifo is empty.  Chips: BB_A0 BB_B0 K2
43384 #define RDIF_REG_DEBUG_ERROR_DATA_VALID                                                              0x30007cUL //Access:RW   DataWidth:0x8   If bit i is set; the data in the debug_error_info address[5:3] = i is valid. By writing 1 to bit j it will clear the valid bits of bit j.  Chips: BB_A0 BB_B0 K2
43385 #define RDIF_REG_DEBUG_BUFFER_0_DATA_0                                                               0x300080UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. TID.  Chips: BB_A0 BB_B0 K2
43386 #define RDIF_REG_DEBUG_BUFFER_0_DATA_1                                                               0x300084UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Initial referance tag.  Chips: BB_A0 BB_B0 K2
43387 #define RDIF_REG_DEBUG_BUFFER_0_DATA_2                                                               0x300088UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [15:0] - application tag; [31:16] - application mask.  Chips: BB_A0 BB_B0 K2
43388 #define RDIF_REG_DEBUG_BUFFER_0_DATA_3                                                               0x30008cUL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calculated checksum.  Chips: BB_A0 BB_B0 K2
43389 #define RDIF_REG_DEBUG_BUFFER_0_DATA_4                                                               0x300090UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Calculated offset in IO.  Chips: BB_A0 BB_B0 K2
43390 #define RDIF_REG_DEBUG_BUFFER_0_DATA_5                                                               0x300094UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Partial DIF/DIX data - referance tag.  Chips: BB_A0 BB_B0 K2
43391 #define RDIF_REG_DEBUG_BUFFER_0_DATA_6                                                               0x300098UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application tag; [31:0] CRC/checksum.  Chips: BB_A0 BB_B0 K2
43392 #define RDIF_REG_DEBUG_BUFFER_0_DATA_7                                                               0x30009cUL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [31] partial_chksum_overflow ; [30:27] dif_bytes_tx ; [26:23] dif_bytes_rx ; [22:19] last_dif_size; [18] eob_flag ; [17] data_is_dix ; [16] set_id ; [15:13] protocol_id; [12:9] type;  [8:0] ltid.  Chips: BB_A0 BB_B0 K2
43393 #define RDIF_REG_DEBUG_BUFFER_0_DATA_8                                                               0x3000a0UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [20:19]  dix_size; [18] ni ; [17:16] hi ; [15:13] interval_size ; [12] fwrd_ref ; [11] fwrd_app ; [10]  fwrd_guard ; [9] validate_ref ; [8] validate_app ; [7] validate_guard ; [6] crc_seed ; [5:4] protection_type ; [3]  set_err_with_eop ; [2] host_guard_is_crc ; [1]  initial_ref_tag_valid; [0] err_in_io.  Chips: BB_A0 BB_B0 K2
43394 #define RDIF_REG_DEBUG_BUFFER_1_DATA_0                                                               0x3000a4UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. TID.  Chips: BB_A0 BB_B0 K2
43395 #define RDIF_REG_DEBUG_BUFFER_1_DATA_1                                                               0x3000a8UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Initial referance tag.  Chips: BB_A0 BB_B0 K2
43396 #define RDIF_REG_DEBUG_BUFFER_1_DATA_2                                                               0x3000acUL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [15:0] - application tag; [31:16] - application mask.  Chips: BB_A0 BB_B0 K2
43397 #define RDIF_REG_DEBUG_BUFFER_1_DATA_3                                                               0x3000b0UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calculated checksum.  Chips: BB_A0 BB_B0 K2
43398 #define RDIF_REG_DEBUG_BUFFER_1_DATA_4                                                               0x3000b4UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Calculated offset in IO.  Chips: BB_A0 BB_B0 K2
43399 #define RDIF_REG_DEBUG_BUFFER_1_DATA_5                                                               0x3000b8UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Partial DIF/DIX data - referance tag.  Chips: BB_A0 BB_B0 K2
43400 #define RDIF_REG_DEBUG_BUFFER_1_DATA_6                                                               0x3000bcUL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application tag; [31:0] CRC/checksum.  Chips: BB_A0 BB_B0 K2
43401 #define RDIF_REG_DEBUG_BUFFER_1_DATA_7                                                               0x3000c0UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [31] partial_chksum_overflow ; [30:27] dif_bytes_tx ; [26:23] dif_bytes_rx ; [22:19] last_dif_size; [18] eob_flag ; [17] data_is_dix ; [16] set_id ; [15:13] protocol_id; [12:9] type;  [8:0] ltid.  Chips: BB_A0 BB_B0 K2
43402 #define RDIF_REG_DEBUG_BUFFER_1_DATA_8                                                               0x3000c4UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [20:19]  dix_size; [18] ni ; [17:16] hi ; [15:13] interval_size ; [12] fwrd_ref ; [11] fwrd_app ; [10]  fwrd_guard ; [9] validate_ref ; [8] validate_app ; [7] validate_guard ; [6] crc_seed ; [5:4] protection_type ; [3]  set_err_with_eop ; [2] host_guard_is_crc ; [1]  initial_ref_tag_valid; [0] err_in_io.  Chips: BB_A0 BB_B0 K2
43403 #define RDIF_REG_DEBUG_DIX_FIFO_EMPTY                                                                0x3000c8UL //Access:R    DataWidth:0x1   Debug: one bit for each protocol ID.  1 =  fifo is empty.  Chips: BB_A0 BB_B0 K2
43404 #define RDIF_REG_DEBUG_UCM_CREDIT                                                                    0x3000ccUL //Access:R    DataWidth:0x1   DEBUG: 0 - no credit; 1 - there is credit.  Chips: BB_A0 BB_B0 K2
43405 #define RDIF_REG_DEBUG_UCM_MSG_PENDING                                                               0x3000d0UL //Access:R    DataWidth:0x1   DEBUG: 0 - no message pending; 1 - message is pending (no credit) or waiting for done.  Chips: BB_A0 BB_B0 K2
43406 #define RDIF_REG_DEBUG_FATAL_CONFIG_ERR_INFO                                                         0x3000d4UL //Access:R    DataWidth:0x15  DEBUG: configuration fatal error. [1:0] host interface; [2] network interface; [3] FWRD ref; [4] FWR app; [5] FWRD guard; [6] vlidate ref; [7] validate app; [8] validate guard; [10:9] protocol ID; [19:11] LTID; [20] buffer select.  Chips: BB_A0 BB_B0 K2
43407 #define RDIF_REG_DEBUG_PIPELINE_IDLE                                                                 0x3000d8UL //Access:R    DataWidth:0x1   DEBUG: if set there is no valid data in the pipeline.  Chips: BB_A0 BB_B0 K2
43408 #define RDIF_REG_STAT_NUM_ERR_INTERVAL_0                                                             0x3000dcUL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 0.  Chips: BB_A0 BB_B0 K2
43409 #define RDIF_REG_INT_STS                                                                             0x300180UL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43410     #define RDIF_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
43411     #define RDIF_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
43412     #define RDIF_REG_INT_STS_FATAL_DIX_ERR                                                           (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
43413     #define RDIF_REG_INT_STS_FATAL_DIX_ERR_SHIFT                                                     1
43414     #define RDIF_REG_INT_STS_FATAL_CONFIG_ERR                                                        (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
43415     #define RDIF_REG_INT_STS_FATAL_CONFIG_ERR_SHIFT                                                  2
43416     #define RDIF_REG_INT_STS_CMD_FIFO_ERR                                                            (0x1<<3) // Write to full FIFO or read from empty FIFO.
43417     #define RDIF_REG_INT_STS_CMD_FIFO_ERR_SHIFT                                                      3
43418     #define RDIF_REG_INT_STS_ORDER_FIFO_ERR                                                          (0x1<<4) // Write to full FIFO or read from empty FIFO.
43419     #define RDIF_REG_INT_STS_ORDER_FIFO_ERR_SHIFT                                                    4
43420     #define RDIF_REG_INT_STS_RDATA_FIFO_ERR                                                          (0x1<<5) // Write to full FIFO or read from empty FIFO.
43421     #define RDIF_REG_INT_STS_RDATA_FIFO_ERR_SHIFT                                                    5
43422     #define RDIF_REG_INT_STS_DIF_STOP_ERR                                                            (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
43423     #define RDIF_REG_INT_STS_DIF_STOP_ERR_SHIFT                                                      6
43424     #define RDIF_REG_INT_STS_PARTIAL_DIF_W_EOB                                                       (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
43425     #define RDIF_REG_INT_STS_PARTIAL_DIF_W_EOB_SHIFT                                                 7
43426     #define RDIF_REG_INT_STS_L1_DIRTY_BIT                                                            (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
43427     #define RDIF_REG_INT_STS_L1_DIRTY_BIT_SHIFT                                                      8
43428 #define RDIF_REG_INT_MASK                                                                            0x300184UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43429     #define RDIF_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.ADDRESS_ERROR .
43430     #define RDIF_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
43431     #define RDIF_REG_INT_MASK_FATAL_DIX_ERR                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.FATAL_DIX_ERR .
43432     #define RDIF_REG_INT_MASK_FATAL_DIX_ERR_SHIFT                                                    1
43433     #define RDIF_REG_INT_MASK_FATAL_CONFIG_ERR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.FATAL_CONFIG_ERR .
43434     #define RDIF_REG_INT_MASK_FATAL_CONFIG_ERR_SHIFT                                                 2
43435     #define RDIF_REG_INT_MASK_CMD_FIFO_ERR                                                           (0x1<<3) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.CMD_FIFO_ERR .
43436     #define RDIF_REG_INT_MASK_CMD_FIFO_ERR_SHIFT                                                     3
43437     #define RDIF_REG_INT_MASK_ORDER_FIFO_ERR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.ORDER_FIFO_ERR .
43438     #define RDIF_REG_INT_MASK_ORDER_FIFO_ERR_SHIFT                                                   4
43439     #define RDIF_REG_INT_MASK_RDATA_FIFO_ERR                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.RDATA_FIFO_ERR .
43440     #define RDIF_REG_INT_MASK_RDATA_FIFO_ERR_SHIFT                                                   5
43441     #define RDIF_REG_INT_MASK_DIF_STOP_ERR                                                           (0x1<<6) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.DIF_STOP_ERR .
43442     #define RDIF_REG_INT_MASK_DIF_STOP_ERR_SHIFT                                                     6
43443     #define RDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.PARTIAL_DIF_W_EOB .
43444     #define RDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB_SHIFT                                                7
43445     #define RDIF_REG_INT_MASK_L1_DIRTY_BIT                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: RDIF_REG_INT_STS.L1_DIRTY_BIT .
43446     #define RDIF_REG_INT_MASK_L1_DIRTY_BIT_SHIFT                                                     8
43447 #define RDIF_REG_INT_STS_WR                                                                          0x300188UL //Access:WR   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43448     #define RDIF_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
43449     #define RDIF_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
43450     #define RDIF_REG_INT_STS_WR_FATAL_DIX_ERR                                                        (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
43451     #define RDIF_REG_INT_STS_WR_FATAL_DIX_ERR_SHIFT                                                  1
43452     #define RDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR                                                     (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
43453     #define RDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR_SHIFT                                               2
43454     #define RDIF_REG_INT_STS_WR_CMD_FIFO_ERR                                                         (0x1<<3) // Write to full FIFO or read from empty FIFO.
43455     #define RDIF_REG_INT_STS_WR_CMD_FIFO_ERR_SHIFT                                                   3
43456     #define RDIF_REG_INT_STS_WR_ORDER_FIFO_ERR                                                       (0x1<<4) // Write to full FIFO or read from empty FIFO.
43457     #define RDIF_REG_INT_STS_WR_ORDER_FIFO_ERR_SHIFT                                                 4
43458     #define RDIF_REG_INT_STS_WR_RDATA_FIFO_ERR                                                       (0x1<<5) // Write to full FIFO or read from empty FIFO.
43459     #define RDIF_REG_INT_STS_WR_RDATA_FIFO_ERR_SHIFT                                                 5
43460     #define RDIF_REG_INT_STS_WR_DIF_STOP_ERR                                                         (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
43461     #define RDIF_REG_INT_STS_WR_DIF_STOP_ERR_SHIFT                                                   6
43462     #define RDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB                                                    (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
43463     #define RDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB_SHIFT                                              7
43464     #define RDIF_REG_INT_STS_WR_L1_DIRTY_BIT                                                         (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
43465     #define RDIF_REG_INT_STS_WR_L1_DIRTY_BIT_SHIFT                                                   8
43466 #define RDIF_REG_INT_STS_CLR                                                                         0x30018cUL //Access:RC   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43467     #define RDIF_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
43468     #define RDIF_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
43469     #define RDIF_REG_INT_STS_CLR_FATAL_DIX_ERR                                                       (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
43470     #define RDIF_REG_INT_STS_CLR_FATAL_DIX_ERR_SHIFT                                                 1
43471     #define RDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR                                                    (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
43472     #define RDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR_SHIFT                                              2
43473     #define RDIF_REG_INT_STS_CLR_CMD_FIFO_ERR                                                        (0x1<<3) // Write to full FIFO or read from empty FIFO.
43474     #define RDIF_REG_INT_STS_CLR_CMD_FIFO_ERR_SHIFT                                                  3
43475     #define RDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR                                                      (0x1<<4) // Write to full FIFO or read from empty FIFO.
43476     #define RDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR_SHIFT                                                4
43477     #define RDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR                                                      (0x1<<5) // Write to full FIFO or read from empty FIFO.
43478     #define RDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR_SHIFT                                                5
43479     #define RDIF_REG_INT_STS_CLR_DIF_STOP_ERR                                                        (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
43480     #define RDIF_REG_INT_STS_CLR_DIF_STOP_ERR_SHIFT                                                  6
43481     #define RDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB                                                   (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
43482     #define RDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB_SHIFT                                             7
43483     #define RDIF_REG_INT_STS_CLR_L1_DIRTY_BIT                                                        (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
43484     #define RDIF_REG_INT_STS_CLR_L1_DIRTY_BIT_SHIFT                                                  8
43485 #define RDIF_REG_PRTY_MASK                                                                           0x300194UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_B0 K2
43486     #define RDIF_REG_PRTY_MASK_DATAPATH_REGISTERS                                                    (0x1<<1) // This bit masks, when set, the Parity bit: RDIF_REG_PRTY_STS.DATAPATH_REGISTERS .
43487     #define RDIF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                              1
43488 #define RDIF_REG_DEBUG_ERROR_INFO                                                                    0x300400UL //Access:R    DataWidth:0x20  Information on the first 8 DIF errors found. In bits [5:3] of the address represent the error number (0-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the address will contain the following data: address[2:0] = 0 - [31:0] calculated reference tag; address[2:0] = 1 - [15:0] calculated application tag; [31:0]; calculated CRC/checksum; address[2:0] = 2 - [31:0] expected reference tag; address[2:0] = 3 - [15:0] expected application tag; [31:0] expected CRC/checksum; address[2:0] = 4 - [31:0] the interval number the error occurred; address[2:0] = 5 - [31:0] TID address[2:0] = 6 - [3:0] - type; [12:4] - LTID; [15:13] protocol ID; [16] set ID; [18:17] host interface; [19] network interface; [22:20] error type ([0] - CRC/checksum; [1] application tag; [2] reference tag); [31:23] reserved; address[2:0] = 7 - reserved.  Chips: BB_A0 BB_B0 K2
43489 #define RDIF_REG_DEBUG_ERROR_INFO_SIZE                                                               64
43490 #define RDIF_REG_DBG_SELECT                                                                          0x300500UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
43491 #define RDIF_REG_DBG_DWORD_ENABLE                                                                    0x300504UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
43492 #define RDIF_REG_DBG_SHIFT                                                                           0x300508UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
43493 #define RDIF_REG_DBG_FORCE_VALID                                                                     0x30050cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
43494 #define RDIF_REG_DBG_FORCE_FRAME                                                                     0x300510UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
43495 #define RDIF_REG_DBG_OUT_DATA                                                                        0x300520UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
43496 #define RDIF_REG_DBG_OUT_DATA_SIZE                                                                   8
43497 #define RDIF_REG_DBG_OUT_VALID                                                                       0x300540UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
43498 #define RDIF_REG_DBG_OUT_FRAME                                                                       0x300544UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
43499 #define RDIF_REG_L1_TASK_CONTEXT                                                                     0x304000UL //Access:WB   DataWidth:0x40  Task context memory. for TDIF Only 320b are valid. Data order:Field name-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offset-0 bits [47:32]; Field name-Application tag mask Address offset-0 bits [63:48]; Field name-Partial CRC value B Address offset-1 bits [15:0]; Field name-Partial checksum value B Address offset-1 bits [31:16]; Field name-Received DIF bytes left B Address offset-1 bits [35:32]; Field name-Transmitted DIF bytes B Address offset-1 bits [39:36]; Field name-Error in IO B Address offset-1 bits [40:40]; Field name-Checksum overflow B Address offset-1 bits [41]; Field name-Reserved Address offset-1  [55:42]; Field name-Ignore application tag for guard  Address offset-1 bits [56]; Field name-Initial reference tag valid  Address offset-1 bits [57]; Field name-Host Guard type Address offset-1 bits [58]; Field name-Set error with EOP Address offset-1 bits [59]; Field name-Protection type Address offset-1 bits [60]; Field name-CRC seed  Address offset-1 bits [62]; Field name-Reserved  Address offset-1 bits [63]; Field name-Validate guard Address offset-2 bits [0]; Field name-Validate application tag Address offset-2 bits [1]; Field name-Validate  reference tag Address offset-2 bits [2]; Field name-Forward guard  Address offset-2 bits [3]; Field name-Forward application tag  Address offset-2 bits [4]; Field name-Forward reference tag  Address offset-2 bits [5]; Field name-Interval size Address offset-2 bits [8:6]; Field name-Host interface Address offset-2 bits [10:9]; Field name-DIX block size Address offset-2 bits [12:11]; Field name-Network Interface  Address offset-2 bits [13]; Field name-Received DIF bytes left A Address offset-2 bits [17:14]; Field name-Transmitted DIF bytes A Address offset-2 bits [21:18]; Field name-Error in IO A Address offset-2 bits [22:22]; Field name-Checksum overflow A Address offset-2 bits [23]; Field name-Reserved Address offset-2 bits [31:24]; Field name-Offset in IO B Address offset-2 bits [63:32]; Field name-Partial CRC value A Address offset-3 bits [15:0]; Field name-Partial checksum value A Address offset-3 bits [31:16]; Field name-Offset in IO A Address offset-3 bits [63:32]; Field name-Partial DIF data A Address offset-4 bits [63:0]; Field name-Partial DIF data B Address offset-5 bits [63:0].  Address offset-6 and 7 - reserved. all reserved fields are un reachable for write and return zero on read. Address offset is in QWORD resolution.  Chips: BB_A0 BB_B0 K2
43500 #define RDIF_REG_L1_TASK_CONTEXT_SIZE                                                                2560
43501 #define TDIF_REG_RESET_MEMORIES                                                                      0x310000UL //Access:W    DataWidth:0x1   Write one to this register will write zero to all L1 entries. When the command is complete zero will be indicated in this register.  Chips: BB_A0 BB_B0 K2
43502 #define TDIF_REG_STOP_ON_ERROR                                                                       0x310040UL //Access:RW   DataWidth:0x1   If set and DIF block found error; the DIF block will be stuck - hard reset is needed.  Chips: BB_A0 BB_B0 K2
43503 #define TDIF_REG_EOB_AND_PARTIAL_DIF_ERR_MASK                                                        0x310044UL //Access:RW   DataWidth:0x1   mask bit for the following case: host interface = DIF end of burst arrived with end of interval and only partial DIF data arrived. If clear and this event occuer a fatal error will cause the DIF block to stop.  Chips: BB_A0 BB_B0 K2
43504 #define TDIF_REG_BYPASS_MODE_EN                                                                      0x310048UL //Access:RW   DataWidth:0x1   If set allow bypass the pipline on pass through commands and in an empty system.  Chips: BB_A0 BB_B0 K2
43505 #define TDIF_REG_ECO_RESERVED                                                                        0x31004cUL //Access:RW   DataWidth:0x8   ECO reserved.  Chips: BB_A0 BB_B0 K2
43506 #define TDIF_REG_MIN_EOB2WF_L1_RD_DEL                                                                0x310050UL //Access:RW   DataWidth:0x6   If the L1 of an LTID is not updated since EOB within the configured number of cycles the dirty_l1 register will be set. Configuring 0 is the same as 1.  Chips: BB_B0 K2
43507 #define TDIF_REG_DIRTY_L1                                                                            0x310054UL //Access:R    DataWidth:0x1   Indicates that there is a pending L1 WB. Set only if this is the case for at least min_eob2wf_l1_rd_del cycles.  Chips: BB_B0 K2
43508 #define TDIF_REG_DEBUG_BUFER_0_READ_EN                                                               0x310058UL //Access:W    DataWidth:0x1   Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_0_data_0..8.  Chips: BB_A0 BB_B0 K2
43509 #define TDIF_REG_DEBUG_BUFER_0_READ_EN_SIZE                                                          2
43510 #define TDIF_REG_DEBUG_BUFER_1_READ_EN                                                               0x310068UL //Access:W    DataWidth:0x1   Writing to this register (any value) will copy the data in buffer 0 to the debug_buffer_1_data_0..8.  Chips: BB_A0 BB_B0 K2
43511 #define TDIF_REG_DEBUG_BUFER_1_READ_EN_SIZE                                                          2
43512 #define TDIF_REG_DEBUG_COMMAND_FIFO_EMPTY                                                            0x310070UL //Access:R    DataWidth:0x1   Debug: 1 =  fifo is empty.  Chips: BB_A0 BB_B0 K2
43513 #define TDIF_REG_DEBUG_ORDER_FIFO_EMPTY                                                              0x310074UL //Access:R    DataWidth:0x1   Debug: 1 =  fifo is empty.  Chips: BB_A0 BB_B0 K2
43514 #define TDIF_REG_DEBUG_RDATA_FIFO_EMPTY                                                              0x310078UL //Access:R    DataWidth:0x1   Debug: 1 =  fifo is empty.  Chips: BB_A0 BB_B0 K2
43515 #define TDIF_REG_DEBUG_ERROR_DATA_VALID                                                              0x31007cUL //Access:RW   DataWidth:0x8   If bit i is set; the data in the debug_error_info address[5:3] = i is valid. By writing 1 to bit j it will clear the valid bits of bit j.  Chips: BB_A0 BB_B0 K2
43516 #define TDIF_REG_DEBUG_BUFFER_0_DATA_0                                                               0x310080UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. TID.  Chips: BB_A0 BB_B0 K2
43517 #define TDIF_REG_DEBUG_BUFFER_0_DATA_1                                                               0x310084UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Initial referance tag.  Chips: BB_A0 BB_B0 K2
43518 #define TDIF_REG_DEBUG_BUFFER_0_DATA_2                                                               0x310088UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [15:0] - application tag; [31:16] - application mask.  Chips: BB_A0 BB_B0 K2
43519 #define TDIF_REG_DEBUG_BUFFER_0_DATA_3                                                               0x31008cUL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calculated checksum.  Chips: BB_A0 BB_B0 K2
43520 #define TDIF_REG_DEBUG_BUFFER_0_DATA_4                                                               0x310090UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Calculated offset in IO.  Chips: BB_A0 BB_B0 K2
43521 #define TDIF_REG_DEBUG_BUFFER_0_DATA_5                                                               0x310094UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Partial DIF/DIX data - referance tag.  Chips: BB_A0 BB_B0 K2
43522 #define TDIF_REG_DEBUG_BUFFER_0_DATA_6                                                               0x310098UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application tag; [31:0] CRC/checksum.  Chips: BB_A0 BB_B0 K2
43523 #define TDIF_REG_DEBUG_BUFFER_0_DATA_7                                                               0x31009cUL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [31] partial_chksum_overflow ; [30:27] dif_bytes_tx ; [26:23] dif_bytes_rx ; [22:19] last_dif_size; [18] eob_flag ; [17] data_is_dix ; [16] set_id ; [15:13] protocol_id; [12:9] type;  [8:0] ltid.  Chips: BB_A0 BB_B0 K2
43524 #define TDIF_REG_DEBUG_BUFFER_0_DATA_8                                                               0x3100a0UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [20:19]  dix_size; [18] ni ; [17:16] hi ; [15:13] interval_size ; [12] fwrd_ref ; [11] fwrd_app ; [10]  fwrd_guard ; [9] validate_ref ; [8] validate_app ; [7] validate_guard ; [6] crc_seed ; [5:4] protection_type ; [3]  set_err_with_eop ; [2] host_guard_is_crc ; [1]  initial_ref_tag_valid; [0] err_in_io.  Chips: BB_A0 BB_B0 K2
43525 #define TDIF_REG_DEBUG_BUFFER_1_DATA_0                                                               0x3100a4UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. TID.  Chips: BB_A0 BB_B0 K2
43526 #define TDIF_REG_DEBUG_BUFFER_1_DATA_1                                                               0x3100a8UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Initial referance tag.  Chips: BB_A0 BB_B0 K2
43527 #define TDIF_REG_DEBUG_BUFFER_1_DATA_2                                                               0x3100acUL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [15:0] - application tag; [31:16] - application mask.  Chips: BB_A0 BB_B0 K2
43528 #define TDIF_REG_DEBUG_BUFFER_1_DATA_3                                                               0x3100b0UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [15:0] - calculated CRC; [31:16] - calculated checksum.  Chips: BB_A0 BB_B0 K2
43529 #define TDIF_REG_DEBUG_BUFFER_1_DATA_4                                                               0x3100b4UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Calculated offset in IO.  Chips: BB_A0 BB_B0 K2
43530 #define TDIF_REG_DEBUG_BUFFER_1_DATA_5                                                               0x3100b8UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Partial DIF/DIX data - referance tag.  Chips: BB_A0 BB_B0 K2
43531 #define TDIF_REG_DEBUG_BUFFER_1_DATA_6                                                               0x3100bcUL //Access:R    DataWidth:0x20  DEBUG: Buffer information. Partial DIF/DIX data - [15:0] application tag; [31:0] CRC/checksum.  Chips: BB_A0 BB_B0 K2
43532 #define TDIF_REG_DEBUG_BUFFER_1_DATA_7                                                               0x3100c0UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [31] partial_chksum_overflow ; [30:27] dif_bytes_tx ; [26:23] dif_bytes_rx ; [22:19] last_dif_size; [18] eob_flag ; [17] data_is_dix ; [16] set_id ; [15:13] protocol_id; [12:9] type;  [8:0] ltid.  Chips: BB_A0 BB_B0 K2
43533 #define TDIF_REG_DEBUG_BUFFER_1_DATA_8                                                               0x3100c4UL //Access:R    DataWidth:0x20  DEBUG: Buffer information. [20:19]  dix_size; [18] ni ; [17:16] hi ; [15:13] interval_size ; [12] fwrd_ref ; [11] fwrd_app ; [10]  fwrd_guard ; [9] validate_ref ; [8] validate_app ; [7] validate_guard ; [6] crc_seed ; [5:4] protection_type ; [3]  set_err_with_eop ; [2] host_guard_is_crc ; [1]  initial_ref_tag_valid; [0] err_in_io.  Chips: BB_A0 BB_B0 K2
43534 #define TDIF_REG_DEBUG_DIX_FIFO_EMPTY                                                                0x3100c8UL //Access:R    DataWidth:0x4   Debug: one bit for each protocol ID.  1 =  fifo is empty.  Chips: BB_A0 BB_B0 K2
43535 #define TDIF_REG_DEBUG_UCM_CREDIT                                                                    0x3100ccUL //Access:R    DataWidth:0x1   DEBUG: 0 - no credit; 1 - there is credit.  Chips: BB_A0 BB_B0 K2
43536 #define TDIF_REG_DEBUG_UCM_MSG_PENDING                                                               0x3100d0UL //Access:R    DataWidth:0x1   DEBUG: 0 - no message pending; 1 - message is pending (no credit) or waiting for done.  Chips: BB_A0 BB_B0 K2
43537 #define TDIF_REG_DEBUG_FATAL_CONFIG_ERR_INFO                                                         0x3100d4UL //Access:R    DataWidth:0x16  DEBUG: configuration fatal error. [1:0] host interface; [2] network interface; [3] FWRD ref; [4] FWR app; [5] FWRD guard; [6] vlidate ref; [7] validate app; [8] validate guard; [11:9] protocol ID; [20:12] LTID; [21] buffer select.  Chips: BB_A0 BB_B0 K2
43538 #define TDIF_REG_DEBUG_DIX_FATAL_ERR_INFO                                                            0x3100d8UL //Access:R    DataWidth:0x1a  [3:0] - error type ([0] Write overflow. [1] Read overflow. [2] Read from DIX when DIX write pointer =< DIX read pointer. [3] EOB arrived and DIX write pointer != DIX read pointer.); [5:4] protocol ID; [6] reserved;  [7] buffer inuse; [16:8] write pointer; [25:17] read pointer.  Chips: BB_A0 BB_B0 K2
43539 #define TDIF_REG_DEBUG_PIPELINE_IDLE                                                                 0x3100dcUL //Access:R    DataWidth:0x1   DEBUG: if set there is no valid data in the pipeline.  Chips: BB_A0 BB_B0 K2
43540 #define TDIF_REG_STAT_NUM_ERR_INTERVAL_0                                                             0x3100e0UL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 0.  Chips: BB_A0 BB_B0 K2
43541 #define TDIF_REG_STAT_NUM_ERR_INTERVAL_1                                                             0x3100e4UL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 1.  Chips: BB_A0 BB_B0 K2
43542 #define TDIF_REG_STAT_NUM_ERR_INTERVAL_2                                                             0x3100e8UL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 2.  Chips: BB_A0 BB_B0 K2
43543 #define TDIF_REG_STAT_NUM_ERR_INTERVAL_3                                                             0x3100ecUL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 3.  Chips: BB_A0 BB_B0 K2
43544 #define TDIF_REG_STAT_NUM_ERR_INTERVAL_4                                                             0x3100f0UL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 4.  Chips: K2
43545 #define TDIF_REG_STAT_NUM_ERR_INTERVAL_5                                                             0x3100f4UL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 5.  Chips: K2
43546 #define TDIF_REG_STAT_NUM_ERR_INTERVAL_6                                                             0x3100f8UL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 6.  Chips: K2
43547 #define TDIF_REG_STAT_NUM_ERR_INTERVAL_7                                                             0x3100fcUL //Access:RW   DataWidth:0x20  Number of interval with error arrived to the DIF for protocol ID 7.  Chips: K2
43548 #define TDIF_REG_INT_STS                                                                             0x310180UL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43549     #define TDIF_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
43550     #define TDIF_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
43551     #define TDIF_REG_INT_STS_FATAL_DIX_ERR                                                           (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
43552     #define TDIF_REG_INT_STS_FATAL_DIX_ERR_SHIFT                                                     1
43553     #define TDIF_REG_INT_STS_FATAL_CONFIG_ERR                                                        (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
43554     #define TDIF_REG_INT_STS_FATAL_CONFIG_ERR_SHIFT                                                  2
43555     #define TDIF_REG_INT_STS_CMD_FIFO_ERR                                                            (0x1<<3) // Write to full FIFO or read from empty FIFO.
43556     #define TDIF_REG_INT_STS_CMD_FIFO_ERR_SHIFT                                                      3
43557     #define TDIF_REG_INT_STS_ORDER_FIFO_ERR                                                          (0x1<<4) // Write to full FIFO or read from empty FIFO.
43558     #define TDIF_REG_INT_STS_ORDER_FIFO_ERR_SHIFT                                                    4
43559     #define TDIF_REG_INT_STS_RDATA_FIFO_ERR                                                          (0x1<<5) // Write to full FIFO or read from empty FIFO.
43560     #define TDIF_REG_INT_STS_RDATA_FIFO_ERR_SHIFT                                                    5
43561     #define TDIF_REG_INT_STS_DIF_STOP_ERR                                                            (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
43562     #define TDIF_REG_INT_STS_DIF_STOP_ERR_SHIFT                                                      6
43563     #define TDIF_REG_INT_STS_PARTIAL_DIF_W_EOB                                                       (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
43564     #define TDIF_REG_INT_STS_PARTIAL_DIF_W_EOB_SHIFT                                                 7
43565     #define TDIF_REG_INT_STS_L1_DIRTY_BIT                                                            (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
43566     #define TDIF_REG_INT_STS_L1_DIRTY_BIT_SHIFT                                                      8
43567 #define TDIF_REG_INT_MASK                                                                            0x310184UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43568     #define TDIF_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.ADDRESS_ERROR .
43569     #define TDIF_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
43570     #define TDIF_REG_INT_MASK_FATAL_DIX_ERR                                                          (0x1<<1) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.FATAL_DIX_ERR .
43571     #define TDIF_REG_INT_MASK_FATAL_DIX_ERR_SHIFT                                                    1
43572     #define TDIF_REG_INT_MASK_FATAL_CONFIG_ERR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.FATAL_CONFIG_ERR .
43573     #define TDIF_REG_INT_MASK_FATAL_CONFIG_ERR_SHIFT                                                 2
43574     #define TDIF_REG_INT_MASK_CMD_FIFO_ERR                                                           (0x1<<3) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.CMD_FIFO_ERR .
43575     #define TDIF_REG_INT_MASK_CMD_FIFO_ERR_SHIFT                                                     3
43576     #define TDIF_REG_INT_MASK_ORDER_FIFO_ERR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.ORDER_FIFO_ERR .
43577     #define TDIF_REG_INT_MASK_ORDER_FIFO_ERR_SHIFT                                                   4
43578     #define TDIF_REG_INT_MASK_RDATA_FIFO_ERR                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.RDATA_FIFO_ERR .
43579     #define TDIF_REG_INT_MASK_RDATA_FIFO_ERR_SHIFT                                                   5
43580     #define TDIF_REG_INT_MASK_DIF_STOP_ERR                                                           (0x1<<6) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.DIF_STOP_ERR .
43581     #define TDIF_REG_INT_MASK_DIF_STOP_ERR_SHIFT                                                     6
43582     #define TDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.PARTIAL_DIF_W_EOB .
43583     #define TDIF_REG_INT_MASK_PARTIAL_DIF_W_EOB_SHIFT                                                7
43584     #define TDIF_REG_INT_MASK_L1_DIRTY_BIT                                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: TDIF_REG_INT_STS.L1_DIRTY_BIT .
43585     #define TDIF_REG_INT_MASK_L1_DIRTY_BIT_SHIFT                                                     8
43586 #define TDIF_REG_INT_STS_WR                                                                          0x310188UL //Access:WR   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43587     #define TDIF_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
43588     #define TDIF_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
43589     #define TDIF_REG_INT_STS_WR_FATAL_DIX_ERR                                                        (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
43590     #define TDIF_REG_INT_STS_WR_FATAL_DIX_ERR_SHIFT                                                  1
43591     #define TDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR                                                     (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
43592     #define TDIF_REG_INT_STS_WR_FATAL_CONFIG_ERR_SHIFT                                               2
43593     #define TDIF_REG_INT_STS_WR_CMD_FIFO_ERR                                                         (0x1<<3) // Write to full FIFO or read from empty FIFO.
43594     #define TDIF_REG_INT_STS_WR_CMD_FIFO_ERR_SHIFT                                                   3
43595     #define TDIF_REG_INT_STS_WR_ORDER_FIFO_ERR                                                       (0x1<<4) // Write to full FIFO or read from empty FIFO.
43596     #define TDIF_REG_INT_STS_WR_ORDER_FIFO_ERR_SHIFT                                                 4
43597     #define TDIF_REG_INT_STS_WR_RDATA_FIFO_ERR                                                       (0x1<<5) // Write to full FIFO or read from empty FIFO.
43598     #define TDIF_REG_INT_STS_WR_RDATA_FIFO_ERR_SHIFT                                                 5
43599     #define TDIF_REG_INT_STS_WR_DIF_STOP_ERR                                                         (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
43600     #define TDIF_REG_INT_STS_WR_DIF_STOP_ERR_SHIFT                                                   6
43601     #define TDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB                                                    (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
43602     #define TDIF_REG_INT_STS_WR_PARTIAL_DIF_W_EOB_SHIFT                                              7
43603     #define TDIF_REG_INT_STS_WR_L1_DIRTY_BIT                                                         (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
43604     #define TDIF_REG_INT_STS_WR_L1_DIRTY_BIT_SHIFT                                                   8
43605 #define TDIF_REG_INT_STS_CLR                                                                         0x31018cUL //Access:RC   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43606     #define TDIF_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
43607     #define TDIF_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
43608     #define TDIF_REG_INT_STS_CLR_FATAL_DIX_ERR                                                       (0x1<<1) // DIX data is missing or end of burst assived and not all DIX data was used.
43609     #define TDIF_REG_INT_STS_CLR_FATAL_DIX_ERR_SHIFT                                                 1
43610     #define TDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR                                                    (0x1<<2) // Fatal configuration error due to illigal comdination of host interface, network interface, validate xxx and forward xxx.
43611     #define TDIF_REG_INT_STS_CLR_FATAL_CONFIG_ERR_SHIFT                                              2
43612     #define TDIF_REG_INT_STS_CLR_CMD_FIFO_ERR                                                        (0x1<<3) // Write to full FIFO or read from empty FIFO.
43613     #define TDIF_REG_INT_STS_CLR_CMD_FIFO_ERR_SHIFT                                                  3
43614     #define TDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR                                                      (0x1<<4) // Write to full FIFO or read from empty FIFO.
43615     #define TDIF_REG_INT_STS_CLR_ORDER_FIFO_ERR_SHIFT                                                4
43616     #define TDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR                                                      (0x1<<5) // Write to full FIFO or read from empty FIFO.
43617     #define TDIF_REG_INT_STS_CLR_RDATA_FIFO_ERR_SHIFT                                                5
43618     #define TDIF_REG_INT_STS_CLR_DIF_STOP_ERR                                                        (0x1<<6) // If stop_on_error is set and the DIF block found error in the DIF/DIX data this interrupt will be asserted. The debug info is in debug_error_info.
43619     #define TDIF_REG_INT_STS_CLR_DIF_STOP_ERR_SHIFT                                                  6
43620     #define TDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB                                                   (0x1<<7) // end of burst arrived with end of interval and only partial DIF data arrived.
43621     #define TDIF_REG_INT_STS_CLR_PARTIAL_DIF_W_EOB_SHIFT                                             7
43622     #define TDIF_REG_INT_STS_CLR_L1_DIRTY_BIT                                                        (0x1<<8) // One of the command buffers has a pending L1 WB for more than MIN_EOB2WF_L1_RD_DEL (register) cycles.
43623     #define TDIF_REG_INT_STS_CLR_L1_DIRTY_BIT_SHIFT                                                  8
43624 #define TDIF_REG_PRTY_MASK                                                                           0x310194UL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: BB_B0 K2
43625     #define TDIF_REG_PRTY_MASK_DATAPATH_REGISTERS                                                    (0x1<<1) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS.DATAPATH_REGISTERS .
43626     #define TDIF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                              1
43627 #define TDIF_REG_PRTY_MASK_H_0                                                                       0x310204UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
43628     #define TDIF_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
43629     #define TDIF_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT                                         0
43630     #define TDIF_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
43631     #define TDIF_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_SHIFT                                         1
43632     #define TDIF_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT                                               (0x1<<2) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
43633     #define TDIF_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT                                         2
43634     #define TDIF_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT                                               (0x1<<3) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
43635     #define TDIF_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_SHIFT                                         3
43636     #define TDIF_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
43637     #define TDIF_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           4
43638     #define TDIF_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
43639     #define TDIF_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           5
43640     #define TDIF_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
43641     #define TDIF_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           6
43642     #define TDIF_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
43643     #define TDIF_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           7
43644     #define TDIF_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
43645     #define TDIF_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           8
43646     #define TDIF_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<9) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
43647     #define TDIF_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           9
43648     #define TDIF_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<10) // This bit masks, when set, the Parity bit: TDIF_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
43649     #define TDIF_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           10
43650 #define TDIF_REG_MEM_ECC_EVENTS                                                                      0x31021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
43651 #define TDIF_REG_MEM001_I_MEM_DFT_K2                                                                 0x310224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_cmd_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
43652 #define TDIF_REG_MEM003_I_MEM_DFT_K2                                                                 0x310228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_dix_data_fifo.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43653 #define TDIF_REG_MEM002_I_MEM_DFT_K2                                                                 0x31022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_data_in_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
43654 #define TDIF_REG_MEM005_I_MEM_DFT_K2                                                                 0x310230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_l1_sector0_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43655 #define TDIF_REG_MEM006_I_MEM_DFT_K2                                                                 0x310234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_l1_sector1_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43656 #define TDIF_REG_MEM007_I_MEM_DFT_K2                                                                 0x310238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_l1_sector2_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43657 #define TDIF_REG_MEM008_I_MEM_DFT_K2                                                                 0x31023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_l1_sector3_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43658 #define TDIF_REG_MEM009_I_MEM_DFT_K2                                                                 0x310240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_l1_sector4_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43659 #define TDIF_REG_MEM010_I_MEM_DFT_K2                                                                 0x310244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_l1_sector5_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43660 #define TDIF_REG_MEM011_I_MEM_DFT_K2                                                                 0x310248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_l1_sector6_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43661 #define TDIF_REG_MEM004_I_MEM_DFT_K2                                                                 0x31024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tdif.i_tdif_err_debug_mem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
43662 #define TDIF_REG_DEBUG_ERROR_INFO                                                                    0x310400UL //Access:R    DataWidth:0x20  Information on the first 8 DIF errors found. In bits [5:3] of the address represent the error number (0-7). Do not read from address[3:5]=i if debug_error_data_valid[i] isn't set. Bits [2:0] in the address will contain the following data: address[2:0] = 0 - [31:0] calculated reference tag; address[2:0] = 1 - [15:0] calculated application tag; [31:0]; calculated CRC/checksum; address[2:0] = 2 - [31:0] expected reference tag; address[2:0] = 3 - [15:0] expected application tag; [31:0] expected CRC/checksum; address[2:0] = 4 - [31:0] the interval number the error occurred; address[2:0] = 5 - [31:0] TID address[2:0] = 6 - [3:0] - type; [12:4] - LTID; [15:13] protocol ID; [16] set ID; [18:17] host interface; [19] network interface; [22:20] error type ([0] - CRC/checksum; [1] application tag; [2] reference tag); [31:23] reserved; address[2:0] = 7 - reserved.  Chips: BB_A0 BB_B0 K2
43663 #define TDIF_REG_DEBUG_ERROR_INFO_SIZE                                                               64
43664 #define TDIF_REG_DBG_SELECT                                                                          0x310500UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
43665 #define TDIF_REG_DBG_DWORD_ENABLE                                                                    0x310504UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
43666 #define TDIF_REG_DBG_SHIFT                                                                           0x310508UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
43667 #define TDIF_REG_DBG_FORCE_VALID                                                                     0x31050cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
43668 #define TDIF_REG_DBG_FORCE_FRAME                                                                     0x310510UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
43669 #define TDIF_REG_DBG_OUT_DATA                                                                        0x310520UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
43670 #define TDIF_REG_DBG_OUT_DATA_SIZE                                                                   8
43671 #define TDIF_REG_DBG_OUT_VALID                                                                       0x310540UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
43672 #define TDIF_REG_DBG_OUT_FRAME                                                                       0x310544UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
43673 #define TDIF_REG_L1_TASK_CONTEXT                                                                     0x318000UL //Access:WB   DataWidth:0x40  Task context memory. for TDIF Only 320b are valid. Data order:Field name-Initial reference tag Address offset-0 bits [31:0]; Field name-Application tag value Address offset-0 bits [47:32]; Field name-Application tag mask Address offset-0 bits [63:48]; Field name-Partial CRC value B Address offset-1 bits [15:0]; Field name-Partial checksum value B Address offset-1 bits [31:16]; Field name-Received DIF bytes left B Address offset-1 bits [35:32]; Field name-Transmitted DIF bytes B Address offset-1 bits [39:36]; Field name-Error in IO B Address offset-1 bits [40:40]; Field name-Checksum overflow B Address offset-1 bits [41]; Field name-Reserved Address offset-1  [55:42]; Field name-Ignore application tag for guard  Address offset-1 bits [56]; Field name-Initial reference tag valid  Address offset-1 bits [57]; Field name-Host Guard type Address offset-1 bits [58]; Field name-Set error with EOP Address offset-1 bits [59]; Field name-Protection type Address offset-1 bits [60]; Field name-CRC seed  Address offset-1 bits [62]; Field name-Reserved  Address offset-1 bits [63]; Field name-Validate guard Address offset-2 bits [0]; Field name-Validate application tag Address offset-2 bits [1]; Field name-Validate  reference tag Address offset-2 bits [2]; Field name-Forward guard  Address offset-2 bits [3]; Field name-Forward application tag  Address offset-2 bits [4]; Field name-Forward reference tag  Address offset-2 bits [5]; Field name-Interval size Address offset-2 bits [8:6]; Field name-Host interface Address offset-2 bits [10:9]; Field name-DIX block size Address offset-2 bits [12:11]; Field name-Network Interface  Address offset-2 bits [13]; Field name-Received DIF bytes left A Address offset-2 bits [17:14]; Field name-Transmitted DIF bytes A Address offset-2 bits [21:18]; Field name-Error in IO A Address offset-2 bits [22:22]; Field name-Checksum overflow A Address offset-2 bits [23]; Field name-Reserved Address offset-2 bits [31:24]; Field name-Offset in IO B Address offset-2 bits [63:32]; Field name-Partial CRC value A Address offset-3 bits [15:0]; Field name-Partial checksum value A Address offset-3 bits [31:16]; Field name-Offset in IO A Address offset-3 bits [63:32]; Field name-Partial DIF data A Address offset-4 bits [63:0]; Field name-Partial DIF data B Address offset-5 bits [63:0].  Address offset-6 and 7 - reserved. all reserved fields are un reachable for write and return zero on read. Address offset is in QWORD resolution.  Chips: BB_A0 BB_B0 K2
43674 #define TDIF_REG_L1_TASK_CONTEXT_SIZE                                                                5120
43675 #define BRB_REG_HW_INIT_EN                                                                           0x340004UL //Access:RW   DataWidth:0x2   Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers will be done by HW.  Bit 1 - if this bit is set then initialization of BIG RAM will be done by HW. Both bits will be reset by HW when initialization is finished.  Chips: BB_A0 BB_B0 K2
43676 #define BRB_REG_INIT_DONE                                                                            0x340008UL //Access:R    DataWidth:0x2   Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers are finished by HW.  Bit 1 - if this bit is set then initialization of BIG RAM is finished by HW.  Chips: BB_A0 BB_B0 K2
43677 #define BRB_REG_START_EN                                                                             0x34000cUL //Access:RW   DataWidth:0x1   This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.  Chips: BB_A0 BB_B0 K2
43678 #define BRB_REG_INT_STS_0                                                                            0x3400c0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
43679     #define BRB_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
43680     #define BRB_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
43681     #define BRB_REG_INT_STS_0_RC_PKT0_RLS_ERROR                                                      (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
43682     #define BRB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT                                                1
43683     #define BRB_REG_INT_STS_0_RC_PKT0_1ST_ERROR                                                      (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
43684     #define BRB_REG_INT_STS_0_RC_PKT0_1ST_ERROR_SHIFT                                                2
43685     #define BRB_REG_INT_STS_0_RC_PKT0_LEN_ERROR                                                      (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
43686     #define BRB_REG_INT_STS_0_RC_PKT0_LEN_ERROR_SHIFT                                                3
43687     #define BRB_REG_INT_STS_0_RC_PKT0_MIDDLE_ERROR                                                   (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
43688     #define BRB_REG_INT_STS_0_RC_PKT0_MIDDLE_ERROR_SHIFT                                             4
43689     #define BRB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR                                                 (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
43690     #define BRB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                           5
43691     #define BRB_REG_INT_STS_0_RC_PKT1_RLS_ERROR                                                      (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
43692     #define BRB_REG_INT_STS_0_RC_PKT1_RLS_ERROR_SHIFT                                                6
43693     #define BRB_REG_INT_STS_0_RC_PKT1_1ST_ERROR                                                      (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
43694     #define BRB_REG_INT_STS_0_RC_PKT1_1ST_ERROR_SHIFT                                                7
43695     #define BRB_REG_INT_STS_0_RC_PKT1_LEN_ERROR                                                      (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
43696     #define BRB_REG_INT_STS_0_RC_PKT1_LEN_ERROR_SHIFT                                                8
43697     #define BRB_REG_INT_STS_0_RC_PKT1_MIDDLE_ERROR                                                   (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
43698     #define BRB_REG_INT_STS_0_RC_PKT1_MIDDLE_ERROR_SHIFT                                             9
43699     #define BRB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR                                                 (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
43700     #define BRB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                           10
43701     #define BRB_REG_INT_STS_0_RC_PKT2_RLS_ERROR                                                      (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
43702     #define BRB_REG_INT_STS_0_RC_PKT2_RLS_ERROR_SHIFT                                                11
43703     #define BRB_REG_INT_STS_0_RC_PKT2_1ST_ERROR                                                      (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
43704     #define BRB_REG_INT_STS_0_RC_PKT2_1ST_ERROR_SHIFT                                                12
43705     #define BRB_REG_INT_STS_0_RC_PKT2_LEN_ERROR                                                      (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
43706     #define BRB_REG_INT_STS_0_RC_PKT2_LEN_ERROR_SHIFT                                                13
43707     #define BRB_REG_INT_STS_0_RC_PKT2_MIDDLE_ERROR                                                   (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
43708     #define BRB_REG_INT_STS_0_RC_PKT2_MIDDLE_ERROR_SHIFT                                             14
43709     #define BRB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR                                                 (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
43710     #define BRB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                           15
43711     #define BRB_REG_INT_STS_0_RC_PKT3_RLS_ERROR                                                      (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
43712     #define BRB_REG_INT_STS_0_RC_PKT3_RLS_ERROR_SHIFT                                                16
43713     #define BRB_REG_INT_STS_0_RC_PKT3_1ST_ERROR                                                      (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
43714     #define BRB_REG_INT_STS_0_RC_PKT3_1ST_ERROR_SHIFT                                                17
43715     #define BRB_REG_INT_STS_0_RC_PKT3_LEN_ERROR                                                      (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
43716     #define BRB_REG_INT_STS_0_RC_PKT3_LEN_ERROR_SHIFT                                                18
43717     #define BRB_REG_INT_STS_0_RC_PKT3_MIDDLE_ERROR                                                   (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
43718     #define BRB_REG_INT_STS_0_RC_PKT3_MIDDLE_ERROR_SHIFT                                             19
43719     #define BRB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR                                                 (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
43720     #define BRB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                           20
43721     #define BRB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR                                               (0x1<<21) // SOP descriptor request from empty TC or port.
43722     #define BRB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                         21
43723     #define BRB_REG_INT_STS_0_UNCOMPLIENT_LOSSLESS_ERROR                                             (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
43724     #define BRB_REG_INT_STS_0_UNCOMPLIENT_LOSSLESS_ERROR_SHIFT                                       22
43725     #define BRB_REG_INT_STS_0_WC0_PROTOCOL_ERROR                                                     (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
43726     #define BRB_REG_INT_STS_0_WC0_PROTOCOL_ERROR_SHIFT                                               23
43727     #define BRB_REG_INT_STS_0_WC1_PROTOCOL_ERROR                                                     (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
43728     #define BRB_REG_INT_STS_0_WC1_PROTOCOL_ERROR_SHIFT                                               24
43729     #define BRB_REG_INT_STS_0_WC2_PROTOCOL_ERROR                                                     (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
43730     #define BRB_REG_INT_STS_0_WC2_PROTOCOL_ERROR_SHIFT                                               25
43731     #define BRB_REG_INT_STS_0_WC3_PROTOCOL_ERROR                                                     (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
43732     #define BRB_REG_INT_STS_0_WC3_PROTOCOL_ERROR_SHIFT                                               26
43733     #define BRB_REG_INT_STS_0_LL_ARB_PREFETCH_SOP_ERROR                                              (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
43734     #define BRB_REG_INT_STS_0_LL_ARB_PREFETCH_SOP_ERROR_SHIFT                                        27
43735     #define BRB_REG_INT_STS_0_LL_BLK_ERROR                                                           (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
43736     #define BRB_REG_INT_STS_0_LL_BLK_ERROR_SHIFT                                                     28
43737     #define BRB_REG_INT_STS_0_PACKET_COUNTER_ERROR                                                   (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
43738     #define BRB_REG_INT_STS_0_PACKET_COUNTER_ERROR_SHIFT                                             29
43739     #define BRB_REG_INT_STS_0_BYTE_COUNTER_ERROR                                                     (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
43740     #define BRB_REG_INT_STS_0_BYTE_COUNTER_ERROR_SHIFT                                               30
43741     #define BRB_REG_INT_STS_0_MAC0_FC_CNT_ERROR                                                      (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
43742     #define BRB_REG_INT_STS_0_MAC0_FC_CNT_ERROR_SHIFT                                                31
43743 #define BRB_REG_INT_MASK_0                                                                           0x3400c4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
43744     #define BRB_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.ADDRESS_ERROR .
43745     #define BRB_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
43746     #define BRB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
43747     #define BRB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT                                               1
43748     #define BRB_REG_INT_MASK_0_RC_PKT0_1ST_ERROR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_1ST_ERROR .
43749     #define BRB_REG_INT_MASK_0_RC_PKT0_1ST_ERROR_SHIFT                                               2
43750     #define BRB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_LEN_ERROR .
43751     #define BRB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR_SHIFT                                               3
43752     #define BRB_REG_INT_MASK_0_RC_PKT0_MIDDLE_ERROR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_MIDDLE_ERROR .
43753     #define BRB_REG_INT_MASK_0_RC_PKT0_MIDDLE_ERROR_SHIFT                                            4
43754     #define BRB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
43755     #define BRB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                          5
43756     #define BRB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
43757     #define BRB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR_SHIFT                                               6
43758     #define BRB_REG_INT_MASK_0_RC_PKT1_1ST_ERROR                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_1ST_ERROR .
43759     #define BRB_REG_INT_MASK_0_RC_PKT1_1ST_ERROR_SHIFT                                               7
43760     #define BRB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_LEN_ERROR .
43761     #define BRB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR_SHIFT                                               8
43762     #define BRB_REG_INT_MASK_0_RC_PKT1_MIDDLE_ERROR                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_MIDDLE_ERROR .
43763     #define BRB_REG_INT_MASK_0_RC_PKT1_MIDDLE_ERROR_SHIFT                                            9
43764     #define BRB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
43765     #define BRB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                          10
43766     #define BRB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
43767     #define BRB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR_SHIFT                                               11
43768     #define BRB_REG_INT_MASK_0_RC_PKT2_1ST_ERROR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_1ST_ERROR .
43769     #define BRB_REG_INT_MASK_0_RC_PKT2_1ST_ERROR_SHIFT                                               12
43770     #define BRB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_LEN_ERROR .
43771     #define BRB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR_SHIFT                                               13
43772     #define BRB_REG_INT_MASK_0_RC_PKT2_MIDDLE_ERROR                                                  (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_MIDDLE_ERROR .
43773     #define BRB_REG_INT_MASK_0_RC_PKT2_MIDDLE_ERROR_SHIFT                                            14
43774     #define BRB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
43775     #define BRB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                          15
43776     #define BRB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR                                                     (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
43777     #define BRB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR_SHIFT                                               16
43778     #define BRB_REG_INT_MASK_0_RC_PKT3_1ST_ERROR                                                     (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_1ST_ERROR .
43779     #define BRB_REG_INT_MASK_0_RC_PKT3_1ST_ERROR_SHIFT                                               17
43780     #define BRB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR                                                     (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_LEN_ERROR .
43781     #define BRB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR_SHIFT                                               18
43782     #define BRB_REG_INT_MASK_0_RC_PKT3_MIDDLE_ERROR                                                  (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_MIDDLE_ERROR .
43783     #define BRB_REG_INT_MASK_0_RC_PKT3_MIDDLE_ERROR_SHIFT                                            19
43784     #define BRB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR                                                (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
43785     #define BRB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                          20
43786     #define BRB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
43787     #define BRB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                        21
43788     #define BRB_REG_INT_MASK_0_UNCOMPLIENT_LOSSLESS_ERROR                                            (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.UNCOMPLIENT_LOSSLESS_ERROR .
43789     #define BRB_REG_INT_MASK_0_UNCOMPLIENT_LOSSLESS_ERROR_SHIFT                                      22
43790     #define BRB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
43791     #define BRB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR_SHIFT                                              23
43792     #define BRB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC1_PROTOCOL_ERROR .
43793     #define BRB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR_SHIFT                                              24
43794     #define BRB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR                                                    (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC2_PROTOCOL_ERROR .
43795     #define BRB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR_SHIFT                                              25
43796     #define BRB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.WC3_PROTOCOL_ERROR .
43797     #define BRB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR_SHIFT                                              26
43798     #define BRB_REG_INT_MASK_0_LL_ARB_PREFETCH_SOP_ERROR                                             (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.LL_ARB_PREFETCH_SOP_ERROR .
43799     #define BRB_REG_INT_MASK_0_LL_ARB_PREFETCH_SOP_ERROR_SHIFT                                       27
43800     #define BRB_REG_INT_MASK_0_LL_BLK_ERROR                                                          (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.LL_BLK_ERROR .
43801     #define BRB_REG_INT_MASK_0_LL_BLK_ERROR_SHIFT                                                    28
43802     #define BRB_REG_INT_MASK_0_PACKET_COUNTER_ERROR                                                  (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.PACKET_COUNTER_ERROR .
43803     #define BRB_REG_INT_MASK_0_PACKET_COUNTER_ERROR_SHIFT                                            29
43804     #define BRB_REG_INT_MASK_0_BYTE_COUNTER_ERROR                                                    (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.BYTE_COUNTER_ERROR .
43805     #define BRB_REG_INT_MASK_0_BYTE_COUNTER_ERROR_SHIFT                                              30
43806     #define BRB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR                                                     (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_0.MAC0_FC_CNT_ERROR .
43807     #define BRB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR_SHIFT                                               31
43808 #define BRB_REG_INT_STS_WR_0                                                                         0x3400c8UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
43809     #define BRB_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
43810     #define BRB_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
43811     #define BRB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR                                                   (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
43812     #define BRB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT                                             1
43813     #define BRB_REG_INT_STS_WR_0_RC_PKT0_1ST_ERROR                                                   (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
43814     #define BRB_REG_INT_STS_WR_0_RC_PKT0_1ST_ERROR_SHIFT                                             2
43815     #define BRB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR                                                   (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
43816     #define BRB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR_SHIFT                                             3
43817     #define BRB_REG_INT_STS_WR_0_RC_PKT0_MIDDLE_ERROR                                                (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
43818     #define BRB_REG_INT_STS_WR_0_RC_PKT0_MIDDLE_ERROR_SHIFT                                          4
43819     #define BRB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR                                              (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
43820     #define BRB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                        5
43821     #define BRB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR                                                   (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
43822     #define BRB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR_SHIFT                                             6
43823     #define BRB_REG_INT_STS_WR_0_RC_PKT1_1ST_ERROR                                                   (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
43824     #define BRB_REG_INT_STS_WR_0_RC_PKT1_1ST_ERROR_SHIFT                                             7
43825     #define BRB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR                                                   (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
43826     #define BRB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR_SHIFT                                             8
43827     #define BRB_REG_INT_STS_WR_0_RC_PKT1_MIDDLE_ERROR                                                (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
43828     #define BRB_REG_INT_STS_WR_0_RC_PKT1_MIDDLE_ERROR_SHIFT                                          9
43829     #define BRB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR                                              (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
43830     #define BRB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                        10
43831     #define BRB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR                                                   (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
43832     #define BRB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR_SHIFT                                             11
43833     #define BRB_REG_INT_STS_WR_0_RC_PKT2_1ST_ERROR                                                   (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
43834     #define BRB_REG_INT_STS_WR_0_RC_PKT2_1ST_ERROR_SHIFT                                             12
43835     #define BRB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR                                                   (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
43836     #define BRB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR_SHIFT                                             13
43837     #define BRB_REG_INT_STS_WR_0_RC_PKT2_MIDDLE_ERROR                                                (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
43838     #define BRB_REG_INT_STS_WR_0_RC_PKT2_MIDDLE_ERROR_SHIFT                                          14
43839     #define BRB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR                                              (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
43840     #define BRB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                        15
43841     #define BRB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR                                                   (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
43842     #define BRB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR_SHIFT                                             16
43843     #define BRB_REG_INT_STS_WR_0_RC_PKT3_1ST_ERROR                                                   (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
43844     #define BRB_REG_INT_STS_WR_0_RC_PKT3_1ST_ERROR_SHIFT                                             17
43845     #define BRB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR                                                   (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
43846     #define BRB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR_SHIFT                                             18
43847     #define BRB_REG_INT_STS_WR_0_RC_PKT3_MIDDLE_ERROR                                                (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
43848     #define BRB_REG_INT_STS_WR_0_RC_PKT3_MIDDLE_ERROR_SHIFT                                          19
43849     #define BRB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR                                              (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
43850     #define BRB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                        20
43851     #define BRB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR                                            (0x1<<21) // SOP descriptor request from empty TC or port.
43852     #define BRB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                      21
43853     #define BRB_REG_INT_STS_WR_0_UNCOMPLIENT_LOSSLESS_ERROR                                          (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
43854     #define BRB_REG_INT_STS_WR_0_UNCOMPLIENT_LOSSLESS_ERROR_SHIFT                                    22
43855     #define BRB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR                                                  (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
43856     #define BRB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR_SHIFT                                            23
43857     #define BRB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR                                                  (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
43858     #define BRB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR_SHIFT                                            24
43859     #define BRB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR                                                  (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
43860     #define BRB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR_SHIFT                                            25
43861     #define BRB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR                                                  (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
43862     #define BRB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR_SHIFT                                            26
43863     #define BRB_REG_INT_STS_WR_0_LL_ARB_PREFETCH_SOP_ERROR                                           (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
43864     #define BRB_REG_INT_STS_WR_0_LL_ARB_PREFETCH_SOP_ERROR_SHIFT                                     27
43865     #define BRB_REG_INT_STS_WR_0_LL_BLK_ERROR                                                        (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
43866     #define BRB_REG_INT_STS_WR_0_LL_BLK_ERROR_SHIFT                                                  28
43867     #define BRB_REG_INT_STS_WR_0_PACKET_COUNTER_ERROR                                                (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
43868     #define BRB_REG_INT_STS_WR_0_PACKET_COUNTER_ERROR_SHIFT                                          29
43869     #define BRB_REG_INT_STS_WR_0_BYTE_COUNTER_ERROR                                                  (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
43870     #define BRB_REG_INT_STS_WR_0_BYTE_COUNTER_ERROR_SHIFT                                            30
43871     #define BRB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR                                                   (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
43872     #define BRB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR_SHIFT                                             31
43873 #define BRB_REG_INT_STS_CLR_0                                                                        0x3400ccUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
43874     #define BRB_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
43875     #define BRB_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
43876     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR                                                  (0x1<<1) // Read packet client PRM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
43877     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT                                            1
43878     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_1ST_ERROR                                                  (0x1<<2) // Read packet client PRM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
43879     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_1ST_ERROR_SHIFT                                            2
43880     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR                                                  (0x1<<3) // Read packet client PRM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
43881     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR_SHIFT                                            3
43882     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_MIDDLE_ERROR                                               (0x1<<4) // Read packet client PRM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR0/PRM/g in Comments::/RX_INT/d in Comments.
43883     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_MIDDLE_ERROR_SHIFT                                         4
43884     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR                                             (0x1<<5) // Read packet client PRM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
43885     #define BRB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                       5
43886     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR                                                  (0x1<<6) // Read packet client MSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
43887     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR_SHIFT                                            6
43888     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_1ST_ERROR                                                  (0x1<<7) // Read packet client MSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
43889     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_1ST_ERROR_SHIFT                                            7
43890     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR                                                  (0x1<<8) // Read packet client MSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
43891     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR_SHIFT                                            8
43892     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_MIDDLE_ERROR                                               (0x1<<9) // Read packet client MSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR1/MSDM/g in Comments::/RX_INT/d in Comments.
43893     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_MIDDLE_ERROR_SHIFT                                         9
43894     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR                                             (0x1<<10) // Read packet client MSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
43895     #define BRB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                       10
43896     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR                                                  (0x1<<11) // Read packet client TSDM release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
43897     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR_SHIFT                                            11
43898     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_1ST_ERROR                                                  (0x1<<12) // Read packet client TSDM first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
43899     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_1ST_ERROR_SHIFT                                            12
43900     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR                                                  (0x1<<13) // Read packet client TSDM length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
43901     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR_SHIFT                                            13
43902     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_MIDDLE_ERROR                                               (0x1<<14) // Read packet client TSDM error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR2/TSDM/g in Comments::/RX_INT/d in Comments.
43903     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_MIDDLE_ERROR_SHIFT                                         14
43904     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR                                             (0x1<<15) // Read packet client TSDM error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
43905     #define BRB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                       15
43906     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR                                                  (0x1<<16) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
43907     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR_SHIFT                                            16
43908     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_1ST_ERROR                                                  (0x1<<17) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
43909     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_1ST_ERROR_SHIFT                                            17
43910     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR                                                  (0x1<<18) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
43911     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR_SHIFT                                            18
43912     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_MIDDLE_ERROR                                               (0x1<<19) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
43913     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_MIDDLE_ERROR_SHIFT                                         19
43914     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR                                             (0x1<<20) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
43915     #define BRB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                       20
43916     #define BRB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR                                           (0x1<<21) // SOP descriptor request from empty TC or port.
43917     #define BRB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                     21
43918     #define BRB_REG_INT_STS_CLR_0_UNCOMPLIENT_LOSSLESS_ERROR                                         (0x1<<22) // One of uncoplient lossless counters is bigger than threshold PAUSE_EN::/PAUSE_EN/d in Comments.
43919     #define BRB_REG_INT_STS_CLR_0_UNCOMPLIENT_LOSSLESS_ERROR_SHIFT                                   22
43920     #define BRB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR                                                 (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
43921     #define BRB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR_SHIFT                                           23
43922     #define BRB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR                                                 (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
43923     #define BRB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR_SHIFT                                           24
43924     #define BRB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR                                                 (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
43925     #define BRB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR_SHIFT                                           25
43926     #define BRB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR                                                 (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
43927     #define BRB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR_SHIFT                                           26
43928     #define BRB_REG_INT_STS_CLR_0_LL_ARB_PREFETCH_SOP_ERROR                                          (0x1<<27) // Link list arbiter prefetch SOP error RX_INT::/RX_INT/d in Comments.
43929     #define BRB_REG_INT_STS_CLR_0_LL_ARB_PREFETCH_SOP_ERROR_SHIFT                                    27
43930     #define BRB_REG_INT_STS_CLR_0_LL_BLK_ERROR                                                       (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
43931     #define BRB_REG_INT_STS_CLR_0_LL_BLK_ERROR_SHIFT                                                 28
43932     #define BRB_REG_INT_STS_CLR_0_PACKET_COUNTER_ERROR                                               (0x1<<29) // Packet counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
43933     #define BRB_REG_INT_STS_CLR_0_PACKET_COUNTER_ERROR_SHIFT                                         29
43934     #define BRB_REG_INT_STS_CLR_0_BYTE_COUNTER_ERROR                                                 (0x1<<30) // Byte counter overflow for generating stop parsing interface RX_INT::/RX_INT/d in Comments.
43935     #define BRB_REG_INT_STS_CLR_0_BYTE_COUNTER_ERROR_SHIFT                                           30
43936     #define BRB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR                                                  (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
43937     #define BRB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR_SHIFT                                            31
43938 #define BRB_REG_INT_STS_1                                                                            0x3400d8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
43939     #define BRB_REG_INT_STS_1_MAC1_FC_CNT_ERROR                                                      (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
43940     #define BRB_REG_INT_STS_1_MAC1_FC_CNT_ERROR_SHIFT                                                0
43941     #define BRB_REG_INT_STS_1_LL_ARB_CALC_ERROR                                                      (0x1<<1) // Calculations error in LL arbiter block.
43942     #define BRB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT                                                1
43943     #define BRB_REG_INT_STS_1_WC0_INP_FIFO_ERROR                                                     (0x1<<3) // Input FIFO error in write client 0.
43944     #define BRB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT                                               3
43945     #define BRB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR                                                     (0x1<<4) // SOP FIFO error in write client 0.
43946     #define BRB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR_SHIFT                                               4
43947     #define BRB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR                                                     (0x1<<6) // EOP FIFO error in write client 0.
43948     #define BRB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR_SHIFT                                               6
43949     #define BRB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR                                                   (0x1<<7) // Queue FIFO error in write client 0.
43950     #define BRB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                             7
43951     #define BRB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR                                              (0x1<<8) // Free ointer FIFO error in write client 0.
43952     #define BRB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                        8
43953     #define BRB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR                                              (0x1<<9) // Next pointer FIFO error in write client 0.
43954     #define BRB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                        9
43955     #define BRB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR                                                    (0x1<<10) // Start FIFO error in write client 0.
43956     #define BRB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR_SHIFT                                              10
43957     #define BRB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR                                             (0x1<<11) // Second descriptor FIFO error in write client 0.
43958     #define BRB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                       11
43959     #define BRB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR                                               (0x1<<12) // Packet available FIFO error in write client 0.
43960     #define BRB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                         12
43961     #define BRB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR                                                 (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
43962     #define BRB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                           13
43963     #define BRB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR                                                  (0x1<<14) // Notify FIFO error in write client 0.
43964     #define BRB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                            14
43965     #define BRB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR                                                  (0x1<<15) // LL req error in write client 0.
43966     #define BRB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                            15
43967     #define BRB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR                                                    (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
43968     #define BRB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR_SHIFT                                              16
43969     #define BRB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR                                                    (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
43970     #define BRB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR_SHIFT                                              17
43971     #define BRB_REG_INT_STS_1_WC1_INP_FIFO_ERROR                                                     (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43972     #define BRB_REG_INT_STS_1_WC1_INP_FIFO_ERROR_SHIFT                                               18
43973     #define BRB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR                                                     (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43974     #define BRB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR_SHIFT                                               19
43975     #define BRB_REG_INT_STS_1_WC1_EOP_FIFO_ERROR                                                     (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43976     #define BRB_REG_INT_STS_1_WC1_EOP_FIFO_ERROR_SHIFT                                               20
43977     #define BRB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR                                                   (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43978     #define BRB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                             21
43979     #define BRB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR                                              (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43980     #define BRB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                        22
43981     #define BRB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR                                              (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43982     #define BRB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                        23
43983     #define BRB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR                                                    (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43984     #define BRB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR_SHIFT                                              24
43985     #define BRB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR                                             (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43986     #define BRB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                       25
43987     #define BRB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR                                               (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
43988     #define BRB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                         26
43989     #define BRB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR                                                 (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43990     #define BRB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                           27
43991     #define BRB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR                                                  (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
43992     #define BRB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                            28
43993     #define BRB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR                                                  (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
43994     #define BRB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                            29
43995     #define BRB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR                                                    (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
43996     #define BRB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR_SHIFT                                              30
43997     #define BRB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR                                                    (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
43998     #define BRB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR_SHIFT                                              31
43999 #define BRB_REG_INT_MASK_1                                                                           0x3400dcUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44000     #define BRB_REG_INT_MASK_1_MAC1_FC_CNT_ERROR                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.MAC1_FC_CNT_ERROR .
44001     #define BRB_REG_INT_MASK_1_MAC1_FC_CNT_ERROR_SHIFT                                               0
44002     #define BRB_REG_INT_MASK_1_LL_ARB_CALC_ERROR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
44003     #define BRB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT                                               1
44004     #define BRB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
44005     #define BRB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT                                              3
44006     #define BRB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
44007     #define BRB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR_SHIFT                                              4
44008     #define BRB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR                                                    (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_EOP_FIFO_ERROR .
44009     #define BRB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR_SHIFT                                              6
44010     #define BRB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
44011     #define BRB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                            7
44012     #define BRB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
44013     #define BRB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                       8
44014     #define BRB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
44015     #define BRB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                       9
44016     #define BRB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR                                                   (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
44017     #define BRB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR_SHIFT                                             10
44018     #define BRB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR                                            (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
44019     #define BRB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                      11
44020     #define BRB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
44021     #define BRB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                        12
44022     #define BRB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_COS_CNT_FIFO_ERROR .
44023     #define BRB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                          13
44024     #define BRB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
44025     #define BRB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                           14
44026     #define BRB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
44027     #define BRB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                           15
44028     #define BRB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
44029     #define BRB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR_SHIFT                                             16
44030     #define BRB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR                                                   (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
44031     #define BRB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR_SHIFT                                             17
44032     #define BRB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR                                                    (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_INP_FIFO_ERROR .
44033     #define BRB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR_SHIFT                                              18
44034     #define BRB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR                                                    (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_SOP_FIFO_ERROR .
44035     #define BRB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR_SHIFT                                              19
44036     #define BRB_REG_INT_MASK_1_WC1_EOP_FIFO_ERROR                                                    (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_EOP_FIFO_ERROR .
44037     #define BRB_REG_INT_MASK_1_WC1_EOP_FIFO_ERROR_SHIFT                                              20
44038     #define BRB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_QUEUE_FIFO_ERROR .
44039     #define BRB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                            21
44040     #define BRB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR                                             (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_FREE_POINT_FIFO_ERROR .
44041     #define BRB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                       22
44042     #define BRB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR                                             (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_NEXT_POINT_FIFO_ERROR .
44043     #define BRB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                       23
44044     #define BRB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_STRT_FIFO_ERROR .
44045     #define BRB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR_SHIFT                                             24
44046     #define BRB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR                                            (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_SECOND_DSCR_FIFO_ERROR .
44047     #define BRB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                      25
44048     #define BRB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR                                              (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_PKT_AVAIL_FIFO_ERROR .
44049     #define BRB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                        26
44050     #define BRB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR                                                (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_COS_CNT_FIFO_ERROR .
44051     #define BRB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                          27
44052     #define BRB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR                                                 (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_NOTIFY_FIFO_ERROR .
44053     #define BRB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                           28
44054     #define BRB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR                                                 (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_LL_REQ_FIFO_ERROR .
44055     #define BRB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                           29
44056     #define BRB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR                                                   (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_LL_PA_CNT_ERROR .
44057     #define BRB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR_SHIFT                                             30
44058     #define BRB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR                                                   (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_1.WC1_BB_PA_CNT_ERROR .
44059     #define BRB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR_SHIFT                                             31
44060 #define BRB_REG_INT_STS_WR_1                                                                         0x3400e0UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44061     #define BRB_REG_INT_STS_WR_1_MAC1_FC_CNT_ERROR                                                   (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
44062     #define BRB_REG_INT_STS_WR_1_MAC1_FC_CNT_ERROR_SHIFT                                             0
44063     #define BRB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR                                                   (0x1<<1) // Calculations error in LL arbiter block.
44064     #define BRB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT                                             1
44065     #define BRB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR                                                  (0x1<<3) // Input FIFO error in write client 0.
44066     #define BRB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT                                            3
44067     #define BRB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR                                                  (0x1<<4) // SOP FIFO error in write client 0.
44068     #define BRB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR_SHIFT                                            4
44069     #define BRB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR                                                  (0x1<<6) // EOP FIFO error in write client 0.
44070     #define BRB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR_SHIFT                                            6
44071     #define BRB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR                                                (0x1<<7) // Queue FIFO error in write client 0.
44072     #define BRB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                          7
44073     #define BRB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR                                           (0x1<<8) // Free ointer FIFO error in write client 0.
44074     #define BRB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                     8
44075     #define BRB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR                                           (0x1<<9) // Next pointer FIFO error in write client 0.
44076     #define BRB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                     9
44077     #define BRB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR                                                 (0x1<<10) // Start FIFO error in write client 0.
44078     #define BRB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR_SHIFT                                           10
44079     #define BRB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR                                          (0x1<<11) // Second descriptor FIFO error in write client 0.
44080     #define BRB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                    11
44081     #define BRB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR                                            (0x1<<12) // Packet available FIFO error in write client 0.
44082     #define BRB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                      12
44083     #define BRB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR                                              (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
44084     #define BRB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                        13
44085     #define BRB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR                                               (0x1<<14) // Notify FIFO error in write client 0.
44086     #define BRB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                         14
44087     #define BRB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR                                               (0x1<<15) // LL req error in write client 0.
44088     #define BRB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                         15
44089     #define BRB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR                                                 (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
44090     #define BRB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                           16
44091     #define BRB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR                                                 (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
44092     #define BRB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                           17
44093     #define BRB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR                                                  (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44094     #define BRB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR_SHIFT                                            18
44095     #define BRB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR                                                  (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44096     #define BRB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR_SHIFT                                            19
44097     #define BRB_REG_INT_STS_WR_1_WC1_EOP_FIFO_ERROR                                                  (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44098     #define BRB_REG_INT_STS_WR_1_WC1_EOP_FIFO_ERROR_SHIFT                                            20
44099     #define BRB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR                                                (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44100     #define BRB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                          21
44101     #define BRB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR                                           (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44102     #define BRB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                     22
44103     #define BRB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR                                           (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44104     #define BRB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                     23
44105     #define BRB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR                                                 (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44106     #define BRB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR_SHIFT                                           24
44107     #define BRB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR                                          (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44108     #define BRB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                    25
44109     #define BRB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR                                            (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
44110     #define BRB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                      26
44111     #define BRB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR                                              (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44112     #define BRB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                        27
44113     #define BRB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR                                               (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44114     #define BRB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                         28
44115     #define BRB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR                                               (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
44116     #define BRB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                         29
44117     #define BRB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR                                                 (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
44118     #define BRB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR_SHIFT                                           30
44119     #define BRB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR                                                 (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
44120     #define BRB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR_SHIFT                                           31
44121 #define BRB_REG_INT_STS_CLR_1                                                                        0x3400e4UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44122     #define BRB_REG_INT_STS_CLR_1_MAC1_FC_CNT_ERROR                                                  (0x1<<0) // Free shared area calculation error for MAC port 1 RX_INT::/RX_INT/d in Comments.
44123     #define BRB_REG_INT_STS_CLR_1_MAC1_FC_CNT_ERROR_SHIFT                                            0
44124     #define BRB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR                                                  (0x1<<1) // Calculations error in LL arbiter block.
44125     #define BRB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT                                            1
44126     #define BRB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR                                                 (0x1<<3) // Input FIFO error in write client 0.
44127     #define BRB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT                                           3
44128     #define BRB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR                                                 (0x1<<4) // SOP FIFO error in write client 0.
44129     #define BRB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR_SHIFT                                           4
44130     #define BRB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR                                                 (0x1<<6) // EOP FIFO error in write client 0.
44131     #define BRB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR_SHIFT                                           6
44132     #define BRB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR                                               (0x1<<7) // Queue FIFO error in write client 0.
44133     #define BRB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                         7
44134     #define BRB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR                                          (0x1<<8) // Free ointer FIFO error in write client 0.
44135     #define BRB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                    8
44136     #define BRB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR                                          (0x1<<9) // Next pointer FIFO error in write client 0.
44137     #define BRB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                    9
44138     #define BRB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR                                                (0x1<<10) // Start FIFO error in write client 0.
44139     #define BRB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR_SHIFT                                          10
44140     #define BRB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR                                         (0x1<<11) // Second descriptor FIFO error in write client 0.
44141     #define BRB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                   11
44142     #define BRB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR                                           (0x1<<12) // Packet available FIFO error in write client 0.
44143     #define BRB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                     12
44144     #define BRB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR                                             (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
44145     #define BRB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                       13
44146     #define BRB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR                                              (0x1<<14) // Notify FIFO error in write client 0.
44147     #define BRB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                        14
44148     #define BRB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR                                              (0x1<<15) // LL req error in write client 0.
44149     #define BRB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                        15
44150     #define BRB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR                                                (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
44151     #define BRB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                          16
44152     #define BRB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR                                                (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
44153     #define BRB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                          17
44154     #define BRB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR                                                 (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44155     #define BRB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR_SHIFT                                           18
44156     #define BRB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR                                                 (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44157     #define BRB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR_SHIFT                                           19
44158     #define BRB_REG_INT_STS_CLR_1_WC1_EOP_FIFO_ERROR                                                 (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44159     #define BRB_REG_INT_STS_CLR_1_WC1_EOP_FIFO_ERROR_SHIFT                                           20
44160     #define BRB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR                                               (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44161     #define BRB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                         21
44162     #define BRB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR                                          (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44163     #define BRB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                    22
44164     #define BRB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR                                          (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44165     #define BRB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                    23
44166     #define BRB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR                                                (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44167     #define BRB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR_SHIFT                                          24
44168     #define BRB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR                                         (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44169     #define BRB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                   25
44170     #define BRB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
44171     #define BRB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                     26
44172     #define BRB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR                                             (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44173     #define BRB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                       27
44174     #define BRB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR                                              (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
44175     #define BRB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                        28
44176     #define BRB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR                                              (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
44177     #define BRB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                        29
44178     #define BRB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR                                                (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
44179     #define BRB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR_SHIFT                                          30
44180     #define BRB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR                                                (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
44181     #define BRB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR_SHIFT                                          31
44182 #define BRB_REG_INT_STS_2                                                                            0x3400f0UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44183     #define BRB_REG_INT_STS_2_WC2_INP_FIFO_ERROR                                                     (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44184     #define BRB_REG_INT_STS_2_WC2_INP_FIFO_ERROR_SHIFT                                               0
44185     #define BRB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR                                                     (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44186     #define BRB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR_SHIFT                                               1
44187     #define BRB_REG_INT_STS_2_WC2_EOP_FIFO_ERROR                                                     (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44188     #define BRB_REG_INT_STS_2_WC2_EOP_FIFO_ERROR_SHIFT                                               2
44189     #define BRB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR                                                   (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44190     #define BRB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                             3
44191     #define BRB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR                                              (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44192     #define BRB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                        4
44193     #define BRB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR                                              (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44194     #define BRB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                        5
44195     #define BRB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR                                                    (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44196     #define BRB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR_SHIFT                                              6
44197     #define BRB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR                                             (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44198     #define BRB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                       7
44199     #define BRB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR                                               (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
44200     #define BRB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                         8
44201     #define BRB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR                                                 (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44202     #define BRB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                           9
44203     #define BRB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR                                                  (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44204     #define BRB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                            10
44205     #define BRB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR                                                  (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
44206     #define BRB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                            11
44207     #define BRB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR                                                    (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
44208     #define BRB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR_SHIFT                                              12
44209     #define BRB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR                                                    (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
44210     #define BRB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR_SHIFT                                              13
44211     #define BRB_REG_INT_STS_2_WC3_INP_FIFO_ERROR                                                     (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44212     #define BRB_REG_INT_STS_2_WC3_INP_FIFO_ERROR_SHIFT                                               14
44213     #define BRB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR                                                     (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44214     #define BRB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR_SHIFT                                               15
44215     #define BRB_REG_INT_STS_2_WC3_EOP_FIFO_ERROR                                                     (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44216     #define BRB_REG_INT_STS_2_WC3_EOP_FIFO_ERROR_SHIFT                                               16
44217     #define BRB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR                                                   (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44218     #define BRB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                             17
44219     #define BRB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR                                              (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44220     #define BRB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                        18
44221     #define BRB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR                                              (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44222     #define BRB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                        19
44223     #define BRB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR                                                    (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44224     #define BRB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR_SHIFT                                              20
44225     #define BRB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR                                             (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44226     #define BRB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                       21
44227     #define BRB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR                                               (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
44228     #define BRB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                         22
44229     #define BRB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR                                                 (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44230     #define BRB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                           23
44231     #define BRB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR                                                  (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44232     #define BRB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                            24
44233     #define BRB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR                                                  (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
44234     #define BRB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                            25
44235     #define BRB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR                                                    (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
44236     #define BRB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR_SHIFT                                              26
44237     #define BRB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR                                                    (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
44238     #define BRB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR_SHIFT                                              27
44239 #define BRB_REG_INT_MASK_2                                                                           0x3400f4UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44240     #define BRB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_INP_FIFO_ERROR .
44241     #define BRB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR_SHIFT                                              0
44242     #define BRB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_SOP_FIFO_ERROR .
44243     #define BRB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR_SHIFT                                              1
44244     #define BRB_REG_INT_MASK_2_WC2_EOP_FIFO_ERROR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_EOP_FIFO_ERROR .
44245     #define BRB_REG_INT_MASK_2_WC2_EOP_FIFO_ERROR_SHIFT                                              2
44246     #define BRB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_QUEUE_FIFO_ERROR .
44247     #define BRB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                            3
44248     #define BRB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_FREE_POINT_FIFO_ERROR .
44249     #define BRB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                       4
44250     #define BRB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_NEXT_POINT_FIFO_ERROR .
44251     #define BRB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                       5
44252     #define BRB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_STRT_FIFO_ERROR .
44253     #define BRB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR_SHIFT                                             6
44254     #define BRB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_SECOND_DSCR_FIFO_ERROR .
44255     #define BRB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                      7
44256     #define BRB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR                                              (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_PKT_AVAIL_FIFO_ERROR .
44257     #define BRB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                        8
44258     #define BRB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_COS_CNT_FIFO_ERROR .
44259     #define BRB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                          9
44260     #define BRB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_NOTIFY_FIFO_ERROR .
44261     #define BRB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                           10
44262     #define BRB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_LL_REQ_FIFO_ERROR .
44263     #define BRB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                           11
44264     #define BRB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR                                                   (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_LL_PA_CNT_ERROR .
44265     #define BRB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR_SHIFT                                             12
44266     #define BRB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR                                                   (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC2_BB_PA_CNT_ERROR .
44267     #define BRB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR_SHIFT                                             13
44268     #define BRB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR                                                    (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_INP_FIFO_ERROR .
44269     #define BRB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR_SHIFT                                              14
44270     #define BRB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR                                                    (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_SOP_FIFO_ERROR .
44271     #define BRB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR_SHIFT                                              15
44272     #define BRB_REG_INT_MASK_2_WC3_EOP_FIFO_ERROR                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_EOP_FIFO_ERROR .
44273     #define BRB_REG_INT_MASK_2_WC3_EOP_FIFO_ERROR_SHIFT                                              16
44274     #define BRB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_QUEUE_FIFO_ERROR .
44275     #define BRB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                            17
44276     #define BRB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_FREE_POINT_FIFO_ERROR .
44277     #define BRB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                       18
44278     #define BRB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_NEXT_POINT_FIFO_ERROR .
44279     #define BRB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                       19
44280     #define BRB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_STRT_FIFO_ERROR .
44281     #define BRB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR_SHIFT                                             20
44282     #define BRB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR                                            (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_SECOND_DSCR_FIFO_ERROR .
44283     #define BRB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                      21
44284     #define BRB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR                                              (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_PKT_AVAIL_FIFO_ERROR .
44285     #define BRB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                        22
44286     #define BRB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_COS_CNT_FIFO_ERROR .
44287     #define BRB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                          23
44288     #define BRB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR                                                 (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_NOTIFY_FIFO_ERROR .
44289     #define BRB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                           24
44290     #define BRB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR                                                 (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_LL_REQ_FIFO_ERROR .
44291     #define BRB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                           25
44292     #define BRB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR                                                   (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_LL_PA_CNT_ERROR .
44293     #define BRB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR_SHIFT                                             26
44294     #define BRB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_2.WC3_BB_PA_CNT_ERROR .
44295     #define BRB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR_SHIFT                                             27
44296 #define BRB_REG_INT_STS_WR_2                                                                         0x3400f8UL //Access:WR   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44297     #define BRB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR                                                  (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44298     #define BRB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR_SHIFT                                            0
44299     #define BRB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR                                                  (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44300     #define BRB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR_SHIFT                                            1
44301     #define BRB_REG_INT_STS_WR_2_WC2_EOP_FIFO_ERROR                                                  (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44302     #define BRB_REG_INT_STS_WR_2_WC2_EOP_FIFO_ERROR_SHIFT                                            2
44303     #define BRB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR                                                (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44304     #define BRB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                          3
44305     #define BRB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR                                           (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44306     #define BRB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                     4
44307     #define BRB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR                                           (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44308     #define BRB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                     5
44309     #define BRB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR                                                 (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44310     #define BRB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR_SHIFT                                           6
44311     #define BRB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR                                          (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44312     #define BRB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                    7
44313     #define BRB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR                                            (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
44314     #define BRB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                      8
44315     #define BRB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR                                              (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44316     #define BRB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                        9
44317     #define BRB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR                                               (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44318     #define BRB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                         10
44319     #define BRB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR                                               (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
44320     #define BRB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                         11
44321     #define BRB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR                                                 (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
44322     #define BRB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR_SHIFT                                           12
44323     #define BRB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR                                                 (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
44324     #define BRB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR_SHIFT                                           13
44325     #define BRB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR                                                  (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44326     #define BRB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR_SHIFT                                            14
44327     #define BRB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR                                                  (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44328     #define BRB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR_SHIFT                                            15
44329     #define BRB_REG_INT_STS_WR_2_WC3_EOP_FIFO_ERROR                                                  (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44330     #define BRB_REG_INT_STS_WR_2_WC3_EOP_FIFO_ERROR_SHIFT                                            16
44331     #define BRB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR                                                (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44332     #define BRB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                          17
44333     #define BRB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR                                           (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44334     #define BRB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                     18
44335     #define BRB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR                                           (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44336     #define BRB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                     19
44337     #define BRB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR                                                 (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44338     #define BRB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR_SHIFT                                           20
44339     #define BRB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR                                          (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44340     #define BRB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                    21
44341     #define BRB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR                                            (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
44342     #define BRB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                      22
44343     #define BRB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR                                              (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44344     #define BRB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                        23
44345     #define BRB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44346     #define BRB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                         24
44347     #define BRB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR                                               (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
44348     #define BRB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                         25
44349     #define BRB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR                                                 (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
44350     #define BRB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR_SHIFT                                           26
44351     #define BRB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR                                                 (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
44352     #define BRB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR_SHIFT                                           27
44353 #define BRB_REG_INT_STS_CLR_2                                                                        0x3400fcUL //Access:RC   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44354     #define BRB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR                                                 (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44355     #define BRB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR_SHIFT                                           0
44356     #define BRB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR                                                 (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44357     #define BRB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR_SHIFT                                           1
44358     #define BRB_REG_INT_STS_CLR_2_WC2_EOP_FIFO_ERROR                                                 (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44359     #define BRB_REG_INT_STS_CLR_2_WC2_EOP_FIFO_ERROR_SHIFT                                           2
44360     #define BRB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR                                               (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44361     #define BRB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                         3
44362     #define BRB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR                                          (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44363     #define BRB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                    4
44364     #define BRB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR                                          (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44365     #define BRB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                    5
44366     #define BRB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR                                                (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44367     #define BRB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR_SHIFT                                          6
44368     #define BRB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR                                         (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44369     #define BRB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                   7
44370     #define BRB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR                                           (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
44371     #define BRB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                     8
44372     #define BRB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR                                             (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44373     #define BRB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                       9
44374     #define BRB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR                                              (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
44375     #define BRB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                        10
44376     #define BRB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR                                              (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
44377     #define BRB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                        11
44378     #define BRB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR                                                (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
44379     #define BRB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR_SHIFT                                          12
44380     #define BRB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR                                                (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
44381     #define BRB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR_SHIFT                                          13
44382     #define BRB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR                                                 (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44383     #define BRB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR_SHIFT                                           14
44384     #define BRB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR                                                 (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44385     #define BRB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR_SHIFT                                           15
44386     #define BRB_REG_INT_STS_CLR_2_WC3_EOP_FIFO_ERROR                                                 (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44387     #define BRB_REG_INT_STS_CLR_2_WC3_EOP_FIFO_ERROR_SHIFT                                           16
44388     #define BRB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR                                               (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44389     #define BRB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                         17
44390     #define BRB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR                                          (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44391     #define BRB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                    18
44392     #define BRB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR                                          (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44393     #define BRB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                    19
44394     #define BRB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR                                                (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44395     #define BRB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR_SHIFT                                          20
44396     #define BRB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR                                         (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44397     #define BRB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                   21
44398     #define BRB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR                                           (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
44399     #define BRB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                     22
44400     #define BRB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR                                             (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44401     #define BRB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                       23
44402     #define BRB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR                                              (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
44403     #define BRB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                        24
44404     #define BRB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR                                              (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
44405     #define BRB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                        25
44406     #define BRB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR                                                (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
44407     #define BRB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR_SHIFT                                          26
44408     #define BRB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR                                                (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
44409     #define BRB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR_SHIFT                                          27
44410 #define BRB_REG_INT_STS_3                                                                            0x340108UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44411     #define BRB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR                                                (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44412     #define BRB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                          1
44413     #define BRB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR                                                 (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44414     #define BRB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                           2
44415     #define BRB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR                                                 (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44416     #define BRB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                           3
44417     #define BRB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                            (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44418     #define BRB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                      4
44419     #define BRB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                            (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44420     #define BRB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                      5
44421     #define BRB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                          (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44422     #define BRB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                    6
44423     #define BRB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR                                                 (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44424     #define BRB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                           7
44425     #define BRB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR                                                (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44426     #define BRB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                          8
44427     #define BRB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR                                                (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44428     #define BRB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                          9
44429     #define BRB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR                                                 (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44430     #define BRB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                           10
44431     #define BRB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR                                                 (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44432     #define BRB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                           11
44433     #define BRB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                            (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44434     #define BRB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                      12
44435     #define BRB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                            (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44436     #define BRB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                      13
44437     #define BRB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                          (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44438     #define BRB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                    14
44439     #define BRB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR                                                 (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44440     #define BRB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                           15
44441     #define BRB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR                                                (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44442     #define BRB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                          16
44443     #define BRB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR                                                (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44444     #define BRB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                          17
44445     #define BRB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR                                                 (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44446     #define BRB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                           18
44447     #define BRB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR                                                 (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44448     #define BRB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                           19
44449     #define BRB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                            (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44450     #define BRB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                      20
44451     #define BRB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                            (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44452     #define BRB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                      21
44453     #define BRB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                          (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44454     #define BRB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                    22
44455     #define BRB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR                                                 (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44456     #define BRB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                           23
44457     #define BRB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR                                                (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44458     #define BRB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                          24
44459     #define BRB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR                                                (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44460     #define BRB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                          25
44461     #define BRB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR                                                 (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44462     #define BRB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                           26
44463     #define BRB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR                                                 (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44464     #define BRB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                           27
44465     #define BRB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                            (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44466     #define BRB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                      28
44467     #define BRB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                            (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44468     #define BRB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                      29
44469     #define BRB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                          (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44470     #define BRB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                    30
44471     #define BRB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR                                                 (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44472     #define BRB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                           31
44473 #define BRB_REG_INT_MASK_3                                                                           0x34010cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44474     #define BRB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
44475     #define BRB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                         1
44476     #define BRB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
44477     #define BRB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                          2
44478     #define BRB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
44479     #define BRB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                          3
44480     #define BRB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                           (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
44481     #define BRB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                     4
44482     #define BRB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                           (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
44483     #define BRB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                     5
44484     #define BRB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
44485     #define BRB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                   6
44486     #define BRB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
44487     #define BRB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                          7
44488     #define BRB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
44489     #define BRB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                         8
44490     #define BRB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
44491     #define BRB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                         9
44492     #define BRB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
44493     #define BRB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                          10
44494     #define BRB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
44495     #define BRB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                          11
44496     #define BRB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
44497     #define BRB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                     12
44498     #define BRB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                           (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
44499     #define BRB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                     13
44500     #define BRB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
44501     #define BRB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                   14
44502     #define BRB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
44503     #define BRB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                          15
44504     #define BRB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
44505     #define BRB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                         16
44506     #define BRB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR                                               (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
44507     #define BRB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                         17
44508     #define BRB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
44509     #define BRB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                          18
44510     #define BRB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR                                                (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
44511     #define BRB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                          19
44512     #define BRB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                           (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
44513     #define BRB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                     20
44514     #define BRB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                           (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
44515     #define BRB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                     21
44516     #define BRB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                         (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
44517     #define BRB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                   22
44518     #define BRB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
44519     #define BRB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                          23
44520     #define BRB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
44521     #define BRB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                         24
44522     #define BRB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
44523     #define BRB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                         25
44524     #define BRB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
44525     #define BRB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                          26
44526     #define BRB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR                                                (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
44527     #define BRB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                          27
44528     #define BRB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
44529     #define BRB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                     28
44530     #define BRB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
44531     #define BRB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                     29
44532     #define BRB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
44533     #define BRB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                   30
44534     #define BRB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
44535     #define BRB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                          31
44536 #define BRB_REG_INT_STS_WR_3                                                                         0x340110UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44537     #define BRB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR                                             (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44538     #define BRB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                       1
44539     #define BRB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR                                              (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44540     #define BRB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                        2
44541     #define BRB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR                                              (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44542     #define BRB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                        3
44543     #define BRB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                         (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44544     #define BRB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                   4
44545     #define BRB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                         (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44546     #define BRB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                   5
44547     #define BRB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                       (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44548     #define BRB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                 6
44549     #define BRB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR                                              (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44550     #define BRB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                        7
44551     #define BRB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR                                             (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44552     #define BRB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                       8
44553     #define BRB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR                                             (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44554     #define BRB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                       9
44555     #define BRB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR                                              (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44556     #define BRB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                        10
44557     #define BRB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR                                              (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44558     #define BRB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                        11
44559     #define BRB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                         (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44560     #define BRB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                   12
44561     #define BRB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                         (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44562     #define BRB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                   13
44563     #define BRB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                       (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44564     #define BRB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                 14
44565     #define BRB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR                                              (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44566     #define BRB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                        15
44567     #define BRB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR                                             (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44568     #define BRB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                       16
44569     #define BRB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR                                             (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44570     #define BRB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                       17
44571     #define BRB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR                                              (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44572     #define BRB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                        18
44573     #define BRB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR                                              (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44574     #define BRB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                        19
44575     #define BRB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                         (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44576     #define BRB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                   20
44577     #define BRB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                         (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44578     #define BRB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                   21
44579     #define BRB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                       (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44580     #define BRB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                 22
44581     #define BRB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR                                              (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44582     #define BRB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                        23
44583     #define BRB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR                                             (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44584     #define BRB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                       24
44585     #define BRB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR                                             (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44586     #define BRB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                       25
44587     #define BRB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR                                              (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44588     #define BRB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                        26
44589     #define BRB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR                                              (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44590     #define BRB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                        27
44591     #define BRB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                         (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44592     #define BRB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                   28
44593     #define BRB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                         (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44594     #define BRB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                   29
44595     #define BRB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                       (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44596     #define BRB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                 30
44597     #define BRB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR                                              (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44598     #define BRB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                        31
44599 #define BRB_REG_INT_STS_CLR_3                                                                        0x340114UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44600     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR                                            (0x1<<1) // Read packet client PRM side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44601     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                      1
44602     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR                                             (0x1<<2) // Read packet client PRM request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44603     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                       2
44604     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR                                             (0x1<<3) // Read packet client PRM block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44605     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                       3
44606     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                        (0x1<<4) // Read packet client PRM releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44607     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                  4
44608     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                        (0x1<<5) // Read packet client PRM start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44609     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                  5
44610     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                      (0x1<<6) // Read packet client PRM second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44611     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                6
44612     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR                                             (0x1<<7) // Read packet client PRM response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44613     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                       7
44614     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR                                            (0x1<<8) // Read packet client PRM descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
44615     #define BRB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                      8
44616     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR                                            (0x1<<9) // Read packet client MSDM side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44617     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                      9
44618     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR                                             (0x1<<10) // Read packet client MSDM request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44619     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                       10
44620     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR                                             (0x1<<11) // Read packet client MSDM block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44621     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                       11
44622     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                        (0x1<<12) // Read packet client MSDM releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44623     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                  12
44624     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                        (0x1<<13) // Read packet client MSDM start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44625     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                  13
44626     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                      (0x1<<14) // Read packet client MSDM second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44627     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                14
44628     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR                                             (0x1<<15) // Read packet client MSDM response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44629     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                       15
44630     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR                                            (0x1<<16) // Read packet client MSDM descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
44631     #define BRB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                      16
44632     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR                                            (0x1<<17) // Read packet client TSDM side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44633     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                      17
44634     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR                                             (0x1<<18) // Read packet client TSDM request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44635     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                       18
44636     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR                                             (0x1<<19) // Read packet client TSDM block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44637     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                       19
44638     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                        (0x1<<20) // Read packet client TSDM releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44639     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                  20
44640     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                        (0x1<<21) // Read packet client TSDM start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44641     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                  21
44642     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                      (0x1<<22) // Read packet client TSDM second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44643     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                22
44644     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR                                             (0x1<<23) // Read packet client TSDM response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44645     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                       23
44646     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR                                            (0x1<<24) // Read packet client TSDM descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
44647     #define BRB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                      24
44648     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR                                            (0x1<<25) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44649     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                      25
44650     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR                                             (0x1<<26) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44651     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                       26
44652     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR                                             (0x1<<27) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44653     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                       27
44654     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                        (0x1<<28) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44655     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                  28
44656     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                        (0x1<<29) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44657     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                  29
44658     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                      (0x1<<30) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44659     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                30
44660     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR                                             (0x1<<31) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44661     #define BRB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                       31
44662 #define BRB_REG_INT_STS_4                                                                            0x340120UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44663     #define BRB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR                                                (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44664     #define BRB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                          0
44665     #define BRB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR                                                 (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
44666     #define BRB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                           1
44667     #define BRB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR                                                  (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
44668     #define BRB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                            2
44669     #define BRB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR                                                 (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
44670     #define BRB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                           3
44671     #define BRB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR                                                (0x1<<4) // Read SOP client queue FIFO error.
44672     #define BRB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                          4
44673     #define BRB_REG_INT_STS_4_RC0_EOP_ERROR                                                          (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
44674     #define BRB_REG_INT_STS_4_RC0_EOP_ERROR_SHIFT                                                    5
44675     #define BRB_REG_INT_STS_4_RC1_EOP_ERROR                                                          (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
44676     #define BRB_REG_INT_STS_4_RC1_EOP_ERROR_SHIFT                                                    6
44677     #define BRB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR                                                  (0x1<<7) // Link list arbiter release FIFO error.
44678     #define BRB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                            7
44679     #define BRB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR                                             (0x1<<8) // Link list arbiter prefetch FIFO error.
44680     #define BRB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                       8
44681     #define BRB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR                                                 (0x1<<9) // Read packet client PRM release fifo error
44682     #define BRB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                           9
44683     #define BRB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR                                                 (0x1<<10) // Read packet client MSDM release fifo error
44684     #define BRB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                           10
44685     #define BRB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR                                                 (0x1<<11) // Read packet client TSDM release fifo error
44686     #define BRB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                           11
44687     #define BRB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR                                                 (0x1<<12) // Read packet client parser release fifo error
44688     #define BRB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                           12
44689     #define BRB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR                                                 (0x1<<13) // Read packet client parser release fifo error
44690     #define BRB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                           13
44691     #define BRB_REG_INT_STS_4_RC_PKT4_RLS_ERROR                                                      (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
44692     #define BRB_REG_INT_STS_4_RC_PKT4_RLS_ERROR_SHIFT                                                19
44693     #define BRB_REG_INT_STS_4_RC_PKT4_1ST_ERROR                                                      (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
44694     #define BRB_REG_INT_STS_4_RC_PKT4_1ST_ERROR_SHIFT                                                20
44695     #define BRB_REG_INT_STS_4_RC_PKT4_LEN_ERROR                                                      (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
44696     #define BRB_REG_INT_STS_4_RC_PKT4_LEN_ERROR_SHIFT                                                21
44697     #define BRB_REG_INT_STS_4_RC_PKT4_MIDDLE_ERROR                                                   (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
44698     #define BRB_REG_INT_STS_4_RC_PKT4_MIDDLE_ERROR_SHIFT                                             22
44699     #define BRB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR                                                 (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
44700     #define BRB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                           23
44701     #define BRB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR                                                (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44702     #define BRB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                          24
44703     #define BRB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR                                                 (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44704     #define BRB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                           25
44705     #define BRB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR                                                 (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44706     #define BRB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                           26
44707     #define BRB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                            (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44708     #define BRB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                      27
44709     #define BRB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                            (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44710     #define BRB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                      28
44711     #define BRB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                          (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44712     #define BRB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                    29
44713     #define BRB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR                                                 (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44714     #define BRB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                           30
44715     #define BRB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR                                                (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44716     #define BRB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                          31
44717 #define BRB_REG_INT_MASK_4                                                                           0x340124UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44718     #define BRB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
44719     #define BRB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                         0
44720     #define BRB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_STRT_FIFO_ERROR .
44721     #define BRB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                          1
44722     #define BRB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_REQ_FIFO_ERROR .
44723     #define BRB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                           2
44724     #define BRB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_DSCR_FIFO_ERROR .
44725     #define BRB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                          3
44726     #define BRB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
44727     #define BRB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                         4
44728     #define BRB_REG_INT_MASK_4_RC0_EOP_ERROR                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC0_EOP_ERROR .
44729     #define BRB_REG_INT_MASK_4_RC0_EOP_ERROR_SHIFT                                                   5
44730     #define BRB_REG_INT_MASK_4_RC1_EOP_ERROR                                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC1_EOP_ERROR .
44731     #define BRB_REG_INT_MASK_4_RC1_EOP_ERROR_SHIFT                                                   6
44732     #define BRB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
44733     #define BRB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                           7
44734     #define BRB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR                                            (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
44735     #define BRB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                      8
44736     #define BRB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
44737     #define BRB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                          9
44738     #define BRB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
44739     #define BRB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                          10
44740     #define BRB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
44741     #define BRB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                          11
44742     #define BRB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
44743     #define BRB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                          12
44744     #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
44745     #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                          13
44746     #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR                                                     (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
44747     #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR_SHIFT                                               19
44748     #define BRB_REG_INT_MASK_4_RC_PKT4_1ST_ERROR                                                     (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_1ST_ERROR .
44749     #define BRB_REG_INT_MASK_4_RC_PKT4_1ST_ERROR_SHIFT                                               20
44750     #define BRB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR                                                     (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_LEN_ERROR .
44751     #define BRB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR_SHIFT                                               21
44752     #define BRB_REG_INT_MASK_4_RC_PKT4_MIDDLE_ERROR                                                  (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_MIDDLE_ERROR .
44753     #define BRB_REG_INT_MASK_4_RC_PKT4_MIDDLE_ERROR_SHIFT                                            22
44754     #define BRB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
44755     #define BRB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                          23
44756     #define BRB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
44757     #define BRB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                         24
44758     #define BRB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR                                                (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
44759     #define BRB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                          25
44760     #define BRB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
44761     #define BRB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                          26
44762     #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
44763     #define BRB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                     27
44764     #define BRB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
44765     #define BRB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                     28
44766     #define BRB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                         (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
44767     #define BRB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                   29
44768     #define BRB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
44769     #define BRB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                          30
44770     #define BRB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR                                               (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
44771     #define BRB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                         31
44772 #define BRB_REG_INT_STS_WR_4                                                                         0x340128UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44773     #define BRB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR                                             (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44774     #define BRB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                       0
44775     #define BRB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR                                              (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
44776     #define BRB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                        1
44777     #define BRB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR                                               (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
44778     #define BRB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                         2
44779     #define BRB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR                                              (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
44780     #define BRB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                        3
44781     #define BRB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR                                             (0x1<<4) // Read SOP client queue FIFO error.
44782     #define BRB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                       4
44783     #define BRB_REG_INT_STS_WR_4_RC0_EOP_ERROR                                                       (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
44784     #define BRB_REG_INT_STS_WR_4_RC0_EOP_ERROR_SHIFT                                                 5
44785     #define BRB_REG_INT_STS_WR_4_RC1_EOP_ERROR                                                       (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
44786     #define BRB_REG_INT_STS_WR_4_RC1_EOP_ERROR_SHIFT                                                 6
44787     #define BRB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR                                               (0x1<<7) // Link list arbiter release FIFO error.
44788     #define BRB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                         7
44789     #define BRB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR                                          (0x1<<8) // Link list arbiter prefetch FIFO error.
44790     #define BRB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                    8
44791     #define BRB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR                                              (0x1<<9) // Read packet client PRM release fifo error
44792     #define BRB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                        9
44793     #define BRB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR                                              (0x1<<10) // Read packet client MSDM release fifo error
44794     #define BRB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                        10
44795     #define BRB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR                                              (0x1<<11) // Read packet client TSDM release fifo error
44796     #define BRB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                        11
44797     #define BRB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR                                              (0x1<<12) // Read packet client parser release fifo error
44798     #define BRB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                        12
44799     #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR                                              (0x1<<13) // Read packet client parser release fifo error
44800     #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                        13
44801     #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR                                                   (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
44802     #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR_SHIFT                                             19
44803     #define BRB_REG_INT_STS_WR_4_RC_PKT4_1ST_ERROR                                                   (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
44804     #define BRB_REG_INT_STS_WR_4_RC_PKT4_1ST_ERROR_SHIFT                                             20
44805     #define BRB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR                                                   (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
44806     #define BRB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR_SHIFT                                             21
44807     #define BRB_REG_INT_STS_WR_4_RC_PKT4_MIDDLE_ERROR                                                (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
44808     #define BRB_REG_INT_STS_WR_4_RC_PKT4_MIDDLE_ERROR_SHIFT                                          22
44809     #define BRB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR                                              (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
44810     #define BRB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                        23
44811     #define BRB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR                                             (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44812     #define BRB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                       24
44813     #define BRB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR                                              (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44814     #define BRB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                        25
44815     #define BRB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR                                              (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44816     #define BRB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                        26
44817     #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                         (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44818     #define BRB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                   27
44819     #define BRB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                         (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44820     #define BRB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                   28
44821     #define BRB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                       (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44822     #define BRB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                 29
44823     #define BRB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR                                              (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44824     #define BRB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                        30
44825     #define BRB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR                                             (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44826     #define BRB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                       31
44827 #define BRB_REG_INT_STS_CLR_4                                                                        0x34012cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44828     #define BRB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR                                            (0x1<<0) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44829     #define BRB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                      0
44830     #define BRB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR                                             (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
44831     #define BRB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                       1
44832     #define BRB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR                                              (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
44833     #define BRB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                        2
44834     #define BRB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR                                             (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
44835     #define BRB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                       3
44836     #define BRB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR                                            (0x1<<4) // Read SOP client queue FIFO error.
44837     #define BRB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                      4
44838     #define BRB_REG_INT_STS_CLR_4_RC0_EOP_ERROR                                                      (0x1<<5) // Read EOP client 0 request FIFO error RX_INT::/RX_INT/d in Comments.
44839     #define BRB_REG_INT_STS_CLR_4_RC0_EOP_ERROR_SHIFT                                                5
44840     #define BRB_REG_INT_STS_CLR_4_RC1_EOP_ERROR                                                      (0x1<<6) // Read EOP client 1 request FIFO error RX_INT::/RX_INT/d in Comments.
44841     #define BRB_REG_INT_STS_CLR_4_RC1_EOP_ERROR_SHIFT                                                6
44842     #define BRB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR                                              (0x1<<7) // Link list arbiter release FIFO error.
44843     #define BRB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                        7
44844     #define BRB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR                                         (0x1<<8) // Link list arbiter prefetch FIFO error.
44845     #define BRB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                   8
44846     #define BRB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR                                             (0x1<<9) // Read packet client PRM release fifo error
44847     #define BRB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                       9
44848     #define BRB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR                                             (0x1<<10) // Read packet client MSDM release fifo error
44849     #define BRB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                       10
44850     #define BRB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR                                             (0x1<<11) // Read packet client TSDM release fifo error
44851     #define BRB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                       11
44852     #define BRB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR                                             (0x1<<12) // Read packet client parser release fifo error
44853     #define BRB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                       12
44854     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR                                             (0x1<<13) // Read packet client parser release fifo error
44855     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                       13
44856     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR                                                  (0x1<<19) // Read packet client parser release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
44857     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR_SHIFT                                            19
44858     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_1ST_ERROR                                                  (0x1<<20) // Read packet client parser first block error when start block of packet is not really first packet block RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
44859     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_1ST_ERROR_SHIFT                                            20
44860     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR                                                  (0x1<<21) // Read packet client parser length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
44861     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR_SHIFT                                            21
44862     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_MIDDLE_ERROR                                               (0x1<<22) // Read packet client parser error when SOP bit is set in the packet block that is not first block f packet RX_INT::s/RC_PKT_DSCR3/parser/g in Comments::/RX_INT/d in Comments.
44863     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_MIDDLE_ERROR_SHIFT                                         22
44864     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR                                             (0x1<<23) // Read packet client parser error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
44865     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                       23
44866     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR                                            (0x1<<24) // Read packet client parser side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44867     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                      24
44868     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR                                             (0x1<<25) // Read packet client parser request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44869     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                       25
44870     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR                                             (0x1<<26) // Read packet client parser block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44871     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                       26
44872     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                        (0x1<<27) // Read packet client parser releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44873     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                  27
44874     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                        (0x1<<28) // Read packet client parser start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44875     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                  28
44876     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                      (0x1<<29) // Read packet client parser second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44877     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                29
44878     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR                                             (0x1<<30) // Read packet client parser response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44879     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                       30
44880     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR                                            (0x1<<31) // Read packet client parser descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
44881     #define BRB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                      31
44882 #define BRB_REG_INT_STS_5                                                                            0x340138UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
44883     #define BRB_REG_INT_STS_5_RC_PKT5_RLS_ERROR                                                      (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
44884     #define BRB_REG_INT_STS_5_RC_PKT5_RLS_ERROR_SHIFT                                                0
44885 #define BRB_REG_INT_MASK_5                                                                           0x34013cUL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
44886     #define BRB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
44887     #define BRB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR_SHIFT                                               0
44888 #define BRB_REG_INT_STS_WR_5                                                                         0x340140UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
44889     #define BRB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR                                                   (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
44890     #define BRB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR_SHIFT                                             0
44891 #define BRB_REG_INT_STS_CLR_5                                                                        0x340144UL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
44892     #define BRB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR                                                  (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
44893     #define BRB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR_SHIFT                                            0
44894 #define BRB_REG_INT_STS_6                                                                            0x340150UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44895     #define BRB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                  (0x1<<0) // Packet available SYNC FIFO error
44896     #define BRB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                            0
44897     #define BRB_REG_INT_STS_6_WC4_PROTOCOL_ERROR                                                     (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
44898     #define BRB_REG_INT_STS_6_WC4_PROTOCOL_ERROR_SHIFT                                               23
44899     #define BRB_REG_INT_STS_6_WC5_PROTOCOL_ERROR                                                     (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
44900     #define BRB_REG_INT_STS_6_WC5_PROTOCOL_ERROR_SHIFT                                               24
44901     #define BRB_REG_INT_STS_6_WC6_PROTOCOL_ERROR                                                     (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
44902     #define BRB_REG_INT_STS_6_WC6_PROTOCOL_ERROR_SHIFT                                               25
44903     #define BRB_REG_INT_STS_6_WC7_PROTOCOL_ERROR                                                     (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
44904     #define BRB_REG_INT_STS_6_WC7_PROTOCOL_ERROR_SHIFT                                               26
44905     #define BRB_REG_INT_STS_6_WC4_INP_FIFO_ERROR                                                     (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
44906     #define BRB_REG_INT_STS_6_WC4_INP_FIFO_ERROR_SHIFT                                               29
44907     #define BRB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR                                                     (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
44908     #define BRB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR_SHIFT                                               30
44909     #define BRB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR                                                   (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
44910     #define BRB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                             31
44911 #define BRB_REG_INT_MASK_6                                                                           0x340154UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44912     #define BRB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
44913     #define BRB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                           0
44914     #define BRB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_PROTOCOL_ERROR .
44915     #define BRB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR_SHIFT                                              23
44916     #define BRB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC5_PROTOCOL_ERROR .
44917     #define BRB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR_SHIFT                                              24
44918     #define BRB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR                                                    (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC6_PROTOCOL_ERROR .
44919     #define BRB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR_SHIFT                                              25
44920     #define BRB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC7_PROTOCOL_ERROR .
44921     #define BRB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR_SHIFT                                              26
44922     #define BRB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_INP_FIFO_ERROR .
44923     #define BRB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR_SHIFT                                              29
44924     #define BRB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR                                                    (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_SOP_FIFO_ERROR .
44925     #define BRB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR_SHIFT                                              30
44926     #define BRB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR                                                  (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_6.WC4_QUEUE_FIFO_ERROR .
44927     #define BRB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                            31
44928 #define BRB_REG_INT_STS_WR_6                                                                         0x340158UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44929     #define BRB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                               (0x1<<0) // Packet available SYNC FIFO error
44930     #define BRB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                         0
44931     #define BRB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR                                                  (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
44932     #define BRB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR_SHIFT                                            23
44933     #define BRB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR                                                  (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
44934     #define BRB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR_SHIFT                                            24
44935     #define BRB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR                                                  (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
44936     #define BRB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR_SHIFT                                            25
44937     #define BRB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR                                                  (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
44938     #define BRB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR_SHIFT                                            26
44939     #define BRB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR                                                  (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
44940     #define BRB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR_SHIFT                                            29
44941     #define BRB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR                                                  (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
44942     #define BRB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR_SHIFT                                            30
44943     #define BRB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR                                                (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
44944     #define BRB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                          31
44945 #define BRB_REG_INT_STS_CLR_6                                                                        0x34015cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44946     #define BRB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                              (0x1<<0) // Packet available SYNC FIFO error
44947     #define BRB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                        0
44948     #define BRB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR                                                 (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
44949     #define BRB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR_SHIFT                                           23
44950     #define BRB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR                                                 (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
44951     #define BRB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR_SHIFT                                           24
44952     #define BRB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR                                                 (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
44953     #define BRB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR_SHIFT                                           25
44954     #define BRB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR                                                 (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
44955     #define BRB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR_SHIFT                                           26
44956     #define BRB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR                                                 (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
44957     #define BRB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR_SHIFT                                           29
44958     #define BRB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR                                                 (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
44959     #define BRB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR_SHIFT                                           30
44960     #define BRB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR                                               (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
44961     #define BRB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                         31
44962 #define BRB_REG_INT_STS_7                                                                            0x340168UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
44963     #define BRB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR                                              (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
44964     #define BRB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                        0
44965     #define BRB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR                                              (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
44966     #define BRB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                        1
44967     #define BRB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR                                                    (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
44968     #define BRB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR_SHIFT                                              2
44969     #define BRB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR                                             (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
44970     #define BRB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                       3
44971     #define BRB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR                                               (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
44972     #define BRB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                         4
44973     #define BRB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR                                                 (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
44974     #define BRB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                           5
44975     #define BRB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR                                                  (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
44976     #define BRB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                            6
44977     #define BRB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR                                                  (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
44978     #define BRB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                            7
44979     #define BRB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR                                                    (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
44980     #define BRB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR_SHIFT                                              8
44981     #define BRB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR                                                    (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
44982     #define BRB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR_SHIFT                                              9
44983     #define BRB_REG_INT_STS_7_WC5_INP_FIFO_ERROR                                                     (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
44984     #define BRB_REG_INT_STS_7_WC5_INP_FIFO_ERROR_SHIFT                                               10
44985     #define BRB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR                                                     (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
44986     #define BRB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR_SHIFT                                               11
44987     #define BRB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR                                                   (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
44988     #define BRB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                             12
44989     #define BRB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR                                              (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
44990     #define BRB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                        13
44991     #define BRB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR                                              (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
44992     #define BRB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                        14
44993     #define BRB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR                                                    (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
44994     #define BRB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR_SHIFT                                              15
44995     #define BRB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR                                             (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
44996     #define BRB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                       16
44997     #define BRB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR                                               (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
44998     #define BRB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                         17
44999     #define BRB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR                                                 (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
45000     #define BRB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                           18
45001     #define BRB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR                                                  (0x1<<19) // Notify FIFO error in write client 5
45002     #define BRB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                            19
45003     #define BRB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR                                                  (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
45004     #define BRB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                            20
45005     #define BRB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR                                                    (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
45006     #define BRB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR_SHIFT                                              21
45007     #define BRB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR                                                    (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
45008     #define BRB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR_SHIFT                                              22
45009     #define BRB_REG_INT_STS_7_WC6_INP_FIFO_ERROR                                                     (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
45010     #define BRB_REG_INT_STS_7_WC6_INP_FIFO_ERROR_SHIFT                                               23
45011     #define BRB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR                                                     (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
45012     #define BRB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR_SHIFT                                               24
45013     #define BRB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR                                                   (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
45014     #define BRB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                             25
45015     #define BRB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR                                              (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
45016     #define BRB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                        26
45017     #define BRB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR                                              (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
45018     #define BRB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                        27
45019     #define BRB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR                                                    (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
45020     #define BRB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR_SHIFT                                              28
45021     #define BRB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR                                             (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
45022     #define BRB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                       29
45023     #define BRB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR                                               (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
45024     #define BRB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                         30
45025     #define BRB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR                                                 (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
45026     #define BRB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                           31
45027 #define BRB_REG_INT_MASK_7                                                                           0x34016cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45028     #define BRB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_FREE_POINT_FIFO_ERROR .
45029     #define BRB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                       0
45030     #define BRB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_NEXT_POINT_FIFO_ERROR .
45031     #define BRB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                       1
45032     #define BRB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_STRT_FIFO_ERROR .
45033     #define BRB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR_SHIFT                                             2
45034     #define BRB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_SECOND_DSCR_FIFO_ERROR .
45035     #define BRB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                      3
45036     #define BRB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_PKT_AVAIL_FIFO_ERROR .
45037     #define BRB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                        4
45038     #define BRB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_COS_CNT_FIFO_ERROR .
45039     #define BRB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                          5
45040     #define BRB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_NOTIFY_FIFO_ERROR .
45041     #define BRB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                           6
45042     #define BRB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_LL_REQ_FIFO_ERROR .
45043     #define BRB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                           7
45044     #define BRB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_LL_PA_CNT_ERROR .
45045     #define BRB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR_SHIFT                                             8
45046     #define BRB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC4_BB_PA_CNT_ERROR .
45047     #define BRB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR_SHIFT                                             9
45048     #define BRB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR                                                    (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_INP_FIFO_ERROR .
45049     #define BRB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR_SHIFT                                              10
45050     #define BRB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR                                                    (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_SOP_FIFO_ERROR .
45051     #define BRB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR_SHIFT                                              11
45052     #define BRB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR                                                  (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_QUEUE_FIFO_ERROR .
45053     #define BRB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                            12
45054     #define BRB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_FREE_POINT_FIFO_ERROR .
45055     #define BRB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                       13
45056     #define BRB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_NEXT_POINT_FIFO_ERROR .
45057     #define BRB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                       14
45058     #define BRB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR                                                   (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_STRT_FIFO_ERROR .
45059     #define BRB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR_SHIFT                                             15
45060     #define BRB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR                                            (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_SECOND_DSCR_FIFO_ERROR .
45061     #define BRB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                      16
45062     #define BRB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_PKT_AVAIL_FIFO_ERROR .
45063     #define BRB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                        17
45064     #define BRB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_COS_CNT_FIFO_ERROR .
45065     #define BRB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                          18
45066     #define BRB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_NOTIFY_FIFO_ERROR .
45067     #define BRB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                           19
45068     #define BRB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_LL_REQ_FIFO_ERROR .
45069     #define BRB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                           20
45070     #define BRB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR                                                   (0x1<<21) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_LL_PA_CNT_ERROR .
45071     #define BRB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR_SHIFT                                             21
45072     #define BRB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC5_BB_PA_CNT_ERROR .
45073     #define BRB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR_SHIFT                                             22
45074     #define BRB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_INP_FIFO_ERROR .
45075     #define BRB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR_SHIFT                                              23
45076     #define BRB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_SOP_FIFO_ERROR .
45077     #define BRB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR_SHIFT                                              24
45078     #define BRB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR                                                  (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_QUEUE_FIFO_ERROR .
45079     #define BRB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                            25
45080     #define BRB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR                                             (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_FREE_POINT_FIFO_ERROR .
45081     #define BRB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                       26
45082     #define BRB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR                                             (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_NEXT_POINT_FIFO_ERROR .
45083     #define BRB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                       27
45084     #define BRB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR                                                   (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_STRT_FIFO_ERROR .
45085     #define BRB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR_SHIFT                                             28
45086     #define BRB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR                                            (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_SECOND_DSCR_FIFO_ERROR .
45087     #define BRB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                      29
45088     #define BRB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR                                              (0x1<<30) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_PKT_AVAIL_FIFO_ERROR .
45089     #define BRB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                        30
45090     #define BRB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_7.WC6_COS_CNT_FIFO_ERROR .
45091     #define BRB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                          31
45092 #define BRB_REG_INT_STS_WR_7                                                                         0x340170UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45093     #define BRB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR                                           (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
45094     #define BRB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                     0
45095     #define BRB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR                                           (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
45096     #define BRB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                     1
45097     #define BRB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR                                                 (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
45098     #define BRB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR_SHIFT                                           2
45099     #define BRB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR                                          (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
45100     #define BRB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                    3
45101     #define BRB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR                                            (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
45102     #define BRB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                      4
45103     #define BRB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR                                              (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
45104     #define BRB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                        5
45105     #define BRB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR                                               (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
45106     #define BRB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                         6
45107     #define BRB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR                                               (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
45108     #define BRB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                         7
45109     #define BRB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR                                                 (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
45110     #define BRB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR_SHIFT                                           8
45111     #define BRB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR                                                 (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
45112     #define BRB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR_SHIFT                                           9
45113     #define BRB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR                                                  (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
45114     #define BRB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR_SHIFT                                            10
45115     #define BRB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR                                                  (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
45116     #define BRB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR_SHIFT                                            11
45117     #define BRB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR                                                (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
45118     #define BRB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                          12
45119     #define BRB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR                                           (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
45120     #define BRB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                     13
45121     #define BRB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR                                           (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
45122     #define BRB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                     14
45123     #define BRB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR                                                 (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
45124     #define BRB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR_SHIFT                                           15
45125     #define BRB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR                                          (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
45126     #define BRB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                    16
45127     #define BRB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR                                            (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
45128     #define BRB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                      17
45129     #define BRB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR                                              (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
45130     #define BRB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                        18
45131     #define BRB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR                                               (0x1<<19) // Notify FIFO error in write client 5
45132     #define BRB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                         19
45133     #define BRB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR                                               (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
45134     #define BRB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                         20
45135     #define BRB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR                                                 (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
45136     #define BRB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR_SHIFT                                           21
45137     #define BRB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR                                                 (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
45138     #define BRB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR_SHIFT                                           22
45139     #define BRB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR                                                  (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
45140     #define BRB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR_SHIFT                                            23
45141     #define BRB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR                                                  (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
45142     #define BRB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR_SHIFT                                            24
45143     #define BRB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR                                                (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
45144     #define BRB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                          25
45145     #define BRB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
45146     #define BRB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                     26
45147     #define BRB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR                                           (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
45148     #define BRB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                     27
45149     #define BRB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR                                                 (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
45150     #define BRB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR_SHIFT                                           28
45151     #define BRB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR                                          (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
45152     #define BRB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                    29
45153     #define BRB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR                                            (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
45154     #define BRB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                      30
45155     #define BRB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR                                              (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
45156     #define BRB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                        31
45157 #define BRB_REG_INT_STS_CLR_7                                                                        0x340174UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45158     #define BRB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR                                          (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
45159     #define BRB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                    0
45160     #define BRB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR                                          (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
45161     #define BRB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                    1
45162     #define BRB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR                                                (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
45163     #define BRB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR_SHIFT                                          2
45164     #define BRB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR                                         (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
45165     #define BRB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                   3
45166     #define BRB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR                                           (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
45167     #define BRB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                     4
45168     #define BRB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR                                             (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
45169     #define BRB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                       5
45170     #define BRB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR                                              (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
45171     #define BRB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                        6
45172     #define BRB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR                                              (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
45173     #define BRB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                        7
45174     #define BRB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR                                                (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
45175     #define BRB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR_SHIFT                                          8
45176     #define BRB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR                                                (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
45177     #define BRB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR_SHIFT                                          9
45178     #define BRB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR                                                 (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
45179     #define BRB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR_SHIFT                                           10
45180     #define BRB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR                                                 (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
45181     #define BRB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR_SHIFT                                           11
45182     #define BRB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR                                               (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
45183     #define BRB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                         12
45184     #define BRB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR                                          (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
45185     #define BRB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                    13
45186     #define BRB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR                                          (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
45187     #define BRB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                    14
45188     #define BRB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR                                                (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
45189     #define BRB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR_SHIFT                                          15
45190     #define BRB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR                                         (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
45191     #define BRB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                   16
45192     #define BRB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR                                           (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
45193     #define BRB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                     17
45194     #define BRB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR                                             (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
45195     #define BRB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                       18
45196     #define BRB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR                                              (0x1<<19) // Notify FIFO error in write client 5
45197     #define BRB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                        19
45198     #define BRB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR                                              (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
45199     #define BRB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                        20
45200     #define BRB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR                                                (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
45201     #define BRB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR_SHIFT                                          21
45202     #define BRB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR                                                (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
45203     #define BRB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR_SHIFT                                          22
45204     #define BRB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR                                                 (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
45205     #define BRB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR_SHIFT                                           23
45206     #define BRB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR                                                 (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
45207     #define BRB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR_SHIFT                                           24
45208     #define BRB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR                                               (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
45209     #define BRB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                         25
45210     #define BRB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR                                          (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
45211     #define BRB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                    26
45212     #define BRB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR                                          (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
45213     #define BRB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                    27
45214     #define BRB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR                                                (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
45215     #define BRB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR_SHIFT                                          28
45216     #define BRB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR                                         (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
45217     #define BRB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                   29
45218     #define BRB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR                                           (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
45219     #define BRB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                     30
45220     #define BRB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR                                             (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
45221     #define BRB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                       31
45222 #define BRB_REG_INT_STS_8                                                                            0x340184UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45223     #define BRB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR                                                  (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
45224     #define BRB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                            0
45225     #define BRB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR                                                  (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
45226     #define BRB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                            1
45227     #define BRB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR                                                    (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
45228     #define BRB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR_SHIFT                                              2
45229     #define BRB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR                                                    (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
45230     #define BRB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR_SHIFT                                              3
45231     #define BRB_REG_INT_STS_8_WC7_INP_FIFO_ERROR                                                     (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
45232     #define BRB_REG_INT_STS_8_WC7_INP_FIFO_ERROR_SHIFT                                               4
45233     #define BRB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR                                                     (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
45234     #define BRB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR_SHIFT                                               5
45235     #define BRB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR                                                   (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
45236     #define BRB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                             6
45237     #define BRB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR                                              (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
45238     #define BRB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                        7
45239     #define BRB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR                                              (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
45240     #define BRB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                        8
45241     #define BRB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR                                                    (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
45242     #define BRB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR_SHIFT                                              9
45243     #define BRB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR                                             (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
45244     #define BRB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                       10
45245     #define BRB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR                                               (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
45246     #define BRB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                         11
45247     #define BRB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR                                                 (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
45248     #define BRB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                           12
45249     #define BRB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR                                                  (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
45250     #define BRB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                            13
45251     #define BRB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR                                                  (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
45252     #define BRB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                            14
45253     #define BRB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR                                                    (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
45254     #define BRB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR_SHIFT                                              15
45255     #define BRB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR                                                    (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
45256     #define BRB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR_SHIFT                                              16
45257 #define BRB_REG_INT_MASK_8                                                                           0x340188UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45258     #define BRB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
45259     #define BRB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                           0
45260     #define BRB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_LL_REQ_FIFO_ERROR .
45261     #define BRB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                           1
45262     #define BRB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_LL_PA_CNT_ERROR .
45263     #define BRB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR_SHIFT                                             2
45264     #define BRB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC6_BB_PA_CNT_ERROR .
45265     #define BRB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR_SHIFT                                             3
45266     #define BRB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_INP_FIFO_ERROR .
45267     #define BRB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR_SHIFT                                              4
45268     #define BRB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_SOP_FIFO_ERROR .
45269     #define BRB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR_SHIFT                                              5
45270     #define BRB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_QUEUE_FIFO_ERROR .
45271     #define BRB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                            6
45272     #define BRB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_FREE_POINT_FIFO_ERROR .
45273     #define BRB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                       7
45274     #define BRB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_NEXT_POINT_FIFO_ERROR .
45275     #define BRB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                       8
45276     #define BRB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_STRT_FIFO_ERROR .
45277     #define BRB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR_SHIFT                                             9
45278     #define BRB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR                                            (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_SECOND_DSCR_FIFO_ERROR .
45279     #define BRB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                      10
45280     #define BRB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR                                              (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_PKT_AVAIL_FIFO_ERROR .
45281     #define BRB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                        11
45282     #define BRB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_COS_CNT_FIFO_ERROR .
45283     #define BRB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                          12
45284     #define BRB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR                                                 (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_NOTIFY_FIFO_ERROR .
45285     #define BRB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                           13
45286     #define BRB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_LL_REQ_FIFO_ERROR .
45287     #define BRB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                           14
45288     #define BRB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR                                                   (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_LL_PA_CNT_ERROR .
45289     #define BRB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR_SHIFT                                             15
45290     #define BRB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_8.WC7_BB_PA_CNT_ERROR .
45291     #define BRB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR_SHIFT                                             16
45292 #define BRB_REG_INT_STS_WR_8                                                                         0x34018cUL //Access:WR   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45293     #define BRB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR                                               (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
45294     #define BRB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                         0
45295     #define BRB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR                                               (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
45296     #define BRB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                         1
45297     #define BRB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR                                                 (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
45298     #define BRB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR_SHIFT                                           2
45299     #define BRB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR                                                 (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
45300     #define BRB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR_SHIFT                                           3
45301     #define BRB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR                                                  (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
45302     #define BRB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR_SHIFT                                            4
45303     #define BRB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR                                                  (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
45304     #define BRB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR_SHIFT                                            5
45305     #define BRB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR                                                (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
45306     #define BRB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                          6
45307     #define BRB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR                                           (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
45308     #define BRB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                     7
45309     #define BRB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR                                           (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
45310     #define BRB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                     8
45311     #define BRB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR                                                 (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
45312     #define BRB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR_SHIFT                                           9
45313     #define BRB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR                                          (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
45314     #define BRB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                    10
45315     #define BRB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR                                            (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
45316     #define BRB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                      11
45317     #define BRB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR                                              (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
45318     #define BRB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                        12
45319     #define BRB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR                                               (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
45320     #define BRB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                         13
45321     #define BRB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR                                               (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
45322     #define BRB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                         14
45323     #define BRB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR                                                 (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
45324     #define BRB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR_SHIFT                                           15
45325     #define BRB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR                                                 (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
45326     #define BRB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR_SHIFT                                           16
45327 #define BRB_REG_INT_STS_CLR_8                                                                        0x340190UL //Access:RC   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45328     #define BRB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR                                              (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
45329     #define BRB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                        0
45330     #define BRB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR                                              (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
45331     #define BRB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                        1
45332     #define BRB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR                                                (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
45333     #define BRB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR_SHIFT                                          2
45334     #define BRB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR                                                (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
45335     #define BRB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR_SHIFT                                          3
45336     #define BRB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR                                                 (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
45337     #define BRB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR_SHIFT                                           4
45338     #define BRB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR                                                 (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
45339     #define BRB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR_SHIFT                                           5
45340     #define BRB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR                                               (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
45341     #define BRB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                         6
45342     #define BRB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR                                          (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
45343     #define BRB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                    7
45344     #define BRB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR                                          (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
45345     #define BRB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                    8
45346     #define BRB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR                                                (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
45347     #define BRB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR_SHIFT                                          9
45348     #define BRB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR                                         (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
45349     #define BRB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                   10
45350     #define BRB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR                                           (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
45351     #define BRB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                     11
45352     #define BRB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR                                             (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
45353     #define BRB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                       12
45354     #define BRB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR                                              (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
45355     #define BRB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                        13
45356     #define BRB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR                                              (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
45357     #define BRB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                        14
45358     #define BRB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR                                                (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
45359     #define BRB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR_SHIFT                                          15
45360     #define BRB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR                                                (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
45361     #define BRB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR_SHIFT                                          16
45362 #define BRB_REG_INT_STS_9                                                                            0x34019cUL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
45363     #define BRB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR                                                   (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
45364     #define BRB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                             0
45365 #define BRB_REG_INT_MASK_9                                                                           0x3401a0UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
45366     #define BRB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
45367     #define BRB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                            0
45368 #define BRB_REG_INT_STS_WR_9                                                                         0x3401a4UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
45369     #define BRB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR                                                (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
45370     #define BRB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                          0
45371 #define BRB_REG_INT_STS_CLR_9                                                                        0x3401a8UL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
45372     #define BRB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR                                               (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
45373     #define BRB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                         0
45374 #define BRB_REG_INT_STS_10                                                                           0x3401b4UL //Access:R    DataWidth:0x1e  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45375     #define BRB_REG_INT_STS_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR                                       (0x1<<1) // SOP input SYNC FIFO error (for BRB)
45376     #define BRB_REG_INT_STS_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                 1
45377     #define BRB_REG_INT_STS_10_RC0_INP_SYNC_FIFO_PUSH_ERROR                                          (0x1<<2) // Packet RC input SYNC FIFO error
45378     #define BRB_REG_INT_STS_10_RC0_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                    2
45379     #define BRB_REG_INT_STS_10_RC1_INP_SYNC_FIFO_PUSH_ERROR                                          (0x1<<3) // Packet RC input SYNC FIFO error
45380     #define BRB_REG_INT_STS_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                    3
45381     #define BRB_REG_INT_STS_10_RC2_INP_SYNC_FIFO_PUSH_ERROR                                          (0x1<<4) // Packet RC input SYNC FIFO error
45382     #define BRB_REG_INT_STS_10_RC2_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                    4
45383     #define BRB_REG_INT_STS_10_RC3_INP_SYNC_FIFO_PUSH_ERROR                                          (0x1<<5) // Packet RC input SYNC FIFO error
45384     #define BRB_REG_INT_STS_10_RC3_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                    5
45385     #define BRB_REG_INT_STS_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR                                          (0x1<<12) // Packet RC output SYNC FIFO error
45386     #define BRB_REG_INT_STS_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                    12
45387     #define BRB_REG_INT_STS_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR                                          (0x1<<13) // Packet RC output SYNC FIFO error
45388     #define BRB_REG_INT_STS_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                    13
45389     #define BRB_REG_INT_STS_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR                                          (0x1<<14) // Packet RC output SYNC FIFO error
45390     #define BRB_REG_INT_STS_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                    14
45391     #define BRB_REG_INT_STS_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR                                          (0x1<<15) // Packet RC output SYNC FIFO error
45392     #define BRB_REG_INT_STS_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                    15
45393     #define BRB_REG_INT_STS_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR                                          (0x1<<16) // Packet RC output SYNC FIFO error
45394     #define BRB_REG_INT_STS_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                    16
45395     #define BRB_REG_INT_STS_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<22) // EOP RC input SYNC FIFO error
45396     #define BRB_REG_INT_STS_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                22
45397     #define BRB_REG_INT_STS_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<23) // EOP RC input SYNC FIFO error
45398     #define BRB_REG_INT_STS_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                23
45399     #define BRB_REG_INT_STS_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<24) // EOP RC input SYNC FIFO error
45400     #define BRB_REG_INT_STS_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                24
45401     #define BRB_REG_INT_STS_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<25) // EOP RC input SYNC FIFO error
45402     #define BRB_REG_INT_STS_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                25
45403     #define BRB_REG_INT_STS_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<26) // EOP RC output SYNC FIFO error
45404     #define BRB_REG_INT_STS_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                26
45405     #define BRB_REG_INT_STS_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<27) // EOP RC output SYNC FIFO error
45406     #define BRB_REG_INT_STS_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                27
45407     #define BRB_REG_INT_STS_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<28) // EOP RC output SYNC FIFO error
45408     #define BRB_REG_INT_STS_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                28
45409     #define BRB_REG_INT_STS_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<29) // EOP RC output SYNC FIFO error
45410     #define BRB_REG_INT_STS_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                29
45411 #define BRB_REG_INT_MASK_10                                                                          0x3401b8UL //Access:RW   DataWidth:0x1e  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45412     #define BRB_REG_INT_MASK_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC_SOP_INP_SYNC_FIFO_PUSH_ERROR .
45413     #define BRB_REG_INT_MASK_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                1
45414     #define BRB_REG_INT_MASK_10_RC0_INP_SYNC_FIFO_PUSH_ERROR                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_INP_SYNC_FIFO_PUSH_ERROR .
45415     #define BRB_REG_INT_MASK_10_RC0_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                   2
45416     #define BRB_REG_INT_MASK_10_RC1_INP_SYNC_FIFO_PUSH_ERROR                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_INP_SYNC_FIFO_PUSH_ERROR .
45417     #define BRB_REG_INT_MASK_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                   3
45418     #define BRB_REG_INT_MASK_10_RC2_INP_SYNC_FIFO_PUSH_ERROR                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_INP_SYNC_FIFO_PUSH_ERROR .
45419     #define BRB_REG_INT_MASK_10_RC2_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                   4
45420     #define BRB_REG_INT_MASK_10_RC3_INP_SYNC_FIFO_PUSH_ERROR                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_INP_SYNC_FIFO_PUSH_ERROR .
45421     #define BRB_REG_INT_MASK_10_RC3_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                   5
45422     #define BRB_REG_INT_MASK_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR                                         (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_OUT_SYNC_FIFO_PUSH_ERROR .
45423     #define BRB_REG_INT_MASK_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                   12
45424     #define BRB_REG_INT_MASK_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR                                         (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_OUT_SYNC_FIFO_PUSH_ERROR .
45425     #define BRB_REG_INT_MASK_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                   13
45426     #define BRB_REG_INT_MASK_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_OUT_SYNC_FIFO_PUSH_ERROR .
45427     #define BRB_REG_INT_MASK_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                   14
45428     #define BRB_REG_INT_MASK_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR                                         (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_OUT_SYNC_FIFO_PUSH_ERROR .
45429     #define BRB_REG_INT_MASK_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                   15
45430     #define BRB_REG_INT_MASK_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR                                         (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC4_OUT_SYNC_FIFO_PUSH_ERROR .
45431     #define BRB_REG_INT_MASK_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                   16
45432     #define BRB_REG_INT_MASK_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR .
45433     #define BRB_REG_INT_MASK_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                               22
45434     #define BRB_REG_INT_MASK_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR                                     (0x1<<23) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR .
45435     #define BRB_REG_INT_MASK_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                               23
45436     #define BRB_REG_INT_MASK_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR                                     (0x1<<24) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR .
45437     #define BRB_REG_INT_MASK_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                               24
45438     #define BRB_REG_INT_MASK_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR                                     (0x1<<25) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR .
45439     #define BRB_REG_INT_MASK_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                               25
45440     #define BRB_REG_INT_MASK_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                     (0x1<<26) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
45441     #define BRB_REG_INT_MASK_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                               26
45442     #define BRB_REG_INT_MASK_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                     (0x1<<27) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
45443     #define BRB_REG_INT_MASK_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                               27
45444     #define BRB_REG_INT_MASK_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                     (0x1<<28) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
45445     #define BRB_REG_INT_MASK_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                               28
45446     #define BRB_REG_INT_MASK_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                     (0x1<<29) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_10.RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR .
45447     #define BRB_REG_INT_MASK_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                               29
45448 #define BRB_REG_INT_STS_WR_10                                                                        0x3401bcUL //Access:WR   DataWidth:0x1e  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45449     #define BRB_REG_INT_STS_WR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR                                    (0x1<<1) // SOP input SYNC FIFO error (for BRB)
45450     #define BRB_REG_INT_STS_WR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                              1
45451     #define BRB_REG_INT_STS_WR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR                                       (0x1<<2) // Packet RC input SYNC FIFO error
45452     #define BRB_REG_INT_STS_WR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                 2
45453     #define BRB_REG_INT_STS_WR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR                                       (0x1<<3) // Packet RC input SYNC FIFO error
45454     #define BRB_REG_INT_STS_WR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                 3
45455     #define BRB_REG_INT_STS_WR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR                                       (0x1<<4) // Packet RC input SYNC FIFO error
45456     #define BRB_REG_INT_STS_WR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                 4
45457     #define BRB_REG_INT_STS_WR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR                                       (0x1<<5) // Packet RC input SYNC FIFO error
45458     #define BRB_REG_INT_STS_WR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                 5
45459     #define BRB_REG_INT_STS_WR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<12) // Packet RC output SYNC FIFO error
45460     #define BRB_REG_INT_STS_WR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 12
45461     #define BRB_REG_INT_STS_WR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<13) // Packet RC output SYNC FIFO error
45462     #define BRB_REG_INT_STS_WR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 13
45463     #define BRB_REG_INT_STS_WR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<14) // Packet RC output SYNC FIFO error
45464     #define BRB_REG_INT_STS_WR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 14
45465     #define BRB_REG_INT_STS_WR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<15) // Packet RC output SYNC FIFO error
45466     #define BRB_REG_INT_STS_WR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 15
45467     #define BRB_REG_INT_STS_WR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<16) // Packet RC output SYNC FIFO error
45468     #define BRB_REG_INT_STS_WR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 16
45469     #define BRB_REG_INT_STS_WR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR                                   (0x1<<22) // EOP RC input SYNC FIFO error
45470     #define BRB_REG_INT_STS_WR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                             22
45471     #define BRB_REG_INT_STS_WR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR                                   (0x1<<23) // EOP RC input SYNC FIFO error
45472     #define BRB_REG_INT_STS_WR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                             23
45473     #define BRB_REG_INT_STS_WR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR                                   (0x1<<24) // EOP RC input SYNC FIFO error
45474     #define BRB_REG_INT_STS_WR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                             24
45475     #define BRB_REG_INT_STS_WR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR                                   (0x1<<25) // EOP RC input SYNC FIFO error
45476     #define BRB_REG_INT_STS_WR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                             25
45477     #define BRB_REG_INT_STS_WR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                   (0x1<<26) // EOP RC output SYNC FIFO error
45478     #define BRB_REG_INT_STS_WR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                             26
45479     #define BRB_REG_INT_STS_WR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                   (0x1<<27) // EOP RC output SYNC FIFO error
45480     #define BRB_REG_INT_STS_WR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                             27
45481     #define BRB_REG_INT_STS_WR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                   (0x1<<28) // EOP RC output SYNC FIFO error
45482     #define BRB_REG_INT_STS_WR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                             28
45483     #define BRB_REG_INT_STS_WR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                   (0x1<<29) // EOP RC output SYNC FIFO error
45484     #define BRB_REG_INT_STS_WR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                             29
45485 #define BRB_REG_INT_STS_CLR_10                                                                       0x3401c0UL //Access:RC   DataWidth:0x1e  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45486     #define BRB_REG_INT_STS_CLR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR                                   (0x1<<1) // SOP input SYNC FIFO error (for BRB)
45487     #define BRB_REG_INT_STS_CLR_10_RC_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                             1
45488     #define BRB_REG_INT_STS_CLR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<2) // Packet RC input SYNC FIFO error
45489     #define BRB_REG_INT_STS_CLR_10_RC0_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                2
45490     #define BRB_REG_INT_STS_CLR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<3) // Packet RC input SYNC FIFO error
45491     #define BRB_REG_INT_STS_CLR_10_RC1_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                3
45492     #define BRB_REG_INT_STS_CLR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<4) // Packet RC input SYNC FIFO error
45493     #define BRB_REG_INT_STS_CLR_10_RC2_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                4
45494     #define BRB_REG_INT_STS_CLR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<5) // Packet RC input SYNC FIFO error
45495     #define BRB_REG_INT_STS_CLR_10_RC3_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                5
45496     #define BRB_REG_INT_STS_CLR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<12) // Packet RC output SYNC FIFO error
45497     #define BRB_REG_INT_STS_CLR_10_RC0_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                12
45498     #define BRB_REG_INT_STS_CLR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<13) // Packet RC output SYNC FIFO error
45499     #define BRB_REG_INT_STS_CLR_10_RC1_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                13
45500     #define BRB_REG_INT_STS_CLR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<14) // Packet RC output SYNC FIFO error
45501     #define BRB_REG_INT_STS_CLR_10_RC2_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                14
45502     #define BRB_REG_INT_STS_CLR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<15) // Packet RC output SYNC FIFO error
45503     #define BRB_REG_INT_STS_CLR_10_RC3_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                15
45504     #define BRB_REG_INT_STS_CLR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<16) // Packet RC output SYNC FIFO error
45505     #define BRB_REG_INT_STS_CLR_10_RC4_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                16
45506     #define BRB_REG_INT_STS_CLR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR                                  (0x1<<22) // EOP RC input SYNC FIFO error
45507     #define BRB_REG_INT_STS_CLR_10_RC0_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                            22
45508     #define BRB_REG_INT_STS_CLR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR                                  (0x1<<23) // EOP RC input SYNC FIFO error
45509     #define BRB_REG_INT_STS_CLR_10_RC1_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                            23
45510     #define BRB_REG_INT_STS_CLR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR                                  (0x1<<24) // EOP RC input SYNC FIFO error
45511     #define BRB_REG_INT_STS_CLR_10_RC2_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                            24
45512     #define BRB_REG_INT_STS_CLR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR                                  (0x1<<25) // EOP RC input SYNC FIFO error
45513     #define BRB_REG_INT_STS_CLR_10_RC3_EOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                            25
45514     #define BRB_REG_INT_STS_CLR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                  (0x1<<26) // EOP RC output SYNC FIFO error
45515     #define BRB_REG_INT_STS_CLR_10_RC0_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                            26
45516     #define BRB_REG_INT_STS_CLR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                  (0x1<<27) // EOP RC output SYNC FIFO error
45517     #define BRB_REG_INT_STS_CLR_10_RC1_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                            27
45518     #define BRB_REG_INT_STS_CLR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                  (0x1<<28) // EOP RC output SYNC FIFO error
45519     #define BRB_REG_INT_STS_CLR_10_RC2_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                            28
45520     #define BRB_REG_INT_STS_CLR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR                                  (0x1<<29) // EOP RC output SYNC FIFO error
45521     #define BRB_REG_INT_STS_CLR_10_RC3_EOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                            29
45522 #define BRB_REG_INT_STS_11                                                                           0x3401ccUL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45523     #define BRB_REG_INT_STS_11_RC2_EOP_ERROR                                                         (0x1<<10) // Read EOP client 2 request FIFO error
45524     #define BRB_REG_INT_STS_11_RC2_EOP_ERROR_SHIFT                                                   10
45525     #define BRB_REG_INT_STS_11_RC3_EOP_ERROR                                                         (0x1<<11) // Read EOP client 2 request FIFO error
45526     #define BRB_REG_INT_STS_11_RC3_EOP_ERROR_SHIFT                                                   11
45527     #define BRB_REG_INT_STS_11_MAC2_FC_CNT_ERROR                                                     (0x1<<12) // Free shared area calculation error for MAC port 2
45528     #define BRB_REG_INT_STS_11_MAC2_FC_CNT_ERROR_SHIFT                                               12
45529     #define BRB_REG_INT_STS_11_MAC3_FC_CNT_ERROR                                                     (0x1<<13) // Free shared area calculation error for MAC port 3
45530     #define BRB_REG_INT_STS_11_MAC3_FC_CNT_ERROR_SHIFT                                               13
45531     #define BRB_REG_INT_STS_11_WC4_EOP_FIFO_ERROR                                                    (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
45532     #define BRB_REG_INT_STS_11_WC4_EOP_FIFO_ERROR_SHIFT                                              14
45533     #define BRB_REG_INT_STS_11_WC5_EOP_FIFO_ERROR                                                    (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
45534     #define BRB_REG_INT_STS_11_WC5_EOP_FIFO_ERROR_SHIFT                                              15
45535     #define BRB_REG_INT_STS_11_WC6_EOP_FIFO_ERROR                                                    (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
45536     #define BRB_REG_INT_STS_11_WC6_EOP_FIFO_ERROR_SHIFT                                              16
45537     #define BRB_REG_INT_STS_11_WC7_EOP_FIFO_ERROR                                                    (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
45538     #define BRB_REG_INT_STS_11_WC7_EOP_FIFO_ERROR_SHIFT                                              17
45539 #define BRB_REG_INT_MASK_11                                                                          0x3401d0UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45540     #define BRB_REG_INT_MASK_11_RC2_EOP_ERROR                                                        (0x1<<10) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.RC2_EOP_ERROR .
45541     #define BRB_REG_INT_MASK_11_RC2_EOP_ERROR_SHIFT                                                  10
45542     #define BRB_REG_INT_MASK_11_RC3_EOP_ERROR                                                        (0x1<<11) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.RC3_EOP_ERROR .
45543     #define BRB_REG_INT_MASK_11_RC3_EOP_ERROR_SHIFT                                                  11
45544     #define BRB_REG_INT_MASK_11_MAC2_FC_CNT_ERROR                                                    (0x1<<12) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.MAC2_FC_CNT_ERROR .
45545     #define BRB_REG_INT_MASK_11_MAC2_FC_CNT_ERROR_SHIFT                                              12
45546     #define BRB_REG_INT_MASK_11_MAC3_FC_CNT_ERROR                                                    (0x1<<13) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.MAC3_FC_CNT_ERROR .
45547     #define BRB_REG_INT_MASK_11_MAC3_FC_CNT_ERROR_SHIFT                                              13
45548     #define BRB_REG_INT_MASK_11_WC4_EOP_FIFO_ERROR                                                   (0x1<<14) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC4_EOP_FIFO_ERROR .
45549     #define BRB_REG_INT_MASK_11_WC4_EOP_FIFO_ERROR_SHIFT                                             14
45550     #define BRB_REG_INT_MASK_11_WC5_EOP_FIFO_ERROR                                                   (0x1<<15) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC5_EOP_FIFO_ERROR .
45551     #define BRB_REG_INT_MASK_11_WC5_EOP_FIFO_ERROR_SHIFT                                             15
45552     #define BRB_REG_INT_MASK_11_WC6_EOP_FIFO_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC6_EOP_FIFO_ERROR .
45553     #define BRB_REG_INT_MASK_11_WC6_EOP_FIFO_ERROR_SHIFT                                             16
45554     #define BRB_REG_INT_MASK_11_WC7_EOP_FIFO_ERROR                                                   (0x1<<17) // This bit masks, when set, the Interrupt bit: BRB_REG_INT_STS_11.WC7_EOP_FIFO_ERROR .
45555     #define BRB_REG_INT_MASK_11_WC7_EOP_FIFO_ERROR_SHIFT                                             17
45556 #define BRB_REG_INT_STS_WR_11                                                                        0x3401d4UL //Access:WR   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45557     #define BRB_REG_INT_STS_WR_11_RC2_EOP_ERROR                                                      (0x1<<10) // Read EOP client 2 request FIFO error
45558     #define BRB_REG_INT_STS_WR_11_RC2_EOP_ERROR_SHIFT                                                10
45559     #define BRB_REG_INT_STS_WR_11_RC3_EOP_ERROR                                                      (0x1<<11) // Read EOP client 2 request FIFO error
45560     #define BRB_REG_INT_STS_WR_11_RC3_EOP_ERROR_SHIFT                                                11
45561     #define BRB_REG_INT_STS_WR_11_MAC2_FC_CNT_ERROR                                                  (0x1<<12) // Free shared area calculation error for MAC port 2
45562     #define BRB_REG_INT_STS_WR_11_MAC2_FC_CNT_ERROR_SHIFT                                            12
45563     #define BRB_REG_INT_STS_WR_11_MAC3_FC_CNT_ERROR                                                  (0x1<<13) // Free shared area calculation error for MAC port 3
45564     #define BRB_REG_INT_STS_WR_11_MAC3_FC_CNT_ERROR_SHIFT                                            13
45565     #define BRB_REG_INT_STS_WR_11_WC4_EOP_FIFO_ERROR                                                 (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
45566     #define BRB_REG_INT_STS_WR_11_WC4_EOP_FIFO_ERROR_SHIFT                                           14
45567     #define BRB_REG_INT_STS_WR_11_WC5_EOP_FIFO_ERROR                                                 (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
45568     #define BRB_REG_INT_STS_WR_11_WC5_EOP_FIFO_ERROR_SHIFT                                           15
45569     #define BRB_REG_INT_STS_WR_11_WC6_EOP_FIFO_ERROR                                                 (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
45570     #define BRB_REG_INT_STS_WR_11_WC6_EOP_FIFO_ERROR_SHIFT                                           16
45571     #define BRB_REG_INT_STS_WR_11_WC7_EOP_FIFO_ERROR                                                 (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
45572     #define BRB_REG_INT_STS_WR_11_WC7_EOP_FIFO_ERROR_SHIFT                                           17
45573 #define BRB_REG_INT_STS_CLR_11                                                                       0x3401d8UL //Access:RC   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45574     #define BRB_REG_INT_STS_CLR_11_RC2_EOP_ERROR                                                     (0x1<<10) // Read EOP client 2 request FIFO error
45575     #define BRB_REG_INT_STS_CLR_11_RC2_EOP_ERROR_SHIFT                                               10
45576     #define BRB_REG_INT_STS_CLR_11_RC3_EOP_ERROR                                                     (0x1<<11) // Read EOP client 2 request FIFO error
45577     #define BRB_REG_INT_STS_CLR_11_RC3_EOP_ERROR_SHIFT                                               11
45578     #define BRB_REG_INT_STS_CLR_11_MAC2_FC_CNT_ERROR                                                 (0x1<<12) // Free shared area calculation error for MAC port 2
45579     #define BRB_REG_INT_STS_CLR_11_MAC2_FC_CNT_ERROR_SHIFT                                           12
45580     #define BRB_REG_INT_STS_CLR_11_MAC3_FC_CNT_ERROR                                                 (0x1<<13) // Free shared area calculation error for MAC port 3
45581     #define BRB_REG_INT_STS_CLR_11_MAC3_FC_CNT_ERROR_SHIFT                                           13
45582     #define BRB_REG_INT_STS_CLR_11_WC4_EOP_FIFO_ERROR                                                (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 4
45583     #define BRB_REG_INT_STS_CLR_11_WC4_EOP_FIFO_ERROR_SHIFT                                          14
45584     #define BRB_REG_INT_STS_CLR_11_WC5_EOP_FIFO_ERROR                                                (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 5
45585     #define BRB_REG_INT_STS_CLR_11_WC5_EOP_FIFO_ERROR_SHIFT                                          15
45586     #define BRB_REG_INT_STS_CLR_11_WC6_EOP_FIFO_ERROR                                                (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 6
45587     #define BRB_REG_INT_STS_CLR_11_WC6_EOP_FIFO_ERROR_SHIFT                                          16
45588     #define BRB_REG_INT_STS_CLR_11_WC7_EOP_FIFO_ERROR                                                (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. EOP FIFO error in write client 7
45589     #define BRB_REG_INT_STS_CLR_11_WC7_EOP_FIFO_ERROR_SHIFT                                          17
45590 #define BRB_REG_PRTY_MASK                                                                            0x3401e0UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0 K2
45591     #define BRB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY                                                      (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
45592     #define BRB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY_SHIFT                                                0
45593     #define BRB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY                                                      (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
45594     #define BRB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT                                                1
45595     #define BRB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY                                                      (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
45596     #define BRB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY_SHIFT                                                2
45597     #define BRB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY                                                      (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
45598     #define BRB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT                                                3
45599     #define BRB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                     (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS.DATAPATH_REGISTERS .
45600     #define BRB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                               4
45601 #define BRB_REG_PRTY_MASK_H_0                                                                        0x340404UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45602     #define BRB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
45603     #define BRB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                          0
45604     #define BRB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
45605     #define BRB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT                                          1
45606     #define BRB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT                                                (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
45607     #define BRB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_SHIFT                                          2
45608     #define BRB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
45609     #define BRB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT                                          3
45610     #define BRB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT                                                (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
45611     #define BRB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_SHIFT                                          4
45612     #define BRB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
45613     #define BRB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_SHIFT                                          5
45614     #define BRB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT                                                (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
45615     #define BRB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_SHIFT                                          6
45616     #define BRB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT                                                (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
45617     #define BRB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_SHIFT                                          7
45618     #define BRB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT                                                (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
45619     #define BRB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT                                          8
45620     #define BRB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT                                                (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
45621     #define BRB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_SHIFT                                          9
45622     #define BRB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT                                                (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
45623     #define BRB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT                                          10
45624     #define BRB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT                                                (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
45625     #define BRB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT                                          11
45626     #define BRB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                                (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
45627     #define BRB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                          12
45628     #define BRB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT                                                (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
45629     #define BRB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT                                          13
45630     #define BRB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT                                                (0x1<<14) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
45631     #define BRB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_SHIFT                                          14
45632     #define BRB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT                                                (0x1<<15) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
45633     #define BRB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_SHIFT                                          15
45634     #define BRB_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY .
45635     #define BRB_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_SHIFT                                            16
45636     #define BRB_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY .
45637     #define BRB_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_SHIFT                                            17
45638     #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
45639     #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_A0_SHIFT                                      17
45640     #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
45641     #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_BB_B0_SHIFT                                      17
45642     #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM053_I_MEM_PRTY .
45643     #define BRB_REG_PRTY_MASK_H_0_MEM053_I_MEM_PRTY_K2_SHIFT                                         18
45644     #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
45645     #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_A0_SHIFT                                      16
45646     #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
45647     #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_BB_B0_SHIFT                                      16
45648     #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM054_I_MEM_PRTY .
45649     #define BRB_REG_PRTY_MASK_H_0_MEM054_I_MEM_PRTY_K2_SHIFT                                         19
45650     #define BRB_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
45651     #define BRB_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_SHIFT                                            20
45652     #define BRB_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
45653     #define BRB_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_SHIFT                                            21
45654     #define BRB_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
45655     #define BRB_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_SHIFT                                            22
45656     #define BRB_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
45657     #define BRB_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_SHIFT                                            23
45658     #define BRB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
45659     #define BRB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_SHIFT                                            24
45660     #define BRB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
45661     #define BRB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_SHIFT                                            25
45662     #define BRB_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
45663     #define BRB_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_SHIFT                                            26
45664     #define BRB_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
45665     #define BRB_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_SHIFT                                            27
45666     #define BRB_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
45667     #define BRB_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_SHIFT                                            28
45668     #define BRB_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
45669     #define BRB_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_SHIFT                                            29
45670     #define BRB_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY .
45671     #define BRB_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_SHIFT                                            30
45672     #define BRB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
45673     #define BRB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_SHIFT                                            18
45674     #define BRB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
45675     #define BRB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_SHIFT                                            19
45676     #define BRB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
45677     #define BRB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_SHIFT                                            20
45678     #define BRB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
45679     #define BRB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_SHIFT                                            21
45680     #define BRB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM049_I_MEM_PRTY .
45681     #define BRB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY_SHIFT                                            22
45682     #define BRB_REG_PRTY_MASK_H_0_MEM050_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM050_I_MEM_PRTY .
45683     #define BRB_REG_PRTY_MASK_H_0_MEM050_I_MEM_PRTY_SHIFT                                            23
45684     #define BRB_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
45685     #define BRB_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_SHIFT                                            24
45686     #define BRB_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM052_I_MEM_PRTY .
45687     #define BRB_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_SHIFT                                            25
45688     #define BRB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
45689     #define BRB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_SHIFT                                            26
45690     #define BRB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
45691     #define BRB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_SHIFT                                            27
45692     #define BRB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
45693     #define BRB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_SHIFT                                            28
45694     #define BRB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
45695     #define BRB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_SHIFT                                            29
45696     #define BRB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
45697     #define BRB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_SHIFT                                            30
45698     #define BRB_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
45699     #define BRB_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_SHIFT                                            30
45700 #define BRB_REG_PRTY_MASK_H_1                                                                        0x340414UL //Access:RW   DataWidth:0x1e  Multi Field Register.  Chips: BB_A0 BB_B0 K2
45701     #define BRB_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM066_I_MEM_PRTY .
45702     #define BRB_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_SHIFT                                            0
45703     #define BRB_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM067_I_MEM_PRTY .
45704     #define BRB_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_SHIFT                                            1
45705     #define BRB_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM068_I_MEM_PRTY .
45706     #define BRB_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_SHIFT                                            2
45707     #define BRB_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
45708     #define BRB_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_SHIFT                                            3
45709     #define BRB_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
45710     #define BRB_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_SHIFT                                            4
45711     #define BRB_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
45712     #define BRB_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_SHIFT                                            5
45713     #define BRB_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
45714     #define BRB_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_SHIFT                                            6
45715     #define BRB_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
45716     #define BRB_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_SHIFT                                            7
45717     #define BRB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
45718     #define BRB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_SHIFT                                            8
45719     #define BRB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
45720     #define BRB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_SHIFT                                            9
45721     #define BRB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
45722     #define BRB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_SHIFT                                            10
45723     #define BRB_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
45724     #define BRB_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_SHIFT                                            11
45725     #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
45726     #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_BB_A0_SHIFT                                      11
45727     #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_BB_B0                                            (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
45728     #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_BB_B0_SHIFT                                      6
45729     #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
45730     #define BRB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_K2_SHIFT                                         12
45731     #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
45732     #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_A0_SHIFT                                      12
45733     #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
45734     #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_BB_B0_SHIFT                                      7
45735     #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
45736     #define BRB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_K2_SHIFT                                         13
45737     #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
45738     #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_BB_A0_SHIFT                                      13
45739     #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_BB_B0                                            (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
45740     #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_BB_B0_SHIFT                                      8
45741     #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
45742     #define BRB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_K2_SHIFT                                         14
45743     #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
45744     #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_A0_SHIFT                                      9
45745     #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
45746     #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_B0_SHIFT                                      4
45747     #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
45748     #define BRB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_K2_SHIFT                                         15
45749     #define BRB_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_BB_A0                                            (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
45750     #define BRB_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_BB_A0_SHIFT                                      1
45751     #define BRB_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
45752     #define BRB_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_K2_SHIFT                                         16
45753     #define BRB_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_BB_A0                                            (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY .
45754     #define BRB_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_BB_A0_SHIFT                                      2
45755     #define BRB_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY .
45756     #define BRB_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_K2_SHIFT                                         17
45757     #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_A0                                            (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
45758     #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_A0_SHIFT                                      10
45759     #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_B0                                            (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
45760     #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_B0_SHIFT                                      5
45761     #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
45762     #define BRB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_K2_SHIFT                                         18
45763     #define BRB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
45764     #define BRB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_SHIFT                                            19
45765     #define BRB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_A0                                            (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
45766     #define BRB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_A0_SHIFT                                      0
45767     #define BRB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2                                               (0x1<<20) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
45768     #define BRB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2_SHIFT                                         20
45769     #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
45770     #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      14
45771     #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
45772     #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      9
45773     #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_K2                                               (0x1<<21) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
45774     #define BRB_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_K2_SHIFT                                         21
45775     #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_A0                                            (0x1<<15) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
45776     #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                      15
45777     #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
45778     #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                      10
45779     #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2                                               (0x1<<22) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
45780     #define BRB_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_K2_SHIFT                                         22
45781     #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
45782     #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                      16
45783     #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
45784     #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      11
45785     #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2                                               (0x1<<23) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
45786     #define BRB_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_K2_SHIFT                                         23
45787     #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
45788     #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      17
45789     #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
45790     #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      12
45791     #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_K2                                               (0x1<<24) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
45792     #define BRB_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_K2_SHIFT                                         24
45793     #define BRB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
45794     #define BRB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_SHIFT                                            25
45795     #define BRB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
45796     #define BRB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_SHIFT                                            26
45797     #define BRB_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
45798     #define BRB_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_SHIFT                                            27
45799     #define BRB_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
45800     #define BRB_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_SHIFT                                            28
45801     #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
45802     #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_A0_SHIFT                                      8
45803     #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
45804     #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_BB_B0_SHIFT                                      3
45805     #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_K2                                               (0x1<<29) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
45806     #define BRB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_K2_SHIFT                                         29
45807     #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_A0                                            (0x1<<5) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
45808     #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_A0_SHIFT                                      5
45809     #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_B0                                            (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
45810     #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_B0_SHIFT                                      0
45811     #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_K2                                               (0x1<<0) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
45812     #define BRB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_K2_SHIFT                                         0
45813     #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_A0                                            (0x1<<6) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
45814     #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_A0_SHIFT                                      6
45815     #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
45816     #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_B0_SHIFT                                      1
45817     #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
45818     #define BRB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_K2_SHIFT                                         1
45819     #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_A0                                            (0x1<<7) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
45820     #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_A0_SHIFT                                      7
45821     #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_B0                                            (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
45822     #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_BB_B0_SHIFT                                      2
45823     #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_K2                                               (0x1<<2) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
45824     #define BRB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_K2_SHIFT                                         2
45825     #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
45826     #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_A0_SHIFT                                      18
45827     #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
45828     #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_BB_B0_SHIFT                                      13
45829     #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
45830     #define BRB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_K2_SHIFT                                         13
45831     #define BRB_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM039_I_MEM_PRTY .
45832     #define BRB_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_SHIFT                                            3
45833     #define BRB_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: BRB_REG_PRTY_STS_H_1.MEM040_I_MEM_PRTY .
45834     #define BRB_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_SHIFT                                            4
45835 #define BRB_REG_MEM_ECC_EVENTS_BB_A0                                                                 0x34046cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0
45836 #define BRB_REG_MEM_ECC_EVENTS_BB_B0                                                                 0x34046cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_B0
45837 #define BRB_REG_MEM_ECC_EVENTS_K2                                                                    0x34042cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
45838 #define BRB_REG_MEM070_I_MEM_DFT_K2                                                                  0x340438UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.i_rc_req_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45839 #define BRB_REG_MEM069_I_MEM_DFT_K2                                                                  0x34043cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.i_dbgsyn_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45840 #define BRB_REG_MEM001_I_MEM_DFT_K2                                                                  0x340440UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45841 #define BRB_REG_MEM008_I_MEM_DFT_K2                                                                  0x340444UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45842 #define BRB_REG_MEM009_I_MEM_DFT_K2                                                                  0x340448UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45843 #define BRB_REG_MEM010_I_MEM_DFT_K2                                                                  0x34044cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45844 #define BRB_REG_MEM011_I_MEM_DFT_K2                                                                  0x340450UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45845 #define BRB_REG_MEM012_I_MEM_DFT_K2                                                                  0x340454UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45846 #define BRB_REG_MEM013_I_MEM_DFT_K2                                                                  0x340458UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45847 #define BRB_REG_MEM014_I_MEM_DFT_K2                                                                  0x34045cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45848 #define BRB_REG_MEM015_I_MEM_DFT_K2                                                                  0x340460UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45849 #define BRB_REG_MEM016_I_MEM_DFT_K2                                                                  0x340464UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45850 #define BRB_REG_MEM002_I_MEM_DFT_K2                                                                  0x340468UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45851 #define BRB_REG_MEM003_I_MEM_DFT_K2                                                                  0x34046cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45852 #define BRB_REG_MEM004_I_MEM_DFT_K2                                                                  0x340470UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45853 #define BRB_REG_MEM005_I_MEM_DFT_K2                                                                  0x340474UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45854 #define BRB_REG_MEM006_I_MEM_DFT_K2                                                                  0x340478UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45855 #define BRB_REG_MEM007_I_MEM_DFT_K2                                                                  0x34047cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
45856 #define BRB_REG_MEM025_I_MEM_DFT_K2                                                                  0x340480UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45857 #define BRB_REG_MEM026_I_MEM_DFT_K2                                                                  0x340484UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45858 #define BRB_REG_MEM027_I_MEM_DFT_K2                                                                  0x340488UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45859 #define BRB_REG_MEM028_I_MEM_DFT_K2                                                                  0x34048cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45860 #define BRB_REG_MEM053_I_MEM_DFT_K2                                                                  0x340490UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_INP_FIFO_GEN_FOR[0].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45861 #define BRB_REG_MEM054_I_MEM_DFT_K2                                                                  0x340494UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_INP_FIFO_GEN_FOR[1].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45862 #define BRB_REG_MEM055_I_MEM_DFT_K2                                                                  0x340498UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_INP_FIFO_GEN_FOR[2].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45863 #define BRB_REG_MEM056_I_MEM_DFT_K2                                                                  0x34049cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_INP_FIFO_GEN_FOR[3].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45864 #define BRB_REG_MEM057_I_MEM_DFT_K2                                                                  0x3404a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_INP_FIFO_GEN_FOR[4].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45865 #define BRB_REG_MEM058_I_MEM_DFT_K2                                                                  0x3404a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_INP_FIFO_GEN_FOR[5].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45866 #define BRB_REG_MEM059_I_MEM_DFT_K2                                                                  0x3404a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_INP_FIFO_GEN_FOR[6].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45867 #define BRB_REG_MEM060_I_MEM_DFT_K2                                                                  0x3404acUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_INP_FIFO_GEN_FOR[7].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45868 #define BRB_REG_MEM061_I_MEM_DFT_K2                                                                  0x3404b0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_SOP_FIFO_GEN_FOR[0].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45869 #define BRB_REG_MEM062_I_MEM_DFT_K2                                                                  0x3404b4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_SOP_FIFO_GEN_FOR[1].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45870 #define BRB_REG_MEM063_I_MEM_DFT_K2                                                                  0x3404b8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_SOP_FIFO_GEN_FOR[2].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45871 #define BRB_REG_MEM064_I_MEM_DFT_K2                                                                  0x3404bcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_SOP_FIFO_GEN_FOR[3].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45872 #define BRB_REG_MEM065_I_MEM_DFT_K2                                                                  0x3404c0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_SOP_FIFO_GEN_FOR[4].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45873 #define BRB_REG_MEM066_I_MEM_DFT_K2                                                                  0x3404c4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_SOP_FIFO_GEN_FOR[5].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45874 #define BRB_REG_MEM067_I_MEM_DFT_K2                                                                  0x3404c8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_SOP_FIFO_GEN_FOR[6].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45875 #define BRB_REG_MEM068_I_MEM_DFT_K2                                                                  0x3404ccUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_SOP_FIFO_GEN_FOR[7].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45876 #define BRB_REG_MEM045_I_MEM_DFT_K2                                                                  0x3404d0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_EOP_FIFO_GEN_FOR[0].i_wc_eop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45877 #define BRB_REG_MEM046_I_MEM_DFT_K2                                                                  0x3404d4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_EOP_FIFO_GEN_FOR[1].i_wc_eop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45878 #define BRB_REG_MEM047_I_MEM_DFT_K2                                                                  0x3404d8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_EOP_FIFO_GEN_FOR[2].i_wc_eop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45879 #define BRB_REG_MEM048_I_MEM_DFT_K2                                                                  0x3404dcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_EOP_FIFO_GEN_FOR[3].i_wc_eop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45880 #define BRB_REG_MEM049_I_MEM_DFT_K2                                                                  0x3404e0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_EOP_FIFO_GEN_FOR[4].i_wc_eop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45881 #define BRB_REG_MEM050_I_MEM_DFT_K2                                                                  0x3404e4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_EOP_FIFO_GEN_FOR[5].i_wc_eop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45882 #define BRB_REG_MEM051_I_MEM_DFT_K2                                                                  0x3404e8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_EOP_FIFO_GEN_FOR[6].i_wc_eop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45883 #define BRB_REG_MEM052_I_MEM_DFT_K2                                                                  0x3404ecUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.WC_EOP_FIFO_GEN_FOR[7].i_wc_eop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45884 #define BRB_REG_MEM039_I_MEM_DFT_K2                                                                  0x3404f0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.RC_RSP_FIFO_GEN_FOR[0].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45885 #define BRB_REG_MEM040_I_MEM_DFT_K2                                                                  0x3404f4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.RC_RSP_FIFO_GEN_FOR[1].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45886 #define BRB_REG_MEM041_I_MEM_DFT_K2                                                                  0x3404f8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.RC_RSP_FIFO_GEN_FOR[2].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45887 #define BRB_REG_MEM042_I_MEM_DFT_K2                                                                  0x3404fcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.RC_RSP_FIFO_GEN_FOR[3].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45888 #define BRB_REG_MEM043_I_MEM_DFT_K2                                                                  0x340500UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.RC_RSP_FIFO_GEN_FOR[4].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
45889 #define BRB_REG_MEM044_I_MEM_DFT_K2                                                                  0x340504UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.SOP_RC_INP_SYNC_FIFO_GEN_FOR[0].SOP_RC_INP_SYNC_FIFO_GEN_IF.i_sop_rc_inp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45890 #define BRB_REG_MEM030_I_MEM_DFT_K2                                                                  0x340508UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_INP_SYNC_FIFO_BIG_GEN_FOR[0].PKT_RC_INP_SYNC_FIFO_BIG_GEN_IF.i_pkt_rc_inp_sync_fifo_big.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45891 #define BRB_REG_MEM031_I_MEM_DFT_K2                                                                  0x34050cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_INP_SYNC_FIFO_REGULAR_GEN_FOR[1].PKT_RC_INP_SYNC_FIFO_REGULAR_GEN_IF.i_pkt_rc_inp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45892 #define BRB_REG_MEM032_I_MEM_DFT_K2                                                                  0x340510UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_INP_SYNC_FIFO_REGULAR_GEN_FOR[2].PKT_RC_INP_SYNC_FIFO_REGULAR_GEN_IF.i_pkt_rc_inp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45893 #define BRB_REG_MEM033_I_MEM_DFT_K2                                                                  0x340514UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_INP_SYNC_FIFO_REGULAR_GEN_FOR[3].PKT_RC_INP_SYNC_FIFO_REGULAR_GEN_IF.i_pkt_rc_inp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45894 #define BRB_REG_MEM037_I_MEM_DFT_K2                                                                  0x340518UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_OUT_SYNC_FIFO_128_SOP_GEN_FOR[4].PKT_RC_OUT_SYNC_FIFO_128_SOP_GEN_IF.i_pkt_rc_out_sync_fifo_data_128b_with_sop.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45895 #define BRB_REG_MEM038_I_MEM_DFT_K2                                                                  0x34051cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_OUT_SYNC_FIFO_256_GEN_FOR[0].PKT_RC_OUT_SYNC_FIFO_256_GEN_IF.i_pkt_rc_out_sync_fifo_data_256b.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45896 #define BRB_REG_MEM034_I_MEM_DFT_K2                                                                  0x340520UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_OUT_SYNC_FIFO_128_GEN_FOR[1].PKT_RC_OUT_SYNC_FIFO_128_GEN_IF.i_pkt_rc_out_sync_fifo_data_128b.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45897 #define BRB_REG_MEM035_I_MEM_DFT_K2                                                                  0x340524UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_OUT_SYNC_FIFO_128_GEN_FOR[2].PKT_RC_OUT_SYNC_FIFO_128_GEN_IF.i_pkt_rc_out_sync_fifo_data_128b.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45898 #define BRB_REG_MEM036_I_MEM_DFT_K2                                                                  0x340528UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_RC_OUT_SYNC_FIFO_128_GEN_FOR[3].PKT_RC_OUT_SYNC_FIFO_128_GEN_IF.i_pkt_rc_out_sync_fifo_data_128b.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45899 #define BRB_REG_MEM017_I_MEM_DFT_K2                                                                  0x34052cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.EOP_RC_INP_SYNC_FIFO_GEN_FOR[0].EOP_RC_INP_SYNC_FIFO_GEN_IF.i_eop_rc_inp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45900 #define BRB_REG_MEM018_I_MEM_DFT_K2                                                                  0x340530UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.EOP_RC_INP_SYNC_FIFO_GEN_FOR[1].EOP_RC_INP_SYNC_FIFO_GEN_IF.i_eop_rc_inp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45901 #define BRB_REG_MEM019_I_MEM_DFT_K2                                                                  0x340534UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.EOP_RC_INP_SYNC_FIFO_GEN_FOR[2].EOP_RC_INP_SYNC_FIFO_GEN_IF.i_eop_rc_inp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45902 #define BRB_REG_MEM020_I_MEM_DFT_K2                                                                  0x340538UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.EOP_RC_INP_SYNC_FIFO_GEN_FOR[3].EOP_RC_INP_SYNC_FIFO_GEN_IF.i_eop_rc_inp_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45903 #define BRB_REG_MEM021_I_MEM_DFT_K2                                                                  0x34053cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.EOP_RC_OUT_SYNC_FIFO_GEN_FOR[0].EOP_RC_OUT_SYNC_FIFO_GEN_IF.i_eop_rc_out_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45904 #define BRB_REG_MEM022_I_MEM_DFT_K2                                                                  0x340540UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.EOP_RC_OUT_SYNC_FIFO_GEN_FOR[1].EOP_RC_OUT_SYNC_FIFO_GEN_IF.i_eop_rc_out_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45905 #define BRB_REG_MEM023_I_MEM_DFT_K2                                                                  0x340544UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.EOP_RC_OUT_SYNC_FIFO_GEN_FOR[2].EOP_RC_OUT_SYNC_FIFO_GEN_IF.i_eop_rc_out_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45906 #define BRB_REG_MEM024_I_MEM_DFT_K2                                                                  0x340548UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.EOP_RC_OUT_SYNC_FIFO_GEN_FOR[3].EOP_RC_OUT_SYNC_FIFO_GEN_IF.i_eop_rc_out_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45907 #define BRB_REG_MEM029_I_MEM_DFT_K2                                                                  0x34054cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance brb.PKT_AVAIL_SYNC_FIFO_GEN_IF.i_pkt_avail_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
45908 #define BRB_REG_BIG_RAM_ADDRESS                                                                      0x340800UL //Access:RW   DataWidth:0xc   Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
45909 #define BRB_REG_HEADER_SIZE                                                                          0x340804UL //Access:RW   DataWidth:0xa   Number of valid bytes in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet available indication. (reset value of 17 suits to 282 bytes of header)::s/HDR_SIZE_RST/17/g in Reset Value.  Chips: BB_A0 BB_B0 K2
45910 #define BRB_REG_FREE_LIST_HEAD                                                                       0x340810UL //Access:RW   DataWidth:0xd   Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
45911 #define BRB_REG_FREE_LIST_HEAD_SIZE                                                                  4
45912 #define BRB_REG_FREE_LIST_TAIL                                                                       0x340820UL //Access:RW   DataWidth:0xd   Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
45913 #define BRB_REG_FREE_LIST_TAIL_SIZE                                                                  4
45914 #define BRB_REG_FREE_LIST_SIZE                                                                       0x340830UL //Access:RW   DataWidth:0xd   Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
45915 #define BRB_REG_FREE_LIST_SIZE_SIZE                                                                  4
45916 #define BRB_REG_MAX_RELEASES                                                                         0x340840UL //Access:RW   DataWidth:0xa   Number of packet copies that should be released before whole packet is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in Required::s/MAX_RLS_REQ/required/g in Software init.  Chips: BB_A0 BB_B0 K2
45917 #define BRB_REG_STOP_ON_LEN_ERR                                                                      0x340844UL //Access:RW   DataWidth:0x5   There is bit for each PACKET read client. When bit is set then read client will not execute more requests till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
45918 #define BRB_REG_SHARED_HR_AREA                                                                       0x340880UL //Access:RW   DataWidth:0xd   The total number available blocks for each MAC port that includes shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45919 #define BRB_REG_SHARED_HR_AREA_SIZE                                                                  4
45920 #define BRB_REG_TOTAL_MAC_SIZE                                                                       0x3408c0UL //Access:RW   DataWidth:0xd   The total number available blocks for each MAC port that includes guaranteed and shared and headroom areas. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45921 #define BRB_REG_TOTAL_MAC_SIZE_SIZE                                                                  4
45922 #define BRB_REG_TC_GUARANTIED_0                                                                      0x340900UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45923 #define BRB_REG_TC_GUARANTIED_1                                                                      0x340904UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45924 #define BRB_REG_TC_GUARANTIED_2                                                                      0x340908UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45925 #define BRB_REG_TC_GUARANTIED_3                                                                      0x34090cUL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45926 #define BRB_REG_TC_GUARANTIED_4                                                                      0x340910UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45927 #define BRB_REG_TC_GUARANTIED_5                                                                      0x340914UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45928 #define BRB_REG_TC_GUARANTIED_6                                                                      0x340918UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45929 #define BRB_REG_TC_GUARANTIED_7                                                                      0x34091cUL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45930 #define BRB_REG_TC_GUARANTIED_8                                                                      0x340920UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45931 #define BRB_REG_TC_GUARANTIED_9                                                                      0x340924UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45932 #define BRB_REG_TC_GUARANTIED_10                                                                     0x340928UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45933 #define BRB_REG_TC_GUARANTIED_11                                                                     0x34092cUL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45934 #define BRB_REG_TC_GUARANTIED_12                                                                     0x340930UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45935 #define BRB_REG_TC_GUARANTIED_13                                                                     0x340934UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45936 #define BRB_REG_TC_GUARANTIED_14                                                                     0x340938UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45937 #define BRB_REG_TC_GUARANTIED_15                                                                     0x34093cUL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45938 #define BRB_REG_TC_GUARANTIED_16                                                                     0x340940UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45939 #define BRB_REG_TC_GUARANTIED_17                                                                     0x340944UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45940 #define BRB_REG_TC_GUARANTIED_18                                                                     0x340948UL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
45941 #define BRB_REG_TC_GUARANTIED_19                                                                     0x34094cUL //Access:RW   DataWidth:0xd   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
45942 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_0                                                            0x340978UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45943 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_1                                                            0x34097cUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45944 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_2                                                            0x340980UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45945 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_3                                                            0x340984UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45946 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_4                                                            0x340988UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45947 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_5                                                            0x34098cUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45948 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_6                                                            0x340990UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45949 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_7                                                            0x340994UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45950 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_8                                                            0x340998UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45951 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_9                                                            0x34099cUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45952 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_10                                                           0x3409a0UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45953 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_11                                                           0x3409a4UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45954 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_12                                                           0x3409a8UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45955 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_13                                                           0x3409acUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45956 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_14                                                           0x3409b0UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45957 #define BRB_REG_MAIN_TC_GUARANTIED_HYST_15                                                           0x3409b4UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each main port.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45958 #define BRB_REG_LB_TC_GUARANTIED_HYST_0                                                              0x3409d8UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45959 #define BRB_REG_LB_TC_GUARANTIED_HYST_1                                                              0x3409dcUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45960 #define BRB_REG_LB_TC_GUARANTIED_HYST_2                                                              0x3409e0UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45961 #define BRB_REG_LB_TC_GUARANTIED_HYST_3                                                              0x3409e4UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45962 #define BRB_REG_LB_TC_GUARANTIED_HYST_4                                                              0x3409e8UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45963 #define BRB_REG_LB_TC_GUARANTIED_HYST_5                                                              0x3409ecUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45964 #define BRB_REG_LB_TC_GUARANTIED_HYST_6                                                              0x3409f0UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45965 #define BRB_REG_LB_TC_GUARANTIED_HYST_7                                                              0x3409f4UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45966 #define BRB_REG_LB_TC_GUARANTIED_HYST_8                                                              0x3409f8UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45967 #define BRB_REG_LB_TC_GUARANTIED_HYST_9                                                              0x3409fcUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45968 #define BRB_REG_LB_TC_GUARANTIED_HYST_10                                                             0x340a00UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45969 #define BRB_REG_LB_TC_GUARANTIED_HYST_11                                                             0x340a04UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45970 #define BRB_REG_LB_TC_GUARANTIED_HYST_12                                                             0x340a08UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45971 #define BRB_REG_LB_TC_GUARANTIED_HYST_13                                                             0x340a0cUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45972 #define BRB_REG_LB_TC_GUARANTIED_HYST_14                                                             0x340a10UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45973 #define BRB_REG_LB_TC_GUARANTIED_HYST_15                                                             0x340a14UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45974 #define BRB_REG_LB_TC_GUARANTIED_HYST_16                                                             0x340a18UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45975 #define BRB_REG_LB_TC_GUARANTIED_HYST_17                                                             0x340a1cUL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45976 #define BRB_REG_LB_TC_GUARANTIED_HYST_18                                                             0x340a20UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
45977 #define BRB_REG_LB_TC_GUARANTIED_HYST_19                                                             0x340a24UL //Access:RW   DataWidth:0xd   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
45978 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0                                                       0x340a50UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45979 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_1                                                       0x340a54UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45980 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_2                                                       0x340a58UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45981 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_3                                                       0x340a5cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45982 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_4                                                       0x340a60UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45983 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_5                                                       0x340a64UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45984 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_6                                                       0x340a68UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45985 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_7                                                       0x340a6cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45986 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_8                                                       0x340a70UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45987 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_9                                                       0x340a74UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45988 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_10                                                      0x340a78UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45989 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_11                                                      0x340a7cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45990 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_12                                                      0x340a80UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45991 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_13                                                      0x340a84UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45992 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_14                                                      0x340a88UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45993 #define BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_15                                                      0x340a8cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45994 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0                                                         0x340ab0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45995 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_1                                                         0x340ab4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45996 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_2                                                         0x340ab8UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45997 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_3                                                         0x340abcUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45998 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_4                                                         0x340ac0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
45999 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_5                                                         0x340ac4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46000 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_6                                                         0x340ac8UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46001 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_7                                                         0x340accUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46002 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_8                                                         0x340ad0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46003 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_9                                                         0x340ad4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46004 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_10                                                        0x340ad8UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46005 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_11                                                        0x340adcUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46006 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_12                                                        0x340ae0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46007 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_13                                                        0x340ae4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46008 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_14                                                        0x340ae8UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46009 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_15                                                        0x340aecUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46010 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_16                                                        0x340af0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46011 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_17                                                        0x340af4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46012 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_18                                                        0x340af8UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46013 #define BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_19                                                        0x340afcUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46014 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0                                                        0x340b28UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46015 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_1                                                        0x340b2cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46016 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_2                                                        0x340b30UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46017 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_3                                                        0x340b34UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46018 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_4                                                        0x340b38UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46019 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_5                                                        0x340b3cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46020 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_6                                                        0x340b40UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46021 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_7                                                        0x340b44UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46022 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_8                                                        0x340b48UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46023 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_9                                                        0x340b4cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46024 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_10                                                       0x340b50UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46025 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_11                                                       0x340b54UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46026 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_12                                                       0x340b58UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46027 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_13                                                       0x340b5cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46028 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_14                                                       0x340b60UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46029 #define BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_15                                                       0x340b64UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each main write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46030 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0                                                          0x340b88UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46031 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_1                                                          0x340b8cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46032 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_2                                                          0x340b90UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46033 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_3                                                          0x340b94UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46034 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_4                                                          0x340b98UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46035 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_5                                                          0x340b9cUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46036 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_6                                                          0x340ba0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46037 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_7                                                          0x340ba4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46038 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_8                                                          0x340ba8UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46039 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_9                                                          0x340bacUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46040 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_10                                                         0x340bb0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46041 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_11                                                         0x340bb4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46042 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_12                                                         0x340bb8UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46043 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_13                                                         0x340bbcUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46044 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_14                                                         0x340bc0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46045 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_15                                                         0x340bc4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46046 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_16                                                         0x340bc8UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46047 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_17                                                         0x340bccUL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46048 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_18                                                         0x340bd0UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46049 #define BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_19                                                         0x340bd4UL //Access:RW   DataWidth:0xd   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46050 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0                                                        0x340c00UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46051 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_1                                                        0x340c04UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46052 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_2                                                        0x340c08UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46053 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_3                                                        0x340c0cUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46054 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_4                                                        0x340c10UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46055 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_5                                                        0x340c14UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46056 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_6                                                        0x340c18UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46057 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_7                                                        0x340c1cUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46058 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_8                                                        0x340c20UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46059 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_9                                                        0x340c24UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46060 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_10                                                       0x340c28UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46061 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_11                                                       0x340c2cUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46062 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_12                                                       0x340c30UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46063 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_13                                                       0x340c34UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46064 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_14                                                       0x340c38UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46065 #define BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_15                                                       0x340c3cUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for main ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46066 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0                                                          0x340c60UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46067 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_1                                                          0x340c64UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46068 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_2                                                          0x340c68UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46069 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_3                                                          0x340c6cUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46070 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_4                                                          0x340c70UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46071 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_5                                                          0x340c74UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46072 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_6                                                          0x340c78UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46073 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_7                                                          0x340c7cUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46074 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_8                                                          0x340c80UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46075 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_9                                                          0x340c84UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46076 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_10                                                         0x340c88UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46077 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_11                                                         0x340c8cUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46078 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_12                                                         0x340c90UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46079 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_13                                                         0x340c94UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46080 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_14                                                         0x340c98UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46081 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_15                                                         0x340c9cUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46082 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_16                                                         0x340ca0UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46083 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_17                                                         0x340ca4UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46084 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_18                                                         0x340ca8UL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46085 #define BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_19                                                         0x340cacUL //Access:RW   DataWidth:0xd   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46086 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0                                                         0x340cd8UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46087 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_1                                                         0x340cdcUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46088 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_2                                                         0x340ce0UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46089 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_3                                                         0x340ce4UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46090 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_4                                                         0x340ce8UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46091 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_5                                                         0x340cecUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46092 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_6                                                         0x340cf0UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46093 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_7                                                         0x340cf4UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46094 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_8                                                         0x340cf8UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46095 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_9                                                         0x340cfcUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46096 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_10                                                        0x340d00UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46097 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_11                                                        0x340d04UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46098 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_12                                                        0x340d08UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46099 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_13                                                        0x340d0cUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46100 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_14                                                        0x340d10UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46101 #define BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_15                                                        0x340d14UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for main ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46102 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_0                                                           0x340d38UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46103 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_1                                                           0x340d3cUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46104 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_2                                                           0x340d40UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46105 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_3                                                           0x340d44UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46106 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_4                                                           0x340d48UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46107 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_5                                                           0x340d4cUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46108 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_6                                                           0x340d50UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46109 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_7                                                           0x340d54UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46110 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_8                                                           0x340d58UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46111 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_9                                                           0x340d5cUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46112 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_10                                                          0x340d60UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46113 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_11                                                          0x340d64UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46114 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_12                                                          0x340d68UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46115 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_13                                                          0x340d6cUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46116 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_14                                                          0x340d70UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46117 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_15                                                          0x340d74UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46118 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_16                                                          0x340d78UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46119 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_17                                                          0x340d7cUL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46120 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_18                                                          0x340d80UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46121 #define BRB_REG_LB_TC_FULL_XON_THRESHOLD_19                                                          0x340d84UL //Access:RW   DataWidth:0xd   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46122 #define BRB_REG_LOSSLESS_THRESHOLD                                                                   0x340db0UL //Access:RW   DataWidth:0xd   The number of allocated blocks in each TC after asserting pause upper whih full to that TC or interrupt will be asserted depending on lossless_int_en::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46123 #define BRB_REG_LOSSLESS_INT_EN                                                                      0x340db4UL //Access:RW   DataWidth:0x1   If 1 then interrupt will be asserted when number of allocated blocks in  TC bigger lossless_threshold, if 0 - then full to that TC will be asserted.::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46124 #define BRB_REG_BRTB_EMPTY_FOR_DUP                                                                   0x340db8UL //Access:RW   DataWidth:0xd   The number of blocks used by the MAC port below which EMPTY[0] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46125 #define BRB_REG_BRTB_EMPTY_FOR_RDMA                                                                  0x340dbcUL //Access:RW   DataWidth:0xd   The number of blocks used by the MAC port below which EMPTY[1] is asserted for this MAC port::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46126 #define BRB_REG_PKT_CNT_THRESHOLD                                                                    0x340dc0UL //Access:RW   DataWidth:0xd   The number of packets that were read by EOP read client interface but not released by BRTB above which stop parsing interface is asserted::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46127 #define BRB_REG_BYTE_CNT_THRESHOLD                                                                   0x340dc4UL //Access:RW   DataWidth:0x14  The number of bytes that were read by EOP read client interface but not released by BRTB above which stop parsing interface is asserted::s/BLK_WDTH_PLUS_7/20/g in Data Width::s/BYTE_CNT_RST/614400/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46128 #define BRB_REG_NO_DEAD_CYCLES_EN                                                                    0x340dc8UL //Access:RW   DataWidth:0x5   There is bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will be read without dead cycles.B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
46129 #define BRB_REG_RC_PKT_PRIORITY                                                                      0x340dccUL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46130     #define BRB_REG_RC_PKT_PRIORITY_PRM_RC_PRI                                                       (0x3<<0) // This is priority for PRM  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
46131     #define BRB_REG_RC_PKT_PRIORITY_PRM_RC_PRI_SHIFT                                                 0
46132     #define BRB_REG_RC_PKT_PRIORITY_MSDM_RC_PRI                                                      (0x3<<2) // This is priority for MSDM  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
46133     #define BRB_REG_RC_PKT_PRIORITY_MSDM_RC_PRI_SHIFT                                                2
46134     #define BRB_REG_RC_PKT_PRIORITY_TSDM_RC_PRI                                                      (0x3<<4) // This is priority for TSDM  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
46135     #define BRB_REG_RC_PKT_PRIORITY_TSDM_RC_PRI_SHIFT                                                4
46136     #define BRB_REG_RC_PKT_PRIORITY_PARSER_RC_PRI                                                    (0x3<<6) // This is priority for parser  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
46137     #define BRB_REG_RC_PKT_PRIORITY_PARSER_RC_PRI_SHIFT                                              6
46138     #define BRB_REG_RC_PKT_PRIORITY_TMLD_RC_PRI                                                      (0x3<<8) // This is priority for TM loader read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 7 is highest. ::/PAUSE_EN/d in Existance.
46139     #define BRB_REG_RC_PKT_PRIORITY_TMLD_RC_PRI_SHIFT                                                8
46140 #define BRB_REG_WC_NO_DEAD_CYCLES_EN                                                                 0x340dd0UL //Access:RW   DataWidth:0x8   There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet will be written without intra packet dead cycles .B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset  Chips: K2
46141 #define BRB_REG_WC_HIGHEST_PRI_EN                                                                    0x340dd4UL //Access:RW   DataWidth:0x8   There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest priority mechanism is enabled for the corresponding client. B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser ::s/NO_DEAD_CYCLE_RST/1/g in Reset  Chips: K2
46142 #define BRB_REG_RC_SOP_PRIORITY                                                                      0x340e08UL //Access:RW   DataWidth:0x2   This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in Reset Value.  Chips: BB_A0 BB_B0 K2
46143 #define BRB_REG_RC_EOP_PRIORITY                                                                      0x340e0cUL //Access:RW   DataWidth:0x2   This is priority for EOP read client to BIG RAM arbiters. Possible values are 0-7. Priority 7 is highest::s/RC_EOP_PRI_RST/4/g in Reset Value::/EOP_RC_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46144 #define BRB_REG_WC_PRIORITY                                                                          0x340e10UL //Access:RW   DataWidth:0x2   This is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in Reset Value.  Chips: BB_A0 BB_B0 K2
46145 #define BRB_REG_PRI_OF_MULT_CLIENTS                                                                  0x340e14UL //Access:RW   DataWidth:0x2   This is priority of multiple clients with identical priority for link list arbiter. Selection from them will be done with round robin. Only one group with multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g in Reset Value.  Chips: BB_A0 BB_B0 K2
46146 #define BRB_REG_INP_FIFO_ALM_FULL                                                                    0x340e18UL //Access:RW   DataWidth:0x6   Number of entries inside input FIFO of each write client upper which full outputs to this write client interface.  Chips: BB_A0 BB_B0 K2
46147 #define BRB_REG_WC_SYNC_FIFO_ALM_FULL                                                                0x340e1cUL //Access:RW   DataWidth:0x5   Number of entries inside sync FIFO of each write client.  Chips: BB_A0 BB_B0 K2
46148 #define BRB_REG_PKT_RC_OUT_SYNC_FIFO_ALM_FULL                                                        0x340e20UL //Access:RW   DataWidth:0x5   Number of entries inside output sync FIFO of each read client.  Chips: BB_A0 BB_B0 K2
46149 #define BRB_REG_PKT_AVAIL_SYNC_FIFO_ALM_FULL                                                         0x340e24UL //Access:RW   DataWidth:0x4   Number of entries inside packet available sync FIFO.  Chips: BB_A0 BB_B0 K2
46150 #define BRB_REG_RLS_SYNC_FIFO_ALM_FULL                                                               0x340e28UL //Access:RW   DataWidth:0x4   Number of entries inside packet available sync FIFO.  Chips: BB_A0 BB_B0 K2
46151 #define BRB_REG_INP_FIFO_HIGH_THRESHOLD                                                              0x340e2cUL //Access:RW   DataWidth:0x5   Number of entries inside input FIFO of each write client upper which all arbiters selects this client with high priority.  Chips: BB_A0 BB_B0 K2
46152 #define BRB_REG_DSCR_FIFO_ALM_FULL                                                                   0x340e30UL //Access:RW   DataWidth:0x5   Number of entries inside descriptors FIFO of each write client upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.  Chips: BB_A0 BB_B0 K2
46153 #define BRB_REG_QUEUE_FIFO_ALM_FULL                                                                  0x340e34UL //Access:RW   DataWidth:0x5   Number of entries inside queue FIFO of each write client upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.  Chips: BB_A0 BB_B0 K2
46154 #define BRB_REG_DSCR_FIFO_HIGH_THRESHOLD                                                             0x340e38UL //Access:RW   DataWidth:0x5   Number of entries inside descriptors FIFO of each write client upper which all arbiters selects this client with high priority.  Chips: BB_A0 BB_B0 K2
46155 #define BRB_REG_PM_TOTAL_PKT_THRESHOLD                                                               0x340e3cUL //Access:RW   DataWidth:0xd   Number of packets above which BRB_above_threshold_mac_n is asserted to power management block::s/BLK_NUM/4800/g in Reset Value::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46156 #define BRB_REG_PM_FREE_THRESHOLD                                                                    0x340e40UL //Access:RW   DataWidth:0xd   Number of free blocks below which BRB_above_threshold_mac_n is asserted to power management block::s/BLK_WDTH/13/g in Data Width::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46157 #define BRB_REG_PM_TC_LATENCY_SENSITIVE_0                                                            0x340e44UL //Access:RW   DataWidth:0x9   Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46158 #define BRB_REG_PM_TC_LATENCY_SENSITIVE_1                                                            0x340e48UL //Access:RW   DataWidth:0x9   Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46159 #define BRB_REG_PM_TC_LATENCY_SENSITIVE_2                                                            0x340e4cUL //Access:RW   DataWidth:0x9   Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: K2
46160 #define BRB_REG_PM_TC_LATENCY_SENSITIVE_3                                                            0x340e50UL //Access:RW   DataWidth:0x9   Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: K2
46161 #define BRB_REG_DBGSYN_ALMOST_FULL_THR                                                               0x340ec4UL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: BB_A0 BB_B0 K2
46162 #define BRB_REG_DBGSYN_STATUS                                                                        0x340ec8UL //Access:R    DataWidth:0x5   Fill level of dbgmux fifo.  Chips: BB_A0 BB_B0 K2
46163 #define BRB_REG_ECO_RESERVED                                                                         0x340eccUL //Access:RW   DataWidth:0x20  This is unused register for future ECOs.  Chips: BB_A0 BB_B0 K2
46164 #define BRB_REG_DBG_SELECT                                                                           0x340ed0UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
46165 #define BRB_REG_DBG_DWORD_ENABLE                                                                     0x340ed4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
46166 #define BRB_REG_DBG_SHIFT                                                                            0x340ed8UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
46167 #define BRB_REG_DBG_FORCE_VALID                                                                      0x340edcUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46168 #define BRB_REG_DBG_FORCE_FRAME                                                                      0x340ee0UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46169 #define BRB_REG_DBG_OUT_DATA                                                                         0x340f00UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
46170 #define BRB_REG_DBG_OUT_DATA_SIZE                                                                    8
46171 #define BRB_REG_DBG_OUT_VALID                                                                        0x340f20UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
46172 #define BRB_REG_DBG_OUT_FRAME                                                                        0x340f24UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
46173 #define BRB_REG_INP_IF_ENABLE                                                                        0x340f28UL //Access:RW   DataWidth:0x19  Multi Field Register.  Chips: BB_A0 BB_B0 K2
46174     #define BRB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN                                                   (0x3ff<<0) // There is bit per each read client interface: B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/PKT_RC_NUM_MINUS_SOP_EN/4/g in Data Width::s/RC_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments.
46175     #define BRB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN_SHIFT                                             0
46176     #define BRB_REG_INP_IF_ENABLE_RC_EOP_INP_IF_EN                                                   (0xf<<10) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted.  All bits of this register should be set after init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/EOP_RC_EN/d in Existance.
46177     #define BRB_REG_INP_IF_ENABLE_RC_EOP_INP_IF_EN_SHIFT                                             10
46178     #define BRB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN                                                   (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted.  All bits of this register should be set after init procedure.
46179     #define BRB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN_SHIFT                                             14
46180     #define BRB_REG_INP_IF_ENABLE_WC_INP_IF_EN                                                       (0x3ff<<15) // There is bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/WC_IF_RST/15/g in Reset Value::s/WC_EN/B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1./g in Comments::s/WC_NUM/4/g in Data Width.
46181     #define BRB_REG_INP_IF_ENABLE_WC_INP_IF_EN_SHIFT                                                 15
46182 #define BRB_REG_OUT_IF_ENABLE                                                                        0x340f2cUL //Access:RW   DataWidth:0x1a  Multi Field Register.  Chips: BB_A0 BB_B0 K2
46183     #define BRB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN                                                   (0x3ff<<0) // There is bit per each read client interface: B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure. ::s/RC_PKT_OUT_IF_RST/31/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
46184     #define BRB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN_SHIFT                                             0
46185     #define BRB_REG_OUT_IF_ENABLE_RC_EOP_OUT_IF_EN                                                   (0xf<<10) // There is bit per each EOP read client interface: B0 - IF0, B1- IF1. When bit is set then appropriate interface is enabled.When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/EOP_RC_EN/d in Existance.
46186     #define BRB_REG_OUT_IF_ENABLE_RC_EOP_OUT_IF_EN_SHIFT                                             10
46187     #define BRB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN                                                   (0x1<<14) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted.  All bits of this register should be set after init procedure.
46188     #define BRB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN_SHIFT                                             14
46189     #define BRB_REG_OUT_IF_ENABLE_PAUSE_OUT_IF_EN                                                    (0xf<<15) // There is bit for all pause interfaces per each MAC port. When bit is set then pause interface is enabled. When bit is reset then any pause will never be set. This bit should be set after init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/PAUSE_EN/d in Existance.
46190     #define BRB_REG_OUT_IF_ENABLE_PAUSE_OUT_IF_EN_SHIFT                                              15
46191     #define BRB_REG_OUT_IF_ENABLE_EMPTY_OUT_IF_EN                                                    (0xf<<19) // There is bit for empty interfaces per each MAC port. When bit is set then empty interface is enabled. When bit is reset then empty interface will never be set. This bit should be set after init procedure. ::s/MAX_SHARE_GRP_CNT/2/g in Data Width::s/MAX_SHARE_GRP_INIT/3/g in Reset Value::/EMPTY_EN/d in Existance.
46192     #define BRB_REG_OUT_IF_ENABLE_EMPTY_OUT_IF_EN_SHIFT                                              19
46193     #define BRB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN                                            (0x1<<23) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set.  This bit should be set after init procedure.
46194     #define BRB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN_SHIFT                                      23
46195     #define BRB_REG_OUT_IF_ENABLE_STOP_PARSING_OUT_IF_EN                                             (0x1<<24) // There is bit for stop parsing interfaces. When bit is set then stop parsing interface is enabled. When bit is reset then stop parsing interface will never be set.  This bit should be set after init procedure. ::/PAUSE_EN/d in Existance.
46196     #define BRB_REG_OUT_IF_ENABLE_STOP_PARSING_OUT_IF_EN_SHIFT                                       24
46197     #define BRB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN                                                       (0x1<<25) // There is bit for power management interfaces. When bit is set then  power management interface is enabled. When bit is reset then  power management interface will never be set.  This bit should be set after init procedure. ::/EMPTY_EN/d in Existance.
46198     #define BRB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN_SHIFT                                                 25
46199 #define BRB_REG_WC_EMPTY_0                                                                           0x340f30UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
46200 #define BRB_REG_WC_EMPTY_1                                                                           0x340f34UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
46201 #define BRB_REG_WC_EMPTY_2                                                                           0x340f38UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
46202 #define BRB_REG_WC_EMPTY_3                                                                           0x340f3cUL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
46203 #define BRB_REG_WC_EMPTY_4                                                                           0x340f40UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: K2
46204 #define BRB_REG_WC_EMPTY_5                                                                           0x340f44UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: K2
46205 #define BRB_REG_WC_EMPTY_6                                                                           0x340f48UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: K2
46206 #define BRB_REG_WC_EMPTY_7                                                                           0x340f4cUL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: K2
46207 #define BRB_REG_WC_FULL_0                                                                            0x340f70UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
46208 #define BRB_REG_WC_FULL_1                                                                            0x340f74UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
46209 #define BRB_REG_WC_FULL_2                                                                            0x340f78UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
46210 #define BRB_REG_WC_FULL_3                                                                            0x340f7cUL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
46211 #define BRB_REG_WC_FULL_4                                                                            0x340f80UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: K2
46212 #define BRB_REG_WC_FULL_5                                                                            0x340f84UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: K2
46213 #define BRB_REG_WC_FULL_6                                                                            0x340f88UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: K2
46214 #define BRB_REG_WC_FULL_7                                                                            0x340f8cUL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: K2
46215 #define BRB_REG_WC_BANDWIDTH_IF_FULL                                                                 0x340fb0UL //Access:R    DataWidth:0x8   Debug register. Full status each write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.  Chips: BB_A0 BB_B0 K2
46216 #define BRB_REG_RC_PKT_IF_FULL                                                                       0x340fb4UL //Access:R    DataWidth:0x5   Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
46217 #define BRB_REG_RC_PKT_EMPTY_0                                                                       0x340fb8UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46218 #define BRB_REG_RC_PKT_EMPTY_1                                                                       0x340fbcUL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46219 #define BRB_REG_RC_PKT_EMPTY_2                                                                       0x340fc0UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46220 #define BRB_REG_RC_PKT_EMPTY_3                                                                       0x340fc4UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46221 #define BRB_REG_RC_PKT_EMPTY_4                                                                       0x340fc8UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46222 #define BRB_REG_RC_PKT_FULL_0                                                                        0x340ff4UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46223 #define BRB_REG_RC_PKT_FULL_1                                                                        0x340ff8UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46224 #define BRB_REG_RC_PKT_FULL_2                                                                        0x340ffcUL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46225 #define BRB_REG_RC_PKT_FULL_3                                                                        0x341000UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46226 #define BRB_REG_RC_PKT_FULL_4                                                                        0x341004UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46227 #define BRB_REG_RC_PKT_STATUS_0                                                                      0x341030UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46228 #define BRB_REG_RC_PKT_STATUS_1                                                                      0x341034UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46229 #define BRB_REG_RC_PKT_STATUS_2                                                                      0x341038UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46230 #define BRB_REG_RC_PKT_STATUS_3                                                                      0x34103cUL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46231 #define BRB_REG_RC_PKT_STATUS_4                                                                      0x341040UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
46232 #define BRB_REG_RC_SOP_EMPTY                                                                         0x34106cUL //Access:R    DataWidth:0x4   Debug register. Empty status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
46233 #define BRB_REG_RC_SOP_FULL                                                                          0x341070UL //Access:R    DataWidth:0x4   Debug register. Full status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
46234 #define BRB_REG_RC_SOP_STATUS                                                                        0x341074UL //Access:R    DataWidth:0x10  Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo;  B7:4-dscr_fifo;  B3:0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
46235 #define BRB_REG_RC_EOP_EMPTY                                                                         0x341078UL //Access:R    DataWidth:0x4   Debug register. Empty status of read EOP  clients: empty status of input FIFO for EOP client 0[0]; empty status of input FIFO for EOP client 1[1]::s/SHARE_GRP_CNT/2/g in Data Width::/EOP_RC_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46236 #define BRB_REG_RC_EOP_FULL                                                                          0x34107cUL //Access:R    DataWidth:0x4   Debug register. Full status of read EOP clients: full status of input FIFO for EOP client 0[0]; full status of input FIFO for EOP client 1[1]::s/SHARE_GRP_CNT/2/g in Data Width::/EOP_RC_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46237 #define BRB_REG_RC_EOP_STATUS                                                                        0x341080UL //Access:R    DataWidth:0xc   Debug register.FIFO counters status of read EOP clients: status of input FIFO for EOP client 0[2:0]; status of input FIFO for EOP client 1[6:3]::s/RC_EOP_STAT_WDTH/6/g in Data Width::/EOP_RC_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46238 #define BRB_REG_LL_ARB_EMPTY                                                                         0x341084UL //Access:R    DataWidth:0x2   Debug register. Empty status of link list arbiter: {rls_fifo; prefetch_fifo}.  Chips: BB_A0 BB_B0 K2
46239 #define BRB_REG_LL_ARB_FULL                                                                          0x341088UL //Access:R    DataWidth:0x2   Debug register. Full status of link list arbiter: {rls_fifo; prefetch_fifo}.  Chips: BB_A0 BB_B0 K2
46240 #define BRB_REG_LL_ARB_STATUS                                                                        0x34108cUL //Access:R    DataWidth:0x8   Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo[3:0]}.  Chips: BB_A0 BB_B0 K2
46241 #define BRB_REG_EMPTY_IF_0                                                                           0x341090UL //Access:R    DataWidth:0x2   Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46242 #define BRB_REG_EMPTY_IF_1                                                                           0x341094UL //Access:R    DataWidth:0x2   Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46243 #define BRB_REG_EMPTY_IF_2                                                                           0x341098UL //Access:R    DataWidth:0x2   Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: K2
46244 #define BRB_REG_EMPTY_IF_3                                                                           0x34109cUL //Access:R    DataWidth:0x2   Debug register. This is empty output IF to SEMI::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: K2
46245 #define BRB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS                                                     0x3410a8UL //Access:R    DataWidth:0x3   Debug register. This is full status of SOP SYNC FIFO for PRS client  Chips: BB_A0 BB_B0 K2
46246 #define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_0                                                       0x3410acUL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC input SYNC FIFO  Chips: BB_A0 BB_B0 K2
46247 #define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_1                                                       0x3410b0UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC input SYNC FIFO  Chips: BB_A0 BB_B0 K2
46248 #define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_2                                                       0x3410b4UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC input SYNC FIFO  Chips: BB_A0 BB_B0 K2
46249 #define BRB_REG_RC_INP_SYNC_FIFO_PUSH_STATUS_3                                                       0x3410b8UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC input SYNC FIFO  Chips: BB_A0 BB_B0 K2
46250 #define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_0                                                       0x3410e8UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
46251 #define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_1                                                       0x3410ecUL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
46252 #define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_2                                                       0x3410f0UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
46253 #define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_3                                                       0x3410f4UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
46254 #define BRB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_4                                                       0x3410f8UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
46255 #define BRB_REG_RC_EOP_INP_SYNC_FIFO_PUSH_STATUS_0                                                   0x341124UL //Access:R    DataWidth:0x3   Debug register. This is full status of EOP RC input SYNC FIFO  Chips: BB_A0 BB_B0 K2
46256 #define BRB_REG_RC_EOP_INP_SYNC_FIFO_PUSH_STATUS_1                                                   0x341128UL //Access:R    DataWidth:0x3   Debug register. This is full status of EOP RC input SYNC FIFO  Chips: BB_A0 BB_B0 K2
46257 #define BRB_REG_RC_EOP_INP_SYNC_FIFO_PUSH_STATUS_2                                                   0x34112cUL //Access:R    DataWidth:0x3   Debug register. This is full status of EOP RC input SYNC FIFO  Chips: K2
46258 #define BRB_REG_RC_EOP_INP_SYNC_FIFO_PUSH_STATUS_3                                                   0x341130UL //Access:R    DataWidth:0x3   Debug register. This is full status of EOP RC input SYNC FIFO  Chips: K2
46259 #define BRB_REG_RC_EOP_OUT_SYNC_FIFO_PUSH_STATUS_0                                                   0x341160UL //Access:R    DataWidth:0x3   Debug register. This is full status of EOP RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
46260 #define BRB_REG_RC_EOP_OUT_SYNC_FIFO_PUSH_STATUS_1                                                   0x341164UL //Access:R    DataWidth:0x3   Debug register. This is full status of EOP RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
46261 #define BRB_REG_RC_EOP_OUT_SYNC_FIFO_PUSH_STATUS_2                                                   0x341168UL //Access:R    DataWidth:0x3   Debug register. This is full status of EOP RC output SYNC FIFO  Chips: K2
46262 #define BRB_REG_RC_EOP_OUT_SYNC_FIFO_PUSH_STATUS_3                                                   0x34116cUL //Access:R    DataWidth:0x3   Debug register. This is full status of EOP RC output SYNC FIFO  Chips: K2
46263 #define BRB_REG_PKT_AVAIL_SYNC_FIFO_PUSH_STATUS                                                      0x34119cUL //Access:R    DataWidth:0x4   Debug register. This is full status of packet available SYNC FIFO  Chips: BB_A0 BB_B0 K2
46264 #define BRB_REG_STOP_PACKET_COUNTER                                                                  0x3411a0UL //Access:R    DataWidth:0xd   Debug register. This is packet counter that counts number of packets from EOP read request till release. This counter is used for stop parsing interface logic.::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46265 #define BRB_REG_STOP_BYTE_COUNTER                                                                    0x3411a4UL //Access:R    DataWidth:0x14  Debug register. This is byte counter that counts number of bytes from EOP read request till release. This counter is used for stop parsing interface logic.::s/BLK_WDTH_PLUS_7/20/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46266 #define BRB_REG_RC_PKT_STATE                                                                         0x3411a8UL //Access:R    DataWidth:0x14  Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.  Chips: BB_A0 BB_B0 K2
46267 #define BRB_REG_MAC_FREE_SHARED_HR_0                                                                 0x3411b8UL //Access:R    DataWidth:0xd   Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46268 #define BRB_REG_MAC_FREE_SHARED_HR_1                                                                 0x3411bcUL //Access:R    DataWidth:0xd   Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46269 #define BRB_REG_MAC_FREE_SHARED_HR_2                                                                 0x3411c0UL //Access:R    DataWidth:0xd   Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: K2
46270 #define BRB_REG_MAC_FREE_SHARED_HR_3                                                                 0x3411c4UL //Access:R    DataWidth:0xd   Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: K2
46271 #define BRB_REG_MAC0_TC_OCCUPANCY_0                                                                  0x3411d0UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46272 #define BRB_REG_MAC0_TC_OCCUPANCY_1                                                                  0x3411d4UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46273 #define BRB_REG_MAC0_TC_OCCUPANCY_2                                                                  0x3411d8UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46274 #define BRB_REG_MAC0_TC_OCCUPANCY_3                                                                  0x3411dcUL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46275 #define BRB_REG_MAC0_TC_OCCUPANCY_4                                                                  0x3411e0UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46276 #define BRB_REG_MAC0_TC_OCCUPANCY_5                                                                  0x3411e4UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46277 #define BRB_REG_MAC0_TC_OCCUPANCY_6                                                                  0x3411e8UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46278 #define BRB_REG_MAC0_TC_OCCUPANCY_7                                                                  0x3411ecUL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46279 #define BRB_REG_MAC0_TC_OCCUPANCY_8                                                                  0x3411f0UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46280 #define BRB_REG_MAC1_TC_OCCUPANCY_0                                                                  0x341210UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46281 #define BRB_REG_MAC1_TC_OCCUPANCY_1                                                                  0x341214UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46282 #define BRB_REG_MAC1_TC_OCCUPANCY_2                                                                  0x341218UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46283 #define BRB_REG_MAC1_TC_OCCUPANCY_3                                                                  0x34121cUL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46284 #define BRB_REG_MAC1_TC_OCCUPANCY_4                                                                  0x341220UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46285 #define BRB_REG_MAC1_TC_OCCUPANCY_5                                                                  0x341224UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46286 #define BRB_REG_MAC1_TC_OCCUPANCY_6                                                                  0x341228UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46287 #define BRB_REG_MAC1_TC_OCCUPANCY_7                                                                  0x34122cUL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46288 #define BRB_REG_MAC1_TC_OCCUPANCY_8                                                                  0x341230UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 1::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46289 #define BRB_REG_MAC2_TC_OCCUPANCY_0                                                                  0x341250UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46290 #define BRB_REG_MAC2_TC_OCCUPANCY_1                                                                  0x341254UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46291 #define BRB_REG_MAC2_TC_OCCUPANCY_2                                                                  0x341258UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46292 #define BRB_REG_MAC2_TC_OCCUPANCY_3                                                                  0x34125cUL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46293 #define BRB_REG_MAC2_TC_OCCUPANCY_4                                                                  0x341260UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 2::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46294 #define BRB_REG_MAC3_TC_OCCUPANCY_0                                                                  0x341290UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46295 #define BRB_REG_MAC3_TC_OCCUPANCY_1                                                                  0x341294UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46296 #define BRB_REG_MAC3_TC_OCCUPANCY_2                                                                  0x341298UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46297 #define BRB_REG_MAC3_TC_OCCUPANCY_3                                                                  0x34129cUL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46298 #define BRB_REG_MAC3_TC_OCCUPANCY_4                                                                  0x3412a0UL //Access:R    DataWidth:0xd   Debug register. The number of block occupied by each TC in each main port 3::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46299 #define BRB_REG_AVAILABLE_MAC_SIZE_0                                                                 0x3412d0UL //Access:R    DataWidth:0xd   Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46300 #define BRB_REG_AVAILABLE_MAC_SIZE_1                                                                 0x3412d4UL //Access:R    DataWidth:0xd   Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46301 #define BRB_REG_AVAILABLE_MAC_SIZE_2                                                                 0x3412d8UL //Access:R    DataWidth:0xd   Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: K2
46302 #define BRB_REG_AVAILABLE_MAC_SIZE_3                                                                 0x3412dcUL //Access:R    DataWidth:0xd   Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: K2
46303 #define BRB_REG_MAIN_TC_PAUSE_0                                                                      0x3412e8UL //Access:R    DataWidth:0x8   Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46304 #define BRB_REG_MAIN_TC_PAUSE_1                                                                      0x3412ecUL //Access:R    DataWidth:0x8   Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46305 #define BRB_REG_MAIN_TC_PAUSE_2                                                                      0x3412f0UL //Access:R    DataWidth:0x8   Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46306 #define BRB_REG_MAIN_TC_PAUSE_3                                                                      0x3412f4UL //Access:R    DataWidth:0x8   Debug register. Output pause signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46307 #define BRB_REG_LB_TC_PAUSE_0                                                                        0x341300UL //Access:R    DataWidth:0x9   Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46308 #define BRB_REG_LB_TC_PAUSE_1                                                                        0x341304UL //Access:R    DataWidth:0x9   Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46309 #define BRB_REG_LB_TC_PAUSE_2                                                                        0x341308UL //Access:R    DataWidth:0x9   Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46310 #define BRB_REG_LB_TC_PAUSE_3                                                                        0x34130cUL //Access:R    DataWidth:0x9   Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46311 #define BRB_REG_MAIN_TC_FULL_0                                                                       0x341318UL //Access:R    DataWidth:0x8   Debug register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46312 #define BRB_REG_MAIN_TC_FULL_1                                                                       0x34131cUL //Access:R    DataWidth:0x8   Debug register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46313 #define BRB_REG_MAIN_TC_FULL_2                                                                       0x341320UL //Access:R    DataWidth:0x8   Debug register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46314 #define BRB_REG_MAIN_TC_FULL_3                                                                       0x341324UL //Access:R    DataWidth:0x8   Debug register. Output full signal by each TC in each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46315 #define BRB_REG_LB_TC_FULL_0                                                                         0x341330UL //Access:R    DataWidth:0x9   Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46316 #define BRB_REG_LB_TC_FULL_1                                                                         0x341334UL //Access:R    DataWidth:0x9   Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46317 #define BRB_REG_LB_TC_FULL_2                                                                         0x341338UL //Access:R    DataWidth:0x9   Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46318 #define BRB_REG_LB_TC_FULL_3                                                                         0x34133cUL //Access:R    DataWidth:0x9   Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46319 #define BRB_REG_MAIN0_TC_LOSSLESS_CNT_0                                                              0x341348UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46320 #define BRB_REG_MAIN0_TC_LOSSLESS_CNT_1                                                              0x34134cUL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46321 #define BRB_REG_MAIN0_TC_LOSSLESS_CNT_2                                                              0x341350UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46322 #define BRB_REG_MAIN0_TC_LOSSLESS_CNT_3                                                              0x341354UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46323 #define BRB_REG_MAIN0_TC_LOSSLESS_CNT_4                                                              0x341358UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46324 #define BRB_REG_MAIN0_TC_LOSSLESS_CNT_5                                                              0x34135cUL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46325 #define BRB_REG_MAIN0_TC_LOSSLESS_CNT_6                                                              0x341360UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46326 #define BRB_REG_MAIN0_TC_LOSSLESS_CNT_7                                                              0x341364UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 0::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46327 #define BRB_REG_MAIN1_TC_LOSSLESS_CNT_0                                                              0x341388UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46328 #define BRB_REG_MAIN1_TC_LOSSLESS_CNT_1                                                              0x34138cUL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46329 #define BRB_REG_MAIN1_TC_LOSSLESS_CNT_2                                                              0x341390UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46330 #define BRB_REG_MAIN1_TC_LOSSLESS_CNT_3                                                              0x341394UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46331 #define BRB_REG_MAIN1_TC_LOSSLESS_CNT_4                                                              0x341398UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46332 #define BRB_REG_MAIN1_TC_LOSSLESS_CNT_5                                                              0x34139cUL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46333 #define BRB_REG_MAIN1_TC_LOSSLESS_CNT_6                                                              0x3413a0UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46334 #define BRB_REG_MAIN1_TC_LOSSLESS_CNT_7                                                              0x3413a4UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 1::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46335 #define BRB_REG_MAIN2_TC_LOSSLESS_CNT_0                                                              0x3413c8UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46336 #define BRB_REG_MAIN2_TC_LOSSLESS_CNT_1                                                              0x3413ccUL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46337 #define BRB_REG_MAIN2_TC_LOSSLESS_CNT_2                                                              0x3413d0UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46338 #define BRB_REG_MAIN2_TC_LOSSLESS_CNT_3                                                              0x3413d4UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46339 #define BRB_REG_MAIN3_TC_LOSSLESS_CNT_0                                                              0x341408UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46340 #define BRB_REG_MAIN3_TC_LOSSLESS_CNT_1                                                              0x34140cUL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46341 #define BRB_REG_MAIN3_TC_LOSSLESS_CNT_2                                                              0x341410UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46342 #define BRB_REG_MAIN3_TC_LOSSLESS_CNT_3                                                              0x341414UL //Access:R    DataWidth:0xd   Debug register. Uncomplient lossless counter for each TC of main port 2::s/COS_MAIN_NUM/8/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: K2
46343 #define BRB_REG_MAIN_TC_LOSSLESS_INT_0                                                               0x341448UL //Access:R    DataWidth:0x8   Debug register. Uncomplient lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46344 #define BRB_REG_MAIN_TC_LOSSLESS_INT_1                                                               0x34144cUL //Access:R    DataWidth:0x8   Debug register. Uncomplient lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
46345 #define BRB_REG_MAIN_TC_LOSSLESS_INT_2                                                               0x341450UL //Access:R    DataWidth:0x8   Debug register. Uncomplient lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46346 #define BRB_REG_MAIN_TC_LOSSLESS_INT_3                                                               0x341454UL //Access:R    DataWidth:0x8   Debug register. Uncomplient lossless counter interrupt for each TC of each main port::s/COS_MAIN_NUM/8/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: K2
46347 #define BRB_REG_BIG_RAM_DATA                                                                         0x341500UL //Access:WB   DataWidth:0x80  Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.  Chips: BB_A0 BB_B0 K2
46348 #define BRB_REG_BIG_RAM_DATA_SIZE                                                                    64
46349 #define BRB_REG_RC_SOP_QUEUE_STATUS                                                                  0x341600UL //Access:R    DataWidth:0x20  Debug register. There is register for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset Value::s/QUEUE_ARRAY/36/g in memory size::s/SOP_STATUS_WDTH/6/g in Address Width.  Chips: BB_A0 BB_B0 K2
46350 #define BRB_REG_RC_SOP_QUEUE_STATUS_SIZE                                                             120
46351 #define BRB_REG_STOPPED_RD_REQ                                                                       0x341800UL //Access:WB_R DataWidth:0x45  If there is length error of first block error then request from read client will be copied to this register for each erad packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelling (MSB->LSB): rest_size_error[0]; len_error[0]; 1st_error[0]; middle_error[0]; rls_to_do[9:0]; start_block[12:0]; rd_req[0]; rls_req[0]; offset[9:0]; length[13:0]; opaque[15:0]  Chips: BB_A0 BB_B0 K2
46352 #define BRB_REG_STOPPED_RD_REQ_SIZE                                                                  20
46353 #define BRB_REG_STOPPED_RLS_REQ                                                                      0x341900UL //Access:WB_R DataWidth:0x4c  If there is release error then request from read client will be copied to this register for each read packet client interface: 0-PRM; 1-MSDM ; 2-TSDM; 3-TMLD; 4-PRS. Message spelling (MSB->LSB): opaque[9:0]; rls_to_do[15:0]; queue_number[3:0]; packet_length[13:0]; rls_left[9:0]; start_block[12:0]  Chips: BB_A0 BB_B0 K2
46354 #define BRB_REG_STOPPED_RLS_REQ_SIZE                                                                 20
46355 #define BRB_REG_PER_TC_COUNTERS                                                                      0x341a00UL //Access:R    DataWidth:0x18  Per-port per-TC counters. In BigBear, entries 0-7 are port 0 (main 0) TCs 0-7. Entries 8-16 are port 1 (lb 0) TCs 0-8. Similarly for entries 17-24 for port 2 and 25-33 for port 3. In K2, entries 0-3 are port 0 TCs 0-3. Entries 4-8 are port 1 TCs 0-3, 8. Similarly for the other 6 ports.  Chips: BB_A0 BB_B0 K2
46356 #define BRB_REG_PER_TC_COUNTERS_SIZE                                                                 34
46357 #define BRB_REG_WC_STATUS_0                                                                          0x341b00UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
46358 #define BRB_REG_WC_STATUS_0_SIZE                                                                     4
46359 #define BRB_REG_WC_STATUS_1                                                                          0x341b10UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
46360 #define BRB_REG_WC_STATUS_1_SIZE                                                                     4
46361 #define BRB_REG_WC_STATUS_2                                                                          0x341b20UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
46362 #define BRB_REG_WC_STATUS_2_SIZE                                                                     4
46363 #define BRB_REG_WC_STATUS_3                                                                          0x341b30UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
46364 #define BRB_REG_WC_STATUS_3_SIZE                                                                     4
46365 #define BRB_REG_WC_STATUS_4                                                                          0x341b40UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: K2
46366 #define BRB_REG_WC_STATUS_4_SIZE                                                                     4
46367 #define BRB_REG_WC_STATUS_5                                                                          0x341b50UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: K2
46368 #define BRB_REG_WC_STATUS_5_SIZE                                                                     4
46369 #define BRB_REG_WC_STATUS_6                                                                          0x341b60UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: K2
46370 #define BRB_REG_WC_STATUS_6_SIZE                                                                     4
46371 #define BRB_REG_WC_STATUS_7                                                                          0x341b70UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: K2
46372 #define BRB_REG_WC_STATUS_7_SIZE                                                                     4
46373 #define BRB_REG_MEMCTRL_WR_RD_N                                                                      0x341c00UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
46374 #define BRB_REG_MEMCTRL_CMD                                                                          0x341c04UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
46375 #define BRB_REG_MEMCTRL_ADDRESS                                                                      0x341c08UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
46376 #define BRB_REG_MEMCTRL_STATUS                                                                       0x341c0cUL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0
46377 #define BRB_REG_LINK_LIST                                                                            0x348000UL //Access:RW   DataWidth:0xe   Link list dual port memory that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/g in Data Width::s/BLK_WDTH/13/g in Address Width.  Chips: BB_A0 BB_B0 K2
46378 #define BRB_REG_LINK_LIST_SIZE                                                                       7680
46379 #define XYLD_REG_SCBD_STRICT_PRIO                                                                    0x4c0000UL //Access:RW   DataWidth:0x4   Each bit indicates if the current queue ahs a strict prioirty; 1: The current queue has strict prority; 0: The current queue is part of the WRR scheme.  Chips: BB_A0 BB_B0 K2
46380 #define XYLD_REG_SCBD_WRR_WEIGHT_Q0                                                                  0x4c0004UL //Access:RW   DataWidth:0x2   The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.  Chips: BB_A0 BB_B0 K2
46381 #define XYLD_REG_SCBD_WRR_WEIGHT_Q1                                                                  0x4c0008UL //Access:RW   DataWidth:0x2   The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.  Chips: BB_A0 BB_B0 K2
46382 #define XYLD_REG_FOCI_FOC_CREDITS                                                                    0x4c000cUL //Access:RW   DataWidth:0x6   Initial credit of the FOC itnerface.  Chips: BB_A0 BB_B0 K2
46383 #define XYLD_REG_PCII_PXP_RD_REQ_CREDITS                                                             0x4c0010UL //Access:RW   DataWidth:0x2   Initial credit for the PCI interface::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46384 #define XYLD_REG_PCII_RD_RESP_NUM_SLOTS                                                              0x4c0014UL //Access:RW   DataWidth:0x3   Number of slots at the PCI read response buffer: 3=4/8 slots of 512 bytes;4=8/16 slots of 256 bytes;5=16/32 slots of 128 bytes;6=32/64 slots of 64 bytes; 7=64/128 slots of 32 bytes::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46385 #define XYLD_REG_BYPASS_QID                                                                          0x4c0018UL //Access:RW   DataWidth:0x2   Selects the queue to which bypass messages will be steered.  Chips: BB_A0 BB_B0 K2
46386 #define XYLD_REG_TCFC_LOAD_MINI_CACHE_EN                                                             0x4c001cUL //Access:RW   DataWidth:0x1   Allowes the TID/CID mini cache feature.  Chips: BB_A0 BB_B0 K2
46387 #define XYLD_REG_CCFC_LOAD_MINI_CACHE_EN                                                             0x4c0020UL //Access:RW   DataWidth:0x1   Allowes the TID/CID mini cache feature.  Chips: BB_A0 BB_B0 K2
46388 #define XYLD_REG_ECO_RESERVED                                                                        0x4c0024UL //Access:RW   DataWidth:0x8   Allowes future ECO's  Chips: BB_A0 BB_B0 K2
46389 #define XYLD_REG_LD_VQID                                                                             0x4c0028UL //Access:RW   DataWidth:0x5   VQID value for PXP read requests issued from all sources (PCI read BD fetches and SGE fetches).  Chips: BB_A0 BB_B0 K2
46390 #define XYLD_REG_CID_REQ_CREDITS                                                                     0x4c002cUL //Access:RW   DataWidth:0x6   Max credits value for the load cid request interface.  Chips: BB_A0 BB_B0 K2
46391 #define XYLD_REG_TID_REQ_CREDITS                                                                     0x4c0030UL //Access:RW   DataWidth:0x6   Max credits value for the load tid request interface.  Chips: BB_A0 BB_B0 K2
46392 #define XYLD_REG_LD_SEG_MSG_Q                                                                        0x4c0034UL //Access:RW   DataWidth:0x2   The QID to which the segment messages can be mapped::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46393 #define XYLD_REG_TID_REMAIN_CREDITS                                                                  0x4c0038UL //Access:R    DataWidth:0x6   Remaining credits for the tid interface  Chips: BB_A0 BB_B0 K2
46394 #define XYLD_REG_TID_MSG_STAT                                                                        0x4c003cUL //Access:RC   DataWidth:0x20  Statistics counter of TID requests  Chips: BB_A0 BB_B0 K2
46395 #define XYLD_REG_CID_REMAIN_CREDITS                                                                  0x4c0040UL //Access:R    DataWidth:0x6   Remaining credits for the cid interface  Chips: BB_A0 BB_B0 K2
46396 #define XYLD_REG_CID_MSG_STAT                                                                        0x4c0044UL //Access:RC   DataWidth:0x20  Statistics counter of CID requests  Chips: BB_A0 BB_B0 K2
46397 #define XYLD_REG_EXT_EV_1_STAT                                                                       0x4c0048UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 1  Chips: BB_A0 BB_B0 K2
46398 #define XYLD_REG_EXT_EV_2_STAT                                                                       0x4c004cUL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 2  Chips: BB_A0 BB_B0 K2
46399 #define XYLD_REG_EXT_EV_3_STAT                                                                       0x4c0050UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 3  Chips: BB_A0 BB_B0 K2
46400 #define XYLD_REG_EXT_EV_4_STAT                                                                       0x4c0054UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 0  Chips: BB_A0 BB_B0 K2
46401 #define XYLD_REG_EXT_EV_5_STAT                                                                       0x4c0058UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 0  Chips: BB_A0 BB_B0 K2
46402 #define XYLD_REG_PENDING_MSG_TO_EXT_EV_1_CTR                                                         0x4c005cUL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 1  Chips: BB_A0 BB_B0 K2
46403 #define XYLD_REG_PENDING_MSG_TO_EXT_EV_2_CTR                                                         0x4c0060UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 2  Chips: BB_A0 BB_B0 K2
46404 #define XYLD_REG_PENDING_MSG_TO_EXT_EV_3_CTR                                                         0x4c0064UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 3  Chips: BB_A0 BB_B0 K2
46405 #define XYLD_REG_PENDING_MSG_TO_EXT_EV_4_CTR                                                         0x4c0068UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 4  Chips: BB_A0 BB_B0 K2
46406 #define XYLD_REG_PENDING_MSG_TO_EXT_EV_5_CTR                                                         0x4c006cUL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 5  Chips: BB_A0 BB_B0 K2
46407 #define XYLD_REG_FOC_REMAIN_CREDITS                                                                  0x4c0070UL //Access:R    DataWidth:0x6   Remaining credits on the FOC interface  Chips: BB_A0 BB_B0 K2
46408 #define XYLD_REG_PXP_MSG_STAT                                                                        0x4c0074UL //Access:RC   DataWidth:0x20  Statistics counter of PXP requests sent  Chips: BB_A0 BB_B0 K2
46409 #define XYLD_REG_PCII_REMAIN_CREDITS                                                                 0x4c0078UL //Access:R    DataWidth:0x2   Remaining credits on the PCI interface  Chips: BB_A0 BB_B0 K2
46410 #define XYLD_REG_PCI_PENDING_MSG_CTR                                                                 0x4c007cUL //Access:R    DataWidth:0x9   Number of messages pending to PCI read request  Chips: BB_A0 BB_B0 K2
46411 #define XYLD_REG_LD_CID_MINICACHE_LOG                                                                0x4c0080UL //Access:R    DataWidth:0x20  Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set  Chips: BB_A0 BB_B0 K2
46412 #define XYLD_REG_LD_TID_MINICACHE_LOG                                                                0x4c0084UL //Access:R    DataWidth:0x20  Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set  Chips: BB_A0 BB_B0 K2
46413 #define XYLD_REG_LD_CID_MINICACHE_RESP_LOG                                                           0x4c0088UL //Access:R    DataWidth:0xe   Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_minicache_log register is valid  Chips: BB_A0 BB_B0 K2
46414 #define XYLD_REG_LD_TID_MINICACHE_RESP_LOG                                                           0x4c008cUL //Access:R    DataWidth:0xe   Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_minicache_log register is valid  Chips: BB_A0 BB_B0 K2
46415 #define XYLD_REG_LD_HDR_LOG                                                                          0x4c0090UL //Access:R    DataWidth:0x4   Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.  Chips: BB_A0 BB_B0 K2
46416 #define XYLD_REG_LD_HDR_1ST_CYC_31_0                                                                 0x4c0094UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46417 #define XYLD_REG_LD_HDR_1ST_CYC_63_32                                                                0x4c0098UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46418 #define XYLD_REG_LD_HDR_1ST_CYC_95_64                                                                0x4c009cUL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46419 #define XYLD_REG_LD_HDR_1ST_CYC_127_96                                                               0x4c00a0UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46420 #define XYLD_REG_LD_HDR_2ND_CYC_31_0                                                                 0x4c00a4UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46421 #define XYLD_REG_LD_HDR_2ND_CYC_63_32                                                                0x4c00a8UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46422 #define XYLD_REG_LD_HDR_2ND_CYC_95_64                                                                0x4c00acUL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46423 #define XYLD_REG_LD_HDR_2ND_CYC_127_96                                                               0x4c00b0UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46424 #define XYLD_REG_CM_HDR_31_0                                                                         0x4c00b4UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46425 #define XYLD_REG_CM_HDR_63_32                                                                        0x4c00b8UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46426 #define XYLD_REG_CM_HDR_95_64                                                                        0x4c00bcUL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46427 #define XYLD_REG_CM_HDR_127_96                                                                       0x4c00c0UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46428 #define XYLD_REG_LD_HDR_CLR                                                                          0x4c00c4UL //Access:W    DataWidth:0x1   Writing to this register clears hdr registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
46429 #define XYLD_REG_SEG_MSG_LOG                                                                         0x4c00c8UL //Access:R    DataWidth:0x8   Logging register for segment message error: bits 3:0 - header len; bits 7:4 - number of iteration::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46430 #define XYLD_REG_SEG_MSG_LOG_LEN_ARR_31_0                                                            0x4c00ccUL //Access:R    DataWidth:0x20  Logging register for segment message error: bits 31:0 - bits 31:0 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46431 #define XYLD_REG_SEG_MSG_LOG_LEN_ARR_63_32                                                           0x4c00d0UL //Access:R    DataWidth:0x20  Logging register for segment message error: bits 31:0 - bits 63:32 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46432 #define XYLD_REG_SEG_MSG_LOG_LEN_ARR_95_64                                                           0x4c00d4UL //Access:R    DataWidth:0x20  Logging register for segment message error: bits 31:0 - bits 95:64 of the segment message length array::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46433 #define XYLD_REG_SEG_MSG_LOG_CLR                                                                     0x4c00d8UL //Access:W    DataWidth:0x1   Writing to this register clears seg msg logging registers and enables logging new error details::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46434 #define XYLD_REG_SEG_MSG_LOG_V                                                                       0x4c00dcUL //Access:R    DataWidth:0x1   Indicates that the data at the seg_msg logging registers is valid::/MULD_DISCARD/d in MULD::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46435 #define XYLD_REG_STAT_FIC_MSG                                                                        0x4c00e0UL //Access:RC   DataWidth:0x20  Number of FIC messages sent to the loader  Chips: BB_A0 BB_B0 K2
46436 #define XYLD_REG_DBG_PENDING_CCFC_REQ                                                                0x4c00e4UL //Access:R    DataWidth:0x6   number of CCFC requests wating for responses  Chips: BB_A0 BB_B0 K2
46437 #define XYLD_REG_DBG_PENDING_TCFC_REQ                                                                0x4c00e8UL //Access:R    DataWidth:0x6   number of TCFC requests wating for responses  Chips: BB_A0 BB_B0 K2
46438 #define XYLD_REG_LEN_ERR_LOG_1                                                                       0x4c00ecUL //Access:R    DataWidth:0x10  Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.  Chips: BB_A0 BB_B0 K2
46439 #define XYLD_REG_LEN_ERR_LOG_2                                                                       0x4c00f0UL //Access:R    DataWidth:0x20  Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB  Chips: BB_A0 BB_B0 K2
46440 #define XYLD_REG_LEN_ERR_LOG_CLR                                                                     0x4c00f4UL //Access:W    DataWidth:0x1   Writing to this register clears len err logging registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
46441 #define XYLD_REG_LEN_ERR_LOG_V                                                                       0x4c00f8UL //Access:R    DataWidth:0x1   Indicates that the data at the len_err logging registers is valid.  Chips: BB_A0 BB_B0 K2
46442 #define XYLD_REG_INT_STS                                                                             0x4c0180UL //Access:R    DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46443     #define XYLD_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
46444     #define XYLD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
46445     #define XYLD_REG_INT_STS_LD_HDR_ERR                                                              (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46446     #define XYLD_REG_INT_STS_LD_HDR_ERR_SHIFT                                                        1
46447     #define XYLD_REG_INT_STS_LD_SEG_MSG_ERR                                                          (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46448     #define XYLD_REG_INT_STS_LD_SEG_MSG_ERR_SHIFT                                                    2
46449     #define XYLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR                                                   (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46450     #define XYLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT                                             3
46451     #define XYLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR                                                   (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46452     #define XYLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_SHIFT                                             4
46453     #define XYLD_REG_INT_STS_LD_LONG_MESSAGE                                                         (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46454     #define XYLD_REG_INT_STS_LD_LONG_MESSAGE_SHIFT                                                   5
46455 #define XYLD_REG_INT_MASK                                                                            0x4c0184UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46456     #define XYLD_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.ADDRESS_ERROR .
46457     #define XYLD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
46458     #define XYLD_REG_INT_MASK_LD_HDR_ERR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_HDR_ERR .
46459     #define XYLD_REG_INT_MASK_LD_HDR_ERR_SHIFT                                                       1
46460     #define XYLD_REG_INT_MASK_LD_SEG_MSG_ERR                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_SEG_MSG_ERR .
46461     #define XYLD_REG_INT_MASK_LD_SEG_MSG_ERR_SHIFT                                                   2
46462     #define XYLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
46463     #define XYLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT                                            3
46464     #define XYLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
46465     #define XYLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_SHIFT                                            4
46466     #define XYLD_REG_INT_MASK_LD_LONG_MESSAGE                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: XYLD_REG_INT_STS.LD_LONG_MESSAGE .
46467     #define XYLD_REG_INT_MASK_LD_LONG_MESSAGE_SHIFT                                                  5
46468 #define XYLD_REG_INT_STS_WR                                                                          0x4c0188UL //Access:WR   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46469     #define XYLD_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
46470     #define XYLD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
46471     #define XYLD_REG_INT_STS_WR_LD_HDR_ERR                                                           (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46472     #define XYLD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT                                                     1
46473     #define XYLD_REG_INT_STS_WR_LD_SEG_MSG_ERR                                                       (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46474     #define XYLD_REG_INT_STS_WR_LD_SEG_MSG_ERR_SHIFT                                                 2
46475     #define XYLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR                                                (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46476     #define XYLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT                                          3
46477     #define XYLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR                                                (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46478     #define XYLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_SHIFT                                          4
46479     #define XYLD_REG_INT_STS_WR_LD_LONG_MESSAGE                                                      (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46480     #define XYLD_REG_INT_STS_WR_LD_LONG_MESSAGE_SHIFT                                                5
46481 #define XYLD_REG_INT_STS_CLR                                                                         0x4c018cUL //Access:RC   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46482     #define XYLD_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
46483     #define XYLD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
46484     #define XYLD_REG_INT_STS_CLR_LD_HDR_ERR                                                          (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46485     #define XYLD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT                                                    1
46486     #define XYLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR                                                      (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46487     #define XYLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_SHIFT                                                2
46488     #define XYLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR                                               (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46489     #define XYLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT                                         3
46490     #define XYLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR                                               (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46491     #define XYLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_SHIFT                                         4
46492     #define XYLD_REG_INT_STS_CLR_LD_LONG_MESSAGE                                                     (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46493     #define XYLD_REG_INT_STS_CLR_LD_LONG_MESSAGE_SHIFT                                               5
46494 #define XYLD_REG_PRTY_MASK_H_0                                                                       0x4c0204UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46495     #define XYLD_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
46496     #define XYLD_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                         0
46497     #define XYLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
46498     #define XYLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_SHIFT                                         1
46499     #define XYLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
46500     #define XYLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           2
46501     #define XYLD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
46502     #define XYLD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           3
46503     #define XYLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
46504     #define XYLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           4
46505     #define XYLD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
46506     #define XYLD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           5
46507     #define XYLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
46508     #define XYLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           6
46509     #define XYLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
46510     #define XYLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           7
46511     #define XYLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: XYLD_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
46512     #define XYLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           8
46513 #define XYLD_REG_MEM_ECC_EVENTS                                                                      0x4c021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
46514 #define XYLD_REG_MEM001_I_MEM_DFT_K2                                                                 0x4c0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xyld.i_cid_load_req_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46515 #define XYLD_REG_MEM008_I_MEM_DFT_K2                                                                 0x4c0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xyld.i_tid_load_req_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46516 #define XYLD_REG_MEM004_I_MEM_DFT_K2                                                                 0x4c022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xyld.i_msgq_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46517 #define XYLD_REG_MEM003_I_MEM_DFT_K2                                                                 0x4c0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xyld.i_input_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46518 #define XYLD_REG_MEM006_I_MEM_DFT_K2                                                                 0x4c0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xyld.i_pci_rsep_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46519 #define XYLD_REG_MEM005_I_MEM_DFT_K2                                                                 0x4c0238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xyld.i_pci_input_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46520 #define XYLD_REG_MEM007_I_MEM_DFT_K2                                                                 0x4c023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xyld.i_seg_hdr_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46521 #define XYLD_REG_DESC_QUEUE_Q0                                                                       0x4c0400UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue0 - Debug access.  Chips: BB_A0 BB_B0 K2
46522 #define XYLD_REG_DESC_QUEUE_Q0_SIZE                                                                  48
46523 #define XYLD_REG_DESC_QUEUE_Q1                                                                       0x4c0800UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue1 - Debug access.  Chips: BB_A0 BB_B0 K2
46524 #define XYLD_REG_DESC_QUEUE_Q1_SIZE                                                                  48
46525 #define XYLD_REG_DBG_SELECT                                                                          0x4c1600UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
46526 #define XYLD_REG_DBG_DWORD_ENABLE                                                                    0x4c1604UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
46527 #define XYLD_REG_DBG_SHIFT                                                                           0x4c1608UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
46528 #define XYLD_REG_DBG_FORCE_VALID                                                                     0x4c160cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46529 #define XYLD_REG_DBG_FORCE_FRAME                                                                     0x4c1610UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46530 #define XYLD_REG_DBG_OUT_DATA                                                                        0x4c1620UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
46531 #define XYLD_REG_DBG_OUT_DATA_SIZE                                                                   8
46532 #define XYLD_REG_DBG_OUT_VALID                                                                       0x4c1640UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
46533 #define XYLD_REG_DBG_OUT_FRAME                                                                       0x4c1644UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
46534 #define XYLD_REG_FIC_INPUT_FIFO                                                                      0x4c2000UL //Access:WB   DataWidth:0x80  Access to input FIC FIFO  Chips: BB_A0 BB_B0 K2
46535 #define XYLD_REG_FIC_INPUT_FIFO_SIZE                                                                 176
46536 #define XYLD_REG_QUEUE_MSG_MEM                                                                       0x4c4000UL //Access:WB   DataWidth:0x80  Debug access to The message queue memory.  Chips: BB_A0 BB_B0 K2
46537 #define XYLD_REG_QUEUE_MSG_MEM_SIZE                                                                  2208
46538 #define YULD_REG_SCBD_STRICT_PRIO                                                                    0x4c8000UL //Access:RW   DataWidth:0x4   Each bit indicates if the current queue ahs a strict prioirty; 1: The current queue has strict prority; 0: The current queue is part of the WRR scheme.  Chips: BB_A0 BB_B0 K2
46539 #define YULD_REG_SCBD_WRR_WEIGHT_Q0                                                                  0x4c8004UL //Access:RW   DataWidth:0x2   The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.  Chips: BB_A0 BB_B0 K2
46540 #define YULD_REG_SCBD_WRR_WEIGHT_Q1                                                                  0x4c8008UL //Access:RW   DataWidth:0x2   The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.  Chips: BB_A0 BB_B0 K2
46541 #define YULD_REG_FOCI_FOC_CREDITS                                                                    0x4c800cUL //Access:RW   DataWidth:0x6   Initial credit of the FOC itnerface.  Chips: BB_A0 BB_B0 K2
46542 #define YULD_REG_BYPASS_QID                                                                          0x4c8010UL //Access:RW   DataWidth:0x2   Selects the queue to which bypass messages will be steered.  Chips: BB_A0 BB_B0 K2
46543 #define YULD_REG_TCFC_LOAD_MINI_CACHE_EN                                                             0x4c8014UL //Access:RW   DataWidth:0x1   Allowes the TID/CID mini cache feature.  Chips: BB_A0 BB_B0 K2
46544 #define YULD_REG_CCFC_LOAD_MINI_CACHE_EN                                                             0x4c8018UL //Access:RW   DataWidth:0x1   Allowes the TID/CID mini cache feature.  Chips: BB_A0 BB_B0 K2
46545 #define YULD_REG_ECO_RESERVED                                                                        0x4c801cUL //Access:RW   DataWidth:0x8   Allowes future ECO's  Chips: BB_A0 BB_B0 K2
46546 #define YULD_REG_CID_REQ_CREDITS                                                                     0x4c8020UL //Access:RW   DataWidth:0x6   Max credits value for the load cid request interface.  Chips: BB_A0 BB_B0 K2
46547 #define YULD_REG_TID_REQ_CREDITS                                                                     0x4c8024UL //Access:RW   DataWidth:0x6   Max credits value for the load tid request interface.  Chips: BB_A0 BB_B0 K2
46548 #define YULD_REG_TID_REMAIN_CREDITS                                                                  0x4c8028UL //Access:R    DataWidth:0x6   Remaining credits for the tid interface  Chips: BB_A0 BB_B0 K2
46549 #define YULD_REG_TID_MSG_STAT                                                                        0x4c802cUL //Access:RC   DataWidth:0x20  Statistics counter of TID requests  Chips: BB_A0 BB_B0 K2
46550 #define YULD_REG_CID_REMAIN_CREDITS                                                                  0x4c8030UL //Access:R    DataWidth:0x6   Remaining credits for the cid interface  Chips: BB_A0 BB_B0 K2
46551 #define YULD_REG_CID_MSG_STAT                                                                        0x4c8034UL //Access:RC   DataWidth:0x20  Statistics counter of CID requests  Chips: BB_A0 BB_B0 K2
46552 #define YULD_REG_EXT_EV_1_STAT                                                                       0x4c8038UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 1  Chips: BB_A0 BB_B0 K2
46553 #define YULD_REG_EXT_EV_2_STAT                                                                       0x4c803cUL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 2  Chips: BB_A0 BB_B0 K2
46554 #define YULD_REG_EXT_EV_3_STAT                                                                       0x4c8040UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 3  Chips: BB_A0 BB_B0 K2
46555 #define YULD_REG_EXT_EV_4_STAT                                                                       0x4c8044UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 0  Chips: BB_A0 BB_B0 K2
46556 #define YULD_REG_EXT_EV_5_STAT                                                                       0x4c8048UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 0  Chips: BB_A0 BB_B0 K2
46557 #define YULD_REG_PENDING_MSG_TO_EXT_EV_1_CTR                                                         0x4c804cUL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 1  Chips: BB_A0 BB_B0 K2
46558 #define YULD_REG_PENDING_MSG_TO_EXT_EV_2_CTR                                                         0x4c8050UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 2  Chips: BB_A0 BB_B0 K2
46559 #define YULD_REG_PENDING_MSG_TO_EXT_EV_3_CTR                                                         0x4c8054UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 3  Chips: BB_A0 BB_B0 K2
46560 #define YULD_REG_PENDING_MSG_TO_EXT_EV_4_CTR                                                         0x4c8058UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 4  Chips: BB_A0 BB_B0 K2
46561 #define YULD_REG_PENDING_MSG_TO_EXT_EV_5_CTR                                                         0x4c805cUL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 5  Chips: BB_A0 BB_B0 K2
46562 #define YULD_REG_FOC_REMAIN_CREDITS                                                                  0x4c8060UL //Access:R    DataWidth:0x6   Remaining credits on the FOC interface  Chips: BB_A0 BB_B0 K2
46563 #define YULD_REG_LD_CID_MINICACHE_LOG                                                                0x4c8064UL //Access:R    DataWidth:0x20  Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set  Chips: BB_A0 BB_B0 K2
46564 #define YULD_REG_LD_TID_MINICACHE_LOG                                                                0x4c8068UL //Access:R    DataWidth:0x20  Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set  Chips: BB_A0 BB_B0 K2
46565 #define YULD_REG_LD_CID_MINICACHE_RESP_LOG                                                           0x4c806cUL //Access:R    DataWidth:0xe   Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_minicache_log register is valid  Chips: BB_A0 BB_B0 K2
46566 #define YULD_REG_LD_TID_MINICACHE_RESP_LOG                                                           0x4c8070UL //Access:R    DataWidth:0xe   Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_minicache_log register is valid  Chips: BB_A0 BB_B0 K2
46567 #define YULD_REG_LD_HDR_LOG                                                                          0x4c8074UL //Access:R    DataWidth:0x4   Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.  Chips: BB_A0 BB_B0 K2
46568 #define YULD_REG_LD_HDR_1ST_CYC_31_0                                                                 0x4c8078UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46569 #define YULD_REG_LD_HDR_1ST_CYC_63_32                                                                0x4c807cUL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46570 #define YULD_REG_LD_HDR_1ST_CYC_95_64                                                                0x4c8080UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46571 #define YULD_REG_LD_HDR_1ST_CYC_127_96                                                               0x4c8084UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46572 #define YULD_REG_LD_HDR_2ND_CYC_31_0                                                                 0x4c8088UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46573 #define YULD_REG_LD_HDR_2ND_CYC_63_32                                                                0x4c808cUL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46574 #define YULD_REG_LD_HDR_2ND_CYC_95_64                                                                0x4c8090UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46575 #define YULD_REG_LD_HDR_2ND_CYC_127_96                                                               0x4c8094UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46576 #define YULD_REG_CM_HDR_31_0                                                                         0x4c8098UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46577 #define YULD_REG_CM_HDR_63_32                                                                        0x4c809cUL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46578 #define YULD_REG_CM_HDR_95_64                                                                        0x4c80a0UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46579 #define YULD_REG_CM_HDR_127_96                                                                       0x4c80a4UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46580 #define YULD_REG_LD_HDR_CLR                                                                          0x4c80a8UL //Access:W    DataWidth:0x1   Writing to this register clears hdr registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
46581 #define YULD_REG_STAT_FIC_MSG                                                                        0x4c80acUL //Access:RC   DataWidth:0x20  Number of FIC messages sent to the loader  Chips: BB_A0 BB_B0 K2
46582 #define YULD_REG_DBG_PENDING_CCFC_REQ                                                                0x4c80b0UL //Access:R    DataWidth:0x5   number of CCFC requests wating for responses  Chips: BB_A0 BB_B0 K2
46583 #define YULD_REG_DBG_PENDING_TCFC_REQ                                                                0x4c80b4UL //Access:R    DataWidth:0x5   number of TCFC requests wating for responses  Chips: BB_A0 BB_B0 K2
46584 #define YULD_REG_LEN_ERR_LOG_1                                                                       0x4c80b8UL //Access:R    DataWidth:0x10  Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.  Chips: BB_A0 BB_B0 K2
46585 #define YULD_REG_LEN_ERR_LOG_2                                                                       0x4c80bcUL //Access:R    DataWidth:0x20  Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB  Chips: BB_A0 BB_B0 K2
46586 #define YULD_REG_LEN_ERR_LOG_CLR                                                                     0x4c80c0UL //Access:W    DataWidth:0x1   Writing to this register clears len err logging registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
46587 #define YULD_REG_LEN_ERR_LOG_V                                                                       0x4c80c4UL //Access:R    DataWidth:0x1   Indicates that the data at the len_err logging registers is valid.  Chips: BB_A0 BB_B0 K2
46588 #define YULD_REG_INT_STS                                                                             0x4c8180UL //Access:R    DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46589     #define YULD_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
46590     #define YULD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
46591     #define YULD_REG_INT_STS_LD_HDR_ERR                                                              (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46592     #define YULD_REG_INT_STS_LD_HDR_ERR_SHIFT                                                        1
46593     #define YULD_REG_INT_STS_LD_SEG_MSG_ERR                                                          (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46594     #define YULD_REG_INT_STS_LD_SEG_MSG_ERR_SHIFT                                                    2
46595     #define YULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR                                                   (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46596     #define YULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT                                             3
46597     #define YULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR                                                   (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46598     #define YULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_SHIFT                                             4
46599     #define YULD_REG_INT_STS_LD_LONG_MESSAGE                                                         (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46600     #define YULD_REG_INT_STS_LD_LONG_MESSAGE_SHIFT                                                   5
46601 #define YULD_REG_INT_MASK                                                                            0x4c8184UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46602     #define YULD_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.ADDRESS_ERROR .
46603     #define YULD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
46604     #define YULD_REG_INT_MASK_LD_HDR_ERR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_HDR_ERR .
46605     #define YULD_REG_INT_MASK_LD_HDR_ERR_SHIFT                                                       1
46606     #define YULD_REG_INT_MASK_LD_SEG_MSG_ERR                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_SEG_MSG_ERR .
46607     #define YULD_REG_INT_MASK_LD_SEG_MSG_ERR_SHIFT                                                   2
46608     #define YULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
46609     #define YULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT                                            3
46610     #define YULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
46611     #define YULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_SHIFT                                            4
46612     #define YULD_REG_INT_MASK_LD_LONG_MESSAGE                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: YULD_REG_INT_STS.LD_LONG_MESSAGE .
46613     #define YULD_REG_INT_MASK_LD_LONG_MESSAGE_SHIFT                                                  5
46614 #define YULD_REG_INT_STS_WR                                                                          0x4c8188UL //Access:WR   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46615     #define YULD_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
46616     #define YULD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
46617     #define YULD_REG_INT_STS_WR_LD_HDR_ERR                                                           (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46618     #define YULD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT                                                     1
46619     #define YULD_REG_INT_STS_WR_LD_SEG_MSG_ERR                                                       (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46620     #define YULD_REG_INT_STS_WR_LD_SEG_MSG_ERR_SHIFT                                                 2
46621     #define YULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR                                                (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46622     #define YULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT                                          3
46623     #define YULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR                                                (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46624     #define YULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_SHIFT                                          4
46625     #define YULD_REG_INT_STS_WR_LD_LONG_MESSAGE                                                      (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46626     #define YULD_REG_INT_STS_WR_LD_LONG_MESSAGE_SHIFT                                                5
46627 #define YULD_REG_INT_STS_CLR                                                                         0x4c818cUL //Access:RC   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46628     #define YULD_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
46629     #define YULD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
46630     #define YULD_REG_INT_STS_CLR_LD_HDR_ERR                                                          (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46631     #define YULD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT                                                    1
46632     #define YULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR                                                      (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46633     #define YULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_SHIFT                                                2
46634     #define YULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR                                               (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46635     #define YULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT                                         3
46636     #define YULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR                                               (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46637     #define YULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_SHIFT                                         4
46638     #define YULD_REG_INT_STS_CLR_LD_LONG_MESSAGE                                                     (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46639     #define YULD_REG_INT_STS_CLR_LD_LONG_MESSAGE_SHIFT                                               5
46640 #define YULD_REG_PRTY_MASK_H_0                                                                       0x4c8204UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46641     #define YULD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
46642     #define YULD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           0
46643     #define YULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
46644     #define YULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           1
46645     #define YULD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
46646     #define YULD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           2
46647     #define YULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
46648     #define YULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           3
46649     #define YULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
46650     #define YULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           4
46651     #define YULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: YULD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
46652     #define YULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           5
46653 #define YULD_REG_MEM_ECC_EVENTS                                                                      0x4c8210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
46654 #define YULD_REG_MEM001_I_MEM_DFT_K2                                                                 0x4c8218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance yuld.i_cid_load_req_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46655 #define YULD_REG_MEM005_I_MEM_DFT_K2                                                                 0x4c821cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance yuld.i_tid_load_req_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46656 #define YULD_REG_MEM004_I_MEM_DFT_K2                                                                 0x4c8220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance yuld.i_msgq_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46657 #define YULD_REG_MEM003_I_MEM_DFT_K2                                                                 0x4c8224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance yuld.i_input_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46658 #define YULD_REG_DESC_QUEUE_Q0                                                                       0x4c8400UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue0 - Debug access.  Chips: BB_A0 BB_B0 K2
46659 #define YULD_REG_DESC_QUEUE_Q0_SIZE                                                                  32
46660 #define YULD_REG_DESC_QUEUE_Q1                                                                       0x4c8800UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue1 - Debug access.  Chips: BB_A0 BB_B0 K2
46661 #define YULD_REG_DESC_QUEUE_Q1_SIZE                                                                  32
46662 #define YULD_REG_DBG_SELECT                                                                          0x4c9600UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
46663 #define YULD_REG_DBG_DWORD_ENABLE                                                                    0x4c9604UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
46664 #define YULD_REG_DBG_SHIFT                                                                           0x4c9608UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
46665 #define YULD_REG_DBG_FORCE_VALID                                                                     0x4c960cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46666 #define YULD_REG_DBG_FORCE_FRAME                                                                     0x4c9610UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46667 #define YULD_REG_DBG_OUT_DATA                                                                        0x4c9620UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
46668 #define YULD_REG_DBG_OUT_DATA_SIZE                                                                   8
46669 #define YULD_REG_DBG_OUT_VALID                                                                       0x4c9640UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
46670 #define YULD_REG_DBG_OUT_FRAME                                                                       0x4c9644UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
46671 #define YULD_REG_FIC_INPUT_FIFO                                                                      0x4ca000UL //Access:WB   DataWidth:0x80  Access to input FIC FIFO  Chips: BB_A0 BB_B0 K2
46672 #define YULD_REG_FIC_INPUT_FIFO_SIZE                                                                 176
46673 #define YULD_REG_QUEUE_MSG_MEM                                                                       0x4cc000UL //Access:WB   DataWidth:0x80  Debug access to The message queue memory.  Chips: BB_A0 BB_B0 K2
46674 #define YULD_REG_QUEUE_MSG_MEM_SIZE                                                                  256
46675 #define TMLD_REG_SCBD_STRICT_PRIO                                                                    0x4d0000UL //Access:RW   DataWidth:0x4   Each bit indicates if the current queue ahs a strict prioirty; 1: The current queue has strict prority; 0: The current queue is part of the WRR scheme.  Chips: BB_A0 BB_B0 K2
46676 #define TMLD_REG_SCBD_WRR_WEIGHT_Q0                                                                  0x4d0004UL //Access:RW   DataWidth:0x2   The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.  Chips: BB_A0 BB_B0 K2
46677 #define TMLD_REG_SCBD_WRR_WEIGHT_Q1                                                                  0x4d0008UL //Access:RW   DataWidth:0x2   The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.  Chips: BB_A0 BB_B0 K2
46678 #define TMLD_REG_FOCI_FOC_CREDITS                                                                    0x4d000cUL //Access:RW   DataWidth:0x6   Initial credit of the FOC itnerface.  Chips: BB_A0 BB_B0 K2
46679 #define TMLD_REG_BYPASS_QID                                                                          0x4d0010UL //Access:RW   DataWidth:0x2   Selects the queue to which bypass messages will be steered.  Chips: BB_A0 BB_B0 K2
46680 #define TMLD_REG_TCFC_LOAD_MINI_CACHE_EN                                                             0x4d0014UL //Access:RW   DataWidth:0x1   Allowes the TID/CID mini cache feature.  Chips: BB_A0 BB_B0 K2
46681 #define TMLD_REG_CCFC_LOAD_MINI_CACHE_EN                                                             0x4d0018UL //Access:RW   DataWidth:0x1   Allowes the TID/CID mini cache feature.  Chips: BB_A0 BB_B0 K2
46682 #define TMLD_REG_ECO_RESERVED                                                                        0x4d001cUL //Access:RW   DataWidth:0x8   Allowes future ECO's  Chips: BB_A0 BB_B0 K2
46683 #define TMLD_REG_BRB_RD_RESP_NUM_SLOTS                                                               0x4d0020UL //Access:RW   DataWidth:0x3   Log2 of number of slots at the BRB read response buffer. The slot size would be the BRB-response-buffer-size/number-of-slots.::/MULD_DISCARD/d in MULD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46684 #define TMLD_REG_CID_REQ_CREDITS                                                                     0x4d0024UL //Access:RW   DataWidth:0x6   Max credits value for the load cid request interface.  Chips: BB_A0 BB_B0 K2
46685 #define TMLD_REG_TID_REQ_CREDITS                                                                     0x4d0028UL //Access:RW   DataWidth:0x6   Max credits value for the load tid request interface.  Chips: BB_A0 BB_B0 K2
46686 #define TMLD_REG_BRB_SWAP_EN                                                                         0x4d002cUL //Access:RW   DataWidth:0x1   When set the data returning from the BRB is swapped.    meaning that bytes 0-3 is swapped with bytes 4-7 in    each 64b boundary  Chips: BB_A0 BB_B0 K2
46687 #define TMLD_REG_BRB_MAX_CREDITS                                                                     0x4d0030UL //Access:RW   DataWidth:0x3   Max credit number for the BRB request-resonse interface::/MULD_DISCARD/d in MULD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46688 #define TMLD_REG_TID_REMAIN_CREDITS                                                                  0x4d0034UL //Access:R    DataWidth:0x6   Remaining credits for the tid interface  Chips: BB_A0 BB_B0 K2
46689 #define TMLD_REG_TID_MSG_STAT                                                                        0x4d0038UL //Access:RC   DataWidth:0x20  Statistics counter of TID requests  Chips: BB_A0 BB_B0 K2
46690 #define TMLD_REG_CID_REMAIN_CREDITS                                                                  0x4d003cUL //Access:R    DataWidth:0x6   Remaining credits for the cid interface  Chips: BB_A0 BB_B0 K2
46691 #define TMLD_REG_CID_MSG_STAT                                                                        0x4d0040UL //Access:RC   DataWidth:0x20  Statistics counter of CID requests  Chips: BB_A0 BB_B0 K2
46692 #define TMLD_REG_EXT_EV_1_STAT                                                                       0x4d0044UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 1  Chips: BB_A0 BB_B0 K2
46693 #define TMLD_REG_EXT_EV_2_STAT                                                                       0x4d0048UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 2  Chips: BB_A0 BB_B0 K2
46694 #define TMLD_REG_EXT_EV_3_STAT                                                                       0x4d004cUL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 3  Chips: BB_A0 BB_B0 K2
46695 #define TMLD_REG_EXT_EV_4_STAT                                                                       0x4d0050UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 0  Chips: BB_A0 BB_B0 K2
46696 #define TMLD_REG_EXT_EV_5_STAT                                                                       0x4d0054UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 0  Chips: BB_A0 BB_B0 K2
46697 #define TMLD_REG_PENDING_MSG_TO_EXT_EV_1_CTR                                                         0x4d0058UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 1  Chips: BB_A0 BB_B0 K2
46698 #define TMLD_REG_PENDING_MSG_TO_EXT_EV_2_CTR                                                         0x4d005cUL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 2  Chips: BB_A0 BB_B0 K2
46699 #define TMLD_REG_PENDING_MSG_TO_EXT_EV_3_CTR                                                         0x4d0060UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 3  Chips: BB_A0 BB_B0 K2
46700 #define TMLD_REG_PENDING_MSG_TO_EXT_EV_4_CTR                                                         0x4d0064UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 4  Chips: BB_A0 BB_B0 K2
46701 #define TMLD_REG_PENDING_MSG_TO_EXT_EV_5_CTR                                                         0x4d0068UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 5  Chips: BB_A0 BB_B0 K2
46702 #define TMLD_REG_FOC_REMAIN_CREDITS                                                                  0x4d006cUL //Access:R    DataWidth:0x6   Remaining credits on the FOC interface  Chips: BB_A0 BB_B0 K2
46703 #define TMLD_REG_STAT_BRB_REQ                                                                        0x4d0070UL //Access:RC   DataWidth:0x20  Counts the number of BRB requests sent  Chips: BB_A0 BB_B0 K2
46704 #define TMLD_REG_BRB_REMAINING_CRED                                                                  0x4d0074UL //Access:R    DataWidth:0x3   Number of remaining credits on the BRB interface  Chips: BB_A0 BB_B0 K2
46705 #define TMLD_REG_LD_CID_MINICACHE_LOG                                                                0x4d0078UL //Access:R    DataWidth:0x20  Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set  Chips: BB_A0 BB_B0 K2
46706 #define TMLD_REG_LD_TID_MINICACHE_LOG                                                                0x4d007cUL //Access:R    DataWidth:0x20  Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set  Chips: BB_A0 BB_B0 K2
46707 #define TMLD_REG_LD_CID_MINICACHE_RESP_LOG                                                           0x4d0080UL //Access:R    DataWidth:0xe   Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_minicache_log register is valid  Chips: BB_A0 BB_B0 K2
46708 #define TMLD_REG_LD_TID_MINICACHE_RESP_LOG                                                           0x4d0084UL //Access:R    DataWidth:0xe   Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_minicache_log register is valid  Chips: BB_A0 BB_B0 K2
46709 #define TMLD_REG_LD_HDR_LOG                                                                          0x4d0088UL //Access:R    DataWidth:0x4   Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.  Chips: BB_A0 BB_B0 K2
46710 #define TMLD_REG_LD_HDR_1ST_CYC_31_0                                                                 0x4d008cUL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46711 #define TMLD_REG_LD_HDR_1ST_CYC_63_32                                                                0x4d0090UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46712 #define TMLD_REG_LD_HDR_1ST_CYC_95_64                                                                0x4d0094UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46713 #define TMLD_REG_LD_HDR_1ST_CYC_127_96                                                               0x4d0098UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46714 #define TMLD_REG_LD_HDR_2ND_CYC_31_0                                                                 0x4d009cUL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46715 #define TMLD_REG_LD_HDR_2ND_CYC_63_32                                                                0x4d00a0UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46716 #define TMLD_REG_LD_HDR_2ND_CYC_95_64                                                                0x4d00a4UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46717 #define TMLD_REG_LD_HDR_2ND_CYC_127_96                                                               0x4d00a8UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46718 #define TMLD_REG_CM_HDR_31_0                                                                         0x4d00acUL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46719 #define TMLD_REG_CM_HDR_63_32                                                                        0x4d00b0UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46720 #define TMLD_REG_CM_HDR_95_64                                                                        0x4d00b4UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46721 #define TMLD_REG_CM_HDR_127_96                                                                       0x4d00b8UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46722 #define TMLD_REG_LD_HDR_CLR                                                                          0x4d00bcUL //Access:W    DataWidth:0x1   Writing to this register clears hdr registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
46723 #define TMLD_REG_STAT_FIC_MSG                                                                        0x4d00c0UL //Access:RC   DataWidth:0x20  Number of FIC messages sent to the loader  Chips: BB_A0 BB_B0 K2
46724 #define TMLD_REG_DBG_PENDING_CCFC_REQ                                                                0x4d00c4UL //Access:R    DataWidth:0x6   number of CCFC requests wating for responses  Chips: BB_A0 BB_B0 K2
46725 #define TMLD_REG_DBG_PENDING_TCFC_REQ                                                                0x4d00c8UL //Access:R    DataWidth:0x6   number of TCFC requests wating for responses  Chips: BB_A0 BB_B0 K2
46726 #define TMLD_REG_LEN_ERR_LOG_1                                                                       0x4d00ccUL //Access:R    DataWidth:0x10  Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.  Chips: BB_A0 BB_B0 K2
46727 #define TMLD_REG_LEN_ERR_LOG_2                                                                       0x4d00d0UL //Access:R    DataWidth:0x20  Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB  Chips: BB_A0 BB_B0 K2
46728 #define TMLD_REG_LEN_ERR_LOG_CLR                                                                     0x4d00d4UL //Access:W    DataWidth:0x1   Writing to this register clears len err logging registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
46729 #define TMLD_REG_LEN_ERR_LOG_V                                                                       0x4d00d8UL //Access:R    DataWidth:0x1   Indicates that the data at the len_err logging registers is valid.  Chips: BB_A0 BB_B0 K2
46730 #define TMLD_REG_INT_STS                                                                             0x4d0180UL //Access:R    DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46731     #define TMLD_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
46732     #define TMLD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
46733     #define TMLD_REG_INT_STS_LD_HDR_ERR                                                              (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46734     #define TMLD_REG_INT_STS_LD_HDR_ERR_SHIFT                                                        1
46735     #define TMLD_REG_INT_STS_LD_SEG_MSG_ERR                                                          (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46736     #define TMLD_REG_INT_STS_LD_SEG_MSG_ERR_SHIFT                                                    2
46737     #define TMLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR                                                   (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46738     #define TMLD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT                                             3
46739     #define TMLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR                                                   (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46740     #define TMLD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_SHIFT                                             4
46741     #define TMLD_REG_INT_STS_LD_LONG_MESSAGE                                                         (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46742     #define TMLD_REG_INT_STS_LD_LONG_MESSAGE_SHIFT                                                   5
46743 #define TMLD_REG_INT_MASK                                                                            0x4d0184UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46744     #define TMLD_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.ADDRESS_ERROR .
46745     #define TMLD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
46746     #define TMLD_REG_INT_MASK_LD_HDR_ERR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_HDR_ERR .
46747     #define TMLD_REG_INT_MASK_LD_HDR_ERR_SHIFT                                                       1
46748     #define TMLD_REG_INT_MASK_LD_SEG_MSG_ERR                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_SEG_MSG_ERR .
46749     #define TMLD_REG_INT_MASK_LD_SEG_MSG_ERR_SHIFT                                                   2
46750     #define TMLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
46751     #define TMLD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT                                            3
46752     #define TMLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
46753     #define TMLD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_SHIFT                                            4
46754     #define TMLD_REG_INT_MASK_LD_LONG_MESSAGE                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: TMLD_REG_INT_STS.LD_LONG_MESSAGE .
46755     #define TMLD_REG_INT_MASK_LD_LONG_MESSAGE_SHIFT                                                  5
46756 #define TMLD_REG_INT_STS_WR                                                                          0x4d0188UL //Access:WR   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46757     #define TMLD_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
46758     #define TMLD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
46759     #define TMLD_REG_INT_STS_WR_LD_HDR_ERR                                                           (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46760     #define TMLD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT                                                     1
46761     #define TMLD_REG_INT_STS_WR_LD_SEG_MSG_ERR                                                       (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46762     #define TMLD_REG_INT_STS_WR_LD_SEG_MSG_ERR_SHIFT                                                 2
46763     #define TMLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR                                                (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46764     #define TMLD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT                                          3
46765     #define TMLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR                                                (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46766     #define TMLD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_SHIFT                                          4
46767     #define TMLD_REG_INT_STS_WR_LD_LONG_MESSAGE                                                      (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46768     #define TMLD_REG_INT_STS_WR_LD_LONG_MESSAGE_SHIFT                                                5
46769 #define TMLD_REG_INT_STS_CLR                                                                         0x4d018cUL //Access:RC   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46770     #define TMLD_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
46771     #define TMLD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
46772     #define TMLD_REG_INT_STS_CLR_LD_HDR_ERR                                                          (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46773     #define TMLD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT                                                    1
46774     #define TMLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR                                                      (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46775     #define TMLD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_SHIFT                                                2
46776     #define TMLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR                                               (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46777     #define TMLD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT                                         3
46778     #define TMLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR                                               (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46779     #define TMLD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_SHIFT                                         4
46780     #define TMLD_REG_INT_STS_CLR_LD_LONG_MESSAGE                                                     (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46781     #define TMLD_REG_INT_STS_CLR_LD_LONG_MESSAGE_SHIFT                                               5
46782 #define TMLD_REG_PRTY_MASK_H_0                                                                       0x4d0204UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46783     #define TMLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
46784     #define TMLD_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_SHIFT                                         0
46785     #define TMLD_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
46786     #define TMLD_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT                                         1
46787     #define TMLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
46788     #define TMLD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           2
46789     #define TMLD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
46790     #define TMLD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           3
46791     #define TMLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
46792     #define TMLD_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           4
46793     #define TMLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
46794     #define TMLD_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           5
46795     #define TMLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
46796     #define TMLD_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           6
46797     #define TMLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: TMLD_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
46798     #define TMLD_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           7
46799 #define TMLD_REG_MEM_ECC_EVENTS                                                                      0x4d021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
46800 #define TMLD_REG_MEM003_I_MEM_DFT_K2                                                                 0x4d0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tmld.i_cid_load_req_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46801 #define TMLD_REG_MEM007_I_MEM_DFT_K2                                                                 0x4d0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tmld.i_tid_load_req_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46802 #define TMLD_REG_MEM006_I_MEM_DFT_K2                                                                 0x4d022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tmld.i_msgq_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46803 #define TMLD_REG_MEM005_I_MEM_DFT_K2                                                                 0x4d0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tmld.i_input_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46804 #define TMLD_REG_MEM001_I_MEM_DFT_K2                                                                 0x4d0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tmld.i_brb_input_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46805 #define TMLD_REG_MEM002_I_MEM_DFT_K2                                                                 0x4d0238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tmld.i_brb_resp_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46806 #define TMLD_REG_DESC_QUEUE_Q0                                                                       0x4d0400UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue0 - Debug access.  Chips: BB_A0 BB_B0 K2
46807 #define TMLD_REG_DESC_QUEUE_Q0_SIZE                                                                  64
46808 #define TMLD_REG_DESC_QUEUE_Q1                                                                       0x4d0800UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue1 - Debug access.  Chips: BB_A0 BB_B0 K2
46809 #define TMLD_REG_DESC_QUEUE_Q1_SIZE                                                                  64
46810 #define TMLD_REG_DBG_SELECT                                                                          0x4d1600UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
46811 #define TMLD_REG_DBG_DWORD_ENABLE                                                                    0x4d1604UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
46812 #define TMLD_REG_DBG_SHIFT                                                                           0x4d1608UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
46813 #define TMLD_REG_DBG_FORCE_VALID                                                                     0x4d160cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46814 #define TMLD_REG_DBG_FORCE_FRAME                                                                     0x4d1610UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46815 #define TMLD_REG_DBG_OUT_DATA                                                                        0x4d1620UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
46816 #define TMLD_REG_DBG_OUT_DATA_SIZE                                                                   8
46817 #define TMLD_REG_DBG_OUT_VALID                                                                       0x4d1640UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
46818 #define TMLD_REG_DBG_OUT_FRAME                                                                       0x4d1644UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
46819 #define TMLD_REG_FIC_INPUT_FIFO                                                                      0x4d2000UL //Access:WB   DataWidth:0x80  Access to input FIC FIFO  Chips: BB_A0 BB_B0 K2
46820 #define TMLD_REG_FIC_INPUT_FIFO_SIZE                                                                 176
46821 #define TMLD_REG_QUEUE_MSG_MEM                                                                       0x4d4000UL //Access:WB   DataWidth:0x80  Debug access to The message queue memory.  Chips: BB_A0 BB_B0 K2
46822 #define TMLD_REG_QUEUE_MSG_MEM_SIZE                                                                  3200
46823 #define MULD_REG_SCBD_STRICT_PRIO                                                                    0x4e0000UL //Access:RW   DataWidth:0x4   Each bit indicates if the current queue ahs a strict prioirty; 1: The current queue has strict prority; 0: The current queue is part of the WRR scheme.  Chips: BB_A0 BB_B0 K2
46824 #define MULD_REG_SCBD_WRR_WEIGHT_Q0                                                                  0x4e0004UL //Access:RW   DataWidth:0x2   The weight of queue 0 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.  Chips: BB_A0 BB_B0 K2
46825 #define MULD_REG_SCBD_WRR_WEIGHT_Q1                                                                  0x4e0008UL //Access:RW   DataWidth:0x2   The weight of queue 1 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg.  Chips: BB_A0 BB_B0 K2
46826 #define MULD_REG_SCBD_WRR_WEIGHT_Q2                                                                  0x4e000cUL //Access:RW   DataWidth:0x2   The weight of queue 2 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46827 #define MULD_REG_SCBD_WRR_WEIGHT_Q3                                                                  0x4e0010UL //Access:RW   DataWidth:0x2   The weight of queue 3 at the WRR arbiteration, in case its bit is reset at scbd_strict_prio reg::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46828 #define MULD_REG_BD_SIZE                                                                             0x4e0014UL //Access:RW   DataWidth:0x4   Log 2 of the BD size in bytes - 2:BD size is 4bytes; 3:BD size is 8bytes; 4:BD size is 16bytes etc::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46829 #define MULD_REG_BD_NEXT_ADDR_OFST                                                                   0x4e0018UL //Access:RW   DataWidth:0x10  Ofset within a given page of the next page's address (in bytes)::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46830 #define MULD_REG_SGE_SIZE                                                                            0x4e001cUL //Access:RW   DataWidth:0x4   Log 2 of the SGE size in bytes - 2:SGE size is 4bytes; 3:SGE size is 8bytes; 4:SGE size is 16bytes etc::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46831 #define MULD_REG_SGE_NEXT_ADDR_OFST                                                                  0x4e0020UL //Access:RW   DataWidth:0x10  Ofset within a given page of the next page's address (in bytes)::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46832 #define MULD_REG_FOCI_FOC_CREDITS                                                                    0x4e0024UL //Access:RW   DataWidth:0x6   Initial credit of the FOC itnerface.  Chips: BB_A0 BB_B0 K2
46833 #define MULD_REG_PCII_PXP_RD_REQ_CREDITS                                                             0x4e0028UL //Access:RW   DataWidth:0x2   Initial credit for the PCI interface::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46834 #define MULD_REG_PCII_RD_RESP_NUM_SLOTS                                                              0x4e002cUL //Access:RW   DataWidth:0x3   Number of slots at the PCI read response buffer: 3=4/8 slots of 512 bytes;4=8/16 slots of 256 bytes;5=16/32 slots of 128 bytes;6=32/64 slots of 64 bytes; 7=64/128 slots of 32 bytes::/TMLD_DISCARD/d in TMLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46835 #define MULD_REG_BYPASS_QID                                                                          0x4e0030UL //Access:RW   DataWidth:0x2   Selects the queue to which bypass messages will be steered.  Chips: BB_A0 BB_B0 K2
46836 #define MULD_REG_TCFC_LOAD_MINI_CACHE_EN                                                             0x4e0034UL //Access:RW   DataWidth:0x1   Allowes the TID/CID mini cache feature.  Chips: BB_A0 BB_B0 K2
46837 #define MULD_REG_CCFC_LOAD_MINI_CACHE_EN                                                             0x4e0038UL //Access:RW   DataWidth:0x1   Allowes the TID/CID mini cache feature.  Chips: BB_A0 BB_B0 K2
46838 #define MULD_REG_ECO_RESERVED                                                                        0x4e003cUL //Access:RW   DataWidth:0x8   Allowes future ECO's  Chips: BB_A0 BB_B0 K2
46839 #define MULD_REG_LD_VQID                                                                             0x4e0040UL //Access:RW   DataWidth:0x5   VQID value for PXP read requests issued from all sources (PCI read BD fetches and SGE fetches).  Chips: BB_A0 BB_B0 K2
46840 #define MULD_REG_CID_REQ_CREDITS                                                                     0x4e0044UL //Access:RW   DataWidth:0x6   Max credits value for the load cid request interface.  Chips: BB_A0 BB_B0 K2
46841 #define MULD_REG_TID_REQ_CREDITS                                                                     0x4e0048UL //Access:RW   DataWidth:0x6   Max credits value for the load tid request interface.  Chips: BB_A0 BB_B0 K2
46842 #define MULD_REG_TID_REMAIN_CREDITS                                                                  0x4e004cUL //Access:R    DataWidth:0x6   Remaining credits for the tid interface  Chips: BB_A0 BB_B0 K2
46843 #define MULD_REG_TID_MSG_STAT                                                                        0x4e0050UL //Access:RC   DataWidth:0x20  Statistics counter of TID requests  Chips: BB_A0 BB_B0 K2
46844 #define MULD_REG_CID_REMAIN_CREDITS                                                                  0x4e0054UL //Access:R    DataWidth:0x6   Remaining credits for the cid interface  Chips: BB_A0 BB_B0 K2
46845 #define MULD_REG_CID_MSG_STAT                                                                        0x4e0058UL //Access:RC   DataWidth:0x20  Statistics counter of CID requests  Chips: BB_A0 BB_B0 K2
46846 #define MULD_REG_EXT_EV_1_STAT                                                                       0x4e005cUL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 1  Chips: BB_A0 BB_B0 K2
46847 #define MULD_REG_EXT_EV_2_STAT                                                                       0x4e0060UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 2  Chips: BB_A0 BB_B0 K2
46848 #define MULD_REG_EXT_EV_3_STAT                                                                       0x4e0064UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 3  Chips: BB_A0 BB_B0 K2
46849 #define MULD_REG_EXT_EV_4_STAT                                                                       0x4e0068UL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 0  Chips: BB_A0 BB_B0 K2
46850 #define MULD_REG_EXT_EV_5_STAT                                                                       0x4e006cUL //Access:RC   DataWidth:0x20  Statistics counter of message pending to external event 0  Chips: BB_A0 BB_B0 K2
46851 #define MULD_REG_PENDING_MSG_TO_EXT_EV_1_CTR                                                         0x4e0070UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 1  Chips: BB_A0 BB_B0 K2
46852 #define MULD_REG_PENDING_MSG_TO_EXT_EV_2_CTR                                                         0x4e0074UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 2  Chips: BB_A0 BB_B0 K2
46853 #define MULD_REG_PENDING_MSG_TO_EXT_EV_3_CTR                                                         0x4e0078UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 3  Chips: BB_A0 BB_B0 K2
46854 #define MULD_REG_PENDING_MSG_TO_EXT_EV_4_CTR                                                         0x4e007cUL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 4  Chips: BB_A0 BB_B0 K2
46855 #define MULD_REG_PENDING_MSG_TO_EXT_EV_5_CTR                                                         0x4e0080UL //Access:R    DataWidth:0x9   Counts the number of messages currently pending to external event 5  Chips: BB_A0 BB_B0 K2
46856 #define MULD_REG_FOC_REMAIN_CREDITS                                                                  0x4e0084UL //Access:R    DataWidth:0x6   Remaining credits on the FOC interface  Chips: BB_A0 BB_B0 K2
46857 #define MULD_REG_BD_PENDING_MSG_CTR                                                                  0x4e0088UL //Access:R    DataWidth:0x9   Number of messages pending to BD fetch  Chips: BB_A0 BB_B0 K2
46858 #define MULD_REG_SGE_PENDING_MSG_CTR                                                                 0x4e008cUL //Access:R    DataWidth:0x9   Number of messages pending to SGE fetch  Chips: BB_A0 BB_B0 K2
46859 #define MULD_REG_PXP_MSG_STAT                                                                        0x4e0090UL //Access:RC   DataWidth:0x20  Statistics counter of PXP requests sent  Chips: BB_A0 BB_B0 K2
46860 #define MULD_REG_PCII_REMAIN_CREDITS                                                                 0x4e0094UL //Access:R    DataWidth:0x2   Remaining credits on the PCI interface  Chips: BB_A0 BB_B0 K2
46861 #define MULD_REG_PCI_PENDING_MSG_CTR                                                                 0x4e0098UL //Access:R    DataWidth:0x9   Number of messages pending to PCI read request  Chips: BB_A0 BB_B0 K2
46862 #define MULD_REG_LD_CID_MINICACHE_LOG                                                                0x4e009cUL //Access:R    DataWidth:0x20  Logging in case of minicache failure.bits 31:0 CID Valid only if bit 13 in ld_cid_minicache_resp_log is set  Chips: BB_A0 BB_B0 K2
46863 #define MULD_REG_LD_TID_MINICACHE_LOG                                                                0x4e00a0UL //Access:R    DataWidth:0x20  Logging in case of minicache failure.bits 31:0 TID Valid only if bit 13 in ld_tid_minicache_resp_log is set  Chips: BB_A0 BB_B0 K2
46864 #define MULD_REG_LD_CID_MINICACHE_RESP_LOG                                                           0x4e00a4UL //Access:R    DataWidth:0xe   Logging in case of minicache failure.bits 12:0 CID load response; bit 13 - Indicates if ld_cid_minicache_log register is valid  Chips: BB_A0 BB_B0 K2
46865 #define MULD_REG_LD_TID_MINICACHE_RESP_LOG                                                           0x4e00a8UL //Access:R    DataWidth:0xe   Logging in case of minicache failure.bits 12:0 TID load response; bit 13 - Indicates if ld_tid_minicache_log register is valid  Chips: BB_A0 BB_B0 K2
46866 #define MULD_REG_LD_HDR_LOG                                                                          0x4e00acUL //Access:R    DataWidth:0x4   Logging of the problem which caused the ld_hdr_err interrupt. Bit 0: ilegal flags combination.  Chips: BB_A0 BB_B0 K2
46867 #define MULD_REG_LD_HDR_1ST_CYC_31_0                                                                 0x4e00b0UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46868 #define MULD_REG_LD_HDR_1ST_CYC_63_32                                                                0x4e00b4UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46869 #define MULD_REG_LD_HDR_1ST_CYC_95_64                                                                0x4e00b8UL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46870 #define MULD_REG_LD_HDR_1ST_CYC_127_96                                                               0x4e00bcUL //Access:R    DataWidth:0x20  Logging of the first loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46871 #define MULD_REG_LD_HDR_2ND_CYC_31_0                                                                 0x4e00c0UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46872 #define MULD_REG_LD_HDR_2ND_CYC_63_32                                                                0x4e00c4UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46873 #define MULD_REG_LD_HDR_2ND_CYC_95_64                                                                0x4e00c8UL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46874 #define MULD_REG_LD_HDR_2ND_CYC_127_96                                                               0x4e00ccUL //Access:R    DataWidth:0x20  Logging of the second loader header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46875 #define MULD_REG_CM_HDR_31_0                                                                         0x4e00d0UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46876 #define MULD_REG_CM_HDR_63_32                                                                        0x4e00d4UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46877 #define MULD_REG_CM_HDR_95_64                                                                        0x4e00d8UL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46878 #define MULD_REG_CM_HDR_127_96                                                                       0x4e00dcUL //Access:R    DataWidth:0x20  Logging of the cm header cycle - for the case ld_hdr_err is raised.  Chips: BB_A0 BB_B0 K2
46879 #define MULD_REG_LD_HDR_CLR                                                                          0x4e00e0UL //Access:W    DataWidth:0x1   Writing to this register clears hdr registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
46880 #define MULD_REG_STAT_FIC_MSG                                                                        0x4e00e4UL //Access:RC   DataWidth:0x20  Number of FIC messages sent to the loader  Chips: BB_A0 BB_B0 K2
46881 #define MULD_REG_DBG_PENDING_CCFC_REQ                                                                0x4e00e8UL //Access:R    DataWidth:0x8   number of CCFC requests wating for responses  Chips: BB_A0 BB_B0 K2
46882 #define MULD_REG_DBG_PENDING_TCFC_REQ                                                                0x4e00ecUL //Access:R    DataWidth:0x8   number of TCFC requests wating for responses  Chips: BB_A0 BB_B0 K2
46883 #define MULD_REG_LEN_ERR_LOG_1                                                                       0x4e00f0UL //Access:R    DataWidth:0x10  Logging register for long message error: bit 0-Segment message; bit 1-Message with PCI read; bit 2- Message with BD fetch; bit 3-Message with SGE fetch; bit 4- Message with BRB fetch; bits 5:6- QID; bits 7-RSV; bits 8-15 message CM length.  Chips: BB_A0 BB_B0 K2
46884 #define MULD_REG_LEN_ERR_LOG_2                                                                       0x4e00f4UL //Access:R    DataWidth:0x20  Logging register for long message error: bit 0:3 Segment message header length; 4:7 RSV;8:15 current length out of the segment message length array; 16:23 PCI response len (including BD and SGE fetches); 24:31 BRB  Chips: BB_A0 BB_B0 K2
46885 #define MULD_REG_LEN_ERR_LOG_CLR                                                                     0x4e00f8UL //Access:W    DataWidth:0x1   Writing to this register clears len err logging registers and enables logging new error details.  Chips: BB_A0 BB_B0 K2
46886 #define MULD_REG_LEN_ERR_LOG_V                                                                       0x4e00fcUL //Access:R    DataWidth:0x1   Indicates that the data at the len_err logging registers is valid.  Chips: BB_A0 BB_B0 K2
46887 #define MULD_REG_INT_STS                                                                             0x4e0180UL //Access:R    DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46888     #define MULD_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
46889     #define MULD_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
46890     #define MULD_REG_INT_STS_LD_HDR_ERR                                                              (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46891     #define MULD_REG_INT_STS_LD_HDR_ERR_SHIFT                                                        1
46892     #define MULD_REG_INT_STS_LD_SEG_MSG_ERR                                                          (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46893     #define MULD_REG_INT_STS_LD_SEG_MSG_ERR_SHIFT                                                    2
46894     #define MULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR                                                   (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46895     #define MULD_REG_INT_STS_LD_TID_MINI_CACHE_ERR_SHIFT                                             3
46896     #define MULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR                                                   (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46897     #define MULD_REG_INT_STS_LD_CID_MINI_CACHE_ERR_SHIFT                                             4
46898     #define MULD_REG_INT_STS_LD_LONG_MESSAGE                                                         (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46899     #define MULD_REG_INT_STS_LD_LONG_MESSAGE_SHIFT                                                   5
46900 #define MULD_REG_INT_MASK                                                                            0x4e0184UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46901     #define MULD_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.ADDRESS_ERROR .
46902     #define MULD_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
46903     #define MULD_REG_INT_MASK_LD_HDR_ERR                                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_HDR_ERR .
46904     #define MULD_REG_INT_MASK_LD_HDR_ERR_SHIFT                                                       1
46905     #define MULD_REG_INT_MASK_LD_SEG_MSG_ERR                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_SEG_MSG_ERR .
46906     #define MULD_REG_INT_MASK_LD_SEG_MSG_ERR_SHIFT                                                   2
46907     #define MULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_TID_MINI_CACHE_ERR .
46908     #define MULD_REG_INT_MASK_LD_TID_MINI_CACHE_ERR_SHIFT                                            3
46909     #define MULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_CID_MINI_CACHE_ERR .
46910     #define MULD_REG_INT_MASK_LD_CID_MINI_CACHE_ERR_SHIFT                                            4
46911     #define MULD_REG_INT_MASK_LD_LONG_MESSAGE                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: MULD_REG_INT_STS.LD_LONG_MESSAGE .
46912     #define MULD_REG_INT_MASK_LD_LONG_MESSAGE_SHIFT                                                  5
46913 #define MULD_REG_INT_STS_WR                                                                          0x4e0188UL //Access:WR   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46914     #define MULD_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
46915     #define MULD_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
46916     #define MULD_REG_INT_STS_WR_LD_HDR_ERR                                                           (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46917     #define MULD_REG_INT_STS_WR_LD_HDR_ERR_SHIFT                                                     1
46918     #define MULD_REG_INT_STS_WR_LD_SEG_MSG_ERR                                                       (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46919     #define MULD_REG_INT_STS_WR_LD_SEG_MSG_ERR_SHIFT                                                 2
46920     #define MULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR                                                (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46921     #define MULD_REG_INT_STS_WR_LD_TID_MINI_CACHE_ERR_SHIFT                                          3
46922     #define MULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR                                                (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46923     #define MULD_REG_INT_STS_WR_LD_CID_MINI_CACHE_ERR_SHIFT                                          4
46924     #define MULD_REG_INT_STS_WR_LD_LONG_MESSAGE                                                      (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46925     #define MULD_REG_INT_STS_WR_LD_LONG_MESSAGE_SHIFT                                                5
46926 #define MULD_REG_INT_STS_CLR                                                                         0x4e018cUL //Access:RC   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46927     #define MULD_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
46928     #define MULD_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
46929     #define MULD_REG_INT_STS_CLR_LD_HDR_ERR                                                          (0x1<<1) // There is a problem with the Loader header. The ld_hdr_log should be checked to see what is the scenario.
46930     #define MULD_REG_INT_STS_CLR_LD_HDR_ERR_SHIFT                                                    1
46931     #define MULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR                                                      (0x1<<2) // Issuese related to the seg message fields - the sum of the seg message length array is more than the FIC message len; segment message with data length 0.
46932     #define MULD_REG_INT_STS_CLR_LD_SEG_MSG_ERR_SHIFT                                                2
46933     #define MULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR                                               (0x1<<3) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LTID value
46934     #define MULD_REG_INT_STS_CLR_LD_TID_MINI_CACHE_ERR_SHIFT                                         3
46935     #define MULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR                                               (0x1<<4) // Mini cache error - meaning that A load response returned for a request used the minicache But there is a mismatch on the LCID value
46936     #define MULD_REG_INT_STS_CLR_LD_CID_MINI_CACHE_ERR_SHIFT                                         4
46937     #define MULD_REG_INT_STS_CLR_LD_LONG_MESSAGE                                                     (0x1<<5) // This interrupt is raised when a FOC message is larger than the max credit value on the FOC itnerface.
46938     #define MULD_REG_INT_STS_CLR_LD_LONG_MESSAGE_SHIFT                                               5
46939 #define MULD_REG_PRTY_MASK_H_0                                                                       0x4e0204UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46940     #define MULD_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT                                               (0x1<<0) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
46941     #define MULD_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT                                         0
46942     #define MULD_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                               (0x1<<1) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
46943     #define MULD_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                         1
46944     #define MULD_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT                                               (0x1<<2) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
46945     #define MULD_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT                                         2
46946     #define MULD_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT                                               (0x1<<3) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
46947     #define MULD_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_SHIFT                                         3
46948     #define MULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
46949     #define MULD_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           4
46950     #define MULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
46951     #define MULD_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           5
46952     #define MULD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
46953     #define MULD_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           6
46954     #define MULD_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
46955     #define MULD_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                           7
46956     #define MULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
46957     #define MULD_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           8
46958     #define MULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<9) // This bit masks, when set, the Parity bit: MULD_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
46959     #define MULD_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           9
46960 #define MULD_REG_MEM_ECC_EVENTS                                                                      0x4e021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
46961 #define MULD_REG_MEM002_I_MEM_DFT_K2                                                                 0x4e0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_cid_load_req_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46962 #define MULD_REG_MEM003_I_MEM_DFT_K2                                                                 0x4e0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_cid_load_resp_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46963 #define MULD_REG_MEM009_I_MEM_DFT_K2                                                                 0x4e022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_tid_load_req_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46964 #define MULD_REG_MEM010_I_MEM_DFT_K2                                                                 0x4e0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_tid_load_resp_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46965 #define MULD_REG_MEM005_I_MEM_DFT_K2                                                                 0x4e0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_msgq_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46966 #define MULD_REG_MEM004_I_MEM_DFT_K2                                                                 0x4e0238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_input_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46967 #define MULD_REG_MEM001_I_MEM_DFT_K2                                                                 0x4e023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_bd_db_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
46968 #define MULD_REG_MEM008_I_MEM_DFT_K2                                                                 0x4e0240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_sge_db_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
46969 #define MULD_REG_MEM007_I_MEM_DFT_K2                                                                 0x4e0244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_pci_rsep_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46970 #define MULD_REG_MEM006_I_MEM_DFT_K2                                                                 0x4e0248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance muld.i_pci_input_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
46971 #define MULD_REG_DESC_QUEUE_Q0                                                                       0x4e0400UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue0 - Debug access.  Chips: BB_A0 BB_B0 K2
46972 #define MULD_REG_DESC_QUEUE_Q0_SIZE                                                                  150
46973 #define MULD_REG_DESC_QUEUE_Q1                                                                       0x4e0800UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue1 - Debug access.  Chips: BB_A0 BB_B0 K2
46974 #define MULD_REG_DESC_QUEUE_Q1_SIZE                                                                  150
46975 #define MULD_REG_DESC_QUEUE_Q2                                                                       0x4e0c00UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue2 - Debug access::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46976 #define MULD_REG_DESC_QUEUE_Q2_SIZE                                                                  150
46977 #define MULD_REG_DESC_QUEUE_Q3                                                                       0x4e1000UL //Access:WB   DataWidth:0x23  Descriptor FIFO queue3 - Debug access::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46978 #define MULD_REG_DESC_QUEUE_Q3_SIZE                                                                  150
46979 #define MULD_REG_DBG_SELECT                                                                          0x4e1600UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
46980 #define MULD_REG_DBG_DWORD_ENABLE                                                                    0x4e1604UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
46981 #define MULD_REG_DBG_SHIFT                                                                           0x4e1608UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
46982 #define MULD_REG_DBG_FORCE_VALID                                                                     0x4e160cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46983 #define MULD_REG_DBG_FORCE_FRAME                                                                     0x4e1610UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
46984 #define MULD_REG_DBG_OUT_DATA                                                                        0x4e1620UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
46985 #define MULD_REG_DBG_OUT_DATA_SIZE                                                                   8
46986 #define MULD_REG_DBG_OUT_VALID                                                                       0x4e1640UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
46987 #define MULD_REG_DBG_OUT_FRAME                                                                       0x4e1644UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
46988 #define MULD_REG_FIC_INPUT_FIFO                                                                      0x4e2000UL //Access:WB   DataWidth:0x80  Access to input FIC FIFO  Chips: BB_A0 BB_B0 K2
46989 #define MULD_REG_FIC_INPUT_FIFO_SIZE                                                                 176
46990 #define MULD_REG_BD_DB_ARR_DW                                                                        0x4e4000UL //Access:WB   DataWidth:0xb4  Access the BD DB - Fields order: [179] Next address valid; [178:177] Endianity bits; [176] No snoop flag; [175] Releaxed ordering flag;[174:172] ATC flags; [171:160] TPH flags; [159:143] Next BD offset; [143:128] FID; [127:64] Next base address; [63:0] Base address::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46991 #define MULD_REG_BD_DB_ARR_DW_SIZE                                                                   2560
46992 #define MULD_REG_SGE_DB_ARR_DW                                                                       0x4e8000UL //Access:WB   DataWidth:0xb4  Access the SGE DB - Fields order: [179] Next address valid;  [178:177] Endianity bits;[176] No snoop flag; [175] Releaxed ordering flag;[174:172] ATC flags; [171:160] TPH flags; [159:143] Next SGE offset; [143:128] FID; [127:64] Next base address; [63:0] Base address::/TMLD_DISCARD/d in TMLD::/XYLD_DISCARD/d in XYLD::/YULD_DISCARD/d in YULD.  Chips: BB_A0 BB_B0 K2
46993 #define MULD_REG_SGE_DB_ARR_DW_SIZE                                                                  2560
46994 #define MULD_REG_QUEUE_MSG_MEM                                                                       0x4f0000UL //Access:WB   DataWidth:0x80  Debug access to The message queue memory.  Chips: BB_A0 BB_B0 K2
46995 #define MULD_REG_QUEUE_MSG_MEM_SIZE                                                                  7500
46996 #define NIG_REG_INT_STS_0                                                                            0x500040UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
46997     #define NIG_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the RF module.
46998     #define NIG_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
46999     #define NIG_REG_INT_STS_0_DEBUG_FIFO_ERROR                                                       (0x1<<1) // FIFO error in debug traffic FIFO.
47000     #define NIG_REG_INT_STS_0_DEBUG_FIFO_ERROR_SHIFT                                                 1
47001     #define NIG_REG_INT_STS_0_DORQ_FIFO_ERROR                                                        (0x1<<2) // FIFO error in DORQ FIFO.
47002     #define NIG_REG_INT_STS_0_DORQ_FIFO_ERROR_SHIFT                                                  2
47003     #define NIG_REG_INT_STS_0_DBG_SYNCFIFO_ERROR_WR                                                  (0x1<<3) // FIFO error in debug traffic sync FIFO.
47004     #define NIG_REG_INT_STS_0_DBG_SYNCFIFO_ERROR_WR_SHIFT                                            3
47005     #define NIG_REG_INT_STS_0_DORQ_SYNCFIFO_ERROR_WR                                                 (0x1<<4) // FIFO error in DORQ sync FIFO.
47006     #define NIG_REG_INT_STS_0_DORQ_SYNCFIFO_ERROR_WR_SHIFT                                           4
47007     #define NIG_REG_INT_STS_0_STORM_SYNCFIFO_ERROR_WR                                                (0x1<<5) // FIFO error in STORM sync FIFO.
47008     #define NIG_REG_INT_STS_0_STORM_SYNCFIFO_ERROR_WR_SHIFT                                          5
47009     #define NIG_REG_INT_STS_0_DBGMUX_SYNCFIFO_ERROR_WR                                               (0x1<<6) // FIFO error in DBGMUX sync FIFO.
47010     #define NIG_REG_INT_STS_0_DBGMUX_SYNCFIFO_ERROR_WR_SHIFT                                         6
47011     #define NIG_REG_INT_STS_0_MSDM_SYNCFIFO_ERROR_WR                                                 (0x1<<7) // FIFO error in MSDM sync FIFO.
47012     #define NIG_REG_INT_STS_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT                                           7
47013     #define NIG_REG_INT_STS_0_TSDM_SYNCFIFO_ERROR_WR                                                 (0x1<<8) // FIFO error in TSDM sync FIFO.
47014     #define NIG_REG_INT_STS_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT                                           8
47015     #define NIG_REG_INT_STS_0_USDM_SYNCFIFO_ERROR_WR                                                 (0x1<<9) // FIFO error in USDM sync FIFO.
47016     #define NIG_REG_INT_STS_0_USDM_SYNCFIFO_ERROR_WR_SHIFT                                           9
47017     #define NIG_REG_INT_STS_0_XSDM_SYNCFIFO_ERROR_WR                                                 (0x1<<10) // FIFO error in XSDM sync FIFO.
47018     #define NIG_REG_INT_STS_0_XSDM_SYNCFIFO_ERROR_WR_SHIFT                                           10
47019     #define NIG_REG_INT_STS_0_YSDM_SYNCFIFO_ERROR_WR                                                 (0x1<<11) // FIFO error in YSDM sync FIFO.
47020     #define NIG_REG_INT_STS_0_YSDM_SYNCFIFO_ERROR_WR_SHIFT                                           11
47021 #define NIG_REG_INT_MASK_0                                                                           0x500044UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
47022     #define NIG_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.ADDRESS_ERROR .
47023     #define NIG_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
47024     #define NIG_REG_INT_MASK_0_DEBUG_FIFO_ERROR                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DEBUG_FIFO_ERROR .
47025     #define NIG_REG_INT_MASK_0_DEBUG_FIFO_ERROR_SHIFT                                                1
47026     #define NIG_REG_INT_MASK_0_DORQ_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DORQ_FIFO_ERROR .
47027     #define NIG_REG_INT_MASK_0_DORQ_FIFO_ERROR_SHIFT                                                 2
47028     #define NIG_REG_INT_MASK_0_DBG_SYNCFIFO_ERROR_WR                                                 (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DBG_SYNCFIFO_ERROR_WR .
47029     #define NIG_REG_INT_MASK_0_DBG_SYNCFIFO_ERROR_WR_SHIFT                                           3
47030     #define NIG_REG_INT_MASK_0_DORQ_SYNCFIFO_ERROR_WR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DORQ_SYNCFIFO_ERROR_WR .
47031     #define NIG_REG_INT_MASK_0_DORQ_SYNCFIFO_ERROR_WR_SHIFT                                          4
47032     #define NIG_REG_INT_MASK_0_STORM_SYNCFIFO_ERROR_WR                                               (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.STORM_SYNCFIFO_ERROR_WR .
47033     #define NIG_REG_INT_MASK_0_STORM_SYNCFIFO_ERROR_WR_SHIFT                                         5
47034     #define NIG_REG_INT_MASK_0_DBGMUX_SYNCFIFO_ERROR_WR                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.DBGMUX_SYNCFIFO_ERROR_WR .
47035     #define NIG_REG_INT_MASK_0_DBGMUX_SYNCFIFO_ERROR_WR_SHIFT                                        6
47036     #define NIG_REG_INT_MASK_0_MSDM_SYNCFIFO_ERROR_WR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.MSDM_SYNCFIFO_ERROR_WR .
47037     #define NIG_REG_INT_MASK_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT                                          7
47038     #define NIG_REG_INT_MASK_0_TSDM_SYNCFIFO_ERROR_WR                                                (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.TSDM_SYNCFIFO_ERROR_WR .
47039     #define NIG_REG_INT_MASK_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT                                          8
47040     #define NIG_REG_INT_MASK_0_USDM_SYNCFIFO_ERROR_WR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.USDM_SYNCFIFO_ERROR_WR .
47041     #define NIG_REG_INT_MASK_0_USDM_SYNCFIFO_ERROR_WR_SHIFT                                          9
47042     #define NIG_REG_INT_MASK_0_XSDM_SYNCFIFO_ERROR_WR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.XSDM_SYNCFIFO_ERROR_WR .
47043     #define NIG_REG_INT_MASK_0_XSDM_SYNCFIFO_ERROR_WR_SHIFT                                          10
47044     #define NIG_REG_INT_MASK_0_YSDM_SYNCFIFO_ERROR_WR                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_0.YSDM_SYNCFIFO_ERROR_WR .
47045     #define NIG_REG_INT_MASK_0_YSDM_SYNCFIFO_ERROR_WR_SHIFT                                          11
47046 #define NIG_REG_INT_STS_WR_0                                                                         0x500048UL //Access:WR   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
47047     #define NIG_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the RF module.
47048     #define NIG_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
47049     #define NIG_REG_INT_STS_WR_0_DEBUG_FIFO_ERROR                                                    (0x1<<1) // FIFO error in debug traffic FIFO.
47050     #define NIG_REG_INT_STS_WR_0_DEBUG_FIFO_ERROR_SHIFT                                              1
47051     #define NIG_REG_INT_STS_WR_0_DORQ_FIFO_ERROR                                                     (0x1<<2) // FIFO error in DORQ FIFO.
47052     #define NIG_REG_INT_STS_WR_0_DORQ_FIFO_ERROR_SHIFT                                               2
47053     #define NIG_REG_INT_STS_WR_0_DBG_SYNCFIFO_ERROR_WR                                               (0x1<<3) // FIFO error in debug traffic sync FIFO.
47054     #define NIG_REG_INT_STS_WR_0_DBG_SYNCFIFO_ERROR_WR_SHIFT                                         3
47055     #define NIG_REG_INT_STS_WR_0_DORQ_SYNCFIFO_ERROR_WR                                              (0x1<<4) // FIFO error in DORQ sync FIFO.
47056     #define NIG_REG_INT_STS_WR_0_DORQ_SYNCFIFO_ERROR_WR_SHIFT                                        4
47057     #define NIG_REG_INT_STS_WR_0_STORM_SYNCFIFO_ERROR_WR                                             (0x1<<5) // FIFO error in STORM sync FIFO.
47058     #define NIG_REG_INT_STS_WR_0_STORM_SYNCFIFO_ERROR_WR_SHIFT                                       5
47059     #define NIG_REG_INT_STS_WR_0_DBGMUX_SYNCFIFO_ERROR_WR                                            (0x1<<6) // FIFO error in DBGMUX sync FIFO.
47060     #define NIG_REG_INT_STS_WR_0_DBGMUX_SYNCFIFO_ERROR_WR_SHIFT                                      6
47061     #define NIG_REG_INT_STS_WR_0_MSDM_SYNCFIFO_ERROR_WR                                              (0x1<<7) // FIFO error in MSDM sync FIFO.
47062     #define NIG_REG_INT_STS_WR_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT                                        7
47063     #define NIG_REG_INT_STS_WR_0_TSDM_SYNCFIFO_ERROR_WR                                              (0x1<<8) // FIFO error in TSDM sync FIFO.
47064     #define NIG_REG_INT_STS_WR_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT                                        8
47065     #define NIG_REG_INT_STS_WR_0_USDM_SYNCFIFO_ERROR_WR                                              (0x1<<9) // FIFO error in USDM sync FIFO.
47066     #define NIG_REG_INT_STS_WR_0_USDM_SYNCFIFO_ERROR_WR_SHIFT                                        9
47067     #define NIG_REG_INT_STS_WR_0_XSDM_SYNCFIFO_ERROR_WR                                              (0x1<<10) // FIFO error in XSDM sync FIFO.
47068     #define NIG_REG_INT_STS_WR_0_XSDM_SYNCFIFO_ERROR_WR_SHIFT                                        10
47069     #define NIG_REG_INT_STS_WR_0_YSDM_SYNCFIFO_ERROR_WR                                              (0x1<<11) // FIFO error in YSDM sync FIFO.
47070     #define NIG_REG_INT_STS_WR_0_YSDM_SYNCFIFO_ERROR_WR_SHIFT                                        11
47071 #define NIG_REG_INT_STS_CLR_0                                                                        0x50004cUL //Access:RC   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
47072     #define NIG_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the RF module.
47073     #define NIG_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
47074     #define NIG_REG_INT_STS_CLR_0_DEBUG_FIFO_ERROR                                                   (0x1<<1) // FIFO error in debug traffic FIFO.
47075     #define NIG_REG_INT_STS_CLR_0_DEBUG_FIFO_ERROR_SHIFT                                             1
47076     #define NIG_REG_INT_STS_CLR_0_DORQ_FIFO_ERROR                                                    (0x1<<2) // FIFO error in DORQ FIFO.
47077     #define NIG_REG_INT_STS_CLR_0_DORQ_FIFO_ERROR_SHIFT                                              2
47078     #define NIG_REG_INT_STS_CLR_0_DBG_SYNCFIFO_ERROR_WR                                              (0x1<<3) // FIFO error in debug traffic sync FIFO.
47079     #define NIG_REG_INT_STS_CLR_0_DBG_SYNCFIFO_ERROR_WR_SHIFT                                        3
47080     #define NIG_REG_INT_STS_CLR_0_DORQ_SYNCFIFO_ERROR_WR                                             (0x1<<4) // FIFO error in DORQ sync FIFO.
47081     #define NIG_REG_INT_STS_CLR_0_DORQ_SYNCFIFO_ERROR_WR_SHIFT                                       4
47082     #define NIG_REG_INT_STS_CLR_0_STORM_SYNCFIFO_ERROR_WR                                            (0x1<<5) // FIFO error in STORM sync FIFO.
47083     #define NIG_REG_INT_STS_CLR_0_STORM_SYNCFIFO_ERROR_WR_SHIFT                                      5
47084     #define NIG_REG_INT_STS_CLR_0_DBGMUX_SYNCFIFO_ERROR_WR                                           (0x1<<6) // FIFO error in DBGMUX sync FIFO.
47085     #define NIG_REG_INT_STS_CLR_0_DBGMUX_SYNCFIFO_ERROR_WR_SHIFT                                     6
47086     #define NIG_REG_INT_STS_CLR_0_MSDM_SYNCFIFO_ERROR_WR                                             (0x1<<7) // FIFO error in MSDM sync FIFO.
47087     #define NIG_REG_INT_STS_CLR_0_MSDM_SYNCFIFO_ERROR_WR_SHIFT                                       7
47088     #define NIG_REG_INT_STS_CLR_0_TSDM_SYNCFIFO_ERROR_WR                                             (0x1<<8) // FIFO error in TSDM sync FIFO.
47089     #define NIG_REG_INT_STS_CLR_0_TSDM_SYNCFIFO_ERROR_WR_SHIFT                                       8
47090     #define NIG_REG_INT_STS_CLR_0_USDM_SYNCFIFO_ERROR_WR                                             (0x1<<9) // FIFO error in USDM sync FIFO.
47091     #define NIG_REG_INT_STS_CLR_0_USDM_SYNCFIFO_ERROR_WR_SHIFT                                       9
47092     #define NIG_REG_INT_STS_CLR_0_XSDM_SYNCFIFO_ERROR_WR                                             (0x1<<10) // FIFO error in XSDM sync FIFO.
47093     #define NIG_REG_INT_STS_CLR_0_XSDM_SYNCFIFO_ERROR_WR_SHIFT                                       10
47094     #define NIG_REG_INT_STS_CLR_0_YSDM_SYNCFIFO_ERROR_WR                                             (0x1<<11) // FIFO error in YSDM sync FIFO.
47095     #define NIG_REG_INT_STS_CLR_0_YSDM_SYNCFIFO_ERROR_WR_SHIFT                                       11
47096 #define NIG_REG_INT_STS_1                                                                            0x500050UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47097     #define NIG_REG_INT_STS_1_TX_SOPQ0_ERROR                                                         (0x1<<0) // Error in the TX SOPQ.
47098     #define NIG_REG_INT_STS_1_TX_SOPQ0_ERROR_SHIFT                                                   0
47099     #define NIG_REG_INT_STS_1_TX_SOPQ1_ERROR                                                         (0x1<<1) // Error in the TX SOPQ.
47100     #define NIG_REG_INT_STS_1_TX_SOPQ1_ERROR_SHIFT                                                   1
47101     #define NIG_REG_INT_STS_1_TX_SOPQ2_ERROR                                                         (0x1<<2) // Error in the TX SOPQ.
47102     #define NIG_REG_INT_STS_1_TX_SOPQ2_ERROR_SHIFT                                                   2
47103     #define NIG_REG_INT_STS_1_TX_SOPQ3_ERROR                                                         (0x1<<3) // Error in the TX SOPQ.
47104     #define NIG_REG_INT_STS_1_TX_SOPQ3_ERROR_SHIFT                                                   3
47105     #define NIG_REG_INT_STS_1_TX_SOPQ4_ERROR                                                         (0x1<<4) // Error in the TX SOPQ.
47106     #define NIG_REG_INT_STS_1_TX_SOPQ4_ERROR_SHIFT                                                   4
47107     #define NIG_REG_INT_STS_1_TX_SOPQ5_ERROR                                                         (0x1<<5) // Error in the TX SOPQ.
47108     #define NIG_REG_INT_STS_1_TX_SOPQ5_ERROR_SHIFT                                                   5
47109     #define NIG_REG_INT_STS_1_TX_SOPQ6_ERROR                                                         (0x1<<6) // Error in the TX SOPQ.
47110     #define NIG_REG_INT_STS_1_TX_SOPQ6_ERROR_SHIFT                                                   6
47111     #define NIG_REG_INT_STS_1_TX_SOPQ7_ERROR                                                         (0x1<<7) // Error in the TX SOPQ.
47112     #define NIG_REG_INT_STS_1_TX_SOPQ7_ERROR_SHIFT                                                   7
47113     #define NIG_REG_INT_STS_1_TX_SOPQ8_ERROR                                                         (0x1<<8) // Error in the TX SOPQ.
47114     #define NIG_REG_INT_STS_1_TX_SOPQ8_ERROR_SHIFT                                                   8
47115     #define NIG_REG_INT_STS_1_TX_SOPQ9_ERROR                                                         (0x1<<9) // Error in the TX SOPQ.
47116     #define NIG_REG_INT_STS_1_TX_SOPQ9_ERROR_SHIFT                                                   9
47117     #define NIG_REG_INT_STS_1_TX_SOPQ10_ERROR                                                        (0x1<<10) // Error in the TX SOPQ.
47118     #define NIG_REG_INT_STS_1_TX_SOPQ10_ERROR_SHIFT                                                  10
47119     #define NIG_REG_INT_STS_1_TX_SOPQ11_ERROR                                                        (0x1<<11) // Error in the TX SOPQ.
47120     #define NIG_REG_INT_STS_1_TX_SOPQ11_ERROR_SHIFT                                                  11
47121     #define NIG_REG_INT_STS_1_TX_SOPQ12_ERROR                                                        (0x1<<12) // Error in the TX SOPQ.
47122     #define NIG_REG_INT_STS_1_TX_SOPQ12_ERROR_SHIFT                                                  12
47123     #define NIG_REG_INT_STS_1_TX_SOPQ13_ERROR                                                        (0x1<<13) // Error in the TX SOPQ.
47124     #define NIG_REG_INT_STS_1_TX_SOPQ13_ERROR_SHIFT                                                  13
47125     #define NIG_REG_INT_STS_1_TX_SOPQ14_ERROR                                                        (0x1<<14) // Error in the TX SOPQ.
47126     #define NIG_REG_INT_STS_1_TX_SOPQ14_ERROR_SHIFT                                                  14
47127     #define NIG_REG_INT_STS_1_TX_SOPQ15_ERROR                                                        (0x1<<15) // Error in the TX SOPQ.
47128     #define NIG_REG_INT_STS_1_TX_SOPQ15_ERROR_SHIFT                                                  15
47129     #define NIG_REG_INT_STS_1_LB_SOPQ0_ERROR                                                         (0x1<<16) // Error in the LB SOPQ.
47130     #define NIG_REG_INT_STS_1_LB_SOPQ0_ERROR_SHIFT                                                   16
47131     #define NIG_REG_INT_STS_1_LB_SOPQ1_ERROR                                                         (0x1<<17) // Error in the LB SOPQ.
47132     #define NIG_REG_INT_STS_1_LB_SOPQ1_ERROR_SHIFT                                                   17
47133     #define NIG_REG_INT_STS_1_LB_SOPQ2_ERROR                                                         (0x1<<18) // Error in the LB SOPQ.
47134     #define NIG_REG_INT_STS_1_LB_SOPQ2_ERROR_SHIFT                                                   18
47135     #define NIG_REG_INT_STS_1_LB_SOPQ3_ERROR                                                         (0x1<<19) // Error in the LB SOPQ.
47136     #define NIG_REG_INT_STS_1_LB_SOPQ3_ERROR_SHIFT                                                   19
47137     #define NIG_REG_INT_STS_1_LB_SOPQ4_ERROR                                                         (0x1<<20) // Error in the LB SOPQ.
47138     #define NIG_REG_INT_STS_1_LB_SOPQ4_ERROR_SHIFT                                                   20
47139     #define NIG_REG_INT_STS_1_LB_SOPQ5_ERROR                                                         (0x1<<21) // Error in the LB SOPQ.
47140     #define NIG_REG_INT_STS_1_LB_SOPQ5_ERROR_SHIFT                                                   21
47141     #define NIG_REG_INT_STS_1_LB_SOPQ6_ERROR                                                         (0x1<<22) // Error in the LB SOPQ.
47142     #define NIG_REG_INT_STS_1_LB_SOPQ6_ERROR_SHIFT                                                   22
47143     #define NIG_REG_INT_STS_1_LB_SOPQ7_ERROR                                                         (0x1<<23) // Error in the LB SOPQ.
47144     #define NIG_REG_INT_STS_1_LB_SOPQ7_ERROR_SHIFT                                                   23
47145     #define NIG_REG_INT_STS_1_LB_SOPQ8_ERROR                                                         (0x1<<24) // Error in the LB SOPQ.
47146     #define NIG_REG_INT_STS_1_LB_SOPQ8_ERROR_SHIFT                                                   24
47147     #define NIG_REG_INT_STS_1_LB_SOPQ9_ERROR                                                         (0x1<<25) // Error in the LB SOPQ.
47148     #define NIG_REG_INT_STS_1_LB_SOPQ9_ERROR_SHIFT                                                   25
47149     #define NIG_REG_INT_STS_1_LB_SOPQ10_ERROR                                                        (0x1<<26) // Error in the LB SOPQ.
47150     #define NIG_REG_INT_STS_1_LB_SOPQ10_ERROR_SHIFT                                                  26
47151     #define NIG_REG_INT_STS_1_LB_SOPQ11_ERROR                                                        (0x1<<27) // Error in the LB SOPQ.
47152     #define NIG_REG_INT_STS_1_LB_SOPQ11_ERROR_SHIFT                                                  27
47153     #define NIG_REG_INT_STS_1_LB_SOPQ12_ERROR                                                        (0x1<<28) // Error in the LB SOPQ.
47154     #define NIG_REG_INT_STS_1_LB_SOPQ12_ERROR_SHIFT                                                  28
47155     #define NIG_REG_INT_STS_1_LB_SOPQ13_ERROR                                                        (0x1<<29) // Error in the LB SOPQ.
47156     #define NIG_REG_INT_STS_1_LB_SOPQ13_ERROR_SHIFT                                                  29
47157     #define NIG_REG_INT_STS_1_LB_SOPQ14_ERROR                                                        (0x1<<30) // Error in the LB SOPQ.
47158     #define NIG_REG_INT_STS_1_LB_SOPQ14_ERROR_SHIFT                                                  30
47159     #define NIG_REG_INT_STS_1_LB_SOPQ15_ERROR                                                        (0x1<<31) // Error in the LB SOPQ.
47160     #define NIG_REG_INT_STS_1_LB_SOPQ15_ERROR_SHIFT                                                  31
47161 #define NIG_REG_INT_MASK_1                                                                           0x500054UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47162     #define NIG_REG_INT_MASK_1_TX_SOPQ0_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ0_ERROR .
47163     #define NIG_REG_INT_MASK_1_TX_SOPQ0_ERROR_SHIFT                                                  0
47164     #define NIG_REG_INT_MASK_1_TX_SOPQ1_ERROR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ1_ERROR .
47165     #define NIG_REG_INT_MASK_1_TX_SOPQ1_ERROR_SHIFT                                                  1
47166     #define NIG_REG_INT_MASK_1_TX_SOPQ2_ERROR                                                        (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ2_ERROR .
47167     #define NIG_REG_INT_MASK_1_TX_SOPQ2_ERROR_SHIFT                                                  2
47168     #define NIG_REG_INT_MASK_1_TX_SOPQ3_ERROR                                                        (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ3_ERROR .
47169     #define NIG_REG_INT_MASK_1_TX_SOPQ3_ERROR_SHIFT                                                  3
47170     #define NIG_REG_INT_MASK_1_TX_SOPQ4_ERROR                                                        (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ4_ERROR .
47171     #define NIG_REG_INT_MASK_1_TX_SOPQ4_ERROR_SHIFT                                                  4
47172     #define NIG_REG_INT_MASK_1_TX_SOPQ5_ERROR                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ5_ERROR .
47173     #define NIG_REG_INT_MASK_1_TX_SOPQ5_ERROR_SHIFT                                                  5
47174     #define NIG_REG_INT_MASK_1_TX_SOPQ6_ERROR                                                        (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ6_ERROR .
47175     #define NIG_REG_INT_MASK_1_TX_SOPQ6_ERROR_SHIFT                                                  6
47176     #define NIG_REG_INT_MASK_1_TX_SOPQ7_ERROR                                                        (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ7_ERROR .
47177     #define NIG_REG_INT_MASK_1_TX_SOPQ7_ERROR_SHIFT                                                  7
47178     #define NIG_REG_INT_MASK_1_TX_SOPQ8_ERROR                                                        (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ8_ERROR .
47179     #define NIG_REG_INT_MASK_1_TX_SOPQ8_ERROR_SHIFT                                                  8
47180     #define NIG_REG_INT_MASK_1_TX_SOPQ9_ERROR                                                        (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ9_ERROR .
47181     #define NIG_REG_INT_MASK_1_TX_SOPQ9_ERROR_SHIFT                                                  9
47182     #define NIG_REG_INT_MASK_1_TX_SOPQ10_ERROR                                                       (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ10_ERROR .
47183     #define NIG_REG_INT_MASK_1_TX_SOPQ10_ERROR_SHIFT                                                 10
47184     #define NIG_REG_INT_MASK_1_TX_SOPQ11_ERROR                                                       (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ11_ERROR .
47185     #define NIG_REG_INT_MASK_1_TX_SOPQ11_ERROR_SHIFT                                                 11
47186     #define NIG_REG_INT_MASK_1_TX_SOPQ12_ERROR                                                       (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ12_ERROR .
47187     #define NIG_REG_INT_MASK_1_TX_SOPQ12_ERROR_SHIFT                                                 12
47188     #define NIG_REG_INT_MASK_1_TX_SOPQ13_ERROR                                                       (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ13_ERROR .
47189     #define NIG_REG_INT_MASK_1_TX_SOPQ13_ERROR_SHIFT                                                 13
47190     #define NIG_REG_INT_MASK_1_TX_SOPQ14_ERROR                                                       (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ14_ERROR .
47191     #define NIG_REG_INT_MASK_1_TX_SOPQ14_ERROR_SHIFT                                                 14
47192     #define NIG_REG_INT_MASK_1_TX_SOPQ15_ERROR                                                       (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.TX_SOPQ15_ERROR .
47193     #define NIG_REG_INT_MASK_1_TX_SOPQ15_ERROR_SHIFT                                                 15
47194     #define NIG_REG_INT_MASK_1_LB_SOPQ0_ERROR                                                        (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ0_ERROR .
47195     #define NIG_REG_INT_MASK_1_LB_SOPQ0_ERROR_SHIFT                                                  16
47196     #define NIG_REG_INT_MASK_1_LB_SOPQ1_ERROR                                                        (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ1_ERROR .
47197     #define NIG_REG_INT_MASK_1_LB_SOPQ1_ERROR_SHIFT                                                  17
47198     #define NIG_REG_INT_MASK_1_LB_SOPQ2_ERROR                                                        (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ2_ERROR .
47199     #define NIG_REG_INT_MASK_1_LB_SOPQ2_ERROR_SHIFT                                                  18
47200     #define NIG_REG_INT_MASK_1_LB_SOPQ3_ERROR                                                        (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ3_ERROR .
47201     #define NIG_REG_INT_MASK_1_LB_SOPQ3_ERROR_SHIFT                                                  19
47202     #define NIG_REG_INT_MASK_1_LB_SOPQ4_ERROR                                                        (0x1<<20) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ4_ERROR .
47203     #define NIG_REG_INT_MASK_1_LB_SOPQ4_ERROR_SHIFT                                                  20
47204     #define NIG_REG_INT_MASK_1_LB_SOPQ5_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ5_ERROR .
47205     #define NIG_REG_INT_MASK_1_LB_SOPQ5_ERROR_SHIFT                                                  21
47206     #define NIG_REG_INT_MASK_1_LB_SOPQ6_ERROR                                                        (0x1<<22) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ6_ERROR .
47207     #define NIG_REG_INT_MASK_1_LB_SOPQ6_ERROR_SHIFT                                                  22
47208     #define NIG_REG_INT_MASK_1_LB_SOPQ7_ERROR                                                        (0x1<<23) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ7_ERROR .
47209     #define NIG_REG_INT_MASK_1_LB_SOPQ7_ERROR_SHIFT                                                  23
47210     #define NIG_REG_INT_MASK_1_LB_SOPQ8_ERROR                                                        (0x1<<24) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ8_ERROR .
47211     #define NIG_REG_INT_MASK_1_LB_SOPQ8_ERROR_SHIFT                                                  24
47212     #define NIG_REG_INT_MASK_1_LB_SOPQ9_ERROR                                                        (0x1<<25) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ9_ERROR .
47213     #define NIG_REG_INT_MASK_1_LB_SOPQ9_ERROR_SHIFT                                                  25
47214     #define NIG_REG_INT_MASK_1_LB_SOPQ10_ERROR                                                       (0x1<<26) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ10_ERROR .
47215     #define NIG_REG_INT_MASK_1_LB_SOPQ10_ERROR_SHIFT                                                 26
47216     #define NIG_REG_INT_MASK_1_LB_SOPQ11_ERROR                                                       (0x1<<27) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ11_ERROR .
47217     #define NIG_REG_INT_MASK_1_LB_SOPQ11_ERROR_SHIFT                                                 27
47218     #define NIG_REG_INT_MASK_1_LB_SOPQ12_ERROR                                                       (0x1<<28) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ12_ERROR .
47219     #define NIG_REG_INT_MASK_1_LB_SOPQ12_ERROR_SHIFT                                                 28
47220     #define NIG_REG_INT_MASK_1_LB_SOPQ13_ERROR                                                       (0x1<<29) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ13_ERROR .
47221     #define NIG_REG_INT_MASK_1_LB_SOPQ13_ERROR_SHIFT                                                 29
47222     #define NIG_REG_INT_MASK_1_LB_SOPQ14_ERROR                                                       (0x1<<30) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ14_ERROR .
47223     #define NIG_REG_INT_MASK_1_LB_SOPQ14_ERROR_SHIFT                                                 30
47224     #define NIG_REG_INT_MASK_1_LB_SOPQ15_ERROR                                                       (0x1<<31) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_1.LB_SOPQ15_ERROR .
47225     #define NIG_REG_INT_MASK_1_LB_SOPQ15_ERROR_SHIFT                                                 31
47226 #define NIG_REG_INT_STS_WR_1                                                                         0x500058UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47227     #define NIG_REG_INT_STS_WR_1_TX_SOPQ0_ERROR                                                      (0x1<<0) // Error in the TX SOPQ.
47228     #define NIG_REG_INT_STS_WR_1_TX_SOPQ0_ERROR_SHIFT                                                0
47229     #define NIG_REG_INT_STS_WR_1_TX_SOPQ1_ERROR                                                      (0x1<<1) // Error in the TX SOPQ.
47230     #define NIG_REG_INT_STS_WR_1_TX_SOPQ1_ERROR_SHIFT                                                1
47231     #define NIG_REG_INT_STS_WR_1_TX_SOPQ2_ERROR                                                      (0x1<<2) // Error in the TX SOPQ.
47232     #define NIG_REG_INT_STS_WR_1_TX_SOPQ2_ERROR_SHIFT                                                2
47233     #define NIG_REG_INT_STS_WR_1_TX_SOPQ3_ERROR                                                      (0x1<<3) // Error in the TX SOPQ.
47234     #define NIG_REG_INT_STS_WR_1_TX_SOPQ3_ERROR_SHIFT                                                3
47235     #define NIG_REG_INT_STS_WR_1_TX_SOPQ4_ERROR                                                      (0x1<<4) // Error in the TX SOPQ.
47236     #define NIG_REG_INT_STS_WR_1_TX_SOPQ4_ERROR_SHIFT                                                4
47237     #define NIG_REG_INT_STS_WR_1_TX_SOPQ5_ERROR                                                      (0x1<<5) // Error in the TX SOPQ.
47238     #define NIG_REG_INT_STS_WR_1_TX_SOPQ5_ERROR_SHIFT                                                5
47239     #define NIG_REG_INT_STS_WR_1_TX_SOPQ6_ERROR                                                      (0x1<<6) // Error in the TX SOPQ.
47240     #define NIG_REG_INT_STS_WR_1_TX_SOPQ6_ERROR_SHIFT                                                6
47241     #define NIG_REG_INT_STS_WR_1_TX_SOPQ7_ERROR                                                      (0x1<<7) // Error in the TX SOPQ.
47242     #define NIG_REG_INT_STS_WR_1_TX_SOPQ7_ERROR_SHIFT                                                7
47243     #define NIG_REG_INT_STS_WR_1_TX_SOPQ8_ERROR                                                      (0x1<<8) // Error in the TX SOPQ.
47244     #define NIG_REG_INT_STS_WR_1_TX_SOPQ8_ERROR_SHIFT                                                8
47245     #define NIG_REG_INT_STS_WR_1_TX_SOPQ9_ERROR                                                      (0x1<<9) // Error in the TX SOPQ.
47246     #define NIG_REG_INT_STS_WR_1_TX_SOPQ9_ERROR_SHIFT                                                9
47247     #define NIG_REG_INT_STS_WR_1_TX_SOPQ10_ERROR                                                     (0x1<<10) // Error in the TX SOPQ.
47248     #define NIG_REG_INT_STS_WR_1_TX_SOPQ10_ERROR_SHIFT                                               10
47249     #define NIG_REG_INT_STS_WR_1_TX_SOPQ11_ERROR                                                     (0x1<<11) // Error in the TX SOPQ.
47250     #define NIG_REG_INT_STS_WR_1_TX_SOPQ11_ERROR_SHIFT                                               11
47251     #define NIG_REG_INT_STS_WR_1_TX_SOPQ12_ERROR                                                     (0x1<<12) // Error in the TX SOPQ.
47252     #define NIG_REG_INT_STS_WR_1_TX_SOPQ12_ERROR_SHIFT                                               12
47253     #define NIG_REG_INT_STS_WR_1_TX_SOPQ13_ERROR                                                     (0x1<<13) // Error in the TX SOPQ.
47254     #define NIG_REG_INT_STS_WR_1_TX_SOPQ13_ERROR_SHIFT                                               13
47255     #define NIG_REG_INT_STS_WR_1_TX_SOPQ14_ERROR                                                     (0x1<<14) // Error in the TX SOPQ.
47256     #define NIG_REG_INT_STS_WR_1_TX_SOPQ14_ERROR_SHIFT                                               14
47257     #define NIG_REG_INT_STS_WR_1_TX_SOPQ15_ERROR                                                     (0x1<<15) // Error in the TX SOPQ.
47258     #define NIG_REG_INT_STS_WR_1_TX_SOPQ15_ERROR_SHIFT                                               15
47259     #define NIG_REG_INT_STS_WR_1_LB_SOPQ0_ERROR                                                      (0x1<<16) // Error in the LB SOPQ.
47260     #define NIG_REG_INT_STS_WR_1_LB_SOPQ0_ERROR_SHIFT                                                16
47261     #define NIG_REG_INT_STS_WR_1_LB_SOPQ1_ERROR                                                      (0x1<<17) // Error in the LB SOPQ.
47262     #define NIG_REG_INT_STS_WR_1_LB_SOPQ1_ERROR_SHIFT                                                17
47263     #define NIG_REG_INT_STS_WR_1_LB_SOPQ2_ERROR                                                      (0x1<<18) // Error in the LB SOPQ.
47264     #define NIG_REG_INT_STS_WR_1_LB_SOPQ2_ERROR_SHIFT                                                18
47265     #define NIG_REG_INT_STS_WR_1_LB_SOPQ3_ERROR                                                      (0x1<<19) // Error in the LB SOPQ.
47266     #define NIG_REG_INT_STS_WR_1_LB_SOPQ3_ERROR_SHIFT                                                19
47267     #define NIG_REG_INT_STS_WR_1_LB_SOPQ4_ERROR                                                      (0x1<<20) // Error in the LB SOPQ.
47268     #define NIG_REG_INT_STS_WR_1_LB_SOPQ4_ERROR_SHIFT                                                20
47269     #define NIG_REG_INT_STS_WR_1_LB_SOPQ5_ERROR                                                      (0x1<<21) // Error in the LB SOPQ.
47270     #define NIG_REG_INT_STS_WR_1_LB_SOPQ5_ERROR_SHIFT                                                21
47271     #define NIG_REG_INT_STS_WR_1_LB_SOPQ6_ERROR                                                      (0x1<<22) // Error in the LB SOPQ.
47272     #define NIG_REG_INT_STS_WR_1_LB_SOPQ6_ERROR_SHIFT                                                22
47273     #define NIG_REG_INT_STS_WR_1_LB_SOPQ7_ERROR                                                      (0x1<<23) // Error in the LB SOPQ.
47274     #define NIG_REG_INT_STS_WR_1_LB_SOPQ7_ERROR_SHIFT                                                23
47275     #define NIG_REG_INT_STS_WR_1_LB_SOPQ8_ERROR                                                      (0x1<<24) // Error in the LB SOPQ.
47276     #define NIG_REG_INT_STS_WR_1_LB_SOPQ8_ERROR_SHIFT                                                24
47277     #define NIG_REG_INT_STS_WR_1_LB_SOPQ9_ERROR                                                      (0x1<<25) // Error in the LB SOPQ.
47278     #define NIG_REG_INT_STS_WR_1_LB_SOPQ9_ERROR_SHIFT                                                25
47279     #define NIG_REG_INT_STS_WR_1_LB_SOPQ10_ERROR                                                     (0x1<<26) // Error in the LB SOPQ.
47280     #define NIG_REG_INT_STS_WR_1_LB_SOPQ10_ERROR_SHIFT                                               26
47281     #define NIG_REG_INT_STS_WR_1_LB_SOPQ11_ERROR                                                     (0x1<<27) // Error in the LB SOPQ.
47282     #define NIG_REG_INT_STS_WR_1_LB_SOPQ11_ERROR_SHIFT                                               27
47283     #define NIG_REG_INT_STS_WR_1_LB_SOPQ12_ERROR                                                     (0x1<<28) // Error in the LB SOPQ.
47284     #define NIG_REG_INT_STS_WR_1_LB_SOPQ12_ERROR_SHIFT                                               28
47285     #define NIG_REG_INT_STS_WR_1_LB_SOPQ13_ERROR                                                     (0x1<<29) // Error in the LB SOPQ.
47286     #define NIG_REG_INT_STS_WR_1_LB_SOPQ13_ERROR_SHIFT                                               29
47287     #define NIG_REG_INT_STS_WR_1_LB_SOPQ14_ERROR                                                     (0x1<<30) // Error in the LB SOPQ.
47288     #define NIG_REG_INT_STS_WR_1_LB_SOPQ14_ERROR_SHIFT                                               30
47289     #define NIG_REG_INT_STS_WR_1_LB_SOPQ15_ERROR                                                     (0x1<<31) // Error in the LB SOPQ.
47290     #define NIG_REG_INT_STS_WR_1_LB_SOPQ15_ERROR_SHIFT                                               31
47291 #define NIG_REG_INT_STS_CLR_1                                                                        0x50005cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47292     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ0_ERROR                                                     (0x1<<0) // Error in the TX SOPQ.
47293     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ0_ERROR_SHIFT                                               0
47294     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ1_ERROR                                                     (0x1<<1) // Error in the TX SOPQ.
47295     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ1_ERROR_SHIFT                                               1
47296     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ2_ERROR                                                     (0x1<<2) // Error in the TX SOPQ.
47297     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ2_ERROR_SHIFT                                               2
47298     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ3_ERROR                                                     (0x1<<3) // Error in the TX SOPQ.
47299     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ3_ERROR_SHIFT                                               3
47300     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ4_ERROR                                                     (0x1<<4) // Error in the TX SOPQ.
47301     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ4_ERROR_SHIFT                                               4
47302     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ5_ERROR                                                     (0x1<<5) // Error in the TX SOPQ.
47303     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ5_ERROR_SHIFT                                               5
47304     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ6_ERROR                                                     (0x1<<6) // Error in the TX SOPQ.
47305     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ6_ERROR_SHIFT                                               6
47306     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ7_ERROR                                                     (0x1<<7) // Error in the TX SOPQ.
47307     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ7_ERROR_SHIFT                                               7
47308     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ8_ERROR                                                     (0x1<<8) // Error in the TX SOPQ.
47309     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ8_ERROR_SHIFT                                               8
47310     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ9_ERROR                                                     (0x1<<9) // Error in the TX SOPQ.
47311     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ9_ERROR_SHIFT                                               9
47312     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ10_ERROR                                                    (0x1<<10) // Error in the TX SOPQ.
47313     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ10_ERROR_SHIFT                                              10
47314     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ11_ERROR                                                    (0x1<<11) // Error in the TX SOPQ.
47315     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ11_ERROR_SHIFT                                              11
47316     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ12_ERROR                                                    (0x1<<12) // Error in the TX SOPQ.
47317     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ12_ERROR_SHIFT                                              12
47318     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ13_ERROR                                                    (0x1<<13) // Error in the TX SOPQ.
47319     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ13_ERROR_SHIFT                                              13
47320     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ14_ERROR                                                    (0x1<<14) // Error in the TX SOPQ.
47321     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ14_ERROR_SHIFT                                              14
47322     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ15_ERROR                                                    (0x1<<15) // Error in the TX SOPQ.
47323     #define NIG_REG_INT_STS_CLR_1_TX_SOPQ15_ERROR_SHIFT                                              15
47324     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ0_ERROR                                                     (0x1<<16) // Error in the LB SOPQ.
47325     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ0_ERROR_SHIFT                                               16
47326     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ1_ERROR                                                     (0x1<<17) // Error in the LB SOPQ.
47327     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ1_ERROR_SHIFT                                               17
47328     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ2_ERROR                                                     (0x1<<18) // Error in the LB SOPQ.
47329     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ2_ERROR_SHIFT                                               18
47330     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ3_ERROR                                                     (0x1<<19) // Error in the LB SOPQ.
47331     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ3_ERROR_SHIFT                                               19
47332     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ4_ERROR                                                     (0x1<<20) // Error in the LB SOPQ.
47333     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ4_ERROR_SHIFT                                               20
47334     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ5_ERROR                                                     (0x1<<21) // Error in the LB SOPQ.
47335     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ5_ERROR_SHIFT                                               21
47336     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ6_ERROR                                                     (0x1<<22) // Error in the LB SOPQ.
47337     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ6_ERROR_SHIFT                                               22
47338     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ7_ERROR                                                     (0x1<<23) // Error in the LB SOPQ.
47339     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ7_ERROR_SHIFT                                               23
47340     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ8_ERROR                                                     (0x1<<24) // Error in the LB SOPQ.
47341     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ8_ERROR_SHIFT                                               24
47342     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ9_ERROR                                                     (0x1<<25) // Error in the LB SOPQ.
47343     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ9_ERROR_SHIFT                                               25
47344     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ10_ERROR                                                    (0x1<<26) // Error in the LB SOPQ.
47345     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ10_ERROR_SHIFT                                              26
47346     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ11_ERROR                                                    (0x1<<27) // Error in the LB SOPQ.
47347     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ11_ERROR_SHIFT                                              27
47348     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ12_ERROR                                                    (0x1<<28) // Error in the LB SOPQ.
47349     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ12_ERROR_SHIFT                                              28
47350     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ13_ERROR                                                    (0x1<<29) // Error in the LB SOPQ.
47351     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ13_ERROR_SHIFT                                              29
47352     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ14_ERROR                                                    (0x1<<30) // Error in the LB SOPQ.
47353     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ14_ERROR_SHIFT                                              30
47354     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ15_ERROR                                                    (0x1<<31) // Error in the LB SOPQ.
47355     #define NIG_REG_INT_STS_CLR_1_LB_SOPQ15_ERROR_SHIFT                                              31
47356 #define NIG_REG_INT_STS_2                                                                            0x500060UL //Access:R    DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47357     #define NIG_REG_INT_STS_2_P0_PURELB_SOPQ_ERROR                                                   (0x1<<0) // Error in the pure-loopback SOPQ.
47358     #define NIG_REG_INT_STS_2_P0_PURELB_SOPQ_ERROR_SHIFT                                             0
47359     #define NIG_REG_INT_STS_2_P0_RX_MACFIFO_ERROR                                                    (0x1<<1) // Error in RX MAC FIFO.
47360     #define NIG_REG_INT_STS_2_P0_RX_MACFIFO_ERROR_SHIFT                                              1
47361     #define NIG_REG_INT_STS_2_P0_TX_MACFIFO_ERROR                                                    (0x1<<2) // Error in TX MAC FIFO.
47362     #define NIG_REG_INT_STS_2_P0_TX_MACFIFO_ERROR_SHIFT                                              2
47363     #define NIG_REG_INT_STS_2_P0_TX_BMB_FIFO_ERROR                                                   (0x1<<3) // FIFO error in TX BMB FIFO.
47364     #define NIG_REG_INT_STS_2_P0_TX_BMB_FIFO_ERROR_SHIFT                                             3
47365     #define NIG_REG_INT_STS_2_P0_LB_BMB_FIFO_ERROR                                                   (0x1<<4) // FIFO error in LB BMB FIFO.
47366     #define NIG_REG_INT_STS_2_P0_LB_BMB_FIFO_ERROR_SHIFT                                             4
47367     #define NIG_REG_INT_STS_2_P0_TX_BTB_FIFO_ERROR                                                   (0x1<<5) // Error in BTB FIFO for TX path.
47368     #define NIG_REG_INT_STS_2_P0_TX_BTB_FIFO_ERROR_SHIFT                                             5
47369     #define NIG_REG_INT_STS_2_P0_LB_BTB_FIFO_ERROR                                                   (0x1<<6) // Error in BTB FIFO for LB path.
47370     #define NIG_REG_INT_STS_2_P0_LB_BTB_FIFO_ERROR_SHIFT                                             6
47371     #define NIG_REG_INT_STS_2_P0_RX_LLH_DFIFO_ERROR                                                  (0x1<<7) // Error in LLH Data FIFO.
47372     #define NIG_REG_INT_STS_2_P0_RX_LLH_DFIFO_ERROR_SHIFT                                            7
47373     #define NIG_REG_INT_STS_2_P0_TX_LLH_DFIFO_ERROR                                                  (0x1<<8) // Error in LLH Data FIFO.
47374     #define NIG_REG_INT_STS_2_P0_TX_LLH_DFIFO_ERROR_SHIFT                                            8
47375     #define NIG_REG_INT_STS_2_P0_LB_LLH_DFIFO_ERROR                                                  (0x1<<9) // Error in LLH Data FIFO.
47376     #define NIG_REG_INT_STS_2_P0_LB_LLH_DFIFO_ERROR_SHIFT                                            9
47377     #define NIG_REG_INT_STS_2_P0_RX_LLH_HFIFO_ERROR                                                  (0x1<<10) // Error in LLH Header FIFO.
47378     #define NIG_REG_INT_STS_2_P0_RX_LLH_HFIFO_ERROR_SHIFT                                            10
47379     #define NIG_REG_INT_STS_2_P0_TX_LLH_HFIFO_ERROR                                                  (0x1<<11) // Error in LLH Header FIFO.
47380     #define NIG_REG_INT_STS_2_P0_TX_LLH_HFIFO_ERROR_SHIFT                                            11
47381     #define NIG_REG_INT_STS_2_P0_LB_LLH_HFIFO_ERROR                                                  (0x1<<12) // Error in LLH Header FIFO.
47382     #define NIG_REG_INT_STS_2_P0_LB_LLH_HFIFO_ERROR_SHIFT                                            12
47383     #define NIG_REG_INT_STS_2_P0_RX_LLH_RFIFO_ERROR                                                  (0x1<<13) // Error in LLH Result FIFO.
47384     #define NIG_REG_INT_STS_2_P0_RX_LLH_RFIFO_ERROR_SHIFT                                            13
47385     #define NIG_REG_INT_STS_2_P0_TX_LLH_RFIFO_ERROR                                                  (0x1<<14) // Error in LLH Result FIFO.
47386     #define NIG_REG_INT_STS_2_P0_TX_LLH_RFIFO_ERROR_SHIFT                                            14
47387     #define NIG_REG_INT_STS_2_P0_LB_LLH_RFIFO_ERROR                                                  (0x1<<15) // Error in LLH Result FIFO.
47388     #define NIG_REG_INT_STS_2_P0_LB_LLH_RFIFO_ERROR_SHIFT                                            15
47389     #define NIG_REG_INT_STS_2_P0_STORM_FIFO_ERROR                                                    (0x1<<16) // FIFO error in STORM message FIFO.
47390     #define NIG_REG_INT_STS_2_P0_STORM_FIFO_ERROR_SHIFT                                              16
47391     #define NIG_REG_INT_STS_2_P0_STORM_DSCR_FIFO_ERROR                                               (0x1<<17) // FIFO error in STORM descriptor FIFO.
47392     #define NIG_REG_INT_STS_2_P0_STORM_DSCR_FIFO_ERROR_SHIFT                                         17
47393     #define NIG_REG_INT_STS_2_P0_TX_GNT_FIFO_ERROR                                                   (0x1<<18) // Error in grant FIFO.
47394     #define NIG_REG_INT_STS_2_P0_TX_GNT_FIFO_ERROR_SHIFT                                             18
47395     #define NIG_REG_INT_STS_2_P0_LB_GNT_FIFO_ERROR                                                   (0x1<<19) // Error in grant FIFO.
47396     #define NIG_REG_INT_STS_2_P0_LB_GNT_FIFO_ERROR_SHIFT                                             19
47397 #define NIG_REG_INT_MASK_2                                                                           0x500064UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47398     #define NIG_REG_INT_MASK_2_P0_PURELB_SOPQ_ERROR                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_PURELB_SOPQ_ERROR .
47399     #define NIG_REG_INT_MASK_2_P0_PURELB_SOPQ_ERROR_SHIFT                                            0
47400     #define NIG_REG_INT_MASK_2_P0_RX_MACFIFO_ERROR                                                   (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_MACFIFO_ERROR .
47401     #define NIG_REG_INT_MASK_2_P0_RX_MACFIFO_ERROR_SHIFT                                             1
47402     #define NIG_REG_INT_MASK_2_P0_TX_MACFIFO_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_MACFIFO_ERROR .
47403     #define NIG_REG_INT_MASK_2_P0_TX_MACFIFO_ERROR_SHIFT                                             2
47404     #define NIG_REG_INT_MASK_2_P0_TX_BMB_FIFO_ERROR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_BMB_FIFO_ERROR .
47405     #define NIG_REG_INT_MASK_2_P0_TX_BMB_FIFO_ERROR_SHIFT                                            3
47406     #define NIG_REG_INT_MASK_2_P0_LB_BMB_FIFO_ERROR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_BMB_FIFO_ERROR .
47407     #define NIG_REG_INT_MASK_2_P0_LB_BMB_FIFO_ERROR_SHIFT                                            4
47408     #define NIG_REG_INT_MASK_2_P0_TX_BTB_FIFO_ERROR                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_BTB_FIFO_ERROR .
47409     #define NIG_REG_INT_MASK_2_P0_TX_BTB_FIFO_ERROR_SHIFT                                            5
47410     #define NIG_REG_INT_MASK_2_P0_LB_BTB_FIFO_ERROR                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_BTB_FIFO_ERROR .
47411     #define NIG_REG_INT_MASK_2_P0_LB_BTB_FIFO_ERROR_SHIFT                                            6
47412     #define NIG_REG_INT_MASK_2_P0_RX_LLH_DFIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_DFIFO_ERROR .
47413     #define NIG_REG_INT_MASK_2_P0_RX_LLH_DFIFO_ERROR_SHIFT                                           7
47414     #define NIG_REG_INT_MASK_2_P0_TX_LLH_DFIFO_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_DFIFO_ERROR .
47415     #define NIG_REG_INT_MASK_2_P0_TX_LLH_DFIFO_ERROR_SHIFT                                           8
47416     #define NIG_REG_INT_MASK_2_P0_LB_LLH_DFIFO_ERROR                                                 (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_DFIFO_ERROR .
47417     #define NIG_REG_INT_MASK_2_P0_LB_LLH_DFIFO_ERROR_SHIFT                                           9
47418     #define NIG_REG_INT_MASK_2_P0_RX_LLH_HFIFO_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_HFIFO_ERROR .
47419     #define NIG_REG_INT_MASK_2_P0_RX_LLH_HFIFO_ERROR_SHIFT                                           10
47420     #define NIG_REG_INT_MASK_2_P0_TX_LLH_HFIFO_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_HFIFO_ERROR .
47421     #define NIG_REG_INT_MASK_2_P0_TX_LLH_HFIFO_ERROR_SHIFT                                           11
47422     #define NIG_REG_INT_MASK_2_P0_LB_LLH_HFIFO_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_HFIFO_ERROR .
47423     #define NIG_REG_INT_MASK_2_P0_LB_LLH_HFIFO_ERROR_SHIFT                                           12
47424     #define NIG_REG_INT_MASK_2_P0_RX_LLH_RFIFO_ERROR                                                 (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_RX_LLH_RFIFO_ERROR .
47425     #define NIG_REG_INT_MASK_2_P0_RX_LLH_RFIFO_ERROR_SHIFT                                           13
47426     #define NIG_REG_INT_MASK_2_P0_TX_LLH_RFIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_LLH_RFIFO_ERROR .
47427     #define NIG_REG_INT_MASK_2_P0_TX_LLH_RFIFO_ERROR_SHIFT                                           14
47428     #define NIG_REG_INT_MASK_2_P0_LB_LLH_RFIFO_ERROR                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_LLH_RFIFO_ERROR .
47429     #define NIG_REG_INT_MASK_2_P0_LB_LLH_RFIFO_ERROR_SHIFT                                           15
47430     #define NIG_REG_INT_MASK_2_P0_STORM_FIFO_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_STORM_FIFO_ERROR .
47431     #define NIG_REG_INT_MASK_2_P0_STORM_FIFO_ERROR_SHIFT                                             16
47432     #define NIG_REG_INT_MASK_2_P0_STORM_DSCR_FIFO_ERROR                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_STORM_DSCR_FIFO_ERROR .
47433     #define NIG_REG_INT_MASK_2_P0_STORM_DSCR_FIFO_ERROR_SHIFT                                        17
47434     #define NIG_REG_INT_MASK_2_P0_TX_GNT_FIFO_ERROR                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_TX_GNT_FIFO_ERROR .
47435     #define NIG_REG_INT_MASK_2_P0_TX_GNT_FIFO_ERROR_SHIFT                                            18
47436     #define NIG_REG_INT_MASK_2_P0_LB_GNT_FIFO_ERROR                                                  (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_2.P0_LB_GNT_FIFO_ERROR .
47437     #define NIG_REG_INT_MASK_2_P0_LB_GNT_FIFO_ERROR_SHIFT                                            19
47438 #define NIG_REG_INT_STS_WR_2                                                                         0x500068UL //Access:WR   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47439     #define NIG_REG_INT_STS_WR_2_P0_PURELB_SOPQ_ERROR                                                (0x1<<0) // Error in the pure-loopback SOPQ.
47440     #define NIG_REG_INT_STS_WR_2_P0_PURELB_SOPQ_ERROR_SHIFT                                          0
47441     #define NIG_REG_INT_STS_WR_2_P0_RX_MACFIFO_ERROR                                                 (0x1<<1) // Error in RX MAC FIFO.
47442     #define NIG_REG_INT_STS_WR_2_P0_RX_MACFIFO_ERROR_SHIFT                                           1
47443     #define NIG_REG_INT_STS_WR_2_P0_TX_MACFIFO_ERROR                                                 (0x1<<2) // Error in TX MAC FIFO.
47444     #define NIG_REG_INT_STS_WR_2_P0_TX_MACFIFO_ERROR_SHIFT                                           2
47445     #define NIG_REG_INT_STS_WR_2_P0_TX_BMB_FIFO_ERROR                                                (0x1<<3) // FIFO error in TX BMB FIFO.
47446     #define NIG_REG_INT_STS_WR_2_P0_TX_BMB_FIFO_ERROR_SHIFT                                          3
47447     #define NIG_REG_INT_STS_WR_2_P0_LB_BMB_FIFO_ERROR                                                (0x1<<4) // FIFO error in LB BMB FIFO.
47448     #define NIG_REG_INT_STS_WR_2_P0_LB_BMB_FIFO_ERROR_SHIFT                                          4
47449     #define NIG_REG_INT_STS_WR_2_P0_TX_BTB_FIFO_ERROR                                                (0x1<<5) // Error in BTB FIFO for TX path.
47450     #define NIG_REG_INT_STS_WR_2_P0_TX_BTB_FIFO_ERROR_SHIFT                                          5
47451     #define NIG_REG_INT_STS_WR_2_P0_LB_BTB_FIFO_ERROR                                                (0x1<<6) // Error in BTB FIFO for LB path.
47452     #define NIG_REG_INT_STS_WR_2_P0_LB_BTB_FIFO_ERROR_SHIFT                                          6
47453     #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_DFIFO_ERROR                                               (0x1<<7) // Error in LLH Data FIFO.
47454     #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_DFIFO_ERROR_SHIFT                                         7
47455     #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_DFIFO_ERROR                                               (0x1<<8) // Error in LLH Data FIFO.
47456     #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_DFIFO_ERROR_SHIFT                                         8
47457     #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_DFIFO_ERROR                                               (0x1<<9) // Error in LLH Data FIFO.
47458     #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_DFIFO_ERROR_SHIFT                                         9
47459     #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_HFIFO_ERROR                                               (0x1<<10) // Error in LLH Header FIFO.
47460     #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_HFIFO_ERROR_SHIFT                                         10
47461     #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_HFIFO_ERROR                                               (0x1<<11) // Error in LLH Header FIFO.
47462     #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_HFIFO_ERROR_SHIFT                                         11
47463     #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_HFIFO_ERROR                                               (0x1<<12) // Error in LLH Header FIFO.
47464     #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_HFIFO_ERROR_SHIFT                                         12
47465     #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_RFIFO_ERROR                                               (0x1<<13) // Error in LLH Result FIFO.
47466     #define NIG_REG_INT_STS_WR_2_P0_RX_LLH_RFIFO_ERROR_SHIFT                                         13
47467     #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_RFIFO_ERROR                                               (0x1<<14) // Error in LLH Result FIFO.
47468     #define NIG_REG_INT_STS_WR_2_P0_TX_LLH_RFIFO_ERROR_SHIFT                                         14
47469     #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_RFIFO_ERROR                                               (0x1<<15) // Error in LLH Result FIFO.
47470     #define NIG_REG_INT_STS_WR_2_P0_LB_LLH_RFIFO_ERROR_SHIFT                                         15
47471     #define NIG_REG_INT_STS_WR_2_P0_STORM_FIFO_ERROR                                                 (0x1<<16) // FIFO error in STORM message FIFO.
47472     #define NIG_REG_INT_STS_WR_2_P0_STORM_FIFO_ERROR_SHIFT                                           16
47473     #define NIG_REG_INT_STS_WR_2_P0_STORM_DSCR_FIFO_ERROR                                            (0x1<<17) // FIFO error in STORM descriptor FIFO.
47474     #define NIG_REG_INT_STS_WR_2_P0_STORM_DSCR_FIFO_ERROR_SHIFT                                      17
47475     #define NIG_REG_INT_STS_WR_2_P0_TX_GNT_FIFO_ERROR                                                (0x1<<18) // Error in grant FIFO.
47476     #define NIG_REG_INT_STS_WR_2_P0_TX_GNT_FIFO_ERROR_SHIFT                                          18
47477     #define NIG_REG_INT_STS_WR_2_P0_LB_GNT_FIFO_ERROR                                                (0x1<<19) // Error in grant FIFO.
47478     #define NIG_REG_INT_STS_WR_2_P0_LB_GNT_FIFO_ERROR_SHIFT                                          19
47479 #define NIG_REG_INT_STS_CLR_2                                                                        0x50006cUL //Access:RC   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47480     #define NIG_REG_INT_STS_CLR_2_P0_PURELB_SOPQ_ERROR                                               (0x1<<0) // Error in the pure-loopback SOPQ.
47481     #define NIG_REG_INT_STS_CLR_2_P0_PURELB_SOPQ_ERROR_SHIFT                                         0
47482     #define NIG_REG_INT_STS_CLR_2_P0_RX_MACFIFO_ERROR                                                (0x1<<1) // Error in RX MAC FIFO.
47483     #define NIG_REG_INT_STS_CLR_2_P0_RX_MACFIFO_ERROR_SHIFT                                          1
47484     #define NIG_REG_INT_STS_CLR_2_P0_TX_MACFIFO_ERROR                                                (0x1<<2) // Error in TX MAC FIFO.
47485     #define NIG_REG_INT_STS_CLR_2_P0_TX_MACFIFO_ERROR_SHIFT                                          2
47486     #define NIG_REG_INT_STS_CLR_2_P0_TX_BMB_FIFO_ERROR                                               (0x1<<3) // FIFO error in TX BMB FIFO.
47487     #define NIG_REG_INT_STS_CLR_2_P0_TX_BMB_FIFO_ERROR_SHIFT                                         3
47488     #define NIG_REG_INT_STS_CLR_2_P0_LB_BMB_FIFO_ERROR                                               (0x1<<4) // FIFO error in LB BMB FIFO.
47489     #define NIG_REG_INT_STS_CLR_2_P0_LB_BMB_FIFO_ERROR_SHIFT                                         4
47490     #define NIG_REG_INT_STS_CLR_2_P0_TX_BTB_FIFO_ERROR                                               (0x1<<5) // Error in BTB FIFO for TX path.
47491     #define NIG_REG_INT_STS_CLR_2_P0_TX_BTB_FIFO_ERROR_SHIFT                                         5
47492     #define NIG_REG_INT_STS_CLR_2_P0_LB_BTB_FIFO_ERROR                                               (0x1<<6) // Error in BTB FIFO for LB path.
47493     #define NIG_REG_INT_STS_CLR_2_P0_LB_BTB_FIFO_ERROR_SHIFT                                         6
47494     #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_DFIFO_ERROR                                              (0x1<<7) // Error in LLH Data FIFO.
47495     #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_DFIFO_ERROR_SHIFT                                        7
47496     #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_DFIFO_ERROR                                              (0x1<<8) // Error in LLH Data FIFO.
47497     #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_DFIFO_ERROR_SHIFT                                        8
47498     #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_DFIFO_ERROR                                              (0x1<<9) // Error in LLH Data FIFO.
47499     #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_DFIFO_ERROR_SHIFT                                        9
47500     #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_HFIFO_ERROR                                              (0x1<<10) // Error in LLH Header FIFO.
47501     #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_HFIFO_ERROR_SHIFT                                        10
47502     #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_HFIFO_ERROR                                              (0x1<<11) // Error in LLH Header FIFO.
47503     #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_HFIFO_ERROR_SHIFT                                        11
47504     #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_HFIFO_ERROR                                              (0x1<<12) // Error in LLH Header FIFO.
47505     #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_HFIFO_ERROR_SHIFT                                        12
47506     #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_RFIFO_ERROR                                              (0x1<<13) // Error in LLH Result FIFO.
47507     #define NIG_REG_INT_STS_CLR_2_P0_RX_LLH_RFIFO_ERROR_SHIFT                                        13
47508     #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_RFIFO_ERROR                                              (0x1<<14) // Error in LLH Result FIFO.
47509     #define NIG_REG_INT_STS_CLR_2_P0_TX_LLH_RFIFO_ERROR_SHIFT                                        14
47510     #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_RFIFO_ERROR                                              (0x1<<15) // Error in LLH Result FIFO.
47511     #define NIG_REG_INT_STS_CLR_2_P0_LB_LLH_RFIFO_ERROR_SHIFT                                        15
47512     #define NIG_REG_INT_STS_CLR_2_P0_STORM_FIFO_ERROR                                                (0x1<<16) // FIFO error in STORM message FIFO.
47513     #define NIG_REG_INT_STS_CLR_2_P0_STORM_FIFO_ERROR_SHIFT                                          16
47514     #define NIG_REG_INT_STS_CLR_2_P0_STORM_DSCR_FIFO_ERROR                                           (0x1<<17) // FIFO error in STORM descriptor FIFO.
47515     #define NIG_REG_INT_STS_CLR_2_P0_STORM_DSCR_FIFO_ERROR_SHIFT                                     17
47516     #define NIG_REG_INT_STS_CLR_2_P0_TX_GNT_FIFO_ERROR                                               (0x1<<18) // Error in grant FIFO.
47517     #define NIG_REG_INT_STS_CLR_2_P0_TX_GNT_FIFO_ERROR_SHIFT                                         18
47518     #define NIG_REG_INT_STS_CLR_2_P0_LB_GNT_FIFO_ERROR                                               (0x1<<19) // Error in grant FIFO.
47519     #define NIG_REG_INT_STS_CLR_2_P0_LB_GNT_FIFO_ERROR_SHIFT                                         19
47520 #define NIG_REG_INT_STS_3                                                                            0x500070UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47521     #define NIG_REG_INT_STS_3_P0_TX_PAUSE_TOO_LONG_INT                                               (0x1<<0) // Triggered by TX path being paused for the configured period of time.
47522     #define NIG_REG_INT_STS_3_P0_TX_PAUSE_TOO_LONG_INT_SHIFT                                         0
47523     #define NIG_REG_INT_STS_3_P0_TC0_PAUSE_TOO_LONG_INT                                              (0x1<<1) // Triggered by TC being paused for the configured period of time.
47524     #define NIG_REG_INT_STS_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT                                        1
47525     #define NIG_REG_INT_STS_3_P0_TC1_PAUSE_TOO_LONG_INT                                              (0x1<<2) // Triggered by TC being paused for the configured period of time.
47526     #define NIG_REG_INT_STS_3_P0_TC1_PAUSE_TOO_LONG_INT_SHIFT                                        2
47527     #define NIG_REG_INT_STS_3_P0_TC2_PAUSE_TOO_LONG_INT                                              (0x1<<3) // Triggered by TC being paused for the configured period of time.
47528     #define NIG_REG_INT_STS_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT                                        3
47529     #define NIG_REG_INT_STS_3_P0_TC3_PAUSE_TOO_LONG_INT                                              (0x1<<4) // Triggered by TC being paused for the configured period of time.
47530     #define NIG_REG_INT_STS_3_P0_TC3_PAUSE_TOO_LONG_INT_SHIFT                                        4
47531     #define NIG_REG_INT_STS_3_P0_TC4_PAUSE_TOO_LONG_INT                                              (0x1<<5) // Triggered by TC being paused for the configured period of time.
47532     #define NIG_REG_INT_STS_3_P0_TC4_PAUSE_TOO_LONG_INT_SHIFT                                        5
47533     #define NIG_REG_INT_STS_3_P0_TC5_PAUSE_TOO_LONG_INT                                              (0x1<<6) // Triggered by TC being paused for the configured period of time.
47534     #define NIG_REG_INT_STS_3_P0_TC5_PAUSE_TOO_LONG_INT_SHIFT                                        6
47535     #define NIG_REG_INT_STS_3_P0_TC6_PAUSE_TOO_LONG_INT                                              (0x1<<7) // Triggered by TC being paused for the configured period of time.
47536     #define NIG_REG_INT_STS_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT                                        7
47537     #define NIG_REG_INT_STS_3_P0_TC7_PAUSE_TOO_LONG_INT                                              (0x1<<8) // Triggered by TC being paused for the configured period of time.
47538     #define NIG_REG_INT_STS_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT                                        8
47539     #define NIG_REG_INT_STS_3_P0_LB_TC0_PAUSE_TOO_LONG_INT                                           (0x1<<9) // Triggered by TC being paused for the configured period of time.
47540     #define NIG_REG_INT_STS_3_P0_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                     9
47541     #define NIG_REG_INT_STS_3_P0_LB_TC1_PAUSE_TOO_LONG_INT                                           (0x1<<10) // Triggered by TC being paused for the configured period of time.
47542     #define NIG_REG_INT_STS_3_P0_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                     10
47543     #define NIG_REG_INT_STS_3_P0_LB_TC2_PAUSE_TOO_LONG_INT                                           (0x1<<11) // Triggered by TC being paused for the configured period of time.
47544     #define NIG_REG_INT_STS_3_P0_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                     11
47545     #define NIG_REG_INT_STS_3_P0_LB_TC3_PAUSE_TOO_LONG_INT                                           (0x1<<12) // Triggered by TC being paused for the configured period of time.
47546     #define NIG_REG_INT_STS_3_P0_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                     12
47547     #define NIG_REG_INT_STS_3_P0_LB_TC4_PAUSE_TOO_LONG_INT                                           (0x1<<13) // Triggered by TC being paused for the configured period of time.
47548     #define NIG_REG_INT_STS_3_P0_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                     13
47549     #define NIG_REG_INT_STS_3_P0_LB_TC5_PAUSE_TOO_LONG_INT                                           (0x1<<14) // Triggered by TC being paused for the configured period of time.
47550     #define NIG_REG_INT_STS_3_P0_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                     14
47551     #define NIG_REG_INT_STS_3_P0_LB_TC6_PAUSE_TOO_LONG_INT                                           (0x1<<15) // Triggered by TC being paused for the configured period of time.
47552     #define NIG_REG_INT_STS_3_P0_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                     15
47553     #define NIG_REG_INT_STS_3_P0_LB_TC7_PAUSE_TOO_LONG_INT                                           (0x1<<16) // Triggered by TC being paused for the configured period of time.
47554     #define NIG_REG_INT_STS_3_P0_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                     16
47555     #define NIG_REG_INT_STS_3_P0_LB_TC8_PAUSE_TOO_LONG_INT                                           (0x1<<17) // Triggered by TC being paused for the configured period of time.
47556     #define NIG_REG_INT_STS_3_P0_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                     17
47557 #define NIG_REG_INT_MASK_3                                                                           0x500074UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47558     #define NIG_REG_INT_MASK_3_P0_TX_PAUSE_TOO_LONG_INT                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TX_PAUSE_TOO_LONG_INT .
47559     #define NIG_REG_INT_MASK_3_P0_TX_PAUSE_TOO_LONG_INT_SHIFT                                        0
47560     #define NIG_REG_INT_MASK_3_P0_TC0_PAUSE_TOO_LONG_INT                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC0_PAUSE_TOO_LONG_INT .
47561     #define NIG_REG_INT_MASK_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT                                       1
47562     #define NIG_REG_INT_MASK_3_P0_TC1_PAUSE_TOO_LONG_INT                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC1_PAUSE_TOO_LONG_INT .
47563     #define NIG_REG_INT_MASK_3_P0_TC1_PAUSE_TOO_LONG_INT_SHIFT                                       2
47564     #define NIG_REG_INT_MASK_3_P0_TC2_PAUSE_TOO_LONG_INT                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC2_PAUSE_TOO_LONG_INT .
47565     #define NIG_REG_INT_MASK_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT                                       3
47566     #define NIG_REG_INT_MASK_3_P0_TC3_PAUSE_TOO_LONG_INT                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC3_PAUSE_TOO_LONG_INT .
47567     #define NIG_REG_INT_MASK_3_P0_TC3_PAUSE_TOO_LONG_INT_SHIFT                                       4
47568     #define NIG_REG_INT_MASK_3_P0_TC4_PAUSE_TOO_LONG_INT                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC4_PAUSE_TOO_LONG_INT .
47569     #define NIG_REG_INT_MASK_3_P0_TC4_PAUSE_TOO_LONG_INT_SHIFT                                       5
47570     #define NIG_REG_INT_MASK_3_P0_TC5_PAUSE_TOO_LONG_INT                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC5_PAUSE_TOO_LONG_INT .
47571     #define NIG_REG_INT_MASK_3_P0_TC5_PAUSE_TOO_LONG_INT_SHIFT                                       6
47572     #define NIG_REG_INT_MASK_3_P0_TC6_PAUSE_TOO_LONG_INT                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC6_PAUSE_TOO_LONG_INT .
47573     #define NIG_REG_INT_MASK_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT                                       7
47574     #define NIG_REG_INT_MASK_3_P0_TC7_PAUSE_TOO_LONG_INT                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_TC7_PAUSE_TOO_LONG_INT .
47575     #define NIG_REG_INT_MASK_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT                                       8
47576     #define NIG_REG_INT_MASK_3_P0_LB_TC0_PAUSE_TOO_LONG_INT                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC0_PAUSE_TOO_LONG_INT .
47577     #define NIG_REG_INT_MASK_3_P0_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                    9
47578     #define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC1_PAUSE_TOO_LONG_INT .
47579     #define NIG_REG_INT_MASK_3_P0_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                    10
47580     #define NIG_REG_INT_MASK_3_P0_LB_TC2_PAUSE_TOO_LONG_INT                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC2_PAUSE_TOO_LONG_INT .
47581     #define NIG_REG_INT_MASK_3_P0_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                    11
47582     #define NIG_REG_INT_MASK_3_P0_LB_TC3_PAUSE_TOO_LONG_INT                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC3_PAUSE_TOO_LONG_INT .
47583     #define NIG_REG_INT_MASK_3_P0_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                    12
47584     #define NIG_REG_INT_MASK_3_P0_LB_TC4_PAUSE_TOO_LONG_INT                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC4_PAUSE_TOO_LONG_INT .
47585     #define NIG_REG_INT_MASK_3_P0_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                    13
47586     #define NIG_REG_INT_MASK_3_P0_LB_TC5_PAUSE_TOO_LONG_INT                                          (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC5_PAUSE_TOO_LONG_INT .
47587     #define NIG_REG_INT_MASK_3_P0_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                    14
47588     #define NIG_REG_INT_MASK_3_P0_LB_TC6_PAUSE_TOO_LONG_INT                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC6_PAUSE_TOO_LONG_INT .
47589     #define NIG_REG_INT_MASK_3_P0_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                    15
47590     #define NIG_REG_INT_MASK_3_P0_LB_TC7_PAUSE_TOO_LONG_INT                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC7_PAUSE_TOO_LONG_INT .
47591     #define NIG_REG_INT_MASK_3_P0_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                    16
47592     #define NIG_REG_INT_MASK_3_P0_LB_TC8_PAUSE_TOO_LONG_INT                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_3.P0_LB_TC8_PAUSE_TOO_LONG_INT .
47593     #define NIG_REG_INT_MASK_3_P0_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                    17
47594 #define NIG_REG_INT_STS_WR_3                                                                         0x500078UL //Access:WR   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47595     #define NIG_REG_INT_STS_WR_3_P0_TX_PAUSE_TOO_LONG_INT                                            (0x1<<0) // Triggered by TX path being paused for the configured period of time.
47596     #define NIG_REG_INT_STS_WR_3_P0_TX_PAUSE_TOO_LONG_INT_SHIFT                                      0
47597     #define NIG_REG_INT_STS_WR_3_P0_TC0_PAUSE_TOO_LONG_INT                                           (0x1<<1) // Triggered by TC being paused for the configured period of time.
47598     #define NIG_REG_INT_STS_WR_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT                                     1
47599     #define NIG_REG_INT_STS_WR_3_P0_TC1_PAUSE_TOO_LONG_INT                                           (0x1<<2) // Triggered by TC being paused for the configured period of time.
47600     #define NIG_REG_INT_STS_WR_3_P0_TC1_PAUSE_TOO_LONG_INT_SHIFT                                     2
47601     #define NIG_REG_INT_STS_WR_3_P0_TC2_PAUSE_TOO_LONG_INT                                           (0x1<<3) // Triggered by TC being paused for the configured period of time.
47602     #define NIG_REG_INT_STS_WR_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT                                     3
47603     #define NIG_REG_INT_STS_WR_3_P0_TC3_PAUSE_TOO_LONG_INT                                           (0x1<<4) // Triggered by TC being paused for the configured period of time.
47604     #define NIG_REG_INT_STS_WR_3_P0_TC3_PAUSE_TOO_LONG_INT_SHIFT                                     4
47605     #define NIG_REG_INT_STS_WR_3_P0_TC4_PAUSE_TOO_LONG_INT                                           (0x1<<5) // Triggered by TC being paused for the configured period of time.
47606     #define NIG_REG_INT_STS_WR_3_P0_TC4_PAUSE_TOO_LONG_INT_SHIFT                                     5
47607     #define NIG_REG_INT_STS_WR_3_P0_TC5_PAUSE_TOO_LONG_INT                                           (0x1<<6) // Triggered by TC being paused for the configured period of time.
47608     #define NIG_REG_INT_STS_WR_3_P0_TC5_PAUSE_TOO_LONG_INT_SHIFT                                     6
47609     #define NIG_REG_INT_STS_WR_3_P0_TC6_PAUSE_TOO_LONG_INT                                           (0x1<<7) // Triggered by TC being paused for the configured period of time.
47610     #define NIG_REG_INT_STS_WR_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT                                     7
47611     #define NIG_REG_INT_STS_WR_3_P0_TC7_PAUSE_TOO_LONG_INT                                           (0x1<<8) // Triggered by TC being paused for the configured period of time.
47612     #define NIG_REG_INT_STS_WR_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT                                     8
47613     #define NIG_REG_INT_STS_WR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT                                        (0x1<<9) // Triggered by TC being paused for the configured period of time.
47614     #define NIG_REG_INT_STS_WR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                  9
47615     #define NIG_REG_INT_STS_WR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT                                        (0x1<<10) // Triggered by TC being paused for the configured period of time.
47616     #define NIG_REG_INT_STS_WR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                  10
47617     #define NIG_REG_INT_STS_WR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT                                        (0x1<<11) // Triggered by TC being paused for the configured period of time.
47618     #define NIG_REG_INT_STS_WR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                  11
47619     #define NIG_REG_INT_STS_WR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT                                        (0x1<<12) // Triggered by TC being paused for the configured period of time.
47620     #define NIG_REG_INT_STS_WR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                  12
47621     #define NIG_REG_INT_STS_WR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT                                        (0x1<<13) // Triggered by TC being paused for the configured period of time.
47622     #define NIG_REG_INT_STS_WR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                  13
47623     #define NIG_REG_INT_STS_WR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT                                        (0x1<<14) // Triggered by TC being paused for the configured period of time.
47624     #define NIG_REG_INT_STS_WR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                  14
47625     #define NIG_REG_INT_STS_WR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT                                        (0x1<<15) // Triggered by TC being paused for the configured period of time.
47626     #define NIG_REG_INT_STS_WR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                  15
47627     #define NIG_REG_INT_STS_WR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT                                        (0x1<<16) // Triggered by TC being paused for the configured period of time.
47628     #define NIG_REG_INT_STS_WR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                  16
47629     #define NIG_REG_INT_STS_WR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT                                        (0x1<<17) // Triggered by TC being paused for the configured period of time.
47630     #define NIG_REG_INT_STS_WR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                  17
47631 #define NIG_REG_INT_STS_CLR_3                                                                        0x50007cUL //Access:RC   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47632     #define NIG_REG_INT_STS_CLR_3_P0_TX_PAUSE_TOO_LONG_INT                                           (0x1<<0) // Triggered by TX path being paused for the configured period of time.
47633     #define NIG_REG_INT_STS_CLR_3_P0_TX_PAUSE_TOO_LONG_INT_SHIFT                                     0
47634     #define NIG_REG_INT_STS_CLR_3_P0_TC0_PAUSE_TOO_LONG_INT                                          (0x1<<1) // Triggered by TC being paused for the configured period of time.
47635     #define NIG_REG_INT_STS_CLR_3_P0_TC0_PAUSE_TOO_LONG_INT_SHIFT                                    1
47636     #define NIG_REG_INT_STS_CLR_3_P0_TC1_PAUSE_TOO_LONG_INT                                          (0x1<<2) // Triggered by TC being paused for the configured period of time.
47637     #define NIG_REG_INT_STS_CLR_3_P0_TC1_PAUSE_TOO_LONG_INT_SHIFT                                    2
47638     #define NIG_REG_INT_STS_CLR_3_P0_TC2_PAUSE_TOO_LONG_INT                                          (0x1<<3) // Triggered by TC being paused for the configured period of time.
47639     #define NIG_REG_INT_STS_CLR_3_P0_TC2_PAUSE_TOO_LONG_INT_SHIFT                                    3
47640     #define NIG_REG_INT_STS_CLR_3_P0_TC3_PAUSE_TOO_LONG_INT                                          (0x1<<4) // Triggered by TC being paused for the configured period of time.
47641     #define NIG_REG_INT_STS_CLR_3_P0_TC3_PAUSE_TOO_LONG_INT_SHIFT                                    4
47642     #define NIG_REG_INT_STS_CLR_3_P0_TC4_PAUSE_TOO_LONG_INT                                          (0x1<<5) // Triggered by TC being paused for the configured period of time.
47643     #define NIG_REG_INT_STS_CLR_3_P0_TC4_PAUSE_TOO_LONG_INT_SHIFT                                    5
47644     #define NIG_REG_INT_STS_CLR_3_P0_TC5_PAUSE_TOO_LONG_INT                                          (0x1<<6) // Triggered by TC being paused for the configured period of time.
47645     #define NIG_REG_INT_STS_CLR_3_P0_TC5_PAUSE_TOO_LONG_INT_SHIFT                                    6
47646     #define NIG_REG_INT_STS_CLR_3_P0_TC6_PAUSE_TOO_LONG_INT                                          (0x1<<7) // Triggered by TC being paused for the configured period of time.
47647     #define NIG_REG_INT_STS_CLR_3_P0_TC6_PAUSE_TOO_LONG_INT_SHIFT                                    7
47648     #define NIG_REG_INT_STS_CLR_3_P0_TC7_PAUSE_TOO_LONG_INT                                          (0x1<<8) // Triggered by TC being paused for the configured period of time.
47649     #define NIG_REG_INT_STS_CLR_3_P0_TC7_PAUSE_TOO_LONG_INT_SHIFT                                    8
47650     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT                                       (0x1<<9) // Triggered by TC being paused for the configured period of time.
47651     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                 9
47652     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT                                       (0x1<<10) // Triggered by TC being paused for the configured period of time.
47653     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                 10
47654     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT                                       (0x1<<11) // Triggered by TC being paused for the configured period of time.
47655     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                 11
47656     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT                                       (0x1<<12) // Triggered by TC being paused for the configured period of time.
47657     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                 12
47658     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT                                       (0x1<<13) // Triggered by TC being paused for the configured period of time.
47659     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                 13
47660     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT                                       (0x1<<14) // Triggered by TC being paused for the configured period of time.
47661     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                 14
47662     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT                                       (0x1<<15) // Triggered by TC being paused for the configured period of time.
47663     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                 15
47664     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT                                       (0x1<<16) // Triggered by TC being paused for the configured period of time.
47665     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                 16
47666     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT                                       (0x1<<17) // Triggered by TC being paused for the configured period of time.
47667     #define NIG_REG_INT_STS_CLR_3_P0_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                 17
47668 #define NIG_REG_INT_STS_4                                                                            0x500080UL //Access:R    DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47669     #define NIG_REG_INT_STS_4_P1_PURELB_SOPQ_ERROR                                                   (0x1<<0) // Error in the pure-loopback SOPQ.
47670     #define NIG_REG_INT_STS_4_P1_PURELB_SOPQ_ERROR_SHIFT                                             0
47671     #define NIG_REG_INT_STS_4_P1_RX_MACFIFO_ERROR                                                    (0x1<<1) // Error in RX MAC FIFO.
47672     #define NIG_REG_INT_STS_4_P1_RX_MACFIFO_ERROR_SHIFT                                              1
47673     #define NIG_REG_INT_STS_4_P1_TX_MACFIFO_ERROR                                                    (0x1<<2) // Error in TX MAC FIFO.
47674     #define NIG_REG_INT_STS_4_P1_TX_MACFIFO_ERROR_SHIFT                                              2
47675     #define NIG_REG_INT_STS_4_P1_TX_BMB_FIFO_ERROR                                                   (0x1<<3) // FIFO error in TX BMB FIFO.
47676     #define NIG_REG_INT_STS_4_P1_TX_BMB_FIFO_ERROR_SHIFT                                             3
47677     #define NIG_REG_INT_STS_4_P1_LB_BMB_FIFO_ERROR                                                   (0x1<<4) // FIFO error in LB BMB FIFO.
47678     #define NIG_REG_INT_STS_4_P1_LB_BMB_FIFO_ERROR_SHIFT                                             4
47679     #define NIG_REG_INT_STS_4_P1_TX_BTB_FIFO_ERROR                                                   (0x1<<5) // Error in BTB FIFO for TX path.
47680     #define NIG_REG_INT_STS_4_P1_TX_BTB_FIFO_ERROR_SHIFT                                             5
47681     #define NIG_REG_INT_STS_4_P1_LB_BTB_FIFO_ERROR                                                   (0x1<<6) // Error in BTB FIFO for LB path.
47682     #define NIG_REG_INT_STS_4_P1_LB_BTB_FIFO_ERROR_SHIFT                                             6
47683     #define NIG_REG_INT_STS_4_P1_RX_LLH_DFIFO_ERROR                                                  (0x1<<7) // Error in LLH Data FIFO.
47684     #define NIG_REG_INT_STS_4_P1_RX_LLH_DFIFO_ERROR_SHIFT                                            7
47685     #define NIG_REG_INT_STS_4_P1_TX_LLH_DFIFO_ERROR                                                  (0x1<<8) // Error in LLH Data FIFO.
47686     #define NIG_REG_INT_STS_4_P1_TX_LLH_DFIFO_ERROR_SHIFT                                            8
47687     #define NIG_REG_INT_STS_4_P1_LB_LLH_DFIFO_ERROR                                                  (0x1<<9) // Error in LLH Data FIFO.
47688     #define NIG_REG_INT_STS_4_P1_LB_LLH_DFIFO_ERROR_SHIFT                                            9
47689     #define NIG_REG_INT_STS_4_P1_RX_LLH_HFIFO_ERROR                                                  (0x1<<10) // Error in LLH Header FIFO.
47690     #define NIG_REG_INT_STS_4_P1_RX_LLH_HFIFO_ERROR_SHIFT                                            10
47691     #define NIG_REG_INT_STS_4_P1_TX_LLH_HFIFO_ERROR                                                  (0x1<<11) // Error in LLH Header FIFO.
47692     #define NIG_REG_INT_STS_4_P1_TX_LLH_HFIFO_ERROR_SHIFT                                            11
47693     #define NIG_REG_INT_STS_4_P1_LB_LLH_HFIFO_ERROR                                                  (0x1<<12) // Error in LLH Header FIFO.
47694     #define NIG_REG_INT_STS_4_P1_LB_LLH_HFIFO_ERROR_SHIFT                                            12
47695     #define NIG_REG_INT_STS_4_P1_RX_LLH_RFIFO_ERROR                                                  (0x1<<13) // Error in LLH Result FIFO.
47696     #define NIG_REG_INT_STS_4_P1_RX_LLH_RFIFO_ERROR_SHIFT                                            13
47697     #define NIG_REG_INT_STS_4_P1_TX_LLH_RFIFO_ERROR                                                  (0x1<<14) // Error in LLH Result FIFO.
47698     #define NIG_REG_INT_STS_4_P1_TX_LLH_RFIFO_ERROR_SHIFT                                            14
47699     #define NIG_REG_INT_STS_4_P1_LB_LLH_RFIFO_ERROR                                                  (0x1<<15) // Error in LLH Result FIFO.
47700     #define NIG_REG_INT_STS_4_P1_LB_LLH_RFIFO_ERROR_SHIFT                                            15
47701     #define NIG_REG_INT_STS_4_P1_STORM_FIFO_ERROR                                                    (0x1<<16) // FIFO error in STORM message FIFO.
47702     #define NIG_REG_INT_STS_4_P1_STORM_FIFO_ERROR_SHIFT                                              16
47703     #define NIG_REG_INT_STS_4_P1_STORM_DSCR_FIFO_ERROR                                               (0x1<<17) // FIFO error in STORM descriptor FIFO.
47704     #define NIG_REG_INT_STS_4_P1_STORM_DSCR_FIFO_ERROR_SHIFT                                         17
47705     #define NIG_REG_INT_STS_4_P1_TX_GNT_FIFO_ERROR                                                   (0x1<<18) // Error in grant FIFO.
47706     #define NIG_REG_INT_STS_4_P1_TX_GNT_FIFO_ERROR_SHIFT                                             18
47707     #define NIG_REG_INT_STS_4_P1_LB_GNT_FIFO_ERROR                                                   (0x1<<19) // Error in grant FIFO.
47708     #define NIG_REG_INT_STS_4_P1_LB_GNT_FIFO_ERROR_SHIFT                                             19
47709 #define NIG_REG_INT_MASK_4                                                                           0x500084UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47710     #define NIG_REG_INT_MASK_4_P1_PURELB_SOPQ_ERROR                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_PURELB_SOPQ_ERROR .
47711     #define NIG_REG_INT_MASK_4_P1_PURELB_SOPQ_ERROR_SHIFT                                            0
47712     #define NIG_REG_INT_MASK_4_P1_RX_MACFIFO_ERROR                                                   (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_MACFIFO_ERROR .
47713     #define NIG_REG_INT_MASK_4_P1_RX_MACFIFO_ERROR_SHIFT                                             1
47714     #define NIG_REG_INT_MASK_4_P1_TX_MACFIFO_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_MACFIFO_ERROR .
47715     #define NIG_REG_INT_MASK_4_P1_TX_MACFIFO_ERROR_SHIFT                                             2
47716     #define NIG_REG_INT_MASK_4_P1_TX_BMB_FIFO_ERROR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_BMB_FIFO_ERROR .
47717     #define NIG_REG_INT_MASK_4_P1_TX_BMB_FIFO_ERROR_SHIFT                                            3
47718     #define NIG_REG_INT_MASK_4_P1_LB_BMB_FIFO_ERROR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_BMB_FIFO_ERROR .
47719     #define NIG_REG_INT_MASK_4_P1_LB_BMB_FIFO_ERROR_SHIFT                                            4
47720     #define NIG_REG_INT_MASK_4_P1_TX_BTB_FIFO_ERROR                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_BTB_FIFO_ERROR .
47721     #define NIG_REG_INT_MASK_4_P1_TX_BTB_FIFO_ERROR_SHIFT                                            5
47722     #define NIG_REG_INT_MASK_4_P1_LB_BTB_FIFO_ERROR                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_BTB_FIFO_ERROR .
47723     #define NIG_REG_INT_MASK_4_P1_LB_BTB_FIFO_ERROR_SHIFT                                            6
47724     #define NIG_REG_INT_MASK_4_P1_RX_LLH_DFIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_DFIFO_ERROR .
47725     #define NIG_REG_INT_MASK_4_P1_RX_LLH_DFIFO_ERROR_SHIFT                                           7
47726     #define NIG_REG_INT_MASK_4_P1_TX_LLH_DFIFO_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_DFIFO_ERROR .
47727     #define NIG_REG_INT_MASK_4_P1_TX_LLH_DFIFO_ERROR_SHIFT                                           8
47728     #define NIG_REG_INT_MASK_4_P1_LB_LLH_DFIFO_ERROR                                                 (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_DFIFO_ERROR .
47729     #define NIG_REG_INT_MASK_4_P1_LB_LLH_DFIFO_ERROR_SHIFT                                           9
47730     #define NIG_REG_INT_MASK_4_P1_RX_LLH_HFIFO_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_HFIFO_ERROR .
47731     #define NIG_REG_INT_MASK_4_P1_RX_LLH_HFIFO_ERROR_SHIFT                                           10
47732     #define NIG_REG_INT_MASK_4_P1_TX_LLH_HFIFO_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_HFIFO_ERROR .
47733     #define NIG_REG_INT_MASK_4_P1_TX_LLH_HFIFO_ERROR_SHIFT                                           11
47734     #define NIG_REG_INT_MASK_4_P1_LB_LLH_HFIFO_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_HFIFO_ERROR .
47735     #define NIG_REG_INT_MASK_4_P1_LB_LLH_HFIFO_ERROR_SHIFT                                           12
47736     #define NIG_REG_INT_MASK_4_P1_RX_LLH_RFIFO_ERROR                                                 (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_RX_LLH_RFIFO_ERROR .
47737     #define NIG_REG_INT_MASK_4_P1_RX_LLH_RFIFO_ERROR_SHIFT                                           13
47738     #define NIG_REG_INT_MASK_4_P1_TX_LLH_RFIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_LLH_RFIFO_ERROR .
47739     #define NIG_REG_INT_MASK_4_P1_TX_LLH_RFIFO_ERROR_SHIFT                                           14
47740     #define NIG_REG_INT_MASK_4_P1_LB_LLH_RFIFO_ERROR                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_LLH_RFIFO_ERROR .
47741     #define NIG_REG_INT_MASK_4_P1_LB_LLH_RFIFO_ERROR_SHIFT                                           15
47742     #define NIG_REG_INT_MASK_4_P1_STORM_FIFO_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_STORM_FIFO_ERROR .
47743     #define NIG_REG_INT_MASK_4_P1_STORM_FIFO_ERROR_SHIFT                                             16
47744     #define NIG_REG_INT_MASK_4_P1_STORM_DSCR_FIFO_ERROR                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_STORM_DSCR_FIFO_ERROR .
47745     #define NIG_REG_INT_MASK_4_P1_STORM_DSCR_FIFO_ERROR_SHIFT                                        17
47746     #define NIG_REG_INT_MASK_4_P1_TX_GNT_FIFO_ERROR                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_TX_GNT_FIFO_ERROR .
47747     #define NIG_REG_INT_MASK_4_P1_TX_GNT_FIFO_ERROR_SHIFT                                            18
47748     #define NIG_REG_INT_MASK_4_P1_LB_GNT_FIFO_ERROR                                                  (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_4.P1_LB_GNT_FIFO_ERROR .
47749     #define NIG_REG_INT_MASK_4_P1_LB_GNT_FIFO_ERROR_SHIFT                                            19
47750 #define NIG_REG_INT_STS_WR_4                                                                         0x500088UL //Access:WR   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47751     #define NIG_REG_INT_STS_WR_4_P1_PURELB_SOPQ_ERROR                                                (0x1<<0) // Error in the pure-loopback SOPQ.
47752     #define NIG_REG_INT_STS_WR_4_P1_PURELB_SOPQ_ERROR_SHIFT                                          0
47753     #define NIG_REG_INT_STS_WR_4_P1_RX_MACFIFO_ERROR                                                 (0x1<<1) // Error in RX MAC FIFO.
47754     #define NIG_REG_INT_STS_WR_4_P1_RX_MACFIFO_ERROR_SHIFT                                           1
47755     #define NIG_REG_INT_STS_WR_4_P1_TX_MACFIFO_ERROR                                                 (0x1<<2) // Error in TX MAC FIFO.
47756     #define NIG_REG_INT_STS_WR_4_P1_TX_MACFIFO_ERROR_SHIFT                                           2
47757     #define NIG_REG_INT_STS_WR_4_P1_TX_BMB_FIFO_ERROR                                                (0x1<<3) // FIFO error in TX BMB FIFO.
47758     #define NIG_REG_INT_STS_WR_4_P1_TX_BMB_FIFO_ERROR_SHIFT                                          3
47759     #define NIG_REG_INT_STS_WR_4_P1_LB_BMB_FIFO_ERROR                                                (0x1<<4) // FIFO error in LB BMB FIFO.
47760     #define NIG_REG_INT_STS_WR_4_P1_LB_BMB_FIFO_ERROR_SHIFT                                          4
47761     #define NIG_REG_INT_STS_WR_4_P1_TX_BTB_FIFO_ERROR                                                (0x1<<5) // Error in BTB FIFO for TX path.
47762     #define NIG_REG_INT_STS_WR_4_P1_TX_BTB_FIFO_ERROR_SHIFT                                          5
47763     #define NIG_REG_INT_STS_WR_4_P1_LB_BTB_FIFO_ERROR                                                (0x1<<6) // Error in BTB FIFO for LB path.
47764     #define NIG_REG_INT_STS_WR_4_P1_LB_BTB_FIFO_ERROR_SHIFT                                          6
47765     #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_DFIFO_ERROR                                               (0x1<<7) // Error in LLH Data FIFO.
47766     #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_DFIFO_ERROR_SHIFT                                         7
47767     #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_DFIFO_ERROR                                               (0x1<<8) // Error in LLH Data FIFO.
47768     #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_DFIFO_ERROR_SHIFT                                         8
47769     #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_DFIFO_ERROR                                               (0x1<<9) // Error in LLH Data FIFO.
47770     #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_DFIFO_ERROR_SHIFT                                         9
47771     #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_HFIFO_ERROR                                               (0x1<<10) // Error in LLH Header FIFO.
47772     #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_HFIFO_ERROR_SHIFT                                         10
47773     #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_HFIFO_ERROR                                               (0x1<<11) // Error in LLH Header FIFO.
47774     #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_HFIFO_ERROR_SHIFT                                         11
47775     #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_HFIFO_ERROR                                               (0x1<<12) // Error in LLH Header FIFO.
47776     #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_HFIFO_ERROR_SHIFT                                         12
47777     #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_RFIFO_ERROR                                               (0x1<<13) // Error in LLH Result FIFO.
47778     #define NIG_REG_INT_STS_WR_4_P1_RX_LLH_RFIFO_ERROR_SHIFT                                         13
47779     #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_RFIFO_ERROR                                               (0x1<<14) // Error in LLH Result FIFO.
47780     #define NIG_REG_INT_STS_WR_4_P1_TX_LLH_RFIFO_ERROR_SHIFT                                         14
47781     #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_RFIFO_ERROR                                               (0x1<<15) // Error in LLH Result FIFO.
47782     #define NIG_REG_INT_STS_WR_4_P1_LB_LLH_RFIFO_ERROR_SHIFT                                         15
47783     #define NIG_REG_INT_STS_WR_4_P1_STORM_FIFO_ERROR                                                 (0x1<<16) // FIFO error in STORM message FIFO.
47784     #define NIG_REG_INT_STS_WR_4_P1_STORM_FIFO_ERROR_SHIFT                                           16
47785     #define NIG_REG_INT_STS_WR_4_P1_STORM_DSCR_FIFO_ERROR                                            (0x1<<17) // FIFO error in STORM descriptor FIFO.
47786     #define NIG_REG_INT_STS_WR_4_P1_STORM_DSCR_FIFO_ERROR_SHIFT                                      17
47787     #define NIG_REG_INT_STS_WR_4_P1_TX_GNT_FIFO_ERROR                                                (0x1<<18) // Error in grant FIFO.
47788     #define NIG_REG_INT_STS_WR_4_P1_TX_GNT_FIFO_ERROR_SHIFT                                          18
47789     #define NIG_REG_INT_STS_WR_4_P1_LB_GNT_FIFO_ERROR                                                (0x1<<19) // Error in grant FIFO.
47790     #define NIG_REG_INT_STS_WR_4_P1_LB_GNT_FIFO_ERROR_SHIFT                                          19
47791 #define NIG_REG_INT_STS_CLR_4                                                                        0x50008cUL //Access:RC   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47792     #define NIG_REG_INT_STS_CLR_4_P1_PURELB_SOPQ_ERROR                                               (0x1<<0) // Error in the pure-loopback SOPQ.
47793     #define NIG_REG_INT_STS_CLR_4_P1_PURELB_SOPQ_ERROR_SHIFT                                         0
47794     #define NIG_REG_INT_STS_CLR_4_P1_RX_MACFIFO_ERROR                                                (0x1<<1) // Error in RX MAC FIFO.
47795     #define NIG_REG_INT_STS_CLR_4_P1_RX_MACFIFO_ERROR_SHIFT                                          1
47796     #define NIG_REG_INT_STS_CLR_4_P1_TX_MACFIFO_ERROR                                                (0x1<<2) // Error in TX MAC FIFO.
47797     #define NIG_REG_INT_STS_CLR_4_P1_TX_MACFIFO_ERROR_SHIFT                                          2
47798     #define NIG_REG_INT_STS_CLR_4_P1_TX_BMB_FIFO_ERROR                                               (0x1<<3) // FIFO error in TX BMB FIFO.
47799     #define NIG_REG_INT_STS_CLR_4_P1_TX_BMB_FIFO_ERROR_SHIFT                                         3
47800     #define NIG_REG_INT_STS_CLR_4_P1_LB_BMB_FIFO_ERROR                                               (0x1<<4) // FIFO error in LB BMB FIFO.
47801     #define NIG_REG_INT_STS_CLR_4_P1_LB_BMB_FIFO_ERROR_SHIFT                                         4
47802     #define NIG_REG_INT_STS_CLR_4_P1_TX_BTB_FIFO_ERROR                                               (0x1<<5) // Error in BTB FIFO for TX path.
47803     #define NIG_REG_INT_STS_CLR_4_P1_TX_BTB_FIFO_ERROR_SHIFT                                         5
47804     #define NIG_REG_INT_STS_CLR_4_P1_LB_BTB_FIFO_ERROR                                               (0x1<<6) // Error in BTB FIFO for LB path.
47805     #define NIG_REG_INT_STS_CLR_4_P1_LB_BTB_FIFO_ERROR_SHIFT                                         6
47806     #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_DFIFO_ERROR                                              (0x1<<7) // Error in LLH Data FIFO.
47807     #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_DFIFO_ERROR_SHIFT                                        7
47808     #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_DFIFO_ERROR                                              (0x1<<8) // Error in LLH Data FIFO.
47809     #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_DFIFO_ERROR_SHIFT                                        8
47810     #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_DFIFO_ERROR                                              (0x1<<9) // Error in LLH Data FIFO.
47811     #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_DFIFO_ERROR_SHIFT                                        9
47812     #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_HFIFO_ERROR                                              (0x1<<10) // Error in LLH Header FIFO.
47813     #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_HFIFO_ERROR_SHIFT                                        10
47814     #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_HFIFO_ERROR                                              (0x1<<11) // Error in LLH Header FIFO.
47815     #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_HFIFO_ERROR_SHIFT                                        11
47816     #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_HFIFO_ERROR                                              (0x1<<12) // Error in LLH Header FIFO.
47817     #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_HFIFO_ERROR_SHIFT                                        12
47818     #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_RFIFO_ERROR                                              (0x1<<13) // Error in LLH Result FIFO.
47819     #define NIG_REG_INT_STS_CLR_4_P1_RX_LLH_RFIFO_ERROR_SHIFT                                        13
47820     #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_RFIFO_ERROR                                              (0x1<<14) // Error in LLH Result FIFO.
47821     #define NIG_REG_INT_STS_CLR_4_P1_TX_LLH_RFIFO_ERROR_SHIFT                                        14
47822     #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_RFIFO_ERROR                                              (0x1<<15) // Error in LLH Result FIFO.
47823     #define NIG_REG_INT_STS_CLR_4_P1_LB_LLH_RFIFO_ERROR_SHIFT                                        15
47824     #define NIG_REG_INT_STS_CLR_4_P1_STORM_FIFO_ERROR                                                (0x1<<16) // FIFO error in STORM message FIFO.
47825     #define NIG_REG_INT_STS_CLR_4_P1_STORM_FIFO_ERROR_SHIFT                                          16
47826     #define NIG_REG_INT_STS_CLR_4_P1_STORM_DSCR_FIFO_ERROR                                           (0x1<<17) // FIFO error in STORM descriptor FIFO.
47827     #define NIG_REG_INT_STS_CLR_4_P1_STORM_DSCR_FIFO_ERROR_SHIFT                                     17
47828     #define NIG_REG_INT_STS_CLR_4_P1_TX_GNT_FIFO_ERROR                                               (0x1<<18) // Error in grant FIFO.
47829     #define NIG_REG_INT_STS_CLR_4_P1_TX_GNT_FIFO_ERROR_SHIFT                                         18
47830     #define NIG_REG_INT_STS_CLR_4_P1_LB_GNT_FIFO_ERROR                                               (0x1<<19) // Error in grant FIFO.
47831     #define NIG_REG_INT_STS_CLR_4_P1_LB_GNT_FIFO_ERROR_SHIFT                                         19
47832 #define NIG_REG_INT_STS_5                                                                            0x500090UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47833     #define NIG_REG_INT_STS_5_P1_TX_PAUSE_TOO_LONG_INT                                               (0x1<<0) // Triggered by TX path being paused for the configured period of time.
47834     #define NIG_REG_INT_STS_5_P1_TX_PAUSE_TOO_LONG_INT_SHIFT                                         0
47835     #define NIG_REG_INT_STS_5_P1_TC0_PAUSE_TOO_LONG_INT                                              (0x1<<1) // Triggered by TC being paused for the configured period of time.
47836     #define NIG_REG_INT_STS_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT                                        1
47837     #define NIG_REG_INT_STS_5_P1_TC1_PAUSE_TOO_LONG_INT                                              (0x1<<2) // Triggered by TC being paused for the configured period of time.
47838     #define NIG_REG_INT_STS_5_P1_TC1_PAUSE_TOO_LONG_INT_SHIFT                                        2
47839     #define NIG_REG_INT_STS_5_P1_TC2_PAUSE_TOO_LONG_INT                                              (0x1<<3) // Triggered by TC being paused for the configured period of time.
47840     #define NIG_REG_INT_STS_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT                                        3
47841     #define NIG_REG_INT_STS_5_P1_TC3_PAUSE_TOO_LONG_INT                                              (0x1<<4) // Triggered by TC being paused for the configured period of time.
47842     #define NIG_REG_INT_STS_5_P1_TC3_PAUSE_TOO_LONG_INT_SHIFT                                        4
47843     #define NIG_REG_INT_STS_5_P1_TC4_PAUSE_TOO_LONG_INT                                              (0x1<<5) // Triggered by TC being paused for the configured period of time.
47844     #define NIG_REG_INT_STS_5_P1_TC4_PAUSE_TOO_LONG_INT_SHIFT                                        5
47845     #define NIG_REG_INT_STS_5_P1_TC5_PAUSE_TOO_LONG_INT                                              (0x1<<6) // Triggered by TC being paused for the configured period of time.
47846     #define NIG_REG_INT_STS_5_P1_TC5_PAUSE_TOO_LONG_INT_SHIFT                                        6
47847     #define NIG_REG_INT_STS_5_P1_TC6_PAUSE_TOO_LONG_INT                                              (0x1<<7) // Triggered by TC being paused for the configured period of time.
47848     #define NIG_REG_INT_STS_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT                                        7
47849     #define NIG_REG_INT_STS_5_P1_TC7_PAUSE_TOO_LONG_INT                                              (0x1<<8) // Triggered by TC being paused for the configured period of time.
47850     #define NIG_REG_INT_STS_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT                                        8
47851     #define NIG_REG_INT_STS_5_P1_LB_TC0_PAUSE_TOO_LONG_INT                                           (0x1<<9) // Triggered by TC being paused for the configured period of time.
47852     #define NIG_REG_INT_STS_5_P1_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                     9
47853     #define NIG_REG_INT_STS_5_P1_LB_TC1_PAUSE_TOO_LONG_INT                                           (0x1<<10) // Triggered by TC being paused for the configured period of time.
47854     #define NIG_REG_INT_STS_5_P1_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                     10
47855     #define NIG_REG_INT_STS_5_P1_LB_TC2_PAUSE_TOO_LONG_INT                                           (0x1<<11) // Triggered by TC being paused for the configured period of time.
47856     #define NIG_REG_INT_STS_5_P1_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                     11
47857     #define NIG_REG_INT_STS_5_P1_LB_TC3_PAUSE_TOO_LONG_INT                                           (0x1<<12) // Triggered by TC being paused for the configured period of time.
47858     #define NIG_REG_INT_STS_5_P1_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                     12
47859     #define NIG_REG_INT_STS_5_P1_LB_TC4_PAUSE_TOO_LONG_INT                                           (0x1<<13) // Triggered by TC being paused for the configured period of time.
47860     #define NIG_REG_INT_STS_5_P1_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                     13
47861     #define NIG_REG_INT_STS_5_P1_LB_TC5_PAUSE_TOO_LONG_INT                                           (0x1<<14) // Triggered by TC being paused for the configured period of time.
47862     #define NIG_REG_INT_STS_5_P1_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                     14
47863     #define NIG_REG_INT_STS_5_P1_LB_TC6_PAUSE_TOO_LONG_INT                                           (0x1<<15) // Triggered by TC being paused for the configured period of time.
47864     #define NIG_REG_INT_STS_5_P1_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                     15
47865     #define NIG_REG_INT_STS_5_P1_LB_TC7_PAUSE_TOO_LONG_INT                                           (0x1<<16) // Triggered by TC being paused for the configured period of time.
47866     #define NIG_REG_INT_STS_5_P1_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                     16
47867     #define NIG_REG_INT_STS_5_P1_LB_TC8_PAUSE_TOO_LONG_INT                                           (0x1<<17) // Triggered by TC being paused for the configured period of time.
47868     #define NIG_REG_INT_STS_5_P1_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                     17
47869 #define NIG_REG_INT_MASK_5                                                                           0x500094UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47870     #define NIG_REG_INT_MASK_5_P1_TX_PAUSE_TOO_LONG_INT                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TX_PAUSE_TOO_LONG_INT .
47871     #define NIG_REG_INT_MASK_5_P1_TX_PAUSE_TOO_LONG_INT_SHIFT                                        0
47872     #define NIG_REG_INT_MASK_5_P1_TC0_PAUSE_TOO_LONG_INT                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC0_PAUSE_TOO_LONG_INT .
47873     #define NIG_REG_INT_MASK_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT                                       1
47874     #define NIG_REG_INT_MASK_5_P1_TC1_PAUSE_TOO_LONG_INT                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC1_PAUSE_TOO_LONG_INT .
47875     #define NIG_REG_INT_MASK_5_P1_TC1_PAUSE_TOO_LONG_INT_SHIFT                                       2
47876     #define NIG_REG_INT_MASK_5_P1_TC2_PAUSE_TOO_LONG_INT                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC2_PAUSE_TOO_LONG_INT .
47877     #define NIG_REG_INT_MASK_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT                                       3
47878     #define NIG_REG_INT_MASK_5_P1_TC3_PAUSE_TOO_LONG_INT                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC3_PAUSE_TOO_LONG_INT .
47879     #define NIG_REG_INT_MASK_5_P1_TC3_PAUSE_TOO_LONG_INT_SHIFT                                       4
47880     #define NIG_REG_INT_MASK_5_P1_TC4_PAUSE_TOO_LONG_INT                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC4_PAUSE_TOO_LONG_INT .
47881     #define NIG_REG_INT_MASK_5_P1_TC4_PAUSE_TOO_LONG_INT_SHIFT                                       5
47882     #define NIG_REG_INT_MASK_5_P1_TC5_PAUSE_TOO_LONG_INT                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC5_PAUSE_TOO_LONG_INT .
47883     #define NIG_REG_INT_MASK_5_P1_TC5_PAUSE_TOO_LONG_INT_SHIFT                                       6
47884     #define NIG_REG_INT_MASK_5_P1_TC6_PAUSE_TOO_LONG_INT                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC6_PAUSE_TOO_LONG_INT .
47885     #define NIG_REG_INT_MASK_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT                                       7
47886     #define NIG_REG_INT_MASK_5_P1_TC7_PAUSE_TOO_LONG_INT                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_TC7_PAUSE_TOO_LONG_INT .
47887     #define NIG_REG_INT_MASK_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT                                       8
47888     #define NIG_REG_INT_MASK_5_P1_LB_TC0_PAUSE_TOO_LONG_INT                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC0_PAUSE_TOO_LONG_INT .
47889     #define NIG_REG_INT_MASK_5_P1_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                    9
47890     #define NIG_REG_INT_MASK_5_P1_LB_TC1_PAUSE_TOO_LONG_INT                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC1_PAUSE_TOO_LONG_INT .
47891     #define NIG_REG_INT_MASK_5_P1_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                    10
47892     #define NIG_REG_INT_MASK_5_P1_LB_TC2_PAUSE_TOO_LONG_INT                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC2_PAUSE_TOO_LONG_INT .
47893     #define NIG_REG_INT_MASK_5_P1_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                    11
47894     #define NIG_REG_INT_MASK_5_P1_LB_TC3_PAUSE_TOO_LONG_INT                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC3_PAUSE_TOO_LONG_INT .
47895     #define NIG_REG_INT_MASK_5_P1_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                    12
47896     #define NIG_REG_INT_MASK_5_P1_LB_TC4_PAUSE_TOO_LONG_INT                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC4_PAUSE_TOO_LONG_INT .
47897     #define NIG_REG_INT_MASK_5_P1_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                    13
47898     #define NIG_REG_INT_MASK_5_P1_LB_TC5_PAUSE_TOO_LONG_INT                                          (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC5_PAUSE_TOO_LONG_INT .
47899     #define NIG_REG_INT_MASK_5_P1_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                    14
47900     #define NIG_REG_INT_MASK_5_P1_LB_TC6_PAUSE_TOO_LONG_INT                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC6_PAUSE_TOO_LONG_INT .
47901     #define NIG_REG_INT_MASK_5_P1_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                    15
47902     #define NIG_REG_INT_MASK_5_P1_LB_TC7_PAUSE_TOO_LONG_INT                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC7_PAUSE_TOO_LONG_INT .
47903     #define NIG_REG_INT_MASK_5_P1_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                    16
47904     #define NIG_REG_INT_MASK_5_P1_LB_TC8_PAUSE_TOO_LONG_INT                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_5.P1_LB_TC8_PAUSE_TOO_LONG_INT .
47905     #define NIG_REG_INT_MASK_5_P1_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                    17
47906 #define NIG_REG_INT_STS_WR_5                                                                         0x500098UL //Access:WR   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47907     #define NIG_REG_INT_STS_WR_5_P1_TX_PAUSE_TOO_LONG_INT                                            (0x1<<0) // Triggered by TX path being paused for the configured period of time.
47908     #define NIG_REG_INT_STS_WR_5_P1_TX_PAUSE_TOO_LONG_INT_SHIFT                                      0
47909     #define NIG_REG_INT_STS_WR_5_P1_TC0_PAUSE_TOO_LONG_INT                                           (0x1<<1) // Triggered by TC being paused for the configured period of time.
47910     #define NIG_REG_INT_STS_WR_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT                                     1
47911     #define NIG_REG_INT_STS_WR_5_P1_TC1_PAUSE_TOO_LONG_INT                                           (0x1<<2) // Triggered by TC being paused for the configured period of time.
47912     #define NIG_REG_INT_STS_WR_5_P1_TC1_PAUSE_TOO_LONG_INT_SHIFT                                     2
47913     #define NIG_REG_INT_STS_WR_5_P1_TC2_PAUSE_TOO_LONG_INT                                           (0x1<<3) // Triggered by TC being paused for the configured period of time.
47914     #define NIG_REG_INT_STS_WR_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT                                     3
47915     #define NIG_REG_INT_STS_WR_5_P1_TC3_PAUSE_TOO_LONG_INT                                           (0x1<<4) // Triggered by TC being paused for the configured period of time.
47916     #define NIG_REG_INT_STS_WR_5_P1_TC3_PAUSE_TOO_LONG_INT_SHIFT                                     4
47917     #define NIG_REG_INT_STS_WR_5_P1_TC4_PAUSE_TOO_LONG_INT                                           (0x1<<5) // Triggered by TC being paused for the configured period of time.
47918     #define NIG_REG_INT_STS_WR_5_P1_TC4_PAUSE_TOO_LONG_INT_SHIFT                                     5
47919     #define NIG_REG_INT_STS_WR_5_P1_TC5_PAUSE_TOO_LONG_INT                                           (0x1<<6) // Triggered by TC being paused for the configured period of time.
47920     #define NIG_REG_INT_STS_WR_5_P1_TC5_PAUSE_TOO_LONG_INT_SHIFT                                     6
47921     #define NIG_REG_INT_STS_WR_5_P1_TC6_PAUSE_TOO_LONG_INT                                           (0x1<<7) // Triggered by TC being paused for the configured period of time.
47922     #define NIG_REG_INT_STS_WR_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT                                     7
47923     #define NIG_REG_INT_STS_WR_5_P1_TC7_PAUSE_TOO_LONG_INT                                           (0x1<<8) // Triggered by TC being paused for the configured period of time.
47924     #define NIG_REG_INT_STS_WR_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT                                     8
47925     #define NIG_REG_INT_STS_WR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT                                        (0x1<<9) // Triggered by TC being paused for the configured period of time.
47926     #define NIG_REG_INT_STS_WR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                  9
47927     #define NIG_REG_INT_STS_WR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT                                        (0x1<<10) // Triggered by TC being paused for the configured period of time.
47928     #define NIG_REG_INT_STS_WR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                  10
47929     #define NIG_REG_INT_STS_WR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT                                        (0x1<<11) // Triggered by TC being paused for the configured period of time.
47930     #define NIG_REG_INT_STS_WR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                  11
47931     #define NIG_REG_INT_STS_WR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT                                        (0x1<<12) // Triggered by TC being paused for the configured period of time.
47932     #define NIG_REG_INT_STS_WR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                  12
47933     #define NIG_REG_INT_STS_WR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT                                        (0x1<<13) // Triggered by TC being paused for the configured period of time.
47934     #define NIG_REG_INT_STS_WR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                  13
47935     #define NIG_REG_INT_STS_WR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT                                        (0x1<<14) // Triggered by TC being paused for the configured period of time.
47936     #define NIG_REG_INT_STS_WR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                  14
47937     #define NIG_REG_INT_STS_WR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT                                        (0x1<<15) // Triggered by TC being paused for the configured period of time.
47938     #define NIG_REG_INT_STS_WR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                  15
47939     #define NIG_REG_INT_STS_WR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT                                        (0x1<<16) // Triggered by TC being paused for the configured period of time.
47940     #define NIG_REG_INT_STS_WR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                  16
47941     #define NIG_REG_INT_STS_WR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT                                        (0x1<<17) // Triggered by TC being paused for the configured period of time.
47942     #define NIG_REG_INT_STS_WR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                  17
47943 #define NIG_REG_INT_STS_CLR_5                                                                        0x50009cUL //Access:RC   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
47944     #define NIG_REG_INT_STS_CLR_5_P1_TX_PAUSE_TOO_LONG_INT                                           (0x1<<0) // Triggered by TX path being paused for the configured period of time.
47945     #define NIG_REG_INT_STS_CLR_5_P1_TX_PAUSE_TOO_LONG_INT_SHIFT                                     0
47946     #define NIG_REG_INT_STS_CLR_5_P1_TC0_PAUSE_TOO_LONG_INT                                          (0x1<<1) // Triggered by TC being paused for the configured period of time.
47947     #define NIG_REG_INT_STS_CLR_5_P1_TC0_PAUSE_TOO_LONG_INT_SHIFT                                    1
47948     #define NIG_REG_INT_STS_CLR_5_P1_TC1_PAUSE_TOO_LONG_INT                                          (0x1<<2) // Triggered by TC being paused for the configured period of time.
47949     #define NIG_REG_INT_STS_CLR_5_P1_TC1_PAUSE_TOO_LONG_INT_SHIFT                                    2
47950     #define NIG_REG_INT_STS_CLR_5_P1_TC2_PAUSE_TOO_LONG_INT                                          (0x1<<3) // Triggered by TC being paused for the configured period of time.
47951     #define NIG_REG_INT_STS_CLR_5_P1_TC2_PAUSE_TOO_LONG_INT_SHIFT                                    3
47952     #define NIG_REG_INT_STS_CLR_5_P1_TC3_PAUSE_TOO_LONG_INT                                          (0x1<<4) // Triggered by TC being paused for the configured period of time.
47953     #define NIG_REG_INT_STS_CLR_5_P1_TC3_PAUSE_TOO_LONG_INT_SHIFT                                    4
47954     #define NIG_REG_INT_STS_CLR_5_P1_TC4_PAUSE_TOO_LONG_INT                                          (0x1<<5) // Triggered by TC being paused for the configured period of time.
47955     #define NIG_REG_INT_STS_CLR_5_P1_TC4_PAUSE_TOO_LONG_INT_SHIFT                                    5
47956     #define NIG_REG_INT_STS_CLR_5_P1_TC5_PAUSE_TOO_LONG_INT                                          (0x1<<6) // Triggered by TC being paused for the configured period of time.
47957     #define NIG_REG_INT_STS_CLR_5_P1_TC5_PAUSE_TOO_LONG_INT_SHIFT                                    6
47958     #define NIG_REG_INT_STS_CLR_5_P1_TC6_PAUSE_TOO_LONG_INT                                          (0x1<<7) // Triggered by TC being paused for the configured period of time.
47959     #define NIG_REG_INT_STS_CLR_5_P1_TC6_PAUSE_TOO_LONG_INT_SHIFT                                    7
47960     #define NIG_REG_INT_STS_CLR_5_P1_TC7_PAUSE_TOO_LONG_INT                                          (0x1<<8) // Triggered by TC being paused for the configured period of time.
47961     #define NIG_REG_INT_STS_CLR_5_P1_TC7_PAUSE_TOO_LONG_INT_SHIFT                                    8
47962     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT                                       (0x1<<9) // Triggered by TC being paused for the configured period of time.
47963     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                 9
47964     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT                                       (0x1<<10) // Triggered by TC being paused for the configured period of time.
47965     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                 10
47966     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT                                       (0x1<<11) // Triggered by TC being paused for the configured period of time.
47967     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                 11
47968     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT                                       (0x1<<12) // Triggered by TC being paused for the configured period of time.
47969     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                 12
47970     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT                                       (0x1<<13) // Triggered by TC being paused for the configured period of time.
47971     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                 13
47972     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT                                       (0x1<<14) // Triggered by TC being paused for the configured period of time.
47973     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                 14
47974     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT                                       (0x1<<15) // Triggered by TC being paused for the configured period of time.
47975     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                 15
47976     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT                                       (0x1<<16) // Triggered by TC being paused for the configured period of time.
47977     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                 16
47978     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT                                       (0x1<<17) // Triggered by TC being paused for the configured period of time.
47979     #define NIG_REG_INT_STS_CLR_5_P1_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                 17
47980 #define NIG_REG_INT_STS_6_K2                                                                         0x5000a0UL //Access:R    DataWidth:0x14  Multi Field Register.  Chips: K2
47981     #define NIG_REG_INT_STS_6_P2_PURELB_SOPQ_ERROR                                                   (0x1<<0) // Error in the pure-loopback SOPQ.
47982     #define NIG_REG_INT_STS_6_P2_PURELB_SOPQ_ERROR_SHIFT                                             0
47983     #define NIG_REG_INT_STS_6_P2_RX_MACFIFO_ERROR                                                    (0x1<<1) // Error in RX MAC FIFO.
47984     #define NIG_REG_INT_STS_6_P2_RX_MACFIFO_ERROR_SHIFT                                              1
47985     #define NIG_REG_INT_STS_6_P2_TX_MACFIFO_ERROR                                                    (0x1<<2) // Error in TX MAC FIFO.
47986     #define NIG_REG_INT_STS_6_P2_TX_MACFIFO_ERROR_SHIFT                                              2
47987     #define NIG_REG_INT_STS_6_P2_TX_BMB_FIFO_ERROR                                                   (0x1<<3) // FIFO error in TX BMB FIFO.
47988     #define NIG_REG_INT_STS_6_P2_TX_BMB_FIFO_ERROR_SHIFT                                             3
47989     #define NIG_REG_INT_STS_6_P2_LB_BMB_FIFO_ERROR                                                   (0x1<<4) // FIFO error in LB BMB FIFO.
47990     #define NIG_REG_INT_STS_6_P2_LB_BMB_FIFO_ERROR_SHIFT                                             4
47991     #define NIG_REG_INT_STS_6_P2_TX_BTB_FIFO_ERROR                                                   (0x1<<5) // Error in BTB FIFO for TX path.
47992     #define NIG_REG_INT_STS_6_P2_TX_BTB_FIFO_ERROR_SHIFT                                             5
47993     #define NIG_REG_INT_STS_6_P2_LB_BTB_FIFO_ERROR                                                   (0x1<<6) // Error in BTB FIFO for LB path.
47994     #define NIG_REG_INT_STS_6_P2_LB_BTB_FIFO_ERROR_SHIFT                                             6
47995     #define NIG_REG_INT_STS_6_P2_RX_LLH_DFIFO_ERROR                                                  (0x1<<7) // Error in LLH Data FIFO.
47996     #define NIG_REG_INT_STS_6_P2_RX_LLH_DFIFO_ERROR_SHIFT                                            7
47997     #define NIG_REG_INT_STS_6_P2_TX_LLH_DFIFO_ERROR                                                  (0x1<<8) // Error in LLH Data FIFO.
47998     #define NIG_REG_INT_STS_6_P2_TX_LLH_DFIFO_ERROR_SHIFT                                            8
47999     #define NIG_REG_INT_STS_6_P2_LB_LLH_DFIFO_ERROR                                                  (0x1<<9) // Error in LLH Data FIFO.
48000     #define NIG_REG_INT_STS_6_P2_LB_LLH_DFIFO_ERROR_SHIFT                                            9
48001     #define NIG_REG_INT_STS_6_P2_RX_LLH_HFIFO_ERROR                                                  (0x1<<10) // Error in LLH Header FIFO.
48002     #define NIG_REG_INT_STS_6_P2_RX_LLH_HFIFO_ERROR_SHIFT                                            10
48003     #define NIG_REG_INT_STS_6_P2_TX_LLH_HFIFO_ERROR                                                  (0x1<<11) // Error in LLH Header FIFO.
48004     #define NIG_REG_INT_STS_6_P2_TX_LLH_HFIFO_ERROR_SHIFT                                            11
48005     #define NIG_REG_INT_STS_6_P2_LB_LLH_HFIFO_ERROR                                                  (0x1<<12) // Error in LLH Header FIFO.
48006     #define NIG_REG_INT_STS_6_P2_LB_LLH_HFIFO_ERROR_SHIFT                                            12
48007     #define NIG_REG_INT_STS_6_P2_RX_LLH_RFIFO_ERROR                                                  (0x1<<13) // Error in LLH Result FIFO.
48008     #define NIG_REG_INT_STS_6_P2_RX_LLH_RFIFO_ERROR_SHIFT                                            13
48009     #define NIG_REG_INT_STS_6_P2_TX_LLH_RFIFO_ERROR                                                  (0x1<<14) // Error in LLH Result FIFO.
48010     #define NIG_REG_INT_STS_6_P2_TX_LLH_RFIFO_ERROR_SHIFT                                            14
48011     #define NIG_REG_INT_STS_6_P2_LB_LLH_RFIFO_ERROR                                                  (0x1<<15) // Error in LLH Result FIFO.
48012     #define NIG_REG_INT_STS_6_P2_LB_LLH_RFIFO_ERROR_SHIFT                                            15
48013     #define NIG_REG_INT_STS_6_P2_STORM_FIFO_ERROR                                                    (0x1<<16) // FIFO error in STORM message FIFO.
48014     #define NIG_REG_INT_STS_6_P2_STORM_FIFO_ERROR_SHIFT                                              16
48015     #define NIG_REG_INT_STS_6_P2_STORM_DSCR_FIFO_ERROR                                               (0x1<<17) // FIFO error in STORM descriptor FIFO.
48016     #define NIG_REG_INT_STS_6_P2_STORM_DSCR_FIFO_ERROR_SHIFT                                         17
48017     #define NIG_REG_INT_STS_6_P2_TX_GNT_FIFO_ERROR                                                   (0x1<<18) // Error in grant FIFO.
48018     #define NIG_REG_INT_STS_6_P2_TX_GNT_FIFO_ERROR_SHIFT                                             18
48019     #define NIG_REG_INT_STS_6_P2_LB_GNT_FIFO_ERROR                                                   (0x1<<19) // Error in grant FIFO.
48020     #define NIG_REG_INT_STS_6_P2_LB_GNT_FIFO_ERROR_SHIFT                                             19
48021 #define NIG_REG_INT_MASK_6_K2                                                                        0x5000a4UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: K2
48022     #define NIG_REG_INT_MASK_6_P2_PURELB_SOPQ_ERROR                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_PURELB_SOPQ_ERROR .
48023     #define NIG_REG_INT_MASK_6_P2_PURELB_SOPQ_ERROR_SHIFT                                            0
48024     #define NIG_REG_INT_MASK_6_P2_RX_MACFIFO_ERROR                                                   (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_MACFIFO_ERROR .
48025     #define NIG_REG_INT_MASK_6_P2_RX_MACFIFO_ERROR_SHIFT                                             1
48026     #define NIG_REG_INT_MASK_6_P2_TX_MACFIFO_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_MACFIFO_ERROR .
48027     #define NIG_REG_INT_MASK_6_P2_TX_MACFIFO_ERROR_SHIFT                                             2
48028     #define NIG_REG_INT_MASK_6_P2_TX_BMB_FIFO_ERROR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_BMB_FIFO_ERROR .
48029     #define NIG_REG_INT_MASK_6_P2_TX_BMB_FIFO_ERROR_SHIFT                                            3
48030     #define NIG_REG_INT_MASK_6_P2_LB_BMB_FIFO_ERROR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_BMB_FIFO_ERROR .
48031     #define NIG_REG_INT_MASK_6_P2_LB_BMB_FIFO_ERROR_SHIFT                                            4
48032     #define NIG_REG_INT_MASK_6_P2_TX_BTB_FIFO_ERROR                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_BTB_FIFO_ERROR .
48033     #define NIG_REG_INT_MASK_6_P2_TX_BTB_FIFO_ERROR_SHIFT                                            5
48034     #define NIG_REG_INT_MASK_6_P2_LB_BTB_FIFO_ERROR                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_BTB_FIFO_ERROR .
48035     #define NIG_REG_INT_MASK_6_P2_LB_BTB_FIFO_ERROR_SHIFT                                            6
48036     #define NIG_REG_INT_MASK_6_P2_RX_LLH_DFIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_DFIFO_ERROR .
48037     #define NIG_REG_INT_MASK_6_P2_RX_LLH_DFIFO_ERROR_SHIFT                                           7
48038     #define NIG_REG_INT_MASK_6_P2_TX_LLH_DFIFO_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_DFIFO_ERROR .
48039     #define NIG_REG_INT_MASK_6_P2_TX_LLH_DFIFO_ERROR_SHIFT                                           8
48040     #define NIG_REG_INT_MASK_6_P2_LB_LLH_DFIFO_ERROR                                                 (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_DFIFO_ERROR .
48041     #define NIG_REG_INT_MASK_6_P2_LB_LLH_DFIFO_ERROR_SHIFT                                           9
48042     #define NIG_REG_INT_MASK_6_P2_RX_LLH_HFIFO_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_HFIFO_ERROR .
48043     #define NIG_REG_INT_MASK_6_P2_RX_LLH_HFIFO_ERROR_SHIFT                                           10
48044     #define NIG_REG_INT_MASK_6_P2_TX_LLH_HFIFO_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_HFIFO_ERROR .
48045     #define NIG_REG_INT_MASK_6_P2_TX_LLH_HFIFO_ERROR_SHIFT                                           11
48046     #define NIG_REG_INT_MASK_6_P2_LB_LLH_HFIFO_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_HFIFO_ERROR .
48047     #define NIG_REG_INT_MASK_6_P2_LB_LLH_HFIFO_ERROR_SHIFT                                           12
48048     #define NIG_REG_INT_MASK_6_P2_RX_LLH_RFIFO_ERROR                                                 (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_RX_LLH_RFIFO_ERROR .
48049     #define NIG_REG_INT_MASK_6_P2_RX_LLH_RFIFO_ERROR_SHIFT                                           13
48050     #define NIG_REG_INT_MASK_6_P2_TX_LLH_RFIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_LLH_RFIFO_ERROR .
48051     #define NIG_REG_INT_MASK_6_P2_TX_LLH_RFIFO_ERROR_SHIFT                                           14
48052     #define NIG_REG_INT_MASK_6_P2_LB_LLH_RFIFO_ERROR                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_LLH_RFIFO_ERROR .
48053     #define NIG_REG_INT_MASK_6_P2_LB_LLH_RFIFO_ERROR_SHIFT                                           15
48054     #define NIG_REG_INT_MASK_6_P2_STORM_FIFO_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_STORM_FIFO_ERROR .
48055     #define NIG_REG_INT_MASK_6_P2_STORM_FIFO_ERROR_SHIFT                                             16
48056     #define NIG_REG_INT_MASK_6_P2_STORM_DSCR_FIFO_ERROR                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_STORM_DSCR_FIFO_ERROR .
48057     #define NIG_REG_INT_MASK_6_P2_STORM_DSCR_FIFO_ERROR_SHIFT                                        17
48058     #define NIG_REG_INT_MASK_6_P2_TX_GNT_FIFO_ERROR                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_TX_GNT_FIFO_ERROR .
48059     #define NIG_REG_INT_MASK_6_P2_TX_GNT_FIFO_ERROR_SHIFT                                            18
48060     #define NIG_REG_INT_MASK_6_P2_LB_GNT_FIFO_ERROR                                                  (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_6.P2_LB_GNT_FIFO_ERROR .
48061     #define NIG_REG_INT_MASK_6_P2_LB_GNT_FIFO_ERROR_SHIFT                                            19
48062 #define NIG_REG_INT_STS_WR_6_K2                                                                      0x5000a8UL //Access:WR   DataWidth:0x14  Multi Field Register.  Chips: K2
48063     #define NIG_REG_INT_STS_WR_6_P2_PURELB_SOPQ_ERROR                                                (0x1<<0) // Error in the pure-loopback SOPQ.
48064     #define NIG_REG_INT_STS_WR_6_P2_PURELB_SOPQ_ERROR_SHIFT                                          0
48065     #define NIG_REG_INT_STS_WR_6_P2_RX_MACFIFO_ERROR                                                 (0x1<<1) // Error in RX MAC FIFO.
48066     #define NIG_REG_INT_STS_WR_6_P2_RX_MACFIFO_ERROR_SHIFT                                           1
48067     #define NIG_REG_INT_STS_WR_6_P2_TX_MACFIFO_ERROR                                                 (0x1<<2) // Error in TX MAC FIFO.
48068     #define NIG_REG_INT_STS_WR_6_P2_TX_MACFIFO_ERROR_SHIFT                                           2
48069     #define NIG_REG_INT_STS_WR_6_P2_TX_BMB_FIFO_ERROR                                                (0x1<<3) // FIFO error in TX BMB FIFO.
48070     #define NIG_REG_INT_STS_WR_6_P2_TX_BMB_FIFO_ERROR_SHIFT                                          3
48071     #define NIG_REG_INT_STS_WR_6_P2_LB_BMB_FIFO_ERROR                                                (0x1<<4) // FIFO error in LB BMB FIFO.
48072     #define NIG_REG_INT_STS_WR_6_P2_LB_BMB_FIFO_ERROR_SHIFT                                          4
48073     #define NIG_REG_INT_STS_WR_6_P2_TX_BTB_FIFO_ERROR                                                (0x1<<5) // Error in BTB FIFO for TX path.
48074     #define NIG_REG_INT_STS_WR_6_P2_TX_BTB_FIFO_ERROR_SHIFT                                          5
48075     #define NIG_REG_INT_STS_WR_6_P2_LB_BTB_FIFO_ERROR                                                (0x1<<6) // Error in BTB FIFO for LB path.
48076     #define NIG_REG_INT_STS_WR_6_P2_LB_BTB_FIFO_ERROR_SHIFT                                          6
48077     #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_DFIFO_ERROR                                               (0x1<<7) // Error in LLH Data FIFO.
48078     #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_DFIFO_ERROR_SHIFT                                         7
48079     #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_DFIFO_ERROR                                               (0x1<<8) // Error in LLH Data FIFO.
48080     #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_DFIFO_ERROR_SHIFT                                         8
48081     #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_DFIFO_ERROR                                               (0x1<<9) // Error in LLH Data FIFO.
48082     #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_DFIFO_ERROR_SHIFT                                         9
48083     #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_HFIFO_ERROR                                               (0x1<<10) // Error in LLH Header FIFO.
48084     #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_HFIFO_ERROR_SHIFT                                         10
48085     #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_HFIFO_ERROR                                               (0x1<<11) // Error in LLH Header FIFO.
48086     #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_HFIFO_ERROR_SHIFT                                         11
48087     #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_HFIFO_ERROR                                               (0x1<<12) // Error in LLH Header FIFO.
48088     #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_HFIFO_ERROR_SHIFT                                         12
48089     #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_RFIFO_ERROR                                               (0x1<<13) // Error in LLH Result FIFO.
48090     #define NIG_REG_INT_STS_WR_6_P2_RX_LLH_RFIFO_ERROR_SHIFT                                         13
48091     #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_RFIFO_ERROR                                               (0x1<<14) // Error in LLH Result FIFO.
48092     #define NIG_REG_INT_STS_WR_6_P2_TX_LLH_RFIFO_ERROR_SHIFT                                         14
48093     #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_RFIFO_ERROR                                               (0x1<<15) // Error in LLH Result FIFO.
48094     #define NIG_REG_INT_STS_WR_6_P2_LB_LLH_RFIFO_ERROR_SHIFT                                         15
48095     #define NIG_REG_INT_STS_WR_6_P2_STORM_FIFO_ERROR                                                 (0x1<<16) // FIFO error in STORM message FIFO.
48096     #define NIG_REG_INT_STS_WR_6_P2_STORM_FIFO_ERROR_SHIFT                                           16
48097     #define NIG_REG_INT_STS_WR_6_P2_STORM_DSCR_FIFO_ERROR                                            (0x1<<17) // FIFO error in STORM descriptor FIFO.
48098     #define NIG_REG_INT_STS_WR_6_P2_STORM_DSCR_FIFO_ERROR_SHIFT                                      17
48099     #define NIG_REG_INT_STS_WR_6_P2_TX_GNT_FIFO_ERROR                                                (0x1<<18) // Error in grant FIFO.
48100     #define NIG_REG_INT_STS_WR_6_P2_TX_GNT_FIFO_ERROR_SHIFT                                          18
48101     #define NIG_REG_INT_STS_WR_6_P2_LB_GNT_FIFO_ERROR                                                (0x1<<19) // Error in grant FIFO.
48102     #define NIG_REG_INT_STS_WR_6_P2_LB_GNT_FIFO_ERROR_SHIFT                                          19
48103 #define NIG_REG_INT_STS_CLR_6_K2                                                                     0x5000acUL //Access:RC   DataWidth:0x14  Multi Field Register.  Chips: K2
48104     #define NIG_REG_INT_STS_CLR_6_P2_PURELB_SOPQ_ERROR                                               (0x1<<0) // Error in the pure-loopback SOPQ.
48105     #define NIG_REG_INT_STS_CLR_6_P2_PURELB_SOPQ_ERROR_SHIFT                                         0
48106     #define NIG_REG_INT_STS_CLR_6_P2_RX_MACFIFO_ERROR                                                (0x1<<1) // Error in RX MAC FIFO.
48107     #define NIG_REG_INT_STS_CLR_6_P2_RX_MACFIFO_ERROR_SHIFT                                          1
48108     #define NIG_REG_INT_STS_CLR_6_P2_TX_MACFIFO_ERROR                                                (0x1<<2) // Error in TX MAC FIFO.
48109     #define NIG_REG_INT_STS_CLR_6_P2_TX_MACFIFO_ERROR_SHIFT                                          2
48110     #define NIG_REG_INT_STS_CLR_6_P2_TX_BMB_FIFO_ERROR                                               (0x1<<3) // FIFO error in TX BMB FIFO.
48111     #define NIG_REG_INT_STS_CLR_6_P2_TX_BMB_FIFO_ERROR_SHIFT                                         3
48112     #define NIG_REG_INT_STS_CLR_6_P2_LB_BMB_FIFO_ERROR                                               (0x1<<4) // FIFO error in LB BMB FIFO.
48113     #define NIG_REG_INT_STS_CLR_6_P2_LB_BMB_FIFO_ERROR_SHIFT                                         4
48114     #define NIG_REG_INT_STS_CLR_6_P2_TX_BTB_FIFO_ERROR                                               (0x1<<5) // Error in BTB FIFO for TX path.
48115     #define NIG_REG_INT_STS_CLR_6_P2_TX_BTB_FIFO_ERROR_SHIFT                                         5
48116     #define NIG_REG_INT_STS_CLR_6_P2_LB_BTB_FIFO_ERROR                                               (0x1<<6) // Error in BTB FIFO for LB path.
48117     #define NIG_REG_INT_STS_CLR_6_P2_LB_BTB_FIFO_ERROR_SHIFT                                         6
48118     #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_DFIFO_ERROR                                              (0x1<<7) // Error in LLH Data FIFO.
48119     #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_DFIFO_ERROR_SHIFT                                        7
48120     #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_DFIFO_ERROR                                              (0x1<<8) // Error in LLH Data FIFO.
48121     #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_DFIFO_ERROR_SHIFT                                        8
48122     #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_DFIFO_ERROR                                              (0x1<<9) // Error in LLH Data FIFO.
48123     #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_DFIFO_ERROR_SHIFT                                        9
48124     #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_HFIFO_ERROR                                              (0x1<<10) // Error in LLH Header FIFO.
48125     #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_HFIFO_ERROR_SHIFT                                        10
48126     #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_HFIFO_ERROR                                              (0x1<<11) // Error in LLH Header FIFO.
48127     #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_HFIFO_ERROR_SHIFT                                        11
48128     #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_HFIFO_ERROR                                              (0x1<<12) // Error in LLH Header FIFO.
48129     #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_HFIFO_ERROR_SHIFT                                        12
48130     #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_RFIFO_ERROR                                              (0x1<<13) // Error in LLH Result FIFO.
48131     #define NIG_REG_INT_STS_CLR_6_P2_RX_LLH_RFIFO_ERROR_SHIFT                                        13
48132     #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_RFIFO_ERROR                                              (0x1<<14) // Error in LLH Result FIFO.
48133     #define NIG_REG_INT_STS_CLR_6_P2_TX_LLH_RFIFO_ERROR_SHIFT                                        14
48134     #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_RFIFO_ERROR                                              (0x1<<15) // Error in LLH Result FIFO.
48135     #define NIG_REG_INT_STS_CLR_6_P2_LB_LLH_RFIFO_ERROR_SHIFT                                        15
48136     #define NIG_REG_INT_STS_CLR_6_P2_STORM_FIFO_ERROR                                                (0x1<<16) // FIFO error in STORM message FIFO.
48137     #define NIG_REG_INT_STS_CLR_6_P2_STORM_FIFO_ERROR_SHIFT                                          16
48138     #define NIG_REG_INT_STS_CLR_6_P2_STORM_DSCR_FIFO_ERROR                                           (0x1<<17) // FIFO error in STORM descriptor FIFO.
48139     #define NIG_REG_INT_STS_CLR_6_P2_STORM_DSCR_FIFO_ERROR_SHIFT                                     17
48140     #define NIG_REG_INT_STS_CLR_6_P2_TX_GNT_FIFO_ERROR                                               (0x1<<18) // Error in grant FIFO.
48141     #define NIG_REG_INT_STS_CLR_6_P2_TX_GNT_FIFO_ERROR_SHIFT                                         18
48142     #define NIG_REG_INT_STS_CLR_6_P2_LB_GNT_FIFO_ERROR                                               (0x1<<19) // Error in grant FIFO.
48143     #define NIG_REG_INT_STS_CLR_6_P2_LB_GNT_FIFO_ERROR_SHIFT                                         19
48144 #define NIG_REG_INT_STS_7                                                                            0x5000b0UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: K2
48145     #define NIG_REG_INT_STS_7_P2_TX_PAUSE_TOO_LONG_INT                                               (0x1<<0) // Triggered by TX path being paused for the configured period of time.
48146     #define NIG_REG_INT_STS_7_P2_TX_PAUSE_TOO_LONG_INT_SHIFT                                         0
48147     #define NIG_REG_INT_STS_7_P2_TC0_PAUSE_TOO_LONG_INT                                              (0x1<<1) // Triggered by TC being paused for the configured period of time.
48148     #define NIG_REG_INT_STS_7_P2_TC0_PAUSE_TOO_LONG_INT_SHIFT                                        1
48149     #define NIG_REG_INT_STS_7_P2_TC1_PAUSE_TOO_LONG_INT                                              (0x1<<2) // Triggered by TC being paused for the configured period of time.
48150     #define NIG_REG_INT_STS_7_P2_TC1_PAUSE_TOO_LONG_INT_SHIFT                                        2
48151     #define NIG_REG_INT_STS_7_P2_TC2_PAUSE_TOO_LONG_INT                                              (0x1<<3) // Triggered by TC being paused for the configured period of time.
48152     #define NIG_REG_INT_STS_7_P2_TC2_PAUSE_TOO_LONG_INT_SHIFT                                        3
48153     #define NIG_REG_INT_STS_7_P2_TC3_PAUSE_TOO_LONG_INT                                              (0x1<<4) // Triggered by TC being paused for the configured period of time.
48154     #define NIG_REG_INT_STS_7_P2_TC3_PAUSE_TOO_LONG_INT_SHIFT                                        4
48155     #define NIG_REG_INT_STS_7_P2_TC4_PAUSE_TOO_LONG_INT                                              (0x1<<5) // Triggered by TC being paused for the configured period of time.
48156     #define NIG_REG_INT_STS_7_P2_TC4_PAUSE_TOO_LONG_INT_SHIFT                                        5
48157     #define NIG_REG_INT_STS_7_P2_TC5_PAUSE_TOO_LONG_INT                                              (0x1<<6) // Triggered by TC being paused for the configured period of time.
48158     #define NIG_REG_INT_STS_7_P2_TC5_PAUSE_TOO_LONG_INT_SHIFT                                        6
48159     #define NIG_REG_INT_STS_7_P2_TC6_PAUSE_TOO_LONG_INT                                              (0x1<<7) // Triggered by TC being paused for the configured period of time.
48160     #define NIG_REG_INT_STS_7_P2_TC6_PAUSE_TOO_LONG_INT_SHIFT                                        7
48161     #define NIG_REG_INT_STS_7_P2_TC7_PAUSE_TOO_LONG_INT                                              (0x1<<8) // Triggered by TC being paused for the configured period of time.
48162     #define NIG_REG_INT_STS_7_P2_TC7_PAUSE_TOO_LONG_INT_SHIFT                                        8
48163     #define NIG_REG_INT_STS_7_P2_LB_TC0_PAUSE_TOO_LONG_INT                                           (0x1<<9) // Triggered by TC being paused for the configured period of time.
48164     #define NIG_REG_INT_STS_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                     9
48165     #define NIG_REG_INT_STS_7_P2_LB_TC1_PAUSE_TOO_LONG_INT                                           (0x1<<10) // Triggered by TC being paused for the configured period of time.
48166     #define NIG_REG_INT_STS_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                     10
48167     #define NIG_REG_INT_STS_7_P2_LB_TC2_PAUSE_TOO_LONG_INT                                           (0x1<<11) // Triggered by TC being paused for the configured period of time.
48168     #define NIG_REG_INT_STS_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                     11
48169     #define NIG_REG_INT_STS_7_P2_LB_TC3_PAUSE_TOO_LONG_INT                                           (0x1<<12) // Triggered by TC being paused for the configured period of time.
48170     #define NIG_REG_INT_STS_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                     12
48171     #define NIG_REG_INT_STS_7_P2_LB_TC4_PAUSE_TOO_LONG_INT                                           (0x1<<13) // Triggered by TC being paused for the configured period of time.
48172     #define NIG_REG_INT_STS_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                     13
48173     #define NIG_REG_INT_STS_7_P2_LB_TC5_PAUSE_TOO_LONG_INT                                           (0x1<<14) // Triggered by TC being paused for the configured period of time.
48174     #define NIG_REG_INT_STS_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                     14
48175     #define NIG_REG_INT_STS_7_P2_LB_TC6_PAUSE_TOO_LONG_INT                                           (0x1<<15) // Triggered by TC being paused for the configured period of time.
48176     #define NIG_REG_INT_STS_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                     15
48177     #define NIG_REG_INT_STS_7_P2_LB_TC7_PAUSE_TOO_LONG_INT                                           (0x1<<16) // Triggered by TC being paused for the configured period of time.
48178     #define NIG_REG_INT_STS_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                     16
48179     #define NIG_REG_INT_STS_7_P2_LB_TC8_PAUSE_TOO_LONG_INT                                           (0x1<<17) // Triggered by TC being paused for the configured period of time.
48180     #define NIG_REG_INT_STS_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                     17
48181 #define NIG_REG_INT_MASK_7                                                                           0x5000b4UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: K2
48182     #define NIG_REG_INT_MASK_7_P2_TX_PAUSE_TOO_LONG_INT                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TX_PAUSE_TOO_LONG_INT .
48183     #define NIG_REG_INT_MASK_7_P2_TX_PAUSE_TOO_LONG_INT_SHIFT                                        0
48184     #define NIG_REG_INT_MASK_7_P2_TC0_PAUSE_TOO_LONG_INT                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC0_PAUSE_TOO_LONG_INT .
48185     #define NIG_REG_INT_MASK_7_P2_TC0_PAUSE_TOO_LONG_INT_SHIFT                                       1
48186     #define NIG_REG_INT_MASK_7_P2_TC1_PAUSE_TOO_LONG_INT                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC1_PAUSE_TOO_LONG_INT .
48187     #define NIG_REG_INT_MASK_7_P2_TC1_PAUSE_TOO_LONG_INT_SHIFT                                       2
48188     #define NIG_REG_INT_MASK_7_P2_TC2_PAUSE_TOO_LONG_INT                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC2_PAUSE_TOO_LONG_INT .
48189     #define NIG_REG_INT_MASK_7_P2_TC2_PAUSE_TOO_LONG_INT_SHIFT                                       3
48190     #define NIG_REG_INT_MASK_7_P2_TC3_PAUSE_TOO_LONG_INT                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC3_PAUSE_TOO_LONG_INT .
48191     #define NIG_REG_INT_MASK_7_P2_TC3_PAUSE_TOO_LONG_INT_SHIFT                                       4
48192     #define NIG_REG_INT_MASK_7_P2_TC4_PAUSE_TOO_LONG_INT                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC4_PAUSE_TOO_LONG_INT .
48193     #define NIG_REG_INT_MASK_7_P2_TC4_PAUSE_TOO_LONG_INT_SHIFT                                       5
48194     #define NIG_REG_INT_MASK_7_P2_TC5_PAUSE_TOO_LONG_INT                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC5_PAUSE_TOO_LONG_INT .
48195     #define NIG_REG_INT_MASK_7_P2_TC5_PAUSE_TOO_LONG_INT_SHIFT                                       6
48196     #define NIG_REG_INT_MASK_7_P2_TC6_PAUSE_TOO_LONG_INT                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC6_PAUSE_TOO_LONG_INT .
48197     #define NIG_REG_INT_MASK_7_P2_TC6_PAUSE_TOO_LONG_INT_SHIFT                                       7
48198     #define NIG_REG_INT_MASK_7_P2_TC7_PAUSE_TOO_LONG_INT                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_TC7_PAUSE_TOO_LONG_INT .
48199     #define NIG_REG_INT_MASK_7_P2_TC7_PAUSE_TOO_LONG_INT_SHIFT                                       8
48200     #define NIG_REG_INT_MASK_7_P2_LB_TC0_PAUSE_TOO_LONG_INT                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC0_PAUSE_TOO_LONG_INT .
48201     #define NIG_REG_INT_MASK_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                    9
48202     #define NIG_REG_INT_MASK_7_P2_LB_TC1_PAUSE_TOO_LONG_INT                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC1_PAUSE_TOO_LONG_INT .
48203     #define NIG_REG_INT_MASK_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                    10
48204     #define NIG_REG_INT_MASK_7_P2_LB_TC2_PAUSE_TOO_LONG_INT                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC2_PAUSE_TOO_LONG_INT .
48205     #define NIG_REG_INT_MASK_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                    11
48206     #define NIG_REG_INT_MASK_7_P2_LB_TC3_PAUSE_TOO_LONG_INT                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC3_PAUSE_TOO_LONG_INT .
48207     #define NIG_REG_INT_MASK_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                    12
48208     #define NIG_REG_INT_MASK_7_P2_LB_TC4_PAUSE_TOO_LONG_INT                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC4_PAUSE_TOO_LONG_INT .
48209     #define NIG_REG_INT_MASK_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                    13
48210     #define NIG_REG_INT_MASK_7_P2_LB_TC5_PAUSE_TOO_LONG_INT                                          (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC5_PAUSE_TOO_LONG_INT .
48211     #define NIG_REG_INT_MASK_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                    14
48212     #define NIG_REG_INT_MASK_7_P2_LB_TC6_PAUSE_TOO_LONG_INT                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC6_PAUSE_TOO_LONG_INT .
48213     #define NIG_REG_INT_MASK_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                    15
48214     #define NIG_REG_INT_MASK_7_P2_LB_TC7_PAUSE_TOO_LONG_INT                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC7_PAUSE_TOO_LONG_INT .
48215     #define NIG_REG_INT_MASK_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                    16
48216     #define NIG_REG_INT_MASK_7_P2_LB_TC8_PAUSE_TOO_LONG_INT                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_7.P2_LB_TC8_PAUSE_TOO_LONG_INT .
48217     #define NIG_REG_INT_MASK_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                    17
48218 #define NIG_REG_INT_STS_WR_7                                                                         0x5000b8UL //Access:WR   DataWidth:0x12  Multi Field Register.  Chips: K2
48219     #define NIG_REG_INT_STS_WR_7_P2_TX_PAUSE_TOO_LONG_INT                                            (0x1<<0) // Triggered by TX path being paused for the configured period of time.
48220     #define NIG_REG_INT_STS_WR_7_P2_TX_PAUSE_TOO_LONG_INT_SHIFT                                      0
48221     #define NIG_REG_INT_STS_WR_7_P2_TC0_PAUSE_TOO_LONG_INT                                           (0x1<<1) // Triggered by TC being paused for the configured period of time.
48222     #define NIG_REG_INT_STS_WR_7_P2_TC0_PAUSE_TOO_LONG_INT_SHIFT                                     1
48223     #define NIG_REG_INT_STS_WR_7_P2_TC1_PAUSE_TOO_LONG_INT                                           (0x1<<2) // Triggered by TC being paused for the configured period of time.
48224     #define NIG_REG_INT_STS_WR_7_P2_TC1_PAUSE_TOO_LONG_INT_SHIFT                                     2
48225     #define NIG_REG_INT_STS_WR_7_P2_TC2_PAUSE_TOO_LONG_INT                                           (0x1<<3) // Triggered by TC being paused for the configured period of time.
48226     #define NIG_REG_INT_STS_WR_7_P2_TC2_PAUSE_TOO_LONG_INT_SHIFT                                     3
48227     #define NIG_REG_INT_STS_WR_7_P2_TC3_PAUSE_TOO_LONG_INT                                           (0x1<<4) // Triggered by TC being paused for the configured period of time.
48228     #define NIG_REG_INT_STS_WR_7_P2_TC3_PAUSE_TOO_LONG_INT_SHIFT                                     4
48229     #define NIG_REG_INT_STS_WR_7_P2_TC4_PAUSE_TOO_LONG_INT                                           (0x1<<5) // Triggered by TC being paused for the configured period of time.
48230     #define NIG_REG_INT_STS_WR_7_P2_TC4_PAUSE_TOO_LONG_INT_SHIFT                                     5
48231     #define NIG_REG_INT_STS_WR_7_P2_TC5_PAUSE_TOO_LONG_INT                                           (0x1<<6) // Triggered by TC being paused for the configured period of time.
48232     #define NIG_REG_INT_STS_WR_7_P2_TC5_PAUSE_TOO_LONG_INT_SHIFT                                     6
48233     #define NIG_REG_INT_STS_WR_7_P2_TC6_PAUSE_TOO_LONG_INT                                           (0x1<<7) // Triggered by TC being paused for the configured period of time.
48234     #define NIG_REG_INT_STS_WR_7_P2_TC6_PAUSE_TOO_LONG_INT_SHIFT                                     7
48235     #define NIG_REG_INT_STS_WR_7_P2_TC7_PAUSE_TOO_LONG_INT                                           (0x1<<8) // Triggered by TC being paused for the configured period of time.
48236     #define NIG_REG_INT_STS_WR_7_P2_TC7_PAUSE_TOO_LONG_INT_SHIFT                                     8
48237     #define NIG_REG_INT_STS_WR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT                                        (0x1<<9) // Triggered by TC being paused for the configured period of time.
48238     #define NIG_REG_INT_STS_WR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                  9
48239     #define NIG_REG_INT_STS_WR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT                                        (0x1<<10) // Triggered by TC being paused for the configured period of time.
48240     #define NIG_REG_INT_STS_WR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                  10
48241     #define NIG_REG_INT_STS_WR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT                                        (0x1<<11) // Triggered by TC being paused for the configured period of time.
48242     #define NIG_REG_INT_STS_WR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                  11
48243     #define NIG_REG_INT_STS_WR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT                                        (0x1<<12) // Triggered by TC being paused for the configured period of time.
48244     #define NIG_REG_INT_STS_WR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                  12
48245     #define NIG_REG_INT_STS_WR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT                                        (0x1<<13) // Triggered by TC being paused for the configured period of time.
48246     #define NIG_REG_INT_STS_WR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                  13
48247     #define NIG_REG_INT_STS_WR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT                                        (0x1<<14) // Triggered by TC being paused for the configured period of time.
48248     #define NIG_REG_INT_STS_WR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                  14
48249     #define NIG_REG_INT_STS_WR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT                                        (0x1<<15) // Triggered by TC being paused for the configured period of time.
48250     #define NIG_REG_INT_STS_WR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                  15
48251     #define NIG_REG_INT_STS_WR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT                                        (0x1<<16) // Triggered by TC being paused for the configured period of time.
48252     #define NIG_REG_INT_STS_WR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                  16
48253     #define NIG_REG_INT_STS_WR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT                                        (0x1<<17) // Triggered by TC being paused for the configured period of time.
48254     #define NIG_REG_INT_STS_WR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                  17
48255 #define NIG_REG_INT_STS_CLR_7                                                                        0x5000bcUL //Access:RC   DataWidth:0x12  Multi Field Register.  Chips: K2
48256     #define NIG_REG_INT_STS_CLR_7_P2_TX_PAUSE_TOO_LONG_INT                                           (0x1<<0) // Triggered by TX path being paused for the configured period of time.
48257     #define NIG_REG_INT_STS_CLR_7_P2_TX_PAUSE_TOO_LONG_INT_SHIFT                                     0
48258     #define NIG_REG_INT_STS_CLR_7_P2_TC0_PAUSE_TOO_LONG_INT                                          (0x1<<1) // Triggered by TC being paused for the configured period of time.
48259     #define NIG_REG_INT_STS_CLR_7_P2_TC0_PAUSE_TOO_LONG_INT_SHIFT                                    1
48260     #define NIG_REG_INT_STS_CLR_7_P2_TC1_PAUSE_TOO_LONG_INT                                          (0x1<<2) // Triggered by TC being paused for the configured period of time.
48261     #define NIG_REG_INT_STS_CLR_7_P2_TC1_PAUSE_TOO_LONG_INT_SHIFT                                    2
48262     #define NIG_REG_INT_STS_CLR_7_P2_TC2_PAUSE_TOO_LONG_INT                                          (0x1<<3) // Triggered by TC being paused for the configured period of time.
48263     #define NIG_REG_INT_STS_CLR_7_P2_TC2_PAUSE_TOO_LONG_INT_SHIFT                                    3
48264     #define NIG_REG_INT_STS_CLR_7_P2_TC3_PAUSE_TOO_LONG_INT                                          (0x1<<4) // Triggered by TC being paused for the configured period of time.
48265     #define NIG_REG_INT_STS_CLR_7_P2_TC3_PAUSE_TOO_LONG_INT_SHIFT                                    4
48266     #define NIG_REG_INT_STS_CLR_7_P2_TC4_PAUSE_TOO_LONG_INT                                          (0x1<<5) // Triggered by TC being paused for the configured period of time.
48267     #define NIG_REG_INT_STS_CLR_7_P2_TC4_PAUSE_TOO_LONG_INT_SHIFT                                    5
48268     #define NIG_REG_INT_STS_CLR_7_P2_TC5_PAUSE_TOO_LONG_INT                                          (0x1<<6) // Triggered by TC being paused for the configured period of time.
48269     #define NIG_REG_INT_STS_CLR_7_P2_TC5_PAUSE_TOO_LONG_INT_SHIFT                                    6
48270     #define NIG_REG_INT_STS_CLR_7_P2_TC6_PAUSE_TOO_LONG_INT                                          (0x1<<7) // Triggered by TC being paused for the configured period of time.
48271     #define NIG_REG_INT_STS_CLR_7_P2_TC6_PAUSE_TOO_LONG_INT_SHIFT                                    7
48272     #define NIG_REG_INT_STS_CLR_7_P2_TC7_PAUSE_TOO_LONG_INT                                          (0x1<<8) // Triggered by TC being paused for the configured period of time.
48273     #define NIG_REG_INT_STS_CLR_7_P2_TC7_PAUSE_TOO_LONG_INT_SHIFT                                    8
48274     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT                                       (0x1<<9) // Triggered by TC being paused for the configured period of time.
48275     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                 9
48276     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT                                       (0x1<<10) // Triggered by TC being paused for the configured period of time.
48277     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                 10
48278     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT                                       (0x1<<11) // Triggered by TC being paused for the configured period of time.
48279     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                 11
48280     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT                                       (0x1<<12) // Triggered by TC being paused for the configured period of time.
48281     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                 12
48282     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT                                       (0x1<<13) // Triggered by TC being paused for the configured period of time.
48283     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                 13
48284     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT                                       (0x1<<14) // Triggered by TC being paused for the configured period of time.
48285     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                 14
48286     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT                                       (0x1<<15) // Triggered by TC being paused for the configured period of time.
48287     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                 15
48288     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT                                       (0x1<<16) // Triggered by TC being paused for the configured period of time.
48289     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                 16
48290     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT                                       (0x1<<17) // Triggered by TC being paused for the configured period of time.
48291     #define NIG_REG_INT_STS_CLR_7_P2_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                 17
48292 #define NIG_REG_INT_STS_8                                                                            0x5000c0UL //Access:R    DataWidth:0x14  Multi Field Register.  Chips: K2
48293     #define NIG_REG_INT_STS_8_P3_PURELB_SOPQ_ERROR                                                   (0x1<<0) // Error in the pure-loopback SOPQ.
48294     #define NIG_REG_INT_STS_8_P3_PURELB_SOPQ_ERROR_SHIFT                                             0
48295     #define NIG_REG_INT_STS_8_P3_RX_MACFIFO_ERROR                                                    (0x1<<1) // Error in RX MAC FIFO.
48296     #define NIG_REG_INT_STS_8_P3_RX_MACFIFO_ERROR_SHIFT                                              1
48297     #define NIG_REG_INT_STS_8_P3_TX_MACFIFO_ERROR                                                    (0x1<<2) // Error in TX MAC FIFO.
48298     #define NIG_REG_INT_STS_8_P3_TX_MACFIFO_ERROR_SHIFT                                              2
48299     #define NIG_REG_INT_STS_8_P3_TX_BMB_FIFO_ERROR                                                   (0x1<<3) // FIFO error in TX BMB FIFO.
48300     #define NIG_REG_INT_STS_8_P3_TX_BMB_FIFO_ERROR_SHIFT                                             3
48301     #define NIG_REG_INT_STS_8_P3_LB_BMB_FIFO_ERROR                                                   (0x1<<4) // FIFO error in LB BMB FIFO.
48302     #define NIG_REG_INT_STS_8_P3_LB_BMB_FIFO_ERROR_SHIFT                                             4
48303     #define NIG_REG_INT_STS_8_P3_TX_BTB_FIFO_ERROR                                                   (0x1<<5) // Error in BTB FIFO for TX path.
48304     #define NIG_REG_INT_STS_8_P3_TX_BTB_FIFO_ERROR_SHIFT                                             5
48305     #define NIG_REG_INT_STS_8_P3_LB_BTB_FIFO_ERROR                                                   (0x1<<6) // Error in BTB FIFO for LB path.
48306     #define NIG_REG_INT_STS_8_P3_LB_BTB_FIFO_ERROR_SHIFT                                             6
48307     #define NIG_REG_INT_STS_8_P3_RX_LLH_DFIFO_ERROR                                                  (0x1<<7) // Error in LLH Data FIFO.
48308     #define NIG_REG_INT_STS_8_P3_RX_LLH_DFIFO_ERROR_SHIFT                                            7
48309     #define NIG_REG_INT_STS_8_P3_TX_LLH_DFIFO_ERROR                                                  (0x1<<8) // Error in LLH Data FIFO.
48310     #define NIG_REG_INT_STS_8_P3_TX_LLH_DFIFO_ERROR_SHIFT                                            8
48311     #define NIG_REG_INT_STS_8_P3_LB_LLH_DFIFO_ERROR                                                  (0x1<<9) // Error in LLH Data FIFO.
48312     #define NIG_REG_INT_STS_8_P3_LB_LLH_DFIFO_ERROR_SHIFT                                            9
48313     #define NIG_REG_INT_STS_8_P3_RX_LLH_HFIFO_ERROR                                                  (0x1<<10) // Error in LLH Header FIFO.
48314     #define NIG_REG_INT_STS_8_P3_RX_LLH_HFIFO_ERROR_SHIFT                                            10
48315     #define NIG_REG_INT_STS_8_P3_TX_LLH_HFIFO_ERROR                                                  (0x1<<11) // Error in LLH Header FIFO.
48316     #define NIG_REG_INT_STS_8_P3_TX_LLH_HFIFO_ERROR_SHIFT                                            11
48317     #define NIG_REG_INT_STS_8_P3_LB_LLH_HFIFO_ERROR                                                  (0x1<<12) // Error in LLH Header FIFO.
48318     #define NIG_REG_INT_STS_8_P3_LB_LLH_HFIFO_ERROR_SHIFT                                            12
48319     #define NIG_REG_INT_STS_8_P3_RX_LLH_RFIFO_ERROR                                                  (0x1<<13) // Error in LLH Result FIFO.
48320     #define NIG_REG_INT_STS_8_P3_RX_LLH_RFIFO_ERROR_SHIFT                                            13
48321     #define NIG_REG_INT_STS_8_P3_TX_LLH_RFIFO_ERROR                                                  (0x1<<14) // Error in LLH Result FIFO.
48322     #define NIG_REG_INT_STS_8_P3_TX_LLH_RFIFO_ERROR_SHIFT                                            14
48323     #define NIG_REG_INT_STS_8_P3_LB_LLH_RFIFO_ERROR                                                  (0x1<<15) // Error in LLH Result FIFO.
48324     #define NIG_REG_INT_STS_8_P3_LB_LLH_RFIFO_ERROR_SHIFT                                            15
48325     #define NIG_REG_INT_STS_8_P3_STORM_FIFO_ERROR                                                    (0x1<<16) // FIFO error in STORM message FIFO.
48326     #define NIG_REG_INT_STS_8_P3_STORM_FIFO_ERROR_SHIFT                                              16
48327     #define NIG_REG_INT_STS_8_P3_STORM_DSCR_FIFO_ERROR                                               (0x1<<17) // FIFO error in STORM descriptor FIFO.
48328     #define NIG_REG_INT_STS_8_P3_STORM_DSCR_FIFO_ERROR_SHIFT                                         17
48329     #define NIG_REG_INT_STS_8_P3_TX_GNT_FIFO_ERROR                                                   (0x1<<18) // Error in grant FIFO.
48330     #define NIG_REG_INT_STS_8_P3_TX_GNT_FIFO_ERROR_SHIFT                                             18
48331     #define NIG_REG_INT_STS_8_P3_LB_GNT_FIFO_ERROR                                                   (0x1<<19) // Error in grant FIFO.
48332     #define NIG_REG_INT_STS_8_P3_LB_GNT_FIFO_ERROR_SHIFT                                             19
48333 #define NIG_REG_INT_MASK_8                                                                           0x5000c4UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: K2
48334     #define NIG_REG_INT_MASK_8_P3_PURELB_SOPQ_ERROR                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_PURELB_SOPQ_ERROR .
48335     #define NIG_REG_INT_MASK_8_P3_PURELB_SOPQ_ERROR_SHIFT                                            0
48336     #define NIG_REG_INT_MASK_8_P3_RX_MACFIFO_ERROR                                                   (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_MACFIFO_ERROR .
48337     #define NIG_REG_INT_MASK_8_P3_RX_MACFIFO_ERROR_SHIFT                                             1
48338     #define NIG_REG_INT_MASK_8_P3_TX_MACFIFO_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_MACFIFO_ERROR .
48339     #define NIG_REG_INT_MASK_8_P3_TX_MACFIFO_ERROR_SHIFT                                             2
48340     #define NIG_REG_INT_MASK_8_P3_TX_BMB_FIFO_ERROR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_BMB_FIFO_ERROR .
48341     #define NIG_REG_INT_MASK_8_P3_TX_BMB_FIFO_ERROR_SHIFT                                            3
48342     #define NIG_REG_INT_MASK_8_P3_LB_BMB_FIFO_ERROR                                                  (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_BMB_FIFO_ERROR .
48343     #define NIG_REG_INT_MASK_8_P3_LB_BMB_FIFO_ERROR_SHIFT                                            4
48344     #define NIG_REG_INT_MASK_8_P3_TX_BTB_FIFO_ERROR                                                  (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_BTB_FIFO_ERROR .
48345     #define NIG_REG_INT_MASK_8_P3_TX_BTB_FIFO_ERROR_SHIFT                                            5
48346     #define NIG_REG_INT_MASK_8_P3_LB_BTB_FIFO_ERROR                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_BTB_FIFO_ERROR .
48347     #define NIG_REG_INT_MASK_8_P3_LB_BTB_FIFO_ERROR_SHIFT                                            6
48348     #define NIG_REG_INT_MASK_8_P3_RX_LLH_DFIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_DFIFO_ERROR .
48349     #define NIG_REG_INT_MASK_8_P3_RX_LLH_DFIFO_ERROR_SHIFT                                           7
48350     #define NIG_REG_INT_MASK_8_P3_TX_LLH_DFIFO_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_DFIFO_ERROR .
48351     #define NIG_REG_INT_MASK_8_P3_TX_LLH_DFIFO_ERROR_SHIFT                                           8
48352     #define NIG_REG_INT_MASK_8_P3_LB_LLH_DFIFO_ERROR                                                 (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_DFIFO_ERROR .
48353     #define NIG_REG_INT_MASK_8_P3_LB_LLH_DFIFO_ERROR_SHIFT                                           9
48354     #define NIG_REG_INT_MASK_8_P3_RX_LLH_HFIFO_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_HFIFO_ERROR .
48355     #define NIG_REG_INT_MASK_8_P3_RX_LLH_HFIFO_ERROR_SHIFT                                           10
48356     #define NIG_REG_INT_MASK_8_P3_TX_LLH_HFIFO_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_HFIFO_ERROR .
48357     #define NIG_REG_INT_MASK_8_P3_TX_LLH_HFIFO_ERROR_SHIFT                                           11
48358     #define NIG_REG_INT_MASK_8_P3_LB_LLH_HFIFO_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_HFIFO_ERROR .
48359     #define NIG_REG_INT_MASK_8_P3_LB_LLH_HFIFO_ERROR_SHIFT                                           12
48360     #define NIG_REG_INT_MASK_8_P3_RX_LLH_RFIFO_ERROR                                                 (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_RX_LLH_RFIFO_ERROR .
48361     #define NIG_REG_INT_MASK_8_P3_RX_LLH_RFIFO_ERROR_SHIFT                                           13
48362     #define NIG_REG_INT_MASK_8_P3_TX_LLH_RFIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_LLH_RFIFO_ERROR .
48363     #define NIG_REG_INT_MASK_8_P3_TX_LLH_RFIFO_ERROR_SHIFT                                           14
48364     #define NIG_REG_INT_MASK_8_P3_LB_LLH_RFIFO_ERROR                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_LLH_RFIFO_ERROR .
48365     #define NIG_REG_INT_MASK_8_P3_LB_LLH_RFIFO_ERROR_SHIFT                                           15
48366     #define NIG_REG_INT_MASK_8_P3_STORM_FIFO_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_STORM_FIFO_ERROR .
48367     #define NIG_REG_INT_MASK_8_P3_STORM_FIFO_ERROR_SHIFT                                             16
48368     #define NIG_REG_INT_MASK_8_P3_STORM_DSCR_FIFO_ERROR                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_STORM_DSCR_FIFO_ERROR .
48369     #define NIG_REG_INT_MASK_8_P3_STORM_DSCR_FIFO_ERROR_SHIFT                                        17
48370     #define NIG_REG_INT_MASK_8_P3_TX_GNT_FIFO_ERROR                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_TX_GNT_FIFO_ERROR .
48371     #define NIG_REG_INT_MASK_8_P3_TX_GNT_FIFO_ERROR_SHIFT                                            18
48372     #define NIG_REG_INT_MASK_8_P3_LB_GNT_FIFO_ERROR                                                  (0x1<<19) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_8.P3_LB_GNT_FIFO_ERROR .
48373     #define NIG_REG_INT_MASK_8_P3_LB_GNT_FIFO_ERROR_SHIFT                                            19
48374 #define NIG_REG_INT_STS_WR_8                                                                         0x5000c8UL //Access:WR   DataWidth:0x14  Multi Field Register.  Chips: K2
48375     #define NIG_REG_INT_STS_WR_8_P3_PURELB_SOPQ_ERROR                                                (0x1<<0) // Error in the pure-loopback SOPQ.
48376     #define NIG_REG_INT_STS_WR_8_P3_PURELB_SOPQ_ERROR_SHIFT                                          0
48377     #define NIG_REG_INT_STS_WR_8_P3_RX_MACFIFO_ERROR                                                 (0x1<<1) // Error in RX MAC FIFO.
48378     #define NIG_REG_INT_STS_WR_8_P3_RX_MACFIFO_ERROR_SHIFT                                           1
48379     #define NIG_REG_INT_STS_WR_8_P3_TX_MACFIFO_ERROR                                                 (0x1<<2) // Error in TX MAC FIFO.
48380     #define NIG_REG_INT_STS_WR_8_P3_TX_MACFIFO_ERROR_SHIFT                                           2
48381     #define NIG_REG_INT_STS_WR_8_P3_TX_BMB_FIFO_ERROR                                                (0x1<<3) // FIFO error in TX BMB FIFO.
48382     #define NIG_REG_INT_STS_WR_8_P3_TX_BMB_FIFO_ERROR_SHIFT                                          3
48383     #define NIG_REG_INT_STS_WR_8_P3_LB_BMB_FIFO_ERROR                                                (0x1<<4) // FIFO error in LB BMB FIFO.
48384     #define NIG_REG_INT_STS_WR_8_P3_LB_BMB_FIFO_ERROR_SHIFT                                          4
48385     #define NIG_REG_INT_STS_WR_8_P3_TX_BTB_FIFO_ERROR                                                (0x1<<5) // Error in BTB FIFO for TX path.
48386     #define NIG_REG_INT_STS_WR_8_P3_TX_BTB_FIFO_ERROR_SHIFT                                          5
48387     #define NIG_REG_INT_STS_WR_8_P3_LB_BTB_FIFO_ERROR                                                (0x1<<6) // Error in BTB FIFO for LB path.
48388     #define NIG_REG_INT_STS_WR_8_P3_LB_BTB_FIFO_ERROR_SHIFT                                          6
48389     #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_DFIFO_ERROR                                               (0x1<<7) // Error in LLH Data FIFO.
48390     #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_DFIFO_ERROR_SHIFT                                         7
48391     #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_DFIFO_ERROR                                               (0x1<<8) // Error in LLH Data FIFO.
48392     #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_DFIFO_ERROR_SHIFT                                         8
48393     #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_DFIFO_ERROR                                               (0x1<<9) // Error in LLH Data FIFO.
48394     #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_DFIFO_ERROR_SHIFT                                         9
48395     #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_HFIFO_ERROR                                               (0x1<<10) // Error in LLH Header FIFO.
48396     #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_HFIFO_ERROR_SHIFT                                         10
48397     #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_HFIFO_ERROR                                               (0x1<<11) // Error in LLH Header FIFO.
48398     #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_HFIFO_ERROR_SHIFT                                         11
48399     #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_HFIFO_ERROR                                               (0x1<<12) // Error in LLH Header FIFO.
48400     #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_HFIFO_ERROR_SHIFT                                         12
48401     #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_RFIFO_ERROR                                               (0x1<<13) // Error in LLH Result FIFO.
48402     #define NIG_REG_INT_STS_WR_8_P3_RX_LLH_RFIFO_ERROR_SHIFT                                         13
48403     #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_RFIFO_ERROR                                               (0x1<<14) // Error in LLH Result FIFO.
48404     #define NIG_REG_INT_STS_WR_8_P3_TX_LLH_RFIFO_ERROR_SHIFT                                         14
48405     #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_RFIFO_ERROR                                               (0x1<<15) // Error in LLH Result FIFO.
48406     #define NIG_REG_INT_STS_WR_8_P3_LB_LLH_RFIFO_ERROR_SHIFT                                         15
48407     #define NIG_REG_INT_STS_WR_8_P3_STORM_FIFO_ERROR                                                 (0x1<<16) // FIFO error in STORM message FIFO.
48408     #define NIG_REG_INT_STS_WR_8_P3_STORM_FIFO_ERROR_SHIFT                                           16
48409     #define NIG_REG_INT_STS_WR_8_P3_STORM_DSCR_FIFO_ERROR                                            (0x1<<17) // FIFO error in STORM descriptor FIFO.
48410     #define NIG_REG_INT_STS_WR_8_P3_STORM_DSCR_FIFO_ERROR_SHIFT                                      17
48411     #define NIG_REG_INT_STS_WR_8_P3_TX_GNT_FIFO_ERROR                                                (0x1<<18) // Error in grant FIFO.
48412     #define NIG_REG_INT_STS_WR_8_P3_TX_GNT_FIFO_ERROR_SHIFT                                          18
48413     #define NIG_REG_INT_STS_WR_8_P3_LB_GNT_FIFO_ERROR                                                (0x1<<19) // Error in grant FIFO.
48414     #define NIG_REG_INT_STS_WR_8_P3_LB_GNT_FIFO_ERROR_SHIFT                                          19
48415 #define NIG_REG_INT_STS_CLR_8                                                                        0x5000ccUL //Access:RC   DataWidth:0x14  Multi Field Register.  Chips: K2
48416     #define NIG_REG_INT_STS_CLR_8_P3_PURELB_SOPQ_ERROR                                               (0x1<<0) // Error in the pure-loopback SOPQ.
48417     #define NIG_REG_INT_STS_CLR_8_P3_PURELB_SOPQ_ERROR_SHIFT                                         0
48418     #define NIG_REG_INT_STS_CLR_8_P3_RX_MACFIFO_ERROR                                                (0x1<<1) // Error in RX MAC FIFO.
48419     #define NIG_REG_INT_STS_CLR_8_P3_RX_MACFIFO_ERROR_SHIFT                                          1
48420     #define NIG_REG_INT_STS_CLR_8_P3_TX_MACFIFO_ERROR                                                (0x1<<2) // Error in TX MAC FIFO.
48421     #define NIG_REG_INT_STS_CLR_8_P3_TX_MACFIFO_ERROR_SHIFT                                          2
48422     #define NIG_REG_INT_STS_CLR_8_P3_TX_BMB_FIFO_ERROR                                               (0x1<<3) // FIFO error in TX BMB FIFO.
48423     #define NIG_REG_INT_STS_CLR_8_P3_TX_BMB_FIFO_ERROR_SHIFT                                         3
48424     #define NIG_REG_INT_STS_CLR_8_P3_LB_BMB_FIFO_ERROR                                               (0x1<<4) // FIFO error in LB BMB FIFO.
48425     #define NIG_REG_INT_STS_CLR_8_P3_LB_BMB_FIFO_ERROR_SHIFT                                         4
48426     #define NIG_REG_INT_STS_CLR_8_P3_TX_BTB_FIFO_ERROR                                               (0x1<<5) // Error in BTB FIFO for TX path.
48427     #define NIG_REG_INT_STS_CLR_8_P3_TX_BTB_FIFO_ERROR_SHIFT                                         5
48428     #define NIG_REG_INT_STS_CLR_8_P3_LB_BTB_FIFO_ERROR                                               (0x1<<6) // Error in BTB FIFO for LB path.
48429     #define NIG_REG_INT_STS_CLR_8_P3_LB_BTB_FIFO_ERROR_SHIFT                                         6
48430     #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_DFIFO_ERROR                                              (0x1<<7) // Error in LLH Data FIFO.
48431     #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_DFIFO_ERROR_SHIFT                                        7
48432     #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_DFIFO_ERROR                                              (0x1<<8) // Error in LLH Data FIFO.
48433     #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_DFIFO_ERROR_SHIFT                                        8
48434     #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_DFIFO_ERROR                                              (0x1<<9) // Error in LLH Data FIFO.
48435     #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_DFIFO_ERROR_SHIFT                                        9
48436     #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_HFIFO_ERROR                                              (0x1<<10) // Error in LLH Header FIFO.
48437     #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_HFIFO_ERROR_SHIFT                                        10
48438     #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_HFIFO_ERROR                                              (0x1<<11) // Error in LLH Header FIFO.
48439     #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_HFIFO_ERROR_SHIFT                                        11
48440     #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_HFIFO_ERROR                                              (0x1<<12) // Error in LLH Header FIFO.
48441     #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_HFIFO_ERROR_SHIFT                                        12
48442     #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_RFIFO_ERROR                                              (0x1<<13) // Error in LLH Result FIFO.
48443     #define NIG_REG_INT_STS_CLR_8_P3_RX_LLH_RFIFO_ERROR_SHIFT                                        13
48444     #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_RFIFO_ERROR                                              (0x1<<14) // Error in LLH Result FIFO.
48445     #define NIG_REG_INT_STS_CLR_8_P3_TX_LLH_RFIFO_ERROR_SHIFT                                        14
48446     #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_RFIFO_ERROR                                              (0x1<<15) // Error in LLH Result FIFO.
48447     #define NIG_REG_INT_STS_CLR_8_P3_LB_LLH_RFIFO_ERROR_SHIFT                                        15
48448     #define NIG_REG_INT_STS_CLR_8_P3_STORM_FIFO_ERROR                                                (0x1<<16) // FIFO error in STORM message FIFO.
48449     #define NIG_REG_INT_STS_CLR_8_P3_STORM_FIFO_ERROR_SHIFT                                          16
48450     #define NIG_REG_INT_STS_CLR_8_P3_STORM_DSCR_FIFO_ERROR                                           (0x1<<17) // FIFO error in STORM descriptor FIFO.
48451     #define NIG_REG_INT_STS_CLR_8_P3_STORM_DSCR_FIFO_ERROR_SHIFT                                     17
48452     #define NIG_REG_INT_STS_CLR_8_P3_TX_GNT_FIFO_ERROR                                               (0x1<<18) // Error in grant FIFO.
48453     #define NIG_REG_INT_STS_CLR_8_P3_TX_GNT_FIFO_ERROR_SHIFT                                         18
48454     #define NIG_REG_INT_STS_CLR_8_P3_LB_GNT_FIFO_ERROR                                               (0x1<<19) // Error in grant FIFO.
48455     #define NIG_REG_INT_STS_CLR_8_P3_LB_GNT_FIFO_ERROR_SHIFT                                         19
48456 #define NIG_REG_INT_STS_9                                                                            0x5000d0UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: K2
48457     #define NIG_REG_INT_STS_9_P3_TX_PAUSE_TOO_LONG_INT                                               (0x1<<0) // Triggered by TX path being paused for the configured period of time.
48458     #define NIG_REG_INT_STS_9_P3_TX_PAUSE_TOO_LONG_INT_SHIFT                                         0
48459     #define NIG_REG_INT_STS_9_P3_TC0_PAUSE_TOO_LONG_INT                                              (0x1<<1) // Triggered by TC being paused for the configured period of time.
48460     #define NIG_REG_INT_STS_9_P3_TC0_PAUSE_TOO_LONG_INT_SHIFT                                        1
48461     #define NIG_REG_INT_STS_9_P3_TC1_PAUSE_TOO_LONG_INT                                              (0x1<<2) // Triggered by TC being paused for the configured period of time.
48462     #define NIG_REG_INT_STS_9_P3_TC1_PAUSE_TOO_LONG_INT_SHIFT                                        2
48463     #define NIG_REG_INT_STS_9_P3_TC2_PAUSE_TOO_LONG_INT                                              (0x1<<3) // Triggered by TC being paused for the configured period of time.
48464     #define NIG_REG_INT_STS_9_P3_TC2_PAUSE_TOO_LONG_INT_SHIFT                                        3
48465     #define NIG_REG_INT_STS_9_P3_TC3_PAUSE_TOO_LONG_INT                                              (0x1<<4) // Triggered by TC being paused for the configured period of time.
48466     #define NIG_REG_INT_STS_9_P3_TC3_PAUSE_TOO_LONG_INT_SHIFT                                        4
48467     #define NIG_REG_INT_STS_9_P3_TC4_PAUSE_TOO_LONG_INT                                              (0x1<<5) // Triggered by TC being paused for the configured period of time.
48468     #define NIG_REG_INT_STS_9_P3_TC4_PAUSE_TOO_LONG_INT_SHIFT                                        5
48469     #define NIG_REG_INT_STS_9_P3_TC5_PAUSE_TOO_LONG_INT                                              (0x1<<6) // Triggered by TC being paused for the configured period of time.
48470     #define NIG_REG_INT_STS_9_P3_TC5_PAUSE_TOO_LONG_INT_SHIFT                                        6
48471     #define NIG_REG_INT_STS_9_P3_TC6_PAUSE_TOO_LONG_INT                                              (0x1<<7) // Triggered by TC being paused for the configured period of time.
48472     #define NIG_REG_INT_STS_9_P3_TC6_PAUSE_TOO_LONG_INT_SHIFT                                        7
48473     #define NIG_REG_INT_STS_9_P3_TC7_PAUSE_TOO_LONG_INT                                              (0x1<<8) // Triggered by TC being paused for the configured period of time.
48474     #define NIG_REG_INT_STS_9_P3_TC7_PAUSE_TOO_LONG_INT_SHIFT                                        8
48475     #define NIG_REG_INT_STS_9_P3_LB_TC0_PAUSE_TOO_LONG_INT                                           (0x1<<9) // Triggered by TC being paused for the configured period of time.
48476     #define NIG_REG_INT_STS_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                     9
48477     #define NIG_REG_INT_STS_9_P3_LB_TC1_PAUSE_TOO_LONG_INT                                           (0x1<<10) // Triggered by TC being paused for the configured period of time.
48478     #define NIG_REG_INT_STS_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                     10
48479     #define NIG_REG_INT_STS_9_P3_LB_TC2_PAUSE_TOO_LONG_INT                                           (0x1<<11) // Triggered by TC being paused for the configured period of time.
48480     #define NIG_REG_INT_STS_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                     11
48481     #define NIG_REG_INT_STS_9_P3_LB_TC3_PAUSE_TOO_LONG_INT                                           (0x1<<12) // Triggered by TC being paused for the configured period of time.
48482     #define NIG_REG_INT_STS_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                     12
48483     #define NIG_REG_INT_STS_9_P3_LB_TC4_PAUSE_TOO_LONG_INT                                           (0x1<<13) // Triggered by TC being paused for the configured period of time.
48484     #define NIG_REG_INT_STS_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                     13
48485     #define NIG_REG_INT_STS_9_P3_LB_TC5_PAUSE_TOO_LONG_INT                                           (0x1<<14) // Triggered by TC being paused for the configured period of time.
48486     #define NIG_REG_INT_STS_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                     14
48487     #define NIG_REG_INT_STS_9_P3_LB_TC6_PAUSE_TOO_LONG_INT                                           (0x1<<15) // Triggered by TC being paused for the configured period of time.
48488     #define NIG_REG_INT_STS_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                     15
48489     #define NIG_REG_INT_STS_9_P3_LB_TC7_PAUSE_TOO_LONG_INT                                           (0x1<<16) // Triggered by TC being paused for the configured period of time.
48490     #define NIG_REG_INT_STS_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                     16
48491     #define NIG_REG_INT_STS_9_P3_LB_TC8_PAUSE_TOO_LONG_INT                                           (0x1<<17) // Triggered by TC being paused for the configured period of time.
48492     #define NIG_REG_INT_STS_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                     17
48493 #define NIG_REG_INT_MASK_9                                                                           0x5000d4UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: K2
48494     #define NIG_REG_INT_MASK_9_P3_TX_PAUSE_TOO_LONG_INT                                              (0x1<<0) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TX_PAUSE_TOO_LONG_INT .
48495     #define NIG_REG_INT_MASK_9_P3_TX_PAUSE_TOO_LONG_INT_SHIFT                                        0
48496     #define NIG_REG_INT_MASK_9_P3_TC0_PAUSE_TOO_LONG_INT                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC0_PAUSE_TOO_LONG_INT .
48497     #define NIG_REG_INT_MASK_9_P3_TC0_PAUSE_TOO_LONG_INT_SHIFT                                       1
48498     #define NIG_REG_INT_MASK_9_P3_TC1_PAUSE_TOO_LONG_INT                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC1_PAUSE_TOO_LONG_INT .
48499     #define NIG_REG_INT_MASK_9_P3_TC1_PAUSE_TOO_LONG_INT_SHIFT                                       2
48500     #define NIG_REG_INT_MASK_9_P3_TC2_PAUSE_TOO_LONG_INT                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC2_PAUSE_TOO_LONG_INT .
48501     #define NIG_REG_INT_MASK_9_P3_TC2_PAUSE_TOO_LONG_INT_SHIFT                                       3
48502     #define NIG_REG_INT_MASK_9_P3_TC3_PAUSE_TOO_LONG_INT                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC3_PAUSE_TOO_LONG_INT .
48503     #define NIG_REG_INT_MASK_9_P3_TC3_PAUSE_TOO_LONG_INT_SHIFT                                       4
48504     #define NIG_REG_INT_MASK_9_P3_TC4_PAUSE_TOO_LONG_INT                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC4_PAUSE_TOO_LONG_INT .
48505     #define NIG_REG_INT_MASK_9_P3_TC4_PAUSE_TOO_LONG_INT_SHIFT                                       5
48506     #define NIG_REG_INT_MASK_9_P3_TC5_PAUSE_TOO_LONG_INT                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC5_PAUSE_TOO_LONG_INT .
48507     #define NIG_REG_INT_MASK_9_P3_TC5_PAUSE_TOO_LONG_INT_SHIFT                                       6
48508     #define NIG_REG_INT_MASK_9_P3_TC6_PAUSE_TOO_LONG_INT                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC6_PAUSE_TOO_LONG_INT .
48509     #define NIG_REG_INT_MASK_9_P3_TC6_PAUSE_TOO_LONG_INT_SHIFT                                       7
48510     #define NIG_REG_INT_MASK_9_P3_TC7_PAUSE_TOO_LONG_INT                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_TC7_PAUSE_TOO_LONG_INT .
48511     #define NIG_REG_INT_MASK_9_P3_TC7_PAUSE_TOO_LONG_INT_SHIFT                                       8
48512     #define NIG_REG_INT_MASK_9_P3_LB_TC0_PAUSE_TOO_LONG_INT                                          (0x1<<9) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC0_PAUSE_TOO_LONG_INT .
48513     #define NIG_REG_INT_MASK_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                    9
48514     #define NIG_REG_INT_MASK_9_P3_LB_TC1_PAUSE_TOO_LONG_INT                                          (0x1<<10) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC1_PAUSE_TOO_LONG_INT .
48515     #define NIG_REG_INT_MASK_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                    10
48516     #define NIG_REG_INT_MASK_9_P3_LB_TC2_PAUSE_TOO_LONG_INT                                          (0x1<<11) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC2_PAUSE_TOO_LONG_INT .
48517     #define NIG_REG_INT_MASK_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                    11
48518     #define NIG_REG_INT_MASK_9_P3_LB_TC3_PAUSE_TOO_LONG_INT                                          (0x1<<12) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC3_PAUSE_TOO_LONG_INT .
48519     #define NIG_REG_INT_MASK_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                    12
48520     #define NIG_REG_INT_MASK_9_P3_LB_TC4_PAUSE_TOO_LONG_INT                                          (0x1<<13) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC4_PAUSE_TOO_LONG_INT .
48521     #define NIG_REG_INT_MASK_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                    13
48522     #define NIG_REG_INT_MASK_9_P3_LB_TC5_PAUSE_TOO_LONG_INT                                          (0x1<<14) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC5_PAUSE_TOO_LONG_INT .
48523     #define NIG_REG_INT_MASK_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                    14
48524     #define NIG_REG_INT_MASK_9_P3_LB_TC6_PAUSE_TOO_LONG_INT                                          (0x1<<15) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC6_PAUSE_TOO_LONG_INT .
48525     #define NIG_REG_INT_MASK_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                    15
48526     #define NIG_REG_INT_MASK_9_P3_LB_TC7_PAUSE_TOO_LONG_INT                                          (0x1<<16) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC7_PAUSE_TOO_LONG_INT .
48527     #define NIG_REG_INT_MASK_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                    16
48528     #define NIG_REG_INT_MASK_9_P3_LB_TC8_PAUSE_TOO_LONG_INT                                          (0x1<<17) // This bit masks, when set, the Interrupt bit: NIG_REG_INT_STS_9.P3_LB_TC8_PAUSE_TOO_LONG_INT .
48529     #define NIG_REG_INT_MASK_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                    17
48530 #define NIG_REG_INT_STS_WR_9                                                                         0x5000d8UL //Access:WR   DataWidth:0x12  Multi Field Register.  Chips: K2
48531     #define NIG_REG_INT_STS_WR_9_P3_TX_PAUSE_TOO_LONG_INT                                            (0x1<<0) // Triggered by TX path being paused for the configured period of time.
48532     #define NIG_REG_INT_STS_WR_9_P3_TX_PAUSE_TOO_LONG_INT_SHIFT                                      0
48533     #define NIG_REG_INT_STS_WR_9_P3_TC0_PAUSE_TOO_LONG_INT                                           (0x1<<1) // Triggered by TC being paused for the configured period of time.
48534     #define NIG_REG_INT_STS_WR_9_P3_TC0_PAUSE_TOO_LONG_INT_SHIFT                                     1
48535     #define NIG_REG_INT_STS_WR_9_P3_TC1_PAUSE_TOO_LONG_INT                                           (0x1<<2) // Triggered by TC being paused for the configured period of time.
48536     #define NIG_REG_INT_STS_WR_9_P3_TC1_PAUSE_TOO_LONG_INT_SHIFT                                     2
48537     #define NIG_REG_INT_STS_WR_9_P3_TC2_PAUSE_TOO_LONG_INT                                           (0x1<<3) // Triggered by TC being paused for the configured period of time.
48538     #define NIG_REG_INT_STS_WR_9_P3_TC2_PAUSE_TOO_LONG_INT_SHIFT                                     3
48539     #define NIG_REG_INT_STS_WR_9_P3_TC3_PAUSE_TOO_LONG_INT                                           (0x1<<4) // Triggered by TC being paused for the configured period of time.
48540     #define NIG_REG_INT_STS_WR_9_P3_TC3_PAUSE_TOO_LONG_INT_SHIFT                                     4
48541     #define NIG_REG_INT_STS_WR_9_P3_TC4_PAUSE_TOO_LONG_INT                                           (0x1<<5) // Triggered by TC being paused for the configured period of time.
48542     #define NIG_REG_INT_STS_WR_9_P3_TC4_PAUSE_TOO_LONG_INT_SHIFT                                     5
48543     #define NIG_REG_INT_STS_WR_9_P3_TC5_PAUSE_TOO_LONG_INT                                           (0x1<<6) // Triggered by TC being paused for the configured period of time.
48544     #define NIG_REG_INT_STS_WR_9_P3_TC5_PAUSE_TOO_LONG_INT_SHIFT                                     6
48545     #define NIG_REG_INT_STS_WR_9_P3_TC6_PAUSE_TOO_LONG_INT                                           (0x1<<7) // Triggered by TC being paused for the configured period of time.
48546     #define NIG_REG_INT_STS_WR_9_P3_TC6_PAUSE_TOO_LONG_INT_SHIFT                                     7
48547     #define NIG_REG_INT_STS_WR_9_P3_TC7_PAUSE_TOO_LONG_INT                                           (0x1<<8) // Triggered by TC being paused for the configured period of time.
48548     #define NIG_REG_INT_STS_WR_9_P3_TC7_PAUSE_TOO_LONG_INT_SHIFT                                     8
48549     #define NIG_REG_INT_STS_WR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT                                        (0x1<<9) // Triggered by TC being paused for the configured period of time.
48550     #define NIG_REG_INT_STS_WR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                  9
48551     #define NIG_REG_INT_STS_WR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT                                        (0x1<<10) // Triggered by TC being paused for the configured period of time.
48552     #define NIG_REG_INT_STS_WR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                  10
48553     #define NIG_REG_INT_STS_WR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT                                        (0x1<<11) // Triggered by TC being paused for the configured period of time.
48554     #define NIG_REG_INT_STS_WR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                  11
48555     #define NIG_REG_INT_STS_WR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT                                        (0x1<<12) // Triggered by TC being paused for the configured period of time.
48556     #define NIG_REG_INT_STS_WR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                  12
48557     #define NIG_REG_INT_STS_WR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT                                        (0x1<<13) // Triggered by TC being paused for the configured period of time.
48558     #define NIG_REG_INT_STS_WR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                  13
48559     #define NIG_REG_INT_STS_WR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT                                        (0x1<<14) // Triggered by TC being paused for the configured period of time.
48560     #define NIG_REG_INT_STS_WR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                  14
48561     #define NIG_REG_INT_STS_WR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT                                        (0x1<<15) // Triggered by TC being paused for the configured period of time.
48562     #define NIG_REG_INT_STS_WR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                  15
48563     #define NIG_REG_INT_STS_WR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT                                        (0x1<<16) // Triggered by TC being paused for the configured period of time.
48564     #define NIG_REG_INT_STS_WR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                  16
48565     #define NIG_REG_INT_STS_WR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT                                        (0x1<<17) // Triggered by TC being paused for the configured period of time.
48566     #define NIG_REG_INT_STS_WR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                  17
48567 #define NIG_REG_INT_STS_CLR_9                                                                        0x5000dcUL //Access:RC   DataWidth:0x12  Multi Field Register.  Chips: K2
48568     #define NIG_REG_INT_STS_CLR_9_P3_TX_PAUSE_TOO_LONG_INT                                           (0x1<<0) // Triggered by TX path being paused for the configured period of time.
48569     #define NIG_REG_INT_STS_CLR_9_P3_TX_PAUSE_TOO_LONG_INT_SHIFT                                     0
48570     #define NIG_REG_INT_STS_CLR_9_P3_TC0_PAUSE_TOO_LONG_INT                                          (0x1<<1) // Triggered by TC being paused for the configured period of time.
48571     #define NIG_REG_INT_STS_CLR_9_P3_TC0_PAUSE_TOO_LONG_INT_SHIFT                                    1
48572     #define NIG_REG_INT_STS_CLR_9_P3_TC1_PAUSE_TOO_LONG_INT                                          (0x1<<2) // Triggered by TC being paused for the configured period of time.
48573     #define NIG_REG_INT_STS_CLR_9_P3_TC1_PAUSE_TOO_LONG_INT_SHIFT                                    2
48574     #define NIG_REG_INT_STS_CLR_9_P3_TC2_PAUSE_TOO_LONG_INT                                          (0x1<<3) // Triggered by TC being paused for the configured period of time.
48575     #define NIG_REG_INT_STS_CLR_9_P3_TC2_PAUSE_TOO_LONG_INT_SHIFT                                    3
48576     #define NIG_REG_INT_STS_CLR_9_P3_TC3_PAUSE_TOO_LONG_INT                                          (0x1<<4) // Triggered by TC being paused for the configured period of time.
48577     #define NIG_REG_INT_STS_CLR_9_P3_TC3_PAUSE_TOO_LONG_INT_SHIFT                                    4
48578     #define NIG_REG_INT_STS_CLR_9_P3_TC4_PAUSE_TOO_LONG_INT                                          (0x1<<5) // Triggered by TC being paused for the configured period of time.
48579     #define NIG_REG_INT_STS_CLR_9_P3_TC4_PAUSE_TOO_LONG_INT_SHIFT                                    5
48580     #define NIG_REG_INT_STS_CLR_9_P3_TC5_PAUSE_TOO_LONG_INT                                          (0x1<<6) // Triggered by TC being paused for the configured period of time.
48581     #define NIG_REG_INT_STS_CLR_9_P3_TC5_PAUSE_TOO_LONG_INT_SHIFT                                    6
48582     #define NIG_REG_INT_STS_CLR_9_P3_TC6_PAUSE_TOO_LONG_INT                                          (0x1<<7) // Triggered by TC being paused for the configured period of time.
48583     #define NIG_REG_INT_STS_CLR_9_P3_TC6_PAUSE_TOO_LONG_INT_SHIFT                                    7
48584     #define NIG_REG_INT_STS_CLR_9_P3_TC7_PAUSE_TOO_LONG_INT                                          (0x1<<8) // Triggered by TC being paused for the configured period of time.
48585     #define NIG_REG_INT_STS_CLR_9_P3_TC7_PAUSE_TOO_LONG_INT_SHIFT                                    8
48586     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT                                       (0x1<<9) // Triggered by TC being paused for the configured period of time.
48587     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC0_PAUSE_TOO_LONG_INT_SHIFT                                 9
48588     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT                                       (0x1<<10) // Triggered by TC being paused for the configured period of time.
48589     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC1_PAUSE_TOO_LONG_INT_SHIFT                                 10
48590     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT                                       (0x1<<11) // Triggered by TC being paused for the configured period of time.
48591     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC2_PAUSE_TOO_LONG_INT_SHIFT                                 11
48592     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT                                       (0x1<<12) // Triggered by TC being paused for the configured period of time.
48593     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC3_PAUSE_TOO_LONG_INT_SHIFT                                 12
48594     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT                                       (0x1<<13) // Triggered by TC being paused for the configured period of time.
48595     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC4_PAUSE_TOO_LONG_INT_SHIFT                                 13
48596     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT                                       (0x1<<14) // Triggered by TC being paused for the configured period of time.
48597     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC5_PAUSE_TOO_LONG_INT_SHIFT                                 14
48598     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT                                       (0x1<<15) // Triggered by TC being paused for the configured period of time.
48599     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC6_PAUSE_TOO_LONG_INT_SHIFT                                 15
48600     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT                                       (0x1<<16) // Triggered by TC being paused for the configured period of time.
48601     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC7_PAUSE_TOO_LONG_INT_SHIFT                                 16
48602     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT                                       (0x1<<17) // Triggered by TC being paused for the configured period of time.
48603     #define NIG_REG_INT_STS_CLR_9_P3_LB_TC8_PAUSE_TOO_LONG_INT_SHIFT                                 17
48604 #define NIG_REG_PRTY_MASK_BB_B0                                                                      0x5000a4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0
48605 #define NIG_REG_PRTY_MASK_K2                                                                         0x5000e4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: K2
48606     #define NIG_REG_PRTY_MASK_DATAPATH_PARITY_ERROR                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS.DATAPATH_PARITY_ERROR .
48607     #define NIG_REG_PRTY_MASK_DATAPATH_PARITY_ERROR_SHIFT                                            0
48608 #define NIG_REG_PRTY_MASK_H_0                                                                        0x500204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
48609     #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM107_I_MEM_PRTY .
48610     #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY_BB_A0_SHIFT                                      9
48611     #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY_K2                                               (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM107_I_MEM_PRTY .
48612     #define NIG_REG_PRTY_MASK_H_0_MEM107_I_MEM_PRTY_K2_SHIFT                                         0
48613     #define NIG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM103_I_MEM_PRTY .
48614     #define NIG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY_BB_A0_SHIFT                                      3
48615     #define NIG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM103_I_MEM_PRTY .
48616     #define NIG_REG_PRTY_MASK_H_0_MEM103_I_MEM_PRTY_K2_SHIFT                                         1
48617     #define NIG_REG_PRTY_MASK_H_0_MEM104_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM104_I_MEM_PRTY .
48618     #define NIG_REG_PRTY_MASK_H_0_MEM104_I_MEM_PRTY_SHIFT                                            2
48619     #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_BB_B0                                            (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM105_I_MEM_PRTY .
48620     #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_BB_B0_SHIFT                                      2
48621     #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_K2                                               (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM105_I_MEM_PRTY .
48622     #define NIG_REG_PRTY_MASK_H_0_MEM105_I_MEM_PRTY_K2_SHIFT                                         3
48623     #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM106_I_MEM_PRTY .
48624     #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_BB_A0_SHIFT                                      8
48625     #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM106_I_MEM_PRTY .
48626     #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_BB_B0_SHIFT                                      3
48627     #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_K2                                               (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM106_I_MEM_PRTY .
48628     #define NIG_REG_PRTY_MASK_H_0_MEM106_I_MEM_PRTY_K2_SHIFT                                         4
48629     #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM072_I_MEM_PRTY .
48630     #define NIG_REG_PRTY_MASK_H_0_MEM072_I_MEM_PRTY_SHIFT                                            5
48631     #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM071_I_MEM_PRTY .
48632     #define NIG_REG_PRTY_MASK_H_0_MEM071_I_MEM_PRTY_SHIFT                                            6
48633     #define NIG_REG_PRTY_MASK_H_0_MEM074_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM074_I_MEM_PRTY .
48634     #define NIG_REG_PRTY_MASK_H_0_MEM074_I_MEM_PRTY_SHIFT                                            7
48635     #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_BB_B0                                            (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY .
48636     #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_BB_B0_SHIFT                                      26
48637     #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2                                               (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM073_I_MEM_PRTY .
48638     #define NIG_REG_PRTY_MASK_H_0_MEM073_I_MEM_PRTY_K2_SHIFT                                         8
48639     #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM076_I_MEM_PRTY .
48640     #define NIG_REG_PRTY_MASK_H_0_MEM076_I_MEM_PRTY_SHIFT                                            9
48641     #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM075_I_MEM_PRTY .
48642     #define NIG_REG_PRTY_MASK_H_0_MEM075_I_MEM_PRTY_SHIFT                                            10
48643     #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_BB_A0                                            (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM078_I_MEM_PRTY .
48644     #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_BB_A0_SHIFT                                      28
48645     #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM078_I_MEM_PRTY .
48646     #define NIG_REG_PRTY_MASK_H_0_MEM078_I_MEM_PRTY_K2_SHIFT                                         11
48647     #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_BB_A0                                            (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM077_I_MEM_PRTY .
48648     #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_BB_A0_SHIFT                                      27
48649     #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM077_I_MEM_PRTY .
48650     #define NIG_REG_PRTY_MASK_H_0_MEM077_I_MEM_PRTY_K2_SHIFT                                         12
48651     #define NIG_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM055_I_MEM_PRTY .
48652     #define NIG_REG_PRTY_MASK_H_0_MEM055_I_MEM_PRTY_SHIFT                                            13
48653     #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM062_I_MEM_PRTY .
48654     #define NIG_REG_PRTY_MASK_H_0_MEM062_I_MEM_PRTY_SHIFT                                            14
48655     #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM063_I_MEM_PRTY .
48656     #define NIG_REG_PRTY_MASK_H_0_MEM063_I_MEM_PRTY_SHIFT                                            15
48657     #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM064_I_MEM_PRTY .
48658     #define NIG_REG_PRTY_MASK_H_0_MEM064_I_MEM_PRTY_SHIFT                                            16
48659     #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM065_I_MEM_PRTY .
48660     #define NIG_REG_PRTY_MASK_H_0_MEM065_I_MEM_PRTY_SHIFT                                            17
48661     #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM066_I_MEM_PRTY .
48662     #define NIG_REG_PRTY_MASK_H_0_MEM066_I_MEM_PRTY_SHIFT                                            18
48663     #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM067_I_MEM_PRTY .
48664     #define NIG_REG_PRTY_MASK_H_0_MEM067_I_MEM_PRTY_SHIFT                                            19
48665     #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM068_I_MEM_PRTY .
48666     #define NIG_REG_PRTY_MASK_H_0_MEM068_I_MEM_PRTY_SHIFT                                            20
48667     #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM069_I_MEM_PRTY .
48668     #define NIG_REG_PRTY_MASK_H_0_MEM069_I_MEM_PRTY_SHIFT                                            21
48669     #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_BB_A0                                            (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY .
48670     #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_BB_A0_SHIFT                                      26
48671     #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2                                               (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM070_I_MEM_PRTY .
48672     #define NIG_REG_PRTY_MASK_H_0_MEM070_I_MEM_PRTY_K2_SHIFT                                         22
48673     #define NIG_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM056_I_MEM_PRTY .
48674     #define NIG_REG_PRTY_MASK_H_0_MEM056_I_MEM_PRTY_SHIFT                                            23
48675     #define NIG_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM057_I_MEM_PRTY .
48676     #define NIG_REG_PRTY_MASK_H_0_MEM057_I_MEM_PRTY_SHIFT                                            24
48677     #define NIG_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM058_I_MEM_PRTY .
48678     #define NIG_REG_PRTY_MASK_H_0_MEM058_I_MEM_PRTY_SHIFT                                            25
48679     #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
48680     #define NIG_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_SHIFT                                            26
48681     #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
48682     #define NIG_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_SHIFT                                            27
48683     #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM061_I_MEM_PRTY .
48684     #define NIG_REG_PRTY_MASK_H_0_MEM061_I_MEM_PRTY_SHIFT                                            28
48685     #define NIG_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
48686     #define NIG_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_SHIFT                                            29
48687     #define NIG_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
48688     #define NIG_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_SHIFT                                            30
48689     #define NIG_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM051_I_MEM_PRTY .
48690     #define NIG_REG_PRTY_MASK_H_0_MEM051_I_MEM_PRTY_SHIFT                                            0
48691     #define NIG_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM052_I_MEM_PRTY .
48692     #define NIG_REG_PRTY_MASK_H_0_MEM052_I_MEM_PRTY_SHIFT                                            1
48693     #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM090_I_MEM_PRTY .
48694     #define NIG_REG_PRTY_MASK_H_0_MEM090_I_MEM_PRTY_SHIFT                                            4
48695     #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_BB_A0                                            (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM089_I_MEM_PRTY .
48696     #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_BB_A0_SHIFT                                      6
48697     #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_BB_B0                                            (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM089_I_MEM_PRTY .
48698     #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_BB_B0_SHIFT                                      5
48699     #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM089_I_MEM_PRTY .
48700     #define NIG_REG_PRTY_MASK_H_0_MEM089_I_MEM_PRTY_K2_SHIFT                                         5
48701     #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM092_I_MEM_PRTY .
48702     #define NIG_REG_PRTY_MASK_H_0_MEM092_I_MEM_PRTY_SHIFT                                            6
48703     #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM091_I_MEM_PRTY .
48704     #define NIG_REG_PRTY_MASK_H_0_MEM091_I_MEM_PRTY_SHIFT                                            7
48705     #define NIG_REG_PRTY_MASK_H_0_MEM109_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM109_I_MEM_PRTY .
48706     #define NIG_REG_PRTY_MASK_H_0_MEM109_I_MEM_PRTY_SHIFT                                            8
48707     #define NIG_REG_PRTY_MASK_H_0_MEM110_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM110_I_MEM_PRTY .
48708     #define NIG_REG_PRTY_MASK_H_0_MEM110_I_MEM_PRTY_SHIFT                                            9
48709     #define NIG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
48710     #define NIG_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            10
48711     #define NIG_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
48712     #define NIG_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                            11
48713     #define NIG_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
48714     #define NIG_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                            12
48715     #define NIG_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
48716     #define NIG_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                            13
48717     #define NIG_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
48718     #define NIG_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                            14
48719     #define NIG_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
48720     #define NIG_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                            15
48721     #define NIG_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
48722     #define NIG_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                            16
48723     #define NIG_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
48724     #define NIG_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT                                            17
48725     #define NIG_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
48726     #define NIG_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_SHIFT                                            18
48727     #define NIG_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
48728     #define NIG_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_SHIFT                                            19
48729     #define NIG_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
48730     #define NIG_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            20
48731     #define NIG_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
48732     #define NIG_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            21
48733     #define NIG_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
48734     #define NIG_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            22
48735     #define NIG_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
48736     #define NIG_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                            23
48737     #define NIG_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
48738     #define NIG_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                            24
48739     #define NIG_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
48740     #define NIG_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                            25
48741     #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_BB_A0                                            (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM080_I_MEM_PRTY .
48742     #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_BB_A0_SHIFT                                      30
48743     #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_BB_B0                                            (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM080_I_MEM_PRTY .
48744     #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_BB_B0_SHIFT                                      27
48745     #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_K2                                               (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM080_I_MEM_PRTY .
48746     #define NIG_REG_PRTY_MASK_H_0_MEM080_I_MEM_PRTY_K2_SHIFT                                         27
48747     #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM081_I_MEM_PRTY .
48748     #define NIG_REG_PRTY_MASK_H_0_MEM081_I_MEM_PRTY_SHIFT                                            28
48749     #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM082_I_MEM_PRTY .
48750     #define NIG_REG_PRTY_MASK_H_0_MEM082_I_MEM_PRTY_SHIFT                                            29
48751     #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM083_I_MEM_PRTY .
48752     #define NIG_REG_PRTY_MASK_H_0_MEM083_I_MEM_PRTY_SHIFT                                            30
48753     #define NIG_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
48754     #define NIG_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_SHIFT                                            0
48755     #define NIG_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM049_I_MEM_PRTY .
48756     #define NIG_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY_SHIFT                                            1
48757     #define NIG_REG_PRTY_MASK_H_0_MEM102_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM102_I_MEM_PRTY .
48758     #define NIG_REG_PRTY_MASK_H_0_MEM102_I_MEM_PRTY_SHIFT                                            2
48759     #define NIG_REG_PRTY_MASK_H_0_MEM087_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM087_I_MEM_PRTY .
48760     #define NIG_REG_PRTY_MASK_H_0_MEM087_I_MEM_PRTY_SHIFT                                            4
48761     #define NIG_REG_PRTY_MASK_H_0_MEM086_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM086_I_MEM_PRTY .
48762     #define NIG_REG_PRTY_MASK_H_0_MEM086_I_MEM_PRTY_SHIFT                                            5
48763     #define NIG_REG_PRTY_MASK_H_0_MEM088_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM088_I_MEM_PRTY .
48764     #define NIG_REG_PRTY_MASK_H_0_MEM088_I_MEM_PRTY_SHIFT                                            7
48765     #define NIG_REG_PRTY_MASK_H_0_MEM079_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_0.MEM079_I_MEM_PRTY .
48766     #define NIG_REG_PRTY_MASK_H_0_MEM079_I_MEM_PRTY_SHIFT                                            29
48767 #define NIG_REG_PRTY_MASK_H_1                                                                        0x500214UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
48768     #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM047_I_MEM_PRTY .
48769     #define NIG_REG_PRTY_MASK_H_1_MEM047_I_MEM_PRTY_SHIFT                                            0
48770     #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM048_I_MEM_PRTY .
48771     #define NIG_REG_PRTY_MASK_H_1_MEM048_I_MEM_PRTY_SHIFT                                            1
48772     #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
48773     #define NIG_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_SHIFT                                            2
48774     #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
48775     #define NIG_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_SHIFT                                            3
48776     #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
48777     #define NIG_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_SHIFT                                            4
48778     #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
48779     #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_BB_A0_SHIFT                                      11
48780     #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
48781     #define NIG_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_K2_SHIFT                                         5
48782     #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_BB_A0                                            (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
48783     #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_BB_A0_SHIFT                                      21
48784     #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
48785     #define NIG_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_K2_SHIFT                                         6
48786     #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_BB_A0                                            (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
48787     #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_BB_A0_SHIFT                                      22
48788     #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
48789     #define NIG_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_K2_SHIFT                                         7
48790     #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
48791     #define NIG_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_SHIFT                                            8
48792     #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
48793     #define NIG_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_SHIFT                                            9
48794     #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY .
48795     #define NIG_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_SHIFT                                            10
48796     #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM039_I_MEM_PRTY .
48797     #define NIG_REG_PRTY_MASK_H_1_MEM039_I_MEM_PRTY_SHIFT                                            11
48798     #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM040_I_MEM_PRTY .
48799     #define NIG_REG_PRTY_MASK_H_1_MEM040_I_MEM_PRTY_SHIFT                                            12
48800     #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM041_I_MEM_PRTY .
48801     #define NIG_REG_PRTY_MASK_H_1_MEM041_I_MEM_PRTY_SHIFT                                            13
48802     #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM042_I_MEM_PRTY .
48803     #define NIG_REG_PRTY_MASK_H_1_MEM042_I_MEM_PRTY_SHIFT                                            14
48804     #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM043_I_MEM_PRTY .
48805     #define NIG_REG_PRTY_MASK_H_1_MEM043_I_MEM_PRTY_SHIFT                                            15
48806     #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM044_I_MEM_PRTY .
48807     #define NIG_REG_PRTY_MASK_H_1_MEM044_I_MEM_PRTY_SHIFT                                            16
48808     #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM045_I_MEM_PRTY .
48809     #define NIG_REG_PRTY_MASK_H_1_MEM045_I_MEM_PRTY_SHIFT                                            17
48810     #define NIG_REG_PRTY_MASK_H_1_MEM091_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM091_I_MEM_PRTY .
48811     #define NIG_REG_PRTY_MASK_H_1_MEM091_I_MEM_PRTY_SHIFT                                            18
48812     #define NIG_REG_PRTY_MASK_H_1_MEM092_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM092_I_MEM_PRTY .
48813     #define NIG_REG_PRTY_MASK_H_1_MEM092_I_MEM_PRTY_SHIFT                                            19
48814     #define NIG_REG_PRTY_MASK_H_1_MEM093_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM093_I_MEM_PRTY .
48815     #define NIG_REG_PRTY_MASK_H_1_MEM093_I_MEM_PRTY_SHIFT                                            20
48816     #define NIG_REG_PRTY_MASK_H_1_MEM094_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM094_I_MEM_PRTY .
48817     #define NIG_REG_PRTY_MASK_H_1_MEM094_I_MEM_PRTY_SHIFT                                            21
48818     #define NIG_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
48819     #define NIG_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_SHIFT                                            22
48820     #define NIG_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
48821     #define NIG_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_SHIFT                                            23
48822     #define NIG_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
48823     #define NIG_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_SHIFT                                            24
48824     #define NIG_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
48825     #define NIG_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_SHIFT                                            25
48826     #define NIG_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
48827     #define NIG_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_SHIFT                                            26
48828     #define NIG_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
48829     #define NIG_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_SHIFT                                            27
48830     #define NIG_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
48831     #define NIG_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_SHIFT                                            28
48832     #define NIG_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM018_I_MEM_PRTY .
48833     #define NIG_REG_PRTY_MASK_H_1_MEM018_I_MEM_PRTY_SHIFT                                            29
48834     #define NIG_REG_PRTY_MASK_H_1_MEM095_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM095_I_MEM_PRTY .
48835     #define NIG_REG_PRTY_MASK_H_1_MEM095_I_MEM_PRTY_SHIFT                                            30
48836     #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM084_I_MEM_PRTY .
48837     #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY_BB_A0_SHIFT                                      3
48838     #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY_BB_B0                                            (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM084_I_MEM_PRTY .
48839     #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY_BB_B0_SHIFT                                      0
48840     #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY_K2                                               (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM084_I_MEM_PRTY .
48841     #define NIG_REG_PRTY_MASK_H_1_MEM084_I_MEM_PRTY_K2_SHIFT                                         0
48842     #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM085_I_MEM_PRTY .
48843     #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_BB_A0_SHIFT                                      4
48844     #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM085_I_MEM_PRTY .
48845     #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_BB_B0_SHIFT                                      1
48846     #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM085_I_MEM_PRTY .
48847     #define NIG_REG_PRTY_MASK_H_1_MEM085_I_MEM_PRTY_K2_SHIFT                                         1
48848     #define NIG_REG_PRTY_MASK_H_1_MEM086_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM086_I_MEM_PRTY .
48849     #define NIG_REG_PRTY_MASK_H_1_MEM086_I_MEM_PRTY_SHIFT                                            2
48850     #define NIG_REG_PRTY_MASK_H_1_MEM087_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM087_I_MEM_PRTY .
48851     #define NIG_REG_PRTY_MASK_H_1_MEM087_I_MEM_PRTY_SHIFT                                            3
48852     #define NIG_REG_PRTY_MASK_H_1_MEM088_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM088_I_MEM_PRTY .
48853     #define NIG_REG_PRTY_MASK_H_1_MEM088_I_MEM_PRTY_SHIFT                                            4
48854     #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM074_I_MEM_PRTY .
48855     #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_BB_A0_SHIFT                                      8
48856     #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_BB_B0                                            (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM074_I_MEM_PRTY .
48857     #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_BB_B0_SHIFT                                      5
48858     #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM074_I_MEM_PRTY .
48859     #define NIG_REG_PRTY_MASK_H_1_MEM074_I_MEM_PRTY_K2_SHIFT                                         5
48860     #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM075_I_MEM_PRTY .
48861     #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB_A0_SHIFT                                      9
48862     #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB_B0                                            (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM075_I_MEM_PRTY .
48863     #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_BB_B0_SHIFT                                      6
48864     #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM075_I_MEM_PRTY .
48865     #define NIG_REG_PRTY_MASK_H_1_MEM075_I_MEM_PRTY_K2_SHIFT                                         6
48866     #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB_A0                                            (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM076_I_MEM_PRTY .
48867     #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB_A0_SHIFT                                      10
48868     #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM076_I_MEM_PRTY .
48869     #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_BB_B0_SHIFT                                      7
48870     #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM076_I_MEM_PRTY .
48871     #define NIG_REG_PRTY_MASK_H_1_MEM076_I_MEM_PRTY_K2_SHIFT                                         7
48872     #define NIG_REG_PRTY_MASK_H_1_MEM077_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM077_I_MEM_PRTY .
48873     #define NIG_REG_PRTY_MASK_H_1_MEM077_I_MEM_PRTY_SHIFT                                            8
48874     #define NIG_REG_PRTY_MASK_H_1_MEM078_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM078_I_MEM_PRTY .
48875     #define NIG_REG_PRTY_MASK_H_1_MEM078_I_MEM_PRTY_SHIFT                                            9
48876     #define NIG_REG_PRTY_MASK_H_1_MEM079_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM079_I_MEM_PRTY .
48877     #define NIG_REG_PRTY_MASK_H_1_MEM079_I_MEM_PRTY_SHIFT                                            10
48878     #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB_A0                                            (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
48879     #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB_A0_SHIFT                                      23
48880     #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
48881     #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_BB_B0_SHIFT                                      11
48882     #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
48883     #define NIG_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_K2_SHIFT                                         11
48884     #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_BB_A0                                            (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY .
48885     #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_BB_A0_SHIFT                                      15
48886     #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY .
48887     #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_BB_B0_SHIFT                                      12
48888     #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY .
48889     #define NIG_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_K2_SHIFT                                         12
48890     #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM065_I_MEM_PRTY .
48891     #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY_BB_A0_SHIFT                                      16
48892     #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM065_I_MEM_PRTY .
48893     #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY_BB_B0_SHIFT                                      13
48894     #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM065_I_MEM_PRTY .
48895     #define NIG_REG_PRTY_MASK_H_1_MEM065_I_MEM_PRTY_K2_SHIFT                                         13
48896     #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM066_I_MEM_PRTY .
48897     #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_BB_A0_SHIFT                                      17
48898     #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM066_I_MEM_PRTY .
48899     #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_BB_B0_SHIFT                                      14
48900     #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM066_I_MEM_PRTY .
48901     #define NIG_REG_PRTY_MASK_H_1_MEM066_I_MEM_PRTY_K2_SHIFT                                         14
48902     #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM067_I_MEM_PRTY .
48903     #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_BB_A0_SHIFT                                      18
48904     #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM067_I_MEM_PRTY .
48905     #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_BB_B0_SHIFT                                      15
48906     #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM067_I_MEM_PRTY .
48907     #define NIG_REG_PRTY_MASK_H_1_MEM067_I_MEM_PRTY_K2_SHIFT                                         15
48908     #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM068_I_MEM_PRTY .
48909     #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_BB_A0_SHIFT                                      19
48910     #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM068_I_MEM_PRTY .
48911     #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_BB_B0_SHIFT                                      16
48912     #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM068_I_MEM_PRTY .
48913     #define NIG_REG_PRTY_MASK_H_1_MEM068_I_MEM_PRTY_K2_SHIFT                                         16
48914     #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM069_I_MEM_PRTY .
48915     #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY_BB_A0_SHIFT                                      20
48916     #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM069_I_MEM_PRTY .
48917     #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY_BB_B0_SHIFT                                      17
48918     #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM069_I_MEM_PRTY .
48919     #define NIG_REG_PRTY_MASK_H_1_MEM069_I_MEM_PRTY_K2_SHIFT                                         17
48920     #define NIG_REG_PRTY_MASK_H_1_MEM070_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM070_I_MEM_PRTY .
48921     #define NIG_REG_PRTY_MASK_H_1_MEM070_I_MEM_PRTY_SHIFT                                            18
48922     #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_BB_A0                                            (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM071_I_MEM_PRTY .
48923     #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_BB_A0_SHIFT                                      5
48924     #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_BB_B0                                            (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM071_I_MEM_PRTY .
48925     #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_BB_B0_SHIFT                                      19
48926     #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM071_I_MEM_PRTY .
48927     #define NIG_REG_PRTY_MASK_H_1_MEM071_I_MEM_PRTY_K2_SHIFT                                         19
48928     #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB_A0                                            (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM072_I_MEM_PRTY .
48929     #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB_A0_SHIFT                                      6
48930     #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB_B0                                            (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM072_I_MEM_PRTY .
48931     #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_BB_B0_SHIFT                                      20
48932     #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_K2                                               (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM072_I_MEM_PRTY .
48933     #define NIG_REG_PRTY_MASK_H_1_MEM072_I_MEM_PRTY_K2_SHIFT                                         20
48934     #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
48935     #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB_A0_SHIFT                                      24
48936     #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB_B0                                            (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
48937     #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_BB_B0_SHIFT                                      21
48938     #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_K2                                               (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
48939     #define NIG_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_K2_SHIFT                                         21
48940     #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_A0                                            (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
48941     #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_A0_SHIFT                                      25
48942     #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_B0                                            (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
48943     #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_B0_SHIFT                                      22
48944     #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2                                               (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
48945     #define NIG_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2_SHIFT                                         22
48946     #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_A0                                            (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
48947     #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_A0_SHIFT                                      26
48948     #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_B0                                            (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
48949     #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_B0_SHIFT                                      23
48950     #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_K2                                               (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
48951     #define NIG_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_K2_SHIFT                                         23
48952     #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB_A0                                            (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
48953     #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB_A0_SHIFT                                      27
48954     #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB_B0                                            (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
48955     #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_BB_B0_SHIFT                                      24
48956     #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_K2                                               (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
48957     #define NIG_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_K2_SHIFT                                         24
48958     #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB_A0                                            (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
48959     #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB_A0_SHIFT                                      28
48960     #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB_B0                                            (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
48961     #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_BB_B0_SHIFT                                      25
48962     #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_K2                                               (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
48963     #define NIG_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_K2_SHIFT                                         25
48964     #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
48965     #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_BB_A0_SHIFT                                      12
48966     #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_BB_B0                                            (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
48967     #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_BB_B0_SHIFT                                      26
48968     #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_K2                                               (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
48969     #define NIG_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_K2_SHIFT                                         26
48970     #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
48971     #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_BB_A0_SHIFT                                      13
48972     #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_BB_B0                                            (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
48973     #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_BB_B0_SHIFT                                      27
48974     #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_K2                                               (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
48975     #define NIG_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_K2_SHIFT                                         27
48976     #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY .
48977     #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_BB_A0_SHIFT                                      14
48978     #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_BB_B0                                            (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY .
48979     #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_BB_B0_SHIFT                                      28
48980     #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_K2                                               (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY .
48981     #define NIG_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_K2_SHIFT                                         28
48982     #define NIG_REG_PRTY_MASK_H_1_MEM099_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM099_I_MEM_PRTY .
48983     #define NIG_REG_PRTY_MASK_H_1_MEM099_I_MEM_PRTY_SHIFT                                            29
48984     #define NIG_REG_PRTY_MASK_H_1_MEM100_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM100_I_MEM_PRTY .
48985     #define NIG_REG_PRTY_MASK_H_1_MEM100_I_MEM_PRTY_SHIFT                                            30
48986     #define NIG_REG_PRTY_MASK_H_1_MEM081_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM081_I_MEM_PRTY .
48987     #define NIG_REG_PRTY_MASK_H_1_MEM081_I_MEM_PRTY_SHIFT                                            0
48988     #define NIG_REG_PRTY_MASK_H_1_MEM082_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM082_I_MEM_PRTY .
48989     #define NIG_REG_PRTY_MASK_H_1_MEM082_I_MEM_PRTY_SHIFT                                            1
48990     #define NIG_REG_PRTY_MASK_H_1_MEM083_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM083_I_MEM_PRTY .
48991     #define NIG_REG_PRTY_MASK_H_1_MEM083_I_MEM_PRTY_SHIFT                                            2
48992     #define NIG_REG_PRTY_MASK_H_1_MEM073_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM073_I_MEM_PRTY .
48993     #define NIG_REG_PRTY_MASK_H_1_MEM073_I_MEM_PRTY_SHIFT                                            7
48994     #define NIG_REG_PRTY_MASK_H_1_MEM096_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM096_I_MEM_PRTY .
48995     #define NIG_REG_PRTY_MASK_H_1_MEM096_I_MEM_PRTY_SHIFT                                            29
48996     #define NIG_REG_PRTY_MASK_H_1_MEM097_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_1.MEM097_I_MEM_PRTY .
48997     #define NIG_REG_PRTY_MASK_H_1_MEM097_I_MEM_PRTY_SHIFT                                            30
48998 #define NIG_REG_PRTY_MASK_H_2                                                                        0x500224UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
48999     #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY_BB_B0                                            (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM096_I_MEM_PRTY .
49000     #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY_BB_B0_SHIFT                                      26
49001     #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY_K2                                               (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM096_I_MEM_PRTY .
49002     #define NIG_REG_PRTY_MASK_H_2_MEM096_I_MEM_PRTY_K2_SHIFT                                         0
49003     #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_BB_B0                                            (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM097_I_MEM_PRTY .
49004     #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_BB_B0_SHIFT                                      29
49005     #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM097_I_MEM_PRTY .
49006     #define NIG_REG_PRTY_MASK_H_2_MEM097_I_MEM_PRTY_K2_SHIFT                                         1
49007     #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM098_I_MEM_PRTY .
49008     #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_BB_A0_SHIFT                                      4
49009     #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_BB_B0                                            (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM098_I_MEM_PRTY .
49010     #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_BB_B0_SHIFT                                      30
49011     #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_K2                                               (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM098_I_MEM_PRTY .
49012     #define NIG_REG_PRTY_MASK_H_2_MEM098_I_MEM_PRTY_K2_SHIFT                                         2
49013     #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY .
49014     #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB_A0_SHIFT                                      12
49015     #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB_B0                                            (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY .
49016     #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_BB_B0_SHIFT                                      21
49017     #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2                                               (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_I_MEM_PRTY .
49018     #define NIG_REG_PRTY_MASK_H_2_MEM031_I_MEM_PRTY_K2_SHIFT                                         3
49019     #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_BB_A0                                            (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM032_I_MEM_PRTY .
49020     #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_BB_A0_SHIFT                                      21
49021     #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_K2                                               (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM032_I_MEM_PRTY .
49022     #define NIG_REG_PRTY_MASK_H_2_MEM032_I_MEM_PRTY_K2_SHIFT                                         4
49023     #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM033_I_MEM_PRTY .
49024     #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_BB_B0_SHIFT                                      12
49025     #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM033_I_MEM_PRTY .
49026     #define NIG_REG_PRTY_MASK_H_2_MEM033_I_MEM_PRTY_K2_SHIFT                                         5
49027     #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY_BB_B0                                            (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM034_I_MEM_PRTY .
49028     #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY_BB_B0_SHIFT                                      23
49029     #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM034_I_MEM_PRTY .
49030     #define NIG_REG_PRTY_MASK_H_2_MEM034_I_MEM_PRTY_K2_SHIFT                                         6
49031     #define NIG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM019_I_MEM_PRTY .
49032     #define NIG_REG_PRTY_MASK_H_2_MEM019_I_MEM_PRTY_SHIFT                                            7
49033     #define NIG_REG_PRTY_MASK_H_2_MEM020_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM020_I_MEM_PRTY .
49034     #define NIG_REG_PRTY_MASK_H_2_MEM020_I_MEM_PRTY_SHIFT                                            8
49035     #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM021_I_MEM_PRTY .
49036     #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_BB_A0_SHIFT                                      24
49037     #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_BB_B0                                            (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM021_I_MEM_PRTY .
49038     #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_BB_B0_SHIFT                                      27
49039     #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM021_I_MEM_PRTY .
49040     #define NIG_REG_PRTY_MASK_H_2_MEM021_I_MEM_PRTY_K2_SHIFT                                         9
49041     #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_BB_A0                                            (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM022_I_MEM_PRTY .
49042     #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_BB_A0_SHIFT                                      25
49043     #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_BB_B0                                            (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM022_I_MEM_PRTY .
49044     #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_BB_B0_SHIFT                                      28
49045     #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM022_I_MEM_PRTY .
49046     #define NIG_REG_PRTY_MASK_H_2_MEM022_I_MEM_PRTY_K2_SHIFT                                         10
49047     #define NIG_REG_PRTY_MASK_H_2_MEM099_I_MEM_PRTY_BB_A0                                            (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM099_I_MEM_PRTY .
49048     #define NIG_REG_PRTY_MASK_H_2_MEM099_I_MEM_PRTY_BB_A0_SHIFT                                      5
49049     #define NIG_REG_PRTY_MASK_H_2_MEM099_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM099_I_MEM_PRTY .
49050     #define NIG_REG_PRTY_MASK_H_2_MEM099_I_MEM_PRTY_K2_SHIFT                                         11
49051     #define NIG_REG_PRTY_MASK_H_2_MEM100_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM100_I_MEM_PRTY .
49052     #define NIG_REG_PRTY_MASK_H_2_MEM100_I_MEM_PRTY_BB_A0_SHIFT                                      13
49053     #define NIG_REG_PRTY_MASK_H_2_MEM100_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM100_I_MEM_PRTY .
49054     #define NIG_REG_PRTY_MASK_H_2_MEM100_I_MEM_PRTY_K2_SHIFT                                         12
49055     #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM101_I_MEM_PRTY .
49056     #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_BB_A0_SHIFT                                      14
49057     #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM101_I_MEM_PRTY .
49058     #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_BB_B0_SHIFT                                      4
49059     #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM101_I_MEM_PRTY .
49060     #define NIG_REG_PRTY_MASK_H_2_MEM101_I_MEM_PRTY_K2_SHIFT                                         13
49061     #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_BB_B0                                            (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM102_I_MEM_PRTY .
49062     #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_BB_B0_SHIFT                                      5
49063     #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM102_I_MEM_PRTY .
49064     #define NIG_REG_PRTY_MASK_H_2_MEM102_I_MEM_PRTY_K2_SHIFT                                         14
49065     #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_BB_A0                                            (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM023_I_MEM_PRTY .
49066     #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_BB_A0_SHIFT                                      28
49067     #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM023_I_MEM_PRTY .
49068     #define NIG_REG_PRTY_MASK_H_2_MEM023_I_MEM_PRTY_K2_SHIFT                                         15
49069     #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_BB_A0                                            (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM024_I_MEM_PRTY .
49070     #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_BB_A0_SHIFT                                      29
49071     #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM024_I_MEM_PRTY .
49072     #define NIG_REG_PRTY_MASK_H_2_MEM024_I_MEM_PRTY_K2_SHIFT                                         16
49073     #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_BB_A0                                            (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY .
49074     #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_BB_A0_SHIFT                                      2
49075     #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_BB_B0                                            (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY .
49076     #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_BB_B0_SHIFT                                      2
49077     #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM025_I_MEM_PRTY .
49078     #define NIG_REG_PRTY_MASK_H_2_MEM025_I_MEM_PRTY_K2_SHIFT                                         17
49079     #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY .
49080     #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB_A0_SHIFT                                      3
49081     #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY .
49082     #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_BB_B0_SHIFT                                      3
49083     #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM026_I_MEM_PRTY .
49084     #define NIG_REG_PRTY_MASK_H_2_MEM026_I_MEM_PRTY_K2_SHIFT                                         18
49085     #define NIG_REG_PRTY_MASK_H_2_MEM083_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM083_I_MEM_PRTY .
49086     #define NIG_REG_PRTY_MASK_H_2_MEM083_I_MEM_PRTY_SHIFT                                            19
49087     #define NIG_REG_PRTY_MASK_H_2_MEM084_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM084_I_MEM_PRTY .
49088     #define NIG_REG_PRTY_MASK_H_2_MEM084_I_MEM_PRTY_SHIFT                                            20
49089     #define NIG_REG_PRTY_MASK_H_2_MEM085_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM085_I_MEM_PRTY .
49090     #define NIG_REG_PRTY_MASK_H_2_MEM085_I_MEM_PRTY_SHIFT                                            21
49091     #define NIG_REG_PRTY_MASK_H_2_MEM086_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM086_I_MEM_PRTY .
49092     #define NIG_REG_PRTY_MASK_H_2_MEM086_I_MEM_PRTY_SHIFT                                            22
49093     #define NIG_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM007_I_MEM_PRTY .
49094     #define NIG_REG_PRTY_MASK_H_2_MEM007_I_MEM_PRTY_SHIFT                                            23
49095     #define NIG_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM008_I_MEM_PRTY .
49096     #define NIG_REG_PRTY_MASK_H_2_MEM008_I_MEM_PRTY_SHIFT                                            24
49097     #define NIG_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM009_I_MEM_PRTY .
49098     #define NIG_REG_PRTY_MASK_H_2_MEM009_I_MEM_PRTY_SHIFT                                            25
49099     #define NIG_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM010_I_MEM_PRTY .
49100     #define NIG_REG_PRTY_MASK_H_2_MEM010_I_MEM_PRTY_SHIFT                                            26
49101     #define NIG_REG_PRTY_MASK_H_2_MEM087_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM087_I_MEM_PRTY .
49102     #define NIG_REG_PRTY_MASK_H_2_MEM087_I_MEM_PRTY_SHIFT                                            27
49103     #define NIG_REG_PRTY_MASK_H_2_MEM088_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM088_I_MEM_PRTY .
49104     #define NIG_REG_PRTY_MASK_H_2_MEM088_I_MEM_PRTY_SHIFT                                            28
49105     #define NIG_REG_PRTY_MASK_H_2_MEM089_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM089_I_MEM_PRTY .
49106     #define NIG_REG_PRTY_MASK_H_2_MEM089_I_MEM_PRTY_SHIFT                                            29
49107     #define NIG_REG_PRTY_MASK_H_2_MEM090_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM090_I_MEM_PRTY .
49108     #define NIG_REG_PRTY_MASK_H_2_MEM090_I_MEM_PRTY_SHIFT                                            30
49109     #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM045_I_MEM_PRTY .
49110     #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_BB_A0_SHIFT                                      8
49111     #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_BB_B0                                            (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM045_I_MEM_PRTY .
49112     #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_BB_B0_SHIFT                                      0
49113     #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_K2                                               (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM045_I_MEM_PRTY .
49114     #define NIG_REG_PRTY_MASK_H_2_MEM045_I_MEM_PRTY_K2_SHIFT                                         0
49115     #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM046_I_MEM_PRTY .
49116     #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_BB_A0_SHIFT                                      16
49117     #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM046_I_MEM_PRTY .
49118     #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_BB_B0_SHIFT                                      1
49119     #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM046_I_MEM_PRTY .
49120     #define NIG_REG_PRTY_MASK_H_2_MEM046_I_MEM_PRTY_K2_SHIFT                                         1
49121     #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM107_I_MEM_PRTY .
49122     #define NIG_REG_PRTY_MASK_H_2_MEM107_I_MEM_PRTY_SHIFT                                            6
49123     #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM047_I_MEM_PRTY .
49124     #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_BB_A0_SHIFT                                      17
49125     #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM047_I_MEM_PRTY .
49126     #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_BB_B0_SHIFT                                      7
49127     #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM047_I_MEM_PRTY .
49128     #define NIG_REG_PRTY_MASK_H_2_MEM047_I_MEM_PRTY_K2_SHIFT                                         7
49129     #define NIG_REG_PRTY_MASK_H_2_MEM048_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM048_I_MEM_PRTY .
49130     #define NIG_REG_PRTY_MASK_H_2_MEM048_I_MEM_PRTY_SHIFT                                            8
49131     #define NIG_REG_PRTY_MASK_H_2_MEM053_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM053_I_MEM_PRTY .
49132     #define NIG_REG_PRTY_MASK_H_2_MEM053_I_MEM_PRTY_SHIFT                                            9
49133     #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM027_I_MEM_PRTY .
49134     #define NIG_REG_PRTY_MASK_H_2_MEM027_I_MEM_PRTY_SHIFT                                            10
49135     #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM028_I_MEM_PRTY .
49136     #define NIG_REG_PRTY_MASK_H_2_MEM028_I_MEM_PRTY_SHIFT                                            11
49137     #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM103_I_MEM_PRTY .
49138     #define NIG_REG_PRTY_MASK_H_2_MEM103_I_MEM_PRTY_SHIFT                                            13
49139     #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB_A0                                            (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM104_I_MEM_PRTY .
49140     #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB_A0_SHIFT                                      6
49141     #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM104_I_MEM_PRTY .
49142     #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_BB_B0_SHIFT                                      14
49143     #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM104_I_MEM_PRTY .
49144     #define NIG_REG_PRTY_MASK_H_2_MEM104_I_MEM_PRTY_K2_SHIFT                                         14
49145     #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM108_I_MEM_PRTY .
49146     #define NIG_REG_PRTY_MASK_H_2_MEM108_I_MEM_PRTY_SHIFT                                            15
49147     #define NIG_REG_PRTY_MASK_H_2_MEM049_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM049_I_MEM_PRTY .
49148     #define NIG_REG_PRTY_MASK_H_2_MEM049_I_MEM_PRTY_SHIFT                                            16
49149     #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM050_I_MEM_PRTY .
49150     #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_BB_A0_SHIFT                                      9
49151     #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM050_I_MEM_PRTY .
49152     #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_BB_B0_SHIFT                                      17
49153     #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM050_I_MEM_PRTY .
49154     #define NIG_REG_PRTY_MASK_H_2_MEM050_I_MEM_PRTY_K2_SHIFT                                         17
49155     #define NIG_REG_PRTY_MASK_H_2_MEM054_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM054_I_MEM_PRTY .
49156     #define NIG_REG_PRTY_MASK_H_2_MEM054_I_MEM_PRTY_SHIFT                                            18
49157     #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM029_I_MEM_PRTY .
49158     #define NIG_REG_PRTY_MASK_H_2_MEM029_I_MEM_PRTY_SHIFT                                            19
49159     #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM030_I_MEM_PRTY .
49160     #define NIG_REG_PRTY_MASK_H_2_MEM030_I_MEM_PRTY_SHIFT                                            20
49161     #define NIG_REG_PRTY_MASK_H_2_MEM031_EXT_I_MEM_PRTY                                              (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM031_EXT_I_MEM_PRTY .
49162     #define NIG_REG_PRTY_MASK_H_2_MEM031_EXT_I_MEM_PRTY_SHIFT                                        22
49163     #define NIG_REG_PRTY_MASK_H_2_MEM034_EXT_I_MEM_PRTY                                              (0x1<<24) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM034_EXT_I_MEM_PRTY .
49164     #define NIG_REG_PRTY_MASK_H_2_MEM034_EXT_I_MEM_PRTY_SHIFT                                        24
49165     #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_BB_A0                                            (0x1<<27) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM095_I_MEM_PRTY .
49166     #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_BB_A0_SHIFT                                      27
49167     #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_BB_B0                                            (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM095_I_MEM_PRTY .
49168     #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_BB_B0_SHIFT                                      25
49169     #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_K2                                               (0x1<<25) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM095_I_MEM_PRTY .
49170     #define NIG_REG_PRTY_MASK_H_2_MEM095_I_MEM_PRTY_K2_SHIFT                                         25
49171     #define NIG_REG_PRTY_MASK_H_2_MEM042_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM042_I_MEM_PRTY .
49172     #define NIG_REG_PRTY_MASK_H_2_MEM042_I_MEM_PRTY_SHIFT                                            0
49173     #define NIG_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM043_I_MEM_PRTY .
49174     #define NIG_REG_PRTY_MASK_H_2_MEM043_I_MEM_PRTY_SHIFT                                            1
49175     #define NIG_REG_PRTY_MASK_H_2_MEM044_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM044_I_MEM_PRTY .
49176     #define NIG_REG_PRTY_MASK_H_2_MEM044_I_MEM_PRTY_SHIFT                                            7
49177     #define NIG_REG_PRTY_MASK_H_2_MEM105_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM105_I_MEM_PRTY .
49178     #define NIG_REG_PRTY_MASK_H_2_MEM105_I_MEM_PRTY_SHIFT                                            15
49179     #define NIG_REG_PRTY_MASK_H_2_MEM051_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM051_I_MEM_PRTY .
49180     #define NIG_REG_PRTY_MASK_H_2_MEM051_I_MEM_PRTY_SHIFT                                            18
49181     #define NIG_REG_PRTY_MASK_H_2_MEM092_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM092_I_MEM_PRTY .
49182     #define NIG_REG_PRTY_MASK_H_2_MEM092_I_MEM_PRTY_SHIFT                                            22
49183     #define NIG_REG_PRTY_MASK_H_2_MEM093_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM093_I_MEM_PRTY .
49184     #define NIG_REG_PRTY_MASK_H_2_MEM093_I_MEM_PRTY_SHIFT                                            23
49185     #define NIG_REG_PRTY_MASK_H_2_MEM094_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM094_I_MEM_PRTY .
49186     #define NIG_REG_PRTY_MASK_H_2_MEM094_I_MEM_PRTY_SHIFT                                            26
49187     #define NIG_REG_PRTY_MASK_H_2_MEM017_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_2.MEM017_I_MEM_PRTY .
49188     #define NIG_REG_PRTY_MASK_H_2_MEM017_I_MEM_PRTY_SHIFT                                            30
49189 #define NIG_REG_PRTY_MASK_H_3                                                                        0x500234UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49190     #define NIG_REG_PRTY_MASK_H_3_MEM011_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM011_I_MEM_PRTY .
49191     #define NIG_REG_PRTY_MASK_H_3_MEM011_I_MEM_PRTY_SHIFT                                            0
49192     #define NIG_REG_PRTY_MASK_H_3_MEM012_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM012_I_MEM_PRTY .
49193     #define NIG_REG_PRTY_MASK_H_3_MEM012_I_MEM_PRTY_SHIFT                                            1
49194     #define NIG_REG_PRTY_MASK_H_3_MEM013_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM013_I_MEM_PRTY .
49195     #define NIG_REG_PRTY_MASK_H_3_MEM013_I_MEM_PRTY_SHIFT                                            2
49196     #define NIG_REG_PRTY_MASK_H_3_MEM014_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM014_I_MEM_PRTY .
49197     #define NIG_REG_PRTY_MASK_H_3_MEM014_I_MEM_PRTY_SHIFT                                            3
49198     #define NIG_REG_PRTY_MASK_H_3_MEM001_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM001_I_MEM_PRTY .
49199     #define NIG_REG_PRTY_MASK_H_3_MEM001_I_MEM_PRTY_SHIFT                                            4
49200     #define NIG_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM002_I_MEM_PRTY .
49201     #define NIG_REG_PRTY_MASK_H_3_MEM002_I_MEM_PRTY_SHIFT                                            5
49202     #define NIG_REG_PRTY_MASK_H_3_MEM079_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM079_I_MEM_PRTY .
49203     #define NIG_REG_PRTY_MASK_H_3_MEM079_I_MEM_PRTY_SHIFT                                            6
49204     #define NIG_REG_PRTY_MASK_H_3_MEM080_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM080_I_MEM_PRTY .
49205     #define NIG_REG_PRTY_MASK_H_3_MEM080_I_MEM_PRTY_SHIFT                                            7
49206     #define NIG_REG_PRTY_MASK_H_3_MEM081_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM081_I_MEM_PRTY .
49207     #define NIG_REG_PRTY_MASK_H_3_MEM081_I_MEM_PRTY_SHIFT                                            8
49208     #define NIG_REG_PRTY_MASK_H_3_MEM082_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM082_I_MEM_PRTY .
49209     #define NIG_REG_PRTY_MASK_H_3_MEM082_I_MEM_PRTY_SHIFT                                            9
49210     #define NIG_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM003_I_MEM_PRTY .
49211     #define NIG_REG_PRTY_MASK_H_3_MEM003_I_MEM_PRTY_SHIFT                                            10
49212     #define NIG_REG_PRTY_MASK_H_3_MEM004_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM004_I_MEM_PRTY .
49213     #define NIG_REG_PRTY_MASK_H_3_MEM004_I_MEM_PRTY_SHIFT                                            11
49214     #define NIG_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM005_I_MEM_PRTY .
49215     #define NIG_REG_PRTY_MASK_H_3_MEM005_I_MEM_PRTY_SHIFT                                            12
49216     #define NIG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM006_I_MEM_PRTY .
49217     #define NIG_REG_PRTY_MASK_H_3_MEM006_I_MEM_PRTY_SHIFT                                            13
49218     #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM023_I_MEM_PRTY .
49219     #define NIG_REG_PRTY_MASK_H_3_MEM023_I_MEM_PRTY_SHIFT                                            0
49220     #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM024_I_MEM_PRTY .
49221     #define NIG_REG_PRTY_MASK_H_3_MEM024_I_MEM_PRTY_SHIFT                                            1
49222     #define NIG_REG_PRTY_MASK_H_3_MEM017_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM017_I_MEM_PRTY .
49223     #define NIG_REG_PRTY_MASK_H_3_MEM017_I_MEM_PRTY_SHIFT                                            2
49224     #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_BB_A0                                            (0x1<<0) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM018_I_MEM_PRTY .
49225     #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                      0
49226     #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM018_I_MEM_PRTY .
49227     #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                      3
49228     #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_K2                                               (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM018_I_MEM_PRTY .
49229     #define NIG_REG_PRTY_MASK_H_3_MEM018_I_MEM_PRTY_K2_SHIFT                                         3
49230     #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM093_I_MEM_PRTY .
49231     #define NIG_REG_PRTY_MASK_H_3_MEM093_I_MEM_PRTY_SHIFT                                            4
49232     #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM094_I_MEM_PRTY .
49233     #define NIG_REG_PRTY_MASK_H_3_MEM094_I_MEM_PRTY_SHIFT                                            5
49234     #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM019_I_MEM_PRTY .
49235     #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                      3
49236     #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM019_I_MEM_PRTY .
49237     #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      6
49238     #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM019_I_MEM_PRTY .
49239     #define NIG_REG_PRTY_MASK_H_3_MEM019_I_MEM_PRTY_K2_SHIFT                                         6
49240     #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM020_I_MEM_PRTY .
49241     #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      4
49242     #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM020_I_MEM_PRTY .
49243     #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      7
49244     #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM020_I_MEM_PRTY .
49245     #define NIG_REG_PRTY_MASK_H_3_MEM020_I_MEM_PRTY_K2_SHIFT                                         7
49246     #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_BB_A0                                            (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM040_I_MEM_PRTY .
49247     #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_BB_A0_SHIFT                                      10
49248     #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_BB_B0                                            (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM040_I_MEM_PRTY .
49249     #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_BB_B0_SHIFT                                      8
49250     #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_K2                                               (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM040_I_MEM_PRTY .
49251     #define NIG_REG_PRTY_MASK_H_3_MEM040_I_MEM_PRTY_K2_SHIFT                                         8
49252     #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY_BB_A0                                            (0x1<<7) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM036_I_MEM_PRTY .
49253     #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY_BB_A0_SHIFT                                      7
49254     #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM036_I_MEM_PRTY .
49255     #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY_BB_B0_SHIFT                                      9
49256     #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM036_I_MEM_PRTY .
49257     #define NIG_REG_PRTY_MASK_H_3_MEM036_I_MEM_PRTY_K2_SHIFT                                         9
49258     #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM039_I_MEM_PRTY .
49259     #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY_BB_A0_SHIFT                                      9
49260     #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM039_I_MEM_PRTY .
49261     #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY_BB_B0_SHIFT                                      10
49262     #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM039_I_MEM_PRTY .
49263     #define NIG_REG_PRTY_MASK_H_3_MEM039_I_MEM_PRTY_K2_SHIFT                                         10
49264     #define NIG_REG_PRTY_MASK_H_3_MEM041_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM041_I_MEM_PRTY .
49265     #define NIG_REG_PRTY_MASK_H_3_MEM041_I_MEM_PRTY_SHIFT                                            11
49266     #define NIG_REG_PRTY_MASK_H_3_MEM042_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM042_I_MEM_PRTY .
49267     #define NIG_REG_PRTY_MASK_H_3_MEM042_I_MEM_PRTY_SHIFT                                            12
49268     #define NIG_REG_PRTY_MASK_H_3_MEM043_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM043_I_MEM_PRTY .
49269     #define NIG_REG_PRTY_MASK_H_3_MEM043_I_MEM_PRTY_SHIFT                                            13
49270     #define NIG_REG_PRTY_MASK_H_3_MEM044_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM044_I_MEM_PRTY .
49271     #define NIG_REG_PRTY_MASK_H_3_MEM044_I_MEM_PRTY_SHIFT                                            14
49272     #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM038_I_MEM_PRTY .
49273     #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY_BB_A0_SHIFT                                      8
49274     #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM038_I_MEM_PRTY .
49275     #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY_BB_B0_SHIFT                                      15
49276     #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM038_I_MEM_PRTY .
49277     #define NIG_REG_PRTY_MASK_H_3_MEM038_I_MEM_PRTY_K2_SHIFT                                         15
49278     #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY_BB_A0                                            (0x1<<5) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM037_I_MEM_PRTY .
49279     #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY_BB_A0_SHIFT                                      5
49280     #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM037_I_MEM_PRTY .
49281     #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY_BB_B0_SHIFT                                      16
49282     #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM037_I_MEM_PRTY .
49283     #define NIG_REG_PRTY_MASK_H_3_MEM037_I_MEM_PRTY_K2_SHIFT                                         16
49284     #define NIG_REG_PRTY_MASK_H_3_MEM090_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM090_I_MEM_PRTY .
49285     #define NIG_REG_PRTY_MASK_H_3_MEM090_I_MEM_PRTY_SHIFT                                            1
49286     #define NIG_REG_PRTY_MASK_H_3_MEM091_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM091_I_MEM_PRTY .
49287     #define NIG_REG_PRTY_MASK_H_3_MEM091_I_MEM_PRTY_SHIFT                                            2
49288     #define NIG_REG_PRTY_MASK_H_3_MEM033_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM033_I_MEM_PRTY .
49289     #define NIG_REG_PRTY_MASK_H_3_MEM033_I_MEM_PRTY_SHIFT                                            6
49290     #define NIG_REG_PRTY_MASK_H_3_MEM035_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM035_I_MEM_PRTY .
49291     #define NIG_REG_PRTY_MASK_H_3_MEM035_I_MEM_PRTY_SHIFT                                            12
49292     #define NIG_REG_PRTY_MASK_H_3_MEM034_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NIG_REG_PRTY_STS_H_3.MEM034_I_MEM_PRTY .
49293     #define NIG_REG_PRTY_MASK_H_3_MEM034_I_MEM_PRTY_SHIFT                                            13
49294 #define NIG_REG_MEM_ECC_EVENTS                                                                       0x500240UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
49295 #define NIG_REG_MEM107_I_MEM_DFT_K2                                                                  0x500254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.i_nig_dbg_syncfifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
49296 #define NIG_REG_MEM103_I_MEM_DFT_K2                                                                  0x500258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_MACINTF_MEM[0].i_nig_tx_mac_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49297 #define NIG_REG_MEM104_I_MEM_DFT_K2                                                                  0x50025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_MACINTF_MEM[1].i_nig_tx_mac_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49298 #define NIG_REG_MEM105_I_MEM_DFT_K2                                                                  0x500260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_MACINTF_MEM[2].i_nig_tx_mac_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49299 #define NIG_REG_MEM106_I_MEM_DFT_K2                                                                  0x500264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_MACINTF_MEM[3].i_nig_tx_mac_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49300 #define NIG_REG_MEM072_I_MEM_DFT_K2                                                                  0x500268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.STORM_MEM_IF.STORM_MEM[0].i_nig_storm_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49301 #define NIG_REG_MEM071_I_MEM_DFT_K2                                                                  0x50026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.STORM_MEM_IF.STORM_MEM[0].i_nig_storm_dscr_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49302 #define NIG_REG_MEM074_I_MEM_DFT_K2                                                                  0x500270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.STORM_MEM_IF.STORM_MEM[1].i_nig_storm_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49303 #define NIG_REG_MEM073_I_MEM_DFT_K2                                                                  0x500274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.STORM_MEM_IF.STORM_MEM[1].i_nig_storm_dscr_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49304 #define NIG_REG_MEM076_I_MEM_DFT_K2                                                                  0x500278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.STORM_MEM_IF.STORM_MEM[2].i_nig_storm_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49305 #define NIG_REG_MEM075_I_MEM_DFT_K2                                                                  0x50027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.STORM_MEM_IF.STORM_MEM[2].i_nig_storm_dscr_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49306 #define NIG_REG_MEM078_I_MEM_DFT_K2                                                                  0x500280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.STORM_MEM_IF.STORM_MEM[3].i_nig_storm_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49307 #define NIG_REG_MEM077_I_MEM_DFT_K2                                                                  0x500284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.STORM_MEM_IF.STORM_MEM[3].i_nig_storm_dscr_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49308 #define NIG_REG_MEM091_I_MEM_DFT_K2                                                                  0x500288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_D_MEM[0].i_nig_tx_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49309 #define NIG_REG_MEM092_I_MEM_DFT_K2                                                                  0x50028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_D_MEM[1].i_nig_tx_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49310 #define NIG_REG_MEM093_I_MEM_DFT_K2                                                                  0x500290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_D_MEM[2].i_nig_tx_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49311 #define NIG_REG_MEM094_I_MEM_DFT_K2                                                                  0x500294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_D_MEM[3].i_nig_tx_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49312 #define NIG_REG_MEM027_I_MEM_DFT_K2                                                                  0x500298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.RX_LLH_D_MEM[0].i_nig_rx_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49313 #define NIG_REG_MEM028_I_MEM_DFT_K2                                                                  0x50029cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.RX_LLH_D_MEM[1].i_nig_rx_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49314 #define NIG_REG_MEM029_I_MEM_DFT_K2                                                                  0x5002a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.RX_LLH_D_MEM[2].i_nig_rx_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49315 #define NIG_REG_MEM030_I_MEM_DFT_K2                                                                  0x5002a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.RX_LLH_D_MEM[3].i_nig_rx_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49316 #define NIG_REG_MEM015_I_MEM_DFT_K2                                                                  0x5002a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_D_MEM[0].i_nig_lb_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49317 #define NIG_REG_MEM016_I_MEM_DFT_K2                                                                  0x5002acUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_D_MEM[1].i_nig_lb_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49318 #define NIG_REG_MEM017_I_MEM_DFT_K2                                                                  0x5002b0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_D_MEM[2].i_nig_lb_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49319 #define NIG_REG_MEM018_I_MEM_DFT_K2                                                                  0x5002b4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_D_MEM[3].i_nig_lb_llh_dfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49320 #define NIG_REG_MEM095_I_MEM_DFT_K2                                                                  0x5002b8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_H_MEM[0].i_nig_tx_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49321 #define NIG_REG_MEM096_I_MEM_DFT_K2                                                                  0x5002bcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_H_MEM[1].i_nig_tx_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49322 #define NIG_REG_MEM097_I_MEM_DFT_K2                                                                  0x5002c0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_H_MEM[2].i_nig_tx_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49323 #define NIG_REG_MEM098_I_MEM_DFT_K2                                                                  0x5002c4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_H_MEM[3].i_nig_tx_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49324 #define NIG_REG_MEM031_I_MEM_DFT_K2                                                                  0x5002c8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.RX_LLH_H_MEM[0].i_nig_rx_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49325 #define NIG_REG_MEM032_I_MEM_DFT_K2                                                                  0x5002ccUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.RX_LLH_H_MEM[1].i_nig_rx_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49326 #define NIG_REG_MEM033_I_MEM_DFT_K2                                                                  0x5002d0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.RX_LLH_H_MEM[2].i_nig_rx_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49327 #define NIG_REG_MEM034_I_MEM_DFT_K2                                                                  0x5002d4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.RX_LLH_H_MEM[3].i_nig_rx_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49328 #define NIG_REG_MEM019_I_MEM_DFT_K2                                                                  0x5002d8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_H_MEM[0].i_nig_lb_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49329 #define NIG_REG_MEM020_I_MEM_DFT_K2                                                                  0x5002dcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_H_MEM[1].i_nig_lb_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49330 #define NIG_REG_MEM021_I_MEM_DFT_K2                                                                  0x5002e0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_H_MEM[2].i_nig_lb_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49331 #define NIG_REG_MEM022_I_MEM_DFT_K2                                                                  0x5002e4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_H_MEM[3].i_nig_lb_llh_hfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49332 #define NIG_REG_MEM099_I_MEM_DFT_K2                                                                  0x5002e8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_R_MEM[0].i_nig_tx_llh_rfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49333 #define NIG_REG_MEM100_I_MEM_DFT_K2                                                                  0x5002ecUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_R_MEM[1].i_nig_tx_llh_rfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49334 #define NIG_REG_MEM101_I_MEM_DFT_K2                                                                  0x5002f0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_R_MEM[2].i_nig_tx_llh_rfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49335 #define NIG_REG_MEM102_I_MEM_DFT_K2                                                                  0x5002f4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_LLH_R_MEM[3].i_nig_tx_llh_rfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49336 #define NIG_REG_MEM023_I_MEM_DFT_K2                                                                  0x5002f8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_R_MEM[0].i_nig_lb_llh_rfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49337 #define NIG_REG_MEM024_I_MEM_DFT_K2                                                                  0x5002fcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_R_MEM[1].i_nig_lb_llh_rfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49338 #define NIG_REG_MEM025_I_MEM_DFT_K2                                                                  0x500300UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_R_MEM[2].i_nig_lb_llh_rfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49339 #define NIG_REG_MEM026_I_MEM_DFT_K2                                                                  0x500304UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_LLH_R_MEM[3].i_nig_lb_llh_rfifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49340 #define NIG_REG_MEM083_I_MEM_DFT_K2                                                                  0x500308UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_BTB_MEM[0].i_nig_tx_btb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49341 #define NIG_REG_MEM084_I_MEM_DFT_K2                                                                  0x50030cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_BTB_MEM[1].i_nig_tx_btb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49342 #define NIG_REG_MEM085_I_MEM_DFT_K2                                                                  0x500310UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_BTB_MEM[2].i_nig_tx_btb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49343 #define NIG_REG_MEM086_I_MEM_DFT_K2                                                                  0x500314UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_BTB_MEM[3].i_nig_tx_btb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49344 #define NIG_REG_MEM007_I_MEM_DFT_K2                                                                  0x500318UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_BTB_MEM[0].i_nig_lb_btb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49345 #define NIG_REG_MEM008_I_MEM_DFT_K2                                                                  0x50031cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_BTB_MEM[1].i_nig_lb_btb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49346 #define NIG_REG_MEM009_I_MEM_DFT_K2                                                                  0x500320UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_BTB_MEM[2].i_nig_lb_btb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49347 #define NIG_REG_MEM010_I_MEM_DFT_K2                                                                  0x500324UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_BTB_MEM[3].i_nig_lb_btb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49348 #define NIG_REG_MEM001_I_MEM_DFT_K2                                                                  0x500328UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.DBG_DORQ_IF.i_nig_dbg_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49349 #define NIG_REG_MEM002_I_MEM_DFT_K2                                                                  0x50032cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.DBG_DORQ_IF.i_nig_dorq_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49350 #define NIG_REG_MEM079_I_MEM_DFT_K2                                                                  0x500330UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_BMB_MEM[0].i_nig_tx_bmb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49351 #define NIG_REG_MEM080_I_MEM_DFT_K2                                                                  0x500334UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_BMB_MEM[1].i_nig_tx_bmb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49352 #define NIG_REG_MEM081_I_MEM_DFT_K2                                                                  0x500338UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_BMB_MEM[2].i_nig_tx_bmb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49353 #define NIG_REG_MEM082_I_MEM_DFT_K2                                                                  0x50033cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.TX_BMB_MEM[3].i_nig_tx_bmb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49354 #define NIG_REG_MEM003_I_MEM_DFT_K2                                                                  0x500340UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_BMB_MEM[0].i_nig_lb_bmb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49355 #define NIG_REG_MEM004_I_MEM_DFT_K2                                                                  0x500344UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_BMB_MEM[1].i_nig_lb_bmb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49356 #define NIG_REG_MEM005_I_MEM_DFT_K2                                                                  0x500348UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_BMB_MEM[2].i_nig_lb_bmb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49357 #define NIG_REG_MEM006_I_MEM_DFT_K2                                                                  0x50034cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nig.LB_BMB_MEM[3].i_nig_lb_bmb_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
49358 #define NIG_REG_CLOSE_GATE_DISABLE                                                                   0x500800UL //Access:RW   DataWidth:0x1   Close-gate function disable bit:  0 - egress drain mode is enabled when close-gate input from MISC to NIG is active; 1 - close-gate input is ignored.  (The egress drain mode is for dropping all packets in the TX pipe without forwarding the packets to the TX MAC.).  Chips: BB_A0 BB_B0 K2
49359 #define NIG_REG_TAG_ETHERTYPE_0                                                                      0x500804UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 0.  Chips: BB_A0 BB_B0 K2
49360 #define NIG_REG_TAG_ETHERTYPE_1                                                                      0x500808UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 1.  The reset value is 9x8100 for inner VLAN.  Chips: BB_A0 BB_B0 K2
49361 #define NIG_REG_TAG_ETHERTYPE_2                                                                      0x50080cUL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 2.  Chips: BB_A0 BB_B0 K2
49362 #define NIG_REG_TAG_ETHERTYPE_3                                                                      0x500810UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 3.  Chips: BB_A0 BB_B0 K2
49363 #define NIG_REG_TAG_ETHERTYPE_4                                                                      0x500814UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 4.  Chips: BB_A0 BB_B0 K2
49364 #define NIG_REG_TAG_ETHERTYPE_5                                                                      0x500818UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 5.  Chips: BB_A0 BB_B0 K2
49365 #define NIG_REG_TAG_LEN_0                                                                            0x50081cUL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: BB_A0 BB_B0 K2
49366 #define NIG_REG_TAG_LEN_1                                                                            0x500820UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: BB_A0 BB_B0 K2
49367 #define NIG_REG_TAG_LEN_2                                                                            0x500824UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: BB_A0 BB_B0 K2
49368 #define NIG_REG_TAG_LEN_3                                                                            0x500828UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: BB_A0 BB_B0 K2
49369 #define NIG_REG_TAG_LEN_4                                                                            0x50082cUL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: BB_A0 BB_B0 K2
49370 #define NIG_REG_TAG_LEN_5                                                                            0x500830UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: BB_A0 BB_B0 K2
49371 #define NIG_REG_MNG_TO_MCP                                                                           0x500834UL //Access:RW   DataWidth:0x1   Direct all management traffic to BMB toward MCP.  Chips: BB_A0 BB_B0 K2
49372 #define NIG_REG_FWD_PKT_TO_STORM                                                                     0x500838UL //Access:RW   DataWidth:0x1   Select bit for choosing between XSTORM and YSTORM for forwarding RX packets.  0 is for XSTORM; 1 is for YSTORM. This configuration should be static during run-time.  Chips: BB_A0 BB_B0 K2
49373 #define NIG_REG_STORM_CREDIT                                                                         0x50083cUL //Access:RW   DataWidth:0x4   Credit for the interface with XSEM and YSEM. Read this register to get the current credit count on the interface. This configuration should be static during run-time.  Chips: BB_A0 BB_B0 K2
49374 #define NIG_REG_CM_HDR                                                                               0x500840UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49375     #define NIG_REG_CM_HDR_EVENT_ID                                                                  (0xff<<0) // Event ID to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
49376     #define NIG_REG_CM_HDR_EVENT_ID_SHIFT                                                            0
49377     #define NIG_REG_CM_HDR_T_BIT                                                                     (0x1<<8) // T-bit to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
49378     #define NIG_REG_CM_HDR_T_BIT_SHIFT                                                               8
49379     #define NIG_REG_CM_HDR_DSTSTORMFLG                                                               (0x1<<9) // DstStormFlg to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
49380     #define NIG_REG_CM_HDR_DSTSTORMFLG_SHIFT                                                         9
49381     #define NIG_REG_CM_HDR_CONDOMAIN                                                                 (0x1<<10) // ConnectionDomainExist to be used in CM header for packets forwarded to the STORM through the X/YSEM interface.
49382     #define NIG_REG_CM_HDR_CONDOMAIN_SHIFT                                                           10
49383 #define NIG_REG_TX_LB_DROP_FWDERR                                                                    0x500844UL //Access:RW   DataWidth:0x1   Global configuration for selecting whether to drop the per-PF drop and per-VPORT drop packets or forward the packet to the destination with the error bit set.  Set this bit to 1 to forward the packet to the destination with error (as if the error indication in the BTB SOP descriptor as set).  This bit affects both the main TX traffic and LB traffic.  Chips: BB_A0 BB_B0 K2
49384 #define NIG_REG_TX_LB_VPORT_DROP_0                                                                   0x500848UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49385 #define NIG_REG_TX_LB_VPORT_DROP_1                                                                   0x50084cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49386 #define NIG_REG_TX_LB_VPORT_DROP_2                                                                   0x500850UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49387 #define NIG_REG_TX_LB_VPORT_DROP_3                                                                   0x500854UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49388 #define NIG_REG_TX_LB_VPORT_DROP_4                                                                   0x500858UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49389 #define NIG_REG_TX_LB_VPORT_DROP_5                                                                   0x50085cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49390 #define NIG_REG_TX_LB_VPORT_DROP_6                                                                   0x500860UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49391 #define NIG_REG_TX_LB_VPORT_DROP_7                                                                   0x500864UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49392 #define NIG_REG_TX_LB_VPORT_DROP_8                                                                   0x500868UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49393 #define NIG_REG_TX_LB_VPORT_DROP_9                                                                   0x50086cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49394 #define NIG_REG_TX_LB_VPORT_DROP_10                                                                  0x500870UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49395 #define NIG_REG_TX_LB_VPORT_DROP_11                                                                  0x500874UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49396 #define NIG_REG_TX_LB_VPORT_DROP_12                                                                  0x500878UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49397 #define NIG_REG_TX_LB_VPORT_DROP_13                                                                  0x50087cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49398 #define NIG_REG_TX_LB_VPORT_DROP_14                                                                  0x500880UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49399 #define NIG_REG_TX_LB_VPORT_DROP_15                                                                  0x500884UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49400 #define NIG_REG_TX_LB_VPORT_DROP_16                                                                  0x500888UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49401 #define NIG_REG_TX_LB_VPORT_DROP_17                                                                  0x50088cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49402 #define NIG_REG_TX_LB_VPORT_DROP_18                                                                  0x500890UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49403 #define NIG_REG_TX_LB_VPORT_DROP_19                                                                  0x500894UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49404 #define NIG_REG_TX_LB_VPORT_DROP_20                                                                  0x500898UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49405 #define NIG_REG_TX_LB_VPORT_DROP_21                                                                  0x50089cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49406 #define NIG_REG_TX_LB_VPORT_DROP_22                                                                  0x5008a0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49407 #define NIG_REG_TX_LB_VPORT_DROP_23                                                                  0x5008a4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49408 #define NIG_REG_TX_LB_VPORT_DROP_24                                                                  0x5008a8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49409 #define NIG_REG_TX_LB_VPORT_DROP_25                                                                  0x5008acUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49410 #define NIG_REG_TX_LB_VPORT_DROP_26                                                                  0x5008b0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49411 #define NIG_REG_TX_LB_VPORT_DROP_27                                                                  0x5008b4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49412 #define NIG_REG_TX_LB_VPORT_DROP_28                                                                  0x5008b8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49413 #define NIG_REG_TX_LB_VPORT_DROP_29                                                                  0x5008bcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49414 #define NIG_REG_TX_LB_VPORT_DROP_30                                                                  0x5008c0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49415 #define NIG_REG_TX_LB_VPORT_DROP_31                                                                  0x5008c4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49416 #define NIG_REG_TX_LB_VPORT_DROP_32                                                                  0x5008c8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49417 #define NIG_REG_TX_LB_VPORT_DROP_33                                                                  0x5008ccUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49418 #define NIG_REG_TX_LB_VPORT_DROP_34                                                                  0x5008d0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49419 #define NIG_REG_TX_LB_VPORT_DROP_35                                                                  0x5008d4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49420 #define NIG_REG_TX_LB_VPORT_DROP_36                                                                  0x5008d8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49421 #define NIG_REG_TX_LB_VPORT_DROP_37                                                                  0x5008dcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49422 #define NIG_REG_TX_LB_VPORT_DROP_38                                                                  0x5008e0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49423 #define NIG_REG_TX_LB_VPORT_DROP_39                                                                  0x5008e4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49424 #define NIG_REG_TX_LB_VPORT_DROP_40                                                                  0x5008e8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49425 #define NIG_REG_TX_LB_VPORT_DROP_41                                                                  0x5008ecUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49426 #define NIG_REG_TX_LB_VPORT_DROP_42                                                                  0x5008f0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49427 #define NIG_REG_TX_LB_VPORT_DROP_43                                                                  0x5008f4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49428 #define NIG_REG_TX_LB_VPORT_DROP_44                                                                  0x5008f8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49429 #define NIG_REG_TX_LB_VPORT_DROP_45                                                                  0x5008fcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49430 #define NIG_REG_TX_LB_VPORT_DROP_46                                                                  0x500900UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49431 #define NIG_REG_TX_LB_VPORT_DROP_47                                                                  0x500904UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49432 #define NIG_REG_TX_LB_VPORT_DROP_48                                                                  0x500908UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49433 #define NIG_REG_TX_LB_VPORT_DROP_49                                                                  0x50090cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49434 #define NIG_REG_TX_LB_VPORT_DROP_50                                                                  0x500910UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49435 #define NIG_REG_TX_LB_VPORT_DROP_51                                                                  0x500914UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49436 #define NIG_REG_TX_LB_VPORT_DROP_52                                                                  0x500918UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49437 #define NIG_REG_TX_LB_VPORT_DROP_53                                                                  0x50091cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49438 #define NIG_REG_TX_LB_VPORT_DROP_54                                                                  0x500920UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49439 #define NIG_REG_TX_LB_VPORT_DROP_55                                                                  0x500924UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49440 #define NIG_REG_TX_LB_VPORT_DROP_56                                                                  0x500928UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49441 #define NIG_REG_TX_LB_VPORT_DROP_57                                                                  0x50092cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49442 #define NIG_REG_TX_LB_VPORT_DROP_58                                                                  0x500930UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49443 #define NIG_REG_TX_LB_VPORT_DROP_59                                                                  0x500934UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49444 #define NIG_REG_TX_LB_VPORT_DROP_60                                                                  0x500938UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49445 #define NIG_REG_TX_LB_VPORT_DROP_61                                                                  0x50093cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49446 #define NIG_REG_TX_LB_VPORT_DROP_62                                                                  0x500940UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49447 #define NIG_REG_TX_LB_VPORT_DROP_63                                                                  0x500944UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49448 #define NIG_REG_TX_LB_VPORT_DROP_64                                                                  0x500948UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49449 #define NIG_REG_TX_LB_VPORT_DROP_65                                                                  0x50094cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49450 #define NIG_REG_TX_LB_VPORT_DROP_66                                                                  0x500950UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49451 #define NIG_REG_TX_LB_VPORT_DROP_67                                                                  0x500954UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49452 #define NIG_REG_TX_LB_VPORT_DROP_68                                                                  0x500958UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49453 #define NIG_REG_TX_LB_VPORT_DROP_69                                                                  0x50095cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49454 #define NIG_REG_TX_LB_VPORT_DROP_70                                                                  0x500960UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49455 #define NIG_REG_TX_LB_VPORT_DROP_71                                                                  0x500964UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49456 #define NIG_REG_TX_LB_VPORT_DROP_72                                                                  0x500968UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49457 #define NIG_REG_TX_LB_VPORT_DROP_73                                                                  0x50096cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49458 #define NIG_REG_TX_LB_VPORT_DROP_74                                                                  0x500970UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49459 #define NIG_REG_TX_LB_VPORT_DROP_75                                                                  0x500974UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49460 #define NIG_REG_TX_LB_VPORT_DROP_76                                                                  0x500978UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49461 #define NIG_REG_TX_LB_VPORT_DROP_77                                                                  0x50097cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49462 #define NIG_REG_TX_LB_VPORT_DROP_78                                                                  0x500980UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49463 #define NIG_REG_TX_LB_VPORT_DROP_79                                                                  0x500984UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49464 #define NIG_REG_TX_LB_VPORT_DROP_80                                                                  0x500988UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49465 #define NIG_REG_TX_LB_VPORT_DROP_81                                                                  0x50098cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49466 #define NIG_REG_TX_LB_VPORT_DROP_82                                                                  0x500990UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49467 #define NIG_REG_TX_LB_VPORT_DROP_83                                                                  0x500994UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49468 #define NIG_REG_TX_LB_VPORT_DROP_84                                                                  0x500998UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49469 #define NIG_REG_TX_LB_VPORT_DROP_85                                                                  0x50099cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49470 #define NIG_REG_TX_LB_VPORT_DROP_86                                                                  0x5009a0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49471 #define NIG_REG_TX_LB_VPORT_DROP_87                                                                  0x5009a4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49472 #define NIG_REG_TX_LB_VPORT_DROP_88                                                                  0x5009a8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49473 #define NIG_REG_TX_LB_VPORT_DROP_89                                                                  0x5009acUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49474 #define NIG_REG_TX_LB_VPORT_DROP_90                                                                  0x5009b0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49475 #define NIG_REG_TX_LB_VPORT_DROP_91                                                                  0x5009b4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49476 #define NIG_REG_TX_LB_VPORT_DROP_92                                                                  0x5009b8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49477 #define NIG_REG_TX_LB_VPORT_DROP_93                                                                  0x5009bcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49478 #define NIG_REG_TX_LB_VPORT_DROP_94                                                                  0x5009c0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49479 #define NIG_REG_TX_LB_VPORT_DROP_95                                                                  0x5009c4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49480 #define NIG_REG_TX_LB_VPORT_DROP_96                                                                  0x5009c8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49481 #define NIG_REG_TX_LB_VPORT_DROP_97                                                                  0x5009ccUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49482 #define NIG_REG_TX_LB_VPORT_DROP_98                                                                  0x5009d0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49483 #define NIG_REG_TX_LB_VPORT_DROP_99                                                                  0x5009d4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49484 #define NIG_REG_TX_LB_VPORT_DROP_100                                                                 0x5009d8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49485 #define NIG_REG_TX_LB_VPORT_DROP_101                                                                 0x5009dcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49486 #define NIG_REG_TX_LB_VPORT_DROP_102                                                                 0x5009e0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49487 #define NIG_REG_TX_LB_VPORT_DROP_103                                                                 0x5009e4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49488 #define NIG_REG_TX_LB_VPORT_DROP_104                                                                 0x5009e8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49489 #define NIG_REG_TX_LB_VPORT_DROP_105                                                                 0x5009ecUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49490 #define NIG_REG_TX_LB_VPORT_DROP_106                                                                 0x5009f0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49491 #define NIG_REG_TX_LB_VPORT_DROP_107                                                                 0x5009f4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49492 #define NIG_REG_TX_LB_VPORT_DROP_108                                                                 0x5009f8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49493 #define NIG_REG_TX_LB_VPORT_DROP_109                                                                 0x5009fcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49494 #define NIG_REG_TX_LB_VPORT_DROP_110                                                                 0x500a00UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49495 #define NIG_REG_TX_LB_VPORT_DROP_111                                                                 0x500a04UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49496 #define NIG_REG_TX_LB_VPORT_DROP_112                                                                 0x500a08UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49497 #define NIG_REG_TX_LB_VPORT_DROP_113                                                                 0x500a0cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49498 #define NIG_REG_TX_LB_VPORT_DROP_114                                                                 0x500a10UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49499 #define NIG_REG_TX_LB_VPORT_DROP_115                                                                 0x500a14UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49500 #define NIG_REG_TX_LB_VPORT_DROP_116                                                                 0x500a18UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49501 #define NIG_REG_TX_LB_VPORT_DROP_117                                                                 0x500a1cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49502 #define NIG_REG_TX_LB_VPORT_DROP_118                                                                 0x500a20UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49503 #define NIG_REG_TX_LB_VPORT_DROP_119                                                                 0x500a24UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49504 #define NIG_REG_TX_LB_VPORT_DROP_120                                                                 0x500a28UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49505 #define NIG_REG_TX_LB_VPORT_DROP_121                                                                 0x500a2cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49506 #define NIG_REG_TX_LB_VPORT_DROP_122                                                                 0x500a30UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49507 #define NIG_REG_TX_LB_VPORT_DROP_123                                                                 0x500a34UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49508 #define NIG_REG_TX_LB_VPORT_DROP_124                                                                 0x500a38UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49509 #define NIG_REG_TX_LB_VPORT_DROP_125                                                                 0x500a3cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49510 #define NIG_REG_TX_LB_VPORT_DROP_126                                                                 0x500a40UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49511 #define NIG_REG_TX_LB_VPORT_DROP_127                                                                 0x500a44UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49512 #define NIG_REG_TX_LB_VPORT_DROP_128                                                                 0x500a48UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49513 #define NIG_REG_TX_LB_VPORT_DROP_129                                                                 0x500a4cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49514 #define NIG_REG_TX_LB_VPORT_DROP_130                                                                 0x500a50UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49515 #define NIG_REG_TX_LB_VPORT_DROP_131                                                                 0x500a54UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49516 #define NIG_REG_TX_LB_VPORT_DROP_132                                                                 0x500a58UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49517 #define NIG_REG_TX_LB_VPORT_DROP_133                                                                 0x500a5cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49518 #define NIG_REG_TX_LB_VPORT_DROP_134                                                                 0x500a60UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49519 #define NIG_REG_TX_LB_VPORT_DROP_135                                                                 0x500a64UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49520 #define NIG_REG_TX_LB_VPORT_DROP_136                                                                 0x500a68UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49521 #define NIG_REG_TX_LB_VPORT_DROP_137                                                                 0x500a6cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49522 #define NIG_REG_TX_LB_VPORT_DROP_138                                                                 0x500a70UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49523 #define NIG_REG_TX_LB_VPORT_DROP_139                                                                 0x500a74UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49524 #define NIG_REG_TX_LB_VPORT_DROP_140                                                                 0x500a78UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49525 #define NIG_REG_TX_LB_VPORT_DROP_141                                                                 0x500a7cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49526 #define NIG_REG_TX_LB_VPORT_DROP_142                                                                 0x500a80UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49527 #define NIG_REG_TX_LB_VPORT_DROP_143                                                                 0x500a84UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49528 #define NIG_REG_TX_LB_VPORT_DROP_144                                                                 0x500a88UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49529 #define NIG_REG_TX_LB_VPORT_DROP_145                                                                 0x500a8cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49530 #define NIG_REG_TX_LB_VPORT_DROP_146                                                                 0x500a90UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49531 #define NIG_REG_TX_LB_VPORT_DROP_147                                                                 0x500a94UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49532 #define NIG_REG_TX_LB_VPORT_DROP_148                                                                 0x500a98UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49533 #define NIG_REG_TX_LB_VPORT_DROP_149                                                                 0x500a9cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49534 #define NIG_REG_TX_LB_VPORT_DROP_150                                                                 0x500aa0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49535 #define NIG_REG_TX_LB_VPORT_DROP_151                                                                 0x500aa4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49536 #define NIG_REG_TX_LB_VPORT_DROP_152                                                                 0x500aa8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49537 #define NIG_REG_TX_LB_VPORT_DROP_153                                                                 0x500aacUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49538 #define NIG_REG_TX_LB_VPORT_DROP_154                                                                 0x500ab0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49539 #define NIG_REG_TX_LB_VPORT_DROP_155                                                                 0x500ab4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49540 #define NIG_REG_TX_LB_VPORT_DROP_156                                                                 0x500ab8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49541 #define NIG_REG_TX_LB_VPORT_DROP_157                                                                 0x500abcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49542 #define NIG_REG_TX_LB_VPORT_DROP_158                                                                 0x500ac0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49543 #define NIG_REG_TX_LB_VPORT_DROP_159                                                                 0x500ac4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49544 #define NIG_REG_TX_LB_VPORT_DROP_160                                                                 0x500ac8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49545 #define NIG_REG_TX_LB_VPORT_DROP_161                                                                 0x500accUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49546 #define NIG_REG_TX_LB_VPORT_DROP_162                                                                 0x500ad0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49547 #define NIG_REG_TX_LB_VPORT_DROP_163                                                                 0x500ad4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49548 #define NIG_REG_TX_LB_VPORT_DROP_164                                                                 0x500ad8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49549 #define NIG_REG_TX_LB_VPORT_DROP_165                                                                 0x500adcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49550 #define NIG_REG_TX_LB_VPORT_DROP_166                                                                 0x500ae0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49551 #define NIG_REG_TX_LB_VPORT_DROP_167                                                                 0x500ae4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49552 #define NIG_REG_TX_LB_VPORT_DROP_168                                                                 0x500ae8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49553 #define NIG_REG_TX_LB_VPORT_DROP_169                                                                 0x500aecUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49554 #define NIG_REG_TX_LB_VPORT_DROP_170                                                                 0x500af0UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49555 #define NIG_REG_TX_LB_VPORT_DROP_171                                                                 0x500af4UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49556 #define NIG_REG_TX_LB_VPORT_DROP_172                                                                 0x500af8UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49557 #define NIG_REG_TX_LB_VPORT_DROP_173                                                                 0x500afcUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49558 #define NIG_REG_TX_LB_VPORT_DROP_174                                                                 0x500b00UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49559 #define NIG_REG_TX_LB_VPORT_DROP_175                                                                 0x500b04UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49560 #define NIG_REG_TX_LB_VPORT_DROP_176                                                                 0x500b08UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49561 #define NIG_REG_TX_LB_VPORT_DROP_177                                                                 0x500b0cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49562 #define NIG_REG_TX_LB_VPORT_DROP_178                                                                 0x500b10UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49563 #define NIG_REG_TX_LB_VPORT_DROP_179                                                                 0x500b14UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49564 #define NIG_REG_TX_LB_VPORT_DROP_180                                                                 0x500b18UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49565 #define NIG_REG_TX_LB_VPORT_DROP_181                                                                 0x500b1cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49566 #define NIG_REG_TX_LB_VPORT_DROP_182                                                                 0x500b20UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49567 #define NIG_REG_TX_LB_VPORT_DROP_183                                                                 0x500b24UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49568 #define NIG_REG_TX_LB_VPORT_DROP_184                                                                 0x500b28UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49569 #define NIG_REG_TX_LB_VPORT_DROP_185                                                                 0x500b2cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49570 #define NIG_REG_TX_LB_VPORT_DROP_186                                                                 0x500b30UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49571 #define NIG_REG_TX_LB_VPORT_DROP_187                                                                 0x500b34UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49572 #define NIG_REG_TX_LB_VPORT_DROP_188                                                                 0x500b38UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49573 #define NIG_REG_TX_LB_VPORT_DROP_189                                                                 0x500b3cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49574 #define NIG_REG_TX_LB_VPORT_DROP_190                                                                 0x500b40UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49575 #define NIG_REG_TX_LB_VPORT_DROP_191                                                                 0x500b44UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49576 #define NIG_REG_TX_LB_VPORT_DROP_192                                                                 0x500b48UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49577 #define NIG_REG_TX_LB_VPORT_DROP_193                                                                 0x500b4cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49578 #define NIG_REG_TX_LB_VPORT_DROP_194                                                                 0x500b50UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49579 #define NIG_REG_TX_LB_VPORT_DROP_195                                                                 0x500b54UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49580 #define NIG_REG_TX_LB_VPORT_DROP_196                                                                 0x500b58UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49581 #define NIG_REG_TX_LB_VPORT_DROP_197                                                                 0x500b5cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49582 #define NIG_REG_TX_LB_VPORT_DROP_198                                                                 0x500b60UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49583 #define NIG_REG_TX_LB_VPORT_DROP_199                                                                 0x500b64UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49584 #define NIG_REG_TX_LB_VPORT_DROP_200                                                                 0x500b68UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49585 #define NIG_REG_TX_LB_VPORT_DROP_201                                                                 0x500b6cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49586 #define NIG_REG_TX_LB_VPORT_DROP_202                                                                 0x500b70UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49587 #define NIG_REG_TX_LB_VPORT_DROP_203                                                                 0x500b74UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49588 #define NIG_REG_TX_LB_VPORT_DROP_204                                                                 0x500b78UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49589 #define NIG_REG_TX_LB_VPORT_DROP_205                                                                 0x500b7cUL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49590 #define NIG_REG_TX_LB_VPORT_DROP_206                                                                 0x500b80UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49591 #define NIG_REG_TX_LB_VPORT_DROP_207                                                                 0x500b84UL //Access:RW   DataWidth:0x1   Per-VPORT drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: K2
49592 #define NIG_REG_TX_LB_PF_DROP_PERPF                                                                  0x500c00UL //Access:RW   DataWidth:0x1   Per-PF drop configuration to be used for main and LB traffic of all ports.  Set the bit to 1 to enable the dropping of packets.  Chips: BB_A0 BB_B0 K2
49593 #define NIG_REG_LB_SOPQ_EMPTY                                                                        0x500c04UL //Access:R    DataWidth:0x14  LB SOP descriptor queue empty status.  Bits 15:0 are for LB traffic queues.  Bits 19:16 are for the pure LB queues.  Chips: BB_A0 BB_B0 K2
49594 #define NIG_REG_LB_SOPQ_FULL                                                                         0x500c08UL //Access:R    DataWidth:0x14  LB SOP descriptor queue full status.  Bits 15:0 are for LB traffic queues.  Bits 19:16 are for the pure LB queues.  Chips: BB_A0 BB_B0 K2
49595 #define NIG_REG_TX_SOPQ_EMPTY                                                                        0x500c0cUL //Access:R    DataWidth:0x10  TX SOP descriptor queue empty status - for main traffic queues.  Chips: BB_A0 BB_B0 K2
49596 #define NIG_REG_TX_SOPQ_FULL                                                                         0x500c10UL //Access:R    DataWidth:0x10  TX SOP descriptor queue full status - for main traffic queues.  Chips: BB_A0 BB_B0 K2
49597 #define NIG_REG_TIMESYNC_GEN_REG                                                                     0x500d00UL //Access:WB   DataWidth:0x40  Addresses for TimeSync related registers in the timesync generator sub-module.  Chips: BB_A0 BB_B0
49598 #define NIG_REG_TIMESYNC_GEN_REG_SIZE                                                                64
49599 #define NIG_REG_DORQ_IN_EN                                                                           0x500e00UL //Access:RW   DataWidth:0x1   Input enable for the DORQ interface.  Chips: BB_A0 BB_B0 K2
49600 #define NIG_REG_DEBUG_IN_EN                                                                          0x500e04UL //Access:RW   DataWidth:0x1   Input enable for debug traffic.  Chips: BB_A0 BB_B0 K2
49601 #define NIG_REG_STORM_OUT_EN                                                                         0x500e08UL //Access:RW   DataWidth:0x1   Output enable for the STORM interface. This configuration should be static during run-time.  Chips: BB_A0 BB_B0 K2
49602 #define NIG_REG_PPP_OUT_EN                                                                           0x500e0cUL //Access:RW   DataWidth:0x1   Output enable of message to PXP IF.  Chips: BB_A0 BB_B0 K2
49603 #define NIG_REG_MAC_IN_EN                                                                            0x500e10UL //Access:RW   DataWidth:0x1   Input enable for RX MAC interface.  Chips: BB_A0 BB_B0 K2
49604 #define NIG_REG_MAC_OUT_EN                                                                           0x500e14UL //Access:RW   DataWidth:0x1   Output enable for TX MAC interface.  Chips: BB_A0 BB_B0 K2
49605 #define NIG_REG_RX_BRB_OUT_EN                                                                        0x500e18UL //Access:RW   DataWidth:0x1   Output enble for RX path to BRB.  Chips: BB_A0 BB_B0 K2
49606 #define NIG_REG_LB_BRB_OUT_EN                                                                        0x500e1cUL //Access:RW   DataWidth:0x1   Output enable for LB path to BRB.  Chips: BB_A0 BB_B0 K2
49607 #define NIG_REG_FLOWCTRL_OUT_EN                                                                      0x500e20UL //Access:RW   DataWidth:0x1   Output enable for flow control interfaces to the MAC.  Chips: BB_A0 BB_B0 K2
49608 #define NIG_REG_TX_MACFIFO_ALM_FULL_THR                                                              0x500e40UL //Access:RW   DataWidth:0x4   Almost full threshold for TX MAC FIFO.  Chips: BB_A0 BB_B0 K2
49609 #define NIG_REG_RX_MACFIFO_EMPTY                                                                     0x500e44UL //Access:R    DataWidth:0x1   RX FIFO for receiving data from MAC is empty.  Chips: BB_A0 BB_B0
49610 #define NIG_REG_RX_MACFIFO_FULL                                                                      0x500e48UL //Access:R    DataWidth:0x1   RX FIFO for receiving data from MAC is full.  Chips: BB_A0 BB_B0
49611 #define NIG_REG_TX_MACFIFO_ALM_FULL                                                                  0x500e4cUL //Access:R    DataWidth:0x1   TX FIFO for transmitting data to MAC is almost full.  Chips: BB_A0 BB_B0 K2
49612 #define NIG_REG_TX_MACFIFO_EMPTY                                                                     0x500e50UL //Access:R    DataWidth:0x1   TX FIFO for transmitting data to MAC is empty.  Chips: BB_A0 BB_B0 K2
49613 #define NIG_REG_TX_MACFIFO_FULL                                                                      0x500f00UL //Access:R    DataWidth:0x1   TX FIFO for transmitting data to MAC is full.  Chips: BB_A0 BB_B0 K2
49614 #define NIG_REG_HDR_SKIP_SIZE                                                                        0x501000UL //Access:RW   DataWidth:0x4   Size of the proprietary header, in 32-bit words, that is present at the start of the packet.  This configuration applies to all packets (excluding flush messages) of the same port.  This informatio is used to skip over or remove the proprietary header.  This is also used in tag insertion for management packets.  Chips: BB_A0 BB_B0
49615 #define NIG_REG_INITIAL_HEADER_SIZE                                                                  0x501004UL //Access:RW   DataWidth:0xa   The number of bytes in the header, counting from the start of the packet, to pass to the frame crackers in LLHs.  The actual size passed to LLH is the entire packet or this value, rounded up to the number of cycles, whichever that is smaller.  Chips: BB_A0 BB_B0 K2
49616 #define NIG_REG_RX_PKT_HAS_FCS                                                                       0x501008UL //Access:RW   DataWidth:0x1   Packet has Ethernet FCS field.  Set this bit to indicate that the packet has the FCS field at the end of the packet.  Chips: BB_A0 BB_B0 K2
49617 #define NIG_REG_LLH_ARP_TYPE                                                                         0x50100cUL //Access:RW   DataWidth:0x10  Ethertype for ARP (filtering rules B).  Defaut is 0x0806.  Chips: BB_A0 BB_B0 K2
49618 #define NIG_REG_LLC_JUMBO_TYPE                                                                       0x501010UL //Access:RW   DataWidth:0x10  Ethertype for jumbo packets.  Chips: BB_A0 BB_B0 K2
49619 #define NIG_REG_LLC_TYPE_THRESHOLD                                                                   0x501014UL //Access:RW   DataWidth:0x10  Upper value of LLC Ethertype.  Chips: BB_A0 BB_B0 K2
49620 #define NIG_REG_FIRST_HDR_HDRS_AFTER_BASIC                                                           0x501018UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.  Bit 0-tag0 (outer tag); bit 1-tag1 (inner VLAN); bit 2-tag2; bit 3-tag3; bit 4-tag4; bit 5-tag5; bit 6-reserved; bit 7-llc/snap.  Reset defaults to 0x82 to allow LLC and Inner VLAN headers.  Chips: BB_A0 BB_B0 K2
49621 #define NIG_REG_FIRST_HDR_HDRS_AFTER_LLC                                                             0x50101cUL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after the LLC header.  Chips: BB_A0 BB_B0
49622 #define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_0                                                           0x501020UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 0.  Chips: BB_A0 BB_B0 K2
49623 #define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_1                                                           0x501024UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 1.  Reset defaults to 0x80 to allow LLC header.  Chips: BB_A0 BB_B0 K2
49624 #define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_2                                                           0x501028UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 2.  Chips: BB_A0 BB_B0 K2
49625 #define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_3                                                           0x50102cUL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 3.  Chips: BB_A0 BB_B0 K2
49626 #define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_4                                                           0x501030UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 4.  Chips: BB_A0 BB_B0 K2
49627 #define NIG_REG_FIRST_HDR_HDRS_AFTER_TAG_5                                                           0x501034UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 5.  Chips: BB_A0 BB_B0 K2
49628 #define NIG_REG_INNER_HDR_HDRS_AFTER_BASIC                                                           0x501038UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after the basic Ethernet header.  Bit 0-tag0 (outer tag); bit 1-tag1 (inner VLAN); bit 2-tag2; bit 3-tag3; bit 4-tag4; bit 5-tag5; bit 6-reserved; bit 7-llc/snap.  Reset defaults to 0x82 to allow LLC and Inner VLAN headers.  Chips: BB_A0 BB_B0 K2
49629 #define NIG_REG_INNER_HDR_HDRS_AFTER_LLC                                                             0x50103cUL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after the LLC header.  Chips: BB_A0 BB_B0
49630 #define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_0                                                           0x501040UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 0.  Chips: BB_A0 BB_B0 K2
49631 #define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_1                                                           0x501044UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 1.  Reset defaults to 0x80 to allow LLC header.  Chips: BB_A0 BB_B0 K2
49632 #define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_2                                                           0x501048UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 2.  Chips: BB_A0 BB_B0 K2
49633 #define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_3                                                           0x50104cUL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 3.  Chips: BB_A0 BB_B0 K2
49634 #define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_4                                                           0x501050UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 4.  Chips: BB_A0 BB_B0 K2
49635 #define NIG_REG_INNER_HDR_HDRS_AFTER_TAG_5                                                           0x501054UL //Access:RW   DataWidth:0x8   Bit-map indicating which L2 hdrs may appear after L2 tag 5.  Chips: BB_A0 BB_B0 K2
49636 #define NIG_REG_ENC_TYPE_ENABLE                                                                      0x501058UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49637     #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE                                              (0x1<<0) // Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation.  This enables the comparison of the GRE protocol type field to the configured *gre_eth_type.
49638     #define NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT                                        0
49639     #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE                                               (0x1<<1) // Enable bit for IP-over-GRE (IP GRE) encapsulation.  This enables the comparison of the GRE protocol type field to the configured *ipv4_type and *ipv6_type.
49640     #define NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT                                         1
49641     #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE                                                     (0x1<<2) // Enable bit for VXLAN encapsulation.  This enables the comparison of the UDP destination port number to the configured *vxlan_port.
49642     #define NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT                                               2
49643 #define NIG_REG_VXLAN_PORT                                                                           0x50105cUL //Access:RW   DataWidth:0x10  UDP destination port number for VXLAN.  Chips: BB_A0 BB_B0 K2
49644 #define NIG_REG_IPV4_TYPE                                                                            0x501060UL //Access:RW   DataWidth:0x10  Ethertype for IPv4 packets.  Defaults to 0x0800.  Chips: BB_A0 BB_B0
49645 #define NIG_REG_IPV6_TYPE                                                                            0x501064UL //Access:RW   DataWidth:0x10  Ethertype for IPv6 packets.  Defaults to 0x86DD.  Chips: BB_A0 BB_B0
49646 #define NIG_REG_FCOE_TYPE                                                                            0x501068UL //Access:RW   DataWidth:0x10  FCOE Ethertype - default is 0x8906.  Chips: BB_A0 BB_B0
49647 #define NIG_REG_ROCE_TYPE                                                                            0x50106cUL //Access:RW   DataWidth:0x10  Ethertype for RoCE packets.  Defaults to 0x8915.  Chips: BB_A0 BB_B0 K2
49648 #define NIG_REG_GRE_ETH_TYPE                                                                         0x501070UL //Access:RW   DataWidth:0x10  Ethertype for the encapsulated Ethernet header following the GRE header.  Chips: BB_A0 BB_B0 K2
49649 #define NIG_REG_TCP_PROTOCOL                                                                         0x501074UL //Access:RW   DataWidth:0x8   Next header value indicating TCP protocol.  Chips: BB_A0 BB_B0
49650 #define NIG_REG_UDP_PROTOCOL                                                                         0x501078UL //Access:RW   DataWidth:0x8   Next header value indicating UDP protocol.  Chips: BB_A0 BB_B0
49651 #define NIG_REG_ICMPV4_PROTOCOL                                                                      0x50107cUL //Access:RW   DataWidth:0x8   IPv4 protocol field for ICMPv4 - defaults to 0x01.  Chips: BB_A0 BB_B0
49652 #define NIG_REG_ICMPV6_PROTOCOL                                                                      0x501080UL //Access:RW   DataWidth:0x8   IPv6 next header field for ICMPv6 - defaults to 0x3A.  Chips: BB_A0 BB_B0
49653 #define NIG_REG_GRE_PROTOCOL                                                                         0x501084UL //Access:RW   DataWidth:0x8   Protocol number for GRE header.  Chips: BB_A0 BB_B0 K2
49654 #define NIG_REG_LLH_DEST_MAC_0_0                                                                     0x501088UL //Access:RW   DataWidth:0x20  Destination MAC address 1; The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49655 #define NIG_REG_LLH_DEST_MAC_0_1                                                                     0x50108cUL //Access:RW   DataWidth:0x10  Destination MAC address 1; The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49656 #define NIG_REG_LLH_DEST_MAC_1_0                                                                     0x501090UL //Access:RW   DataWidth:0x20  Destination MAC address 2;The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49657 #define NIG_REG_LLH_DEST_MAC_1_1                                                                     0x501094UL //Access:RW   DataWidth:0x10  Destination MAC address 2;The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49658 #define NIG_REG_LLH_DEST_MAC_2_0                                                                     0x501098UL //Access:RW   DataWidth:0x20  Destination MAC address 3;The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49659 #define NIG_REG_LLH_DEST_MAC_2_1                                                                     0x50109cUL //Access:RW   DataWidth:0x10  Destination MAC address 3;The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49660 #define NIG_REG_LLH_DEST_MAC_3_0                                                                     0x5010a0UL //Access:RW   DataWidth:0x20  Destination MAC address 3.  LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49661 #define NIG_REG_LLH_DEST_MAC_3_1                                                                     0x5010a4UL //Access:RW   DataWidth:0x10  Destination MAC address 3.  LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49662 #define NIG_REG_LLH_DEST_MAC_4_0                                                                     0x5010a8UL //Access:RW   DataWidth:0x20  Destination MAC address 4.  LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49663 #define NIG_REG_LLH_DEST_MAC_4_1                                                                     0x5010acUL //Access:RW   DataWidth:0x10  Destination MAC address 4.  LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49664 #define NIG_REG_LLH_DEST_MAC_5_0                                                                     0x5010b0UL //Access:RW   DataWidth:0x20  Destination MAC address 5.  LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49665 #define NIG_REG_LLH_DEST_MAC_5_1                                                                     0x5010b4UL //Access:RW   DataWidth:0x10  Destination MAC address 5.  LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49666 #define NIG_REG_LLH_ETHERTYPE0                                                                       0x5010b8UL //Access:RW   DataWidth:0x10  Ethertype for filtering packets.  Chips: BB_A0 BB_B0 K2
49667 #define NIG_REG_LLH_ETHERTYPE1                                                                       0x5010bcUL //Access:RW   DataWidth:0x10  Ethertype for filtering packets.  Chips: BB_A0 BB_B0 K2
49668 #define NIG_REG_LLH_VLAN_ID_0                                                                        0x5010c0UL //Access:RW   DataWidth:0xc   Inner VLAN ID  0 used in NCSI filtering.  Chips: BB_A0 BB_B0 K2
49669 #define NIG_REG_LLH_VLAN_ID_1                                                                        0x5010c4UL //Access:RW   DataWidth:0xc   Inner VLAN ID  1 used in NCSI filtering.  Chips: BB_A0 BB_B0 K2
49670 #define NIG_REG_LLH_VLAN_ID_2                                                                        0x5010c8UL //Access:RW   DataWidth:0xc   Inner VLAN ID  2 used in NCSI filtering.  Chips: BB_A0 BB_B0 K2
49671 #define NIG_REG_OUTER_TAG_ID0                                                                        0x5010ccUL //Access:RW   DataWidth:0x10  Outer Tag value to be compared with for NCSI outer tag rules that are enabled by *llh_ncsi_*_mask_otag0 mask bits.  Bits that are not masked out by *outer_tag_value_mask are compared with the value extracted from the packet.  The value from the packet is taken according to the *outer_tag_value_list* configurations, as used for PF classification.  Chips: BB_A0 BB_B0 K2
49672 #define NIG_REG_OUTER_TAG_ID1                                                                        0x5010d0UL //Access:RW   DataWidth:0x10  Outer Tag value to be compared with for NCSI outer tag rules that are enabled by *llh_ncsi_*_mask_otag1 mask bits.  Bits that are not masked out by *outer_tag_value_mask are compared with the value extracted from the packet.  The value from the packet is taken according to the *outer_tag_value_list* configurations, as used for PF classification.  Chips: BB_A0 BB_B0 K2
49673 #define NIG_REG_LLH_DEST_IP_0_0                                                                      0x5010d4UL //Access:RW   DataWidth:0x20  Destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49674 #define NIG_REG_LLH_DEST_IP_0_1                                                                      0x5010d8UL //Access:RW   DataWidth:0x20  Destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49675 #define NIG_REG_LLH_DEST_IP_0_2                                                                      0x5010dcUL //Access:RW   DataWidth:0x20  Destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49676 #define NIG_REG_LLH_DEST_IP_0_3                                                                      0x5010e0UL //Access:RW   DataWidth:0x20  Destination IP address 1;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49677 #define NIG_REG_LLH_DEST_IP_1_0                                                                      0x5010e4UL //Access:RW   DataWidth:0x20  Destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49678 #define NIG_REG_LLH_DEST_IP_1_1                                                                      0x5010e8UL //Access:RW   DataWidth:0x20  Destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49679 #define NIG_REG_LLH_DEST_IP_1_2                                                                      0x5010ecUL //Access:RW   DataWidth:0x20  Destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49680 #define NIG_REG_LLH_DEST_IP_1_3                                                                      0x5010f0UL //Access:RW   DataWidth:0x20  Destination IP address 2;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49681 #define NIG_REG_LLH_DEST_IP_2_0                                                                      0x5010f4UL //Access:RW   DataWidth:0x20  Destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49682 #define NIG_REG_LLH_DEST_IP_2_1                                                                      0x5010f8UL //Access:RW   DataWidth:0x20  Destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49683 #define NIG_REG_LLH_DEST_IP_2_2                                                                      0x5010fcUL //Access:RW   DataWidth:0x20  Destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49684 #define NIG_REG_LLH_DEST_IP_2_3                                                                      0x501100UL //Access:RW   DataWidth:0x20  Destination IP address 3;The LLH will look for this address in all incoming packets. In case of IPv4 use only 32lsb.  Chips: BB_A0 BB_B0 K2
49685 #define NIG_REG_LLH_IPV4_IPV6_0                                                                      0x501104UL //Access:RW   DataWidth:0x1   Determine the IP version to look for in llh_dest_ip_0: 0 - IPv6; 1-IPv4.  Chips: BB_A0 BB_B0 K2
49686 #define NIG_REG_LLH_IPV4_IPV6_1                                                                      0x501108UL //Access:RW   DataWidth:0x1   Determine the IP version to look for in llh_dest_ip_1: 0 - IPv6; 1-IPv4.  Chips: BB_A0 BB_B0 K2
49687 #define NIG_REG_LLH_IPV4_IPV6_2                                                                      0x50110cUL //Access:RW   DataWidth:0x1   Determine the IP version to look for in llh_dest_ip_2: 0 - IPv6; 1-IPv4.  Chips: BB_A0 BB_B0 K2
49688 #define NIG_REG_LLH_DEST_TCP_0                                                                       0x501110UL //Access:RW   DataWidth:0x10  Destination TCP address  1. The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49689 #define NIG_REG_LLH_DEST_TCP_1                                                                       0x501114UL //Access:RW   DataWidth:0x10  Destination TCP address  2. The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49690 #define NIG_REG_LLH_DEST_TCP_2                                                                       0x501118UL //Access:RW   DataWidth:0x10  Destination TCP address  3. The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49691 #define NIG_REG_LLH_DEST_UDP_0                                                                       0x50111cUL //Access:RW   DataWidth:0x10  Destination UDP address  1 The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49692 #define NIG_REG_LLH_DEST_UDP_1                                                                       0x501120UL //Access:RW   DataWidth:0x10  Destination UDP address  2  The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49693 #define NIG_REG_LLH_DEST_UDP_2                                                                       0x501124UL //Access:RW   DataWidth:0x10  Destination UDP address  3  The LLH will look for this address in all incoming packets.  Chips: BB_A0 BB_B0 K2
49694 #define NIG_REG_RX_LLH_NCSI_MCP_MASK                                                                 0x501128UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
49695     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_BRCST                                                       (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to MCP.
49696     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_BRCST_SHIFT                                                 0
49697     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ALLMLCST                                                    (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to MCP.
49698     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ALLMLCST_SHIFT                                              1
49699     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV4MLCST                                                   (0x1<<2) // Mask bit for forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to MCP.
49700     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV4MLCST_SHIFT                                             2
49701     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV6_MLCST                                                  (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to MCP.
49702     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IPV6_MLCST_SHIFT                                            3
49703     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UNCST                                                       (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to MCP.
49704     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UNCST_SHIFT                                                 4
49705     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC0                                                        (0x1<<5) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to MCP.
49706     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC0_SHIFT                                                  5
49707     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC1                                                        (0x1<<6) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to MCP.
49708     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC1_SHIFT                                                  6
49709     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC2                                                        (0x1<<7) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to MCP.
49710     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC2_SHIFT                                                  7
49711     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC3                                                        (0x1<<8) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_3 to MCP.
49712     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC3_SHIFT                                                  8
49713     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC4                                                        (0x1<<9) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to MCP.
49714     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC4_SHIFT                                                  9
49715     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC5                                                        (0x1<<10) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to MCP.
49716     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_MAC5_SHIFT                                                  10
49717     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE0                                                  (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to MCP.
49718     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE0_SHIFT                                            11
49719     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE1                                                  (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
49720     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ETHERTYPE1_SHIFT                                            12
49721     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ARP                                                         (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and Bcast address to MCP.
49722     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ARP_SHIFT                                                   13
49723     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP0                                                         (0x1<<14) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to MCP.
49724     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP0_SHIFT                                                   14
49725     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP1                                                         (0x1<<15) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to MCP.
49726     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP1_SHIFT                                                   15
49727     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP2                                                         (0x1<<16) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to MCP.
49728     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IP2_SHIFT                                                   16
49729     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP0                                                        (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to MCP.
49730     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP0_SHIFT                                                  17
49731     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP1                                                        (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to MCP.
49732     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP1_SHIFT                                                  18
49733     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP2                                                        (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to MCP.
49734     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_TCP2_SHIFT                                                  19
49735     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_DST                                                  (0x1<<20) // Mask bit for forwarding packets with NetBIOS TCP destination port 137/138/139 to MCP.
49736     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_DST_SHIFT                                            20
49737     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_SRC                                                  (0x1<<21) // Mask bit for forwarding packets with NetBIOS TCP source port 137/138 /139 to MCP.
49738     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_T_SRC_SHIFT                                            21
49739     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP0                                                        (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to MCP.
49740     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP0_SHIFT                                                  22
49741     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP1                                                        (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to MCP.
49742     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP1_SHIFT                                                  23
49743     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP2                                                        (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to MCP.
49744     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_UDP2_SHIFT                                                  24
49745     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_RMCP                                                        (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to MCP.
49746     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_RMCP_SHIFT                                                  25
49747     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_DST                                                  (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to MCP.
49748     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_DST_SHIFT                                            26
49749     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_SRC                                                  (0x1<<27) // Mask bit for forwarding packets with NetBIOS UDP source port 137/138 /139 to MCP.
49750     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_NTBS_U_SRC_SHIFT                                            27
49751     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_DHCP                                                        (0x1<<28) // Mask bit for forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to MCP.
49752     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_DHCP_SHIFT                                                  28
49753     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_NA                                                   (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to MCP.
49754     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_NA_SHIFT                                             29
49755     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_RA                                                   (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type= 134 and dst_mac = 0x33:33:00:00:00:01) to MCP.
49756     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_RA_SHIFT                                             30
49757     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6                                                      (0x1<<31) // Mask bit for forwarding ICMPv6 packets to MCP.
49758     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_ICMPV6_SHIFT                                                31
49759 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN                                                           0x50112cUL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49760     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ANY                                                   (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to MCP.
49761     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ANY_SHIFT                                             0
49762     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_NONE                                                  (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to MCP.
49763     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_NONE_SHIFT                                            1
49764     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID0                                                   (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to MCP.
49765     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID0_SHIFT                                             2
49766     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID1                                                   (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to MCP.
49767     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID1_SHIFT                                             3
49768     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID2                                                   (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to MCP.
49769     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_IVLAN_ID2_SHIFT                                             4
49770 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG                                                            0x501130UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49771     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_ANY                                                    (0x1<<0) // Mask bit for forwarding packets with outer tag present to MCP.
49772     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_ANY_SHIFT                                              0
49773     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_NONE                                                   (0x1<<1) // Mask bit for forwarding packets with no outer tag to MCP.
49774     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_NONE_SHIFT                                             1
49775     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG0                                                       (0x1<<2) // Mask bit for forwarding packets with the outer tag matching *outer_tag_id0 to MCP.
49776     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG0_SHIFT                                                 2
49777     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG1                                                       (0x1<<3) // Mask bit for forwarding packets with the outer tag matching *outer_tag_id1 to MCP.
49778     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG1_SHIFT                                                 3
49779     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_PF                                                     (0x1<<4) // Mask bit for forwarding packets with outer tag matching the outer tag of one of the enabled PFs to MCP.
49780     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_OTAG_PF_SHIFT                                               4
49781 #define NIG_REG_RX_LLH_SVOL_MCP_MASK                                                                 0x501134UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49782     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ARP                                                         (0x1<<0) // Mask bit for forwarding packets with Ethertype matching llh_arp_type to MCP.
49783     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ARP_SHIFT                                                   0
49784     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4                                                      (0x1<<1) // Mask bit for forwarding IPv4 packets with protocol field matching llh_icmpv4_protocol to MCP.
49785     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_SHIFT                                                1
49786     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6                                                      (0x1<<2) // Mask bit for forwarding IPv6 packets with next header field matching llh_icmpv6_protocol to MCP.
49787     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_SHIFT                                                2
49788     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_ER                                                   (0x1<<3) // Mask bit for forwarding ICMPv4 packets with ICMP type 8 to MCP.
49789     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV4_ER_SHIFT                                             3
49790     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_ER                                                   (0x1<<4) // Mask bit for forwarding ICMPv6 packets with ICMP type 128 to MCP.
49791     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_ER_SHIFT                                             4
49792     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_NS                                                   (0x1<<5) // Mask bit for forwarding ICMPv6 packets with ICMP type 135 to MCP.
49793     #define NIG_REG_RX_LLH_SVOL_MCP_MASK_ICMPV6_NS_SHIFT                                             5
49794 #define NIG_REG_RX_LLH_SVOL_MCP_FWD_ALLPF                                                            0x501138UL //Access:RW   DataWidth:0x1   Enable bit for forwarding packets from all PFs, including packets that failed PF classification, to MCP in multifunction mode.  Chips: BB_A0 BB_B0 K2
49795 #define NIG_REG_RX_LLH_SVOL_MCP_FWD_PERPF                                                            0x50113cUL //Access:RW   DataWidth:0x1   Enable bit for forwarding packets for each PF to MCP in multifunction mode.  This is a per-PF split register.  Chips: BB_A0 BB_B0 K2
49796 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK                                                          0x501140UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
49797     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_BRCST                                                (0x1<<0) // Mask bit for not forwarding broadcast (MAC destination address of all 1's) packets to the host.
49798     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_BRCST_SHIFT                                          0
49799     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ALLMLCST                                             (0x1<<1) // Mask bit for not forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to the host.
49800     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ALLMLCST_SHIFT                                       1
49801     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV4MLCST                                            (0x1<<2) // Mask bit for not forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to the host.
49802     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV4MLCST_SHIFT                                      2
49803     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLCST                                           (0x1<<3) // Mask bit for not forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the host.
49804     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLCST_SHIFT                                     3
49805     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UNCST                                                (0x1<<4) // Mask bit for not forwarding unicast (MAC destination address[40]==0) packets to the host.
49806     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UNCST_SHIFT                                          4
49807     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC0                                                 (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to the host.
49808     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC0_SHIFT                                           5
49809     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC1                                                 (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to the host.
49810     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC1_SHIFT                                           6
49811     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC2                                                 (0x1<<7) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to the host.
49812     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC2_SHIFT                                           7
49813     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC3                                                 (0x1<<8) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_3 to the host.
49814     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC3_SHIFT                                           8
49815     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC4                                                 (0x1<<9) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to the host.
49816     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC4_SHIFT                                           9
49817     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC5                                                 (0x1<<10) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to the host.
49818     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC5_SHIFT                                           10
49819     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE0                                           (0x1<<11) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype0 to the host.
49820     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE0_SHIFT                                     11
49821     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE1                                           (0x1<<12) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
49822     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ETHERTYPE1_SHIFT                                     12
49823     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ARP                                                  (0x1<<13) // Mask bit for not forwarding packets with Ethertype of 0x0806 and bcast address to the host.
49824     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ARP_SHIFT                                            13
49825     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP0                                                  (0x1<<14) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the host.
49826     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP0_SHIFT                                            14
49827     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP1                                                  (0x1<<15) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the host.
49828     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP1_SHIFT                                            15
49829     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP2                                                  (0x1<<16) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the host.
49830     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IP2_SHIFT                                            16
49831     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP0                                                 (0x1<<17) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the host.
49832     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP0_SHIFT                                           17
49833     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP1                                                 (0x1<<18) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the host.
49834     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP1_SHIFT                                           18
49835     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP2                                                 (0x1<<19) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the host.
49836     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_TCP2_SHIFT                                           19
49837     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_DST                                           (0x1<<20) // Mask bit for not forwarding packets with NetBIOS TCP destination port 137/138/139 to the host.
49838     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_DST_SHIFT                                     20
49839     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_SRC                                           (0x1<<21) // Mask bit for not forwarding packets with NetBIOS TCP source port 137/138 /139 to the host.
49840     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_T_SRC_SHIFT                                     21
49841     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP0                                                 (0x1<<22) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the host.
49842     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP0_SHIFT                                           22
49843     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP1                                                 (0x1<<23) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the host.
49844     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP1_SHIFT                                           23
49845     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP2                                                 (0x1<<24) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the host.
49846     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_UDP2_SHIFT                                           24
49847     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_RMCP                                                 (0x1<<25) // Mask bit for not forwarding packets with RMCP UDP ports (0x26f and 0x298) to the host.
49848     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_RMCP_SHIFT                                           25
49849     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_DST                                           (0x1<<26) // Mask bit for not forwarding packets with NetBIOS UDP destination port 137/138/139 to the host.
49850     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_DST_SHIFT                                     26
49851     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_SRC                                           (0x1<<27) // Mask bit for not forwarding packets with NetBIOS UDP source port 137/138 /139 to the host.
49852     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_NTBS_U_SRC_SHIFT                                     27
49853     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP                                                 (0x1<<28) // Mask bit for not forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to the host.
49854     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_SHIFT                                           28
49855     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_NA                                            (0x1<<29) // Mask bit for not forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the host.
49856     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_NA_SHIFT                                      29
49857     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_RA                                            (0x1<<30) // Mask bit for not forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the host.
49858     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_RA_SHIFT                                      30
49859     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6                                               (0x1<<31) // Mask bit for not forwarding ICMPv6 packets to the host.
49860     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_ICMPV6_SHIFT                                         31
49861 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN                                                    0x501144UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49862     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ANY                                            (0x1<<0) // Mask bit for not forwarding packets with inner VLAN present to the host.
49863     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ANY_SHIFT                                      0
49864     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_NONE                                           (0x1<<1) // Mask bit for not forwarding packets with no inner VLAN to the host.
49865     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_NONE_SHIFT                                     1
49866     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID0                                            (0x1<<2) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the host.
49867     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID0_SHIFT                                      2
49868     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID1                                            (0x1<<3) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the host.
49869     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID1_SHIFT                                      3
49870     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID2                                            (0x1<<4) // Mask bit for not forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the host.
49871     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_IVLAN_ID2_SHIFT                                      4
49872 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG                                                     0x501148UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49873     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_ANY                                             (0x1<<0) // Mask bit for not forwarding packets with outer tag present to the host.
49874     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_ANY_SHIFT                                       0
49875     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_NONE                                            (0x1<<1) // Mask bit for not forwarding packets with no outer tag to the host.
49876     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_NONE_SHIFT                                      1
49877     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG0                                                (0x1<<2) // Mask bit for not forwarding packets with the outer tag matching *outer_tag_id0 to the host.
49878     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG0_SHIFT                                          2
49879     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG1                                                (0x1<<3) // Mask bit for not forwarding packets with the outer tag matching *outer_tag_id1 to the host.
49880     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG1_SHIFT                                          3
49881     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_PF                                              (0x1<<4) // Mask bit for not forwarding packets with outer tag matching the outer tag of one of the enabled PFs to the host.
49882     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_OTAG_PF_SHIFT                                        4
49883 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK                                                          0x50114cUL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49884     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ARP                                                  (0x1<<0) // Mask bit for not forwarding packets with Ethertype matching llh_arp_type to the host.
49885     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ARP_SHIFT                                            0
49886     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4                                               (0x1<<1) // Mask bit for not forwarding IPv4 packets with protocol field matching llh_icmpv4_protocol to the host.
49887     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_SHIFT                                         1
49888     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6                                               (0x1<<2) // Mask bit for not forwarding IPv6 packets with next header field matching llh_icmpv6_protocol to the host.
49889     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_SHIFT                                         2
49890     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_ER                                            (0x1<<3) // Mask bit for not forwarding ICMPv4 packets with ICMP type 8 to the host.
49891     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV4_ER_SHIFT                                      3
49892     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_ER                                            (0x1<<4) // Mask bit for not forwarding ICMPv6 packets with ICMP type 128 to the host.
49893     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_ER_SHIFT                                      4
49894     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_NS                                            (0x1<<5) // Mask bit for not forwarding ICMPv6 packets with ICMP type 135 to the host.
49895     #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_MASK_ICMPV6_NS_SHIFT                                      5
49896 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_ALLPF                                                         0x501150UL //Access:RW   DataWidth:0x1   Enable bit for not forwarding packets from all PFs, including packets that failed PF classification, to the host in multifunction mode.  Chips: BB_A0 BB_B0 K2
49897 #define NIG_REG_RX_LLH_SVOL_BRB_DNTFWD_PERPF                                                         0x501154UL //Access:RW   DataWidth:0x1   Enable bit for not forwarding packets for the PF to the host in multifunction mode.  This is a per-PF split register.  Chips: BB_A0 BB_B0 K2
49898 #define NIG_REG_L2FILT_ETHERTYPE0                                                                    0x501158UL //Access:RW   DataWidth:0x10  Ethertype configuration for L2 filter.  Chips: BB_A0 BB_B0 K2
49899 #define NIG_REG_L2FILT_ETHERTYPE1                                                                    0x50115cUL //Access:RW   DataWidth:0x10  Ethertype configuration for L2 filter.  Chips: BB_A0 BB_B0 K2
49900 #define NIG_REG_L2FILT_ETHERTYPE2                                                                    0x501160UL //Access:RW   DataWidth:0x10  Ethertype configuration for L2 filter.  Chips: BB_A0 BB_B0 K2
49901 #define NIG_REG_L2FILT_ETHERTYPE3                                                                    0x501164UL //Access:RW   DataWidth:0x10  Ethertype configuration for L2 filter.  Chips: BB_A0 BB_B0 K2
49902 #define NIG_REG_L2FILT_ETHERTYPE4                                                                    0x501168UL //Access:RW   DataWidth:0x10  Ethertype configuration for L2 filter.  Chips: BB_A0 BB_B0 K2
49903 #define NIG_REG_L2FILT_ETHERTYPE5                                                                    0x50116cUL //Access:RW   DataWidth:0x10  Ethertype configuration for L2 filter.  Chips: BB_A0 BB_B0 K2
49904 #define NIG_REG_L2FILT_MAC_DA0_0                                                                     0x501170UL //Access:RW   DataWidth:0x20  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49905 #define NIG_REG_L2FILT_MAC_DA0_1                                                                     0x501174UL //Access:RW   DataWidth:0x10  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49906 #define NIG_REG_L2FILT_MAC_DA1_0                                                                     0x501178UL //Access:RW   DataWidth:0x20  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49907 #define NIG_REG_L2FILT_MAC_DA1_1                                                                     0x50117cUL //Access:RW   DataWidth:0x10  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49908 #define NIG_REG_L2FILT_MAC_DA2_0                                                                     0x501180UL //Access:RW   DataWidth:0x20  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49909 #define NIG_REG_L2FILT_MAC_DA2_1                                                                     0x501184UL //Access:RW   DataWidth:0x10  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49910 #define NIG_REG_L2FILT_MAC_DA3_0                                                                     0x501188UL //Access:RW   DataWidth:0x20  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49911 #define NIG_REG_L2FILT_MAC_DA3_1                                                                     0x50118cUL //Access:RW   DataWidth:0x10  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49912 #define NIG_REG_L2FILT_MAC_DA4_0                                                                     0x501190UL //Access:RW   DataWidth:0x20  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49913 #define NIG_REG_L2FILT_MAC_DA4_1                                                                     0x501194UL //Access:RW   DataWidth:0x10  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49914 #define NIG_REG_L2FILT_MAC_DA5_0                                                                     0x501198UL //Access:RW   DataWidth:0x20  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49915 #define NIG_REG_L2FILT_MAC_DA5_1                                                                     0x50119cUL //Access:RW   DataWidth:0x10  MAC destination address for L2 filter.  Chips: BB_A0 BB_B0 K2
49916 #define NIG_REG_L2FILT_INNER_VLAN                                                                    0x5011a0UL //Access:RW   DataWidth:0xc   Inner VLAN ID for L2 filter.  Chips: BB_A0 BB_B0 K2
49917 #define NIG_REG_L2FILT_OUTER_TAG                                                                     0x5011a4UL //Access:RW   DataWidth:0x10  Outer tag value for L2 filter.  Chips: BB_A0 BB_B0 K2
49918 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0                                                              0x5011a8UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49919     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_EN                                                       (0x1<<0) // L2 filter rule enable.  Set this bit to enable this rule.
49920     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_EN_SHIFT                                                 0
49921     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_EN                                                  (0x1<<1) // L2 filter address matching enable.
49922     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_EN_SHIFT                                            1
49923     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_SEL                                                 (0x7<<2) // L2 filter address select for choosing one of the *llh_l2filt_mac_da* configurations for comparison.  A value of 6 selects the broadcast address of all 1's for comparison.  A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
49924     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ADDR_SEL_SHIFT                                           2
49925     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_EN                                             (0x1<<5) // L2 filter Ethertype matching enable.
49926     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_EN_SHIFT                                       5
49927     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_SEL                                            (0x7<<6) // L2 filter Ethertype select for choosing one of the *llh_l2filt_ethertype* configurations for comparison.
49928     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_ETHERTYPE_SEL_SHIFT                                      6
49929     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_INNER_VLAN_EN                                            (0x1<<9) // L2 filter inner VLAN matching enable.
49930     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_INNER_VLAN_EN_SHIFT                                      9
49931     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_OUTER_TAG_EN                                             (0x1<<10) // L2 filter outer tag matching enable.
49932     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE0_OUTER_TAG_EN_SHIFT                                       10
49933 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1                                                              0x5011acUL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49934     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_EN                                                       (0x1<<0) // See definition for *l2filt_mcp_rule0.
49935     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_EN_SHIFT                                                 0
49936     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_EN                                                  (0x1<<1) // See definition for *l2filt_mcp_rule0.
49937     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_EN_SHIFT                                            1
49938     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_SEL                                                 (0x7<<2) // See definition for *l2filt_mcp_rule0.
49939     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ADDR_SEL_SHIFT                                           2
49940     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_EN                                             (0x1<<5) // See definition for *l2filt_mcp_rule0.
49941     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_EN_SHIFT                                       5
49942     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_SEL                                            (0x7<<6) // See definition for *l2filt_mcp_rule0.
49943     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_ETHERTYPE_SEL_SHIFT                                      6
49944     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_INNER_VLAN_EN                                            (0x1<<9) // L2 filter inner VLAN matching enable.
49945     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_INNER_VLAN_EN_SHIFT                                      9
49946     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_OUTER_TAG_EN                                             (0x1<<10) // L2 filter outer tag matching enable.
49947     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE1_OUTER_TAG_EN_SHIFT                                       10
49948 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2                                                              0x5011b0UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49949     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_EN                                                       (0x1<<0) // See definition for *l2filt_mcp_rule0.
49950     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_EN_SHIFT                                                 0
49951     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_EN                                                  (0x1<<1) // See definition for *l2filt_mcp_rule0.
49952     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_EN_SHIFT                                            1
49953     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_SEL                                                 (0x7<<2) // See definition for *l2filt_mcp_rule0.
49954     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ADDR_SEL_SHIFT                                           2
49955     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_EN                                             (0x1<<5) // See definition for *l2filt_mcp_rule0.
49956     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_EN_SHIFT                                       5
49957     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_SEL                                            (0x7<<6) // See definition for *l2filt_mcp_rule0.
49958     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_ETHERTYPE_SEL_SHIFT                                      6
49959     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_INNER_VLAN_EN                                            (0x1<<9) // L2 filter inner VLAN matching enable.
49960     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_INNER_VLAN_EN_SHIFT                                      9
49961     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_OUTER_TAG_EN                                             (0x1<<10) // L2 filter outer tag matching enable.
49962     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE2_OUTER_TAG_EN_SHIFT                                       10
49963 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3                                                              0x5011b4UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49964     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_EN                                                       (0x1<<0) // See definition for *l2filt_mcp_rule0.
49965     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_EN_SHIFT                                                 0
49966     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_EN                                                  (0x1<<1) // See definition for *l2filt_mcp_rule0.
49967     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_EN_SHIFT                                            1
49968     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_SEL                                                 (0x7<<2) // See definition for *l2filt_mcp_rule0.
49969     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ADDR_SEL_SHIFT                                           2
49970     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_EN                                             (0x1<<5) // See definition for *l2filt_mcp_rule0.
49971     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_EN_SHIFT                                       5
49972     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_SEL                                            (0x7<<6) // See definition for *l2filt_mcp_rule0.
49973     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_ETHERTYPE_SEL_SHIFT                                      6
49974     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_INNER_VLAN_EN                                            (0x1<<9) // L2 filter inner VLAN matching enable.
49975     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_INNER_VLAN_EN_SHIFT                                      9
49976     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_OUTER_TAG_EN                                             (0x1<<10) // L2 filter outer tag matching enable.
49977     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE3_OUTER_TAG_EN_SHIFT                                       10
49978 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4                                                              0x5011b8UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49979     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_EN                                                       (0x1<<0) // See definition for *l2filt_mcp_rule0.
49980     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_EN_SHIFT                                                 0
49981     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_EN                                                  (0x1<<1) // See definition for *l2filt_mcp_rule0.
49982     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_EN_SHIFT                                            1
49983     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_SEL                                                 (0x7<<2) // See definition for *l2filt_mcp_rule0.
49984     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ADDR_SEL_SHIFT                                           2
49985     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_EN                                             (0x1<<5) // See definition for *l2filt_mcp_rule0.
49986     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_EN_SHIFT                                       5
49987     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_SEL                                            (0x7<<6) // See definition for *l2filt_mcp_rule0.
49988     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_ETHERTYPE_SEL_SHIFT                                      6
49989     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_INNER_VLAN_EN                                            (0x1<<9) // L2 filter inner VLAN matching enable.
49990     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_INNER_VLAN_EN_SHIFT                                      9
49991     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_OUTER_TAG_EN                                             (0x1<<10) // L2 filter outer tag matching enable.
49992     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE4_OUTER_TAG_EN_SHIFT                                       10
49993 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5                                                              0x5011bcUL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
49994     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_EN                                                       (0x1<<0) // See definition for *l2filt_mcp_rule0.
49995     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_EN_SHIFT                                                 0
49996     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_EN                                                  (0x1<<1) // See definition for *l2filt_mcp_rule0.
49997     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_EN_SHIFT                                            1
49998     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_SEL                                                 (0x7<<2) // See definition for *l2filt_mcp_rule0.
49999     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ADDR_SEL_SHIFT                                           2
50000     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_EN                                             (0x1<<5) // See definition for *l2filt_mcp_rule0.
50001     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_EN_SHIFT                                       5
50002     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_SEL                                            (0x7<<6) // See definition for *l2filt_mcp_rule0.
50003     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_ETHERTYPE_SEL_SHIFT                                      6
50004     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_INNER_VLAN_EN                                            (0x1<<9) // L2 filter inner VLAN matching enable.
50005     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_INNER_VLAN_EN_SHIFT                                      9
50006     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_OUTER_TAG_EN                                             (0x1<<10) // L2 filter outer tag matching enable.
50007     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE5_OUTER_TAG_EN_SHIFT                                       10
50008 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6                                                              0x5011c0UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50009     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_EN                                                       (0x1<<0) // See definition for *l2filt_mcp_rule0.
50010     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_EN_SHIFT                                                 0
50011     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_EN                                                  (0x1<<1) // See definition for *l2filt_mcp_rule0.
50012     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_EN_SHIFT                                            1
50013     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_SEL                                                 (0x7<<2) // See definition for *l2filt_mcp_rule0.
50014     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ADDR_SEL_SHIFT                                           2
50015     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_EN                                             (0x1<<5) // See definition for *l2filt_mcp_rule0.
50016     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_EN_SHIFT                                       5
50017     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_SEL                                            (0x7<<6) // See definition for *l2filt_mcp_rule0.
50018     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_ETHERTYPE_SEL_SHIFT                                      6
50019     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_INNER_VLAN_EN                                            (0x1<<9) // L2 filter inner VLAN matching enable.
50020     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_INNER_VLAN_EN_SHIFT                                      9
50021     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_OUTER_TAG_EN                                             (0x1<<10) // L2 filter outer tag matching enable.
50022     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE6_OUTER_TAG_EN_SHIFT                                       10
50023 #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7                                                              0x5011c4UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50024     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_EN                                                       (0x1<<0) // See definition for *l2filt_mcp_rule0.
50025     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_EN_SHIFT                                                 0
50026     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_EN                                                  (0x1<<1) // See definition for *l2filt_mcp_rule0.
50027     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_EN_SHIFT                                            1
50028     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_SEL                                                 (0x7<<2) // See definition for *l2filt_mcp_rule0.
50029     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ADDR_SEL_SHIFT                                           2
50030     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_EN                                             (0x1<<5) // See definition for *l2filt_mcp_rule0.
50031     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_EN_SHIFT                                       5
50032     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_SEL                                            (0x7<<6) // See definition for *l2filt_mcp_rule0.
50033     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_ETHERTYPE_SEL_SHIFT                                      6
50034     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_INNER_VLAN_EN                                            (0x1<<9) // L2 filter inner VLAN matching enable.
50035     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_INNER_VLAN_EN_SHIFT                                      9
50036     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_OUTER_TAG_EN                                             (0x1<<10) // L2 filter outer tag matching enable.
50037     #define NIG_REG_RX_LLH_L2FILT_MCP_RULE7_OUTER_TAG_EN_SHIFT                                       10
50038 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0                                                       0x5011c8UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50039     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_EN                                                (0x1<<0) // L2 filter (for not forwarding to the host) rule enable.  Set this bit to enable this rule.
50040     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_EN_SHIFT                                          0
50041     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_EN                                           (0x1<<1) // L2 filter (for not forwarding to the host) address matching enable.
50042     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_EN_SHIFT                                     1
50043     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_SEL                                          (0x7<<2) // L2 filter (for not forwarding to the host) address select for choosing one of the *llh_l2filt_mac_da* configurations for comparison.  A value of 6 selects the broadcast address of all 1's for comparison. A value of 7 selects the MAC address range 01-80-C2-00-00-00 to 01-80-C2-00-00-0F.
50044     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ADDR_SEL_SHIFT                                    2
50045     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_EN                                      (0x1<<5) // L2 filter (for not forwarding to the host) Ethertype matching enable.
50046     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_EN_SHIFT                                5
50047     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_SEL                                     (0x7<<6) // L2 filter (for not forwarding to the host) Ethertype select for choosing one of the *llh_l2filt_ethertype* configurations for comparison.
50048     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_ETHERTYPE_SEL_SHIFT                               6
50049     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_INNER_VLAN_EN                                     (0x1<<9) // L2 filter inner VLAN matching enable.
50050     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_INNER_VLAN_EN_SHIFT                               9
50051     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_OUTER_TAG_EN                                      (0x1<<10) // L2 filter outer tag matching enable.
50052     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE0_OUTER_TAG_EN_SHIFT                                10
50053 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1                                                       0x5011ccUL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50054     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_EN                                                (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
50055     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_EN_SHIFT                                          0
50056     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_EN                                           (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
50057     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_EN_SHIFT                                     1
50058     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_SEL                                          (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
50059     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ADDR_SEL_SHIFT                                    2
50060     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_EN                                      (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
50061     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_EN_SHIFT                                5
50062     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_SEL                                     (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
50063     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_ETHERTYPE_SEL_SHIFT                               6
50064     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_INNER_VLAN_EN                                     (0x1<<9) // L2 filter inner VLAN matching enable.
50065     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_INNER_VLAN_EN_SHIFT                               9
50066     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_OUTER_TAG_EN                                      (0x1<<10) // L2 filter outer tag matching enable.
50067     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE1_OUTER_TAG_EN_SHIFT                                10
50068 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2                                                       0x5011d0UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50069     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_EN                                                (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
50070     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_EN_SHIFT                                          0
50071     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_EN                                           (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
50072     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_EN_SHIFT                                     1
50073     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_SEL                                          (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
50074     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ADDR_SEL_SHIFT                                    2
50075     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_EN                                      (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
50076     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_EN_SHIFT                                5
50077     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_SEL                                     (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
50078     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_ETHERTYPE_SEL_SHIFT                               6
50079     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_INNER_VLAN_EN                                     (0x1<<9) // L2 filter inner VLAN matching enable.
50080     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_INNER_VLAN_EN_SHIFT                               9
50081     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_OUTER_TAG_EN                                      (0x1<<10) // L2 filter outer tag matching enable.
50082     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE2_OUTER_TAG_EN_SHIFT                                10
50083 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3                                                       0x5011d4UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50084     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_EN                                                (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
50085     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_EN_SHIFT                                          0
50086     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_EN                                           (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
50087     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_EN_SHIFT                                     1
50088     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_SEL                                          (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
50089     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ADDR_SEL_SHIFT                                    2
50090     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_EN                                      (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
50091     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_EN_SHIFT                                5
50092     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_SEL                                     (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
50093     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_ETHERTYPE_SEL_SHIFT                               6
50094     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_INNER_VLAN_EN                                     (0x1<<9) // L2 filter inner VLAN matching enable.
50095     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_INNER_VLAN_EN_SHIFT                               9
50096     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_OUTER_TAG_EN                                      (0x1<<10) // L2 filter outer tag matching enable.
50097     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE3_OUTER_TAG_EN_SHIFT                                10
50098 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4                                                       0x5011d8UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50099     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_EN                                                (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
50100     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_EN_SHIFT                                          0
50101     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_EN                                           (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
50102     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_EN_SHIFT                                     1
50103     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_SEL                                          (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
50104     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ADDR_SEL_SHIFT                                    2
50105     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_EN                                      (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
50106     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_EN_SHIFT                                5
50107     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_SEL                                     (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
50108     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_ETHERTYPE_SEL_SHIFT                               6
50109     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_INNER_VLAN_EN                                     (0x1<<9) // L2 filter inner VLAN matching enable.
50110     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_INNER_VLAN_EN_SHIFT                               9
50111     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_OUTER_TAG_EN                                      (0x1<<10) // L2 filter outer tag matching enable.
50112     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE4_OUTER_TAG_EN_SHIFT                                10
50113 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5                                                       0x5011dcUL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50114     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_EN                                                (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
50115     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_EN_SHIFT                                          0
50116     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_EN                                           (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
50117     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_EN_SHIFT                                     1
50118     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_SEL                                          (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
50119     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ADDR_SEL_SHIFT                                    2
50120     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_EN                                      (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
50121     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_EN_SHIFT                                5
50122     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_SEL                                     (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
50123     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_ETHERTYPE_SEL_SHIFT                               6
50124     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_INNER_VLAN_EN                                     (0x1<<9) // L2 filter inner VLAN matching enable.
50125     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_INNER_VLAN_EN_SHIFT                               9
50126     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_OUTER_TAG_EN                                      (0x1<<10) // L2 filter outer tag matching enable.
50127     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE5_OUTER_TAG_EN_SHIFT                                10
50128 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6                                                       0x5011e0UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50129     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_EN                                                (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
50130     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_EN_SHIFT                                          0
50131     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_EN                                           (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
50132     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_EN_SHIFT                                     1
50133     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_SEL                                          (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
50134     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ADDR_SEL_SHIFT                                    2
50135     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_EN                                      (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
50136     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_EN_SHIFT                                5
50137     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_SEL                                     (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
50138     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_ETHERTYPE_SEL_SHIFT                               6
50139     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_INNER_VLAN_EN                                     (0x1<<9) // L2 filter inner VLAN matching enable.
50140     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_INNER_VLAN_EN_SHIFT                               9
50141     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_OUTER_TAG_EN                                      (0x1<<10) // L2 filter outer tag matching enable.
50142     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE6_OUTER_TAG_EN_SHIFT                                10
50143 #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7                                                       0x5011e4UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50144     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_EN                                                (0x1<<0) // See definition for *l2filt_brb_dntfwd_rule0.
50145     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_EN_SHIFT                                          0
50146     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_EN                                           (0x1<<1) // See definition for *l2filt_brb_dntfwd_rule0.
50147     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_EN_SHIFT                                     1
50148     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_SEL                                          (0x7<<2) // See definition for *l2filt_brb_dntfwd_rule0.
50149     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ADDR_SEL_SHIFT                                    2
50150     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_EN                                      (0x1<<5) // See definition for *l2filt_brb_dntfwd_rule0.
50151     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_EN_SHIFT                                5
50152     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_SEL                                     (0x7<<6) // See definition for *l2filt_brb_dntfwd_rule0.
50153     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_ETHERTYPE_SEL_SHIFT                               6
50154     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_INNER_VLAN_EN                                     (0x1<<9) // L2 filter inner VLAN matching enable.
50155     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_INNER_VLAN_EN_SHIFT                               9
50156     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_OUTER_TAG_EN                                      (0x1<<10) // L2 filter outer tag matching enable.
50157     #define NIG_REG_RX_LLH_L2FILT_BRB_DNTFWD_RULE7_OUTER_TAG_EN_SHIFT                                10
50158 #define NIG_REG_BRB_GATE_DNTFWD_PORT                                                                 0x5011e8UL //Access:RW   DataWidth:0x1   Disable bit for forwarding packets to the host for this port.  No packet is forwarded to BRB when this bit is set.  Chips: BB_A0 BB_B0 K2
50159 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD                                                               0x5011ecUL //Access:RW   DataWidth:0x1   Disable bit for forwarding packets to the host.  No packet is forwarded to BRB when this bit is set.  Chips: BB_A0 BB_B0 K2
50160 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_CLSFAILED                                                     0x5011f0UL //Access:RW   DataWidth:0x1   Disable bit for forwarding packets that failed PF classification to the host.  No packet with classification failed status is forwarded to BRB when this bit is set in multifunction mode.  Chips: BB_A0 BB_B0 K2
50161 #define NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF                                                         0x5011f4UL //Access:RW   DataWidth:0x1   Per-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that have this bit set in multifunction mode.  This is a per-PF split register.  Chips: BB_A0 BB_B0 K2
50162 #define NIG_REG_STORM_ETHERTYPE0                                                                     0x5011f8UL //Access:RW   DataWidth:0x10  Ethertype for filtering packets to the STORM(s).  Chips: BB_A0 BB_B0 K2
50163 #define NIG_REG_STORM_ETHERTYPE1                                                                     0x5011fcUL //Access:RW   DataWidth:0x10  Ethertype for filtering packets to the STORM(s).  Chips: BB_A0 BB_B0 K2
50164 #define NIG_REG_STORM_ETHERTYPE2                                                                     0x501200UL //Access:RW   DataWidth:0x10  Ethertype for filtering packets to the STORM(s).  Chips: BB_A0 BB_B0 K2
50165 #define NIG_REG_STORM_ETHERTYPE3                                                                     0x501204UL //Access:RW   DataWidth:0x10  Ethertype for filtering packets to the STORM(s).  Chips: BB_A0 BB_B0 K2
50166 #define NIG_REG_RX_LLH_STORM_MASK                                                                    0x501208UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50167     #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE0                                                     (0x1<<0) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype0 to the STORM(s).
50168     #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE0_SHIFT                                               0
50169     #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE1                                                     (0x1<<1) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype1 to the STORM(s).
50170     #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE1_SHIFT                                               1
50171     #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE2                                                     (0x1<<2) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype2 to the STORM(s).
50172     #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE2_SHIFT                                               2
50173     #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE3                                                     (0x1<<3) // Mask bit for filtering packets with Ethertype matching *llh_storm_ethertype3 to the STORM(s).
50174     #define NIG_REG_RX_LLH_STORM_MASK_ETHERTYPE3_SHIFT                                               3
50175 #define NIG_REG_RX_LLH_DFIFO_EMPTY                                                                   0x501308UL //Access:R    DataWidth:0x1   LLH Data FIFO empty.  Chips: BB_A0 BB_B0 K2
50176 #define NIG_REG_RX_LLH_DFIFO_FULL                                                                    0x50130cUL //Access:R    DataWidth:0x1   LLH Data FIFO full.  Chips: BB_A0 BB_B0 K2
50177 #define NIG_REG_RX_LLH_HFIFO_EMPTY                                                                   0x501310UL //Access:R    DataWidth:0x1   LLH header FIFO empty.  Chips: BB_A0 BB_B0 K2
50178 #define NIG_REG_RX_LLH_HFIFO_FULL                                                                    0x501314UL //Access:R    DataWidth:0x1   LLH header FIFO full.  Chips: BB_A0 BB_B0 K2
50179 #define NIG_REG_RX_LLH_RFIFO_EMPTY                                                                   0x501318UL //Access:R    DataWidth:0x1   LLH result FIFO empty.  Chips: BB_A0 BB_B0 K2
50180 #define NIG_REG_RX_LLH_RFIFO_FULL                                                                    0x50131cUL //Access:R    DataWidth:0x1   LLH result FIFO full.  Chips: BB_A0 BB_B0 K2
50181 #define NIG_REG_STORM_STATUS                                                                         0x501400UL //Access:R    DataWidth:0x6   Status from the STORM interface logic.  Bit 0 - message FIFO empty. Bit 1 - descriptor FIFO empty. Bit 2 - message FIFO has more than 32 entries of data. Bit 3 - descriptor FIFO has more than 4 entries of data. Bit 4 - message FIFO is full. Bit 5 - descriptor FIFO is full.  Chips: BB_A0 BB_B0 K2
50182 #define NIG_REG_LB_MIN_CYC_THRESHOLD                                                                 0x501500UL //Access:RW   DataWidth:0x6   Minimum cycle threshold register for specifying the minimum number of cycles of ready-to-send data remaining below which ETS arbiter for the LB path should start selecting the next packet.  This value should cover the BTB access latency and arbitration time to provide back-to-back packets as needed to sustain the data rate, but should be as low as possilbe to minimize delay in responding to a flow control request.  Chips: BB_A0 BB_B0 K2
50183 #define NIG_REG_LB_PKT_HAS_FCS                                                                       0x501504UL //Access:RW   DataWidth:0x1   Packet has Ethernet FCS field.  Set this bit to indicate that the packet has the FCS field at the end of the packet.  Chips: BB_A0 BB_B0 K2
50184 #define NIG_REG_LB_ZERO_PAD_EN                                                                       0x501508UL //Access:RW   DataWidth:0x1   Zero-padding enable for LB packets.  Set this bit to enable the padding of short packets to 60B.  When this bit is clear, LB packets with less than 60B are dropped and not forwarded to the BRB.  Chips: BB_A0 BB_B0 K2
50185 #define NIG_REG_LB_BRBRATELIMIT_CTRL                                                                 0x50150cUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50186     #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN                                          (0x1<<0) // Enable bit for the BRB interface rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 40Gbps.
50187     #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT                                    0
50188     #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE                                   (0x3<<1) // Select between byte, cycle, and packet level of fairness for the BRB interface rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50189     #define NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT                             1
50190 #define NIG_REG_LB_BRBRATELIMIT_INC_PERIOD                                                           0x501510UL //Access:RW   DataWidth:0x20  Increment PERIOD for the BRB interface  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50191 #define NIG_REG_LB_BRBRATELIMIT_INC_VALUE                                                            0x501514UL //Access:RW   DataWidth:0x20  Increment VALUE for the BRB interface  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50192 #define NIG_REG_LB_BRBRATELIMIT_MAX_VALUE                                                            0x501518UL //Access:RW   DataWidth:0x20  Upper bound VALUE for the BRB interface  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50193 #define NIG_REG_LB_BRBRATELIMIT_IFG_SIZE                                                             0x50151cUL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the BRB interface rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50194 #define NIG_REG_LB_TCRATELIMIT_CTRL_0                                                                0x501520UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50195     #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0                                        (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
50196     #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT                                  0
50197     #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0                                 (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50198     #define NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT                           1
50199 #define NIG_REG_LB_TCRATELIMIT_CTRL_1                                                                0x501524UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50200     #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_EN_1                                        (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
50201     #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_EN_1_SHIFT                                  0
50202     #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_BASE_TYPE_1                                 (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50203     #define NIG_REG_LB_TCRATELIMIT_CTRL_1_LB_TCRATELIMIT_BASE_TYPE_1_SHIFT                           1
50204 #define NIG_REG_LB_TCRATELIMIT_CTRL_2                                                                0x501528UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50205     #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_EN_2                                        (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
50206     #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_EN_2_SHIFT                                  0
50207     #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_BASE_TYPE_2                                 (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50208     #define NIG_REG_LB_TCRATELIMIT_CTRL_2_LB_TCRATELIMIT_BASE_TYPE_2_SHIFT                           1
50209 #define NIG_REG_LB_TCRATELIMIT_CTRL_3                                                                0x50152cUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50210     #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_EN_3                                        (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
50211     #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_EN_3_SHIFT                                  0
50212     #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_BASE_TYPE_3                                 (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50213     #define NIG_REG_LB_TCRATELIMIT_CTRL_3_LB_TCRATELIMIT_BASE_TYPE_3_SHIFT                           1
50214 #define NIG_REG_LB_TCRATELIMIT_CTRL_4                                                                0x501530UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50215     #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_EN_4                                        (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
50216     #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_EN_4_SHIFT                                  0
50217     #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_BASE_TYPE_4                                 (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50218     #define NIG_REG_LB_TCRATELIMIT_CTRL_4_LB_TCRATELIMIT_BASE_TYPE_4_SHIFT                           1
50219 #define NIG_REG_LB_TCRATELIMIT_CTRL_5                                                                0x501534UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50220     #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_EN_5                                        (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
50221     #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_EN_5_SHIFT                                  0
50222     #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_BASE_TYPE_5                                 (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50223     #define NIG_REG_LB_TCRATELIMIT_CTRL_5_LB_TCRATELIMIT_BASE_TYPE_5_SHIFT                           1
50224 #define NIG_REG_LB_TCRATELIMIT_CTRL_6                                                                0x501538UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50225     #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_EN_6                                        (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
50226     #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_EN_6_SHIFT                                  0
50227     #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_BASE_TYPE_6                                 (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50228     #define NIG_REG_LB_TCRATELIMIT_CTRL_6_LB_TCRATELIMIT_BASE_TYPE_6_SHIFT                           1
50229 #define NIG_REG_LB_TCRATELIMIT_CTRL_7                                                                0x50153cUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50230     #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_EN_7                                        (0x1<<0) // Enable bit for the per-TC rate limiter to be used in pacing LB traffic.  Default to enabled rate limiter for 20Gbps.
50231     #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_EN_7_SHIFT                                  0
50232     #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_BASE_TYPE_7                                 (0x3<<1) // Select between byte, cycle, and packet level of fairness for the per-TC rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50233     #define NIG_REG_LB_TCRATELIMIT_CTRL_7_LB_TCRATELIMIT_BASE_TYPE_7_SHIFT                           1
50234 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0                                                          0x501540UL //Access:RW   DataWidth:0x20  Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50235 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_1                                                          0x501544UL //Access:RW   DataWidth:0x20  Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50236 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_2                                                          0x501548UL //Access:RW   DataWidth:0x20  Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50237 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_3                                                          0x50154cUL //Access:RW   DataWidth:0x20  Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50238 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_4                                                          0x501550UL //Access:RW   DataWidth:0x20  Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50239 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_5                                                          0x501554UL //Access:RW   DataWidth:0x20  Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50240 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_6                                                          0x501558UL //Access:RW   DataWidth:0x20  Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50241 #define NIG_REG_LB_TCRATELIMIT_INC_PERIOD_7                                                          0x50155cUL //Access:RW   DataWidth:0x20  Increment PERIOD for the per-TC  rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50242 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_0                                                           0x501560UL //Access:RW   DataWidth:0x20  Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50243 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_1                                                           0x501564UL //Access:RW   DataWidth:0x20  Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50244 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_2                                                           0x501568UL //Access:RW   DataWidth:0x20  Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50245 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_3                                                           0x50156cUL //Access:RW   DataWidth:0x20  Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50246 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_4                                                           0x501570UL //Access:RW   DataWidth:0x20  Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50247 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_5                                                           0x501574UL //Access:RW   DataWidth:0x20  Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50248 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_6                                                           0x501578UL //Access:RW   DataWidth:0x20  Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50249 #define NIG_REG_LB_TCRATELIMIT_INC_VALUE_7                                                           0x50157cUL //Access:RW   DataWidth:0x20  Increment VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50250 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0                                                           0x501580UL //Access:RW   DataWidth:0x20  Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50251 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_1                                                           0x501584UL //Access:RW   DataWidth:0x20  Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50252 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_2                                                           0x501588UL //Access:RW   DataWidth:0x20  Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50253 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_3                                                           0x50158cUL //Access:RW   DataWidth:0x20  Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50254 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_4                                                           0x501590UL //Access:RW   DataWidth:0x20  Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50255 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_5                                                           0x501594UL //Access:RW   DataWidth:0x20  Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50256 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_6                                                           0x501598UL //Access:RW   DataWidth:0x20  Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50257 #define NIG_REG_LB_TCRATELIMIT_MAX_VALUE_7                                                           0x50159cUL //Access:RW   DataWidth:0x20  Upper bound VALUE for the per-TC  rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50258 #define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_0                                                            0x5015a0UL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50259 #define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_1                                                            0x5015a4UL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50260 #define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_2                                                            0x5015a8UL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50261 #define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_3                                                            0x5015acUL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50262 #define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_4                                                            0x5015b0UL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50263 #define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_5                                                            0x5015b4UL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50264 #define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_6                                                            0x5015b8UL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50265 #define NIG_REG_LB_TCRATELIMIT_IFG_SIZE_7                                                            0x5015bcUL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50266 #define NIG_REG_LB_ARB_CLIENT_IS_STRICT                                                              0x5015c0UL //Access:RW   DataWidth:0xa   Specify whether the client competes directly in the strict priority arbiter.  The bits are mapped according to client ID  (client IDs are defined in *_arb_priority_client): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 traffic.  Default value is set to enable strict priorities for all clients.  Chips: BB_A0 BB_B0 K2
50267 #define NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ                                                         0x5015c4UL //Access:RW   DataWidth:0xa   Specify whether the client is subject to WFQ credit blocking.  The bits are mapped according to client ID (client IDs are defined in *_arb_priority_client): 0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 traffic.  Default value is 0 for not using WFQ credit blocking.  Chips: BB_A0 BB_B0 K2
50268 #define NIG_REG_LB_ARB_NUM_STRICT_ARB_SLOTS                                                          0x5015c8UL //Access:RW   DataWidth:0xc   Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation.  A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter.  Chips: BB_A0 BB_B0 K2
50269 #define NIG_REG_LB_ARB_PRIORITY_CLIENT                                                               0x5015d0UL //Access:WB   DataWidth:0x28  Specify the client number to be assigned to each priority of the strict priority arbiter.  Priority 0 is the highest priority.  Bits [3:0] are for priority 0 client; bits [39:36] are for priority 9 client.  The clients are assigned the following IDs:  0-management; 1-TC0 traffic; 2-TC1 traffic; 3-TC2 traffic; 4-TC3 traffic; 5-TC4 traffic; 6-TC5 traffic; 7-TC6 traffic; 8-TC7 traffic; 9-TC8 traffic.  The reset value is set to 0x1234567890.  Chips: BB_A0 BB_B0 K2
50270 #define NIG_REG_LB_ARB_PRIORITY_CLIENT_SIZE                                                          2
50271 #define NIG_REG_LB_ARB_BURST_MODE                                                                    0x5015d8UL //Access:RW   DataWidth:0x2   Burst mode enables.  Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the next one.  Bit 0 is for the main round-robin arbiter.  Bit 1 is for the round-robin arbiter within the strict priority with anti-starvation feature.  Chips: BB_A0 BB_B0 K2
50272 #define NIG_REG_LB_ARB_IFG_SIZE                                                                      0x5015dcUL //Access:RW   DataWidth:0x8   Specify the number of bytes to be deducted from the client credit register at the time of grant in additional to the normal packet credit costs.  This may include the IPG and FCS field.  Chips: BB_A0 BB_B0 K2
50273 #define NIG_REG_LB_ARB_PSEUDO_RR_EN                                                                  0x5015e0UL //Access:RW   DataWidth:0x1   Enable bit for the pseudo-random arbitration mode.  Chips: BB_A0 BB_B0 K2
50274 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0                                                          0x5015e4UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 0 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50275 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1                                                          0x5015e8UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 1 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50276 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_2                                                          0x5015ecUL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 2 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50277 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_3                                                          0x5015f0UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 3 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50278 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_4                                                          0x5015f4UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 4 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50279 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_5                                                          0x5015f8UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 5 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50280 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_6                                                          0x5015fcUL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 6 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50281 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_7                                                          0x501600UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 7 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50282 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_8                                                          0x501604UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 8 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50283 #define NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_9                                                          0x501608UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 9 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50284 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_0                                                               0x50160cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 0 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50285 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_1                                                               0x501610UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 1 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50286 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_2                                                               0x501614UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 2 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50287 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_3                                                               0x501618UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 3 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50288 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_4                                                               0x50161cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 4 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50289 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_5                                                               0x501620UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 5 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50290 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_6                                                               0x501624UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 6 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50291 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_7                                                               0x501628UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 7 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50292 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_8                                                               0x50162cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 8 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50293 #define NIG_REG_LB_ARB_CREDIT_WEIGHT_9                                                               0x501630UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 9 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50294 #define NIG_REG_LB_ARB_CURRENT_CREDIT_0                                                              0x501634UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 0.  Chips: BB_A0 BB_B0 K2
50295 #define NIG_REG_LB_ARB_CURRENT_CREDIT_1                                                              0x501638UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 1.  Chips: BB_A0 BB_B0 K2
50296 #define NIG_REG_LB_ARB_CURRENT_CREDIT_2                                                              0x50163cUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 2.  Chips: BB_A0 BB_B0 K2
50297 #define NIG_REG_LB_ARB_CURRENT_CREDIT_3                                                              0x501640UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 3.  Chips: BB_A0 BB_B0 K2
50298 #define NIG_REG_LB_ARB_CURRENT_CREDIT_4                                                              0x501644UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 4.  Chips: BB_A0 BB_B0 K2
50299 #define NIG_REG_LB_ARB_CURRENT_CREDIT_5                                                              0x501648UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 5.  Chips: BB_A0 BB_B0 K2
50300 #define NIG_REG_LB_ARB_CURRENT_CREDIT_6                                                              0x50164cUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 6.  Chips: BB_A0 BB_B0 K2
50301 #define NIG_REG_LB_ARB_CURRENT_CREDIT_7                                                              0x501650UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 7.  Chips: BB_A0 BB_B0 K2
50302 #define NIG_REG_LB_ARB_CURRENT_CREDIT_8                                                              0x501654UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 8.  Chips: BB_A0 BB_B0 K2
50303 #define NIG_REG_LB_ARB_CURRENT_CREDIT_9                                                              0x501658UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in LB arbiter credit register 9.  Chips: BB_A0 BB_B0 K2
50304 #define NIG_REG_LB_LLH_BRB_GATE_DNTFWD                                                               0x50165cUL //Access:RW   DataWidth:0x1   Disable bit for forwarding packets to the host.  No packet is forwarded to BRB when this bit is set.  Chips: BB_A0 BB_B0 K2
50305 #define NIG_REG_LB_LLH_BRB_GATE_DNTFWD_CLSFAILED                                                     0x501660UL //Access:RW   DataWidth:0x1   Disable bit for forwarding packets that failed PF classification to the host.  No packet with classification failed status is forwarded to BRB when this bit is set in multifunction mode.  Chips: BB_A0 BB_B0 K2
50306 #define NIG_REG_LB_LLH_BRB_GATE_DNTFWD_PERPF                                                         0x501664UL //Access:RW   DataWidth:0x1   Per-PF disable bit for forwarding packets to the host. Packets are not forwarded to BRB for PFs that have this bit set in multifunction mode.  This is a per-PF split register.  Chips: BB_A0 BB_B0 K2
50307 #define NIG_REG_LB_BTB_FIFO_ALM_FULL_THR                                                             0x501764UL //Access:RW   DataWidth:0x5   Almost full threshold for LB BTB FIFO.  Chips: BB_A0 BB_B0 K2
50308 #define NIG_REG_LB_GNT_FIFO_ALM_FULL_THR                                                             0x501768UL //Access:RW   DataWidth:0x4   Almost full threshold for LB GNT FIFO.  Chips: BB_A0 BB_B0 K2
50309 #define NIG_REG_LB_BTB_FIFO_EMPTY                                                                    0x50176cUL //Access:R    DataWidth:0x1   LB BTB FIFO empty status.  Chips: BB_A0 BB_B0 K2
50310 #define NIG_REG_LB_BTB_FIFO_FULL                                                                     0x501770UL //Access:R    DataWidth:0x1   LB BTB FIFO full status.  Chips: BB_A0 BB_B0 K2
50311 #define NIG_REG_LB_LLH_DFIFO_ALM_FULL_THR                                                            0x501774UL //Access:RW   DataWidth:0x6   LLH Data FIFO almost full threshold.  Chips: BB_A0 BB_B0 K2
50312 #define NIG_REG_LB_LLH_HFIFO_ALM_FULL_THR                                                            0x501778UL //Access:RW   DataWidth:0x5   LLH header FIFO almost full threshold.  Chips: BB_A0 BB_B0 K2
50313 #define NIG_REG_LB_LLH_RFIFO_ALM_FULL_THR                                                            0x50177cUL //Access:RW   DataWidth:0x4   LLH result FIFO almost full threshold.  Chips: BB_A0 BB_B0 K2
50314 #define NIG_REG_LB_LLH_DFIFO_EMPTY                                                                   0x501780UL //Access:R    DataWidth:0x1   LLH Data FIFO empty.  Chips: BB_A0 BB_B0 K2
50315 #define NIG_REG_LB_LLH_DFIFO_ALM_FULL                                                                0x501784UL //Access:R    DataWidth:0x1   LLH Data FIFO almost full.  Chips: BB_A0 BB_B0 K2
50316 #define NIG_REG_LB_LLH_DFIFO_FULL                                                                    0x501788UL //Access:R    DataWidth:0x1   LLH Data FIFO full.  Chips: BB_A0 BB_B0 K2
50317 #define NIG_REG_LB_LLH_HFIFO_EMPTY                                                                   0x50178cUL //Access:R    DataWidth:0x1   LLH header FIFO empty.  Chips: BB_A0 BB_B0 K2
50318 #define NIG_REG_LB_LLH_HFIFO_ALM_FULL                                                                0x501790UL //Access:R    DataWidth:0x1   LLH header FIFO almost full.  Chips: BB_A0 BB_B0 K2
50319 #define NIG_REG_LB_LLH_HFIFO_FULL                                                                    0x501794UL //Access:R    DataWidth:0x1   LLH header FIFO full.  Chips: BB_A0 BB_B0 K2
50320 #define NIG_REG_LB_LLH_RFIFO_EMPTY                                                                   0x501798UL //Access:R    DataWidth:0x1   LLH result FIFO empty.  Chips: BB_A0 BB_B0 K2
50321 #define NIG_REG_LB_LLH_RFIFO_ALM_FULL                                                                0x50179cUL //Access:R    DataWidth:0x1   LLH result FIFO almost full.  Chips: BB_A0 BB_B0 K2
50322 #define NIG_REG_LB_LLH_RFIFO_FULL                                                                    0x501800UL //Access:R    DataWidth:0x1   LLH result FIFO full.  Chips: BB_A0 BB_B0 K2
50323 #define NIG_REG_RX_PTP_EN                                                                            0x501900UL //Access:RW   DataWidth:0x3   Enable for TimeSync feature.  Bit 0 enables TimeSync on RX side.  Bit 1 enables V1 frame format in timesync event detection on RX side.  Bit 2 enables V2 frame format in timesync event detection on RX side.  Note that for HW to detect PTP packet and extract data from the packet, at least one of the version bits of that traffic direction has to be enabled.  Chips: BB_A0 BB_B0 K2
50324 #define NIG_REG_TX_PTP_EN                                                                            0x501904UL //Access:RW   DataWidth:0x3   Enable for TimeSync feature.  Bit 0 enables TimeSync on TX side.  Bit 1 enables V1 frame format in timesync event detection on TX side.  Bit 2 enables V2 frame format in timesync event detection on TX side.  Note that for HW to detect PTP packet and extract data from the packet, at least one of the version bits of that traffic direction has to be enabled.  Chips: BB_A0 BB_B0 K2
50325 #define NIG_REG_LLH_PTP_TO_HOST                                                                      0x501908UL //Access:RW   DataWidth:0x1   Set to 1 to enable PTP packets to be forwarded to the host.  Chips: BB_A0 BB_B0 K2
50326 #define NIG_REG_LLH_PTP_TO_MCP                                                                       0x50190cUL //Access:RW   DataWidth:0x1   Set to 1 to enable PTP packets to be forwarded to MCP.  Chips: BB_A0 BB_B0 K2
50327 #define NIG_REG_PTP_SW_TXTSEN                                                                        0x501910UL //Access:RW   DataWidth:0x1   Enable for SW-specified packet timestamp mode.  NIG will capture the timestamp value of the packet that SW indicated through PBF interface for host traffic or through the p*_tx_mng_timestamp_pkt bit for TX management packet.  Note that the tx_ptp_en[0] bit has to be set to enable TimeSync on TX side for this mode to work.  NIG will extract and capture the sequence ID if one of the version bits is enabled.  Chips: BB_A0 BB_B0 K2
50328 #define NIG_REG_LLH_PTP_ETHERTYPE_1                                                                  0x501914UL //Access:RW   DataWidth:0x10  MAC Ethertype 1 for PTP packet detection.  Ethertype 0 is fixed at 0x88F7.  This register defaults to 0x88f7.  Chips: BB_A0 BB_B0 K2
50329 #define NIG_REG_LLH_PTP_MAC_DA_2_LSB                                                                 0x501918UL //Access:RW   DataWidth:0x20  MAC destination address 2 for PTP packet detection.  This register holds the lower 4 bytes of the address.  MAC destination address 0 is fixed at 0x011B_1900_0000.  MAC destination address 1 is fixed at 0x0180_C200_000E.  This register defaults to 0x011B_1900_0000.  Chips: BB_A0 BB_B0 K2
50330 #define NIG_REG_LLH_PTP_MAC_DA_2_MSB                                                                 0x50191cUL //Access:RW   DataWidth:0x10  MAC destination address 2 for PTP packet detection.  This register holds the lower 4 bytes of the address.  MAC destination address 0 is fixed at 0x011B_1900_0000.  MAC destination address 1 is fixed at 0x0180_C200_000E.  This register defaults to 0x011B_1900_0000.  Chips: BB_A0 BB_B0 K2
50331 #define NIG_REG_LLH_PTP_PARAM_MASK                                                                   0x501920UL //Access:RW   DataWidth:0xb   Mask register for the various parameters used in determining PTP packet presence.  Set each bit to 1 to mask out the particular parameter.  0-IPv4 DA 0 of 224.0.1.129.   1-IPv4 DA 1 of 224.0.0.107.   2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181.   3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B.   4-UDP destination port 0 of 319. 5-UDP destination port 1 of 320.  6-MAC Ethertype 0 of 0x88F7.   7-configurable MAC Ethertype 1.   8-MAC DA 0 of 0x01-1B-19-00-00-00.   9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable MAC DA 2.  The reset default is set to mask out all parameters.  Chips: BB_A0 BB_B0 K2
50332 #define NIG_REG_LLH_PTP_RULE_MASK                                                                    0x501924UL //Access:RW   DataWidth:0xe   Mask regiser for the rules used in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .   1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} .  3-{IPv4 DA 1; UDP DP 1} . 4-{IPv6 DA 0; UDP DP 0} .  5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} .  7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} .  9-{MAC DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} .  11-{MAC DA 1; Ethertype 1} . 12-{MAC DA 2; Ethertype 0} .  13-{MAC DA 2; Ethertype 1} . The reset default is to mask out all of the rules.  Note that rules 0-3 are for IPv4 packets only and require that the packet is IPv4 for the rules to match.  Note that rules 4-7 are for IPv6 packets only and require that the packet is IPv6 for the rules to match.  Chips: BB_A0 BB_B0 K2
50333 #define NIG_REG_TX_LLH_PTP_PARAM_MASK                                                                0x501928UL //Access:RW   DataWidth:0xb   Mask register for the various parameters used in determining PTP packet presence.  Set each bit to 1 to mask out the particular parameter.  0-IPv4 DA 0 of 224.0.1.129.   1-IPv4 DA 1 of 224.0.0.107.   2-IPv6 DA 0 of 0xFF0*:0:0:0:0:0:0:181.   3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B.   4-UDP destination port 0 of 319. 5-UDP destination port 1 of 320.  6-MAC Ethertype 0 of 0x88F7.   7-configurable MAC Ethertype 1.   8-MAC DA 0 of 0x01-1B-19-00-00-00.   9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable MAC DA 2.  The reset default is set to mask out all parameters.  Chips: BB_A0 BB_B0 K2
50334 #define NIG_REG_TX_LLH_PTP_RULE_MASK                                                                 0x50192cUL //Access:RW   DataWidth:0xe   Mask regiser for the rules used in detecting PTP packets. Set each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .   1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} .  3-{IPv4 DA 1; UDP DP 1} . 4-{IPv6 DA 0; UDP DP 0} .  5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1; UDP DP 0} .  7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} .  9-{MAC DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} .  11-{MAC DA 1; Ethertype 1} . 12-{MAC DA 2; Ethertype 0} .  13-{MAC DA 2; Ethertype 1} . The reset default is to mask out all of the rules.  Chips: BB_A0 BB_B0 K2
50335 #define NIG_REG_LLH_PTP_HOST_BUF_SEQID                                                               0x501930UL //Access:RW   DataWidth:0x11  Packet TimeSync information that is buffered in 1-deep FIFOs for the host.  Bits [15:0] return the sequence ID of the packet.  Bit 16 indicates the validity of the data in the buffer.  Writing a 1 to bit 16 will clear the buffer.  Chips: BB_A0 BB_B0 K2
50336 #define NIG_REG_LLH_PTP_HOST_BUF_TS_LSB                                                              0x501934UL //Access:R    DataWidth:0x20  Packet TimeSync information that is buffered in 1-deep FIFOs for the host.  This location returns the lower 32 bits of timestamp value.  Chips: BB_A0 BB_B0 K2
50337 #define NIG_REG_LLH_PTP_HOST_BUF_TS_MSB                                                              0x501938UL //Access:R    DataWidth:0x20  Packet TimeSync information that is buffered in 1-deep FIFOs for the host.  This location returns the upper 32 bits of timestamp value.  Chips: BB_A0 BB_B0 K2
50338 #define NIG_REG_LLH_PTP_MCP_BUF_SEQID                                                                0x50193cUL //Access:RW   DataWidth:0x11  Packet TimeSync information that is buffered in 1-deep FIFOs for MCP.  Bits [15:0] return the sequence ID of the packet.  Bit 16 indicates the validity of the data in the buffer.  Writing a 1 to bit 16 will clear the buffer.  Chips: BB_A0 BB_B0 K2
50339 #define NIG_REG_LLH_PTP_MCP_BUF_TS_LSB                                                               0x501940UL //Access:R    DataWidth:0x20  Packet TimeSync information that is buffered in 1-deep FIFOs for MCP.  This location returns the lower 32 bits of timestamp value.  Chips: BB_A0 BB_B0 K2
50340 #define NIG_REG_LLH_PTP_MCP_BUF_TS_MSB                                                               0x501944UL //Access:R    DataWidth:0x20  Packet TimeSync information that is buffered in 1-deep FIFOs for MCP.  This location returns the upper 32 bits of timestamp value.  Chips: BB_A0 BB_B0 K2
50341 #define NIG_REG_TX_LLH_PTP_BUF_SEQID                                                                 0x501948UL //Access:RW   DataWidth:0x13  Packet TimeSync information that is buffered in 1-deep FIFOs for TX side.  Bits [15:0] reflect the sequence ID of the packet.  Bit 16 indicates the validity of the data in the buffer.  Bit 17 indicates that the sequence ID is valid and it is waiting for the TX timestamp value.  Bit 18 indicates whether the timestamp is from a SW request (value of 1) or HW request (value of 0).  Writing a 1 to bit 16 will clear the buffer.  Chips: BB_A0 BB_B0 K2
50342 #define NIG_REG_TX_LLH_PTP_BUF_TS_LSB                                                                0x50194cUL //Access:R    DataWidth:0x20  Packet TimeSync information that is buffered in 1-deep FIFO for the TX path.  This location returns the lower 32 bits of timestamp value.  Chips: BB_A0 BB_B0 K2
50343 #define NIG_REG_TX_LLH_PTP_BUF_TS_MSB                                                                0x501950UL //Access:R    DataWidth:0x20  Packet TimeSync information that is buffered in 1-deep FIFO for the TX path.  This location returns the upper 32 bits of timestamp value.  Chips: BB_A0 BB_B0 K2
50344 #define NIG_REG_RX_PTP_TS_MSB_ERR                                                                    0x501954UL //Access:RW   DataWidth:0x6   Error detected in adjustment of the upper 32-bit time for the 64-bit timestamp value.  Error occurs when bits [31:30] of the MAC timestamp value and the current free-running time are different by 2.  Bits 1:0 reflects MAC timestamp value 31:30.  Bits 3:2 reflects current time value 31:30.  Bit 4 indicates that no adjustment is made to the upper 32-bit time from the current time.  Bit 5 indicates that the upper 32-bit time is the decremented value from the current time.  The error status is latched until cleared by writing a '1' to bit 0.  Chips: BB_A0 BB_B0 K2
50345 #define NIG_REG_TX_PTP_TS_MSB_ERR                                                                    0x501958UL //Access:RW   DataWidth:0x6   Error detected in adjustment of the upper 32-bit time for the 64-bit timestamp value.  Error occurs when bits [31:30] of the MAC timestamp value and the current free-running time are different by 2.  Bits 1:0 reflects MAC timestamp value 31:30.  Bits 3:2 reflects current time value 31:30.  Bit 4 indicates that no adjustment is made to the upper 32-bit time from the current time.  Bit 5 indicates that the upper 32-bit time is the decremented value from the current time.  The error status is latched until cleared by writing a '1' to bit 0.  Chips: BB_A0 BB_B0 K2
50346 #define NIG_REG_LLH_MULTI_FUNCTION_MODE                                                              0x50195cUL //Access:RW   DataWidth:0x1   Multifunction mode enable.  Set this bit to perform PF classification before sending the packet to the BRB and performing WOL detection.  In single function mode, the PFID for port 0 is based on the translation table entry 0 of port 0, the PFID for port 1 is based on the translation table entry 1 of port 1, the PFID for port 2 is based on the translation table entry 2 of port 2, and the PFID for port 3 is based on the translation table entry 3 of port 3. If reset default values are used, then PFID is the same as port ID.  Chips: BB_A0 BB_B0 K2
50347 #define NIG_REG_LLH_CLS_TYPE                                                                         0x501960UL //Access:RW   DataWidth:0x2   Select the PF classification mode. 0: no classification.  1: classification based on tag/VLAN/MAC matching.  2: classification based on protocol. 3: dual-stage classification. When no classification is performed in multifunction mode, PPFID defaults to 0 and PFID is set as specified in entry 0 of the translation table.  Chips: BB_A0 BB_B0 K2
50348 #define NIG_REG_LLH_CLS_TYPE_DUALMODE                                                                0x501964UL //Access:RW   DataWidth:0x2   Set this register to select the resolution method for combining the results from the two stages in dual-stage classification mode; value of 0: AND the hit vectors; value of 1: OR the hit vectors; value of 2: take the protocol-based hit vector if there is a hit - otherwise take the other vector; value of 3: take the tag/vlan/mac hit vector if there is a hit - take the other hit vector otherwise.  Note that the hit vectors referenced here are the results from each stage, taken after muxing with the default vectors for that case that there is no match found.  Chips: BB_A0 BB_B0 K2
50349 #define NIG_REG_LLH_PROTOCOL_DEF_PF_VECTOR                                                           0x501968UL //Access:RW   DataWidth:0x8   Default per-port value to be used when protocol-based classification fails.  This is the per-port per-PF ID (PPFID) value represented in bit-mapped form.  Note that the classification fail flag is set only when the final classification vector is 0 for not having identified a PF.  Chips: BB_A0 BB_B0 K2
50350 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR                                                             0x50196cUL //Access:RW   DataWidth:0x8   Default per-port value to be used when outer-tag/inner VLAN/MAC  classification fails.  This is the per-port per-PF ID (PPFID) value represented in bit-mapped form. Note that the classification fail flag is set only when the final classification vector is 0 for not having identified a PF.  Chips: BB_A0 BB_B0 K2
50351 #define NIG_REG_LLH_PPFID2PFID_TBL_0                                                                 0x501970UL //Access:RW   DataWidth:0x4   Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7.  In single-function mode, program this register of port 0 to change the PFID for port 0. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.  Chips: BB_A0 BB_B0 K2
50352 #define NIG_REG_LLH_PPFID2PFID_TBL_1                                                                 0x501974UL //Access:RW   DataWidth:0x4   Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7.  In single-function mode, program this register of port 1 to change the PFID for port 1. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.  Chips: BB_A0 BB_B0 K2
50353 #define NIG_REG_LLH_PPFID2PFID_TBL_2                                                                 0x501978UL //Access:RW   DataWidth:0x4   Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7.  In single-function mode, program this register of port 2 to change the PFID for port 2. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.  Chips: BB_A0 BB_B0 K2
50354 #define NIG_REG_LLH_PPFID2PFID_TBL_3                                                                 0x50197cUL //Access:RW   DataWidth:0x4   Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7.  In single-function mode, program this register of port 3 to change the PFID for port 3. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.  Chips: BB_A0 BB_B0 K2
50355 #define NIG_REG_LLH_PPFID2PFID_TBL_4                                                                 0x501980UL //Access:RW   DataWidth:0x4   Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.  Chips: BB_A0 BB_B0 K2
50356 #define NIG_REG_LLH_PPFID2PFID_TBL_5                                                                 0x501984UL //Access:RW   DataWidth:0x4   Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.  Chips: BB_A0 BB_B0 K2
50357 #define NIG_REG_LLH_PPFID2PFID_TBL_6                                                                 0x501988UL //Access:RW   DataWidth:0x4   Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.  Chips: BB_A0 BB_B0 K2
50358 #define NIG_REG_LLH_PPFID2PFID_TBL_7                                                                 0x50198cUL //Access:RW   DataWidth:0x4   Table for translating 3-bit PPFID to 4-bit global PFID. Each port supports 8 functions.  These 8 functions are locally referred to as PPF for port PF.  These functions are identified using PPFID.  The PPFID is mapped to the global PFID based on the information in this table before sending out of the NIG block.  Register *_0 holds the PFID value for the local function 0.  Register *_7 holds the PFID value for the local function 7. Valid PFID values for BB are 0-7.  Valid PFID values for K2 are 0-15.  Chips: BB_A0 BB_B0 K2
50359 #define NIG_REG_OUTER_TAG_VALUE_LIST0                                                                0x501990UL //Access:RW   DataWidth:0x18  Outer tag value list.  This register is used to specify the index of the 64-bit field immediately following the Ethertype to be used for each of the outer tag value bit. The first bit following the Ethertype is referred to as bit 63.  The 64th bit following the Ethertype is referred to as bit 0.  The outer tag value is 16-bit wide.  This register specify the indexes for bits 3:0 of the outer tag value[15:0].  Bits [23:18] of this register specify the index for bit 3.  Bits [5:0] of this register specify the index for bit 0.  These registers default to select the 16 bits starting from the 1st bit following the tag Ethertype (bits [63:48] of the 64-bit field).  Chips: BB_A0 BB_B0 K2
50360 #define NIG_REG_OUTER_TAG_VALUE_LIST1                                                                0x501994UL //Access:RW   DataWidth:0x18  Outer tag value list.  See the description for *outer_tag_value_list0.  This register specify the indexes for bits 7:4 of the outer tag value[15:0].  Bits [23:18] of this register specify the index for bit 7.  Bits [5:0] of this register specify the index for bit 4.  Chips: BB_A0 BB_B0 K2
50361 #define NIG_REG_OUTER_TAG_VALUE_LIST2                                                                0x501998UL //Access:RW   DataWidth:0x18  Outer tag value list.  See the description for *outer_tag_value_list0.  This register specify the indexes for bits 11:8 of the outer tag value[15:0].  Bits [23:18] of this register specify the index for bit 11.  Bits [5:0] of this register specify the index for bit 8.  Chips: BB_A0 BB_B0 K2
50362 #define NIG_REG_OUTER_TAG_VALUE_LIST3                                                                0x50199cUL //Access:RW   DataWidth:0x18  Outer tag value list.  See the description for *outer_tag_value_list0.  This register specify the indexes for bits 15:12 of the outer tag value[15:0].  Bits [23:18] of this register specify the index for bit 15.  Bits [5:0] of this register specify the index for bit 12.  Chips: BB_A0 BB_B0 K2
50363 #define NIG_REG_OUTER_TAG_VALUE_MASK                                                                 0x5019a0UL //Access:RW   DataWidth:0x10  Outer tag value mask.  Set a bit to 0 to mask out the corresponding bit of the outer tag value.  This register defaults to mask out the upper 4 bits of the tag value.  Chips: BB_A0 BB_B0 K2
50364 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE                                                             0x5019a4UL //Access:RW   DataWidth:0x3   This is a per-port per-PF register.  This register selects the classification type for the tag/VLAN/MAC mode.  Bits 1:0 are decoded as follow:  0 - outer-tag/inner VLAN; 1 - MAC address; 2 - both outer-tag/inner VLAN and MAC address; 3 - either outer-tag/inner VLAN or MAC address. Bit 2 specifies whether the classification is based on Inner VLAN (set to 1) or outer-tag (set to 0).  Chips: BB_A0 BB_B0 K2
50365 #define NIG_REG_LLH_FUNC_TAG_EN                                                                      0x5019b0UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  Per-function outer tag/inner VLAN enable for PF classification.  There are 4 of this register per port per function.  Chips: BB_A0 BB_B0 K2
50366 #define NIG_REG_LLH_FUNC_TAG_EN_SIZE                                                                 4
50367 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL                                                                 0x5019c0UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  Per-function select bit for choosing between the tunnel and encapsulated header from which to take the inner VLAN for comparison with that in llh_func_tag_value for PF classification; 0 selects the outer/tunnel header.  There are 4 of this register per port per function.  Chips: BB_A0 BB_B0 K2
50368 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_SIZE                                                            4
50369 #define NIG_REG_LLH_FUNC_TAG_VALUE                                                                   0x5019d0UL //Access:RW   DataWidth:0x10  This is a per-port per-PF register.  Per-function outer tag/inner VLAN configuration for PF classification.  These bits specify the value for comparison.  There are 4 of this register per port per function.  Only bits 11:0 are used to specify the inner VLAN ID. Configuration of an inner VLAN ID of 0 also enables a match for the function when there is no inner VLAN.  Chips: BB_A0 BB_B0 K2
50370 #define NIG_REG_LLH_FUNC_TAG_VALUE_SIZE                                                              4
50371 #define NIG_REG_LLH_FUNC_NO_TAG                                                                      0x5019e0UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  Per-function no outer tag/inner VLAN configuration for PF classification.  Set this bit to enable a match for the function when there is no outer tag/inner VLAN.  Chips: BB_A0 BB_B0 K2
50372 #define NIG_REG_LLH_FUNC_FILTER_VALUE                                                                0x501a00UL //Access:WB   DataWidth:0x30  This is a per-port per-PF register.  Per-function MAC addresses to be matched with for MAC-address-based classification.  This register is also used for protocol-based classification; bits [47:32] are for Ethertype; bits [31:16] are for the source port; and bits [15:0] are for the destination port.  There are 16 of this register per port per function.  Chips: BB_A0 BB_B0 K2
50373 #define NIG_REG_LLH_FUNC_FILTER_VALUE_SIZE                                                           32
50374 #define NIG_REG_LLH_FUNC_FILTER_EN                                                                   0x501a80UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  Per-function filter enable for PF classification.  There are 16 of this register per port per function.  Chips: BB_A0 BB_B0 K2
50375 #define NIG_REG_LLH_FUNC_FILTER_EN_SIZE                                                              16
50376 #define NIG_REG_LLH_FUNC_FILTER_MODE                                                                 0x501ac0UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  Per-function mode select bit to indicate whether the filter is to be used for MAC-addresss based classification or protocol-based classification.  Set this bit to 1 to select protocol-based classification.  There are 16 of this register per port per function.  Chips: BB_A0 BB_B0 K2
50377 #define NIG_REG_LLH_FUNC_FILTER_MODE_SIZE                                                            16
50378 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE                                                        0x501b00UL //Access:RW   DataWidth:0x7   This is a per-port per-PF register.  Per-function select bits for the different protocol types to be evaluated in protocol-based classification mode: bit 0: compare the Ethertype; bit 1: compare the TCP source port; bit 2: compare the TCP destination port; bit 3: compare the TCP source and destination ports. bit 4: compare the UDP source port; bit 5: compare the UDP destination port; bit 6: compare the UDP source and destination ports. Set the bit to 1 to enable the comparison.  The results are logically OR'ed together, and thus, a match is found when one or more of the enabled types compare successfully. There are 16 of this register per port per function.  Chips: BB_A0 BB_B0 K2
50379 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_SIZE                                                   16
50380 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL                                                              0x501b40UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  Per-function select bit for choosing between the tunnel and encapsulated header from which to take the MAC address to be compared with that in llh_func_filter_value for PF classification; 0 selects the outer/tunnel header.  There are 16 of this register per port per function.  Chips: BB_A0 BB_B0 K2
50381 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_SIZE                                                         16
50382 #define NIG_REG_LLH_ENG_CLS_TYPE                                                                     0x501b80UL //Access:RW   DataWidth:0x1   Engine classification type.  0 selects connection-based classification.  1 selects the PF-based classification. This register is used only in the single-port with dual engine mode.  Chips: BB_A0 BB_B0 K2
50383 #define NIG_REG_LLH_ENG_CLS_TCP_4_TUPLE_SEARCH                                                       0x501b84UL //Access:RW   DataWidth:0x1   TCP 4-tuple search for TCP packets.  Set this bit to use the TCP 4-tuple (TCP source and destination port numbers and IP source and destination IP addresses) as the hash string. This register is used only in the single-port with dual engine mode.  Chips: BB_A0 BB_B0 K2
50384 #define NIG_REG_LLH_ENG_CLS_UDP_4_TUPLE_SEARCH                                                       0x501b88UL //Access:RW   DataWidth:0x1   UDP 4-tuple search for UDP packets.  Set this bit to use the UDP 4-tuple (UDP source and destination port numbers and IP source and destination IP addresses) as the hash string.  This register is used only in the single-port with dual engine mode.  Chips: BB_A0 BB_B0 K2
50385 #define NIG_REG_LLH_ENG_CLS_CRC8_INIT_VAL                                                            0x501b8cUL //Access:RW   DataWidth:0x8   Initial remainder value for the CRC8 function used to hash the data string in connection-based engine classification.  This register is used only in the single-port with dual engine mode.  Chips: BB_A0 BB_B0 K2
50386 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL                                                               0x501b90UL //Access:WB   DataWidth:0x40  64-entry Engine ID lookup table, with 1 bit per entry.  Set the bit to 1 to have packets associated with the index to be routed to engine 1.  Otherwise, the packet is routed to engine 0.  This register is used only in the single-port with dual engine mode.  Chips: BB_A0 BB_B0 K2
50387 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL_SIZE                                                          2
50388 #define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL                                                              0x501b98UL //Access:RW   DataWidth:0x5   RoCE destination QP bit select.  This configuration selects one of the 24-bit destination QP bits to be used as the engine ID.  Valid values are 0-23.  This register is used only in the single-port with dual engine mode.  Chips: BB_A0 BB_B0 K2
50389 #define NIG_REG_LLH_ENG_CLS_ENG_ID_PERPF                                                             0x501b9cUL //Access:RW   DataWidth:0x1   Per-global-PF engine ID to be used in PF-based engine classification.  Set the bit to 1 to have packets associated with the PF to be routed to engine 1.  Otherwise, the packet is routed to engine 0.  This register is used only in the single-port with dual engine mode.  Chips: BB_A0 BB_B0 K2
50390 #define NIG_REG_FLOWCTRL_MODE                                                                        0x501ba0UL //Access:RW   DataWidth:0x3   Flow control mode.  0 - disable; 1 - PFC; 2 - LLFC; 3 - PPP; 4 - PAUSE; 5-7 are invalid values.  Chips: BB_A0 BB_B0 K2
50391 #define NIG_REG_PKT_PRIORITY_TO_TC                                                                   0x501ba4UL //Access:RW   DataWidth:0x20  Eight 4-bit configurations for specifying which TC (0-15 for future expansion) each priorty is to be mapped to. Bits 3:0 specify the TC for priority 0.  Bits 31:28 specify the TC for priority 7.  Chips: BB_A0 BB_B0 K2
50392 #define NIG_REG_PKT_PRIORITY_TAG                                                                     0x501ba8UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50393     #define NIG_REG_PKT_PRIORITY_TAG_N_SEL                                                           (0x7<<0) // Select for the L2 tag to be used for extracting the packet priority information.  Valid values are 2-5 for selecting one of the L2 tags 2-5.  This field is evaluated only when the selected tag is the first tag in the packet. Set this field to 0 when not used.
50394     #define NIG_REG_PKT_PRIORITY_TAG_N_SEL_SHIFT                                                     0
50395     #define NIG_REG_PKT_PRIORITY_TAG_PKT_PRIORITY_OTAG_BITOFFSET                                     (0xf<<3) // Bit offset in the outer tag starting from which to extract the 3-bit packet priority information.  The first bit following the Ethertype field is referenced as bit 15.  Values of 0 and 1 are invalid.
50396     #define NIG_REG_PKT_PRIORITY_TAG_PKT_PRIORITY_OTAG_BITOFFSET_SHIFT                               3
50397     #define NIG_REG_PKT_PRIORITY_TAG_N_BITOFFSET                                                     (0xf<<7) // Bit offset in the selected tag starting from which to extract the 3-bit packet priority information.   The first bit following the Ethertype field is referenced as bit 15.  Values of 0 and 1 are invalid.
50398     #define NIG_REG_PKT_PRIORITY_TAG_N_BITOFFSET_SHIFT                                               7
50399 #define NIG_REG_FORCE_BRB_FULL                                                                       0x501bacUL //Access:RW   DataWidth:0x9   Force brb_nig_*_tc_full.  There is one bit per TC and the same configuration is applicable to both RX and LB interfaces to the BRB of the same port.  Set a bit to 1 to force 'full' condition.  This is meant to allow BRB configuration change during run time by truncating/discarding all traffic the same way as if BRB asserted the corresponding per-TC full signals.  This register may change during run time.  Packet truncation/discarding affects all packet types, including LB packets with LB-only header and LB packets with no-drop indication.  Chips: BB_A0 BB_B0 K2
50400 #define NIG_REG_FORCE_BRB_PAUSE                                                                      0x501bb0UL //Access:RW   DataWidth:0x9   Force 'pause' condition for traffic going to BRB.  There is one bit per TC and the same configuration is applicable to both RX and LB interfaces to the BRB of the same port.  Set a bit to 1 to force 'pause' condition.  This is meant to allow BRB configuration change during run time by pausing/dropping all traffic the same way as if BRB asserted the corresponding signals.  This register may change during run time.  Chips: BB_A0 BB_B0 K2
50401 #define NIG_REG_RX_TC_EN                                                                             0x501bb4UL //Access:RW   DataWidth:0x8   Per-TC flow control enable for received XOFF requests to pause transmit queues.  Set a bit to 1 to enable the corresponding TC.  A TC is in XON state when not enabled.  Chips: BB_A0 BB_B0 K2
50402 #define NIG_REG_TX_TC_EN                                                                             0x501bb8UL //Access:RW   DataWidth:0x8   Per-TC flow control enable for XOFF messages sent to the MAC.  Set a bit to 1 to enable a  TC.  A TC is in XON state when not enabled.  Chips: BB_A0 BB_B0 K2
50403 #define NIG_REG_LB_TC_EN                                                                             0x501bbcUL //Access:RW   DataWidth:0x9   Per-TC flow control enable for received XOFF requests to pause LB queues.  Set a bit to 1 to enable a TC.  A TC is in XON state when not enabled.  Chips: BB_A0 BB_B0 K2
50404 #define NIG_REG_LB_NO_DROP_EN                                                                        0x501bc0UL //Access:RW   DataWidth:0x1   Enable bit for the no-drop-hdr-ind field of the LB-only-header.  When set, the no-drop-hdr-ind bit of the TC has the same effect as the lb_tc_en configuration above.  Chips: BB_A0 BB_B0 K2
50405 #define NIG_REG_LB_NO_DROP_ON_FULL                                                                   0x501bc4UL //Access:RW   DataWidth:0x1   Enable the no-drop of LB packets with the no-drop-hdr-ind bit set due to per-TC full backpressure from the BRB.  Note that only the first lb_no_drop_hdr_size cycles of the packet are not dropped. If per-TC full condition exists after the lb_no_drop_hdr_size cycles, then a trunctation cycle of EOP+ERR is sent to the BRB.  Chips: BB_A0 BB_B0 K2
50406 #define NIG_REG_LB_NO_DROP_HDR_SIZE                                                                  0x501bc8UL //Access:RW   DataWidth:0x5   This field specifies the number of 256-bit cycles, starting from the SOP cycle, of the packet not to be dropped due to no_drop_on_full. If per-TC full condition exists after the lb_no_drop_hdr_size cycles, then a trunctation cycle of EOP+ERR is sent to the BRB.  Chips: BB_A0 BB_B0 K2
50407 #define NIG_REG_PRIORITY_FOR_TC_0                                                                    0x501bccUL //Access:RW   DataWidth:0x10  Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.  Chips: BB_A0 BB_B0 K2
50408 #define NIG_REG_PRIORITY_FOR_TC_1                                                                    0x501bd0UL //Access:RW   DataWidth:0x10  Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.  Chips: BB_A0 BB_B0 K2
50409 #define NIG_REG_PRIORITY_FOR_TC_2                                                                    0x501bd4UL //Access:RW   DataWidth:0x10  Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.  Chips: BB_A0 BB_B0 K2
50410 #define NIG_REG_PRIORITY_FOR_TC_3                                                                    0x501bd8UL //Access:RW   DataWidth:0x10  Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.  Chips: BB_A0 BB_B0 K2
50411 #define NIG_REG_PRIORITY_FOR_TC_4                                                                    0x501bdcUL //Access:RW   DataWidth:0x10  Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.  Chips: BB_A0 BB_B0 K2
50412 #define NIG_REG_PRIORITY_FOR_TC_5                                                                    0x501be0UL //Access:RW   DataWidth:0x10  Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.  Chips: BB_A0 BB_B0 K2
50413 #define NIG_REG_PRIORITY_FOR_TC_6                                                                    0x501be4UL //Access:RW   DataWidth:0x10  Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.  Chips: BB_A0 BB_B0 K2
50414 #define NIG_REG_PRIORITY_FOR_TC_7                                                                    0x501be8UL //Access:RW   DataWidth:0x10  Flow control priorities used for each TC.  This register is bit-mapped with one bit for each priority.  Chips: BB_A0 BB_B0 K2
50415 #define NIG_REG_RX_TC0_PRIORITY_MASK                                                                 0x501becUL //Access:RW   DataWidth:0x10  Bit-map indicating which received SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set, allowing multiple priorities to be mapped to one TC.  Chips: BB_A0 BB_B0 K2
50416 #define NIG_REG_RX_TC1_PRIORITY_MASK                                                                 0x501bf0UL //Access:RW   DataWidth:0x10  Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Chips: BB_A0 BB_B0 K2
50417 #define NIG_REG_RX_TC2_PRIORITY_MASK                                                                 0x501bf4UL //Access:RW   DataWidth:0x10  Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Chips: BB_A0 BB_B0 K2
50418 #define NIG_REG_RX_TC3_PRIORITY_MASK                                                                 0x501bf8UL //Access:RW   DataWidth:0x10  Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Chips: BB_A0 BB_B0 K2
50419 #define NIG_REG_RX_TC4_PRIORITY_MASK                                                                 0x501bfcUL //Access:RW   DataWidth:0x10  Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Note that in quad-port per engine mode, there are only TC0-3.  Chips: BB_A0 BB_B0 K2
50420 #define NIG_REG_RX_TC5_PRIORITY_MASK                                                                 0x501c00UL //Access:RW   DataWidth:0x10  Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Note that in quad-port per engine mode, there are only TC0-3.  Chips: BB_A0 BB_B0 K2
50421 #define NIG_REG_RX_TC6_PRIORITY_MASK                                                                 0x501c04UL //Access:RW   DataWidth:0x10  Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Note that in quad-port per engine mode, there are only TC0-3.  Chips: BB_A0 BB_B0 K2
50422 #define NIG_REG_RX_TC7_PRIORITY_MASK                                                                 0x501c08UL //Access:RW   DataWidth:0x10  Bit-map indicating which SAFC/PFC priorities to map to the TC.  A priority is mapped to the TC when the corresponding mask bit is 1.  More than one bit may be set; allowing multiple priorities to be mapped to one TC.  Note that in quad-port per engine mode, there are only TC0-3.  Chips: BB_A0 BB_B0 K2
50423 #define NIG_REG_TC_PAUSE_MAX_0                                                                       0x501c0cUL //Access:RW   DataWidth:0x20  Maximum number of cycles that a TC can be XOFFed/paused before an interrupt is asserted.  This is used for all TCs of the same port.  Chips: BB_A0 BB_B0 K2
50424 #define NIG_REG_TC_PAUSE_MAX_1                                                                       0x501c10UL //Access:RW   DataWidth:0x8   Maximum number of cycles that a TC can be XOFFed/paused before an interrupt is asserted.  This is used for all TCs of the same port.  Chips: BB_A0 BB_B0 K2
50425 #define NIG_REG_TX_PAUSE_MAX_0                                                                       0x501c14UL //Access:RW   DataWidth:0x20  Maximum number of cycles that the TX path is PAUSEd before an interrupt is asserted.  This is used for PAUSE only.  Chips: BB_A0 BB_B0 K2
50426 #define NIG_REG_TX_PAUSE_MAX_1                                                                       0x501c18UL //Access:RW   DataWidth:0x8   Maximum number of cycles that the TX path is PAUSEd before an interrupt is asserted.  This is used for PAUSE only.  Chips: BB_A0 BB_B0 K2
50427 #define NIG_REG_TX_DRAIN_EN                                                                          0x501c1cUL //Access:RW   DataWidth:0x1   Drain mode enable.  Set this bit to enable drain mode. Drain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion.  Chips: BB_A0 BB_B0 K2
50428 #define NIG_REG_TX_MCP_DRAIN_EN                                                                      0x501c20UL //Access:RW   DataWidth:0x1   Drain mode enable for TX MCP traffic.  Set this bit to enable drain mode.  Drain mode starts immediately upon assertion and stops at the next packet boundary upon de-assertion.  Note that TX MCP traffic may also be drained if it is based on a TC and the corresponding TC is enabled to drain.  Chips: BB_A0 BB_B0 K2
50429 #define NIG_REG_TX_TC_DRAIN_EN                                                                       0x501c24UL //Access:RW   DataWidth:0x8   Set these bits to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow.  Bit 7 is for TC7 flow.  When enabled -- draining of the corrresponding TC  starts immediately - packet data are dropped and not forwarded to the MAC.  When disabled--draining stops at the next packet boundary.  Chips: BB_A0 BB_B0 K2
50430 #define NIG_REG_LB_TC_DRAIN_EN                                                                       0x501c28UL //Access:RW   DataWidth:0x9   Set these bits to enable the drain mode for TC0 and TC7. Bit 0 is for TC0 flow.  Bit 8 is for TC8 flow.  When enabled -- draining of the corrresponding TC  starts immediately - packet data are dropped and not forwarded to the BRB.  When disabled--draining stops at the next packet boundary.  Chips: BB_A0 BB_B0 K2
50431 #define NIG_REG_LLFC_XOFF_TIMER_MAX                                                                  0x501c2cUL //Access:RW   DataWidth:0x16  Timeout value for LLFC XOFF timer in the TX direction for sending refresh LLFC messages to the MAC.  The value is in term of the number of core clock cycles.  The timer starts whenever an LLFC request is sent to the MAC with at least one priority in the XOFF state.  An update LLFC request is sent when the timer expires.  This value should be less than (LLFC XOFF TIME x 512) / (data rate in Gbps x core clock period in ns).  The default value is set for XOFF time of 0x8000, data rate of 10Gbps, and core clock of 375MHz, with 64 deducted from the calculated value.  Chips: BB_A0 BB_B0 K2
50432 #define NIG_REG_LLFC_TX_CYCLE_NUM                                                                    0x501c30UL //Access:RW   DataWidth:0xa   Number of cycles between 2 LLFC request to the MAC; The minimum value of this register must be 16. The value of this register must be bigger then [ LLFC_IMG register x (core frequency / MAC frequency)].  Chips: BB_A0 BB_B0 K2
50433 #define NIG_REG_PAUSE_STATUS_BRB                                                                     0x501c34UL //Access:R    DataWidth:0x8   TC pause status from BRB input for main RX traffic, per port.  Chips: BB_A0 BB_B0 K2
50434 #define NIG_REG_PAUSE_STATUS_BRB_LB                                                                  0x501c38UL //Access:R    DataWidth:0x9   TC pause status from BRB input for LB traffic, per port.  Chips: BB_A0 BB_B0 K2
50435 #define NIG_REG_PAUSE_STATUS_MSDM                                                                    0x501c3cUL //Access:R    DataWidth:0x8   TC pause status from MSDM input, per port.  This affects main and LB traffic going into RX pipe of the chip.  Chips: BB_A0 BB_B0 K2
50436 #define NIG_REG_PAUSE_STATUS_TSDM                                                                    0x501c40UL //Access:R    DataWidth:0x8   TC pause status from TSDM input, per port.  This affects main and LB traffic going into RX pipe of the chip.  Chips: BB_A0 BB_B0 K2
50437 #define NIG_REG_PAUSE_STATUS_USDM                                                                    0x501c44UL //Access:R    DataWidth:0x8   TC pause status from USDM input, per port.  This affects main and LB traffic going into RX pipe of the chip.  Chips: BB_A0 BB_B0 K2
50438 #define NIG_REG_PAUSE_PRIORITY_TO_MAC                                                                0x501c48UL //Access:R    DataWidth:0x10  Current value of PFC/LLFC priority or PAUSE signal sent to MAC/PXP, depending on the flow control mode.  Chips: BB_A0 BB_B0 K2
50439 #define NIG_REG_RX_FLOWCTRL_STATUS                                                                   0x501c4cUL //Access:R    DataWidth:0x10  Current latched flow control (PFC/LLFC) priorities received from the MAC, depending on the *flowctrl_mode.  Chips: BB_A0 BB_B0 K2
50440 #define NIG_REG_RX_FLOWCTRL_STATUS_CLEAR                                                             0x501c50UL //Access:RW   DataWidth:0x1   Set this bit to clear the current flow control (PFC and LLFC) latched status.  Chips: BB_A0 BB_B0 K2
50441 #define NIG_REG_PPP_ADDRESS                                                                          0x501c54UL //Access:RW   DataWidth:0x10  Address to be used in the header of the flow control message sent to PXP internal write interface.  This configuration should be static while flowctrl_mode is set to PPP.  Chips: BB_A0 BB_B0 K2
50442 #define NIG_REG_PPP_STORM_ID                                                                         0x501c58UL //Access:RW   DataWidth:0x4   STORM ID to be used for the Destination Client ID field for the header of the flow control message sent to PXP internal write interface.  This configuration should be static while flowctrl_mode is set to PPP.  Chips: BB_A0 BB_B0 K2
50443 #define NIG_REG_PPP_COMPPARAMS                                                                       0x501c5cUL //Access:RW   DataWidth:0x10  CompParams value for the header of the flow control message sent to PXP internal write interface. This configuration should be static while flowctrl_mode is set to PPP.  Chips: BB_A0 BB_B0 K2
50444 #define NIG_REG_PPP_TRIG                                                                             0x501c60UL //Access:RW   DataWidth:0x4   Trigger value to be used in the header of the flow control message sent to PXP internal write interface. This configuration should be static while flowctrl_mode is set to PPP.  Chips: BB_A0 BB_B0 K2
50445 #define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_0                                                        0x501c64UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50446 #define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_1                                                        0x501c68UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50447 #define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_2                                                        0x501c6cUL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50448 #define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_3                                                        0x501c70UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50449 #define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_4                                                        0x501c74UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50450 #define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_5                                                        0x501c78UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50451 #define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_6                                                        0x501c7cUL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50452 #define NIG_REG_STAT_RX_BRB_PACKET_PRIORITY_7                                                        0x501c80UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50453 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_0                                                         0x501ca0UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50454 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_0_SIZE                                                    2
50455 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_1                                                         0x501ca8UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50456 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_1_SIZE                                                    2
50457 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_2                                                         0x501cb0UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50458 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_2_SIZE                                                    2
50459 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_3                                                         0x501cb8UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50460 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_3_SIZE                                                    2
50461 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_4                                                         0x501cc0UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50462 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_4_SIZE                                                    2
50463 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_5                                                         0x501cc8UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50464 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_5_SIZE                                                    2
50465 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_6                                                         0x501cd0UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50466 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_6_SIZE                                                    2
50467 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_7                                                         0x501cd8UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50468 #define NIG_REG_STAT_RX_BRB_OCTET_PRIORITY_7_SIZE                                                    2
50469 #define NIG_REG_STAT_RX_NO_DEST                                                                      0x501ce0UL //Access:RC   DataWidth:0x20  Statistics for packets dropped due to minimum size, parsing errors, and filtering. Note that statistics for packets with 32B or less are in stat_*1cyc_pkt_drop.  Chips: BB_A0 BB_B0 K2
50470 #define NIG_REG_STAT_RX_1CYC_PKT_DROP                                                                0x501ce4UL //Access:RC   DataWidth:0x20  Statistics for the number of single-cycle packets dropped. This is an RF generated RC statistics register - reading this register clears the value to 0.  Chips: BB_A0 BB_B0 K2
50471 #define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_0                                                      0x501ce8UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50472 #define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_1                                                      0x501cecUL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50473 #define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_2                                                      0x501cf0UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50474 #define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_3                                                      0x501cf4UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50475 #define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_4                                                      0x501cf8UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50476 #define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_5                                                      0x501cfcUL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50477 #define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_6                                                      0x501d00UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50478 #define NIG_REG_STAT_RX_BRB_TRUNCATE_PRIORITY_7                                                      0x501d04UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50479 #define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_0                                                       0x501d08UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50480 #define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_1                                                       0x501d0cUL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50481 #define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_2                                                       0x501d10UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50482 #define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_3                                                       0x501d14UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50483 #define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_4                                                       0x501d18UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50484 #define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_5                                                       0x501d1cUL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50485 #define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_6                                                       0x501d20UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50486 #define NIG_REG_STAT_RX_BRB_DISCARD_PRIORITY_7                                                       0x501d24UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50487 #define NIG_REG_STAT_RX_STORM_PACKET_SENT                                                            0x501d28UL //Access:RC   DataWidth:0x20  Statistics for the number of packets forwarded to the STORM.  Chips: BB_A0 BB_B0 K2
50488 #define NIG_REG_STAT_RX_STORM_PACKET_DISCARD                                                         0x501d2cUL //Access:RC   DataWidth:0x20  Statistics for the number of packets for the STORM that are dropped due to buffer full.  This is an RF generated RC statistics register - reading this register clears the value to 0.  Chips: BB_A0 BB_B0 K2
50489 #define NIG_REG_STAT_RX_STORM_PACKET_TRUNCATE                                                        0x501d30UL //Access:RC   DataWidth:0x20  Statistics for the number of packets for the STORM that are truncated due to buffer full.  This is an RF generated RC statistics register - reading this register clears the value to 0.  Chips: BB_A0 BB_B0 K2
50490 #define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_0                                                        0x501d40UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50491 #define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_1                                                        0x501d44UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50492 #define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_2                                                        0x501d48UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50493 #define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_3                                                        0x501d4cUL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50494 #define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_4                                                        0x501d50UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50495 #define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_5                                                        0x501d54UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50496 #define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_6                                                        0x501d58UL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50497 #define NIG_REG_STAT_LB_BRB_PACKET_PRIORITY_7                                                        0x501d5cUL //Access:RC   DataWidth:0x20  Statistics for the number of packets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50498 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_0                                                         0x501d60UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50499 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_0_SIZE                                                    2
50500 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_1                                                         0x501d68UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50501 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_1_SIZE                                                    2
50502 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_2                                                         0x501d70UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50503 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_2_SIZE                                                    2
50504 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_3                                                         0x501d78UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50505 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_3_SIZE                                                    2
50506 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_4                                                         0x501d80UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50507 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_4_SIZE                                                    2
50508 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_5                                                         0x501d88UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50509 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_5_SIZE                                                    2
50510 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_6                                                         0x501d90UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50511 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_6_SIZE                                                    2
50512 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_7                                                         0x501d98UL //Access:ST   DataWidth:0x40  Statistics for the number octets to be routed toward the BRB for the priority. This includes the discarded and truncated packets.  Chips: BB_A0 BB_B0 K2
50513 #define NIG_REG_STAT_LB_BRB_OCTET_PRIORITY_7_SIZE                                                    2
50514 #define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_0                                                      0x501da0UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50515 #define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_1                                                      0x501da4UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50516 #define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_2                                                      0x501da8UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50517 #define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_3                                                      0x501dacUL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50518 #define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_4                                                      0x501db0UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50519 #define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_5                                                      0x501db4UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50520 #define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_6                                                      0x501db8UL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50521 #define NIG_REG_STAT_LB_BRB_TRUNCATE_PRIORITY_7                                                      0x501dbcUL //Access:RC   DataWidth:0x20  Statistics for the number of packets being truncated due to BRB full.  Chips: BB_A0 BB_B0 K2
50522 #define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_0                                                       0x501dc0UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50523 #define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_1                                                       0x501dc4UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50524 #define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_2                                                       0x501dc8UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50525 #define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_3                                                       0x501dccUL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50526 #define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_4                                                       0x501dd0UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50527 #define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_5                                                       0x501dd4UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50528 #define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_6                                                       0x501dd8UL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50529 #define NIG_REG_STAT_LB_BRB_DISCARD_PRIORITY_7                                                       0x501ddcUL //Access:RC   DataWidth:0x20  Statistics for the number of packets discarded due to BRB backpressure.  Chips: BB_A0 BB_B0 K2
50530 #define NIG_REG_STAT_LB_NO_DEST                                                                      0x501de0UL //Access:RC   DataWidth:0x20  Statistics for packets dropped due to minimum size, parsing errors, and filtering. Note that statistics for packets with 32B or less are in stat_*1cyc_pkt_drop.  Chips: BB_A0 BB_B0 K2
50531 #define NIG_REG_STAT_LB_1CYC_PKT_DROP                                                                0x501de4UL //Access:RC   DataWidth:0x20  Statistics for the number of single-cycle packets dropped. This is an RF generated RC statistics register - reading this register clears the value to 0.  Chips: BB_A0 BB_B0 K2
50532 #define NIG_REG_STAT_TX_DROP                                                                         0x501de8UL //Access:RC   DataWidth:0x20  Statistic register for all of the TX packets dropped,  due to the drop bit, the per-PF drop, the per-VPORT drop, and the MCP/per-TC drain mode, and are not forwarded to the destination.  Chips: BB_A0 BB_B0 K2
50533 #define NIG_REG_STAT_TX_PF_VPORTDROP                                                                 0x501decUL //Access:RC   DataWidth:0x20  Statistic register for the number of TX packets that have the per-PF drop or per-VPORT drop configuration set. These packets may be dropped or forwarded to the destination with error, depending on the tx_lb_drop_fwderr. There may be scenarios of changing drop configurations on the fly. In this case it counts dropped SOP messages  Chips: BB_A0 BB_B0 K2
50534 #define NIG_REG_STAT_LB_DROP                                                                         0x501df0UL //Access:RC   DataWidth:0x20  Statistic register for all of the LB packets dropped,  due to the drop bit, the per-PF drop, the per-VPORT drop, and the per-TC drain mode, and are not forwarded to the destination.  Chips: BB_A0 BB_B0 K2
50535 #define NIG_REG_STAT_LB_PF_VPORTDROP                                                                 0x501df4UL //Access:RC   DataWidth:0x20  Statistic register for the number of LB packets that have the per-PF drop or per-VPORT drop configuration set while the no-drop-hdr-ind in the packet is cleared. These packets may be dropped or forwarded to the destination with error, depending on the tx_lb_drop_fwderr.  When the no-drop-hdr-ind bit is set, the packet drop bit and the per-PF/VPORT drop conditions are ignored and not processed; thus, this statistics does not increment in that case.  Chips: BB_A0 BB_B0 K2
50536 #define NIG_REG_STAT_TX_PACKET_TC_0                                                                  0x501df8UL //Access:RC   DataWidth:0x20  Statistics for the number of user packets transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50537 #define NIG_REG_STAT_TX_PACKET_TC_1                                                                  0x501dfcUL //Access:RC   DataWidth:0x20  Statistics for the number of user packets transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50538 #define NIG_REG_STAT_TX_PACKET_TC_2                                                                  0x501e00UL //Access:RC   DataWidth:0x20  Statistics for the number of user packets transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50539 #define NIG_REG_STAT_TX_PACKET_TC_3                                                                  0x501e04UL //Access:RC   DataWidth:0x20  Statistics for the number of user packets transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50540 #define NIG_REG_STAT_TX_PACKET_TC_4                                                                  0x501e08UL //Access:RC   DataWidth:0x20  Statistics for the number of user packets transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50541 #define NIG_REG_STAT_TX_PACKET_TC_5                                                                  0x501e0cUL //Access:RC   DataWidth:0x20  Statistics for the number of user packets transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50542 #define NIG_REG_STAT_TX_PACKET_TC_6                                                                  0x501e10UL //Access:RC   DataWidth:0x20  Statistics for the number of user packets transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50543 #define NIG_REG_STAT_TX_PACKET_TC_7                                                                  0x501e14UL //Access:RC   DataWidth:0x20  Statistics for the number of user packets transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50544 #define NIG_REG_STAT_TX_OCTET_TC_0                                                                   0x501e18UL //Access:ST   DataWidth:0x40  Statistics for the number of user bytes transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50545 #define NIG_REG_STAT_TX_OCTET_TC_0_SIZE                                                              2
50546 #define NIG_REG_STAT_TX_OCTET_TC_1                                                                   0x501e20UL //Access:ST   DataWidth:0x40  Statistics for the number of user bytes transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50547 #define NIG_REG_STAT_TX_OCTET_TC_1_SIZE                                                              2
50548 #define NIG_REG_STAT_TX_OCTET_TC_2                                                                   0x501e28UL //Access:ST   DataWidth:0x40  Statistics for the number of user bytes transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50549 #define NIG_REG_STAT_TX_OCTET_TC_2_SIZE                                                              2
50550 #define NIG_REG_STAT_TX_OCTET_TC_3                                                                   0x501e30UL //Access:ST   DataWidth:0x40  Statistics for the number of user bytes transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50551 #define NIG_REG_STAT_TX_OCTET_TC_3_SIZE                                                              2
50552 #define NIG_REG_STAT_TX_OCTET_TC_4                                                                   0x501e38UL //Access:ST   DataWidth:0x40  Statistics for the number of user bytes transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50553 #define NIG_REG_STAT_TX_OCTET_TC_4_SIZE                                                              2
50554 #define NIG_REG_STAT_TX_OCTET_TC_5                                                                   0x501e40UL //Access:ST   DataWidth:0x40  Statistics for the number of user bytes transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50555 #define NIG_REG_STAT_TX_OCTET_TC_5_SIZE                                                              2
50556 #define NIG_REG_STAT_TX_OCTET_TC_6                                                                   0x501e48UL //Access:ST   DataWidth:0x40  Statistics for the number of user bytes transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50557 #define NIG_REG_STAT_TX_OCTET_TC_6_SIZE                                                              2
50558 #define NIG_REG_STAT_TX_OCTET_TC_7                                                                   0x501e50UL //Access:ST   DataWidth:0x40  Statistics for the number of user bytes transmitted for the TC.  Chips: BB_A0 BB_B0 K2
50559 #define NIG_REG_STAT_TX_OCTET_TC_7_SIZE                                                              2
50560 #define NIG_REG_TX_XOFF_CYC_TC_0                                                                     0x501e58UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50561 #define NIG_REG_TX_XOFF_CYC_TC_0_SIZE                                                                2
50562 #define NIG_REG_TX_XOFF_CYC_TC_1                                                                     0x501e60UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50563 #define NIG_REG_TX_XOFF_CYC_TC_1_SIZE                                                                2
50564 #define NIG_REG_TX_XOFF_CYC_TC_2                                                                     0x501e68UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50565 #define NIG_REG_TX_XOFF_CYC_TC_2_SIZE                                                                2
50566 #define NIG_REG_TX_XOFF_CYC_TC_3                                                                     0x501e70UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50567 #define NIG_REG_TX_XOFF_CYC_TC_3_SIZE                                                                2
50568 #define NIG_REG_TX_XOFF_CYC_TC_4                                                                     0x501e78UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50569 #define NIG_REG_TX_XOFF_CYC_TC_4_SIZE                                                                2
50570 #define NIG_REG_TX_XOFF_CYC_TC_5                                                                     0x501e80UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50571 #define NIG_REG_TX_XOFF_CYC_TC_5_SIZE                                                                2
50572 #define NIG_REG_TX_XOFF_CYC_TC_6                                                                     0x501e88UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50573 #define NIG_REG_TX_XOFF_CYC_TC_6_SIZE                                                                2
50574 #define NIG_REG_TX_XOFF_CYC_TC_7                                                                     0x501e90UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50575 #define NIG_REG_TX_XOFF_CYC_TC_7_SIZE                                                                2
50576 #define NIG_REG_LB_XOFF_CYC_TC_0                                                                     0x501e98UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50577 #define NIG_REG_LB_XOFF_CYC_TC_0_SIZE                                                                2
50578 #define NIG_REG_LB_XOFF_CYC_TC_1                                                                     0x501ea0UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50579 #define NIG_REG_LB_XOFF_CYC_TC_1_SIZE                                                                2
50580 #define NIG_REG_LB_XOFF_CYC_TC_2                                                                     0x501ea8UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50581 #define NIG_REG_LB_XOFF_CYC_TC_2_SIZE                                                                2
50582 #define NIG_REG_LB_XOFF_CYC_TC_3                                                                     0x501eb0UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50583 #define NIG_REG_LB_XOFF_CYC_TC_3_SIZE                                                                2
50584 #define NIG_REG_LB_XOFF_CYC_TC_4                                                                     0x501eb8UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50585 #define NIG_REG_LB_XOFF_CYC_TC_4_SIZE                                                                2
50586 #define NIG_REG_LB_XOFF_CYC_TC_5                                                                     0x501ec0UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50587 #define NIG_REG_LB_XOFF_CYC_TC_5_SIZE                                                                2
50588 #define NIG_REG_LB_XOFF_CYC_TC_6                                                                     0x501ec8UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50589 #define NIG_REG_LB_XOFF_CYC_TC_6_SIZE                                                                2
50590 #define NIG_REG_LB_XOFF_CYC_TC_7                                                                     0x501ed0UL //Access:WB_R DataWidth:0x28  Statistics for the number of cycles that the TC is XOFFed.  Chips: BB_A0 BB_B0 K2
50591 #define NIG_REG_LB_XOFF_CYC_TC_7_SIZE                                                                2
50592 #define NIG_REG_STAT_RX_BMB_OCTET                                                                    0x501ed8UL //Access:RC   DataWidth:0x20  Number of RX octets to be forwarded to BMB.  Chips: BB_A0 BB_B0 K2
50593 #define NIG_REG_STAT_RX_BMB_PACKET                                                                   0x501edcUL //Access:RC   DataWidth:0x20  Number of RX packets to be forwarded to BMB.  Chips: BB_A0 BB_B0 K2
50594 #define NIG_REG_STAT_RX_BMB_PACKET_TRUNCATE                                                          0x501ee0UL //Access:RC   DataWidth:0x20  Number of RX packets to be forwarded to BMB that got truncated due to BMB full backpressure.  Chips: BB_A0 BB_B0 K2
50595 #define NIG_REG_STAT_RX_BMB_PACKET_DISCARD                                                           0x501ee4UL //Access:RC   DataWidth:0x20  Number of RX packets to be forwarded to BMB that got discarded due to BMB full backpressure.  Chips: BB_A0 BB_B0 K2
50596 #define NIG_REG_STAT_TX_H2BMB_OCTET                                                                  0x501ee8UL //Access:RC   DataWidth:0x20  Number of TX octets to be forwarded to BMB.  Chips: BB_A0 BB_B0 K2
50597 #define NIG_REG_STAT_TX_H2BMB_PACKET                                                                 0x501eecUL //Access:RC   DataWidth:0x20  Number of TX packets to be forwarded to BMB.  Chips: BB_A0 BB_B0 K2
50598 #define NIG_REG_STAT_TX_H2BMB_PACKET_TRUNCATE                                                        0x501ef0UL //Access:RC   DataWidth:0x20  Number of TX packets to be forwarded to BMB that got truncated due to BMB full backpressure.  Chips: BB_A0 BB_B0 K2
50599 #define NIG_REG_STAT_TX_H2BMB_PACKET_DISCARD                                                         0x501ef4UL //Access:RC   DataWidth:0x20  Number of TX packets to be forwarded to BMB that got discarded due to BMB full backpressure.  Chips: BB_A0 BB_B0 K2
50600 #define NIG_REG_STAT_TX_BMB_PACKET                                                                   0x501ef8UL //Access:RC   DataWidth:0x20  Statistics for the number of packets received from BMB for sending to the network.  Chips: BB_A0 BB_B0 K2
50601 #define NIG_REG_STAT_LB_BMB_PACKET                                                                   0x501efcUL //Access:RC   DataWidth:0x20  Number of packets received from BMB for forwarding to the host.  Chips: BB_A0 BB_B0 K2
50602 #define NIG_REG_STAT_LB_BMB_PACKET_TRUNCATE                                                          0x501f00UL //Access:RC   DataWidth:0x20  Number of packets from BMB to be forwarded to the host that got truncated due to BRB LB per-TC full backpressure.  Chips: BB_A0 BB_B0 K2
50603 #define NIG_REG_STAT_LB_BMB_PACKET_DISCARD                                                           0x501f04UL //Access:RC   DataWidth:0x20  Number of packets from BMB to be forwarded to the host that got dropped due to BRB LB per-TC full backpressure.  Chips: BB_A0 BB_B0 K2
50604 #define NIG_REG_TX_ZERO_PAD_EN                                                                       0x501f08UL //Access:RW   DataWidth:0x1   Zero-padding enable for TX packets.  Set this bit to enable the padding of short packets to 60B.  Chips: BB_A0 BB_B0 K2
50605 #define NIG_REG_TX_EDPM_CTRL                                                                         0x501f0cUL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50606     #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN                                                          (0x1<<0) // Enable EDPM for the port.
50607     #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_EN_SHIFT                                                    0
50608     #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN                                                       (0xff<<1) // TC enable for EDPM.  There is one bit per TC.  This is used in the generation of the EDPM enable output to DORQ.
50609     #define NIG_REG_TX_EDPM_CTRL_TX_EDPM_TC_EN_SHIFT                                                 1
50610 #define NIG_REG_TX_MIN_CYC_THRESHOLD                                                                 0x501f10UL //Access:RW   DataWidth:0x6   Minimum cycle threshold register for specifying the minimum number of cycles of ready-to-transmit data remaining  below which ETS arbiter for the transmit path should start selecting the next packet.  This value should cover the BTB access latency and arbitration time to provide back-to-back packets as needed to sustain the data rate, but should be as low as possilbe to minimize delay in responding to a flow control request.  Chips: BB_A0 BB_B0 K2
50611 #define NIG_REG_TX_BTB_FIFO_ALM_FULL_THR                                                             0x501f14UL //Access:RW   DataWidth:0x5   Almost full threshold for TX BTB FIFO.  Chips: BB_A0 BB_B0 K2
50612 #define NIG_REG_TX_GNT_FIFO_ALM_FULL_THR                                                             0x501f18UL //Access:RW   DataWidth:0x4   Almost full threshold for TX GNT FIFO.  Chips: BB_A0 BB_B0 K2
50613 #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL                                                              0x501f1cUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50614     #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN                                    (0x1<<0) // Enable bit for the global rate limiter to be used in pacing TX and LB traffic of the same port.  Defaults to enabled rate limit of 48Gbps.
50615     #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT                              0
50616     #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE                             (0x3<<1) // Select between byte, cycle, and packet level of fairness for the global rate limiter.  0 selects packet level.  1 selects byte level.  2 selects cycle level.  Value configurations should match the type of fairness selected here.
50617     #define NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT                       1
50618 #define NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD                                                        0x501f20UL //Access:RW   DataWidth:0x20  Increment PERIOD for the global rate limiter - in term of 25MHz clock cycles.  Note that this register should be programmed only while this rate limiter is disabled.  Chips: BB_A0 BB_B0 K2
50619 #define NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE                                                         0x501f24UL //Access:RW   DataWidth:0x20  Increment VALUE for the global rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration). This is the amount of data allowed in the configured increment period *inc_period to get the desired data rate.  Chips: BB_A0 BB_B0 K2
50620 #define NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE                                                         0x501f28UL //Access:RW   DataWidth:0x20  Upper bound VALUE for the global rate limiter - in term of bytes, cycles, or packets (as selected in the *base_type configuration).  Chips: BB_A0 BB_B0 K2
50621 #define NIG_REG_TX_LB_GLBRATELIMIT_IFG_SIZE                                                          0x501f2cUL //Access:RW   DataWidth:0x8   Value to be added to the packet size for the rate limiter to account for IPG, FCS, preamble, etc..., in term of bytes.  Chips: BB_A0 BB_B0 K2
50622 #define NIG_REG_TX_ARB_EN                                                                            0x501f30UL //Access:RW   DataWidth:0x1   TX ETS arbitration enable.  Chips: BB_A0 BB_B0 K2
50623 #define NIG_REG_TX_ARB_CLIENT_IS_STRICT                                                              0x501f34UL //Access:RW   DataWidth:0xc   Specify whether the client competes directly in the strict priority arbiter.  The bits are mapped according to client ID  (client IDs are defined in *_arb_priority_client): 0-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 traffic; 10-TC6 traffic; 11-TC7 traffic.  Default value is set to enable strict priorities for all clients.  Chips: BB_A0 BB_B0 K2
50624 #define NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ                                                         0x501f38UL //Access:RW   DataWidth:0xc   Specify whether the client is subject to WFQ credit blocking.  The bits are mapped according to client ID (client IDs are defined in *_arb_priority_client): 0-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 traffic; 10-TC6 traffic; 11-TC7 traffic.  Default value is 0 for not using WFQ credit blocking.  Chips: BB_A0 BB_B0 K2
50625 #define NIG_REG_TX_ARB_NUM_STRICT_ARB_SLOTS                                                          0x501f3cUL //Access:RW   DataWidth:0xc   Specify the number of strict priority arbitration slots between two round-robin arbitration slots to avoid starvation.  A value of 0 means no strict priority cycles - the strict priority with anti-starvation arbiter becomes a round-robin arbiter.  Chips: BB_A0 BB_B0 K2
50626 #define NIG_REG_TX_ARB_PRIORITY_CLIENT                                                               0x501f40UL //Access:WB   DataWidth:0x30  Specify the client number to be assigned to each priority of the strict priority arbiter.  Priority 0 is the highest priority.  Bits [3:0] are for priority 0 client; bits [47:44] are for priority 11 client.  The clients are assigned the following IDs:  0-DORQ; 1-management; 2-debug traffic from this port; 3-debug traffic from other port; 4-TC0 traffic; 5-TC1 traffic; 6-TC2 traffic; 7-TC3 traffic; 8-TC4 traffic; 9-TC5 traffic; 10-TC6 traffic; 11-TC7 traffic.  The reset value is set to 0x456789ab_1320.  Chips: BB_A0 BB_B0 K2
50627 #define NIG_REG_TX_ARB_PRIORITY_CLIENT_SIZE                                                          2
50628 #define NIG_REG_TX_ARB_BURST_MODE                                                                    0x501f48UL //Access:RW   DataWidth:0x2   Burst mode enables.  Set these bits to have the round-robin arbiter stays on the winning input instead of moving to the next one.  Bit 0 is for the main round-robin arbiter.  Bit 1 is for the round-robin arbiter within the strict priority with anti-starvation feature.  Chips: BB_A0 BB_B0 K2
50629 #define NIG_REG_TX_ARB_IFG_SIZE                                                                      0x501f4cUL //Access:RW   DataWidth:0x8   Specify the number of bytes to be deducted from the client credit register at the time of grant in additional to the normal packet credit costs.  This may include the IPG and FCS field.  Chips: BB_A0 BB_B0 K2
50630 #define NIG_REG_TX_ARB_PSEUDO_RR_EN                                                                  0x501f50UL //Access:RW   DataWidth:0x1   Enable bit for the pseudo-random arbitration mode.  Chips: BB_A0 BB_B0 K2
50631 #define NIG_REG_TX_ARB_DBG_CLIENT_DISABLE                                                            0x501f54UL //Access:RW   DataWidth:0x1   Set this bit to disable debug traffic at the inputs to the ETS arbiter.  Chips: BB_A0 BB_B0 K2
50632 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0                                                          0x501f58UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 0 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50633 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1                                                          0x501f5cUL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 1 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50634 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_2                                                          0x501f60UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 2 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50635 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_3                                                          0x501f64UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 3 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50636 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_4                                                          0x501f68UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 4 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50637 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_5                                                          0x501f6cUL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 5 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50638 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_6                                                          0x501f70UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 6 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50639 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_7                                                          0x501f74UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 7 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50640 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_8                                                          0x501f78UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 8 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50641 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_9                                                          0x501f7cUL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 9 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50642 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_10                                                         0x501f80UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 10 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50643 #define NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_11                                                         0x501f84UL //Access:RW   DataWidth:0x20  Specify the upper bound that credit register 11 is allowed to reach.  Chips: BB_A0 BB_B0 K2
50644 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_0                                                               0x501f88UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 0 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50645 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_1                                                               0x501f8cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 1 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50646 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_2                                                               0x501f90UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 2 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50647 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_3                                                               0x501f94UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 3 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50648 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_4                                                               0x501f98UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 4 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50649 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_5                                                               0x501f9cUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 5 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50650 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_6                                                               0x501fa0UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 6 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50651 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_7                                                               0x501fa4UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 7 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50652 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_8                                                               0x501fa8UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 8 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50653 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_9                                                               0x501facUL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 9 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50654 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_10                                                              0x501fb0UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 10 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50655 #define NIG_REG_TX_ARB_CREDIT_WEIGHT_11                                                              0x501fb4UL //Access:RW   DataWidth:0x20  Specify the weight (in bytes) to be added to credit register 11 when it is time to increment.  Chips: BB_A0 BB_B0 K2
50656 #define NIG_REG_TX_ARB_CURRENT_CREDIT_0                                                              0x501fb8UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 0.  Chips: BB_A0 BB_B0 K2
50657 #define NIG_REG_TX_ARB_CURRENT_CREDIT_1                                                              0x501fbcUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 1.  Chips: BB_A0 BB_B0 K2
50658 #define NIG_REG_TX_ARB_CURRENT_CREDIT_2                                                              0x501fc0UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 2.  Chips: BB_A0 BB_B0 K2
50659 #define NIG_REG_TX_ARB_CURRENT_CREDIT_3                                                              0x501fc4UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 3.  Chips: BB_A0 BB_B0 K2
50660 #define NIG_REG_TX_ARB_CURRENT_CREDIT_4                                                              0x501fc8UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 4.  Chips: BB_A0 BB_B0 K2
50661 #define NIG_REG_TX_ARB_CURRENT_CREDIT_5                                                              0x501fccUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 5.  Chips: BB_A0 BB_B0 K2
50662 #define NIG_REG_TX_ARB_CURRENT_CREDIT_6                                                              0x501fd0UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 6.  Chips: BB_A0 BB_B0 K2
50663 #define NIG_REG_TX_ARB_CURRENT_CREDIT_7                                                              0x501fd4UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 7.  Chips: BB_A0 BB_B0 K2
50664 #define NIG_REG_TX_ARB_CURRENT_CREDIT_8                                                              0x501fd8UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 8.  Chips: BB_A0 BB_B0 K2
50665 #define NIG_REG_TX_ARB_CURRENT_CREDIT_9                                                              0x501fdcUL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 9.  Chips: BB_A0 BB_B0 K2
50666 #define NIG_REG_TX_ARB_CURRENT_CREDIT_10                                                             0x501fe0UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 10.  Chips: BB_A0 BB_B0 K2
50667 #define NIG_REG_TX_ARB_CURRENT_CREDIT_11                                                             0x501fe4UL //Access:R    DataWidth:0x20  Current upper 32 bits of the 33-bit value in TX arbiter credit register 11.  Chips: BB_A0 BB_B0 K2
50668 #define NIG_REG_TX_LLH_NCSI_MCP_MASK                                                                 0x501fe8UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
50669     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_BRCST                                                       (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to MCP.
50670     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_BRCST_SHIFT                                                 0
50671     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ALLMLCST                                                    (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to MCP.
50672     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ALLMLCST_SHIFT                                              1
50673     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV4MLCST                                                   (0x1<<2) // Mask bit for forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to MCP.
50674     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV4MLCST_SHIFT                                             2
50675     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV6_MLCST                                                  (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to MCP.
50676     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IPV6_MLCST_SHIFT                                            3
50677     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UNCST                                                       (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to MCP.
50678     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UNCST_SHIFT                                                 4
50679     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC0                                                        (0x1<<5) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to MCP.
50680     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC0_SHIFT                                                  5
50681     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC1                                                        (0x1<<6) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to MCP.
50682     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC1_SHIFT                                                  6
50683     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC2                                                        (0x1<<7) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to MCP.
50684     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC2_SHIFT                                                  7
50685     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC3                                                        (0x1<<8) // Mask bit for forwarding packets with the MAC destination address  mtching *llh*_dest_mac_3 to MCP.
50686     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC3_SHIFT                                                  8
50687     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC4                                                        (0x1<<9) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to MCP.
50688     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC4_SHIFT                                                  9
50689     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC5                                                        (0x1<<10) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to MCP.
50690     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_MAC5_SHIFT                                                  10
50691     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE0                                                  (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to MCP.
50692     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE0_SHIFT                                            11
50693     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE1                                                  (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the host.
50694     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ETHERTYPE1_SHIFT                                            12
50695     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ARP                                                         (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and bcast address to MCP.
50696     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ARP_SHIFT                                                   13
50697     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP0                                                         (0x1<<14) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to MCP.
50698     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP0_SHIFT                                                   14
50699     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP1                                                         (0x1<<15) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to MCP.
50700     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP1_SHIFT                                                   15
50701     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP2                                                         (0x1<<16) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to MCP.
50702     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IP2_SHIFT                                                   16
50703     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP0                                                        (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to MCP.
50704     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP0_SHIFT                                                  17
50705     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP1                                                        (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to MCP.
50706     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP1_SHIFT                                                  18
50707     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP2                                                        (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to MCP.
50708     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_TCP2_SHIFT                                                  19
50709     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_DST                                                  (0x1<<20) // Mask bit for forwarding packets with NetBIOS TCP destination port 137/138/139 to MCP.
50710     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_DST_SHIFT                                            20
50711     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_SRC                                                  (0x1<<21) // Mask bit for forwarding packets with NetBIOS TCP source port 137/138 /139 to MCP.
50712     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_T_SRC_SHIFT                                            21
50713     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP0                                                        (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to MCP.
50714     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP0_SHIFT                                                  22
50715     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP1                                                        (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to MCP.
50716     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP1_SHIFT                                                  23
50717     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP2                                                        (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to MCP.
50718     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_UDP2_SHIFT                                                  24
50719     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_RMCP                                                        (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to MCP.
50720     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_RMCP_SHIFT                                                  25
50721     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_DST                                                  (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to MCP.
50722     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_DST_SHIFT                                            26
50723     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_SRC                                                  (0x1<<27) // Mask bit for forwarding packets with NetBIOS UDP source port 137/138 /139 to MCP.
50724     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_NTBS_U_SRC_SHIFT                                            27
50725     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_DHCP                                                        (0x1<<28) // Mask bit for forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to MCP.
50726     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_DHCP_SHIFT                                                  28
50727     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_NA                                                   (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to MCP.
50728     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_NA_SHIFT                                             29
50729     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_RA                                                   (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type= 134 and dst_mac = 0x33:33:00:00:00:01) to MCP.
50730     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_RA_SHIFT                                             30
50731     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6                                                      (0x1<<31) // Mask bit for forwarding ICMPv6 packets to MCP.
50732     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_ICMPV6_SHIFT                                                31
50733 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN                                                           0x501fecUL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50734     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ANY                                                   (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to the network.
50735     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ANY_SHIFT                                             0
50736     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_NONE                                                  (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to the network.
50737     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_NONE_SHIFT                                            1
50738     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID0                                                   (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the network.
50739     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID0_SHIFT                                             2
50740     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID1                                                   (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the network.
50741     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID1_SHIFT                                             3
50742     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID2                                                   (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the network.
50743     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_IVLAN_ID2_SHIFT                                             4
50744 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK                                                         0x501ff0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
50745     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_BRCST                                               (0x1<<0) // Mask bit for not forwarding broadcast (MAC destination address of all 1's) packets to the network.
50746     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_BRCST_SHIFT                                         0
50747     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ALLMLCST                                            (0x1<<1) // Mask bit for not forwarding multicast (MAC destination address[40]==1 and it is not a broadcast packet) packets to the network.
50748     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ALLMLCST_SHIFT                                      1
50749     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV4MLCST                                           (0x1<<2) // Mask bit for not forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to the network.
50750     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV4MLCST_SHIFT                                     2
50751     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLCST                                          (0x1<<3) // Mask bit for not forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the network.
50752     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLCST_SHIFT                                    3
50753     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UNCST                                               (0x1<<4) // Mask bit for not forwarding unicast (MAC destination address[40]==0) packets to the network.
50754     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UNCST_SHIFT                                         4
50755     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC0                                                (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to the network.
50756     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC0_SHIFT                                          5
50757     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC1                                                (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to the network.
50758     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC1_SHIFT                                          6
50759     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC2                                                (0x1<<7) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to the network.
50760     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC2_SHIFT                                          7
50761     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC3                                                (0x1<<8) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_3 to the network.
50762     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC3_SHIFT                                          8
50763     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC4                                                (0x1<<9) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to the network.
50764     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC4_SHIFT                                          9
50765     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC5                                                (0x1<<10) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to the network.
50766     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_MAC5_SHIFT                                          10
50767     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE0                                          (0x1<<11) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype0 to the network.
50768     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE0_SHIFT                                    11
50769     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE1                                          (0x1<<12) // Mask bit for not forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the network.
50770     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ETHERTYPE1_SHIFT                                    12
50771     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ARP                                                 (0x1<<13) // Mask bit for not forwarding packets with Ethertype of 0x0806 and bcast address to the network.
50772     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ARP_SHIFT                                           13
50773     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP0                                                 (0x1<<14) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the network.
50774     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP0_SHIFT                                           14
50775     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP1                                                 (0x1<<15) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the network.
50776     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP1_SHIFT                                           15
50777     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP2                                                 (0x1<<16) // Mask bit for not forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the network.
50778     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IP2_SHIFT                                           16
50779     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP0                                                (0x1<<17) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the network.
50780     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP0_SHIFT                                          17
50781     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP1                                                (0x1<<18) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the network.
50782     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP1_SHIFT                                          18
50783     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP2                                                (0x1<<19) // Mask bit for not forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the network.
50784     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_TCP2_SHIFT                                          19
50785     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_DST                                          (0x1<<20) // Mask bit for not forwarding packets with NetBIOS TCP destination port 137/138/139 to the network.
50786     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_DST_SHIFT                                    20
50787     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_SRC                                          (0x1<<21) // Mask bit for not forwarding packets with NetBIOS TCP source port 137/138 /139 to the network.
50788     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_T_SRC_SHIFT                                    21
50789     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP0                                                (0x1<<22) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the network.
50790     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP0_SHIFT                                          22
50791     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP1                                                (0x1<<23) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the network.
50792     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP1_SHIFT                                          23
50793     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP2                                                (0x1<<24) // Mask bit for not forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the network.
50794     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_UDP2_SHIFT                                          24
50795     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_RMCP                                                (0x1<<25) // Mask bit for not forwarding packets with RMCP UDP ports (0x26f and 0x298) to the network.
50796     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_RMCP_SHIFT                                          25
50797     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_DST                                          (0x1<<26) // Mask bit for not forwarding packets with NetBIOS UDP destination port 137/138/139 to the network.
50798     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_DST_SHIFT                                    26
50799     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_SRC                                          (0x1<<27) // Mask bit for not forwarding packets with NetBIOS UDP source port 137/138 /139 to the network.
50800     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_NTBS_U_SRC_SHIFT                                    27
50801     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP                                                (0x1<<28) // Mask bit for not forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to the network.
50802     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_SHIFT                                          28
50803     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_NA                                           (0x1<<29) // Mask bit for not forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the network.
50804     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_NA_SHIFT                                     29
50805     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_RA                                           (0x1<<30) // Mask bit for not forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the network.
50806     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_RA_SHIFT                                     30
50807     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6                                              (0x1<<31) // Mask bit for not forwarding ICMPv6 packets to the network.
50808     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_ICMPV6_SHIFT                                        31
50809 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK                                                                0x501ff4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
50810     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_BRCST                                                      (0x1<<0) // Mask bit for forwarding broadcast (MAC destination address of all 1's) packets to the network.
50811     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_BRCST_SHIFT                                                0
50812     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ALLMLCST                                                   (0x1<<1) // Mask bit for forwarding multicast (MAC destination address[40]==1 and it is a broadcast packet) packets to the network.
50813     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ALLMLCST_SHIFT                                             1
50814     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV4MLCST                                                  (0x1<<2) // Mask bit for forwarding IPv4 multicast (MAC destination address [47:40]==0x01) packets to the network.
50815     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV4MLCST_SHIFT                                            2
50816     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV6_MLCST                                                 (0x1<<3) // Mask bit for forwarding IPv6 multicast (MAC destination address [47:32]==0x3333) packets to the network.
50817     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IPV6_MLCST_SHIFT                                           3
50818     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UNCST                                                      (0x1<<4) // Mask bit for forwarding unicast (MAC destination address[40]==0) packets to the network.
50819     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UNCST_SHIFT                                                4
50820     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC0                                                       (0x1<<5) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_0 to the network.
50821     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC0_SHIFT                                                 5
50822     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC1                                                       (0x1<<6) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_1 to the network.
50823     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC1_SHIFT                                                 6
50824     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC2                                                       (0x1<<7) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_2 to the network.
50825     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC2_SHIFT                                                 7
50826     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC3                                                       (0x1<<8) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_3 to the network.
50827     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC3_SHIFT                                                 8
50828     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC4                                                       (0x1<<9) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_4 to the network.
50829     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC4_SHIFT                                                 9
50830     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC5                                                       (0x1<<10) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_5 to the network.
50831     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_MAC5_SHIFT                                                 10
50832     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE0                                                 (0x1<<11) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype0 to the network.
50833     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE0_SHIFT                                           11
50834     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE1                                                 (0x1<<12) // Mask bit for forwarding packets with Ethertype matching *llh_ethertype1 to be forwarded to the network.
50835     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ETHERTYPE1_SHIFT                                           12
50836     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ARP                                                        (0x1<<13) // Mask bit for forwarding packets with Ethertype of 0x0806 and bcast address to the network.
50837     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ARP_SHIFT                                                  13
50838     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP0                                                        (0x1<<14) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_0 and the IP version matching *llh*_ipv4_ipv6_0 to the network.
50839     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP0_SHIFT                                                  14
50840     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP1                                                        (0x1<<15) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_1 and the IP version matching *llh*_ipv4_ipv6_1 to the network.
50841     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP1_SHIFT                                                  15
50842     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP2                                                        (0x1<<16) // Mask bit for forwarding packets with the IP destination address  matching *llh*_dest_ip_2 and the IP version matching *llh*_ipv4_ipv6_2 to the network.
50843     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IP2_SHIFT                                                  16
50844     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP0                                                       (0x1<<17) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_0 to the network.
50845     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP0_SHIFT                                                 17
50846     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP1                                                       (0x1<<18) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_1 to the network.
50847     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP1_SHIFT                                                 18
50848     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP2                                                       (0x1<<19) // Mask bit for forwarding packets with the TCP destination port matching *llh*_dest_tcp_2 to the network.
50849     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_TCP2_SHIFT                                                 19
50850     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_DST                                                 (0x1<<20) // Mask bit for forwarding packets with NetBIOS TCP destination port 137/138/139 to the network.
50851     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_DST_SHIFT                                           20
50852     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_SRC                                                 (0x1<<21) // Mask bit for forwarding packets with NetBIOS TCP source port 137/138 /139 to the network.
50853     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_T_SRC_SHIFT                                           21
50854     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP0                                                       (0x1<<22) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_0 to the network.
50855     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP0_SHIFT                                                 22
50856     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP1                                                       (0x1<<23) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_1 to the network.
50857     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP1_SHIFT                                                 23
50858     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP2                                                       (0x1<<24) // Mask bit for forwarding packets with the UDP destination port matching *llh*_dest_udp_2 to the network.
50859     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_UDP2_SHIFT                                                 24
50860     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_RMCP                                                       (0x1<<25) // Mask bit for forwarding packets with RMCP UDP ports (0x26f and 0x298) to the network.
50861     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_RMCP_SHIFT                                                 25
50862     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_DST                                                 (0x1<<26) // Mask bit for forwarding packets with NetBIOS UDP destination port 137/138/139 to the network.
50863     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_DST_SHIFT                                           26
50864     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_SRC                                                 (0x1<<27) // Mask bit for forwarding packets with NetBIOS UDP source port 137/138 /139 to the network.
50865     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_NTBS_U_SRC_SHIFT                                           27
50866     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_DHCP                                                       (0x1<<28) // Mask bit for forwarding packets with DHCP UDP/TCP ports 67/68/546/547/647/847 to the network.
50867     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_DHCP_SHIFT                                                 28
50868     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_NA                                                  (0x1<<29) // Mask bit for forwarding ICMPv6 Neighbor Advertisement packets (ICMP over IPv6 with ICMP type = 136 and dst_mac = 0x33:33:00:00:00:01) to the network.
50869     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_NA_SHIFT                                            29
50870     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_RA                                                  (0x1<<30) // Mask bit for forwarding ICMPv6 Router Advertisement packets (ICMP over IPv6 with ICMP type = 134 and dst_mac = 0x33:33:00:00:00:01) to the network.
50871     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_RA_SHIFT                                            30
50872     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6                                                     (0x1<<31) // Mask bit for forwarding ICMPv6 packets to the network.
50873     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_ICMPV6_SHIFT                                               31
50874 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN                                                          0x501ff8UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
50875     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ANY                                                  (0x1<<0) // Mask bit for forwarding packets with inner VLAN present to the network.
50876     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ANY_SHIFT                                            0
50877     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_NONE                                                 (0x1<<1) // Mask bit for forwarding packets with no inner VLAN to the network.
50878     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_NONE_SHIFT                                           1
50879     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID0                                                  (0x1<<2) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_0 to the network.
50880     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID0_SHIFT                                            2
50881     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID1                                                  (0x1<<3) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_1 to the network.
50882     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID1_SHIFT                                            3
50883     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID2                                                  (0x1<<4) // Mask bit for forwarding packets with the inner VLAN ID matching *llh*_vlan_id_2 to the network.
50884     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_IVLAN_ID2_SHIFT                                            4
50885 #define NIG_REG_TX_BTB_FIFO_EMPTY                                                                    0x501ffcUL //Access:R    DataWidth:0x1   TX BTB FIFO empty status.  Chips: BB_A0 BB_B0 K2
50886 #define NIG_REG_TX_BTB_FIFO_FULL                                                                     0x502000UL //Access:R    DataWidth:0x1   TX BTB FIFO full status.  Chips: BB_A0 BB_B0 K2
50887 #define NIG_REG_TX_LLH_DFIFO_ALM_FULL_THR                                                            0x502004UL //Access:RW   DataWidth:0x6   TX LLH Data FIFO almost full threshold.  Chips: BB_A0 BB_B0 K2
50888 #define NIG_REG_TX_LLH_HFIFO_ALM_FULL_THR                                                            0x502008UL //Access:RW   DataWidth:0x5   TX LLH header FIFO almost full threshold.  Chips: BB_A0 BB_B0 K2
50889 #define NIG_REG_TX_LLH_RFIFO_ALM_FULL_THR                                                            0x50200cUL //Access:RW   DataWidth:0x4   TX LLH result FIFO almost full threshold.  Chips: BB_A0 BB_B0 K2
50890 #define NIG_REG_TX_LLH_DFIFO_EMPTY                                                                   0x502010UL //Access:R    DataWidth:0x1   TX LLH Data FIFO is empty.  Chips: BB_A0 BB_B0 K2
50891 #define NIG_REG_TX_LLH_DFIFO_ALM_FULL                                                                0x502014UL //Access:R    DataWidth:0x1   TX LLH Data FIFO almost full.  Chips: BB_A0 BB_B0 K2
50892 #define NIG_REG_TX_LLH_DFIFO_FULL                                                                    0x502018UL //Access:R    DataWidth:0x1   TX LLH Data FIFO is full.  Chips: BB_A0 BB_B0 K2
50893 #define NIG_REG_TX_LLH_HFIFO_EMPTY                                                                   0x50201cUL //Access:R    DataWidth:0x1   TX LLH header FIFO is empty.  Chips: BB_A0 BB_B0 K2
50894 #define NIG_REG_TX_LLH_HFIFO_ALM_FULL                                                                0x502020UL //Access:R    DataWidth:0x1   TX LLH header FIFO almost full.  Chips: BB_A0 BB_B0 K2
50895 #define NIG_REG_TX_LLH_HFIFO_FULL                                                                    0x502024UL //Access:R    DataWidth:0x1   TX LLH header FIFO is full.  Chips: BB_A0 BB_B0 K2
50896 #define NIG_REG_TX_LLH_RFIFO_EMPTY                                                                   0x502028UL //Access:R    DataWidth:0x1   TX LLH result FIFO is empty.  Chips: BB_A0 BB_B0 K2
50897 #define NIG_REG_TX_LLH_RFIFO_ALM_FULL                                                                0x50202cUL //Access:R    DataWidth:0x1   TX LLH result FIFO almost full.  Chips: BB_A0 BB_B0 K2
50898 #define NIG_REG_TX_LLH_RFIFO_FULL                                                                    0x502030UL //Access:R    DataWidth:0x1   TX LLH result FIFO is full.  Chips: BB_A0 BB_B0 K2
50899 #define NIG_REG_TX_GNT_FIFO_EMPTY                                                                    0x502034UL //Access:R    DataWidth:0x1   TX GNT FIFO empty status.  Chips: BB_A0 BB_B0 K2
50900 #define NIG_REG_TX_GNT_FIFO_FULL                                                                     0x502038UL //Access:R    DataWidth:0x1   TX GNT FIFO full status.  Chips: BB_A0 BB_B0 K2
50901 #define NIG_REG_MNG_OUTER_TAG0_0                                                                     0x50203cUL //Access:RW   DataWidth:0x20  Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50902 #define NIG_REG_MNG_OUTER_TAG0_1                                                                     0x502040UL //Access:RW   DataWidth:0x20  Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50903 #define NIG_REG_MNG_OUTER_TAG1_0                                                                     0x502044UL //Access:RW   DataWidth:0x20  Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50904 #define NIG_REG_MNG_OUTER_TAG1_1                                                                     0x502048UL //Access:RW   DataWidth:0x20  Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50905 #define NIG_REG_MNG_INNER_VLAN_TAG0                                                                  0x50204cUL //Access:RW   DataWidth:0x10  Value of inner VLAN tag to be used in tag insertion/override for management packets.  This field consists of {3-bit priority, 1-bit drop eligible, 12-bit VLAN ID}.  Chips: BB_A0 BB_B0
50906 #define NIG_REG_MNG_INNER_VLAN_TAG1                                                                  0x502050UL //Access:RW   DataWidth:0x10  Value of inner VLAN tag to be used in tag insertion/override for management packets.  This field consists of {3-bit priority, 1-bit drop eligible, 12-bit VLAN ID}.  Chips: BB_A0 BB_B0
50907 #define NIG_REG_MNG_PROP_HDR0_0                                                                      0x502054UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50908 #define NIG_REG_MNG_PROP_HDR0_1                                                                      0x502058UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50909 #define NIG_REG_MNG_PROP_HDR0_2                                                                      0x50205cUL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50910 #define NIG_REG_MNG_PROP_HDR0_3                                                                      0x502060UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50911 #define NIG_REG_MNG_PROP_HDR0_4                                                                      0x502064UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50912 #define NIG_REG_MNG_PROP_HDR0_5                                                                      0x502068UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50913 #define NIG_REG_MNG_PROP_HDR0_6                                                                      0x50206cUL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50914 #define NIG_REG_MNG_PROP_HDR0_7                                                                      0x502070UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The header value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50915 #define NIG_REG_MNG_PROP_HDR1_0                                                                      0x502074UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50916 #define NIG_REG_MNG_PROP_HDR1_1                                                                      0x502078UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50917 #define NIG_REG_MNG_PROP_HDR1_2                                                                      0x50207cUL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50918 #define NIG_REG_MNG_PROP_HDR1_3                                                                      0x502080UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50919 #define NIG_REG_MNG_PROP_HDR1_4                                                                      0x502084UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50920 #define NIG_REG_MNG_PROP_HDR1_5                                                                      0x502088UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50921 #define NIG_REG_MNG_PROP_HDR1_6                                                                      0x50208cUL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50922 #define NIG_REG_MNG_PROP_HDR1_7                                                                      0x502090UL //Access:RW   DataWidth:0x20  Value of proprietary header to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: BB_A0 BB_B0
50923 #define NIG_REG_MNG_TC                                                                               0x502094UL //Access:RW   DataWidth:0x3   TC to be used for management traffic.  This is used in the BMC-to-host path to BRB.  This is also used in the TX management path (when enabled by *tx_mng_tc_en).  Valid values are 0-7, since pure-LB TC cannot be used.  Chips: BB_A0 BB_B0 K2
50924 #define NIG_REG_TX_MNG_TC_EN                                                                         0x502098UL //Access:RW   DataWidth:0x1   Enable the use of TC to control the flow of TX management traffic.  Set this bit to 1 to enable the use of *mng_tc configuration to select the TC to use to pause/drain management traffic sent to the network.  Chips: BB_A0 BB_B0 K2
50925 #define NIG_REG_TX_HOST_MNG_ENABLE                                                                   0x50209cUL //Access:RW   DataWidth:0x1   Host-to-MCP path enable.  Set this bit to enable the routing of management packets from PBF interface toward MCP when the criteria for the MCP filters are met.  All packets from PBF are forwarded to the network when this bit is cleared.  Chips: BB_A0 BB_B0
50926 #define NIG_REG_TX_MNG_TIMESTAMP_PKT                                                                 0x5020a0UL //Access:RW   DataWidth:0x1   Indicate to timestamp the packet from MCP to network when *_ptp_sw_txtsen is set.  Chips: BB_A0 BB_B0 K2
50927 #define NIG_REG_BMB_PAUSE_NTWK_EN                                                                    0x5020a4UL //Access:RW   DataWidth:0x1   Enable the usage of BMB WC pause inputs to OR with others for pausing the network peer.  Chips: BB_A0 BB_B0 K2
50928 #define NIG_REG_BMB_PKT_LEN                                                                          0x5020a8UL //Access:RW   DataWidth:0x9   Maximum length of management packets, in term of the number of data cycles.  Chips: BB_A0 BB_B0 K2
50929 #define NIG_REG_BMB_FIFO_ALM_FULL_THR                                                                0x5020acUL //Access:RW   DataWidth:0x5   Almost-full threshold for BMB FIFO.  Chips: BB_A0 BB_B0 K2
50930 #define NIG_REG_TX_BMB_FIFO_EMPTY                                                                    0x5020b0UL //Access:R    DataWidth:0x1   TX BMB FIFO empty status.  Chips: BB_A0 BB_B0 K2
50931 #define NIG_REG_TX_BMB_FIFO_FULL                                                                     0x5020b4UL //Access:R    DataWidth:0x1   TX BMB FIFO full status.  Chips: BB_A0 BB_B0 K2
50932 #define NIG_REG_LB_BMB_FIFO_EMPTY                                                                    0x5020b8UL //Access:R    DataWidth:0x1   LB BMB FIFO empty status.  Chips: BB_A0 BB_B0 K2
50933 #define NIG_REG_LB_BMB_FIFO_FULL                                                                     0x5020bcUL //Access:R    DataWidth:0x1   LB BMB FIFO full status.  Chips: BB_A0 BB_B0 K2
50934 #define NIG_REG_DORQ_FIFO_ALM_FULL_THR                                                               0x5020c0UL //Access:RW   DataWidth:0x7   Almost-full threshold for DORQ FIFO.  Chips: BB_A0 BB_B0 K2
50935 #define NIG_REG_DORQ_FIFO_EMPTY                                                                      0x5020c4UL //Access:R    DataWidth:0x1   DORQ FIFO is empty..  Chips: BB_A0 BB_B0 K2
50936 #define NIG_REG_DORQ_FIFO_FULL                                                                       0x5020c8UL //Access:R    DataWidth:0x1   DORQ FIFO is full.  Chips: BB_A0 BB_B0 K2
50937 #define NIG_REG_DORQ_PKT_WAIT_SIZE                                                                   0x5020ccUL //Access:RW   DataWidth:0x5   This register specifies the received number of cycles of a DORQ packet, counting from SOP, before enqueuing the packet for transmission.  This is applicalbe to packets longer than this many cycles.  The valid values are 1 to 16.  Chips: BB_A0 BB_B0 K2
50938 #define NIG_REG_DEBUG_PORT                                                                           0x5020d0UL //Access:RW   DataWidth:0x2   Port configuration for traffic from the debug interface. 0 - send debug traffic through port 0.  1 - send debug traffic through port 1. 2 - send debug traffic through port 2 (valid  in K2 mode only).  3 - send debug traffic through port 3 (valid  in K2 mode only).  Chips: BB_A0 BB_B0 K2
50939 #define NIG_REG_DEBUG_PKT_LEN                                                                        0x5020d4UL //Access:RW   DataWidth:0x9   Maximum length of debug packets, in term of the number of data cycles.  Chips: BB_A0 BB_B0 K2
50940 #define NIG_REG_DEBUG_PKT_WAIT_SIZE                                                                  0x5020d8UL //Access:RW   DataWidth:0x8   This register specifies the received number of cycles of a debug packet, counting from SOP, before enqueuing the packet for transmission.  This is applicalbe to packets longer than this many cycles.  The valid values are 1 to 128.  Chips: BB_A0 BB_B0 K2
50941 #define NIG_REG_DEBUG_FIFO_ALM_FULL_THR                                                              0x5020dcUL //Access:RW   DataWidth:0x8   Almost-full threshold for debug traffic FIFO.  Chips: BB_A0 BB_B0 K2
50942 #define NIG_REG_DEBUG_FIFO_EMPTY                                                                     0x5020e0UL //Access:R    DataWidth:0x1   Debug traffic FIFO is empty..  Chips: BB_A0 BB_B0 K2
50943 #define NIG_REG_DEBUG_FIFO_FULL                                                                      0x5020e4UL //Access:R    DataWidth:0x1   Debug traffic FIFO is full.  Chips: BB_A0 BB_B0 K2
50944 #define NIG_REG_DEBUG_PACKET                                                                         0x502100UL //Access:WB_W DataWidth:0x108 Data register for loading debug packet to RX LLH through RBC.  The bits are mapped as follow: [255:0] data; [260:256]eop_bvalid - the number of valid bytes in the last cycle (0=all bytes are valid); [261]eop - active on the last cycle of the packet; [262]sop - active on the first cycle of the packet; [263]error - indicates error in the packet.  This should be used only when there is no RX traffic from the MAC.  Chips: BB_A0 BB_B0 K2
50945 #define NIG_REG_DEBUG_PACKET_SIZE                                                                    16
50946 #define NIG_REG_DBG_SELECT                                                                           0x502140UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
50947 #define NIG_REG_DBG_DWORD_ENABLE                                                                     0x502144UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
50948 #define NIG_REG_DBG_SHIFT                                                                            0x502148UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
50949 #define NIG_REG_DBG_FORCE_VALID                                                                      0x50214cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50950 #define NIG_REG_DBG_FORCE_FRAME                                                                      0x502150UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50951 #define NIG_REG_DBG_OUT_DATA                                                                         0x502160UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
50952 #define NIG_REG_DBG_OUT_DATA_SIZE                                                                    8
50953 #define NIG_REG_DBG_OUT_VALID                                                                        0x502180UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
50954 #define NIG_REG_DBG_OUT_FRAME                                                                        0x502184UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
50955 #define NIG_REG_RX_FC_DBG_SELECT                                                                     0x502188UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
50956 #define NIG_REG_RX_FC_DBG_DWORD_ENABLE                                                               0x50218cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
50957 #define NIG_REG_RX_FC_DBG_SHIFT                                                                      0x502190UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
50958 #define NIG_REG_RX_FC_DBG_FORCE_VALID                                                                0x502194UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50959 #define NIG_REG_RX_FC_DBG_FORCE_FRAME                                                                0x502198UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50960 #define NIG_REG_TX_FC_DBG_SELECT                                                                     0x50219cUL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
50961 #define NIG_REG_TX_FC_DBG_DWORD_ENABLE                                                               0x5021a0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
50962 #define NIG_REG_TX_FC_DBG_SHIFT                                                                      0x5021a4UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
50963 #define NIG_REG_TX_FC_DBG_FORCE_VALID                                                                0x5021a8UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50964 #define NIG_REG_TX_FC_DBG_FORCE_FRAME                                                                0x5021acUL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50965 #define NIG_REG_LB_FC_DBG_SELECT                                                                     0x5021b0UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
50966 #define NIG_REG_LB_FC_DBG_DWORD_ENABLE                                                               0x5021b4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
50967 #define NIG_REG_LB_FC_DBG_SHIFT                                                                      0x5021b8UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
50968 #define NIG_REG_LB_FC_DBG_FORCE_VALID                                                                0x5021bcUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50969 #define NIG_REG_LB_FC_DBG_FORCE_FRAME                                                                0x5021c0UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50970 #define NIG_REG_RX_FC_DBG_SELECT_PLLH                                                                0x5021c4UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
50971 #define NIG_REG_RX_FC_DBG_DWORD_ENABLE_PLLH                                                          0x5021c8UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
50972 #define NIG_REG_RX_FC_DBG_SHIFT_PLLH                                                                 0x5021ccUL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
50973 #define NIG_REG_RX_FC_DBG_FORCE_VALID_PLLH                                                           0x5021d0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50974 #define NIG_REG_RX_FC_DBG_FORCE_FRAME_PLLH                                                           0x5021d4UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50975 #define NIG_REG_TX_FC_DBG_SELECT_PLLH                                                                0x5021d8UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
50976 #define NIG_REG_TX_FC_DBG_DWORD_ENABLE_PLLH                                                          0x5021dcUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
50977 #define NIG_REG_TX_FC_DBG_SHIFT_PLLH                                                                 0x5021e0UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
50978 #define NIG_REG_TX_FC_DBG_FORCE_VALID_PLLH                                                           0x5021e4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50979 #define NIG_REG_TX_FC_DBG_FORCE_FRAME_PLLH                                                           0x5021e8UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50980 #define NIG_REG_LB_FC_DBG_SELECT_PLLH                                                                0x5021ecUL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
50981 #define NIG_REG_LB_FC_DBG_DWORD_ENABLE_PLLH                                                          0x5021f0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
50982 #define NIG_REG_LB_FC_DBG_SHIFT_PLLH                                                                 0x5021f4UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
50983 #define NIG_REG_LB_FC_DBG_FORCE_VALID_PLLH                                                           0x5021f8UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50984 #define NIG_REG_LB_FC_DBG_FORCE_FRAME_PLLH                                                           0x5021fcUL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
50985 #define NIG_REG_ECO_RESERVED                                                                         0x502200UL //Access:RW   DataWidth:0x20  Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
50986 #define NIG_REG_ECO_RESERVED_PERPORT                                                                 0x502204UL //Access:RW   DataWidth:0x10  Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
50987 #define NIG_REG_ACPI_TAG_RM                                                                          0x508000UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  L2 tag removal configuration for ACPI.  Bit mapped as follow: bit 0: 5 - L2 tags 0 to 5. Bit 6 is reserved and should be set to 0.  Bit 7 is for LLC/SNAP.  Set these bits to 1's to enable the removal of the corresponding tag when it is present in the  packet.  Clear the bit to keep the tag in the  packet.  Chips: BB_A0 BB_B0
50988 #define NIG_REG_ACPI_PROP_HDR_RM                                                                     0x508004UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  Proprietary header removal configuration for ACPI.  Set this bit to 1 to enable the removal of the header.  Clear the bit to keep the header in the  packet.  Chips: BB_A0 BB_B0
50989 #define NIG_REG_MF_GLOBAL_EN                                                                         0x508008UL //Access:RW   DataWidth:0x1   Set this bit to enable ACPI pattern matching and TCP SYN matching in multi-function mode even when the per-function outer tag matching fails.  Chips: BB_A0 BB_B0
50990 #define NIG_REG_UPON_MGMT                                                                            0x50800cUL //Access:RW   DataWidth:0x1   Set this bit to enable ACPI and TCP SYN matching even when the packet is forwarded to MCP.  Clear this bit to disable ACPI and TCP SYN matching when the packet is forwarded to MCP.  Chips: BB_A0 BB_B0
50991 #define NIG_REG_ACPI_BE_MEM                                                                          0x508080UL //Access:WB   DataWidth:0x100 This is a per-port per-PF register.  Byte enable memory for 8 ACPI patterns.  Chips: BB_A0 BB_B0
50992 #define NIG_REG_ACPI_BE_MEM_SIZE                                                                     32
50993 #define NIG_REG_ACPI_ENABLE                                                                          0x508100UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  When this bit is set  ACPI packet recognition will be enabled. This bit must not be enabled until after all other ACPI registers were configured.  Chips: BB_A0 BB_B0
50994 #define NIG_REG_ACPI_PAT_0_CRC                                                                       0x508104UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 0.  Chips: BB_A0 BB_B0
50995 #define NIG_REG_ACPI_PAT_0_LEN                                                                       0x508108UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: BB_A0 BB_B0
50996 #define NIG_REG_ACPI_PAT_1_CRC                                                                       0x50810cUL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 1.  Chips: BB_A0 BB_B0
50997 #define NIG_REG_ACPI_PAT_1_LEN                                                                       0x508110UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: BB_A0 BB_B0
50998 #define NIG_REG_ACPI_PAT_2_CRC                                                                       0x508114UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 2.  Chips: BB_A0 BB_B0
50999 #define NIG_REG_ACPI_PAT_2_LEN                                                                       0x508118UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: BB_A0 BB_B0
51000 #define NIG_REG_ACPI_PAT_3_CRC                                                                       0x50811cUL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 3.  Chips: BB_A0 BB_B0
51001 #define NIG_REG_ACPI_PAT_3_LEN                                                                       0x508120UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: BB_A0 BB_B0
51002 #define NIG_REG_ACPI_PAT_4_CRC                                                                       0x508124UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 4.  Chips: BB_A0 BB_B0
51003 #define NIG_REG_ACPI_PAT_4_LEN                                                                       0x508128UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: BB_A0 BB_B0
51004 #define NIG_REG_ACPI_PAT_5_CRC                                                                       0x50812cUL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 5.  Chips: BB_A0 BB_B0
51005 #define NIG_REG_ACPI_PAT_5_LEN                                                                       0x508130UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: BB_A0 BB_B0
51006 #define NIG_REG_ACPI_PAT_6_CRC                                                                       0x508134UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 6.  Chips: BB_A0 BB_B0
51007 #define NIG_REG_ACPI_PAT_6_LEN                                                                       0x508138UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: BB_A0 BB_B0
51008 #define NIG_REG_ACPI_PAT_7_CRC                                                                       0x50813cUL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 7.  Chips: BB_A0 BB_B0
51009 #define NIG_REG_ACPI_PAT_7_LEN                                                                       0x508140UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: BB_A0 BB_B0
51010 #define NIG_REG_TCP_SYN_ENABLE                                                                       0x508144UL //Access:RW   DataWidth:0x2   This is a per-port per-PF register.  Set bit 0 to enable wake on IPv4 TCP SYN. Set bit 1 to enable wake on IPv6 TCP SYN. These bits must not be set until after after all other registers needed for this feature are configured.  Chips: BB_A0 BB_B0 K2
51011 #define NIG_REG_TCP_SYN_IPV6_MASK                                                                    0x508148UL //Access:RW   DataWidth:0x4   This is a per-port per-PF register.  Enable bits for fields to be compared if IPv6 is present in the packet.  Bit 0 - TCP destination port; bit 1 - TCP source port; bit 2 - IP destination addresss; bit 3 - IP source address.  Set the bit to 1 to enable comparison.  Chips: BB_A0 BB_B0 K2
51012 #define NIG_REG_TCP_SYN_IPV4_MASK                                                                    0x50814cUL //Access:RW   DataWidth:0x4   This is a per-port per-PF register.  Enable bits for fields to be compared if IPv4 is present in the packet.  Bit 0 - TCP destination port; bit 1 - TCP source port; bit 2 - IP destination addresss; bit 3 - IP source address.  Set the bit to 1 to enable comparison.  Chips: BB_A0 BB_B0 K2
51013 #define NIG_REG_TCP_SYN_IPV6_SRC_PORT                                                                0x508150UL //Access:RW   DataWidth:0x10  This is a per-port per-PF register.  IPv6 TCP source port.  Chips: BB_A0 BB_B0 K2
51014 #define NIG_REG_TCP_SYN_IPV6_DST_PORT                                                                0x508154UL //Access:RW   DataWidth:0x10  This is a per-port per-PF register.  TCP IPv6 destination port.  Chips: BB_A0 BB_B0 K2
51015 #define NIG_REG_TCP_SYN_IPV4_SRC_PORT                                                                0x508158UL //Access:RW   DataWidth:0x10  This is a per-port per-PF register.  IPv4 TCP source port.  Chips: BB_A0 BB_B0 K2
51016 #define NIG_REG_TCP_SYN_IPV4_DST_PORT                                                                0x50815cUL //Access:RW   DataWidth:0x10  This is a per-port per-PF register.  TCP IPv4 destination port.  Chips: BB_A0 BB_B0 K2
51017 #define NIG_REG_TCP_SYN_IPV6_SRC_ADDR                                                                0x508160UL //Access:WB   DataWidth:0x80  This is a per-port per-PF register.  IPv6 source address.  Chips: BB_A0 BB_B0 K2
51018 #define NIG_REG_TCP_SYN_IPV6_SRC_ADDR_SIZE                                                           4
51019 #define NIG_REG_TCP_SYN_IPV6_DST_ADDR                                                                0x508170UL //Access:WB   DataWidth:0x80  This is a per-port per-PF register.  IPv6 destination address.  Chips: BB_A0 BB_B0 K2
51020 #define NIG_REG_TCP_SYN_IPV6_DST_ADDR_SIZE                                                           4
51021 #define NIG_REG_TCP_SYN_IPV4_SRC_ADDR                                                                0x508180UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  IPv4 source address.  Chips: BB_A0 BB_B0 K2
51022 #define NIG_REG_TCP_SYN_IPV4_DST_ADDR                                                                0x508184UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  IPv4 destination address.  Chips: BB_A0 BB_B0 K2
51023 #define NIG_REG_MPKT_ENABLE                                                                          0x508188UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  When this bit is set  Magic Packet recognition will be enabled. This bit must not be enabled until after after all other Magic Packet registers are configured.  Chips: BB_A0 BB_B0
51024 #define NIG_REG_MPKT_MAC_ADDR                                                                        0x508190UL //Access:WB   DataWidth:0x30  This is a per-port per-PF register.  MAC address for Magic Packet detection.  Chips: BB_A0 BB_B0
51025 #define NIG_REG_MPKT_MAC_ADDR_SIZE                                                                   2
51026 #define NIG_REG_FORCE_WOL                                                                            0x508198UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  A low-to-high transition of this bit forces a wake event.  Chips: BB_A0 BB_B0
51027 #define NIG_REG_WAKE_BUFFER                                                                          0x5081a0UL //Access:WB_R DataWidth:0x100 Read-only data from the Wake Buffer (organized as a FIFO).  Chips: BB_A0 BB_B0
51028 #define NIG_REG_WAKE_BUFFER_SIZE                                                                     8
51029 #define NIG_REG_WAKE_BUFFER_CLEAR                                                                    0x5081c0UL //Access:RW   DataWidth:0x1   Clear the Wake Buffer and Status - a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details registers and allows the wake buffer to be overwritten, thereby re-enabling pattern detection.  Chips: BB_A0 BB_B0
51030 #define NIG_REG_WAKE_INFO                                                                            0x5081c4UL //Access:R    DataWidth:0x15  Wake information register - all fields are sticky.  Bits  15:0 - PF Vector: The bit-mapped vector indicating which of the global PFs detected the wake event.  More than 1 bit may be set. Bit 16 - ACPI RCVD:  This bit is set when an ACPI packet is received. This is an OR of the results from the 8 functions. Bit 17 - MPKT:  This bit is set when a Magic packet is received. This is an OR of the results from the 8 functions. Bit 18 - TCP SYN RCVD:  This bit is set when TCP SYN packet is received. This is an OR of the results from the 8 functions. Bit 19 - FORCE RCVD:  This bit is set when force WOL event is received. This is an OR of the results from the 8 functions. Bit 20 - BUFFER NOT EMPTY:  This bit  is set when the buffer has the 'wake' packet. All fields are cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on these fields.  Chips: BB_A0 BB_B0
51031 #define NIG_REG_WAKE_PKT_LEN                                                                         0x5081c8UL //Access:R    DataWidth:0xe   Wake packet length - the actual length of the 'wake' packet, in bytes. This register is sticky and is cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on this register.  Chips: BB_A0 BB_B0
51032 #define NIG_REG_WAKE_DETAILS                                                                         0x5081ccUL //Access:R    DataWidth:0x20  Wake detail register - all fields are sticky.  Bits 7:0   - ACPI MATCH:  Per-function bit-mapped result from ACPI pattern match. Bits 15:8  - MPKT MATCH:  Per-function bit-mapped result from Magic packet pattern match. Bits 23:16 - TCP SYN MATCH:  Per-function bit-mapped result from TCP SYN match. Bits 31:24 - FORCE WOL MATCH:  Per-function bit-mapped result from force WOL match. All fields are cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on these fields.  Chips: BB_A0 BB_B0
51033 #define NIG_REG_LLH_PTP_HOST_BUF_SRC_PORT_IDEN                                                       0x508800UL //Access:WB_R DataWidth:0x50  Packet TimeSync information that is buffered in 1-deep FIFOs for the host. Source port identify field  Chips: BB_B0 K2
51034 #define NIG_REG_LLH_PTP_HOST_BUF_SRC_PORT_IDEN_SIZE                                                  4
51035 #define NIG_REG_TX_LLH_PTP_HOST_BUF_SRC_PORT_IDEN                                                    0x508810UL //Access:WB_R DataWidth:0x50  Packet TimeSync information that is buffered in 1-deep FIFO for the TX path. Source port identify field.  Chips: BB_B0 K2
51036 #define NIG_REG_TX_LLH_PTP_HOST_BUF_SRC_PORT_IDEN_SIZE                                               4
51037 #define NIG_REG_TX_UP_TS_EN                                                                          0x508820UL //Access:RW   DataWidth:0x1   TX User protocol time stamp enable  Chips: BB_B0
51038 #define NIG_REG_RX_UP_TS_EN                                                                          0x508824UL //Access:RW   DataWidth:0x1   RX User protocol time stamp enable  Chips: BB_B0
51039 #define NIG_REG_TX_PTP_ONE_STP_EN                                                                    0x508828UL //Access:RW   DataWidth:0x1   Enable TS update for one step packets in the TX path.  Chips: BB_B0 K2
51040 #define NIG_REG_RX_PTP_ONE_STP_EN                                                                    0x50882cUL //Access:RW   DataWidth:0x1   Enable one step 1588 on RX  Chips: BB_B0 K2
51041 #define NIG_REG_TX_UP_TS_ADDR_0                                                                      0x508830UL //Access:RW   DataWidth:0x20  TX User protocol address for packet classiification. It serves as source/dset mac address[47:0] or {source/dest UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]  Chips: BB_B0
51042 #define NIG_REG_TX_UP_TS_ADDR_1                                                                      0x508834UL //Access:RW   DataWidth:0x10  TX User protocol address for packet classiification. It serves as source/dset mac address[47:0] or {source/dest UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]  Chips: BB_B0
51043 #define NIG_REG_RX_UP_TS_ADDR_0                                                                      0x508838UL //Access:RW   DataWidth:0x20  RX User protocol address for packet classiification. It serves as source/dset mac address[47:0] or {source/dest UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]  Chips: BB_B0
51044 #define NIG_REG_RX_UP_TS_ADDR_1                                                                      0x50883cUL //Access:RW   DataWidth:0x10  RX User protocol address for packet classiification. It serves as source/dset mac address[47:0] or {source/dest UDP port[15:0], source/dest IPV4 address[31:0]} or ethernet type[15:0] or IPV4OptionNumber[7:0]  Chips: BB_B0
51045 #define NIG_REG_TX_UP_TS_PARAM_MASK                                                                  0x508840UL //Access:RW   DataWidth:0x6   TX user protocol classification mask bits bit 0: mask_dstMac bit 1: mask_srcMac bit 2: mask_dstIPv4 bit 3: mask_srcIPv4 bit 4: mask_dstUDP bit 5: mask_srcUDP  Chips: BB_B0
51046 #define NIG_REG_RX_UP_TS_PARAM_MASK                                                                  0x508844UL //Access:RW   DataWidth:0x6   RX user protocol classification mask bits bit 0: mask_dstMac bit 1: mask_srcMac bit 2: mask_dstIPv4 bit 3: mask_srcIPv4 bit 4: mask_dstUDP bit 5: mask_srcUDP  Chips: BB_B0
51047 #define NIG_REG_TX_ENABLE_UP_RULES                                                                   0x508848UL //Access:RW   DataWidth:0x5   TX enable bits for user protocol classification rules bit 0: MAC address enable bit 1: IPV4 + UDP enable bit 2: Ethernet type enable bit 3: IPV4 option enable bit 4: Record time stamp bit from PBF enable  Chips: BB_B0
51048 #define NIG_REG_RX_ENABLE_UP_RULES                                                                   0x50884cUL //Access:RW   DataWidth:0x5   RX enable bits for user protocol classification rules bit 0: MAC address enable bit 1: IPV4 + UDP enable bit 2: Ethernet type enable bit 3: IPV4 option enable bit 4: Record time stamp bit from PBF enable  Chips: BB_B0
51049 #define NIG_REG_ADD_FREECNT_OFFSET                                                                   0x508850UL //Access:RW   DataWidth:0x1   This bit defines whether to add offset and jitter of the timestamp to the returned timestamp from the MAC This bit is shared by TX and RX paths.  Chips: BB_B0 K2
51050 #define NIG_REG_UP_TS_INSERT_EN                                                                      0x508854UL //Access:RW   DataWidth:0x1   Enable for on wire timestamp insertion for user protocol packets  Chips: BB_B0
51051 #define NIG_REG_PM_TIMER_SELECT                                                                      0x508858UL //Access:RW   DataWidth:0x3   Selector for the 48 bits timer which is sent to the port macro. 0: free running counter. [1..4]: synchronized counter for port [1..4]  Chips: BB_B0 K2
51052 #define NIG_REG_TS_FOR_SEMI_SELECT                                                                   0x50885cUL //Access:RW   DataWidth:0x3   Selects which timer will be sent to SEMI/MCP 0: free running counter. [1..4]: synchronized counter for port [1..4]  Chips: BB_B0 K2
51053 #define NIG_REG_USER_ONE_STEP_TYPE                                                                   0x508860UL //Access:RW   DataWidth:0x3   Define the required operation for user protocol packets: 0: NO_USER_ONE_STEP ? no change to outgoing packet 1: ETHERTYPE ? insert timestamp if EtherType filter had a hit 2: UDP ? insert timestamp to UDP packet and regenerate checksum 3: TRAILER ? insert timestamp to packet trailer 4: IPv4_STANDARD ? insert timestamp using standard IPv4 Timestamp option. In this mode 32-bit timestamp with set_msb is used  Chips: BB_B0
51054 #define NIG_REG_TXOSTS_SIGNEXT                                                                       0x508864UL //Access:RW   DataWidth:0x1   sign extension indication for the MAC.  Chips: BB_B0
51055 #define NIG_REG_UP_TS_OFFSET                                                                         0x508868UL //Access:RW   DataWidth:0x8   Correction field offset for user protocol packets. the offset is relative to the configured value field in user_one_step_type.  Chips: BB_B0
51056 #define NIG_REG_TS_SHIFT                                                                             0x50886cUL //Access:RW   DataWidth:0x5   Global timestamp shift for the free running counter. Legal values are 0-16  Chips: BB_B0
51057 #define NIG_REG_TS_OUTPUT_ENABLE_PDA                                                                 0x508870UL //Access:RW   DataWidth:0x1   Output enable for TS passed to the Port Macro  Chips: BB_B0 K2
51058 #define NIG_REG_TS_OUTPUT_ENABLE_HV                                                                  0x508874UL //Access:RW   DataWidth:0x1   Output enable for TS passed to the Port Macro  Chips: BB_B0 K2
51059 #define NIG_REG_USER_ONE_STEP_32                                                                     0x508878UL //Access:RW   DataWidth:0x1   Global parameter which defines that 32 bits timestamp will be inserted to the packet instead of 48 bits  Chips: BB_B0
51060 #define NIG_REG_LLH_UP_BUF_SEQID                                                                     0x50887cUL //Access:RW   DataWidth:0x15  RX User protocol Packet information that is buffered in 1-deep FIFOs.  Bits [15:0] return the sequence ID of the packet which is set by free running counter for user protocol packets.  Bits [19:16] indicate PF ID Bit 20 indicates the validity of the data in the buffer.  Writing a 1 to bit 16 will clear the buffer.  Chips: BB_B0
51061 #define NIG_REG_LLH_UP_BUF_TIMESTAMP                                                                 0x508880UL //Access:WB_R DataWidth:0x40  RX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp field  Chips: BB_B0
51062 #define NIG_REG_LLH_UP_BUF_TIMESTAMP_SIZE                                                            2
51063 #define NIG_REG_LLH_UP_BUF_SRC_ADDR                                                                  0x508888UL //Access:WB_R DataWidth:0x30  RX user protocol packet information that is buffered in 1-deep FIFO. Source address field  Chips: BB_B0
51064 #define NIG_REG_LLH_UP_BUF_SRC_ADDR_SIZE                                                             2
51065 #define NIG_REG_TX_LLH_UP_BUF_SEQID                                                                  0x508890UL //Access:RW   DataWidth:0x15  TX User protocol Packet information that is buffered in 1-deep FIFOs.  Bits [15:0] return the sequence ID of the packet which is set by free running counter for user protocol packets.  Bits [19:16] indicate PF ID Bit 20 indicates the validity of the data in the buffer.  Writing a 1 to bit 16 will clear the buffer.  Chips: BB_B0
51066 #define NIG_REG_TX_LLH_UP_BUF_TIMESTAMP                                                              0x508898UL //Access:WB_R DataWidth:0x40  TX user protocol Packet information that is buffered in 1-deep FIFO. Timestamp field  Chips: BB_B0
51067 #define NIG_REG_TX_LLH_UP_BUF_TIMESTAMP_SIZE                                                         2
51068 #define NIG_REG_LLH_UP_BUF_DST_ADDR                                                                  0x5088a0UL //Access:WB_R DataWidth:0x30  RX user protocol packet information that is buffered in 1-deep FIFO. Destination address field  Chips: BB_B0
51069 #define NIG_REG_LLH_UP_BUF_DST_ADDR_SIZE                                                             2
51070 #define NIG_REG_TSGEN_FREE_CNT_VALUE_LSB                                                             0x5088a8UL //Access:RW   DataWidth:0x20  This register contains the 32 bit LSB of the configured free counter. The value is written to the HW when writing to the MSB register  Chips: BB_B0 K2
51071 #define NIG_REG_TSGEN_FREE_CNT_VALUE_MSB                                                             0x5088acUL //Access:RW   DataWidth:0x20  This register contains the 32 bit MSB of the configured free counter. Writing to this register also updatea HW value with MSB and LSB registers' value  Chips: BB_B0 K2
51072 #define NIG_REG_TSGEN_OFFSET_VALUE_LSB                                                               0x5088b0UL //Access:RW   DataWidth:0x20  This register contains the 32 bit LSB of the offset value. This value is added to the Free Running Counter to create the synchronized time. The value is written to the HW when writing to the MSB register.  Chips: BB_B0 K2
51073 #define NIG_REG_TSGEN_OFFSET_VALUE_MSB                                                               0x5088b4UL //Access:RW   DataWidth:0x20  This register contains the 32 bit MSB of the offset value. This value is added to the Free Running Counter to create the synchronized time. Writing to this register also updatea HW value with MSB and LSB registers' value. Read: Since offset width is 64 bits, tsgen_offset_value_lsb should be read first in order to latch the offset's value.  Chips: BB_B0 K2
51074 #define NIG_REG_TSGEN_FREECNT_LSB                                                                    0x5088b8UL //Access:R    DataWidth:0x20  This register contains the 32 bit LSB of the free running counter  Chips: BB_B0 K2
51075 #define NIG_REG_TSGEN_FREECNT_MSB                                                                    0x5088bcUL //Access:R    DataWidth:0x20  This register contains the 32 bit MSB of the free running counter. Since free counter width is 64 bits, tsgen_freecnt_lsb should be read first in order to latch the counter's value.  Chips: BB_B0 K2
51076 #define NIG_REG_TSGEN_SYNC_TIME_LSB                                                                  0x5088c0UL //Access:R    DataWidth:0x20  This register contains the 32 bit LSB of the synchronized time.  Chips: BB_B0 K2
51077 #define NIG_REG_TSGEN_SYNC_TIME_MSB                                                                  0x5088c4UL //Access:R    DataWidth:0x20  This register contains the 32 bit MSB of the synchronized time. Since synchronized time width is 64 bits, tsgen_sync_time_lsb should be read first in order to latch the counter's value.  Chips: BB_B0 K2
51078 #define NIG_REG_TSGEN_HW_PPS_EN                                                                      0x5088c8UL //Access:RW   DataWidth:0x1   In this mode,  Start time, high period and low period are all configurable, and when asserting this bit the PPS starts to toggle accoring to HW machine  Chips: BB_B0 K2
51079 #define NIG_REG_TSGEN_SW_PPS_EN                                                                      0x5088ccUL //Access:RW   DataWidth:0x1   In this mode,  whenever the synchronized time reaches a configurable value, PPS signal is toggled  Chips: BB_B0 K2
51080 #define NIG_REG_TSGEN_PPS_HIGH_TIME                                                                  0x5088d0UL //Access:RW   DataWidth:0x20  Duration of high PPS period. Valid when tsgen_hw_pps_en is enabled  Chips: BB_B0 K2
51081 #define NIG_REG_TSGEN_PPS_LOW_TIME                                                                   0x5088d4UL //Access:RW   DataWidth:0x20  Duration of low PPS period. Valid when tsgen_hw_pps_en is enabled  Chips: BB_B0 K2
51082 #define NIG_REG_TSGEN_RST_DRIFT_CNTR                                                                 0x5088d8UL //Access:RW   DataWidth:0x1   This is a level indication to reset drift counter's value  Chips: BB_B0 K2
51083 #define NIG_REG_TSGEN_DRIFT_CNTR_CONF                                                                0x5088dcUL //Access:RW   DataWidth:0x20  This register should be configure only when tsgen_rst_drift_cntr is 1. Bits 27:0 specify how many 16 nsec time quantas to wait before making a Drift adjustment to the TSGEN_OFFSET_T0 register.  Bits 30:28 specify how many ns to add or subtract from the TSGEN_OFFSET_T0 register when making a Drift adjustment.  Bit 31 controls whether the Adjustment_Value is added (1'b1) or subtracted (1'b0) from the TSGEN_OFFSET_T0 register when making a Drift adjustment.  Chips: BB_B0 K2
51084 #define NIG_REG_TSGEN_TSIO_OEB                                                                       0x5088e0UL //Access:RW   DataWidth:0x4   Bits 3:0 are the active-low output enables for the TSIO Output pins 3:0.  Chips: BB_B0 K2
51085 #define NIG_REG_TSGEN_TSIO_OUT_PULSE                                                                 0x5088e4UL //Access:R    DataWidth:0x4   Bits 3:0 reflect pulse value for the TSIO Output pins 3:0.  Chips: BB_B0 K2
51086 #define NIG_REG_EDPM_FIFO_FULL_THRESH                                                                0x5088e8UL //Access:RW   DataWidth:0x7   When EDPM FIFO data bytes occupancy is higher than this threshold nig_dorq_edpm_en is de-asserted. The value is configured in 32 bytes multiples.  Chips: BB_B0 K2
51087 #define NIG_REG_MLD_MSG_TYPE                                                                         0x5088ecUL //Access:RW   DataWidth:0x8   This field sets message type value in ICMP header to identify MLD packets  Chips: BB_B0
51088 #define NIG_REG_ROCE_DUPLICATE_TO_HOST                                                               0x5088f0UL //Access:RW   DataWidth:0x3   This field is relevant to ROCE/RROCE: bit 0 marks that packet should be duplicated to host and Storm when BTH opcode equals bth_hdr_flow_ctrl_opcode_1. bit 1 marks that packet should be duplicated to host and Storm when BTH opcode equals bth_hdr_flow_ctrl_opcode_2. bit 2 marks than packet should be duplicated to host and Storm when (ECN == 2'b11).  Chips: BB_B0 K2
51089 #define NIG_REG_DEFAULT_ENGINE_ID_SEL                                                                0x5088f4UL //Access:RW   DataWidth:0x2   This field selects engine ID in case that PF classification fails: 0: Use engine 0. 1: Use engine 1. 2/3: Use connection based classification.  Chips: BB_B0 K2
51090 #define NIG_REG_DSCP_TO_TC_MAP_ENABLE                                                                0x5088f8UL //Access:RW   DataWidth:0x1   This field enables the feature that maps DSCP to TC in case that there is no TC in one of the L2 tags  Chips: BB_B0 K2
51091 #define NIG_REG_PPF_TO_ENGINE_SEL                                                                    0x508900UL //Access:RW   DataWidth:0x4   This field maps Port PF (PPF) to engine selection for ROCE/RROCE packets: Bits [1:0] define decision for ROCE/RROCE packets. Bits [3:2] define decision for other packets 0: use engine 0 1: use engine 1 2/3: use connection based classification  Chips: BB_B0 K2
51092 #define NIG_REG_PPF_TO_ENGINE_SEL_SIZE                                                               8
51093 #define NIG_REG_DSCP_TO_TC_MAP                                                                       0x508a00UL //Access:RW   DataWidth:0x6   This field maps (ipv4_tos >> 2) 6 bits to 6 bits: bits 5:3 - priority bits 2:0 - TC This configuration is used when there is no priority field in one of the L2 headers  Chips: BB_B0 K2
51094 #define NIG_REG_DSCP_TO_TC_MAP_SIZE                                                                  64
51095 #define NIG_REG_VXLAN_ZERO_UDP_IGNORE                                                                0x508b00UL //Access:RW   DataWidth:0x1   This field defines whether to ignore zero UDP value for VXLAN  Chips: BB_B0 K2
51096 #define NIG_REG_NGE_ZERO_UDP_IGNORE                                                                  0x508b04UL //Access:RW   DataWidth:0x1   This field defines whether to ignore zero UDP value for NGE  Chips: BB_B0 K2
51097 #define NIG_REG_RROCE_ZERO_UDP_IGNORE                                                                0x508b08UL //Access:RW   DataWidth:0x1   This field defines whether to ignore zero UDP value for RROCE  Chips: BB_B0 K2
51098 #define NIG_REG_RROCE_PORT                                                                           0x508b0cUL //Access:RW   DataWidth:0x10  This field defines UDP destination port number of RROCE  Chips: BB_B0 K2
51099 #define NIG_REG_ACPI_TAG_REMOVE                                                                      0x508b10UL //Access:RW   DataWidth:0x8   This is a per-port register  L2 tag removal configuration for ACPI.  Bit mapped as follow: bit 0: 5 - L2 tags 0 to 5. Bit 6 is reserved and should be set to 0.  Bit 7 is for LLC/SNAP.  Set these bits to 1's to enable the removal of the corresponding tag when it is present in the  packet.  Clear the bit to keep the tag in the  packet.  Chips: BB_B0
51100 #define NIG_REG_ACPI_PROP_HDR_REMOVE                                                                 0x508b14UL //Access:RW   DataWidth:0x1   This is a per-port register.  Proprietary header removal configuration for ACPI.  Set this bit to 1 to enable the removal of the header.  Clear the bit to keep the header in the  packet.  Chips: BB_B0
51101 #define NIG_REG_CHECK_ETH_CRC                                                                        0x508b18UL //Access:RW   DataWidth:0x1   This is a per-port register.  When enabled, NIG will check Ethernet CRC in the packet and update error indication before transferring it to BRB/BMB/Storm  Chips: BB_B0
51102 #define NIG_REG_RM_ETH_CRC                                                                           0x508b1cUL //Access:RW   DataWidth:0x1   This is a per-port register.  When enabled, NIG will remove Ethernet CRC from the packet before transferring it to BRB/BMB/Storm  Chips: BB_B0
51103 #define NIG_REG_ADD_ETH_CRC                                                                          0x508b20UL //Access:RW   DataWidth:0x1   This is a per-port register.  When enabled, it indicates that the CNIG will add ethernet CRC to the packet. In that case, when the last cycle of the packet to the CNIG contains more than 28 valid bytes, a dead cycle will be inserted before the next packet in order to allow the CNIG time to add the CRC.  Chips: BB_B0 K2
51104 #define NIG_REG_CORRUPT_ETH_CRC                                                                      0x508b24UL //Access:RW   DataWidth:0x1   This is a per-port register.  When enabled, NIG will corrupt ethernet CRC for packets which are received from BTB with error indication or are classified by the NIG as packets which should be transmitted with errors  Chips: BB_B0
51105 #define NIG_REG_NGE_IP_ENABLE                                                                        0x508b28UL //Access:RW   DataWidth:0x1   This is a per-port register.  Enables NGE port matching during UDP header parsing when the encapsulated header is IP.  Chips: BB_B0 K2
51106 #define NIG_REG_NGE_ETH_ENABLE                                                                       0x508b2cUL //Access:RW   DataWidth:0x1   This is a per-port register. Enables NGE port matching during UDP header parsing when the encapsulated header is Ethernet.  Chips: BB_B0 K2
51107 #define NIG_REG_NGE_COMP_VER                                                                         0x508b30UL //Access:RW   DataWidth:0x1   This is a per-port register.  Perform NGE version match to 2?b0  Chips: BB_B0 K2
51108 #define NIG_REG_NGE_ETH_TYPE                                                                         0x508b34UL //Access:RW   DataWidth:0x10  This is a per-port register.  Next protocol value to be used for Ethernet in NGE header  Chips: BB_B0 K2
51109 #define NIG_REG_NGE_PORT                                                                             0x508b38UL //Access:RW   DataWidth:0x10  This is a per-port register. Destination port value used to designate a NGE header following the UDP header.  Matching can only occur when nge_ip_enable or nge_eth_enable are set.  Chips: BB_B0 K2
51110 #define NIG_REG_LLH_LB_TC_REMAP                                                                      0x508b3cUL //Access:RW   DataWidth:0x18  This is a per-port register which defines mapping of TC from the received TC to the TC sent to the BRB. bits 2:0: TC 0 bits 5:3: TC 1 ... bits 23:21: TC 7  Chips: BB_B0 K2
51111 #define NIG_REG_BTH_HDR_FLOW_CTRL_OPCODE_1                                                           0x508b40UL //Access:RW   DataWidth:0x8   This is the first opcode in the BTH header for flow control packet identification.  Chips: BB_B0 K2
51112 #define NIG_REG_BTH_HDR_FLOW_CTRL_OPCODE_2                                                           0x508b44UL //Access:RW   DataWidth:0x8   This is the second opcode in the BTH header for flow control packet identification.  Chips: BB_B0 K2
51113 #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2                                                               0x508b48UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_B0 K2
51114     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_MLD                             (0x1<<0) // Mask bit for forwarding IPV6 MLD (configurable MLD MsgType) packets to MCP.
51115     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_MLD_SHIFT                       0
51116     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI                      (0x1<<1) // Mask bit for forwarding IPv6 Neighbor solicitation packets to MCP.
51117     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI_SHIFT                1
51118     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER                       (0x1<<2) // Mask bit for forwarding IPv6 DHCP server packets to MCP.
51119     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER_SHIFT                 2
51120     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT                       (0x1<<3) // Mask bit for forwarding DCHPv4 client packets to MCP.
51121     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT_SHIFT                 3
51122     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER                       (0x1<<4) // Mask bit for forwarding DHCP V4 packets to MCP.
51123     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER_SHIFT                 4
51124     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC6                                 (0x1<<5) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_6 to MCP.
51125     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC6_SHIFT                           5
51126     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC7                                 (0x1<<6) // Mask bit for forwarding packets with the MAC destination address  matching *llh*_dest_mac_7 to MCP.
51127     #define NIG_REG_RX_LLH_NCSI_MCP_MASK_2_RX_LLH_NCSI_MCP_MASK_MAC7_SHIFT                           6
51128 #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2                                                               0x508b4cUL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0 K2
51129     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_MLD                             (0x1<<0) // Mask bit for forwarding unicast IPv6 MLD (Configurable MsgType) packets to MCP.
51130     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_MLD_SHIFT                       0
51131     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI                      (0x1<<1) // Mask bit for forwarding IPv6 neighbor solicitation packets to MCP.
51132     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_IPV6_NEI_SOLICI_SHIFT                1
51133     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER                       (0x1<<2) // Mask bit for forwarding DHCP V6 server packets to MCP.
51134     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V6_SERVER_SHIFT                 2
51135     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT                       (0x1<<3) // Mask bit for forwarding DHCP V4 client packets to MCP.
51136     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_CLIENT_SHIFT                 3
51137     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER                       (0x1<<4) // Mask bit for forwarding DHCP V4 server packets to MCP.
51138     #define NIG_REG_TX_LLH_NCSI_MCP_MASK_2_TX_LLH_NCSI_MCP_MASK_DHCP_V4_SERVER_SHIFT                 4
51139 #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2                                                        0x508b50UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_B0 K2
51140     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLD               (0x1<<0) // Mask bit for not forwarding IPv6 MLD (Configurable MsgType) packets to the host.
51141     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_MLD_SHIFT         0
51142     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_NEI_SOLICI        (0x1<<1) // Mask bit for not forwarding IPv6 neighbor solicitation packets to the host.
51143     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_IPV6_NEI_SOLICI_SHIFT  1
51144     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_SERVER         (0x1<<2) // Mask bit for not forwarding DHCP V6 server packets to the host.
51145     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V6_SERVER_SHIFT   2
51146     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_CLIENT         (0x1<<3) // Mask bit for not forwarding DHCP V4 client packets to the host.
51147     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_CLIENT_SHIFT   3
51148     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_SERVER         (0x1<<4) // Mask bit for not forwarding DHCP V4 server packets to the host.
51149     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_DHCP_V4_SERVER_SHIFT   4
51150     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC6                   (0x1<<5) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_6 to the host.
51151     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC6_SHIFT             5
51152     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC7                   (0x1<<6) // Mask bit for not forwarding packets with the MAC destination address  matching *llh*_dest_mac_7 to the host.
51153     #define NIG_REG_RX_LLH_NCSI_BRB_DNTFWD_MASK_2_RX_LLH_NCSI_BRB_DNTFWD_MASK_MAC7_SHIFT             6
51154 #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2                                                       0x508b54UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0 K2
51155     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLD             (0x1<<0) // Mask bit for not forwarding IPv6 MLD (Configurable MsgType) packets to the network.
51156     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_MLD_SHIFT       0
51157     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_NEI_SOLICI      (0x1<<1) // Mask bit for not forwarding IPv6 neighbor solicitation packets to the network.
51158     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_IPV6_NEI_SOLICI_SHIFT 1
51159     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_SERVER       (0x1<<2) // Mask bit for not forwarding DHCP V6 server packets to the network.
51160     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V6_SERVER_SHIFT 2
51161     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_CLIENT       (0x1<<3) // Mask bit for not forwarding DHCP V4 client packets to the network.
51162     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_CLIENT_SHIFT 3
51163     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_SERVER       (0x1<<4) // Mask bit for not forwarding DHCP V4 server packets to the network.
51164     #define NIG_REG_TX_LLH_NCSI_NTWK_DNTFWD_MASK_2_TX_LLH_NCSI_NTWK_DNTFWD_MASK_DHCP_V4_SERVER_SHIFT 4
51165 #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2                                                              0x508b58UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0 K2
51166     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_MLD                           (0x1<<0) // Mask bit for forwarding IPv6 MLD (Configurable MsgType) packets to the network.
51167     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_MLD_SHIFT                     0
51168     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_NEI_SOLICI                    (0x1<<1) // Mask bit for forwarding IPv6 neighbor solicitation packets to the network.
51169     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_IPV6_NEI_SOLICI_SHIFT              1
51170     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_SERVER                     (0x1<<2) // Mask bit for forwarding DHCP V6 server packets to the network.
51171     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V6_SERVER_SHIFT               2
51172     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_CLIENT                     (0x1<<3) // Mask bit for forwarding DHCP V4 client packets to the network.
51173     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_CLIENT_SHIFT               3
51174     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_SERVER                     (0x1<<4) // Mask bit for forwarding DHCP V4 server packets to the network.
51175     #define NIG_REG_TX_LLH_NCSI_NTWK_MASK_2_TX_LLH_NCSI_NTWK_MASK_DHCP_V4_SERVER_SHIFT               4
51176 #define NIG_REG_DBGMUX_OVFLW_IND_EN                                                                  0x508b5cUL //Access:RW   DataWidth:0x1   This is a Global register.  When this bit is enabled, instead of sending frame[0] from dbgmux, NIG will set an indication that some of the entries to the debug mux Were not written as the FIFO was full. This indication will be valid In the next entry which will be written to the FIFO.  Chips: BB_B0 K2
51177 #define NIG_REG_TIMER_COUNTER                                                                        0x508b60UL //Access:R    DataWidth:0x20  This fields reflects 32 lower bits value of the pause too long timer.  Chips: BB_B0 K2
51178 #define NIG_REG_LB_GNT_FIFO_EMPTY                                                                    0x508b64UL //Access:R    DataWidth:0x1   LB GNT FIFO empty status.  Chips: BB_B0 K2
51179 #define NIG_REG_LB_GNT_FIFO_FULL                                                                     0x508b68UL //Access:R    DataWidth:0x1   LB GNT FIFO full status.  Chips: BB_B0 K2
51180 #define NIG_REG_RX_PARITY_ERR                                                                        0x508b6cUL //Access:R    DataWidth:0x3   parity error status. Indicating the source of the parity error  Chips: BB_B0 K2
51181 #define NIG_REG_TX_PARITY_ERR                                                                        0x508b70UL //Access:R    DataWidth:0x7   parity error status. Indicating the source of the parity error  Chips: BB_B0 K2
51182 #define NIG_REG_LB_PARITY_ERR                                                                        0x508b74UL //Access:R    DataWidth:0x6   parity error status. Indicating the source of the parity error  Chips: BB_B0 K2
51183 #define NIG_REG_TX_PARITY_ERROR_CLOSE_EGRESS                                                         0x508b78UL //Access:RW   DataWidth:0x1   When this bit is set and there is a parity error on the Tranmit data path, the data to the CNIG will be discarded.  Chips: BB_B0 K2
51184 #define NIG_REG_TX_PARITY_ERROR_TIMER                                                                0x508b7cUL //Access:RW   DataWidth:0x8   This field defines the amount of time that the interface to the CNIG will be closed in case a parity error occured in the transmit data path.  Chips: BB_B0 K2
51185 #define NIG_REG_TX_ARB_CLIENT_0_MAP                                                                  0x508b80UL //Access:RW   DataWidth:0x4   This field defines the mapping of the DORQ request to one of the credit reisters. This enables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.  Chips: BB_B0 K2
51186 #define NIG_REG_TX_ARB_CLIENT_1_MAP                                                                  0x508b84UL //Access:RW   DataWidth:0x4   This field defines the mapping of the management request to one of the credit reisters. This enables credit sharing with one of the BTB TCs. 0: DORQ. 1: MNG. 2: Debug. 3: N/A. 4-11: BTB per TC.  Chips: BB_B0 K2
51187 #define NIG_REG_LB_ARB_CLIENT_0_MAP                                                                  0x508b88UL //Access:RW   DataWidth:0x4   This field defines the mapping of the management request to one of the credit reisters. This enables credit sharing with one of the BTB TCs. 0:   MNG. 1-8: BTB per TC. 9:   BTB pure LB.  Chips: BB_B0 K2
51188 #define NIG_REG_TX_INHIBIT_BMB_ARB_EN                                                                0x508b8cUL //Access:RW   DataWidth:0x1   This bit inhibits sending more than one outstanding packet request to the BMB until the last data of the current granted packet is received.  Chips: BB_B0 K2
51189 #define NIG_REG_LB_INHIBIT_BMB_ARB_EN                                                                0x508b90UL //Access:RW   DataWidth:0x1   This bit inhibits sending more than one outstanding packet request to the BMB until the last data of the current granted packet is received.  Chips: BB_B0 K2
51190 #define NIG_REG_TX_TDM_0_ENABLE                                                                      0x509000UL //Access:RW   DataWidth:0x1   When this bit is configured to 1, NIG trasmits ports 0 and 1 data in TDM manner. If 0, then NIG transmits only port 0 data.  Chips: K2
51191 #define NIG_REG_TX_TDM_1_ENABLE                                                                      0x509004UL //Access:RW   DataWidth:0x1   When this bit is configured to 1, NIG trasmits ports 2 and 2 data in TDM manner. If 0, then NIG transmits only port 2 data.  Chips: K2
51192 #define NIG_REG_TSGEN_FREECNT_UPDATE                                                                 0x509008UL //Access:RW   DataWidth:0x3   Writing to this register: Bit 0: resets the value of the free running counter. Bit 1: pauses the auto increment of the free running counter. Bit 2: updates the value of the free running counter from tsgen_free_cnt_value_msb and tsgen_free_cnt_value_lsb fields.  Chips: K2
51193 #define NIG_REG_TSGEN_PPS_OUT_SEL_MASK_0                                                             0x50900cUL //Access:RW   DataWidth:0x2   This register selects which timer will be used as the source to PPS logic of nig_ifmux_tsio_0_out.  Chips: K2
51194 #define NIG_REG_TSGEN_PPS_OUT_SEL_MASK_1                                                             0x509010UL //Access:RW   DataWidth:0x2   This register selects which timer will be used as the source to PPS logic of nig_ifmux_tsio_1_out.  Chips: K2
51195 #define NIG_REG_TSGEN_PPS_OUT_SEL_MASK_2                                                             0x509014UL //Access:RW   DataWidth:0x2   This register selects which timer will be used as the source to PPS logic of nig_ifmux_tsio_2_out.  Chips: K2
51196 #define NIG_REG_TSGEN_PPS_OUT_SEL_MASK_3                                                             0x509018UL //Access:RW   DataWidth:0x2   This register selects which timer will be used as the source to PPS logic of nig_ifmux_tsio_3_out.  Chips: K2
51197 #define NIG_REG_TSGEN_TSIO_IN_SEL_MASK                                                               0x50901cUL //Access:RW   DataWidth:0x4   This register selects which TSIO Input signals are used to latch the synchronized time for the per port timer.  Chips: K2
51198 #define NIG_REG_TSGEN_TSIO_IN_SEL_POL                                                                0x509020UL //Access:RW   DataWidth:0x1   This register selects the polarity of TSIO signals. 1: active high. 0: active low  Chips: K2
51199 #define NIG_REG_TSGEN_TSIO_IN_VAL                                                                    0x509024UL //Access:R    DataWidth:0x4   This register reflects the value of the TSIN pins.  Chips: K2
51200 #define NIG_REG_TSGEN_TSIO_IN_LATCHED_VALUE                                                          0x509028UL //Access:WB_R DataWidth:0x40  This register reflects the value of the Timestamp when the it is latched by input pins.  Chips: K2
51201 #define NIG_REG_TSGEN_TSIO_IN_LATCHED_VALUE_SIZE                                                     2
51202 #define NIG_REG_TSGEN_TSIO_OUT_NEXT_TOGGLE_TIME                                                      0x509030UL //Access:WB_R DataWidth:0x40  This register reflects the timestamp of the next PPS toggle.  Chips: K2
51203 #define NIG_REG_TSGEN_TSIO_OUT_NEXT_TOGGLE_TIME_SIZE                                                 2
51204 #define NIG_REG_TSGEN_PPS_START_TIME_0                                                               0x509038UL //Access:RW   DataWidth:0x20  This register reflects the start time of PPS.  Chips: K2
51205 #define NIG_REG_TSGEN_PPS_START_TIME_1                                                               0x50903cUL //Access:RW   DataWidth:0x20  This register reflects the start time of PPS.  Chips: K2
51206 #define NIG_REG_PTP_LATCH_OSTS_PKT_TIME                                                              0x509040UL //Access:RW   DataWidth:0x1   This bit enables time stamp latching for one step PTP packets.  Chips: K2
51207 #define NIG_REG_PTP_LATCH_SW_OSTS_PKT_TIME                                                           0x509044UL //Access:RW   DataWidth:0x1   This bit enables time stamp latching for one step PTP packets with RECORD_TIME_STAMP bit from BTB/PBF on. This feature is enabled when ptp_sw_txtsen is 1.  Chips: K2
51208 #define NIG_REG_PTP_UPDATE_SW_OSTS_PKT_TIME                                                          0x509048UL //Access:RW   DataWidth:0x1   This bit enables correction field update for one step PTP packets with RECORD_TIME_STAMP bit from BTB/PBF on. This feature is enabled when ptp_sw_txtsen is 1.  Chips: K2
51209 #define NIG_REG_TS_FOR_PXP_SELECT                                                                    0x50904cUL //Access:RW   DataWidth:0x3   Selects which timer will be sent to PXP 0: free running counter. [1..4]: synchronized counter for port [1..4]  Chips: K2
51210 #define NIG_REG_PTM_TIME_LATCH                                                                       0x509050UL //Access:WB_R DataWidth:0x40  When this register is read, it reflects the latched time at that moment.  Chips: K2
51211 #define NIG_REG_PTM_TIME_LATCH_SIZE                                                                  2
51212 #define NIG_REG_LLH_DEST_MAC_6_0                                                                     0x509058UL //Access:RW   DataWidth:0x20  Destination MAC address 6.  LLH will look for this address in all incoming packets.  Chips: K2
51213 #define NIG_REG_LLH_DEST_MAC_6_1                                                                     0x50905cUL //Access:RW   DataWidth:0x10  Destination MAC address 6.  LLH will look for this address in all incoming packets.  Chips: K2
51214 #define NIG_REG_LLH_DEST_MAC_7_0                                                                     0x509060UL //Access:RW   DataWidth:0x20  Destination MAC address 7.  LLH will look for this address in all incoming packets.  Chips: K2
51215 #define NIG_REG_LLH_DEST_MAC_7_1                                                                     0x509064UL //Access:RW   DataWidth:0x10  Destination MAC address 7.  LLH will look for this address in all incoming packets.  Chips: K2
51216 #define NIG_REG_MPA_MUL_PDU_CRC_CALC_EN                                                              0x509068UL //Access:RW   DataWidth:0x1   This bit selects whether to use the MPA CRC calculation on one fully contained PDU (legacy mode - 0) or on multiple PDUs (1).  Chips: K2
51217 #define BMB_REG_HW_INIT_EN                                                                           0x540004UL //Access:RW   DataWidth:0x2   Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers will be done by HW.  Bit 1 - if this bit is set then initialization of BIG RAM will be done by HW. Both bits will be reset by HW when initialization is finished.  Chips: BB_A0 BB_B0 K2
51218 #define BMB_REG_INIT_DONE                                                                            0x540008UL //Access:R    DataWidth:0x2   Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers are finished by HW.  Bit 1 - if this bit is set then initialization of BIG RAM is finished by HW.  Chips: BB_A0 BB_B0 K2
51219 #define BMB_REG_START_EN                                                                             0x54000cUL //Access:RW   DataWidth:0x1   This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.  Chips: BB_A0 BB_B0 K2
51220 #define BMB_REG_INT_STS_0                                                                            0x5400c0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51221     #define BMB_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
51222     #define BMB_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
51223     #define BMB_REG_INT_STS_0_RC_PKT0_RLS_ERROR                                                      (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
51224     #define BMB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT                                                1
51225     #define BMB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR                                                 (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
51226     #define BMB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                           5
51227     #define BMB_REG_INT_STS_0_RC_PKT1_RLS_ERROR                                                      (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
51228     #define BMB_REG_INT_STS_0_RC_PKT1_RLS_ERROR_SHIFT                                                6
51229     #define BMB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR                                                 (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
51230     #define BMB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                           10
51231     #define BMB_REG_INT_STS_0_RC_PKT2_RLS_ERROR                                                      (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
51232     #define BMB_REG_INT_STS_0_RC_PKT2_RLS_ERROR_SHIFT                                                11
51233     #define BMB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR                                                 (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
51234     #define BMB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                           15
51235     #define BMB_REG_INT_STS_0_RC_PKT3_RLS_ERROR                                                      (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
51236     #define BMB_REG_INT_STS_0_RC_PKT3_RLS_ERROR_SHIFT                                                16
51237     #define BMB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR                                                 (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
51238     #define BMB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                           20
51239     #define BMB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR                                               (0x1<<21) // SOP descriptor request from empty TC or port.
51240     #define BMB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                         21
51241     #define BMB_REG_INT_STS_0_WC0_PROTOCOL_ERROR                                                     (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
51242     #define BMB_REG_INT_STS_0_WC0_PROTOCOL_ERROR_SHIFT                                               23
51243     #define BMB_REG_INT_STS_0_WC1_PROTOCOL_ERROR                                                     (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
51244     #define BMB_REG_INT_STS_0_WC1_PROTOCOL_ERROR_SHIFT                                               24
51245     #define BMB_REG_INT_STS_0_WC2_PROTOCOL_ERROR                                                     (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
51246     #define BMB_REG_INT_STS_0_WC2_PROTOCOL_ERROR_SHIFT                                               25
51247     #define BMB_REG_INT_STS_0_WC3_PROTOCOL_ERROR                                                     (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
51248     #define BMB_REG_INT_STS_0_WC3_PROTOCOL_ERROR_SHIFT                                               26
51249     #define BMB_REG_INT_STS_0_LL_BLK_ERROR                                                           (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
51250     #define BMB_REG_INT_STS_0_LL_BLK_ERROR_SHIFT                                                     28
51251     #define BMB_REG_INT_STS_0_MAC0_FC_CNT_ERROR                                                      (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
51252     #define BMB_REG_INT_STS_0_MAC0_FC_CNT_ERROR_SHIFT                                                31
51253 #define BMB_REG_INT_MASK_0                                                                           0x5400c4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51254     #define BMB_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.ADDRESS_ERROR .
51255     #define BMB_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
51256     #define BMB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
51257     #define BMB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT                                               1
51258     #define BMB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
51259     #define BMB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                          5
51260     #define BMB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
51261     #define BMB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR_SHIFT                                               6
51262     #define BMB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
51263     #define BMB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                          10
51264     #define BMB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
51265     #define BMB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR_SHIFT                                               11
51266     #define BMB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
51267     #define BMB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                          15
51268     #define BMB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR                                                     (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
51269     #define BMB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR_SHIFT                                               16
51270     #define BMB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR                                                (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
51271     #define BMB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                          20
51272     #define BMB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
51273     #define BMB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                        21
51274     #define BMB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
51275     #define BMB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR_SHIFT                                              23
51276     #define BMB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC1_PROTOCOL_ERROR .
51277     #define BMB_REG_INT_MASK_0_WC1_PROTOCOL_ERROR_SHIFT                                              24
51278     #define BMB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR                                                    (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC2_PROTOCOL_ERROR .
51279     #define BMB_REG_INT_MASK_0_WC2_PROTOCOL_ERROR_SHIFT                                              25
51280     #define BMB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.WC3_PROTOCOL_ERROR .
51281     #define BMB_REG_INT_MASK_0_WC3_PROTOCOL_ERROR_SHIFT                                              26
51282     #define BMB_REG_INT_MASK_0_LL_BLK_ERROR                                                          (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.LL_BLK_ERROR .
51283     #define BMB_REG_INT_MASK_0_LL_BLK_ERROR_SHIFT                                                    28
51284     #define BMB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR                                                     (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_0.MAC0_FC_CNT_ERROR .
51285     #define BMB_REG_INT_MASK_0_MAC0_FC_CNT_ERROR_SHIFT                                               31
51286 #define BMB_REG_INT_STS_WR_0                                                                         0x5400c8UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51287     #define BMB_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
51288     #define BMB_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
51289     #define BMB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR                                                   (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
51290     #define BMB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT                                             1
51291     #define BMB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR                                              (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
51292     #define BMB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                        5
51293     #define BMB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR                                                   (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
51294     #define BMB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR_SHIFT                                             6
51295     #define BMB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR                                              (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
51296     #define BMB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                        10
51297     #define BMB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR                                                   (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
51298     #define BMB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR_SHIFT                                             11
51299     #define BMB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR                                              (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
51300     #define BMB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                        15
51301     #define BMB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR                                                   (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
51302     #define BMB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR_SHIFT                                             16
51303     #define BMB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR                                              (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
51304     #define BMB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                        20
51305     #define BMB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR                                            (0x1<<21) // SOP descriptor request from empty TC or port.
51306     #define BMB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                      21
51307     #define BMB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR                                                  (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
51308     #define BMB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR_SHIFT                                            23
51309     #define BMB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR                                                  (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
51310     #define BMB_REG_INT_STS_WR_0_WC1_PROTOCOL_ERROR_SHIFT                                            24
51311     #define BMB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR                                                  (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
51312     #define BMB_REG_INT_STS_WR_0_WC2_PROTOCOL_ERROR_SHIFT                                            25
51313     #define BMB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR                                                  (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
51314     #define BMB_REG_INT_STS_WR_0_WC3_PROTOCOL_ERROR_SHIFT                                            26
51315     #define BMB_REG_INT_STS_WR_0_LL_BLK_ERROR                                                        (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
51316     #define BMB_REG_INT_STS_WR_0_LL_BLK_ERROR_SHIFT                                                  28
51317     #define BMB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR                                                   (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
51318     #define BMB_REG_INT_STS_WR_0_MAC0_FC_CNT_ERROR_SHIFT                                             31
51319 #define BMB_REG_INT_STS_CLR_0                                                                        0x5400ccUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51320     #define BMB_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
51321     #define BMB_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
51322     #define BMB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR                                                  (0x1<<1) // Read packet client rc0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
51323     #define BMB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT                                            1
51324     #define BMB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR                                             (0x1<<5) // Read packet client rc0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
51325     #define BMB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                       5
51326     #define BMB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR                                                  (0x1<<6) // Read packet client rc1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
51327     #define BMB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR_SHIFT                                            6
51328     #define BMB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR                                             (0x1<<10) // Read packet client rc1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
51329     #define BMB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                       10
51330     #define BMB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR                                                  (0x1<<11) // Read packet client rc2 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
51331     #define BMB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR_SHIFT                                            11
51332     #define BMB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR                                             (0x1<<15) // Read packet client rc2 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
51333     #define BMB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                       15
51334     #define BMB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR                                                  (0x1<<16) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
51335     #define BMB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR_SHIFT                                            16
51336     #define BMB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR                                             (0x1<<20) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
51337     #define BMB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                       20
51338     #define BMB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR                                           (0x1<<21) // SOP descriptor request from empty TC or port.
51339     #define BMB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                     21
51340     #define BMB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR                                                 (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
51341     #define BMB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR_SHIFT                                           23
51342     #define BMB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR                                                 (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 1 RX_INT ::/RX_INT/d in Comments.
51343     #define BMB_REG_INT_STS_CLR_0_WC1_PROTOCOL_ERROR_SHIFT                                           24
51344     #define BMB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR                                                 (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 2 RX_INT ::/RX_INT/d in Comments.
51345     #define BMB_REG_INT_STS_CLR_0_WC2_PROTOCOL_ERROR_SHIFT                                           25
51346     #define BMB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR                                                 (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 3 RX_INT ::/RX_INT/d in Comments.
51347     #define BMB_REG_INT_STS_CLR_0_WC3_PROTOCOL_ERROR_SHIFT                                           26
51348     #define BMB_REG_INT_STS_CLR_0_LL_BLK_ERROR                                                       (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
51349     #define BMB_REG_INT_STS_CLR_0_LL_BLK_ERROR_SHIFT                                                 28
51350     #define BMB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR                                                  (0x1<<31) // Free shared area calculation error for MAC port 0 RX_INT::/RX_INT/d in Comments.
51351     #define BMB_REG_INT_STS_CLR_0_MAC0_FC_CNT_ERROR_SHIFT                                            31
51352 #define BMB_REG_INT_STS_1                                                                            0x5400d8UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51353     #define BMB_REG_INT_STS_1_LL_ARB_CALC_ERROR                                                      (0x1<<1) // Calculations error in LL arbiter block.
51354     #define BMB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT                                                1
51355     #define BMB_REG_INT_STS_1_WC0_INP_FIFO_ERROR                                                     (0x1<<3) // Input FIFO error in write client 0.
51356     #define BMB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT                                               3
51357     #define BMB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR                                                     (0x1<<4) // SOP FIFO error in write client 0.
51358     #define BMB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR_SHIFT                                               4
51359     #define BMB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR                                                     (0x1<<5) // LEN FIFO error in write client 0.
51360     #define BMB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR_SHIFT                                               5
51361     #define BMB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR                                                   (0x1<<7) // Queue FIFO error in write client 0.
51362     #define BMB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                             7
51363     #define BMB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR                                              (0x1<<8) // Free ointer FIFO error in write client 0.
51364     #define BMB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                        8
51365     #define BMB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR                                              (0x1<<9) // Next pointer FIFO error in write client 0.
51366     #define BMB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                        9
51367     #define BMB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR                                                    (0x1<<10) // Start FIFO error in write client 0.
51368     #define BMB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR_SHIFT                                              10
51369     #define BMB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR                                             (0x1<<11) // Second descriptor FIFO error in write client 0.
51370     #define BMB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                       11
51371     #define BMB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR                                               (0x1<<12) // Packet available FIFO error in write client 0.
51372     #define BMB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                         12
51373     #define BMB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR                                                 (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
51374     #define BMB_REG_INT_STS_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                           13
51375     #define BMB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR                                                  (0x1<<14) // Notify FIFO error in write client 0.
51376     #define BMB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                            14
51377     #define BMB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR                                                  (0x1<<15) // LL req error in write client 0.
51378     #define BMB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                            15
51379     #define BMB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR                                                    (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
51380     #define BMB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR_SHIFT                                              16
51381     #define BMB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR                                                    (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
51382     #define BMB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR_SHIFT                                              17
51383     #define BMB_REG_INT_STS_1_WC1_INP_FIFO_ERROR                                                     (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51384     #define BMB_REG_INT_STS_1_WC1_INP_FIFO_ERROR_SHIFT                                               18
51385     #define BMB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR                                                     (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51386     #define BMB_REG_INT_STS_1_WC1_SOP_FIFO_ERROR_SHIFT                                               19
51387     #define BMB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR                                                   (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51388     #define BMB_REG_INT_STS_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                             21
51389     #define BMB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR                                              (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51390     #define BMB_REG_INT_STS_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                        22
51391     #define BMB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR                                              (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51392     #define BMB_REG_INT_STS_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                        23
51393     #define BMB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR                                                    (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51394     #define BMB_REG_INT_STS_1_WC1_STRT_FIFO_ERROR_SHIFT                                              24
51395     #define BMB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR                                             (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51396     #define BMB_REG_INT_STS_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                       25
51397     #define BMB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR                                               (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
51398     #define BMB_REG_INT_STS_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                         26
51399     #define BMB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR                                                 (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51400     #define BMB_REG_INT_STS_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                           27
51401     #define BMB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR                                                  (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51402     #define BMB_REG_INT_STS_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                            28
51403     #define BMB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR                                                  (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
51404     #define BMB_REG_INT_STS_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                            29
51405     #define BMB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR                                                    (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
51406     #define BMB_REG_INT_STS_1_WC1_LL_PA_CNT_ERROR_SHIFT                                              30
51407     #define BMB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR                                                    (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
51408     #define BMB_REG_INT_STS_1_WC1_BB_PA_CNT_ERROR_SHIFT                                              31
51409 #define BMB_REG_INT_MASK_1                                                                           0x5400dcUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51410     #define BMB_REG_INT_MASK_1_LL_ARB_CALC_ERROR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
51411     #define BMB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT                                               1
51412     #define BMB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
51413     #define BMB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT                                              3
51414     #define BMB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
51415     #define BMB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR_SHIFT                                              4
51416     #define BMB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LEN_FIFO_ERROR .
51417     #define BMB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR_SHIFT                                              5
51418     #define BMB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
51419     #define BMB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                            7
51420     #define BMB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
51421     #define BMB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                       8
51422     #define BMB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
51423     #define BMB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                       9
51424     #define BMB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR                                                   (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
51425     #define BMB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR_SHIFT                                             10
51426     #define BMB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR                                            (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
51427     #define BMB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                      11
51428     #define BMB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
51429     #define BMB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                        12
51430     #define BMB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_COS_CNT_FIFO_ERROR .
51431     #define BMB_REG_INT_MASK_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                          13
51432     #define BMB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
51433     #define BMB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                           14
51434     #define BMB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
51435     #define BMB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                           15
51436     #define BMB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
51437     #define BMB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR_SHIFT                                             16
51438     #define BMB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR                                                   (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
51439     #define BMB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR_SHIFT                                             17
51440     #define BMB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR                                                    (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_INP_FIFO_ERROR .
51441     #define BMB_REG_INT_MASK_1_WC1_INP_FIFO_ERROR_SHIFT                                              18
51442     #define BMB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR                                                    (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_SOP_FIFO_ERROR .
51443     #define BMB_REG_INT_MASK_1_WC1_SOP_FIFO_ERROR_SHIFT                                              19
51444     #define BMB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_QUEUE_FIFO_ERROR .
51445     #define BMB_REG_INT_MASK_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                            21
51446     #define BMB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR                                             (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_FREE_POINT_FIFO_ERROR .
51447     #define BMB_REG_INT_MASK_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                       22
51448     #define BMB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR                                             (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_NEXT_POINT_FIFO_ERROR .
51449     #define BMB_REG_INT_MASK_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                       23
51450     #define BMB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR                                                   (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_STRT_FIFO_ERROR .
51451     #define BMB_REG_INT_MASK_1_WC1_STRT_FIFO_ERROR_SHIFT                                             24
51452     #define BMB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR                                            (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_SECOND_DSCR_FIFO_ERROR .
51453     #define BMB_REG_INT_MASK_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                      25
51454     #define BMB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR                                              (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_PKT_AVAIL_FIFO_ERROR .
51455     #define BMB_REG_INT_MASK_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                        26
51456     #define BMB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR                                                (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_COS_CNT_FIFO_ERROR .
51457     #define BMB_REG_INT_MASK_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                          27
51458     #define BMB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR                                                 (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_NOTIFY_FIFO_ERROR .
51459     #define BMB_REG_INT_MASK_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                           28
51460     #define BMB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR                                                 (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_LL_REQ_FIFO_ERROR .
51461     #define BMB_REG_INT_MASK_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                           29
51462     #define BMB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR                                                   (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_LL_PA_CNT_ERROR .
51463     #define BMB_REG_INT_MASK_1_WC1_LL_PA_CNT_ERROR_SHIFT                                             30
51464     #define BMB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR                                                   (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_1.WC1_BB_PA_CNT_ERROR .
51465     #define BMB_REG_INT_MASK_1_WC1_BB_PA_CNT_ERROR_SHIFT                                             31
51466 #define BMB_REG_INT_STS_WR_1                                                                         0x5400e0UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51467     #define BMB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR                                                   (0x1<<1) // Calculations error in LL arbiter block.
51468     #define BMB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT                                             1
51469     #define BMB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR                                                  (0x1<<3) // Input FIFO error in write client 0.
51470     #define BMB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT                                            3
51471     #define BMB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR                                                  (0x1<<4) // SOP FIFO error in write client 0.
51472     #define BMB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR_SHIFT                                            4
51473     #define BMB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR                                                  (0x1<<5) // LEN FIFO error in write client 0.
51474     #define BMB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR_SHIFT                                            5
51475     #define BMB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR                                                (0x1<<7) // Queue FIFO error in write client 0.
51476     #define BMB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                          7
51477     #define BMB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR                                           (0x1<<8) // Free ointer FIFO error in write client 0.
51478     #define BMB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                     8
51479     #define BMB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR                                           (0x1<<9) // Next pointer FIFO error in write client 0.
51480     #define BMB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                     9
51481     #define BMB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR                                                 (0x1<<10) // Start FIFO error in write client 0.
51482     #define BMB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR_SHIFT                                           10
51483     #define BMB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR                                          (0x1<<11) // Second descriptor FIFO error in write client 0.
51484     #define BMB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                    11
51485     #define BMB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR                                            (0x1<<12) // Packet available FIFO error in write client 0.
51486     #define BMB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                      12
51487     #define BMB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR                                              (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
51488     #define BMB_REG_INT_STS_WR_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                        13
51489     #define BMB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR                                               (0x1<<14) // Notify FIFO error in write client 0.
51490     #define BMB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                         14
51491     #define BMB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR                                               (0x1<<15) // LL req error in write client 0.
51492     #define BMB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                         15
51493     #define BMB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR                                                 (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
51494     #define BMB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                           16
51495     #define BMB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR                                                 (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
51496     #define BMB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                           17
51497     #define BMB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR                                                  (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51498     #define BMB_REG_INT_STS_WR_1_WC1_INP_FIFO_ERROR_SHIFT                                            18
51499     #define BMB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR                                                  (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51500     #define BMB_REG_INT_STS_WR_1_WC1_SOP_FIFO_ERROR_SHIFT                                            19
51501     #define BMB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR                                                (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51502     #define BMB_REG_INT_STS_WR_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                          21
51503     #define BMB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR                                           (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51504     #define BMB_REG_INT_STS_WR_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                     22
51505     #define BMB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR                                           (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51506     #define BMB_REG_INT_STS_WR_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                     23
51507     #define BMB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR                                                 (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51508     #define BMB_REG_INT_STS_WR_1_WC1_STRT_FIFO_ERROR_SHIFT                                           24
51509     #define BMB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR                                          (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51510     #define BMB_REG_INT_STS_WR_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                    25
51511     #define BMB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR                                            (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
51512     #define BMB_REG_INT_STS_WR_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                      26
51513     #define BMB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR                                              (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51514     #define BMB_REG_INT_STS_WR_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                        27
51515     #define BMB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR                                               (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51516     #define BMB_REG_INT_STS_WR_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                         28
51517     #define BMB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR                                               (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
51518     #define BMB_REG_INT_STS_WR_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                         29
51519     #define BMB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR                                                 (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
51520     #define BMB_REG_INT_STS_WR_1_WC1_LL_PA_CNT_ERROR_SHIFT                                           30
51521     #define BMB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR                                                 (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
51522     #define BMB_REG_INT_STS_WR_1_WC1_BB_PA_CNT_ERROR_SHIFT                                           31
51523 #define BMB_REG_INT_STS_CLR_1                                                                        0x5400e4UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51524     #define BMB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR                                                  (0x1<<1) // Calculations error in LL arbiter block.
51525     #define BMB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT                                            1
51526     #define BMB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR                                                 (0x1<<3) // Input FIFO error in write client 0.
51527     #define BMB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT                                           3
51528     #define BMB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR                                                 (0x1<<4) // SOP FIFO error in write client 0.
51529     #define BMB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR_SHIFT                                           4
51530     #define BMB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR                                                 (0x1<<5) // LEN FIFO error in write client 0.
51531     #define BMB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR_SHIFT                                           5
51532     #define BMB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR                                               (0x1<<7) // Queue FIFO error in write client 0.
51533     #define BMB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                         7
51534     #define BMB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR                                          (0x1<<8) // Free ointer FIFO error in write client 0.
51535     #define BMB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                    8
51536     #define BMB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR                                          (0x1<<9) // Next pointer FIFO error in write client 0.
51537     #define BMB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                    9
51538     #define BMB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR                                                (0x1<<10) // Start FIFO error in write client 0.
51539     #define BMB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR_SHIFT                                          10
51540     #define BMB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR                                         (0x1<<11) // Second descriptor FIFO error in write client 0.
51541     #define BMB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                   11
51542     #define BMB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR                                           (0x1<<12) // Packet available FIFO error in write client 0.
51543     #define BMB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                     12
51544     #define BMB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR                                             (0x1<<13) // COS counter FIFO error in write client 0 RX_INT::/RX_INT/d in Comments.
51545     #define BMB_REG_INT_STS_CLR_1_WC0_COS_CNT_FIFO_ERROR_SHIFT                                       13
51546     #define BMB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR                                              (0x1<<14) // Notify FIFO error in write client 0.
51547     #define BMB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                        14
51548     #define BMB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR                                              (0x1<<15) // LL req error in write client 0.
51549     #define BMB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                        15
51550     #define BMB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR                                                (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
51551     #define BMB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                          16
51552     #define BMB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR                                                (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
51553     #define BMB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                          17
51554     #define BMB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR                                                 (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51555     #define BMB_REG_INT_STS_CLR_1_WC1_INP_FIFO_ERROR_SHIFT                                           18
51556     #define BMB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR                                                 (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51557     #define BMB_REG_INT_STS_CLR_1_WC1_SOP_FIFO_ERROR_SHIFT                                           19
51558     #define BMB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR                                               (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51559     #define BMB_REG_INT_STS_CLR_1_WC1_QUEUE_FIFO_ERROR_SHIFT                                         21
51560     #define BMB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR                                          (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51561     #define BMB_REG_INT_STS_CLR_1_WC1_FREE_POINT_FIFO_ERROR_SHIFT                                    22
51562     #define BMB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR                                          (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51563     #define BMB_REG_INT_STS_CLR_1_WC1_NEXT_POINT_FIFO_ERROR_SHIFT                                    23
51564     #define BMB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR                                                (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51565     #define BMB_REG_INT_STS_CLR_1_WC1_STRT_FIFO_ERROR_SHIFT                                          24
51566     #define BMB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR                                         (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51567     #define BMB_REG_INT_STS_CLR_1_WC1_SECOND_DSCR_FIFO_ERROR_SHIFT                                   25
51568     #define BMB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 1 RX_INT ::/RX_INT/d in Comments.
51569     #define BMB_REG_INT_STS_CLR_1_WC1_PKT_AVAIL_FIFO_ERROR_SHIFT                                     26
51570     #define BMB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR                                             (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51571     #define BMB_REG_INT_STS_CLR_1_WC1_COS_CNT_FIFO_ERROR_SHIFT                                       27
51572     #define BMB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR                                              (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 1 RX_INT::/RX_INT/d in Comments.
51573     #define BMB_REG_INT_STS_CLR_1_WC1_NOTIFY_FIFO_ERROR_SHIFT                                        28
51574     #define BMB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR                                              (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 1 RX_INT::/RX_INT/d in Comments.
51575     #define BMB_REG_INT_STS_CLR_1_WC1_LL_REQ_FIFO_ERROR_SHIFT                                        29
51576     #define BMB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR                                                (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list RX_INT::/RX_INT/d in Comments.
51577     #define BMB_REG_INT_STS_CLR_1_WC1_LL_PA_CNT_ERROR_SHIFT                                          30
51578     #define BMB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR                                                (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor RX_INT::/RX_INT/d in Comments.
51579     #define BMB_REG_INT_STS_CLR_1_WC1_BB_PA_CNT_ERROR_SHIFT                                          31
51580 #define BMB_REG_INT_STS_2                                                                            0x5400f0UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51581     #define BMB_REG_INT_STS_2_WC2_INP_FIFO_ERROR                                                     (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51582     #define BMB_REG_INT_STS_2_WC2_INP_FIFO_ERROR_SHIFT                                               0
51583     #define BMB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR                                                     (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51584     #define BMB_REG_INT_STS_2_WC2_SOP_FIFO_ERROR_SHIFT                                               1
51585     #define BMB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR                                                   (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51586     #define BMB_REG_INT_STS_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                             3
51587     #define BMB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR                                              (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51588     #define BMB_REG_INT_STS_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                        4
51589     #define BMB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR                                              (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51590     #define BMB_REG_INT_STS_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                        5
51591     #define BMB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR                                                    (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51592     #define BMB_REG_INT_STS_2_WC2_STRT_FIFO_ERROR_SHIFT                                              6
51593     #define BMB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR                                             (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51594     #define BMB_REG_INT_STS_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                       7
51595     #define BMB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR                                               (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
51596     #define BMB_REG_INT_STS_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                         8
51597     #define BMB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR                                                 (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51598     #define BMB_REG_INT_STS_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                           9
51599     #define BMB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR                                                  (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51600     #define BMB_REG_INT_STS_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                            10
51601     #define BMB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR                                                  (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
51602     #define BMB_REG_INT_STS_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                            11
51603     #define BMB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR                                                    (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
51604     #define BMB_REG_INT_STS_2_WC2_LL_PA_CNT_ERROR_SHIFT                                              12
51605     #define BMB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR                                                    (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
51606     #define BMB_REG_INT_STS_2_WC2_BB_PA_CNT_ERROR_SHIFT                                              13
51607     #define BMB_REG_INT_STS_2_WC3_INP_FIFO_ERROR                                                     (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51608     #define BMB_REG_INT_STS_2_WC3_INP_FIFO_ERROR_SHIFT                                               14
51609     #define BMB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR                                                     (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51610     #define BMB_REG_INT_STS_2_WC3_SOP_FIFO_ERROR_SHIFT                                               15
51611     #define BMB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR                                                   (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51612     #define BMB_REG_INT_STS_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                             17
51613     #define BMB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR                                              (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51614     #define BMB_REG_INT_STS_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                        18
51615     #define BMB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR                                              (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51616     #define BMB_REG_INT_STS_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                        19
51617     #define BMB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR                                                    (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51618     #define BMB_REG_INT_STS_2_WC3_STRT_FIFO_ERROR_SHIFT                                              20
51619     #define BMB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR                                             (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51620     #define BMB_REG_INT_STS_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                       21
51621     #define BMB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR                                               (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
51622     #define BMB_REG_INT_STS_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                         22
51623     #define BMB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR                                                 (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51624     #define BMB_REG_INT_STS_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                           23
51625     #define BMB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR                                                  (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51626     #define BMB_REG_INT_STS_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                            24
51627     #define BMB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR                                                  (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
51628     #define BMB_REG_INT_STS_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                            25
51629     #define BMB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR                                                    (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
51630     #define BMB_REG_INT_STS_2_WC3_LL_PA_CNT_ERROR_SHIFT                                              26
51631     #define BMB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR                                                    (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
51632     #define BMB_REG_INT_STS_2_WC3_BB_PA_CNT_ERROR_SHIFT                                              27
51633 #define BMB_REG_INT_MASK_2                                                                           0x5400f4UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51634     #define BMB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR                                                    (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_INP_FIFO_ERROR .
51635     #define BMB_REG_INT_MASK_2_WC2_INP_FIFO_ERROR_SHIFT                                              0
51636     #define BMB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_SOP_FIFO_ERROR .
51637     #define BMB_REG_INT_MASK_2_WC2_SOP_FIFO_ERROR_SHIFT                                              1
51638     #define BMB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR                                                  (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_QUEUE_FIFO_ERROR .
51639     #define BMB_REG_INT_MASK_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                            3
51640     #define BMB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR                                             (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_FREE_POINT_FIFO_ERROR .
51641     #define BMB_REG_INT_MASK_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                       4
51642     #define BMB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR                                             (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_NEXT_POINT_FIFO_ERROR .
51643     #define BMB_REG_INT_MASK_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                       5
51644     #define BMB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_STRT_FIFO_ERROR .
51645     #define BMB_REG_INT_MASK_2_WC2_STRT_FIFO_ERROR_SHIFT                                             6
51646     #define BMB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_SECOND_DSCR_FIFO_ERROR .
51647     #define BMB_REG_INT_MASK_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                      7
51648     #define BMB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR                                              (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_PKT_AVAIL_FIFO_ERROR .
51649     #define BMB_REG_INT_MASK_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                        8
51650     #define BMB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_COS_CNT_FIFO_ERROR .
51651     #define BMB_REG_INT_MASK_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                          9
51652     #define BMB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_NOTIFY_FIFO_ERROR .
51653     #define BMB_REG_INT_MASK_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                           10
51654     #define BMB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_LL_REQ_FIFO_ERROR .
51655     #define BMB_REG_INT_MASK_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                           11
51656     #define BMB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR                                                   (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_LL_PA_CNT_ERROR .
51657     #define BMB_REG_INT_MASK_2_WC2_LL_PA_CNT_ERROR_SHIFT                                             12
51658     #define BMB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR                                                   (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC2_BB_PA_CNT_ERROR .
51659     #define BMB_REG_INT_MASK_2_WC2_BB_PA_CNT_ERROR_SHIFT                                             13
51660     #define BMB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR                                                    (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_INP_FIFO_ERROR .
51661     #define BMB_REG_INT_MASK_2_WC3_INP_FIFO_ERROR_SHIFT                                              14
51662     #define BMB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR                                                    (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_SOP_FIFO_ERROR .
51663     #define BMB_REG_INT_MASK_2_WC3_SOP_FIFO_ERROR_SHIFT                                              15
51664     #define BMB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_QUEUE_FIFO_ERROR .
51665     #define BMB_REG_INT_MASK_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                            17
51666     #define BMB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR                                             (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_FREE_POINT_FIFO_ERROR .
51667     #define BMB_REG_INT_MASK_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                       18
51668     #define BMB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_NEXT_POINT_FIFO_ERROR .
51669     #define BMB_REG_INT_MASK_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                       19
51670     #define BMB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR                                                   (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_STRT_FIFO_ERROR .
51671     #define BMB_REG_INT_MASK_2_WC3_STRT_FIFO_ERROR_SHIFT                                             20
51672     #define BMB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR                                            (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_SECOND_DSCR_FIFO_ERROR .
51673     #define BMB_REG_INT_MASK_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                      21
51674     #define BMB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR                                              (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_PKT_AVAIL_FIFO_ERROR .
51675     #define BMB_REG_INT_MASK_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                        22
51676     #define BMB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_COS_CNT_FIFO_ERROR .
51677     #define BMB_REG_INT_MASK_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                          23
51678     #define BMB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR                                                 (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_NOTIFY_FIFO_ERROR .
51679     #define BMB_REG_INT_MASK_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                           24
51680     #define BMB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR                                                 (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_LL_REQ_FIFO_ERROR .
51681     #define BMB_REG_INT_MASK_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                           25
51682     #define BMB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR                                                   (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_LL_PA_CNT_ERROR .
51683     #define BMB_REG_INT_MASK_2_WC3_LL_PA_CNT_ERROR_SHIFT                                             26
51684     #define BMB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_2.WC3_BB_PA_CNT_ERROR .
51685     #define BMB_REG_INT_MASK_2_WC3_BB_PA_CNT_ERROR_SHIFT                                             27
51686 #define BMB_REG_INT_STS_WR_2                                                                         0x5400f8UL //Access:WR   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51687     #define BMB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR                                                  (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51688     #define BMB_REG_INT_STS_WR_2_WC2_INP_FIFO_ERROR_SHIFT                                            0
51689     #define BMB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR                                                  (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51690     #define BMB_REG_INT_STS_WR_2_WC2_SOP_FIFO_ERROR_SHIFT                                            1
51691     #define BMB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR                                                (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51692     #define BMB_REG_INT_STS_WR_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                          3
51693     #define BMB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR                                           (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51694     #define BMB_REG_INT_STS_WR_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                     4
51695     #define BMB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR                                           (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51696     #define BMB_REG_INT_STS_WR_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                     5
51697     #define BMB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR                                                 (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51698     #define BMB_REG_INT_STS_WR_2_WC2_STRT_FIFO_ERROR_SHIFT                                           6
51699     #define BMB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR                                          (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51700     #define BMB_REG_INT_STS_WR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                    7
51701     #define BMB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR                                            (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
51702     #define BMB_REG_INT_STS_WR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                      8
51703     #define BMB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR                                              (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51704     #define BMB_REG_INT_STS_WR_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                        9
51705     #define BMB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR                                               (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51706     #define BMB_REG_INT_STS_WR_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                         10
51707     #define BMB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR                                               (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
51708     #define BMB_REG_INT_STS_WR_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                         11
51709     #define BMB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR                                                 (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
51710     #define BMB_REG_INT_STS_WR_2_WC2_LL_PA_CNT_ERROR_SHIFT                                           12
51711     #define BMB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR                                                 (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
51712     #define BMB_REG_INT_STS_WR_2_WC2_BB_PA_CNT_ERROR_SHIFT                                           13
51713     #define BMB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR                                                  (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51714     #define BMB_REG_INT_STS_WR_2_WC3_INP_FIFO_ERROR_SHIFT                                            14
51715     #define BMB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR                                                  (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51716     #define BMB_REG_INT_STS_WR_2_WC3_SOP_FIFO_ERROR_SHIFT                                            15
51717     #define BMB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR                                                (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51718     #define BMB_REG_INT_STS_WR_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                          17
51719     #define BMB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR                                           (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51720     #define BMB_REG_INT_STS_WR_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                     18
51721     #define BMB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR                                           (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51722     #define BMB_REG_INT_STS_WR_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                     19
51723     #define BMB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR                                                 (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51724     #define BMB_REG_INT_STS_WR_2_WC3_STRT_FIFO_ERROR_SHIFT                                           20
51725     #define BMB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR                                          (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51726     #define BMB_REG_INT_STS_WR_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                    21
51727     #define BMB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR                                            (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
51728     #define BMB_REG_INT_STS_WR_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                      22
51729     #define BMB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR                                              (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51730     #define BMB_REG_INT_STS_WR_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                        23
51731     #define BMB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51732     #define BMB_REG_INT_STS_WR_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                         24
51733     #define BMB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR                                               (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
51734     #define BMB_REG_INT_STS_WR_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                         25
51735     #define BMB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR                                                 (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
51736     #define BMB_REG_INT_STS_WR_2_WC3_LL_PA_CNT_ERROR_SHIFT                                           26
51737     #define BMB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR                                                 (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
51738     #define BMB_REG_INT_STS_WR_2_WC3_BB_PA_CNT_ERROR_SHIFT                                           27
51739 #define BMB_REG_INT_STS_CLR_2                                                                        0x5400fcUL //Access:RC   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51740     #define BMB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR                                                 (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51741     #define BMB_REG_INT_STS_CLR_2_WC2_INP_FIFO_ERROR_SHIFT                                           0
51742     #define BMB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR                                                 (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51743     #define BMB_REG_INT_STS_CLR_2_WC2_SOP_FIFO_ERROR_SHIFT                                           1
51744     #define BMB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR                                               (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51745     #define BMB_REG_INT_STS_CLR_2_WC2_QUEUE_FIFO_ERROR_SHIFT                                         3
51746     #define BMB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR                                          (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51747     #define BMB_REG_INT_STS_CLR_2_WC2_FREE_POINT_FIFO_ERROR_SHIFT                                    4
51748     #define BMB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR                                          (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51749     #define BMB_REG_INT_STS_CLR_2_WC2_NEXT_POINT_FIFO_ERROR_SHIFT                                    5
51750     #define BMB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR                                                (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51751     #define BMB_REG_INT_STS_CLR_2_WC2_STRT_FIFO_ERROR_SHIFT                                          6
51752     #define BMB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR                                         (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51753     #define BMB_REG_INT_STS_CLR_2_WC2_SECOND_DSCR_FIFO_ERROR_SHIFT                                   7
51754     #define BMB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR                                           (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 2 RX_INT ::/RX_INT/d in Comments.
51755     #define BMB_REG_INT_STS_CLR_2_WC2_PKT_AVAIL_FIFO_ERROR_SHIFT                                     8
51756     #define BMB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR                                             (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51757     #define BMB_REG_INT_STS_CLR_2_WC2_COS_CNT_FIFO_ERROR_SHIFT                                       9
51758     #define BMB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR                                              (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 2 RX_INT::/RX_INT/d in Comments.
51759     #define BMB_REG_INT_STS_CLR_2_WC2_NOTIFY_FIFO_ERROR_SHIFT                                        10
51760     #define BMB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR                                              (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 2 RX_INT::/RX_INT/d in Comments.
51761     #define BMB_REG_INT_STS_CLR_2_WC2_LL_REQ_FIFO_ERROR_SHIFT                                        11
51762     #define BMB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR                                                (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 2 RX_INT::/RX_INT/d in Comments.
51763     #define BMB_REG_INT_STS_CLR_2_WC2_LL_PA_CNT_ERROR_SHIFT                                          12
51764     #define BMB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR                                                (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 2 RX_INT::/RX_INT/d in Comments.
51765     #define BMB_REG_INT_STS_CLR_2_WC2_BB_PA_CNT_ERROR_SHIFT                                          13
51766     #define BMB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR                                                 (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51767     #define BMB_REG_INT_STS_CLR_2_WC3_INP_FIFO_ERROR_SHIFT                                           14
51768     #define BMB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR                                                 (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51769     #define BMB_REG_INT_STS_CLR_2_WC3_SOP_FIFO_ERROR_SHIFT                                           15
51770     #define BMB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR                                               (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51771     #define BMB_REG_INT_STS_CLR_2_WC3_QUEUE_FIFO_ERROR_SHIFT                                         17
51772     #define BMB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR                                          (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51773     #define BMB_REG_INT_STS_CLR_2_WC3_FREE_POINT_FIFO_ERROR_SHIFT                                    18
51774     #define BMB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR                                          (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51775     #define BMB_REG_INT_STS_CLR_2_WC3_NEXT_POINT_FIFO_ERROR_SHIFT                                    19
51776     #define BMB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR                                                (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51777     #define BMB_REG_INT_STS_CLR_2_WC3_STRT_FIFO_ERROR_SHIFT                                          20
51778     #define BMB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR                                         (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51779     #define BMB_REG_INT_STS_CLR_2_WC3_SECOND_DSCR_FIFO_ERROR_SHIFT                                   21
51780     #define BMB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR                                           (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 3 RX_INT ::/RX_INT/d in Comments.
51781     #define BMB_REG_INT_STS_CLR_2_WC3_PKT_AVAIL_FIFO_ERROR_SHIFT                                     22
51782     #define BMB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR                                             (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51783     #define BMB_REG_INT_STS_CLR_2_WC3_COS_CNT_FIFO_ERROR_SHIFT                                       23
51784     #define BMB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR                                              (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 3 RX_INT::/RX_INT/d in Comments.
51785     #define BMB_REG_INT_STS_CLR_2_WC3_NOTIFY_FIFO_ERROR_SHIFT                                        24
51786     #define BMB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR                                              (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 3 RX_INT::/RX_INT/d in Comments.
51787     #define BMB_REG_INT_STS_CLR_2_WC3_LL_REQ_FIFO_ERROR_SHIFT                                        25
51788     #define BMB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR                                                (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 3 RX_INT::/RX_INT/d in Comments.
51789     #define BMB_REG_INT_STS_CLR_2_WC3_LL_PA_CNT_ERROR_SHIFT                                          26
51790     #define BMB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR                                                (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 3 RX_INT::/RX_INT/d in Comments.
51791     #define BMB_REG_INT_STS_CLR_2_WC3_BB_PA_CNT_ERROR_SHIFT                                          27
51792 #define BMB_REG_INT_STS_3                                                                            0x540108UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51793     #define BMB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR                                                (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51794     #define BMB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                          1
51795     #define BMB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR                                                 (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51796     #define BMB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                           2
51797     #define BMB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR                                                 (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51798     #define BMB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                           3
51799     #define BMB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                            (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51800     #define BMB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                      4
51801     #define BMB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                            (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51802     #define BMB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                      5
51803     #define BMB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                          (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51804     #define BMB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                    6
51805     #define BMB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR                                                 (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51806     #define BMB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                           7
51807     #define BMB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR                                                (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51808     #define BMB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                          8
51809     #define BMB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR                                                (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51810     #define BMB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                          9
51811     #define BMB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR                                                 (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51812     #define BMB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                           10
51813     #define BMB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR                                                 (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51814     #define BMB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                           11
51815     #define BMB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                            (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51816     #define BMB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                      12
51817     #define BMB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                            (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51818     #define BMB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                      13
51819     #define BMB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                          (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51820     #define BMB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                    14
51821     #define BMB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR                                                 (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51822     #define BMB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                           15
51823     #define BMB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR                                                (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51824     #define BMB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                          16
51825     #define BMB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR                                                (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51826     #define BMB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                          17
51827     #define BMB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR                                                 (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51828     #define BMB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                           18
51829     #define BMB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR                                                 (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51830     #define BMB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                           19
51831     #define BMB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                            (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51832     #define BMB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                      20
51833     #define BMB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                            (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51834     #define BMB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                      21
51835     #define BMB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                          (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51836     #define BMB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                    22
51837     #define BMB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR                                                 (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51838     #define BMB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                           23
51839     #define BMB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR                                                (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51840     #define BMB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                          24
51841     #define BMB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR                                                (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51842     #define BMB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                          25
51843     #define BMB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR                                                 (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51844     #define BMB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                           26
51845     #define BMB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR                                                 (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51846     #define BMB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                           27
51847     #define BMB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                            (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51848     #define BMB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                      28
51849     #define BMB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                            (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51850     #define BMB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                      29
51851     #define BMB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                          (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51852     #define BMB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                    30
51853     #define BMB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR                                                 (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51854     #define BMB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                           31
51855 #define BMB_REG_INT_MASK_3                                                                           0x54010cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51856     #define BMB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
51857     #define BMB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                         1
51858     #define BMB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
51859     #define BMB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                          2
51860     #define BMB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
51861     #define BMB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                          3
51862     #define BMB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                           (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
51863     #define BMB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                     4
51864     #define BMB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                           (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
51865     #define BMB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                     5
51866     #define BMB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
51867     #define BMB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                   6
51868     #define BMB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
51869     #define BMB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                          7
51870     #define BMB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
51871     #define BMB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                         8
51872     #define BMB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
51873     #define BMB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                         9
51874     #define BMB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
51875     #define BMB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                          10
51876     #define BMB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
51877     #define BMB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                          11
51878     #define BMB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
51879     #define BMB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                     12
51880     #define BMB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                           (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
51881     #define BMB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                     13
51882     #define BMB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
51883     #define BMB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                   14
51884     #define BMB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
51885     #define BMB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                          15
51886     #define BMB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
51887     #define BMB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                         16
51888     #define BMB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR                                               (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
51889     #define BMB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                         17
51890     #define BMB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
51891     #define BMB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                          18
51892     #define BMB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR                                                (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
51893     #define BMB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                          19
51894     #define BMB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                           (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
51895     #define BMB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                     20
51896     #define BMB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                           (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
51897     #define BMB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                     21
51898     #define BMB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                         (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
51899     #define BMB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                   22
51900     #define BMB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
51901     #define BMB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                          23
51902     #define BMB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
51903     #define BMB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                         24
51904     #define BMB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
51905     #define BMB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                         25
51906     #define BMB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
51907     #define BMB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                          26
51908     #define BMB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR                                                (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
51909     #define BMB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                          27
51910     #define BMB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
51911     #define BMB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                     28
51912     #define BMB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
51913     #define BMB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                     29
51914     #define BMB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
51915     #define BMB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                   30
51916     #define BMB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
51917     #define BMB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                          31
51918 #define BMB_REG_INT_STS_WR_3                                                                         0x540110UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51919     #define BMB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR                                             (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51920     #define BMB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                       1
51921     #define BMB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR                                              (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51922     #define BMB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                        2
51923     #define BMB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR                                              (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51924     #define BMB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                        3
51925     #define BMB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                         (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51926     #define BMB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                   4
51927     #define BMB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                         (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51928     #define BMB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                   5
51929     #define BMB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                       (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51930     #define BMB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                 6
51931     #define BMB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR                                              (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51932     #define BMB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                        7
51933     #define BMB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR                                             (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51934     #define BMB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                       8
51935     #define BMB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR                                             (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51936     #define BMB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                       9
51937     #define BMB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR                                              (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51938     #define BMB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                        10
51939     #define BMB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR                                              (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51940     #define BMB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                        11
51941     #define BMB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                         (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51942     #define BMB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                   12
51943     #define BMB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                         (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51944     #define BMB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                   13
51945     #define BMB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                       (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51946     #define BMB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                 14
51947     #define BMB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR                                              (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51948     #define BMB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                        15
51949     #define BMB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR                                             (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51950     #define BMB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                       16
51951     #define BMB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR                                             (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51952     #define BMB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                       17
51953     #define BMB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR                                              (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51954     #define BMB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                        18
51955     #define BMB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR                                              (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51956     #define BMB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                        19
51957     #define BMB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                         (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51958     #define BMB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                   20
51959     #define BMB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                         (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51960     #define BMB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                   21
51961     #define BMB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                       (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51962     #define BMB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                 22
51963     #define BMB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR                                              (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51964     #define BMB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                        23
51965     #define BMB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR                                             (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
51966     #define BMB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                       24
51967     #define BMB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR                                             (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51968     #define BMB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                       25
51969     #define BMB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR                                              (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51970     #define BMB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                        26
51971     #define BMB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR                                              (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51972     #define BMB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                        27
51973     #define BMB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                         (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51974     #define BMB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                   28
51975     #define BMB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                         (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51976     #define BMB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                   29
51977     #define BMB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                       (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51978     #define BMB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                 30
51979     #define BMB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR                                              (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
51980     #define BMB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                        31
51981 #define BMB_REG_INT_STS_CLR_3                                                                        0x540114UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
51982     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR                                            (0x1<<1) // Read packet client rc0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51983     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                      1
51984     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR                                             (0x1<<2) // Read packet client rc0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51985     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                       2
51986     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR                                             (0x1<<3) // Read packet client rc0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51987     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                       3
51988     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                        (0x1<<4) // Read packet client rc0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51989     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                  4
51990     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                        (0x1<<5) // Read packet client rc0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51991     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                  5
51992     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                      (0x1<<6) // Read packet client rc0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51993     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                6
51994     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR                                             (0x1<<7) // Read packet client rc0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51995     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                       7
51996     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR                                            (0x1<<8) // Read packet client rc0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
51997     #define BMB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                      8
51998     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR                                            (0x1<<9) // Read packet client rc1 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
51999     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                      9
52000     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR                                             (0x1<<10) // Read packet client rc1 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
52001     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                       10
52002     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR                                             (0x1<<11) // Read packet client rc1 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
52003     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                       11
52004     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                        (0x1<<12) // Read packet client rc1 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
52005     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                  12
52006     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                        (0x1<<13) // Read packet client rc1 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
52007     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                  13
52008     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                      (0x1<<14) // Read packet client rc1 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
52009     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                14
52010     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR                                             (0x1<<15) // Read packet client rc1 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
52011     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                       15
52012     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR                                            (0x1<<16) // Read packet client rc1 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
52013     #define BMB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                      16
52014     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR                                            (0x1<<17) // Read packet client rc2 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
52015     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                      17
52016     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR                                             (0x1<<18) // Read packet client rc2 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
52017     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                       18
52018     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR                                             (0x1<<19) // Read packet client rc2 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
52019     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                       19
52020     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                        (0x1<<20) // Read packet client rc2 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
52021     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                  20
52022     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                        (0x1<<21) // Read packet client rc2 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
52023     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                  21
52024     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                      (0x1<<22) // Read packet client rc2 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
52025     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                22
52026     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR                                             (0x1<<23) // Read packet client rc2 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
52027     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                       23
52028     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR                                            (0x1<<24) // Read packet client rc2 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
52029     #define BMB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                      24
52030     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR                                            (0x1<<25) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52031     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                      25
52032     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR                                             (0x1<<26) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52033     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                       26
52034     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR                                             (0x1<<27) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52035     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                       27
52036     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                        (0x1<<28) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52037     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                  28
52038     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                        (0x1<<29) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52039     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                  29
52040     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                      (0x1<<30) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52041     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                30
52042     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR                                             (0x1<<31) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52043     #define BMB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                       31
52044 #define BMB_REG_INT_STS_4                                                                            0x540120UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52045     #define BMB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR                                                (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52046     #define BMB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                          0
52047     #define BMB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR                                                 (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
52048     #define BMB_REG_INT_STS_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                           1
52049     #define BMB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR                                                  (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
52050     #define BMB_REG_INT_STS_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                            2
52051     #define BMB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR                                                 (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
52052     #define BMB_REG_INT_STS_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                           3
52053     #define BMB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR                                                (0x1<<4) // Read SOP client queue FIFO error.
52054     #define BMB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                          4
52055     #define BMB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR                                                  (0x1<<7) // Link list arbiter release FIFO error.
52056     #define BMB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                            7
52057     #define BMB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR                                             (0x1<<8) // Link list arbiter prefetch FIFO error.
52058     #define BMB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                       8
52059     #define BMB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR                                                 (0x1<<9) // Read packet client rc0 release fifo error
52060     #define BMB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                           9
52061     #define BMB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR                                                 (0x1<<10) // Read packet client rc1 release fifo error
52062     #define BMB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                           10
52063     #define BMB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR                                                 (0x1<<11) // Read packet client rc2 release fifo error
52064     #define BMB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                           11
52065     #define BMB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR                                                 (0x1<<12) // Read packet client rc3 release fifo error
52066     #define BMB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                           12
52067     #define BMB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR                                                 (0x1<<13) // Read packet client rc4 release fifo error
52068     #define BMB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                           13
52069     #define BMB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR                                                 (0x1<<14) // Read packet client rc4 release fifo error
52070     #define BMB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                           14
52071     #define BMB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR                                                 (0x1<<15) // Read packet client rc4 release fifo error
52072     #define BMB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                           15
52073     #define BMB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR                                                 (0x1<<16) // Read packet client rc4 release fifo error
52074     #define BMB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                           16
52075     #define BMB_REG_INT_STS_4_RC_PKT8_RLS_FIFO_ERROR                                                 (0x1<<17) // Read packet client rc4 release fifo error
52076     #define BMB_REG_INT_STS_4_RC_PKT8_RLS_FIFO_ERROR_SHIFT                                           17
52077     #define BMB_REG_INT_STS_4_RC_PKT9_RLS_FIFO_ERROR                                                 (0x1<<18) // Read packet client rc4 release fifo error
52078     #define BMB_REG_INT_STS_4_RC_PKT9_RLS_FIFO_ERROR_SHIFT                                           18
52079     #define BMB_REG_INT_STS_4_RC_PKT4_RLS_ERROR                                                      (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
52080     #define BMB_REG_INT_STS_4_RC_PKT4_RLS_ERROR_SHIFT                                                19
52081     #define BMB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR                                                 (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
52082     #define BMB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                           23
52083     #define BMB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR                                                (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52084     #define BMB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                          24
52085     #define BMB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR                                                 (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52086     #define BMB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                           25
52087     #define BMB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR                                                 (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52088     #define BMB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                           26
52089     #define BMB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                            (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52090     #define BMB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                      27
52091     #define BMB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                            (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52092     #define BMB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                      28
52093     #define BMB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                          (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52094     #define BMB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                    29
52095     #define BMB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR                                                 (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52096     #define BMB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                           30
52097     #define BMB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR                                                (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52098     #define BMB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                          31
52099 #define BMB_REG_INT_MASK_4                                                                           0x540124UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52100     #define BMB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
52101     #define BMB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                         0
52102     #define BMB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_STRT_FIFO_ERROR .
52103     #define BMB_REG_INT_MASK_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                          1
52104     #define BMB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR                                                 (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_REQ_FIFO_ERROR .
52105     #define BMB_REG_INT_MASK_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                           2
52106     #define BMB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_DSCR_FIFO_ERROR .
52107     #define BMB_REG_INT_MASK_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                          3
52108     #define BMB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
52109     #define BMB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                         4
52110     #define BMB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
52111     #define BMB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                           7
52112     #define BMB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR                                            (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
52113     #define BMB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                      8
52114     #define BMB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
52115     #define BMB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                          9
52116     #define BMB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
52117     #define BMB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                          10
52118     #define BMB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
52119     #define BMB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                          11
52120     #define BMB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
52121     #define BMB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                          12
52122     #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
52123     #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                          13
52124     #define BMB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR                                                (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT5_RLS_FIFO_ERROR .
52125     #define BMB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                          14
52126     #define BMB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT6_RLS_FIFO_ERROR .
52127     #define BMB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                          15
52128     #define BMB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT7_RLS_FIFO_ERROR .
52129     #define BMB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                          16
52130     #define BMB_REG_INT_MASK_4_RC_PKT8_RLS_FIFO_ERROR                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT8_RLS_FIFO_ERROR .
52131     #define BMB_REG_INT_MASK_4_RC_PKT8_RLS_FIFO_ERROR_SHIFT                                          17
52132     #define BMB_REG_INT_MASK_4_RC_PKT9_RLS_FIFO_ERROR                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT9_RLS_FIFO_ERROR .
52133     #define BMB_REG_INT_MASK_4_RC_PKT9_RLS_FIFO_ERROR_SHIFT                                          18
52134     #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR                                                     (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
52135     #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR_SHIFT                                               19
52136     #define BMB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
52137     #define BMB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                          23
52138     #define BMB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
52139     #define BMB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                         24
52140     #define BMB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR                                                (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
52141     #define BMB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                          25
52142     #define BMB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
52143     #define BMB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                          26
52144     #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
52145     #define BMB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                     27
52146     #define BMB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
52147     #define BMB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                     28
52148     #define BMB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                         (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
52149     #define BMB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                   29
52150     #define BMB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
52151     #define BMB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                          30
52152     #define BMB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR                                               (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
52153     #define BMB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                         31
52154 #define BMB_REG_INT_STS_WR_4                                                                         0x540128UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52155     #define BMB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR                                             (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52156     #define BMB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                       0
52157     #define BMB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR                                              (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
52158     #define BMB_REG_INT_STS_WR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                        1
52159     #define BMB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR                                               (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
52160     #define BMB_REG_INT_STS_WR_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                         2
52161     #define BMB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR                                              (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
52162     #define BMB_REG_INT_STS_WR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                        3
52163     #define BMB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR                                             (0x1<<4) // Read SOP client queue FIFO error.
52164     #define BMB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                       4
52165     #define BMB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR                                               (0x1<<7) // Link list arbiter release FIFO error.
52166     #define BMB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                         7
52167     #define BMB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR                                          (0x1<<8) // Link list arbiter prefetch FIFO error.
52168     #define BMB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                    8
52169     #define BMB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR                                              (0x1<<9) // Read packet client rc0 release fifo error
52170     #define BMB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                        9
52171     #define BMB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR                                              (0x1<<10) // Read packet client rc1 release fifo error
52172     #define BMB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                        10
52173     #define BMB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR                                              (0x1<<11) // Read packet client rc2 release fifo error
52174     #define BMB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                        11
52175     #define BMB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR                                              (0x1<<12) // Read packet client rc3 release fifo error
52176     #define BMB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                        12
52177     #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR                                              (0x1<<13) // Read packet client rc4 release fifo error
52178     #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                        13
52179     #define BMB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR                                              (0x1<<14) // Read packet client rc4 release fifo error
52180     #define BMB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                        14
52181     #define BMB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR                                              (0x1<<15) // Read packet client rc4 release fifo error
52182     #define BMB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                        15
52183     #define BMB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR                                              (0x1<<16) // Read packet client rc4 release fifo error
52184     #define BMB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                        16
52185     #define BMB_REG_INT_STS_WR_4_RC_PKT8_RLS_FIFO_ERROR                                              (0x1<<17) // Read packet client rc4 release fifo error
52186     #define BMB_REG_INT_STS_WR_4_RC_PKT8_RLS_FIFO_ERROR_SHIFT                                        17
52187     #define BMB_REG_INT_STS_WR_4_RC_PKT9_RLS_FIFO_ERROR                                              (0x1<<18) // Read packet client rc4 release fifo error
52188     #define BMB_REG_INT_STS_WR_4_RC_PKT9_RLS_FIFO_ERROR_SHIFT                                        18
52189     #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR                                                   (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
52190     #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR_SHIFT                                             19
52191     #define BMB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR                                              (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
52192     #define BMB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                        23
52193     #define BMB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR                                             (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52194     #define BMB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                       24
52195     #define BMB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR                                              (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52196     #define BMB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                        25
52197     #define BMB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR                                              (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52198     #define BMB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                        26
52199     #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                         (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52200     #define BMB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                   27
52201     #define BMB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                         (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52202     #define BMB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                   28
52203     #define BMB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                       (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52204     #define BMB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                 29
52205     #define BMB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR                                              (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52206     #define BMB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                        30
52207     #define BMB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR                                             (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52208     #define BMB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                       31
52209 #define BMB_REG_INT_STS_CLR_4                                                                        0x54012cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52210     #define BMB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR                                            (0x1<<0) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52211     #define BMB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                      0
52212     #define BMB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR                                             (0x1<<1) // Read SOP client strt pointer FIFO error RX_INT::/RX_INT/d in Comments.
52213     #define BMB_REG_INT_STS_CLR_4_RC_SOP_STRT_FIFO_ERROR_SHIFT                                       1
52214     #define BMB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR                                              (0x1<<2) // Read SOP client request FIFO error RX_INT::/RX_INT/d in Comments.
52215     #define BMB_REG_INT_STS_CLR_4_RC_SOP_REQ_FIFO_ERROR_SHIFT                                        2
52216     #define BMB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR                                             (0x1<<3) // Read SOP client descriptor FIFO error RX_INT::/RX_INT/d in Comments.
52217     #define BMB_REG_INT_STS_CLR_4_RC_SOP_DSCR_FIFO_ERROR_SHIFT                                       3
52218     #define BMB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR                                            (0x1<<4) // Read SOP client queue FIFO error.
52219     #define BMB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                      4
52220     #define BMB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR                                              (0x1<<7) // Link list arbiter release FIFO error.
52221     #define BMB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                        7
52222     #define BMB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR                                         (0x1<<8) // Link list arbiter prefetch FIFO error.
52223     #define BMB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                   8
52224     #define BMB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR                                             (0x1<<9) // Read packet client rc0 release fifo error
52225     #define BMB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                       9
52226     #define BMB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR                                             (0x1<<10) // Read packet client rc1 release fifo error
52227     #define BMB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                       10
52228     #define BMB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR                                             (0x1<<11) // Read packet client rc2 release fifo error
52229     #define BMB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                       11
52230     #define BMB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR                                             (0x1<<12) // Read packet client rc3 release fifo error
52231     #define BMB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                       12
52232     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR                                             (0x1<<13) // Read packet client rc4 release fifo error
52233     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                       13
52234     #define BMB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR                                             (0x1<<14) // Read packet client rc4 release fifo error
52235     #define BMB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                       14
52236     #define BMB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR                                             (0x1<<15) // Read packet client rc4 release fifo error
52237     #define BMB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                       15
52238     #define BMB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR                                             (0x1<<16) // Read packet client rc4 release fifo error
52239     #define BMB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                       16
52240     #define BMB_REG_INT_STS_CLR_4_RC_PKT8_RLS_FIFO_ERROR                                             (0x1<<17) // Read packet client rc4 release fifo error
52241     #define BMB_REG_INT_STS_CLR_4_RC_PKT8_RLS_FIFO_ERROR_SHIFT                                       17
52242     #define BMB_REG_INT_STS_CLR_4_RC_PKT9_RLS_FIFO_ERROR                                             (0x1<<18) // Read packet client rc4 release fifo error
52243     #define BMB_REG_INT_STS_CLR_4_RC_PKT9_RLS_FIFO_ERROR_SHIFT                                       18
52244     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR                                                  (0x1<<19) // Read packet client rc3 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
52245     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR_SHIFT                                            19
52246     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR                                             (0x1<<23) // Read packet client rc3 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
52247     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                       23
52248     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR                                            (0x1<<24) // Read packet client rc3 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52249     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                      24
52250     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR                                             (0x1<<25) // Read packet client rc3 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52251     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                       25
52252     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR                                             (0x1<<26) // Read packet client rc3 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52253     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                       26
52254     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                        (0x1<<27) // Read packet client rc3 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52255     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                  27
52256     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                        (0x1<<28) // Read packet client rc3 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52257     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                  28
52258     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                      (0x1<<29) // Read packet client rc3 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52259     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                29
52260     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR                                             (0x1<<30) // Read packet client rc3 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52261     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                       30
52262     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR                                            (0x1<<31) // Read packet client rc3 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
52263     #define BMB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                      31
52264 #define BMB_REG_INT_STS_5                                                                            0x540138UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52265     #define BMB_REG_INT_STS_5_RC_PKT5_RLS_ERROR                                                      (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
52266     #define BMB_REG_INT_STS_5_RC_PKT5_RLS_ERROR_SHIFT                                                0
52267     #define BMB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR                                                 (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
52268     #define BMB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                           2
52269     #define BMB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR                                                (0x1<<3) // Read packet client5 side info FIFO error
52270     #define BMB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                          3
52271     #define BMB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR                                                 (0x1<<4) // Read packet client5 request FIFO error
52272     #define BMB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                           4
52273     #define BMB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR                                                 (0x1<<5) // Read packet client5 block FIFO error
52274     #define BMB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                           5
52275     #define BMB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                            (0x1<<6) // Read packet client5 releases left FIFO error
52276     #define BMB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                      6
52277     #define BMB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                            (0x1<<7) // Read packet client5 start pointer FIFO error
52278     #define BMB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                      7
52279     #define BMB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                          (0x1<<8) // Read packet client5 second pointer FIFO
52280     #define BMB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                    8
52281     #define BMB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR                                                 (0x1<<9) // Read packet client5 response FIFO error
52282     #define BMB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                           9
52283     #define BMB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR                                                (0x1<<10) // Read packet client5 descriptor FIFO error
52284     #define BMB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                          10
52285     #define BMB_REG_INT_STS_5_RC_PKT6_RLS_ERROR                                                      (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
52286     #define BMB_REG_INT_STS_5_RC_PKT6_RLS_ERROR_SHIFT                                                11
52287     #define BMB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR                                                 (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
52288     #define BMB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                           13
52289     #define BMB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR                                                (0x1<<14) // Read packet client6 side info FIFO error
52290     #define BMB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                          14
52291     #define BMB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR                                                 (0x1<<15) // Read packet client6 request FIFO error
52292     #define BMB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                           15
52293     #define BMB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR                                                 (0x1<<16) // Read packet client6 block FIFO error
52294     #define BMB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                           16
52295     #define BMB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                            (0x1<<17) // Read packet client6 releases left FIFO error
52296     #define BMB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                      17
52297     #define BMB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                            (0x1<<18) // Read packet client6 start pointer FIFO error
52298     #define BMB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                      18
52299     #define BMB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                          (0x1<<19) // Read packet client6 second pointer FIFO
52300     #define BMB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                    19
52301     #define BMB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR                                                 (0x1<<20) // Read packet client6 response FIFO error
52302     #define BMB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                           20
52303     #define BMB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR                                                (0x1<<21) // Read packet client6 descriptor FIFO error
52304     #define BMB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                          21
52305     #define BMB_REG_INT_STS_5_RC_PKT7_RLS_ERROR                                                      (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
52306     #define BMB_REG_INT_STS_5_RC_PKT7_RLS_ERROR_SHIFT                                                22
52307     #define BMB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR                                                 (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
52308     #define BMB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                           24
52309     #define BMB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR                                                (0x1<<25) // Read packet client7 side info FIFO error
52310     #define BMB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                          25
52311     #define BMB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR                                                 (0x1<<26) // Read packet client7 request FIFO error
52312     #define BMB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                           26
52313     #define BMB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR                                                 (0x1<<27) // Read packet client7 block FIFO error
52314     #define BMB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                           27
52315     #define BMB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                            (0x1<<28) // Read packet client7 releases left FIFO error
52316     #define BMB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                      28
52317     #define BMB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                            (0x1<<29) // Read packet client7 start pointer FIFO error
52318     #define BMB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                      29
52319     #define BMB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                          (0x1<<30) // Read packet client7 second pointer FIFO
52320     #define BMB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                    30
52321     #define BMB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR                                                 (0x1<<31) // Read packet client7 response FIFO error
52322     #define BMB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                           31
52323 #define BMB_REG_INT_MASK_5                                                                           0x54013cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52324     #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
52325     #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR_SHIFT                                               0
52326     #define BMB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_PROTOCOL_ERROR .
52327     #define BMB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                          2
52328     #define BMB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_SIDE_FIFO_ERROR .
52329     #define BMB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                         3
52330     #define BMB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_REQ_FIFO_ERROR .
52331     #define BMB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                          4
52332     #define BMB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_BLK_FIFO_ERROR .
52333     #define BMB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                          5
52334     #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                           (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RLS_LEFT_FIFO_ERROR .
52335     #define BMB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                     6
52336     #define BMB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_STRT_PTR_FIFO_ERROR .
52337     #define BMB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                     7
52338     #define BMB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_SECOND_PTR_FIFO_ERROR .
52339     #define BMB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                   8
52340     #define BMB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_RSP_FIFO_ERROR .
52341     #define BMB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                          9
52342     #define BMB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT5_DSCR_FIFO_ERROR .
52343     #define BMB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                         10
52344     #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RLS_ERROR .
52345     #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR_SHIFT                                               11
52346     #define BMB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_PROTOCOL_ERROR .
52347     #define BMB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                          13
52348     #define BMB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_SIDE_FIFO_ERROR .
52349     #define BMB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                         14
52350     #define BMB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_REQ_FIFO_ERROR .
52351     #define BMB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                          15
52352     #define BMB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_BLK_FIFO_ERROR .
52353     #define BMB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                          16
52354     #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RLS_LEFT_FIFO_ERROR .
52355     #define BMB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                     17
52356     #define BMB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                           (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_STRT_PTR_FIFO_ERROR .
52357     #define BMB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                     18
52358     #define BMB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_SECOND_PTR_FIFO_ERROR .
52359     #define BMB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                   19
52360     #define BMB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR                                                (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_RSP_FIFO_ERROR .
52361     #define BMB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                          20
52362     #define BMB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT6_DSCR_FIFO_ERROR .
52363     #define BMB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                         21
52364     #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR                                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RLS_ERROR .
52365     #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR_SHIFT                                               22
52366     #define BMB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR                                                (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_PROTOCOL_ERROR .
52367     #define BMB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                          24
52368     #define BMB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_SIDE_FIFO_ERROR .
52369     #define BMB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                         25
52370     #define BMB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_REQ_FIFO_ERROR .
52371     #define BMB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                          26
52372     #define BMB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR                                                (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_BLK_FIFO_ERROR .
52373     #define BMB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                          27
52374     #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RLS_LEFT_FIFO_ERROR .
52375     #define BMB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                     28
52376     #define BMB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_STRT_PTR_FIFO_ERROR .
52377     #define BMB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                     29
52378     #define BMB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_SECOND_PTR_FIFO_ERROR .
52379     #define BMB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                   30
52380     #define BMB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_5.RC_PKT7_RSP_FIFO_ERROR .
52381     #define BMB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                          31
52382 #define BMB_REG_INT_STS_WR_5                                                                         0x540140UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52383     #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR                                                   (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
52384     #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR_SHIFT                                             0
52385     #define BMB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR                                              (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
52386     #define BMB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                        2
52387     #define BMB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR                                             (0x1<<3) // Read packet client5 side info FIFO error
52388     #define BMB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                       3
52389     #define BMB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR                                              (0x1<<4) // Read packet client5 request FIFO error
52390     #define BMB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                        4
52391     #define BMB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR                                              (0x1<<5) // Read packet client5 block FIFO error
52392     #define BMB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                        5
52393     #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                         (0x1<<6) // Read packet client5 releases left FIFO error
52394     #define BMB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                   6
52395     #define BMB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                         (0x1<<7) // Read packet client5 start pointer FIFO error
52396     #define BMB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                   7
52397     #define BMB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                       (0x1<<8) // Read packet client5 second pointer FIFO
52398     #define BMB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                 8
52399     #define BMB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR                                              (0x1<<9) // Read packet client5 response FIFO error
52400     #define BMB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                        9
52401     #define BMB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR                                             (0x1<<10) // Read packet client5 descriptor FIFO error
52402     #define BMB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                       10
52403     #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR                                                   (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
52404     #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR_SHIFT                                             11
52405     #define BMB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR                                              (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
52406     #define BMB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                        13
52407     #define BMB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR                                             (0x1<<14) // Read packet client6 side info FIFO error
52408     #define BMB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                       14
52409     #define BMB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR                                              (0x1<<15) // Read packet client6 request FIFO error
52410     #define BMB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                        15
52411     #define BMB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR                                              (0x1<<16) // Read packet client6 block FIFO error
52412     #define BMB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                        16
52413     #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                         (0x1<<17) // Read packet client6 releases left FIFO error
52414     #define BMB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                   17
52415     #define BMB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                         (0x1<<18) // Read packet client6 start pointer FIFO error
52416     #define BMB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                   18
52417     #define BMB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                       (0x1<<19) // Read packet client6 second pointer FIFO
52418     #define BMB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                 19
52419     #define BMB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR                                              (0x1<<20) // Read packet client6 response FIFO error
52420     #define BMB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                        20
52421     #define BMB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR                                             (0x1<<21) // Read packet client6 descriptor FIFO error
52422     #define BMB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                       21
52423     #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR                                                   (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
52424     #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR_SHIFT                                             22
52425     #define BMB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR                                              (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
52426     #define BMB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                        24
52427     #define BMB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR                                             (0x1<<25) // Read packet client7 side info FIFO error
52428     #define BMB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                       25
52429     #define BMB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR                                              (0x1<<26) // Read packet client7 request FIFO error
52430     #define BMB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                        26
52431     #define BMB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR                                              (0x1<<27) // Read packet client7 block FIFO error
52432     #define BMB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                        27
52433     #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                         (0x1<<28) // Read packet client7 releases left FIFO error
52434     #define BMB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                   28
52435     #define BMB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                         (0x1<<29) // Read packet client7 start pointer FIFO error
52436     #define BMB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                   29
52437     #define BMB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                       (0x1<<30) // Read packet client7 second pointer FIFO
52438     #define BMB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                 30
52439     #define BMB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR                                              (0x1<<31) // Read packet client7 response FIFO error
52440     #define BMB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                        31
52441 #define BMB_REG_INT_STS_CLR_5                                                                        0x540144UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52442     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR                                                  (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
52443     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR_SHIFT                                            0
52444     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR                                             (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
52445     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                       2
52446     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR                                            (0x1<<3) // Read packet client5 side info FIFO error
52447     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                      3
52448     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR                                             (0x1<<4) // Read packet client5 request FIFO error
52449     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                       4
52450     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR                                             (0x1<<5) // Read packet client5 block FIFO error
52451     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                       5
52452     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                        (0x1<<6) // Read packet client5 releases left FIFO error
52453     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                  6
52454     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                        (0x1<<7) // Read packet client5 start pointer FIFO error
52455     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                  7
52456     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                      (0x1<<8) // Read packet client5 second pointer FIFO
52457     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                8
52458     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR                                             (0x1<<9) // Read packet client5 response FIFO error
52459     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                       9
52460     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR                                            (0x1<<10) // Read packet client5 descriptor FIFO error
52461     #define BMB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                      10
52462     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR                                                  (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
52463     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR_SHIFT                                            11
52464     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR                                             (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
52465     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                       13
52466     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR                                            (0x1<<14) // Read packet client6 side info FIFO error
52467     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                      14
52468     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR                                             (0x1<<15) // Read packet client6 request FIFO error
52469     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                       15
52470     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR                                             (0x1<<16) // Read packet client6 block FIFO error
52471     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                       16
52472     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                        (0x1<<17) // Read packet client6 releases left FIFO error
52473     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                  17
52474     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                        (0x1<<18) // Read packet client6 start pointer FIFO error
52475     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                  18
52476     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                      (0x1<<19) // Read packet client6 second pointer FIFO
52477     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                19
52478     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR                                             (0x1<<20) // Read packet client6 response FIFO error
52479     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                       20
52480     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR                                            (0x1<<21) // Read packet client6 descriptor FIFO error
52481     #define BMB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                      21
52482     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR                                                  (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
52483     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR_SHIFT                                            22
52484     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR                                             (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
52485     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                       24
52486     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR                                            (0x1<<25) // Read packet client7 side info FIFO error
52487     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                      25
52488     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR                                             (0x1<<26) // Read packet client7 request FIFO error
52489     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                       26
52490     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR                                             (0x1<<27) // Read packet client7 block FIFO error
52491     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                       27
52492     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                        (0x1<<28) // Read packet client7 releases left FIFO error
52493     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                  28
52494     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                        (0x1<<29) // Read packet client7 start pointer FIFO error
52495     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                  29
52496     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                      (0x1<<30) // Read packet client7 second pointer FIFO
52497     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                30
52498     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR                                             (0x1<<31) // Read packet client7 response FIFO error
52499     #define BMB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                       31
52500 #define BMB_REG_INT_STS_6                                                                            0x540150UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52501     #define BMB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                  (0x1<<0) // Packet available SYNC FIFO error
52502     #define BMB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                            0
52503     #define BMB_REG_INT_STS_6_RC_PKT8_RLS_ERROR                                                      (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
52504     #define BMB_REG_INT_STS_6_RC_PKT8_RLS_ERROR_SHIFT                                                1
52505     #define BMB_REG_INT_STS_6_RC_PKT8_PROTOCOL_ERROR                                                 (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
52506     #define BMB_REG_INT_STS_6_RC_PKT8_PROTOCOL_ERROR_SHIFT                                           3
52507     #define BMB_REG_INT_STS_6_RC_PKT8_SIDE_FIFO_ERROR                                                (0x1<<4) // Read packet client8 side info FIFO error
52508     #define BMB_REG_INT_STS_6_RC_PKT8_SIDE_FIFO_ERROR_SHIFT                                          4
52509     #define BMB_REG_INT_STS_6_RC_PKT8_REQ_FIFO_ERROR                                                 (0x1<<5) // Read packet client8 request FIFO error
52510     #define BMB_REG_INT_STS_6_RC_PKT8_REQ_FIFO_ERROR_SHIFT                                           5
52511     #define BMB_REG_INT_STS_6_RC_PKT8_BLK_FIFO_ERROR                                                 (0x1<<6) // Read packet client8 block FIFO error
52512     #define BMB_REG_INT_STS_6_RC_PKT8_BLK_FIFO_ERROR_SHIFT                                           6
52513     #define BMB_REG_INT_STS_6_RC_PKT8_RLS_LEFT_FIFO_ERROR                                            (0x1<<7) // Read packet client8 releases left FIFO error
52514     #define BMB_REG_INT_STS_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT                                      7
52515     #define BMB_REG_INT_STS_6_RC_PKT8_STRT_PTR_FIFO_ERROR                                            (0x1<<8) // Read packet client8 start pointer FIFO error
52516     #define BMB_REG_INT_STS_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT                                      8
52517     #define BMB_REG_INT_STS_6_RC_PKT8_SECOND_PTR_FIFO_ERROR                                          (0x1<<9) // Read packet client8 second pointer FIFO
52518     #define BMB_REG_INT_STS_6_RC_PKT8_SECOND_PTR_FIFO_ERROR_SHIFT                                    9
52519     #define BMB_REG_INT_STS_6_RC_PKT8_RSP_FIFO_ERROR                                                 (0x1<<10) // Read packet client8 response FIFO error
52520     #define BMB_REG_INT_STS_6_RC_PKT8_RSP_FIFO_ERROR_SHIFT                                           10
52521     #define BMB_REG_INT_STS_6_RC_PKT8_DSCR_FIFO_ERROR                                                (0x1<<11) // Read packet client8 descriptor FIFO error
52522     #define BMB_REG_INT_STS_6_RC_PKT8_DSCR_FIFO_ERROR_SHIFT                                          11
52523     #define BMB_REG_INT_STS_6_RC_PKT9_RLS_ERROR                                                      (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
52524     #define BMB_REG_INT_STS_6_RC_PKT9_RLS_ERROR_SHIFT                                                12
52525     #define BMB_REG_INT_STS_6_RC_PKT9_PROTOCOL_ERROR                                                 (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
52526     #define BMB_REG_INT_STS_6_RC_PKT9_PROTOCOL_ERROR_SHIFT                                           14
52527     #define BMB_REG_INT_STS_6_RC_PKT9_SIDE_FIFO_ERROR                                                (0x1<<15) // Read packet client9 side info FIFO error
52528     #define BMB_REG_INT_STS_6_RC_PKT9_SIDE_FIFO_ERROR_SHIFT                                          15
52529     #define BMB_REG_INT_STS_6_RC_PKT9_REQ_FIFO_ERROR                                                 (0x1<<16) // Read packet client9 request FIFO error
52530     #define BMB_REG_INT_STS_6_RC_PKT9_REQ_FIFO_ERROR_SHIFT                                           16
52531     #define BMB_REG_INT_STS_6_RC_PKT9_BLK_FIFO_ERROR                                                 (0x1<<17) // Read packet client9 block FIFO error
52532     #define BMB_REG_INT_STS_6_RC_PKT9_BLK_FIFO_ERROR_SHIFT                                           17
52533     #define BMB_REG_INT_STS_6_RC_PKT9_RLS_LEFT_FIFO_ERROR                                            (0x1<<18) // Read packet client9 releases left FIFO error
52534     #define BMB_REG_INT_STS_6_RC_PKT9_RLS_LEFT_FIFO_ERROR_SHIFT                                      18
52535     #define BMB_REG_INT_STS_6_RC_PKT9_STRT_PTR_FIFO_ERROR                                            (0x1<<19) // Read packet client9 start pointer FIFO error
52536     #define BMB_REG_INT_STS_6_RC_PKT9_STRT_PTR_FIFO_ERROR_SHIFT                                      19
52537     #define BMB_REG_INT_STS_6_RC_PKT9_SECOND_PTR_FIFO_ERROR                                          (0x1<<20) // Read packet client9 second pointer FIFO
52538     #define BMB_REG_INT_STS_6_RC_PKT9_SECOND_PTR_FIFO_ERROR_SHIFT                                    20
52539     #define BMB_REG_INT_STS_6_RC_PKT9_RSP_FIFO_ERROR                                                 (0x1<<21) // Read packet client9 response FIFO error
52540     #define BMB_REG_INT_STS_6_RC_PKT9_RSP_FIFO_ERROR_SHIFT                                           21
52541     #define BMB_REG_INT_STS_6_RC_PKT9_DSCR_FIFO_ERROR                                                (0x1<<22) // Read packet client9 descriptor FIFO error
52542     #define BMB_REG_INT_STS_6_RC_PKT9_DSCR_FIFO_ERROR_SHIFT                                          22
52543     #define BMB_REG_INT_STS_6_WC4_PROTOCOL_ERROR                                                     (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
52544     #define BMB_REG_INT_STS_6_WC4_PROTOCOL_ERROR_SHIFT                                               23
52545     #define BMB_REG_INT_STS_6_WC5_PROTOCOL_ERROR                                                     (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
52546     #define BMB_REG_INT_STS_6_WC5_PROTOCOL_ERROR_SHIFT                                               24
52547     #define BMB_REG_INT_STS_6_WC6_PROTOCOL_ERROR                                                     (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
52548     #define BMB_REG_INT_STS_6_WC6_PROTOCOL_ERROR_SHIFT                                               25
52549     #define BMB_REG_INT_STS_6_WC7_PROTOCOL_ERROR                                                     (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
52550     #define BMB_REG_INT_STS_6_WC7_PROTOCOL_ERROR_SHIFT                                               26
52551     #define BMB_REG_INT_STS_6_WC8_PROTOCOL_ERROR                                                     (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
52552     #define BMB_REG_INT_STS_6_WC8_PROTOCOL_ERROR_SHIFT                                               27
52553     #define BMB_REG_INT_STS_6_WC9_PROTOCOL_ERROR                                                     (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
52554     #define BMB_REG_INT_STS_6_WC9_PROTOCOL_ERROR_SHIFT                                               28
52555     #define BMB_REG_INT_STS_6_WC4_INP_FIFO_ERROR                                                     (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
52556     #define BMB_REG_INT_STS_6_WC4_INP_FIFO_ERROR_SHIFT                                               29
52557     #define BMB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR                                                     (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
52558     #define BMB_REG_INT_STS_6_WC4_SOP_FIFO_ERROR_SHIFT                                               30
52559     #define BMB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR                                                   (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
52560     #define BMB_REG_INT_STS_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                             31
52561 #define BMB_REG_INT_MASK_6                                                                           0x540154UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52562     #define BMB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
52563     #define BMB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                           0
52564     #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_ERROR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RLS_ERROR .
52565     #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_ERROR_SHIFT                                               1
52566     #define BMB_REG_INT_MASK_6_RC_PKT8_PROTOCOL_ERROR                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_PROTOCOL_ERROR .
52567     #define BMB_REG_INT_MASK_6_RC_PKT8_PROTOCOL_ERROR_SHIFT                                          3
52568     #define BMB_REG_INT_MASK_6_RC_PKT8_SIDE_FIFO_ERROR                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_SIDE_FIFO_ERROR .
52569     #define BMB_REG_INT_MASK_6_RC_PKT8_SIDE_FIFO_ERROR_SHIFT                                         4
52570     #define BMB_REG_INT_MASK_6_RC_PKT8_REQ_FIFO_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_REQ_FIFO_ERROR .
52571     #define BMB_REG_INT_MASK_6_RC_PKT8_REQ_FIFO_ERROR_SHIFT                                          5
52572     #define BMB_REG_INT_MASK_6_RC_PKT8_BLK_FIFO_ERROR                                                (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_BLK_FIFO_ERROR .
52573     #define BMB_REG_INT_MASK_6_RC_PKT8_BLK_FIFO_ERROR_SHIFT                                          6
52574     #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_LEFT_FIFO_ERROR                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RLS_LEFT_FIFO_ERROR .
52575     #define BMB_REG_INT_MASK_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT                                     7
52576     #define BMB_REG_INT_MASK_6_RC_PKT8_STRT_PTR_FIFO_ERROR                                           (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_STRT_PTR_FIFO_ERROR .
52577     #define BMB_REG_INT_MASK_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT                                     8
52578     #define BMB_REG_INT_MASK_6_RC_PKT8_SECOND_PTR_FIFO_ERROR                                         (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_SECOND_PTR_FIFO_ERROR .
52579     #define BMB_REG_INT_MASK_6_RC_PKT8_SECOND_PTR_FIFO_ERROR_SHIFT                                   9
52580     #define BMB_REG_INT_MASK_6_RC_PKT8_RSP_FIFO_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_RSP_FIFO_ERROR .
52581     #define BMB_REG_INT_MASK_6_RC_PKT8_RSP_FIFO_ERROR_SHIFT                                          10
52582     #define BMB_REG_INT_MASK_6_RC_PKT8_DSCR_FIFO_ERROR                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT8_DSCR_FIFO_ERROR .
52583     #define BMB_REG_INT_MASK_6_RC_PKT8_DSCR_FIFO_ERROR_SHIFT                                         11
52584     #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_ERROR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RLS_ERROR .
52585     #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_ERROR_SHIFT                                               12
52586     #define BMB_REG_INT_MASK_6_RC_PKT9_PROTOCOL_ERROR                                                (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_PROTOCOL_ERROR .
52587     #define BMB_REG_INT_MASK_6_RC_PKT9_PROTOCOL_ERROR_SHIFT                                          14
52588     #define BMB_REG_INT_MASK_6_RC_PKT9_SIDE_FIFO_ERROR                                               (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_SIDE_FIFO_ERROR .
52589     #define BMB_REG_INT_MASK_6_RC_PKT9_SIDE_FIFO_ERROR_SHIFT                                         15
52590     #define BMB_REG_INT_MASK_6_RC_PKT9_REQ_FIFO_ERROR                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_REQ_FIFO_ERROR .
52591     #define BMB_REG_INT_MASK_6_RC_PKT9_REQ_FIFO_ERROR_SHIFT                                          16
52592     #define BMB_REG_INT_MASK_6_RC_PKT9_BLK_FIFO_ERROR                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_BLK_FIFO_ERROR .
52593     #define BMB_REG_INT_MASK_6_RC_PKT9_BLK_FIFO_ERROR_SHIFT                                          17
52594     #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_LEFT_FIFO_ERROR                                           (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RLS_LEFT_FIFO_ERROR .
52595     #define BMB_REG_INT_MASK_6_RC_PKT9_RLS_LEFT_FIFO_ERROR_SHIFT                                     18
52596     #define BMB_REG_INT_MASK_6_RC_PKT9_STRT_PTR_FIFO_ERROR                                           (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_STRT_PTR_FIFO_ERROR .
52597     #define BMB_REG_INT_MASK_6_RC_PKT9_STRT_PTR_FIFO_ERROR_SHIFT                                     19
52598     #define BMB_REG_INT_MASK_6_RC_PKT9_SECOND_PTR_FIFO_ERROR                                         (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_SECOND_PTR_FIFO_ERROR .
52599     #define BMB_REG_INT_MASK_6_RC_PKT9_SECOND_PTR_FIFO_ERROR_SHIFT                                   20
52600     #define BMB_REG_INT_MASK_6_RC_PKT9_RSP_FIFO_ERROR                                                (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_RSP_FIFO_ERROR .
52601     #define BMB_REG_INT_MASK_6_RC_PKT9_RSP_FIFO_ERROR_SHIFT                                          21
52602     #define BMB_REG_INT_MASK_6_RC_PKT9_DSCR_FIFO_ERROR                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.RC_PKT9_DSCR_FIFO_ERROR .
52603     #define BMB_REG_INT_MASK_6_RC_PKT9_DSCR_FIFO_ERROR_SHIFT                                         22
52604     #define BMB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_PROTOCOL_ERROR .
52605     #define BMB_REG_INT_MASK_6_WC4_PROTOCOL_ERROR_SHIFT                                              23
52606     #define BMB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC5_PROTOCOL_ERROR .
52607     #define BMB_REG_INT_MASK_6_WC5_PROTOCOL_ERROR_SHIFT                                              24
52608     #define BMB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR                                                    (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC6_PROTOCOL_ERROR .
52609     #define BMB_REG_INT_MASK_6_WC6_PROTOCOL_ERROR_SHIFT                                              25
52610     #define BMB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR                                                    (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC7_PROTOCOL_ERROR .
52611     #define BMB_REG_INT_MASK_6_WC7_PROTOCOL_ERROR_SHIFT                                              26
52612     #define BMB_REG_INT_MASK_6_WC8_PROTOCOL_ERROR                                                    (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC8_PROTOCOL_ERROR .
52613     #define BMB_REG_INT_MASK_6_WC8_PROTOCOL_ERROR_SHIFT                                              27
52614     #define BMB_REG_INT_MASK_6_WC9_PROTOCOL_ERROR                                                    (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC9_PROTOCOL_ERROR .
52615     #define BMB_REG_INT_MASK_6_WC9_PROTOCOL_ERROR_SHIFT                                              28
52616     #define BMB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_INP_FIFO_ERROR .
52617     #define BMB_REG_INT_MASK_6_WC4_INP_FIFO_ERROR_SHIFT                                              29
52618     #define BMB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR                                                    (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_SOP_FIFO_ERROR .
52619     #define BMB_REG_INT_MASK_6_WC4_SOP_FIFO_ERROR_SHIFT                                              30
52620     #define BMB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR                                                  (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_6.WC4_QUEUE_FIFO_ERROR .
52621     #define BMB_REG_INT_MASK_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                            31
52622 #define BMB_REG_INT_STS_WR_6                                                                         0x540158UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52623     #define BMB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                               (0x1<<0) // Packet available SYNC FIFO error
52624     #define BMB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                         0
52625     #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_ERROR                                                   (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
52626     #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_ERROR_SHIFT                                             1
52627     #define BMB_REG_INT_STS_WR_6_RC_PKT8_PROTOCOL_ERROR                                              (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
52628     #define BMB_REG_INT_STS_WR_6_RC_PKT8_PROTOCOL_ERROR_SHIFT                                        3
52629     #define BMB_REG_INT_STS_WR_6_RC_PKT8_SIDE_FIFO_ERROR                                             (0x1<<4) // Read packet client8 side info FIFO error
52630     #define BMB_REG_INT_STS_WR_6_RC_PKT8_SIDE_FIFO_ERROR_SHIFT                                       4
52631     #define BMB_REG_INT_STS_WR_6_RC_PKT8_REQ_FIFO_ERROR                                              (0x1<<5) // Read packet client8 request FIFO error
52632     #define BMB_REG_INT_STS_WR_6_RC_PKT8_REQ_FIFO_ERROR_SHIFT                                        5
52633     #define BMB_REG_INT_STS_WR_6_RC_PKT8_BLK_FIFO_ERROR                                              (0x1<<6) // Read packet client8 block FIFO error
52634     #define BMB_REG_INT_STS_WR_6_RC_PKT8_BLK_FIFO_ERROR_SHIFT                                        6
52635     #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR                                         (0x1<<7) // Read packet client8 releases left FIFO error
52636     #define BMB_REG_INT_STS_WR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT                                   7
52637     #define BMB_REG_INT_STS_WR_6_RC_PKT8_STRT_PTR_FIFO_ERROR                                         (0x1<<8) // Read packet client8 start pointer FIFO error
52638     #define BMB_REG_INT_STS_WR_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT                                   8
52639     #define BMB_REG_INT_STS_WR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR                                       (0x1<<9) // Read packet client8 second pointer FIFO
52640     #define BMB_REG_INT_STS_WR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR_SHIFT                                 9
52641     #define BMB_REG_INT_STS_WR_6_RC_PKT8_RSP_FIFO_ERROR                                              (0x1<<10) // Read packet client8 response FIFO error
52642     #define BMB_REG_INT_STS_WR_6_RC_PKT8_RSP_FIFO_ERROR_SHIFT                                        10
52643     #define BMB_REG_INT_STS_WR_6_RC_PKT8_DSCR_FIFO_ERROR                                             (0x1<<11) // Read packet client8 descriptor FIFO error
52644     #define BMB_REG_INT_STS_WR_6_RC_PKT8_DSCR_FIFO_ERROR_SHIFT                                       11
52645     #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_ERROR                                                   (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
52646     #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_ERROR_SHIFT                                             12
52647     #define BMB_REG_INT_STS_WR_6_RC_PKT9_PROTOCOL_ERROR                                              (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
52648     #define BMB_REG_INT_STS_WR_6_RC_PKT9_PROTOCOL_ERROR_SHIFT                                        14
52649     #define BMB_REG_INT_STS_WR_6_RC_PKT9_SIDE_FIFO_ERROR                                             (0x1<<15) // Read packet client9 side info FIFO error
52650     #define BMB_REG_INT_STS_WR_6_RC_PKT9_SIDE_FIFO_ERROR_SHIFT                                       15
52651     #define BMB_REG_INT_STS_WR_6_RC_PKT9_REQ_FIFO_ERROR                                              (0x1<<16) // Read packet client9 request FIFO error
52652     #define BMB_REG_INT_STS_WR_6_RC_PKT9_REQ_FIFO_ERROR_SHIFT                                        16
52653     #define BMB_REG_INT_STS_WR_6_RC_PKT9_BLK_FIFO_ERROR                                              (0x1<<17) // Read packet client9 block FIFO error
52654     #define BMB_REG_INT_STS_WR_6_RC_PKT9_BLK_FIFO_ERROR_SHIFT                                        17
52655     #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR                                         (0x1<<18) // Read packet client9 releases left FIFO error
52656     #define BMB_REG_INT_STS_WR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR_SHIFT                                   18
52657     #define BMB_REG_INT_STS_WR_6_RC_PKT9_STRT_PTR_FIFO_ERROR                                         (0x1<<19) // Read packet client9 start pointer FIFO error
52658     #define BMB_REG_INT_STS_WR_6_RC_PKT9_STRT_PTR_FIFO_ERROR_SHIFT                                   19
52659     #define BMB_REG_INT_STS_WR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR                                       (0x1<<20) // Read packet client9 second pointer FIFO
52660     #define BMB_REG_INT_STS_WR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR_SHIFT                                 20
52661     #define BMB_REG_INT_STS_WR_6_RC_PKT9_RSP_FIFO_ERROR                                              (0x1<<21) // Read packet client9 response FIFO error
52662     #define BMB_REG_INT_STS_WR_6_RC_PKT9_RSP_FIFO_ERROR_SHIFT                                        21
52663     #define BMB_REG_INT_STS_WR_6_RC_PKT9_DSCR_FIFO_ERROR                                             (0x1<<22) // Read packet client9 descriptor FIFO error
52664     #define BMB_REG_INT_STS_WR_6_RC_PKT9_DSCR_FIFO_ERROR_SHIFT                                       22
52665     #define BMB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR                                                  (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
52666     #define BMB_REG_INT_STS_WR_6_WC4_PROTOCOL_ERROR_SHIFT                                            23
52667     #define BMB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR                                                  (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
52668     #define BMB_REG_INT_STS_WR_6_WC5_PROTOCOL_ERROR_SHIFT                                            24
52669     #define BMB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR                                                  (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
52670     #define BMB_REG_INT_STS_WR_6_WC6_PROTOCOL_ERROR_SHIFT                                            25
52671     #define BMB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR                                                  (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
52672     #define BMB_REG_INT_STS_WR_6_WC7_PROTOCOL_ERROR_SHIFT                                            26
52673     #define BMB_REG_INT_STS_WR_6_WC8_PROTOCOL_ERROR                                                  (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
52674     #define BMB_REG_INT_STS_WR_6_WC8_PROTOCOL_ERROR_SHIFT                                            27
52675     #define BMB_REG_INT_STS_WR_6_WC9_PROTOCOL_ERROR                                                  (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
52676     #define BMB_REG_INT_STS_WR_6_WC9_PROTOCOL_ERROR_SHIFT                                            28
52677     #define BMB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR                                                  (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
52678     #define BMB_REG_INT_STS_WR_6_WC4_INP_FIFO_ERROR_SHIFT                                            29
52679     #define BMB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR                                                  (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
52680     #define BMB_REG_INT_STS_WR_6_WC4_SOP_FIFO_ERROR_SHIFT                                            30
52681     #define BMB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR                                                (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
52682     #define BMB_REG_INT_STS_WR_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                          31
52683 #define BMB_REG_INT_STS_CLR_6                                                                        0x54015cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52684     #define BMB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                              (0x1<<0) // Packet available SYNC FIFO error
52685     #define BMB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                        0
52686     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_ERROR                                                  (0x1<<1) // Read packet client8 error when number of requested packet copies is bigger than real number of packet copies
52687     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_ERROR_SHIFT                                            1
52688     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_PROTOCOL_ERROR                                             (0x1<<3) // Read packet client8 error when packet doesn't have SOP or EOP on read response
52689     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_PROTOCOL_ERROR_SHIFT                                       3
52690     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SIDE_FIFO_ERROR                                            (0x1<<4) // Read packet client8 side info FIFO error
52691     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SIDE_FIFO_ERROR_SHIFT                                      4
52692     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_REQ_FIFO_ERROR                                             (0x1<<5) // Read packet client8 request FIFO error
52693     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_REQ_FIFO_ERROR_SHIFT                                       5
52694     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_BLK_FIFO_ERROR                                             (0x1<<6) // Read packet client8 block FIFO error
52695     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_BLK_FIFO_ERROR_SHIFT                                       6
52696     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR                                        (0x1<<7) // Read packet client8 releases left FIFO error
52697     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RLS_LEFT_FIFO_ERROR_SHIFT                                  7
52698     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_STRT_PTR_FIFO_ERROR                                        (0x1<<8) // Read packet client8 start pointer FIFO error
52699     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_STRT_PTR_FIFO_ERROR_SHIFT                                  8
52700     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR                                      (0x1<<9) // Read packet client8 second pointer FIFO
52701     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_SECOND_PTR_FIFO_ERROR_SHIFT                                9
52702     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RSP_FIFO_ERROR                                             (0x1<<10) // Read packet client8 response FIFO error
52703     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_RSP_FIFO_ERROR_SHIFT                                       10
52704     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_DSCR_FIFO_ERROR                                            (0x1<<11) // Read packet client8 descriptor FIFO error
52705     #define BMB_REG_INT_STS_CLR_6_RC_PKT8_DSCR_FIFO_ERROR_SHIFT                                      11
52706     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_ERROR                                                  (0x1<<12) // Read packet client9 error when number of requested packet copies is bigger than real number of packet copies
52707     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_ERROR_SHIFT                                            12
52708     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_PROTOCOL_ERROR                                             (0x1<<14) // Read packet client9 error when packet doesn't have SOP or EOP on read response
52709     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_PROTOCOL_ERROR_SHIFT                                       14
52710     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SIDE_FIFO_ERROR                                            (0x1<<15) // Read packet client9 side info FIFO error
52711     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SIDE_FIFO_ERROR_SHIFT                                      15
52712     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_REQ_FIFO_ERROR                                             (0x1<<16) // Read packet client9 request FIFO error
52713     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_REQ_FIFO_ERROR_SHIFT                                       16
52714     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_BLK_FIFO_ERROR                                             (0x1<<17) // Read packet client9 block FIFO error
52715     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_BLK_FIFO_ERROR_SHIFT                                       17
52716     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR                                        (0x1<<18) // Read packet client9 releases left FIFO error
52717     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RLS_LEFT_FIFO_ERROR_SHIFT                                  18
52718     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_STRT_PTR_FIFO_ERROR                                        (0x1<<19) // Read packet client9 start pointer FIFO error
52719     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_STRT_PTR_FIFO_ERROR_SHIFT                                  19
52720     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR                                      (0x1<<20) // Read packet client9 second pointer FIFO
52721     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_SECOND_PTR_FIFO_ERROR_SHIFT                                20
52722     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RSP_FIFO_ERROR                                             (0x1<<21) // Read packet client9 response FIFO error
52723     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_RSP_FIFO_ERROR_SHIFT                                       21
52724     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_DSCR_FIFO_ERROR                                            (0x1<<22) // Read packet client9 descriptor FIFO error
52725     #define BMB_REG_INT_STS_CLR_6_RC_PKT9_DSCR_FIFO_ERROR_SHIFT                                      22
52726     #define BMB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR                                                 (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 4.
52727     #define BMB_REG_INT_STS_CLR_6_WC4_PROTOCOL_ERROR_SHIFT                                           23
52728     #define BMB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR                                                 (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 5
52729     #define BMB_REG_INT_STS_CLR_6_WC5_PROTOCOL_ERROR_SHIFT                                           24
52730     #define BMB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR                                                 (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 6
52731     #define BMB_REG_INT_STS_CLR_6_WC6_PROTOCOL_ERROR_SHIFT                                           25
52732     #define BMB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR                                                 (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 7
52733     #define BMB_REG_INT_STS_CLR_6_WC7_PROTOCOL_ERROR_SHIFT                                           26
52734     #define BMB_REG_INT_STS_CLR_6_WC8_PROTOCOL_ERROR                                                 (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 8
52735     #define BMB_REG_INT_STS_CLR_6_WC8_PROTOCOL_ERROR_SHIFT                                           27
52736     #define BMB_REG_INT_STS_CLR_6_WC9_PROTOCOL_ERROR                                                 (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Write packet error when packet doesn't have SOP or EOP on write interface 9
52737     #define BMB_REG_INT_STS_CLR_6_WC9_PROTOCOL_ERROR_SHIFT                                           28
52738     #define BMB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR                                                 (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 4 RX_INT::/RX_INT/d in Comments.
52739     #define BMB_REG_INT_STS_CLR_6_WC4_INP_FIFO_ERROR_SHIFT                                           29
52740     #define BMB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR                                                 (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 4
52741     #define BMB_REG_INT_STS_CLR_6_WC4_SOP_FIFO_ERROR_SHIFT                                           30
52742     #define BMB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR                                               (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 4
52743     #define BMB_REG_INT_STS_CLR_6_WC4_QUEUE_FIFO_ERROR_SHIFT                                         31
52744 #define BMB_REG_INT_STS_7                                                                            0x540168UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52745     #define BMB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR                                              (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
52746     #define BMB_REG_INT_STS_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                        0
52747     #define BMB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR                                              (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
52748     #define BMB_REG_INT_STS_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                        1
52749     #define BMB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR                                                    (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
52750     #define BMB_REG_INT_STS_7_WC4_STRT_FIFO_ERROR_SHIFT                                              2
52751     #define BMB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR                                             (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
52752     #define BMB_REG_INT_STS_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                       3
52753     #define BMB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR                                               (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
52754     #define BMB_REG_INT_STS_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                         4
52755     #define BMB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR                                                 (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
52756     #define BMB_REG_INT_STS_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                           5
52757     #define BMB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR                                                  (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
52758     #define BMB_REG_INT_STS_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                            6
52759     #define BMB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR                                                  (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
52760     #define BMB_REG_INT_STS_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                            7
52761     #define BMB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR                                                    (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
52762     #define BMB_REG_INT_STS_7_WC4_LL_PA_CNT_ERROR_SHIFT                                              8
52763     #define BMB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR                                                    (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
52764     #define BMB_REG_INT_STS_7_WC4_BB_PA_CNT_ERROR_SHIFT                                              9
52765     #define BMB_REG_INT_STS_7_WC5_INP_FIFO_ERROR                                                     (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
52766     #define BMB_REG_INT_STS_7_WC5_INP_FIFO_ERROR_SHIFT                                               10
52767     #define BMB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR                                                     (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
52768     #define BMB_REG_INT_STS_7_WC5_SOP_FIFO_ERROR_SHIFT                                               11
52769     #define BMB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR                                                   (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
52770     #define BMB_REG_INT_STS_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                             12
52771     #define BMB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR                                              (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
52772     #define BMB_REG_INT_STS_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                        13
52773     #define BMB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR                                              (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
52774     #define BMB_REG_INT_STS_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                        14
52775     #define BMB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR                                                    (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
52776     #define BMB_REG_INT_STS_7_WC5_STRT_FIFO_ERROR_SHIFT                                              15
52777     #define BMB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR                                             (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
52778     #define BMB_REG_INT_STS_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                       16
52779     #define BMB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR                                               (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
52780     #define BMB_REG_INT_STS_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                         17
52781     #define BMB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR                                                 (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
52782     #define BMB_REG_INT_STS_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                           18
52783     #define BMB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR                                                  (0x1<<19) // Notify FIFO error in write client 5
52784     #define BMB_REG_INT_STS_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                            19
52785     #define BMB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR                                                  (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
52786     #define BMB_REG_INT_STS_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                            20
52787     #define BMB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR                                                    (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
52788     #define BMB_REG_INT_STS_7_WC5_LL_PA_CNT_ERROR_SHIFT                                              21
52789     #define BMB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR                                                    (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
52790     #define BMB_REG_INT_STS_7_WC5_BB_PA_CNT_ERROR_SHIFT                                              22
52791     #define BMB_REG_INT_STS_7_WC6_INP_FIFO_ERROR                                                     (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
52792     #define BMB_REG_INT_STS_7_WC6_INP_FIFO_ERROR_SHIFT                                               23
52793     #define BMB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR                                                     (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
52794     #define BMB_REG_INT_STS_7_WC6_SOP_FIFO_ERROR_SHIFT                                               24
52795     #define BMB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR                                                   (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
52796     #define BMB_REG_INT_STS_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                             25
52797     #define BMB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR                                              (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
52798     #define BMB_REG_INT_STS_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                        26
52799     #define BMB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR                                              (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
52800     #define BMB_REG_INT_STS_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                        27
52801     #define BMB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR                                                    (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
52802     #define BMB_REG_INT_STS_7_WC6_STRT_FIFO_ERROR_SHIFT                                              28
52803     #define BMB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR                                             (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
52804     #define BMB_REG_INT_STS_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                       29
52805     #define BMB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR                                               (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
52806     #define BMB_REG_INT_STS_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                         30
52807     #define BMB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR                                                 (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
52808     #define BMB_REG_INT_STS_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                           31
52809 #define BMB_REG_INT_MASK_7                                                                           0x54016cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52810     #define BMB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR                                             (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_FREE_POINT_FIFO_ERROR .
52811     #define BMB_REG_INT_MASK_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                       0
52812     #define BMB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_NEXT_POINT_FIFO_ERROR .
52813     #define BMB_REG_INT_MASK_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                       1
52814     #define BMB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_STRT_FIFO_ERROR .
52815     #define BMB_REG_INT_MASK_7_WC4_STRT_FIFO_ERROR_SHIFT                                             2
52816     #define BMB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR                                            (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_SECOND_DSCR_FIFO_ERROR .
52817     #define BMB_REG_INT_MASK_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                      3
52818     #define BMB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR                                              (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_PKT_AVAIL_FIFO_ERROR .
52819     #define BMB_REG_INT_MASK_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                        4
52820     #define BMB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_COS_CNT_FIFO_ERROR .
52821     #define BMB_REG_INT_MASK_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                          5
52822     #define BMB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_NOTIFY_FIFO_ERROR .
52823     #define BMB_REG_INT_MASK_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                           6
52824     #define BMB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_LL_REQ_FIFO_ERROR .
52825     #define BMB_REG_INT_MASK_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                           7
52826     #define BMB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR                                                   (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_LL_PA_CNT_ERROR .
52827     #define BMB_REG_INT_MASK_7_WC4_LL_PA_CNT_ERROR_SHIFT                                             8
52828     #define BMB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC4_BB_PA_CNT_ERROR .
52829     #define BMB_REG_INT_MASK_7_WC4_BB_PA_CNT_ERROR_SHIFT                                             9
52830     #define BMB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR                                                    (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_INP_FIFO_ERROR .
52831     #define BMB_REG_INT_MASK_7_WC5_INP_FIFO_ERROR_SHIFT                                              10
52832     #define BMB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR                                                    (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_SOP_FIFO_ERROR .
52833     #define BMB_REG_INT_MASK_7_WC5_SOP_FIFO_ERROR_SHIFT                                              11
52834     #define BMB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR                                                  (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_QUEUE_FIFO_ERROR .
52835     #define BMB_REG_INT_MASK_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                            12
52836     #define BMB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR                                             (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_FREE_POINT_FIFO_ERROR .
52837     #define BMB_REG_INT_MASK_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                       13
52838     #define BMB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR                                             (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_NEXT_POINT_FIFO_ERROR .
52839     #define BMB_REG_INT_MASK_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                       14
52840     #define BMB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR                                                   (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_STRT_FIFO_ERROR .
52841     #define BMB_REG_INT_MASK_7_WC5_STRT_FIFO_ERROR_SHIFT                                             15
52842     #define BMB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR                                            (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_SECOND_DSCR_FIFO_ERROR .
52843     #define BMB_REG_INT_MASK_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                      16
52844     #define BMB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR                                              (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_PKT_AVAIL_FIFO_ERROR .
52845     #define BMB_REG_INT_MASK_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                        17
52846     #define BMB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_COS_CNT_FIFO_ERROR .
52847     #define BMB_REG_INT_MASK_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                          18
52848     #define BMB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_NOTIFY_FIFO_ERROR .
52849     #define BMB_REG_INT_MASK_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                           19
52850     #define BMB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_LL_REQ_FIFO_ERROR .
52851     #define BMB_REG_INT_MASK_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                           20
52852     #define BMB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR                                                   (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_LL_PA_CNT_ERROR .
52853     #define BMB_REG_INT_MASK_7_WC5_LL_PA_CNT_ERROR_SHIFT                                             21
52854     #define BMB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC5_BB_PA_CNT_ERROR .
52855     #define BMB_REG_INT_MASK_7_WC5_BB_PA_CNT_ERROR_SHIFT                                             22
52856     #define BMB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_INP_FIFO_ERROR .
52857     #define BMB_REG_INT_MASK_7_WC6_INP_FIFO_ERROR_SHIFT                                              23
52858     #define BMB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR                                                    (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_SOP_FIFO_ERROR .
52859     #define BMB_REG_INT_MASK_7_WC6_SOP_FIFO_ERROR_SHIFT                                              24
52860     #define BMB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR                                                  (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_QUEUE_FIFO_ERROR .
52861     #define BMB_REG_INT_MASK_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                            25
52862     #define BMB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR                                             (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_FREE_POINT_FIFO_ERROR .
52863     #define BMB_REG_INT_MASK_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                       26
52864     #define BMB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR                                             (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_NEXT_POINT_FIFO_ERROR .
52865     #define BMB_REG_INT_MASK_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                       27
52866     #define BMB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR                                                   (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_STRT_FIFO_ERROR .
52867     #define BMB_REG_INT_MASK_7_WC6_STRT_FIFO_ERROR_SHIFT                                             28
52868     #define BMB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR                                            (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_SECOND_DSCR_FIFO_ERROR .
52869     #define BMB_REG_INT_MASK_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                      29
52870     #define BMB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR                                              (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_PKT_AVAIL_FIFO_ERROR .
52871     #define BMB_REG_INT_MASK_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                        30
52872     #define BMB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_7.WC6_COS_CNT_FIFO_ERROR .
52873     #define BMB_REG_INT_MASK_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                          31
52874 #define BMB_REG_INT_STS_WR_7                                                                         0x540170UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52875     #define BMB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR                                           (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
52876     #define BMB_REG_INT_STS_WR_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                     0
52877     #define BMB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR                                           (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
52878     #define BMB_REG_INT_STS_WR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                     1
52879     #define BMB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR                                                 (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
52880     #define BMB_REG_INT_STS_WR_7_WC4_STRT_FIFO_ERROR_SHIFT                                           2
52881     #define BMB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR                                          (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
52882     #define BMB_REG_INT_STS_WR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                    3
52883     #define BMB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR                                            (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
52884     #define BMB_REG_INT_STS_WR_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                      4
52885     #define BMB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR                                              (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
52886     #define BMB_REG_INT_STS_WR_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                        5
52887     #define BMB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR                                               (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
52888     #define BMB_REG_INT_STS_WR_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                         6
52889     #define BMB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR                                               (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
52890     #define BMB_REG_INT_STS_WR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                         7
52891     #define BMB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR                                                 (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
52892     #define BMB_REG_INT_STS_WR_7_WC4_LL_PA_CNT_ERROR_SHIFT                                           8
52893     #define BMB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR                                                 (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
52894     #define BMB_REG_INT_STS_WR_7_WC4_BB_PA_CNT_ERROR_SHIFT                                           9
52895     #define BMB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR                                                  (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
52896     #define BMB_REG_INT_STS_WR_7_WC5_INP_FIFO_ERROR_SHIFT                                            10
52897     #define BMB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR                                                  (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
52898     #define BMB_REG_INT_STS_WR_7_WC5_SOP_FIFO_ERROR_SHIFT                                            11
52899     #define BMB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR                                                (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
52900     #define BMB_REG_INT_STS_WR_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                          12
52901     #define BMB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR                                           (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
52902     #define BMB_REG_INT_STS_WR_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                     13
52903     #define BMB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR                                           (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
52904     #define BMB_REG_INT_STS_WR_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                     14
52905     #define BMB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR                                                 (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
52906     #define BMB_REG_INT_STS_WR_7_WC5_STRT_FIFO_ERROR_SHIFT                                           15
52907     #define BMB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR                                          (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
52908     #define BMB_REG_INT_STS_WR_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                    16
52909     #define BMB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR                                            (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
52910     #define BMB_REG_INT_STS_WR_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                      17
52911     #define BMB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR                                              (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
52912     #define BMB_REG_INT_STS_WR_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                        18
52913     #define BMB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR                                               (0x1<<19) // Notify FIFO error in write client 5
52914     #define BMB_REG_INT_STS_WR_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                         19
52915     #define BMB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR                                               (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
52916     #define BMB_REG_INT_STS_WR_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                         20
52917     #define BMB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR                                                 (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
52918     #define BMB_REG_INT_STS_WR_7_WC5_LL_PA_CNT_ERROR_SHIFT                                           21
52919     #define BMB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR                                                 (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
52920     #define BMB_REG_INT_STS_WR_7_WC5_BB_PA_CNT_ERROR_SHIFT                                           22
52921     #define BMB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR                                                  (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
52922     #define BMB_REG_INT_STS_WR_7_WC6_INP_FIFO_ERROR_SHIFT                                            23
52923     #define BMB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR                                                  (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
52924     #define BMB_REG_INT_STS_WR_7_WC6_SOP_FIFO_ERROR_SHIFT                                            24
52925     #define BMB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR                                                (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
52926     #define BMB_REG_INT_STS_WR_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                          25
52927     #define BMB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR                                           (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
52928     #define BMB_REG_INT_STS_WR_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                     26
52929     #define BMB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR                                           (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
52930     #define BMB_REG_INT_STS_WR_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                     27
52931     #define BMB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR                                                 (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
52932     #define BMB_REG_INT_STS_WR_7_WC6_STRT_FIFO_ERROR_SHIFT                                           28
52933     #define BMB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR                                          (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
52934     #define BMB_REG_INT_STS_WR_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                    29
52935     #define BMB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR                                            (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
52936     #define BMB_REG_INT_STS_WR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                      30
52937     #define BMB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR                                              (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
52938     #define BMB_REG_INT_STS_WR_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                        31
52939 #define BMB_REG_INT_STS_CLR_7                                                                        0x540174UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
52940     #define BMB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR                                          (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 4
52941     #define BMB_REG_INT_STS_CLR_7_WC4_FREE_POINT_FIFO_ERROR_SHIFT                                    0
52942     #define BMB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR                                          (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 4
52943     #define BMB_REG_INT_STS_CLR_7_WC4_NEXT_POINT_FIFO_ERROR_SHIFT                                    1
52944     #define BMB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR                                                (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 4
52945     #define BMB_REG_INT_STS_CLR_7_WC4_STRT_FIFO_ERROR_SHIFT                                          2
52946     #define BMB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR                                         (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 4
52947     #define BMB_REG_INT_STS_CLR_7_WC4_SECOND_DSCR_FIFO_ERROR_SHIFT                                   3
52948     #define BMB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR                                           (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 4
52949     #define BMB_REG_INT_STS_CLR_7_WC4_PKT_AVAIL_FIFO_ERROR_SHIFT                                     4
52950     #define BMB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR                                             (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 4
52951     #define BMB_REG_INT_STS_CLR_7_WC4_COS_CNT_FIFO_ERROR_SHIFT                                       5
52952     #define BMB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR                                              (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 4
52953     #define BMB_REG_INT_STS_CLR_7_WC4_NOTIFY_FIFO_ERROR_SHIFT                                        6
52954     #define BMB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR                                              (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 4
52955     #define BMB_REG_INT_STS_CLR_7_WC4_LL_REQ_FIFO_ERROR_SHIFT                                        7
52956     #define BMB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR                                                (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 4
52957     #define BMB_REG_INT_STS_CLR_7_WC4_LL_PA_CNT_ERROR_SHIFT                                          8
52958     #define BMB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR                                                (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 4
52959     #define BMB_REG_INT_STS_CLR_7_WC4_BB_PA_CNT_ERROR_SHIFT                                          9
52960     #define BMB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR                                                 (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 5
52961     #define BMB_REG_INT_STS_CLR_7_WC5_INP_FIFO_ERROR_SHIFT                                           10
52962     #define BMB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR                                                 (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 5
52963     #define BMB_REG_INT_STS_CLR_7_WC5_SOP_FIFO_ERROR_SHIFT                                           11
52964     #define BMB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR                                               (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 5
52965     #define BMB_REG_INT_STS_CLR_7_WC5_QUEUE_FIFO_ERROR_SHIFT                                         12
52966     #define BMB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR                                          (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 5
52967     #define BMB_REG_INT_STS_CLR_7_WC5_FREE_POINT_FIFO_ERROR_SHIFT                                    13
52968     #define BMB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR                                          (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 5
52969     #define BMB_REG_INT_STS_CLR_7_WC5_NEXT_POINT_FIFO_ERROR_SHIFT                                    14
52970     #define BMB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR                                                (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 5
52971     #define BMB_REG_INT_STS_CLR_7_WC5_STRT_FIFO_ERROR_SHIFT                                          15
52972     #define BMB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR                                         (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 5
52973     #define BMB_REG_INT_STS_CLR_7_WC5_SECOND_DSCR_FIFO_ERROR_SHIFT                                   16
52974     #define BMB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR                                           (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 5
52975     #define BMB_REG_INT_STS_CLR_7_WC5_PKT_AVAIL_FIFO_ERROR_SHIFT                                     17
52976     #define BMB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR                                             (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 5
52977     #define BMB_REG_INT_STS_CLR_7_WC5_COS_CNT_FIFO_ERROR_SHIFT                                       18
52978     #define BMB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR                                              (0x1<<19) // Notify FIFO error in write client 5
52979     #define BMB_REG_INT_STS_CLR_7_WC5_NOTIFY_FIFO_ERROR_SHIFT                                        19
52980     #define BMB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR                                              (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 5
52981     #define BMB_REG_INT_STS_CLR_7_WC5_LL_REQ_FIFO_ERROR_SHIFT                                        20
52982     #define BMB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR                                                (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 5
52983     #define BMB_REG_INT_STS_CLR_7_WC5_LL_PA_CNT_ERROR_SHIFT                                          21
52984     #define BMB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR                                                (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 5
52985     #define BMB_REG_INT_STS_CLR_7_WC5_BB_PA_CNT_ERROR_SHIFT                                          22
52986     #define BMB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR                                                 (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 6
52987     #define BMB_REG_INT_STS_CLR_7_WC6_INP_FIFO_ERROR_SHIFT                                           23
52988     #define BMB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR                                                 (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 6
52989     #define BMB_REG_INT_STS_CLR_7_WC6_SOP_FIFO_ERROR_SHIFT                                           24
52990     #define BMB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR                                               (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 6
52991     #define BMB_REG_INT_STS_CLR_7_WC6_QUEUE_FIFO_ERROR_SHIFT                                         25
52992     #define BMB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR                                          (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 6
52993     #define BMB_REG_INT_STS_CLR_7_WC6_FREE_POINT_FIFO_ERROR_SHIFT                                    26
52994     #define BMB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR                                          (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 6
52995     #define BMB_REG_INT_STS_CLR_7_WC6_NEXT_POINT_FIFO_ERROR_SHIFT                                    27
52996     #define BMB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR                                                (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 6
52997     #define BMB_REG_INT_STS_CLR_7_WC6_STRT_FIFO_ERROR_SHIFT                                          28
52998     #define BMB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR                                         (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 6
52999     #define BMB_REG_INT_STS_CLR_7_WC6_SECOND_DSCR_FIFO_ERROR_SHIFT                                   29
53000     #define BMB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR                                           (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 6
53001     #define BMB_REG_INT_STS_CLR_7_WC6_PKT_AVAIL_FIFO_ERROR_SHIFT                                     30
53002     #define BMB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR                                             (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 6
53003     #define BMB_REG_INT_STS_CLR_7_WC6_COS_CNT_FIFO_ERROR_SHIFT                                       31
53004 #define BMB_REG_INT_STS_8                                                                            0x540184UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53005     #define BMB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR                                                  (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
53006     #define BMB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                            0
53007     #define BMB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR                                                  (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
53008     #define BMB_REG_INT_STS_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                            1
53009     #define BMB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR                                                    (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
53010     #define BMB_REG_INT_STS_8_WC6_LL_PA_CNT_ERROR_SHIFT                                              2
53011     #define BMB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR                                                    (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
53012     #define BMB_REG_INT_STS_8_WC6_BB_PA_CNT_ERROR_SHIFT                                              3
53013     #define BMB_REG_INT_STS_8_WC7_INP_FIFO_ERROR                                                     (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
53014     #define BMB_REG_INT_STS_8_WC7_INP_FIFO_ERROR_SHIFT                                               4
53015     #define BMB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR                                                     (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
53016     #define BMB_REG_INT_STS_8_WC7_SOP_FIFO_ERROR_SHIFT                                               5
53017     #define BMB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR                                                   (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
53018     #define BMB_REG_INT_STS_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                             6
53019     #define BMB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR                                              (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
53020     #define BMB_REG_INT_STS_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                        7
53021     #define BMB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR                                              (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
53022     #define BMB_REG_INT_STS_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                        8
53023     #define BMB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR                                                    (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
53024     #define BMB_REG_INT_STS_8_WC7_STRT_FIFO_ERROR_SHIFT                                              9
53025     #define BMB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR                                             (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
53026     #define BMB_REG_INT_STS_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                       10
53027     #define BMB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR                                               (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
53028     #define BMB_REG_INT_STS_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                         11
53029     #define BMB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR                                                 (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
53030     #define BMB_REG_INT_STS_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                           12
53031     #define BMB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR                                                  (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
53032     #define BMB_REG_INT_STS_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                            13
53033     #define BMB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR                                                  (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
53034     #define BMB_REG_INT_STS_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                            14
53035     #define BMB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR                                                    (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
53036     #define BMB_REG_INT_STS_8_WC7_LL_PA_CNT_ERROR_SHIFT                                              15
53037     #define BMB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR                                                    (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
53038     #define BMB_REG_INT_STS_8_WC7_BB_PA_CNT_ERROR_SHIFT                                              16
53039     #define BMB_REG_INT_STS_8_WC8_INP_FIFO_ERROR                                                     (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
53040     #define BMB_REG_INT_STS_8_WC8_INP_FIFO_ERROR_SHIFT                                               17
53041     #define BMB_REG_INT_STS_8_WC8_SOP_FIFO_ERROR                                                     (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
53042     #define BMB_REG_INT_STS_8_WC8_SOP_FIFO_ERROR_SHIFT                                               18
53043     #define BMB_REG_INT_STS_8_WC8_QUEUE_FIFO_ERROR                                                   (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
53044     #define BMB_REG_INT_STS_8_WC8_QUEUE_FIFO_ERROR_SHIFT                                             19
53045     #define BMB_REG_INT_STS_8_WC8_FREE_POINT_FIFO_ERROR                                              (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
53046     #define BMB_REG_INT_STS_8_WC8_FREE_POINT_FIFO_ERROR_SHIFT                                        20
53047     #define BMB_REG_INT_STS_8_WC8_NEXT_POINT_FIFO_ERROR                                              (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
53048     #define BMB_REG_INT_STS_8_WC8_NEXT_POINT_FIFO_ERROR_SHIFT                                        21
53049     #define BMB_REG_INT_STS_8_WC8_STRT_FIFO_ERROR                                                    (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
53050     #define BMB_REG_INT_STS_8_WC8_STRT_FIFO_ERROR_SHIFT                                              22
53051     #define BMB_REG_INT_STS_8_WC8_SECOND_DSCR_FIFO_ERROR                                             (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
53052     #define BMB_REG_INT_STS_8_WC8_SECOND_DSCR_FIFO_ERROR_SHIFT                                       23
53053     #define BMB_REG_INT_STS_8_WC8_PKT_AVAIL_FIFO_ERROR                                               (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
53054     #define BMB_REG_INT_STS_8_WC8_PKT_AVAIL_FIFO_ERROR_SHIFT                                         24
53055     #define BMB_REG_INT_STS_8_WC8_COS_CNT_FIFO_ERROR                                                 (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
53056     #define BMB_REG_INT_STS_8_WC8_COS_CNT_FIFO_ERROR_SHIFT                                           25
53057     #define BMB_REG_INT_STS_8_WC8_NOTIFY_FIFO_ERROR                                                  (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
53058     #define BMB_REG_INT_STS_8_WC8_NOTIFY_FIFO_ERROR_SHIFT                                            26
53059     #define BMB_REG_INT_STS_8_WC8_LL_REQ_FIFO_ERROR                                                  (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
53060     #define BMB_REG_INT_STS_8_WC8_LL_REQ_FIFO_ERROR_SHIFT                                            27
53061     #define BMB_REG_INT_STS_8_WC8_LL_PA_CNT_ERROR                                                    (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
53062     #define BMB_REG_INT_STS_8_WC8_LL_PA_CNT_ERROR_SHIFT                                              28
53063     #define BMB_REG_INT_STS_8_WC8_BB_PA_CNT_ERROR                                                    (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
53064     #define BMB_REG_INT_STS_8_WC8_BB_PA_CNT_ERROR_SHIFT                                              29
53065     #define BMB_REG_INT_STS_8_WC9_INP_FIFO_ERROR                                                     (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
53066     #define BMB_REG_INT_STS_8_WC9_INP_FIFO_ERROR_SHIFT                                               30
53067     #define BMB_REG_INT_STS_8_WC9_SOP_FIFO_ERROR                                                     (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
53068     #define BMB_REG_INT_STS_8_WC9_SOP_FIFO_ERROR_SHIFT                                               31
53069 #define BMB_REG_INT_MASK_8                                                                           0x540188UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53070     #define BMB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
53071     #define BMB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                           0
53072     #define BMB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR                                                 (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_LL_REQ_FIFO_ERROR .
53073     #define BMB_REG_INT_MASK_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                           1
53074     #define BMB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_LL_PA_CNT_ERROR .
53075     #define BMB_REG_INT_MASK_8_WC6_LL_PA_CNT_ERROR_SHIFT                                             2
53076     #define BMB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC6_BB_PA_CNT_ERROR .
53077     #define BMB_REG_INT_MASK_8_WC6_BB_PA_CNT_ERROR_SHIFT                                             3
53078     #define BMB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_INP_FIFO_ERROR .
53079     #define BMB_REG_INT_MASK_8_WC7_INP_FIFO_ERROR_SHIFT                                              4
53080     #define BMB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_SOP_FIFO_ERROR .
53081     #define BMB_REG_INT_MASK_8_WC7_SOP_FIFO_ERROR_SHIFT                                              5
53082     #define BMB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR                                                  (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_QUEUE_FIFO_ERROR .
53083     #define BMB_REG_INT_MASK_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                            6
53084     #define BMB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_FREE_POINT_FIFO_ERROR .
53085     #define BMB_REG_INT_MASK_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                       7
53086     #define BMB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_NEXT_POINT_FIFO_ERROR .
53087     #define BMB_REG_INT_MASK_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                       8
53088     #define BMB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_STRT_FIFO_ERROR .
53089     #define BMB_REG_INT_MASK_8_WC7_STRT_FIFO_ERROR_SHIFT                                             9
53090     #define BMB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR                                            (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_SECOND_DSCR_FIFO_ERROR .
53091     #define BMB_REG_INT_MASK_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                      10
53092     #define BMB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR                                              (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_PKT_AVAIL_FIFO_ERROR .
53093     #define BMB_REG_INT_MASK_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                        11
53094     #define BMB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_COS_CNT_FIFO_ERROR .
53095     #define BMB_REG_INT_MASK_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                          12
53096     #define BMB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR                                                 (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_NOTIFY_FIFO_ERROR .
53097     #define BMB_REG_INT_MASK_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                           13
53098     #define BMB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_LL_REQ_FIFO_ERROR .
53099     #define BMB_REG_INT_MASK_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                           14
53100     #define BMB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR                                                   (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_LL_PA_CNT_ERROR .
53101     #define BMB_REG_INT_MASK_8_WC7_LL_PA_CNT_ERROR_SHIFT                                             15
53102     #define BMB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC7_BB_PA_CNT_ERROR .
53103     #define BMB_REG_INT_MASK_8_WC7_BB_PA_CNT_ERROR_SHIFT                                             16
53104     #define BMB_REG_INT_MASK_8_WC8_INP_FIFO_ERROR                                                    (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_INP_FIFO_ERROR .
53105     #define BMB_REG_INT_MASK_8_WC8_INP_FIFO_ERROR_SHIFT                                              17
53106     #define BMB_REG_INT_MASK_8_WC8_SOP_FIFO_ERROR                                                    (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_SOP_FIFO_ERROR .
53107     #define BMB_REG_INT_MASK_8_WC8_SOP_FIFO_ERROR_SHIFT                                              18
53108     #define BMB_REG_INT_MASK_8_WC8_QUEUE_FIFO_ERROR                                                  (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_QUEUE_FIFO_ERROR .
53109     #define BMB_REG_INT_MASK_8_WC8_QUEUE_FIFO_ERROR_SHIFT                                            19
53110     #define BMB_REG_INT_MASK_8_WC8_FREE_POINT_FIFO_ERROR                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_FREE_POINT_FIFO_ERROR .
53111     #define BMB_REG_INT_MASK_8_WC8_FREE_POINT_FIFO_ERROR_SHIFT                                       20
53112     #define BMB_REG_INT_MASK_8_WC8_NEXT_POINT_FIFO_ERROR                                             (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_NEXT_POINT_FIFO_ERROR .
53113     #define BMB_REG_INT_MASK_8_WC8_NEXT_POINT_FIFO_ERROR_SHIFT                                       21
53114     #define BMB_REG_INT_MASK_8_WC8_STRT_FIFO_ERROR                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_STRT_FIFO_ERROR .
53115     #define BMB_REG_INT_MASK_8_WC8_STRT_FIFO_ERROR_SHIFT                                             22
53116     #define BMB_REG_INT_MASK_8_WC8_SECOND_DSCR_FIFO_ERROR                                            (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_SECOND_DSCR_FIFO_ERROR .
53117     #define BMB_REG_INT_MASK_8_WC8_SECOND_DSCR_FIFO_ERROR_SHIFT                                      23
53118     #define BMB_REG_INT_MASK_8_WC8_PKT_AVAIL_FIFO_ERROR                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_PKT_AVAIL_FIFO_ERROR .
53119     #define BMB_REG_INT_MASK_8_WC8_PKT_AVAIL_FIFO_ERROR_SHIFT                                        24
53120     #define BMB_REG_INT_MASK_8_WC8_COS_CNT_FIFO_ERROR                                                (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_COS_CNT_FIFO_ERROR .
53121     #define BMB_REG_INT_MASK_8_WC8_COS_CNT_FIFO_ERROR_SHIFT                                          25
53122     #define BMB_REG_INT_MASK_8_WC8_NOTIFY_FIFO_ERROR                                                 (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_NOTIFY_FIFO_ERROR .
53123     #define BMB_REG_INT_MASK_8_WC8_NOTIFY_FIFO_ERROR_SHIFT                                           26
53124     #define BMB_REG_INT_MASK_8_WC8_LL_REQ_FIFO_ERROR                                                 (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_LL_REQ_FIFO_ERROR .
53125     #define BMB_REG_INT_MASK_8_WC8_LL_REQ_FIFO_ERROR_SHIFT                                           27
53126     #define BMB_REG_INT_MASK_8_WC8_LL_PA_CNT_ERROR                                                   (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_LL_PA_CNT_ERROR .
53127     #define BMB_REG_INT_MASK_8_WC8_LL_PA_CNT_ERROR_SHIFT                                             28
53128     #define BMB_REG_INT_MASK_8_WC8_BB_PA_CNT_ERROR                                                   (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC8_BB_PA_CNT_ERROR .
53129     #define BMB_REG_INT_MASK_8_WC8_BB_PA_CNT_ERROR_SHIFT                                             29
53130     #define BMB_REG_INT_MASK_8_WC9_INP_FIFO_ERROR                                                    (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC9_INP_FIFO_ERROR .
53131     #define BMB_REG_INT_MASK_8_WC9_INP_FIFO_ERROR_SHIFT                                              30
53132     #define BMB_REG_INT_MASK_8_WC9_SOP_FIFO_ERROR                                                    (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_8.WC9_SOP_FIFO_ERROR .
53133     #define BMB_REG_INT_MASK_8_WC9_SOP_FIFO_ERROR_SHIFT                                              31
53134 #define BMB_REG_INT_STS_WR_8                                                                         0x54018cUL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53135     #define BMB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR                                               (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
53136     #define BMB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                         0
53137     #define BMB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR                                               (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
53138     #define BMB_REG_INT_STS_WR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                         1
53139     #define BMB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR                                                 (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
53140     #define BMB_REG_INT_STS_WR_8_WC6_LL_PA_CNT_ERROR_SHIFT                                           2
53141     #define BMB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR                                                 (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
53142     #define BMB_REG_INT_STS_WR_8_WC6_BB_PA_CNT_ERROR_SHIFT                                           3
53143     #define BMB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR                                                  (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
53144     #define BMB_REG_INT_STS_WR_8_WC7_INP_FIFO_ERROR_SHIFT                                            4
53145     #define BMB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR                                                  (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
53146     #define BMB_REG_INT_STS_WR_8_WC7_SOP_FIFO_ERROR_SHIFT                                            5
53147     #define BMB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR                                                (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
53148     #define BMB_REG_INT_STS_WR_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                          6
53149     #define BMB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR                                           (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
53150     #define BMB_REG_INT_STS_WR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                     7
53151     #define BMB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR                                           (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
53152     #define BMB_REG_INT_STS_WR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                     8
53153     #define BMB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR                                                 (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
53154     #define BMB_REG_INT_STS_WR_8_WC7_STRT_FIFO_ERROR_SHIFT                                           9
53155     #define BMB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR                                          (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
53156     #define BMB_REG_INT_STS_WR_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                    10
53157     #define BMB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR                                            (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
53158     #define BMB_REG_INT_STS_WR_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                      11
53159     #define BMB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR                                              (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
53160     #define BMB_REG_INT_STS_WR_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                        12
53161     #define BMB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR                                               (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
53162     #define BMB_REG_INT_STS_WR_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                         13
53163     #define BMB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR                                               (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
53164     #define BMB_REG_INT_STS_WR_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                         14
53165     #define BMB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR                                                 (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
53166     #define BMB_REG_INT_STS_WR_8_WC7_LL_PA_CNT_ERROR_SHIFT                                           15
53167     #define BMB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR                                                 (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
53168     #define BMB_REG_INT_STS_WR_8_WC7_BB_PA_CNT_ERROR_SHIFT                                           16
53169     #define BMB_REG_INT_STS_WR_8_WC8_INP_FIFO_ERROR                                                  (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
53170     #define BMB_REG_INT_STS_WR_8_WC8_INP_FIFO_ERROR_SHIFT                                            17
53171     #define BMB_REG_INT_STS_WR_8_WC8_SOP_FIFO_ERROR                                                  (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
53172     #define BMB_REG_INT_STS_WR_8_WC8_SOP_FIFO_ERROR_SHIFT                                            18
53173     #define BMB_REG_INT_STS_WR_8_WC8_QUEUE_FIFO_ERROR                                                (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
53174     #define BMB_REG_INT_STS_WR_8_WC8_QUEUE_FIFO_ERROR_SHIFT                                          19
53175     #define BMB_REG_INT_STS_WR_8_WC8_FREE_POINT_FIFO_ERROR                                           (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
53176     #define BMB_REG_INT_STS_WR_8_WC8_FREE_POINT_FIFO_ERROR_SHIFT                                     20
53177     #define BMB_REG_INT_STS_WR_8_WC8_NEXT_POINT_FIFO_ERROR                                           (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
53178     #define BMB_REG_INT_STS_WR_8_WC8_NEXT_POINT_FIFO_ERROR_SHIFT                                     21
53179     #define BMB_REG_INT_STS_WR_8_WC8_STRT_FIFO_ERROR                                                 (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
53180     #define BMB_REG_INT_STS_WR_8_WC8_STRT_FIFO_ERROR_SHIFT                                           22
53181     #define BMB_REG_INT_STS_WR_8_WC8_SECOND_DSCR_FIFO_ERROR                                          (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
53182     #define BMB_REG_INT_STS_WR_8_WC8_SECOND_DSCR_FIFO_ERROR_SHIFT                                    23
53183     #define BMB_REG_INT_STS_WR_8_WC8_PKT_AVAIL_FIFO_ERROR                                            (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
53184     #define BMB_REG_INT_STS_WR_8_WC8_PKT_AVAIL_FIFO_ERROR_SHIFT                                      24
53185     #define BMB_REG_INT_STS_WR_8_WC8_COS_CNT_FIFO_ERROR                                              (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
53186     #define BMB_REG_INT_STS_WR_8_WC8_COS_CNT_FIFO_ERROR_SHIFT                                        25
53187     #define BMB_REG_INT_STS_WR_8_WC8_NOTIFY_FIFO_ERROR                                               (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
53188     #define BMB_REG_INT_STS_WR_8_WC8_NOTIFY_FIFO_ERROR_SHIFT                                         26
53189     #define BMB_REG_INT_STS_WR_8_WC8_LL_REQ_FIFO_ERROR                                               (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
53190     #define BMB_REG_INT_STS_WR_8_WC8_LL_REQ_FIFO_ERROR_SHIFT                                         27
53191     #define BMB_REG_INT_STS_WR_8_WC8_LL_PA_CNT_ERROR                                                 (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
53192     #define BMB_REG_INT_STS_WR_8_WC8_LL_PA_CNT_ERROR_SHIFT                                           28
53193     #define BMB_REG_INT_STS_WR_8_WC8_BB_PA_CNT_ERROR                                                 (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
53194     #define BMB_REG_INT_STS_WR_8_WC8_BB_PA_CNT_ERROR_SHIFT                                           29
53195     #define BMB_REG_INT_STS_WR_8_WC9_INP_FIFO_ERROR                                                  (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
53196     #define BMB_REG_INT_STS_WR_8_WC9_INP_FIFO_ERROR_SHIFT                                            30
53197     #define BMB_REG_INT_STS_WR_8_WC9_SOP_FIFO_ERROR                                                  (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
53198     #define BMB_REG_INT_STS_WR_8_WC9_SOP_FIFO_ERROR_SHIFT                                            31
53199 #define BMB_REG_INT_STS_CLR_8                                                                        0x540190UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53200     #define BMB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR                                              (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
53201     #define BMB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                        0
53202     #define BMB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR                                              (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 6
53203     #define BMB_REG_INT_STS_CLR_8_WC6_LL_REQ_FIFO_ERROR_SHIFT                                        1
53204     #define BMB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR                                                (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 6
53205     #define BMB_REG_INT_STS_CLR_8_WC6_LL_PA_CNT_ERROR_SHIFT                                          2
53206     #define BMB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR                                                (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 6
53207     #define BMB_REG_INT_STS_CLR_8_WC6_BB_PA_CNT_ERROR_SHIFT                                          3
53208     #define BMB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR                                                 (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 7
53209     #define BMB_REG_INT_STS_CLR_8_WC7_INP_FIFO_ERROR_SHIFT                                           4
53210     #define BMB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR                                                 (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 7
53211     #define BMB_REG_INT_STS_CLR_8_WC7_SOP_FIFO_ERROR_SHIFT                                           5
53212     #define BMB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR                                               (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 7
53213     #define BMB_REG_INT_STS_CLR_8_WC7_QUEUE_FIFO_ERROR_SHIFT                                         6
53214     #define BMB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR                                          (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 7
53215     #define BMB_REG_INT_STS_CLR_8_WC7_FREE_POINT_FIFO_ERROR_SHIFT                                    7
53216     #define BMB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR                                          (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 7
53217     #define BMB_REG_INT_STS_CLR_8_WC7_NEXT_POINT_FIFO_ERROR_SHIFT                                    8
53218     #define BMB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR                                                (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 7
53219     #define BMB_REG_INT_STS_CLR_8_WC7_STRT_FIFO_ERROR_SHIFT                                          9
53220     #define BMB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR                                         (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 7
53221     #define BMB_REG_INT_STS_CLR_8_WC7_SECOND_DSCR_FIFO_ERROR_SHIFT                                   10
53222     #define BMB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR                                           (0x1<<11) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 7
53223     #define BMB_REG_INT_STS_CLR_8_WC7_PKT_AVAIL_FIFO_ERROR_SHIFT                                     11
53224     #define BMB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR                                             (0x1<<12) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 7
53225     #define BMB_REG_INT_STS_CLR_8_WC7_COS_CNT_FIFO_ERROR_SHIFT                                       12
53226     #define BMB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR                                              (0x1<<13) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 7
53227     #define BMB_REG_INT_STS_CLR_8_WC7_NOTIFY_FIFO_ERROR_SHIFT                                        13
53228     #define BMB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR                                              (0x1<<14) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 7
53229     #define BMB_REG_INT_STS_CLR_8_WC7_LL_REQ_FIFO_ERROR_SHIFT                                        14
53230     #define BMB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR                                                (0x1<<15) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 7
53231     #define BMB_REG_INT_STS_CLR_8_WC7_LL_PA_CNT_ERROR_SHIFT                                          15
53232     #define BMB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR                                                (0x1<<16) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 7
53233     #define BMB_REG_INT_STS_CLR_8_WC7_BB_PA_CNT_ERROR_SHIFT                                          16
53234     #define BMB_REG_INT_STS_CLR_8_WC8_INP_FIFO_ERROR                                                 (0x1<<17) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 8
53235     #define BMB_REG_INT_STS_CLR_8_WC8_INP_FIFO_ERROR_SHIFT                                           17
53236     #define BMB_REG_INT_STS_CLR_8_WC8_SOP_FIFO_ERROR                                                 (0x1<<18) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 8
53237     #define BMB_REG_INT_STS_CLR_8_WC8_SOP_FIFO_ERROR_SHIFT                                           18
53238     #define BMB_REG_INT_STS_CLR_8_WC8_QUEUE_FIFO_ERROR                                               (0x1<<19) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 8
53239     #define BMB_REG_INT_STS_CLR_8_WC8_QUEUE_FIFO_ERROR_SHIFT                                         19
53240     #define BMB_REG_INT_STS_CLR_8_WC8_FREE_POINT_FIFO_ERROR                                          (0x1<<20) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 8
53241     #define BMB_REG_INT_STS_CLR_8_WC8_FREE_POINT_FIFO_ERROR_SHIFT                                    20
53242     #define BMB_REG_INT_STS_CLR_8_WC8_NEXT_POINT_FIFO_ERROR                                          (0x1<<21) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 8
53243     #define BMB_REG_INT_STS_CLR_8_WC8_NEXT_POINT_FIFO_ERROR_SHIFT                                    21
53244     #define BMB_REG_INT_STS_CLR_8_WC8_STRT_FIFO_ERROR                                                (0x1<<22) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 8
53245     #define BMB_REG_INT_STS_CLR_8_WC8_STRT_FIFO_ERROR_SHIFT                                          22
53246     #define BMB_REG_INT_STS_CLR_8_WC8_SECOND_DSCR_FIFO_ERROR                                         (0x1<<23) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 8
53247     #define BMB_REG_INT_STS_CLR_8_WC8_SECOND_DSCR_FIFO_ERROR_SHIFT                                   23
53248     #define BMB_REG_INT_STS_CLR_8_WC8_PKT_AVAIL_FIFO_ERROR                                           (0x1<<24) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 8
53249     #define BMB_REG_INT_STS_CLR_8_WC8_PKT_AVAIL_FIFO_ERROR_SHIFT                                     24
53250     #define BMB_REG_INT_STS_CLR_8_WC8_COS_CNT_FIFO_ERROR                                             (0x1<<25) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 8
53251     #define BMB_REG_INT_STS_CLR_8_WC8_COS_CNT_FIFO_ERROR_SHIFT                                       25
53252     #define BMB_REG_INT_STS_CLR_8_WC8_NOTIFY_FIFO_ERROR                                              (0x1<<26) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 8
53253     #define BMB_REG_INT_STS_CLR_8_WC8_NOTIFY_FIFO_ERROR_SHIFT                                        26
53254     #define BMB_REG_INT_STS_CLR_8_WC8_LL_REQ_FIFO_ERROR                                              (0x1<<27) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 8
53255     #define BMB_REG_INT_STS_CLR_8_WC8_LL_REQ_FIFO_ERROR_SHIFT                                        27
53256     #define BMB_REG_INT_STS_CLR_8_WC8_LL_PA_CNT_ERROR                                                (0x1<<28) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 8
53257     #define BMB_REG_INT_STS_CLR_8_WC8_LL_PA_CNT_ERROR_SHIFT                                          28
53258     #define BMB_REG_INT_STS_CLR_8_WC8_BB_PA_CNT_ERROR                                                (0x1<<29) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 8
53259     #define BMB_REG_INT_STS_CLR_8_WC8_BB_PA_CNT_ERROR_SHIFT                                          29
53260     #define BMB_REG_INT_STS_CLR_8_WC9_INP_FIFO_ERROR                                                 (0x1<<30) // Warning! Check this bit connection for E4 A0 in RTL. Input FIFO error in write client 9
53261     #define BMB_REG_INT_STS_CLR_8_WC9_INP_FIFO_ERROR_SHIFT                                           30
53262     #define BMB_REG_INT_STS_CLR_8_WC9_SOP_FIFO_ERROR                                                 (0x1<<31) // Warning! Check this bit connection for E4 A0 in RTL. SOP FIFO error in write client 9
53263     #define BMB_REG_INT_STS_CLR_8_WC9_SOP_FIFO_ERROR_SHIFT                                           31
53264 #define BMB_REG_INT_STS_9                                                                            0x54019cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53265     #define BMB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR                                                   (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
53266     #define BMB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                             0
53267     #define BMB_REG_INT_STS_9_WC9_FREE_POINT_FIFO_ERROR                                              (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
53268     #define BMB_REG_INT_STS_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT                                        1
53269     #define BMB_REG_INT_STS_9_WC9_NEXT_POINT_FIFO_ERROR                                              (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
53270     #define BMB_REG_INT_STS_9_WC9_NEXT_POINT_FIFO_ERROR_SHIFT                                        2
53271     #define BMB_REG_INT_STS_9_WC9_STRT_FIFO_ERROR                                                    (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
53272     #define BMB_REG_INT_STS_9_WC9_STRT_FIFO_ERROR_SHIFT                                              3
53273     #define BMB_REG_INT_STS_9_WC9_SECOND_DSCR_FIFO_ERROR                                             (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
53274     #define BMB_REG_INT_STS_9_WC9_SECOND_DSCR_FIFO_ERROR_SHIFT                                       4
53275     #define BMB_REG_INT_STS_9_WC9_PKT_AVAIL_FIFO_ERROR                                               (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
53276     #define BMB_REG_INT_STS_9_WC9_PKT_AVAIL_FIFO_ERROR_SHIFT                                         5
53277     #define BMB_REG_INT_STS_9_WC9_COS_CNT_FIFO_ERROR                                                 (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
53278     #define BMB_REG_INT_STS_9_WC9_COS_CNT_FIFO_ERROR_SHIFT                                           6
53279     #define BMB_REG_INT_STS_9_WC9_NOTIFY_FIFO_ERROR                                                  (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
53280     #define BMB_REG_INT_STS_9_WC9_NOTIFY_FIFO_ERROR_SHIFT                                            7
53281     #define BMB_REG_INT_STS_9_WC9_LL_REQ_FIFO_ERROR                                                  (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
53282     #define BMB_REG_INT_STS_9_WC9_LL_REQ_FIFO_ERROR_SHIFT                                            8
53283     #define BMB_REG_INT_STS_9_WC9_LL_PA_CNT_ERROR                                                    (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
53284     #define BMB_REG_INT_STS_9_WC9_LL_PA_CNT_ERROR_SHIFT                                              9
53285     #define BMB_REG_INT_STS_9_WC9_BB_PA_CNT_ERROR                                                    (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
53286     #define BMB_REG_INT_STS_9_WC9_BB_PA_CNT_ERROR_SHIFT                                              10
53287     #define BMB_REG_INT_STS_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR                                         (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
53288     #define BMB_REG_INT_STS_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_SHIFT                                   11
53289     #define BMB_REG_INT_STS_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<12) // SOP output SYNC FIFO error for RC8
53290     #define BMB_REG_INT_STS_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 12
53291     #define BMB_REG_INT_STS_9_RC0_SOP_PEND_FIFO_ERROR                                                (0x1<<13) // SOP pending FIFO error for RC0
53292     #define BMB_REG_INT_STS_9_RC0_SOP_PEND_FIFO_ERROR_SHIFT                                          13
53293     #define BMB_REG_INT_STS_9_RC1_SOP_PEND_FIFO_ERROR                                                (0x1<<14) // SOP pending FIFO error for RC01
53294     #define BMB_REG_INT_STS_9_RC1_SOP_PEND_FIFO_ERROR_SHIFT                                          14
53295     #define BMB_REG_INT_STS_9_RC2_SOP_PEND_FIFO_ERROR                                                (0x1<<15) // SOP pending FIFO error for RC2
53296     #define BMB_REG_INT_STS_9_RC2_SOP_PEND_FIFO_ERROR_SHIFT                                          15
53297     #define BMB_REG_INT_STS_9_RC3_SOP_PEND_FIFO_ERROR                                                (0x1<<16) // SOP pending FIFO error for RC3
53298     #define BMB_REG_INT_STS_9_RC3_SOP_PEND_FIFO_ERROR_SHIFT                                          16
53299     #define BMB_REG_INT_STS_9_RC4_SOP_PEND_FIFO_ERROR                                                (0x1<<17) // SOP pending FIFO error for RC4
53300     #define BMB_REG_INT_STS_9_RC4_SOP_PEND_FIFO_ERROR_SHIFT                                          17
53301     #define BMB_REG_INT_STS_9_RC5_SOP_PEND_FIFO_ERROR                                                (0x1<<18) // SOP pending FIFO error for RC05
53302     #define BMB_REG_INT_STS_9_RC5_SOP_PEND_FIFO_ERROR_SHIFT                                          18
53303     #define BMB_REG_INT_STS_9_RC6_SOP_PEND_FIFO_ERROR                                                (0x1<<19) // SOP pending FIFO error for RC6
53304     #define BMB_REG_INT_STS_9_RC6_SOP_PEND_FIFO_ERROR_SHIFT                                          19
53305     #define BMB_REG_INT_STS_9_RC7_SOP_PEND_FIFO_ERROR                                                (0x1<<20) // SOP pending FIFO error for RC7
53306     #define BMB_REG_INT_STS_9_RC7_SOP_PEND_FIFO_ERROR_SHIFT                                          20
53307     #define BMB_REG_INT_STS_9_RC0_DSCR_PEND_FIFO_ERROR                                               (0x1<<21) // SOP descriptor FIFO error for RC0
53308     #define BMB_REG_INT_STS_9_RC0_DSCR_PEND_FIFO_ERROR_SHIFT                                         21
53309     #define BMB_REG_INT_STS_9_RC1_DSCR_PEND_FIFO_ERROR                                               (0x1<<22) // SOP descriptor FIFO error for RC1
53310     #define BMB_REG_INT_STS_9_RC1_DSCR_PEND_FIFO_ERROR_SHIFT                                         22
53311     #define BMB_REG_INT_STS_9_RC2_DSCR_PEND_FIFO_ERROR                                               (0x1<<23) // SOP descriptor FIFO error for RC02
53312     #define BMB_REG_INT_STS_9_RC2_DSCR_PEND_FIFO_ERROR_SHIFT                                         23
53313     #define BMB_REG_INT_STS_9_RC3_DSCR_PEND_FIFO_ERROR                                               (0x1<<24) // SOP descriptor FIFO error for RC3
53314     #define BMB_REG_INT_STS_9_RC3_DSCR_PEND_FIFO_ERROR_SHIFT                                         24
53315     #define BMB_REG_INT_STS_9_RC4_DSCR_PEND_FIFO_ERROR                                               (0x1<<25) // SOP descriptor FIFO error for RC4
53316     #define BMB_REG_INT_STS_9_RC4_DSCR_PEND_FIFO_ERROR_SHIFT                                         25
53317     #define BMB_REG_INT_STS_9_RC5_DSCR_PEND_FIFO_ERROR                                               (0x1<<26) // SOP descriptor FIFO error for RC5
53318     #define BMB_REG_INT_STS_9_RC5_DSCR_PEND_FIFO_ERROR_SHIFT                                         26
53319     #define BMB_REG_INT_STS_9_RC6_DSCR_PEND_FIFO_ERROR                                               (0x1<<27) // SOP descriptor FIFO error for RC6
53320     #define BMB_REG_INT_STS_9_RC6_DSCR_PEND_FIFO_ERROR_SHIFT                                         27
53321     #define BMB_REG_INT_STS_9_RC7_DSCR_PEND_FIFO_ERROR                                               (0x1<<28) // SOP descriptor FIFO error for RC7
53322     #define BMB_REG_INT_STS_9_RC7_DSCR_PEND_FIFO_ERROR_SHIFT                                         28
53323     #define BMB_REG_INT_STS_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR                                       (0x1<<29) // SOP input SYNC FIFO error for RC8
53324     #define BMB_REG_INT_STS_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                 29
53325     #define BMB_REG_INT_STS_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR                                       (0x1<<30) // SOP input SYNC FIFO error for RC9
53326     #define BMB_REG_INT_STS_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                 30
53327     #define BMB_REG_INT_STS_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<31) // SOP output SYNC FIFO error for RC8
53328     #define BMB_REG_INT_STS_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 31
53329 #define BMB_REG_INT_MASK_9                                                                           0x5401a0UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53330     #define BMB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
53331     #define BMB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                            0
53332     #define BMB_REG_INT_MASK_9_WC9_FREE_POINT_FIFO_ERROR                                             (0x1<<1) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_FREE_POINT_FIFO_ERROR .
53333     #define BMB_REG_INT_MASK_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT                                       1
53334     #define BMB_REG_INT_MASK_9_WC9_NEXT_POINT_FIFO_ERROR                                             (0x1<<2) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_NEXT_POINT_FIFO_ERROR .
53335     #define BMB_REG_INT_MASK_9_WC9_NEXT_POINT_FIFO_ERROR_SHIFT                                       2
53336     #define BMB_REG_INT_MASK_9_WC9_STRT_FIFO_ERROR                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_STRT_FIFO_ERROR .
53337     #define BMB_REG_INT_MASK_9_WC9_STRT_FIFO_ERROR_SHIFT                                             3
53338     #define BMB_REG_INT_MASK_9_WC9_SECOND_DSCR_FIFO_ERROR                                            (0x1<<4) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_SECOND_DSCR_FIFO_ERROR .
53339     #define BMB_REG_INT_MASK_9_WC9_SECOND_DSCR_FIFO_ERROR_SHIFT                                      4
53340     #define BMB_REG_INT_MASK_9_WC9_PKT_AVAIL_FIFO_ERROR                                              (0x1<<5) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_PKT_AVAIL_FIFO_ERROR .
53341     #define BMB_REG_INT_MASK_9_WC9_PKT_AVAIL_FIFO_ERROR_SHIFT                                        5
53342     #define BMB_REG_INT_MASK_9_WC9_COS_CNT_FIFO_ERROR                                                (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_COS_CNT_FIFO_ERROR .
53343     #define BMB_REG_INT_MASK_9_WC9_COS_CNT_FIFO_ERROR_SHIFT                                          6
53344     #define BMB_REG_INT_MASK_9_WC9_NOTIFY_FIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_NOTIFY_FIFO_ERROR .
53345     #define BMB_REG_INT_MASK_9_WC9_NOTIFY_FIFO_ERROR_SHIFT                                           7
53346     #define BMB_REG_INT_MASK_9_WC9_LL_REQ_FIFO_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_LL_REQ_FIFO_ERROR .
53347     #define BMB_REG_INT_MASK_9_WC9_LL_REQ_FIFO_ERROR_SHIFT                                           8
53348     #define BMB_REG_INT_MASK_9_WC9_LL_PA_CNT_ERROR                                                   (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_LL_PA_CNT_ERROR .
53349     #define BMB_REG_INT_MASK_9_WC9_LL_PA_CNT_ERROR_SHIFT                                             9
53350     #define BMB_REG_INT_MASK_9_WC9_BB_PA_CNT_ERROR                                                   (0x1<<10) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.WC9_BB_PA_CNT_ERROR .
53351     #define BMB_REG_INT_MASK_9_WC9_BB_PA_CNT_ERROR_SHIFT                                             10
53352     #define BMB_REG_INT_MASK_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR                                        (0x1<<11) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_RC_OUT_SYNC_FIFO_ERROR .
53353     #define BMB_REG_INT_MASK_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_SHIFT                                  11
53354     #define BMB_REG_INT_MASK_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
53355     #define BMB_REG_INT_MASK_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                12
53356     #define BMB_REG_INT_MASK_9_RC0_SOP_PEND_FIFO_ERROR                                               (0x1<<13) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC0_SOP_PEND_FIFO_ERROR .
53357     #define BMB_REG_INT_MASK_9_RC0_SOP_PEND_FIFO_ERROR_SHIFT                                         13
53358     #define BMB_REG_INT_MASK_9_RC1_SOP_PEND_FIFO_ERROR                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_SOP_PEND_FIFO_ERROR .
53359     #define BMB_REG_INT_MASK_9_RC1_SOP_PEND_FIFO_ERROR_SHIFT                                         14
53360     #define BMB_REG_INT_MASK_9_RC2_SOP_PEND_FIFO_ERROR                                               (0x1<<15) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_SOP_PEND_FIFO_ERROR .
53361     #define BMB_REG_INT_MASK_9_RC2_SOP_PEND_FIFO_ERROR_SHIFT                                         15
53362     #define BMB_REG_INT_MASK_9_RC3_SOP_PEND_FIFO_ERROR                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC3_SOP_PEND_FIFO_ERROR .
53363     #define BMB_REG_INT_MASK_9_RC3_SOP_PEND_FIFO_ERROR_SHIFT                                         16
53364     #define BMB_REG_INT_MASK_9_RC4_SOP_PEND_FIFO_ERROR                                               (0x1<<17) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC4_SOP_PEND_FIFO_ERROR .
53365     #define BMB_REG_INT_MASK_9_RC4_SOP_PEND_FIFO_ERROR_SHIFT                                         17
53366     #define BMB_REG_INT_MASK_9_RC5_SOP_PEND_FIFO_ERROR                                               (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC5_SOP_PEND_FIFO_ERROR .
53367     #define BMB_REG_INT_MASK_9_RC5_SOP_PEND_FIFO_ERROR_SHIFT                                         18
53368     #define BMB_REG_INT_MASK_9_RC6_SOP_PEND_FIFO_ERROR                                               (0x1<<19) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC6_SOP_PEND_FIFO_ERROR .
53369     #define BMB_REG_INT_MASK_9_RC6_SOP_PEND_FIFO_ERROR_SHIFT                                         19
53370     #define BMB_REG_INT_MASK_9_RC7_SOP_PEND_FIFO_ERROR                                               (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC7_SOP_PEND_FIFO_ERROR .
53371     #define BMB_REG_INT_MASK_9_RC7_SOP_PEND_FIFO_ERROR_SHIFT                                         20
53372     #define BMB_REG_INT_MASK_9_RC0_DSCR_PEND_FIFO_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC0_DSCR_PEND_FIFO_ERROR .
53373     #define BMB_REG_INT_MASK_9_RC0_DSCR_PEND_FIFO_ERROR_SHIFT                                        21
53374     #define BMB_REG_INT_MASK_9_RC1_DSCR_PEND_FIFO_ERROR                                              (0x1<<22) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC1_DSCR_PEND_FIFO_ERROR .
53375     #define BMB_REG_INT_MASK_9_RC1_DSCR_PEND_FIFO_ERROR_SHIFT                                        22
53376     #define BMB_REG_INT_MASK_9_RC2_DSCR_PEND_FIFO_ERROR                                              (0x1<<23) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC2_DSCR_PEND_FIFO_ERROR .
53377     #define BMB_REG_INT_MASK_9_RC2_DSCR_PEND_FIFO_ERROR_SHIFT                                        23
53378     #define BMB_REG_INT_MASK_9_RC3_DSCR_PEND_FIFO_ERROR                                              (0x1<<24) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC3_DSCR_PEND_FIFO_ERROR .
53379     #define BMB_REG_INT_MASK_9_RC3_DSCR_PEND_FIFO_ERROR_SHIFT                                        24
53380     #define BMB_REG_INT_MASK_9_RC4_DSCR_PEND_FIFO_ERROR                                              (0x1<<25) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC4_DSCR_PEND_FIFO_ERROR .
53381     #define BMB_REG_INT_MASK_9_RC4_DSCR_PEND_FIFO_ERROR_SHIFT                                        25
53382     #define BMB_REG_INT_MASK_9_RC5_DSCR_PEND_FIFO_ERROR                                              (0x1<<26) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC5_DSCR_PEND_FIFO_ERROR .
53383     #define BMB_REG_INT_MASK_9_RC5_DSCR_PEND_FIFO_ERROR_SHIFT                                        26
53384     #define BMB_REG_INT_MASK_9_RC6_DSCR_PEND_FIFO_ERROR                                              (0x1<<27) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC6_DSCR_PEND_FIFO_ERROR .
53385     #define BMB_REG_INT_MASK_9_RC6_DSCR_PEND_FIFO_ERROR_SHIFT                                        27
53386     #define BMB_REG_INT_MASK_9_RC7_DSCR_PEND_FIFO_ERROR                                              (0x1<<28) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC7_DSCR_PEND_FIFO_ERROR .
53387     #define BMB_REG_INT_MASK_9_RC7_DSCR_PEND_FIFO_ERROR_SHIFT                                        28
53388     #define BMB_REG_INT_MASK_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<29) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR .
53389     #define BMB_REG_INT_MASK_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                29
53390     #define BMB_REG_INT_MASK_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR                                      (0x1<<30) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR .
53391     #define BMB_REG_INT_MASK_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                                30
53392     #define BMB_REG_INT_MASK_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<31) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_9.RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR .
53393     #define BMB_REG_INT_MASK_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                31
53394 #define BMB_REG_INT_STS_WR_9                                                                         0x5401a4UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53395     #define BMB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR                                                (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
53396     #define BMB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                          0
53397     #define BMB_REG_INT_STS_WR_9_WC9_FREE_POINT_FIFO_ERROR                                           (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
53398     #define BMB_REG_INT_STS_WR_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT                                     1
53399     #define BMB_REG_INT_STS_WR_9_WC9_NEXT_POINT_FIFO_ERROR                                           (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
53400     #define BMB_REG_INT_STS_WR_9_WC9_NEXT_POINT_FIFO_ERROR_SHIFT                                     2
53401     #define BMB_REG_INT_STS_WR_9_WC9_STRT_FIFO_ERROR                                                 (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
53402     #define BMB_REG_INT_STS_WR_9_WC9_STRT_FIFO_ERROR_SHIFT                                           3
53403     #define BMB_REG_INT_STS_WR_9_WC9_SECOND_DSCR_FIFO_ERROR                                          (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
53404     #define BMB_REG_INT_STS_WR_9_WC9_SECOND_DSCR_FIFO_ERROR_SHIFT                                    4
53405     #define BMB_REG_INT_STS_WR_9_WC9_PKT_AVAIL_FIFO_ERROR                                            (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
53406     #define BMB_REG_INT_STS_WR_9_WC9_PKT_AVAIL_FIFO_ERROR_SHIFT                                      5
53407     #define BMB_REG_INT_STS_WR_9_WC9_COS_CNT_FIFO_ERROR                                              (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
53408     #define BMB_REG_INT_STS_WR_9_WC9_COS_CNT_FIFO_ERROR_SHIFT                                        6
53409     #define BMB_REG_INT_STS_WR_9_WC9_NOTIFY_FIFO_ERROR                                               (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
53410     #define BMB_REG_INT_STS_WR_9_WC9_NOTIFY_FIFO_ERROR_SHIFT                                         7
53411     #define BMB_REG_INT_STS_WR_9_WC9_LL_REQ_FIFO_ERROR                                               (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
53412     #define BMB_REG_INT_STS_WR_9_WC9_LL_REQ_FIFO_ERROR_SHIFT                                         8
53413     #define BMB_REG_INT_STS_WR_9_WC9_LL_PA_CNT_ERROR                                                 (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
53414     #define BMB_REG_INT_STS_WR_9_WC9_LL_PA_CNT_ERROR_SHIFT                                           9
53415     #define BMB_REG_INT_STS_WR_9_WC9_BB_PA_CNT_ERROR                                                 (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
53416     #define BMB_REG_INT_STS_WR_9_WC9_BB_PA_CNT_ERROR_SHIFT                                           10
53417     #define BMB_REG_INT_STS_WR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR                                      (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
53418     #define BMB_REG_INT_STS_WR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_SHIFT                                11
53419     #define BMB_REG_INT_STS_WR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR                                    (0x1<<12) // SOP output SYNC FIFO error for RC8
53420     #define BMB_REG_INT_STS_WR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                              12
53421     #define BMB_REG_INT_STS_WR_9_RC0_SOP_PEND_FIFO_ERROR                                             (0x1<<13) // SOP pending FIFO error for RC0
53422     #define BMB_REG_INT_STS_WR_9_RC0_SOP_PEND_FIFO_ERROR_SHIFT                                       13
53423     #define BMB_REG_INT_STS_WR_9_RC1_SOP_PEND_FIFO_ERROR                                             (0x1<<14) // SOP pending FIFO error for RC01
53424     #define BMB_REG_INT_STS_WR_9_RC1_SOP_PEND_FIFO_ERROR_SHIFT                                       14
53425     #define BMB_REG_INT_STS_WR_9_RC2_SOP_PEND_FIFO_ERROR                                             (0x1<<15) // SOP pending FIFO error for RC2
53426     #define BMB_REG_INT_STS_WR_9_RC2_SOP_PEND_FIFO_ERROR_SHIFT                                       15
53427     #define BMB_REG_INT_STS_WR_9_RC3_SOP_PEND_FIFO_ERROR                                             (0x1<<16) // SOP pending FIFO error for RC3
53428     #define BMB_REG_INT_STS_WR_9_RC3_SOP_PEND_FIFO_ERROR_SHIFT                                       16
53429     #define BMB_REG_INT_STS_WR_9_RC4_SOP_PEND_FIFO_ERROR                                             (0x1<<17) // SOP pending FIFO error for RC4
53430     #define BMB_REG_INT_STS_WR_9_RC4_SOP_PEND_FIFO_ERROR_SHIFT                                       17
53431     #define BMB_REG_INT_STS_WR_9_RC5_SOP_PEND_FIFO_ERROR                                             (0x1<<18) // SOP pending FIFO error for RC05
53432     #define BMB_REG_INT_STS_WR_9_RC5_SOP_PEND_FIFO_ERROR_SHIFT                                       18
53433     #define BMB_REG_INT_STS_WR_9_RC6_SOP_PEND_FIFO_ERROR                                             (0x1<<19) // SOP pending FIFO error for RC6
53434     #define BMB_REG_INT_STS_WR_9_RC6_SOP_PEND_FIFO_ERROR_SHIFT                                       19
53435     #define BMB_REG_INT_STS_WR_9_RC7_SOP_PEND_FIFO_ERROR                                             (0x1<<20) // SOP pending FIFO error for RC7
53436     #define BMB_REG_INT_STS_WR_9_RC7_SOP_PEND_FIFO_ERROR_SHIFT                                       20
53437     #define BMB_REG_INT_STS_WR_9_RC0_DSCR_PEND_FIFO_ERROR                                            (0x1<<21) // SOP descriptor FIFO error for RC0
53438     #define BMB_REG_INT_STS_WR_9_RC0_DSCR_PEND_FIFO_ERROR_SHIFT                                      21
53439     #define BMB_REG_INT_STS_WR_9_RC1_DSCR_PEND_FIFO_ERROR                                            (0x1<<22) // SOP descriptor FIFO error for RC1
53440     #define BMB_REG_INT_STS_WR_9_RC1_DSCR_PEND_FIFO_ERROR_SHIFT                                      22
53441     #define BMB_REG_INT_STS_WR_9_RC2_DSCR_PEND_FIFO_ERROR                                            (0x1<<23) // SOP descriptor FIFO error for RC02
53442     #define BMB_REG_INT_STS_WR_9_RC2_DSCR_PEND_FIFO_ERROR_SHIFT                                      23
53443     #define BMB_REG_INT_STS_WR_9_RC3_DSCR_PEND_FIFO_ERROR                                            (0x1<<24) // SOP descriptor FIFO error for RC3
53444     #define BMB_REG_INT_STS_WR_9_RC3_DSCR_PEND_FIFO_ERROR_SHIFT                                      24
53445     #define BMB_REG_INT_STS_WR_9_RC4_DSCR_PEND_FIFO_ERROR                                            (0x1<<25) // SOP descriptor FIFO error for RC4
53446     #define BMB_REG_INT_STS_WR_9_RC4_DSCR_PEND_FIFO_ERROR_SHIFT                                      25
53447     #define BMB_REG_INT_STS_WR_9_RC5_DSCR_PEND_FIFO_ERROR                                            (0x1<<26) // SOP descriptor FIFO error for RC5
53448     #define BMB_REG_INT_STS_WR_9_RC5_DSCR_PEND_FIFO_ERROR_SHIFT                                      26
53449     #define BMB_REG_INT_STS_WR_9_RC6_DSCR_PEND_FIFO_ERROR                                            (0x1<<27) // SOP descriptor FIFO error for RC6
53450     #define BMB_REG_INT_STS_WR_9_RC6_DSCR_PEND_FIFO_ERROR_SHIFT                                      27
53451     #define BMB_REG_INT_STS_WR_9_RC7_DSCR_PEND_FIFO_ERROR                                            (0x1<<28) // SOP descriptor FIFO error for RC7
53452     #define BMB_REG_INT_STS_WR_9_RC7_DSCR_PEND_FIFO_ERROR_SHIFT                                      28
53453     #define BMB_REG_INT_STS_WR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR                                    (0x1<<29) // SOP input SYNC FIFO error for RC8
53454     #define BMB_REG_INT_STS_WR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                              29
53455     #define BMB_REG_INT_STS_WR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR                                    (0x1<<30) // SOP input SYNC FIFO error for RC9
53456     #define BMB_REG_INT_STS_WR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                              30
53457     #define BMB_REG_INT_STS_WR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR                                    (0x1<<31) // SOP output SYNC FIFO error for RC8
53458     #define BMB_REG_INT_STS_WR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                              31
53459 #define BMB_REG_INT_STS_CLR_9                                                                        0x5401a8UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53460     #define BMB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR                                               (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
53461     #define BMB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                         0
53462     #define BMB_REG_INT_STS_CLR_9_WC9_FREE_POINT_FIFO_ERROR                                          (0x1<<1) // Warning! Check this bit connection for E4 A0 in RTL. Free ointer FIFO error in write client 9
53463     #define BMB_REG_INT_STS_CLR_9_WC9_FREE_POINT_FIFO_ERROR_SHIFT                                    1
53464     #define BMB_REG_INT_STS_CLR_9_WC9_NEXT_POINT_FIFO_ERROR                                          (0x1<<2) // Warning! Check this bit connection for E4 A0 in RTL. Next pointer FIFO error in write client 9
53465     #define BMB_REG_INT_STS_CLR_9_WC9_NEXT_POINT_FIFO_ERROR_SHIFT                                    2
53466     #define BMB_REG_INT_STS_CLR_9_WC9_STRT_FIFO_ERROR                                                (0x1<<3) // Warning! Check this bit connection for E4 A0 in RTL. Start FIFO error in write client 9
53467     #define BMB_REG_INT_STS_CLR_9_WC9_STRT_FIFO_ERROR_SHIFT                                          3
53468     #define BMB_REG_INT_STS_CLR_9_WC9_SECOND_DSCR_FIFO_ERROR                                         (0x1<<4) // Warning! Check this bit connection for E4 A0 in RTL. Second descriptor FIFO error in write client 9
53469     #define BMB_REG_INT_STS_CLR_9_WC9_SECOND_DSCR_FIFO_ERROR_SHIFT                                   4
53470     #define BMB_REG_INT_STS_CLR_9_WC9_PKT_AVAIL_FIFO_ERROR                                           (0x1<<5) // Warning! Check this bit connection for E4 A0 in RTL. Packet available FIFO error in write client 9
53471     #define BMB_REG_INT_STS_CLR_9_WC9_PKT_AVAIL_FIFO_ERROR_SHIFT                                     5
53472     #define BMB_REG_INT_STS_CLR_9_WC9_COS_CNT_FIFO_ERROR                                             (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. COS counter FIFO error in write client 9
53473     #define BMB_REG_INT_STS_CLR_9_WC9_COS_CNT_FIFO_ERROR_SHIFT                                       6
53474     #define BMB_REG_INT_STS_CLR_9_WC9_NOTIFY_FIFO_ERROR                                              (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 9
53475     #define BMB_REG_INT_STS_CLR_9_WC9_NOTIFY_FIFO_ERROR_SHIFT                                        7
53476     #define BMB_REG_INT_STS_CLR_9_WC9_LL_REQ_FIFO_ERROR                                              (0x1<<8) // Warning! Check this bit connection for E4 A0 in RTL. LL req error in write client 9
53477     #define BMB_REG_INT_STS_CLR_9_WC9_LL_REQ_FIFO_ERROR_SHIFT                                        8
53478     #define BMB_REG_INT_STS_CLR_9_WC9_LL_PA_CNT_ERROR                                                (0x1<<9) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to link list in write client 9
53479     #define BMB_REG_INT_STS_CLR_9_WC9_LL_PA_CNT_ERROR_SHIFT                                          9
53480     #define BMB_REG_INT_STS_CLR_9_WC9_BB_PA_CNT_ERROR                                                (0x1<<10) // Warning! Check this bit connection for E4 A0 in RTL. Packet available counter overflow or underflow for requests to big ram of SOP descriptor in write client 9
53481     #define BMB_REG_INT_STS_CLR_9_WC9_BB_PA_CNT_ERROR_SHIFT                                          10
53482     #define BMB_REG_INT_STS_CLR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR                                     (0x1<<11) // SOP DSCR SYNC FIFO error for RC9
53483     #define BMB_REG_INT_STS_CLR_9_RC9_SOP_RC_OUT_SYNC_FIFO_ERROR_SHIFT                               11
53484     #define BMB_REG_INT_STS_CLR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR                                   (0x1<<12) // SOP output SYNC FIFO error for RC8
53485     #define BMB_REG_INT_STS_CLR_9_RC9_SOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                             12
53486     #define BMB_REG_INT_STS_CLR_9_RC0_SOP_PEND_FIFO_ERROR                                            (0x1<<13) // SOP pending FIFO error for RC0
53487     #define BMB_REG_INT_STS_CLR_9_RC0_SOP_PEND_FIFO_ERROR_SHIFT                                      13
53488     #define BMB_REG_INT_STS_CLR_9_RC1_SOP_PEND_FIFO_ERROR                                            (0x1<<14) // SOP pending FIFO error for RC01
53489     #define BMB_REG_INT_STS_CLR_9_RC1_SOP_PEND_FIFO_ERROR_SHIFT                                      14
53490     #define BMB_REG_INT_STS_CLR_9_RC2_SOP_PEND_FIFO_ERROR                                            (0x1<<15) // SOP pending FIFO error for RC2
53491     #define BMB_REG_INT_STS_CLR_9_RC2_SOP_PEND_FIFO_ERROR_SHIFT                                      15
53492     #define BMB_REG_INT_STS_CLR_9_RC3_SOP_PEND_FIFO_ERROR                                            (0x1<<16) // SOP pending FIFO error for RC3
53493     #define BMB_REG_INT_STS_CLR_9_RC3_SOP_PEND_FIFO_ERROR_SHIFT                                      16
53494     #define BMB_REG_INT_STS_CLR_9_RC4_SOP_PEND_FIFO_ERROR                                            (0x1<<17) // SOP pending FIFO error for RC4
53495     #define BMB_REG_INT_STS_CLR_9_RC4_SOP_PEND_FIFO_ERROR_SHIFT                                      17
53496     #define BMB_REG_INT_STS_CLR_9_RC5_SOP_PEND_FIFO_ERROR                                            (0x1<<18) // SOP pending FIFO error for RC05
53497     #define BMB_REG_INT_STS_CLR_9_RC5_SOP_PEND_FIFO_ERROR_SHIFT                                      18
53498     #define BMB_REG_INT_STS_CLR_9_RC6_SOP_PEND_FIFO_ERROR                                            (0x1<<19) // SOP pending FIFO error for RC6
53499     #define BMB_REG_INT_STS_CLR_9_RC6_SOP_PEND_FIFO_ERROR_SHIFT                                      19
53500     #define BMB_REG_INT_STS_CLR_9_RC7_SOP_PEND_FIFO_ERROR                                            (0x1<<20) // SOP pending FIFO error for RC7
53501     #define BMB_REG_INT_STS_CLR_9_RC7_SOP_PEND_FIFO_ERROR_SHIFT                                      20
53502     #define BMB_REG_INT_STS_CLR_9_RC0_DSCR_PEND_FIFO_ERROR                                           (0x1<<21) // SOP descriptor FIFO error for RC0
53503     #define BMB_REG_INT_STS_CLR_9_RC0_DSCR_PEND_FIFO_ERROR_SHIFT                                     21
53504     #define BMB_REG_INT_STS_CLR_9_RC1_DSCR_PEND_FIFO_ERROR                                           (0x1<<22) // SOP descriptor FIFO error for RC1
53505     #define BMB_REG_INT_STS_CLR_9_RC1_DSCR_PEND_FIFO_ERROR_SHIFT                                     22
53506     #define BMB_REG_INT_STS_CLR_9_RC2_DSCR_PEND_FIFO_ERROR                                           (0x1<<23) // SOP descriptor FIFO error for RC02
53507     #define BMB_REG_INT_STS_CLR_9_RC2_DSCR_PEND_FIFO_ERROR_SHIFT                                     23
53508     #define BMB_REG_INT_STS_CLR_9_RC3_DSCR_PEND_FIFO_ERROR                                           (0x1<<24) // SOP descriptor FIFO error for RC3
53509     #define BMB_REG_INT_STS_CLR_9_RC3_DSCR_PEND_FIFO_ERROR_SHIFT                                     24
53510     #define BMB_REG_INT_STS_CLR_9_RC4_DSCR_PEND_FIFO_ERROR                                           (0x1<<25) // SOP descriptor FIFO error for RC4
53511     #define BMB_REG_INT_STS_CLR_9_RC4_DSCR_PEND_FIFO_ERROR_SHIFT                                     25
53512     #define BMB_REG_INT_STS_CLR_9_RC5_DSCR_PEND_FIFO_ERROR                                           (0x1<<26) // SOP descriptor FIFO error for RC5
53513     #define BMB_REG_INT_STS_CLR_9_RC5_DSCR_PEND_FIFO_ERROR_SHIFT                                     26
53514     #define BMB_REG_INT_STS_CLR_9_RC6_DSCR_PEND_FIFO_ERROR                                           (0x1<<27) // SOP descriptor FIFO error for RC6
53515     #define BMB_REG_INT_STS_CLR_9_RC6_DSCR_PEND_FIFO_ERROR_SHIFT                                     27
53516     #define BMB_REG_INT_STS_CLR_9_RC7_DSCR_PEND_FIFO_ERROR                                           (0x1<<28) // SOP descriptor FIFO error for RC7
53517     #define BMB_REG_INT_STS_CLR_9_RC7_DSCR_PEND_FIFO_ERROR_SHIFT                                     28
53518     #define BMB_REG_INT_STS_CLR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR                                   (0x1<<29) // SOP input SYNC FIFO error for RC8
53519     #define BMB_REG_INT_STS_CLR_9_RC8_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                             29
53520     #define BMB_REG_INT_STS_CLR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR                                   (0x1<<30) // SOP input SYNC FIFO error for RC9
53521     #define BMB_REG_INT_STS_CLR_9_RC9_SOP_INP_SYNC_FIFO_PUSH_ERROR_SHIFT                             30
53522     #define BMB_REG_INT_STS_CLR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR                                   (0x1<<31) // SOP output SYNC FIFO error for RC8
53523     #define BMB_REG_INT_STS_CLR_9_RC8_SOP_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                             31
53524 #define BMB_REG_INT_STS_10                                                                           0x5401b4UL //Access:R    DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53525     #define BMB_REG_INT_STS_10_RC_GNT_PEND_FIFO_ERROR                                                (0x1<<0) //
53526     #define BMB_REG_INT_STS_10_RC_GNT_PEND_FIFO_ERROR_SHIFT                                          0
53527     #define BMB_REG_INT_STS_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR                                          (0x1<<20) // Packet RC output SYNC FIFO error
53528     #define BMB_REG_INT_STS_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                    20
53529     #define BMB_REG_INT_STS_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR                                          (0x1<<21) // Packet RC output SYNC FIFO error
53530     #define BMB_REG_INT_STS_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                    21
53531 #define BMB_REG_INT_MASK_10                                                                          0x5401b8UL //Access:RW   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53532     #define BMB_REG_INT_MASK_10_RC_GNT_PEND_FIFO_ERROR                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC_GNT_PEND_FIFO_ERROR .
53533     #define BMB_REG_INT_MASK_10_RC_GNT_PEND_FIFO_ERROR_SHIFT                                         0
53534     #define BMB_REG_INT_MASK_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR                                         (0x1<<20) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC8_OUT_SYNC_FIFO_PUSH_ERROR .
53535     #define BMB_REG_INT_MASK_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                   20
53536     #define BMB_REG_INT_MASK_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR                                         (0x1<<21) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_10.RC9_OUT_SYNC_FIFO_PUSH_ERROR .
53537     #define BMB_REG_INT_MASK_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                   21
53538 #define BMB_REG_INT_STS_WR_10                                                                        0x5401bcUL //Access:WR   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53539     #define BMB_REG_INT_STS_WR_10_RC_GNT_PEND_FIFO_ERROR                                             (0x1<<0) //
53540     #define BMB_REG_INT_STS_WR_10_RC_GNT_PEND_FIFO_ERROR_SHIFT                                       0
53541     #define BMB_REG_INT_STS_WR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<20) // Packet RC output SYNC FIFO error
53542     #define BMB_REG_INT_STS_WR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 20
53543     #define BMB_REG_INT_STS_WR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR                                       (0x1<<21) // Packet RC output SYNC FIFO error
53544     #define BMB_REG_INT_STS_WR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                 21
53545 #define BMB_REG_INT_STS_CLR_10                                                                       0x5401c0UL //Access:RC   DataWidth:0x16  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53546     #define BMB_REG_INT_STS_CLR_10_RC_GNT_PEND_FIFO_ERROR                                            (0x1<<0) //
53547     #define BMB_REG_INT_STS_CLR_10_RC_GNT_PEND_FIFO_ERROR_SHIFT                                      0
53548     #define BMB_REG_INT_STS_CLR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<20) // Packet RC output SYNC FIFO error
53549     #define BMB_REG_INT_STS_CLR_10_RC8_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                20
53550     #define BMB_REG_INT_STS_CLR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR                                      (0x1<<21) // Packet RC output SYNC FIFO error
53551     #define BMB_REG_INT_STS_CLR_10_RC9_OUT_SYNC_FIFO_PUSH_ERROR_SHIFT                                21
53552 #define BMB_REG_INT_STS_11                                                                           0x5401ccUL //Access:R    DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53553     #define BMB_REG_INT_STS_11_WC8_SYNC_FIFO_PUSH_ERROR                                              (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
53554     #define BMB_REG_INT_STS_11_WC8_SYNC_FIFO_PUSH_ERROR_SHIFT                                        6
53555     #define BMB_REG_INT_STS_11_WC9_SYNC_FIFO_PUSH_ERROR                                              (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
53556     #define BMB_REG_INT_STS_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT                                        7
53557     #define BMB_REG_INT_STS_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR                                        (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
53558     #define BMB_REG_INT_STS_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_SHIFT                                  9
53559     #define BMB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR                                               (0x1<<18) // Read packet client7 descriptor FIFO error
53560     #define BMB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                         18
53561 #define BMB_REG_INT_MASK_11                                                                          0x5401d0UL //Access:RW   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53562     #define BMB_REG_INT_MASK_11_WC8_SYNC_FIFO_PUSH_ERROR                                             (0x1<<6) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.WC8_SYNC_FIFO_PUSH_ERROR .
53563     #define BMB_REG_INT_MASK_11_WC8_SYNC_FIFO_PUSH_ERROR_SHIFT                                       6
53564     #define BMB_REG_INT_MASK_11_WC9_SYNC_FIFO_PUSH_ERROR                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.WC9_SYNC_FIFO_PUSH_ERROR .
53565     #define BMB_REG_INT_MASK_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT                                       7
53566     #define BMB_REG_INT_MASK_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR                                       (0x1<<9) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.RC8_SOP_RC_OUT_SYNC_FIFO_ERROR .
53567     #define BMB_REG_INT_MASK_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_SHIFT                                 9
53568     #define BMB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR                                              (0x1<<18) // This bit masks, when set, the Interrupt bit: BMB_REG_INT_STS_11.RC_PKT7_DSCR_FIFO_ERROR .
53569     #define BMB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                        18
53570 #define BMB_REG_INT_STS_WR_11                                                                        0x5401d4UL //Access:WR   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53571     #define BMB_REG_INT_STS_WR_11_WC8_SYNC_FIFO_PUSH_ERROR                                           (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
53572     #define BMB_REG_INT_STS_WR_11_WC8_SYNC_FIFO_PUSH_ERROR_SHIFT                                     6
53573     #define BMB_REG_INT_STS_WR_11_WC9_SYNC_FIFO_PUSH_ERROR                                           (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
53574     #define BMB_REG_INT_STS_WR_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT                                     7
53575     #define BMB_REG_INT_STS_WR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR                                     (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
53576     #define BMB_REG_INT_STS_WR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_SHIFT                               9
53577     #define BMB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR                                            (0x1<<18) // Read packet client7 descriptor FIFO error
53578     #define BMB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                      18
53579 #define BMB_REG_INT_STS_CLR_11                                                                       0x5401d8UL //Access:RC   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53580     #define BMB_REG_INT_STS_CLR_11_WC8_SYNC_FIFO_PUSH_ERROR                                          (0x1<<6) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
53581     #define BMB_REG_INT_STS_CLR_11_WC8_SYNC_FIFO_PUSH_ERROR_SHIFT                                    6
53582     #define BMB_REG_INT_STS_CLR_11_WC9_SYNC_FIFO_PUSH_ERROR                                          (0x1<<7) // Warning! Check this bit connection for E4 A0 in RTL. WC input SYNC FIFO error
53583     #define BMB_REG_INT_STS_CLR_11_WC9_SYNC_FIFO_PUSH_ERROR_SHIFT                                    7
53584     #define BMB_REG_INT_STS_CLR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR                                    (0x1<<9) // SOP DSCR SYNC FIFO error for RC8
53585     #define BMB_REG_INT_STS_CLR_11_RC8_SOP_RC_OUT_SYNC_FIFO_ERROR_SHIFT                              9
53586     #define BMB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR                                           (0x1<<18) // Read packet client7 descriptor FIFO error
53587     #define BMB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                     18
53588 #define BMB_REG_PRTY_MASK                                                                            0x5401e0UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0 K2
53589     #define BMB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY                                                      (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
53590     #define BMB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY_SHIFT                                                0
53591     #define BMB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY                                                      (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
53592     #define BMB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT                                                1
53593     #define BMB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY                                                      (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
53594     #define BMB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY_SHIFT                                                2
53595     #define BMB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY                                                      (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
53596     #define BMB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT                                                3
53597     #define BMB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                     (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS.DATAPATH_REGISTERS .
53598     #define BMB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                               4
53599 #define BMB_REG_PRTY_MASK_H_0                                                                        0x540404UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53600     #define BMB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
53601     #define BMB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                          0
53602     #define BMB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
53603     #define BMB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT                                          1
53604     #define BMB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT                                                (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
53605     #define BMB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_SHIFT                                          2
53606     #define BMB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
53607     #define BMB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT                                          3
53608     #define BMB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT                                                (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
53609     #define BMB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_SHIFT                                          4
53610     #define BMB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
53611     #define BMB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_SHIFT                                          5
53612     #define BMB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT                                                (0x1<<6) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
53613     #define BMB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_SHIFT                                          6
53614     #define BMB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT                                                (0x1<<7) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
53615     #define BMB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_SHIFT                                          7
53616     #define BMB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT                                                (0x1<<8) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
53617     #define BMB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT                                          8
53618     #define BMB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT                                                (0x1<<9) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
53619     #define BMB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_SHIFT                                          9
53620     #define BMB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT                                                (0x1<<10) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
53621     #define BMB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT                                          10
53622     #define BMB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT                                                (0x1<<11) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
53623     #define BMB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT                                          11
53624     #define BMB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                                (0x1<<12) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
53625     #define BMB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                          12
53626     #define BMB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT                                                (0x1<<13) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
53627     #define BMB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT                                          13
53628     #define BMB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT                                                (0x1<<14) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
53629     #define BMB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_SHIFT                                          14
53630     #define BMB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT                                                (0x1<<15) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
53631     #define BMB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_SHIFT                                          15
53632     #define BMB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM059_I_MEM_PRTY .
53633     #define BMB_REG_PRTY_MASK_H_0_MEM059_I_MEM_PRTY_SHIFT                                            16
53634     #define BMB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM060_I_MEM_PRTY .
53635     #define BMB_REG_PRTY_MASK_H_0_MEM060_I_MEM_PRTY_SHIFT                                            17
53636     #define BMB_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
53637     #define BMB_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_SHIFT                                            18
53638     #define BMB_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
53639     #define BMB_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_SHIFT                                            19
53640     #define BMB_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
53641     #define BMB_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_SHIFT                                            20
53642     #define BMB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
53643     #define BMB_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_SHIFT                                            21
53644     #define BMB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
53645     #define BMB_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_SHIFT                                            22
53646     #define BMB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
53647     #define BMB_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_SHIFT                                            23
53648     #define BMB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
53649     #define BMB_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_SHIFT                                            24
53650     #define BMB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
53651     #define BMB_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_SHIFT                                            25
53652     #define BMB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
53653     #define BMB_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_SHIFT                                            26
53654     #define BMB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM046_I_MEM_PRTY .
53655     #define BMB_REG_PRTY_MASK_H_0_MEM046_I_MEM_PRTY_SHIFT                                            27
53656     #define BMB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
53657     #define BMB_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_SHIFT                                            28
53658     #define BMB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
53659     #define BMB_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_SHIFT                                            29
53660     #define BMB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_0.MEM049_I_MEM_PRTY .
53661     #define BMB_REG_PRTY_MASK_H_0_MEM049_I_MEM_PRTY_SHIFT                                            30
53662 #define BMB_REG_PRTY_MASK_H_1                                                                        0x540414UL //Access:RW   DataWidth:0xf   Multi Field Register.  Chips: BB_A0 BB_B0 K2
53663     #define BMB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
53664     #define BMB_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_SHIFT                                            0
53665     #define BMB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
53666     #define BMB_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_SHIFT                                            1
53667     #define BMB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM052_I_MEM_PRTY .
53668     #define BMB_REG_PRTY_MASK_H_1_MEM052_I_MEM_PRTY_SHIFT                                            2
53669     #define BMB_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
53670     #define BMB_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_SHIFT                                            3
53671     #define BMB_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
53672     #define BMB_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_SHIFT                                            4
53673     #define BMB_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
53674     #define BMB_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_SHIFT                                            5
53675     #define BMB_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM056_I_MEM_PRTY .
53676     #define BMB_REG_PRTY_MASK_H_1_MEM056_I_MEM_PRTY_SHIFT                                            6
53677     #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
53678     #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_A0_SHIFT                                      17
53679     #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
53680     #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_BB_B0_SHIFT                                      7
53681     #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
53682     #define BMB_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_K2_SHIFT                                         7
53683     #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
53684     #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_A0_SHIFT                                      18
53685     #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_B0                                            (0x1<<8) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
53686     #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_BB_B0_SHIFT                                      8
53687     #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_K2                                               (0x1<<8) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
53688     #define BMB_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_K2_SHIFT                                         8
53689     #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
53690     #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_A0_SHIFT                                      19
53691     #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
53692     #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_BB_B0_SHIFT                                      9
53693     #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
53694     #define BMB_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_K2_SHIFT                                         9
53695     #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
53696     #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_A0_SHIFT                                      20
53697     #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
53698     #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_BB_B0_SHIFT                                      10
53699     #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM034_I_MEM_PRTY .
53700     #define BMB_REG_PRTY_MASK_H_1_MEM034_I_MEM_PRTY_K2_SHIFT                                         10
53701     #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_A0                                            (0x1<<21) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
53702     #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_A0_SHIFT                                      21
53703     #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
53704     #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_BB_B0_SHIFT                                      11
53705     #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
53706     #define BMB_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_K2_SHIFT                                         11
53707     #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_A0                                            (0x1<<22) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
53708     #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_A0_SHIFT                                      22
53709     #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
53710     #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_BB_B0_SHIFT                                      12
53711     #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
53712     #define BMB_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_K2_SHIFT                                         12
53713     #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_A0                                            (0x1<<23) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
53714     #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_A0_SHIFT                                      23
53715     #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
53716     #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_BB_B0_SHIFT                                      13
53717     #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
53718     #define BMB_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_K2_SHIFT                                         13
53719     #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
53720     #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_A0_SHIFT                                      24
53721     #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
53722     #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_BB_B0_SHIFT                                      14
53723     #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
53724     #define BMB_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_K2_SHIFT                                         14
53725     #define BMB_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
53726     #define BMB_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_SHIFT                                            7
53727     #define BMB_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
53728     #define BMB_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_SHIFT                                            8
53729     #define BMB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
53730     #define BMB_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_SHIFT                                            9
53731     #define BMB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
53732     #define BMB_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_SHIFT                                            10
53733     #define BMB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
53734     #define BMB_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_SHIFT                                            11
53735     #define BMB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
53736     #define BMB_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_SHIFT                                            12
53737     #define BMB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
53738     #define BMB_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_SHIFT                                            13
53739     #define BMB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
53740     #define BMB_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_SHIFT                                            14
53741     #define BMB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
53742     #define BMB_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_SHIFT                                            15
53743     #define BMB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: BMB_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
53744     #define BMB_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_SHIFT                                            16
53745 #define BMB_REG_MEM_ECC_EVENTS                                                                       0x54046cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
53746 #define BMB_REG_MEM059_I_MEM_DFT_K2                                                                  0x540474UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.i_dbgsyn_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53747 #define BMB_REG_MEM060_I_MEM_DFT_K2                                                                  0x540478UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.i_pkt_avail_sync_fifo_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53748 #define BMB_REG_MEM001_I_MEM_DFT_K2                                                                  0x54047cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[0].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53749 #define BMB_REG_MEM008_I_MEM_DFT_K2                                                                  0x540480UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[1].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53750 #define BMB_REG_MEM009_I_MEM_DFT_K2                                                                  0x540484UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[2].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53751 #define BMB_REG_MEM010_I_MEM_DFT_K2                                                                  0x540488UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[3].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53752 #define BMB_REG_MEM011_I_MEM_DFT_K2                                                                  0x54048cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[4].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53753 #define BMB_REG_MEM012_I_MEM_DFT_K2                                                                  0x540490UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[5].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53754 #define BMB_REG_MEM013_I_MEM_DFT_K2                                                                  0x540494UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[6].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53755 #define BMB_REG_MEM014_I_MEM_DFT_K2                                                                  0x540498UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[7].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53756 #define BMB_REG_MEM015_I_MEM_DFT_K2                                                                  0x54049cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[8].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53757 #define BMB_REG_MEM016_I_MEM_DFT_K2                                                                  0x5404a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[9].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53758 #define BMB_REG_MEM002_I_MEM_DFT_K2                                                                  0x5404a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[10].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53759 #define BMB_REG_MEM003_I_MEM_DFT_K2                                                                  0x5404a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[11].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53760 #define BMB_REG_MEM004_I_MEM_DFT_K2                                                                  0x5404acUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[12].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53761 #define BMB_REG_MEM005_I_MEM_DFT_K2                                                                  0x5404b0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[13].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53762 #define BMB_REG_MEM006_I_MEM_DFT_K2                                                                  0x5404b4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[14].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53763 #define BMB_REG_MEM007_I_MEM_DFT_K2                                                                  0x5404b8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.BB_BANK_GEN_FOR[15].i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
53764 #define BMB_REG_MEM017_I_MEM_DFT_K2                                                                  0x5404bcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.LL_BANK_GEN_FOR[0].i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53765 #define BMB_REG_MEM018_I_MEM_DFT_K2                                                                  0x5404c0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.LL_BANK_GEN_FOR[1].i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53766 #define BMB_REG_MEM019_I_MEM_DFT_K2                                                                  0x5404c4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.LL_BANK_GEN_FOR[2].i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53767 #define BMB_REG_MEM020_I_MEM_DFT_K2                                                                  0x5404c8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.LL_BANK_GEN_FOR[3].i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53768 #define BMB_REG_MEM037_I_MEM_DFT_K2                                                                  0x5404ccUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[0].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53769 #define BMB_REG_MEM038_I_MEM_DFT_K2                                                                  0x5404d0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[1].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53770 #define BMB_REG_MEM039_I_MEM_DFT_K2                                                                  0x5404d4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[2].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53771 #define BMB_REG_MEM040_I_MEM_DFT_K2                                                                  0x5404d8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[3].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53772 #define BMB_REG_MEM041_I_MEM_DFT_K2                                                                  0x5404dcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[4].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53773 #define BMB_REG_MEM042_I_MEM_DFT_K2                                                                  0x5404e0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[5].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53774 #define BMB_REG_MEM043_I_MEM_DFT_K2                                                                  0x5404e4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[6].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53775 #define BMB_REG_MEM044_I_MEM_DFT_K2                                                                  0x5404e8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[7].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53776 #define BMB_REG_MEM045_I_MEM_DFT_K2                                                                  0x5404ecUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[8].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53777 #define BMB_REG_MEM046_I_MEM_DFT_K2                                                                  0x5404f0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_INP_FIFO_GEN_FOR[9].i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53778 #define BMB_REG_MEM047_I_MEM_DFT_K2                                                                  0x5404f4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[0].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53779 #define BMB_REG_MEM048_I_MEM_DFT_K2                                                                  0x5404f8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[1].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53780 #define BMB_REG_MEM049_I_MEM_DFT_K2                                                                  0x5404fcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[2].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53781 #define BMB_REG_MEM050_I_MEM_DFT_K2                                                                  0x540500UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[3].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53782 #define BMB_REG_MEM051_I_MEM_DFT_K2                                                                  0x540504UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[4].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53783 #define BMB_REG_MEM052_I_MEM_DFT_K2                                                                  0x540508UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[5].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53784 #define BMB_REG_MEM053_I_MEM_DFT_K2                                                                  0x54050cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[6].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53785 #define BMB_REG_MEM054_I_MEM_DFT_K2                                                                  0x540510UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[7].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53786 #define BMB_REG_MEM055_I_MEM_DFT_K2                                                                  0x540514UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[8].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53787 #define BMB_REG_MEM056_I_MEM_DFT_K2                                                                  0x540518UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SOP_FIFO_GEN_FOR[9].i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53788 #define BMB_REG_MEM023_I_MEM_DFT_K2                                                                  0x54051cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[0].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53789 #define BMB_REG_MEM024_I_MEM_DFT_K2                                                                  0x540520UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[1].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53790 #define BMB_REG_MEM025_I_MEM_DFT_K2                                                                  0x540524UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[2].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53791 #define BMB_REG_MEM026_I_MEM_DFT_K2                                                                  0x540528UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[3].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53792 #define BMB_REG_MEM027_I_MEM_DFT_K2                                                                  0x54052cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[4].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53793 #define BMB_REG_MEM028_I_MEM_DFT_K2                                                                  0x540530UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[5].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53794 #define BMB_REG_MEM029_I_MEM_DFT_K2                                                                  0x540534UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[6].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53795 #define BMB_REG_MEM030_I_MEM_DFT_K2                                                                  0x540538UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[7].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53796 #define BMB_REG_MEM031_I_MEM_DFT_K2                                                                  0x54053cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[8].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53797 #define BMB_REG_MEM032_I_MEM_DFT_K2                                                                  0x540540UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.RC_RSP_FIFO_GEN_FOR[9].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
53798 #define BMB_REG_MEM057_I_MEM_DFT_K2                                                                  0x540544UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SYNC_FIFO_GEN_FOR[8].WC_SYNC_FIFO_GEN_IF.i_wc_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53799 #define BMB_REG_MEM058_I_MEM_DFT_K2                                                                  0x540548UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.WC_SYNC_FIFO_GEN_FOR[9].WC_SYNC_FIFO_GEN_IF.i_wc_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53800 #define BMB_REG_MEM033_I_MEM_DFT_K2                                                                  0x54054cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.SOP_RC_INP_SYNC_FIFO_GEN_FOR[8].SOP_RC_INP_SYNC_FIFO_GEN_IF.i_sop_rc_inp_sync_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53801 #define BMB_REG_MEM034_I_MEM_DFT_K2                                                                  0x540550UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.SOP_RC_INP_SYNC_FIFO_GEN_FOR[9].SOP_RC_INP_SYNC_FIFO_GEN_IF.i_sop_rc_inp_sync_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53802 #define BMB_REG_MEM035_I_MEM_DFT_K2                                                                  0x540554UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.SOP_RC_OUT_SYNC_FIFO_GEN_FOR[8].SOP_RC_OUT_SYNC_FIFO_GEN_IF.i_ra_sop_rc_out_sync_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53803 #define BMB_REG_MEM036_I_MEM_DFT_K2                                                                  0x540558UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.SOP_RC_OUT_SYNC_FIFO_GEN_FOR[9].SOP_RC_OUT_SYNC_FIFO_GEN_IF.i_ra_sop_rc_out_sync_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53804 #define BMB_REG_MEM021_I_MEM_DFT_K2                                                                  0x54055cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.PKT_RC_OUT_SYNC_FIFO_GEN_FOR[8].PKT_RC_OUT_SYNC_FIFO_GEN_IF.i_pkt_rc_out_sync_fifo_data_256b_with_sop.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53805 #define BMB_REG_MEM022_I_MEM_DFT_K2                                                                  0x540560UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance bmb.PKT_RC_OUT_SYNC_FIFO_GEN_FOR[9].PKT_RC_OUT_SYNC_FIFO_GEN_IF.i_pkt_rc_out_sync_fifo_data_256b_with_sop.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
53806 #define BMB_REG_BIG_RAM_ADDRESS                                                                      0x540800UL //Access:RW   DataWidth:0xa   Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
53807 #define BMB_REG_HEADER_SIZE                                                                          0x540804UL //Access:RW   DataWidth:0xa   Number of valid bytes in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet available indication. (reset value of 17 suits to 282 bytes of header)::s/HDR_SIZE_RST/17/g in Reset Value.  Chips: BB_A0 BB_B0 K2
53808 #define BMB_REG_FREE_LIST_HEAD                                                                       0x540810UL //Access:RW   DataWidth:0xb   Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
53809 #define BMB_REG_FREE_LIST_HEAD_SIZE                                                                  4
53810 #define BMB_REG_FREE_LIST_TAIL                                                                       0x540820UL //Access:RW   DataWidth:0xb   Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
53811 #define BMB_REG_FREE_LIST_TAIL_SIZE                                                                  4
53812 #define BMB_REG_FREE_LIST_SIZE                                                                       0x540830UL //Access:RW   DataWidth:0xb   Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
53813 #define BMB_REG_FREE_LIST_SIZE_SIZE                                                                  4
53814 #define BMB_REG_MAX_RELEASES                                                                         0x540840UL //Access:RW   DataWidth:0x2   Number of packet copies that should be released before whole packet is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in Required::s/MAX_RLS_REQ/required/g in Software init.  Chips: BB_A0 BB_B0 K2
53815 #define BMB_REG_STOP_ON_LEN_ERR                                                                      0x540844UL //Access:RW   DataWidth:0xa   There is bit for each PACKET read client. When bit is set then read client will not execute more requests till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
53816 #define BMB_REG_SHARED_HR_AREA                                                                       0x540848UL //Access:RW   DataWidth:0xb   The total number available blocks for each MAC port that includes shared and headroom areas. This register should be equal to total_mac_size - SUM(tc_guarantied) Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53817 #define BMB_REG_TOTAL_MAC_SIZE                                                                       0x54084cUL //Access:RW   DataWidth:0xb   The total number available blocks for each MAC port that includes guaranteed and shared and headroom areas. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width::s/MAX_SHARE_GRP_WDTH/1/g in Address Width::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53818 #define BMB_REG_TC_GUARANTIED_0                                                                      0x540850UL //Access:RW   DataWidth:0xb   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53819 #define BMB_REG_TC_GUARANTIED_1                                                                      0x540854UL //Access:RW   DataWidth:0xb   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53820 #define BMB_REG_TC_GUARANTIED_2                                                                      0x540858UL //Access:RW   DataWidth:0xb   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53821 #define BMB_REG_TC_GUARANTIED_3                                                                      0x54085cUL //Access:RW   DataWidth:0xb   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53822 #define BMB_REG_TC_GUARANTIED_4                                                                      0x540860UL //Access:RW   DataWidth:0xb   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53823 #define BMB_REG_TC_GUARANTIED_5                                                                      0x540864UL //Access:RW   DataWidth:0xb   The number of blocks guaranteed to each TC in each MAC. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Data Width in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53824 #define BMB_REG_TC_GUARANTIED_HYST_0                                                                 0x540878UL //Access:RW   DataWidth:0xb   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53825 #define BMB_REG_TC_GUARANTIED_HYST_1                                                                 0x54087cUL //Access:RW   DataWidth:0xb   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53826 #define BMB_REG_TC_GUARANTIED_HYST_2                                                                 0x540880UL //Access:RW   DataWidth:0xb   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53827 #define BMB_REG_TC_GUARANTIED_HYST_3                                                                 0x540884UL //Access:RW   DataWidth:0xb   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53828 #define BMB_REG_TC_GUARANTIED_HYST_4                                                                 0x540888UL //Access:RW   DataWidth:0xb   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53829 #define BMB_REG_TC_GUARANTIED_HYST_5                                                                 0x54088cUL //Access:RW   DataWidth:0xb   The hysteresis on the guarantied area between XOFF and XON when the shared area is not used by the TC. There is configuration for each TC in each LB port. Reset value is right for 128B block size only. It should be twice smaller for 256B block size.::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53830 #define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_0                                                            0x5408a0UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53831 #define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_1                                                            0x5408a4UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53832 #define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_2                                                            0x5408a8UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53833 #define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_3                                                            0x5408acUL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53834 #define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_4                                                            0x5408b0UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53835 #define BMB_REG_TC_PAUSE_XOFF_THRESHOLD_5                                                            0x5408b4UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas below which PAUSE is asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53836 #define BMB_REG_TC_PAUSE_XON_THRESHOLD_0                                                             0x5408c8UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53837 #define BMB_REG_TC_PAUSE_XON_THRESHOLD_1                                                             0x5408ccUL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53838 #define BMB_REG_TC_PAUSE_XON_THRESHOLD_2                                                             0x5408d0UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53839 #define BMB_REG_TC_PAUSE_XON_THRESHOLD_3                                                             0x5408d4UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53840 #define BMB_REG_TC_PAUSE_XON_THRESHOLD_4                                                             0x5408d8UL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53841 #define BMB_REG_TC_PAUSE_XON_THRESHOLD_5                                                             0x5408dcUL //Access:RW   DataWidth:0xb   If the area guaranteed for TC of each LB write client is full - the number of free blocks in the shared and headroom areas above which PAUSE is de-asserted for the TC. This is actually the shared size that can be used by this TC.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53842 #define BMB_REG_TC_FULL_XOFF_THRESHOLD_0                                                             0x5408f0UL //Access:RW   DataWidth:0xb   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53843 #define BMB_REG_TC_FULL_XOFF_THRESHOLD_1                                                             0x5408f4UL //Access:RW   DataWidth:0xb   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53844 #define BMB_REG_TC_FULL_XOFF_THRESHOLD_2                                                             0x5408f8UL //Access:RW   DataWidth:0xb   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53845 #define BMB_REG_TC_FULL_XOFF_THRESHOLD_3                                                             0x5408fcUL //Access:RW   DataWidth:0xb   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53846 #define BMB_REG_TC_FULL_XOFF_THRESHOLD_4                                                             0x540900UL //Access:RW   DataWidth:0xb   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53847 #define BMB_REG_TC_FULL_XOFF_THRESHOLD_5                                                             0x540904UL //Access:RW   DataWidth:0xb   If the area guaranteed for that TC is full - the number of free blocks in the shared and headroom areas below which FULL is asserted for the TC. This is configuration for LB ports. Minimal value is 33 for dual engine device and 25 for single engine device. Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53848 #define BMB_REG_TC_FULL_XON_THRESHOLD_0                                                              0x540918UL //Access:RW   DataWidth:0xb   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53849 #define BMB_REG_TC_FULL_XON_THRESHOLD_1                                                              0x54091cUL //Access:RW   DataWidth:0xb   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53850 #define BMB_REG_TC_FULL_XON_THRESHOLD_2                                                              0x540920UL //Access:RW   DataWidth:0xb   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53851 #define BMB_REG_TC_FULL_XON_THRESHOLD_3                                                              0x540924UL //Access:RW   DataWidth:0xb   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53852 #define BMB_REG_TC_FULL_XON_THRESHOLD_4                                                              0x540928UL //Access:RW   DataWidth:0xb   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53853 #define BMB_REG_TC_FULL_XON_THRESHOLD_5                                                              0x54092cUL //Access:RW   DataWidth:0xb   The number of free shared and headroom blocks used by TC above which FULL is de-asserted for this TC. This is actually the headroom size for this TC. If the TC is lossy it will still have its headroom; but it will be a small value used just for the FULL round-trip and flashing input buffers. This is configuration for LB ports.Reset value is right for 128B block size only. It should be twice smaller for 256B block size. ::s/BLK_WDTH/13/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53854 #define BMB_REG_NO_DEAD_CYCLES_EN                                                                    0x540940UL //Access:RW   DataWidth:0xa   There is bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will be read without dead cycles.TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
53855 #define BMB_REG_RC_PKT_PRIORITY                                                                      0x540944UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53856     #define BMB_REG_RC_PKT_PRIORITY_RC0_PRI                                                          (0x3<<0) // This is priority for rc0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
53857     #define BMB_REG_RC_PKT_PRIORITY_RC0_PRI_SHIFT                                                    0
53858     #define BMB_REG_RC_PKT_PRIORITY_RC1_PRI                                                          (0x3<<2) // This is priority for rc1  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
53859     #define BMB_REG_RC_PKT_PRIORITY_RC1_PRI_SHIFT                                                    2
53860     #define BMB_REG_RC_PKT_PRIORITY_RC2_PRI                                                          (0x3<<4) // This is priority for rc2  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
53861     #define BMB_REG_RC_PKT_PRIORITY_RC2_PRI_SHIFT                                                    4
53862     #define BMB_REG_RC_PKT_PRIORITY_RC3_PRI                                                          (0x3<<6) // This is priority for rc3  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
53863     #define BMB_REG_RC_PKT_PRIORITY_RC3_PRI_SHIFT                                                    6
53864     #define BMB_REG_RC_PKT_PRIORITY_RC4_PRI                                                          (0x3<<8) // This is priority for rc0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
53865     #define BMB_REG_RC_PKT_PRIORITY_RC4_PRI_SHIFT                                                    8
53866     #define BMB_REG_RC_PKT_PRIORITY_RC5_PRI                                                          (0x3<<10) // This is priority for rc5  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
53867     #define BMB_REG_RC_PKT_PRIORITY_RC5_PRI_SHIFT                                                    10
53868     #define BMB_REG_RC_PKT_PRIORITY_RC6_PRI                                                          (0x3<<12) // This is priority for parser  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
53869     #define BMB_REG_RC_PKT_PRIORITY_RC6_PRI_SHIFT                                                    12
53870     #define BMB_REG_RC_PKT_PRIORITY_RC7_PRI                                                          (0x3<<14) // This is priority for parser  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
53871     #define BMB_REG_RC_PKT_PRIORITY_RC7_PRI_SHIFT                                                    14
53872     #define BMB_REG_RC_PKT_PRIORITY_RC8_PRI                                                          (0x3<<16) // This is priority for read client 8 that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest
53873     #define BMB_REG_RC_PKT_PRIORITY_RC8_PRI_SHIFT                                                    16
53874     #define BMB_REG_RC_PKT_PRIORITY_RC9_PRI                                                          (0x3<<18) // This is priority for read client 9 that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest
53875     #define BMB_REG_RC_PKT_PRIORITY_RC9_PRI_SHIFT                                                    18
53876 #define BMB_REG_WC_NO_DEAD_CYCLES_EN                                                                 0x540948UL //Access:RW   DataWidth:0xa   There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet will be written without intra packet dead cycles .TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset  Chips: K2
53877 #define BMB_REG_WC_HIGHEST_PRI_EN                                                                    0x54094cUL //Access:RW   DataWidth:0xa   There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest priority mechanism is enabled for the corresponding client. TBD ::s/NO_DEAD_CYCLE_RST/1/g in Reset  Chips: K2
53878 #define BMB_REG_RC_SOP_PRIORITY                                                                      0x540980UL //Access:RW   DataWidth:0x2   This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in Reset Value.  Chips: BB_A0 BB_B0 K2
53879 #define BMB_REG_WC_PRIORITY                                                                          0x540984UL //Access:RW   DataWidth:0x2   This is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in Reset Value.  Chips: BB_A0 BB_B0 K2
53880 #define BMB_REG_PRI_OF_MULT_CLIENTS                                                                  0x540988UL //Access:RW   DataWidth:0x2   This is priority of multiple clients with identical priority for link list arbiter. Selection from them will be done with round robin. Only one group with multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g in Reset Value.  Chips: BB_A0 BB_B0 K2
53881 #define BMB_REG_INP_FIFO_ALM_FULL                                                                    0x54098cUL //Access:RW   DataWidth:0x5   Number of entries inside input FIFO of each write client upper which full outputs to this write client interface.  Chips: BB_A0 BB_B0 K2
53882 #define BMB_REG_WC_SYNC_FIFO_ALM_FULL                                                                0x540990UL //Access:RW   DataWidth:0x5   Number of entries inside sync FIFO of each write client.  Chips: BB_A0 BB_B0 K2
53883 #define BMB_REG_PKT_RC_OUT_SYNC_FIFO_ALM_FULL                                                        0x540994UL //Access:RW   DataWidth:0x5   Number of entries inside output sync FIFO of each read client.  Chips: BB_A0 BB_B0 K2
53884 #define BMB_REG_PKT_AVAIL_SYNC_FIFO_ALM_FULL                                                         0x540998UL //Access:RW   DataWidth:0x4   Number of entries inside packet available sync FIFO.  Chips: BB_A0 BB_B0 K2
53885 #define BMB_REG_RLS_SYNC_FIFO_ALM_FULL                                                               0x54099cUL //Access:RW   DataWidth:0x4   Number of entries inside packet available sync FIFO.  Chips: BB_A0 BB_B0 K2
53886 #define BMB_REG_INP_FIFO_HIGH_THRESHOLD                                                              0x5409a0UL //Access:RW   DataWidth:0x5   Number of entries inside input FIFO of each write client upper which all arbiters selects this client with high priority.  Chips: BB_A0 BB_B0 K2
53887 #define BMB_REG_DSCR_FIFO_ALM_FULL                                                                   0x5409a4UL //Access:RW   DataWidth:0x5   Number of entries inside descriptors FIFO of each write client upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.  Chips: BB_A0 BB_B0 K2
53888 #define BMB_REG_QUEUE_FIFO_ALM_FULL                                                                  0x5409a8UL //Access:RW   DataWidth:0x5   Number of entries inside queue FIFO of each write client upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.  Chips: BB_A0 BB_B0 K2
53889 #define BMB_REG_DSCR_FIFO_HIGH_THRESHOLD                                                             0x5409acUL //Access:RW   DataWidth:0x5   Number of entries inside descriptors FIFO of each write client upper which all arbiters selects this client with high priority.  Chips: BB_A0 BB_B0 K2
53890 #define BMB_REG_PM_TC_LATENCY_SENSITIVE_0                                                            0x5409b0UL //Access:RW   DataWidth:0x6   Per TC enable for output BRB_above_threshold_mac_n to power management block when number of packets of appropriate TC is bigger than 1::s/COS_NUM/9/g in Data Width::s/LATENCY_RST/511/g in Reset Value::s/SHARE_GRP_CNT/2/g in Array Size::/EMPTY_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
53891 #define BMB_REG_PM_COS_THRESHOLD_0                                                                   0x540a30UL //Access:RW   DataWidth:0xb   Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.  Chips: BB_A0 BB_B0 K2
53892 #define BMB_REG_PM_COS_THRESHOLD_1                                                                   0x540a34UL //Access:RW   DataWidth:0xb   Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.  Chips: BB_A0 BB_B0 K2
53893 #define BMB_REG_PM_COS_THRESHOLD_2                                                                   0x540a38UL //Access:RW   DataWidth:0xb   Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.  Chips: BB_A0 BB_B0 K2
53894 #define BMB_REG_PM_COS_THRESHOLD_3                                                                   0x540a3cUL //Access:RW   DataWidth:0xb   Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.  Chips: BB_A0 BB_B0 K2
53895 #define BMB_REG_PM_COS_THRESHOLD_4                                                                   0x540a40UL //Access:RW   DataWidth:0xb   Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.  Chips: BB_A0 BB_B0 K2
53896 #define BMB_REG_PM_COS_THRESHOLD_5                                                                   0x540a44UL //Access:RW   DataWidth:0xb   Per COS threshold. BRTB indicates full to CPMU if one of the COSes has more blocks than its threshold.  Chips: BB_A0 BB_B0 K2
53897 #define BMB_REG_DBGSYN_ALMOST_FULL_THR                                                               0x540a70UL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: BB_A0 BB_B0 K2
53898 #define BMB_REG_DBGSYN_STATUS                                                                        0x540a74UL //Access:R    DataWidth:0x5   Fill level of dbgmux fifo.  Chips: BB_A0 BB_B0 K2
53899 #define BMB_REG_ECO_RESERVED                                                                         0x540a78UL //Access:RW   DataWidth:0x20  This is unused register for future ECOs.  Chips: BB_A0 BB_B0 K2
53900 #define BMB_REG_DBG_SELECT                                                                           0x540a7cUL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
53901 #define BMB_REG_DBG_DWORD_ENABLE                                                                     0x540a80UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
53902 #define BMB_REG_DBG_SHIFT                                                                            0x540a84UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
53903 #define BMB_REG_DBG_FORCE_VALID                                                                      0x540a88UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
53904 #define BMB_REG_DBG_FORCE_FRAME                                                                      0x540a8cUL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
53905 #define BMB_REG_DBG_OUT_DATA                                                                         0x540aa0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
53906 #define BMB_REG_DBG_OUT_DATA_SIZE                                                                    8
53907 #define BMB_REG_DBG_OUT_VALID                                                                        0x540ac0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
53908 #define BMB_REG_DBG_OUT_FRAME                                                                        0x540ac4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
53909 #define BMB_REG_INP_IF_ENABLE                                                                        0x540ac8UL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53910     #define BMB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN                                                   (0x3ff<<0) // There is bit per each read client interface: TBD. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/PKT_RC_NUM_MINUS_SOP_EN/4/g in Data Width::s/RC_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments.
53911     #define BMB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN_SHIFT                                             0
53912     #define BMB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN                                                   (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted.  All bits of this register should be set after init procedure.
53913     #define BMB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN_SHIFT                                             10
53914     #define BMB_REG_INP_IF_ENABLE_WC_INP_IF_EN                                                       (0x3ff<<11) // There is bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/WC_IF_RST/15/g in Reset Value::s/WC_EN/B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1./g in Comments::s/WC_NUM/4/g in Data Width.
53915     #define BMB_REG_INP_IF_ENABLE_WC_INP_IF_EN_SHIFT                                                 11
53916 #define BMB_REG_OUT_IF_ENABLE                                                                        0x540accUL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
53917     #define BMB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN                                                   (0x3ff<<0) // There is bit per each read client interface: TBD. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure. ::s/RC_PKT_OUT_IF_RST/31/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
53918     #define BMB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN_SHIFT                                             0
53919     #define BMB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN                                                   (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted.  All bits of this register should be set after init procedure.
53920     #define BMB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN_SHIFT                                             10
53921     #define BMB_REG_OUT_IF_ENABLE_PAUSE_OUT_IF_EN                                                    (0xf<<11) // There is bit for all pause interfaces per each MAC port. When bit is set then pause interface is enabled. When bit is reset then any pause will never be set. This bit should be set after init procedure. ::s/SHARE_GRP_CNT/2/g in Data Width::s/SHARE_GRP_INIT/3/g in Reset Value::/PAUSE_EN/d in Existance.
53922     #define BMB_REG_OUT_IF_ENABLE_PAUSE_OUT_IF_EN_SHIFT                                              11
53923     #define BMB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN                                            (0x1<<15) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set.  This bit should be set after init procedure.
53924     #define BMB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN_SHIFT                                      15
53925     #define BMB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN                                                       (0x1<<16) // There is bit for power management interfaces. When bit is set then  power management interface is enabled. When bit is reset then  power management interface will never be set.  This bit should be set after init procedure. ::/EMPTY_EN/d in Existance.
53926     #define BMB_REG_OUT_IF_ENABLE_PM_OUT_IF_EN_SHIFT                                                 16
53927 #define BMB_REG_WC_EMPTY_0                                                                           0x540ad0UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53928 #define BMB_REG_WC_EMPTY_1                                                                           0x540ad4UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53929 #define BMB_REG_WC_EMPTY_2                                                                           0x540ad8UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53930 #define BMB_REG_WC_EMPTY_3                                                                           0x540adcUL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53931 #define BMB_REG_WC_EMPTY_4                                                                           0x540ae0UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53932 #define BMB_REG_WC_EMPTY_5                                                                           0x540ae4UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53933 #define BMB_REG_WC_EMPTY_6                                                                           0x540ae8UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53934 #define BMB_REG_WC_EMPTY_7                                                                           0x540aecUL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53935 #define BMB_REG_WC_EMPTY_8                                                                           0x540af0UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53936 #define BMB_REG_WC_EMPTY_9                                                                           0x540af4UL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. TBD: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
53937 #define BMB_REG_WC_FULL_0                                                                            0x540b10UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53938 #define BMB_REG_WC_FULL_1                                                                            0x540b14UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53939 #define BMB_REG_WC_FULL_2                                                                            0x540b18UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53940 #define BMB_REG_WC_FULL_3                                                                            0x540b1cUL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53941 #define BMB_REG_WC_FULL_4                                                                            0x540b20UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53942 #define BMB_REG_WC_FULL_5                                                                            0x540b24UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53943 #define BMB_REG_WC_FULL_6                                                                            0x540b28UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53944 #define BMB_REG_WC_FULL_7                                                                            0x540b2cUL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53945 #define BMB_REG_WC_FULL_8                                                                            0x540b30UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53946 #define BMB_REG_WC_FULL_9                                                                            0x540b34UL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. TBD: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
53947 #define BMB_REG_WC_BANDWIDTH_IF_FULL                                                                 0x540b50UL //Access:R    DataWidth:0xa   Debug register. Full status each write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.  Chips: BB_A0 BB_B0 K2
53948 #define BMB_REG_RC_PKT_IF_FULL                                                                       0x540b54UL //Access:R    DataWidth:0xa   Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
53949 #define BMB_REG_RC_PKT_EMPTY_0                                                                       0x540b58UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53950 #define BMB_REG_RC_PKT_EMPTY_1                                                                       0x540b5cUL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53951 #define BMB_REG_RC_PKT_EMPTY_2                                                                       0x540b60UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53952 #define BMB_REG_RC_PKT_EMPTY_3                                                                       0x540b64UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53953 #define BMB_REG_RC_PKT_EMPTY_4                                                                       0x540b68UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53954 #define BMB_REG_RC_PKT_EMPTY_5                                                                       0x540b6cUL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53955 #define BMB_REG_RC_PKT_EMPTY_6                                                                       0x540b70UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53956 #define BMB_REG_RC_PKT_EMPTY_7                                                                       0x540b74UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53957 #define BMB_REG_RC_PKT_EMPTY_8                                                                       0x540b78UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53958 #define BMB_REG_RC_PKT_EMPTY_9                                                                       0x540b7cUL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53959 #define BMB_REG_RC_PKT_FULL_0                                                                        0x540b94UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53960 #define BMB_REG_RC_PKT_FULL_1                                                                        0x540b98UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53961 #define BMB_REG_RC_PKT_FULL_2                                                                        0x540b9cUL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53962 #define BMB_REG_RC_PKT_FULL_3                                                                        0x540ba0UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53963 #define BMB_REG_RC_PKT_FULL_4                                                                        0x540ba4UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53964 #define BMB_REG_RC_PKT_FULL_5                                                                        0x540ba8UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53965 #define BMB_REG_RC_PKT_FULL_6                                                                        0x540bacUL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53966 #define BMB_REG_RC_PKT_FULL_7                                                                        0x540bb0UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53967 #define BMB_REG_RC_PKT_FULL_8                                                                        0x540bb4UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53968 #define BMB_REG_RC_PKT_FULL_9                                                                        0x540bb8UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53969 #define BMB_REG_RC_PKT_STATUS_0                                                                      0x540bd0UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53970 #define BMB_REG_RC_PKT_STATUS_1                                                                      0x540bd4UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53971 #define BMB_REG_RC_PKT_STATUS_2                                                                      0x540bd8UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53972 #define BMB_REG_RC_PKT_STATUS_3                                                                      0x540bdcUL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53973 #define BMB_REG_RC_PKT_STATUS_4                                                                      0x540be0UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53974 #define BMB_REG_RC_PKT_STATUS_5                                                                      0x540be4UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53975 #define BMB_REG_RC_PKT_STATUS_6                                                                      0x540be8UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53976 #define BMB_REG_RC_PKT_STATUS_7                                                                      0x540becUL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53977 #define BMB_REG_RC_PKT_STATUS_8                                                                      0x540bf0UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53978 #define BMB_REG_RC_PKT_STATUS_9                                                                      0x540bf4UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
53979 #define BMB_REG_RC_SOP_EMPTY                                                                         0x540c0cUL //Access:R    DataWidth:0x4   Debug register. Empty status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
53980 #define BMB_REG_RC_SOP_FULL                                                                          0x540c10UL //Access:R    DataWidth:0x4   Debug register. Full status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
53981 #define BMB_REG_RC_SOP_STATUS                                                                        0x540c14UL //Access:R    DataWidth:0x10  Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo;  B7:4-dscr_fifo;  B3:0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
53982 #define BMB_REG_LL_ARB_EMPTY                                                                         0x540c18UL //Access:R    DataWidth:0x2   Debug register. Empty status of link list arbiter: {rls_fifo; prefetch_fifo}.  Chips: BB_A0 BB_B0 K2
53983 #define BMB_REG_LL_ARB_FULL                                                                          0x540c1cUL //Access:R    DataWidth:0x2   Debug register. Full status of link list arbiter: {rls_fifo; prefetch_fifo}.  Chips: BB_A0 BB_B0 K2
53984 #define BMB_REG_LL_ARB_STATUS                                                                        0x540c20UL //Access:R    DataWidth:0x8   Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo[3:0]}.  Chips: BB_A0 BB_B0 K2
53985 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_0                                                             0x540c24UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53986 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_1                                                             0x540c28UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53987 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_2                                                             0x540c2cUL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53988 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_3                                                             0x540c30UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53989 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_4                                                             0x540c34UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53990 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_5                                                             0x540c38UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53991 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_6                                                             0x540c3cUL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53992 #define BMB_REG_RC_SOP_PEND_FIFO_EMPTY_7                                                             0x540c40UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53993 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_0                                                              0x540c44UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53994 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_1                                                              0x540c48UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53995 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_2                                                              0x540c4cUL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53996 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_3                                                              0x540c50UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53997 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_4                                                              0x540c54UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53998 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_5                                                              0x540c58UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
53999 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_6                                                              0x540c5cUL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54000 #define BMB_REG_RC_SOP_PEND_FIFO_FULL_7                                                              0x540c60UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54001 #define BMB_REG_RC_SOP_PEND_FIFO_CNT_0                                                               0x540c64UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54002 #define BMB_REG_RC_SOP_PEND_FIFO_CNT_1                                                               0x540c68UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54003 #define BMB_REG_RC_SOP_PEND_FIFO_CNT_2                                                               0x540c6cUL //Access:R    DataWidth:0x2   Debug register. This is status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54004 #define BMB_REG_RC_SOP_PEND_FIFO_CNT_3                                                               0x540c70UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54005 #define BMB_REG_RC_SOP_PEND_FIFO_CNT_4                                                               0x540c74UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54006 #define BMB_REG_RC_SOP_PEND_FIFO_CNT_5                                                               0x540c78UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54007 #define BMB_REG_RC_SOP_PEND_FIFO_CNT_6                                                               0x540c7cUL //Access:R    DataWidth:0x2   Debug register. This is status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54008 #define BMB_REG_RC_SOP_PEND_FIFO_CNT_7                                                               0x540c80UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54009 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_0                                                            0x540c84UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54010 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_1                                                            0x540c88UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54011 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_2                                                            0x540c8cUL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54012 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_3                                                            0x540c90UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54013 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_4                                                            0x540c94UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54014 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_5                                                            0x540c98UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54015 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_6                                                            0x540c9cUL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54016 #define BMB_REG_RC_DSCR_PEND_FIFO_EMPTY_7                                                            0x540ca0UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54017 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_0                                                             0x540ca4UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54018 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_1                                                             0x540ca8UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54019 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_2                                                             0x540cacUL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54020 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_3                                                             0x540cb0UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54021 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_4                                                             0x540cb4UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54022 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_5                                                             0x540cb8UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54023 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_6                                                             0x540cbcUL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54024 #define BMB_REG_RC_DSCR_PEND_FIFO_FULL_7                                                             0x540cc0UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54025 #define BMB_REG_RC_DSCR_PEND_FIFO_CNT_0                                                              0x540cc4UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54026 #define BMB_REG_RC_DSCR_PEND_FIFO_CNT_1                                                              0x540cc8UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54027 #define BMB_REG_RC_DSCR_PEND_FIFO_CNT_2                                                              0x540cccUL //Access:R    DataWidth:0x2   Debug register. This is status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54028 #define BMB_REG_RC_DSCR_PEND_FIFO_CNT_3                                                              0x540cd0UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54029 #define BMB_REG_RC_DSCR_PEND_FIFO_CNT_4                                                              0x540cd4UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54030 #define BMB_REG_RC_DSCR_PEND_FIFO_CNT_5                                                              0x540cd8UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54031 #define BMB_REG_RC_DSCR_PEND_FIFO_CNT_6                                                              0x540cdcUL //Access:R    DataWidth:0x2   Debug register. This is status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54032 #define BMB_REG_RC_DSCR_PEND_FIFO_CNT_7                                                              0x540ce0UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP DSCR pending FIFO for each client  Chips: BB_A0 BB_B0 K2
54033 #define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_8                                                     0x540ce4UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP SYNC INP FIFO for client 8  Chips: BB_A0 BB_B0 K2
54034 #define BMB_REG_RC_SOP_INP_SYNC_FIFO_POP_EMPTY_9                                                     0x540ce8UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP SYNC INP FIFO for client 9  Chips: BB_A0 BB_B0 K2
54035 #define BMB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS_8                                                   0x540cecUL //Access:R    DataWidth:0x2   Debug register. This is status of SOP SYNC INP FIFO for each client  Chips: BB_A0 BB_B0 K2
54036 #define BMB_REG_RC_SOP_INP_SYNC_FIFO_PUSH_STATUS_9                                                   0x540cf0UL //Access:R    DataWidth:0x2   Debug register. This is status of SOP SYNC INP FIFO for each client  Chips: BB_A0 BB_B0 K2
54037 #define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_8                                                     0x540cf4UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP SYNC out FIFO for client 8  Chips: BB_A0 BB_B0 K2
54038 #define BMB_REG_RC_SOP_OUT_SYNC_FIFO_POP_EMPTY_9                                                     0x540cf8UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP SYNC out FIFO for client 9  Chips: BB_A0 BB_B0 K2
54039 #define BMB_REG_RC_SOP_OUT_SYNC_FIFO_PUSH_STATUS_8                                                   0x540cfcUL //Access:R    DataWidth:0x2   Debug register. This is full status of SOP SYNC OUT FIFO for each client  Chips: BB_A0 BB_B0 K2
54040 #define BMB_REG_RC_SOP_OUT_SYNC_FIFO_PUSH_STATUS_9                                                   0x540d00UL //Access:R    DataWidth:0x2   Debug register. This is full status of SOP SYNC OUT FIFO for each client  Chips: BB_A0 BB_B0 K2
54041 #define BMB_REG_RC_GNT_PEND_FIFO_EMPTY                                                               0x540d04UL //Access:R    DataWidth:0x1   Debug register. This is empty status of SOP grant FIFO  Chips: BB_A0 BB_B0 K2
54042 #define BMB_REG_RC_GNT_PEND_FIFO_FULL                                                                0x540d08UL //Access:R    DataWidth:0x1   Debug register. This is full status of SOP grant FIFO  Chips: BB_A0 BB_B0 K2
54043 #define BMB_REG_RC_GNT_PEND_FIFO_CNT                                                                 0x540d0cUL //Access:R    DataWidth:0x5   Debug register. This is full status of SOP grant FIFO  Chips: BB_A0 BB_B0 K2
54044 #define BMB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_8                                                       0x540d10UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
54045 #define BMB_REG_RC_OUT_SYNC_FIFO_PUSH_STATUS_9                                                       0x540d14UL //Access:R    DataWidth:0x5   Debug register. This is full status of packet RC output SYNC FIFO  Chips: BB_A0 BB_B0 K2
54046 #define BMB_REG_WC_SYNC_FIFO_PUSH_STATUS_8                                                           0x540d4cUL //Access:R    DataWidth:0x6   Debug register. This is full status of WC SYNC FIFO  Chips: BB_A0 BB_B0 K2
54047 #define BMB_REG_WC_SYNC_FIFO_PUSH_STATUS_9                                                           0x540d50UL //Access:R    DataWidth:0x6   Debug register. This is full status of WC SYNC FIFO  Chips: BB_A0 BB_B0 K2
54048 #define BMB_REG_PKT_AVAIL_SYNC_FIFO_PUSH_STATUS                                                      0x540d88UL //Access:R    DataWidth:0x4   Debug register. This is full status of packet available SYNC FIFO  Chips: BB_A0 BB_B0 K2
54049 #define BMB_REG_RC_PKT_STATE                                                                         0x540d8cUL //Access:R    DataWidth:0x20  Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.  Chips: BB_A0 BB_B0 K2
54050 #define BMB_REG_RC_PKT_STATE_1                                                                       0x540d90UL //Access:R    DataWidth:0x8   Debug register. This is state machine for each read client 8 and 9.  Chips: BB_A0 BB_B0 K2
54051 #define BMB_REG_MAC_FREE_SHARED_HR_0                                                                 0x540d9cUL //Access:R    DataWidth:0xb   Debug register. The number of free blocks for each MAC port that includes shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/SHARED_HR_RST/2112/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54052 #define BMB_REG_TC_OCCUPANCY_0                                                                       0x540db4UL //Access:R    DataWidth:0xb   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54053 #define BMB_REG_TC_OCCUPANCY_1                                                                       0x540db8UL //Access:R    DataWidth:0xb   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54054 #define BMB_REG_TC_OCCUPANCY_2                                                                       0x540dbcUL //Access:R    DataWidth:0xb   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54055 #define BMB_REG_TC_OCCUPANCY_3                                                                       0x540dc0UL //Access:R    DataWidth:0xb   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54056 #define BMB_REG_TC_OCCUPANCY_4                                                                       0x540dc4UL //Access:R    DataWidth:0xb   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54057 #define BMB_REG_TC_OCCUPANCY_5                                                                       0x540dc8UL //Access:R    DataWidth:0xb   Debug register. The number of block occupied by each TC in each main port 0::s/COS_NUM/9/g in Array Size::s/BLK_WDTH/13/g in Data Width::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54058 #define BMB_REG_AVAILABLE_MAC_SIZE_0                                                                 0x540df4UL //Access:R    DataWidth:0xb   Debug register. The available number of blocks for each MAC port that includes guaranteed and shared and headroom areas.::s/BLK_WDTH/13/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::s/TOTAL_MAC_RST/2400/g in Reset Value::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54059 #define BMB_REG_TC_PAUSE_0                                                                           0x540e0cUL //Access:R    DataWidth:0x6   Debug register. Output pause signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54060 #define BMB_REG_TC_FULL_0                                                                            0x540e24UL //Access:R    DataWidth:0x6   Debug register. Output full signal by each TC in each main port::s/COS_NUM/9/g in Data Width::s/SHARE_GRP_CNT/2/g in Array Size::/PAUSE_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
54061 #define BMB_REG_BIG_RAM_DATA                                                                         0x540f00UL //Access:WB   DataWidth:0x80  Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.  Chips: BB_A0 BB_B0 K2
54062 #define BMB_REG_BIG_RAM_DATA_SIZE                                                                    64
54063 #define BMB_REG_RC_SOP_QUEUE_STATUS                                                                  0x541000UL //Access:R    DataWidth:0x20  Debug register. There is register for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset Value::s/QUEUE_ARRAY/36/g in memory size::s/SOP_STATUS_WDTH/6/g in Address Width.  Chips: BB_A0 BB_B0 K2
54064 #define BMB_REG_RC_SOP_QUEUE_STATUS_SIZE                                                             90
54065 #define BMB_REG_STOPPED_RD_REQ                                                                       0x541200UL //Access:WB_R DataWidth:0x3f  If there is length error of first block error then request from read client will be copied to this register for each erad packet client interface: TBD. Message spelling (MSB->LSB): rest_size_error[0]; len_error[0]; 1st_error[0]; middle_error[0]; rls_to_do[1:0]; start_block[12:0]; rd_req[0]; rls_req[0]; offset[9:0]; length[13:0]; opaque[15:0]  Chips: BB_A0 BB_B0 K2
54066 #define BMB_REG_STOPPED_RD_REQ_SIZE                                                                  20
54067 #define BMB_REG_STOPPED_RLS_REQ                                                                      0x541300UL //Access:WB_R DataWidth:0x4c  If there is release error then request from read client will be copied to this register for each read packet client interface: TBD. Message spelling (MSB->LSB): opaque[1:0]; rls_to_do[15:0]; queue_number[3:0]; packet_length[13:0]; rls_left[1:0]; start_block[12:0]  Chips: BB_A0 BB_B0 K2
54068 #define BMB_REG_STOPPED_RLS_REQ_SIZE                                                                 40
54069 #define BMB_REG_WC_STATUS_0                                                                          0x541400UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54070 #define BMB_REG_WC_STATUS_0_SIZE                                                                     4
54071 #define BMB_REG_WC_STATUS_1                                                                          0x541410UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54072 #define BMB_REG_WC_STATUS_1_SIZE                                                                     4
54073 #define BMB_REG_WC_STATUS_2                                                                          0x541420UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54074 #define BMB_REG_WC_STATUS_2_SIZE                                                                     4
54075 #define BMB_REG_WC_STATUS_3                                                                          0x541430UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54076 #define BMB_REG_WC_STATUS_3_SIZE                                                                     4
54077 #define BMB_REG_WC_STATUS_4                                                                          0x541440UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54078 #define BMB_REG_WC_STATUS_4_SIZE                                                                     4
54079 #define BMB_REG_WC_STATUS_5                                                                          0x541450UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54080 #define BMB_REG_WC_STATUS_5_SIZE                                                                     4
54081 #define BMB_REG_WC_STATUS_6                                                                          0x541460UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54082 #define BMB_REG_WC_STATUS_6_SIZE                                                                     4
54083 #define BMB_REG_WC_STATUS_7                                                                          0x541470UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54084 #define BMB_REG_WC_STATUS_7_SIZE                                                                     4
54085 #define BMB_REG_WC_STATUS_8                                                                          0x541480UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54086 #define BMB_REG_WC_STATUS_8_SIZE                                                                     4
54087 #define BMB_REG_WC_STATUS_9                                                                          0x541490UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. TBD: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
54088 #define BMB_REG_WC_STATUS_9_SIZE                                                                     4
54089 #define BMB_REG_LINK_LIST                                                                            0x542000UL //Access:RW   DataWidth:0xc   Link list dual port memory that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/g in Data Width::s/BLK_WDTH/13/g in Address Width.  Chips: BB_A0 BB_B0 K2
54090 #define BMB_REG_LINK_LIST_SIZE                                                                       1152
54091 #define PTU_REG_ATC_INIT_ARRAY                                                                       0x560000UL //Access:RW   DataWidth:0x1   Initiate the ATC array - reset all the valid bits.  Chips: BB_A0 BB_B0 K2
54092 #define PTU_REG_ATC_INIT_DONE                                                                        0x560004UL //Access:R    DataWidth:0x1   ATC initalization done.  Chips: BB_A0 BB_B0 K2
54093 #define PTU_REG_LOG_TRANSPEND_REUSE_MISS_TID                                                         0x560040UL //Access:RC   DataWidth:0x20  Logging register for reuse miss on transpend entry [31:0] - TID of the problematic request  Chips: BB_A0 BB_B0 K2
54094 #define PTU_REG_LOG_TRANSPEND_REUSE_MISS_PAGE_INDEX                                                  0x560044UL //Access:RC   DataWidth:0x1c  Logging register for reuse miss on transpend entry [27:0] - ATC page index of the problematic request  Chips: BB_A0 BB_B0 K2
54095 #define PTU_REG_LOG_TRANSPEND_REUSE_MISS_REUSE_CNT                                                   0x560048UL //Access:RC   DataWidth:0x18  Logging register for reuse miss on transpend entry [11:0] - Reuse count of the problematic lookuprequest [23:12] - Reuse count stored in the matched entry  Chips: BB_A0 BB_B0 K2
54096 #define PTU_REG_LOG_INV_HALT_TID                                                                     0x56004cUL //Access:RC   DataWidth:0x20  Logging register for the case of invalidation halt (lkpres of invalidated range) [31:0] - TID of the problematic request  Chips: BB_A0 BB_B0 K2
54097 #define PTU_REG_LOG_INV_HALT_PAGE_INDEX                                                              0x560050UL //Access:RC   DataWidth:0x1c  Logging register for the case of invalidation halt (lkpres of invalidated range) [27:0] - ATC page index of the problematic request  Chips: BB_A0 BB_B0 K2
54098 #define PTU_REG_LOG_INV_HALT_REUSE_CNT                                                               0x560054UL //Access:RC   DataWidth:0xc   Logging register for the case of invalidation halt (lkpres of invalidated range) [11:0] - Reuse count of the problematic lookuprequest  Chips: BB_A0 BB_B0 K2
54099 #define PTU_REG_VQID_CFG                                                                             0x560058UL //Access:RW   DataWidth:0x5   VQID of the PXP read requests issued by the PTU logic.  Chips: BB_A0 BB_B0 K2
54100 #define PTU_REG_TPH_CFG                                                                              0x56005cUL //Access:RW   DataWidth:0xc   TPH fileds of the PXP read requests issued by the PTU logic. [0:8] - ST index; [10:9] - ST hint; [11] - ST valid.  Chips: BB_A0 BB_B0 K2
54101 #define PTU_REG_RO_CFG                                                                               0x560060UL //Access:RW   DataWidth:0x1   Releaxed Ordering flag of the PXP read requests issued by the PTU.  Chips: BB_A0 BB_B0 K2
54102 #define PTU_REG_NS_CFG                                                                               0x560064UL //Access:RW   DataWidth:0x1   No Snoop flag of the PXP read requests issued by the PTU.  Chips: BB_A0 BB_B0 K2
54103 #define PTU_REG_ATC_FLG_CFG                                                                          0x560068UL //Access:RW   DataWidth:0x3   ATC flags of the PXP read requests issued by the PTU logic.  Chips: BB_A0 BB_B0 K2
54104 #define PTU_REG_PBL_PAGE_SIZE                                                                        0x56006cUL //Access:RW   DataWidth:0x5   Page size in the PBL table, needed for calculating the address of the translation read request.  Chips: BB_A0 BB_B0 K2
54105 #define PTU_REG_PXP_ERR_CTR                                                                          0x560070UL //Access:RC   DataWidth:0x10  Counter for the number of PTU read responses retunring with error flag set.  Chips: BB_A0 BB_B0 K2
54106 #define PTU_REG_INV_ERR_CTR                                                                          0x560074UL //Access:R    DataWidth:0x10  Counter for the number of PTU requests to addresses belongs to ongoing invalidations.  Chips: BB_A0 BB_B0 K2
54107 #define PTU_REG_INV_TID                                                                              0x560078UL //Access:RW   DataWidth:0x20  TID of the invalidated range - register per PF.  Chips: BB_A0 BB_B0 K2
54108 #define PTU_REG_INV_TID_MASK                                                                         0x56007cUL //Access:RW   DataWidth:0x20  Bit mask for the invalidated TID. Shows which of the TID bits should be compared in the invalidation flow.  Chips: BB_A0 BB_B0 K2
54109 #define PTU_REG_INV_TID_V                                                                            0x560080UL //Access:RW   DataWidth:0x1   Bit per PF.Indicates that the data in inv_tid and inv_tid_mask is valid and invalidation should take place. When invalidation operation is done, the corresponding bit in inv_tid_done is set  Chips: BB_A0 BB_B0 K2
54110 #define PTU_REG_INV_TID_DONE                                                                         0x560084UL //Access:RW   DataWidth:0x1   Bit per PF. Indicates that the marked invalidation is done - when read it is also being reset.  Chips: BB_A0 BB_B0 K2
54111 #define PTU_REG_INV_HALT_ON_ERR                                                                      0x560088UL //Access:RW   DataWidth:0x1   Bit per PF. If set, the block halts in case it gets PTU requests to an address belongs to a range which is currently invalidated; if reset such requests will be sent towards the PXP with the PBLBase and discard flag (in case of PRM).  Chips: BB_A0 BB_B0 K2
54112 #define PTU_REG_INV_HALT_ON_REUSE_CNT_ERR                                                            0x56008cUL //Access:RW   DataWidth:0x1   When set - the block will halt in case reuse cnt error is found, other wise the erronous request will be sent on with error indication  Chips: BB_A0 BB_B0 K2
54113 #define PTU_REG_PBF_PXP_CREDITS                                                                      0x560090UL //Access:RW   DataWidth:0x3   Max credits of the PBF->PXP interface.  Chips: BB_A0 BB_B0 K2
54114 #define PTU_REG_PRM_PXP_CREDITS                                                                      0x560094UL //Access:RW   DataWidth:0x3   Max credits of the PRM->PXP interface.  Chips: BB_A0 BB_B0 K2
54115 #define PTU_REG_PTU_PXP_CREDITS                                                                      0x560098UL //Access:RW   DataWidth:0x3   Max credits of the PTU->PXP interface.  Chips: BB_A0 BB_B0 K2
54116 #define PTU_REG_PXP_1ST_REQ_ATC_CFG                                                                  0x56009cUL //Access:RW   DataWidth:0x3   Max credits of the PTU->PXP interface.  Chips: BB_A0 BB_B0 K2
54117 #define PTU_REG_PXP_2ND_REQ_ATC_CFG                                                                  0x5600a0UL //Access:RW   DataWidth:0x3   Max credits of the PTU->PXP interface.  Chips: BB_A0 BB_B0 K2
54118 #define PTU_REG_USE_CRC_INDEX1                                                                       0x5600a4UL //Access:RW   DataWidth:0x1   CRC Index1 enable  Chips: BB_A0 BB_B0 K2
54119 #define PTU_REG_USE_CRC_INDEX2                                                                       0x5600a8UL //Access:RW   DataWidth:0x1   CRC Index2 enable  Chips: BB_A0 BB_B0 K2
54120 #define PTU_REG_INDEX1_SHIFT                                                                         0x5600acUL //Access:RW   DataWidth:0x5   CRC Index1 shift right value  Chips: BB_A0 BB_B0 K2
54121 #define PTU_REG_INDEX2_SHIFT                                                                         0x5600b0UL //Access:RW   DataWidth:0x5   CRC Index2 shift right value  Chips: BB_A0 BB_B0 K2
54122 #define PTU_REG_INDEX3_SHIFT                                                                         0x5600b4UL //Access:RW   DataWidth:0x5   CRC Index3 shift right value  Chips: BB_A0 BB_B0 K2
54123 #define PTU_REG_INDEX1_MASK                                                                          0x5600b8UL //Access:RW   DataWidth:0x20  CRC Index1 mask  Chips: BB_A0 BB_B0 K2
54124 #define PTU_REG_INDEX2_MASK                                                                          0x5600bcUL //Access:RW   DataWidth:0x20  CRC Index2 mask  Chips: BB_A0 BB_B0 K2
54125 #define PTU_REG_INDEX3_MASK                                                                          0x5600c0UL //Access:RW   DataWidth:0x20  CRC Index3 mask  Chips: BB_A0 BB_B0 K2
54126 #define PTU_REG_ATC_REP_MODE                                                                         0x5600c4UL //Access:RW   DataWidth:0x1   Replacement mode for the ATC. If de-asserted then low priority request will replace a high priority entry only if there are no low priority entries at all. If set then a high priority with PLRU=0 will be replaced in higher priority than low priority entries with PLRU=1.  Chips: BB_A0 BB_B0 K2
54127 #define PTU_REG_PBF_FILL_LEVEL                                                                       0x5600c8UL //Access:R    DataWidth:0x7   Current number of pending pbf messages  Chips: BB_A0 BB_B0 K2
54128 #define PTU_REG_PRM_FILL_LEVEL                                                                       0x5600ccUL //Access:R    DataWidth:0x7   Current number of pending prm messages  Chips: BB_A0 BB_B0 K2
54129 #define PTU_REG_PBF_FILL_LEVEL_MH                                                                    0x5600d0UL //Access:RC   DataWidth:0x7   Maximal number of pending pbf messages  Chips: BB_A0 BB_B0 K2
54130 #define PTU_REG_PRM_FILL_LEVEL_MH                                                                    0x5600d4UL //Access:RC   DataWidth:0x7   Maximal number of pending prm messages  Chips: BB_A0 BB_B0 K2
54131 #define PTU_REG_PTU_B0_DISABLE                                                                       0x5600d8UL //Access:RW   DataWidth:0x1   Disable B0 feature  Chips: BB_B0 K2
54132 #define PTU_REG_ATC_OTB_OVERRUN_FIX_CHICKEN_BIT                                                      0x5600dcUL //Access:RW   DataWidth:0x1   Chicken bit for the atc otb overrun fix.  Chips: K2
54133 #define PTU_REG_DBG_SELECT                                                                           0x560100UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
54134 #define PTU_REG_DBG_DWORD_ENABLE                                                                     0x560104UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
54135 #define PTU_REG_DBG_SHIFT                                                                            0x560108UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
54136 #define PTU_REG_DBG_FORCE_VALID                                                                      0x56010cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
54137 #define PTU_REG_DBG_FORCE_FRAME                                                                      0x560110UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
54138 #define PTU_REG_DBG_OUT_DATA                                                                         0x560120UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
54139 #define PTU_REG_DBG_OUT_DATA_SIZE                                                                    8
54140 #define PTU_REG_DBG_OUT_VALID                                                                        0x560140UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
54141 #define PTU_REG_DBG_OUT_FRAME                                                                        0x560144UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
54142 #define PTU_REG_INT_STS                                                                              0x560180UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54143     #define PTU_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
54144     #define PTU_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
54145     #define PTU_REG_INT_STS_ATC_TCPL_TO_NOT_PEND                                                     (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
54146     #define PTU_REG_INT_STS_ATC_TCPL_TO_NOT_PEND_SHIFT                                               1
54147     #define PTU_REG_INT_STS_ATC_GPA_MULTIPLE_HITS                                                    (0x1<<2) // Several hits in the GPA for the same lookup.
54148     #define PTU_REG_INT_STS_ATC_GPA_MULTIPLE_HITS_SHIFT                                              2
54149     #define PTU_REG_INT_STS_ATC_RCPL_TO_EMPTY_CNT                                                    (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
54150     #define PTU_REG_INT_STS_ATC_RCPL_TO_EMPTY_CNT_SHIFT                                              3
54151     #define PTU_REG_INT_STS_ATC_TCPL_ERROR                                                           (0x1<<4) // Indicates TCPL response with error code set.
54152     #define PTU_REG_INT_STS_ATC_TCPL_ERROR_SHIFT                                                     4
54153     #define PTU_REG_INT_STS_ATC_INV_HALT                                                             (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
54154     #define PTU_REG_INT_STS_ATC_INV_HALT_SHIFT                                                       5
54155     #define PTU_REG_INT_STS_ATC_REUSE_TRANSPEND                                                      (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
54156     #define PTU_REG_INT_STS_ATC_REUSE_TRANSPEND_SHIFT                                                6
54157     #define PTU_REG_INT_STS_ATC_IREQ_LESS_THAN_STU                                                   (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
54158     #define PTU_REG_INT_STS_ATC_IREQ_LESS_THAN_STU_SHIFT                                             7
54159 #define PTU_REG_INT_MASK                                                                             0x560184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54160     #define PTU_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ADDRESS_ERROR .
54161     #define PTU_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
54162     #define PTU_REG_INT_MASK_ATC_TCPL_TO_NOT_PEND                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_TCPL_TO_NOT_PEND .
54163     #define PTU_REG_INT_MASK_ATC_TCPL_TO_NOT_PEND_SHIFT                                              1
54164     #define PTU_REG_INT_MASK_ATC_GPA_MULTIPLE_HITS                                                   (0x1<<2) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_GPA_MULTIPLE_HITS .
54165     #define PTU_REG_INT_MASK_ATC_GPA_MULTIPLE_HITS_SHIFT                                             2
54166     #define PTU_REG_INT_MASK_ATC_RCPL_TO_EMPTY_CNT                                                   (0x1<<3) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_RCPL_TO_EMPTY_CNT .
54167     #define PTU_REG_INT_MASK_ATC_RCPL_TO_EMPTY_CNT_SHIFT                                             3
54168     #define PTU_REG_INT_MASK_ATC_TCPL_ERROR                                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_TCPL_ERROR .
54169     #define PTU_REG_INT_MASK_ATC_TCPL_ERROR_SHIFT                                                    4
54170     #define PTU_REG_INT_MASK_ATC_INV_HALT                                                            (0x1<<5) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_INV_HALT .
54171     #define PTU_REG_INT_MASK_ATC_INV_HALT_SHIFT                                                      5
54172     #define PTU_REG_INT_MASK_ATC_REUSE_TRANSPEND                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_REUSE_TRANSPEND .
54173     #define PTU_REG_INT_MASK_ATC_REUSE_TRANSPEND_SHIFT                                               6
54174     #define PTU_REG_INT_MASK_ATC_IREQ_LESS_THAN_STU                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: PTU_REG_INT_STS.ATC_IREQ_LESS_THAN_STU .
54175     #define PTU_REG_INT_MASK_ATC_IREQ_LESS_THAN_STU_SHIFT                                            7
54176 #define PTU_REG_INT_STS_WR                                                                           0x560188UL //Access:WR   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54177     #define PTU_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
54178     #define PTU_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
54179     #define PTU_REG_INT_STS_WR_ATC_TCPL_TO_NOT_PEND                                                  (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
54180     #define PTU_REG_INT_STS_WR_ATC_TCPL_TO_NOT_PEND_SHIFT                                            1
54181     #define PTU_REG_INT_STS_WR_ATC_GPA_MULTIPLE_HITS                                                 (0x1<<2) // Several hits in the GPA for the same lookup.
54182     #define PTU_REG_INT_STS_WR_ATC_GPA_MULTIPLE_HITS_SHIFT                                           2
54183     #define PTU_REG_INT_STS_WR_ATC_RCPL_TO_EMPTY_CNT                                                 (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
54184     #define PTU_REG_INT_STS_WR_ATC_RCPL_TO_EMPTY_CNT_SHIFT                                           3
54185     #define PTU_REG_INT_STS_WR_ATC_TCPL_ERROR                                                        (0x1<<4) // Indicates TCPL response with error code set.
54186     #define PTU_REG_INT_STS_WR_ATC_TCPL_ERROR_SHIFT                                                  4
54187     #define PTU_REG_INT_STS_WR_ATC_INV_HALT                                                          (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
54188     #define PTU_REG_INT_STS_WR_ATC_INV_HALT_SHIFT                                                    5
54189     #define PTU_REG_INT_STS_WR_ATC_REUSE_TRANSPEND                                                   (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
54190     #define PTU_REG_INT_STS_WR_ATC_REUSE_TRANSPEND_SHIFT                                             6
54191     #define PTU_REG_INT_STS_WR_ATC_IREQ_LESS_THAN_STU                                                (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
54192     #define PTU_REG_INT_STS_WR_ATC_IREQ_LESS_THAN_STU_SHIFT                                          7
54193 #define PTU_REG_INT_STS_CLR                                                                          0x56018cUL //Access:RC   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54194     #define PTU_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
54195     #define PTU_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
54196     #define PTU_REG_INT_STS_CLR_ATC_TCPL_TO_NOT_PEND                                                 (0x1<<1) // TCPL arrives to an entry not in Trans-Pend state.
54197     #define PTU_REG_INT_STS_CLR_ATC_TCPL_TO_NOT_PEND_SHIFT                                           1
54198     #define PTU_REG_INT_STS_CLR_ATC_GPA_MULTIPLE_HITS                                                (0x1<<2) // Several hits in the GPA for the same lookup.
54199     #define PTU_REG_INT_STS_CLR_ATC_GPA_MULTIPLE_HITS_SHIFT                                          2
54200     #define PTU_REG_INT_STS_CLR_ATC_RCPL_TO_EMPTY_CNT                                                (0x1<<3) // RCPL arrives to an entry with empty R_Cnt.
54201     #define PTU_REG_INT_STS_CLR_ATC_RCPL_TO_EMPTY_CNT_SHIFT                                          3
54202     #define PTU_REG_INT_STS_CLR_ATC_TCPL_ERROR                                                       (0x1<<4) // Indicates TCPL response with error code set.
54203     #define PTU_REG_INT_STS_CLR_ATC_TCPL_ERROR_SHIFT                                                 4
54204     #define PTU_REG_INT_STS_CLR_ATC_INV_HALT                                                         (0x1<<5) // Indicates Lookup to invalidated range with inv_halt_on_err set
54205     #define PTU_REG_INT_STS_CLR_ATC_INV_HALT_SHIFT                                                   5
54206     #define PTU_REG_INT_STS_CLR_ATC_REUSE_TRANSPEND                                                  (0x1<<6) // Indicates Lookup to entry markes as transpend with reuse counter mismatch
54207     #define PTU_REG_INT_STS_CLR_ATC_REUSE_TRANSPEND_SHIFT                                            6
54208     #define PTU_REG_INT_STS_CLR_ATC_IREQ_LESS_THAN_STU                                               (0x1<<7) // Indicates Ireq with invalidation range shorter than STU of the relevant func.
54209     #define PTU_REG_INT_STS_CLR_ATC_IREQ_LESS_THAN_STU_SHIFT                                         7
54210 #define PTU_REG_PRTY_MASK_H_0                                                                        0x560204UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54211     #define PTU_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM017_I_ECC_RF_INT .
54212     #define PTU_REG_PRTY_MASK_H_0_MEM017_I_ECC_RF_INT_SHIFT                                          0
54213     #define PTU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
54214     #define PTU_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_SHIFT                                            1
54215     #define PTU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
54216     #define PTU_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                            2
54217     #define PTU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
54218     #define PTU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            3
54219     #define PTU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
54220     #define PTU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            4
54221     #define PTU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
54222     #define PTU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            5
54223     #define PTU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
54224     #define PTU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            6
54225     #define PTU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
54226     #define PTU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                            7
54227     #define PTU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
54228     #define PTU_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                            8
54229     #define PTU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
54230     #define PTU_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                            9
54231     #define PTU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
54232     #define PTU_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_SHIFT                                            10
54233     #define PTU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
54234     #define PTU_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                            11
54235     #define PTU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
54236     #define PTU_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_SHIFT                                            12
54237     #define PTU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
54238     #define PTU_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                            13
54239     #define PTU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
54240     #define PTU_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                            14
54241     #define PTU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
54242     #define PTU_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT                                            15
54243     #define PTU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
54244     #define PTU_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                            16
54245     #define PTU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: PTU_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
54246     #define PTU_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                            17
54247 #define PTU_REG_MEM_ECC_EVENTS                                                                       0x56021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
54248 #define PTU_REG_MEM017_I_MEM_DFT_K2                                                                  0x560224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ram_spa.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54249 #define PTU_REG_MEM018_I_MEM_DFT_K2                                                                  0x560228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_tfifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
54250 #define PTU_REG_MEM006_I_MEM_DFT_K2                                                                  0x56022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ififo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
54251 #define PTU_REG_MEM001_I_MEM_DFT_K2                                                                  0x560230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_gpa_data_0_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54252 #define PTU_REG_MEM002_I_MEM_DFT_K2                                                                  0x560234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_gpa_data_1_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54253 #define PTU_REG_MEM003_I_MEM_DFT_K2                                                                  0x560238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_gpa_data_2_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54254 #define PTU_REG_MEM004_I_MEM_DFT_K2                                                                  0x56023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_gpa_data_3_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54255 #define PTU_REG_MEM005_I_MEM_DFT_K2                                                                  0x560240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_gpa_set_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54256 #define PTU_REG_MEM009_I_MEM_DFT_K2                                                                  0x560244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_pend_msg_addr_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54257 #define PTU_REG_MEM010_I_MEM_DFT_K2                                                                  0x560248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_pend_msg_data_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54258 #define PTU_REG_MEM016_I_MEM_DFT_K2                                                                  0x56024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_req_inp_fifo_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54259 #define PTU_REG_MEM007_I_MEM_DFT_K2                                                                  0x560250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_lkpres_fifo_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54260 #define PTU_REG_MEM013_I_MEM_DFT_K2                                                                  0x560254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_pxp_2nd_req_fifo_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54261 #define PTU_REG_MEM012_I_MEM_DFT_K2                                                                  0x560258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_pxp_2nd_addr_fifo_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54262 #define PTU_REG_MEM014_I_MEM_DFT_K2                                                                  0x56025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_pxp_req_fifo_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54263 #define PTU_REG_MEM011_I_MEM_DFT_K2                                                                  0x560260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_prm_out_fifo_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54264 #define PTU_REG_MEM008_I_MEM_DFT_K2                                                                  0x560264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ptu.i_ptu_pbf_out_fifo_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54265 #define PTU_REG_ATC_NUM_SETS                                                                         0x560400UL //Access:RW   DataWidth:0x2   Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32.  Chips: BB_A0 BB_B0 K2
54266 #define PTU_REG_ATC_1_WAY                                                                            0x560404UL //Access:RW   DataWidth:0x1   If set the ATC will use only one way per set.  Chips: BB_A0 BB_B0 K2
54267 #define PTU_REG_ATC_FULL_REG                                                                         0x560408UL //Access:R    DataWidth:0x8   SPA Done FIFO full bit; RCPL FIFO full bit; TCPL FIFO full bit; IREQ full bit; PLKP FIFO full bit; MLKP FIFO full bit; OTB full bit; OIB full bit.  Chips: BB_A0 BB_B0 K2
54268 #define PTU_REG_ATC_EMPTY_REG                                                                        0x56040cUL //Access:R    DataWidth:0x8   SPA Done FIFO empty bit; RCPL FIFO empty bit; TCPL FIFO empty bit; IREQ empty bit; PLKP FIFO empty bit; MLKP FIFO empty bit; OTB empty bit; OIB empty bit.  Chips: BB_A0 BB_B0 K2
54269 #define PTU_REG_ATC_WAIT_IF_MISS                                                                     0x560410UL //Access:RW   DataWidth:0x1   WaitIfMiss configuration bit.  Chips: BB_A0 BB_B0 K2
54270 #define PTU_REG_ATC_WAIT_IF_PENDING                                                                  0x560414UL //Access:RW   DataWidth:0x1   WaitTransPending cofiguration bit.  Chips: BB_A0 BB_B0 K2
54271 #define PTU_REG_ATC_STALL_SEQ_0                                                                      0x560418UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54272 #define PTU_REG_ATC_STALL_SEQ_1                                                                      0x56041cUL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54273 #define PTU_REG_ATC_STALL_SEQ_2                                                                      0x560420UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54274 #define PTU_REG_ATC_STALL_SEQ_3                                                                      0x560424UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54275 #define PTU_REG_ATC_STALL_SEQ_4                                                                      0x560428UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54276 #define PTU_REG_ATC_STALL_SEQ_5                                                                      0x56042cUL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54277 #define PTU_REG_ATC_SET_STALL_SEQ_0                                                                  0x560430UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54278 #define PTU_REG_ATC_SET_STALL_SEQ_1                                                                  0x560434UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54279 #define PTU_REG_ATC_SET_STALL_SEQ_2                                                                  0x560438UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54280 #define PTU_REG_ATC_SET_STALL_SEQ_3                                                                  0x56043cUL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54281 #define PTU_REG_ATC_SET_STALL_SEQ_4                                                                  0x560440UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54282 #define PTU_REG_ATC_SET_STALL_SEQ_5                                                                  0x560444UL //Access:RW   DataWidth:0x6   Indicates the B2B event sequnece which will cause stall in case of 2 consecutive accesses to the same set (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rcpl. The order of the bits inside the vector is the same. Stall is taking place when there is a sequence of two events X and than Y to the same set; and atc_stall_seq[X][Y] is set to 1. Comment for E2: stall is not available for lookups due to the bounded latency restriction.  Chips: BB_A0 BB_B0 K2
54283 #define PTU_REG_ATC_DISABLE_BYPASS                                                                   0x560448UL //Access:RW   DataWidth:0x1   Disables the bypass on the GPA table.  Chips: BB_A0 BB_B0 K2
54284 #define PTU_REG_ATC_ISSUE_4_CYCLES                                                                   0x56044cUL //Access:RW   DataWidth:0x1   Issue event once in four cycles (instead of 2).  Chips: BB_A0 BB_B0 K2
54285 #define PTU_REG_ATC_IREQ_FIFO_SIZE                                                                   0x560450UL //Access:RW   DataWidth:0x8   Defines the size of the IREQ fifo.  Chips: BB_A0 BB_B0 K2
54286 #define PTU_REG_ATC_IREQ_ALMOST_FULL_THR                                                             0x560454UL //Access:RW   DataWidth:0x8   Debug only: defines the IFIFO almost full threshold. Its size can't be bigger than the Ireq FIFO size. The full resp delay of the interface is 4. There is a problem with the implementation and the real value the FIFO can absorbe is 1 below the configured value, but 4 request still can be received when the register configured to 6  Chips: BB_A0 BB_B0 K2
54287 #define PTU_REG_ATC_PIGGYBACKED_TREQ_EN                                                              0x560458UL //Access:RW   DataWidth:0x1   Piggybacked treq issue enabled.  Chips: BB_A0 BB_B0 K2
54288 #define PTU_REG_ATC_WAIT_RESP                                                                        0x56045cUL //Access:RW   DataWidth:0x1   Allows the ATC to return Wait response.  Chips: BB_A0 BB_B0 K2
54289 #define PTU_REG_ATC_TREQ_CREDITS                                                                     0x560460UL //Access:RW   DataWidth:0x6   Number of credits for the treq interface.  Chips: BB_A0 BB_B0 K2
54290 #define PTU_REG_ATC_ARBITER_PRIO_MLKP                                                                0x560464UL //Access:RW   DataWidth:0x2   MLKP prio.  Chips: BB_A0 BB_B0 K2
54291 #define PTU_REG_ATC_ARBITER_PRIO_PLKP                                                                0x560468UL //Access:RW   DataWidth:0x2   PLKP prio.  Chips: BB_A0 BB_B0 K2
54292 #define PTU_REG_ATC_ARBITER_PRIO_IREQ                                                                0x56046cUL //Access:RW   DataWidth:0x2   IREQ prio.  Chips: BB_A0 BB_B0 K2
54293 #define PTU_REG_ATC_ARBITER_PRIO_TCPL                                                                0x560470UL //Access:RW   DataWidth:0x2   TCPL prio.  Chips: BB_A0 BB_B0 K2
54294 #define PTU_REG_ATC_ARBITER_PRIO_SPAD                                                                0x560474UL //Access:RW   DataWidth:0x2   SPAD prio.  Chips: BB_A0 BB_B0 K2
54295 #define PTU_REG_ATC_ARBITER_PRIO_RCPL                                                                0x560478UL //Access:RW   DataWidth:0x2   RCPL prio.  Chips: BB_A0 BB_B0 K2
54296 #define PTU_REG_ATC_OTB_MAX_ENTRY                                                                    0x56047cUL //Access:RW   DataWidth:0x6   Defines the number of entries in the OTB when 31 indicates 32 entries (entries count begins in 0).  Chips: BB_A0 BB_B0 K2
54297 #define PTU_REG_ATC_CHECK_TAGS                                                                       0x560480UL //Access:RW   DataWidth:0x1   CheckTags configuration bit - when set the available NPH credits is checked before issuing TREQ.  Chips: BB_A0 BB_B0 K2
54298 #define PTU_REG_ATC_TAG_THR                                                                          0x560484UL //Access:RW   DataWidth:0x8   TAG threshold - for the checkTags feature.  Chips: BB_A0 BB_B0 K2
54299 #define PTU_REG_ATC_ICPL_CREDIT                                                                      0x560488UL //Access:RW   DataWidth:0x3   Credit value for the ICPL interface.  Chips: BB_A0 BB_B0 K2
54300 #define PTU_REG_ATC_DIS_MLKP                                                                         0x56048cUL //Access:RW   DataWidth:0x1   Disables the main lookup interface.  Chips: BB_A0 BB_B0 K2
54301 #define PTU_REG_ATC_DIS_PLKP                                                                         0x560490UL //Access:RW   DataWidth:0x1   Disables the pre lookup interface.  Chips: BB_A0 BB_B0 K2
54302 #define PTU_REG_ATC_DIS_IREQ                                                                         0x560494UL //Access:RW   DataWidth:0x1   Disables the invalidation request interface.  Chips: BB_A0 BB_B0 K2
54303 #define PTU_REG_ATC_DIS_TCPL                                                                         0x560498UL //Access:RW   DataWidth:0x1   Disables the translation completion interface.  Chips: BB_A0 BB_B0 K2
54304 #define PTU_REG_ATC_DIS_SPAD                                                                         0x56049cUL //Access:RW   DataWidth:0x1   Disables the spa done interface.  Chips: BB_A0 BB_B0 K2
54305 #define PTU_REG_ATC_DIS_RCPL                                                                         0x5604a0UL //Access:RW   DataWidth:0x1   Disables the Read Completion interface.  Chips: BB_A0 BB_B0 K2
54306 #define PTU_REG_ATC_DIS_LKPRES                                                                       0x5604a4UL //Access:RW   DataWidth:0x1   Disables the lookup response interface.  Chips: BB_A0 BB_B0 K2
54307 #define PTU_REG_ATC_DIS_TREQ                                                                         0x5604a8UL //Access:RW   DataWidth:0x1   Disables the translation request interface.  Chips: BB_A0 BB_B0 K2
54308 #define PTU_REG_ATC_DIS_ICPL                                                                         0x5604acUL //Access:RW   DataWidth:0x1   Disables the invalidation completion interface.  Chips: BB_A0 BB_B0 K2
54309 #define PTU_REG_ATC_SCRUB_CYC                                                                        0x5604b0UL //Access:RW   DataWidth:0x8   Number of cycles between one scrub event to another.  Chips: BB_A0 BB_B0 K2
54310 #define PTU_REG_ATC_SCRUB_DIS                                                                        0x5604b4UL //Access:RW   DataWidth:0x1   Disable bit for the scrubbing event of the GPA table.  Chips: BB_A0 BB_B0 K2
54311 #define PTU_REG_ATC_STAT_MLKP_HITS                                                                   0x5604b8UL //Access:RC   DataWidth:0x20  Number of hits for Main-lookups in the ATC.  Chips: BB_A0 BB_B0 K2
54312 #define PTU_REG_ATC_STAT_MLKP_NUM                                                                    0x5604bcUL //Access:RC   DataWidth:0x20  Number of Main lookups in the ATC.  Chips: BB_A0 BB_B0 K2
54313 #define PTU_REG_ATC_STAT_PLKP_TREQ                                                                   0x5604c0UL //Access:RC   DataWidth:0x20  Number of treqs issued due to pre-lookup.  Chips: BB_A0 BB_B0 K2
54314 #define PTU_REG_ATC_STAT_PLKP_NUM                                                                    0x5604c4UL //Access:RC   DataWidth:0x20  Number of Pre Lookps in the ATC.  Chips: BB_A0 BB_B0 K2
54315 #define PTU_REG_ATC_STAT_EVICT_NUM                                                                   0x5604c8UL //Access:RC   DataWidth:0x20  Number of evictions out of the ATC.  Chips: BB_A0 BB_B0 K2
54316 #define PTU_REG_ATC_STAT_INV_NUM                                                                     0x5604ccUL //Access:RC   DataWidth:0x20  Number of invalidations handled by the ATC.  Chips: BB_A0 BB_B0 K2
54317 #define PTU_REG_ATC_STAT_TREQ_NUM                                                                    0x5604d0UL //Access:RC   DataWidth:0x20  Number of translation requests issued by the ATC.  Chips: BB_A0 BB_B0 K2
54318 #define PTU_REG_ATC_STAT_ACTIVE                                                                      0x5604d4UL //Access:RW   DataWidth:0x1   When this signal is set the statistics count is on.  Chips: BB_A0 BB_B0 K2
54319 #define PTU_REG_ATC_STAT_USDM_LKP_NUM                                                                0x5604d8UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54320 #define PTU_REG_ATC_STAT_USDM_HIT_NUM                                                                0x5604dcUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54321 #define PTU_REG_ATC_STAT_XSDM_LKP_NUM                                                                0x5604e0UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54322 #define PTU_REG_ATC_STAT_XSDM_HIT_NUM                                                                0x5604e4UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54323 #define PTU_REG_ATC_STAT_TSDM_LKP_NUM                                                                0x5604e8UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54324 #define PTU_REG_ATC_STAT_TSDM_HIT_NUM                                                                0x5604ecUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54325 #define PTU_REG_ATC_STAT_PBF_LKP_NUM                                                                 0x5604f0UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54326 #define PTU_REG_ATC_STAT_PBF_HIT_NUM                                                                 0x5604f4UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54327 #define PTU_REG_ATC_STAT_QM_LKP_NUM                                                                  0x5604f8UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54328 #define PTU_REG_ATC_STAT_QM_HIT_NUM                                                                  0x5604fcUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54329 #define PTU_REG_ATC_STAT_TM_LKP_NUM                                                                  0x560500UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54330 #define PTU_REG_ATC_STAT_TM_HIT_NUM                                                                  0x560504UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54331 #define PTU_REG_ATC_STAT_SRC_LKP_NUM                                                                 0x560508UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54332 #define PTU_REG_ATC_STAT_SRC_HIT_NUM                                                                 0x56050cUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54333 #define PTU_REG_ATC_STAT_CDURD_LKP_NUM                                                               0x560510UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54334 #define PTU_REG_ATC_STAT_CDURD_HIT_NUM                                                               0x560514UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54335 #define PTU_REG_ATC_STAT_DMAE_LKP_NUM                                                                0x560518UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54336 #define PTU_REG_ATC_STAT_DMAE_HIT_NUM                                                                0x56051cUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54337 #define PTU_REG_ATC_STAT_HC_LKP_NUM                                                                  0x560520UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54338 #define PTU_REG_ATC_STAT_HC_HIT_NUM                                                                  0x560524UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54339 #define PTU_REG_ATC_STAT_CDUWR_LKP_NUM                                                               0x560528UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54340 #define PTU_REG_ATC_STAT_CDUWR_HIT_NUM                                                               0x56052cUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54341 #define PTU_REG_ATC_STAT_DBG_LKP_NUM                                                                 0x560530UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54342 #define PTU_REG_ATC_STAT_DBG_HIT_NUM                                                                 0x560534UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54343 #define PTU_REG_ATC_STAT_MSDM_LKP_NUM                                                                0x560538UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54344 #define PTU_REG_ATC_STAT_MSDM_HIT_NUM                                                                0x56053cUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54345 #define PTU_REG_ATC_STAT_YSDM_LKP_NUM                                                                0x560540UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54346 #define PTU_REG_ATC_STAT_YSDM_HIT_NUM                                                                0x560544UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54347 #define PTU_REG_ATC_STAT_PSDM_LKP_NUM                                                                0x560548UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54348 #define PTU_REG_ATC_STAT_PSDM_HIT_NUM                                                                0x56054cUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54349 #define PTU_REG_ATC_STAT_MULD_LKP_NUM                                                                0x560550UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54350 #define PTU_REG_ATC_STAT_MULD_HIT_NUM                                                                0x560554UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54351 #define PTU_REG_ATC_STAT_XYLD_LKP_NUM                                                                0x560558UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54352 #define PTU_REG_ATC_STAT_XYLD_HIT_NUM                                                                0x56055cUL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54353 #define PTU_REG_ATC_STAT_PRM_LKP_NUM                                                                 0x560560UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54354 #define PTU_REG_ATC_STAT_PRM_HIT_NUM                                                                 0x560564UL //Access:RC   DataWidth:0x20  Count lookups and hit for the different clients.  Chips: BB_A0 BB_B0 K2
54355 #define PTU_REG_ATC_GPA_HASH_EN                                                                      0x560568UL //Access:RW   DataWidth:0x1   Enable the use of a hash function for the GPA table; instead of the lsb bits of the address.  Chips: BB_A0 BB_B0 K2
54356 #define PTU_REG_ATC_GPA_HASH_CRC                                                                     0x56056cUL //Access:RW   DataWidth:0x1   Relevant only if hash_en is set. selects the CRC as hash function for the GPA table; If reset use xor of the FID LS bits with the relevant bits out of the GPA as hash function.  Chips: BB_A0 BB_B0 K2
54357 #define PTU_REG_ATC_TCPL_LOG_ON_ERROR                                                                0x560570UL //Access:RW   DataWidth:0x5   In case of TCPL with error log the relevant data. The seperation for the different errors is: BME clear [0]; Unsupported request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4].  Chips: BB_A0 BB_B0 K2
54358 #define PTU_REG_ATC_TCPL_DIS_ON_ERROR                                                                0x560574UL //Access:RW   DataWidth:0x5   In case of TCPL with error disable the ATC.  The seperation for the different errors is: BME clear [0]; Unsupported request [1]; Completer abort/completion timeout [2]; Both R & W bits are reset [3]; Other [4].  Chips: BB_A0 BB_B0 K2
54359 #define PTU_REG_ATC_TCPL_ERR_LOG                                                                     0x560578UL //Access:R    DataWidth:0x19  Data belongs to an erroneous TCPL: [12:0] Func (VF_Valid;VFID;PFID);[13] U bit; [14] W bit; [15] R bit; [16] NS bit; [21:17] OTBEntryID;[24:22] Error code.  Chips: BB_A0 BB_B0 K2
54360 #define PTU_REG_ATC_TCPL_ERR_ADDR_LSB                                                                0x56057cUL //Access:R    DataWidth:0x20  Data belongs to an erroneous TCPL: [31:0]-bits [31:0] of the address.  Chips: BB_A0 BB_B0 K2
54361 #define PTU_REG_ATC_TCPL_ERR_ADDR_MSB                                                                0x560580UL //Access:R    DataWidth:0x14  Data belongs to an erroneous TCPL: [19:0]-bits [51:32] of the address.  Chips: BB_A0 BB_B0 K2
54362 #define PTU_REG_ATC_TCPL_ERR_LOG_VALID                                                               0x560584UL //Access:R    DataWidth:0x1   Indicates valid data at the tcpl error log registers.  Chips: BB_A0 BB_B0 K2
54363 #define PTU_REG_ATC_ARRAY_ACCESS_ENABLE                                                              0x560588UL //Access:RW   DataWidth:0x1   Allows GRC access to the GPA and SPA table.  Chips: BB_A0 BB_B0 K2
54364 #define PTU_REG_ATC_DURING_FLI                                                                       0x56058cUL //Access:R    DataWidth:0x1   Indication that the ATC currently handles FLI.  Chips: BB_A0 BB_B0 K2
54365 #define PTU_REG_ATC_DURING_INV                                                                       0x560590UL //Access:R    DataWidth:0x1   Indication that the ATC currently handles Any type of invalidation.  Chips: BB_A0 BB_B0 K2
54366 #define PTU_REG_ATC_FLI_DONE_VF_31_0                                                                 0x560594UL //Access:R    DataWidth:0x20  Indicates the end of FLI flow for VF 31-0.  Chips: BB_A0 BB_B0 K2
54367 #define PTU_REG_ATC_FLI_DONE_VF_63_32                                                                0x560598UL //Access:R    DataWidth:0x20  Indicates the end of FLI flow for VF 63-32.  Chips: BB_A0 BB_B0 K2
54368 #define PTU_REG_ATC_FLI_DONE_VF_95_64                                                                0x56059cUL //Access:R    DataWidth:0x20  Indicates the end of FLI flow for VF 95-64.  Chips: BB_A0 BB_B0 K2
54369 #define PTU_REG_ATC_FLI_DONE_VF_127_96                                                               0x5605a0UL //Access:R    DataWidth:0x20  Indicates the end of FLI flow for VF 127-96.  Chips: BB_A0 BB_B0 K2
54370 #define PTU_REG_ATC_FLI_DONE_VF_159_128                                                              0x5605a4UL //Access:R    DataWidth:0x20  Indicates the end of FLI flow for VF 159-128.  Chips: BB_A0 BB_B0 K2
54371 #define PTU_REG_ATC_FLI_DONE_VF_191_160                                                              0x5605a8UL //Access:R    DataWidth:0x20  Indicates the end of FLI flow for VF 191-160.  Chips: BB_A0 BB_B0 K2
54372 #define PTU_REG_ATC_FLI_DONE_PF_15_0                                                                 0x5605acUL //Access:R    DataWidth:0x10  Indicates the end of FLI flow for PF 15-0.  Chips: BB_A0 BB_B0 K2
54373 #define PTU_REG_ATC_FLI_DONE_CLR_VF_31_0                                                             0x5605b0UL //Access:RW   DataWidth:0x20  Clears the FLI done indication for VF bits 31-0 accordingly.  Chips: BB_A0 BB_B0 K2
54374 #define PTU_REG_ATC_FLI_DONE_CLR_VF_63_32                                                            0x5605b4UL //Access:RW   DataWidth:0x20  Clears the FLI done indication for VFbits 63-32 accordingly.  Chips: BB_A0 BB_B0 K2
54375 #define PTU_REG_ATC_FLI_DONE_CLR_VF_95_64                                                            0x5605b8UL //Access:RW   DataWidth:0x20  Clears the FLI done indication for VF bits 95-64 accordingly.  Chips: BB_A0 BB_B0 K2
54376 #define PTU_REG_ATC_FLI_DONE_CLR_VF_127_96                                                           0x5605bcUL //Access:RW   DataWidth:0x20  Clears the FLI done indication for VFbits 127-96 accordingly.  Chips: BB_A0 BB_B0 K2
54377 #define PTU_REG_ATC_FLI_DONE_CLR_VF_159_128                                                          0x5605c0UL //Access:RW   DataWidth:0x20  Clears the FLI done indication for VF bits 159-128 accordingly.  Chips: BB_A0 BB_B0 K2
54378 #define PTU_REG_ATC_FLI_DONE_CLR_VF_191_160                                                          0x5605c4UL //Access:RW   DataWidth:0x20  Clears the FLI done indication for VFbits 191-160 accordingly.  Chips: BB_A0 BB_B0 K2
54379 #define PTU_REG_ATC_FLI_DONE_CLR_PF_15_0                                                             0x5605c8UL //Access:RW   DataWidth:0x10  Clears the FLI done indication for PF bits 15-0 accordingly.  Chips: BB_A0 BB_B0 K2
54380 #define PTU_REG_DBGSYN_ALMOST_FULL_THR                                                               0x5605ccUL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed. Its value can't be bigger than the set dbg FIFO size.  Chips: BB_A0 BB_B0 K2
54381 #define PTU_REG_ATC_ALLOW_LOW_REP_HIGH                                                               0x5605d0UL //Access:RW   DataWidth:0x1   When set low priority lookup can replace high priority entry; iff the set is full with high prio entries.  Chips: BB_A0 BB_B0 K2
54382 #define PTU_REG_ATC_DIS_IREQ_EVENT                                                                   0x5605d4UL //Access:RW   DataWidth:0x1   When set Ireq event won't be selected by the ATC arbiter.  Chips: BB_A0 BB_B0 K2
54383 #define PTU_REG_ATC_ECO_RESERVED                                                                     0x5605d8UL //Access:RW   DataWidth:0x1   For future ECOs implementation.  Chips: BB_A0 BB_B0 K2
54384 #define PTU_REG_ATC_TM                                                                               0x5605dcUL //Access:RW   DataWidth:0x1e  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54385     #define PTU_REG_ATC_TM_ATC_SPA_TABLE_TM                                                          (0x1f<<0) // TM bits of SPA table.
54386     #define PTU_REG_ATC_TM_ATC_SPA_TABLE_TM_SHIFT                                                    0
54387     #define PTU_REG_ATC_TM_ATC_GPA_DATA_W0_TM                                                        (0x1f<<5) // TM bits of GPA data Way0.
54388     #define PTU_REG_ATC_TM_ATC_GPA_DATA_W0_TM_SHIFT                                                  5
54389     #define PTU_REG_ATC_TM_ATC_GPA_DATA_W1_TM                                                        (0x1f<<10) // TM bits of GPA data Way1.
54390     #define PTU_REG_ATC_TM_ATC_GPA_DATA_W1_TM_SHIFT                                                  10
54391     #define PTU_REG_ATC_TM_ATC_GPA_DATA_W2_TM                                                        (0x1f<<15) // TM bits of GPA data Way2.
54392     #define PTU_REG_ATC_TM_ATC_GPA_DATA_W2_TM_SHIFT                                                  15
54393     #define PTU_REG_ATC_TM_ATC_GPA_DATA_W3_TM                                                        (0x1f<<20) // TM bits of GPA data Way3.
54394     #define PTU_REG_ATC_TM_ATC_GPA_DATA_W3_TM_SHIFT                                                  20
54395     #define PTU_REG_ATC_TM_ATC_GPA_STATE_TM                                                          (0x1f<<25) // TM bits of GPA state array.
54396     #define PTU_REG_ATC_TM_ATC_GPA_STATE_TM_SHIFT                                                    25
54397 #define PTU_REG_ATC_IREQ_FIFO_TM                                                                     0x5605e0UL //Access:RW   DataWidth:0x8   TM bits of GPA state array.  Chips: BB_A0 BB_B0 K2
54398 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_W0                                                              0x560800UL //Access:WB   DataWidth:0x40  Access the GPA table way 0; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:0]-[63:61].  Chips: BB_A0 BB_B0 K2
54399 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_W0_SIZE                                                         512
54400 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_W1                                                              0x561000UL //Access:WB   DataWidth:0x40  Access the GPA table way 1; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:0]-[63:60].  Chips: BB_A0 BB_B0 K2
54401 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_W1_SIZE                                                         512
54402 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_W2                                                              0x561800UL //Access:WB   DataWidth:0x40  Access the GPA table way 2; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID[2:0]-[63:61].  Chips: BB_A0 BB_B0 K2
54403 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_W2_SIZE                                                         512
54404 #define PTU_REG_ATC_SPA_ARRAY_ACCESS                                                                 0x562000UL //Access:WB   DataWidth:0x34  Debug access to the SPA array.  Chips: BB_A0 BB_B0 K2
54405 #define PTU_REG_ATC_SPA_ARRAY_ACCESS_SIZE                                                            2048
54406 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_W3                                                              0x564000UL //Access:WB   DataWidth:0x40  Access the GPA table way3; format is: GPA - [51:0]; VF_Valid-[52]; VFID-[60:53]; PFID-[63:61].  Chips: BB_A0 BB_B0 K2
54407 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_W3_SIZE                                                         512
54408 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_STATE                                                           0x564800UL //Access:WB   DataWidth:0x14  Access the state fields of the GPA table; format is: W3 - {par - [51]; NS bit - [50]; W bit - [49]; R bit - [48]; U bit - [47]; Priority bit - [46]; PLRU - [45];  R-counter - [44:42]; transpend bit - [41]; invpend bit [40]; valid bit[39]}; W2 - {par - [38]; NS bit - [37]; W bit - [36]; R bit - [35]; U bit - [34]; Priority bit - [33]; PLRU - [32];  R-counter - [31:29]; transpend bit - [28]; invpend bit [27]; valid bit[26]}; W1 -  {par - [25]; NS bit - [24]; W bit - [23]; R bit - [22]; U bit - [21]; Priority bit - [20]; PLRU - [19];  R-counter - [18:16]; transpend bit - [15]; invpend bit [14]; valid bit[13]}; W0 -  {par - [12]; NS bit - [11]; W bit - [10]; R bit - [9]; U bit - [8]; Priority bit - [7]; PLRU - [6];  R-counter - [5:3]; transpend bit - [2]; invpend bit [1]; valid bit[0]}.  Chips: BB_A0 BB_B0 K2
54409 #define PTU_REG_ATC_GPA_ARRAY_ACCESS_STATE_SIZE                                                      256
54410 #define CDU_REG_CONTROL0                                                                             0x580040UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54411     #define CDU_REG_CONTROL0_ENABLE_PXP                                                              (0x1<<0) // Enables PXP Accesses.
54412     #define CDU_REG_CONTROL0_ENABLE_PXP_SHIFT                                                        0
54413     #define CDU_REG_CONTROL0_ENABLE_INPUTS                                                           (0x1<<1) // Enables CDU Inputs -- Must be set for normal operation.
54414     #define CDU_REG_CONTROL0_ENABLE_INPUTS_SHIFT                                                     1
54415     #define CDU_REG_CONTROL0_ENABLE_OUTPUTS                                                          (0x1<<2) // Enables CDU Outputs --  Must be set for normal operation.
54416     #define CDU_REG_CONTROL0_ENABLE_OUTPUTS_SHIFT                                                    2
54417     #define CDU_REG_CONTROL0_L1TT_SP                                                                 (0x1<<3) // Sets the L1TT Arbiter to Strict Priority;  This causes the WB Controller to always have priority over the LD Controller.
54418     #define CDU_REG_CONTROL0_L1TT_SP_SHIFT                                                           3
54419     #define CDU_REG_CONTROL0_MATT_SP                                                                 (0x1<<4) // Sets the MATT Arbiter to Strict Priority;  This causes the WB Controller to always have priority over the LD Controller.
54420     #define CDU_REG_CONTROL0_MATT_SP_SHIFT                                                           4
54421     #define CDU_REG_CONTROL0_PXP_SP                                                                  (0x1<<5) // Sets the PXP Arbiter to Strict Priority;  This causes the WB Controller to always have priority over the LD Controller.
54422     #define CDU_REG_CONTROL0_PXP_SP_SHIFT                                                            5
54423     #define CDU_REG_CONTROL0_MASK_PCIE_ERR                                                           (0x1<<6) // Masks all PCIE Errors for Load transactions.         NOTE -- This is not connected in E4 A0.
54424     #define CDU_REG_CONTROL0_MASK_PCIE_ERR_SHIFT                                                     6
54425 #define CDU_REG_INT_STS                                                                              0x5801c0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54426     #define CDU_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
54427     #define CDU_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
54428     #define CDU_REG_INT_STS_CCFC_LD_L1_NUM_ERROR                                                     (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
54429     #define CDU_REG_INT_STS_CCFC_LD_L1_NUM_ERROR_SHIFT                                               1
54430     #define CDU_REG_INT_STS_TCFC_LD_L1_NUM_ERROR                                                     (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
54431     #define CDU_REG_INT_STS_TCFC_LD_L1_NUM_ERROR_SHIFT                                               2
54432     #define CDU_REG_INT_STS_CCFC_WB_L1_NUM_ERROR                                                     (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
54433     #define CDU_REG_INT_STS_CCFC_WB_L1_NUM_ERROR_SHIFT                                               3
54434     #define CDU_REG_INT_STS_TCFC_WB_L1_NUM_ERROR                                                     (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
54435     #define CDU_REG_INT_STS_TCFC_WB_L1_NUM_ERROR_SHIFT                                               4
54436     #define CDU_REG_INT_STS_CCFC_CVLD_ERROR                                                          (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
54437     #define CDU_REG_INT_STS_CCFC_CVLD_ERROR_SHIFT                                                    5
54438     #define CDU_REG_INT_STS_TCFC_CVLD_ERROR                                                          (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
54439     #define CDU_REG_INT_STS_TCFC_CVLD_ERROR_SHIFT                                                    6
54440     #define CDU_REG_INT_STS_BVALID_ERROR                                                             (0x1<<7) // Byte valid Error on PXP Interface.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
54441     #define CDU_REG_INT_STS_BVALID_ERROR_SHIFT                                                       7
54442 #define CDU_REG_INT_STS_CLR                                                                          0x5801c4UL //Access:RC   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54443     #define CDU_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
54444     #define CDU_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
54445     #define CDU_REG_INT_STS_CLR_CCFC_LD_L1_NUM_ERROR                                                 (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
54446     #define CDU_REG_INT_STS_CLR_CCFC_LD_L1_NUM_ERROR_SHIFT                                           1
54447     #define CDU_REG_INT_STS_CLR_TCFC_LD_L1_NUM_ERROR                                                 (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
54448     #define CDU_REG_INT_STS_CLR_TCFC_LD_L1_NUM_ERROR_SHIFT                                           2
54449     #define CDU_REG_INT_STS_CLR_CCFC_WB_L1_NUM_ERROR                                                 (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
54450     #define CDU_REG_INT_STS_CLR_CCFC_WB_L1_NUM_ERROR_SHIFT                                           3
54451     #define CDU_REG_INT_STS_CLR_TCFC_WB_L1_NUM_ERROR                                                 (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
54452     #define CDU_REG_INT_STS_CLR_TCFC_WB_L1_NUM_ERROR_SHIFT                                           4
54453     #define CDU_REG_INT_STS_CLR_CCFC_CVLD_ERROR                                                      (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
54454     #define CDU_REG_INT_STS_CLR_CCFC_CVLD_ERROR_SHIFT                                                5
54455     #define CDU_REG_INT_STS_CLR_TCFC_CVLD_ERROR                                                      (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
54456     #define CDU_REG_INT_STS_CLR_TCFC_CVLD_ERROR_SHIFT                                                6
54457     #define CDU_REG_INT_STS_CLR_BVALID_ERROR                                                         (0x1<<7) // Byte valid Error on PXP Interface.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
54458     #define CDU_REG_INT_STS_CLR_BVALID_ERROR_SHIFT                                                   7
54459 #define CDU_REG_INT_STS_WR                                                                           0x5801c8UL //Access:WR   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54460     #define CDU_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
54461     #define CDU_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
54462     #define CDU_REG_INT_STS_WR_CCFC_LD_L1_NUM_ERROR                                                  (0x1<<1) // Number of L1s within a CCFC Load Request exceeds total number of L1s allowed. Error data is logged in the ccfc_ld_l1_num_error_data register.
54463     #define CDU_REG_INT_STS_WR_CCFC_LD_L1_NUM_ERROR_SHIFT                                            1
54464     #define CDU_REG_INT_STS_WR_TCFC_LD_L1_NUM_ERROR                                                  (0x1<<2) // Number of L1s within a TCFC Load Request exceeds total number of L1s allowed. Error data is logged in the tcfc_ld_l1_num_error_data register.
54465     #define CDU_REG_INT_STS_WR_TCFC_LD_L1_NUM_ERROR_SHIFT                                            2
54466     #define CDU_REG_INT_STS_WR_CCFC_WB_L1_NUM_ERROR                                                  (0x1<<3) // Number of L1s within a CCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the ccfc_wb_l1_num_error_data register.
54467     #define CDU_REG_INT_STS_WR_CCFC_WB_L1_NUM_ERROR_SHIFT                                            3
54468     #define CDU_REG_INT_STS_WR_TCFC_WB_L1_NUM_ERROR                                                  (0x1<<4) // Number of L1s within a TCFC WriteBack Request exceeds total number of L1s allowed. Error data is logged in the tcfc_wb_l1_num_error_data register.
54469     #define CDU_REG_INT_STS_WR_TCFC_WB_L1_NUM_ERROR_SHIFT                                            4
54470     #define CDU_REG_INT_STS_WR_CCFC_CVLD_ERROR                                                       (0x1<<5) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
54471     #define CDU_REG_INT_STS_WR_CCFC_CVLD_ERROR_SHIFT                                                 5
54472     #define CDU_REG_INT_STS_WR_TCFC_CVLD_ERROR                                                       (0x1<<6) // Context or Active Validation error in CCFC Load Datapath. Error data is logged in the ccfc_cvld_error_data register.
54473     #define CDU_REG_INT_STS_WR_TCFC_CVLD_ERROR_SHIFT                                                 6
54474     #define CDU_REG_INT_STS_WR_BVALID_ERROR                                                          (0x1<<7) // Byte valid Error on PXP Interface.  All transactions should be either 8 or 16 bytes, so pxp_bvalid[2:0] should always be 3'b000.
54475     #define CDU_REG_INT_STS_WR_BVALID_ERROR_SHIFT                                                    7
54476 #define CDU_REG_INT_MASK                                                                             0x5801ccUL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54477     #define CDU_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.ADDRESS_ERROR .
54478     #define CDU_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
54479     #define CDU_REG_INT_MASK_CCFC_LD_L1_NUM_ERROR                                                    (0x1<<1) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_LD_L1_NUM_ERROR .
54480     #define CDU_REG_INT_MASK_CCFC_LD_L1_NUM_ERROR_SHIFT                                              1
54481     #define CDU_REG_INT_MASK_TCFC_LD_L1_NUM_ERROR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_LD_L1_NUM_ERROR .
54482     #define CDU_REG_INT_MASK_TCFC_LD_L1_NUM_ERROR_SHIFT                                              2
54483     #define CDU_REG_INT_MASK_CCFC_WB_L1_NUM_ERROR                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_WB_L1_NUM_ERROR .
54484     #define CDU_REG_INT_MASK_CCFC_WB_L1_NUM_ERROR_SHIFT                                              3
54485     #define CDU_REG_INT_MASK_TCFC_WB_L1_NUM_ERROR                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_WB_L1_NUM_ERROR .
54486     #define CDU_REG_INT_MASK_TCFC_WB_L1_NUM_ERROR_SHIFT                                              4
54487     #define CDU_REG_INT_MASK_CCFC_CVLD_ERROR                                                         (0x1<<5) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.CCFC_CVLD_ERROR .
54488     #define CDU_REG_INT_MASK_CCFC_CVLD_ERROR_SHIFT                                                   5
54489     #define CDU_REG_INT_MASK_TCFC_CVLD_ERROR                                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.TCFC_CVLD_ERROR .
54490     #define CDU_REG_INT_MASK_TCFC_CVLD_ERROR_SHIFT                                                   6
54491     #define CDU_REG_INT_MASK_BVALID_ERROR                                                            (0x1<<7) // This bit masks, when set, the Interrupt bit: CDU_REG_INT_STS.BVALID_ERROR .
54492     #define CDU_REG_INT_MASK_BVALID_ERROR_SHIFT                                                      7
54493 #define CDU_REG_PRTY_MASK_H_0                                                                        0x580204UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
54494     #define CDU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
54495     #define CDU_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            0
54496     #define CDU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
54497     #define CDU_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            1
54498     #define CDU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
54499     #define CDU_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            2
54500     #define CDU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
54501     #define CDU_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                            3
54502     #define CDU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: CDU_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
54503     #define CDU_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            4
54504 #define CDU_REG_MEM_ECC_EVENTS                                                                       0x580210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
54505 #define CDU_REG_MEM001_I_MEM_DFT_K2                                                                  0x580218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cdu.u_cdu_ccfc_l1tt.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54506 #define CDU_REG_MEM004_I_MEM_DFT_K2                                                                  0x58021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cdu.u_cdu_tcfc_l1tt.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54507 #define CDU_REG_MEM002_I_MEM_DFT_K2                                                                  0x580220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cdu.u_cdu_ccfc_matt.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54508 #define CDU_REG_MEM005_I_MEM_DFT_K2                                                                  0x580224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cdu.u_cdu_tcfc_matt.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54509 #define CDU_REG_MEM003_I_MEM_DFT_K2                                                                  0x580228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance cdu.u_cdu_tcfc_fl_matt.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54510 #define CDU_REG_CCFC_CTX_VALID0                                                                      0x580400UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54511     #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN0_CCFC                                                   (0xff<<0) // CCFC Conxtext Validation for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54512     #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN0_CCFC_SHIFT                                             0
54513     #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN1_CCFC                                                   (0xff<<8) // CCFC Conxtext Validation for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54514     #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN1_CCFC_SHIFT                                             8
54515     #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN2_CCFC                                                   (0xff<<16) // CCFC Conxtext Validation for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54516     #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN2_CCFC_SHIFT                                             16
54517     #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN3_CCFC                                                   (0xff<<24) // CCFC Conxtext Validation for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54518     #define CDU_REG_CCFC_CTX_VALID0_CHECK_EN3_CCFC_SHIFT                                             24
54519 #define CDU_REG_CCFC_CTX_VALID1                                                                      0x580404UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54520     #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN4_CCFC                                                   (0xff<<0) // CCFC Conxtext Validation for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54521     #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN4_CCFC_SHIFT                                             0
54522     #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN5_CCFC                                                   (0xff<<8) // CCFC Conxtext Validation for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54523     #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN5_CCFC_SHIFT                                             8
54524     #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN6_CCFC                                                   (0xff<<16) // CCFC Conxtext Validation for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54525     #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN6_CCFC_SHIFT                                             16
54526     #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN7_CCFC                                                   (0xff<<24) // CCFC Conxtext Validation for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54527     #define CDU_REG_CCFC_CTX_VALID1_CHECK_EN7_CCFC_SHIFT                                             24
54528 #define CDU_REG_TCFC_CTX_VALID0                                                                      0x580408UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54529     #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN0_TCFC                                                   (0xff<<0) // TCFC Conxtext Validation for Region0 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54530     #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN0_TCFC_SHIFT                                             0
54531     #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN1_TCFC                                                   (0xff<<8) // TCFC Conxtext Validation for Region1 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54532     #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN1_TCFC_SHIFT                                             8
54533     #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN2_TCFC                                                   (0xff<<16) // TCFC Conxtext Validation for Region2 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54534     #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN2_TCFC_SHIFT                                             16
54535     #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN3_TCFC                                                   (0xff<<24) // TCFC Conxtext Validation for Region3 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54536     #define CDU_REG_TCFC_CTX_VALID0_CHECK_EN3_TCFC_SHIFT                                             24
54537 #define CDU_REG_TCFC_CTX_VALID1                                                                      0x58040cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54538     #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN4_TCFC                                                   (0xff<<0) // TCFC Conxtext Validation for Region4 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54539     #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN4_TCFC_SHIFT                                             0
54540     #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN5_TCFC                                                   (0xff<<8) // TCFC Conxtext Validation for Region5 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54541     #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN5_TCFC_SHIFT                                             8
54542     #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN6_TCFC                                                   (0xff<<16) // TCFC Conxtext Validation for Region6 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54543     #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN6_TCFC_SHIFT                                             16
54544     #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN7_TCFC                                                   (0xff<<24) // TCFC Conxtext Validation for Region7 Fields:[7:6] - Reserved; [5] - Active; [4] - CID; [3] - Region; [2] - Type; [1] - Check_Type_B (0=A;1=B); [0] - Check Enable.
54545     #define CDU_REG_TCFC_CTX_VALID1_CHECK_EN7_TCFC_SHIFT                                             24
54546 #define CDU_REG_LDBUF_AF_THRESH                                                                      0x580500UL //Access:RW   DataWidth:0x4   Almost Full Threshold on Load Datapath;  Controls the Full signal to PXP. This register must never be set higher than 8 -- doing so will result in FIFO overflows due to the Reponse time from the PXP lock.  Chips: BB_A0 BB_B0 K2
54547 #define CDU_REG_WBBUF_AF_THRESH                                                                      0x580504UL //Access:RW   DataWidth:0x4   Almost Full Threshold on Writeback Datapath;  Stops Reading L1 Memories when past this limit. This register must never be set higher than 13 -- doing so will result in data corruption to the PXP due to FIFO overflow.  Chips: BB_A0 BB_B0 K2
54548 #define CDU_REG_CCFC_PXP                                                                             0x580600UL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54549     #define CDU_REG_CCFC_PXP_CCFC_ATC_FLAGS_WB                                                       (0x7<<0) // ATC Flags Field for CCFC PXP Writes.
54550     #define CDU_REG_CCFC_PXP_CCFC_ATC_FLAGS_WB_SHIFT                                                 0
54551     #define CDU_REG_CCFC_PXP_CCFC_ATC_FLAGS_LD                                                       (0x7<<3) // ATC Flags Field for CCFC PXP Reads.
54552     #define CDU_REG_CCFC_PXP_CCFC_ATC_FLAGS_LD_SHIFT                                                 3
54553     #define CDU_REG_CCFC_PXP_RESERVED_4                                                              (0x3ff<<6) // Reserved Bits.
54554     #define CDU_REG_CCFC_PXP_RESERVED_4_SHIFT                                                        6
54555     #define CDU_REG_CCFC_PXP_CCFC_TPH_VALID                                                          (0x1<<16) // TPH Valid bit for CCFC PXP Requests.
54556     #define CDU_REG_CCFC_PXP_CCFC_TPH_VALID_SHIFT                                                    16
54557     #define CDU_REG_CCFC_PXP_CCFC_RO_LD                                                              (0x1<<17) // Relaxed ordering bit for CCFC PXP rd_req.
54558     #define CDU_REG_CCFC_PXP_CCFC_RO_LD_SHIFT                                                        17
54559     #define CDU_REG_CCFC_PXP_CCFC_RO_WB                                                              (0x1<<18) // Relaxed ordering bit for CCFC PXP wr_req.
54560     #define CDU_REG_CCFC_PXP_CCFC_RO_WB_SHIFT                                                        18
54561     #define CDU_REG_CCFC_PXP_CCFC_NS_LD                                                              (0x1<<19) // No snoop bit for CCFC PXP rd_req.
54562     #define CDU_REG_CCFC_PXP_CCFC_NS_LD_SHIFT                                                        19
54563     #define CDU_REG_CCFC_PXP_CCFC_NS_WB                                                              (0x1<<20) // No snoop bit for CCFC PXP wr_req.
54564     #define CDU_REG_CCFC_PXP_CCFC_NS_WB_SHIFT                                                        20
54565 #define CDU_REG_TCFC_PXP                                                                             0x580604UL //Access:RW   DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54566     #define CDU_REG_TCFC_PXP_TCFC_ATC_FLAGS_WB                                                       (0x7<<0) // ATC Flags Field for TCFC PXP Writes.
54567     #define CDU_REG_TCFC_PXP_TCFC_ATC_FLAGS_WB_SHIFT                                                 0
54568     #define CDU_REG_TCFC_PXP_TCFC_ATC_FLAGS_LD                                                       (0x7<<3) // ATC Flags Field for TCFC PXP Reads.
54569     #define CDU_REG_TCFC_PXP_TCFC_ATC_FLAGS_LD_SHIFT                                                 3
54570     #define CDU_REG_TCFC_PXP_RESERVED_5                                                              (0x3ff<<6) // Reserved Bits.
54571     #define CDU_REG_TCFC_PXP_RESERVED_5_SHIFT                                                        6
54572     #define CDU_REG_TCFC_PXP_TCFC_TPH_VALID                                                          (0x1<<16) // TPH Valid bit for TCFC PXP Requests.
54573     #define CDU_REG_TCFC_PXP_TCFC_TPH_VALID_SHIFT                                                    16
54574     #define CDU_REG_TCFC_PXP_TCFC_RO_LD                                                              (0x1<<17) // Relaxed ordering bit for TCFC working memory PXP rd_req.
54575     #define CDU_REG_TCFC_PXP_TCFC_RO_LD_SHIFT                                                        17
54576     #define CDU_REG_TCFC_PXP_TCFC_FL_RO_LD                                                           (0x1<<18) // Relaxed ordering bit for TCFC init memory PXP rd_req.
54577     #define CDU_REG_TCFC_PXP_TCFC_FL_RO_LD_SHIFT                                                     18
54578     #define CDU_REG_TCFC_PXP_TCFC_RO_WB                                                              (0x1<<19) // Relaxed ordering bit for TCFC working memory PXP wr_req.
54579     #define CDU_REG_TCFC_PXP_TCFC_RO_WB_SHIFT                                                        19
54580     #define CDU_REG_TCFC_PXP_TCFC_NS_LD                                                              (0x1<<20) // No snoop bit for TCFC working memory PXP rd_req.
54581     #define CDU_REG_TCFC_PXP_TCFC_NS_LD_SHIFT                                                        20
54582     #define CDU_REG_TCFC_PXP_TCFC_FL_NS_LD                                                           (0x1<<21) // No snoop bit for TCFC init memory PXP rd_req.
54583     #define CDU_REG_TCFC_PXP_TCFC_FL_NS_LD_SHIFT                                                     21
54584     #define CDU_REG_TCFC_PXP_TCFC_NS_WB                                                              (0x1<<22) // No snoop bit for TCFC working memory PXP wr_req.
54585     #define CDU_REG_TCFC_PXP_TCFC_NS_WB_SHIFT                                                        22
54586 #define CDU_REG_LD_VQID                                                                              0x580608UL //Access:RW   DataWidth:0x5   VQID used for PXP Read (Load) transactions.  Chips: BB_A0 BB_B0 K2
54587 #define CDU_REG_WB_VQID                                                                              0x58060cUL //Access:RW   DataWidth:0x5   VQID used for PXP Write (WriteBack) transactions.  Chips: BB_A0 BB_B0 K2
54588 #define CDU_REG_DEBUG                                                                                0x580700UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54589     #define CDU_REG_DEBUG_DISABLE_MERGE                                                              (0x1<<0) // Disables Merge Functionality.
54590     #define CDU_REG_DEBUG_DISABLE_MERGE_SHIFT                                                        0
54591     #define CDU_REG_DEBUG_RESERVED_1                                                                 (0x7fff<<1) // Reserved Bits.
54592     #define CDU_REG_DEBUG_RESERVED_1_SHIFT                                                           1
54593     #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT                                                          (0x3<<16) // PXP Read Request Credits.
54594     #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT_SHIFT                                                    16
54595     #define CDU_REG_DEBUG_RESERVED_2                                                                 (0x1f<<18) // Reserved Bits.
54596     #define CDU_REG_DEBUG_RESERVED_2_SHIFT                                                           18
54597     #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT_SET                                                      (0x1<<23) // Uses pxp_init_ldcredit to update PXP Read Credits.
54598     #define CDU_REG_DEBUG_PXP_INIT_LDCREDIT_SET_SHIFT                                                23
54599     #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT                                                          (0x3<<24) // PXP Write Request Credits.
54600     #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT_SHIFT                                                    24
54601     #define CDU_REG_DEBUG_RESERVED_3                                                                 (0x1f<<26) // Reserved Bits.
54602     #define CDU_REG_DEBUG_RESERVED_3_SHIFT                                                           26
54603     #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT_SET                                                      (0x1<<31) // Uses pxp_init_wbcredit to update PXP Write Credits.
54604     #define CDU_REG_DEBUG_PXP_INIT_WBCREDIT_SET_SHIFT                                                31
54605 #define CDU_REG_DBG_SELECT                                                                           0x580704UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
54606 #define CDU_REG_DBG_DWORD_ENABLE                                                                     0x580708UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
54607 #define CDU_REG_DBG_SHIFT                                                                            0x58070cUL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
54608 #define CDU_REG_DBG_FORCE_VALID                                                                      0x580710UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
54609 #define CDU_REG_DBG_FORCE_FRAME                                                                      0x580714UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
54610 #define CDU_REG_DBG_OUT_DATA                                                                         0x580720UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
54611 #define CDU_REG_DBG_OUT_DATA_SIZE                                                                    8
54612 #define CDU_REG_DBG_OUT_VALID                                                                        0x580740UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
54613 #define CDU_REG_DBG_OUT_FRAME                                                                        0x580744UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
54614 #define CDU_REG_ECO_RESERVED                                                                         0x580748UL //Access:RW   DataWidth:0x8   Eco reserved register.  Chips: BB_A0 BB_B0 K2
54615 #define CDU_REG_MEMCTRL_WR_RD_N                                                                      0x58074cUL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
54616 #define CDU_REG_MEMCTRL_CMD                                                                          0x580750UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
54617 #define CDU_REG_MEMCTRL_ADDRESS                                                                      0x580754UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
54618 #define CDU_REG_MEMCTRL_STATUS                                                                       0x580758UL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0
54619 #define CDU_REG_CCFC_CVLD_ERROR_DATA                                                                 0x580800UL //Access:R    DataWidth:0x19  CCFC Context Validation Error Data. [24:16] LCID of Error Transaction [14:8]  Expected Compressed Context [6:0]   Received Compressed Context  Chips: BB_A0 BB_B0 K2
54620 #define CDU_REG_TCFC_CVLD_ERROR_DATA                                                                 0x580804UL //Access:R    DataWidth:0x19  TCFC Context Validation Error Data. [24:16] LCID of Error Transaction [14:8]  Expected Compressed Context [6:0]   Received Compressed Context  Chips: BB_A0 BB_B0 K2
54621 #define CDU_REG_CCFC_LD_L1_NUM_ERROR_DATA                                                            0x580808UL //Access:R    DataWidth:0x19  Logging of error data in case of a CCFC Load error. [24:16]  LCID [11:8]   Type [7:0]    Regions  Chips: BB_A0 BB_B0 K2
54622 #define CDU_REG_TCFC_LD_L1_NUM_ERROR_DATA                                                            0x58080cUL //Access:R    DataWidth:0x19  Logging of error data in case of a TCFC Load error. [24:16]  LCID [11:8]   Type [7:0]    Regions  Chips: BB_A0 BB_B0 K2
54623 #define CDU_REG_CCFC_WB_L1_NUM_ERROR_DATA                                                            0x580810UL //Access:R    DataWidth:0x19  Logging of error data in case of a CCFC Writeback Error. [24:16]  LCID [11:8]   Type [7:0]    Regions  Chips: BB_A0 BB_B0 K2
54624 #define CDU_REG_TCFC_WB_L1_NUM_ERROR_DATA                                                            0x580814UL //Access:R    DataWidth:0x19  Logging of error data in case of a TCFC Writeback Error. [24:16]  LCID [11:8]   Type [7:0]    Regions  Chips: BB_A0 BB_B0 K2
54625 #define CDU_REG_CID_ADDR_PARAMS                                                                      0x580900UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54626     #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE                                                     (0xfff<<0) // Global context size of a CID.
54627     #define CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT                                               0
54628     #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE                                                      (0xfff<<12) // Block waste within a page. this number equals to PageSize-NCIB*ContextSize.
54629     #define CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT                                                12
54630     #define CDU_REG_CID_ADDR_PARAMS_NCIB                                                             (0xff<<24) // Number of CIDs in Block.
54631     #define CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT                                                       24
54632 #define CDU_REG_SEGMENT0_PARAMS                                                                      0x580904UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54633     #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK                                             (0xfff<<0) // Number of TIDs per Block for this Segment (Type0).
54634     #define CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT                                       0
54635     #define CDU_REG_SEGMENT0_PARAMS_RESERVED_6                                                       (0xf<<12) // Reserved Bits.
54636     #define CDU_REG_SEGMENT0_PARAMS_RESERVED_6_SHIFT                                                 12
54637     #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE                                               (0xff<<16) // Number of Waste locations per TID Block (in Qwords) (Type0).
54638     #define CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT                                         16
54639     #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE                                                      (0xff<<24) // Size of TID (in Qwords) (Type0).
54640     #define CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT                                                24
54641 #define CDU_REG_SEGMENT1_PARAMS                                                                      0x580908UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
54642     #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK                                             (0xfff<<0) // Number of TIDs per Block for this Segment (Type1).
54643     #define CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT                                       0
54644     #define CDU_REG_SEGMENT1_PARAMS_RESERVED_7                                                       (0xf<<12) // Reserved Bits.
54645     #define CDU_REG_SEGMENT1_PARAMS_RESERVED_7_SHIFT                                                 12
54646     #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE                                               (0xff<<16) // Number of Waste locations per TID Block (in Qwords) (Type1).
54647     #define CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT                                         16
54648     #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE                                                      (0xff<<24) // Size of TID (in Qwords) (Type1).
54649     #define CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT                                                24
54650 #define CDU_REG_PF_SEG0_TYPE_OFFSET                                                                  0x58090cUL //Access:RW   DataWidth:0x12  Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54651 #define CDU_REG_PF_SEG1_TYPE_OFFSET                                                                  0x580910UL //Access:RW   DataWidth:0x12  Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54652 #define CDU_REG_PF_SEG2_TYPE_OFFSET                                                                  0x580914UL //Access:RW   DataWidth:0x12  Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54653 #define CDU_REG_PF_SEG3_TYPE_OFFSET                                                                  0x580918UL //Access:RW   DataWidth:0x12  Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54654 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET                                                               0x58091cUL //Access:RW   DataWidth:0x12  Force Load Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54655 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET                                                               0x580920UL //Access:RW   DataWidth:0x12  Force Load Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54656 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET                                                               0x580924UL //Access:RW   DataWidth:0x12  Force Load Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54657 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET                                                               0x580928UL //Access:RW   DataWidth:0x12  Force Load Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54658 #define CDU_REG_VF_SEG_TYPE_OFFSET                                                                   0x58092cUL //Access:RW   DataWidth:0x12  VF Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54659 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET                                                                0x580930UL //Access:RW   DataWidth:0xd   VF Force Load Start Offset for this Segment (in 32KB pages).  Chips: BB_A0 BB_B0 K2
54660 #define CDU_REG_CCFC_L1TT                                                                            0x581000UL //Access:WB   DataWidth:0x110 L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*[4:0]}.  Chips: BB_A0 BB_B0 K2
54661 #define CDU_REG_CCFC_L1TT_SIZE                                                                       1024
54662 #define CDU_REG_TCFC_L1TT                                                                            0x582000UL //Access:WB   DataWidth:0x110 L1TT Access; Each entry has the following format: {Offset - 16*[5:0]; Length - 16*[5:0]; ID - 16*[4:0]}.  Chips: BB_A0 BB_B0 K2
54663 #define CDU_REG_TCFC_L1TT_SIZE                                                                       1024
54664 #define CDU_REG_CCFC_MATT                                                                            0x583000UL //Access:WB   DataWidth:0x18  MATT Access; Each entry has the following format: {RegionLength[11:0]; RegionOffset[11:0]}.  Chips: BB_A0 BB_B0 K2
54665 #define CDU_REG_CCFC_MATT_SIZE                                                                       64
54666 #define CDU_REG_TCFC_MATT                                                                            0x583100UL //Access:WB   DataWidth:0x18  MATT Access; Each entry has the following format: {RegionLength[11:0]; RegionOffset[11:0]}.  Chips: BB_A0 BB_B0 K2
54667 #define CDU_REG_TCFC_MATT_SIZE                                                                       64
54668 #define CDU_REG_TCFC_FL_MATT                                                                         0x583200UL //Access:WB   DataWidth:0x18  MATT Access; Each entry has the following format: {RegionLength[11:0]; RegionOffset[11:0]}.  Chips: BB_A0 BB_B0 K2
54669 #define CDU_REG_TCFC_FL_MATT_SIZE                                                                    64
54670 #define WOL_REG_INT_STS_0                                                                            0x600040UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: K2
54671     #define WOL_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the RF module.
54672     #define WOL_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
54673 #define WOL_REG_INT_MASK_0                                                                           0x600044UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: K2
54674     #define WOL_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: WOL_REG_INT_STS_0.ADDRESS_ERROR .
54675     #define WOL_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
54676 #define WOL_REG_INT_STS_WR_0                                                                         0x600048UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: K2
54677     #define WOL_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the RF module.
54678     #define WOL_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
54679 #define WOL_REG_INT_STS_CLR_0                                                                        0x60004cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: K2
54680     #define WOL_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the RF module.
54681     #define WOL_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
54682 #define WOL_REG_DBG_SELECT                                                                           0x600140UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
54683 #define WOL_REG_DBG_DWORD_ENABLE                                                                     0x600144UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
54684 #define WOL_REG_DBG_SHIFT                                                                            0x600148UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
54685 #define WOL_REG_DBG_FORCE_VALID                                                                      0x60014cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
54686 #define WOL_REG_DBG_FORCE_FRAME                                                                      0x600150UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
54687 #define WOL_REG_DBG_OUT_DATA                                                                         0x600160UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
54688 #define WOL_REG_DBG_OUT_DATA_SIZE                                                                    8
54689 #define WOL_REG_DBG_OUT_VALID                                                                        0x600180UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
54690 #define WOL_REG_DBG_OUT_FRAME                                                                        0x600184UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
54691 #define WOL_REG_PRTY_MASK_H_0                                                                        0x600204UL //Access:RW   DataWidth:0x18  Multi Field Register.  Chips: K2
54692     #define WOL_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
54693     #define WOL_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_SHIFT                                            0
54694     #define WOL_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
54695     #define WOL_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_SHIFT                                            1
54696     #define WOL_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
54697     #define WOL_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_SHIFT                                            2
54698     #define WOL_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
54699     #define WOL_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_SHIFT                                            3
54700     #define WOL_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
54701     #define WOL_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                            4
54702     #define WOL_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
54703     #define WOL_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_SHIFT                                            5
54704     #define WOL_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
54705     #define WOL_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_SHIFT                                            6
54706     #define WOL_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
54707     #define WOL_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                            7
54708     #define WOL_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
54709     #define WOL_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            8
54710     #define WOL_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
54711     #define WOL_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                            9
54712     #define WOL_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
54713     #define WOL_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                            10
54714     #define WOL_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
54715     #define WOL_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                            11
54716     #define WOL_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
54717     #define WOL_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                            12
54718     #define WOL_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
54719     #define WOL_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                            13
54720     #define WOL_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
54721     #define WOL_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                            14
54722     #define WOL_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
54723     #define WOL_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT                                            15
54724     #define WOL_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
54725     #define WOL_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_SHIFT                                            16
54726     #define WOL_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
54727     #define WOL_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_SHIFT                                            17
54728     #define WOL_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
54729     #define WOL_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            18
54730     #define WOL_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
54731     #define WOL_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            19
54732     #define WOL_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
54733     #define WOL_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            20
54734     #define WOL_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
54735     #define WOL_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                            21
54736     #define WOL_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
54737     #define WOL_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                            22
54738     #define WOL_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: WOL_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
54739     #define WOL_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                            23
54740 #define WOL_REG_MEM_ECC_EVENTS                                                                       0x600210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
54741 #define WOL_REG_MEM017_I_MEM_DFT                                                                     0x600218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.HEADER_MEM[0].i_wol_hdr_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54742 #define WOL_REG_MEM018_I_MEM_DFT                                                                     0x60021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.HEADER_MEM[1].i_wol_hdr_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54743 #define WOL_REG_MEM019_I_MEM_DFT                                                                     0x600220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.HEADER_MEM[2].i_wol_hdr_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54744 #define WOL_REG_MEM020_I_MEM_DFT                                                                     0x600224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.HEADER_MEM[3].i_wol_hdr_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
54745 #define WOL_REG_MEM021_I_MEM_DFT                                                                     0x600228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.WAKE_MEM[0].i_wol_wake_buffer.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54746 #define WOL_REG_MEM022_I_MEM_DFT                                                                     0x60022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.WAKE_MEM[1].i_wol_wake_buffer.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54747 #define WOL_REG_MEM023_I_MEM_DFT                                                                     0x600230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.WAKE_MEM[2].i_wol_wake_buffer.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54748 #define WOL_REG_MEM024_I_MEM_DFT                                                                     0x600234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.WAKE_MEM[3].i_wol_wake_buffer.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54749 #define WOL_REG_MEM001_I_MEM_DFT                                                                     0x600238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[0].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54750 #define WOL_REG_MEM008_I_MEM_DFT                                                                     0x60023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[1].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54751 #define WOL_REG_MEM009_I_MEM_DFT                                                                     0x600240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[2].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54752 #define WOL_REG_MEM010_I_MEM_DFT                                                                     0x600244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[3].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54753 #define WOL_REG_MEM011_I_MEM_DFT                                                                     0x600248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[4].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54754 #define WOL_REG_MEM012_I_MEM_DFT                                                                     0x60024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[5].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54755 #define WOL_REG_MEM013_I_MEM_DFT                                                                     0x600250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[6].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54756 #define WOL_REG_MEM014_I_MEM_DFT                                                                     0x600254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[7].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54757 #define WOL_REG_MEM015_I_MEM_DFT                                                                     0x600258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[8].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54758 #define WOL_REG_MEM016_I_MEM_DFT                                                                     0x60025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[9].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54759 #define WOL_REG_MEM002_I_MEM_DFT                                                                     0x600260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[10].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54760 #define WOL_REG_MEM003_I_MEM_DFT                                                                     0x600264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[11].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54761 #define WOL_REG_MEM004_I_MEM_DFT                                                                     0x600268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[12].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54762 #define WOL_REG_MEM005_I_MEM_DFT                                                                     0x60026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[13].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54763 #define WOL_REG_MEM006_I_MEM_DFT                                                                     0x600270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[14].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54764 #define WOL_REG_MEM007_I_MEM_DFT                                                                     0x600274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance wol.ACPI_MEM_256[15].i_wol_acpi_bemem.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
54765 #define WOL_REG_ACPI_TAG_RM                                                                          0x608000UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  L2 tag removal configuration for ACPI.  Bit mapped as follow: bit 0: 5 - L2 tags 0 to 5. Bit 6 is reserved and should be set to 0.  Bit 7 is for LLC/SNAP.  Set these bits to 1's to enable the removal of the corresponding tag when it is present in the  packet.  Clear the bit to keep the tag in the  packet.  Chips: K2
54766 #define WOL_REG_UPON_MGMT                                                                            0x608004UL //Access:RW   DataWidth:0x1   Set this bit to enable ACPI and TCP SYN matching even when the packet is forwarded to MCP.  Clear this bit to disable ACPI and TCP SYN matching when the packet is forwarded to MCP.  Chips: K2
54767 #define WOL_REG_ACPI_BE_MEM                                                                          0x608080UL //Access:WB   DataWidth:0x100 This is a per-port per-PF register.  Byte enable memory for 8 ACPI patterns.  Chips: K2
54768 #define WOL_REG_ACPI_BE_MEM_SIZE                                                                     32
54769 #define WOL_REG_ACPI_ENABLE                                                                          0x608100UL //Access:RW   DataWidth:0x1   This is a per-port register.  When this bit is set  ACPI packet recognition will be enabled. This bit must not be enabled until after all other ACPI registers were configured.  Chips: K2
54770 #define WOL_REG_ACPI_PAT_0_CRC                                                                       0x608104UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 0.  Chips: K2
54771 #define WOL_REG_ACPI_PAT_0_LEN                                                                       0x608108UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: K2
54772 #define WOL_REG_ACPI_PAT_1_CRC                                                                       0x60810cUL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 1.  Chips: K2
54773 #define WOL_REG_ACPI_PAT_1_LEN                                                                       0x608110UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: K2
54774 #define WOL_REG_ACPI_PAT_2_CRC                                                                       0x608114UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 2.  Chips: K2
54775 #define WOL_REG_ACPI_PAT_2_LEN                                                                       0x608118UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: K2
54776 #define WOL_REG_ACPI_PAT_3_CRC                                                                       0x60811cUL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 3.  Chips: K2
54777 #define WOL_REG_ACPI_PAT_3_LEN                                                                       0x608120UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: K2
54778 #define WOL_REG_ACPI_PAT_4_CRC                                                                       0x608124UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 4.  Chips: K2
54779 #define WOL_REG_ACPI_PAT_4_LEN                                                                       0x608128UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: K2
54780 #define WOL_REG_ACPI_PAT_5_CRC                                                                       0x60812cUL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 5.  Chips: K2
54781 #define WOL_REG_ACPI_PAT_5_LEN                                                                       0x608130UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: K2
54782 #define WOL_REG_ACPI_PAT_6_CRC                                                                       0x608134UL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 6.  Chips: K2
54783 #define WOL_REG_ACPI_PAT_6_LEN                                                                       0x608138UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: K2
54784 #define WOL_REG_ACPI_PAT_7_CRC                                                                       0x60813cUL //Access:RW   DataWidth:0x20  This is a per-port per-PF register.  CRC32C for pattern 7.  Chips: K2
54785 #define WOL_REG_ACPI_PAT_7_LEN                                                                       0x608140UL //Access:RW   DataWidth:0x8   This is a per-port per-PF register.  Length of ACPI Pattern, in bytes.  Length must be multiples of 4 bytes.  Chips: K2
54786 #define WOL_REG_MPKT_ENABLE                                                                          0x608144UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  When this bit is set  Magic Packet recognition will be enabled. This bit must not be enabled until after after all other Magic Packet registers are configured.  Chips: K2
54787 #define WOL_REG_MPKT_MAC_ADDR                                                                        0x608148UL //Access:WB   DataWidth:0x30  This is a per-port per-PF register.  MAC address for Magic Packet detection.  Chips: K2
54788 #define WOL_REG_MPKT_MAC_ADDR_SIZE                                                                   2
54789 #define WOL_REG_FORCE_WOL                                                                            0x608150UL //Access:RW   DataWidth:0x1   This is a per-port per-PF register.  A low-to-high transition of this bit forces a wake event.  Chips: K2
54790 #define WOL_REG_WAKE_BUFFER                                                                          0x608160UL //Access:WB_R DataWidth:0x100 Read-only data from the Wake Buffer (organized as a FIFO).  Chips: K2
54791 #define WOL_REG_WAKE_BUFFER_SIZE                                                                     8
54792 #define WOL_REG_WAKE_BUFFER_CLEAR                                                                    0x608180UL //Access:RW   DataWidth:0x1   Clear the Wake Buffer and Status - a low-to-high transition of this bit clears the wake_info, wake_pkt_len, and wake_details registers and allows the wake buffer to be overwritten, thereby re-enabling pattern detection.  Chips: K2
54793 #define WOL_REG_WAKE_INFO                                                                            0x608184UL //Access:R    DataWidth:0x15  Wake information register - all fields are sticky.  Bits  15:0 - PF Vector: The bit-mapped vector indicating which of the global PFs detected the wake event.  More than 1 bit may be set. Bit 16 - ACPI RCVD:  This bit is set when an ACPI packet is received. This is an OR of the results from the 8 functions. Bit 17 - MPKT:  This bit is set when a Magic packet is received. This is an OR of the results from the 8 functions. Bit 18 - TCP SYN RCVD:  This bit is set when TCP SYN packet is received. This is an OR of the results from the 8 functions. Bit 19 - FORCE RCVD:  This bit is set when force WOL event is received. This is an OR of the results from the 8 functions. Bit 20 - BUFFER NOT EMPTY:  This bit  is set when the buffer has the 'wake' packet. All fields are cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on these fields.  Chips: K2
54794 #define WOL_REG_WAKE_PKT_LEN                                                                         0x608188UL //Access:R    DataWidth:0xe   Wake packet length - the actual length of the 'wake' packet, in bytes. This register is sticky and is cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on this register.  Chips: K2
54795 #define WOL_REG_WAKE_DETAILS                                                                         0x60818cUL //Access:R    DataWidth:0x20  Wake detail register - all fields are sticky.  Bits 7:0   - ACPI MATCH:  Per-function bit-mapped result from ACPI pattern match. Bits 15:8  - MPKT MATCH:  Per-function bit-mapped result from Magic packet pattern match. Bits 23:16 - TCP SYN MATCH:  Per-function bit-mapped result from TCP SYN match. Bits 31:24 - FORCE WOL MATCH:  Per-function bit-mapped result from force WOL match. All fields are cleared by wake_buffer_clear or during a Hard Reset only. Core Reset has no effect on these fields.  Chips: K2
54796 #define WOL_REG_ACPI_DEFAULT_PF_SEL                                                                  0x608190UL //Access:RW   DataWidth:0x3   This bit selects the default PF for selecting the ACPI patterns.  Chips: K2
54797 #define WOL_REG_ACPI_PAT_SEL                                                                         0x608194UL //Access:RW   DataWidth:0x2   These two bits select which pattern will be chosen for the ACPI CRC matching: 0: Select patterns based on LLH PF classification. 1: Select patterns based on static PF selection - acpi_default_pf_sel. 2: Select the first of each: 2 ports (quad_port_mode is 0) - use one of each PF. 4 ports (quad_port_mode is 1) - use two of each PF. 3: reserved.  Chips: K2
54798 #define WOL_REG_TCP_SYN_ENABLE                                                                       0x608198UL //Access:RW   DataWidth:0x2   This is a per-PF register.  Set bit 0 to enable wake on IPv4 TCP SYN. Set bit 1 to enable wake on IPv6 TCP SYN. These bits must not be set until after after all other registers needed for this feature are configured.  Chips: K2
54799 #define WOL_REG_TAG_LEN_0                                                                            0x60819cUL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: K2
54800 #define WOL_REG_TAG_LEN_1                                                                            0x6081a0UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: K2
54801 #define WOL_REG_TAG_LEN_2                                                                            0x6081a4UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: K2
54802 #define WOL_REG_TAG_LEN_3                                                                            0x6081a8UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: K2
54803 #define WOL_REG_TAG_LEN_4                                                                            0x6081acUL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: K2
54804 #define WOL_REG_TAG_LEN_5                                                                            0x6081b0UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: K2
54805 #define WOL_REG_WAKE_MEM_RD_OFFSET                                                                   0x6081b4UL //Access:R    DataWidth:0x3   This is the current offset of the read pointer in the wake buffer.  Chips: K2
54806 #define WOL_REG_ECO_RESERVED                                                                         0x6081b8UL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: K2
54807 #define WOL_REG_ECO_RESERVED_PERPORT                                                                 0x6081bcUL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: K2
54808 #define WOL_REG_HDR_FIFO_EMPTY                                                                       0x6081c0UL //Access:R    DataWidth:0x1   WOL header FIFO empty status.  Chips: K2
54809 #define WOL_REG_HDR_FIFO_FULL                                                                        0x6081c4UL //Access:R    DataWidth:0x1   WOL header FIFO full status.  Chips: K2
54810 #define WOL_REG_HDR_FIFO_ERROR                                                                       0x6081c8UL //Access:R    DataWidth:0x1   WOL header FIFO error status.  Chips: K2
54811 #define BMBN_REG_INT_STS_0                                                                           0x610040UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: K2
54812     #define BMBN_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the RF module.
54813     #define BMBN_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
54814 #define BMBN_REG_INT_MASK_0                                                                          0x610044UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: K2
54815     #define BMBN_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: BMBN_REG_INT_STS_0.ADDRESS_ERROR .
54816     #define BMBN_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
54817 #define BMBN_REG_INT_STS_WR_0                                                                        0x610048UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: K2
54818     #define BMBN_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the RF module.
54819     #define BMBN_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
54820 #define BMBN_REG_INT_STS_CLR_0                                                                       0x61004cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: K2
54821     #define BMBN_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the RF module.
54822     #define BMBN_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
54823 #define BMBN_REG_DBG_SELECT                                                                          0x610140UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
54824 #define BMBN_REG_DBG_DWORD_ENABLE                                                                    0x610144UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
54825 #define BMBN_REG_DBG_SHIFT                                                                           0x610148UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
54826 #define BMBN_REG_DBG_FORCE_VALID                                                                     0x61014cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
54827 #define BMBN_REG_DBG_FORCE_FRAME                                                                     0x610150UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
54828 #define BMBN_REG_DBG_OUT_DATA                                                                        0x610160UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
54829 #define BMBN_REG_DBG_OUT_DATA_SIZE                                                                   8
54830 #define BMBN_REG_DBG_OUT_VALID                                                                       0x610180UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
54831 #define BMBN_REG_DBG_OUT_FRAME                                                                       0x610184UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
54832 #define BMBN_REG_MNG_OUTER_TAG0_0                                                                    0x6101e0UL //Access:RW   DataWidth:0x20  Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: K2
54833 #define BMBN_REG_MNG_OUTER_TAG0_1                                                                    0x6101e4UL //Access:RW   DataWidth:0x20  Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: K2
54834 #define BMBN_REG_MNG_OUTER_TAG1_0                                                                    0x6101e8UL //Access:RW   DataWidth:0x20  Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: K2
54835 #define BMBN_REG_MNG_OUTER_TAG1_1                                                                    0x6101ecUL //Access:RW   DataWidth:0x20  Value of outer tag to be inserted into the management packets.  The tag value should have the MSB aligned with the MSB of this register.  Chips: K2
54836 #define BMBN_REG_MNG_INNER_VLAN_TAG0                                                                 0x6101f0UL //Access:RW   DataWidth:0x10  Value of inner VLAN tag to be used in tag insertion/override for management packets.  This field consists of {3-bit priority, 1-bit drop eligible, 12-bit VLAN ID}.  Chips: K2
54837 #define BMBN_REG_MNG_INNER_VLAN_TAG1                                                                 0x6101f4UL //Access:RW   DataWidth:0x10  Value of inner VLAN tag to be used in tag insertion/override for management packets.  This field consists of {3-bit priority, 1-bit drop eligible, 12-bit VLAN ID}.  Chips: K2
54838 #define BMBN_REG_TAG_LEN_0                                                                           0x6101f8UL //Access:RW   DataWidth:0x3   The length, in 2-byte granularity, of the info field for the L2 tag.  Valid values are 1 to 7.  This length does not include the Ethertype field.  Chips: K2
54839 #define BMBN_REG_TAG_ETHERTYPE_1                                                                     0x6101fcUL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 1.  The reset value is 9x8100 for inner VLAN.  Chips: K2
54840 #define BMBN_REG_ECO_RESERVED                                                                        0x610200UL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: K2
54841 #define BMBN_REG_ECO_RESERVED_PERPORT                                                                0x610204UL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: K2
54842 #define PHY_PCIE_REG_PHY0                                                                            0x620000UL //Access:RW   DataWidth:0x10  AHB bus for pcie_phy 0.  Chips: K2
54843 #define PHY_PCIE_REG_PHY0_SIZE                                                                       4096
54844 #define PHY_PCIE_REG_PHY1                                                                            0x624000UL //Access:RW   DataWidth:0x10  AHB bus for pcie_phy 1.  Chips: K2
54845 #define PHY_PCIE_REG_PHY1_SIZE                                                                       4096
54846 #define PHY_PCIE_REG_ECO_RESERVED                                                                    0x628000UL //Access:RW   DataWidth:0x20    Chips: K2
54847 #define PHY_PCIE_REG_PHY_REFCLK_SELECT                                                               0x628004UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: K2
54848     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_INPUT_SEL_I                               (0x3<<0) //
54849     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_INPUT_SEL_I_SHIFT                         0
54850     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_L_I                                    (0x1<<2) //
54851     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_L_I_SHIFT                              2
54852     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_L_I                                  (0x1<<3) //
54853     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_L_I_SHIFT                            3
54854     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_R_I                                    (0x1<<4) //
54855     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_OE_R_I_SHIFT                              4
54856     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_R_I                                  (0x1<<5) //
54857     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_QFWD_R_I_SHIFT                            5
54858     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_SEL_I                                     (0x1<<6) //
54859     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY0_CMU_REFCLK_SEL_I_SHIFT                               6
54860     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_INPUT_SEL_I                               (0x3<<7) //
54861     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_INPUT_SEL_I_SHIFT                         7
54862     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_L_I                                    (0x1<<9) //
54863     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_L_I_SHIFT                              9
54864     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_L_I                                  (0x1<<10) //
54865     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_L_I_SHIFT                            10
54866     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_R_I                                    (0x1<<11) //
54867     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_OE_R_I_SHIFT                              11
54868     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_R_I                                  (0x1<<12) //
54869     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_QFWD_R_I_SHIFT                            12
54870     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_SEL_I                                     (0x1<<13) //
54871     #define PHY_PCIE_REG_PHY_REFCLK_SELECT_PHY1_CMU_REFCLK_SEL_I_SHIFT                               13
54872 #define PHY_PCIE_REG_PHY_REFCLK_CONTROL                                                              0x628008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
54873     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_CMU_CK_SOC_DIV_I                                         (0x3<<0) //
54874     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_CMU_CK_SOC_DIV_I_SHIFT                                   0
54875     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_PD_I                                            (0x1<<2) //
54876     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_PD_I_SHIFT                                      2
54877     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_PD_I                                            (0x1<<3) //
54878     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_PD_I_SHIFT                                      3
54879     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_IDDQ_I                                          (0x1<<4) //
54880     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_CMU_IDDQ_I_SHIFT                                    4
54881     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_IDDQ_I                                          (0x1<<5) //
54882     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_CMU_IDDQ_I_SHIFT                                    5
54883     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_REFCLK_GATE_I                                       (0x1<<6) //
54884     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY0_REFCLK_GATE_I_SHIFT                                 6
54885     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_REFCLK_GATE_I                                       (0x1<<7) //
54886     #define PHY_PCIE_REG_PHY_REFCLK_CONTROL_PHY1_REFCLK_GATE_I_SHIFT                                 7
54887 #define PHY_PCIE_REG_SOFT_RESET_CONTROL                                                              0x62800cUL //Access:RW   DataWidth:0x2   Multi Field Register.  Chips: K2
54888     #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PWR_RST_N                                           (0x1<<0) //
54889     #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PWR_RST_N_SHIFT                                     0
54890     #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PHY_RST_N                                           (0x1<<1) //
54891     #define PHY_PCIE_REG_SOFT_RESET_CONTROL_SOFT_PHY_RST_N_SHIFT                                     1
54892 #define PHY_PCIE_REG_PHY_RESET_CONTROL                                                               0x628010UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: K2
54893     #define PHY_PCIE_REG_PHY_RESET_CONTROL_LNX_RSTN_I                                                (0xff<<0) // Firmware must set this bit to 1 after finished configuring PCIe Serdes AHB registers to bring Serdes channel out of reset
54894     #define PHY_PCIE_REG_PHY_RESET_CONTROL_LNX_RSTN_I_SHIFT                                          0
54895     #define PHY_PCIE_REG_PHY_RESET_CONTROL_CMU_RESETN_I                                              (0x1<<8) // Firmware must set this bit to 1 after finished configuring PCIe Serdes AHB registers to bring Serdes CMU out of reset
54896     #define PHY_PCIE_REG_PHY_RESET_CONTROL_CMU_RESETN_I_SHIFT                                        8
54897 #define PHY_PCIE_REG_PHY_STATUS                                                                      0x628014UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: K2
54898     #define PHY_PCIE_REG_PHY_STATUS_PHY0_CMU_OK_O                                                    (0x1<<0) //
54899     #define PHY_PCIE_REG_PHY_STATUS_PHY0_CMU_OK_O_SHIFT                                              0
54900     #define PHY_PCIE_REG_PHY_STATUS_PHY1_CMU_OK_O                                                    (0x1<<1) //
54901     #define PHY_PCIE_REG_PHY_STATUS_PHY1_CMU_OK_O_SHIFT                                              1
54902     #define PHY_PCIE_REG_PHY_STATUS_PHY0_REFCLK_GATE_ACK_O                                           (0x1<<2) //
54903     #define PHY_PCIE_REG_PHY_STATUS_PHY0_REFCLK_GATE_ACK_O_SHIFT                                     2
54904     #define PHY_PCIE_REG_PHY_STATUS_PHY1_REFCLK_GATE_ACK_O                                           (0x1<<3) //
54905     #define PHY_PCIE_REG_PHY_STATUS_PHY1_REFCLK_GATE_ACK_O_SHIFT                                     3
54906     #define PHY_PCIE_REG_PHY_STATUS_PHY_MAC_PHYSTATUS                                                (0xff<<4) //
54907     #define PHY_PCIE_REG_PHY_STATUS_PHY_MAC_PHYSTATUS_SHIFT                                          4
54908 #define PHY_PCIE_REG_EII_STATUS_BUS_MASK_I                                                           0x628018UL //Access:RW   DataWidth:0x10  Bit masks to be ANDed with cxpl_debug_info_ei[15:0] to control glue_mac_init_info_i[15:0] of PCIe PHY  Chips: K2
54909 #define PHY_PCIE_REG_PCS_CONTROL_2                                                                   0x62801cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: K2
54910     #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXSIG_DET_MASK_I                                          (0xff<<0) //
54911     #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXSIG_DET_MASK_I_SHIFT                                    0
54912     #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXEII_EXIT_TYPE_I                                         (0xff<<8) //
54913     #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXEII_EXIT_TYPE_I_SHIFT                                   8
54914     #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXEI_INFER_I                                              (0xff<<16) //
54915     #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_RXEI_INFER_I_SHIFT                                        16
54916     #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_IDDQ_I                                                    (0xff<<24) //
54917     #define PHY_PCIE_REG_PCS_CONTROL_2_LNX_IDDQ_I_SHIFT                                              24
54918 #define PHY_PCIE_REG_PCIE_PHY0_ASTAT                                                                 0x628020UL //Access:R    DataWidth:0x18  Multi Field Register.  Chips: K2
54919     #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN0_ASTAT_O                                                 (0x3f<<0) //
54920     #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN0_ASTAT_O_SHIFT                                           0
54921     #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN1_ASTAT_O                                                 (0x3f<<6) //
54922     #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN1_ASTAT_O_SHIFT                                           6
54923     #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN2_ASTAT_O                                                 (0x3f<<12) //
54924     #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN2_ASTAT_O_SHIFT                                           12
54925     #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN3_ASTAT_O                                                 (0x3f<<18) //
54926     #define PHY_PCIE_REG_PCIE_PHY0_ASTAT_LN3_ASTAT_O_SHIFT                                           18
54927 #define PHY_PCIE_REG_PCIE_PHY1_ASTAT                                                                 0x628024UL //Access:R    DataWidth:0x18  Multi Field Register.  Chips: K2
54928     #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN4_ASTAT_O                                                 (0x3f<<0) //
54929     #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN4_ASTAT_O_SHIFT                                           0
54930     #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN5_ASTAT_O                                                 (0x3f<<6) //
54931     #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN5_ASTAT_O_SHIFT                                           6
54932     #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN6_ASTAT_O                                                 (0x3f<<12) //
54933     #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN6_ASTAT_O_SHIFT                                           12
54934     #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN7_ASTAT_O                                                 (0x3f<<18) //
54935     #define PHY_PCIE_REG_PCIE_PHY1_ASTAT_LN7_ASTAT_O_SHIFT                                           18
54936 #define PHY_PCIE_REG_HW_INIT_CONFIG                                                                  0x628028UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: K2
54937     #define PHY_PCIE_REG_HW_INIT_CONFIG_FIRMWARE_EXIST                                               (0x1<<0) // When set to 1, represents FW exists
54938     #define PHY_PCIE_REG_HW_INIT_CONFIG_FIRMWARE_EXIST_SHIFT                                         0
54939     #define PHY_PCIE_REG_HW_INIT_CONFIG_CMU_RESET_OVR                                                (0x1<<1) // When set to 0, HWInit controls cmu_reset
54940     #define PHY_PCIE_REG_HW_INIT_CONFIG_CMU_RESET_OVR_SHIFT                                          1
54941     #define PHY_PCIE_REG_HW_INIT_CONFIG_LN_RESET_OVR                                                 (0x1<<2) // When set to 0, HWInit controls ln_reset
54942     #define PHY_PCIE_REG_HW_INIT_CONFIG_LN_RESET_OVR_SHIFT                                           2
54943 #define PHY_PCIE_REG_DBGSYN_STATUS                                                                   0x62802cUL //Access:R    DataWidth:0x5     Chips: K2
54944 #define PHY_PCIE_REG_DBG_OUT_DATA                                                                    0x629fc0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
54945 #define PHY_PCIE_REG_DBG_OUT_DATA_SIZE                                                               8
54946 #define PHY_PCIE_REG_DBG_OUT_VALID                                                                   0x629fe0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
54947 #define PHY_PCIE_REG_DBG_OUT_FRAME                                                                   0x629fe4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
54948 #define PHY_PCIE_REG_DBG_SELECT                                                                      0x629fe8UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
54949 #define PHY_PCIE_REG_DBG_DWORD_ENABLE                                                                0x629fecUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
54950 #define PHY_PCIE_REG_DBG_SHIFT                                                                       0x629ff0UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
54951 #define PHY_PCIE_REG_DBG_FORCE_VALID                                                                 0x629ff4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
54952 #define PHY_PCIE_REG_DBG_FORCE_FRAME                                                                 0x629ff8UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
54953 #define MS_REG_COMMON_CONTROL                                                                        0x6a0000UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: K2
54954     #define MS_REG_COMMON_CONTROL_POR_N_I                                                            (0x1<<0) // Controls por_n_i reset signal into the SerDes. This should be 0 (Reset value) write 1 to this bit to allow the SerDes to begin normal Operation.
54955     #define MS_REG_COMMON_CONTROL_POR_N_I_SHIFT                                                      0
54956     #define MS_REG_COMMON_CONTROL_CMU_RESETN_I                                                       (0x1<<1) // Active low. Can be asserted on CMU0 in multiple CMU PHYs to save power if TX clock is being supplied by CMU1 and there are active lanes.
54957     #define MS_REG_COMMON_CONTROL_CMU_RESETN_I_SHIFT                                                 1
54958     #define MS_REG_COMMON_CONTROL_CMU_PD_I                                                           (0x1<<2) // Powerdown control for CMU. Can be asserted when CMU is in reset mode for increased power savings. Cannot be asserted on CMU0 in multiple CMU PHYs if there are any active lanes. Signal is over-riden by por_n_i so has no affect in power on reset state.
54959     #define MS_REG_COMMON_CONTROL_CMU_PD_I_SHIFT                                                     2
54960     #define MS_REG_COMMON_CONTROL_CMU_IDDQ_I                                                         (0x1<<3) // Turn off CMU master bias only. Cannot be asserted if there are any active lanes.
54961     #define MS_REG_COMMON_CONTROL_CMU_IDDQ_I_SHIFT                                                   3
54962     #define MS_REG_COMMON_CONTROL_CMU_CK_SOC_DIV_I                                                   (0x3<<4) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 01,10 = Divide by 2 11 = Divide by 4
54963     #define MS_REG_COMMON_CONTROL_CMU_CK_SOC_DIV_I_SHIFT                                             4
54964     #define MS_REG_COMMON_CONTROL_CMU1_RESETN_I                                                      (0x1<<6) // Active low.
54965     #define MS_REG_COMMON_CONTROL_CMU1_RESETN_I_SHIFT                                                6
54966     #define MS_REG_COMMON_CONTROL_CMU1_PD_I                                                          (0x1<<7) // Powerdown control for CMU1.
54967     #define MS_REG_COMMON_CONTROL_CMU1_PD_I_SHIFT                                                    7
54968     #define MS_REG_COMMON_CONTROL_CMU1_IDDQ_I                                                        (0x1<<8) // Turn off CMU master bias only. Cannot be asserted if there are any active lanes.
54969     #define MS_REG_COMMON_CONTROL_CMU1_IDDQ_I_SHIFT                                                  8
54970     #define MS_REG_COMMON_CONTROL_CMU1_CK_SOC_DIV_I                                                  (0x3<<9) // Divider control for SOC 1 clock for both CMUs. 00 = Divide by 1 01,10 = Divide by 2 11 = Divide by 4
54971     #define MS_REG_COMMON_CONTROL_CMU1_CK_SOC_DIV_I_SHIFT                                            9
54972     #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_L_I                                               (0x1<<11) // Forward reference clock control from refclk_l_o.
54973     #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_L_I_SHIFT                                         11
54974     #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_R_I                                               (0x1<<12) // Forward reference clock control from refclk_r_o.
54975     #define MS_REG_COMMON_CONTROL_CMU1_REFCLK_QFWD_R_I_SHIFT                                         12
54976 #define MS_REG_LN1_CNTL                                                                              0x6a0004UL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: K2
54977     #define MS_REG_LN1_CNTL_LN1_PD                                                                   (0x7<<0) // Lane Partial powerdown mode enable signal. ln1_pd[0] = Lane partial power down enable. ln1_pd[1] = Lane Slumber power down enable. ln1_pd[2] = Reserved.
54978     #define MS_REG_LN1_CNTL_LN1_PD_SHIFT                                                             0
54979     #define MS_REG_LN1_CNTL_LN1_IDDQ                                                                 (0x1<<3) // Lane IDDQ mode enable.  Powers down entire PMA lane when asserted.
54980     #define MS_REG_LN1_CNTL_LN1_IDDQ_SHIFT                                                           3
54981     #define MS_REG_LN1_CNTL_LN1_RATE                                                                 (0x1f<<4) // Data rate control. See 4.2.4 changing data rates section of User Guide.
54982     #define MS_REG_LN1_CNTL_LN1_RATE_SHIFT                                                           4
54983     #define MS_REG_LN1_CNTL_LN1_CTRL                                                                 (0x1ff<<9) // Lane control 17 - rxsig_det_mask_i 16 - rxeii_exit_type_i 15 - rxei_infer_i 14 - bslip_req_i 13 - data_width_i - 0 = 10bit internal main data path, 1 = 20bit internal main data path. 12 - rxpolarity_i 11 - txcompliance_i 10 - txenable_i[1] send ln1_txdata_i[19:10] 9  - txenable_i[0] send ln1_txdata_i[9:0]
54984     #define MS_REG_LN1_CNTL_LN1_CTRL_SHIFT                                                           9
54985     #define MS_REG_LN1_CNTL_LN1_RSTN_I                                                               (0x1<<18) // Active low. lane reset signal.
54986     #define MS_REG_LN1_CNTL_LN1_RSTN_I_SHIFT                                                         18
54987     #define MS_REG_LN1_CNTL_MS_OPCS_SDET_SELECT                                                      (0x3<<19) // Selects which signal is used to drive ms_opcs_sdet 0 - ln1_stat_o[2]  (RX Locked indicator) 1 - ln1_astat_o[5] (Raw signal detext indicator) 2 - ln1_stat_o[12] (lane OK indicator) 3 - Reserved
54988     #define MS_REG_LN1_CNTL_MS_OPCS_SDET_SELECT_SHIFT                                                19
54989 #define MS_REG_CMU_STATUS                                                                            0x6a0008UL //Access:R    DataWidth:0x2   Multi Field Register.  Chips: K2
54990     #define MS_REG_CMU_STATUS_CMU_OK_O                                                               (0x1<<0) // Indicates CMU PLL has locked to the reference clock and all output clocks are at the correct frequency.
54991     #define MS_REG_CMU_STATUS_CMU_OK_O_SHIFT                                                         0
54992     #define MS_REG_CMU_STATUS_CMU1_OK_O                                                              (0x1<<1) // Indicates CMU1 PLL has locked to the reference clock and all output clocks are at the correct frequency.
54993     #define MS_REG_CMU_STATUS_CMU1_OK_O_SHIFT                                                        1
54994 #define MS_REG_LN1_STATUS                                                                            0x6a000cUL //Access:R    DataWidth:0x14  Multi Field Register.  Chips: K2
54995     #define MS_REG_LN1_STATUS_LN1_STAT_O                                                             (0x3fff<<0) // 13 - not used 12 - ln1_ok_o 11 - ln1_runlen_err_o 10:4 - not used 3:2 - ln1_rx_locked_o - bit 3 =rxdata[19:10] locked, bit 2 = rxdata[9:0] locked. 1:0 - ln1_k28p5_det_o - bit 1 = k28.5 detected on [19:10], bit 0 = k28.5 detected on [9:0]
54996     #define MS_REG_LN1_STATUS_LN1_STAT_O_SHIFT                                                       0
54997     #define MS_REG_LN1_STATUS_LN1_ASTAT_O                                                            (0x3f<<14) // 19 - Raw signal detect - Bit Slip Ack 18 - ln1_bitslip_ack_o - Bit Slip Ack 17 - not used 16 - not used 15 - not used 14 - ln1_sig_level_valid_o
54998     #define MS_REG_LN1_STATUS_LN1_ASTAT_O_SHIFT                                                      14
54999 #define MS_REG_CLOCK_SELECT                                                                          0x6a0010UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: K2
55000     #define MS_REG_CLOCK_SELECT_CMU_REFCLK_INPUT_SEL_I                                               (0x7<<0) // Reference clock input select
55001     #define MS_REG_CLOCK_SELECT_CMU_REFCLK_INPUT_SEL_I_SHIFT                                         0
55002     #define MS_REG_CLOCK_SELECT_CMU_REFCLK_SEL_I                                                     (0x1<<3) // Assert to provide CMU0 with the reference clock selected by CMU1.
55003     #define MS_REG_CLOCK_SELECT_CMU_REFCLK_SEL_I_SHIFT                                               3
55004     #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_INPUT_SEL_I                                              (0x3<<4) // Reference clock input select
55005     #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_INPUT_SEL_I_SHIFT                                        4
55006     #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_SEL_I                                                    (0x1<<6) // Assert to provide CMU1 with the reference clock selected by CMU0.
55007     #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_SEL_I_SHIFT                                              6
55008     #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_L_I                                                   (0x1<<7) // Output enables for bidirectional CML refclk buffers.
55009     #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_L_I_SHIFT                                             7
55010     #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_R_I                                                   (0x1<<8) // Output enables for bidirectional CML refclk buffers.
55011     #define MS_REG_CLOCK_SELECT_CMU1_REFCLK_OE_R_I_SHIFT                                             8
55012 #define MS_REG_ECO_RESERVED                                                                          0x6a0014UL //Access:RW   DataWidth:0x20  This is unused register for future ECOs.  Chips: K2
55013 #define MS_REG_INT_STS                                                                               0x6a0180UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: K2
55014     #define MS_REG_INT_STS_ADDRESS_ERROR                                                             (0x1<<0) // Signals an unknown address to the rf module.
55015     #define MS_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                       0
55016 #define MS_REG_INT_MASK                                                                              0x6a0184UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: K2
55017     #define MS_REG_INT_MASK_ADDRESS_ERROR                                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: MS_REG_INT_STS.ADDRESS_ERROR .
55018     #define MS_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                      0
55019 #define MS_REG_INT_STS_WR                                                                            0x6a0188UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: K2
55020     #define MS_REG_INT_STS_WR_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
55021     #define MS_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                    0
55022 #define MS_REG_INT_STS_CLR                                                                           0x6a018cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: K2
55023     #define MS_REG_INT_STS_CLR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
55024     #define MS_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                   0
55025 #define MS_REG_DBG_OUT_DATA                                                                          0x6a0200UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
55026 #define MS_REG_DBG_OUT_DATA_SIZE                                                                     8
55027 #define MS_REG_DBG_OUT_VALID                                                                         0x6a0220UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
55028 #define MS_REG_DBG_OUT_FRAME                                                                         0x6a0224UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
55029 #define MS_REG_DBG_SELECT                                                                            0x6a0228UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
55030 #define MS_REG_DBG_DWORD_ENABLE                                                                      0x6a022cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
55031 #define MS_REG_DBG_SHIFT                                                                             0x6a0230UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
55032 #define MS_REG_DBG_FORCE_VALID                                                                       0x6a0234UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
55033 #define MS_REG_DBG_FORCE_FRAME                                                                       0x6a0238UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
55034 #define MS_REG_DBGSYN_ALMOST_FULL_THR                                                                0x6a023cUL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: K2
55035 #define MS_REG_DBGSYN_STATUS                                                                         0x6a0240UL //Access:R    DataWidth:0x5   Debug only: Fill level of dbgmux fifo.  Chips: K2
55036 #define MS_REG_DBG_SAMPLING_INTERVAL                                                                 0x6a0244UL //Access:RW   DataWidth:0x14  Debug only: Sampling interval * pclk, 2ns to 2ms.  Chips: K2
55037 #define MS_REG_DBG_REPEAT_THRESHOLD_COUNT                                                            0x6a0248UL //Access:RW   DataWidth:0x4   Debug only: If 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.  Chips: K2
55038 #define MS_REG_DBG_POST_TRIGGER_LATENCY_COUNT                                                        0x6a024cUL //Access:RW   DataWidth:0x18  Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms  Chips: K2
55039 #define MS_REG_DBG_FW_TRIGGER_ENABLE                                                                 0x6a0250UL //Access:RW   DataWidth:0x1   Debug only: FW trigger is set.  Chips: K2
55040 #define MS_REG_MS_CMU                                                                                0x6a4000UL //Access:RW   DataWidth:0x8   CMU registers   = 0-0x1ff. Reserved        = 0x200-0x3ff. LANE1 registers = 0x400-0x5ff. Reserved        = 0x600-0x7ff. Reserved        = 0x800-0x9ff. Common Lane block registers = 0xa00-0xbff. CMU1 registers  = 0xc00-0xdff.  Chips: K2
55041 #define MS_REG_MS_CMU_SIZE                                                                           4096
55042 #define LED_REG_CONTROL                                                                              0x6b8000UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: K2
55043     #define LED_REG_CONTROL_OVERRIDE_TRAFFIC                                                         (0x1<<0) // If set overrides hardware control of the Traffic LED. The Traffic LED will then be controlled via bit LED_CONTROL_TRAFFIC And LED_CONTROL_BLINK_TRAFFIC
55044     #define LED_REG_CONTROL_OVERRIDE_TRAFFIC_SHIFT                                                   0
55045     #define LED_REG_CONTROL_TRAFFIC                                                                  (0x1<<4) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit turns on the Traffic LED. If the LED_CONTROL_BLINK_TRAFFIC bit bit is also set; the LED will blink with blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
55046     #define LED_REG_CONTROL_TRAFFIC_SHIFT                                                            4
55047     #define LED_REG_CONTROL_BLINK_TRAFFIC                                                            (0x1<<8) // If set along with the LED_CONTROL_OVERRIDE_TRAFFIC bit and LED_CONTROL_TRAFFIC LED bit; the Traffic LED will blink with the blink rate specified in LED_CONTROL_BLINK_RATE and LED_CONTROL_BLINK_RATE_ENA fields.
55048     #define LED_REG_CONTROL_BLINK_TRAFFIC_SHIFT                                                      8
55049     #define LED_REG_CONTROL_BLINK_RATE_ENA                                                           (0x1<<12) // This bit is set to enable the use of the LED_CONTROL_BLINK_RATE field defined below. If this bit is cleared: Number of main clock cycles the led is ON will be 2^32. Number of main clock cycles the led is ON will be 2^32.
55050     #define LED_REG_CONTROL_BLINK_RATE_ENA_SHIFT                                                     12
55051     #define LED_REG_CONTROL_ALTERNATING                                                              (0x1<<13) // This bit is set to enable the alternating between activity and speed LEDs of the same port The alternating feature is used only with MAC1 and MAC2 modes.
55052     #define LED_REG_CONTROL_ALTERNATING_SHIFT                                                        13
55053     #define LED_REG_CONTROL_BLINK_RATE                                                               (0x1ffff<<15) // Specifies the period of each blink cycle (on + off) for Traffic LED. number of main clock cycles the led is ON  = (contorl_blink_rate*2^15) number of main clock cycles the led is OFF = (contorl_blink_rate*2^15)
55054     #define LED_REG_CONTROL_BLINK_RATE_SHIFT                                                         15
55055 #define LED_REG_MODE                                                                                 0x6b8004UL //Access:RW   DataWidth:0x4   Led mode: 0     -> MAC; 1-2   -> PHY1; 3     -> PHY3; 4     -> MAC2; 5-6   -> PHY4; 7     -> PHY6; 8     -> MAC3; 9     -> PHY7; 10    -> PHY8; 11    -> PHY9; 12    -> MAC4; 13    -> PHY10; 14    -> PHY11; 15    -> PHY1;  Chips: K2
55056 #define LED_REG_PORT_SPD0_EN                                                                         0x6b8008UL //Access:RW   DataWidth:0x5   LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location will enable the corresponding speed to activate the LED.  Chips: K2
55057 #define LED_REG_PORT_SPD1_EN                                                                         0x6b800cUL //Access:RW   DataWidth:0x5   LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location will enable the corresponding speed to activate the LED.  Chips: K2
55058 #define LED_REG_PORT_SPD2_EN                                                                         0x6b8010UL //Access:RW   DataWidth:0x5   LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G A '1' to each bit location will enable the corresponding speed to activate the LED.  Chips: K2
55059 #define LED_REG_MAC_LED_SPEED                                                                        0x6b8014UL //Access:RW   DataWidth:0x5   LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G This register allows the MAC (Driver/FW) to set the link speed of the particular port. This combined with the mask for each LED will activate the corresponding LED. For ex. if the link speed is 10G, then SW will set bit[1] of this register. If 10G is enabled on LED SPD1, then SPD1 will light up, SPD0 and SPD2 will not.  Chips: K2
55060 #define LED_REG_MAC_LED_SWAP                                                                         0x6b8018UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: K2
55061     #define LED_REG_MAC_LED_SWAP_P0                                                                  (0x3<<0) // Device Drivers view of a physical port is through the PCIE physical function that was enumerated. In a typical setup, Physical function 0 is connected to Network Port 0, PF1 to NW1 and so on. However, there are cases when the PF and NW conenctions are swapped. This register sets up which PF is connected to which Network Port. For a multiport/multifunction configuration, appropriate settings should be chosen. For ex. in a two port device, only two sets of the the bits below are valid. a Four port device has all four sets of bits valid. These bits makes the connection of Network Port 0 to the corresponding Physical function. 0  -> NW0 connects to PF0 1  -> NW0 connects to PF1 2  -> NW0 connects to PF2 3  -> NW0 connects to PF3
55062     #define LED_REG_MAC_LED_SWAP_P0_SHIFT                                                            0
55063     #define LED_REG_MAC_LED_SWAP_P1                                                                  (0x3<<4) // These bits makes the connection of Network Port 1 to the corresponding Physical function. 0  -> NW1 connects to PF0 1  -> NW1 connects to PF1 2  -> NW1 connects to PF2 3  -> NW1 connects to PF3
55064     #define LED_REG_MAC_LED_SWAP_P1_SHIFT                                                            4
55065     #define LED_REG_MAC_LED_SWAP_P2                                                                  (0x3<<8) // These bits makes the connection of Network Port 2 to the corresponding Physical function. 0  -> NW2 connects to PF0 1  -> NW2 connects to PF1 2  -> NW2 connects to PF2 3  -> NW2 connects to PF3
55066     #define LED_REG_MAC_LED_SWAP_P2_SHIFT                                                            8
55067     #define LED_REG_MAC_LED_SWAP_P3                                                                  (0x3<<12) // These bits makes the connection of Network Port 2 to the corresponding Physical function. 0  -> NW3 connects to PF0 1  -> NW3 connects to PF1 2  -> NW3 connects to PF2 3  -> NW3 connects to PF3
55068     #define LED_REG_MAC_LED_SWAP_P3_SHIFT                                                            12
55069 #define LED_REG_RAW_SPEED_LN0                                                                        0x6b801cUL //Access:R    DataWidth:0x5   LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G RAW version of the LED from the SERDES..  Chips: K2
55070 #define LED_REG_RAW_SPEED_LN1                                                                        0x6b8020UL //Access:R    DataWidth:0x5   LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G RAW version of the LED from the SERDES..  Chips: K2
55071 #define LED_REG_RAW_SPEED_LN2                                                                        0x6b8024UL //Access:R    DataWidth:0x5   LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G RAW version of the LED from the SERDES..  Chips: K2
55072 #define LED_REG_RAW_SPEED_LN3                                                                        0x6b8028UL //Access:R    DataWidth:0x5   LED decode [0] -> 1G [1] -> 10G [2] -> 25G [3] -> 40G [4] -> 50G RAW version of the LED from the SERDES..  Chips: K2
55073 #define LED_REG_ECO_RESERVED                                                                         0x6b802cUL //Access:RW   DataWidth:0x20  This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: K2
55074 #define LED_REG_INT_STS_0                                                                            0x6b8180UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: K2
55075     #define LED_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
55076     #define LED_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
55077 #define LED_REG_INT_MASK_0                                                                           0x6b8184UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: K2
55078     #define LED_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: LED_REG_INT_STS_0.ADDRESS_ERROR .
55079     #define LED_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
55080 #define LED_REG_INT_STS_WR_0                                                                         0x6b8188UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: K2
55081     #define LED_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
55082     #define LED_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
55083 #define LED_REG_INT_STS_CLR_0                                                                        0x6b818cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: K2
55084     #define LED_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
55085     #define LED_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
55086 #define NWS_REG_COMMON_CONTROL                                                                       0x700000UL //Access:RW   DataWidth:0x1e  Multi Field Register.  Chips: K2
55087     #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I                                                (0x3<<0) // 0x0 - Select reference clock from Bump 0x1 - Select inter-macro refrence clock from the left side 0x2 - Same as 0x0 0x3 - Select inter-macro refrence clock from the right side
55088     #define NWS_REG_COMMON_CONTROL_REFCLK_INPUT_SEL_I_SHIFT                                          0
55089     #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I                                                 (0x3<<2) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the right side 0x3 - Same as 0x2
55090     #define NWS_REG_COMMON_CONTROL_REFCLK_LEFT_SEL_I_SHIFT                                           2
55091     #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I                                                (0x3<<4) // 0x0 - Saves Power 0x1 - Select reference clock from Bump 0x2 - Select inter-macro refrence clock from the left side 0x3 - Same as 0x2
55092     #define NWS_REG_COMMON_CONTROL_REFCLK_RIGHT_SEL_I_SHIFT                                          4
55093     #define NWS_REG_COMMON_CONTROL_STAT_LOS_SELECT                                                   (0x3<<6) // Selects which stat_los signal is used for nws_nwm_sd_energy_detect. 0 - use ~lnX_stat_los_o 1 - use ~lnX_stat_los_deglitch_o (Default) 2 - use lnX_stat_rxvalid_o
55094     #define NWS_REG_COMMON_CONTROL_STAT_LOS_SELECT_SHIFT                                             6
55095     #define NWS_REG_COMMON_CONTROL_CPU_RESET                                                         (0x1<<10) // Controls cpu_reset_i reset signal into the SerDes.
55096     #define NWS_REG_COMMON_CONTROL_CPU_RESET_SHIFT                                                   10
55097     #define NWS_REG_COMMON_CONTROL_POR_N                                                             (0x1<<11) // Controls por_n_i reset signal into the SerDes. This should be 0 (Reset value) while the SerDes program and data rams are being written, and the serdes is being configured.  This holds the SerDes in Reset. Once the memory is configured, write 1 to this bit to allow the SerDes to begin normal Operation.
55098     #define NWS_REG_COMMON_CONTROL_POR_N_SHIFT                                                       11
55099     #define NWS_REG_COMMON_CONTROL_CM0_RST_N                                                         (0x1<<12) // Controls cm0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation.
55100     #define NWS_REG_COMMON_CONTROL_CM0_RST_N_SHIFT                                                   12
55101     #define NWS_REG_COMMON_CONTROL_CM1_RST_N                                                         (0x1<<13) // Controls cm1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the cmu0 in Reset. write 1 to this bit to allow the SerDes to begin normal Operation.
55102     #define NWS_REG_COMMON_CONTROL_CM1_RST_N_SHIFT                                                   13
55103     #define NWS_REG_COMMON_CONTROL_LN0_RST_N                                                         (0x1<<14) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln0 in Reset. write 1 to begin normal Operation on ln0.
55104     #define NWS_REG_COMMON_CONTROL_LN0_RST_N_SHIFT                                                   14
55105     #define NWS_REG_COMMON_CONTROL_LN1_RST_N                                                         (0x1<<15) // Controls ln1_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln1 in Reset. write 1 to begin normal Operation on ln1.
55106     #define NWS_REG_COMMON_CONTROL_LN1_RST_N_SHIFT                                                   15
55107     #define NWS_REG_COMMON_CONTROL_LN2_RST_N                                                         (0x1<<16) // Controls ln0_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln2 in Reset. write 1 to begin normal Operation on ln2.
55108     #define NWS_REG_COMMON_CONTROL_LN2_RST_N_SHIFT                                                   16
55109     #define NWS_REG_COMMON_CONTROL_LN3_RST_N                                                         (0x1<<17) // Controls ln3_rst_n_i reset signal into the SerDes. This should be 0 (Reset value) This holds the ln3 in Reset. write 1 to begin normal Operation on ln3.
55110     #define NWS_REG_COMMON_CONTROL_LN3_RST_N_SHIFT                                                   17
55111     #define NWS_REG_COMMON_CONTROL_CM0_PD                                                            (0x3<<18) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
55112     #define NWS_REG_COMMON_CONTROL_CM0_PD_SHIFT                                                      18
55113     #define NWS_REG_COMMON_CONTROL_CM1_PD                                                            (0x3<<20) // CMU Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
55114     #define NWS_REG_COMMON_CONTROL_CM1_PD_SHIFT                                                      20
55115     #define NWS_REG_COMMON_CONTROL_LN0_PD                                                            (0x3<<22) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
55116     #define NWS_REG_COMMON_CONTROL_LN0_PD_SHIFT                                                      22
55117     #define NWS_REG_COMMON_CONTROL_LN1_PD                                                            (0x3<<24) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
55118     #define NWS_REG_COMMON_CONTROL_LN1_PD_SHIFT                                                      24
55119     #define NWS_REG_COMMON_CONTROL_LN2_PD                                                            (0x3<<26) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
55120     #define NWS_REG_COMMON_CONTROL_LN2_PD_SHIFT                                                      26
55121     #define NWS_REG_COMMON_CONTROL_LN3_PD                                                            (0x3<<28) // Lane Macro Power down control 0x0 - Normal / Active 0x1 - Partial power down 0x2 - Most blocks powered down (only LOS active) 0x3 - Complete power down (IDDQ mode)
55122     #define NWS_REG_COMMON_CONTROL_LN3_PD_SHIFT                                                      28
55123 #define NWS_REG_PHY_CTRL                                                                             0x700004UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: K2
55124     #define NWS_REG_PHY_CTRL_REFCLK                                                                  (0x1f<<0) // Sets phy_ctrl_refclk_i used for CMU0 0x09 - refclk is 257.8125Mhz
55125     #define NWS_REG_PHY_CTRL_REFCLK_SHIFT                                                            0
55126     #define NWS_REG_PHY_CTRL_RATE1                                                                   (0x3f<<5) // Sets phy_ctrl_rate1_i used for CMU0 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125 Gbps 0x2F - Data rate is 1.25 Gbps
55127     #define NWS_REG_PHY_CTRL_RATE1_SHIFT                                                             5
55128     #define NWS_REG_PHY_CTRL_RATE2                                                                   (0x3f<<11) // Sets phy_ctrl_rate1_i used for CMU1 0x03 - Data rate is 25.78125 Gbps 0x23 - Data rate is 10.3125 Gbps 0x2F - Data rate is 1.25 Gbps
55129     #define NWS_REG_PHY_CTRL_RATE2_SHIFT                                                             11
55130 #define NWS_REG_ANEG_CFG                                                                             0x700008UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
55131     #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I                                                          (0x3<<0) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
55132     #define NWS_REG_ANEG_CFG_LN0_ANEG_CFG_I_SHIFT                                                    0
55133     #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I                                                          (0x3<<2) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
55134     #define NWS_REG_ANEG_CFG_LN1_ANEG_CFG_I_SHIFT                                                    2
55135     #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I                                                          (0x3<<4) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
55136     #define NWS_REG_ANEG_CFG_LN2_ANEG_CFG_I_SHIFT                                                    4
55137     #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I                                                          (0x3<<6) // 0x0 - Not auto-negotiation controlled. Lane will be manually controlled via lnX_pd_i and lnX_rst_i. 0x1 - auto-negotiation controlled, but auto-negotiation is not run on the lane (call it an AN-slave lane) 0x2 - auto-negotiation controlled, and auto-negotiation is run on the lane (call it an AN-master lane) 0x3 - reserved
55138     #define NWS_REG_ANEG_CFG_LN3_ANEG_CFG_I_SHIFT                                                    6
55139 #define NWS_REG_COMMON_STATUS                                                                        0x70000cUL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: K2
55140     #define NWS_REG_COMMON_STATUS_ERR_O                                                              (0x1<<0) // 0x0 - No error 0x1 - Phy has internal error
55141     #define NWS_REG_COMMON_STATUS_ERR_O_SHIFT                                                        0
55142     #define NWS_REG_COMMON_STATUS_CM0_OK_O                                                           (0x1<<1) // 0x1 - Indicates CMU0 PLL has locked to the reference clock and all output clocks are at the correct frequency
55143     #define NWS_REG_COMMON_STATUS_CM0_OK_O_SHIFT                                                     1
55144     #define NWS_REG_COMMON_STATUS_CM1_OK_O                                                           (0x1<<2) // 0x1 - Indicates CMU1 PLL has locked to the reference clock and all output clocks are at the correct frequency
55145     #define NWS_REG_COMMON_STATUS_CM1_OK_O_SHIFT                                                     2
55146     #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O                                                 (0x1<<3) // 0x0 - PHY is not ready to respond to cm0_rst_n_i and cm0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm0_rst_n_i and cm0_pd_i[1:0].
55147     #define NWS_REG_COMMON_STATUS_CM0_RST_PD_READY_O_SHIFT                                           3
55148     #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O                                                 (0x1<<4) // 0x0 - PHY is not ready to respond to cm1_rst_n_i and cm1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to cm1_rst_n_i and cm1_pd_i[1:0].
55149     #define NWS_REG_COMMON_STATUS_CM1_RST_PD_READY_O_SHIFT                                           4
55150     #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O                                                 (0x1<<5) // 0x0 - PHY is not ready to respond to ln0_rst_n_i and ln0_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln0_rst_n_i and ln0_pd_i[1:0].
55151     #define NWS_REG_COMMON_STATUS_LN0_RST_PD_READY_O_SHIFT                                           5
55152     #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O                                                 (0x1<<6) // 0x0 - PHY is not ready to respond to ln1_rst_n_i and ln1_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln1_rst_n_i and ln1_pd_i[1:0].
55153     #define NWS_REG_COMMON_STATUS_LN1_RST_PD_READY_O_SHIFT                                           6
55154     #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O                                                 (0x1<<7) // 0x0 - PHY is not ready to respond to ln2_rst_n_i and ln2_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln2_rst_n_i and ln2_pd_i[1:0].
55155     #define NWS_REG_COMMON_STATUS_LN2_RST_PD_READY_O_SHIFT                                           7
55156     #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O                                                 (0x1<<8) // 0x0 - PHY is not ready to respond to ln3_rst_n_i and ln3_pd_i[1:0]. The signals should not be changed. 0x1 - PHY is ready to respond to ln3_rst_n_i and ln3_pd_i[1:0].
55157     #define NWS_REG_COMMON_STATUS_LN3_RST_PD_READY_O_SHIFT                                           8
55158 #define NWS_REG_LN0_CNTL                                                                             0x700010UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
55159     #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH                                                     (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
55160     #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_WIDTH_SHIFT                                               0
55161     #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY                                                     (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
55162     #define NWS_REG_LN0_CNTL_LN0_CTRL_RXPOLARITY_SHIFT                                               3
55163     #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN                                                     (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
55164     #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_EN_SHIFT                                               4
55165     #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE                                                  (0x1<<5) // Informs the PHY that the received signal was lost.
55166     #define NWS_REG_LN0_CNTL_LN0_CTRL_LOS_EII_VALUE_SHIFT                                            5
55167     #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I                                                    (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
55168     #define NWS_REG_LN0_CNTL_LN0_CTRL_DATA_RATE_I_SHIFT                                              8
55169 #define NWS_REG_LN0_STATUS                                                                           0x700014UL //Access:R    DataWidth:0x5   Multi Field Register.  Chips: K2
55170     #define NWS_REG_LN0_STATUS_LN0_STAT_OK                                                           (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
55171     #define NWS_REG_LN0_STATUS_LN0_STAT_OK_SHIFT                                                     0
55172     #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID                                                      (0x1<<1) // 0x0 - data on ln0_rxdata_o is invalid. 0x1 - data on the active bits of ln0_rxdata_o is valid.
55173     #define NWS_REG_LN0_STATUS_LN0_STAT_RXVALID_SHIFT                                                1
55174     #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR                                                   (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
55175     #define NWS_REG_LN0_STATUS_LN0_STAT_RUNLEN_ERR_SHIFT                                             2
55176     #define NWS_REG_LN0_STATUS_LN0_STAT_LOS                                                          (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins.
55177     #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_SHIFT                                                    3
55178     #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH                                                 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln0_rxp_i / ln0_rxm_i pins. 0x1 - No Signal detected on ln0_rxp_i / ln0_rxm_i pins.
55179     #define NWS_REG_LN0_STATUS_LN0_STAT_LOS_DEGLITCH_SHIFT                                           4
55180 #define NWS_REG_LN0_AN_LINK_INPUTS                                                                   0x700018UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: K2
55181     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I                                     (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
55182     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_CR2_I_SHIFT                               0
55183     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I                                     (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
55184     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_50G_KR2_I_SHIFT                               1
55185     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I                                     (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
55186     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_CR4_I_SHIFT                               2
55187     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I                                     (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
55188     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_40G_KR4_I_SHIFT                               3
55189     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I                                      (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
55190     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_CR_I_SHIFT                                4
55191     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I                                      (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
55192     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_GR_I_SHIFT                                5
55193     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I                                      (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
55194     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_25G_KR_I_SHIFT                                6
55195     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I                                      (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
55196     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_10G_KR_I_SHIFT                                7
55197     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I                                       (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
55198     #define NWS_REG_LN0_AN_LINK_INPUTS_LN0_LINK_STATUS_1G_KX_I_SHIFT                                 8
55199 #define NWS_REG_LN0_AN_LINK_OUTPUTS                                                                  0x70001cUL //Access:R    DataWidth:0x19  Multi Field Register.  Chips: K2
55200     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O                                      (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55201     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_CR2_O_SHIFT                                0
55202     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O                                      (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55203     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_50G_KR2_O_SHIFT                                2
55204     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O                                      (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55205     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_CR4_O_SHIFT                                4
55206     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O                                      (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55207     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_40G_KR4_O_SHIFT                                6
55208     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O                                       (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55209     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_CR_O_SHIFT                                 8
55210     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O                                       (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55211     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_GR_O_SHIFT                                 10
55212     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O                                       (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55213     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_25G_KR_O_SHIFT                                 12
55214     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O                                       (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55215     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_10G_KR_O_SHIFT                                 14
55216     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O                                        (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55217     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_LINK_CNTL_1G_KX_O_SHIFT                                  16
55218     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O                                         (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
55219     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_STAT_LT_SIGDET_O_SHIFT                                   18
55220     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O                                              (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
55221     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_DME_OP_O_SHIFT                                        19
55222     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O                                         (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
55223     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_TX_PAUSE_EN_O_SHIFT                                   20
55224     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O                                         (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
55225     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RX_PAUSE_EN_O_SHIFT                                   21
55226     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O                                           (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
55227     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_FC_FEC_EN_O_SHIFT                                     22
55228     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O                                           (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
55229     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_RS_FEC_EN_O_SHIFT                                     23
55230     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O                                              (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
55231     #define NWS_REG_LN0_AN_LINK_OUTPUTS_LN0_AN_EEE_EN_O_SHIFT                                        24
55232 #define NWS_REG_LN1_CNTL                                                                             0x700020UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
55233     #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH                                                     (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
55234     #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_WIDTH_SHIFT                                               0
55235     #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY                                                     (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
55236     #define NWS_REG_LN1_CNTL_LN1_CTRL_RXPOLARITY_SHIFT                                               3
55237     #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN                                                     (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
55238     #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_EN_SHIFT                                               4
55239     #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE                                                  (0x1<<5) // Informs the PHY that the received signal was lost.
55240     #define NWS_REG_LN1_CNTL_LN1_CTRL_LOS_EII_VALUE_SHIFT                                            5
55241     #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I                                                    (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
55242     #define NWS_REG_LN1_CNTL_LN1_CTRL_DATA_RATE_I_SHIFT                                              8
55243 #define NWS_REG_LN1_STATUS                                                                           0x700024UL //Access:R    DataWidth:0x5   Multi Field Register.  Chips: K2
55244     #define NWS_REG_LN1_STATUS_LN1_STAT_OK                                                           (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
55245     #define NWS_REG_LN1_STATUS_LN1_STAT_OK_SHIFT                                                     0
55246     #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID                                                      (0x1<<1) // 0x0 - data on ln1_rxdata_o is invalid. 0x1 - data on the active bits of ln1_rxdata_o is valid.
55247     #define NWS_REG_LN1_STATUS_LN1_STAT_RXVALID_SHIFT                                                1
55248     #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR                                                   (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
55249     #define NWS_REG_LN1_STATUS_LN1_STAT_RUNLEN_ERR_SHIFT                                             2
55250     #define NWS_REG_LN1_STATUS_LN1_STAT_LOS                                                          (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins.
55251     #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_SHIFT                                                    3
55252     #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH                                                 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln1_rxp_i / ln1_rxm_i pins. 0x1 - No Signal detected on ln1_rxp_i / ln1_rxm_i pins.
55253     #define NWS_REG_LN1_STATUS_LN1_STAT_LOS_DEGLITCH_SHIFT                                           4
55254 #define NWS_REG_LN1_AN_LINK_INPUTS                                                                   0x700028UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: K2
55255     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I                                     (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
55256     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_CR2_I_SHIFT                               0
55257     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I                                     (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
55258     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_50G_KR2_I_SHIFT                               1
55259     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I                                     (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
55260     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_CR4_I_SHIFT                               2
55261     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I                                     (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
55262     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_40G_KR4_I_SHIFT                               3
55263     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I                                      (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
55264     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_CR_I_SHIFT                                4
55265     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I                                      (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
55266     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_GR_I_SHIFT                                5
55267     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I                                      (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
55268     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_25G_KR_I_SHIFT                                6
55269     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I                                      (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
55270     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_10G_KR_I_SHIFT                                7
55271     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I                                       (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
55272     #define NWS_REG_LN1_AN_LINK_INPUTS_LN1_LINK_STATUS_1G_KX_I_SHIFT                                 8
55273 #define NWS_REG_LN1_AN_LINK_OUTPUTS                                                                  0x70002cUL //Access:R    DataWidth:0x19  Multi Field Register.  Chips: K2
55274     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O                                      (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55275     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_CR2_O_SHIFT                                0
55276     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O                                      (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55277     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_50G_KR2_O_SHIFT                                2
55278     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O                                      (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55279     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_CR4_O_SHIFT                                4
55280     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O                                      (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55281     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_40G_KR4_O_SHIFT                                6
55282     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O                                       (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55283     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_CR_O_SHIFT                                 8
55284     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O                                       (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55285     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_GR_O_SHIFT                                 10
55286     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O                                       (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55287     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_25G_KR_O_SHIFT                                 12
55288     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O                                       (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55289     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_10G_KR_O_SHIFT                                 14
55290     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O                                        (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55291     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_LINK_CNTL_1G_KX_O_SHIFT                                  16
55292     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O                                         (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
55293     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_STAT_LT_SIGDET_O_SHIFT                                   18
55294     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O                                              (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
55295     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_DME_OP_O_SHIFT                                        19
55296     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O                                         (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
55297     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_TX_PAUSE_EN_O_SHIFT                                   20
55298     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O                                         (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
55299     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RX_PAUSE_EN_O_SHIFT                                   21
55300     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O                                           (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
55301     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_FC_FEC_EN_O_SHIFT                                     22
55302     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O                                           (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
55303     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_RS_FEC_EN_O_SHIFT                                     23
55304     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O                                              (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
55305     #define NWS_REG_LN1_AN_LINK_OUTPUTS_LN1_AN_EEE_EN_O_SHIFT                                        24
55306 #define NWS_REG_LN2_CNTL                                                                             0x700030UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
55307     #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH                                                     (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
55308     #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_WIDTH_SHIFT                                               0
55309     #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY                                                     (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
55310     #define NWS_REG_LN2_CNTL_LN2_CTRL_RXPOLARITY_SHIFT                                               3
55311     #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN                                                     (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
55312     #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_EN_SHIFT                                               4
55313     #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE                                                  (0x1<<5) // Informs the PHY that the received signal was lost.
55314     #define NWS_REG_LN2_CNTL_LN2_CTRL_LOS_EII_VALUE_SHIFT                                            5
55315     #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I                                                    (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
55316     #define NWS_REG_LN2_CNTL_LN2_CTRL_DATA_RATE_I_SHIFT                                              8
55317 #define NWS_REG_LN2_STATUS                                                                           0x700034UL //Access:R    DataWidth:0x5   Multi Field Register.  Chips: K2
55318     #define NWS_REG_LN2_STATUS_LN2_STAT_OK                                                           (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
55319     #define NWS_REG_LN2_STATUS_LN2_STAT_OK_SHIFT                                                     0
55320     #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID                                                      (0x1<<1) // 0x0 - data on ln2_rxdata_o is invalid. 0x1 - data on the active bits of ln2_rxdata_o is valid.
55321     #define NWS_REG_LN2_STATUS_LN2_STAT_RXVALID_SHIFT                                                1
55322     #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR                                                   (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
55323     #define NWS_REG_LN2_STATUS_LN2_STAT_RUNLEN_ERR_SHIFT                                             2
55324     #define NWS_REG_LN2_STATUS_LN2_STAT_LOS                                                          (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins.
55325     #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_SHIFT                                                    3
55326     #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH                                                 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln2_rxp_i / ln2_rxm_i pins. 0x1 - No Signal detected on ln2_rxp_i / ln2_rxm_i pins.
55327     #define NWS_REG_LN2_STATUS_LN2_STAT_LOS_DEGLITCH_SHIFT                                           4
55328 #define NWS_REG_LN2_AN_LINK_INPUTS                                                                   0x700038UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: K2
55329     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I                                     (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
55330     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_CR2_I_SHIFT                               0
55331     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I                                     (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
55332     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_50G_KR2_I_SHIFT                               1
55333     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I                                     (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
55334     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_CR4_I_SHIFT                               2
55335     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I                                     (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
55336     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_40G_KR4_I_SHIFT                               3
55337     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I                                      (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
55338     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_CR_I_SHIFT                                4
55339     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I                                      (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
55340     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_GR_I_SHIFT                                5
55341     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I                                      (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
55342     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_25G_KR_I_SHIFT                                6
55343     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I                                      (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
55344     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_10G_KR_I_SHIFT                                7
55345     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I                                       (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
55346     #define NWS_REG_LN2_AN_LINK_INPUTS_LN2_LINK_STATUS_1G_KX_I_SHIFT                                 8
55347 #define NWS_REG_LN2_AN_LINK_OUTPUTS                                                                  0x70003cUL //Access:R    DataWidth:0x19  Multi Field Register.  Chips: K2
55348     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O                                      (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55349     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_CR2_O_SHIFT                                0
55350     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O                                      (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55351     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_50G_KR2_O_SHIFT                                2
55352     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O                                      (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55353     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_CR4_O_SHIFT                                4
55354     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O                                      (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55355     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_40G_KR4_O_SHIFT                                6
55356     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O                                       (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55357     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_CR_O_SHIFT                                 8
55358     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O                                       (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55359     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_GR_O_SHIFT                                 10
55360     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O                                       (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55361     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_25G_KR_O_SHIFT                                 12
55362     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O                                       (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55363     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_10G_KR_O_SHIFT                                 14
55364     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O                                        (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55365     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_LINK_CNTL_1G_KX_O_SHIFT                                  16
55366     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O                                         (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
55367     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_STAT_LT_SIGDET_O_SHIFT                                   18
55368     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O                                              (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
55369     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_DME_OP_O_SHIFT                                        19
55370     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O                                         (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
55371     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_TX_PAUSE_EN_O_SHIFT                                   20
55372     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O                                         (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
55373     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RX_PAUSE_EN_O_SHIFT                                   21
55374     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O                                           (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
55375     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_FC_FEC_EN_O_SHIFT                                     22
55376     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O                                           (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
55377     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_RS_FEC_EN_O_SHIFT                                     23
55378     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O                                              (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
55379     #define NWS_REG_LN2_AN_LINK_OUTPUTS_LN2_AN_EEE_EN_O_SHIFT                                        24
55380 #define NWS_REG_LN3_CNTL                                                                             0x700040UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
55381     #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH                                                     (0x7<<0) // 0x0 - 8bit 0x1 - 10bit (1G) 0x2 - 16bit 0x3 - 20bit (10G) 0x4 - 32bit 0x5 - 40bit (25G/50G) Others - Reserved
55382     #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_WIDTH_SHIFT                                               0
55383     #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY                                                     (0x1<<3) // 0 - Phy does no polarity inversion. 1 - Phy does polarity inversion.
55384     #define NWS_REG_LN3_CNTL_LN3_CTRL_RXPOLARITY_SHIFT                                               3
55385     #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN                                                     (0x1<<4) // Informs the PHY to bypass the output of the analog LOS detector and instead rely upon a protocal LOS mechanism in the SoC/ASIC 0 - LOS opperates as normal 1 - Bypass analog LOS output and instead rely upon protocol-level LOS detection via input lnX_ctrl_los_eli_value (net bit in this register).
55386     #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_EN_SHIFT                                               4
55387     #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE                                                  (0x1<<5) // Informs the PHY that the received signal was lost.
55388     #define NWS_REG_LN3_CNTL_LN3_CTRL_LOS_EII_VALUE_SHIFT                                            5
55389     #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I                                                    (0x3<<8) // 0x0 - Select Rate1 (25G) 0x1 - Select Rate2 (10G) 0x2 - Select Rate2/4.125 (1G) Others - Reserved
55390     #define NWS_REG_LN3_CNTL_LN3_CTRL_DATA_RATE_I_SHIFT                                              8
55391 #define NWS_REG_LN3_STATUS                                                                           0x700044UL //Access:R    DataWidth:0x5   Multi Field Register.  Chips: K2
55392     #define NWS_REG_LN3_STATUS_LN3_STAT_OK                                                           (0x1<<0) // 0x0 - Lane is not ready to send and receive data. 0x1 - Lane is ready to send and receive data.
55393     #define NWS_REG_LN3_STATUS_LN3_STAT_OK_SHIFT                                                     0
55394     #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID                                                      (0x1<<1) // 0x0 - data on ln3_rxdata_o is invalid. 0x1 - data on the active bits of ln3_rxdata_o is valid.
55395     #define NWS_REG_LN3_STATUS_LN3_STAT_RXVALID_SHIFT                                                1
55396     #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR                                                   (0x1<<2) // 0x0 - received data run length has not exceeded the programmable run length detector threshold. 0x1 - received data run length has exceeded the programmable run length detector threshold.
55397     #define NWS_REG_LN3_STATUS_LN3_STAT_RUNLEN_ERR_SHIFT                                             2
55398     #define NWS_REG_LN3_STATUS_LN3_STAT_LOS                                                          (0x1<<3) // Loss of Signal (LOS) indicator that includes the combined functions of the digitally assisted analog LOS, digital LOS, and protocol LOS override features. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins.
55399     #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_SHIFT                                                    3
55400     #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH                                                 (0x1<<4) // This is another LOS status indicator that is the direct output of the digitally filtered analog LOS and does not include the digital LOS and protocol LOS bypass features. This signal can be used as a wakeup signal in the case that the digital or protocol LOS features are enabled. 0x0 - Signal detected on ln3_rxp_i / ln3_rxm_i pins. 0x1 - No Signal detected on ln3_rxp_i / ln3_rxm_i pins.
55401     #define NWS_REG_LN3_STATUS_LN3_STAT_LOS_DEGLITCH_SHIFT                                           4
55402 #define NWS_REG_LN3_AN_LINK_INPUTS                                                                   0x700048UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: K2
55403     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I                                     (0x1<<0) // Set to 1 if the respective link is receiving a valid signal from the link partner
55404     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_CR2_I_SHIFT                               0
55405     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I                                     (0x1<<1) // Set to 1 if the respective link is receiving a valid signal from the link partner
55406     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_50G_KR2_I_SHIFT                               1
55407     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I                                     (0x1<<2) // Set to 1 if the respective link is receiving a valid signal from the link partner
55408     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_CR4_I_SHIFT                               2
55409     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I                                     (0x1<<3) // Set to 1 if the respective link is receiving a valid signal from the link partner
55410     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_40G_KR4_I_SHIFT                               3
55411     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I                                      (0x1<<4) // Set to 1 if the respective link is receiving a valid signal from the link partner
55412     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_CR_I_SHIFT                                4
55413     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I                                      (0x1<<5) // Set to 1 if the respective link is receiving a valid signal from the link partner
55414     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_GR_I_SHIFT                                5
55415     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I                                      (0x1<<6) // Set to 1 if the respective link is receiving a valid signal from the link partner
55416     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_25G_KR_I_SHIFT                                6
55417     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I                                      (0x1<<7) // Set to 1 if the respective link is receiving a valid signal from the link partner
55418     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_10G_KR_I_SHIFT                                7
55419     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I                                       (0x1<<8) // Set to 1 if the respective link is receiving a valid signal from the link partner
55420     #define NWS_REG_LN3_AN_LINK_INPUTS_LN3_LINK_STATUS_1G_KX_I_SHIFT                                 8
55421 #define NWS_REG_LN3_AN_LINK_OUTPUTS                                                                  0x70004cUL //Access:R    DataWidth:0x19  Multi Field Register.  Chips: K2
55422     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O                                      (0x3<<0) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55423     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_CR2_O_SHIFT                                0
55424     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O                                      (0x3<<2) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55425     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_50G_KR2_O_SHIFT                                2
55426     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O                                      (0x3<<4) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55427     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_CR4_O_SHIFT                                4
55428     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O                                      (0x3<<6) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55429     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_40G_KR4_O_SHIFT                                6
55430     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O                                       (0x3<<8) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55431     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_CR_O_SHIFT                                 8
55432     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O                                       (0x3<<10) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55433     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_GR_O_SHIFT                                 10
55434     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O                                       (0x3<<12) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55435     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_25G_KR_O_SHIFT                                 12
55436     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O                                       (0x3<<14) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55437     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_10G_KR_O_SHIFT                                 14
55438     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O                                        (0x3<<16) // 0x0 - Link is off; Drivers are disabled. 0x1 - Link is on; Scan for Carrier; Configuration is auto-negotiation. 0x2 - Reserved. 0x3 - Link is on; Configuration is Mission Mode.
55439     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_LINK_CNTL_1G_KX_O_SHIFT                                  16
55440     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O                                         (0x1<<18) // This signal detect output corresponds to the sigdet variable described in the Ethernet LT specification.
55441     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_STAT_LT_SIGDET_O_SHIFT                                   18
55442     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O                                              (0x1<<19) // This is an active high signal that indicates when the auto negotiation circuit is transmitting valid DME pages. It is intended to be used in instances where the PMD output is optically or magnetically coupled, and a changing signal is always required. In those instances, this output signal may be used to turn off driver circuits during auto-negotiation when only a steady mark or idle signal is being sent. When the DME_OP signal is high, the auto-negotiation circuit is transmitting valid DME pages. When this signal is low, the auto-negotiation circuit is transmitting a steady idle or mark signal.
55443     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_DME_OP_O_SHIFT                                        19
55444     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O                                         (0x1<<20) // This is the negotiated enable signal to allow pause control packets to be generated in the MAC and transmitted from the output of the transmitter. When this signal is a 1, it allows the transmitter to generate pause control packets according to any predetermined algorithm. When this signal is a 0, it prevents the transmitter generating pause control packets.
55445     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_TX_PAUSE_EN_O_SHIFT                                   20
55446     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O                                         (0x1<<21) // This is the negotiated enable signal to allow pause control packets that have arrived at the receiver to be detected in the MAC and subsequently used to suspend the transmitter. If this bit is a 1, pause control packets that arrived at the receiver are detected in the MAC and are subsequently used to suspend the transmitter. If this bit is a 0, pause control packets that arrive at the receiver have no effect on the behavior of the transmitter.
55447     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RX_PAUSE_EN_O_SHIFT                                   21
55448     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O                                           (0x1<<22) // This is the negotiated output enable signal for the Fire-code forward error correction. If this output is a 1, the Clause 74 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 74 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
55449     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_FC_FEC_EN_O_SHIFT                                     22
55450     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O                                           (0x1<<23) // This is the negotiated output enable signal for the Reed-Solomon forward error correction. If this output is a 1, the Clause 91 forward error correction hardware must be switched on and muxed into the transmit and receive paths, respectively. If this output is a 0, the Clause 91 forward error correction hardware must be switched off and muxed out of the transmit and receive paths respectively.
55451     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_RS_FEC_EN_O_SHIFT                                     23
55452     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O                                              (0x1<<24) // This is an active high signal that indicates the resolved EEE capability. If the output is 1, both the local device and the link partner advertise the EEE capability for the resolved PHY type. It is 0 otherewise. Note that it indicates deep sleep capability. Note the EEE capability can also be resolved by logis outside of the PHY. Therefore, the PHY does not implement any logic based on the state of this output.
55453     #define NWS_REG_LN3_AN_LINK_OUTPUTS_LN3_AN_EEE_EN_O_SHIFT                                        24
55454 #define NWS_REG_EXTERNAL_SIGNAL_DETECT                                                               0x700050UL //Access:R    DataWidth:0x4   Multi Field Register.  Chips: K2
55455     #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P0                                        (0x1<<0) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P0_SIGDET
55456     #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P0_SHIFT                                  0
55457     #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P1                                        (0x1<<1) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P1_SIGDET
55458     #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P1_SHIFT                                  1
55459     #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P2                                        (0x1<<2) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P2_SIGDET
55460     #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P2_SHIFT                                  2
55461     #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P3                                        (0x1<<3) // Used to detect the presence of energy on SerDes receive channels or to detect the receiver loss condition(RX_LOS) from an external optical module Connects directly to pin P3_SIGDET
55462     #define NWS_REG_EXTERNAL_SIGNAL_DETECT_EXTERNAL_SIGDET_P3_SHIFT                                  3
55463 #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS                                                           0x700054UL //Access:R    DataWidth:0x4   Multi Field Register.  Chips: K2
55464     #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P0                                (0x1<<0) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P0_PHY_LASI_B
55465     #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P0_SHIFT                          0
55466     #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P1                                (0x1<<1) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P1_PHY_LASI_B
55467     #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P1_SHIFT                          1
55468     #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P2                                (0x1<<2) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P2_PHY_LASI_B
55469     #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P2_SHIFT                          2
55470     #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P3                                (0x1<<3) // Link Alarm Status Indication An asserted low input from the optical module or external PHY. When asserted, this signal indicates that a fault condition has been detected or cleared. Refer to the XENPAK MSA Release v3.0 for more details. This signal is an output from an external PHY that can drive LASI to the Controller to indicate a link status change or other events outlined in the XENPAK MSA standard. Connects directly to pin P3_PHY_LASI_B
55471     #define NWS_REG_EXTERNAL_LINK_ALARM_STATUS_EXTERNAL_PHY_LASI_B_P3_SHIFT                          3
55472 #define NWS_REG_ECO_RESERVED                                                                         0x700058UL //Access:RW   DataWidth:0x20  This is unused register for future ECOs.  Chips: K2
55473 #define NWS_REG_DBG_OUT_DATA                                                                         0x700100UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
55474 #define NWS_REG_DBG_OUT_DATA_SIZE                                                                    8
55475 #define NWS_REG_DBG_OUT_VALID                                                                        0x700120UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
55476 #define NWS_REG_DBG_OUT_FRAME                                                                        0x700124UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
55477 #define NWS_REG_DBG_SELECT                                                                           0x700128UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
55478 #define NWS_REG_DBG_DWORD_ENABLE                                                                     0x70012cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
55479 #define NWS_REG_DBG_SHIFT                                                                            0x700130UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
55480 #define NWS_REG_DBG_FORCE_VALID                                                                      0x700134UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
55481 #define NWS_REG_DBG_FORCE_FRAME                                                                      0x700138UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
55482 #define NWS_REG_DBGSYN_ALMOST_FULL_THR                                                               0x70013cUL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: K2
55483 #define NWS_REG_DBGSYN_STATUS                                                                        0x700140UL //Access:R    DataWidth:0x5   Debug only: Fill level of dbgmux fifo.  Chips: K2
55484 #define NWS_REG_DBG_SAMPLING_INTERVAL                                                                0x700144UL //Access:RW   DataWidth:0x14  Debug only: Sampling interval * pclk, 2ns to 2ms.  Chips: K2
55485 #define NWS_REG_DBG_REPEAT_THRESHOLD_COUNT                                                           0x700148UL //Access:RW   DataWidth:0x4   Debug only: If 0 or 1, trigger on first occurrence. If greater than 1, wait until counter value match to trigger.  Chips: K2
55486 #define NWS_REG_DBG_POST_TRIGGER_LATENCY_COUNT                                                       0x70014cUL //Access:RW   DataWidth:0x18  Debug only: If greater than 0, delay trigger count value * pclk, 0 to 32ms  Chips: K2
55487 #define NWS_REG_DBG_FW_TRIGGER_ENABLE                                                                0x700150UL //Access:RW   DataWidth:0x1   Debug only: FW trigger is set.  Chips: K2
55488 #define NWS_REG_INT_STS_0                                                                            0x700180UL //Access:R    DataWidth:0xa   Multi Field Register.  Chips: K2
55489     #define NWS_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
55490     #define NWS_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
55491     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2                                                 (0x1<<1) // Autonegotiation resolved to 50g_cr2
55492     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_CR2_SHIFT                                           1
55493     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2                                                 (0x1<<2) // Autonegotiation resolved to 50g_kr2
55494     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_50G_KR2_SHIFT                                           2
55495     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4                                                 (0x1<<3) // Autonegotiation resolved to 40g_cr4
55496     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_CR4_SHIFT                                           3
55497     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4                                                 (0x1<<4) // Autonegotiation resolved to 40g_kr4
55498     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_40G_KR4_SHIFT                                           4
55499     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR                                                  (0x1<<5) // Autonegotiation resolved to 25g_gr
55500     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_GR_SHIFT                                            5
55501     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR                                                  (0x1<<6) // Autonegotiation resolved to 25g_cr
55502     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_CR_SHIFT                                            6
55503     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR                                                  (0x1<<7) // Autonegotiation resolved to 25g_kr
55504     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_25G_KR_SHIFT                                            7
55505     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR                                                  (0x1<<8) // Autonegotiation resolved to 10g_kr
55506     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_10G_KR_SHIFT                                            8
55507     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX                                                   (0x1<<9) // Autonegotiation resolved to 1g_kx
55508     #define NWS_REG_INT_STS_0_LN0_AN_RESOLVE_1G_KX_SHIFT                                             9
55509 #define NWS_REG_INT_MASK_0                                                                           0x700184UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
55510     #define NWS_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.ADDRESS_ERROR .
55511     #define NWS_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
55512     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_CR2 .
55513     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_CR2_SHIFT                                          1
55514     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_50G_KR2 .
55515     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_50G_KR2_SHIFT                                          2
55516     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_CR4 .
55517     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_CR4_SHIFT                                          3
55518     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_40G_KR4 .
55519     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_40G_KR4_SHIFT                                          4
55520     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_GR .
55521     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_GR_SHIFT                                           5
55522     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_CR .
55523     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_CR_SHIFT                                           6
55524     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_25G_KR .
55525     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_25G_KR_SHIFT                                           7
55526     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_10G_KR .
55527     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_10G_KR_SHIFT                                           8
55528     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_0.LN0_AN_RESOLVE_1G_KX .
55529     #define NWS_REG_INT_MASK_0_LN0_AN_RESOLVE_1G_KX_SHIFT                                            9
55530 #define NWS_REG_INT_STS_WR_0                                                                         0x700188UL //Access:WR   DataWidth:0xa   Multi Field Register.  Chips: K2
55531     #define NWS_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
55532     #define NWS_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
55533     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2                                              (0x1<<1) // Autonegotiation resolved to 50g_cr2
55534     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_CR2_SHIFT                                        1
55535     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2                                              (0x1<<2) // Autonegotiation resolved to 50g_kr2
55536     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_50G_KR2_SHIFT                                        2
55537     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4                                              (0x1<<3) // Autonegotiation resolved to 40g_cr4
55538     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_CR4_SHIFT                                        3
55539     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4                                              (0x1<<4) // Autonegotiation resolved to 40g_kr4
55540     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_40G_KR4_SHIFT                                        4
55541     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR                                               (0x1<<5) // Autonegotiation resolved to 25g_gr
55542     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_GR_SHIFT                                         5
55543     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR                                               (0x1<<6) // Autonegotiation resolved to 25g_cr
55544     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_CR_SHIFT                                         6
55545     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR                                               (0x1<<7) // Autonegotiation resolved to 25g_kr
55546     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_25G_KR_SHIFT                                         7
55547     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR                                               (0x1<<8) // Autonegotiation resolved to 10g_kr
55548     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_10G_KR_SHIFT                                         8
55549     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX                                                (0x1<<9) // Autonegotiation resolved to 1g_kx
55550     #define NWS_REG_INT_STS_WR_0_LN0_AN_RESOLVE_1G_KX_SHIFT                                          9
55551 #define NWS_REG_INT_STS_CLR_0                                                                        0x70018cUL //Access:RC   DataWidth:0xa   Multi Field Register.  Chips: K2
55552     #define NWS_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
55553     #define NWS_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
55554     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2                                             (0x1<<1) // Autonegotiation resolved to 50g_cr2
55555     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_CR2_SHIFT                                       1
55556     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2                                             (0x1<<2) // Autonegotiation resolved to 50g_kr2
55557     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_50G_KR2_SHIFT                                       2
55558     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4                                             (0x1<<3) // Autonegotiation resolved to 40g_cr4
55559     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_CR4_SHIFT                                       3
55560     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4                                             (0x1<<4) // Autonegotiation resolved to 40g_kr4
55561     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_40G_KR4_SHIFT                                       4
55562     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR                                              (0x1<<5) // Autonegotiation resolved to 25g_gr
55563     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_GR_SHIFT                                        5
55564     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR                                              (0x1<<6) // Autonegotiation resolved to 25g_cr
55565     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_CR_SHIFT                                        6
55566     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR                                              (0x1<<7) // Autonegotiation resolved to 25g_kr
55567     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_25G_KR_SHIFT                                        7
55568     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR                                              (0x1<<8) // Autonegotiation resolved to 10g_kr
55569     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_10G_KR_SHIFT                                        8
55570     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX                                               (0x1<<9) // Autonegotiation resolved to 1g_kx
55571     #define NWS_REG_INT_STS_CLR_0_LN0_AN_RESOLVE_1G_KX_SHIFT                                         9
55572 #define NWS_REG_INT_STS_1                                                                            0x700190UL //Access:R    DataWidth:0xa   Multi Field Register.  Chips: K2
55573     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2                                                 (0x1<<1) // Autonegotiation resolved to 50g_cr2
55574     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_CR2_SHIFT                                           1
55575     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2                                                 (0x1<<2) // Autonegotiation resolved to 50g_kr2
55576     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_50G_KR2_SHIFT                                           2
55577     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4                                                 (0x1<<3) // Autonegotiation resolved to 40g_cr4
55578     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_CR4_SHIFT                                           3
55579     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4                                                 (0x1<<4) // Autonegotiation resolved to 40g_kr4
55580     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_40G_KR4_SHIFT                                           4
55581     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR                                                  (0x1<<5) // Autonegotiation resolved to 25g_gr
55582     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_GR_SHIFT                                            5
55583     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR                                                  (0x1<<6) // Autonegotiation resolved to 25g_cr
55584     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_CR_SHIFT                                            6
55585     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR                                                  (0x1<<7) // Autonegotiation resolved to 25g_kr
55586     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_25G_KR_SHIFT                                            7
55587     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR                                                  (0x1<<8) // Autonegotiation resolved to 10g_kr
55588     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_10G_KR_SHIFT                                            8
55589     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX                                                   (0x1<<9) // Autonegotiation resolved to 1g_kx
55590     #define NWS_REG_INT_STS_1_LN1_AN_RESOLVE_1G_KX_SHIFT                                             9
55591 #define NWS_REG_INT_MASK_1                                                                           0x700194UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
55592     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_CR2 .
55593     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_CR2_SHIFT                                          1
55594     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_50G_KR2 .
55595     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_50G_KR2_SHIFT                                          2
55596     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_CR4 .
55597     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_CR4_SHIFT                                          3
55598     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_40G_KR4 .
55599     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_40G_KR4_SHIFT                                          4
55600     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_GR .
55601     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_GR_SHIFT                                           5
55602     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_CR .
55603     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_CR_SHIFT                                           6
55604     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_25G_KR .
55605     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_25G_KR_SHIFT                                           7
55606     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_10G_KR .
55607     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_10G_KR_SHIFT                                           8
55608     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_1.LN1_AN_RESOLVE_1G_KX .
55609     #define NWS_REG_INT_MASK_1_LN1_AN_RESOLVE_1G_KX_SHIFT                                            9
55610 #define NWS_REG_INT_STS_WR_1                                                                         0x700198UL //Access:WR   DataWidth:0xa   Multi Field Register.  Chips: K2
55611     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2                                              (0x1<<1) // Autonegotiation resolved to 50g_cr2
55612     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_CR2_SHIFT                                        1
55613     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2                                              (0x1<<2) // Autonegotiation resolved to 50g_kr2
55614     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_50G_KR2_SHIFT                                        2
55615     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4                                              (0x1<<3) // Autonegotiation resolved to 40g_cr4
55616     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_CR4_SHIFT                                        3
55617     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4                                              (0x1<<4) // Autonegotiation resolved to 40g_kr4
55618     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_40G_KR4_SHIFT                                        4
55619     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR                                               (0x1<<5) // Autonegotiation resolved to 25g_gr
55620     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_GR_SHIFT                                         5
55621     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR                                               (0x1<<6) // Autonegotiation resolved to 25g_cr
55622     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_CR_SHIFT                                         6
55623     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR                                               (0x1<<7) // Autonegotiation resolved to 25g_kr
55624     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_25G_KR_SHIFT                                         7
55625     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR                                               (0x1<<8) // Autonegotiation resolved to 10g_kr
55626     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_10G_KR_SHIFT                                         8
55627     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX                                                (0x1<<9) // Autonegotiation resolved to 1g_kx
55628     #define NWS_REG_INT_STS_WR_1_LN1_AN_RESOLVE_1G_KX_SHIFT                                          9
55629 #define NWS_REG_INT_STS_CLR_1                                                                        0x70019cUL //Access:RC   DataWidth:0xa   Multi Field Register.  Chips: K2
55630     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2                                             (0x1<<1) // Autonegotiation resolved to 50g_cr2
55631     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_CR2_SHIFT                                       1
55632     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2                                             (0x1<<2) // Autonegotiation resolved to 50g_kr2
55633     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_50G_KR2_SHIFT                                       2
55634     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4                                             (0x1<<3) // Autonegotiation resolved to 40g_cr4
55635     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_CR4_SHIFT                                       3
55636     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4                                             (0x1<<4) // Autonegotiation resolved to 40g_kr4
55637     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_40G_KR4_SHIFT                                       4
55638     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR                                              (0x1<<5) // Autonegotiation resolved to 25g_gr
55639     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_GR_SHIFT                                        5
55640     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR                                              (0x1<<6) // Autonegotiation resolved to 25g_cr
55641     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_CR_SHIFT                                        6
55642     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR                                              (0x1<<7) // Autonegotiation resolved to 25g_kr
55643     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_25G_KR_SHIFT                                        7
55644     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR                                              (0x1<<8) // Autonegotiation resolved to 10g_kr
55645     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_10G_KR_SHIFT                                        8
55646     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX                                               (0x1<<9) // Autonegotiation resolved to 1g_kx
55647     #define NWS_REG_INT_STS_CLR_1_LN1_AN_RESOLVE_1G_KX_SHIFT                                         9
55648 #define NWS_REG_INT_STS_2                                                                            0x7001a0UL //Access:R    DataWidth:0xa   Multi Field Register.  Chips: K2
55649     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2                                                 (0x1<<1) // Autonegotiation resolved to 50g_cr2
55650     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_CR2_SHIFT                                           1
55651     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2                                                 (0x1<<2) // Autonegotiation resolved to 50g_kr2
55652     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_50G_KR2_SHIFT                                           2
55653     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4                                                 (0x1<<3) // Autonegotiation resolved to 40g_cr4
55654     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_CR4_SHIFT                                           3
55655     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4                                                 (0x1<<4) // Autonegotiation resolved to 40g_kr4
55656     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_40G_KR4_SHIFT                                           4
55657     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR                                                  (0x1<<5) // Autonegotiation resolved to 25g_gr
55658     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_GR_SHIFT                                            5
55659     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR                                                  (0x1<<6) // Autonegotiation resolved to 25g_cr
55660     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_CR_SHIFT                                            6
55661     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR                                                  (0x1<<7) // Autonegotiation resolved to 25g_kr
55662     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_25G_KR_SHIFT                                            7
55663     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR                                                  (0x1<<8) // Autonegotiation resolved to 10g_kr
55664     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_10G_KR_SHIFT                                            8
55665     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX                                                   (0x1<<9) // Autonegotiation resolved to 1g_kx
55666     #define NWS_REG_INT_STS_2_LN2_AN_RESOLVE_1G_KX_SHIFT                                             9
55667 #define NWS_REG_INT_MASK_2                                                                           0x7001a4UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
55668     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_CR2 .
55669     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_CR2_SHIFT                                          1
55670     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_50G_KR2 .
55671     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_50G_KR2_SHIFT                                          2
55672     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_CR4 .
55673     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_CR4_SHIFT                                          3
55674     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_40G_KR4 .
55675     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_40G_KR4_SHIFT                                          4
55676     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_GR .
55677     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_GR_SHIFT                                           5
55678     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_CR .
55679     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_CR_SHIFT                                           6
55680     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_25G_KR .
55681     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_25G_KR_SHIFT                                           7
55682     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_10G_KR .
55683     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_10G_KR_SHIFT                                           8
55684     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_2.LN2_AN_RESOLVE_1G_KX .
55685     #define NWS_REG_INT_MASK_2_LN2_AN_RESOLVE_1G_KX_SHIFT                                            9
55686 #define NWS_REG_INT_STS_WR_2                                                                         0x7001a8UL //Access:WR   DataWidth:0xa   Multi Field Register.  Chips: K2
55687     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2                                              (0x1<<1) // Autonegotiation resolved to 50g_cr2
55688     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_CR2_SHIFT                                        1
55689     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2                                              (0x1<<2) // Autonegotiation resolved to 50g_kr2
55690     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_50G_KR2_SHIFT                                        2
55691     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4                                              (0x1<<3) // Autonegotiation resolved to 40g_cr4
55692     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_CR4_SHIFT                                        3
55693     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4                                              (0x1<<4) // Autonegotiation resolved to 40g_kr4
55694     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_40G_KR4_SHIFT                                        4
55695     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR                                               (0x1<<5) // Autonegotiation resolved to 25g_gr
55696     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_GR_SHIFT                                         5
55697     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR                                               (0x1<<6) // Autonegotiation resolved to 25g_cr
55698     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_CR_SHIFT                                         6
55699     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR                                               (0x1<<7) // Autonegotiation resolved to 25g_kr
55700     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_25G_KR_SHIFT                                         7
55701     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR                                               (0x1<<8) // Autonegotiation resolved to 10g_kr
55702     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_10G_KR_SHIFT                                         8
55703     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX                                                (0x1<<9) // Autonegotiation resolved to 1g_kx
55704     #define NWS_REG_INT_STS_WR_2_LN2_AN_RESOLVE_1G_KX_SHIFT                                          9
55705 #define NWS_REG_INT_STS_CLR_2                                                                        0x7001acUL //Access:RC   DataWidth:0xa   Multi Field Register.  Chips: K2
55706     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2                                             (0x1<<1) // Autonegotiation resolved to 50g_cr2
55707     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_CR2_SHIFT                                       1
55708     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2                                             (0x1<<2) // Autonegotiation resolved to 50g_kr2
55709     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_50G_KR2_SHIFT                                       2
55710     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4                                             (0x1<<3) // Autonegotiation resolved to 40g_cr4
55711     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_CR4_SHIFT                                       3
55712     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4                                             (0x1<<4) // Autonegotiation resolved to 40g_kr4
55713     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_40G_KR4_SHIFT                                       4
55714     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR                                              (0x1<<5) // Autonegotiation resolved to 25g_gr
55715     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_GR_SHIFT                                        5
55716     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR                                              (0x1<<6) // Autonegotiation resolved to 25g_cr
55717     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_CR_SHIFT                                        6
55718     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR                                              (0x1<<7) // Autonegotiation resolved to 25g_kr
55719     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_25G_KR_SHIFT                                        7
55720     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR                                              (0x1<<8) // Autonegotiation resolved to 10g_kr
55721     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_10G_KR_SHIFT                                        8
55722     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX                                               (0x1<<9) // Autonegotiation resolved to 1g_kx
55723     #define NWS_REG_INT_STS_CLR_2_LN2_AN_RESOLVE_1G_KX_SHIFT                                         9
55724 #define NWS_REG_INT_STS_3                                                                            0x7001b0UL //Access:R    DataWidth:0xa   Multi Field Register.  Chips: K2
55725     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2                                                 (0x1<<1) // Autonegotiation resolved to 50g_cr2
55726     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_CR2_SHIFT                                           1
55727     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2                                                 (0x1<<2) // Autonegotiation resolved to 50g_kr2
55728     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_50G_KR2_SHIFT                                           2
55729     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4                                                 (0x1<<3) // Autonegotiation resolved to 40g_cr4
55730     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_CR4_SHIFT                                           3
55731     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4                                                 (0x1<<4) // Autonegotiation resolved to 40g_kr4
55732     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_40G_KR4_SHIFT                                           4
55733     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR                                                  (0x1<<5) // Autonegotiation resolved to 25g_gr
55734     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_GR_SHIFT                                            5
55735     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR                                                  (0x1<<6) // Autonegotiation resolved to 25g_cr
55736     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_CR_SHIFT                                            6
55737     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR                                                  (0x1<<7) // Autonegotiation resolved to 25g_kr
55738     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_25G_KR_SHIFT                                            7
55739     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR                                                  (0x1<<8) // Autonegotiation resolved to 10g_kr
55740     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_10G_KR_SHIFT                                            8
55741     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX                                                   (0x1<<9) // Autonegotiation resolved to 1g_kx
55742     #define NWS_REG_INT_STS_3_LN3_AN_RESOLVE_1G_KX_SHIFT                                             9
55743 #define NWS_REG_INT_MASK_3                                                                           0x7001b4UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
55744     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2                                                (0x1<<1) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_CR2 .
55745     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_CR2_SHIFT                                          1
55746     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_50G_KR2 .
55747     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_50G_KR2_SHIFT                                          2
55748     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_CR4 .
55749     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_CR4_SHIFT                                          3
55750     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_40G_KR4 .
55751     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_40G_KR4_SHIFT                                          4
55752     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR                                                 (0x1<<5) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_GR .
55753     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_GR_SHIFT                                           5
55754     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_CR .
55755     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_CR_SHIFT                                           6
55756     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_25G_KR .
55757     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_25G_KR_SHIFT                                           7
55758     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_10G_KR .
55759     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_10G_KR_SHIFT                                           8
55760     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX                                                  (0x1<<9) // This bit masks, when set, the Interrupt bit: NWS_REG_INT_STS_3.LN3_AN_RESOLVE_1G_KX .
55761     #define NWS_REG_INT_MASK_3_LN3_AN_RESOLVE_1G_KX_SHIFT                                            9
55762 #define NWS_REG_INT_STS_WR_3                                                                         0x7001b8UL //Access:WR   DataWidth:0xa   Multi Field Register.  Chips: K2
55763     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2                                              (0x1<<1) // Autonegotiation resolved to 50g_cr2
55764     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_CR2_SHIFT                                        1
55765     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2                                              (0x1<<2) // Autonegotiation resolved to 50g_kr2
55766     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_50G_KR2_SHIFT                                        2
55767     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4                                              (0x1<<3) // Autonegotiation resolved to 40g_cr4
55768     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_CR4_SHIFT                                        3
55769     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4                                              (0x1<<4) // Autonegotiation resolved to 40g_kr4
55770     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_40G_KR4_SHIFT                                        4
55771     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR                                               (0x1<<5) // Autonegotiation resolved to 25g_gr
55772     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_GR_SHIFT                                         5
55773     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR                                               (0x1<<6) // Autonegotiation resolved to 25g_cr
55774     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_CR_SHIFT                                         6
55775     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR                                               (0x1<<7) // Autonegotiation resolved to 25g_kr
55776     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_25G_KR_SHIFT                                         7
55777     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR                                               (0x1<<8) // Autonegotiation resolved to 10g_kr
55778     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_10G_KR_SHIFT                                         8
55779     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX                                                (0x1<<9) // Autonegotiation resolved to 1g_kx
55780     #define NWS_REG_INT_STS_WR_3_LN3_AN_RESOLVE_1G_KX_SHIFT                                          9
55781 #define NWS_REG_INT_STS_CLR_3                                                                        0x7001bcUL //Access:RC   DataWidth:0xa   Multi Field Register.  Chips: K2
55782     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2                                             (0x1<<1) // Autonegotiation resolved to 50g_cr2
55783     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_CR2_SHIFT                                       1
55784     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2                                             (0x1<<2) // Autonegotiation resolved to 50g_kr2
55785     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_50G_KR2_SHIFT                                       2
55786     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4                                             (0x1<<3) // Autonegotiation resolved to 40g_cr4
55787     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_CR4_SHIFT                                       3
55788     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4                                             (0x1<<4) // Autonegotiation resolved to 40g_kr4
55789     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_40G_KR4_SHIFT                                       4
55790     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR                                              (0x1<<5) // Autonegotiation resolved to 25g_gr
55791     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_GR_SHIFT                                        5
55792     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR                                              (0x1<<6) // Autonegotiation resolved to 25g_cr
55793     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_CR_SHIFT                                        6
55794     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR                                              (0x1<<7) // Autonegotiation resolved to 25g_kr
55795     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_25G_KR_SHIFT                                        7
55796     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR                                              (0x1<<8) // Autonegotiation resolved to 10g_kr
55797     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_10G_KR_SHIFT                                        8
55798     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX                                               (0x1<<9) // Autonegotiation resolved to 1g_kx
55799     #define NWS_REG_INT_STS_CLR_3_LN3_AN_RESOLVE_1G_KX_SHIFT                                         9
55800 #define NWS_REG_PRTY_MASK_H_0                                                                        0x700204UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: K2
55801     #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
55802     #define NWS_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                            0
55803     #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
55804     #define NWS_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                            1
55805     #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
55806     #define NWS_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            2
55807     #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: NWS_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
55808     #define NWS_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            3
55809 #define NWS_REG_MEM_ECC_EVENTS                                                                       0x700210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
55810 #define NWS_REG_MEM003_I_MEM_DFT                                                                     0x700218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nws.i_nws_internal_memory_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
55811 #define NWS_REG_MEM001_I_MEM_DFT                                                                     0x70021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nws.i_nws_data_memory_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
55812 #define NWS_REG_MEM004_I_MEM_DFT                                                                     0x700220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nws.i_nws_program_memory_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
55813 #define NWS_REG_MEM002_I_MEM_DFT                                                                     0x700224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nws.i_nws_eth_dbgsyn_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
55814 #define NWS_REG_NWS_CMU                                                                              0x720000UL //Access:RW   DataWidth:0x8   PHY Top registers = 0-0x7ff. CMU0 registers    = 0x0800-0x0bff. CMU1 registers    = 0x0c00-0x0fff. Reserved          = 0x1000-0x17ff. LANE0 registers   = 0x1800-0x1fff. LANE1 registers   = 0x2000-0x27ff. LANE2 registers   = 0x2800-0x2fff. LANE3 registers   = 0x3000-0x37ff. Please see IPXACT_Capri_4l2c.xml for details.  Chips: K2
55815 #define NWS_REG_NWS_CMU_SIZE                                                                         20479
55816 #define NWS_REG_NWS_DATA_RAM_ACCESS                                                                  0x740000UL //Access:RW   DataWidth:0x20  Used to load operating tables into data ram. Each register location is 4 bytes in ram. bits[31:24] = ram address [0] bits[23:16] = ram address [1] bits[15:8]  = ram address [2] bits[7:0]   = ram address [3] register 0 = ram location [3:0] register 1 = ram location [7:4] register 2 = ram location [11:8]  Chips: K2
55817 #define NWS_REG_NWS_DATA_RAM_ACCESS_SIZE                                                             2048
55818 #define NWS_REG_NWS_PROGRAM_RAM_ACCESS                                                               0x760000UL //Access:RW   DataWidth:0x20  Used to load operating firmware into program ram. Each register location is 4 bytes in ram. bits[31:24] = ram address [0] bits[23:16] = ram address [1] bits[15:8]  = ram address [2] bits[7:0]   = ram address [3] register 0 = ram location [3:0] register 1 = ram location [7:4] register 2 = ram location [11:8]  Chips: K2
55819 #define NWS_REG_NWS_PROGRAM_RAM_ACCESS_SIZE                                                          32768
55820 #define NWM_REG_INT_STS                                                                              0x800004UL //Access:R    DataWidth:0x18  Multi Field Register.  Chips: K2
55821     #define NWM_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
55822     #define NWM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
55823     #define NWM_REG_INT_STS_TX_OVERFLOW_0                                                            (0x1<<1) // TX fifo overflow
55824     #define NWM_REG_INT_STS_TX_OVERFLOW_0_SHIFT                                                      1
55825     #define NWM_REG_INT_STS_TX_UNDERFLOW_0                                                           (0x1<<2) // TX fifo underflow
55826     #define NWM_REG_INT_STS_TX_UNDERFLOW_0_SHIFT                                                     2
55827     #define NWM_REG_INT_STS_TX_OVERFLOW_1                                                            (0x1<<3) // TX fifo overflow
55828     #define NWM_REG_INT_STS_TX_OVERFLOW_1_SHIFT                                                      3
55829     #define NWM_REG_INT_STS_TX_UNDERFLOW_1                                                           (0x1<<4) // TX fifo underflow
55830     #define NWM_REG_INT_STS_TX_UNDERFLOW_1_SHIFT                                                     4
55831     #define NWM_REG_INT_STS_TX_OVERFLOW_2                                                            (0x1<<5) // TX fifo overflow
55832     #define NWM_REG_INT_STS_TX_OVERFLOW_2_SHIFT                                                      5
55833     #define NWM_REG_INT_STS_TX_UNDERFLOW_2                                                           (0x1<<6) // TX fifo underflow
55834     #define NWM_REG_INT_STS_TX_UNDERFLOW_2_SHIFT                                                     6
55835     #define NWM_REG_INT_STS_TX_OVERFLOW_3                                                            (0x1<<7) // TX fifo overflow
55836     #define NWM_REG_INT_STS_TX_OVERFLOW_3_SHIFT                                                      7
55837     #define NWM_REG_INT_STS_TX_UNDERFLOW_3                                                           (0x1<<8) // TX fifo underflow
55838     #define NWM_REG_INT_STS_TX_UNDERFLOW_3_SHIFT                                                     8
55839     #define NWM_REG_INT_STS_LN0_AT_10M                                                               (0x1<<16) // Lane 0 Resolved to 10Mb rate
55840     #define NWM_REG_INT_STS_LN0_AT_10M_SHIFT                                                         16
55841     #define NWM_REG_INT_STS_LN0_AT_100M                                                              (0x1<<17) // Lane 0 Resolved to 100Mb rate
55842     #define NWM_REG_INT_STS_LN0_AT_100M_SHIFT                                                        17
55843     #define NWM_REG_INT_STS_LN1_AT_10M                                                               (0x1<<18) // Lane 1 Resolved to 10Mb rate
55844     #define NWM_REG_INT_STS_LN1_AT_10M_SHIFT                                                         18
55845     #define NWM_REG_INT_STS_LN1_AT_100M                                                              (0x1<<19) // Lane 1 Resolved to 100Mb rate
55846     #define NWM_REG_INT_STS_LN1_AT_100M_SHIFT                                                        19
55847     #define NWM_REG_INT_STS_LN2_AT_10M                                                               (0x1<<20) // Lane 2 Resolved to 10Mb rate
55848     #define NWM_REG_INT_STS_LN2_AT_10M_SHIFT                                                         20
55849     #define NWM_REG_INT_STS_LN2_AT_100M                                                              (0x1<<21) // Lane 2 Resolved to 100Mb rate
55850     #define NWM_REG_INT_STS_LN2_AT_100M_SHIFT                                                        21
55851     #define NWM_REG_INT_STS_LN3_AT_10M                                                               (0x1<<22) // Lane 3 Resolved to 10Mb rate
55852     #define NWM_REG_INT_STS_LN3_AT_10M_SHIFT                                                         22
55853     #define NWM_REG_INT_STS_LN3_AT_100M                                                              (0x1<<23) // Lane 3 Resolved to 100Mb rate
55854     #define NWM_REG_INT_STS_LN3_AT_100M_SHIFT                                                        23
55855 #define NWM_REG_INT_MASK                                                                             0x800008UL //Access:RW   DataWidth:0x18  Multi Field Register.  Chips: K2
55856     #define NWM_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.ADDRESS_ERROR .
55857     #define NWM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
55858     #define NWM_REG_INT_MASK_TX_OVERFLOW_0                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_0 .
55859     #define NWM_REG_INT_MASK_TX_OVERFLOW_0_SHIFT                                                     1
55860     #define NWM_REG_INT_MASK_TX_UNDERFLOW_0                                                          (0x1<<2) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_0 .
55861     #define NWM_REG_INT_MASK_TX_UNDERFLOW_0_SHIFT                                                    2
55862     #define NWM_REG_INT_MASK_TX_OVERFLOW_1                                                           (0x1<<3) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_1 .
55863     #define NWM_REG_INT_MASK_TX_OVERFLOW_1_SHIFT                                                     3
55864     #define NWM_REG_INT_MASK_TX_UNDERFLOW_1                                                          (0x1<<4) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_1 .
55865     #define NWM_REG_INT_MASK_TX_UNDERFLOW_1_SHIFT                                                    4
55866     #define NWM_REG_INT_MASK_TX_OVERFLOW_2                                                           (0x1<<5) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_2 .
55867     #define NWM_REG_INT_MASK_TX_OVERFLOW_2_SHIFT                                                     5
55868     #define NWM_REG_INT_MASK_TX_UNDERFLOW_2                                                          (0x1<<6) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_2 .
55869     #define NWM_REG_INT_MASK_TX_UNDERFLOW_2_SHIFT                                                    6
55870     #define NWM_REG_INT_MASK_TX_OVERFLOW_3                                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_OVERFLOW_3 .
55871     #define NWM_REG_INT_MASK_TX_OVERFLOW_3_SHIFT                                                     7
55872     #define NWM_REG_INT_MASK_TX_UNDERFLOW_3                                                          (0x1<<8) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.TX_UNDERFLOW_3 .
55873     #define NWM_REG_INT_MASK_TX_UNDERFLOW_3_SHIFT                                                    8
55874     #define NWM_REG_INT_MASK_LN0_AT_10M                                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN0_AT_10M .
55875     #define NWM_REG_INT_MASK_LN0_AT_10M_SHIFT                                                        16
55876     #define NWM_REG_INT_MASK_LN0_AT_100M                                                             (0x1<<17) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN0_AT_100M .
55877     #define NWM_REG_INT_MASK_LN0_AT_100M_SHIFT                                                       17
55878     #define NWM_REG_INT_MASK_LN1_AT_10M                                                              (0x1<<18) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN1_AT_10M .
55879     #define NWM_REG_INT_MASK_LN1_AT_10M_SHIFT                                                        18
55880     #define NWM_REG_INT_MASK_LN1_AT_100M                                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN1_AT_100M .
55881     #define NWM_REG_INT_MASK_LN1_AT_100M_SHIFT                                                       19
55882     #define NWM_REG_INT_MASK_LN2_AT_10M                                                              (0x1<<20) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN2_AT_10M .
55883     #define NWM_REG_INT_MASK_LN2_AT_10M_SHIFT                                                        20
55884     #define NWM_REG_INT_MASK_LN2_AT_100M                                                             (0x1<<21) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN2_AT_100M .
55885     #define NWM_REG_INT_MASK_LN2_AT_100M_SHIFT                                                       21
55886     #define NWM_REG_INT_MASK_LN3_AT_10M                                                              (0x1<<22) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN3_AT_10M .
55887     #define NWM_REG_INT_MASK_LN3_AT_10M_SHIFT                                                        22
55888     #define NWM_REG_INT_MASK_LN3_AT_100M                                                             (0x1<<23) // This bit masks, when set, the Interrupt bit: NWM_REG_INT_STS.LN3_AT_100M .
55889     #define NWM_REG_INT_MASK_LN3_AT_100M_SHIFT                                                       23
55890 #define NWM_REG_INT_STS_WR                                                                           0x80000cUL //Access:WR   DataWidth:0x18  Multi Field Register.  Chips: K2
55891     #define NWM_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
55892     #define NWM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
55893     #define NWM_REG_INT_STS_WR_TX_OVERFLOW_0                                                         (0x1<<1) // TX fifo overflow
55894     #define NWM_REG_INT_STS_WR_TX_OVERFLOW_0_SHIFT                                                   1
55895     #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_0                                                        (0x1<<2) // TX fifo underflow
55896     #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_0_SHIFT                                                  2
55897     #define NWM_REG_INT_STS_WR_TX_OVERFLOW_1                                                         (0x1<<3) // TX fifo overflow
55898     #define NWM_REG_INT_STS_WR_TX_OVERFLOW_1_SHIFT                                                   3
55899     #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_1                                                        (0x1<<4) // TX fifo underflow
55900     #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_1_SHIFT                                                  4
55901     #define NWM_REG_INT_STS_WR_TX_OVERFLOW_2                                                         (0x1<<5) // TX fifo overflow
55902     #define NWM_REG_INT_STS_WR_TX_OVERFLOW_2_SHIFT                                                   5
55903     #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_2                                                        (0x1<<6) // TX fifo underflow
55904     #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_2_SHIFT                                                  6
55905     #define NWM_REG_INT_STS_WR_TX_OVERFLOW_3                                                         (0x1<<7) // TX fifo overflow
55906     #define NWM_REG_INT_STS_WR_TX_OVERFLOW_3_SHIFT                                                   7
55907     #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_3                                                        (0x1<<8) // TX fifo underflow
55908     #define NWM_REG_INT_STS_WR_TX_UNDERFLOW_3_SHIFT                                                  8
55909     #define NWM_REG_INT_STS_WR_LN0_AT_10M                                                            (0x1<<16) // Lane 0 Resolved to 10Mb rate
55910     #define NWM_REG_INT_STS_WR_LN0_AT_10M_SHIFT                                                      16
55911     #define NWM_REG_INT_STS_WR_LN0_AT_100M                                                           (0x1<<17) // Lane 0 Resolved to 100Mb rate
55912     #define NWM_REG_INT_STS_WR_LN0_AT_100M_SHIFT                                                     17
55913     #define NWM_REG_INT_STS_WR_LN1_AT_10M                                                            (0x1<<18) // Lane 1 Resolved to 10Mb rate
55914     #define NWM_REG_INT_STS_WR_LN1_AT_10M_SHIFT                                                      18
55915     #define NWM_REG_INT_STS_WR_LN1_AT_100M                                                           (0x1<<19) // Lane 1 Resolved to 100Mb rate
55916     #define NWM_REG_INT_STS_WR_LN1_AT_100M_SHIFT                                                     19
55917     #define NWM_REG_INT_STS_WR_LN2_AT_10M                                                            (0x1<<20) // Lane 2 Resolved to 10Mb rate
55918     #define NWM_REG_INT_STS_WR_LN2_AT_10M_SHIFT                                                      20
55919     #define NWM_REG_INT_STS_WR_LN2_AT_100M                                                           (0x1<<21) // Lane 2 Resolved to 100Mb rate
55920     #define NWM_REG_INT_STS_WR_LN2_AT_100M_SHIFT                                                     21
55921     #define NWM_REG_INT_STS_WR_LN3_AT_10M                                                            (0x1<<22) // Lane 3 Resolved to 10Mb rate
55922     #define NWM_REG_INT_STS_WR_LN3_AT_10M_SHIFT                                                      22
55923     #define NWM_REG_INT_STS_WR_LN3_AT_100M                                                           (0x1<<23) // Lane 3 Resolved to 100Mb rate
55924     #define NWM_REG_INT_STS_WR_LN3_AT_100M_SHIFT                                                     23
55925 #define NWM_REG_INT_STS_CLR                                                                          0x800010UL //Access:RC   DataWidth:0x18  Multi Field Register.  Chips: K2
55926     #define NWM_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
55927     #define NWM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
55928     #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_0                                                        (0x1<<1) // TX fifo overflow
55929     #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_0_SHIFT                                                  1
55930     #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_0                                                       (0x1<<2) // TX fifo underflow
55931     #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_0_SHIFT                                                 2
55932     #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_1                                                        (0x1<<3) // TX fifo overflow
55933     #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_1_SHIFT                                                  3
55934     #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_1                                                       (0x1<<4) // TX fifo underflow
55935     #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_1_SHIFT                                                 4
55936     #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_2                                                        (0x1<<5) // TX fifo overflow
55937     #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_2_SHIFT                                                  5
55938     #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_2                                                       (0x1<<6) // TX fifo underflow
55939     #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_2_SHIFT                                                 6
55940     #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_3                                                        (0x1<<7) // TX fifo overflow
55941     #define NWM_REG_INT_STS_CLR_TX_OVERFLOW_3_SHIFT                                                  7
55942     #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_3                                                       (0x1<<8) // TX fifo underflow
55943     #define NWM_REG_INT_STS_CLR_TX_UNDERFLOW_3_SHIFT                                                 8
55944     #define NWM_REG_INT_STS_CLR_LN0_AT_10M                                                           (0x1<<16) // Lane 0 Resolved to 10Mb rate
55945     #define NWM_REG_INT_STS_CLR_LN0_AT_10M_SHIFT                                                     16
55946     #define NWM_REG_INT_STS_CLR_LN0_AT_100M                                                          (0x1<<17) // Lane 0 Resolved to 100Mb rate
55947     #define NWM_REG_INT_STS_CLR_LN0_AT_100M_SHIFT                                                    17
55948     #define NWM_REG_INT_STS_CLR_LN1_AT_10M                                                           (0x1<<18) // Lane 1 Resolved to 10Mb rate
55949     #define NWM_REG_INT_STS_CLR_LN1_AT_10M_SHIFT                                                     18
55950     #define NWM_REG_INT_STS_CLR_LN1_AT_100M                                                          (0x1<<19) // Lane 1 Resolved to 100Mb rate
55951     #define NWM_REG_INT_STS_CLR_LN1_AT_100M_SHIFT                                                    19
55952     #define NWM_REG_INT_STS_CLR_LN2_AT_10M                                                           (0x1<<20) // Lane 2 Resolved to 10Mb rate
55953     #define NWM_REG_INT_STS_CLR_LN2_AT_10M_SHIFT                                                     20
55954     #define NWM_REG_INT_STS_CLR_LN2_AT_100M                                                          (0x1<<21) // Lane 2 Resolved to 100Mb rate
55955     #define NWM_REG_INT_STS_CLR_LN2_AT_100M_SHIFT                                                    21
55956     #define NWM_REG_INT_STS_CLR_LN3_AT_10M                                                           (0x1<<22) // Lane 3 Resolved to 10Mb rate
55957     #define NWM_REG_INT_STS_CLR_LN3_AT_10M_SHIFT                                                     22
55958     #define NWM_REG_INT_STS_CLR_LN3_AT_100M                                                          (0x1<<23) // Lane 3 Resolved to 100Mb rate
55959     #define NWM_REG_INT_STS_CLR_LN3_AT_100M_SHIFT                                                    23
55960 #define NWM_REG_MAC0_PEER_DELAY                                                                      0x800014UL //Access:RW   DataWidth:0x1e  A so-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to the MAC reference guide 1-step description on usage. Reset = 0  Chips: K2
55961 #define NWM_REG_MAC1_PEER_DELAY                                                                      0x800018UL //Access:RW   DataWidth:0x1e  A so-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to the MAC reference guide 1-step description on usage. Reset = 0  Chips: K2
55962 #define NWM_REG_MAC2_PEER_DELAY                                                                      0x80001cUL //Access:RW   DataWidth:0x1e  A so-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to the MAC reference guide 1-step description on usage. Reset = 0  Chips: K2
55963 #define NWM_REG_MAC3_PEER_DELAY                                                                      0x800020UL //Access:RW   DataWidth:0x1e  A so-called Peer Delay value that can be added to the correction field for all 1-step updates Refer to the MAC reference guide 1-step description on usage. Reset = 0  Chips: K2
55964 #define NWM_REG_FEC_LOCKED                                                                           0x800024UL //Access:R    DataWidth:0x8   Per virtual lane indication that FEC has acheived lock on the FEC boundaries and valid data is being decoded.  Chips: K2
55965 #define NWM_REG_LN0_LATCHED_STATUS                                                                   0x800028UL //Access:RC   DataWidth:0xa   The following bits a latched high.  All bits are cleared when the register is read. bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Remote_fault indicator has transitioned from Low to High since last read. bit 7 - LINK_INTERRUPT_LH Link Interrupt Received indicator has transitioned from Low to High since last read. bit 6 - LPI_RECEIVED_LH LPI Received indicator has transitioned from Low to High since last read. bit 5 - HI_BER_LH HI BER indicator has transitioned from Low to High since last read. bit 4 - HI_BER_LL HI BER indicator has transitioned from High to Low since last read. bit 3 - LINK_STATUS_LH Link Status indicator has transitioned from Low to High since last read. bit 2 - LINK_STATUS_LL Link Status indicator has transitioned from High to Low since last read. bit 1 - BLOCK_LOCK_LH Link Status indicator has transitioned from Low to High since last read. bit 0 - BLOCK_LOCK_LL Link Status indicator has transitioned from High to Low since last read.  Chips: K2
55966 #define NWM_REG_LN0_LIVE_STS                                                                         0x80002cUL //Access:R    DataWidth:0x7   Multi Field Register.  Chips: K2
55967     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LOCAL_FAULT                                                (0x1<<6) // Live Local Fault Indicator
55968     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LOCAL_FAULT_SHIFT                                          6
55969     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_REMOTE_FAULT                                               (0x1<<7) // Live Remote Fault Indicator
55970     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_REMOTE_FAULT_SHIFT                                         7
55971     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_INTERRUPT                                             (0x1<<8) // Live Link Interrupt Indicator
55972     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_INTERRUPT_SHIFT                                       8
55973     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LPI_RECEIVED                                               (0x1<<9) // Live LPI Received Indicator
55974     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LPI_RECEIVED_SHIFT                                         9
55975     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_HI_BER                                                     (0x1<<10) // Live Hi BER Indicator
55976     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_HI_BER_SHIFT                                               10
55977     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_STATUS                                                (0x1<<11) // Live Link Status Indicator
55978     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_LINK_STATUS_SHIFT                                          11
55979     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_BLOCK_LOCK                                                 (0x1<<12) // Live block lock Indicator
55980     #define NWM_REG_LN0_LIVE_STS_LN0_LIVE_BLOCK_LOCK_SHIFT                                           12
55981 #define NWM_REG_LN1_LATCHED_STATUS                                                                   0x800030UL //Access:RC   DataWidth:0xa   The following bits a latched high.  All bits are cleared when the register is read. bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Remote_fault indicator has transitioned from Low to High since last read. bit 7 - LINK_INTERRUPT_LH Link Interrupt Received indicator has transitioned from Low to High since last read. bit 6 - LPI_RECEIVED_LH LPI Received indicator has transitioned from Low to High since last read. bit 5 - HI_BER_LH HI BER indicator has transitioned from Low to High since last read. bit 4 - HI_BER_LL HI BER indicator has transitioned from High to Low since last read. bit 3 - LINK_STATUS_LH Link Status indicator has transitioned from Low to High since last read. bit 2 - LINK_STATUS_LL Link Status indicator has transitioned from High to Low since last read. bit 1 - BLOCK_LOCK_LH Link Status indicator has transitioned from Low to High since last read. bit 0 - BLOCK_LOCK_LL Link Status indicator has transitioned from High to Low since last read.  Chips: K2
55982 #define NWM_REG_LN1_LIVE_STS                                                                         0x800034UL //Access:R    DataWidth:0x7   Multi Field Register.  Chips: K2
55983     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LOCAL_FAULT                                                (0x1<<6) // Live Local Fault Indicator
55984     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LOCAL_FAULT_SHIFT                                          6
55985     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_REMOTE_FAULT                                               (0x1<<7) // Live Remote Fault Indicator
55986     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_REMOTE_FAULT_SHIFT                                         7
55987     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_INTERRUPT                                             (0x1<<8) // Live Link Interrupt Indicator
55988     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_INTERRUPT_SHIFT                                       8
55989     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LPI_RECEIVED                                               (0x1<<9) // Live LPI Received Indicator
55990     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LPI_RECEIVED_SHIFT                                         9
55991     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_HI_BER                                                     (0x1<<10) // Live Hi BER Indicator
55992     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_HI_BER_SHIFT                                               10
55993     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_STATUS                                                (0x1<<11) // Live Link Status Indicator
55994     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_LINK_STATUS_SHIFT                                          11
55995     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_BLOCK_LOCK                                                 (0x1<<12) // Live block lock Indicator
55996     #define NWM_REG_LN1_LIVE_STS_LN1_LIVE_BLOCK_LOCK_SHIFT                                           12
55997 #define NWM_REG_LN2_LATCHED_STATUS                                                                   0x800038UL //Access:RC   DataWidth:0xa   The following bits a latched high.  All bits are cleared when the register is read. bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Remote_fault indicator has transitioned from Low to High since last read. bit 7 - LINK_INTERRUPT_LH Link Interrupt Received indicator has transitioned from Low to High since last read. bit 6 - LPI_RECEIVED_LH LPI Received indicator has transitioned from Low to High since last read. bit 5 - HI_BER_LH HI BER indicator has transitioned from Low to High since last read. bit 4 - HI_BER_LL HI BER indicator has transitioned from High to Low since last read. bit 3 - LINK_STATUS_LH Link Status indicator has transitioned from Low to High since last read. bit 2 - LINK_STATUS_LL Link Status indicator has transitioned from High to Low since last read. bit 1 - BLOCK_LOCK_LH Link Status indicator has transitioned from Low to High since last read. bit 0 - BLOCK_LOCK_LL Link Status indicator has transitioned from High to Low since last read.  Chips: K2
55998 #define NWM_REG_LN2_LIVE_STS                                                                         0x80003cUL //Access:R    DataWidth:0x7   Multi Field Register.  Chips: K2
55999     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LOCAL_FAULT                                                (0x1<<6) // Live Local Fault Indicator
56000     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LOCAL_FAULT_SHIFT                                          6
56001     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_REMOTE_FAULT                                               (0x1<<7) // Live Remote Fault Indicator
56002     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_REMOTE_FAULT_SHIFT                                         7
56003     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_INTERRUPT                                             (0x1<<8) // Live Link Interrupt Indicator
56004     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_INTERRUPT_SHIFT                                       8
56005     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LPI_RECEIVED                                               (0x1<<9) // Live LPI Received Indicator
56006     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LPI_RECEIVED_SHIFT                                         9
56007     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_HI_BER                                                     (0x1<<10) // Live Hi BER Indicator
56008     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_HI_BER_SHIFT                                               10
56009     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_STATUS                                                (0x1<<11) // Live Link Status Indicator
56010     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_LINK_STATUS_SHIFT                                          11
56011     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_BLOCK_LOCK                                                 (0x1<<12) // Live block lock Indicator
56012     #define NWM_REG_LN2_LIVE_STS_LN2_LIVE_BLOCK_LOCK_SHIFT                                           12
56013 #define NWM_REG_LN3_LATCHED_STATUS                                                                   0x800040UL //Access:RC   DataWidth:0xa   The following bits a latched high.  All bits are cleared when the register is read. bit 9 - LOCAL_FAULT_LH Local Fault indicator has transitioned from Low to High since last read. bit 8 - REMOTE_FAULT_LH Remote_fault indicator has transitioned from Low to High since last read. bit 7 - LINK_INTERRUPT_LH Link Interrupt Received indicator has transitioned from Low to High since last read. bit 6 - LPI_RECEIVED_LH LPI Received indicator has transitioned from Low to High since last read. bit 5 - HI_BER_LH HI BER indicator has transitioned from Low to High since last read. bit 4 - HI_BER_LL HI BER indicator has transitioned from High to Low since last read. bit 3 - LINK_STATUS_LH Link Status indicator has transitioned from Low to High since last read. bit 2 - LINK_STATUS_LL Link Status indicator has transitioned from High to Low since last read. bit 1 - BLOCK_LOCK_LH Link Status indicator has transitioned from Low to High since last read. bit 0 - BLOCK_LOCK_LL Link Status indicator has transitioned from High to Low since last read.  Chips: K2
56014 #define NWM_REG_LN3_LIVE_STS                                                                         0x800044UL //Access:R    DataWidth:0x7   Multi Field Register.  Chips: K2
56015     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LOCAL_FAULT                                                (0x1<<6) // Live Local Fault Indicator
56016     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LOCAL_FAULT_SHIFT                                          6
56017     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_REMOTE_FAULT                                               (0x1<<7) // Live Remote Fault Indicator
56018     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_REMOTE_FAULT_SHIFT                                         7
56019     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_INTERRUPT                                             (0x1<<8) // Live Link Interrupt Indicator
56020     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_INTERRUPT_SHIFT                                       8
56021     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LPI_RECEIVED                                               (0x1<<9) // Live LPI Received Indicator
56022     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LPI_RECEIVED_SHIFT                                         9
56023     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_HI_BER                                                     (0x1<<10) // Live Hi BER Indicator
56024     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_HI_BER_SHIFT                                               10
56025     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_STATUS                                                (0x1<<11) // Live Link Status Indicator
56026     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_LINK_STATUS_SHIFT                                          11
56027     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_BLOCK_LOCK                                                 (0x1<<12) // Live block lock Indicator
56028     #define NWM_REG_LN3_LIVE_STS_LN3_LIVE_BLOCK_LOCK_SHIFT                                           12
56029 #define NWM_REG_PCS_SELECT                                                                           0x800048UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: K2
56030     #define NWM_REG_PCS_SELECT_SG0_ENA                                                               (0x1<<0) // SGMII PCS Enable.  When set to 1, the SGMII PCS is enabled.  When set to 0, the 10/25/40/50Geth PCS is enabled.
56031     #define NWM_REG_PCS_SELECT_SG0_ENA_SHIFT                                                         0
56032     #define NWM_REG_PCS_SELECT_SG1_ENA                                                               (0x1<<1) // SGMII PCS Enable.  When set to 1, the SGMII PCS is enabled.  When set to 0, the 10/25/50Geth PCS is enabled.
56033     #define NWM_REG_PCS_SELECT_SG1_ENA_SHIFT                                                         1
56034     #define NWM_REG_PCS_SELECT_SG2_ENA                                                               (0x1<<2) // SGMII PCS Enable.  When set to 1, the SGMII PCS is enabled.  When set to 0, the 10/25Geth PCS is enabled.
56035     #define NWM_REG_PCS_SELECT_SG2_ENA_SHIFT                                                         2
56036     #define NWM_REG_PCS_SELECT_SG3_ENA                                                               (0x1<<3) // SGMII PCS Enable.  When set to 1, the SGMII PCS is enabled.  When set to 0, the 10/25Geth PCS is enabled.
56037     #define NWM_REG_PCS_SELECT_SG3_ENA_SHIFT                                                         3
56038 #define NWM_REG_SGMII_PCS_STATUS                                                                     0x80004cUL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: K2
56039     #define NWM_REG_SGMII_PCS_STATUS_SG0_RX_SYNC                                                     (0x1<<0) // Set to '1' to indicate successul link synchronization.
56040     #define NWM_REG_SGMII_PCS_STATUS_SG0_RX_SYNC_SHIFT                                               0
56041     #define NWM_REG_SGMII_PCS_STATUS_SG0_AN_DONE                                                     (0x1<<1) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
56042     #define NWM_REG_SGMII_PCS_STATUS_SG0_AN_DONE_SHIFT                                               1
56043     #define NWM_REG_SGMII_PCS_STATUS_SG1_RX_SYNC                                                     (0x1<<2) // Set to '1' to indicate successul link synchronization.
56044     #define NWM_REG_SGMII_PCS_STATUS_SG1_RX_SYNC_SHIFT                                               2
56045     #define NWM_REG_SGMII_PCS_STATUS_SG1_AN_DONE                                                     (0x1<<3) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
56046     #define NWM_REG_SGMII_PCS_STATUS_SG1_AN_DONE_SHIFT                                               3
56047     #define NWM_REG_SGMII_PCS_STATUS_SG2_RX_SYNC                                                     (0x1<<4) // Set to '1' to indicate successul link synchronization.
56048     #define NWM_REG_SGMII_PCS_STATUS_SG2_RX_SYNC_SHIFT                                               4
56049     #define NWM_REG_SGMII_PCS_STATUS_SG2_AN_DONE                                                     (0x1<<5) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
56050     #define NWM_REG_SGMII_PCS_STATUS_SG2_AN_DONE_SHIFT                                               5
56051     #define NWM_REG_SGMII_PCS_STATUS_SG3_RX_SYNC                                                     (0x1<<6) // Set to '1' to indicate successul link synchronization.
56052     #define NWM_REG_SGMII_PCS_STATUS_SG3_RX_SYNC_SHIFT                                               6
56053     #define NWM_REG_SGMII_PCS_STATUS_SG3_AN_DONE                                                     (0x1<<7) // Auto-Negotiation status. Set to '1' when the Auto-Negotiation is complete.
56054     #define NWM_REG_SGMII_PCS_STATUS_SG3_AN_DONE_SHIFT                                               7
56055 #define NWM_REG_FC_FEC_CONTROL_SIGNALS                                                               0x800050UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: K2
56056     #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ENA_TX                                                (0xf<<0) // Set to '1' for a given lane to enable FEC74.
56057     #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ENA_TX_SHIFT                                          0
56058     #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ENA_RX                                                (0xf<<4) // Set to '1' for a given lane to enable FEC74.
56059     #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ENA_RX_SHIFT                                          4
56060     #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ERR_ENA                                               (0xf<<8) // Set to '1' for a given lane to enable FEC74 forward indication of uncorrectable errors to the PCS layer by corrupting sync headers. Per lane.
56061     #define NWM_REG_FC_FEC_CONTROL_SIGNALS_FEC_ERR_ENA_SHIFT                                         8
56062 #define NWM_REG_SERDES_CROSSBAR_CONTROLS                                                             0x800054UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: K2
56063     #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD0_SEL                                                 (0x3<<0) // Defines for each physical serdes lane separately, to which PCS lane it should connect
56064     #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD0_SEL_SHIFT                                           0
56065     #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD1_SEL                                                 (0x3<<2) // Defines for each physical serdes lane separately, to which PCS lane it should connect
56066     #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD1_SEL_SHIFT                                           2
56067     #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD2_SEL                                                 (0x3<<4) // Defines for each physical serdes lane separately, to which PCS lane it should connect
56068     #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD2_SEL_SHIFT                                           4
56069     #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD3_SEL                                                 (0x3<<6) // Defines for each physical serdes lane separately, to which PCS lane it should connect
56070     #define NWM_REG_SERDES_CROSSBAR_CONTROLS_SD3_SEL_SHIFT                                           6
56071 #define NWM_REG_XPCS0_LPI_FW                                                                         0x800058UL //Access:RW   DataWidth:0x1   Controls the fast-wake mode for the LPI transmit and receive functions. When set to 1, the link is to use fast wake mechanisim. When set to 0, the link is to use the optional deep sleep mechanism for each direction. Should default to 1 and may only be cleared if the optional deep sleep mode is supported.  Chips: K2
56072 #define NWM_REG_PORT0_XPCS_EEE_STATUS                                                                0x80005cUL //Access:R    DataWidth:0xa   Multi Field Register.  Chips: K2
56073     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_TX_LPI_MODE                                          (0x3<<0) // A variable reflecting the state of the LPI transmit function.
56074     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_TX_LPI_MODE_SHIFT                                    0
56075     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_TX_LPI_STATE                                         (0x7<<2) // A variable reflecting the state of the LPI Transmit State Machine.
56076     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_TX_LPI_STATE_SHIFT                                   2
56077     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_MODE                                          (0x1<<5) // A variable reflecting the state of the LPI receive function.
56078     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_MODE_SHIFT                                    5
56079     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_STATE                                         (0x7<<6) // A variable reflecting the state of the LPI Receive State Machine.
56080     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_STATE_SHIFT                                   6
56081     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_ACTIVE                                        (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
56082     #define NWM_REG_PORT0_XPCS_EEE_STATUS_XPCS0_RX_LPI_ACTIVE_SHIFT                                  9
56083 #define NWM_REG_PORT1_XPCS_EEE_STATUS                                                                0x800060UL //Access:R    DataWidth:0xa   Multi Field Register.  Chips: K2
56084     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_TX_LPI_MODE                                          (0x3<<0) // A variable reflecting the state of the LPI transmit function.
56085     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_TX_LPI_MODE_SHIFT                                    0
56086     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_TX_LPI_STATE                                         (0x7<<2) // A variable reflecting the state of the LPI Transmit State Machine.
56087     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_TX_LPI_STATE_SHIFT                                   2
56088     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_MODE                                          (0x1<<5) // A variable reflecting the state of the LPI receive function.
56089     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_MODE_SHIFT                                    5
56090     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_STATE                                         (0x7<<6) // A variable reflecting the state of the LPI Receive State Machine.
56091     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_STATE_SHIFT                                   6
56092     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_ACTIVE                                        (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
56093     #define NWM_REG_PORT1_XPCS_EEE_STATUS_XPCS1_RX_LPI_ACTIVE_SHIFT                                  9
56094 #define NWM_REG_PORT2_XPCS_EEE_STATUS                                                                0x800064UL //Access:R    DataWidth:0xa   Multi Field Register.  Chips: K2
56095     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_TX_LPI_MODE                                          (0x3<<0) // A variable reflecting the state of the LPI transmit function.
56096     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_TX_LPI_MODE_SHIFT                                    0
56097     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_TX_LPI_STATE                                         (0x7<<2) // A variable reflecting the state of the LPI Transmit State Machine.
56098     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_TX_LPI_STATE_SHIFT                                   2
56099     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_MODE                                          (0x1<<5) // A variable reflecting the state of the LPI receive function.
56100     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_MODE_SHIFT                                    5
56101     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_STATE                                         (0x7<<6) // A variable reflecting the state of the LPI Receive State Machine.
56102     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_STATE_SHIFT                                   6
56103     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_ACTIVE                                        (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
56104     #define NWM_REG_PORT2_XPCS_EEE_STATUS_XPCS2_RX_LPI_ACTIVE_SHIFT                                  9
56105 #define NWM_REG_PORT3_XPCS_EEE_STATUS                                                                0x800068UL //Access:R    DataWidth:0xa   Multi Field Register.  Chips: K2
56106     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_TX_LPI_MODE                                          (0x3<<0) // A variable reflecting the state of the LPI transmit function.
56107     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_TX_LPI_MODE_SHIFT                                    0
56108     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_TX_LPI_STATE                                         (0x7<<2) // A variable reflecting the state of the LPI Transmit State Machine.
56109     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_TX_LPI_STATE_SHIFT                                   2
56110     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_MODE                                          (0x1<<5) // A variable reflecting the state of the LPI receive function.
56111     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_MODE_SHIFT                                    5
56112     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_STATE                                         (0x7<<6) // A variable reflecting the state of the LPI Receive State Machine.
56113     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_STATE_SHIFT                                   6
56114     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_ACTIVE                                        (0x1<<9) // A boolean value that is set true (1) when the receive is in a low power state and set to false (0) when it is in an active state and capable of receiving data.
56115     #define NWM_REG_PORT3_XPCS_EEE_STATUS_XPCS3_RX_LPI_ACTIVE_SHIFT                                  9
56116 #define NWM_REG_PORT0_SG_EEE_STATUS                                                                  0x80006cUL //Access:R    DataWidth:0x4   Multi Field Register.  Chips: K2
56117     #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_TX_LPI_ACTIVE                                            (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
56118     #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_TX_LPI_ACTIVE_SHIFT                                      0
56119     #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_TXMODE_QUIET                                         (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
56120     #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_TXMODE_QUIET_SHIFT                                   1
56121     #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_RX_LPI_ACTIVE                                            (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
56122     #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_RX_LPI_ACTIVE_SHIFT                                      2
56123     #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_RXMODE_QUIET                                         (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
56124     #define NWM_REG_PORT0_SG_EEE_STATUS_SG0_PMA_RXMODE_QUIET_SHIFT                                   3
56125 #define NWM_REG_PORT1_SG_EEE_STATUS                                                                  0x800070UL //Access:R    DataWidth:0x4   Multi Field Register.  Chips: K2
56126     #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_TX_LPI_ACTIVE                                            (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
56127     #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_TX_LPI_ACTIVE_SHIFT                                      0
56128     #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_TXMODE_QUIET                                         (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
56129     #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_TXMODE_QUIET_SHIFT                                   1
56130     #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_RX_LPI_ACTIVE                                            (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
56131     #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_RX_LPI_ACTIVE_SHIFT                                      2
56132     #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_RXMODE_QUIET                                         (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
56133     #define NWM_REG_PORT1_SG_EEE_STATUS_SG1_PMA_RXMODE_QUIET_SHIFT                                   3
56134 #define NWM_REG_PORT2_SG_EEE_STATUS                                                                  0x800074UL //Access:R    DataWidth:0x4   Multi Field Register.  Chips: K2
56135     #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_TX_LPI_ACTIVE                                            (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
56136     #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_TX_LPI_ACTIVE_SHIFT                                      0
56137     #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_TXMODE_QUIET                                         (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
56138     #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_TXMODE_QUIET_SHIFT                                   1
56139     #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_RX_LPI_ACTIVE                                            (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
56140     #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_RX_LPI_ACTIVE_SHIFT                                      2
56141     #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_RXMODE_QUIET                                         (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
56142     #define NWM_REG_PORT2_SG_EEE_STATUS_SG2_PMA_RXMODE_QUIET_SHIFT                                   3
56143 #define NWM_REG_PORT3_SG_EEE_STATUS                                                                  0x800078UL //Access:R    DataWidth:0x4   Multi Field Register.  Chips: K2
56144     #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_TX_LPI_ACTIVE                                            (0x1<<0) // PCS Indication to the application that the transmitter is performing a low power cycle.
56145     #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_TX_LPI_ACTIVE_SHIFT                                      0
56146     #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_TXMODE_QUIET                                         (0x1<<1) // Indicates (when 1) that the transmitter has reached the quiet state.
56147     #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_TXMODE_QUIET_SHIFT                                   1
56148     #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_RX_LPI_ACTIVE                                            (0x1<<2) // Indicates (when 1) that the PCS receiver is performing a low power cycle.
56149     #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_RX_LPI_ACTIVE_SHIFT                                      2
56150     #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_RXMODE_QUIET                                         (0x1<<3) // Indication that the remote has disabled its transmitter and the local Serdes receiver can be put in a low-power state.
56151     #define NWM_REG_PORT3_SG_EEE_STATUS_SG3_PMA_RXMODE_QUIET_SHIFT                                   3
56152 #define NWM_REG_PCS_STATUS                                                                           0x80007cUL //Access:R    DataWidth:0x10  Multi Field Register.  Chips: K2
56153     #define NWM_REG_PCS_STATUS_ALIGN_DONE                                                            (0xf<<0) // Alignment Marker Lock indication, per PCS. When asserted (1) the alignment marker lock state machines could successfully lock onto detection of alignment markers on all virtual lanes. The signal stays asserted as long as alignment marker lock is maintained.
56154     #define NWM_REG_PCS_STATUS_ALIGN_DONE_SHIFT                                                      0
56155     #define NWM_REG_PCS_STATUS_BLOCK_LOCK                                                            (0xf<<4) // Combined Block synchronization indication for each PCS (not lane). When asserted (1) the block synchronization state machines could successfully lock onto 66-bit block boundaries on all virtual lanes relevant to the PCS. The signals stay asserted as long as block lock is maintained.
56156     #define NWM_REG_PCS_STATUS_BLOCK_LOCK_SHIFT                                                      4
56157     #define NWM_REG_PCS_STATUS_HI_BER                                                                (0xf<<8) // High Bit Error Rate indication for all lanes. Depending on mode, when asserted, at least 97 invalid synchronization headers have been found in a 1.25ms measurement period (40G) or 16 invalid headers within 125?s (10G), indicating a high bit error rate on the Serdes side. As long as hi_ber stays asserted, local fault is signaled on XLGMII. hi_ber deasserts again, only if less than the acceptable invalid synchronization headers have been detected within the same measurement period. Note: If the short marker distance is configured (See Register VL_INTVL) the measurement period shrinks to 12.5?s, independent of the mode. Note: the mentioned values are correct only for standard modes, which is 10G and 40G. The measurement window shrinks accordingly when operating in 25G or 50G modes.
56158     #define NWM_REG_PCS_STATUS_HI_BER_SHIFT                                                          8
56159     #define NWM_REG_PCS_STATUS_LINK_STATUS                                                           (0xf<<12) // Indicates operational status of the link, per PCS. When 1 indicates the link is in its normal operational state. It is the result of an asserted block-lock or align-done status, depending on current mode, and a cleared hi-ber status. The signal stays asserted during EEE quiet states. The signal represents the link status (802.3 variable PCS_Status) usable by Clause 73 backplane auto-negotiation according to 802.3 Clauses 49.2.16 and 82.6. Note: When a channel has its SGMII PCS enabled this link status has no meaning and instead the SGMII PCS' status (sg_rx_sync) is then relevant.
56160     #define NWM_REG_PCS_STATUS_LINK_STATUS_SHIFT                                                     12
56161 #define NWM_REG_RX_FAULT                                                                             0x800080UL //Access:R    DataWidth:0xc   Multi Field Register.  Chips: K2
56162     #define NWM_REG_RX_FAULT_RX_LINK_INTERRUPTION                                                    (0xf<<0) // Asserted when the  XLGMII reconciliation layer detects the remote sequences received on the link. One bit per port.
56163     #define NWM_REG_RX_FAULT_RX_LINK_INTERRUPTION_SHIFT                                              0
56164     #define NWM_REG_RX_FAULT_RX_LOCAL_FAULT                                                          (0xf<<4) // Asserted when the  XLGMII/XGMII reconciliation layer detects the local fault sequences received on the link. One bit per port.
56165     #define NWM_REG_RX_FAULT_RX_LOCAL_FAULT_SHIFT                                                    4
56166     #define NWM_REG_RX_FAULT_RX_REMOTE_FAULT                                                         (0xf<<8) // Asserted when the  XLGMII reconciliation layer detects the Link Interruption (fault) sequences received on the link. One bit per port.
56167     #define NWM_REG_RX_FAULT_RX_REMOTE_FAULT_SHIFT                                                   8
56168 #define NWM_REG_TX_FAULT                                                                             0x800084UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: K2
56169     #define NWM_REG_TX_FAULT_MAC0_TX_LOC_FAULT                                                       (0x1<<0) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
56170     #define NWM_REG_TX_FAULT_MAC0_TX_LOC_FAULT_SHIFT                                                 0
56171     #define NWM_REG_TX_FAULT_MAC0_TX_REM_FAULT                                                       (0x1<<1) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
56172     #define NWM_REG_TX_FAULT_MAC0_TX_REM_FAULT_SHIFT                                                 1
56173     #define NWM_REG_TX_FAULT_MAC0_TX_LI_FAULT                                                        (0x1<<2) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
56174     #define NWM_REG_TX_FAULT_MAC0_TX_LI_FAULT_SHIFT                                                  2
56175     #define NWM_REG_TX_FAULT_MAC1_TX_LOC_FAULT                                                       (0x1<<3) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
56176     #define NWM_REG_TX_FAULT_MAC1_TX_LOC_FAULT_SHIFT                                                 3
56177     #define NWM_REG_TX_FAULT_MAC1_TX_REM_FAULT                                                       (0x1<<4) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
56178     #define NWM_REG_TX_FAULT_MAC1_TX_REM_FAULT_SHIFT                                                 4
56179     #define NWM_REG_TX_FAULT_MAC1_TX_LI_FAULT                                                        (0x1<<5) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
56180     #define NWM_REG_TX_FAULT_MAC1_TX_LI_FAULT_SHIFT                                                  5
56181     #define NWM_REG_TX_FAULT_MAC2_TX_LOC_FAULT                                                       (0x1<<6) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
56182     #define NWM_REG_TX_FAULT_MAC2_TX_LOC_FAULT_SHIFT                                                 6
56183     #define NWM_REG_TX_FAULT_MAC2_TX_REM_FAULT                                                       (0x1<<7) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
56184     #define NWM_REG_TX_FAULT_MAC2_TX_REM_FAULT_SHIFT                                                 7
56185     #define NWM_REG_TX_FAULT_MAC2_TX_LI_FAULT                                                        (0x1<<8) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
56186     #define NWM_REG_TX_FAULT_MAC2_TX_LI_FAULT_SHIFT                                                  8
56187     #define NWM_REG_TX_FAULT_MAC3_TX_LOC_FAULT                                                       (0x1<<9) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Note: Only one of macN_tx_xxx_fault can be asserted at any time. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send loc fault 0 - don't send loc fault
56188     #define NWM_REG_TX_FAULT_MAC3_TX_LOC_FAULT_SHIFT                                                 9
56189     #define NWM_REG_TX_FAULT_MAC3_TX_REM_FAULT                                                       (0x1<<10) // Instructs the XLGMII/XGMII reconciliation layer to transmit Local Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send rem fault 0 - don't send loc rem
56190     #define NWM_REG_TX_FAULT_MAC3_TX_REM_FAULT_SHIFT                                                 10
56191     #define NWM_REG_TX_FAULT_MAC3_TX_LI_FAULT                                                        (0x1<<11) // Instructs the XLGMII/XGMII reconciliation layer to transmit Link Interruption Fault sequences (possibly truncating a frame being transmitted) and hold transmission of further frames. Overrides the RS layer tx behavior in case fault sequences are received. 1 - send li fault 0 - don't send li rem
56192     #define NWM_REG_TX_FAULT_MAC3_TX_LI_FAULT_SHIFT                                                  11
56193 #define NWM_REG_LPI_IDLE_CNT_VAL_0                                                                   0x800088UL //Access:RW   DataWidth:0x9   This field controls the minimum amount of time in which idle character will be transferred on TX line after going off LPI mode (and before transferring packets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.  Chips: K2
56194 #define NWM_REG_LPI_IDLE_CNT_VAL_1                                                                   0x80008cUL //Access:RW   DataWidth:0x9   This field controls the minimum amount of time in which idle character will be transferred on TX line after going off LPI mode (and before transferring packets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.  Chips: K2
56195 #define NWM_REG_LPI_IDLE_CNT_VAL_2                                                                   0x800090UL //Access:RW   DataWidth:0x9   This field controls the minimum amount of time in which idle character will be transferred on TX line after going off LPI mode (and before transferring packets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.  Chips: K2
56196 #define NWM_REG_LPI_IDLE_CNT_VAL_3                                                                   0x800094UL //Access:RW   DataWidth:0x9   This field controls the minimum amount of time in which idle character will be transferred on TX line after going off LPI mode (and before transferring packets). The time for idle counter is defined as "REGISTER VAL"x100nsec. The reset value for this counter is 70 which represent 7usec.  Chips: K2
56197 #define NWM_REG_BER_TIMER_DONE_COUNT_0                                                               0x800098UL //Access:RC   DataWidth:0x20  count of the number of times ber_timer_done asserted. Clear on Read.  Chips: K2
56198 #define NWM_REG_BER_TIMER_DONE_COUNT_1                                                               0x80009cUL //Access:RC   DataWidth:0x20  count of the number of times ber_timer_done asserted. Clear on Read.  Chips: K2
56199 #define NWM_REG_BER_TIMER_DONE_COUNT_2                                                               0x8000a0UL //Access:RC   DataWidth:0x20  count of the number of times ber_timer_done asserted. Clear on Read.  Chips: K2
56200 #define NWM_REG_BER_TIMER_DONE_COUNT_3                                                               0x8000a4UL //Access:RC   DataWidth:0x20  count of the number of times ber_timer_done asserted. Clear on Read.  Chips: K2
56201 #define NWM_REG_FC_FEC_CERR_COUNT_0                                                                  0x8000a8UL //Access:RC   DataWidth:0x20  FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 0. Clear on Read.  Chips: K2
56202 #define NWM_REG_FC_FEC_CERR_COUNT_1                                                                  0x8000acUL //Access:RC   DataWidth:0x20  FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 1. Clear on Read.  Chips: K2
56203 #define NWM_REG_FC_FEC_CERR_COUNT_2                                                                  0x8000b0UL //Access:RC   DataWidth:0x20  FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 2. Clear on Read.  Chips: K2
56204 #define NWM_REG_FC_FEC_CERR_COUNT_3                                                                  0x8000b4UL //Access:RC   DataWidth:0x20  FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 3. Clear on Read.  Chips: K2
56205 #define NWM_REG_FC_FEC_CERR_COUNT_4                                                                  0x8000b8UL //Access:RC   DataWidth:0x20  FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 4. Clear on Read.  Chips: K2
56206 #define NWM_REG_FC_FEC_CERR_COUNT_5                                                                  0x8000bcUL //Access:RC   DataWidth:0x20  FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 5. Clear on Read.  Chips: K2
56207 #define NWM_REG_FC_FEC_CERR_COUNT_6                                                                  0x8000c0UL //Access:RC   DataWidth:0x20  FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 6. Clear on Read.  Chips: K2
56208 #define NWM_REG_FC_FEC_CERR_COUNT_7                                                                  0x8000c4UL //Access:RC   DataWidth:0x20  FEC corrected error indication. The FEC could detect and correct receive errors in a block. count of the number of times fec_cerr asserted for virtual lane 7. Clear on Read.  Chips: K2
56209 #define NWM_REG_FC_FEC_NCERR_COUNT_0                                                                 0x8000c8UL //Access:RC   DataWidth:0x20  count of the number of times fec_ncerr asserted for virtual lane 0. Clear on Read.  Chips: K2
56210 #define NWM_REG_FC_FEC_NCERR_COUNT_1                                                                 0x8000ccUL //Access:RC   DataWidth:0x20  FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 1. Clear on Read.  Chips: K2
56211 #define NWM_REG_FC_FEC_NCERR_COUNT_2                                                                 0x8000d0UL //Access:RC   DataWidth:0x20  FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 2. Clear on Read.  Chips: K2
56212 #define NWM_REG_FC_FEC_NCERR_COUNT_3                                                                 0x8000d4UL //Access:RC   DataWidth:0x20  FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 3. Clear on Read.  Chips: K2
56213 #define NWM_REG_FC_FEC_NCERR_COUNT_4                                                                 0x8000d8UL //Access:RC   DataWidth:0x20  FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 4. Clear on Read.  Chips: K2
56214 #define NWM_REG_FC_FEC_NCERR_COUNT_5                                                                 0x8000dcUL //Access:RC   DataWidth:0x20  FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 5. Clear on Read.  Chips: K2
56215 #define NWM_REG_FC_FEC_NCERR_COUNT_6                                                                 0x8000e0UL //Access:RC   DataWidth:0x20  FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 6. Clear on Read.  Chips: K2
56216 #define NWM_REG_FC_FEC_NCERR_COUNT_7                                                                 0x8000e4UL //Access:RC   DataWidth:0x20  FEC uncorrectable error indication. The FEC could detect but not correct receive errors in a block. count of the number of times fec_ncerr asserted for virtual lane 7. Clear on Read.  Chips: K2
56217 #define NWM_REG_ECO_RESERVED                                                                         0x8000e8UL //Access:RW   DataWidth:0x20  This is unused register for future ECOs.  Chips: K2
56218 #define NWM_REG_DBG_SELECT                                                                           0x8000ecUL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: K2
56219 #define NWM_REG_DBG_DWORD_ENABLE                                                                     0x8000f0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: K2
56220 #define NWM_REG_DBG_SHIFT                                                                            0x8000f4UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: K2
56221 #define NWM_REG_DBG_FORCE_VALID                                                                      0x8000f8UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
56222 #define NWM_REG_DBG_FORCE_FRAME                                                                      0x8000fcUL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: K2
56223 #define NWM_REG_DBG_OUT_DATA                                                                         0x800100UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: K2
56224 #define NWM_REG_DBG_OUT_DATA_SIZE                                                                    8
56225 #define NWM_REG_DBG_OUT_VALID                                                                        0x800120UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: K2
56226 #define NWM_REG_DBG_OUT_FRAME                                                                        0x800124UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: K2
56227 #define NWM_REG_PRTY_MASK_H_0                                                                        0x800204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: K2
56228     #define NWM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
56229     #define NWM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_SHIFT                                            0
56230     #define NWM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
56231     #define NWM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_SHIFT                                            1
56232     #define NWM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
56233     #define NWM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_SHIFT                                            2
56234     #define NWM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM044_I_MEM_PRTY .
56235     #define NWM_REG_PRTY_MASK_H_0_MEM044_I_MEM_PRTY_SHIFT                                            3
56236     #define NWM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
56237     #define NWM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_SHIFT                                            4
56238     #define NWM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
56239     #define NWM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_SHIFT                                            5
56240     #define NWM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
56241     #define NWM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_SHIFT                                            6
56242     #define NWM_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM047_I_MEM_PRTY .
56243     #define NWM_REG_PRTY_MASK_H_0_MEM047_I_MEM_PRTY_SHIFT                                            7
56244     #define NWM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
56245     #define NWM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                            8
56246     #define NWM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
56247     #define NWM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_SHIFT                                            9
56248     #define NWM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
56249     #define NWM_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_SHIFT                                            10
56250     #define NWM_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM048_I_MEM_PRTY .
56251     #define NWM_REG_PRTY_MASK_H_0_MEM048_I_MEM_PRTY_SHIFT                                            11
56252     #define NWM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
56253     #define NWM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_SHIFT                                            12
56254     #define NWM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
56255     #define NWM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT                                            13
56256     #define NWM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
56257     #define NWM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_SHIFT                                            14
56258     #define NWM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM042_I_MEM_PRTY .
56259     #define NWM_REG_PRTY_MASK_H_0_MEM042_I_MEM_PRTY_SHIFT                                            15
56260     #define NWM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
56261     #define NWM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_SHIFT                                            16
56262     #define NWM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
56263     #define NWM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_SHIFT                                            17
56264     #define NWM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
56265     #define NWM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_SHIFT                                            18
56266     #define NWM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM041_I_MEM_PRTY .
56267     #define NWM_REG_PRTY_MASK_H_0_MEM041_I_MEM_PRTY_SHIFT                                            19
56268     #define NWM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
56269     #define NWM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                            20
56270     #define NWM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
56271     #define NWM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_SHIFT                                            21
56272     #define NWM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
56273     #define NWM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_SHIFT                                            22
56274     #define NWM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM045_I_MEM_PRTY .
56275     #define NWM_REG_PRTY_MASK_H_0_MEM045_I_MEM_PRTY_SHIFT                                            23
56276     #define NWM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
56277     #define NWM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_SHIFT                                            24
56278     #define NWM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
56279     #define NWM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_SHIFT                                            25
56280     #define NWM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
56281     #define NWM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_SHIFT                                            26
56282     #define NWM_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM043_I_MEM_PRTY .
56283     #define NWM_REG_PRTY_MASK_H_0_MEM043_I_MEM_PRTY_SHIFT                                            27
56284     #define NWM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
56285     #define NWM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_SHIFT                                            28
56286     #define NWM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
56287     #define NWM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_SHIFT                                            29
56288     #define NWM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
56289     #define NWM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_SHIFT                                            30
56290 #define NWM_REG_PRTY_MASK_H_1                                                                        0x800214UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: K2
56291     #define NWM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM046_I_MEM_PRTY .
56292     #define NWM_REG_PRTY_MASK_H_1_MEM046_I_MEM_PRTY_SHIFT                                            0
56293     #define NWM_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM057_I_MEM_PRTY .
56294     #define NWM_REG_PRTY_MASK_H_1_MEM057_I_MEM_PRTY_SHIFT                                            1
56295     #define NWM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM059_I_MEM_PRTY .
56296     #define NWM_REG_PRTY_MASK_H_1_MEM059_I_MEM_PRTY_SHIFT                                            2
56297     #define NWM_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM061_I_MEM_PRTY .
56298     #define NWM_REG_PRTY_MASK_H_1_MEM061_I_MEM_PRTY_SHIFT                                            3
56299     #define NWM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM063_I_MEM_PRTY .
56300     #define NWM_REG_PRTY_MASK_H_1_MEM063_I_MEM_PRTY_SHIFT                                            4
56301     #define NWM_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM058_I_MEM_PRTY .
56302     #define NWM_REG_PRTY_MASK_H_1_MEM058_I_MEM_PRTY_SHIFT                                            5
56303     #define NWM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM060_I_MEM_PRTY .
56304     #define NWM_REG_PRTY_MASK_H_1_MEM060_I_MEM_PRTY_SHIFT                                            6
56305     #define NWM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM062_I_MEM_PRTY .
56306     #define NWM_REG_PRTY_MASK_H_1_MEM062_I_MEM_PRTY_SHIFT                                            7
56307     #define NWM_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM064_I_MEM_PRTY .
56308     #define NWM_REG_PRTY_MASK_H_1_MEM064_I_MEM_PRTY_SHIFT                                            8
56309     #define NWM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
56310     #define NWM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_SHIFT                                            9
56311     #define NWM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
56312     #define NWM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_SHIFT                                            10
56313     #define NWM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY                                                  (0x1<<11) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
56314     #define NWM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_SHIFT                                            11
56315     #define NWM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY                                                  (0x1<<12) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
56316     #define NWM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_SHIFT                                            12
56317     #define NWM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
56318     #define NWM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_SHIFT                                            13
56319     #define NWM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
56320     #define NWM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_SHIFT                                            14
56321     #define NWM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
56322     #define NWM_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_SHIFT                                            15
56323     #define NWM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
56324     #define NWM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_SHIFT                                            16
56325     #define NWM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
56326     #define NWM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_SHIFT                                            17
56327     #define NWM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
56328     #define NWM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_SHIFT                                            18
56329     #define NWM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
56330     #define NWM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_SHIFT                                            19
56331     #define NWM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
56332     #define NWM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_SHIFT                                            20
56333     #define NWM_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
56334     #define NWM_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_SHIFT                                            21
56335     #define NWM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
56336     #define NWM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_SHIFT                                            22
56337     #define NWM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
56338     #define NWM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_SHIFT                                            23
56339     #define NWM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
56340     #define NWM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_SHIFT                                            24
56341     #define NWM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM049_I_MEM_PRTY .
56342     #define NWM_REG_PRTY_MASK_H_1_MEM049_I_MEM_PRTY_SHIFT                                            25
56343     #define NWM_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM053_I_MEM_PRTY .
56344     #define NWM_REG_PRTY_MASK_H_1_MEM053_I_MEM_PRTY_SHIFT                                            26
56345     #define NWM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM050_I_MEM_PRTY .
56346     #define NWM_REG_PRTY_MASK_H_1_MEM050_I_MEM_PRTY_SHIFT                                            27
56347     #define NWM_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM054_I_MEM_PRTY .
56348     #define NWM_REG_PRTY_MASK_H_1_MEM054_I_MEM_PRTY_SHIFT                                            28
56349     #define NWM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM051_I_MEM_PRTY .
56350     #define NWM_REG_PRTY_MASK_H_1_MEM051_I_MEM_PRTY_SHIFT                                            29
56351     #define NWM_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_1.MEM055_I_MEM_PRTY .
56352     #define NWM_REG_PRTY_MASK_H_1_MEM055_I_MEM_PRTY_SHIFT                                            30
56353 #define NWM_REG_PRTY_MASK_H_2                                                                        0x800224UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: K2
56354     #define NWM_REG_PRTY_MASK_H_2_MEM052_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM052_I_MEM_PRTY .
56355     #define NWM_REG_PRTY_MASK_H_2_MEM052_I_MEM_PRTY_SHIFT                                            0
56356     #define NWM_REG_PRTY_MASK_H_2_MEM056_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM056_I_MEM_PRTY .
56357     #define NWM_REG_PRTY_MASK_H_2_MEM056_I_MEM_PRTY_SHIFT                                            1
56358     #define NWM_REG_PRTY_MASK_H_2_MEM066_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM066_I_MEM_PRTY .
56359     #define NWM_REG_PRTY_MASK_H_2_MEM066_I_MEM_PRTY_SHIFT                                            2
56360     #define NWM_REG_PRTY_MASK_H_2_MEM068_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM068_I_MEM_PRTY .
56361     #define NWM_REG_PRTY_MASK_H_2_MEM068_I_MEM_PRTY_SHIFT                                            3
56362     #define NWM_REG_PRTY_MASK_H_2_MEM070_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM070_I_MEM_PRTY .
56363     #define NWM_REG_PRTY_MASK_H_2_MEM070_I_MEM_PRTY_SHIFT                                            4
56364     #define NWM_REG_PRTY_MASK_H_2_MEM072_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM072_I_MEM_PRTY .
56365     #define NWM_REG_PRTY_MASK_H_2_MEM072_I_MEM_PRTY_SHIFT                                            5
56366     #define NWM_REG_PRTY_MASK_H_2_MEM065_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM065_I_MEM_PRTY .
56367     #define NWM_REG_PRTY_MASK_H_2_MEM065_I_MEM_PRTY_SHIFT                                            6
56368     #define NWM_REG_PRTY_MASK_H_2_MEM067_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM067_I_MEM_PRTY .
56369     #define NWM_REG_PRTY_MASK_H_2_MEM067_I_MEM_PRTY_SHIFT                                            7
56370     #define NWM_REG_PRTY_MASK_H_2_MEM069_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM069_I_MEM_PRTY .
56371     #define NWM_REG_PRTY_MASK_H_2_MEM069_I_MEM_PRTY_SHIFT                                            8
56372     #define NWM_REG_PRTY_MASK_H_2_MEM071_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: NWM_REG_PRTY_STS_H_2.MEM071_I_MEM_PRTY .
56373     #define NWM_REG_PRTY_MASK_H_2_MEM071_I_MEM_PRTY_SHIFT                                            9
56374 #define NWM_REG_MEM_ECC_EVENTS                                                                       0x800230UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
56375 #define NWM_REG_MEM020_I_MEM_DFT                                                                     0x800240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac0_rxd_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56376 #define NWM_REG_MEM028_I_MEM_DFT                                                                     0x800244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac1_rxd_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56377 #define NWM_REG_MEM036_I_MEM_DFT                                                                     0x800248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac2_rxd_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56378 #define NWM_REG_MEM044_I_MEM_DFT                                                                     0x80024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac3_rxd_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56379 #define NWM_REG_MEM023_I_MEM_DFT                                                                     0x800250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac0_txd_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56380 #define NWM_REG_MEM031_I_MEM_DFT                                                                     0x800254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac1_txd_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56381 #define NWM_REG_MEM039_I_MEM_DFT                                                                     0x800258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac2_txd_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56382 #define NWM_REG_MEM047_I_MEM_DFT                                                                     0x80025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac3_txd_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56383 #define NWM_REG_MEM024_I_MEM_DFT                                                                     0x800260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac0_txs_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56384 #define NWM_REG_MEM032_I_MEM_DFT                                                                     0x800264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac1_txs_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56385 #define NWM_REG_MEM040_I_MEM_DFT                                                                     0x800268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac2_txs_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56386 #define NWM_REG_MEM048_I_MEM_DFT                                                                     0x80026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac3_txs_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56387 #define NWM_REG_MEM018_I_MEM_DFT                                                                     0x800270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac0_oid_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56388 #define NWM_REG_MEM026_I_MEM_DFT                                                                     0x800274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac1_oid_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56389 #define NWM_REG_MEM034_I_MEM_DFT                                                                     0x800278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac2_oid_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56390 #define NWM_REG_MEM042_I_MEM_DFT                                                                     0x80027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac3_oid_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56391 #define NWM_REG_MEM017_I_MEM_DFT                                                                     0x800280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac0_ock_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56392 #define NWM_REG_MEM025_I_MEM_DFT                                                                     0x800284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac1_ock_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56393 #define NWM_REG_MEM033_I_MEM_DFT                                                                     0x800288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac2_ock_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56394 #define NWM_REG_MEM041_I_MEM_DFT                                                                     0x80028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac3_ock_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56395 #define NWM_REG_MEM021_I_MEM_DFT                                                                     0x800290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac0_tscr_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56396 #define NWM_REG_MEM029_I_MEM_DFT                                                                     0x800294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac1_tscr_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56397 #define NWM_REG_MEM037_I_MEM_DFT                                                                     0x800298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac2_tscr_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56398 #define NWM_REG_MEM045_I_MEM_DFT                                                                     0x80029cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac3_tscr_fifo_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56399 #define NWM_REG_MEM019_I_MEM_DFT                                                                     0x8002a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac0_rx_stat_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56400 #define NWM_REG_MEM027_I_MEM_DFT                                                                     0x8002a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac1_rx_stat_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56401 #define NWM_REG_MEM035_I_MEM_DFT                                                                     0x8002a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac2_rx_stat_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56402 #define NWM_REG_MEM043_I_MEM_DFT                                                                     0x8002acUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac3_rx_stat_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56403 #define NWM_REG_MEM022_I_MEM_DFT                                                                     0x8002b0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac0_tx_stat_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56404 #define NWM_REG_MEM030_I_MEM_DFT                                                                     0x8002b4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac1_tx_stat_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56405 #define NWM_REG_MEM038_I_MEM_DFT                                                                     0x8002b8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac2_tx_stat_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56406 #define NWM_REG_MEM046_I_MEM_DFT                                                                     0x8002bcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_mac3_tx_stat_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56407 #define NWM_REG_MEM057_I_MEM_DFT                                                                     0x8002c0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_rsff0_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56408 #define NWM_REG_MEM059_I_MEM_DFT                                                                     0x8002c4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_rsff1_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56409 #define NWM_REG_MEM061_I_MEM_DFT                                                                     0x8002c8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_rsff2_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56410 #define NWM_REG_MEM063_I_MEM_DFT                                                                     0x8002ccUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_rsff3_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56411 #define NWM_REG_MEM058_I_MEM_DFT                                                                     0x8002d0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_rsff0_rxdm_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56412 #define NWM_REG_MEM060_I_MEM_DFT                                                                     0x8002d4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_rsff1_rxdm_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56413 #define NWM_REG_MEM062_I_MEM_DFT                                                                     0x8002d8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_rsff2_rxdm_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56414 #define NWM_REG_MEM064_I_MEM_DFT                                                                     0x8002dcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_rsff3_rxdm_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56415 #define NWM_REG_MEM009_I_MEM_DFT                                                                     0x8002e0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcff0_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56416 #define NWM_REG_MEM010_I_MEM_DFT                                                                     0x8002e4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcff1_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56417 #define NWM_REG_MEM011_I_MEM_DFT                                                                     0x8002e8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcff2_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56418 #define NWM_REG_MEM012_I_MEM_DFT                                                                     0x8002ecUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcff3_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56419 #define NWM_REG_MEM013_I_MEM_DFT                                                                     0x8002f0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcff4_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56420 #define NWM_REG_MEM014_I_MEM_DFT                                                                     0x8002f4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcff5_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56421 #define NWM_REG_MEM015_I_MEM_DFT                                                                     0x8002f8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcff6_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56422 #define NWM_REG_MEM016_I_MEM_DFT                                                                     0x8002fcUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcff7_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56423 #define NWM_REG_MEM001_I_MEM_DFT                                                                     0x800300UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcfd0_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56424 #define NWM_REG_MEM002_I_MEM_DFT                                                                     0x800304UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcfd1_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56425 #define NWM_REG_MEM003_I_MEM_DFT                                                                     0x800308UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcfd2_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56426 #define NWM_REG_MEM004_I_MEM_DFT                                                                     0x80030cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcfd3_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56427 #define NWM_REG_MEM005_I_MEM_DFT                                                                     0x800310UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcfd4_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56428 #define NWM_REG_MEM006_I_MEM_DFT                                                                     0x800314UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcfd5_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56429 #define NWM_REG_MEM007_I_MEM_DFT                                                                     0x800318UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcfd6_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56430 #define NWM_REG_MEM008_I_MEM_DFT                                                                     0x80031cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_fcfd7_rxd_frame_read_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56431 #define NWM_REG_MEM049_I_MEM_DFT                                                                     0x800320UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_pcs00_rxd_deskew_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56432 #define NWM_REG_MEM053_I_MEM_DFT                                                                     0x800324UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_pcs10_rxd_deskew_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56433 #define NWM_REG_MEM050_I_MEM_DFT                                                                     0x800328UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_pcs01_rxd_deskew_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56434 #define NWM_REG_MEM054_I_MEM_DFT                                                                     0x80032cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_pcs11_rxd_deskew_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56435 #define NWM_REG_MEM051_I_MEM_DFT                                                                     0x800330UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_pcs02_rxd_deskew_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56436 #define NWM_REG_MEM055_I_MEM_DFT                                                                     0x800334UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_pcs12_rxd_deskew_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56437 #define NWM_REG_MEM052_I_MEM_DFT                                                                     0x800338UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_pcs03_rxd_deskew_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56438 #define NWM_REG_MEM056_I_MEM_DFT                                                                     0x80033cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_pcs13_rxd_deskew_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56439 #define NWM_REG_MEM066_I_MEM_DFT                                                                     0x800340UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_sd0_txd_clk_decoupling_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56440 #define NWM_REG_MEM068_I_MEM_DFT                                                                     0x800344UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_sd1_txd_clk_decoupling_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56441 #define NWM_REG_MEM070_I_MEM_DFT                                                                     0x800348UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_sd2_txd_clk_decoupling_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56442 #define NWM_REG_MEM072_I_MEM_DFT                                                                     0x80034cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_sd3_txd_clk_decoupling_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56443 #define NWM_REG_MEM065_I_MEM_DFT                                                                     0x800350UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_sd0_rxd_clk_decoupling_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56444 #define NWM_REG_MEM067_I_MEM_DFT                                                                     0x800354UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_sd1_rxd_clk_decoupling_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56445 #define NWM_REG_MEM069_I_MEM_DFT                                                                     0x800358UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_sd2_rxd_clk_decoupling_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56446 #define NWM_REG_MEM071_I_MEM_DFT                                                                     0x80035cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance nwm.i_sd3_rxd_clk_decoupling_ram.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
56447 #define NWM_REG_MAC0                                                                                 0x800400UL //Access:RW   DataWidth:0x20  Register space for MAC port 0. Registers defined in MAC64.1.0.xml  Chips: K2
56448 #define NWM_REG_MAC0_SIZE                                                                            256
56449 #define NWM_REG_MAC1                                                                                 0x800800UL //Access:RW   DataWidth:0x20  Register space for MAC port 1. Registers defined in MAC64.1.0.xml  Chips: K2
56450 #define NWM_REG_MAC1_SIZE                                                                            256
56451 #define NWM_REG_MAC2                                                                                 0x800c00UL //Access:RW   DataWidth:0x20  Register space for MAC port 2. Registers defined in MAC64.1.0.xml  Chips: K2
56452 #define NWM_REG_MAC2_SIZE                                                                            256
56453 #define NWM_REG_MAC3                                                                                 0x801000UL //Access:RW   DataWidth:0x20  Register space for MAC port 3. Registers defined in MAC64.1.0.xml  Chips: K2
56454 #define NWM_REG_MAC3_SIZE                                                                            256
56455 #define NWM_REG_PCS_REG91_0                                                                          0x801400UL //Access:RW   DataWidth:0x10  Register space for 10/25/40/50G PCS RS FEC port 0. Registers defined in rsfec91.1.0.xml  Chips: K2
56456 #define NWM_REG_PCS_REG91_0_SIZE                                                                     256
56457 #define NWM_REG_PCS_REG91_1                                                                          0x801800UL //Access:RW   DataWidth:0x10  Register space for 10/25/40/50G PCS RS FEC port 1. Registers defined in rsfec91.1.0.xml  Chips: K2
56458 #define NWM_REG_PCS_REG91_1_SIZE                                                                     256
56459 #define NWM_REG_PCS_REG91_2                                                                          0x801c00UL //Access:RW   DataWidth:0x10  Register space for 10/25G PCS RS FEC port 2. Registers defined in rsfec91.1.0.xml  Chips: K2
56460 #define NWM_REG_PCS_REG91_2_SIZE                                                                     256
56461 #define NWM_REG_PCS_REG91_3                                                                          0x802000UL //Access:RW   DataWidth:0x10  Register space for 10/25G PCS RS FEC port 3. Registers defined in rsfec91.1.0.xml  Chips: K2
56462 #define NWM_REG_PCS_REG91_3_SIZE                                                                     256
56463 #define NWM_REG_PCS_LS0                                                                              0x802400UL //Access:RW   DataWidth:0x10  Register space for 1G PCS port 0. Registers defined in PCS_1000basex_sgmii.1.0.xml  Chips: K2
56464 #define NWM_REG_PCS_LS0_SIZE                                                                         32
56465 #define NWM_REG_PCS_LS1                                                                              0x802480UL //Access:RW   DataWidth:0x10  Register space for 1G PCS port 1. Registers defined in PCS_1000basex_sgmii.1.0.xml  Chips: K2
56466 #define NWM_REG_PCS_LS1_SIZE                                                                         32
56467 #define NWM_REG_PCS_LS2                                                                              0x802500UL //Access:RW   DataWidth:0x10  Register space for 1G PCS port 2. Registers defined in PCS_1000basex_sgmii.1.0.xml  Chips: K2
56468 #define NWM_REG_PCS_LS2_SIZE                                                                         32
56469 #define NWM_REG_PCS_LS3                                                                              0x802580UL //Access:RW   DataWidth:0x10  Register space for 1G PCS port 3. Registers defined in PCS_1000basex_sgmii.1.0.xml  Chips: K2
56470 #define NWM_REG_PCS_LS3_SIZE                                                                         32
56471 #define NWM_REG_PCS_HS0                                                                              0x840000UL //Access:RW   DataWidth:0x10  Register space for 10/25/40/50G PCS port 0. Registers defined in pcs10254050.1.0.xml  Chips: K2
56472 #define NWM_REG_PCS_HS0_SIZE                                                                         65536
56473 #define NWM_REG_PCS_HS1                                                                              0x880000UL //Access:RW   DataWidth:0x10  Register space for 10/25/40/50G PCS port 1. Registers defined in pcs10254050.1.0.xml  Chips: K2
56474 #define NWM_REG_PCS_HS1_SIZE                                                                         65536
56475 #define NWM_REG_PCS_HS2                                                                              0x8c0000UL //Access:RW   DataWidth:0x10  Register space for 10/25G PCS port 2. Registers defined in pcs1025.1.0.xml  Chips: K2
56476 #define NWM_REG_PCS_HS2_SIZE                                                                         65536
56477 #define NWM_REG_PCS_HS3                                                                              0x900000UL //Access:RW   DataWidth:0x10  Register space for 10/25G PCS port 3. Registers defined in pcs1025.1.0.xml  Chips: K2
56478 #define NWM_REG_PCS_HS3_SIZE                                                                         65536
56479 #define PBF_REG_INIT                                                                                 0xd80000UL //Access:RW   DataWidth:0x1   Init bit. When set the initial credits are copied to the credit registers (except the port credits). Should be set and then reset after the configuration of the block has ended.  Chips: BB_A0 BB_B0 K2
56480 #define PBF_REG_IF_ENABLE_REG                                                                        0xd80040UL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56481     #define PBF_REG_IF_ENABLE_REG_DORQ_IF_ENABLE                                                     (0x1<<0) // Enables the dorq interface.
56482     #define PBF_REG_IF_ENABLE_REG_DORQ_IF_ENABLE_SHIFT                                               0
56483     #define PBF_REG_IF_ENABLE_REG_YSEM_IF_ENABLE                                                     (0x1<<1) // Enables the ysem interface.
56484     #define PBF_REG_IF_ENABLE_REG_YSEM_IF_ENABLE_SHIFT                                               1
56485     #define PBF_REG_IF_ENABLE_REG_PTU_REQ_IF_ENABLE                                                  (0x1<<2) // Enables the ptu_req interface.
56486     #define PBF_REG_IF_ENABLE_REG_PTU_REQ_IF_ENABLE_SHIFT                                            2
56487     #define PBF_REG_IF_ENABLE_REG_PCM_IF_ENABLE                                                      (0x1<<3) // Enables the pcm interface.
56488     #define PBF_REG_IF_ENABLE_REG_PCM_IF_ENABLE_SHIFT                                                3
56489     #define PBF_REG_IF_ENABLE_REG_TDIF_CMD_IF_ENABLE                                                 (0x1<<4) // Enables the tdif_cmd interface.
56490     #define PBF_REG_IF_ENABLE_REG_TDIF_CMD_IF_ENABLE_SHIFT                                           4
56491     #define PBF_REG_IF_ENABLE_REG_TDIF_RDATA_IF_ENABLE                                               (0x1<<5) // Enables the tdif_rdata interface.
56492     #define PBF_REG_IF_ENABLE_REG_TDIF_RDATA_IF_ENABLE_SHIFT                                         5
56493     #define PBF_REG_IF_ENABLE_REG_PSEM_IF_ENABLE                                                     (0x1<<6) // Enables the psem interface.
56494     #define PBF_REG_IF_ENABLE_REG_PSEM_IF_ENABLE_SHIFT                                               6
56495     #define PBF_REG_IF_ENABLE_REG_QM_LINE_CREDIT_IF_ENABLE                                           (0x1<<7) // Enables the qm_line_credit interface.
56496     #define PBF_REG_IF_ENABLE_REG_QM_LINE_CREDIT_IF_ENABLE_SHIFT                                     7
56497     #define PBF_REG_IF_ENABLE_REG_TM_REQ_IF_ENABLE                                                   (0x1<<8) // Enables the tm_req interface.
56498     #define PBF_REG_IF_ENABLE_REG_TM_REQ_IF_ENABLE_SHIFT                                             8
56499     #define PBF_REG_IF_ENABLE_REG_PXP_INT_WRREQ_IF_ENABLE                                            (0x1<<9) // Enables the pxp_int_wrreq interface.
56500     #define PBF_REG_IF_ENABLE_REG_PXP_INT_WRREQ_IF_ENABLE_SHIFT                                      9
56501     #define PBF_REG_IF_ENABLE_REG_BTB_DATA_IF_ENABLE                                                 (0x1<<10) // Enables the btb_data interface.
56502     #define PBF_REG_IF_ENABLE_REG_BTB_DATA_IF_ENABLE_SHIFT                                           10
56503     #define PBF_REG_IF_ENABLE_REG_BTB_RLS_IF_ENABLE                                                  (0x1<<11) // Enables the btb_rls interface.
56504     #define PBF_REG_IF_ENABLE_REG_BTB_RLS_IF_ENABLE_SHIFT                                            11
56505     #define PBF_REG_IF_ENABLE_REG_TCM_IF_ENABLE                                                      (0x1<<12) // Enables the tcm interface.
56506     #define PBF_REG_IF_ENABLE_REG_TCM_IF_ENABLE_SHIFT                                                12
56507     #define PBF_REG_IF_ENABLE_REG_MCM_IF_ENABLE                                                      (0x1<<13) // Enables the mcm interface.
56508     #define PBF_REG_IF_ENABLE_REG_MCM_IF_ENABLE_SHIFT                                                13
56509     #define PBF_REG_IF_ENABLE_REG_UCM_IF_ENABLE                                                      (0x1<<14) // Enables the ucm interface.
56510     #define PBF_REG_IF_ENABLE_REG_UCM_IF_ENABLE_SHIFT                                                14
56511     #define PBF_REG_IF_ENABLE_REG_XCM_IF_ENABLE                                                      (0x1<<15) // Enables the xcm interface.
56512     #define PBF_REG_IF_ENABLE_REG_XCM_IF_ENABLE_SHIFT                                                15
56513     #define PBF_REG_IF_ENABLE_REG_YCM_IF_ENABLE                                                      (0x1<<16) // Enables the ycm interface.
56514     #define PBF_REG_IF_ENABLE_REG_YCM_IF_ENABLE_SHIFT                                                16
56515     #define PBF_REG_IF_ENABLE_REG_TCM_DONE_IF_ENABLE                                                 (0x1<<17) // Enables the tcm_done interface.
56516     #define PBF_REG_IF_ENABLE_REG_TCM_DONE_IF_ENABLE_SHIFT                                           17
56517     #define PBF_REG_IF_ENABLE_REG_MCM_DONE_IF_ENABLE                                                 (0x1<<18) // Enables the mcm_done interface.
56518     #define PBF_REG_IF_ENABLE_REG_MCM_DONE_IF_ENABLE_SHIFT                                           18
56519     #define PBF_REG_IF_ENABLE_REG_UCM_DONE_IF_ENABLE                                                 (0x1<<19) // Enables the ucm_done interface.
56520     #define PBF_REG_IF_ENABLE_REG_UCM_DONE_IF_ENABLE_SHIFT                                           19
56521     #define PBF_REG_IF_ENABLE_REG_YCM_DONE_IF_ENABLE                                                 (0x1<<20) // Enables the ycm_done interface.
56522     #define PBF_REG_IF_ENABLE_REG_YCM_DONE_IF_ENABLE_SHIFT                                           20
56523 #define PBF_REG_DBG_SELECT                                                                           0xd80060UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
56524 #define PBF_REG_DBG_DWORD_ENABLE                                                                     0xd80064UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
56525 #define PBF_REG_DBG_SHIFT                                                                            0xd80068UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
56526 #define PBF_REG_DBG_FORCE_VALID                                                                      0xd8006cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
56527 #define PBF_REG_DBG_FORCE_FRAME                                                                      0xd80070UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
56528 #define PBF_REG_DBG_OUT_DATA                                                                         0xd80080UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
56529 #define PBF_REG_DBG_OUT_DATA_SIZE                                                                    8
56530 #define PBF_REG_DBG_OUT_VALID                                                                        0xd800a0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
56531 #define PBF_REG_DBG_OUT_FRAME                                                                        0xd800a4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
56532 #define PBF_REG_FC_DBG_SELECT                                                                        0xd800a8UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
56533 #define PBF_REG_FC_DBG_DWORD_ENABLE                                                                  0xd800acUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
56534 #define PBF_REG_FC_DBG_SHIFT                                                                         0xd800b0UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
56535 #define PBF_REG_FC_DBG_OUT_DATA                                                                      0xd800c0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
56536 #define PBF_REG_FC_DBG_OUT_DATA_SIZE                                                                 8
56537 #define PBF_REG_FC_DBG_FORCE_VALID                                                                   0xd800e0UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
56538 #define PBF_REG_FC_DBG_FORCE_FRAME                                                                   0xd800e4UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
56539 #define PBF_REG_FC_DBG_OUT_VALID                                                                     0xd800e8UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
56540 #define PBF_REG_FC_DBG_OUT_FRAME                                                                     0xd800ecUL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
56541 #define PBF_REG_MEMCTRL_WR_RD_N                                                                      0xd80100UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
56542 #define PBF_REG_MEMCTRL_CMD                                                                          0xd80104UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
56543 #define PBF_REG_MEMCTRL_ADDRESS                                                                      0xd80108UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
56544 #define PBF_REG_MEMCTRL_STATUS                                                                       0xd8010cUL //Access:R    DataWidth:0x20  obsolete  Chips: BB_A0 BB_B0 K2
56545 #define PBF_REG_INT_STS                                                                              0xd80180UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
56546     #define PBF_REG_INT_STS_ADDRESS_ERROR                                                            (0x1<<0) // Signals an unknown address to the rf module.
56547     #define PBF_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                      0
56548 #define PBF_REG_INT_MASK                                                                             0xd80184UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
56549     #define PBF_REG_INT_MASK_ADDRESS_ERROR                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: PBF_REG_INT_STS.ADDRESS_ERROR .
56550     #define PBF_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                     0
56551 #define PBF_REG_INT_STS_WR                                                                           0xd80188UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
56552     #define PBF_REG_INT_STS_WR_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
56553     #define PBF_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                   0
56554 #define PBF_REG_INT_STS_CLR                                                                          0xd8018cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
56555     #define PBF_REG_INT_STS_CLR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
56556     #define PBF_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                  0
56557 #define PBF_REG_PRTY_MASK                                                                            0xd80194UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
56558     #define PBF_REG_PRTY_MASK_DATAPATH_REGISTERS                                                     (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS.DATAPATH_REGISTERS .
56559     #define PBF_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                               0
56560 #define PBF_REG_PRTY_MASK_H_0                                                                        0xd80204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56561     #define PBF_REG_PRTY_MASK_H_0_MEM041_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM041_I_ECC_RF_INT .
56562     #define PBF_REG_PRTY_MASK_H_0_MEM041_I_ECC_RF_INT_SHIFT                                          0
56563     #define PBF_REG_PRTY_MASK_H_0_MEM042_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM042_I_ECC_RF_INT .
56564     #define PBF_REG_PRTY_MASK_H_0_MEM042_I_ECC_RF_INT_SHIFT                                          1
56565     #define PBF_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT                                                (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT .
56566     #define PBF_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_SHIFT                                          2
56567     #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
56568     #define PBF_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT                                          3
56569     #define PBF_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT                                                (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM018_I_ECC_RF_INT .
56570     #define PBF_REG_PRTY_MASK_H_0_MEM018_I_ECC_RF_INT_SHIFT                                          4
56571     #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT                                              (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM009_I_ECC_0_RF_INT .
56572     #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_SHIFT                                        5
56573     #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT                                              (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM009_I_ECC_1_RF_INT .
56574     #define PBF_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT_SHIFT                                        6
56575     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_0_RF_INT .
56576     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_0_RF_INT_SHIFT                                        7
56577     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT                                              (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_1_RF_INT .
56578     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_1_RF_INT_SHIFT                                        8
56579     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_2_RF_INT                                              (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_2_RF_INT .
56580     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_2_RF_INT_SHIFT                                        9
56581     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_3_RF_INT                                              (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_3_RF_INT .
56582     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_3_RF_INT_SHIFT                                        10
56583     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_4_RF_INT                                              (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_4_RF_INT .
56584     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_4_RF_INT_SHIFT                                        11
56585     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_5_RF_INT                                              (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_5_RF_INT .
56586     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_5_RF_INT_SHIFT                                        12
56587     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_6_RF_INT                                              (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_6_RF_INT .
56588     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_6_RF_INT_SHIFT                                        13
56589     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_7_RF_INT                                              (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_7_RF_INT .
56590     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_7_RF_INT_SHIFT                                        14
56591     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_8_RF_INT                                              (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_8_RF_INT .
56592     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_8_RF_INT_SHIFT                                        15
56593     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_9_RF_INT                                              (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_9_RF_INT .
56594     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_9_RF_INT_SHIFT                                        16
56595     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_10_RF_INT                                             (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_10_RF_INT .
56596     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_10_RF_INT_SHIFT                                       17
56597     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_11_RF_INT                                             (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_11_RF_INT .
56598     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_11_RF_INT_SHIFT                                       18
56599     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_12_RF_INT                                             (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_12_RF_INT .
56600     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_12_RF_INT_SHIFT                                       19
56601     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_13_RF_INT                                             (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_13_RF_INT .
56602     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_13_RF_INT_SHIFT                                       20
56603     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_14_RF_INT                                             (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_14_RF_INT .
56604     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_14_RF_INT_SHIFT                                       21
56605     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_15_RF_INT                                             (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM012_I_ECC_15_RF_INT .
56606     #define PBF_REG_PRTY_MASK_H_0_MEM012_I_ECC_15_RF_INT_SHIFT                                       22
56607     #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
56608     #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_A0_SHIFT                                      24
56609     #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_B0                                            (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
56610     #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_BB_B0_SHIFT                                      23
56611     #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_K2                                               (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM040_I_MEM_PRTY .
56612     #define PBF_REG_PRTY_MASK_H_0_MEM040_I_MEM_PRTY_K2_SHIFT                                         23
56613     #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_A0                                            (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
56614     #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_A0_SHIFT                                      23
56615     #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_B0                                            (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
56616     #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_BB_B0_SHIFT                                      24
56617     #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2                                               (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
56618     #define PBF_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_K2_SHIFT                                         24
56619     #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
56620     #define PBF_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_SHIFT                                            25
56621     #define PBF_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
56622     #define PBF_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_SHIFT                                            26
56623     #define PBF_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
56624     #define PBF_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_SHIFT                                            27
56625     #define PBF_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
56626     #define PBF_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_SHIFT                                            28
56627     #define PBF_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
56628     #define PBF_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_SHIFT                                            29
56629     #define PBF_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
56630     #define PBF_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_SHIFT                                            30
56631 #define PBF_REG_PRTY_MASK_H_1                                                                        0xd80214UL //Access:RW   DataWidth:0x1b  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56632     #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM022_I_MEM_PRTY .
56633     #define PBF_REG_PRTY_MASK_H_1_MEM022_I_MEM_PRTY_SHIFT                                            0
56634     #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM023_I_MEM_PRTY .
56635     #define PBF_REG_PRTY_MASK_H_1_MEM023_I_MEM_PRTY_SHIFT                                            1
56636     #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM021_I_MEM_PRTY .
56637     #define PBF_REG_PRTY_MASK_H_1_MEM021_I_MEM_PRTY_SHIFT                                            2
56638     #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM020_I_MEM_PRTY .
56639     #define PBF_REG_PRTY_MASK_H_1_MEM020_I_MEM_PRTY_SHIFT                                            3
56640     #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
56641     #define PBF_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_SHIFT                                            4
56642     #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
56643     #define PBF_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_SHIFT                                            5
56644     #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
56645     #define PBF_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_SHIFT                                            6
56646     #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY                                                  (0x1<<7) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
56647     #define PBF_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_SHIFT                                            7
56648     #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY                                                  (0x1<<8) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM005_I_MEM_PRTY .
56649     #define PBF_REG_PRTY_MASK_H_1_MEM005_I_MEM_PRTY_SHIFT                                            8
56650     #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
56651     #define PBF_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_SHIFT                                            9
56652     #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
56653     #define PBF_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_SHIFT                                            10
56654     #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
56655     #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_A0_SHIFT                                      12
56656     #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
56657     #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_BB_B0_SHIFT                                      11
56658     #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM026_I_MEM_PRTY .
56659     #define PBF_REG_PRTY_MASK_H_1_MEM026_I_MEM_PRTY_K2_SHIFT                                         11
56660     #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
56661     #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_A0_SHIFT                                      11
56662     #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
56663     #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_BB_B0_SHIFT                                      12
56664     #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM027_I_MEM_PRTY .
56665     #define PBF_REG_PRTY_MASK_H_1_MEM027_I_MEM_PRTY_K2_SHIFT                                         12
56666     #define PBF_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY                                                  (0x1<<13) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM019_I_MEM_PRTY .
56667     #define PBF_REG_PRTY_MASK_H_1_MEM019_I_MEM_PRTY_SHIFT                                            13
56668     #define PBF_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
56669     #define PBF_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_SHIFT                                            14
56670     #define PBF_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM017_I_MEM_PRTY .
56671     #define PBF_REG_PRTY_MASK_H_1_MEM017_I_MEM_PRTY_SHIFT                                            15
56672     #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
56673     #define PBF_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_SHIFT                                            16
56674     #define PBF_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
56675     #define PBF_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_SHIFT                                            17
56676     #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
56677     #define PBF_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_SHIFT                                            18
56678     #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM024_I_MEM_PRTY .
56679     #define PBF_REG_PRTY_MASK_H_1_MEM024_I_MEM_PRTY_SHIFT                                            19
56680     #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM025_I_MEM_PRTY .
56681     #define PBF_REG_PRTY_MASK_H_1_MEM025_I_MEM_PRTY_SHIFT                                            20
56682     #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM037_I_MEM_PRTY .
56683     #define PBF_REG_PRTY_MASK_H_1_MEM037_I_MEM_PRTY_SHIFT                                            21
56684     #define PBF_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM036_I_MEM_PRTY .
56685     #define PBF_REG_PRTY_MASK_H_1_MEM036_I_MEM_PRTY_SHIFT                                            22
56686     #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM035_I_MEM_PRTY .
56687     #define PBF_REG_PRTY_MASK_H_1_MEM035_I_MEM_PRTY_SHIFT                                            23
56688     #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
56689     #define PBF_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_SHIFT                                            24
56690     #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM015_I_MEM_PRTY .
56691     #define PBF_REG_PRTY_MASK_H_1_MEM015_I_MEM_PRTY_SHIFT                                            25
56692     #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: PBF_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
56693     #define PBF_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_SHIFT                                            26
56694 #define PBF_REG_MEM_ECC_EVENTS                                                                       0xd80234UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
56695 #define PBF_REG_MEM040_I_MEM_DFT_K2                                                                  0xd80240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_ycmd_qs.i_pbf_mem_dorq_in_q_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56696 #define PBF_REG_MEM039_I_MEM_DFT_K2                                                                  0xd80244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_ycmd_qs.i_pbf_lra_ysem_in.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56697 #define PBF_REG_MEM041_I_MEM_DFT_K2                                                                  0xd80248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_even.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
56698 #define PBF_REG_MEM042_I_MEM_DFT_K2                                                                  0xd8024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_ycmd_qs.i_ycmd_qs_mem_odd.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
56699 #define PBF_REG_MEM038_I_MEM_DFT_K2                                                                  0xd80250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_ycmd_handler.i_pbf_mem_ycommand_prefetch_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56700 #define PBF_REG_MEM032_I_MEM_DFT_K2                                                                  0xd80254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_pmsgb.i_pbf_lra_y2p_sbinfo.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56701 #define PBF_REG_MEM031_I_MEM_DFT_K2                                                                  0xd80258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_pmsgb.i_pbf_lra_y2p_msg.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56702 #define PBF_REG_MEM033_I_MEM_DFT_K2                                                                  0xd8025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_pmsgb.i_pbf_mem_parsing_info_database.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56703 #define PBF_REG_MEM030_I_MEM_DFT_K2                                                                  0xd80260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_pmsgb.i_pbf_lra_parse_info_prefetch.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56704 #define PBF_REG_MEM029_I_MEM_DFT_K2                                                                  0xd80264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_pcmd_handler.i_pbf_lra_psem_in.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56705 #define PBF_REG_MEM022_I_MEM_DFT_K2                                                                  0xd80268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_hdr_parser.i_pbf_mem_hprs_data_in_buff.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56706 #define PBF_REG_MEM023_I_MEM_DFT_K2                                                                  0xd8026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_hdr_parser.i_pbf_mem_hprs_ysinfo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56707 #define PBF_REG_MEM020_I_MEM_DFT_K2                                                                  0xd80270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_hdr_parser.i_pbf_mem_extracted_hdr.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56708 #define PBF_REG_MEM003_I_MEM_DFT_K2                                                                  0xd80274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pb1_db.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56709 #define PBF_REG_MEM005_I_MEM_DFT_K2                                                                  0xd80278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pb1_tq_low.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56710 #define PBF_REG_MEM004_I_MEM_DFT_K2                                                                  0xd8027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pb1_tq_high.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56711 #define PBF_REG_MEM026_I_MEM_DFT_K2                                                                  0xd80280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_mrku.i_fifo_mem_pb1_egress_out.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56712 #define PBF_REG_MEM019_I_MEM_DFT_K2                                                                  0xd80284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_hb.i_hb_mem.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56713 #define PBF_REG_MEM018_I_MEM_DFT_K2                                                                  0xd80288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_hahd.i_pbf_mem_header_database.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
56714 #define PBF_REG_MEM017_I_MEM_DFT_K2                                                                  0xd8028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_hahd.i_pbf_mem_hdr_dbase_prefetch.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56715 #define PBF_REG_MEM008_I_MEM_DFT_K2                                                                  0xd80290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pb2_db.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56716 #define PBF_REG_MEM011_I_MEM_DFT_K2                                                                  0xd80294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pb2_tq_low.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56717 #define PBF_REG_MEM010_I_MEM_DFT_K2                                                                  0xd80298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pb2_tq_high.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56718 #define PBF_REG_MEM009_I_MEM_DFT_K2                                                                  0xd8029cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pb2_l1.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
56719 #define PBF_REG_MEM024_I_MEM_DFT_K2                                                                  0xd802a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_hm.i_fifo_mem_pb2_egress_out.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56720 #define PBF_REG_MEM025_I_MEM_DFT_K2                                                                  0xd802a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_hm.i_pbf_mem_hm_cmd_q.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56721 #define PBF_REG_MEM036_I_MEM_DFT_K2                                                                  0xd802a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_smg.i_pbf_lra_smg_msg_in.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56722 #define PBF_REG_MEM014_I_MEM_DFT_K2                                                                  0xd802acUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_btbif.i_pbf_mem_btbif_ycommand_q.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56723 #define PBF_REG_MEM015_I_MEM_DFT_K2                                                                  0xd802b0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_btbif.i_pbf_sfifo_btbif_pcommand_q.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56724 #define PBF_REG_MEM012_I_MEM_DFT_K2                                                                  0xd802b4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pbf.i_pbf_btbif.i_btbif_buff.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
56725 #define PBF_REG_PXP_REQ_IF_INIT_CRD                                                                  0xd80400UL //Access:RW   DataWidth:0x3   PXP read request interface initial credit - transoriented.  Chips: BB_A0 BB_B0 K2
56726 #define PBF_REG_TDIF_PASS_THROUGH_INIT_CRD                                                           0xd80404UL //Access:RW   DataWidth:0x6   TDIF pass-through command interface initial credit.  Chips: BB_A0 BB_B0 K2
56727 #define PBF_REG_TDIF_NON_PASS_THROUGH_INIT_CRD                                                       0xd80408UL //Access:RW   DataWidth:0x6   TDIF non_pass-through command interface initial credit.  Chips: BB_A0 BB_B0 K2
56728 #define PBF_REG_QM_LINE_CREDIT_IF_INIT_CRD                                                           0xd8040cUL //Access:RW   DataWidth:0x2   QM line credit interface initial credit.  Chips: BB_A0 BB_B0 K2
56729 #define PBF_REG_PXP_INT_WRREQ_IF_INIT_CRD                                                            0xd80410UL //Access:RW   DataWidth:0x2   PXP internal write interface initial credit - transoriented.  Chips: BB_A0 BB_B0 K2
56730 #define PBF_REG_TM_IF_INIT_CRD                                                                       0xd80414UL //Access:RW   DataWidth:0x3   TM interface initial credit - transoriented.  Chips: BB_A0 BB_B0 K2
56731 #define PBF_REG_PCM_IF_INIT_CRD                                                                      0xd80418UL //Access:RW   DataWidth:0x6   PCM interface initial credit.  Chips: BB_A0 BB_B0 K2
56732 #define PBF_REG_TCM_IF_INIT_CRD                                                                      0xd8041cUL //Access:RW   DataWidth:0x4   TCM interface initial credit.  Chips: BB_A0 BB_B0 K2
56733 #define PBF_REG_MCM_IF_INIT_CRD                                                                      0xd80420UL //Access:RW   DataWidth:0x4   MCM interface initial credit.  Chips: BB_A0 BB_B0 K2
56734 #define PBF_REG_UCM_IF_INIT_CRD                                                                      0xd80424UL //Access:RW   DataWidth:0x4   UCM interface initial credit.  Chips: BB_A0 BB_B0 K2
56735 #define PBF_REG_XCM_IF_INIT_CRD                                                                      0xd80428UL //Access:RW   DataWidth:0x4   XCM interface initial credit.  Chips: BB_A0 BB_B0 K2
56736 #define PBF_REG_YCM_IF_INIT_CRD                                                                      0xd8042cUL //Access:RW   DataWidth:0x4   YCM interface initial credit.  Chips: BB_A0 BB_B0 K2
56737 #define PBF_REG_PB1_DB_ALMOST_FULL_THRSH                                                             0xd80440UL //Access:RW   DataWidth:0x7   Almost full threhsold for PB1 that indicates the occupancy before full will be raised.  Chips: BB_A0 BB_B0 K2
56738 #define PBF_REG_PB2_DB_ALMOST_FULL_THRSH                                                             0xd80444UL //Access:RW   DataWidth:0x5   Almost full threhsold for PB2 that indicates the occupancy before full will be raised.  Chips: BB_A0 BB_B0 K2
56739 #define PBF_REG_PB1_TQ_ALMOST_FULL_THRSH                                                             0xd80448UL //Access:RW   DataWidth:0x7   Almost full threhsold for PB1 that indicates the occupancy before full will be raised.  Chips: BB_A0 BB_B0 K2
56740 #define PBF_REG_PB2_TQ_ALMOST_FULL_THRSH                                                             0xd8044cUL //Access:RW   DataWidth:0x7   Almost full threhsold for PB2 that indicates the occupancy before full will be raised.  Chips: BB_A0 BB_B0 K2
56741 #define PBF_REG_HPRS_DIN_BUFF_ALMOST_FULL_THRSH                                                      0xd80450UL //Access:RW   DataWidth:0x6   Almost full threhsold for header parser data input buffer that indicates the occupancy before full will be raised.  Chips: BB_A0 BB_B0 K2
56742 #define PBF_REG_HPRS_EXT_HDR_BUFF_ALMOST_FULL_THRSH                                                  0xd80454UL //Access:RW   DataWidth:0x5   Almost full threhsold for header parser extracted header buffer that indicates the occupancy before full will be raised.  Chips: BB_A0 BB_B0 K2
56743 #define PBF_REG_HB_MEM_ALMOST_FULL_THRSH                                                             0xd80458UL //Access:RW   DataWidth:0x5   Almost full threhsold for the memory that holds the header builder header, that indicates the occupancy before full will be raised.  Chips: BB_A0 BB_B0 K2
56744 #define PBF_REG_MRKU_ALMOST_FULL_THRSH                                                               0xd8045cUL //Access:RW   DataWidth:0x4   Almost full threhsold for the FIFO at the output of PB1, that indicates the occupancy before full will be raised.  Chips: BB_A0 BB_B0 K2
56745 #define PBF_REG_TAG_ETHERTYPE_0                                                                      0xd80480UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 0.  Chips: BB_A0 BB_B0 K2
56746 #define PBF_REG_TAG_ETHERTYPE_1                                                                      0xd80484UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 1.  Chips: BB_A0 BB_B0 K2
56747 #define PBF_REG_TAG_ETHERTYPE_2                                                                      0xd80488UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 2.  Chips: BB_A0 BB_B0 K2
56748 #define PBF_REG_TAG_ETHERTYPE_3                                                                      0xd8048cUL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 3.  Chips: BB_A0 BB_B0 K2
56749 #define PBF_REG_TAG_ETHERTYPE_4                                                                      0xd80490UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 4.  Chips: BB_A0 BB_B0 K2
56750 #define PBF_REG_TAG_ETHERTYPE_5                                                                      0xd80494UL //Access:RW   DataWidth:0x10  The Ethernet type value for L2 tag 5.  Chips: BB_A0 BB_B0 K2
56751 #define PBF_REG_TAG_LEN_0                                                                            0xd80498UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 0.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
56752 #define PBF_REG_TAG_LEN_1                                                                            0xd8049cUL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 1.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
56753 #define PBF_REG_TAG_LEN_2                                                                            0xd804a0UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 2.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
56754 #define PBF_REG_TAG_LEN_3                                                                            0xd804a4UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 3.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
56755 #define PBF_REG_TAG_LEN_4                                                                            0xd804a8UL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 4.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
56756 #define PBF_REG_TAG_LEN_5                                                                            0xd804acUL //Access:RW   DataWidth:0x3   The length of the info field for L2 tag 5.  The length is between 2B and 14B; in 2B granularity.  Chips: BB_A0 BB_B0 K2
56757 #define PBF_REG_FIRST_HDR_HDRS_AFTER_BASIC                                                           0xd804b0UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56758 #define PBF_REG_FIRST_HDR_HDRS_AFTER_LLC                                                             0xd804b4UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56759 #define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_0                                                           0xd804b8UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56760 #define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_1                                                           0xd804bcUL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56761 #define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_2                                                           0xd804c0UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56762 #define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_3                                                           0xd804c4UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56763 #define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_4                                                           0xd804c8UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56764 #define PBF_REG_FIRST_HDR_HDRS_AFTER_TAG_5                                                           0xd804ccUL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56765 #define PBF_REG_FIRST_HDR_MUST_HAVE_HDRS                                                             0xd804d0UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which headers must appear in the packet on this port.  This applies to the tunnel header in encapsulated packets or to the regular header of non-encapsulated packets.  Chips: BB_A0 BB_B0 K2
56766 #define PBF_REG_INNER_HDR_HDRS_AFTER_BASIC                                                           0xd804d4UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after the basic Ethernet header on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56767 #define PBF_REG_INNER_HDR_HDRS_AFTER_LLC                                                             0xd804d8UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after the LLC header on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56768 #define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_0                                                           0xd804dcUL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _0 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56769 #define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_1                                                           0xd804e0UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _1 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56770 #define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_2                                                           0xd804e4UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _2 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56771 #define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_3                                                           0xd804e8UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _3 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56772 #define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_4                                                           0xd804ecUL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _4 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56773 #define PBF_REG_INNER_HDR_HDRS_AFTER_TAG_5                                                           0xd804f0UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which L2 hdrs may appear after L2 tag _5 on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56774 #define PBF_REG_INNER_HDR_MUST_HAVE_HDRS                                                             0xd804f4UL //Access:RW   DataWidth:0x8   Per-port: Bit-map indicating which headers must appear in the packet on this port.  Applicable only on encapsulated packets and refers to the inner (encapsulated) header.  Chips: BB_A0 BB_B0 K2
56775 #define PBF_REG_LLC_TYPE_THRESHOLD                                                                   0xd804f8UL //Access:RW   DataWidth:0x10  Upper value of LLC Ethertype range.  Chips: BB_A0 BB_B0 K2
56776 #define PBF_REG_LLC_JUMBO_TYPE                                                                       0xd804fcUL //Access:RW   DataWidth:0x10  Jumbo value of LLC Ethertype.  Chips: BB_A0 BB_B0 K2
56777 #define PBF_REG_GRE_ETH_TYPE                                                                         0xd80500UL //Access:RW   DataWidth:0x10  Ethertype for encapsulated ethernet used in GRE header parsing.  Chips: BB_A0 BB_B0 K2
56778 #define PBF_REG_IPV4_TYPE                                                                            0xd80504UL //Access:RW   DataWidth:0x10  IPv4 Ethertype.  Chips: BB_A0 BB_B0 K2
56779 #define PBF_REG_IPV6_TYPE                                                                            0xd80508UL //Access:RW   DataWidth:0x10  IPv6 Ethertype.  Chips: BB_A0 BB_B0 K2
56780 #define PBF_REG_TCP_PROTOCOL                                                                         0xd8050cUL //Access:RW   DataWidth:0x8   Value used to designate TCP in the IPv4 Protocol and IPv6 Next Header fields.  Chips: BB_A0 BB_B0 K2
56781 #define PBF_REG_UDP_PROTOCOL                                                                         0xd80510UL //Access:RW   DataWidth:0x8   Value used to designate UDP in the IPv4 Protocol and IPv6 Next Header fields.  Chips: BB_A0 BB_B0 K2
56782 #define PBF_REG_GRE_PROTOCOL                                                                         0xd80514UL //Access:RW   DataWidth:0x8   Value used to designate GRE in the IPv4 Protocol and IPv6 Next Header fields.  Chips: BB_A0 BB_B0 K2
56783 #define PBF_REG_VXLAN_PORT                                                                           0xd80518UL //Access:RW   DataWidth:0x10  Dest port value used to designate a VXLAN header following the UDP header.  Chips: BB_A0 BB_B0 K2
56784 #define PBF_REG_NGE_PORT                                                                             0xd8051cUL //Access:RW   DataWidth:0x10  Dest port value used to designate a NGE header following the UDP header.  Chips: BB_B0 K2
56785 #define PBF_REG_NGE_ETH_TYPE                                                                         0xd80520UL //Access:RW   DataWidth:0x10  Ethertype for encapsulated ethernet used in NGE header parsing.  Chips: BB_B0 K2
56786 #define PBF_REG_NGE_COMP_VER                                                                         0xd80524UL //Access:RW   DataWidth:0x1   Per-port:  Flag to compare the value of nge version to 2'b00.  Chips: BB_B0 K2
56787 #define PBF_REG_PROP_HDR_SIZE                                                                        0xd80580UL //Access:RW   DataWidth:0x3   PORT SPLIT. Size of the Propriatery/HiGig header. (in 4B increments). If HiGig is disabled this value should be 0.  Chips: BB_A0 BB_B0 K2
56788 #define PBF_REG_REGULAR_INBAND_TAG_ORDER                                                             0xd80584UL //Access:RW   DataWidth:0x1c  The regular inband TAG order. Reset value is in the order from left to right: tag0; tag1; tag2; tag3; tag4; tag5; llc-snap.  Chips: BB_A0 BB_B0 K2
56789 #define PBF_REG_T_TAG_TAGNUM                                                                         0xd80588UL //Access:RW   DataWidth:0x4   Per-Port: Specifies the flexible L2 tag to be used for T-tag.  The MSB enables T-tag recognition.  Chips: BB_A0 BB_B0 K2
56790 #define PBF_REG_DST_MAC_GLOBAL_0                                                                     0xd8058cUL //Access:RW   DataWidth:0x20  Global destination address match value.  Chips: BB_A0 BB_B0 K2
56791 #define PBF_REG_DST_MAC_GLOBAL_1                                                                     0xd80590UL //Access:RW   DataWidth:0x10  Global destination address match value.  Chips: BB_A0 BB_B0 K2
56792 #define PBF_REG_DST_MAC_GLOBAL_MASK_0                                                                0xd80594UL //Access:RW   DataWidth:0x20  Mask for global destination address match value. A zero in this                 register will cause the corresponding bit to not be included in the match.  Chips: BB_A0 BB_B0 K2
56793 #define PBF_REG_DST_MAC_GLOBAL_MASK_1                                                                0xd80598UL //Access:RW   DataWidth:0x10  Mask for global destination address match value. A zero in this                 register will cause the corresponding bit to not be included in the match.  Chips: BB_A0 BB_B0 K2
56794 #define PBF_REG_UDP_DST_PORT_CFG_0                                                                   0xd8059cUL //Access:RW   DataWidth:0x10  UDP destination port configuration 0 for match check.  Chips: BB_A0 BB_B0 K2
56795 #define PBF_REG_UDP_DST_PORT_CFG_1                                                                   0xd805a0UL //Access:RW   DataWidth:0x10  UDP destination port configuration 1 for match check.  Chips: BB_A0 BB_B0 K2
56796 #define PBF_REG_UDP_DST_PORT_CFG_2                                                                   0xd805a4UL //Access:RW   DataWidth:0x10  UDP destination port configuration 2 for match check.  Chips: BB_A0 BB_B0 K2
56797 #define PBF_REG_BTB_SHARED_AREA_SIZE                                                                 0xd805c0UL //Access:RW   DataWidth:0xb   Number of shared BTB 256 byte blocks which can be used by all TC-s in the port.  Chips: BB_A0 BB_B0 K2
56798 #define PBF_REG_BTB_ALLOCATED_BLOCKS_SHARED                                                          0xd805c4UL //Access:R    DataWidth:0xc   Number of blocks that are currently allocated in the shared area of the port.  Chips: BB_A0 BB_B0 K2
56799 #define PBF_REG_JUMBO_PKT_THRSH                                                                      0xd805c8UL //Access:RW   DataWidth:0x6   Jumbo packet threshold in 256 byte blocks to determine if a TC can use the BTB shared area.  Chips: BB_A0 BB_B0 K2
56800 #define PBF_REG_PRIORITY_CLIENT                                                                      0xd805ccUL //Access:RW   DataWidth:0x20  Each nibble in the register from LS nibble to MS nibble holds the TC number of the corresponding priority. bits 3:0 hold the TC number from 0 to 7 of the highest priority TC. bits 31:28 hold the TC number from 0 to 7 of the lowest priority TC.  Chips: BB_A0 BB_B0 K2
56801 #define PBF_REG_NUM_STRICT_PRIORITY_SLOTS                                                            0xd805d0UL //Access:RW   DataWidth:0xa   The number of strict priority arbitration slots between 2 RR arbitration slots in the ycommand arbiter. A value of 0 means no strict priority cycles; i.e. the strict-priority w/ anti-starvation arbiter is a RR arbiter. A value of all ones means no RR slots; i.e. the strict-priority w/ anti-starvation arbiter is a strict-priority arbiter.  Chips: BB_A0 BB_B0 K2
56802 #define PBF_REG_L2_EDPM_THRSH                                                                        0xd805d4UL //Access:RW   DataWidth:0x8   L2 EDPM threshold in 256 byte blocks. Only if all TC-s have allocated blocks below this threshold, L2 EDPM will be enabled.  Chips: BB_A0 BB_B0 K2
56803 #define PBF_REG_CPMU_THRSH                                                                           0xd805d8UL //Access:RW   DataWidth:0xb   CPMU threshold in 256 byte blocks. Only if all TC-s in port N have allocated blocks above this threshold, the corresponding bit for that port will be set towards CPMU.  Chips: BB_A0 BB_B0 K2
56804 #define PBF_REG_IP_ID_MASK_0                                                                         0xd80600UL //Access:RW   DataWidth:0x10  1st bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.  Chips: BB_A0 BB_B0 K2
56805 #define PBF_REG_IP_ID_MASK_1                                                                         0xd80604UL //Access:RW   DataWidth:0x10  2nd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.  Chips: BB_A0 BB_B0 K2
56806 #define PBF_REG_IP_ID_MASK_2                                                                         0xd80608UL //Access:RW   DataWidth:0x10  3rd bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.  Chips: BB_A0 BB_B0 K2
56807 #define PBF_REG_IP_ID_MASK_3                                                                         0xd8060cUL //Access:RW   DataWidth:0x10  4th bit mask used to control the rollover when increasing the IP ID field in the packet. Selected per command.  Chips: BB_A0 BB_B0 K2
56808 #define PBF_REG_ACK_FLG_MODE                                                                         0xd80610UL //Access:RW   DataWidth:0x2   Update mode for the ACK flag  Chips: BB_A0 BB_B0 K2
56809 #define PBF_REG_CWR_FLG_MODE                                                                         0xd80614UL //Access:RW   DataWidth:0x2   Update mode for the CWR flag  Chips: BB_A0 BB_B0 K2
56810 #define PBF_REG_ECE_FLG_MODE                                                                         0xd80618UL //Access:RW   DataWidth:0x2   Update mode for the ECE flag  Chips: BB_A0 BB_B0 K2
56811 #define PBF_REG_FIN_FLG_MODE                                                                         0xd8061cUL //Access:RW   DataWidth:0x2   Update mode for the FIN flag  Chips: BB_A0 BB_B0 K2
56812 #define PBF_REG_NS_FLG_MODE                                                                          0xd80620UL //Access:RW   DataWidth:0x2   Update mode for the NS flag  Chips: BB_A0 BB_B0 K2
56813 #define PBF_REG_PUSH_FLG_MODE                                                                        0xd80624UL //Access:RW   DataWidth:0x2   Update mode for the PUSH flag  Chips: BB_A0 BB_B0 K2
56814 #define PBF_REG_RST_FLG_MODE                                                                         0xd80628UL //Access:RW   DataWidth:0x2   Update mode for the RESET flag  Chips: BB_A0 BB_B0 K2
56815 #define PBF_REG_SYN_FLG_MODE                                                                         0xd8062cUL //Access:RW   DataWidth:0x2   Update mode for the SYN flag  Chips: BB_A0 BB_B0 K2
56816 #define PBF_REG_URG_FLG_MODE                                                                         0xd80630UL //Access:RW   DataWidth:0x2   Update mode for the URG flag  Chips: BB_A0 BB_B0 K2
56817 #define PBF_REG_TCM_SND_NXT_REG_OFFSET                                                               0xd80634UL //Access:RW   DataWidth:0x4   Update mode for the URG flag  Chips: BB_A0 BB_B0 K2
56818 #define PBF_REG_PCI_VQ_ID                                                                            0xd80640UL //Access:RW   DataWidth:0x5   PCI VOQ ID used in read request to PCI.  Chips: BB_A0 BB_B0 K2
56819 #define PBF_REG_DROP_PKT_UPON_ERR                                                                    0xd80644UL //Access:RW   DataWidth:0x1   if set, packets with a PCIE/DIF error will be sent to BTB with a drop indication, otherwise will be sent with an error indication.  Chips: BB_A0 BB_B0 K2
56820 #define PBF_REG_PER_VOQ_STAT_MASK                                                                    0xd80658UL //Access:RW   DataWidth:0x14  per VOQ indication if it should be accounted for in bytes/packet statistics  Chips: BB_A0 BB_B0 K2
56821 #define PBF_REG_NUM_PKTS_SENT_TO_BTB                                                                 0xd8065cUL //Access:RC   DataWidth:0x20  Number of packets sent to BTB  Chips: BB_A0 BB_B0 K2
56822 #define PBF_REG_NUM_BYTES_SENT_TO_BTB                                                                0xd80660UL //Access:ST   DataWidth:0x30  Number of bytes sent to BTB  Chips: BB_A0 BB_B0 K2
56823 #define PBF_REG_NUM_BYTES_SENT_TO_BTB_SIZE                                                           2
56824 #define PBF_REG_NUM_PKTS_RECEIVED_WITH_ERROR                                                         0xd80668UL //Access:RC   DataWidth:0x8   Number of packets received with error indication from PXP/TDIF  Chips: BB_A0 BB_B0 K2
56825 #define PBF_REG_NUM_PKTS_SENT_WITH_ERROR_TO_BTB                                                      0xd8066cUL //Access:RC   DataWidth:0x8   Number of packets sent to BTB with error indication  Chips: BB_A0 BB_B0 K2
56826 #define PBF_REG_NUM_PKTS_SENT_WITH_DROP_TO_BTB                                                       0xd80670UL //Access:RC   DataWidth:0x8   Number of packets sent to BTB with drop indication  Chips: BB_A0 BB_B0 K2
56827 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0                                                               0xd806a0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 0.  Chips: BB_A0 BB_B0 K2
56828 #define PBF_REG_YCMD_QS_THRSH_VOQ0                                                                   0xd806a4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 0 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56829 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ0                                                    0xd806a8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 0  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56830 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ0                                                            0xd806acUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 0 from YSTORM.  Chips: BB_A0 BB_B0 K2
56831 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ0                                                                 0xd806b0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 0.  Chips: BB_A0 BB_B0 K2
56832 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ0                                                         0xd806b4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 0. Reset upon init.  Chips: BB_A0 BB_B0 K2
56833 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ0                                                               0xd806b8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 0.  Chips: BB_A0 BB_B0 K2
56834 #define PBF_REG_BTB_GUARANTEED_VOQ0                                                                  0xd806bcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 0  Chips: BB_A0 BB_B0 K2
56835 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0                                                           0xd806c0UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56836     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_MAX_SHARED_ALLOC_VOQ0                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 0
56837     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_MAX_SHARED_ALLOC_VOQ0_SHIFT                       0
56838     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_VOQ0                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56839     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_VOQ0_SHIFT                         16
56840     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ0                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56841     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ0_SHIFT               17
56842 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ0                                                            0xd806c4UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 0 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56843 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ0                                                       0xd806c8UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 0. Reset upon init.  Chips: BB_A0 BB_B0 K2
56844 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ0                                                       0xd806ccUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 0. Reset upon init.  Chips: BB_A0 BB_B0 K2
56845 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1                                                               0xd806e0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 1.  Chips: BB_A0 BB_B0 K2
56846 #define PBF_REG_YCMD_QS_THRSH_VOQ1                                                                   0xd806e4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 1 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56847 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ1                                                    0xd806e8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 1  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56848 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ1                                                            0xd806ecUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 1 from YSTORM.  Chips: BB_A0 BB_B0 K2
56849 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ1                                                                 0xd806f0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 1.  Chips: BB_A0 BB_B0 K2
56850 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ1                                                         0xd806f4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 1. Reset upon init.  Chips: BB_A0 BB_B0 K2
56851 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ1                                                               0xd806f8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 1.  Chips: BB_A0 BB_B0 K2
56852 #define PBF_REG_BTB_GUARANTEED_VOQ1                                                                  0xd806fcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 1  Chips: BB_A0 BB_B0 K2
56853 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1                                                           0xd80700UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56854     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_MAX_SHARED_ALLOC_VOQ1                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 1
56855     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_MAX_SHARED_ALLOC_VOQ1_SHIFT                       0
56856     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_VOQ1                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56857     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_VOQ1_SHIFT                         16
56858     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ1                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56859     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ1_SHIFT               17
56860 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ1                                                            0xd80704UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 1 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56861 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ1                                                       0xd80708UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 1. Reset upon init.  Chips: BB_A0 BB_B0 K2
56862 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ1                                                       0xd8070cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 1. Reset upon init.  Chips: BB_A0 BB_B0 K2
56863 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2                                                               0xd80720UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 2.  Chips: BB_A0 BB_B0 K2
56864 #define PBF_REG_YCMD_QS_THRSH_VOQ2                                                                   0xd80724UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 2 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56865 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ2                                                    0xd80728UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 2  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56866 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ2                                                            0xd8072cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 2 from YSTORM.  Chips: BB_A0 BB_B0 K2
56867 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ2                                                                 0xd80730UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 2.  Chips: BB_A0 BB_B0 K2
56868 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ2                                                         0xd80734UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 2. Reset upon init.  Chips: BB_A0 BB_B0 K2
56869 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ2                                                               0xd80738UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 2.  Chips: BB_A0 BB_B0 K2
56870 #define PBF_REG_BTB_GUARANTEED_VOQ2                                                                  0xd8073cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 2  Chips: BB_A0 BB_B0 K2
56871 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2                                                           0xd80740UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56872     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_MAX_SHARED_ALLOC_VOQ2                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 2
56873     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_MAX_SHARED_ALLOC_VOQ2_SHIFT                       0
56874     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_VOQ2                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56875     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_VOQ2_SHIFT                         16
56876     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ2                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56877     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ2_SHIFT               17
56878 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ2                                                            0xd80744UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 2 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56879 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ2                                                       0xd80748UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 2. Reset upon init.  Chips: BB_A0 BB_B0 K2
56880 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ2                                                       0xd8074cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 2. Reset upon init.  Chips: BB_A0 BB_B0 K2
56881 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3                                                               0xd80760UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 3.  Chips: BB_A0 BB_B0 K2
56882 #define PBF_REG_YCMD_QS_THRSH_VOQ3                                                                   0xd80764UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 3 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56883 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ3                                                    0xd80768UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 3  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56884 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ3                                                            0xd8076cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 3 from YSTORM.  Chips: BB_A0 BB_B0 K2
56885 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ3                                                                 0xd80770UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 3.  Chips: BB_A0 BB_B0 K2
56886 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ3                                                         0xd80774UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 3. Reset upon init.  Chips: BB_A0 BB_B0 K2
56887 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ3                                                               0xd80778UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 3.  Chips: BB_A0 BB_B0 K2
56888 #define PBF_REG_BTB_GUARANTEED_VOQ3                                                                  0xd8077cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 3  Chips: BB_A0 BB_B0 K2
56889 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3                                                           0xd80780UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56890     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_MAX_SHARED_ALLOC_VOQ3                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 3
56891     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_MAX_SHARED_ALLOC_VOQ3_SHIFT                       0
56892     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_VOQ3                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56893     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_VOQ3_SHIFT                         16
56894     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ3                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56895     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ3_SHIFT               17
56896 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ3                                                            0xd80784UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 3 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56897 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ3                                                       0xd80788UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 3. Reset upon init.  Chips: BB_A0 BB_B0 K2
56898 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ3                                                       0xd8078cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 3. Reset upon init.  Chips: BB_A0 BB_B0 K2
56899 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4                                                               0xd807a0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 4.  Chips: BB_A0 BB_B0 K2
56900 #define PBF_REG_YCMD_QS_THRSH_VOQ4                                                                   0xd807a4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 4 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56901 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ4                                                    0xd807a8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 4  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56902 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ4                                                            0xd807acUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 4 from YSTORM.  Chips: BB_A0 BB_B0 K2
56903 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ4                                                                 0xd807b0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 4.  Chips: BB_A0 BB_B0 K2
56904 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ4                                                         0xd807b4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 4. Reset upon init.  Chips: BB_A0 BB_B0 K2
56905 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ4                                                               0xd807b8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 4.  Chips: BB_A0 BB_B0 K2
56906 #define PBF_REG_BTB_GUARANTEED_VOQ4                                                                  0xd807bcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 4  Chips: BB_A0 BB_B0 K2
56907 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4                                                           0xd807c0UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56908     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_MAX_SHARED_ALLOC_VOQ4                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 4
56909     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_MAX_SHARED_ALLOC_VOQ4_SHIFT                       0
56910     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_VOQ4                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56911     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_VOQ4_SHIFT                         16
56912     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ4                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56913     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ4_SHIFT               17
56914 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ4                                                            0xd807c4UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 4 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56915 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ4                                                       0xd807c8UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 4. Reset upon init.  Chips: BB_A0 BB_B0 K2
56916 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ4                                                       0xd807ccUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 4. Reset upon init.  Chips: BB_A0 BB_B0 K2
56917 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5                                                               0xd807e0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 5.  Chips: BB_A0 BB_B0 K2
56918 #define PBF_REG_YCMD_QS_THRSH_VOQ5                                                                   0xd807e4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 5 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56919 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ5                                                    0xd807e8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 5  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56920 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ5                                                            0xd807ecUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 5 from YSTORM.  Chips: BB_A0 BB_B0 K2
56921 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ5                                                                 0xd807f0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 5.  Chips: BB_A0 BB_B0 K2
56922 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ5                                                         0xd807f4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 5. Reset upon init.  Chips: BB_A0 BB_B0 K2
56923 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ5                                                               0xd807f8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 5.  Chips: BB_A0 BB_B0 K2
56924 #define PBF_REG_BTB_GUARANTEED_VOQ5                                                                  0xd807fcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 5  Chips: BB_A0 BB_B0 K2
56925 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5                                                           0xd80800UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56926     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_MAX_SHARED_ALLOC_VOQ5                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 5
56927     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_MAX_SHARED_ALLOC_VOQ5_SHIFT                       0
56928     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_VOQ5                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56929     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_VOQ5_SHIFT                         16
56930     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ5                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56931     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ5_SHIFT               17
56932 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ5                                                            0xd80804UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 5 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56933 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ5                                                       0xd80808UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 5. Reset upon init.  Chips: BB_A0 BB_B0 K2
56934 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ5                                                       0xd8080cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 5. Reset upon init.  Chips: BB_A0 BB_B0 K2
56935 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6                                                               0xd80820UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 6.  Chips: BB_A0 BB_B0 K2
56936 #define PBF_REG_YCMD_QS_THRSH_VOQ6                                                                   0xd80824UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 6 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56937 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ6                                                    0xd80828UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 6  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56938 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ6                                                            0xd8082cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 6 from YSTORM.  Chips: BB_A0 BB_B0 K2
56939 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ6                                                                 0xd80830UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 6.  Chips: BB_A0 BB_B0 K2
56940 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ6                                                         0xd80834UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 6. Reset upon init.  Chips: BB_A0 BB_B0 K2
56941 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ6                                                               0xd80838UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 6.  Chips: BB_A0 BB_B0 K2
56942 #define PBF_REG_BTB_GUARANTEED_VOQ6                                                                  0xd8083cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 6  Chips: BB_A0 BB_B0 K2
56943 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6                                                           0xd80840UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56944     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_MAX_SHARED_ALLOC_VOQ6                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 6
56945     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_MAX_SHARED_ALLOC_VOQ6_SHIFT                       0
56946     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_VOQ6                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56947     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_VOQ6_SHIFT                         16
56948     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ6                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56949     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ6_SHIFT               17
56950 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ6                                                            0xd80844UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 6 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56951 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ6                                                       0xd80848UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 6. Reset upon init.  Chips: BB_A0 BB_B0 K2
56952 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ6                                                       0xd8084cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 6. Reset upon init.  Chips: BB_A0 BB_B0 K2
56953 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7                                                               0xd80860UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 7.  Chips: BB_A0 BB_B0 K2
56954 #define PBF_REG_YCMD_QS_THRSH_VOQ7                                                                   0xd80864UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 7 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56955 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ7                                                    0xd80868UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 7  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56956 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ7                                                            0xd8086cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 7 from YSTORM.  Chips: BB_A0 BB_B0 K2
56957 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ7                                                                 0xd80870UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 7.  Chips: BB_A0 BB_B0 K2
56958 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ7                                                         0xd80874UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 7. Reset upon init.  Chips: BB_A0 BB_B0 K2
56959 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ7                                                               0xd80878UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 7.  Chips: BB_A0 BB_B0 K2
56960 #define PBF_REG_BTB_GUARANTEED_VOQ7                                                                  0xd8087cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 7  Chips: BB_A0 BB_B0 K2
56961 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7                                                           0xd80880UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56962     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_MAX_SHARED_ALLOC_VOQ7                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 7
56963     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_MAX_SHARED_ALLOC_VOQ7_SHIFT                       0
56964     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_VOQ7                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56965     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_VOQ7_SHIFT                         16
56966     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ7                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56967     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ7_SHIFT               17
56968 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ7                                                            0xd80884UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 7 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56969 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ7                                                       0xd80888UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 7. Reset upon init.  Chips: BB_A0 BB_B0 K2
56970 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ7                                                       0xd8088cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 7. Reset upon init.  Chips: BB_A0 BB_B0 K2
56971 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8                                                               0xd808a0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 8.  Chips: BB_A0 BB_B0 K2
56972 #define PBF_REG_YCMD_QS_THRSH_VOQ8                                                                   0xd808a4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 8 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56973 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ8                                                    0xd808a8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 8  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56974 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ8                                                            0xd808acUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 8 from YSTORM.  Chips: BB_A0 BB_B0 K2
56975 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ8                                                                 0xd808b0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 8.  Chips: BB_A0 BB_B0 K2
56976 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ8                                                         0xd808b4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 8. Reset upon init.  Chips: BB_A0 BB_B0 K2
56977 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ8                                                               0xd808b8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 8.  Chips: BB_A0 BB_B0 K2
56978 #define PBF_REG_BTB_GUARANTEED_VOQ8                                                                  0xd808bcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 8  Chips: BB_A0 BB_B0 K2
56979 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8                                                           0xd808c0UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56980     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_MAX_SHARED_ALLOC_VOQ8                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 8
56981     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_MAX_SHARED_ALLOC_VOQ8_SHIFT                       0
56982     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_VOQ8                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56983     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_VOQ8_SHIFT                         16
56984     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ8                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
56985     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ8_SHIFT               17
56986 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ8                                                            0xd808c4UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 8 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
56987 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ8                                                       0xd808c8UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 8. Reset upon init.  Chips: BB_A0 BB_B0 K2
56988 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ8                                                       0xd808ccUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 8. Reset upon init.  Chips: BB_A0 BB_B0 K2
56989 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9                                                               0xd808e0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 9.  Chips: BB_A0 BB_B0 K2
56990 #define PBF_REG_YCMD_QS_THRSH_VOQ9                                                                   0xd808e4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 9 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
56991 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ9                                                    0xd808e8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 9  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
56992 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ9                                                            0xd808ecUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 9 from YSTORM.  Chips: BB_A0 BB_B0 K2
56993 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ9                                                                 0xd808f0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 9.  Chips: BB_A0 BB_B0 K2
56994 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ9                                                         0xd808f4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 9. Reset upon init.  Chips: BB_A0 BB_B0 K2
56995 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ9                                                               0xd808f8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 9.  Chips: BB_A0 BB_B0 K2
56996 #define PBF_REG_BTB_GUARANTEED_VOQ9                                                                  0xd808fcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 9  Chips: BB_A0 BB_B0 K2
56997 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9                                                           0xd80900UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
56998     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_MAX_SHARED_ALLOC_VOQ9                             (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 9
56999     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_MAX_SHARED_ALLOC_VOQ9_SHIFT                       0
57000     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_VOQ9                               (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57001     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_VOQ9_SHIFT                         16
57002     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ9                     (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57003     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ9_SHIFT               17
57004 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ9                                                            0xd80904UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 9 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57005 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ9                                                       0xd80908UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 9. Reset upon init.  Chips: BB_A0 BB_B0 K2
57006 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ9                                                       0xd8090cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 9. Reset upon init.  Chips: BB_A0 BB_B0 K2
57007 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10                                                              0xd80920UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 10.  Chips: BB_A0 BB_B0 K2
57008 #define PBF_REG_YCMD_QS_THRSH_VOQ10                                                                  0xd80924UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 10 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57009 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ10                                                   0xd80928UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 10  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57010 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ10                                                           0xd8092cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 10 from YSTORM.  Chips: BB_A0 BB_B0 K2
57011 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ10                                                                0xd80930UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 10.  Chips: BB_A0 BB_B0 K2
57012 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ10                                                        0xd80934UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 10. Reset upon init.  Chips: BB_A0 BB_B0 K2
57013 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ10                                                              0xd80938UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 10.  Chips: BB_A0 BB_B0 K2
57014 #define PBF_REG_BTB_GUARANTEED_VOQ10                                                                 0xd8093cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 10  Chips: BB_A0 BB_B0 K2
57015 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10                                                          0xd80940UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57016     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_MAX_SHARED_ALLOC_VOQ10                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 10
57017     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_MAX_SHARED_ALLOC_VOQ10_SHIFT                     0
57018     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_VOQ10                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57019     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_VOQ10_SHIFT                       16
57020     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ10                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57021     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ10_SHIFT             17
57022 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ10                                                           0xd80944UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 10 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57023 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ10                                                      0xd80948UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 10. Reset upon init.  Chips: BB_A0 BB_B0 K2
57024 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ10                                                      0xd8094cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 10. Reset upon init.  Chips: BB_A0 BB_B0 K2
57025 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11                                                              0xd80960UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 11.  Chips: BB_A0 BB_B0 K2
57026 #define PBF_REG_YCMD_QS_THRSH_VOQ11                                                                  0xd80964UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 11 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57027 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ11                                                   0xd80968UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 11  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57028 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ11                                                           0xd8096cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 11 from YSTORM.  Chips: BB_A0 BB_B0 K2
57029 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ11                                                                0xd80970UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 11.  Chips: BB_A0 BB_B0 K2
57030 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ11                                                        0xd80974UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 11. Reset upon init.  Chips: BB_A0 BB_B0 K2
57031 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ11                                                              0xd80978UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 11.  Chips: BB_A0 BB_B0 K2
57032 #define PBF_REG_BTB_GUARANTEED_VOQ11                                                                 0xd8097cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 11  Chips: BB_A0 BB_B0 K2
57033 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11                                                          0xd80980UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57034     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_MAX_SHARED_ALLOC_VOQ11                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 11
57035     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_MAX_SHARED_ALLOC_VOQ11_SHIFT                     0
57036     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_VOQ11                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57037     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_VOQ11_SHIFT                       16
57038     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ11                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57039     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ11_SHIFT             17
57040 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ11                                                           0xd80984UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 11 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57041 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ11                                                      0xd80988UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 11. Reset upon init.  Chips: BB_A0 BB_B0 K2
57042 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ11                                                      0xd8098cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 11. Reset upon init.  Chips: BB_A0 BB_B0 K2
57043 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12                                                              0xd809a0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 12.  Chips: BB_A0 BB_B0 K2
57044 #define PBF_REG_YCMD_QS_THRSH_VOQ12                                                                  0xd809a4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 12 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57045 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ12                                                   0xd809a8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 12  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57046 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ12                                                           0xd809acUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 12 from YSTORM.  Chips: BB_A0 BB_B0 K2
57047 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ12                                                                0xd809b0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 12.  Chips: BB_A0 BB_B0 K2
57048 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ12                                                        0xd809b4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 12. Reset upon init.  Chips: BB_A0 BB_B0 K2
57049 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ12                                                              0xd809b8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 12.  Chips: BB_A0 BB_B0 K2
57050 #define PBF_REG_BTB_GUARANTEED_VOQ12                                                                 0xd809bcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 12  Chips: BB_A0 BB_B0 K2
57051 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12                                                          0xd809c0UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57052     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_MAX_SHARED_ALLOC_VOQ12                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 12
57053     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_MAX_SHARED_ALLOC_VOQ12_SHIFT                     0
57054     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_VOQ12                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57055     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_VOQ12_SHIFT                       16
57056     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ12                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57057     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ12_SHIFT             17
57058 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ12                                                           0xd809c4UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 12 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57059 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ12                                                      0xd809c8UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 12. Reset upon init.  Chips: BB_A0 BB_B0 K2
57060 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ12                                                      0xd809ccUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 12. Reset upon init.  Chips: BB_A0 BB_B0 K2
57061 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13                                                              0xd809e0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 13.  Chips: BB_A0 BB_B0 K2
57062 #define PBF_REG_YCMD_QS_THRSH_VOQ13                                                                  0xd809e4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 13 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57063 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ13                                                   0xd809e8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 13  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57064 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ13                                                           0xd809ecUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 13 from YSTORM.  Chips: BB_A0 BB_B0 K2
57065 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ13                                                                0xd809f0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 13.  Chips: BB_A0 BB_B0 K2
57066 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ13                                                        0xd809f4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 13. Reset upon init.  Chips: BB_A0 BB_B0 K2
57067 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ13                                                              0xd809f8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 13.  Chips: BB_A0 BB_B0 K2
57068 #define PBF_REG_BTB_GUARANTEED_VOQ13                                                                 0xd809fcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 13  Chips: BB_A0 BB_B0 K2
57069 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13                                                          0xd80a00UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57070     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_MAX_SHARED_ALLOC_VOQ13                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 13
57071     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_MAX_SHARED_ALLOC_VOQ13_SHIFT                     0
57072     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_VOQ13                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57073     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_VOQ13_SHIFT                       16
57074     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ13                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57075     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ13_SHIFT             17
57076 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ13                                                           0xd80a04UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 13 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57077 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ13                                                      0xd80a08UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 13. Reset upon init.  Chips: BB_A0 BB_B0 K2
57078 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ13                                                      0xd80a0cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 13. Reset upon init.  Chips: BB_A0 BB_B0 K2
57079 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14                                                              0xd80a20UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 14.  Chips: BB_A0 BB_B0 K2
57080 #define PBF_REG_YCMD_QS_THRSH_VOQ14                                                                  0xd80a24UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 14 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57081 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ14                                                   0xd80a28UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 14  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57082 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ14                                                           0xd80a2cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 14 from YSTORM.  Chips: BB_A0 BB_B0 K2
57083 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ14                                                                0xd80a30UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 14.  Chips: BB_A0 BB_B0 K2
57084 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ14                                                        0xd80a34UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 14. Reset upon init.  Chips: BB_A0 BB_B0 K2
57085 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ14                                                              0xd80a38UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 14.  Chips: BB_A0 BB_B0 K2
57086 #define PBF_REG_BTB_GUARANTEED_VOQ14                                                                 0xd80a3cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 14  Chips: BB_A0 BB_B0 K2
57087 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14                                                          0xd80a40UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57088     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_MAX_SHARED_ALLOC_VOQ14                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 14
57089     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_MAX_SHARED_ALLOC_VOQ14_SHIFT                     0
57090     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_VOQ14                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57091     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_VOQ14_SHIFT                       16
57092     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ14                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57093     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ14_SHIFT             17
57094 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ14                                                           0xd80a44UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 14 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57095 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ14                                                      0xd80a48UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 14. Reset upon init.  Chips: BB_A0 BB_B0 K2
57096 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ14                                                      0xd80a4cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 14. Reset upon init.  Chips: BB_A0 BB_B0 K2
57097 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15                                                              0xd80a60UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 15.  Chips: BB_A0 BB_B0 K2
57098 #define PBF_REG_YCMD_QS_THRSH_VOQ15                                                                  0xd80a64UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 15 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57099 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ15                                                   0xd80a68UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 15  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57100 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ15                                                           0xd80a6cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 15 from YSTORM.  Chips: BB_A0 BB_B0 K2
57101 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ15                                                                0xd80a70UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 15.  Chips: BB_A0 BB_B0 K2
57102 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ15                                                        0xd80a74UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 15. Reset upon init.  Chips: BB_A0 BB_B0 K2
57103 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ15                                                              0xd80a78UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 15.  Chips: BB_A0 BB_B0 K2
57104 #define PBF_REG_BTB_GUARANTEED_VOQ15                                                                 0xd80a7cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 15  Chips: BB_A0 BB_B0 K2
57105 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15                                                          0xd80a80UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57106     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_MAX_SHARED_ALLOC_VOQ15                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 15
57107     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_MAX_SHARED_ALLOC_VOQ15_SHIFT                     0
57108     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_VOQ15                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57109     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_VOQ15_SHIFT                       16
57110     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ15                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57111     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ15_SHIFT             17
57112 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ15                                                           0xd80a84UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 15 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57113 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ15                                                      0xd80a88UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 15. Reset upon init.  Chips: BB_A0 BB_B0 K2
57114 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ15                                                      0xd80a8cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 15. Reset upon init.  Chips: BB_A0 BB_B0 K2
57115 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16                                                              0xd80aa0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 16.  Chips: BB_A0 BB_B0 K2
57116 #define PBF_REG_YCMD_QS_THRSH_VOQ16                                                                  0xd80aa4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 16 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57117 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ16                                                   0xd80aa8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 16  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57118 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ16                                                           0xd80aacUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 16 from YSTORM.  Chips: BB_A0 BB_B0 K2
57119 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ16                                                                0xd80ab0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 16.  Chips: BB_A0 BB_B0 K2
57120 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ16                                                        0xd80ab4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 16. Reset upon init.  Chips: BB_A0 BB_B0 K2
57121 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ16                                                              0xd80ab8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 16.  Chips: BB_A0 BB_B0 K2
57122 #define PBF_REG_BTB_GUARANTEED_VOQ16                                                                 0xd80abcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 16  Chips: BB_A0 BB_B0 K2
57123 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16                                                          0xd80ac0UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57124     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_MAX_SHARED_ALLOC_VOQ16                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 16
57125     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_MAX_SHARED_ALLOC_VOQ16_SHIFT                     0
57126     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_VOQ16                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57127     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_VOQ16_SHIFT                       16
57128     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ16                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57129     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ16_SHIFT             17
57130 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ16                                                           0xd80ac4UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 16 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57131 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ16                                                      0xd80ac8UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 16. Reset upon init.  Chips: BB_A0 BB_B0 K2
57132 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ16                                                      0xd80accUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 16. Reset upon init.  Chips: BB_A0 BB_B0 K2
57133 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17                                                              0xd80ae0UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 17.  Chips: BB_A0 BB_B0 K2
57134 #define PBF_REG_YCMD_QS_THRSH_VOQ17                                                                  0xd80ae4UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 17 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57135 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ17                                                   0xd80ae8UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 17  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57136 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ17                                                           0xd80aecUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 17 from YSTORM.  Chips: BB_A0 BB_B0 K2
57137 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ17                                                                0xd80af0UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 17.  Chips: BB_A0 BB_B0 K2
57138 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ17                                                        0xd80af4UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 17. Reset upon init.  Chips: BB_A0 BB_B0 K2
57139 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ17                                                              0xd80af8UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 17.  Chips: BB_A0 BB_B0 K2
57140 #define PBF_REG_BTB_GUARANTEED_VOQ17                                                                 0xd80afcUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 17  Chips: BB_A0 BB_B0 K2
57141 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17                                                          0xd80b00UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57142     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_MAX_SHARED_ALLOC_VOQ17                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 17
57143     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_MAX_SHARED_ALLOC_VOQ17_SHIFT                     0
57144     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_VOQ17                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57145     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_VOQ17_SHIFT                       16
57146     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ17                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57147     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ17_SHIFT             17
57148 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ17                                                           0xd80b04UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 17 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57149 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ17                                                      0xd80b08UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 17. Reset upon init.  Chips: BB_A0 BB_B0 K2
57150 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ17                                                      0xd80b0cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 17. Reset upon init.  Chips: BB_A0 BB_B0 K2
57151 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18                                                              0xd80b20UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 18.  Chips: BB_A0 BB_B0 K2
57152 #define PBF_REG_YCMD_QS_THRSH_VOQ18                                                                  0xd80b24UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 18 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57153 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ18                                                   0xd80b28UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 18  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57154 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ18                                                           0xd80b2cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 18 from YSTORM.  Chips: BB_A0 BB_B0 K2
57155 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ18                                                                0xd80b30UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 18.  Chips: BB_A0 BB_B0 K2
57156 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ18                                                        0xd80b34UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 18. Reset upon init.  Chips: BB_A0 BB_B0 K2
57157 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ18                                                              0xd80b38UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 18.  Chips: BB_A0 BB_B0 K2
57158 #define PBF_REG_BTB_GUARANTEED_VOQ18                                                                 0xd80b3cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 18  Chips: BB_A0 BB_B0 K2
57159 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18                                                          0xd80b40UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57160     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_MAX_SHARED_ALLOC_VOQ18                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 18
57161     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_MAX_SHARED_ALLOC_VOQ18_SHIFT                     0
57162     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_VOQ18                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57163     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_VOQ18_SHIFT                       16
57164     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ18                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57165     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ18_SHIFT             17
57166 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ18                                                           0xd80b44UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 18 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57167 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ18                                                      0xd80b48UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 18. Reset upon init.  Chips: BB_A0 BB_B0 K2
57168 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ18                                                      0xd80b4cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 18. Reset upon init.  Chips: BB_A0 BB_B0 K2
57169 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19                                                              0xd80b60UL //Access:RW   DataWidth:0xc   Number of 32 byte lines in the YSTORM command Q reserved for VOQ 19.  Chips: BB_A0 BB_B0 K2
57170 #define PBF_REG_YCMD_QS_THRSH_VOQ19                                                                  0xd80b64UL //Access:RW   DataWidth:0x5   Almost full threshold for VOQ 19 in the YSTORM command Q in 32 byte lines.  Chips: BB_A0 BB_B0 K2
57171 #define PBF_REG_YCMD_QS_DISABLE_NEW_CMD_PROC_VOQ19                                                   0xd80b68UL //Access:RW   DataWidth:0x1   Disable processing further Y commands from VOQ 19  (after ending the current command in process).  Chips: BB_A0 BB_B0 K2
57172 #define PBF_REG_YCMD_QS_CMDS_RCVD_ON_VOQ19                                                           0xd80b6cUL //Access:RC   DataWidth:0x20  Number of commands received on VOQ 19 from YSTORM.  Chips: BB_A0 BB_B0 K2
57173 #define PBF_REG_YCMD_QS_CMD_CNT_VOQ19                                                                0xd80b70UL //Access:R    DataWidth:0xa   Number of commands in the Y command queue of VOQ 19.  Chips: BB_A0 BB_B0 K2
57174 #define PBF_REG_YCMD_QS_LINES_FREED_CNT_VOQ19                                                        0xd80b74UL //Access:R    DataWidth:0x20  Cyclic counter for number of 16 byte lines freed from the Y command queue of VOQ 19. Reset upon init.  Chips: BB_A0 BB_B0 K2
57175 #define PBF_REG_YCMD_QS_OCCUPANCY_VOQ19                                                              0xd80b78UL //Access:R    DataWidth:0xd   Number of 16 bytes lines occupied in the Y command queue of VOQ 19.  Chips: BB_A0 BB_B0 K2
57176 #define PBF_REG_BTB_GUARANTEED_VOQ19                                                                 0xd80b7cUL //Access:RW   DataWidth:0xb   The number of BTB 256 byte blocks guaranteed for VOQ 19  Chips: BB_A0 BB_B0 K2
57177 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19                                                          0xd80b80UL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57178     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_MAX_SHARED_ALLOC_VOQ19                           (0x7ff<<0) // The maximum number of BTB 256 byte blocks that a TC can allocate in the shared area for VOQ 19
57179     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_MAX_SHARED_ALLOC_VOQ19_SHIFT                     0
57180     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_VOQ19                             (0x1<<16) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57181     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_VOQ19_SHIFT                       16
57182     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ19                   (0x1<<17) // if set, enables using the shared area for a TC when the guaranteed space is exhausted, regardless of the packet size.
57183     #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_BTB_CAN_USE_SHARED_FOR_JUMBO_VOQ19_SHIFT             17
57184 #define PBF_REG_BTB_ALLOCATED_BLOCKS_VOQ19                                                           0xd80b84UL //Access:R    DataWidth:0xc   Number of blocks allocated in the BTB for VOQ 19 in both guaranteed and shared areas.  Chips: BB_A0 BB_B0 K2
57185 #define PBF_REG_NUM_BLOCKS_ALLOCATED_PROD_VOQ19                                                      0xd80b88UL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks allocated (producer) for VOQ 19. Reset upon init.  Chips: BB_A0 BB_B0 K2
57186 #define PBF_REG_NUM_BLOCKS_ALLOCATED_CONS_VOQ19                                                      0xd80b8cUL //Access:R    DataWidth:0x20  Cyclic counter for number of blocks released (consumer) for VOQ 19. Reset upon init.  Chips: BB_A0 BB_B0 K2
57187 #define PBF_REG_ECO_RESERVED                                                                         0xd80ea0UL //Access:RW   DataWidth:0x20  reserved for ECOs  Chips: BB_A0 BB_B0 K2
57188 #define PBF_PB1_REG_INT_STS                                                                          0xda0040UL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57189     #define PBF_PB1_REG_INT_STS_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
57190     #define PBF_PB1_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                  0
57191     #define PBF_PB1_REG_INT_STS_EOP_ERROR                                                            (0x1<<1) // EOP check error.
57192     #define PBF_PB1_REG_INT_STS_EOP_ERROR_SHIFT                                                      1
57193     #define PBF_PB1_REG_INT_STS_IFIFO_ERROR                                                          (0x1<<2) // Instruction FIFO error.
57194     #define PBF_PB1_REG_INT_STS_IFIFO_ERROR_SHIFT                                                    2
57195     #define PBF_PB1_REG_INT_STS_PFIFO_ERROR                                                          (0x1<<3) // Parameter FIFO error.
57196     #define PBF_PB1_REG_INT_STS_PFIFO_ERROR_SHIFT                                                    3
57197     #define PBF_PB1_REG_INT_STS_DB_BUF_ERROR                                                         (0x1<<4) // DB FIFO error.
57198     #define PBF_PB1_REG_INT_STS_DB_BUF_ERROR_SHIFT                                                   4
57199     #define PBF_PB1_REG_INT_STS_TH_EXEC_ERROR                                                        (0x1<<5) //
57200     #define PBF_PB1_REG_INT_STS_TH_EXEC_ERROR_SHIFT                                                  5
57201     #define PBF_PB1_REG_INT_STS_TQ_ERROR_WR                                                          (0x1<<6) // TQ write overflow.
57202     #define PBF_PB1_REG_INT_STS_TQ_ERROR_WR_SHIFT                                                    6
57203     #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_TH                                                       (0x1<<7) // TQ read underflow by task handler.
57204     #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT                                                 7
57205     #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_IH                                                       (0x1<<8) // TQ read underflow by instruction handler.
57206     #define PBF_PB1_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT                                                 8
57207 #define PBF_PB1_REG_INT_MASK                                                                         0xda0044UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57208     #define PBF_PB1_REG_INT_MASK_ADDRESS_ERROR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
57209     #define PBF_PB1_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                 0
57210     #define PBF_PB1_REG_INT_MASK_EOP_ERROR                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
57211     #define PBF_PB1_REG_INT_MASK_EOP_ERROR_SHIFT                                                     1
57212     #define PBF_PB1_REG_INT_MASK_IFIFO_ERROR                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
57213     #define PBF_PB1_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                   2
57214     #define PBF_PB1_REG_INT_MASK_PFIFO_ERROR                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
57215     #define PBF_PB1_REG_INT_MASK_PFIFO_ERROR_SHIFT                                                   3
57216     #define PBF_PB1_REG_INT_MASK_DB_BUF_ERROR                                                        (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
57217     #define PBF_PB1_REG_INT_MASK_DB_BUF_ERROR_SHIFT                                                  4
57218     #define PBF_PB1_REG_INT_MASK_TH_EXEC_ERROR                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
57219     #define PBF_PB1_REG_INT_MASK_TH_EXEC_ERROR_SHIFT                                                 5
57220     #define PBF_PB1_REG_INT_MASK_TQ_ERROR_WR                                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
57221     #define PBF_PB1_REG_INT_MASK_TQ_ERROR_WR_SHIFT                                                   6
57222     #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_TH                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
57223     #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT                                                7
57224     #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_IH                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
57225     #define PBF_PB1_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT                                                8
57226 #define PBF_PB1_REG_INT_STS_WR                                                                       0xda0048UL //Access:WR   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57227     #define PBF_PB1_REG_INT_STS_WR_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
57228     #define PBF_PB1_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                               0
57229     #define PBF_PB1_REG_INT_STS_WR_EOP_ERROR                                                         (0x1<<1) // EOP check error.
57230     #define PBF_PB1_REG_INT_STS_WR_EOP_ERROR_SHIFT                                                   1
57231     #define PBF_PB1_REG_INT_STS_WR_IFIFO_ERROR                                                       (0x1<<2) // Instruction FIFO error.
57232     #define PBF_PB1_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                 2
57233     #define PBF_PB1_REG_INT_STS_WR_PFIFO_ERROR                                                       (0x1<<3) // Parameter FIFO error.
57234     #define PBF_PB1_REG_INT_STS_WR_PFIFO_ERROR_SHIFT                                                 3
57235     #define PBF_PB1_REG_INT_STS_WR_DB_BUF_ERROR                                                      (0x1<<4) // DB FIFO error.
57236     #define PBF_PB1_REG_INT_STS_WR_DB_BUF_ERROR_SHIFT                                                4
57237     #define PBF_PB1_REG_INT_STS_WR_TH_EXEC_ERROR                                                     (0x1<<5) //
57238     #define PBF_PB1_REG_INT_STS_WR_TH_EXEC_ERROR_SHIFT                                               5
57239     #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_WR                                                       (0x1<<6) // TQ write overflow.
57240     #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_WR_SHIFT                                                 6
57241     #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_TH                                                    (0x1<<7) // TQ read underflow by task handler.
57242     #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT                                              7
57243     #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_IH                                                    (0x1<<8) // TQ read underflow by instruction handler.
57244     #define PBF_PB1_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT                                              8
57245 #define PBF_PB1_REG_INT_STS_CLR                                                                      0xda004cUL //Access:RC   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57246     #define PBF_PB1_REG_INT_STS_CLR_ADDRESS_ERROR                                                    (0x1<<0) // Signals an unknown address to the rf module.
57247     #define PBF_PB1_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                              0
57248     #define PBF_PB1_REG_INT_STS_CLR_EOP_ERROR                                                        (0x1<<1) // EOP check error.
57249     #define PBF_PB1_REG_INT_STS_CLR_EOP_ERROR_SHIFT                                                  1
57250     #define PBF_PB1_REG_INT_STS_CLR_IFIFO_ERROR                                                      (0x1<<2) // Instruction FIFO error.
57251     #define PBF_PB1_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                2
57252     #define PBF_PB1_REG_INT_STS_CLR_PFIFO_ERROR                                                      (0x1<<3) // Parameter FIFO error.
57253     #define PBF_PB1_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT                                                3
57254     #define PBF_PB1_REG_INT_STS_CLR_DB_BUF_ERROR                                                     (0x1<<4) // DB FIFO error.
57255     #define PBF_PB1_REG_INT_STS_CLR_DB_BUF_ERROR_SHIFT                                               4
57256     #define PBF_PB1_REG_INT_STS_CLR_TH_EXEC_ERROR                                                    (0x1<<5) //
57257     #define PBF_PB1_REG_INT_STS_CLR_TH_EXEC_ERROR_SHIFT                                              5
57258     #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_WR                                                      (0x1<<6) // TQ write overflow.
57259     #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_WR_SHIFT                                                6
57260     #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_TH                                                   (0x1<<7) // TQ read underflow by task handler.
57261     #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT                                             7
57262     #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_IH                                                   (0x1<<8) // TQ read underflow by instruction handler.
57263     #define PBF_PB1_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT                                             8
57264 #define PBF_PB1_REG_PRTY_MASK                                                                        0xda0054UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
57265     #define PBF_PB1_REG_PRTY_MASK_DATAPATH_REGISTERS                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
57266     #define PBF_PB1_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                           0
57267 #define PBF_PB1_REG_CONTROL                                                                          0xda0400UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57268     #define PBF_PB1_REG_CONTROL_BYTE_ORDER_SWITCH                                                    (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
57269     #define PBF_PB1_REG_CONTROL_BYTE_ORDER_SWITCH_SHIFT                                              0
57270     #define PBF_PB1_REG_CONTROL_DB_IGNORE_ERROR                                                      (0x1<<1) // Indicates if to ignore the input error indication.
57271     #define PBF_PB1_REG_CONTROL_DB_IGNORE_ERROR_SHIFT                                                1
57272     #define PBF_PB1_REG_CONTROL_DONT_PASS_ERROR                                                      (0x1<<2) // Masks error on output of pb.
57273     #define PBF_PB1_REG_CONTROL_DONT_PASS_ERROR_SHIFT                                                2
57274     #define PBF_PB1_REG_CONTROL_EOP_CHECK_DISABLE                                                    (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
57275     #define PBF_PB1_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT                                              3
57276     #define PBF_PB1_REG_CONTROL_CRC_COMPARE_DISABLE                                                  (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
57277     #define PBF_PB1_REG_CONTROL_CRC_COMPARE_DISABLE_SHIFT                                            4
57278     #define PBF_PB1_REG_CONTROL_EN_INPUTS                                                            (0x1<<5) // Enable inputs.
57279     #define PBF_PB1_REG_CONTROL_EN_INPUTS_SHIFT                                                      5
57280     #define PBF_PB1_REG_CONTROL_DISABLE_PB                                                           (0x1<<6) // Debug only: Disable PB.
57281     #define PBF_PB1_REG_CONTROL_DISABLE_PB_SHIFT                                                     6
57282     #define PBF_PB1_REG_CONTROL_DEBUG_SELECT                                                         (0xf<<7) // Obsolete.
57283     #define PBF_PB1_REG_CONTROL_DEBUG_SELECT_SHIFT                                                   7
57284     #define PBF_PB1_REG_CONTROL_RELAX_TH                                                             (0x1<<11) // Dbug only.
57285     #define PBF_PB1_REG_CONTROL_RELAX_TH_SHIFT                                                       11
57286     #define PBF_PB1_REG_CONTROL_DUMMY_ERR_ALLOW                                                      (0x1<<12) // Dummy ingress error allow.  When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
57287     #define PBF_PB1_REG_CONTROL_DUMMY_ERR_ALLOW_SHIFT                                                12
57288 #define PBF_PB1_REG_CRC_MASK_1_0                                                                     0xda0404UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57289 #define PBF_PB1_REG_CRC_MASK_1_1                                                                     0xda0408UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57290 #define PBF_PB1_REG_CRC_MASK_1_2                                                                     0xda040cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57291 #define PBF_PB1_REG_CRC_MASK_1_3                                                                     0xda0410UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57292 #define PBF_PB1_REG_CRC_MASK_2_0                                                                     0xda0414UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57293 #define PBF_PB1_REG_CRC_MASK_2_1                                                                     0xda0418UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57294 #define PBF_PB1_REG_CRC_MASK_2_2                                                                     0xda041cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57295 #define PBF_PB1_REG_CRC_MASK_2_3                                                                     0xda0420UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57296 #define PBF_PB1_REG_CRC_MASK_3_0                                                                     0xda0424UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57297 #define PBF_PB1_REG_CRC_MASK_3_1                                                                     0xda0428UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57298 #define PBF_PB1_REG_CRC_MASK_3_2                                                                     0xda042cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57299 #define PBF_PB1_REG_CRC_MASK_3_3                                                                     0xda0430UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57300 #define PBF_PB1_REG_DB_EMPTY                                                                         0xda0500UL //Access:R    DataWidth:0x1   Data Buffer empty status.  Chips: BB_A0 BB_B0 K2
57301 #define PBF_PB1_REG_DB_FULL                                                                          0xda0504UL //Access:R    DataWidth:0x1   Data Buffer full status.  Chips: BB_A0 BB_B0 K2
57302 #define PBF_PB1_REG_TQ_EMPTY                                                                         0xda0508UL //Access:R    DataWidth:0x1   Task Queue empty status.  Chips: BB_A0 BB_B0 K2
57303 #define PBF_PB1_REG_TQ_FULL                                                                          0xda050cUL //Access:R    DataWidth:0x1   Task Queue full status.  Chips: BB_A0 BB_B0 K2
57304 #define PBF_PB1_REG_IFIFO_EMPTY                                                                      0xda0510UL //Access:R    DataWidth:0x1   Instruction FIFO empty status.  Chips: BB_A0 BB_B0 K2
57305 #define PBF_PB1_REG_IFIFO_FULL                                                                       0xda0514UL //Access:R    DataWidth:0x1   Instruction FIFO full status.  Chips: BB_A0 BB_B0 K2
57306 #define PBF_PB1_REG_PFIFO_EMPTY                                                                      0xda0518UL //Access:R    DataWidth:0x1   Parameter FIFO empty status.  Chips: BB_A0 BB_B0 K2
57307 #define PBF_PB1_REG_PFIFO_FULL                                                                       0xda051cUL //Access:R    DataWidth:0x1   Parameter FIFO full status.  Chips: BB_A0 BB_B0 K2
57308 #define PBF_PB1_REG_TQ_TH_EMPTY                                                                      0xda0520UL //Access:R    DataWidth:0x1   Task Queue empty status for task handler.  Chips: BB_A0 BB_B0 K2
57309 #define PBF_PB1_REG_ERRORED_CRC                                                                      0xda0600UL //Access:R    DataWidth:0x20  CRC mismatch debug register.  This register stores the calculated CRC value that resulted in the most recent CRC error event.  Chips: BB_A0 BB_B0 K2
57310 #define PBF_PB1_REG_ERRORED_INSTR                                                                    0xda0604UL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the instruction being executed at the time EOP error is detected. The instruction is aligned with the least significant bit of this register.  Bits 31:29 provide additional information about the instruction.  Bit 31 indicates whether the instruction is valid.  Bit 30 indicates if the instruction is the first instruction in the task.  Bit 29 indicates whether the instruction is the last instruction in the task.  Chips: BB_A0 BB_B0 K2
57311 #define PBF_PB1_REG_ERRORED_HDR_LOW                                                                  0xda0608UL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the lower 32 bits of the task header being executed at the time EOP error is detected.  The instruction length is not kept and is read as 0.  Chips: BB_A0 BB_B0 K2
57312 #define PBF_PB1_REG_ERRORED_HDR_HIGH                                                                 0xda060cUL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the upper 32 bits of the task header being executed at the time EOP error is detected.  The task passthrough bit is not kept and is read as 0.  Chips: BB_A0 BB_B0 K2
57313 #define PBF_PB1_REG_ERRORED_LENGTH                                                                   0xda0610UL //Access:R    DataWidth:0x10  EOP mismatch debug register.  This register provides the number of data bytes remaining to be read from DB at the time of EOP error detection.  Chips: BB_A0 BB_B0 K2
57314 #define PBF_PB1_REG_ECO_RESERVED                                                                     0xda0614UL //Access:RW   DataWidth:0x8   For future eco.  Chips: BB_A0 BB_B0 K2
57315 #define PBF_PB1_REG_DBG_OUT_DATA                                                                     0xda0700UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
57316 #define PBF_PB1_REG_DBG_OUT_DATA_SIZE                                                                8
57317 #define PBF_PB1_REG_DBG_OUT_VALID                                                                    0xda0720UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
57318 #define PBF_PB1_REG_DBG_OUT_FRAME                                                                    0xda0724UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
57319 #define PBF_PB1_REG_DBG_SELECT                                                                       0xda0728UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
57320 #define PBF_PB1_REG_DBG_DWORD_ENABLE                                                                 0xda072cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
57321 #define PBF_PB1_REG_DBG_SHIFT                                                                        0xda0730UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
57322 #define PBF_PB1_REG_DBG_FORCE_VALID                                                                  0xda0734UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
57323 #define PBF_PB1_REG_DBG_FORCE_FRAME                                                                  0xda0738UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
57324 #define PBF_PB1_REG_DB_FIFO                                                                          0xda2000UL //Access:WB_R DataWidth:0x108 Provides read-only access of the data buffer FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
57325 #define PBF_PB1_REG_DB_FIFO_SIZE                                                                     512
57326 #define PBF_PB1_REG_L1                                                                               0xda3000UL //Access:WB   DataWidth:0x40  L1 CRC memory access.  Chips: BB_A0 BB_B0 K2
57327 #define PBF_PB1_REG_L1_SIZE                                                                          640
57328 #define PBF_PB2_REG_INT_STS                                                                          0xda4040UL //Access:R    DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57329     #define PBF_PB2_REG_INT_STS_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
57330     #define PBF_PB2_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                  0
57331     #define PBF_PB2_REG_INT_STS_EOP_ERROR                                                            (0x1<<1) // EOP check error.
57332     #define PBF_PB2_REG_INT_STS_EOP_ERROR_SHIFT                                                      1
57333     #define PBF_PB2_REG_INT_STS_IFIFO_ERROR                                                          (0x1<<2) // Instruction FIFO error.
57334     #define PBF_PB2_REG_INT_STS_IFIFO_ERROR_SHIFT                                                    2
57335     #define PBF_PB2_REG_INT_STS_PFIFO_ERROR                                                          (0x1<<3) // Parameter FIFO error.
57336     #define PBF_PB2_REG_INT_STS_PFIFO_ERROR_SHIFT                                                    3
57337     #define PBF_PB2_REG_INT_STS_DB_BUF_ERROR                                                         (0x1<<4) // DB FIFO error.
57338     #define PBF_PB2_REG_INT_STS_DB_BUF_ERROR_SHIFT                                                   4
57339     #define PBF_PB2_REG_INT_STS_TH_EXEC_ERROR                                                        (0x1<<5) //
57340     #define PBF_PB2_REG_INT_STS_TH_EXEC_ERROR_SHIFT                                                  5
57341     #define PBF_PB2_REG_INT_STS_TQ_ERROR_WR                                                          (0x1<<6) // TQ write overflow.
57342     #define PBF_PB2_REG_INT_STS_TQ_ERROR_WR_SHIFT                                                    6
57343     #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_TH                                                       (0x1<<7) // TQ read underflow by task handler.
57344     #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_TH_SHIFT                                                 7
57345     #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_IH                                                       (0x1<<8) // TQ read underflow by instruction handler.
57346     #define PBF_PB2_REG_INT_STS_TQ_ERROR_RD_IH_SHIFT                                                 8
57347 #define PBF_PB2_REG_INT_MASK                                                                         0xda4044UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57348     #define PBF_PB2_REG_INT_MASK_ADDRESS_ERROR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.ADDRESS_ERROR .
57349     #define PBF_PB2_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                 0
57350     #define PBF_PB2_REG_INT_MASK_EOP_ERROR                                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.EOP_ERROR .
57351     #define PBF_PB2_REG_INT_MASK_EOP_ERROR_SHIFT                                                     1
57352     #define PBF_PB2_REG_INT_MASK_IFIFO_ERROR                                                         (0x1<<2) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.IFIFO_ERROR .
57353     #define PBF_PB2_REG_INT_MASK_IFIFO_ERROR_SHIFT                                                   2
57354     #define PBF_PB2_REG_INT_MASK_PFIFO_ERROR                                                         (0x1<<3) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.PFIFO_ERROR .
57355     #define PBF_PB2_REG_INT_MASK_PFIFO_ERROR_SHIFT                                                   3
57356     #define PBF_PB2_REG_INT_MASK_DB_BUF_ERROR                                                        (0x1<<4) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.DB_BUF_ERROR .
57357     #define PBF_PB2_REG_INT_MASK_DB_BUF_ERROR_SHIFT                                                  4
57358     #define PBF_PB2_REG_INT_MASK_TH_EXEC_ERROR                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TH_EXEC_ERROR .
57359     #define PBF_PB2_REG_INT_MASK_TH_EXEC_ERROR_SHIFT                                                 5
57360     #define PBF_PB2_REG_INT_MASK_TQ_ERROR_WR                                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_WR .
57361     #define PBF_PB2_REG_INT_MASK_TQ_ERROR_WR_SHIFT                                                   6
57362     #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_TH                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_TH .
57363     #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_TH_SHIFT                                                7
57364     #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_IH                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: PB_REG_INT_STS.TQ_ERROR_RD_IH .
57365     #define PBF_PB2_REG_INT_MASK_TQ_ERROR_RD_IH_SHIFT                                                8
57366 #define PBF_PB2_REG_INT_STS_WR                                                                       0xda4048UL //Access:WR   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57367     #define PBF_PB2_REG_INT_STS_WR_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
57368     #define PBF_PB2_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                               0
57369     #define PBF_PB2_REG_INT_STS_WR_EOP_ERROR                                                         (0x1<<1) // EOP check error.
57370     #define PBF_PB2_REG_INT_STS_WR_EOP_ERROR_SHIFT                                                   1
57371     #define PBF_PB2_REG_INT_STS_WR_IFIFO_ERROR                                                       (0x1<<2) // Instruction FIFO error.
57372     #define PBF_PB2_REG_INT_STS_WR_IFIFO_ERROR_SHIFT                                                 2
57373     #define PBF_PB2_REG_INT_STS_WR_PFIFO_ERROR                                                       (0x1<<3) // Parameter FIFO error.
57374     #define PBF_PB2_REG_INT_STS_WR_PFIFO_ERROR_SHIFT                                                 3
57375     #define PBF_PB2_REG_INT_STS_WR_DB_BUF_ERROR                                                      (0x1<<4) // DB FIFO error.
57376     #define PBF_PB2_REG_INT_STS_WR_DB_BUF_ERROR_SHIFT                                                4
57377     #define PBF_PB2_REG_INT_STS_WR_TH_EXEC_ERROR                                                     (0x1<<5) //
57378     #define PBF_PB2_REG_INT_STS_WR_TH_EXEC_ERROR_SHIFT                                               5
57379     #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_WR                                                       (0x1<<6) // TQ write overflow.
57380     #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_WR_SHIFT                                                 6
57381     #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_TH                                                    (0x1<<7) // TQ read underflow by task handler.
57382     #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_TH_SHIFT                                              7
57383     #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_IH                                                    (0x1<<8) // TQ read underflow by instruction handler.
57384     #define PBF_PB2_REG_INT_STS_WR_TQ_ERROR_RD_IH_SHIFT                                              8
57385 #define PBF_PB2_REG_INT_STS_CLR                                                                      0xda404cUL //Access:RC   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57386     #define PBF_PB2_REG_INT_STS_CLR_ADDRESS_ERROR                                                    (0x1<<0) // Signals an unknown address to the rf module.
57387     #define PBF_PB2_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                              0
57388     #define PBF_PB2_REG_INT_STS_CLR_EOP_ERROR                                                        (0x1<<1) // EOP check error.
57389     #define PBF_PB2_REG_INT_STS_CLR_EOP_ERROR_SHIFT                                                  1
57390     #define PBF_PB2_REG_INT_STS_CLR_IFIFO_ERROR                                                      (0x1<<2) // Instruction FIFO error.
57391     #define PBF_PB2_REG_INT_STS_CLR_IFIFO_ERROR_SHIFT                                                2
57392     #define PBF_PB2_REG_INT_STS_CLR_PFIFO_ERROR                                                      (0x1<<3) // Parameter FIFO error.
57393     #define PBF_PB2_REG_INT_STS_CLR_PFIFO_ERROR_SHIFT                                                3
57394     #define PBF_PB2_REG_INT_STS_CLR_DB_BUF_ERROR                                                     (0x1<<4) // DB FIFO error.
57395     #define PBF_PB2_REG_INT_STS_CLR_DB_BUF_ERROR_SHIFT                                               4
57396     #define PBF_PB2_REG_INT_STS_CLR_TH_EXEC_ERROR                                                    (0x1<<5) //
57397     #define PBF_PB2_REG_INT_STS_CLR_TH_EXEC_ERROR_SHIFT                                              5
57398     #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_WR                                                      (0x1<<6) // TQ write overflow.
57399     #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_WR_SHIFT                                                6
57400     #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_TH                                                   (0x1<<7) // TQ read underflow by task handler.
57401     #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_TH_SHIFT                                             7
57402     #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_IH                                                   (0x1<<8) // TQ read underflow by instruction handler.
57403     #define PBF_PB2_REG_INT_STS_CLR_TQ_ERROR_RD_IH_SHIFT                                             8
57404 #define PBF_PB2_REG_PRTY_MASK                                                                        0xda4054UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_B0 K2
57405     #define PBF_PB2_REG_PRTY_MASK_DATAPATH_REGISTERS                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PB_REG_PRTY_STS.DATAPATH_REGISTERS .
57406     #define PBF_PB2_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                           0
57407 #define PBF_PB2_REG_CONTROL                                                                          0xda4400UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
57408     #define PBF_PB2_REG_CONTROL_BYTE_ORDER_SWITCH                                                    (0x1<<0) // Indicates if to switch the CRC result byte ordering. 0=don't switch;1=switch.
57409     #define PBF_PB2_REG_CONTROL_BYTE_ORDER_SWITCH_SHIFT                                              0
57410     #define PBF_PB2_REG_CONTROL_DB_IGNORE_ERROR                                                      (0x1<<1) // Indicates if to ignore the input error indication.
57411     #define PBF_PB2_REG_CONTROL_DB_IGNORE_ERROR_SHIFT                                                1
57412     #define PBF_PB2_REG_CONTROL_DONT_PASS_ERROR                                                      (0x1<<2) // Masks error on output of pb.
57413     #define PBF_PB2_REG_CONTROL_DONT_PASS_ERROR_SHIFT                                                2
57414     #define PBF_PB2_REG_CONTROL_EOP_CHECK_DISABLE                                                    (0x1<<3) // Disables EOP check (EOP check verifies that the last Task instruction is accessing a line that has EOP on it. this way one could find mismatches between expected length and actual length on some packet.
57415     #define PBF_PB2_REG_CONTROL_EOP_CHECK_DISABLE_SHIFT                                              3
57416     #define PBF_PB2_REG_CONTROL_CRC_COMPARE_DISABLE                                                  (0x1<<4) // Disables CRC2 machine (the machine that is used for comparing actual CRC with a value that is provided to the PB.
57417     #define PBF_PB2_REG_CONTROL_CRC_COMPARE_DISABLE_SHIFT                                            4
57418     #define PBF_PB2_REG_CONTROL_EN_INPUTS                                                            (0x1<<5) // Enable inputs.
57419     #define PBF_PB2_REG_CONTROL_EN_INPUTS_SHIFT                                                      5
57420     #define PBF_PB2_REG_CONTROL_DISABLE_PB                                                           (0x1<<6) // Debug only: Disable PB.
57421     #define PBF_PB2_REG_CONTROL_DISABLE_PB_SHIFT                                                     6
57422     #define PBF_PB2_REG_CONTROL_DEBUG_SELECT                                                         (0xf<<7) // Obsolete.
57423     #define PBF_PB2_REG_CONTROL_DEBUG_SELECT_SHIFT                                                   7
57424     #define PBF_PB2_REG_CONTROL_RELAX_TH                                                             (0x1<<11) // Dbug only.
57425     #define PBF_PB2_REG_CONTROL_RELAX_TH_SHIFT                                                       11
57426     #define PBF_PB2_REG_CONTROL_DUMMY_ERR_ALLOW                                                      (0x1<<12) // Dummy ingress error allow.  When cleared, an error received on the ingress interface will be masked for instructions in which the "dummy read" bit is set.
57427     #define PBF_PB2_REG_CONTROL_DUMMY_ERR_ALLOW_SHIFT                                                12
57428 #define PBF_PB2_REG_CRC_MASK_1_0                                                                     0xda4404UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57429 #define PBF_PB2_REG_CRC_MASK_1_1                                                                     0xda4408UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57430 #define PBF_PB2_REG_CRC_MASK_1_2                                                                     0xda440cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57431 #define PBF_PB2_REG_CRC_MASK_1_3                                                                     0xda4410UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57432 #define PBF_PB2_REG_CRC_MASK_2_0                                                                     0xda4414UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57433 #define PBF_PB2_REG_CRC_MASK_2_1                                                                     0xda4418UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57434 #define PBF_PB2_REG_CRC_MASK_2_2                                                                     0xda441cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57435 #define PBF_PB2_REG_CRC_MASK_2_3                                                                     0xda4420UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57436 #define PBF_PB2_REG_CRC_MASK_3_0                                                                     0xda4424UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57437 #define PBF_PB2_REG_CRC_MASK_3_1                                                                     0xda4428UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57438 #define PBF_PB2_REG_CRC_MASK_3_2                                                                     0xda442cUL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57439 #define PBF_PB2_REG_CRC_MASK_3_3                                                                     0xda4430UL //Access:RW   DataWidth:0x20  defines the crc masking of nibles, replaces the crc input with 0xf.                              bit 0 masks the first nibble of the packet(bits [255:252] of the first 256 bits)                              ,bit 1 masks the second nibble(bits [251:248])  Chips: BB_B0 K2
57440 #define PBF_PB2_REG_DB_EMPTY                                                                         0xda4500UL //Access:R    DataWidth:0x1   Data Buffer empty status.  Chips: BB_A0 BB_B0 K2
57441 #define PBF_PB2_REG_DB_FULL                                                                          0xda4504UL //Access:R    DataWidth:0x1   Data Buffer full status.  Chips: BB_A0 BB_B0 K2
57442 #define PBF_PB2_REG_TQ_EMPTY                                                                         0xda4508UL //Access:R    DataWidth:0x1   Task Queue empty status.  Chips: BB_A0 BB_B0 K2
57443 #define PBF_PB2_REG_TQ_FULL                                                                          0xda450cUL //Access:R    DataWidth:0x1   Task Queue full status.  Chips: BB_A0 BB_B0 K2
57444 #define PBF_PB2_REG_IFIFO_EMPTY                                                                      0xda4510UL //Access:R    DataWidth:0x1   Instruction FIFO empty status.  Chips: BB_A0 BB_B0 K2
57445 #define PBF_PB2_REG_IFIFO_FULL                                                                       0xda4514UL //Access:R    DataWidth:0x1   Instruction FIFO full status.  Chips: BB_A0 BB_B0 K2
57446 #define PBF_PB2_REG_PFIFO_EMPTY                                                                      0xda4518UL //Access:R    DataWidth:0x1   Parameter FIFO empty status.  Chips: BB_A0 BB_B0 K2
57447 #define PBF_PB2_REG_PFIFO_FULL                                                                       0xda451cUL //Access:R    DataWidth:0x1   Parameter FIFO full status.  Chips: BB_A0 BB_B0 K2
57448 #define PBF_PB2_REG_TQ_TH_EMPTY                                                                      0xda4520UL //Access:R    DataWidth:0x1   Task Queue empty status for task handler.  Chips: BB_A0 BB_B0 K2
57449 #define PBF_PB2_REG_ERRORED_CRC                                                                      0xda4600UL //Access:R    DataWidth:0x20  CRC mismatch debug register.  This register stores the calculated CRC value that resulted in the most recent CRC error event.  Chips: BB_A0 BB_B0 K2
57450 #define PBF_PB2_REG_ERRORED_INSTR                                                                    0xda4604UL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the instruction being executed at the time EOP error is detected. The instruction is aligned with the least significant bit of this register.  Bits 31:29 provide additional information about the instruction.  Bit 31 indicates whether the instruction is valid.  Bit 30 indicates if the instruction is the first instruction in the task.  Bit 29 indicates whether the instruction is the last instruction in the task.  Chips: BB_A0 BB_B0 K2
57451 #define PBF_PB2_REG_ERRORED_HDR_LOW                                                                  0xda4608UL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the lower 32 bits of the task header being executed at the time EOP error is detected.  The instruction length is not kept and is read as 0.  Chips: BB_A0 BB_B0 K2
57452 #define PBF_PB2_REG_ERRORED_HDR_HIGH                                                                 0xda460cUL //Access:R    DataWidth:0x20  EOP mismatch debug register.  Use this address to read the upper 32 bits of the task header being executed at the time EOP error is detected.  The task passthrough bit is not kept and is read as 0.  Chips: BB_A0 BB_B0 K2
57453 #define PBF_PB2_REG_ERRORED_LENGTH                                                                   0xda4610UL //Access:R    DataWidth:0x10  EOP mismatch debug register.  This register provides the number of data bytes remaining to be read from DB at the time of EOP error detection.  Chips: BB_A0 BB_B0 K2
57454 #define PBF_PB2_REG_ECO_RESERVED                                                                     0xda4614UL //Access:RW   DataWidth:0x8   For future eco.  Chips: BB_A0 BB_B0 K2
57455 #define PBF_PB2_REG_DBG_OUT_DATA                                                                     0xda4700UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
57456 #define PBF_PB2_REG_DBG_OUT_DATA_SIZE                                                                8
57457 #define PBF_PB2_REG_DBG_OUT_VALID                                                                    0xda4720UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
57458 #define PBF_PB2_REG_DBG_OUT_FRAME                                                                    0xda4724UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
57459 #define PBF_PB2_REG_DBG_SELECT                                                                       0xda4728UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
57460 #define PBF_PB2_REG_DBG_DWORD_ENABLE                                                                 0xda472cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
57461 #define PBF_PB2_REG_DBG_SHIFT                                                                        0xda4730UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
57462 #define PBF_PB2_REG_DBG_FORCE_VALID                                                                  0xda4734UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
57463 #define PBF_PB2_REG_DBG_FORCE_FRAME                                                                  0xda4738UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
57464 #define PBF_PB2_REG_DB_FIFO                                                                          0xda6000UL //Access:WB_R DataWidth:0x108 Provides read-only access of the data buffer FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
57465 #define PBF_PB2_REG_DB_FIFO_SIZE                                                                     512
57466 #define PBF_PB2_REG_L1                                                                               0xda7000UL //Access:WB   DataWidth:0x40  L1 CRC memory access.  Chips: BB_A0 BB_B0 K2
57467 #define PBF_PB2_REG_L1_SIZE                                                                          640
57468 #define BTB_REG_HW_INIT_EN                                                                           0xdb0004UL //Access:RW   DataWidth:0x2   Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers will be done by HW.  Bit 1 - if this bit is set then initialization of BIG RAM will be done by HW. Both bits will be reset by HW when initialization is finished.  Chips: BB_A0 BB_B0 K2
57469 #define BTB_REG_INIT_DONE                                                                            0xdb0008UL //Access:R    DataWidth:0x2   Bit 0 - if this bit is set then initialization of link list; all head; tail and start_en registers are finished by HW.  Bit 1 - if this bit is set then initialization of BIG RAM is finished by HW.  Chips: BB_A0 BB_B0 K2
57470 #define BTB_REG_START_EN                                                                             0xdb000cUL //Access:RW   DataWidth:0x1   This bit should be set when initialization of all BRTB registers and memories is finished. BRTB will fill all prefetch FIFO with free pointers. BRTB will not be able to get packets from write clients when this bit is reset. If link list was configured by HW then this bit will be set by HW.  Chips: BB_A0 BB_B0 K2
57471 #define BTB_REG_INT_STS_0                                                                            0xdb00c0UL //Access:R    DataWidth:0x1d  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57472     #define BTB_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
57473     #define BTB_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
57474     #define BTB_REG_INT_STS_0_RC_PKT0_RLS_ERROR                                                      (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
57475     #define BTB_REG_INT_STS_0_RC_PKT0_RLS_ERROR_SHIFT                                                1
57476     #define BTB_REG_INT_STS_0_RC_PKT0_LEN_ERROR                                                      (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
57477     #define BTB_REG_INT_STS_0_RC_PKT0_LEN_ERROR_SHIFT                                                3
57478     #define BTB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR                                                 (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
57479     #define BTB_REG_INT_STS_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                           5
57480     #define BTB_REG_INT_STS_0_RC_PKT1_RLS_ERROR                                                      (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
57481     #define BTB_REG_INT_STS_0_RC_PKT1_RLS_ERROR_SHIFT                                                6
57482     #define BTB_REG_INT_STS_0_RC_PKT1_LEN_ERROR                                                      (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
57483     #define BTB_REG_INT_STS_0_RC_PKT1_LEN_ERROR_SHIFT                                                8
57484     #define BTB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR                                                 (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
57485     #define BTB_REG_INT_STS_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                           10
57486     #define BTB_REG_INT_STS_0_RC_PKT2_RLS_ERROR                                                      (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
57487     #define BTB_REG_INT_STS_0_RC_PKT2_RLS_ERROR_SHIFT                                                11
57488     #define BTB_REG_INT_STS_0_RC_PKT2_LEN_ERROR                                                      (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
57489     #define BTB_REG_INT_STS_0_RC_PKT2_LEN_ERROR_SHIFT                                                13
57490     #define BTB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR                                                 (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
57491     #define BTB_REG_INT_STS_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                           15
57492     #define BTB_REG_INT_STS_0_RC_PKT3_RLS_ERROR                                                      (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
57493     #define BTB_REG_INT_STS_0_RC_PKT3_RLS_ERROR_SHIFT                                                16
57494     #define BTB_REG_INT_STS_0_RC_PKT3_LEN_ERROR                                                      (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
57495     #define BTB_REG_INT_STS_0_RC_PKT3_LEN_ERROR_SHIFT                                                18
57496     #define BTB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR                                                 (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
57497     #define BTB_REG_INT_STS_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                           20
57498     #define BTB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR                                               (0x1<<21) // SOP descriptor request from empty TC or port.
57499     #define BTB_REG_INT_STS_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                         21
57500     #define BTB_REG_INT_STS_0_WC0_PROTOCOL_ERROR                                                     (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
57501     #define BTB_REG_INT_STS_0_WC0_PROTOCOL_ERROR_SHIFT                                               23
57502     #define BTB_REG_INT_STS_0_LL_BLK_ERROR                                                           (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
57503     #define BTB_REG_INT_STS_0_LL_BLK_ERROR_SHIFT                                                     28
57504 #define BTB_REG_INT_MASK_0                                                                           0xdb00c4UL //Access:RW   DataWidth:0x1d  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57505     #define BTB_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.ADDRESS_ERROR .
57506     #define BTB_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
57507     #define BTB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_RLS_ERROR .
57508     #define BTB_REG_INT_MASK_0_RC_PKT0_RLS_ERROR_SHIFT                                               1
57509     #define BTB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_LEN_ERROR .
57510     #define BTB_REG_INT_MASK_0_RC_PKT0_LEN_ERROR_SHIFT                                               3
57511     #define BTB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT0_PROTOCOL_ERROR .
57512     #define BTB_REG_INT_MASK_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                          5
57513     #define BTB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_RLS_ERROR .
57514     #define BTB_REG_INT_MASK_0_RC_PKT1_RLS_ERROR_SHIFT                                               6
57515     #define BTB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_LEN_ERROR .
57516     #define BTB_REG_INT_MASK_0_RC_PKT1_LEN_ERROR_SHIFT                                               8
57517     #define BTB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT1_PROTOCOL_ERROR .
57518     #define BTB_REG_INT_MASK_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                          10
57519     #define BTB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_RLS_ERROR .
57520     #define BTB_REG_INT_MASK_0_RC_PKT2_RLS_ERROR_SHIFT                                               11
57521     #define BTB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_LEN_ERROR .
57522     #define BTB_REG_INT_MASK_0_RC_PKT2_LEN_ERROR_SHIFT                                               13
57523     #define BTB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT2_PROTOCOL_ERROR .
57524     #define BTB_REG_INT_MASK_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                          15
57525     #define BTB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR                                                     (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_RLS_ERROR .
57526     #define BTB_REG_INT_MASK_0_RC_PKT3_RLS_ERROR_SHIFT                                               16
57527     #define BTB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR                                                     (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_LEN_ERROR .
57528     #define BTB_REG_INT_MASK_0_RC_PKT3_LEN_ERROR_SHIFT                                               18
57529     #define BTB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR                                                (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_PKT3_PROTOCOL_ERROR .
57530     #define BTB_REG_INT_MASK_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                          20
57531     #define BTB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.RC_SOP_REQ_TC_PORT_ERROR .
57532     #define BTB_REG_INT_MASK_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                        21
57533     #define BTB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR                                                    (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.WC0_PROTOCOL_ERROR .
57534     #define BTB_REG_INT_MASK_0_WC0_PROTOCOL_ERROR_SHIFT                                              23
57535     #define BTB_REG_INT_MASK_0_LL_BLK_ERROR                                                          (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_0.LL_BLK_ERROR .
57536     #define BTB_REG_INT_MASK_0_LL_BLK_ERROR_SHIFT                                                    28
57537 #define BTB_REG_INT_STS_WR_0                                                                         0xdb00c8UL //Access:WR   DataWidth:0x1d  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57538     #define BTB_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
57539     #define BTB_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
57540     #define BTB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR                                                   (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
57541     #define BTB_REG_INT_STS_WR_0_RC_PKT0_RLS_ERROR_SHIFT                                             1
57542     #define BTB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR                                                   (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
57543     #define BTB_REG_INT_STS_WR_0_RC_PKT0_LEN_ERROR_SHIFT                                             3
57544     #define BTB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR                                              (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
57545     #define BTB_REG_INT_STS_WR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                        5
57546     #define BTB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR                                                   (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
57547     #define BTB_REG_INT_STS_WR_0_RC_PKT1_RLS_ERROR_SHIFT                                             6
57548     #define BTB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR                                                   (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
57549     #define BTB_REG_INT_STS_WR_0_RC_PKT1_LEN_ERROR_SHIFT                                             8
57550     #define BTB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR                                              (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
57551     #define BTB_REG_INT_STS_WR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                        10
57552     #define BTB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR                                                   (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
57553     #define BTB_REG_INT_STS_WR_0_RC_PKT2_RLS_ERROR_SHIFT                                             11
57554     #define BTB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR                                                   (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
57555     #define BTB_REG_INT_STS_WR_0_RC_PKT2_LEN_ERROR_SHIFT                                             13
57556     #define BTB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR                                              (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
57557     #define BTB_REG_INT_STS_WR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                        15
57558     #define BTB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR                                                   (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
57559     #define BTB_REG_INT_STS_WR_0_RC_PKT3_RLS_ERROR_SHIFT                                             16
57560     #define BTB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR                                                   (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
57561     #define BTB_REG_INT_STS_WR_0_RC_PKT3_LEN_ERROR_SHIFT                                             18
57562     #define BTB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR                                              (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
57563     #define BTB_REG_INT_STS_WR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                        20
57564     #define BTB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR                                            (0x1<<21) // SOP descriptor request from empty TC or port.
57565     #define BTB_REG_INT_STS_WR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                      21
57566     #define BTB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR                                                  (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
57567     #define BTB_REG_INT_STS_WR_0_WC0_PROTOCOL_ERROR_SHIFT                                            23
57568     #define BTB_REG_INT_STS_WR_0_LL_BLK_ERROR                                                        (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
57569     #define BTB_REG_INT_STS_WR_0_LL_BLK_ERROR_SHIFT                                                  28
57570 #define BTB_REG_INT_STS_CLR_0                                                                        0xdb00ccUL //Access:RC   DataWidth:0x1d  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57571     #define BTB_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
57572     #define BTB_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
57573     #define BTB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR                                                  (0x1<<1) // Read packet client NIG main port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR0/PRM/g in Comments.
57574     #define BTB_REG_INT_STS_CLR_0_RC_PKT0_RLS_ERROR_SHIFT                                            1
57575     #define BTB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR                                                  (0x1<<3) // Read packet client NIG main port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR0/PRM/g in Comments.
57576     #define BTB_REG_INT_STS_CLR_0_RC_PKT0_LEN_ERROR_SHIFT                                            3
57577     #define BTB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR                                             (0x1<<5) // Read packet client NIG main port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR0/PRM/g in Comments.
57578     #define BTB_REG_INT_STS_CLR_0_RC_PKT0_PROTOCOL_ERROR_SHIFT                                       5
57579     #define BTB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR                                                  (0x1<<6) // Read packet client NIG LB port 0 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR1/MSDM/g in Comments.
57580     #define BTB_REG_INT_STS_CLR_0_RC_PKT1_RLS_ERROR_SHIFT                                            6
57581     #define BTB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR                                                  (0x1<<8) // Read packet client NIG LB port 0 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR1/MSDM/g in Comments.
57582     #define BTB_REG_INT_STS_CLR_0_RC_PKT1_LEN_ERROR_SHIFT                                            8
57583     #define BTB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR                                             (0x1<<10) // Read packet client NIG LB port 0 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR1/MSDM/g in Comments.
57584     #define BTB_REG_INT_STS_CLR_0_RC_PKT1_PROTOCOL_ERROR_SHIFT                                       10
57585     #define BTB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR                                                  (0x1<<11) // Read packet client NIG main port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR2/TSDM/g in Comments.
57586     #define BTB_REG_INT_STS_CLR_0_RC_PKT2_RLS_ERROR_SHIFT                                            11
57587     #define BTB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR                                                  (0x1<<13) // Read packet client NIG main port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR2/TSDM/g in Comments.
57588     #define BTB_REG_INT_STS_CLR_0_RC_PKT2_LEN_ERROR_SHIFT                                            13
57589     #define BTB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR                                             (0x1<<15) // Read packet client NIG main port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR2/TSDM/g in Comments.
57590     #define BTB_REG_INT_STS_CLR_0_RC_PKT2_PROTOCOL_ERROR_SHIFT                                       15
57591     #define BTB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR                                                  (0x1<<16) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
57592     #define BTB_REG_INT_STS_CLR_0_RC_PKT3_RLS_ERROR_SHIFT                                            16
57593     #define BTB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR                                                  (0x1<<18) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
57594     #define BTB_REG_INT_STS_CLR_0_RC_PKT3_LEN_ERROR_SHIFT                                            18
57595     #define BTB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR                                             (0x1<<20) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
57596     #define BTB_REG_INT_STS_CLR_0_RC_PKT3_PROTOCOL_ERROR_SHIFT                                       20
57597     #define BTB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR                                           (0x1<<21) // SOP descriptor request from empty TC or port.
57598     #define BTB_REG_INT_STS_CLR_0_RC_SOP_REQ_TC_PORT_ERROR_SHIFT                                     21
57599     #define BTB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR                                                 (0x1<<23) // Write packet error when packet doesn't have SOP or EOP on write interface 0.
57600     #define BTB_REG_INT_STS_CLR_0_WC0_PROTOCOL_ERROR_SHIFT                                           23
57601     #define BTB_REG_INT_STS_CLR_0_LL_BLK_ERROR                                                       (0x1<<28) // Head or tail pointer of some link list has a value bigger than number of blocks.
57602     #define BTB_REG_INT_STS_CLR_0_LL_BLK_ERROR_SHIFT                                                 28
57603 #define BTB_REG_INT_STS_1                                                                            0xdb00d8UL //Access:R    DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57604     #define BTB_REG_INT_STS_1_LL_ARB_CALC_ERROR                                                      (0x1<<1) // Calculations error in LL arbiter block.
57605     #define BTB_REG_INT_STS_1_LL_ARB_CALC_ERROR_SHIFT                                                1
57606     #define BTB_REG_INT_STS_1_FC_ALM_CALC_ERROR                                                      (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
57607     #define BTB_REG_INT_STS_1_FC_ALM_CALC_ERROR_SHIFT                                                2
57608     #define BTB_REG_INT_STS_1_WC0_INP_FIFO_ERROR                                                     (0x1<<3) // Input FIFO error in write client 0.
57609     #define BTB_REG_INT_STS_1_WC0_INP_FIFO_ERROR_SHIFT                                               3
57610     #define BTB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR                                                     (0x1<<4) // SOP FIFO error in write client 0.
57611     #define BTB_REG_INT_STS_1_WC0_SOP_FIFO_ERROR_SHIFT                                               4
57612     #define BTB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR                                                     (0x1<<5) // LEN FIFO error in write client 0.
57613     #define BTB_REG_INT_STS_1_WC0_LEN_FIFO_ERROR_SHIFT                                               5
57614     #define BTB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR                                                     (0x1<<6) // EOP FIFO error in write client 0.
57615     #define BTB_REG_INT_STS_1_WC0_EOP_FIFO_ERROR_SHIFT                                               6
57616     #define BTB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR                                                   (0x1<<7) // Queue FIFO error in write client 0.
57617     #define BTB_REG_INT_STS_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                             7
57618     #define BTB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR                                              (0x1<<8) // Free ointer FIFO error in write client 0.
57619     #define BTB_REG_INT_STS_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                        8
57620     #define BTB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR                                              (0x1<<9) // Next pointer FIFO error in write client 0.
57621     #define BTB_REG_INT_STS_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                        9
57622     #define BTB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR                                                    (0x1<<10) // Start FIFO error in write client 0.
57623     #define BTB_REG_INT_STS_1_WC0_STRT_FIFO_ERROR_SHIFT                                              10
57624     #define BTB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR                                             (0x1<<11) // Second descriptor FIFO error in write client 0.
57625     #define BTB_REG_INT_STS_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                       11
57626     #define BTB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR                                               (0x1<<12) // Packet available FIFO error in write client 0.
57627     #define BTB_REG_INT_STS_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                         12
57628     #define BTB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR                                                  (0x1<<14) // Notify FIFO error in write client 0.
57629     #define BTB_REG_INT_STS_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                            14
57630     #define BTB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR                                                  (0x1<<15) // LL req error in write client 0.
57631     #define BTB_REG_INT_STS_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                            15
57632     #define BTB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR                                                    (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
57633     #define BTB_REG_INT_STS_1_WC0_LL_PA_CNT_ERROR_SHIFT                                              16
57634     #define BTB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR                                                    (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
57635     #define BTB_REG_INT_STS_1_WC0_BB_PA_CNT_ERROR_SHIFT                                              17
57636 #define BTB_REG_INT_MASK_1                                                                           0xdb00dcUL //Access:RW   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57637     #define BTB_REG_INT_MASK_1_LL_ARB_CALC_ERROR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.LL_ARB_CALC_ERROR .
57638     #define BTB_REG_INT_MASK_1_LL_ARB_CALC_ERROR_SHIFT                                               1
57639     #define BTB_REG_INT_MASK_1_FC_ALM_CALC_ERROR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.FC_ALM_CALC_ERROR .
57640     #define BTB_REG_INT_MASK_1_FC_ALM_CALC_ERROR_SHIFT                                               2
57641     #define BTB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR                                                    (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_INP_FIFO_ERROR .
57642     #define BTB_REG_INT_MASK_1_WC0_INP_FIFO_ERROR_SHIFT                                              3
57643     #define BTB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR                                                    (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_SOP_FIFO_ERROR .
57644     #define BTB_REG_INT_MASK_1_WC0_SOP_FIFO_ERROR_SHIFT                                              4
57645     #define BTB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR                                                    (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LEN_FIFO_ERROR .
57646     #define BTB_REG_INT_MASK_1_WC0_LEN_FIFO_ERROR_SHIFT                                              5
57647     #define BTB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR                                                    (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_EOP_FIFO_ERROR .
57648     #define BTB_REG_INT_MASK_1_WC0_EOP_FIFO_ERROR_SHIFT                                              6
57649     #define BTB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR                                                  (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_QUEUE_FIFO_ERROR .
57650     #define BTB_REG_INT_MASK_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                            7
57651     #define BTB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_FREE_POINT_FIFO_ERROR .
57652     #define BTB_REG_INT_MASK_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                       8
57653     #define BTB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR                                             (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_NEXT_POINT_FIFO_ERROR .
57654     #define BTB_REG_INT_MASK_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                       9
57655     #define BTB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR                                                   (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_STRT_FIFO_ERROR .
57656     #define BTB_REG_INT_MASK_1_WC0_STRT_FIFO_ERROR_SHIFT                                             10
57657     #define BTB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR                                            (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_SECOND_DSCR_FIFO_ERROR .
57658     #define BTB_REG_INT_MASK_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                      11
57659     #define BTB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR                                              (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_PKT_AVAIL_FIFO_ERROR .
57660     #define BTB_REG_INT_MASK_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                        12
57661     #define BTB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_NOTIFY_FIFO_ERROR .
57662     #define BTB_REG_INT_MASK_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                           14
57663     #define BTB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR                                                 (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LL_REQ_FIFO_ERROR .
57664     #define BTB_REG_INT_MASK_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                           15
57665     #define BTB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_LL_PA_CNT_ERROR .
57666     #define BTB_REG_INT_MASK_1_WC0_LL_PA_CNT_ERROR_SHIFT                                             16
57667     #define BTB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR                                                   (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_1.WC0_BB_PA_CNT_ERROR .
57668     #define BTB_REG_INT_MASK_1_WC0_BB_PA_CNT_ERROR_SHIFT                                             17
57669 #define BTB_REG_INT_STS_WR_1                                                                         0xdb00e0UL //Access:WR   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57670     #define BTB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR                                                   (0x1<<1) // Calculations error in LL arbiter block.
57671     #define BTB_REG_INT_STS_WR_1_LL_ARB_CALC_ERROR_SHIFT                                             1
57672     #define BTB_REG_INT_STS_WR_1_FC_ALM_CALC_ERROR                                                   (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
57673     #define BTB_REG_INT_STS_WR_1_FC_ALM_CALC_ERROR_SHIFT                                             2
57674     #define BTB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR                                                  (0x1<<3) // Input FIFO error in write client 0.
57675     #define BTB_REG_INT_STS_WR_1_WC0_INP_FIFO_ERROR_SHIFT                                            3
57676     #define BTB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR                                                  (0x1<<4) // SOP FIFO error in write client 0.
57677     #define BTB_REG_INT_STS_WR_1_WC0_SOP_FIFO_ERROR_SHIFT                                            4
57678     #define BTB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR                                                  (0x1<<5) // LEN FIFO error in write client 0.
57679     #define BTB_REG_INT_STS_WR_1_WC0_LEN_FIFO_ERROR_SHIFT                                            5
57680     #define BTB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR                                                  (0x1<<6) // EOP FIFO error in write client 0.
57681     #define BTB_REG_INT_STS_WR_1_WC0_EOP_FIFO_ERROR_SHIFT                                            6
57682     #define BTB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR                                                (0x1<<7) // Queue FIFO error in write client 0.
57683     #define BTB_REG_INT_STS_WR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                          7
57684     #define BTB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR                                           (0x1<<8) // Free ointer FIFO error in write client 0.
57685     #define BTB_REG_INT_STS_WR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                     8
57686     #define BTB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR                                           (0x1<<9) // Next pointer FIFO error in write client 0.
57687     #define BTB_REG_INT_STS_WR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                     9
57688     #define BTB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR                                                 (0x1<<10) // Start FIFO error in write client 0.
57689     #define BTB_REG_INT_STS_WR_1_WC0_STRT_FIFO_ERROR_SHIFT                                           10
57690     #define BTB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR                                          (0x1<<11) // Second descriptor FIFO error in write client 0.
57691     #define BTB_REG_INT_STS_WR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                    11
57692     #define BTB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR                                            (0x1<<12) // Packet available FIFO error in write client 0.
57693     #define BTB_REG_INT_STS_WR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                      12
57694     #define BTB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR                                               (0x1<<14) // Notify FIFO error in write client 0.
57695     #define BTB_REG_INT_STS_WR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                         14
57696     #define BTB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR                                               (0x1<<15) // LL req error in write client 0.
57697     #define BTB_REG_INT_STS_WR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                         15
57698     #define BTB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR                                                 (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
57699     #define BTB_REG_INT_STS_WR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                           16
57700     #define BTB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR                                                 (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
57701     #define BTB_REG_INT_STS_WR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                           17
57702 #define BTB_REG_INT_STS_CLR_1                                                                        0xdb00e4UL //Access:RC   DataWidth:0x12  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57703     #define BTB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR                                                  (0x1<<1) // Calculations error in LL arbiter block.
57704     #define BTB_REG_INT_STS_CLR_1_LL_ARB_CALC_ERROR_SHIFT                                            1
57705     #define BTB_REG_INT_STS_CLR_1_FC_ALM_CALC_ERROR                                                  (0x1<<2) // Calculations error in almost full counter block ALM_FULL_EN::/ALM_FULL_EN/d in Comments.
57706     #define BTB_REG_INT_STS_CLR_1_FC_ALM_CALC_ERROR_SHIFT                                            2
57707     #define BTB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR                                                 (0x1<<3) // Input FIFO error in write client 0.
57708     #define BTB_REG_INT_STS_CLR_1_WC0_INP_FIFO_ERROR_SHIFT                                           3
57709     #define BTB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR                                                 (0x1<<4) // SOP FIFO error in write client 0.
57710     #define BTB_REG_INT_STS_CLR_1_WC0_SOP_FIFO_ERROR_SHIFT                                           4
57711     #define BTB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR                                                 (0x1<<5) // LEN FIFO error in write client 0.
57712     #define BTB_REG_INT_STS_CLR_1_WC0_LEN_FIFO_ERROR_SHIFT                                           5
57713     #define BTB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR                                                 (0x1<<6) // EOP FIFO error in write client 0.
57714     #define BTB_REG_INT_STS_CLR_1_WC0_EOP_FIFO_ERROR_SHIFT                                           6
57715     #define BTB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR                                               (0x1<<7) // Queue FIFO error in write client 0.
57716     #define BTB_REG_INT_STS_CLR_1_WC0_QUEUE_FIFO_ERROR_SHIFT                                         7
57717     #define BTB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR                                          (0x1<<8) // Free ointer FIFO error in write client 0.
57718     #define BTB_REG_INT_STS_CLR_1_WC0_FREE_POINT_FIFO_ERROR_SHIFT                                    8
57719     #define BTB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR                                          (0x1<<9) // Next pointer FIFO error in write client 0.
57720     #define BTB_REG_INT_STS_CLR_1_WC0_NEXT_POINT_FIFO_ERROR_SHIFT                                    9
57721     #define BTB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR                                                (0x1<<10) // Start FIFO error in write client 0.
57722     #define BTB_REG_INT_STS_CLR_1_WC0_STRT_FIFO_ERROR_SHIFT                                          10
57723     #define BTB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR                                         (0x1<<11) // Second descriptor FIFO error in write client 0.
57724     #define BTB_REG_INT_STS_CLR_1_WC0_SECOND_DSCR_FIFO_ERROR_SHIFT                                   11
57725     #define BTB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR                                           (0x1<<12) // Packet available FIFO error in write client 0.
57726     #define BTB_REG_INT_STS_CLR_1_WC0_PKT_AVAIL_FIFO_ERROR_SHIFT                                     12
57727     #define BTB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR                                              (0x1<<14) // Notify FIFO error in write client 0.
57728     #define BTB_REG_INT_STS_CLR_1_WC0_NOTIFY_FIFO_ERROR_SHIFT                                        14
57729     #define BTB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR                                              (0x1<<15) // LL req error in write client 0.
57730     #define BTB_REG_INT_STS_CLR_1_WC0_LL_REQ_FIFO_ERROR_SHIFT                                        15
57731     #define BTB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR                                                (0x1<<16) // Packet available counter overflow or underflow for requests to link list.
57732     #define BTB_REG_INT_STS_CLR_1_WC0_LL_PA_CNT_ERROR_SHIFT                                          16
57733     #define BTB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR                                                (0x1<<17) // Packet available counter overflow or underflow for requests to big ram of SOP descriptor.
57734     #define BTB_REG_INT_STS_CLR_1_WC0_BB_PA_CNT_ERROR_SHIFT                                          17
57735 #define BTB_REG_INT_STS_2                                                                            0xdb00f0UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57736     #define BTB_REG_INT_STS_2_WC_DUP_UPD_DATA_FIFO_ERROR                                             (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57737     #define BTB_REG_INT_STS_2_WC_DUP_UPD_DATA_FIFO_ERROR_SHIFT                                       28
57738     #define BTB_REG_INT_STS_2_WC_DUP_RSP_DSCR_FIFO_ERROR                                             (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57739     #define BTB_REG_INT_STS_2_WC_DUP_RSP_DSCR_FIFO_ERROR_SHIFT                                       29
57740     #define BTB_REG_INT_STS_2_WC_DUP_UPD_POINT_FIFO_ERROR                                            (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57741     #define BTB_REG_INT_STS_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT                                      30
57742     #define BTB_REG_INT_STS_2_WC_DUP_PKT_AVAIL_FIFO_ERROR                                            (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57743     #define BTB_REG_INT_STS_2_WC_DUP_PKT_AVAIL_FIFO_ERROR_SHIFT                                      31
57744 #define BTB_REG_INT_MASK_2                                                                           0xdb00f4UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57745     #define BTB_REG_INT_MASK_2_WC_DUP_UPD_DATA_FIFO_ERROR                                            (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_UPD_DATA_FIFO_ERROR .
57746     #define BTB_REG_INT_MASK_2_WC_DUP_UPD_DATA_FIFO_ERROR_SHIFT                                      28
57747     #define BTB_REG_INT_MASK_2_WC_DUP_RSP_DSCR_FIFO_ERROR                                            (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_RSP_DSCR_FIFO_ERROR .
57748     #define BTB_REG_INT_MASK_2_WC_DUP_RSP_DSCR_FIFO_ERROR_SHIFT                                      29
57749     #define BTB_REG_INT_MASK_2_WC_DUP_UPD_POINT_FIFO_ERROR                                           (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_UPD_POINT_FIFO_ERROR .
57750     #define BTB_REG_INT_MASK_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT                                     30
57751     #define BTB_REG_INT_MASK_2_WC_DUP_PKT_AVAIL_FIFO_ERROR                                           (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_2.WC_DUP_PKT_AVAIL_FIFO_ERROR .
57752     #define BTB_REG_INT_MASK_2_WC_DUP_PKT_AVAIL_FIFO_ERROR_SHIFT                                     31
57753 #define BTB_REG_INT_STS_WR_2                                                                         0xdb00f8UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57754     #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_DATA_FIFO_ERROR                                          (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57755     #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_DATA_FIFO_ERROR_SHIFT                                    28
57756     #define BTB_REG_INT_STS_WR_2_WC_DUP_RSP_DSCR_FIFO_ERROR                                          (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57757     #define BTB_REG_INT_STS_WR_2_WC_DUP_RSP_DSCR_FIFO_ERROR_SHIFT                                    29
57758     #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_POINT_FIFO_ERROR                                         (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57759     #define BTB_REG_INT_STS_WR_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT                                   30
57760     #define BTB_REG_INT_STS_WR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR                                         (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57761     #define BTB_REG_INT_STS_WR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR_SHIFT                                   31
57762 #define BTB_REG_INT_STS_CLR_2                                                                        0xdb00fcUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57763     #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_DATA_FIFO_ERROR                                         (0x1<<28) // Updated data FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57764     #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_DATA_FIFO_ERROR_SHIFT                                   28
57765     #define BTB_REG_INT_STS_CLR_2_WC_DUP_RSP_DSCR_FIFO_ERROR                                         (0x1<<29) // Response descriptor FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57766     #define BTB_REG_INT_STS_CLR_2_WC_DUP_RSP_DSCR_FIFO_ERROR_SHIFT                                   29
57767     #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_POINT_FIFO_ERROR                                        (0x1<<30) // Updated pointer FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57768     #define BTB_REG_INT_STS_CLR_2_WC_DUP_UPD_POINT_FIFO_ERROR_SHIFT                                  30
57769     #define BTB_REG_INT_STS_CLR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR                                        (0x1<<31) // Packet available FIFO error in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57770     #define BTB_REG_INT_STS_CLR_2_WC_DUP_PKT_AVAIL_FIFO_ERROR_SHIFT                                  31
57771 #define BTB_REG_INT_STS_3                                                                            0xdb0108UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57772     #define BTB_REG_INT_STS_3_WC_DUP_PKT_AVAIL_CNT_ERROR                                             (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57773     #define BTB_REG_INT_STS_3_WC_DUP_PKT_AVAIL_CNT_ERROR_SHIFT                                       0
57774     #define BTB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR                                                (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57775     #define BTB_REG_INT_STS_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                          1
57776     #define BTB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR                                                 (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57777     #define BTB_REG_INT_STS_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                           2
57778     #define BTB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR                                                 (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57779     #define BTB_REG_INT_STS_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                           3
57780     #define BTB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                            (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57781     #define BTB_REG_INT_STS_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                      4
57782     #define BTB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                            (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57783     #define BTB_REG_INT_STS_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                      5
57784     #define BTB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                          (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57785     #define BTB_REG_INT_STS_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                    6
57786     #define BTB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR                                                 (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57787     #define BTB_REG_INT_STS_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                           7
57788     #define BTB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR                                                (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57789     #define BTB_REG_INT_STS_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                          8
57790     #define BTB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR                                                (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57791     #define BTB_REG_INT_STS_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                          9
57792     #define BTB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR                                                 (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57793     #define BTB_REG_INT_STS_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                           10
57794     #define BTB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR                                                 (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57795     #define BTB_REG_INT_STS_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                           11
57796     #define BTB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                            (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57797     #define BTB_REG_INT_STS_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                      12
57798     #define BTB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                            (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57799     #define BTB_REG_INT_STS_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                      13
57800     #define BTB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                          (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57801     #define BTB_REG_INT_STS_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                    14
57802     #define BTB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR                                                 (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57803     #define BTB_REG_INT_STS_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                           15
57804     #define BTB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR                                                (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57805     #define BTB_REG_INT_STS_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                          16
57806     #define BTB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR                                                (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57807     #define BTB_REG_INT_STS_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                          17
57808     #define BTB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR                                                 (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57809     #define BTB_REG_INT_STS_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                           18
57810     #define BTB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR                                                 (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57811     #define BTB_REG_INT_STS_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                           19
57812     #define BTB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                            (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57813     #define BTB_REG_INT_STS_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                      20
57814     #define BTB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                            (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57815     #define BTB_REG_INT_STS_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                      21
57816     #define BTB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                          (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57817     #define BTB_REG_INT_STS_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                    22
57818     #define BTB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR                                                 (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57819     #define BTB_REG_INT_STS_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                           23
57820     #define BTB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR                                                (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57821     #define BTB_REG_INT_STS_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                          24
57822     #define BTB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR                                                (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57823     #define BTB_REG_INT_STS_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                          25
57824     #define BTB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR                                                 (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57825     #define BTB_REG_INT_STS_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                           26
57826     #define BTB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR                                                 (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57827     #define BTB_REG_INT_STS_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                           27
57828     #define BTB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                            (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57829     #define BTB_REG_INT_STS_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                      28
57830     #define BTB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                            (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57831     #define BTB_REG_INT_STS_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                      29
57832     #define BTB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                          (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57833     #define BTB_REG_INT_STS_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                    30
57834     #define BTB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR                                                 (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57835     #define BTB_REG_INT_STS_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                           31
57836 #define BTB_REG_INT_MASK_3                                                                           0xdb010cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57837     #define BTB_REG_INT_MASK_3_WC_DUP_PKT_AVAIL_CNT_ERROR                                            (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.WC_DUP_PKT_AVAIL_CNT_ERROR .
57838     #define BTB_REG_INT_MASK_3_WC_DUP_PKT_AVAIL_CNT_ERROR_SHIFT                                      0
57839     #define BTB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR                                               (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_SIDE_FIFO_ERROR .
57840     #define BTB_REG_INT_MASK_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                         1
57841     #define BTB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_REQ_FIFO_ERROR .
57842     #define BTB_REG_INT_MASK_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                          2
57843     #define BTB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR                                                (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_BLK_FIFO_ERROR .
57844     #define BTB_REG_INT_MASK_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                          3
57845     #define BTB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                           (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_RLS_LEFT_FIFO_ERROR .
57846     #define BTB_REG_INT_MASK_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                     4
57847     #define BTB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                           (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_STRT_PTR_FIFO_ERROR .
57848     #define BTB_REG_INT_MASK_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                     5
57849     #define BTB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                         (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_SECOND_PTR_FIFO_ERROR .
57850     #define BTB_REG_INT_MASK_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                   6
57851     #define BTB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_RSP_FIFO_ERROR .
57852     #define BTB_REG_INT_MASK_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                          7
57853     #define BTB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT0_DSCR_FIFO_ERROR .
57854     #define BTB_REG_INT_MASK_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                         8
57855     #define BTB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR                                               (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_SIDE_FIFO_ERROR .
57856     #define BTB_REG_INT_MASK_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                         9
57857     #define BTB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_REQ_FIFO_ERROR .
57858     #define BTB_REG_INT_MASK_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                          10
57859     #define BTB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_BLK_FIFO_ERROR .
57860     #define BTB_REG_INT_MASK_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                          11
57861     #define BTB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                           (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_RLS_LEFT_FIFO_ERROR .
57862     #define BTB_REG_INT_MASK_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                     12
57863     #define BTB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                           (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_STRT_PTR_FIFO_ERROR .
57864     #define BTB_REG_INT_MASK_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                     13
57865     #define BTB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_SECOND_PTR_FIFO_ERROR .
57866     #define BTB_REG_INT_MASK_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                   14
57867     #define BTB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_RSP_FIFO_ERROR .
57868     #define BTB_REG_INT_MASK_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                          15
57869     #define BTB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR                                               (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT1_DSCR_FIFO_ERROR .
57870     #define BTB_REG_INT_MASK_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                         16
57871     #define BTB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR                                               (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_SIDE_FIFO_ERROR .
57872     #define BTB_REG_INT_MASK_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                         17
57873     #define BTB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR                                                (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_REQ_FIFO_ERROR .
57874     #define BTB_REG_INT_MASK_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                          18
57875     #define BTB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR                                                (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_BLK_FIFO_ERROR .
57876     #define BTB_REG_INT_MASK_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                          19
57877     #define BTB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                           (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_RLS_LEFT_FIFO_ERROR .
57878     #define BTB_REG_INT_MASK_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                     20
57879     #define BTB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                           (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_STRT_PTR_FIFO_ERROR .
57880     #define BTB_REG_INT_MASK_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                     21
57881     #define BTB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                         (0x1<<22) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_SECOND_PTR_FIFO_ERROR .
57882     #define BTB_REG_INT_MASK_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                   22
57883     #define BTB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_RSP_FIFO_ERROR .
57884     #define BTB_REG_INT_MASK_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                          23
57885     #define BTB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT2_DSCR_FIFO_ERROR .
57886     #define BTB_REG_INT_MASK_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                         24
57887     #define BTB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_SIDE_FIFO_ERROR .
57888     #define BTB_REG_INT_MASK_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                         25
57889     #define BTB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_REQ_FIFO_ERROR .
57890     #define BTB_REG_INT_MASK_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                          26
57891     #define BTB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR                                                (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_BLK_FIFO_ERROR .
57892     #define BTB_REG_INT_MASK_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                          27
57893     #define BTB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_RLS_LEFT_FIFO_ERROR .
57894     #define BTB_REG_INT_MASK_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                     28
57895     #define BTB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_STRT_PTR_FIFO_ERROR .
57896     #define BTB_REG_INT_MASK_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                     29
57897     #define BTB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_SECOND_PTR_FIFO_ERROR .
57898     #define BTB_REG_INT_MASK_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                   30
57899     #define BTB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_3.RC_PKT3_RSP_FIFO_ERROR .
57900     #define BTB_REG_INT_MASK_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                          31
57901 #define BTB_REG_INT_STS_WR_3                                                                         0xdb0110UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57902     #define BTB_REG_INT_STS_WR_3_WC_DUP_PKT_AVAIL_CNT_ERROR                                          (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57903     #define BTB_REG_INT_STS_WR_3_WC_DUP_PKT_AVAIL_CNT_ERROR_SHIFT                                    0
57904     #define BTB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR                                             (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57905     #define BTB_REG_INT_STS_WR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                       1
57906     #define BTB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR                                              (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57907     #define BTB_REG_INT_STS_WR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                        2
57908     #define BTB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR                                              (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57909     #define BTB_REG_INT_STS_WR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                        3
57910     #define BTB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                         (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57911     #define BTB_REG_INT_STS_WR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                   4
57912     #define BTB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                         (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57913     #define BTB_REG_INT_STS_WR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                   5
57914     #define BTB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                       (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57915     #define BTB_REG_INT_STS_WR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                 6
57916     #define BTB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR                                              (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57917     #define BTB_REG_INT_STS_WR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                        7
57918     #define BTB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR                                             (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57919     #define BTB_REG_INT_STS_WR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                       8
57920     #define BTB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR                                             (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57921     #define BTB_REG_INT_STS_WR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                       9
57922     #define BTB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR                                              (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57923     #define BTB_REG_INT_STS_WR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                        10
57924     #define BTB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR                                              (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57925     #define BTB_REG_INT_STS_WR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                        11
57926     #define BTB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                         (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57927     #define BTB_REG_INT_STS_WR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                   12
57928     #define BTB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                         (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57929     #define BTB_REG_INT_STS_WR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                   13
57930     #define BTB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                       (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57931     #define BTB_REG_INT_STS_WR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                 14
57932     #define BTB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR                                              (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57933     #define BTB_REG_INT_STS_WR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                        15
57934     #define BTB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR                                             (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57935     #define BTB_REG_INT_STS_WR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                       16
57936     #define BTB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR                                             (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57937     #define BTB_REG_INT_STS_WR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                       17
57938     #define BTB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR                                              (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57939     #define BTB_REG_INT_STS_WR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                        18
57940     #define BTB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR                                              (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57941     #define BTB_REG_INT_STS_WR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                        19
57942     #define BTB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                         (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57943     #define BTB_REG_INT_STS_WR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                   20
57944     #define BTB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                         (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57945     #define BTB_REG_INT_STS_WR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                   21
57946     #define BTB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                       (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57947     #define BTB_REG_INT_STS_WR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                 22
57948     #define BTB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR                                              (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57949     #define BTB_REG_INT_STS_WR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                        23
57950     #define BTB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR                                             (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
57951     #define BTB_REG_INT_STS_WR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                       24
57952     #define BTB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR                                             (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57953     #define BTB_REG_INT_STS_WR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                       25
57954     #define BTB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR                                              (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57955     #define BTB_REG_INT_STS_WR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                        26
57956     #define BTB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR                                              (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57957     #define BTB_REG_INT_STS_WR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                        27
57958     #define BTB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                         (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57959     #define BTB_REG_INT_STS_WR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                   28
57960     #define BTB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                         (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57961     #define BTB_REG_INT_STS_WR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                   29
57962     #define BTB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                       (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57963     #define BTB_REG_INT_STS_WR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                 30
57964     #define BTB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR                                              (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
57965     #define BTB_REG_INT_STS_WR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                        31
57966 #define BTB_REG_INT_STS_CLR_3                                                                        0xdb0114UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
57967     #define BTB_REG_INT_STS_CLR_3_WC_DUP_PKT_AVAIL_CNT_ERROR                                         (0x1<<0) // Packet available counter overflow or underflow in duplicated write client DUP_EN::/DUP_EN/d in Comments.
57968     #define BTB_REG_INT_STS_CLR_3_WC_DUP_PKT_AVAIL_CNT_ERROR_SHIFT                                   0
57969     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR                                            (0x1<<1) // Read packet client NIG main port 0 side info FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57970     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SIDE_FIFO_ERROR_SHIFT                                      1
57971     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR                                             (0x1<<2) // Read packet client NIG main port 0 request FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57972     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_REQ_FIFO_ERROR_SHIFT                                       2
57973     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR                                             (0x1<<3) // Read packet client NIG main port 0 block FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57974     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_BLK_FIFO_ERROR_SHIFT                                       3
57975     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR                                        (0x1<<4) // Read packet client NIG main port 0 releases left FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57976     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RLS_LEFT_FIFO_ERROR_SHIFT                                  4
57977     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR                                        (0x1<<5) // Read packet client NIG main port 0 start pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57978     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_STRT_PTR_FIFO_ERROR_SHIFT                                  5
57979     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR                                      (0x1<<6) // Read packet client NIG main port 0 second pointer FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57980     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_SECOND_PTR_FIFO_ERROR_SHIFT                                6
57981     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR                                             (0x1<<7) // Read packet client NIG main port 0 response FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57982     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_RSP_FIFO_ERROR_SHIFT                                       7
57983     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR                                            (0x1<<8) // Read packet client NIG main port 0 descriptor FIFO error ::s/RC_PKT_DSCR0/PRM/g in Comments.
57984     #define BTB_REG_INT_STS_CLR_3_RC_PKT0_DSCR_FIFO_ERROR_SHIFT                                      8
57985     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR                                            (0x1<<9) // Read packet client NIG LB port 0 side info FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57986     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SIDE_FIFO_ERROR_SHIFT                                      9
57987     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR                                             (0x1<<10) // Read packet client NIG LB port 0 request FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57988     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_REQ_FIFO_ERROR_SHIFT                                       10
57989     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR                                             (0x1<<11) // Read packet client NIG LB port 0 block FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57990     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_BLK_FIFO_ERROR_SHIFT                                       11
57991     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR                                        (0x1<<12) // Read packet client NIG LB port 0 releases left FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57992     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RLS_LEFT_FIFO_ERROR_SHIFT                                  12
57993     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR                                        (0x1<<13) // Read packet client NIG LB port 0 start pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57994     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_STRT_PTR_FIFO_ERROR_SHIFT                                  13
57995     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR                                      (0x1<<14) // Read packet client NIG LB port 0 second pointer FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57996     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_SECOND_PTR_FIFO_ERROR_SHIFT                                14
57997     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR                                             (0x1<<15) // Read packet client NIG LB port 0 response FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
57998     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_RSP_FIFO_ERROR_SHIFT                                       15
57999     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR                                            (0x1<<16) // Read packet client NIG LB port 0 descriptor FIFO error ::s/RC_PKT_DSCR1/MSDM/g in Comments.
58000     #define BTB_REG_INT_STS_CLR_3_RC_PKT1_DSCR_FIFO_ERROR_SHIFT                                      16
58001     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR                                            (0x1<<17) // Read packet client NIG main port 1 side info FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
58002     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SIDE_FIFO_ERROR_SHIFT                                      17
58003     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR                                             (0x1<<18) // Read packet client NIG main port 1 request FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
58004     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_REQ_FIFO_ERROR_SHIFT                                       18
58005     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR                                             (0x1<<19) // Read packet client NIG main port 1 block FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
58006     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_BLK_FIFO_ERROR_SHIFT                                       19
58007     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR                                        (0x1<<20) // Read packet client NIG main port 1 releases left FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
58008     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RLS_LEFT_FIFO_ERROR_SHIFT                                  20
58009     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR                                        (0x1<<21) // Read packet client NIG main port 1 start pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
58010     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_STRT_PTR_FIFO_ERROR_SHIFT                                  21
58011     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR                                      (0x1<<22) // Read packet client NIG main port 1 second pointer FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
58012     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_SECOND_PTR_FIFO_ERROR_SHIFT                                22
58013     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR                                             (0x1<<23) // Read packet client NIG main port 1 response FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
58014     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_RSP_FIFO_ERROR_SHIFT                                       23
58015     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR                                            (0x1<<24) // Read packet client NIG main port 1 descriptor FIFO error ::s/RC_PKT_DSCR2/TSDM/g in Comments.
58016     #define BTB_REG_INT_STS_CLR_3_RC_PKT2_DSCR_FIFO_ERROR_SHIFT                                      24
58017     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR                                            (0x1<<25) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58018     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SIDE_FIFO_ERROR_SHIFT                                      25
58019     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR                                             (0x1<<26) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58020     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_REQ_FIFO_ERROR_SHIFT                                       26
58021     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR                                             (0x1<<27) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58022     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_BLK_FIFO_ERROR_SHIFT                                       27
58023     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR                                        (0x1<<28) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58024     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RLS_LEFT_FIFO_ERROR_SHIFT                                  28
58025     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR                                        (0x1<<29) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58026     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_STRT_PTR_FIFO_ERROR_SHIFT                                  29
58027     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR                                      (0x1<<30) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58028     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_SECOND_PTR_FIFO_ERROR_SHIFT                                30
58029     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR                                             (0x1<<31) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58030     #define BTB_REG_INT_STS_CLR_3_RC_PKT3_RSP_FIFO_ERROR_SHIFT                                       31
58031 #define BTB_REG_INT_STS_4                                                                            0xdb0120UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58032     #define BTB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR                                                (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58033     #define BTB_REG_INT_STS_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                          0
58034     #define BTB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR                                                (0x1<<4) // Read SOP client queue FIFO error.
58035     #define BTB_REG_INT_STS_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                          4
58036     #define BTB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR                                                  (0x1<<7) // Link list arbiter release FIFO error.
58037     #define BTB_REG_INT_STS_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                            7
58038     #define BTB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR                                             (0x1<<8) // Link list arbiter prefetch FIFO error.
58039     #define BTB_REG_INT_STS_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                       8
58040     #define BTB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR                                                 (0x1<<9) // Read packet client NIG main port 0 release fifo error
58041     #define BTB_REG_INT_STS_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                           9
58042     #define BTB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR                                                 (0x1<<10) // Read packet client NIG LB port 0 release fifo error
58043     #define BTB_REG_INT_STS_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                           10
58044     #define BTB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR                                                 (0x1<<11) // Read packet client NIG main port 1 release fifo error
58045     #define BTB_REG_INT_STS_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                           11
58046     #define BTB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR                                                 (0x1<<12) // Read packet client NIG LB port 1 release fifo error
58047     #define BTB_REG_INT_STS_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                           12
58048     #define BTB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR                                                 (0x1<<13) // Read packet client NIG main port 2 release fifo error
58049     #define BTB_REG_INT_STS_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                           13
58050     #define BTB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR                                                 (0x1<<14) // Read packet client NIG main port 2 release fifo error
58051     #define BTB_REG_INT_STS_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                           14
58052     #define BTB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR                                                 (0x1<<15) // Read packet client NIG main port 2 release fifo error
58053     #define BTB_REG_INT_STS_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                           15
58054     #define BTB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR                                                 (0x1<<16) // Read packet client NIG main port 2 release fifo error
58055     #define BTB_REG_INT_STS_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                           16
58056     #define BTB_REG_INT_STS_4_RC_PKT4_RLS_ERROR                                                      (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
58057     #define BTB_REG_INT_STS_4_RC_PKT4_RLS_ERROR_SHIFT                                                19
58058     #define BTB_REG_INT_STS_4_RC_PKT4_LEN_ERROR                                                      (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
58059     #define BTB_REG_INT_STS_4_RC_PKT4_LEN_ERROR_SHIFT                                                21
58060     #define BTB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR                                                 (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
58061     #define BTB_REG_INT_STS_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                           23
58062     #define BTB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR                                                (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58063     #define BTB_REG_INT_STS_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                          24
58064     #define BTB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR                                                 (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58065     #define BTB_REG_INT_STS_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                           25
58066     #define BTB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR                                                 (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58067     #define BTB_REG_INT_STS_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                           26
58068     #define BTB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                            (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58069     #define BTB_REG_INT_STS_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                      27
58070     #define BTB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                            (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58071     #define BTB_REG_INT_STS_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                      28
58072     #define BTB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                          (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58073     #define BTB_REG_INT_STS_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                    29
58074     #define BTB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR                                                 (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58075     #define BTB_REG_INT_STS_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                           30
58076     #define BTB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR                                                (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58077     #define BTB_REG_INT_STS_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                          31
58078 #define BTB_REG_INT_MASK_4                                                                           0xdb0124UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58079     #define BTB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR                                               (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT3_DSCR_FIFO_ERROR .
58080     #define BTB_REG_INT_MASK_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                         0
58081     #define BTB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_SOP_QUEUE_FIFO_ERROR .
58082     #define BTB_REG_INT_MASK_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                         4
58083     #define BTB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.LL_ARB_RLS_FIFO_ERROR .
58084     #define BTB_REG_INT_MASK_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                           7
58085     #define BTB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR                                            (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.LL_ARB_PREFETCH_FIFO_ERROR .
58086     #define BTB_REG_INT_MASK_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                      8
58087     #define BTB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT0_RLS_FIFO_ERROR .
58088     #define BTB_REG_INT_MASK_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                          9
58089     #define BTB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR                                                (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT1_RLS_FIFO_ERROR .
58090     #define BTB_REG_INT_MASK_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                          10
58091     #define BTB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR                                                (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT2_RLS_FIFO_ERROR .
58092     #define BTB_REG_INT_MASK_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                          11
58093     #define BTB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR                                                (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT3_RLS_FIFO_ERROR .
58094     #define BTB_REG_INT_MASK_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                          12
58095     #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_FIFO_ERROR .
58096     #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                          13
58097     #define BTB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR                                                (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT5_RLS_FIFO_ERROR .
58098     #define BTB_REG_INT_MASK_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                          14
58099     #define BTB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT6_RLS_FIFO_ERROR .
58100     #define BTB_REG_INT_MASK_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                          15
58101     #define BTB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT7_RLS_FIFO_ERROR .
58102     #define BTB_REG_INT_MASK_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                          16
58103     #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR                                                     (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_ERROR .
58104     #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_ERROR_SHIFT                                               19
58105     #define BTB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR                                                     (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_LEN_ERROR .
58106     #define BTB_REG_INT_MASK_4_RC_PKT4_LEN_ERROR_SHIFT                                               21
58107     #define BTB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_PROTOCOL_ERROR .
58108     #define BTB_REG_INT_MASK_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                          23
58109     #define BTB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR                                               (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_SIDE_FIFO_ERROR .
58110     #define BTB_REG_INT_MASK_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                         24
58111     #define BTB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR                                                (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_REQ_FIFO_ERROR .
58112     #define BTB_REG_INT_MASK_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                          25
58113     #define BTB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_BLK_FIFO_ERROR .
58114     #define BTB_REG_INT_MASK_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                          26
58115     #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                           (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RLS_LEFT_FIFO_ERROR .
58116     #define BTB_REG_INT_MASK_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                     27
58117     #define BTB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_STRT_PTR_FIFO_ERROR .
58118     #define BTB_REG_INT_MASK_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                     28
58119     #define BTB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                         (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_SECOND_PTR_FIFO_ERROR .
58120     #define BTB_REG_INT_MASK_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                   29
58121     #define BTB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR                                                (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_RSP_FIFO_ERROR .
58122     #define BTB_REG_INT_MASK_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                          30
58123     #define BTB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR                                               (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_4.RC_PKT4_DSCR_FIFO_ERROR .
58124     #define BTB_REG_INT_MASK_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                         31
58125 #define BTB_REG_INT_STS_WR_4                                                                         0xdb0128UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58126     #define BTB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR                                             (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58127     #define BTB_REG_INT_STS_WR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                       0
58128     #define BTB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR                                             (0x1<<4) // Read SOP client queue FIFO error.
58129     #define BTB_REG_INT_STS_WR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                       4
58130     #define BTB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR                                               (0x1<<7) // Link list arbiter release FIFO error.
58131     #define BTB_REG_INT_STS_WR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                         7
58132     #define BTB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR                                          (0x1<<8) // Link list arbiter prefetch FIFO error.
58133     #define BTB_REG_INT_STS_WR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                    8
58134     #define BTB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR                                              (0x1<<9) // Read packet client NIG main port 0 release fifo error
58135     #define BTB_REG_INT_STS_WR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                        9
58136     #define BTB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR                                              (0x1<<10) // Read packet client NIG LB port 0 release fifo error
58137     #define BTB_REG_INT_STS_WR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                        10
58138     #define BTB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR                                              (0x1<<11) // Read packet client NIG main port 1 release fifo error
58139     #define BTB_REG_INT_STS_WR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                        11
58140     #define BTB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR                                              (0x1<<12) // Read packet client NIG LB port 1 release fifo error
58141     #define BTB_REG_INT_STS_WR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                        12
58142     #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR                                              (0x1<<13) // Read packet client NIG main port 2 release fifo error
58143     #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                        13
58144     #define BTB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR                                              (0x1<<14) // Read packet client NIG main port 2 release fifo error
58145     #define BTB_REG_INT_STS_WR_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                        14
58146     #define BTB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR                                              (0x1<<15) // Read packet client NIG main port 2 release fifo error
58147     #define BTB_REG_INT_STS_WR_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                        15
58148     #define BTB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR                                              (0x1<<16) // Read packet client NIG main port 2 release fifo error
58149     #define BTB_REG_INT_STS_WR_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                        16
58150     #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR                                                   (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
58151     #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_ERROR_SHIFT                                             19
58152     #define BTB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR                                                   (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
58153     #define BTB_REG_INT_STS_WR_4_RC_PKT4_LEN_ERROR_SHIFT                                             21
58154     #define BTB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR                                              (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
58155     #define BTB_REG_INT_STS_WR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                        23
58156     #define BTB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR                                             (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58157     #define BTB_REG_INT_STS_WR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                       24
58158     #define BTB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR                                              (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58159     #define BTB_REG_INT_STS_WR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                        25
58160     #define BTB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR                                              (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58161     #define BTB_REG_INT_STS_WR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                        26
58162     #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                         (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58163     #define BTB_REG_INT_STS_WR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                   27
58164     #define BTB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                         (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58165     #define BTB_REG_INT_STS_WR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                   28
58166     #define BTB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                       (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58167     #define BTB_REG_INT_STS_WR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                 29
58168     #define BTB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR                                              (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58169     #define BTB_REG_INT_STS_WR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                        30
58170     #define BTB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR                                             (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58171     #define BTB_REG_INT_STS_WR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                       31
58172 #define BTB_REG_INT_STS_CLR_4                                                                        0xdb012cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58173     #define BTB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR                                            (0x1<<0) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58174     #define BTB_REG_INT_STS_CLR_4_RC_PKT3_DSCR_FIFO_ERROR_SHIFT                                      0
58175     #define BTB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR                                            (0x1<<4) // Read SOP client queue FIFO error.
58176     #define BTB_REG_INT_STS_CLR_4_RC_SOP_QUEUE_FIFO_ERROR_SHIFT                                      4
58177     #define BTB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR                                              (0x1<<7) // Link list arbiter release FIFO error.
58178     #define BTB_REG_INT_STS_CLR_4_LL_ARB_RLS_FIFO_ERROR_SHIFT                                        7
58179     #define BTB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR                                         (0x1<<8) // Link list arbiter prefetch FIFO error.
58180     #define BTB_REG_INT_STS_CLR_4_LL_ARB_PREFETCH_FIFO_ERROR_SHIFT                                   8
58181     #define BTB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR                                             (0x1<<9) // Read packet client NIG main port 0 release fifo error
58182     #define BTB_REG_INT_STS_CLR_4_RC_PKT0_RLS_FIFO_ERROR_SHIFT                                       9
58183     #define BTB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR                                             (0x1<<10) // Read packet client NIG LB port 0 release fifo error
58184     #define BTB_REG_INT_STS_CLR_4_RC_PKT1_RLS_FIFO_ERROR_SHIFT                                       10
58185     #define BTB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR                                             (0x1<<11) // Read packet client NIG main port 1 release fifo error
58186     #define BTB_REG_INT_STS_CLR_4_RC_PKT2_RLS_FIFO_ERROR_SHIFT                                       11
58187     #define BTB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR                                             (0x1<<12) // Read packet client NIG LB port 1 release fifo error
58188     #define BTB_REG_INT_STS_CLR_4_RC_PKT3_RLS_FIFO_ERROR_SHIFT                                       12
58189     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR                                             (0x1<<13) // Read packet client NIG main port 2 release fifo error
58190     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_FIFO_ERROR_SHIFT                                       13
58191     #define BTB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR                                             (0x1<<14) // Read packet client NIG main port 2 release fifo error
58192     #define BTB_REG_INT_STS_CLR_4_RC_PKT5_RLS_FIFO_ERROR_SHIFT                                       14
58193     #define BTB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR                                             (0x1<<15) // Read packet client NIG main port 2 release fifo error
58194     #define BTB_REG_INT_STS_CLR_4_RC_PKT6_RLS_FIFO_ERROR_SHIFT                                       15
58195     #define BTB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR                                             (0x1<<16) // Read packet client NIG main port 2 release fifo error
58196     #define BTB_REG_INT_STS_CLR_4_RC_PKT7_RLS_FIFO_ERROR_SHIFT                                       16
58197     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR                                                  (0x1<<19) // Read packet client NIG LB port 1 release error when number of requested packet copies is bigger than real number of packet copies::s/RC_PKT_DSCR3/parser/g in Comments.
58198     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_ERROR_SHIFT                                            19
58199     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR                                                  (0x1<<21) // Read packet client NIG LB port 1 length error when requested packet length is bigger than real packet length::s/RC_PKT_DSCR3/parser/g in Comments.
58200     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_LEN_ERROR_SHIFT                                            21
58201     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR                                             (0x1<<23) // Read packet client NIG LB port 1 error when packet doesn't have SOP or EOP on read response interface::s/RC_PKT_DSCR3/parser/g in Comments.
58202     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_PROTOCOL_ERROR_SHIFT                                       23
58203     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR                                            (0x1<<24) // Read packet client NIG LB port 1 side info FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58204     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SIDE_FIFO_ERROR_SHIFT                                      24
58205     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR                                             (0x1<<25) // Read packet client NIG LB port 1 request FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58206     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_REQ_FIFO_ERROR_SHIFT                                       25
58207     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR                                             (0x1<<26) // Read packet client NIG LB port 1 block FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58208     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_BLK_FIFO_ERROR_SHIFT                                       26
58209     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR                                        (0x1<<27) // Read packet client NIG LB port 1 releases left FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58210     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RLS_LEFT_FIFO_ERROR_SHIFT                                  27
58211     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR                                        (0x1<<28) // Read packet client NIG LB port 1 start pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58212     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_STRT_PTR_FIFO_ERROR_SHIFT                                  28
58213     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR                                      (0x1<<29) // Read packet client NIG LB port 1 second pointer FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58214     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_SECOND_PTR_FIFO_ERROR_SHIFT                                29
58215     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR                                             (0x1<<30) // Read packet client NIG LB port 1 response FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58216     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_RSP_FIFO_ERROR_SHIFT                                       30
58217     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR                                            (0x1<<31) // Read packet client NIG LB port 1 descriptor FIFO error ::s/RC_PKT_DSCR3/parser/g in Comments.
58218     #define BTB_REG_INT_STS_CLR_4_RC_PKT4_DSCR_FIFO_ERROR_SHIFT                                      31
58219 #define BTB_REG_INT_STS_5                                                                            0xdb0138UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58220     #define BTB_REG_INT_STS_5_RC_PKT5_RLS_ERROR                                                      (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
58221     #define BTB_REG_INT_STS_5_RC_PKT5_RLS_ERROR_SHIFT                                                0
58222     #define BTB_REG_INT_STS_5_RC_PKT5_LEN_ERROR                                                      (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
58223     #define BTB_REG_INT_STS_5_RC_PKT5_LEN_ERROR_SHIFT                                                1
58224     #define BTB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR                                                 (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
58225     #define BTB_REG_INT_STS_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                           2
58226     #define BTB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR                                                (0x1<<3) // Read packet client5 side info FIFO error
58227     #define BTB_REG_INT_STS_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                          3
58228     #define BTB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR                                                 (0x1<<4) // Read packet client5 request FIFO error
58229     #define BTB_REG_INT_STS_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                           4
58230     #define BTB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR                                                 (0x1<<5) // Read packet client5 block FIFO error
58231     #define BTB_REG_INT_STS_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                           5
58232     #define BTB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                            (0x1<<6) // Read packet client5 releases left FIFO error
58233     #define BTB_REG_INT_STS_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                      6
58234     #define BTB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                            (0x1<<7) // Read packet client5 start pointer FIFO error
58235     #define BTB_REG_INT_STS_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                      7
58236     #define BTB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                          (0x1<<8) // Read packet client5 second pointer FIFO
58237     #define BTB_REG_INT_STS_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                    8
58238     #define BTB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR                                                 (0x1<<9) // Read packet client5 response FIFO error
58239     #define BTB_REG_INT_STS_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                           9
58240     #define BTB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR                                                (0x1<<10) // Read packet client5 descriptor FIFO error
58241     #define BTB_REG_INT_STS_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                          10
58242     #define BTB_REG_INT_STS_5_RC_PKT6_RLS_ERROR                                                      (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
58243     #define BTB_REG_INT_STS_5_RC_PKT6_RLS_ERROR_SHIFT                                                11
58244     #define BTB_REG_INT_STS_5_RC_PKT6_LEN_ERROR                                                      (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
58245     #define BTB_REG_INT_STS_5_RC_PKT6_LEN_ERROR_SHIFT                                                12
58246     #define BTB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR                                                 (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
58247     #define BTB_REG_INT_STS_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                           13
58248     #define BTB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR                                                (0x1<<14) // Read packet client6 side info FIFO error
58249     #define BTB_REG_INT_STS_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                          14
58250     #define BTB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR                                                 (0x1<<15) // Read packet client6 request FIFO error
58251     #define BTB_REG_INT_STS_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                           15
58252     #define BTB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR                                                 (0x1<<16) // Read packet client6 block FIFO error
58253     #define BTB_REG_INT_STS_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                           16
58254     #define BTB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                            (0x1<<17) // Read packet client6 releases left FIFO error
58255     #define BTB_REG_INT_STS_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                      17
58256     #define BTB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                            (0x1<<18) // Read packet client6 start pointer FIFO error
58257     #define BTB_REG_INT_STS_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                      18
58258     #define BTB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                          (0x1<<19) // Read packet client6 second pointer FIFO
58259     #define BTB_REG_INT_STS_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                    19
58260     #define BTB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR                                                 (0x1<<20) // Read packet client6 response FIFO error
58261     #define BTB_REG_INT_STS_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                           20
58262     #define BTB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR                                                (0x1<<21) // Read packet client6 descriptor FIFO error
58263     #define BTB_REG_INT_STS_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                          21
58264     #define BTB_REG_INT_STS_5_RC_PKT7_RLS_ERROR                                                      (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
58265     #define BTB_REG_INT_STS_5_RC_PKT7_RLS_ERROR_SHIFT                                                22
58266     #define BTB_REG_INT_STS_5_RC_PKT7_LEN_ERROR                                                      (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
58267     #define BTB_REG_INT_STS_5_RC_PKT7_LEN_ERROR_SHIFT                                                23
58268     #define BTB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR                                                 (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
58269     #define BTB_REG_INT_STS_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                           24
58270     #define BTB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR                                                (0x1<<25) // Read packet client7 side info FIFO error
58271     #define BTB_REG_INT_STS_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                          25
58272     #define BTB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR                                                 (0x1<<26) // Read packet client7 request FIFO error
58273     #define BTB_REG_INT_STS_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                           26
58274     #define BTB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR                                                 (0x1<<27) // Read packet client7 block FIFO error
58275     #define BTB_REG_INT_STS_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                           27
58276     #define BTB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                            (0x1<<28) // Read packet client7 releases left FIFO error
58277     #define BTB_REG_INT_STS_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                      28
58278     #define BTB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                            (0x1<<29) // Read packet client7 start pointer FIFO error
58279     #define BTB_REG_INT_STS_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                      29
58280     #define BTB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                          (0x1<<30) // Read packet client7 second pointer FIFO
58281     #define BTB_REG_INT_STS_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                    30
58282     #define BTB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR                                                 (0x1<<31) // Read packet client7 response FIFO error
58283     #define BTB_REG_INT_STS_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                           31
58284 #define BTB_REG_INT_MASK_5                                                                           0xdb013cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58285     #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RLS_ERROR .
58286     #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_ERROR_SHIFT                                               0
58287     #define BTB_REG_INT_MASK_5_RC_PKT5_LEN_ERROR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_LEN_ERROR .
58288     #define BTB_REG_INT_MASK_5_RC_PKT5_LEN_ERROR_SHIFT                                               1
58289     #define BTB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR                                                (0x1<<2) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_PROTOCOL_ERROR .
58290     #define BTB_REG_INT_MASK_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                          2
58291     #define BTB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_SIDE_FIFO_ERROR .
58292     #define BTB_REG_INT_MASK_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                         3
58293     #define BTB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_REQ_FIFO_ERROR .
58294     #define BTB_REG_INT_MASK_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                          4
58295     #define BTB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_BLK_FIFO_ERROR .
58296     #define BTB_REG_INT_MASK_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                          5
58297     #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                           (0x1<<6) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RLS_LEFT_FIFO_ERROR .
58298     #define BTB_REG_INT_MASK_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                     6
58299     #define BTB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                           (0x1<<7) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_STRT_PTR_FIFO_ERROR .
58300     #define BTB_REG_INT_MASK_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                     7
58301     #define BTB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                         (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_SECOND_PTR_FIFO_ERROR .
58302     #define BTB_REG_INT_MASK_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                   8
58303     #define BTB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_RSP_FIFO_ERROR .
58304     #define BTB_REG_INT_MASK_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                          9
58305     #define BTB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR                                               (0x1<<10) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT5_DSCR_FIFO_ERROR .
58306     #define BTB_REG_INT_MASK_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                         10
58307     #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RLS_ERROR .
58308     #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_ERROR_SHIFT                                               11
58309     #define BTB_REG_INT_MASK_5_RC_PKT6_LEN_ERROR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_LEN_ERROR .
58310     #define BTB_REG_INT_MASK_5_RC_PKT6_LEN_ERROR_SHIFT                                               12
58311     #define BTB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR                                                (0x1<<13) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_PROTOCOL_ERROR .
58312     #define BTB_REG_INT_MASK_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                          13
58313     #define BTB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR                                               (0x1<<14) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_SIDE_FIFO_ERROR .
58314     #define BTB_REG_INT_MASK_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                         14
58315     #define BTB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR                                                (0x1<<15) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_REQ_FIFO_ERROR .
58316     #define BTB_REG_INT_MASK_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                          15
58317     #define BTB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR                                                (0x1<<16) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_BLK_FIFO_ERROR .
58318     #define BTB_REG_INT_MASK_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                          16
58319     #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                           (0x1<<17) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RLS_LEFT_FIFO_ERROR .
58320     #define BTB_REG_INT_MASK_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                     17
58321     #define BTB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                           (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_STRT_PTR_FIFO_ERROR .
58322     #define BTB_REG_INT_MASK_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                     18
58323     #define BTB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_SECOND_PTR_FIFO_ERROR .
58324     #define BTB_REG_INT_MASK_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                   19
58325     #define BTB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR                                                (0x1<<20) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_RSP_FIFO_ERROR .
58326     #define BTB_REG_INT_MASK_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                          20
58327     #define BTB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR                                               (0x1<<21) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT6_DSCR_FIFO_ERROR .
58328     #define BTB_REG_INT_MASK_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                         21
58329     #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR                                                     (0x1<<22) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RLS_ERROR .
58330     #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_ERROR_SHIFT                                               22
58331     #define BTB_REG_INT_MASK_5_RC_PKT7_LEN_ERROR                                                     (0x1<<23) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_LEN_ERROR .
58332     #define BTB_REG_INT_MASK_5_RC_PKT7_LEN_ERROR_SHIFT                                               23
58333     #define BTB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR                                                (0x1<<24) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_PROTOCOL_ERROR .
58334     #define BTB_REG_INT_MASK_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                          24
58335     #define BTB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_SIDE_FIFO_ERROR .
58336     #define BTB_REG_INT_MASK_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                         25
58337     #define BTB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_REQ_FIFO_ERROR .
58338     #define BTB_REG_INT_MASK_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                          26
58339     #define BTB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR                                                (0x1<<27) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_BLK_FIFO_ERROR .
58340     #define BTB_REG_INT_MASK_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                          27
58341     #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                           (0x1<<28) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RLS_LEFT_FIFO_ERROR .
58342     #define BTB_REG_INT_MASK_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                     28
58343     #define BTB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                           (0x1<<29) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_STRT_PTR_FIFO_ERROR .
58344     #define BTB_REG_INT_MASK_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                     29
58345     #define BTB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                         (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_SECOND_PTR_FIFO_ERROR .
58346     #define BTB_REG_INT_MASK_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                   30
58347     #define BTB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR                                                (0x1<<31) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_5.RC_PKT7_RSP_FIFO_ERROR .
58348     #define BTB_REG_INT_MASK_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                          31
58349 #define BTB_REG_INT_STS_WR_5                                                                         0xdb0140UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58350     #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR                                                   (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
58351     #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_ERROR_SHIFT                                             0
58352     #define BTB_REG_INT_STS_WR_5_RC_PKT5_LEN_ERROR                                                   (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
58353     #define BTB_REG_INT_STS_WR_5_RC_PKT5_LEN_ERROR_SHIFT                                             1
58354     #define BTB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR                                              (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
58355     #define BTB_REG_INT_STS_WR_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                        2
58356     #define BTB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR                                             (0x1<<3) // Read packet client5 side info FIFO error
58357     #define BTB_REG_INT_STS_WR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                       3
58358     #define BTB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR                                              (0x1<<4) // Read packet client5 request FIFO error
58359     #define BTB_REG_INT_STS_WR_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                        4
58360     #define BTB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR                                              (0x1<<5) // Read packet client5 block FIFO error
58361     #define BTB_REG_INT_STS_WR_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                        5
58362     #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                         (0x1<<6) // Read packet client5 releases left FIFO error
58363     #define BTB_REG_INT_STS_WR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                   6
58364     #define BTB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                         (0x1<<7) // Read packet client5 start pointer FIFO error
58365     #define BTB_REG_INT_STS_WR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                   7
58366     #define BTB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                       (0x1<<8) // Read packet client5 second pointer FIFO
58367     #define BTB_REG_INT_STS_WR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                 8
58368     #define BTB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR                                              (0x1<<9) // Read packet client5 response FIFO error
58369     #define BTB_REG_INT_STS_WR_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                        9
58370     #define BTB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR                                             (0x1<<10) // Read packet client5 descriptor FIFO error
58371     #define BTB_REG_INT_STS_WR_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                       10
58372     #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR                                                   (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
58373     #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_ERROR_SHIFT                                             11
58374     #define BTB_REG_INT_STS_WR_5_RC_PKT6_LEN_ERROR                                                   (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
58375     #define BTB_REG_INT_STS_WR_5_RC_PKT6_LEN_ERROR_SHIFT                                             12
58376     #define BTB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR                                              (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
58377     #define BTB_REG_INT_STS_WR_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                        13
58378     #define BTB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR                                             (0x1<<14) // Read packet client6 side info FIFO error
58379     #define BTB_REG_INT_STS_WR_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                       14
58380     #define BTB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR                                              (0x1<<15) // Read packet client6 request FIFO error
58381     #define BTB_REG_INT_STS_WR_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                        15
58382     #define BTB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR                                              (0x1<<16) // Read packet client6 block FIFO error
58383     #define BTB_REG_INT_STS_WR_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                        16
58384     #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                         (0x1<<17) // Read packet client6 releases left FIFO error
58385     #define BTB_REG_INT_STS_WR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                   17
58386     #define BTB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                         (0x1<<18) // Read packet client6 start pointer FIFO error
58387     #define BTB_REG_INT_STS_WR_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                   18
58388     #define BTB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                       (0x1<<19) // Read packet client6 second pointer FIFO
58389     #define BTB_REG_INT_STS_WR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                 19
58390     #define BTB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR                                              (0x1<<20) // Read packet client6 response FIFO error
58391     #define BTB_REG_INT_STS_WR_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                        20
58392     #define BTB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR                                             (0x1<<21) // Read packet client6 descriptor FIFO error
58393     #define BTB_REG_INT_STS_WR_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                       21
58394     #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR                                                   (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
58395     #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_ERROR_SHIFT                                             22
58396     #define BTB_REG_INT_STS_WR_5_RC_PKT7_LEN_ERROR                                                   (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
58397     #define BTB_REG_INT_STS_WR_5_RC_PKT7_LEN_ERROR_SHIFT                                             23
58398     #define BTB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR                                              (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
58399     #define BTB_REG_INT_STS_WR_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                        24
58400     #define BTB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR                                             (0x1<<25) // Read packet client7 side info FIFO error
58401     #define BTB_REG_INT_STS_WR_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                       25
58402     #define BTB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR                                              (0x1<<26) // Read packet client7 request FIFO error
58403     #define BTB_REG_INT_STS_WR_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                        26
58404     #define BTB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR                                              (0x1<<27) // Read packet client7 block FIFO error
58405     #define BTB_REG_INT_STS_WR_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                        27
58406     #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                         (0x1<<28) // Read packet client7 releases left FIFO error
58407     #define BTB_REG_INT_STS_WR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                   28
58408     #define BTB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                         (0x1<<29) // Read packet client7 start pointer FIFO error
58409     #define BTB_REG_INT_STS_WR_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                   29
58410     #define BTB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                       (0x1<<30) // Read packet client7 second pointer FIFO
58411     #define BTB_REG_INT_STS_WR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                 30
58412     #define BTB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR                                              (0x1<<31) // Read packet client7 response FIFO error
58413     #define BTB_REG_INT_STS_WR_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                        31
58414 #define BTB_REG_INT_STS_CLR_5                                                                        0xdb0144UL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58415     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR                                                  (0x1<<0) // Read packet client5 error when number of requested packet copies is bigger than real number of packet copies
58416     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_ERROR_SHIFT                                            0
58417     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_LEN_ERROR                                                  (0x1<<1) // Read packet client5 length error when requested packet length is bigger than real packet length
58418     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_LEN_ERROR_SHIFT                                            1
58419     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR                                             (0x1<<2) // Read packet client5 error when packet doesn't have SOP or EOP on read response
58420     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_PROTOCOL_ERROR_SHIFT                                       2
58421     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR                                            (0x1<<3) // Read packet client5 side info FIFO error
58422     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SIDE_FIFO_ERROR_SHIFT                                      3
58423     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR                                             (0x1<<4) // Read packet client5 request FIFO error
58424     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_REQ_FIFO_ERROR_SHIFT                                       4
58425     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR                                             (0x1<<5) // Read packet client5 block FIFO error
58426     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_BLK_FIFO_ERROR_SHIFT                                       5
58427     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR                                        (0x1<<6) // Read packet client5 releases left FIFO error
58428     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RLS_LEFT_FIFO_ERROR_SHIFT                                  6
58429     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR                                        (0x1<<7) // Read packet client5 start pointer FIFO error
58430     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_STRT_PTR_FIFO_ERROR_SHIFT                                  7
58431     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR                                      (0x1<<8) // Read packet client5 second pointer FIFO
58432     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_SECOND_PTR_FIFO_ERROR_SHIFT                                8
58433     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR                                             (0x1<<9) // Read packet client5 response FIFO error
58434     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_RSP_FIFO_ERROR_SHIFT                                       9
58435     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR                                            (0x1<<10) // Read packet client5 descriptor FIFO error
58436     #define BTB_REG_INT_STS_CLR_5_RC_PKT5_DSCR_FIFO_ERROR_SHIFT                                      10
58437     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR                                                  (0x1<<11) // Read packet client6 error when number of requested packet copies is bigger than real number of packet copies
58438     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_ERROR_SHIFT                                            11
58439     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_LEN_ERROR                                                  (0x1<<12) // Read packet client6 length error when requested packet length is bigger than real packet length
58440     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_LEN_ERROR_SHIFT                                            12
58441     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR                                             (0x1<<13) // Read packet client6 error when packet doesn't have SOP or EOP on read response
58442     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_PROTOCOL_ERROR_SHIFT                                       13
58443     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR                                            (0x1<<14) // Read packet client6 side info FIFO error
58444     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SIDE_FIFO_ERROR_SHIFT                                      14
58445     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR                                             (0x1<<15) // Read packet client6 request FIFO error
58446     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_REQ_FIFO_ERROR_SHIFT                                       15
58447     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR                                             (0x1<<16) // Read packet client6 block FIFO error
58448     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_BLK_FIFO_ERROR_SHIFT                                       16
58449     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR                                        (0x1<<17) // Read packet client6 releases left FIFO error
58450     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RLS_LEFT_FIFO_ERROR_SHIFT                                  17
58451     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR                                        (0x1<<18) // Read packet client6 start pointer FIFO error
58452     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_STRT_PTR_FIFO_ERROR_SHIFT                                  18
58453     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR                                      (0x1<<19) // Read packet client6 second pointer FIFO
58454     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_SECOND_PTR_FIFO_ERROR_SHIFT                                19
58455     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR                                             (0x1<<20) // Read packet client6 response FIFO error
58456     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_RSP_FIFO_ERROR_SHIFT                                       20
58457     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR                                            (0x1<<21) // Read packet client6 descriptor FIFO error
58458     #define BTB_REG_INT_STS_CLR_5_RC_PKT6_DSCR_FIFO_ERROR_SHIFT                                      21
58459     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR                                                  (0x1<<22) // Read packet client7 error when number of requested packet copies is bigger than real number of packet copies
58460     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_ERROR_SHIFT                                            22
58461     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_LEN_ERROR                                                  (0x1<<23) // Read packet client7 length error when requested packet length is bigger than real packet length
58462     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_LEN_ERROR_SHIFT                                            23
58463     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR                                             (0x1<<24) // Read packet client7 error when packet doesn't have SOP or EOP on read response
58464     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_PROTOCOL_ERROR_SHIFT                                       24
58465     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR                                            (0x1<<25) // Read packet client7 side info FIFO error
58466     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SIDE_FIFO_ERROR_SHIFT                                      25
58467     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR                                             (0x1<<26) // Read packet client7 request FIFO error
58468     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_REQ_FIFO_ERROR_SHIFT                                       26
58469     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR                                             (0x1<<27) // Read packet client7 block FIFO error
58470     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_BLK_FIFO_ERROR_SHIFT                                       27
58471     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR                                        (0x1<<28) // Read packet client7 releases left FIFO error
58472     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RLS_LEFT_FIFO_ERROR_SHIFT                                  28
58473     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR                                        (0x1<<29) // Read packet client7 start pointer FIFO error
58474     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_STRT_PTR_FIFO_ERROR_SHIFT                                  29
58475     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR                                      (0x1<<30) // Read packet client7 second pointer FIFO
58476     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_SECOND_PTR_FIFO_ERROR_SHIFT                                30
58477     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR                                             (0x1<<31) // Read packet client7 response FIFO error
58478     #define BTB_REG_INT_STS_CLR_5_RC_PKT7_RSP_FIFO_ERROR_SHIFT                                       31
58479 #define BTB_REG_INT_STS_6                                                                            0xdb0150UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58480     #define BTB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                  (0x1<<0) // Packet available SYNC FIFO error
58481     #define BTB_REG_INT_STS_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                            0
58482 #define BTB_REG_INT_MASK_6                                                                           0xdb0154UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58483     #define BTB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_6.PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR .
58484     #define BTB_REG_INT_MASK_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                           0
58485 #define BTB_REG_INT_STS_WR_6                                                                         0xdb0158UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58486     #define BTB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                               (0x1<<0) // Packet available SYNC FIFO error
58487     #define BTB_REG_INT_STS_WR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                         0
58488 #define BTB_REG_INT_STS_CLR_6                                                                        0xdb015cUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58489     #define BTB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR                              (0x1<<0) // Packet available SYNC FIFO error
58490     #define BTB_REG_INT_STS_CLR_6_PACKET_AVAILABLE_SYNC_FIFO_PUSH_ERROR_SHIFT                        0
58491 #define BTB_REG_INT_STS_8                                                                            0xdb0184UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58492     #define BTB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR                                                  (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
58493     #define BTB_REG_INT_STS_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                            0
58494 #define BTB_REG_INT_MASK_8                                                                           0xdb0188UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58495     #define BTB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR                                                 (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_8.WC6_NOTIFY_FIFO_ERROR .
58496     #define BTB_REG_INT_MASK_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                           0
58497 #define BTB_REG_INT_STS_WR_8                                                                         0xdb018cUL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58498     #define BTB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR                                               (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
58499     #define BTB_REG_INT_STS_WR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                         0
58500 #define BTB_REG_INT_STS_CLR_8                                                                        0xdb0190UL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58501     #define BTB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR                                              (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Notify FIFO error in write client 6
58502     #define BTB_REG_INT_STS_CLR_8_WC6_NOTIFY_FIFO_ERROR_SHIFT                                        0
58503 #define BTB_REG_INT_STS_9                                                                            0xdb019cUL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58504     #define BTB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR                                                   (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
58505     #define BTB_REG_INT_STS_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                             0
58506 #define BTB_REG_INT_MASK_9                                                                           0xdb01a0UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58507     #define BTB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_9.WC9_QUEUE_FIFO_ERROR .
58508     #define BTB_REG_INT_MASK_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                            0
58509 #define BTB_REG_INT_STS_WR_9                                                                         0xdb01a4UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58510     #define BTB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR                                                (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
58511     #define BTB_REG_INT_STS_WR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                          0
58512 #define BTB_REG_INT_STS_CLR_9                                                                        0xdb01a8UL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58513     #define BTB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR                                               (0x1<<0) // Warning! Check this bit connection for E4 A0 in RTL. Queue FIFO error in write client 9
58514     #define BTB_REG_INT_STS_CLR_9_WC9_QUEUE_FIFO_ERROR_SHIFT                                         0
58515 #define BTB_REG_INT_STS_10                                                                           0xdb01b4UL //Access:R    DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58516     #define BTB_REG_INT_STS_10_WC0_SYNC_FIFO_PUSH_ERROR                                              (0x1<<30) // WC input SYNC FIFO error
58517     #define BTB_REG_INT_STS_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT                                        30
58518 #define BTB_REG_INT_MASK_10                                                                          0xdb01b8UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58519     #define BTB_REG_INT_MASK_10_WC0_SYNC_FIFO_PUSH_ERROR                                             (0x1<<30) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_10.WC0_SYNC_FIFO_PUSH_ERROR .
58520     #define BTB_REG_INT_MASK_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT                                       30
58521 #define BTB_REG_INT_STS_WR_10                                                                        0xdb01bcUL //Access:WR   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58522     #define BTB_REG_INT_STS_WR_10_WC0_SYNC_FIFO_PUSH_ERROR                                           (0x1<<30) // WC input SYNC FIFO error
58523     #define BTB_REG_INT_STS_WR_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT                                     30
58524 #define BTB_REG_INT_STS_CLR_10                                                                       0xdb01c0UL //Access:RC   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58525     #define BTB_REG_INT_STS_CLR_10_WC0_SYNC_FIFO_PUSH_ERROR                                          (0x1<<30) // WC input SYNC FIFO error
58526     #define BTB_REG_INT_STS_CLR_10_WC0_SYNC_FIFO_PUSH_ERROR_SHIFT                                    30
58527 #define BTB_REG_INT_STS_11                                                                           0xdb01ccUL //Access:R    DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58528     #define BTB_REG_INT_STS_11_RLS_SYNC_FIFO_PUSH_ERROR                                              (0x1<<8) // Release SYNC FIFO error
58529     #define BTB_REG_INT_STS_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT                                        8
58530     #define BTB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR                                               (0x1<<18) // Read packet client7 descriptor FIFO error
58531     #define BTB_REG_INT_STS_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                         18
58532 #define BTB_REG_INT_MASK_11                                                                          0xdb01d0UL //Access:RW   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58533     #define BTB_REG_INT_MASK_11_RLS_SYNC_FIFO_PUSH_ERROR                                             (0x1<<8) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_11.RLS_SYNC_FIFO_PUSH_ERROR .
58534     #define BTB_REG_INT_MASK_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT                                       8
58535     #define BTB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR                                              (0x1<<18) // This bit masks, when set, the Interrupt bit: BTB_REG_INT_STS_11.RC_PKT7_DSCR_FIFO_ERROR .
58536     #define BTB_REG_INT_MASK_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                        18
58537 #define BTB_REG_INT_STS_WR_11                                                                        0xdb01d4UL //Access:WR   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58538     #define BTB_REG_INT_STS_WR_11_RLS_SYNC_FIFO_PUSH_ERROR                                           (0x1<<8) // Release SYNC FIFO error
58539     #define BTB_REG_INT_STS_WR_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT                                     8
58540     #define BTB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR                                            (0x1<<18) // Read packet client7 descriptor FIFO error
58541     #define BTB_REG_INT_STS_WR_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                      18
58542 #define BTB_REG_INT_STS_CLR_11                                                                       0xdb01d8UL //Access:RC   DataWidth:0x13  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58543     #define BTB_REG_INT_STS_CLR_11_RLS_SYNC_FIFO_PUSH_ERROR                                          (0x1<<8) // Release SYNC FIFO error
58544     #define BTB_REG_INT_STS_CLR_11_RLS_SYNC_FIFO_PUSH_ERROR_SHIFT                                    8
58545     #define BTB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR                                           (0x1<<18) // Read packet client7 descriptor FIFO error
58546     #define BTB_REG_INT_STS_CLR_11_RC_PKT7_DSCR_FIFO_ERROR_SHIFT                                     18
58547 #define BTB_REG_PRTY_MASK                                                                            0xdb01e0UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_B0 K2
58548     #define BTB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY                                                      (0x1<<0) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK0_MEM_PRTY .
58549     #define BTB_REG_PRTY_MASK_LL_BANK0_MEM_PRTY_SHIFT                                                0
58550     #define BTB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY                                                      (0x1<<1) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK1_MEM_PRTY .
58551     #define BTB_REG_PRTY_MASK_LL_BANK1_MEM_PRTY_SHIFT                                                1
58552     #define BTB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY                                                      (0x1<<2) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK2_MEM_PRTY .
58553     #define BTB_REG_PRTY_MASK_LL_BANK2_MEM_PRTY_SHIFT                                                2
58554     #define BTB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY                                                      (0x1<<3) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.LL_BANK3_MEM_PRTY .
58555     #define BTB_REG_PRTY_MASK_LL_BANK3_MEM_PRTY_SHIFT                                                3
58556     #define BTB_REG_PRTY_MASK_DATAPATH_REGISTERS                                                     (0x1<<4) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS.DATAPATH_REGISTERS .
58557     #define BTB_REG_PRTY_MASK_DATAPATH_REGISTERS_SHIFT                                               4
58558 #define BTB_REG_PRTY_MASK_H_0                                                                        0xdb0404UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58559     #define BTB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
58560     #define BTB_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                          0
58561     #define BTB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
58562     #define BTB_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT                                          1
58563     #define BTB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT                                                (0x1<<2) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM009_I_ECC_RF_INT .
58564     #define BTB_REG_PRTY_MASK_H_0_MEM009_I_ECC_RF_INT_SHIFT                                          2
58565     #define BTB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT                                                (0x1<<3) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM010_I_ECC_RF_INT .
58566     #define BTB_REG_PRTY_MASK_H_0_MEM010_I_ECC_RF_INT_SHIFT                                          3
58567     #define BTB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT                                                (0x1<<4) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
58568     #define BTB_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_SHIFT                                          4
58569     #define BTB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
58570     #define BTB_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_SHIFT                                          5
58571     #define BTB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT                                                (0x1<<6) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM013_I_ECC_RF_INT .
58572     #define BTB_REG_PRTY_MASK_H_0_MEM013_I_ECC_RF_INT_SHIFT                                          6
58573     #define BTB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT                                                (0x1<<7) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM014_I_ECC_RF_INT .
58574     #define BTB_REG_PRTY_MASK_H_0_MEM014_I_ECC_RF_INT_SHIFT                                          7
58575     #define BTB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT                                                (0x1<<8) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM015_I_ECC_RF_INT .
58576     #define BTB_REG_PRTY_MASK_H_0_MEM015_I_ECC_RF_INT_SHIFT                                          8
58577     #define BTB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT                                                (0x1<<9) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM016_I_ECC_RF_INT .
58578     #define BTB_REG_PRTY_MASK_H_0_MEM016_I_ECC_RF_INT_SHIFT                                          9
58579     #define BTB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT                                                (0x1<<10) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM002_I_ECC_RF_INT .
58580     #define BTB_REG_PRTY_MASK_H_0_MEM002_I_ECC_RF_INT_SHIFT                                          10
58581     #define BTB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT                                                (0x1<<11) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
58582     #define BTB_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT                                          11
58583     #define BTB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                                (0x1<<12) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
58584     #define BTB_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                          12
58585     #define BTB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT                                                (0x1<<13) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM005_I_ECC_RF_INT .
58586     #define BTB_REG_PRTY_MASK_H_0_MEM005_I_ECC_RF_INT_SHIFT                                          13
58587     #define BTB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT                                                (0x1<<14) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
58588     #define BTB_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_SHIFT                                          14
58589     #define BTB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT                                                (0x1<<15) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM007_I_ECC_RF_INT .
58590     #define BTB_REG_PRTY_MASK_H_0_MEM007_I_ECC_RF_INT_SHIFT                                          15
58591     #define BTB_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
58592     #define BTB_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_SHIFT                                            16
58593     #define BTB_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
58594     #define BTB_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_SHIFT                                            17
58595     #define BTB_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
58596     #define BTB_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_SHIFT                                            18
58597     #define BTB_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY                                                  (0x1<<19) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
58598     #define BTB_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_SHIFT                                            19
58599     #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
58600     #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_A0_SHIFT                                      17
58601     #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
58602     #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_B0_SHIFT                                      17
58603     #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2                                               (0x1<<20) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
58604     #define BTB_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_SHIFT                                         20
58605     #define BTB_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
58606     #define BTB_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                            21
58607     #define BTB_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
58608     #define BTB_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_SHIFT                                            22
58609     #define BTB_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
58610     #define BTB_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_SHIFT                                            23
58611     #define BTB_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
58612     #define BTB_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                            24
58613     #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_A0                                            (0x1<<26) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
58614     #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_A0_SHIFT                                      26
58615     #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_B0                                            (0x1<<22) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
58616     #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_B0_SHIFT                                      22
58617     #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2                                               (0x1<<25) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
58618     #define BTB_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_SHIFT                                         25
58619     #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_A0                                            (0x1<<25) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
58620     #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_A0_SHIFT                                      25
58621     #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_B0                                            (0x1<<21) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
58622     #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_B0_SHIFT                                      21
58623     #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2                                               (0x1<<26) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
58624     #define BTB_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_SHIFT                                         26
58625     #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
58626     #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0_SHIFT                                      20
58627     #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0                                            (0x1<<20) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
58628     #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0_SHIFT                                      20
58629     #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                               (0x1<<27) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
58630     #define BTB_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                         27
58631     #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
58632     #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0_SHIFT                                      19
58633     #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0                                            (0x1<<19) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
58634     #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0_SHIFT                                      19
58635     #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                               (0x1<<28) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
58636     #define BTB_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                         28
58637     #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
58638     #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_A0_SHIFT                                      18
58639     #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0                                            (0x1<<18) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
58640     #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0_SHIFT                                      18
58641     #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                               (0x1<<29) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
58642     #define BTB_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                         29
58643     #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
58644     #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0_SHIFT                                      16
58645     #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
58646     #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0_SHIFT                                      16
58647     #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                               (0x1<<30) // This bit masks, when set, the Parity bit: BTB_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
58648     #define BTB_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                         30
58649 #define BTB_REG_MEM_ECC_EVENTS_BB_A0                                                                 0xdb045cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0
58650 #define BTB_REG_MEM_ECC_EVENTS_BB_B0                                                                 0xdb045cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_B0
58651 #define BTB_REG_MEM_ECC_EVENTS_K2                                                                    0xdb041cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: K2
58652 #define BTB_REG_MEM033_I_MEM_DFT_K2                                                                  0xdb0424UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.i_wc_inp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58653 #define BTB_REG_MEM035_I_MEM_DFT_K2                                                                  0xdb0428UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.i_wc_sop_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58654 #define BTB_REG_MEM031_I_MEM_DFT_K2                                                                  0xdb042cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.i_dbgsyn_mem.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
58655 #define BTB_REG_MEM001_I_MEM_DFT_K2                                                                  0xdb0430UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[0].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58656 #define BTB_REG_MEM008_I_MEM_DFT_K2                                                                  0xdb0434UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[1].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58657 #define BTB_REG_MEM009_I_MEM_DFT_K2                                                                  0xdb0438UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[2].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58658 #define BTB_REG_MEM010_I_MEM_DFT_K2                                                                  0xdb043cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[3].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58659 #define BTB_REG_MEM011_I_MEM_DFT_K2                                                                  0xdb0440UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[4].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58660 #define BTB_REG_MEM012_I_MEM_DFT_K2                                                                  0xdb0444UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[5].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58661 #define BTB_REG_MEM013_I_MEM_DFT_K2                                                                  0xdb0448UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[6].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58662 #define BTB_REG_MEM014_I_MEM_DFT_K2                                                                  0xdb044cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[7].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58663 #define BTB_REG_MEM015_I_MEM_DFT_K2                                                                  0xdb0450UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[8].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58664 #define BTB_REG_MEM016_I_MEM_DFT_K2                                                                  0xdb0454UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[9].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58665 #define BTB_REG_MEM002_I_MEM_DFT_K2                                                                  0xdb0458UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[10].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58666 #define BTB_REG_MEM003_I_MEM_DFT_K2                                                                  0xdb045cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[11].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58667 #define BTB_REG_MEM004_I_MEM_DFT_K2                                                                  0xdb0460UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[12].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58668 #define BTB_REG_MEM005_I_MEM_DFT_K2                                                                  0xdb0464UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[13].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58669 #define BTB_REG_MEM006_I_MEM_DFT_K2                                                                  0xdb0468UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[14].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58670 #define BTB_REG_MEM007_I_MEM_DFT_K2                                                                  0xdb046cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.BB_BANK_K2_GEN_FOR[15].BB_BANK_K2_GEN_IF.i_bb_bank.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
58671 #define BTB_REG_MEM017_I_MEM_DFT_K2                                                                  0xdb0470UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.LL_BANK_K2_GEN_FOR[0].LL_BANK_K2_GEN_IF.i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
58672 #define BTB_REG_MEM018_I_MEM_DFT_K2                                                                  0xdb0474UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.LL_BANK_K2_GEN_FOR[1].LL_BANK_K2_GEN_IF.i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
58673 #define BTB_REG_MEM019_I_MEM_DFT_K2                                                                  0xdb0478UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.LL_BANK_K2_GEN_FOR[2].LL_BANK_K2_GEN_IF.i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
58674 #define BTB_REG_MEM020_I_MEM_DFT_K2                                                                  0xdb047cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.LL_BANK_K2_GEN_FOR[3].LL_BANK_K2_GEN_IF.i_link_list.i_mem of module es_gmem_2rw_1clk. [2]=rme, [1:0]=t_strw.  Chips: K2
58675 #define BTB_REG_MEM021_I_MEM_DFT_K2                                                                  0xdb0480UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RC_RSP_FIFO_GEN_FOR[0].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58676 #define BTB_REG_MEM022_I_MEM_DFT_K2                                                                  0xdb0484UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RC_RSP_FIFO_GEN_FOR[1].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58677 #define BTB_REG_MEM023_I_MEM_DFT_K2                                                                  0xdb0488UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RC_RSP_FIFO_GEN_FOR[2].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58678 #define BTB_REG_MEM024_I_MEM_DFT_K2                                                                  0xdb048cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RC_RSP_FIFO_GEN_FOR[3].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58679 #define BTB_REG_MEM025_I_MEM_DFT_K2                                                                  0xdb0490UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RC_RSP_FIFO_GEN_FOR[4].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58680 #define BTB_REG_MEM026_I_MEM_DFT_K2                                                                  0xdb0494UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RC_RSP_FIFO_GEN_FOR[5].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58681 #define BTB_REG_MEM027_I_MEM_DFT_K2                                                                  0xdb0498UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RC_RSP_FIFO_GEN_FOR[6].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58682 #define BTB_REG_MEM028_I_MEM_DFT_K2                                                                  0xdb049cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RC_RSP_FIFO_GEN_FOR[7].i_rc_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
58683 #define BTB_REG_MEM030_I_MEM_DFT_K2                                                                  0xdb04a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.WC_SYNC_FIFO_GEN_FOR[0].WC_SYNC_FIFO_GEN_IF.i_wc_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
58684 #define BTB_REG_MEM029_I_MEM_DFT_K2                                                                  0xdb04a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance btb.RLS_SYNC_FIFO_GEN_IF.i_rls_sync_fifo.i_mem of module es_gmem_1r1w_2clk. [2]=rme, [1:0]=t_strw.  Chips: K2
58685 #define BTB_REG_BIG_RAM_ADDRESS                                                                      0xdb0800UL //Access:RW   DataWidth:0xb   Debug register. It contains address to Big RAM for RBC operations. Value of this register will be incremented by one it was done write access to 32 MSB bits of big_ram_data register or read from 32 LSB bits of big_ram-data register::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
58686 #define BTB_REG_HEADER_SIZE                                                                          0xdb0804UL //Access:RW   DataWidth:0xa   Number of valid bytes in header in 16-bytes resolution. After this number of bytes will input to BRTB will be sent packet available indication. (reset value of 17 suits to 282 bytes of header)::s/HDR_SIZE_RST/17/g in Reset Value.  Chips: BB_A0 BB_B0 K2
58687 #define BTB_REG_FREE_LIST_HEAD                                                                       0xdb0810UL //Access:RW   DataWidth:0xc   Head pointer to each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
58688 #define BTB_REG_FREE_LIST_HEAD_SIZE                                                                  4
58689 #define BTB_REG_FREE_LIST_TAIL                                                                       0xdb0820UL //Access:RW   DataWidth:0xc   Tail pointer of each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
58690 #define BTB_REG_FREE_LIST_TAIL_SIZE                                                                  4
58691 #define BTB_REG_FREE_LIST_SIZE                                                                       0xdb0830UL //Access:RW   DataWidth:0xc   Number of free blocks in each one of 4 free lists::s/BLK_WDTH/13/g in Data Width.  Chips: BB_A0 BB_B0 K2
58692 #define BTB_REG_FREE_LIST_SIZE_SIZE                                                                  4
58693 #define BTB_REG_MAX_RELEASES                                                                         0xdb0840UL //Access:RW   DataWidth:0x2   Number of packet copies that should be released before whole packet is released::s/MAX_RLS_WDTH/10/g in Data Width::s/MAX_RLS_RST/512/g in Reset Value::s/MAX_RLS_REQ/required/g in Required::s/MAX_RLS_REQ/required/g in Software init.  Chips: BB_A0 BB_B0 K2
58694 #define BTB_REG_STOP_ON_LEN_ERR                                                                      0xdb0844UL //Access:RW   DataWidth:0x8   There is bit for each PACKET read client. When bit is set then read client will not execute more requests till reset in a case of length error other way it will continue to work as usual.::s/STOP_LEN_ERR_RST/7/g in Reset Value::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
58695 #define BTB_REG_ALM_FULL_THRESHOLD                                                                   0xdb0848UL //Access:RW   DataWidth:0xc   The number of blocks occupied in BTB upper which ALMOST FULL is asserted and BTB stops writing new packets to BIG RAM from its input FIFO. Miniml value is total number of TCs for all ports + 2 + number of blocks in maximal packet size::s/BLK_WDTH/13/g in Data Width::/ALM_FULL_EN/d in Existance. Value for 40G mode (reset value, both BB and K2): 2880 - (34 + 2 + (9600+32)/128) = 2768 = 0xAD0 Value for 100G mode (BB only): 2880/2  (34/2 + 2 + (9600+64)/256) = 1383 = 0x567  Chips: BB_A0 BB_B0 K2
58696 #define BTB_REG_NO_DEAD_CYCLES_EN                                                                    0xdb084cUL //Access:RW   DataWidth:0x8   There is bit for each PACKET read client. Bit 0 suits to client 0 and so on. If bit is set then packet will be read without dead cycles.B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
58697 #define BTB_REG_RC_PKT_PRIORITY                                                                      0xdb0850UL //Access:RW   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58698     #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN0_RC_PRI                                                 (0x3<<0) // This is priority for NIG main port 0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
58699     #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN0_RC_PRI_SHIFT                                           0
58700     #define BTB_REG_RC_PKT_PRIORITY_NIG_LB0_RC_PRI                                                   (0x3<<2) // This is priority for NIG LB port 0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
58701     #define BTB_REG_RC_PKT_PRIORITY_NIG_LB0_RC_PRI_SHIFT                                             2
58702     #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN1_RC_PRI                                                 (0x3<<4) // This is priority for NIG main port 1  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
58703     #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN1_RC_PRI_SHIFT                                           4
58704     #define BTB_REG_RC_PKT_PRIORITY_NIG_LB1_RC_PRI                                                   (0x3<<6) // This is priority for NIG LB port 1  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
58705     #define BTB_REG_RC_PKT_PRIORITY_NIG_LB1_RC_PRI_SHIFT                                             6
58706     #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN2_RC_PRI                                                 (0x3<<8) // This is priority for NIG main port 0  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
58707     #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN2_RC_PRI_SHIFT                                           8
58708     #define BTB_REG_RC_PKT_PRIORITY_NIG_LB2_RC_PRI                                                   (0x3<<10) // This is priority for NIG LB port 2  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
58709     #define BTB_REG_RC_PKT_PRIORITY_NIG_LB2_RC_PRI_SHIFT                                             10
58710     #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN3_RC_PRI                                                 (0x3<<12) // This is priority for NIG main port 3  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
58711     #define BTB_REG_RC_PKT_PRIORITY_NIG_MAIN3_RC_PRI_SHIFT                                           12
58712     #define BTB_REG_RC_PKT_PRIORITY_NIG_LB3_RC_PRI                                                   (0x3<<14) // This is priority for NIG LB port 3  read client that is used in link list and big ram arbiters. If all read clients have identical priority then selection between them is done with RR. Possible values are 1-3. Priority 3 is highest.::s/RC_PKT_PRI_0/prm_rc_pri/g in Field::s/RC_PKT_DSCR0/PRM/g in Comments::s/RC_PKT_PRI_RST_0/6/g in Reset Value.
58713     #define BTB_REG_RC_PKT_PRIORITY_NIG_LB3_RC_PRI_SHIFT                                             14
58714 #define BTB_REG_WC_NO_DEAD_CYCLES_EN                                                                 0xdb0854UL //Access:RW   DataWidth:0x1   There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then packet will be written without intra packet dead cycles .B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in Reset  Chips: K2
58715 #define BTB_REG_WC_HIGHEST_PRI_EN                                                                    0xdb0858UL //Access:RW   DataWidth:0x1   There is bit for each PACKET write client. Bit 0 suits to client 0 and so on. If bit is set then highest priority mechanism is enabled for the corresponding client. B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1 ::s/NO_DEAD_CYCLE_RST/1/g in Reset  Chips: K2
58716 #define BTB_REG_RC_SOP_PRIORITY                                                                      0xdb088cUL //Access:RW   DataWidth:0x2   This is priority for SOP read client to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_SOP_PRI_RST/5/g in Reset Value.  Chips: BB_A0 BB_B0 K2
58717 #define BTB_REG_WC_PRIORITY                                                                          0xdb0890UL //Access:RW   DataWidth:0x2   This is priority for packet request of write client group to Big RAM arbiter. Possible values are 1-3. Priority 3 is highest::s/RC_WC_PRI_RST/7/g in Reset Value.  Chips: BB_A0 BB_B0 K2
58718 #define BTB_REG_PRI_OF_MULT_CLIENTS                                                                  0xdb0894UL //Access:RW   DataWidth:0x2   This is priority of multiple clients with identical priority for link list arbiter. Selection from them will be done with round robin. Only one group with multiple clients of identical priority is supported. Possible values are 1-3. Priority 3 is highest::s/RC_MULT_PRI_RST/6/g in Reset Value.  Chips: BB_A0 BB_B0 K2
58719 #define BTB_REG_INP_FIFO_ALM_FULL                                                                    0xdb0898UL //Access:RW   DataWidth:0x6   Number of entries inside input FIFO of each write client upper which full outputs to this write client interface.  Chips: BB_A0 BB_B0 K2
58720 #define BTB_REG_WC_SYNC_FIFO_ALM_FULL                                                                0xdb089cUL //Access:RW   DataWidth:0x6   Number of entries inside sync FIFO of each write client.  Chips: BB_A0 BB_B0 K2
58721 #define BTB_REG_PKT_RC_OUT_SYNC_FIFO_ALM_FULL                                                        0xdb08a0UL //Access:RW   DataWidth:0x5   Number of entries inside output sync FIFO of each read client.  Chips: BB_A0 BB_B0 K2
58722 #define BTB_REG_PKT_AVAIL_SYNC_FIFO_ALM_FULL                                                         0xdb08a4UL //Access:RW   DataWidth:0x4   Number of entries inside packet available sync FIFO.  Chips: BB_A0 BB_B0 K2
58723 #define BTB_REG_RLS_SYNC_FIFO_ALM_FULL                                                               0xdb08a8UL //Access:RW   DataWidth:0x4   Number of entries inside packet available sync FIFO.  Chips: BB_A0 BB_B0 K2
58724 #define BTB_REG_INP_FIFO_HIGH_THRESHOLD                                                              0xdb08acUL //Access:RW   DataWidth:0x5   Number of entries inside input FIFO of each write client upper which all arbiters selects this client with high priority.  Chips: BB_A0 BB_B0 K2
58725 #define BTB_REG_DSCR_FIFO_ALM_FULL                                                                   0xdb08b0UL //Access:RW   DataWidth:0x5   Number of entries inside descriptors FIFO of each write client upper which full outputs to this write client interface.::s/DSCR_FIFO_RST/12/g in Reset Value.  Chips: BB_A0 BB_B0 K2
58726 #define BTB_REG_QUEUE_FIFO_ALM_FULL                                                                  0xdb08b4UL //Access:RW   DataWidth:0x5   Number of entries inside queue FIFO of each write client upper which full outputs to this write client interface.::s/QUEUE_FIFO_RST/8/g in Reset Value.  Chips: BB_A0 BB_B0 K2
58727 #define BTB_REG_DSCR_FIFO_HIGH_THRESHOLD                                                             0xdb08b8UL //Access:RW   DataWidth:0x5   Number of entries inside descriptors FIFO of each write client upper which all arbiters selects this client with high priority.  Chips: BB_A0 BB_B0 K2
58728 #define BTB_REG_DBGSYN_ALMOST_FULL_THR                                                               0xdb08bcUL //Access:RW   DataWidth:0x4   Debug only: If more than this Number of entries are occupied in the dbgsyn clock synchronization FIFO; it does not enable writing to the fifo. This value is based on implementation and should not be changed.  Chips: BB_A0 BB_B0 K2
58729 #define BTB_REG_DBGSYN_STATUS                                                                        0xdb08c0UL //Access:R    DataWidth:0x5   Fill level of dbgmux fifo.  Chips: BB_A0 BB_B0 K2
58730 #define BTB_REG_ECO_RESERVED                                                                         0xdb08c4UL //Access:RW   DataWidth:0x20  This is unused register for future ECOs.  Chips: BB_A0 BB_B0 K2
58731 #define BTB_REG_DBG_SELECT                                                                           0xdb08c8UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
58732 #define BTB_REG_DBG_DWORD_ENABLE                                                                     0xdb08ccUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
58733 #define BTB_REG_DBG_SHIFT                                                                            0xdb08d0UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
58734 #define BTB_REG_DBG_FORCE_VALID                                                                      0xdb08d4UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
58735 #define BTB_REG_DBG_FORCE_FRAME                                                                      0xdb08d8UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
58736 #define BTB_REG_DBG_OUT_DATA                                                                         0xdb08e0UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
58737 #define BTB_REG_DBG_OUT_DATA_SIZE                                                                    8
58738 #define BTB_REG_DBG_OUT_VALID                                                                        0xdb0900UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
58739 #define BTB_REG_DBG_OUT_FRAME                                                                        0xdb0904UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
58740 #define BTB_REG_INP_IF_ENABLE                                                                        0xdb0908UL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58741     #define BTB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN                                                   (0x3ff<<0) // There is bit per each read client interface: B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/PKT_RC_NUM_MINUS_SOP_EN/4/g in Data Width::s/RC_PKT_INP_IF_RST/15/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments.
58742     #define BTB_REG_INP_IF_ENABLE_RC_PKT_INP_IF_EN_SHIFT                                             0
58743     #define BTB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN                                                   (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted.  All bits of this register should be set after init procedure.
58744     #define BTB_REG_INP_IF_ENABLE_RC_SOP_INP_IF_EN_SHIFT                                             10
58745     #define BTB_REG_INP_IF_ENABLE_WC_INP_IF_EN                                                       (0x3ff<<11) // There is bit per write client interface: B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1.. When bit is set then appropriate interface is enabled. When bit is reset then request from that interface will not be accepted. All bits of this register should be set after init procedure. ::s/WC_IF_RST/15/g in Reset Value::s/WC_EN/B0 - NIG main port0; B1 - NIG LB port0; B2 - NIG main port1; B3 - NIG LB port1./g in Comments::s/WC_NUM/4/g in Data Width.
58746     #define BTB_REG_INP_IF_ENABLE_WC_INP_IF_EN_SHIFT                                                 11
58747 #define BTB_REG_OUT_IF_ENABLE                                                                        0xdb090cUL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
58748     #define BTB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN                                                   (0x3ff<<0) // There is bit per each read client interface: B0-NIG main port0; B1-NIG LB port0; B2-NIG main port1; B2-NIG LB port1. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted. All bits of this register should be set after init procedure. ::s/RC_PKT_OUT_IF_RST/31/g in Reset Value::s/NO_DEAD_CYCLE_DSCR/B0-PRM; B1 -MSDM ; B2 -TSDM; B3 -parser/g in Comments::s/PKT_RC_NUM/5/g in Data Width.
58749     #define BTB_REG_OUT_IF_ENABLE_RC_PKT_OUT_IF_EN_SHIFT                                             0
58750     #define BTB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN                                                   (0x1<<10) // There is bit per SOP read client interface. When bit is set then appropriate interface is enabled. When bit is reset then valid to that interface will never be asserted.  All bits of this register should be set after init procedure.
58751     #define BTB_REG_OUT_IF_ENABLE_RC_SOP_OUT_IF_EN_SHIFT                                             10
58752     #define BTB_REG_OUT_IF_ENABLE_ALM_FULL_OUT_IF_EN                                                 (0x1<<11) // There is bit for almost full interfaces. When bit is set then almost full interface is enabled. When bit is reset then almost full will never be set.  All bits of this register should be set after init procedure. ::/ALM_FULL_EN/d in Existance.
58753     #define BTB_REG_OUT_IF_ENABLE_ALM_FULL_OUT_IF_EN_SHIFT                                           11
58754     #define BTB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN                                            (0x1<<12) // There is bit for packet avalable interfaces. When bit is set then packet avalable interface is enabled. When bit is reset then packet avalable interface will never be set.  This bit should be set after init procedure.
58755     #define BTB_REG_OUT_IF_ENABLE_PKT_AVAILABLE_OUT_IF_EN_SHIFT                                      12
58756     #define BTB_REG_OUT_IF_ENABLE_RELEASE_OUT_IF_EN                                                  (0x1<<13) // There is bit for release interfaces. When bit is set then release interface is enabled. When bit is reset then release interface will never be set.  This bit should be set after init procedure. ::/RLS_EN/d in Existance.
58757     #define BTB_REG_OUT_IF_ENABLE_RELEASE_OUT_IF_EN_SHIFT                                            13
58758 #define BTB_REG_WC_DUP_EMPTY                                                                         0xdb0910UL //Access:R    DataWidth:0x4   Debug register. Empty status of write clients: {pkt_avail_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
58759 #define BTB_REG_WC_DUP_FULL                                                                          0xdb0914UL //Access:R    DataWidth:0x4   Debug register. Full status of write clients: {pkt_avail_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
58760 #define BTB_REG_WC_DUP_STATUS                                                                        0xdb0918UL //Access:R    DataWidth:0x10  Debug register. FIFO counters status of write clients: {delayed_fifo ;upd_point_fifo ; rsp_dscr_fifo; upd_data_fifo}::/DUP_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
58761 #define BTB_REG_WC_EMPTY_0                                                                           0xdb091cUL //Access:R    DataWidth:0xd   Debug register. Empty status of each write clients. 8 bits spelling of write client status: {ll_req_fifo;notify_fifo;cos_cnt_fifo;pkt_avail_fifo;inp_fifo; sop_fifo; len_fifo; eop_fifo; queue_fifo; free_point_fifo;next_point_fifo; strt_fifo; second_dscr_fifo}::s/WC_DSCR/B7:0 - NIG main port0; B15:8 - NIG LB port0; B23:16 - NIG main port1; B31:24 - NIG LB port1. 8 bits spelling of each client/g in Comments::s/WC_NUM/4/g in Array Size.  Chips: BB_A0 BB_B0 K2
58762 #define BTB_REG_WC_FULL_0                                                                            0xdb095cUL //Access:R    DataWidth:0xd   Debug register. Full status of write clients. 8 bits spelling of write client status: {ll_req_fifo_full; notify_queue_fifo_full; cos_cnt_fifo_full; pkt_avail_fifo_full; inp_fifo_full; sop_fifo_full; len_fifo_full; eop_fifo_full; queue_fifo_full; next_point_fifo_full; strt_fifo_full; second_dscr_fifo_full; free_point_fifo_full}  Chips: BB_A0 BB_B0 K2
58763 #define BTB_REG_WC_BANDWIDTH_IF_FULL                                                                 0xdb099cUL //Access:R    DataWidth:0x1   Debug register. Full status each write client because of temporal bandwidth problem on interface::s/WC_NUM_MAX/4/g in Data Width.  Chips: BB_A0 BB_B0 K2
58764 #define BTB_REG_RC_PKT_IF_FULL                                                                       0xdb09a0UL //Access:R    DataWidth:0x8   Debug register. Full status of each read packet client interface::s/PKT_RC_NUM/5/g in Data Width.  Chips: BB_A0 BB_B0 K2
58765 #define BTB_REG_RC_PKT_EMPTY_0                                                                       0xdb09a4UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58766 #define BTB_REG_RC_PKT_EMPTY_1                                                                       0xdb09a8UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58767 #define BTB_REG_RC_PKT_EMPTY_2                                                                       0xdb09acUL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58768 #define BTB_REG_RC_PKT_EMPTY_3                                                                       0xdb09b0UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58769 #define BTB_REG_RC_PKT_EMPTY_4                                                                       0xdb09b4UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58770 #define BTB_REG_RC_PKT_EMPTY_5                                                                       0xdb09b8UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58771 #define BTB_REG_RC_PKT_EMPTY_6                                                                       0xdb09bcUL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58772 #define BTB_REG_RC_PKT_EMPTY_7                                                                       0xdb09c0UL //Access:R    DataWidth:0x8   Debug register. Empty status of read packet clients. B7:0 - read client 0, B15:8 - read client 1, B23:16 - read client 2, B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fifo; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58773 #define BTB_REG_RC_PKT_FULL_0                                                                        0xdb09e0UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58774 #define BTB_REG_RC_PKT_FULL_1                                                                        0xdb09e4UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58775 #define BTB_REG_RC_PKT_FULL_2                                                                        0xdb09e8UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58776 #define BTB_REG_RC_PKT_FULL_3                                                                        0xdb09ecUL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58777 #define BTB_REG_RC_PKT_FULL_4                                                                        0xdb09f0UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58778 #define BTB_REG_RC_PKT_FULL_5                                                                        0xdb09f4UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58779 #define BTB_REG_RC_PKT_FULL_6                                                                        0xdb09f8UL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58780 #define BTB_REG_RC_PKT_FULL_7                                                                        0xdb09fcUL //Access:R    DataWidth:0x8   Debug register. Full status of read packet clients. B7:0 - read client 0; B15:8 - read client 1, B23:16 - read client 2; B31:24 -  - read client 3. 8 bits spelling of each client: {side_info_fio; req_fifo; blk_fifo; rls_left_fifo; strt_ptr_fifo; second_ptr_fifo; rsp_fifo; dscr_fifo}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58781 #define BTB_REG_RC_PKT_STATUS_0                                                                      0xdb0a1cUL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58782 #define BTB_REG_RC_PKT_STATUS_1                                                                      0xdb0a20UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58783 #define BTB_REG_RC_PKT_STATUS_2                                                                      0xdb0a24UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58784 #define BTB_REG_RC_PKT_STATUS_3                                                                      0xdb0a28UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: BB_A0 BB_B0 K2
58785 #define BTB_REG_RC_PKT_STATUS_4                                                                      0xdb0a2cUL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58786 #define BTB_REG_RC_PKT_STATUS_5                                                                      0xdb0a30UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58787 #define BTB_REG_RC_PKT_STATUS_6                                                                      0xdb0a34UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58788 #define BTB_REG_RC_PKT_STATUS_7                                                                      0xdb0a38UL //Access:R    DataWidth:0x20  Debug register. FIFO counters status of read packet clientsB31:0 - read client 0; B63:328 - read client 1; B95:64 - read client 2; B127:96 -  - read client 3. 32 bits spelling of each client: { req_fifo[31:26]; blk_fifo[25:23]; rls_shift[22:20]; second_ptr_fifo[19:17]; side_fifo[16:12]; rls_left_fifo[11:8]; rsp_fifo[7:3]; dscr_fifo[2:0]}::s/PKT_RC_NUM/5/g in Array Size.  Chips: K2
58789 #define BTB_REG_RC_SOP_EMPTY                                                                         0xdb0a58UL //Access:R    DataWidth:0x4   Debug register. Empty status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
58790 #define BTB_REG_RC_SOP_FULL                                                                          0xdb0a5cUL //Access:R    DataWidth:0x4   Debug register. Full status of read SOP clients: {B2-req_fifo;  B1-dscr_fifo;  B0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
58791 #define BTB_REG_RC_SOP_STATUS                                                                        0xdb0a60UL //Access:R    DataWidth:0x10  Debug register. FIFO counters status of read SOP clients: {B11:8-req_fifo;  B7:4-dscr_fifo;  B3:0-queue_fifo}.  Chips: BB_A0 BB_B0 K2
58792 #define BTB_REG_LL_ARB_EMPTY                                                                         0xdb0a64UL //Access:R    DataWidth:0x2   Debug register. Empty status of link list arbiter: {rls_fifo; prefetch_fifo}.  Chips: BB_A0 BB_B0 K2
58793 #define BTB_REG_LL_ARB_FULL                                                                          0xdb0a68UL //Access:R    DataWidth:0x2   Debug register. Full status of link list arbiter: {rls_fifo; prefetch_fifo}.  Chips: BB_A0 BB_B0 K2
58794 #define BTB_REG_LL_ARB_STATUS                                                                        0xdb0a6cUL //Access:R    DataWidth:0x8   Debug register. FIFO counters status of link list arbiter: {rls_fifo[7:4]; prefetch_fifo[3:0]}.  Chips: BB_A0 BB_B0 K2
58795 #define BTB_REG_BLOCK_OCCUPANCY                                                                      0xdb0a70UL //Access:R    DataWidth:0xc   Debug register. This is number of allocated blocks ::s/BLK_WDTH/13/g in Data Width::/ALM_FULL_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
58796 #define BTB_REG_ALM_FULL                                                                             0xdb0a74UL //Access:R    DataWidth:0x1   Debug register. This is  almost full output IF to PBF::/ALM_FULL_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
58797 #define BTB_REG_WC_SYNC_FIFO_PUSH_STATUS_0                                                           0xdb0a78UL //Access:R    DataWidth:0x7   Debug register. This is full status of WC SYNC FIFO  Chips: BB_A0 BB_B0 K2
58798 #define BTB_REG_RLS_SYNC_FIFO_PUSH_STATUS                                                            0xdb0ab4UL //Access:R    DataWidth:0x4   Debug register. This is full status of release SYNC FIFO  Chips: BB_A0 BB_B0 K2
58799 #define BTB_REG_RC_PKT_STATE                                                                         0xdb0ab8UL //Access:R    DataWidth:0x20  Debug register. This is state machine for each read client. ::s/PKT_RC_NUM_ST/20/g in Data Width.  Chips: BB_A0 BB_B0 K2
58800 #define BTB_REG_CLOCKS_RATIO                                                                         0xdb0ac8UL //Access:RW   DataWidth:0x4   Indicates the ratio of bytes arrived we need to wait for, in power of 2, before sending new packet indication to read client. This should ensure no underflow when read client reads the packet in higher frequency than write client writes it. In E4 the configuration value will be 3, meaning after 1/(2power3) of the packet arrived it can be sent to the read client. This is because (375-425)/425 is less then 1/(2power3).  Chips: BB_A0 BB_B0 K2
58801 #define BTB_REG_LAST_BLK_POOL                                                                        0xdb0b00UL //Access:R    DataWidth:0xf   Debug register. There is requister for each queue of duplicated client that contains pointer to first block of last packet from that queue in bits 11:0; b12: update enable status; b13: duplicated queue update enable; b14: man queue update status.::/DUP_EN/d in Existance.  Chips: BB_A0 BB_B0 K2
58802 #define BTB_REG_LAST_BLK_POOL_SIZE                                                                   34
58803 #define BTB_REG_BIG_RAM_DATA                                                                         0xdb0c00UL //Access:WB   DataWidth:0x80  Debug register. Data to BIG RAM memory. Write to 32 MSB bits of this register will generate write to BIG RAM according to address that is written in big_ram_address register. Read from 32 LSB bits of this register will generate read from BIG RAM according to address written in big_ram_address register.  Chips: BB_A0 BB_B0 K2
58804 #define BTB_REG_BIG_RAM_DATA_SIZE                                                                    64
58805 #define BTB_REG_RC_SOP_QUEUE_STATUS                                                                  0xdb0e00UL //Access:R    DataWidth:0x20  Debug register. There is register for each queue of each write client. It contains: b31 - valid; b30:16 - queue size; b15:0 - queue start pointer::s/SOP_STATUS_RST/536805376/g in Reset Value::s/QUEUE_ARRAY/36/g in memory size::s/SOP_STATUS_WDTH/6/g in Address Width.  Chips: BB_A0 BB_B0 K2
58806 #define BTB_REG_RC_SOP_QUEUE_STATUS_SIZE                                                             36
58807 #define BTB_REG_STOPPED_RD_REQ                                                                       0xdb1000UL //Access:WB_R DataWidth:0x40  If there is length error of first block error then request from read client will be copied to this register for each erad packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1. Message spelling (MSB->LSB): rest_size_error[0]; len_error[0]; 1st_error[0]; middle_error[0]; rls_to_do[1:0]; start_block[12:0]; rd_req[0]; rls_req[0]; offset[9:0]; length[13:0]; opaque[15:0]  Chips: BB_A0 BB_B0 K2
58808 #define BTB_REG_STOPPED_RD_REQ_SIZE                                                                  16
58809 #define BTB_REG_STOPPED_RLS_REQ                                                                      0xdb1100UL //Access:WB_R DataWidth:0x3c  If there is release error then request from read client will be copied to this register for each read packet client interface: 0-NIG main port0; 1-NIG LB port0; 2-NIG main port1; 2-NIG LB port1. Message spelling (MSB->LSB): opaque[1:0]; rls_to_do[15:0]; queue_number[5:0]; packet_length[13:0]; rls_left[1:0]; start_block[12:0]  Chips: BB_A0 BB_B0 K2
58810 #define BTB_REG_STOPPED_RLS_REQ_SIZE                                                                 16
58811 #define BTB_REG_WC_STATUS_0                                                                          0xdb1200UL //Access:WB_R DataWidth:0x5b  Debug register. FIFO counters status of write clients. 8 bits spelling of write client status: {cos_cnt[90:88]; notify_fifo[87:80]; pkt_avail_fifo[79:72]; len_fifo[71:64]; sop_fifo[63:56]; eop_fifo[55:48]; queue_fifo[47:40]; next_point_fifo[39:32]; strt_fifo[31:24]; second_dscr_fifo[23:16]; inp_fifo[15:8]; ll_req_fifo[7:4]; free_point_fifo[3:0]}  Chips: BB_A0 BB_B0 K2
58812 #define BTB_REG_WC_STATUS_0_SIZE                                                                     4
58813 #define BTB_REG_LINK_LIST                                                                            0xdb4000UL //Access:RW   DataWidth:0xc   Link list dual port memory that contains per-block descriptor::s/BLK_NUM/4800/g in memory size::s/BLK_WDTH_PLUS_SOP_EN/14/g in Data Width::s/BLK_WDTH/13/g in Address Width.  Chips: BB_A0 BB_B0 K2
58814 #define BTB_REG_LINK_LIST_SIZE                                                                       3680
58815 #define MCP_REG_MCP_CONTROL                                                                          0xe00080UL //Access:RW   DataWidth:0x20  These are basic configurations for the MCP block.  Chips: BB_A0 BB_B0 K2
58816     #define MCP_REG_MCP_CONTROL_UNUSED0                                                              (0x7fffffff<<0) //
58817     #define MCP_REG_MCP_CONTROL_UNUSED0_SHIFT                                                        0
58818     #define MCP_REG_MCP_CONTROL_MCP_ISOLATE                                                          (0x1<<31) // This bit is set by the driver before it sets the MCP_RESET bit. When set this bit disables MCP's GRC Master interface. This bit should cleared by the driver when the MCP reset completes.
58819     #define MCP_REG_MCP_CONTROL_MCP_ISOLATE_SHIFT                                                    31
58820 #define MCP_REG_MCP_ATTENTION_STATUS                                                                 0xe00084UL //Access:RW   DataWidth:0x20  SHARE : This register shows the status of the bits that generate attention from the MCP.  Chips: BB_A0 BB_B0 K2
58821     #define MCP_REG_MCP_ATTENTION_STATUS_UNUSED0                                                     (0x3ffffff<<0) //
58822     #define MCP_REG_MCP_ATTENTION_STATUS_UNUSED0_SHIFT                                               0
58823     #define MCP_REG_MCP_ATTENTION_STATUS_M2P_ATTN                                                    (0x1<<26) // Attention from the M2P Block.
58824     #define MCP_REG_MCP_ATTENTION_STATUS_M2P_ATTN_SHIFT                                              26
58825     #define MCP_REG_MCP_ATTENTION_STATUS_SPAD_CACHE_ATTN                                             (0x1<<27) // Illegal transaction occurred in the MCP cache block.
58826     #define MCP_REG_MCP_ATTENTION_STATUS_SPAD_CACHE_ATTN_SHIFT                                       27
58827     #define MCP_REG_MCP_ATTENTION_STATUS_SMB_EVENT                                                   (0x1<<28) // Event from the SMBUS Block.
58828     #define MCP_REG_MCP_ATTENTION_STATUS_SMB_EVENT_SHIFT                                             28
58829     #define MCP_REG_MCP_ATTENTION_STATUS_FLSH_EVENT                                                  (0x1<<29) // Event from the Flash Block.
58830     #define MCP_REG_MCP_ATTENTION_STATUS_FLSH_EVENT_SHIFT                                            29
58831     #define MCP_REG_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT                                            (0x1<<30) // This bit is set when the watchdog timer expires. This bit reflects state of the WATCHDOG_ATTN bit. When this bit is written as '1', the value will return to '0'. !!! Writing '1' has effect only after watchdog_reset register had been written !!!
58832     #define MCP_REG_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT_SHIFT                                      30
58833     #define MCP_REG_MCP_ATTENTION_STATUS_CPU_EVENT                                                   (0x1<<31) // This bit is set any time an internal CPU event that requires the driver's attention happens.
58834     #define MCP_REG_MCP_ATTENTION_STATUS_CPU_EVENT_SHIFT                                             31
58835 #define MCP_REG_MCP_HEARTBEAT_CONTROL                                                                0xe00088UL //Access:RW   DataWidth:0x20  Control for MCP heartbeat feature.  Chips: BB_A0 BB_B0 K2
58836     #define MCP_REG_MCP_HEARTBEAT_CONTROL_UNUSED0                                                    (0x7fffffff<<0) //
58837     #define MCP_REG_MCP_HEARTBEAT_CONTROL_UNUSED0_SHIFT                                              0
58838     #define MCP_REG_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE                                       (0x1<<31) // When this bit is set by the driver it indicates to MCP that it should start incrementing the MCP_HEARTBEAT register. The MCP reports the increment period to the driver using MCP_HEARTBEAT_STATUS register.
58839     #define MCP_REG_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE_SHIFT                                 31
58840 #define MCP_REG_MCP_HEARTBEAT_STATUS                                                                 0xe0008cUL //Access:RW   DataWidth:0x20  Status of MCP heartbeat feature.  Chips: BB_A0 BB_B0 K2
58841     #define MCP_REG_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD                                        (0x7ff<<0) // This value is written by the MCP and indicates (in ms) to the driver MCP_HEARTBEAT increment period. This is just rough increment period as estimated by the firmware and not the exact increment period.
58842     #define MCP_REG_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD_SHIFT                                  0
58843     #define MCP_REG_MCP_HEARTBEAT_STATUS_UNUSED0                                                     (0xfffff<<11) //
58844     #define MCP_REG_MCP_HEARTBEAT_STATUS_UNUSED0_SHIFT                                               11
58845     #define MCP_REG_MCP_HEARTBEAT_STATUS_VALID                                                       (0x1<<31) // When set this bit validates bits 10-0 of this register.
58846     #define MCP_REG_MCP_HEARTBEAT_STATUS_VALID_SHIFT                                                 31
58847 #define MCP_REG_MCP_HEARTBEAT                                                                        0xe00090UL //Access:RW   DataWidth:0x20  Doorbell registoer for MCP heartbeat feature.  Chips: BB_A0 BB_B0 K2
58848     #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT                                                (0x3fffffff<<0) // This is free running counter incremented roughly with the period that is specified in MCP_HEARTBEAT_STATUS register.
58849     #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT_SHIFT                                          0
58850     #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_INC                                                  (0x1<<30) // When set this bit causes MCP heartbeat counter to increment. Typically used by the MCP.
58851     #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_INC_SHIFT                                            30
58852     #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET                                                (0x1<<31) // When set this bit resets the heartbeat counter. Typically used by the MCP or the driver.
58853     #define MCP_REG_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET_SHIFT                                          31
58854 #define MCP_REG_WATCHDOG_RESET                                                                       0xe00094UL //Access:RW   DataWidth:0x20  Doorbell to reset the watchog timer.  Chips: BB_A0 BB_B0 K2
58855     #define MCP_REG_WATCHDOG_RESET_UNUSED0                                                           (0x3fffffff<<0) //
58856     #define MCP_REG_WATCHDOG_RESET_UNUSED0_SHIFT                                                     0
58857     #define MCP_REG_WATCHDOG_RESET_WATCHDOG_2_RESET                                                  (0x1<<30) // When set this bit resets the watchdog timer #2. Typically used by the MCP or the driver.
58858     #define MCP_REG_WATCHDOG_RESET_WATCHDOG_2_RESET_SHIFT                                            30
58859     #define MCP_REG_WATCHDOG_RESET_WATCHDOG_RESET                                                    (0x1<<31) // When set this bit resets the watchdog timer #1. Typically used by the MCP or the driver.
58860     #define MCP_REG_WATCHDOG_RESET_WATCHDOG_RESET_SHIFT                                              31
58861 #define MCP_REG_WATCHDOG_CONTROL                                                                     0xe00098UL //Access:RW   DataWidth:0x20  Control for the watchog timer.  Chips: BB_A0 BB_B0 K2
58862     #define MCP_REG_WATCHDOG_CONTROL_UNUSED0                                                         (0x7ffffff<<0) //
58863     #define MCP_REG_WATCHDOG_CONTROL_UNUSED0_SHIFT                                                   0
58864     #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_2_ENABLE                                               (0x1<<27) // When set this bit enables watchdog timer #2. Typically used by the driver
58865     #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_2_ENABLE_SHIFT                                         27
58866     #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_MASTER_WRITE_STALL_ENABLE                              (0x1<<28) // When this bit is set, expiration of watchdog timer will result in MCP losing ability to perform GRC master write operations. Default is for MCP to have GRC write capability even through a watchdog timer expiration.
58867     #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_MASTER_WRITE_STALL_ENABLE_SHIFT                        28
58868     #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ATTN                                                   (0x1<<29) // When set indicates that watchdog timer has reached 0 and that it requires driver's attention. Low to high transition on this bit should generate MCP attention toward the HC which will send it back to the driver using driver status block. Cleared when the watchdog timer is reset.
58869     #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ATTN_SHIFT                                             29
58870     #define MCP_REG_WATCHDOG_CONTROL_MCP_RST_ENABLE                                                  (0x1<<30) // When set this bit enables the watchdog timer to reset the MCP instead of halting it. The watchdog hardware must set MCP_ISOLATE bit before it resets the MCP.
58871     #define MCP_REG_WATCHDOG_CONTROL_MCP_RST_ENABLE_SHIFT                                            30
58872     #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ENABLE                                                 (0x1<<31) // When set this bit enables watchdog timer #1. Typically used by the driver.
58873     #define MCP_REG_WATCHDOG_CONTROL_WATCHDOG_ENABLE_SHIFT                                           31
58874 #define MCP_REG_WATCHDOG_1_TIMEOUT                                                                   0xe0009cUL //Access:RW   DataWidth:0x20  Timeout value for watchog timer #1. These bits specify the watchdog timeout period with respect to the MCP (1/2 speed) core_clk. Using core clock should provide timeout period scaling in case where core/cpu clocks are slowed down. Reset value is 500ms.  Chips: BB_A0 BB_B0 K2
58875 #define MCP_REG_WATCHDOG_2_TIMEOUT                                                                   0xe000a0UL //Access:RW   DataWidth:0x20  Timeout value for watchog timer #2. These bits specify the watchdog timeout period with respect to the MCP (1/2 speed) core_clk. Using core clock should provide timeout period scaling in case where core/cpu clocks are slowed down. Reset value is 2 seconds.  Chips: BB_A0 BB_B0 K2
58876 #define MCP_REG_ACCESS_LOCK                                                                          0xe000a4UL //Access:RW   DataWidth:0x20  SPLIT16: Access Lock Register.  Chips: BB_A0 BB_B0 K2
58877     #define MCP_REG_ACCESS_LOCK_UNUSED0                                                              (0x7fffffff<<0) //
58878     #define MCP_REG_ACCESS_LOCK_UNUSED0_SHIFT                                                        0
58879     #define MCP_REG_ACCESS_LOCK_LOCK                                                                 (0x1<<31) // Driver writes '1' to this bit in order to obtain the lock over the shared resources within the chip. The actual "lock" is implemented in hardware using the state machine that keeps track of who is the owner of the lock. Only the owner of the lock can release the lock. When read by the driver as '1' (after it was written with '1' it tells the driver that it obtained the lock. If read as '0' it means that the other driver holds the lock. Driver writes '0' to this bit to release the lock in case that it owns the lock.
58880     #define MCP_REG_ACCESS_LOCK_LOCK_SHIFT                                                           31
58881 #define MCP_REG_TOE_ID                                                                               0xe000a8UL //Access:R    DataWidth:0x20  SPLIT2: Function ID register  Chips: BB_A0 BB_B0 K2
58882     #define MCP_REG_TOE_ID_UNUSED0                                                                   (0x7fffffff<<0) //
58883     #define MCP_REG_TOE_ID_UNUSED0_SHIFT                                                             0
58884     #define MCP_REG_TOE_ID_FUNCTION_ID                                                               (0x1<<31) // This bit tells driver the PCIE function that is associated with. '0' corresponds to even PCIE functions '1' to odd PCIE functions. Since the value is different for both functions, the reset value is shown as unknown.
58885     #define MCP_REG_TOE_ID_FUNCTION_ID_SHIFT                                                         31
58886 #define MCP_REG_MAILBOX_CFG                                                                          0xe000acUL //Access:RW   DataWidth:0x20  SPLIT2: Configuration for mailbox trigger.  Chips: BB_A0 BB_B0 K2
58887     #define MCP_REG_MAILBOX_CFG_MAILBOX_OFFSET                                                       (0x3fff<<0) // Offset (in 32-bit words) of the mailbox within the MCP scratchpad. There are two reset values. Register that corresponds to even functions should have reset value of 0x3EC0 and register that corresponds to odd functions should have reset value of 0x3F00
58888     #define MCP_REG_MAILBOX_CFG_MAILBOX_OFFSET_SHIFT                                                 0
58889     #define MCP_REG_MAILBOX_CFG_UNUSED0                                                              (0x3f<<14) //
58890     #define MCP_REG_MAILBOX_CFG_UNUSED0_SHIFT                                                        14
58891     #define MCP_REG_MAILBOX_CFG_MAILBOX_SIZE                                                         (0xfff<<20) // Mailbox size in 32-bit words. Default mailbox size is 1KB.
58892     #define MCP_REG_MAILBOX_CFG_MAILBOX_SIZE_SHIFT                                                   20
58893 #define MCP_REG_MAILBOX_CFG_OTHER_FUNC                                                               0xe000b0UL //Access:RW   DataWidth:0x20  SPLIT2: Configuration for mailbox trigger.  Chips: BB_A0 BB_B0 K2
58894     #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET                                            (0x3fff<<0) // Offset (in 32-bit words) of the mailbox within the MCP scratchpad. There are two reset values. Register that corresponds to even functions should have reset value of 0x3EC0 and register that corresponds to odd functions should have reset value of 0x3F00
58895     #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET_SHIFT                                      0
58896     #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_UNUSED0                                                   (0x3f<<14) //
58897     #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_UNUSED0_SHIFT                                             14
58898     #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE                                              (0xfff<<20) // Mailbox size in 32-bit words. Default mailbox size is 1KB.
58899     #define MCP_REG_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE_SHIFT                                        20
58900 #define MCP_REG_MCP_DOORBELL                                                                         0xe000b4UL //Access:RW   DataWidth:0x20  SPLIT16: Doorbell that is written by firmware.  Chips: BB_A0 BB_B0 K2
58901     #define MCP_REG_MCP_DOORBELL_UNUSED0                                                             (0x7fffffff<<0) //
58902     #define MCP_REG_MCP_DOORBELL_UNUSED0_SHIFT                                                       0
58903     #define MCP_REG_MCP_DOORBELL_MCP_DOORBELL                                                        (0x1<<31) // Set by the driver to alert the MCP. Changing this register updates the corresponding per-PF bit in the MCP Doorbell Status register. Cleared by the MCP when it services the message.
58904     #define MCP_REG_MCP_DOORBELL_MCP_DOORBELL_SHIFT                                                  31
58905 #define MCP_REG_MCP_VFID                                                                             0xe000c4UL //Access:RW   DataWidth:0x20  VFID settings.  Chips: BB_A0 BB_B0 K2
58906     #define MCP_REG_MCP_VFID_VFID                                                                    (0xff<<0) // Register supports up to an 8 bit VFID. For smaller VFIDs, the extra bits wil be ignored.
58907     #define MCP_REG_MCP_VFID_VFID_SHIFT                                                              0
58908     #define MCP_REG_MCP_VFID_UNUSED0                                                                 (0xff<<8) //
58909     #define MCP_REG_MCP_VFID_UNUSED0_SHIFT                                                           8
58910     #define MCP_REG_MCP_VFID_VFID_VALID                                                              (0x1<<16) //
58911     #define MCP_REG_MCP_VFID_VFID_VALID_SHIFT                                                        16
58912     #define MCP_REG_MCP_VFID_UNUSED1                                                                 (0x7<<17) //
58913     #define MCP_REG_MCP_VFID_UNUSED1_SHIFT                                                           17
58914     #define MCP_REG_MCP_VFID_PATHID                                                                  (0x1<<20) //
58915     #define MCP_REG_MCP_VFID_PATHID_SHIFT                                                            20
58916     #define MCP_REG_MCP_VFID_UNUSED2                                                                 (0x3ff<<21) //
58917     #define MCP_REG_MCP_VFID_UNUSED2_SHIFT                                                           21
58918     #define MCP_REG_MCP_VFID_PATH_FORCE                                                              (0x1<<31) //
58919     #define MCP_REG_MCP_VFID_PATH_FORCE_SHIFT                                                        31
58920 #define MCP_REG_GP_INPUTS                                                                            0xe000c8UL //Access:R    DataWidth:0x20  Extended General Purpose Inputs  Chips: BB_A0 BB_B0 K2
58921 #define MCP_REG_PORT_MODE                                                                            0xe000ccUL //Access:RW   DataWidth:0x20  Port mode for GRC Master transactions 0: 1-port mode, 1: 2-port mode, 2: 4-port mode All bits are RW, but only the 2 lsb are relevant  Chips: BB_A0 BB_B0 K2
58922 #define MCP_REG_GP_OENABLE                                                                           0xe000d0UL //Access:RW   DataWidth:0x20  Extended General Purpose Output Enable  Chips: BB_A0 BB_B0 K2
58923 #define MCP_REG_GP_MASK_HI_TO_LO                                                                     0xe000d4UL //Access:RW   DataWidth:0x20  EPIO mask for signal transitioning from high to low. 1 -&gt; MASK the event  Chips: BB_A0 BB_B0 K2
58924 #define MCP_REG_GP_MASK_LO_TO_HI                                                                     0xe000d8UL //Access:RW   DataWidth:0x20  EPIO mask for signal transitioning from low to high. 1 -&gt; MASK the event  Chips: BB_A0 BB_B0 K2
58925 #define MCP_REG_GP_HI_TO_LO                                                                          0xe000dcUL //Access:RW   DataWidth:0x20  EPIO event status for high to low transition prior to mask  Chips: BB_A0 BB_B0 K2
58926 #define MCP_REG_GP_LO_TO_HI                                                                          0xe000e0UL //Access:RW   DataWidth:0x20  EPIO event status for low to high transition prior to mask  Chips: BB_A0 BB_B0 K2
58927 #define MCP_REG_GP_EVENT_VEC                                                                         0xe000e4UL //Access:RW   DataWidth:0x20  EPIO event status for either transitions with the mask applied.  Chips: BB_A0 BB_B0 K2
58928 #define MCP_REG_CPU_MODE                                                                             0xe05000UL //Access:RW   DataWidth:0x20  CPU Internal registers.  Chips: BB_A0 BB_B0 K2
58929     #define MCP_REG_CPU_MODE_LOCAL_RST                                                               (0x1<<0) // When this bit is written to a 1, the processor will reset as if from power-up state. All "Reset" value of registers will be assigned.
58930     #define MCP_REG_CPU_MODE_LOCAL_RST_SHIFT                                                         0
58931     #define MCP_REG_CPU_MODE_STEP_ENA                                                                (0x1<<1) // When this bit is set, the processor is allowed to execute one cycle regardless of any halt conditions. If the halting condition still exists, the CPU will halt again after the one cycle, otherwise, it will resume normal operation.
58932     #define MCP_REG_CPU_MODE_STEP_ENA_SHIFT                                                          1
58933     #define MCP_REG_CPU_MODE_PAGE_0_DATA_ENA                                                         (0x1<<2) // This bit enables the processor to halt and to latch the value of bit 3 of the state register when data references the first 256 bytes of memory space (page 0). This bit is cleared by an interrupt or reset.
58934     #define MCP_REG_CPU_MODE_PAGE_0_DATA_ENA_SHIFT                                                   2
58935     #define MCP_REG_CPU_MODE_PAGE_0_INST_ENA                                                         (0x1<<3) // This bit enables the processor to halt and to latch the value of bit 4 of the state register when an instruction references the first 256 bytes of memory space (page 0). This bit is cleared by an interrupt or reset.
58936     #define MCP_REG_CPU_MODE_PAGE_0_INST_ENA_SHIFT                                                   3
58937     #define MCP_REG_CPU_MODE_UNUSED0                                                                 (0x3<<4) //
58938     #define MCP_REG_CPU_MODE_UNUSED0_SHIFT                                                           4
58939     #define MCP_REG_CPU_MODE_MSG_BIT1                                                                (0x1<<6) // This is a simple RW bit.
58940     #define MCP_REG_CPU_MODE_MSG_BIT1_SHIFT                                                          6
58941     #define MCP_REG_CPU_MODE_INTERRUPT_ENA                                                           (0x1<<7) // When this bit is set to 1, the interrupt is enabled. When this bit is zero, any interrupt will be ignored. This bit can also be set by writing the interrupt_enable register
58942     #define MCP_REG_CPU_MODE_INTERRUPT_ENA_SHIFT                                                     7
58943     #define MCP_REG_CPU_MODE_UNUSED1                                                                 (0x3<<8) //
58944     #define MCP_REG_CPU_MODE_UNUSED1_SHIFT                                                           8
58945     #define MCP_REG_CPU_MODE_SOFT_HALT                                                               (0x1<<10) // When this bit is set, the CPU will halt. This bit is cleared by an exception or reset. If the processor does not have a ROM, then this bit will reset to set so that no code is executed from the scratchpad. If the processor does have a ROM, this bit resets a cleared so that the processor executes from ROM after reset.
58946     #define MCP_REG_CPU_MODE_SOFT_HALT_SHIFT                                                         10
58947     #define MCP_REG_CPU_MODE_BAD_DATA_HALT_ENA                                                       (0x1<<11) // When this bit is set, the CPU will halt when any condition that causes bit 5 in the CPU state register to be set occurs. This bit is cleared by an interrupt.
58948     #define MCP_REG_CPU_MODE_BAD_DATA_HALT_ENA_SHIFT                                                 11
58949     #define MCP_REG_CPU_MODE_BAD_INST_HALT_ENA                                                       (0x1<<12) // When this bit is set, the CPU will halt when any condition that causes bit 6 in the CPU state register to be set occurs. This bit is cleared by an interrupt.
58950     #define MCP_REG_CPU_MODE_BAD_INST_HALT_ENA_SHIFT                                                 12
58951     #define MCP_REG_CPU_MODE_FIO_ABORT_HALT_ENA                                                      (0x1<<13) // When this bit is set, the CPU will halt when a abort is indicated from any "Fast IO" space peripheral.
58952     #define MCP_REG_CPU_MODE_FIO_ABORT_HALT_ENA_SHIFT                                                13
58953     #define MCP_REG_CPU_MODE_UNUSED2                                                                 (0x1<<14) //
58954     #define MCP_REG_CPU_MODE_UNUSED2_SHIFT                                                           14
58955     #define MCP_REG_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA                                                 (0x1<<15) // When this bit is set, the CPU will halt when state bit 11 is set.
58956     #define MCP_REG_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA_SHIFT                                           15
58957 #define MCP_REG_CPU_STATE                                                                            0xe05004UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
58958     #define MCP_REG_CPU_STATE_BREAKPOINT                                                             (0x1<<0) // This bit is set while the processor is halted due reaching a hardware breakpoint as enabled in the mode register. This bit is cleared by writing a 1 to this bit position.
58959     #define MCP_REG_CPU_STATE_BREAKPOINT_SHIFT                                                       0
58960     #define MCP_REG_CPU_STATE_UNUSED0                                                                (0x1<<1) //
58961     #define MCP_REG_CPU_STATE_UNUSED0_SHIFT                                                          1
58962     #define MCP_REG_CPU_STATE_BAD_INST_HALTED                                                        (0x1<<2) // This bit is set while the processor is halted due fetching an invalid instruction. This bit is cleared by writing a 1 to this bit position.
58963     #define MCP_REG_CPU_STATE_BAD_INST_HALTED_SHIFT                                                  2
58964     #define MCP_REG_CPU_STATE_PAGE_0_DATA_HALTED                                                     (0x1<<3) // This bit is set while the processor is halted due to accessing data within page 0 (the first 256 bytes) of memory. This bit is cleared by writing a 1 to this bit position.
58965     #define MCP_REG_CPU_STATE_PAGE_0_DATA_HALTED_SHIFT                                               3
58966     #define MCP_REG_CPU_STATE_PAGE_0_INST_HALTED                                                     (0x1<<4) // This bit is set while the processor is halted due to executing an instruction within page 0 (the first 256 bytes) of memory. This bit is cleared by writing a 1 to this bit position.
58967     #define MCP_REG_CPU_STATE_PAGE_0_INST_HALTED_SHIFT                                               4
58968     #define MCP_REG_CPU_STATE_BAD_DATA_ADDR_HALTED                                                   (0x1<<5) // This bit is set while the processor is halted due to bad data reference address. This bit is cleared by writing a 1 to this bit position.
58969     #define MCP_REG_CPU_STATE_BAD_DATA_ADDR_HALTED_SHIFT                                             5
58970     #define MCP_REG_CPU_STATE_BAD_PC_HALTED                                                          (0x1<<6) // This bit is set while the processor is halted due to bad value in the Program Counter (PC). This bit is cleared by writing a 1 to this bit position.
58971     #define MCP_REG_CPU_STATE_BAD_PC_HALTED_SHIFT                                                    6
58972     #define MCP_REG_CPU_STATE_ALIGN_HALTED                                                           (0x1<<7) // This bit is set while the processor is halted due to bad memory alignment problem on a load or store instruction. This bit is cleared by writing a 1 to this bit position.
58973     #define MCP_REG_CPU_STATE_ALIGN_HALTED_SHIFT                                                     7
58974     #define MCP_REG_CPU_STATE_FIO_ABORT_HALTED                                                       (0x1<<8) // This bit is set while the processor is halted due to the generation of a abort condition by one, or more, "Fast IO" devices within the CPU block. This will only happen if halt is enabled by bit 13 in the mode register.
58975     #define MCP_REG_CPU_STATE_FIO_ABORT_HALTED_SHIFT                                                 8
58976     #define MCP_REG_CPU_STATE_UNUSED1                                                                (0x1<<9) //
58977     #define MCP_REG_CPU_STATE_UNUSED1_SHIFT                                                          9
58978     #define MCP_REG_CPU_STATE_SOFT_HALTED                                                            (0x1<<10) // This bit is set while the processor is halted due to the setting of bit 10 in the mode register.
58979     #define MCP_REG_CPU_STATE_SOFT_HALTED_SHIFT                                                      10
58980     #define MCP_REG_CPU_STATE_SPAD_UNDERFLOW                                                         (0x1<<11) // This bit is each time an attempt is made to access the underflow area of the Scratchpad.
58981     #define MCP_REG_CPU_STATE_SPAD_UNDERFLOW_SHIFT                                                   11
58982     #define MCP_REG_CPU_STATE_INTERRRUPT                                                             (0x1<<12) // This bit is each time an interrupt input is asserted, regardless of the interrupt enable bit (bit 7, mode).
58983     #define MCP_REG_CPU_STATE_INTERRRUPT_SHIFT                                                       12
58984     #define MCP_REG_CPU_STATE_UNUSED2                                                                (0x1<<13) //
58985     #define MCP_REG_CPU_STATE_UNUSED2_SHIFT                                                          13
58986     #define MCP_REG_CPU_STATE_DATA_ACCESS_STALL                                                      (0x1<<14) // This bit is set while the processor is stalled due to data access.
58987     #define MCP_REG_CPU_STATE_DATA_ACCESS_STALL_SHIFT                                                14
58988     #define MCP_REG_CPU_STATE_INST_FETCH_STALL                                                       (0x1<<15) // This bit is set while the processor is stalled due to instruction fetch.
58989     #define MCP_REG_CPU_STATE_INST_FETCH_STALL_SHIFT                                                 15
58990     #define MCP_REG_CPU_STATE_UNUSED3                                                                (0x7fff<<16) //
58991     #define MCP_REG_CPU_STATE_UNUSED3_SHIFT                                                          16
58992     #define MCP_REG_CPU_STATE_BLOCKED_READ                                                           (0x1<<31) // This bit indicates that a blocking data cache miss occurred, causing the CPU to stall while data is fetched from memory. This is intended as a debugging tool. No state is saved other than the fact that the miss occurred. This bit is cleared by writing a 1 to this bit position.
58993     #define MCP_REG_CPU_STATE_BLOCKED_READ_SHIFT                                                     31
58994 #define MCP_REG_CPU_EVENT_MASK                                                                       0xe05008UL //Access:RW   DataWidth:0x20  This register provides one bit for each state register bit to enable it into the equation for generation the TX Processor Attention output. The reset value of 1 masks all halt conditions from generating an attention.  Chips: BB_A0 BB_B0 K2
58995     #define MCP_REG_CPU_EVENT_MASK_BREAKPOINT_MASK                                                   (0x1<<0) // This bit enables breakpoints to generate Attention output.
58996     #define MCP_REG_CPU_EVENT_MASK_BREAKPOINT_MASK_SHIFT                                             0
58997     #define MCP_REG_CPU_EVENT_MASK_UNUSED0                                                           (0x1<<1) //
58998     #define MCP_REG_CPU_EVENT_MASK_UNUSED0_SHIFT                                                     1
58999     #define MCP_REG_CPU_EVENT_MASK_BAD_INST_HALTED_MASK                                              (0x1<<2) // This bit enables invalid instruction decodes to generate Attention output.
59000     #define MCP_REG_CPU_EVENT_MASK_BAD_INST_HALTED_MASK_SHIFT                                        2
59001     #define MCP_REG_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK                                           (0x1<<3) // This bit enables page 0 data access to generate Attention output.
59002     #define MCP_REG_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK_SHIFT                                     3
59003     #define MCP_REG_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK                                           (0x1<<4) // This bit enables page 0 instructions to generate Attention output.
59004     #define MCP_REG_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK_SHIFT                                     4
59005     #define MCP_REG_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK                                         (0x1<<5) // This bit enables invalid data addresses to generate Attention output.
59006     #define MCP_REG_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK_SHIFT                                   5
59007     #define MCP_REG_CPU_EVENT_MASK_BAD_PC_HALTED_MASK                                                (0x1<<6) // This bit enables invalid PC values to generate Attention output.
59008     #define MCP_REG_CPU_EVENT_MASK_BAD_PC_HALTED_MASK_SHIFT                                          6
59009     #define MCP_REG_CPU_EVENT_MASK_ALIGN_HALTED_MASK                                                 (0x1<<7) // This bit enables alignment errors to generate Attention output.
59010     #define MCP_REG_CPU_EVENT_MASK_ALIGN_HALTED_MASK_SHIFT                                           7
59011     #define MCP_REG_CPU_EVENT_MASK_FIO_ABORT_MASK                                                    (0x1<<8) // This bit enables the attention output when bit 8 of the state register is set.
59012     #define MCP_REG_CPU_EVENT_MASK_FIO_ABORT_MASK_SHIFT                                              8
59013     #define MCP_REG_CPU_EVENT_MASK_UNUSED1                                                           (0x1<<9) //
59014     #define MCP_REG_CPU_EVENT_MASK_UNUSED1_SHIFT                                                     9
59015     #define MCP_REG_CPU_EVENT_MASK_SOFT_HALTED_MASK                                                  (0x1<<10) // This bit enables soft halts to generate Attention output.
59016     #define MCP_REG_CPU_EVENT_MASK_SOFT_HALTED_MASK_SHIFT                                            10
59017     #define MCP_REG_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK                                               (0x1<<11) // This bit attention when bit 11 of the state register is set.
59018     #define MCP_REG_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK_SHIFT                                         11
59019     #define MCP_REG_CPU_EVENT_MASK_INTERRUPT_MASK                                                    (0x1<<12) // This bit attention when bit 12 of the state register is set.
59020     #define MCP_REG_CPU_EVENT_MASK_INTERRUPT_MASK_SHIFT                                              12
59021 #define MCP_REG_CPU_PROGRAM_COUNTER                                                                  0xe0501cUL //Access:RW   DataWidth:0x20  This register allows the program counter to read at any time. The value can be modified when the processor is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-0 are ignored. If the processor has a ROM, then the reset value of this register points to the internal ROM. If the processor does not have a ROM, then this reset value points to the scratchpad area.  Chips: BB_A0 BB_B0 K2
59022 #define MCP_REG_CPU_INSTRUCTION                                                                      0xe05020UL //Access:RW   DataWidth:0x20  This register allows access instruction in the decode sate of the pipeline while the processor is halted. This register is only intended for debugging use. This register may be used to replace a halt instruction with some other instruction after the halt has been executed.  Chips: BB_A0 BB_B0 K2
59023 #define MCP_REG_CPU_DATA_ACCESS                                                                      0xe05024UL //Access:R    DataWidth:0x20  This register allows access to the address of the current data access of the processor. It is only valid when the processor is doing a load or a store. Normally this will be used for debug of stalls caused by firmware accesses to invalid memory areas.  Chips: BB_A0 BB_B0 K2
59024 #define MCP_REG_CPU_INTERRUPT_ENABLE                                                                 0xe05028UL //Access:W    DataWidth:0x20  Any write to this register will enable CPU Interrupts (set bit 7 in mode register). This register is intended to allow a way to return from an interrupt service routine (ISR) using only 2 general purpose registers. MIPS conventions reserve registers 26 and 27 (k0 and k1) for use by an interrupt handler. At the end of an ISR, k0 should be loaded with the return address from the CPU Interrupt Saved PC register. Then k1 should be loaded with the address of the CPU Interrupt Enable register. The last 2 instructions in the ISR should be a jump register (jr) to k0 followed immediately by a store word (sw) to k1. This ensures that we can't respond to another interrupt until we are safely out of the ISR. Interrupts can also be enabled through the CPU Mode Register. They can be disabled only through the CPU Mode Register. Each time this register is written, bit 7 of the mode register is set. The data value of the write is not used. The read value of this register is always zero.  Chips: BB_A0 BB_B0 K2
59025 #define MCP_REG_CPU_INTERRUPT_VECTOR                                                                 0xe0502cUL //Access:RW   DataWidth:0x20  This register sets the program counter value that will be loaded when an interrupt is performed due to the interrupt input.  Chips: BB_A0 BB_B0 K2
59026 #define MCP_REG_CPU_INTERRUPT_SAVED_PC                                                               0xe05030UL //Access:R    DataWidth:0x20  This register reports the PC that was saved during the execution of an interrupt.  Chips: BB_A0 BB_B0 K2
59027 #define MCP_REG_CPU_HW_BREAKPOINT                                                                    0xe05034UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59028     #define MCP_REG_CPU_HW_BREAKPOINT_DISABLE                                                        (0x1<<0) // Reset: 1 When this bit is set, the hardware breakpoint feature is disabled.
59029     #define MCP_REG_CPU_HW_BREAKPOINT_DISABLE_SHIFT                                                  0
59030     #define MCP_REG_CPU_HW_BREAKPOINT_UNUSED0                                                        (0x1<<1) //
59031     #define MCP_REG_CPU_HW_BREAKPOINT_UNUSED0_SHIFT                                                  1
59032     #define MCP_REG_CPU_HW_BREAKPOINT_ADDRESS                                                        (0x3fffffff<<2) // This field sets the 32-bit word on which the * hardware breakpoint will execute.
59033     #define MCP_REG_CPU_HW_BREAKPOINT_ADDRESS_SHIFT                                                  2
59034 #define MCP_REG_CPU_DEBUG_VECT_PEEK                                                                  0xe05038UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59035     #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_VALUE                                                     (0x7ff<<0) // 11 bit set-1 debug visibility vector value. This value is selected by the 1_SEL value and enabled by 1_PEEK_EN. This value is undefined if 1_PEEK_EN is '0'.
59036     #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_VALUE_SHIFT                                               0
59037     #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_PEEK_EN                                                   (0x1<<11) // When this bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is available on the visibility output pins. When this bit is '1', then the mux is controlled by 1_SEL.
59038     #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_PEEK_EN_SHIFT                                             11
59039     #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_SEL                                                       (0xf<<12) // 4 bit select for the peek value of the set-1 debug visibility vector.
59040     #define MCP_REG_CPU_DEBUG_VECT_PEEK__1_SEL_SHIFT                                                 12
59041     #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_VALUE                                                     (0x7ff<<16) // 11 bit set-2 debug visibility vector value. This value is selected by the 2_SEL value and enabled by 2_PEEK_EN. This value is undefined if 2_PEEK_EN is '0'.
59042     #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_VALUE_SHIFT                                               16
59043     #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_PEEK_EN                                                   (0x1<<27) // When this bit is '0', then the debug visiblity mux is controlled by the setting in the misc. block and is available on the visibility output pins. When this bit is '1', then the mux is controlled by 1_SEL.
59044     #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_PEEK_EN_SHIFT                                             27
59045     #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_SEL                                                       (0xf<<28) // 4 bit select for the peek value of the set-2 debug visibility vector.
59046     #define MCP_REG_CPU_DEBUG_VECT_PEEK__2_SEL_SHIFT                                                 28
59047 #define MCP_REG_CPU_LAST_BRANCH_ADDR                                                                 0xe05048UL //Access:R    DataWidth:0x20  This register indicates that address and branch type of the last branch that was taken. This register is for debug use only.  Chips: BB_A0 BB_B0 K2
59048     #define MCP_REG_CPU_LAST_BRANCH_ADDR_UNUSED0                                                     (0x1<<0) //
59049     #define MCP_REG_CPU_LAST_BRANCH_ADDR_UNUSED0_SHIFT                                               0
59050     #define MCP_REG_CPU_LAST_BRANCH_ADDR_TYPE                                                        (0x1<<1) // This bit indicates the type of branch that * was last taken.
59051     #define MCP_REG_CPU_LAST_BRANCH_ADDR_TYPE_SHIFT                                                  1
59052     #define MCP_REG_CPU_LAST_BRANCH_ADDR_LBA                                                         (0x3fffffff<<2) // This value indicates the address of the last branch that was taken. An offset as indicated by the type field must be subtracted from this value.
59053     #define MCP_REG_CPU_LAST_BRANCH_ADDR_LBA_SHIFT                                                   2
59054 #define MCP_REG_CPU_REG_FILE                                                                         0xe05200UL //Access:RW   DataWidth:0x20  While the processor is halted, the general purpose processor registers (r0-r31) can be read and written through these register locations.  Chips: BB_A0 BB_B0 K2
59055 #define MCP_REG_CPU_REG_FILE_SIZE                                                                    32
59056 #define MCP_REG_MDIO_AUTO_POLL                                                                       0xe054a8UL //Access:RW   DataWidth:0x20  This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.  Chips: BB_A0 BB_B0 K2
59057     #define MCP_REG_MDIO_AUTO_POLL_DATA_MASK                                                         (0xffff<<0) // This value is used to specify the bit at the auto-polled address that indicates "link up". The bit which corresponds to "link up" should be set in this data mask field.
59058     #define MCP_REG_MDIO_AUTO_POLL_DATA_MASK_SHIFT                                                   0
59059     #define MCP_REG_MDIO_AUTO_POLL_REG_ADDR                                                          (0xffff<<16) // This value is used to define the register address in MDIO auto-poll transactions. For Clause 22, only the bottom 5 bits are utilized. For Clause 45, all 16 bits are utilized.
59060     #define MCP_REG_MDIO_AUTO_POLL_REG_ADDR_SHIFT                                                    16
59061 #define MCP_REG_MDIO_COMM                                                                            0xe054acUL //Access:RW   DataWidth:0x20  This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.  Chips: BB_A0 BB_B0 K2
59062     #define MCP_REG_MDIO_COMM_DATA                                                                   (0xffff<<0) // When this register is read, it returns the results of the last MDIO transaction that was performed. When this register value is written, it updates the value that will be used on the next MDIO write transaction that will be performed. In case of Clause 45, when the address transaction is executed, this value specifies the register address. On chip versions before TetonII-B0, on the first read of this register when the START_BUSY bit returns to '0', this value, in the same read, is invalid. A 2nd read must be executed to get the correct value. This problem is fixed in TetonII-B0 and later.
59063     #define MCP_REG_MDIO_COMM_DATA_SHIFT                                                             0
59064     #define MCP_REG_MDIO_COMM_REG_ADDR                                                               (0x1f<<16) // This value is used to define the register address portion of the MDIO transaction for Clause 22. This selects what register within a PHY device is being accessed. In case of Clause 45 this value specifies the device address.
59065     #define MCP_REG_MDIO_COMM_REG_ADDR_SHIFT                                                         16
59066     #define MCP_REG_MDIO_COMM_PHY_ADDR                                                               (0x1f<<21) // This value is used to define the PHY address portion of the MDIO transaction for Clause 22 and the port address for Clause 45.
59067     #define MCP_REG_MDIO_COMM_PHY_ADDR_SHIFT                                                         21
59068     #define MCP_REG_MDIO_COMM_COMMAND                                                                (0x3<<26) // This field controls the type of MDIO transaction that will be performed when the START_BUSY bit is set.
59069     #define MCP_REG_MDIO_COMM_COMMAND_SHIFT                                                          26
59070     #define MCP_REG_MDIO_COMM_FAIL                                                                   (0x1<<28) // This bit is updated at the end of each MDIO transaction when the START_BUSY bit is set. If an error occurred on the MDIO interface during the operation, this bit will be updated to '1', otherwise, it will be updated to '0'. Errors usually happen when the attached PHY fails to drive a response during a read. This bit is only modified by completing a new MDIO transaction.
59071     #define MCP_REG_MDIO_COMM_FAIL_SHIFT                                                             28
59072     #define MCP_REG_MDIO_COMM_START_BUSY                                                             (0x1<<29) // This bit is self clearing. When written to a '1', the currently programmed MDIO transaction will activate. When the operation is complete, this bit will clear and the MI_COMPLETE bit will be set in the emac_status register. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting to prevent un-predictable results. On chip versions before TetonII-B0, on the first read of this register when this bit returns to '0', the DATA value in the same read is invalid. A 2nd read must be executed to get the correct DATA value. This problem is fixed in TetonII, B0 and later.
59073     #define MCP_REG_MDIO_COMM_START_BUSY_SHIFT                                                       29
59074 #define MCP_REG_MDIO_STATUS                                                                          0xe054b0UL //Access:RW   DataWidth:0x20  This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.  Chips: BB_A0 BB_B0 K2
59075     #define MCP_REG_MDIO_STATUS_LINK                                                                 (0x1<<0) // This bit is updated by the MDIO interface if auto-polling is enabled. The value of this bit is reflected by in the main link status bit if auto-polling of the MDIO is enabled.
59076     #define MCP_REG_MDIO_STATUS_LINK_SHIFT                                                           0
59077     #define MCP_REG_MDIO_STATUS__10MB                                                                (0x1<<1) // This bit is manually controlled only. It is not effect at all by the MDIO interface. The value of this setting is not used for TetonII. The mode is completly determined from the mode register settings.
59078     #define MCP_REG_MDIO_STATUS__10MB_SHIFT                                                          1
59079 #define MCP_REG_MDIO_MODE                                                                            0xe054b4UL //Access:RW   DataWidth:0x20  This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.  Chips: BB_A0 BB_B0 K2
59080     #define MCP_REG_MDIO_MODE_UNUSED0                                                                (0x1<<0) //
59081     #define MCP_REG_MDIO_MODE_UNUSED0_SHIFT                                                          0
59082     #define MCP_REG_MDIO_MODE_SHORT_PREAMBLE                                                         (0x1<<1) // If this bit is set, the 32-bit pre-amble will not be generated during auto-polling.
59083     #define MCP_REG_MDIO_MODE_SHORT_PREAMBLE_SHIFT                                                   1
59084     #define MCP_REG_MDIO_MODE_UNUSED1                                                                (0x3<<2) //
59085     #define MCP_REG_MDIO_MODE_UNUSED1_SHIFT                                                          2
59086     #define MCP_REG_MDIO_MODE_AUTO_POLL                                                              (0x1<<4) // This bit enables auto-polling. When auto-polling is on, the START_BUSY bit in the mdio_comm register must not be set. The interface will automatically poll the PHY device and set the LINK bit in the mdio_status register according to bit 2 of the PHY register 1. The PHY address used is that programmed into the PHY_ADDR field of the mdio_comm register.
59087     #define MCP_REG_MDIO_MODE_AUTO_POLL_SHIFT                                                        4
59088     #define MCP_REG_MDIO_MODE_UNUSED2                                                                (0x7<<5) //
59089     #define MCP_REG_MDIO_MODE_UNUSED2_SHIFT                                                          5
59090     #define MCP_REG_MDIO_MODE_BIT_BANG                                                               (0x1<<8) // If this bit is '1', the MDIO interface is controlled by the MDIO, MDIO_OE, and MDC bits in this register. When this bit is '0', the commands in the mdio_cmd register will be executed.
59091     #define MCP_REG_MDIO_MODE_BIT_BANG_SHIFT                                                         8
59092     #define MCP_REG_MDIO_MODE_MDIO                                                                   (0x1<<9) // The write value of this bit controls the drive state of the MDIO pin if the BIT_BANG bit is set. The read value of this bit always reflects the state of the MDIO pin.
59093     #define MCP_REG_MDIO_MODE_MDIO_SHIFT                                                             9
59094     #define MCP_REG_MDIO_MODE_MDIO_OE                                                                (0x1<<10) // Setting this bit to '1' will cause the MDIO pin to drive the value written to the MDIO bit if the BIT_BANG bit is set. Setting this bit to zero will make the MDIO pin an input.
59095     #define MCP_REG_MDIO_MODE_MDIO_OE_SHIFT                                                          10
59096     #define MCP_REG_MDIO_MODE_MDC                                                                    (0x1<<11) // Setting this bit to '1' will cause the MDC pin to high if the BIT_BANG bit is set. . Setting this pin low will cause the MDC pin to drive low if the BIT_BANG bit is set.
59097     #define MCP_REG_MDIO_MODE_MDC_SHIFT                                                              11
59098     #define MCP_REG_MDIO_MODE_MDINT                                                                  (0x1<<12) // The read value of this bit reflects the current state of the MDINT input pin from the Copper PHY. If the interrupt is asserted, this bit will be '0', otherwise, this bit will be '1'.
59099     #define MCP_REG_MDIO_MODE_MDINT_SHIFT                                                            12
59100     #define MCP_REG_MDIO_MODE_EXT_MDINT                                                              (0x1<<13) // The read value of this bit reflects the current state of the External MDINT input pin. If the interrupt is asserted, this bit will be '0', otherwise, this bit will be '1'.
59101     #define MCP_REG_MDIO_MODE_EXT_MDINT_SHIFT                                                        13
59102     #define MCP_REG_MDIO_MODE_UNUSED3                                                                (0x3<<14) //
59103     #define MCP_REG_MDIO_MODE_UNUSED3_SHIFT                                                          14
59104     #define MCP_REG_MDIO_MODE_CLOCK_CNT                                                              (0x3f<<16) // This field controls the MDIO clock speed. The output MDIO clock runs at a frequency equal to CORE_CLK/(2*(CLOCK_CNT+1)). A value of 0 is invalid for this register.
59105     #define MCP_REG_MDIO_MODE_CLOCK_CNT_SHIFT                                                        16
59106     #define MCP_REG_MDIO_MODE_UNUSED4                                                                (0x1ff<<22) //
59107     #define MCP_REG_MDIO_MODE_UNUSED4_SHIFT                                                          22
59108     #define MCP_REG_MDIO_MODE_CLAUSE_45                                                              (0x1<<31) // When set to 1 this bit indicates that the current MDIO transaction will be executed as a Clause 45 transaction. When 0 the transaction is executed as a Clause 22 transaction. Value of this bit also determines the meaning of bits specified in bits [27:0] of the MDIO COMMAND register. This bit must be set to proper value before the link auto-polling function is enabled.
59109     #define MCP_REG_MDIO_MODE_CLAUSE_45_SHIFT                                                        31
59110 #define MCP_REG_MDIO_AUTO_STATUS                                                                     0xe054b8UL //Access:RW   DataWidth:0x20  This register is mirrored from EMAC. Hardware uses EMAC defines, so this register must match EMAC register.  Chips: BB_A0 BB_B0 K2
59111     #define MCP_REG_MDIO_AUTO_STATUS_AUTO_ERR                                                        (0x1<<0) // This bit is set each time an error is detected during a auto poll sequence. The bit is cleared by writing a '1' to this bit position.
59112     #define MCP_REG_MDIO_AUTO_STATUS_AUTO_ERR_SHIFT                                                  0
59113 #define MCP_REG_UCINT_WARP_MODE                                                                      0xe05900UL //Access:RW   DataWidth:0x20  This register controls accesses to 3 WarpCore SERDES microcontroller program memory interfaces.  Chips: BB_A0 BB_B0 K2
59114     #define MCP_REG_UCINT_WARP_MODE_ACCESS_MODE                                                      (0x3<<0) // Enumeration:
59115     #define MCP_REG_UCINT_WARP_MODE_ACCESS_MODE_SHIFT                                                0
59116     #define MCP_REG_UCINT_WARP_MODE_UNUSED0                                                          (0x3<<2) //
59117     #define MCP_REG_UCINT_WARP_MODE_UNUSED0_SHIFT                                                    2
59118     #define MCP_REG_UCINT_WARP_MODE_TARGET                                                           (0x3<<4) // This field controls which of the uC interfaces will be accessed when the access_mode field is set to specific_read or specific_write.
59119     #define MCP_REG_UCINT_WARP_MODE_TARGET_SHIFT                                                     4
59120     #define MCP_REG_UCINT_WARP_MODE_UNUSED1                                                          (0x3<<6) //
59121     #define MCP_REG_UCINT_WARP_MODE_UNUSED1_SHIFT                                                    6
59122     #define MCP_REG_UCINT_WARP_MODE_BYTE_SWAP                                                        (0x1<<8) // This field controls the swapping of the data register bytes when accessing the uC interface.
59123     #define MCP_REG_UCINT_WARP_MODE_BYTE_SWAP_SHIFT                                                  8
59124     #define MCP_REG_UCINT_WARP_MODE_UNUSED2                                                          (0x7f<<9) //
59125     #define MCP_REG_UCINT_WARP_MODE_UNUSED2_SHIFT                                                    9
59126     #define MCP_REG_UCINT_WARP_MODE_DUMMY_CYCLES                                                     (0xff<<16) // This field controls how many dummy ext_mem_clk cycles will be driven when a new target is enabled based on a change in the access_mode field.
59127     #define MCP_REG_UCINT_WARP_MODE_DUMMY_CYCLES_SHIFT                                               16
59128 #define MCP_REG_UCINT_WARP_CLK_DIV                                                                   0xe05904UL //Access:RW   DataWidth:0x20  This register controls the clock speed for the 3 WarpCore SERDES microcontroller program memory interfaces. All clocks are divided from the MCP (1/2 speed) core_clk.  Chips: BB_A0 BB_B0 K2
59129     #define MCP_REG_UCINT_WARP_CLK_DIV_CLOCK_RATE                                                    (0x3<<0) // Enumeration:
59130     #define MCP_REG_UCINT_WARP_CLK_DIV_CLOCK_RATE_SHIFT                                              0
59131 #define MCP_REG_UCINT_WARP_ADDRESS                                                                   0xe05908UL //Access:RW   DataWidth:0x20  This register controls the address offset for the 3 WarpCore SERDES microcontroller program memory interfaces. This register auto-increments after each transaction.  Chips: BB_A0 BB_B0 K2
59132     #define MCP_REG_UCINT_WARP_ADDRESS_ADDRESS                                                       (0xffff<<0) //
59133     #define MCP_REG_UCINT_WARP_ADDRESS_ADDRESS_SHIFT                                                 0
59134 #define MCP_REG_UCINT_WARP_DATA                                                                      0xe0590cUL //Access:RW   DataWidth:0x20  Read/write data register for the 3 WarpCore SERDES microcontroller program memory interfaces. Accessing this register will start the transaction specified in the mode register.  Chips: BB_A0 BB_B0 K2
59135 #define MCP_REG_UCINT_WARP_TARGET_ENABLE                                                             0xe05910UL //Access:RW   DataWidth:0x20  This register controls the level of the uC_enable signal for the 3 WarpCore SERDES microcontroller program memory interfaces.  Chips: BB_A0 BB_B0 K2
59136     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET0                                                 (0x1<<0) // Write this bit as a '1' to set ext_uc_enable for target 0.
59137     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET0_SHIFT                                           0
59138     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET1                                                 (0x1<<1) // Write this bit as a '1' to set ext_uc_enable for target 1.
59139     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET1_SHIFT                                           1
59140     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET2                                                 (0x1<<2) // Write this bit as a '1' to set ext_uc_enable for target 2.
59141     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_SET2_SHIFT                                           2
59142     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED0                                                 (0x1f<<3) //
59143     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED0_SHIFT                                           3
59144     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR0                                                 (0x1<<8) // Write this bit as a '1' to clear ext_uc_enable for target 0.
59145     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR0_SHIFT                                           8
59146     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR1                                                 (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable for target 1.
59147     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR1_SHIFT                                           9
59148     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR2                                                 (0x1<<10) // Write this bit as a '1' to clear ext_uc_enable for target 2.
59149     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_EN_CLR2_SHIFT                                           10
59150     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED1                                                 (0x1f<<11) //
59151     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UNUSED1_SHIFT                                           11
59152     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE0                                              (0x1<<16) // Current status of ext_uc_enable for target 0.
59153     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE0_SHIFT                                        16
59154     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE1                                              (0x1<<17) // Current status of ext_uc_enable for target 1.
59155     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE1_SHIFT                                        17
59156     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE2                                              (0x1<<18) // Current status of ext_uc_enable for target 2.
59157     #define MCP_REG_UCINT_WARP_TARGET_ENABLE_UC_ENABLE2_SHIFT                                        18
59158 #define MCP_REG_UCINT_PCIE_MODE                                                                      0xe05914UL //Access:RW   DataWidth:0x20  This register controls accesses to 2 PCIE SERDES microcontroller program memory interfaces.  Chips: BB_A0 BB_B0 K2
59159     #define MCP_REG_UCINT_PCIE_MODE_ACCESS_MODE                                                      (0x3<<0) // Enumeration:
59160     #define MCP_REG_UCINT_PCIE_MODE_ACCESS_MODE_SHIFT                                                0
59161     #define MCP_REG_UCINT_PCIE_MODE_UNUSED0                                                          (0x3<<2) //
59162     #define MCP_REG_UCINT_PCIE_MODE_UNUSED0_SHIFT                                                    2
59163     #define MCP_REG_UCINT_PCIE_MODE_TARGET                                                           (0x3<<4) // This field controls which of the uC interfaces will be accessed when the access_mode field is set to specific_read or specific_write.
59164     #define MCP_REG_UCINT_PCIE_MODE_TARGET_SHIFT                                                     4
59165     #define MCP_REG_UCINT_PCIE_MODE_UNUSED1                                                          (0x3<<6) //
59166     #define MCP_REG_UCINT_PCIE_MODE_UNUSED1_SHIFT                                                    6
59167     #define MCP_REG_UCINT_PCIE_MODE_BYTE_SWAP                                                        (0x1<<8) // This field controls the swapping of the data register bytes when accessing the uC interface.
59168     #define MCP_REG_UCINT_PCIE_MODE_BYTE_SWAP_SHIFT                                                  8
59169     #define MCP_REG_UCINT_PCIE_MODE_UNUSED2                                                          (0x7f<<9) //
59170     #define MCP_REG_UCINT_PCIE_MODE_UNUSED2_SHIFT                                                    9
59171     #define MCP_REG_UCINT_PCIE_MODE_DUMMY_CYCLES                                                     (0xff<<16) // This field controls how many dummy ext_mem_clk cycles will be driven when a new target is enabled based on a change in the access_mode field.
59172     #define MCP_REG_UCINT_PCIE_MODE_DUMMY_CYCLES_SHIFT                                               16
59173 #define MCP_REG_UCINT_PCIE_CLK_DIV                                                                   0xe05918UL //Access:RW   DataWidth:0x20  This register controls the clock speed for the 2 PCIE SERDES microcontroller program memory interfaces. All clocks are divided from the MCP (1/2 speed) core_clk.  Chips: BB_A0 BB_B0 K2
59174     #define MCP_REG_UCINT_PCIE_CLK_DIV_CLOCK_RATE                                                    (0x3<<0) // Enumeration:
59175     #define MCP_REG_UCINT_PCIE_CLK_DIV_CLOCK_RATE_SHIFT                                              0
59176 #define MCP_REG_UCINT_PCIE_ADDRESS                                                                   0xe0591cUL //Access:RW   DataWidth:0x20  This register controls the address offset for the 2 PCIE SERDES microcontroller program memory interfaces. This register auto-increments after each transaction.  Chips: BB_A0 BB_B0 K2
59177     #define MCP_REG_UCINT_PCIE_ADDRESS_ADDRESS                                                       (0xffff<<0) //
59178     #define MCP_REG_UCINT_PCIE_ADDRESS_ADDRESS_SHIFT                                                 0
59179 #define MCP_REG_UCINT_PCIE_DATA                                                                      0xe05920UL //Access:RW   DataWidth:0x20  Read/write data register for the 2 PCIE SERDES microcontroller program memory interfaces. Accessing this register will start the transaction specified in the mode register.  Chips: BB_A0 BB_B0 K2
59180 #define MCP_REG_UCINT_PCIE_TARGET_ENABLE                                                             0xe05924UL //Access:RW   DataWidth:0x20  This register controls the level of the uC_enable signal for the 2 PCIE SERDES microcontroller program memory interfaces.  Chips: BB_A0 BB_B0 K2
59181     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET0                                                 (0x1<<0) // Write this bit as a '1' to set ext_uc_enable for target 0.
59182     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET0_SHIFT                                           0
59183     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET1                                                 (0x1<<1) // Write this bit as a '1' to set ext_uc_enable for target 1.
59184     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_SET1_SHIFT                                           1
59185     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UNUSED0                                                 (0x3f<<2) //
59186     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UNUSED0_SHIFT                                           2
59187     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR0                                                 (0x1<<8) // Write this bit as a '1' to clear ext_uc_enable for target 0.
59188     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR0_SHIFT                                           8
59189     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR1                                                 (0x1<<9) // Write this bit as a '1' to clear ext_uc_enable for target 1.
59190     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_EN_CLR1_SHIFT                                           9
59191     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UNUSED1                                                 (0x3f<<10) //
59192     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UNUSED1_SHIFT                                           10
59193     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE0                                              (0x1<<16) // Current status of ext_uc_enable for target 0.
59194     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE0_SHIFT                                        16
59195     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE1                                              (0x1<<17) // Current status of ext_uc_enable for target 1.
59196     #define MCP_REG_UCINT_PCIE_TARGET_ENABLE_UC_ENABLE1_SHIFT                                        17
59197 #define MCP_REG_UCINT_AVS_ADDRESS                                                                    0xe05928UL //Access:RW   DataWidth:0x20  This register controls the address offset for the AVS RBUS program memory interface. This register auto-increments after each transaction.  Chips: BB_A0 BB_B0 K2
59198     #define MCP_REG_UCINT_AVS_ADDRESS_ADDRESS                                                        (0x1ffff<<0) //
59199     #define MCP_REG_UCINT_AVS_ADDRESS_ADDRESS_SHIFT                                                  0
59200 #define MCP_REG_UCINT_AVS_DATA                                                                       0xe0592cUL //Access:RW   DataWidth:0x20  Read/write data register for the AVS microcontroller program memory interfaces. Accessing this register will start the transaction specified in the mode register.  Chips: BB_A0 BB_B0 K2
59201 #define MCP_REG_IMC_COMMAND                                                                          0xe05a00UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59202     #define MCP_REG_IMC_COMMAND_TRANSFER_COUNT                                                       (0x1f<<0) // Number of bytes to be transfered in Read or Write operation. Valid lengths are 0-16.
59203     #define MCP_REG_IMC_COMMAND_TRANSFER_COUNT_SHIFT                                                 0
59204     #define MCP_REG_IMC_COMMAND_UNUSED0                                                              (0x7<<5) //
59205     #define MCP_REG_IMC_COMMAND_UNUSED0_SHIFT                                                        5
59206     #define MCP_REG_IMC_COMMAND_TRANSFER_ADDRESS                                                     (0xf<<8) // Address of initial Data Register for Read or Write operation. If the transfer_count&gt;1, additional bytes will be accessed. Address 0 is DataReg0[7:0], Address 7 is DataReg3[31:24].
59207     #define MCP_REG_IMC_COMMAND_TRANSFER_ADDRESS_SHIFT                                               8
59208     #define MCP_REG_IMC_COMMAND_UNUSED1                                                              (0xf<<12) //
59209     #define MCP_REG_IMC_COMMAND_UNUSED1_SHIFT                                                        12
59210     #define MCP_REG_IMC_COMMAND_IMC_STATUS                                                           (0x3<<16) // Status of current IMC Transaction. 00: No_Op 01: Successful Completion 10: Transaction Pending 10: Error
59211     #define MCP_REG_IMC_COMMAND_IMC_STATUS_SHIFT                                                     16
59212     #define MCP_REG_IMC_COMMAND_UNUSED2                                                              (0x3ff<<18) //
59213     #define MCP_REG_IMC_COMMAND_UNUSED2_SHIFT                                                        18
59214     #define MCP_REG_IMC_COMMAND_OPERATION                                                            (0x3<<28) // Setting these bits starts a I2C Operation 00: No_Op 01: Read 10: Write 11: Flush
59215     #define MCP_REG_IMC_COMMAND_OPERATION_SHIFT                                                      28
59216     #define MCP_REG_IMC_COMMAND_SOFT_RESET                                                           (0x1<<30) // Setting this bit will synchronously reset the entire IMC Block.
59217     #define MCP_REG_IMC_COMMAND_SOFT_RESET_SHIFT                                                     30
59218     #define MCP_REG_IMC_COMMAND_ENABLE                                                               (0x1<<31) // Setting this bit enables the IMC Block
59219     #define MCP_REG_IMC_COMMAND_ENABLE_SHIFT                                                         31
59220 #define MCP_REG_IMC_SLAVE_CONTROL                                                                    0xe05a04UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59221     #define MCP_REG_IMC_SLAVE_CONTROL_SLAVE_ADDRESS                                                  (0xff<<0) // This field sets the address which is sent to the Slave Device as the source/destination for the Read or Write transfer. This is not used during FLUSH operations.
59222     #define MCP_REG_IMC_SLAVE_CONTROL_SLAVE_ADDRESS_SHIFT                                            0
59223     #define MCP_REG_IMC_SLAVE_CONTROL_UNUSED0                                                        (0x1ff<<8) //
59224     #define MCP_REG_IMC_SLAVE_CONTROL_UNUSED0_SHIFT                                                  8
59225     #define MCP_REG_IMC_SLAVE_CONTROL_SLAVE_DEVICE_ID                                                (0x7f<<17) // This field sets the Device ID of the Slave Device. This is a 7-bit field as defined by the I2C spec, but can be written here as 8-bits -- the LSB is ignored.
59226     #define MCP_REG_IMC_SLAVE_CONTROL_SLAVE_DEVICE_ID_SHIFT                                          17
59227 #define MCP_REG_IMC_TIMING0                                                                          0xe05a14UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59228     #define MCP_REG_IMC_TIMING0_SCL_LOW_PERIOD                                                       (0x7ff<<0) // This timing value sets the number of core_clk cycles while SCL is low.
59229     #define MCP_REG_IMC_TIMING0_SCL_LOW_PERIOD_SHIFT                                                 0
59230     #define MCP_REG_IMC_TIMING0_UNUSED0                                                              (0x1f<<11) //
59231     #define MCP_REG_IMC_TIMING0_UNUSED0_SHIFT                                                        11
59232     #define MCP_REG_IMC_TIMING0_SCL_HIGH_PERIOD                                                      (0x7ff<<16) // This timing value sets the number of core_clk cycles while SCL is high.
59233     #define MCP_REG_IMC_TIMING0_SCL_HIGH_PERIOD_SHIFT                                                16
59234 #define MCP_REG_IMC_TIMING1                                                                          0xe05a18UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59235     #define MCP_REG_IMC_TIMING1_START_TO_SCL_LOW                                                     (0x7ff<<0) // This timing value sets the number of core_clk cycles between a START and SCL going low.
59236     #define MCP_REG_IMC_TIMING1_START_TO_SCL_LOW_SHIFT                                               0
59237     #define MCP_REG_IMC_TIMING1_UNUSED0                                                              (0x1f<<11) //
59238     #define MCP_REG_IMC_TIMING1_UNUSED0_SHIFT                                                        11
59239     #define MCP_REG_IMC_TIMING1_DATA_HOLD_TIME                                                       (0x7ff<<16) // This timing value sets the number of core_clk cycles of hold time on SDA after SCL goes low.
59240     #define MCP_REG_IMC_TIMING1_DATA_HOLD_TIME_SHIFT                                                 16
59241 #define MCP_REG_IMC_TIMING2                                                                          0xe05a1cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59242     #define MCP_REG_IMC_TIMING2_STOP_TO_SDA_HIGH                                                     (0x7ff<<0) // This timing value sets the number of core_clk cycles between a STOP and SDA going high.
59243     #define MCP_REG_IMC_TIMING2_STOP_TO_SDA_HIGH_SHIFT                                               0
59244     #define MCP_REG_IMC_TIMING2_UNUSED0                                                              (0x1f<<11) //
59245     #define MCP_REG_IMC_TIMING2_UNUSED0_SHIFT                                                        11
59246     #define MCP_REG_IMC_TIMING2_STOP_TO_START                                                        (0x7ff<<16) // This timing value sets the number of core_clk cycles between a STOP and a START.
59247     #define MCP_REG_IMC_TIMING2_STOP_TO_START_SHIFT                                                  16
59248 #define MCP_REG_IMC_DATAREG0                                                                         0xe05a20UL //Access:RW   DataWidth:0x20  This register is used to store bytes for Read or Write I2C Transactions.  Chips: BB_A0 BB_B0 K2
59249 #define MCP_REG_IMC_DATAREG1                                                                         0xe05a24UL //Access:RW   DataWidth:0x20  This register is used to store bytes for Read or Write I2C Transactions.  Chips: BB_A0 BB_B0 K2
59250 #define MCP_REG_IMC_DATAREG2                                                                         0xe05a28UL //Access:RW   DataWidth:0x20  This register is used to store bytes for Read or Write I2C Transactions.  Chips: BB_A0 BB_B0 K2
59251 #define MCP_REG_IMC_DATAREG3                                                                         0xe05a2cUL //Access:RW   DataWidth:0x20  This register is used to store bytes for Read or Write I2C Transactions.  Chips: BB_A0 BB_B0 K2
59252 #define MCP_REG_M2P_M2P_STATUS                                                                       0xe06100UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59253     #define MCP_REG_M2P_M2P_STATUS_M2P_BUSY                                                          (0x1<<0) // This bit indicates that M2P is currently sending a packet. If this bit is set, no new data should be written to the FIFO memory or to the Header registers. This should be polled until it is clear once a VDM transfer is started before another can begin.
59254     #define MCP_REG_M2P_M2P_STATUS_M2P_BUSY_SHIFT                                                    0
59255     #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_INUSE_ERROR                                               (0x1<<1) // This bit indicates that in In-Use Error has occured. This is generated if a new VDM transfer is started when the m2p_busy bit was already set.
59256     #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_INUSE_ERROR_SHIFT                                         1
59257     #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_OVERFLOW_ERROR                                            (0x1<<2) // This bit indicates that the packet FIFO was overwritten with too much data. The FIFO is designed to hold a max sized packet of 256 bytes.
59258     #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_OVERFLOW_ERROR_SHIFT                                      2
59259     #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_UNDERFLOW_ERROR                                           (0x1<<3) // This bit is set when the Length specified in the VDM header exceeded the amount of data in the Packet FIFO.
59260     #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_UNDERFLOW_ERROR_SHIFT                                     3
59261     #define MCP_REG_M2P_M2P_STATUS_M2P_ZERO_LENGTH_ERROR                                             (0x1<<4) // This bit is set when a packet is transmitted while the VDM Length is set to 0x0.
59262     #define MCP_REG_M2P_M2P_STATUS_M2P_ZERO_LENGTH_ERROR_SHIFT                                       4
59263     #define MCP_REG_M2P_M2P_STATUS_UNUSED0                                                           (0x7<<5) //
59264     #define MCP_REG_M2P_M2P_STATUS_UNUSED0_SHIFT                                                     5
59265     #define MCP_REG_M2P_M2P_STATUS_M2P_DATA_SM                                                       (0x3<<8) // This is the internal State Machine, for debugging purposes only.
59266     #define MCP_REG_M2P_M2P_STATUS_M2P_DATA_SM_SHIFT                                                 8
59267     #define MCP_REG_M2P_M2P_STATUS_UNUSED1                                                           (0x3f<<10) //
59268     #define MCP_REG_M2P_M2P_STATUS_UNUSED1_SHIFT                                                     10
59269     #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_FIFO_STATUS                                               (0x3f<<16) // This is the current count of locations used in the packet FIFO, for debugging.
59270     #define MCP_REG_M2P_M2P_STATUS_M2P_PKT_FIFO_STATUS_SHIFT                                         16
59271 #define MCP_REG_M2P_M2P_COMMAND                                                                      0xe06104UL //Access:W    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59272     #define MCP_REG_M2P_M2P_COMMAND_SEND_PKT_TO_PXP                                                  (0x1<<0) // Setting this bit will transmit the VDM that was already loaded in the packet FIFO.
59273     #define MCP_REG_M2P_M2P_COMMAND_SEND_PKT_TO_PXP_SHIFT                                            0
59274 #define MCP_REG_M2P_M2P_VDM_LENGTH                                                                   0xe06108UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59275     #define MCP_REG_M2P_M2P_VDM_LENGTH_VDM_LENGTH                                                    (0x7f<<0) // This is the length of the VDM packet, in 32-bit DWords. 0x0 is an illegal value. Max sized packet is 256 bytes (0x100).
59276     #define MCP_REG_M2P_M2P_VDM_LENGTH_VDM_LENGTH_SHIFT                                              0
59277 #define MCP_REG_M2P_M2P_PCI_ID                                                                       0xe0610cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59278     #define MCP_REG_M2P_M2P_PCI_ID_PCI_ID                                                            (0xffff<<0) // This is the PCI Target ID field for the VDM Header.
59279     #define MCP_REG_M2P_M2P_PCI_ID_PCI_ID_SHIFT                                                      0
59280 #define MCP_REG_M2P_M2P_VENDOR_ID                                                                    0xe06110UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59281     #define MCP_REG_M2P_M2P_VENDOR_ID_VENDOR_ID                                                      (0xffff<<0) // This is the Vendor ID field for the VDM Header.
59282     #define MCP_REG_M2P_M2P_VENDOR_ID_VENDOR_ID_SHIFT                                                0
59283 #define MCP_REG_M2P_M2P_VQ_ID                                                                        0xe06114UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59284     #define MCP_REG_M2P_M2P_VQ_ID_VQR_ID                                                             (0x1f<<0) // This is the VQ_ID field for the VDM Header.
59285     #define MCP_REG_M2P_M2P_VQ_ID_VQR_ID_SHIFT                                                       0
59286 #define MCP_REG_M2P_M2P_SRC_FID                                                                      0xe06118UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59287     #define MCP_REG_M2P_M2P_SRC_FID_SRC_FID                                                          (0xffff<<0) // This is the SRC_FID field for the VDM Header.
59288     #define MCP_REG_M2P_M2P_SRC_FID_SRC_FID_SHIFT                                                    0
59289 #define MCP_REG_M2P_M2P_ROUTE_TYPE                                                                   0xe0611cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59290     #define MCP_REG_M2P_M2P_ROUTE_TYPE_ROUTE_TYPE                                                    (0x7<<0) // This is the Route/Type field for the VDM Header.
59291     #define MCP_REG_M2P_M2P_ROUTE_TYPE_ROUTE_TYPE_SHIFT                                              0
59292 #define MCP_REG_M2P_M2P_TAG                                                                          0xe06120UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59293     #define MCP_REG_M2P_M2P_TAG_TAG                                                                  (0xff<<0) // This is the Tag field for the VDM Header.
59294     #define MCP_REG_M2P_M2P_TAG_TAG_SHIFT                                                            0
59295 #define MCP_REG_M2P_M2P_VENDOR_DWORD                                                                 0xe06124UL //Access:RW   DataWidth:0x20  This is the Vendor DWord field for the VDM Header.  Chips: BB_A0 BB_B0 K2
59296 #define MCP_REG_M2P_M2P_PATH_ID                                                                      0xe06128UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59297     #define MCP_REG_M2P_M2P_PATH_ID_PATH_ID                                                          (0x1<<0) // This bit selects whether the VDM will be sent to Engine 0 or Engine 1.
59298     #define MCP_REG_M2P_M2P_PATH_ID_PATH_ID_SHIFT                                                    0
59299 #define MCP_REG_M2P_M2P_TX_DATA_FIFO                                                                 0xe0612cUL //Access:W    DataWidth:0x20  Writing to this register will store the data in the Tx FIFO to be sent in the VDM.  Chips: BB_A0 BB_B0 K2
59300 #define MCP_REG_P2M_P2M_STATUS                                                                       0xe06200UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59301     #define MCP_REG_P2M_P2M_STATUS_PKT_HDR_CNT                                                       (0x7f<<0) // This field is a count of the number of Packet Headers currently stored in the P2M FIFO.
59302     #define MCP_REG_P2M_P2M_STATUS_PKT_HDR_CNT_SHIFT                                                 0
59303     #define MCP_REG_P2M_P2M_STATUS_RESERVED1                                                         (0x1ff<<7) // Reserved for future use.
59304     #define MCP_REG_P2M_P2M_STATUS_RESERVED1_SHIFT                                                   7
59305     #define MCP_REG_P2M_P2M_STATUS_PKT_DATA_CNT                                                      (0x1ff<<16) // This field is a count of the number of Packet Data Words currently stored in the P2M FIFO.
59306     #define MCP_REG_P2M_P2M_STATUS_PKT_DATA_CNT_SHIFT                                                16
59307     #define MCP_REG_P2M_P2M_STATUS_RESERVED2                                                         (0x3f<<25) // Reserved for future use.
59308     #define MCP_REG_P2M_P2M_STATUS_RESERVED2_SHIFT                                                   25
59309     #define MCP_REG_P2M_P2M_STATUS_P2M_ATTN_BIT                                                      (0x1<<31) // This bit shows the current status of the P2M Attention signal.
59310     #define MCP_REG_P2M_P2M_STATUS_P2M_ATTN_BIT_SHIFT                                                31
59311 #define MCP_REG_P2M_P2M_CONFIG                                                                       0xe06204UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59312     #define MCP_REG_P2M_P2M_CONFIG_BACKPRESSURE_MODE                                                 (0x1<<0) // Setting this bit will cause the P2M block to assert backpressure to the PXP when the packet FIFO is full. If this bit is cleared, packets arriving when the FIFO is full are discarded.
59313     #define MCP_REG_P2M_P2M_CONFIG_BACKPRESSURE_MODE_SHIFT                                           0
59314     #define MCP_REG_P2M_P2M_CONFIG_DRAIN_MODE                                                        (0x1<<1) // When set, this bit forces P2M to constantly drain the packet FIFO and discard all received packets.
59315     #define MCP_REG_P2M_P2M_CONFIG_DRAIN_MODE_SHIFT                                                  1
59316     #define MCP_REG_P2M_P2M_CONFIG_VID_FILTER_DISCARD                                                (0x1<<2) // When set, this bit will cause any packet that doesn't match one of the two Vendor ID Filters to be discarded. If this bit isn't set, all packets that don't match will be accepted.
59317     #define MCP_REG_P2M_P2M_CONFIG_VID_FILTER_DISCARD_SHIFT                                          2
59318     #define MCP_REG_P2M_P2M_CONFIG_RESERVED                                                          (0x1fffffff<<3) // Reserved for future use.
59319     #define MCP_REG_P2M_P2M_CONFIG_RESERVED_SHIFT                                                    3
59320 #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0                                                            0xe06208UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59321     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_VENDORID                                      (0xffff<<0) // This is the Vendor ID to use for this VID Filter.
59322     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_VENDORID_SHIFT                                0
59323     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_DISCARD                                       (0x1<<16) // When set, this bit causes packets which match this VID Filter to be discarded.
59324     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_DISCARD_SHIFT                                 16
59325     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_ENABLE                                        (0x1<<17) // When set, this VID Filter is enabled.
59326     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_0_VID_FILT_ENABLE_SHIFT                                  17
59327 #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1                                                            0xe0620cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59328     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_VENDORID                                      (0xffff<<0) // This is the Vendor ID to use for this VID Filter.
59329     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_VENDORID_SHIFT                                0
59330     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_DISCARD                                       (0x1<<16) // When set, this bit causes packets which match this VID Filter to be discarded.
59331     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_DISCARD_SHIFT                                 16
59332     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_ENABLE                                        (0x1<<17) // When set, this VID Filter is enabled.
59333     #define MCP_REG_P2M_P2M_VID_FILT_CONFIG_1_VID_FILT_ENABLE_SHIFT                                  17
59334 #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG                                                              0xe06210UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59335     #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_VALUE                                           (0xff<<0) // This is the Tag Value to use in the Filter.
59336     #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_VALUE_SHIFT                                     0
59337     #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_MASK                                            (0xff<<8) // This is the mask value to apply to the Tag for Filtering.
59338     #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_MASK_SHIFT                                      8
59339     #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_DISCARD                                         (0x1<<16) // When set, packets matching the Tag Filter will be discarded.
59340     #define MCP_REG_P2M_P2M_TAG_FILT_CONFIG_TAG_FILT_DISCARD_SHIFT                                   16
59341 #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG                                                           0xe06214UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59342     #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_LENGTH_MIN_VALUE                                      (0x7f<<0) // This is the Minimum VDM Length Value that will be accepted. Packets smaller than this will be discarded. This length is in DWords, as in the VDM Header.
59343     #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_LENGTH_MIN_VALUE_SHIFT                                0
59344     #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_UNUSED0                                               (0x1<<7) //
59345     #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_UNUSED0_SHIFT                                         7
59346     #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_TAG_FILT_MASK                                         (0x7f<<8) // This is the Maximum VDM Length Value that will be accepted. Packets larger than this will be discarded. This length is in DWords, as in the VDM Header.
59347     #define MCP_REG_P2M_P2M_LENGTH_FILT_CONFIG_TAG_FILT_MASK_SHIFT                                   8
59348 #define MCP_REG_P2M_P2M_DISCARD_STAT_VENDORID                                                        0xe06218UL //Access:R    DataWidth:0x20  This statistic counts the number of VDM packets discarded due to VendorID Filtering. Reading this register will clear the statistic.  Chips: BB_A0 BB_B0 K2
59349 #define MCP_REG_P2M_P2M_DISCARD_STAT_TAG                                                             0xe0621cUL //Access:R    DataWidth:0x20  This statistic counts the number of VDM packets discarded due to Tag Filtering. Reading this register will clear the statistic.  Chips: BB_A0 BB_B0 K2
59350 #define MCP_REG_P2M_P2M_DISCARD_STAT_LENGTH                                                          0xe06220UL //Access:R    DataWidth:0x20  This statistic counts the number of VDM packets discarded due to Length Filtering. Reading this register will clear the statistic.  Chips: BB_A0 BB_B0 K2
59351 #define MCP_REG_P2M_P2M_DROP_STAT                                                                    0xe06224UL //Access:R    DataWidth:0x20  This statistic counts the number of VDM packets dropped due to the FIFO being full. This also counts packets being dropped while in Drain mode. Reading this register will clear the statistic.  Chips: BB_A0 BB_B0 K2
59352 #define MCP_REG_P2M_P2M_RCVD_STAT                                                                    0xe06228UL //Access:R    DataWidth:0x20  This statistic counts the number of VDM packets received and passed to the MCP. This does not count packets which were dropped or discarded. Reading this register will clear the statistic.  Chips: BB_A0 BB_B0 K2
59353 #define MCP_REG_P2M_P2M_HDR_SINGLE_REG                                                               0xe0622cUL //Access:R    DataWidth:0x20  Reading this register will give the next 32-bits of the current Header. The first access will give bits [31:0], then [63:32], then [95:64]. The fourth access will give bits [98:96] and will automatically pop the FIFO so that the next access will give data for the next Header in the FIFO. Be sure to always access this register four times to ensure correct behavior.  Chips: BB_A0 BB_B0 K2
59354 #define MCP_REG_P2M_P2M_HDR_FIFO_0                                                                   0xe06230UL //Access:R    DataWidth:0x20  Bits [31:0] of the Header Data.  Chips: BB_A0 BB_B0 K2
59355 #define MCP_REG_P2M_P2M_HDR_FIFO_1                                                                   0xe06234UL //Access:R    DataWidth:0x20  Bits [63:32] of the Header Data.  Chips: BB_A0 BB_B0 K2
59356 #define MCP_REG_P2M_P2M_HDR_FIFO_2                                                                   0xe06238UL //Access:R    DataWidth:0x20  Bits [95:64] of the Header Data.  Chips: BB_A0 BB_B0 K2
59357 #define MCP_REG_P2M_P2M_HDR_FIFO_3                                                                   0xe0623cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59358     #define MCP_REG_P2M_P2M_HDR_FIFO_3_HEADER_3                                                      (0x7<<0) // Bits [98:96] of the Header Data.
59359     #define MCP_REG_P2M_P2M_HDR_FIFO_3_HEADER_3_SHIFT                                                0
59360     #define MCP_REG_P2M_P2M_HDR_FIFO_3_RESERVED                                                      (0x1fffffff<<3) // Reserved for future use.
59361     #define MCP_REG_P2M_P2M_HDR_FIFO_3_RESERVED_SHIFT                                                3
59362 #define MCP_REG_P2M_P2M_DATA_FIFO                                                                    0xe06240UL //Access:R    DataWidth:0x20  32-bit Packet Data.  Chips: BB_A0 BB_B0 K2
59363 #define MCP_REG_P2M_P2M_VDM_LENGTH                                                                   0xe06244UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59364     #define MCP_REG_P2M_P2M_VDM_LENGTH_VDM_LENGTH                                                    (0x7f<<0) // 7-bit Length from VDM Header, in DWords.
59365     #define MCP_REG_P2M_P2M_VDM_LENGTH_VDM_LENGTH_SHIFT                                              0
59366 #define MCP_REG_P2M_P2M_PCI_REQ_ID                                                                   0xe06248UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59367     #define MCP_REG_P2M_P2M_PCI_REQ_ID_PCI_REQ_ID                                                    (0xffff<<0) // 16-bit PCI Requester ID from VDM Header.
59368     #define MCP_REG_P2M_P2M_PCI_REQ_ID_PCI_REQ_ID_SHIFT                                              0
59369 #define MCP_REG_P2M_P2M_VENDOR_ID                                                                    0xe0624cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59370     #define MCP_REG_P2M_P2M_VENDOR_ID_VENDOR_ID                                                      (0xffff<<0) // 16-bit Vendor ID from VDM Header.
59371     #define MCP_REG_P2M_P2M_VENDOR_ID_VENDOR_ID_SHIFT                                                0
59372 #define MCP_REG_P2M_P2M_FID                                                                          0xe06250UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59373     #define MCP_REG_P2M_P2M_FID_FID                                                                  (0xffff<<0) // 16-bit FID from VDM Header.
59374     #define MCP_REG_P2M_P2M_FID_FID_SHIFT                                                            0
59375 #define MCP_REG_P2M_P2M_VENDOR_DWORD                                                                 0xe06254UL //Access:R    DataWidth:0x20  32-bit Vendor Defined DWord from VDM Header. For MCTP, this is the MCTP Transport Header.  Chips: BB_A0 BB_B0 K2
59376 #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS                                                             0xe06258UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59377     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_PATH_ID                                                 (0x1<<0) // This is the Path ID of the PCI Function on which the message arrived.
59378     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_PATH_ID_SHIFT                                           0
59379     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED0                                                 (0x7<<1) //
59380     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED0_SHIFT                                           1
59381     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_ROUTING_FIELD                                           (0x7<<4) // This field is the 3 LSB's of the TLP Type.
59382     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_ROUTING_FIELD_SHIFT                                     4
59383     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED1                                                 (0x1ff<<7) //
59384     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_UNUSED1_SHIFT                                           7
59385     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_TAG                                                     (0xff<<16) // This is the 8-bit Tag from VDM Header.
59386     #define MCP_REG_P2M_P2M_OTHER_HDR_FIELDS_TAG_SHIFT                                               16
59387 #define MCP_REG_CACHE_PIM_NVRAM_BASE                                                                 0xe06300UL //Access:RW   DataWidth:0x20  The start address of the PIM in the NVRAM.  Chips: BB_A0 BB_B0 K2
59388 #define MCP_REG_CACHE_PAGING_ENABLE                                                                  0xe06304UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59389     #define MCP_REG_CACHE_PAGING_ENABLE_ENABLE                                                       (0x1<<0) // If this bit is cleared then the look-up is bypassed and the scratchpad is always accessed with the address that was provided by the MCP. When this bit is changed from 1 to 0, all appropriate status and valid bits are cleared.
59390     #define MCP_REG_CACHE_PAGING_ENABLE_ENABLE_SHIFT                                                 0
59391 #define MCP_REG_CACHE_FETCH_COMPLETION                                                               0xe06308UL //Access:W    DataWidth:0x20  Any write to this register will signal completion of the page fetch by the expansion ROM engine.  Chips: BB_A0 BB_B0 K2
59392 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0                                                            0xe0630cUL //Access:RW   DataWidth:0x20  Reflects the status of page 0.  Chips: BB_A0 BB_B0 K2
59393     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59394     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_LOCK_SHIFT                                             0
59395     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59396     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_ACTIVE_SHIFT                                           1
59397     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_VALID                                                  (0x1<<2) // The data in this page is valid.
59398     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_VALID_SHIFT                                            2
59399     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59400     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_0_NVRAM_PAGE_OFFSET_SHIFT                                3
59401 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1                                                            0xe06310UL //Access:RW   DataWidth:0x20  Reflects the status of page 1.  Chips: BB_A0 BB_B0 K2
59402     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59403     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_LOCK_SHIFT                                             0
59404     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59405     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_ACTIVE_SHIFT                                           1
59406     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_VALID                                                  (0x1<<2) // The data in this page is valid.
59407     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_VALID_SHIFT                                            2
59408     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59409     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_1_NVRAM_PAGE_OFFSET_SHIFT                                3
59410 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2                                                            0xe06314UL //Access:RW   DataWidth:0x20  Reflects the status of page 2.  Chips: BB_A0 BB_B0 K2
59411     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59412     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_LOCK_SHIFT                                             0
59413     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59414     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_ACTIVE_SHIFT                                           1
59415     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_VALID                                                  (0x1<<2) // The data in this page is valid.
59416     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_VALID_SHIFT                                            2
59417     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59418     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_2_NVRAM_PAGE_OFFSET_SHIFT                                3
59419 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3                                                            0xe06318UL //Access:RW   DataWidth:0x20  Reflects the status of page 3.  Chips: BB_A0 BB_B0 K2
59420     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59421     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_LOCK_SHIFT                                             0
59422     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59423     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_ACTIVE_SHIFT                                           1
59424     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_VALID                                                  (0x1<<2) // The data in this page is valid.
59425     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_VALID_SHIFT                                            2
59426     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59427     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_3_NVRAM_PAGE_OFFSET_SHIFT                                3
59428 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4                                                            0xe0631cUL //Access:RW   DataWidth:0x20  Reflects the status of page 4.  Chips: BB_A0 BB_B0 K2
59429     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59430     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_LOCK_SHIFT                                             0
59431     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59432     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_ACTIVE_SHIFT                                           1
59433     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_VALID                                                  (0x1<<2) // The data in this page is valid.
59434     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_VALID_SHIFT                                            2
59435     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59436     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_4_NVRAM_PAGE_OFFSET_SHIFT                                3
59437 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5                                                            0xe06320UL //Access:RW   DataWidth:0x20  Reflects the status of page 5.  Chips: BB_A0 BB_B0 K2
59438     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59439     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_LOCK_SHIFT                                             0
59440     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59441     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_ACTIVE_SHIFT                                           1
59442     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_VALID                                                  (0x1<<2) // The data in this page is valid.
59443     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_VALID_SHIFT                                            2
59444     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59445     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_5_NVRAM_PAGE_OFFSET_SHIFT                                3
59446 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6                                                            0xe06324UL //Access:RW   DataWidth:0x20  Reflects the status of page 6.  Chips: BB_A0 BB_B0 K2
59447     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59448     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_LOCK_SHIFT                                             0
59449     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59450     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_ACTIVE_SHIFT                                           1
59451     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_VALID                                                  (0x1<<2) // The data in this page is valid.
59452     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_VALID_SHIFT                                            2
59453     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59454     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_6_NVRAM_PAGE_OFFSET_SHIFT                                3
59455 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7                                                            0xe06328UL //Access:RW   DataWidth:0x20  Reflects the status of page 7.  Chips: BB_A0 BB_B0 K2
59456     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59457     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_LOCK_SHIFT                                             0
59458     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59459     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_ACTIVE_SHIFT                                           1
59460     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_VALID                                                  (0x1<<2) // The data in this page is valid.
59461     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_VALID_SHIFT                                            2
59462     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59463     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_7_NVRAM_PAGE_OFFSET_SHIFT                                3
59464 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8                                                            0xe0632cUL //Access:RW   DataWidth:0x20  Reflects the status of page 8.  Chips: BB_A0 BB_B0 K2
59465     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59466     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_LOCK_SHIFT                                             0
59467     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59468     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_ACTIVE_SHIFT                                           1
59469     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_VALID                                                  (0x1<<2) // The data in this page is valid.
59470     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_VALID_SHIFT                                            2
59471     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59472     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_8_NVRAM_PAGE_OFFSET_SHIFT                                3
59473 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9                                                            0xe06330UL //Access:RW   DataWidth:0x20  Reflects the status of page 9.  Chips: BB_A0 BB_B0 K2
59474     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_LOCK                                                   (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59475     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_LOCK_SHIFT                                             0
59476     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_ACTIVE                                                 (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59477     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_ACTIVE_SHIFT                                           1
59478     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_VALID                                                  (0x1<<2) // The data in this page is valid.
59479     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_VALID_SHIFT                                            2
59480     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_NVRAM_PAGE_OFFSET                                      (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59481     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_9_NVRAM_PAGE_OFFSET_SHIFT                                3
59482 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10                                                           0xe06334UL //Access:RW   DataWidth:0x20  Reflects the status of page 10.  Chips: BB_A0 BB_B0 K2
59483     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_LOCK                                                  (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59484     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_LOCK_SHIFT                                            0
59485     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_ACTIVE                                                (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59486     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_ACTIVE_SHIFT                                          1
59487     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_VALID                                                 (0x1<<2) // The data in this page is valid.
59488     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_VALID_SHIFT                                           2
59489     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_NVRAM_PAGE_OFFSET                                     (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59490     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_10_NVRAM_PAGE_OFFSET_SHIFT                               3
59491 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11                                                           0xe06338UL //Access:RW   DataWidth:0x20  Reflects the status of page 11.  Chips: BB_A0 BB_B0 K2
59492     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_LOCK                                                  (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59493     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_LOCK_SHIFT                                            0
59494     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_ACTIVE                                                (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59495     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_ACTIVE_SHIFT                                          1
59496     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_VALID                                                 (0x1<<2) // The data in this page is valid.
59497     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_VALID_SHIFT                                           2
59498     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_NVRAM_PAGE_OFFSET                                     (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59499     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_11_NVRAM_PAGE_OFFSET_SHIFT                               3
59500 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12                                                           0xe0633cUL //Access:RW   DataWidth:0x20  Reflects the status of page 12.  Chips: BB_A0 BB_B0 K2
59501     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_LOCK                                                  (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59502     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_LOCK_SHIFT                                            0
59503     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_ACTIVE                                                (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59504     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_ACTIVE_SHIFT                                          1
59505     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_VALID                                                 (0x1<<2) // The data in this page is valid.
59506     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_VALID_SHIFT                                           2
59507     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_NVRAM_PAGE_OFFSET                                     (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59508     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_12_NVRAM_PAGE_OFFSET_SHIFT                               3
59509 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13                                                           0xe06340UL //Access:RW   DataWidth:0x20  Reflects the status of page 13.  Chips: BB_A0 BB_B0 K2
59510     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_LOCK                                                  (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59511     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_LOCK_SHIFT                                            0
59512     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_ACTIVE                                                (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59513     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_ACTIVE_SHIFT                                          1
59514     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_VALID                                                 (0x1<<2) // The data in this page is valid.
59515     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_VALID_SHIFT                                           2
59516     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_NVRAM_PAGE_OFFSET                                     (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59517     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_13_NVRAM_PAGE_OFFSET_SHIFT                               3
59518 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14                                                           0xe06344UL //Access:RW   DataWidth:0x20  Reflects the status of page 14.  Chips: BB_A0 BB_B0 K2
59519     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_LOCK                                                  (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59520     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_LOCK_SHIFT                                            0
59521     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_ACTIVE                                                (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59522     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_ACTIVE_SHIFT                                          1
59523     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_VALID                                                 (0x1<<2) // The data in this page is valid.
59524     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_VALID_SHIFT                                           2
59525     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_NVRAM_PAGE_OFFSET                                     (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59526     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_14_NVRAM_PAGE_OFFSET_SHIFT                               3
59527 #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15                                                           0xe06348UL //Access:RW   DataWidth:0x20  Reflects the status of page 15.  Chips: BB_A0 BB_B0 K2
59528     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_LOCK                                                  (0x1<<0) // If set, this page is treated as part of the static memory. When this bit is set, the valid valid and active bits are ignored and the appropriate CAM page table entry will receive the page address value.
59529     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_LOCK_SHIFT                                            0
59530     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_ACTIVE                                                (0x1<<1) // The data is in use. If the valid bit is clear this bit will be clear too.
59531     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_ACTIVE_SHIFT                                          1
59532     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_VALID                                                 (0x1<<2) // The data in this page is valid.
59533     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_VALID_SHIFT                                           2
59534     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_NVRAM_PAGE_OFFSET                                     (0x1ff<<3) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59535     #define MCP_REG_CACHE_CACHE_CTRL_STATUS_15_NVRAM_PAGE_OFFSET_SHIFT                               3
59536 #define MCP_REG_CACHE_IMG_LOADER_BADDR                                                               0xe0634cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59537     #define MCP_REG_CACHE_IMG_LOADER_BADDR_UNUSED0                                                   (0x3<<0) //
59538     #define MCP_REG_CACHE_IMG_LOADER_BADDR_UNUSED0_SHIFT                                             0
59539     #define MCP_REG_CACHE_IMG_LOADER_BADDR_VALUE                                                     (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Baddr register used in the cache fetch logic. Reset value points to Engine 0.
59540     #define MCP_REG_CACHE_IMG_LOADER_BADDR_VALUE_SHIFT                                               2
59541 #define MCP_REG_CACHE_IMG_LOADER_GADDR                                                               0xe06350UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59542     #define MCP_REG_CACHE_IMG_LOADER_GADDR_UNUSED0                                                   (0x3<<0) //
59543     #define MCP_REG_CACHE_IMG_LOADER_GADDR_UNUSED0_SHIFT                                             0
59544     #define MCP_REG_CACHE_IMG_LOADER_GADDR_VALUE                                                     (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Gaddr register used in the cache fetch logic. Reset value points to Engine 0.
59545     #define MCP_REG_CACHE_IMG_LOADER_GADDR_VALUE_SHIFT                                               2
59546 #define MCP_REG_CACHE_IMG_LOADER_CADDR                                                               0xe06354UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59547     #define MCP_REG_CACHE_IMG_LOADER_CADDR_UNUSED0                                                   (0x3<<0) //
59548     #define MCP_REG_CACHE_IMG_LOADER_CADDR_UNUSED0_SHIFT                                             0
59549     #define MCP_REG_CACHE_IMG_LOADER_CADDR_VALUE                                                     (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Caddr register used in the cache fetch logic. Reset value points to Engine 0.
59550     #define MCP_REG_CACHE_IMG_LOADER_CADDR_VALUE_SHIFT                                               2
59551 #define MCP_REG_CACHE_IMG_LOADER_CDATA                                                               0xe06358UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59552     #define MCP_REG_CACHE_IMG_LOADER_CDATA_UNUSED0                                                   (0x3<<0) //
59553     #define MCP_REG_CACHE_IMG_LOADER_CDATA_UNUSED0_SHIFT                                             0
59554     #define MCP_REG_CACHE_IMG_LOADER_CDATA_VALUE                                                     (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Cdata register used in the cache fetch logic. Reset value points to Engine 0.
59555     #define MCP_REG_CACHE_IMG_LOADER_CDATA_VALUE_SHIFT                                               2
59556 #define MCP_REG_CACHE_IMG_LOADER_CFG                                                                 0xe0635cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59557     #define MCP_REG_CACHE_IMG_LOADER_CFG_UNUSED0                                                     (0x3<<0) //
59558     #define MCP_REG_CACHE_IMG_LOADER_CFG_UNUSED0_SHIFT                                               0
59559     #define MCP_REG_CACHE_IMG_LOADER_CFG_VALUE                                                       (0x7fffff<<2) // This register provides the GRC address of the Expansion ROM Engine Cfg register used in the cache fetch logic. Reset value points to Engine 0.
59560     #define MCP_REG_CACHE_IMG_LOADER_CFG_VALUE_SHIFT                                                 2
59561 #define MCP_REG_CACHE_STAT_HIT_COUNTER                                                               0xe06360UL //Access:RW   DataWidth:0x20  Statistic: Incremented whenever a Pageable-memory instruction hits in the page cache. Will be stuck on all ones.  Chips: BB_A0 BB_B0 K2
59562 #define MCP_REG_CACHE_STAT_MISS_COUNTER                                                              0xe06364UL //Access:RW   DataWidth:0x20  Statistic: Incremented whenever a Pageable-memory instruction misses in the page cache. Will be stuck on all ones.  Chips: BB_A0 BB_B0 K2
59563 #define MCP_REG_CACHE_LAST_PAGE_0                                                                    0xe06368UL //Access:RW   DataWidth:0x20  Stores the values from one of the last 2 pages used.  Chips: BB_A0 BB_B0 K2
59564     #define MCP_REG_CACHE_LAST_PAGE_0_VALID                                                          (0x1<<0) // The data in this register is valid.
59565     #define MCP_REG_CACHE_LAST_PAGE_0_VALID_SHIFT                                                    0
59566     #define MCP_REG_CACHE_LAST_PAGE_0_IS_LAST                                                        (0x1<<1) // If set, this page is the most recently accessed.
59567     #define MCP_REG_CACHE_LAST_PAGE_0_IS_LAST_SHIFT                                                  1
59568     #define MCP_REG_CACHE_LAST_PAGE_0_PAGE_INDEX                                                     (0xf<<2) // Index in the page table associated with this page.
59569     #define MCP_REG_CACHE_LAST_PAGE_0_PAGE_INDEX_SHIFT                                               2
59570     #define MCP_REG_CACHE_LAST_PAGE_0_PAGE_OFFSET                                                    (0x1ff<<6) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59571     #define MCP_REG_CACHE_LAST_PAGE_0_PAGE_OFFSET_SHIFT                                              6
59572 #define MCP_REG_CACHE_LAST_PAGE_1                                                                    0xe0636cUL //Access:RW   DataWidth:0x20  Stores the values from one of the last 2 pages used.  Chips: BB_A0 BB_B0 K2
59573     #define MCP_REG_CACHE_LAST_PAGE_1_VALID                                                          (0x1<<0) // The data in this register is valid.
59574     #define MCP_REG_CACHE_LAST_PAGE_1_VALID_SHIFT                                                    0
59575     #define MCP_REG_CACHE_LAST_PAGE_1_IS_LAST                                                        (0x1<<1) // If set, this page is the most recently accessed.
59576     #define MCP_REG_CACHE_LAST_PAGE_1_IS_LAST_SHIFT                                                  1
59577     #define MCP_REG_CACHE_LAST_PAGE_1_PAGE_INDEX                                                     (0xf<<2) // Index in the page table associated with this page.
59578     #define MCP_REG_CACHE_LAST_PAGE_1_PAGE_INDEX_SHIFT                                               2
59579     #define MCP_REG_CACHE_LAST_PAGE_1_PAGE_OFFSET                                                    (0x1ff<<6) // Offset in the PIM associated with this page. This is added to the pim_nvram_base to get the physical NVRAM address of the page.
59580     #define MCP_REG_CACHE_LAST_PAGE_1_PAGE_OFFSET_SHIFT                                              6
59581 #define MCP_REG_CACHE_PAGE_FETCH_STATE                                                               0xe06370UL //Access:R    DataWidth:0x20  For debug: the cache status  Chips: BB_A0 BB_B0 K2
59582 #define MCP_REG_CACHE_CACHE_ERROR_STATUS                                                             0xe06374UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59583     #define MCP_REG_CACHE_CACHE_ERROR_STATUS_OUT_OF_BOUNDS_READ                                      (0x1<<0) // If set, Paging_enable is clear and read from address &gt; StaticMemorySize + PageableMemorySize
59584     #define MCP_REG_CACHE_CACHE_ERROR_STATUS_OUT_OF_BOUNDS_READ_SHIFT                                0
59585     #define MCP_REG_CACHE_CACHE_ERROR_STATUS_ILLEGAL_FETCH                                           (0x1<<1) // If set, a read attempt to a second page was detected while a page fetch was already in progress.
59586     #define MCP_REG_CACHE_CACHE_ERROR_STATUS_ILLEGAL_FETCH_SHIFT                                     1
59587 #define MCP_REG_NVM_COMMAND                                                                          0xe06400UL //Access:RW   DataWidth:0x20  NVM Command register.  Chips: BB_A0 BB_B0 K2
59588     #define MCP_REG_NVM_COMMAND_RST                                                                  (0x1<<0) // When set, the entire NVM state machine is reset. This bit is self clearing.
59589     #define MCP_REG_NVM_COMMAND_RST_SHIFT                                                            0
59590     #define MCP_REG_NVM_COMMAND_UNUSED0                                                              (0x3<<1) //
59591     #define MCP_REG_NVM_COMMAND_UNUSED0_SHIFT                                                        1
59592     #define MCP_REG_NVM_COMMAND_DONE                                                                 (0x1<<3) // Sequence completion bit that is asserted when the command requested by assertion of the doit bit has completed. done Will be cleared while the command is in progress. done Will stay asserted until doit is reasserted or the done bit is cleared by writing a 1 to the done bit. The done bit is the FLSH_ATTN signal.
59593     #define MCP_REG_NVM_COMMAND_DONE_SHIFT                                                           3
59594     #define MCP_REG_NVM_COMMAND_DOIT                                                                 (0x1<<4) // Command from software to start the defined command. The done bit must be clear before setting this bit. This bit is self clearing and will remain set while the command is active.
59595     #define MCP_REG_NVM_COMMAND_DOIT_SHIFT                                                           4
59596     #define MCP_REG_NVM_COMMAND_WR                                                                   (0x1<<5) // The Write/Not_Read command bit. Set high to execute write or erase.
59597     #define MCP_REG_NVM_COMMAND_WR_SHIFT                                                             5
59598     #define MCP_REG_NVM_COMMAND_ERASE                                                                (0x1<<6) // The erase page/sector command bit. Set high to execute a page/sector erase_cmd. This bit is ignored if the WR bit is clear.
59599     #define MCP_REG_NVM_COMMAND_ERASE_SHIFT                                                          6
59600     #define MCP_REG_NVM_COMMAND_FIRST                                                                (0x1<<7) // This bit is passed to the SEE_FSM or SPI_FSM if the pass_mode bit is set.
59601     #define MCP_REG_NVM_COMMAND_FIRST_SHIFT                                                          7
59602     #define MCP_REG_NVM_COMMAND_LAST                                                                 (0x1<<8) // When this bit is set, the next command sequence will be interpreted as the last one of a burst and any cleanup work will be done. This means that the buffer will be written to flash memory if needed on a write.
59603     #define MCP_REG_NVM_COMMAND_LAST_SHIFT                                                           8
59604     #define MCP_REG_NVM_COMMAND_ADDR_INCR                                                            (0x1<<9) // When this bit is set, the address in the address register will be incremented by 4 (1 word) after the command sequence has finished. Intended to be used for consecutive read or write access eliminating the need to update the address register on each access.
59605     #define MCP_REG_NVM_COMMAND_ADDR_INCR_SHIFT                                                      9
59606     #define MCP_REG_NVM_COMMAND_UNUSED1                                                              (0x3f<<10) //
59607     #define MCP_REG_NVM_COMMAND_UNUSED1_SHIFT                                                        10
59608     #define MCP_REG_NVM_COMMAND_WREN                                                                 (0x1<<16) // The write enable command bit. Set '1' will make flash interface state machine Generate wren_cmd to flash device through SPI interface to set Flash device to be write-enabled. Used for the device with protection function
59609     #define MCP_REG_NVM_COMMAND_WREN_SHIFT                                                           16
59610     #define MCP_REG_NVM_COMMAND_WRDI                                                                 (0x1<<17) // The write disable command bit. Set '1' will make flash interface state machine Generate wrdi_cmd to flash device through SPI interface to set Flash device to be write-disabled. Used for the device with protection function.
59611     #define MCP_REG_NVM_COMMAND_WRDI_SHIFT                                                           17
59612     #define MCP_REG_NVM_COMMAND_ERASE_ALL                                                            (0x1<<18) // The erase all/chip command bit. Set high to execute an all/chip erase_all_cmd. This bit is ignored if the WR bit is clear.
59613     #define MCP_REG_NVM_COMMAND_ERASE_ALL_SHIFT                                                      18
59614     #define MCP_REG_NVM_COMMAND_UNUSED2                                                              (0x1<<19) //
59615     #define MCP_REG_NVM_COMMAND_UNUSED2_SHIFT                                                        19
59616     #define MCP_REG_NVM_COMMAND_RD_ID                                                                (0x1<<20) // The read ID command bit. When set, the flash controller will read the ID register from the external flash device. This is specifically for ST devices. Setting this bit for Atmel devices will give the same results as RD_STATUS.
59617     #define MCP_REG_NVM_COMMAND_RD_ID_SHIFT                                                          20
59618     #define MCP_REG_NVM_COMMAND_RD_STATUS                                                            (0x1<<21) // The read status command bit. When set, the flash controller will read the status register from the external flash device
59619     #define MCP_REG_NVM_COMMAND_RD_STATUS_SHIFT                                                      21
59620     #define MCP_REG_NVM_COMMAND_MODE_256                                                             (0x1<<22) // The 256B page size mode disable bit. A 256 byte page mode has been added to the block. This mode is normally on. The mode helps convert a 264B page Atmel part to act more like a 256B page part. For reads, the controller transparently closes the page after byte location 0xFF and opens the next page. For writes, it is the FW or SW responsiblity to close the page at 0xFF and start a new operation on the next page. When this bit is written as '1' when the FIRST bit is set, the 256B page mode is disabled for the next operation. It is self-clearing when both the LAST bit is set and the DONE bit is asserted. Effects Atmel only. No effect with ST devices.
59621     #define MCP_REG_NVM_COMMAND_MODE_256_SHIFT                                                       22
59622 #define MCP_REG_NVM_STATUS                                                                           0xe06404UL //Access:R    DataWidth:0x20  NVM Status register.  Chips: BB_A0 BB_B0 K2
59623     #define MCP_REG_NVM_STATUS_SPI_FSM_STATE                                                         (0x3f<<0) // Enumeration:
59624     #define MCP_REG_NVM_STATUS_SPI_FSM_STATE_SHIFT                                                   0
59625 #define MCP_REG_NVM_WRITE                                                                            0xe06408UL //Access:RW   DataWidth:0x20  NVM data write register.  Chips: BB_A0 BB_B0 K2
59626 #define MCP_REG_NVM_ADDR                                                                             0xe0640cUL //Access:RW   DataWidth:0x20  NVM address register.  Chips: BB_A0 BB_B0 K2
59627     #define MCP_REG_NVM_ADDR_NVM_ADDR_VALUE                                                          (0xffffff<<0) // 24 bit address value used in read, write and erase operations. When in bit-bang mode, the bottom 6 bits control the output enable for each pin.
59628     #define MCP_REG_NVM_ADDR_NVM_ADDR_VALUE_SHIFT                                                    0
59629 #define MCP_REG_NVM_READ                                                                             0xe06410UL //Access:R    DataWidth:0x20  NVM data read register.  Chips: BB_A0 BB_B0 K2
59630 #define MCP_REG_NVM_CFG1                                                                             0xe06414UL //Access:RW   DataWidth:0x20  NVM configuration one register.  Chips: BB_A0 BB_B0 K2
59631     #define MCP_REG_NVM_CFG1_FLASH_MODE                                                              (0x1<<0) // Legacy strap_value[1]. Read only. Set based on new strap values to indicate either Atmel o
59632     #define MCP_REG_NVM_CFG1_FLASH_MODE_SHIFT                                                        0
59633     #define MCP_REG_NVM_CFG1_BUFFER_MODE                                                             (0x1<<1) // Legacy strap_value[0]. Read only. Set based on new strap values to indicate either Atmel or ST.
59634     #define MCP_REG_NVM_CFG1_BUFFER_MODE_SHIFT                                                       1
59635     #define MCP_REG_NVM_CFG1_PASS_MODE                                                               (0x1<<2) // Enable pass-thru mode to the byte level SPI state machine. When this mode is enabled, the controller can send/recieve single bytes at the SPI level. All upper level functions of the controller state machine are disabled.
59636     #define MCP_REG_NVM_CFG1_PASS_MODE_SHIFT                                                         2
59637     #define MCP_REG_NVM_CFG1_BITBANG_MODE                                                            (0x1<<3) // Enable bit-bang mode to control pins.
59638     #define MCP_REG_NVM_CFG1_BITBANG_MODE_SHIFT                                                      3
59639     #define MCP_REG_NVM_CFG1_STATUS_BIT                                                              (0x7<<4) // Bit offset in status command response to interpret as the "ready" flag. For Atmel, this defaults to 3'h7. For ST, this defaults to 3'h0. NOTE: For ST, the status value of 1'b0 means "ready". For Atmel, the status value of 1 means "ready". This is automatically interpreted by hardware. This value is self-configured on reset based on the strap values. It can be overriden.
59640     #define MCP_REG_NVM_CFG1_STATUS_BIT_SHIFT                                                        4
59641     #define MCP_REG_NVM_CFG1_SPI_CLK_DIV                                                             (0xf<<7) // Divisor used to create all "1x" time for all Flash Interface I/O pin timing definition A value of 0 means that SCLK will be 1/2 of core_clk [f(SCLK) = f(CLK)/2]. The equation to calculate the Flash clock frequency for SCLK is: f(SCLK) = f(CLK)/((spi_clk_div + 1) * 2).
59642     #define MCP_REG_NVM_CFG1_SPI_CLK_DIV_SHIFT                                                       7
59643     #define MCP_REG_NVM_CFG1_SEE_CLK_DIV                                                             (0x7ff<<11) // Legacy value. Read only.
59644     #define MCP_REG_NVM_CFG1_SEE_CLK_DIV_SHIFT                                                       11
59645     #define MCP_REG_NVM_CFG1_UNUSED0                                                                 (0x1<<22) //
59646     #define MCP_REG_NVM_CFG1_UNUSED0_SHIFT                                                           22
59647     #define MCP_REG_NVM_CFG1_STRAP_CONTROL_0                                                         (0x1<<23) // Legacy strap_control[1] bit. Read only set to 1, indicating FLASH has already been configured.
59648     #define MCP_REG_NVM_CFG1_STRAP_CONTROL_0_SHIFT                                                   23
59649     #define MCP_REG_NVM_CFG1_PROTECT_MODE                                                            (0x1<<24) // Legacy strap_value[2]. Read only. Set based on new strap values to indicate either Atmel or ST.
59650     #define MCP_REG_NVM_CFG1_PROTECT_MODE_SHIFT                                                      24
59651     #define MCP_REG_NVM_CFG1_FLASH_SIZE                                                              (0x1<<25) // Legacy strap_value[3]. Read only. Set based on new strap values to indicate either Atmel or ST.
59652     #define MCP_REG_NVM_CFG1_FLASH_SIZE_SHIFT                                                        25
59653     #define MCP_REG_NVM_CFG1_FW_USTRAP_1                                                             (0x1<<26) // Legacy strap_value[1]. Read only. Set based on new strap values to indicate either Atmel or ST.
59654     #define MCP_REG_NVM_CFG1_FW_USTRAP_1_SHIFT                                                       26
59655     #define MCP_REG_NVM_CFG1_FW_USTRAP_0                                                             (0x1<<27) // Legacy strap_value[0]. Read only. Set based on new strap values to indicate either Atmel or ST.
59656     #define MCP_REG_NVM_CFG1_FW_USTRAP_0_SHIFT                                                       27
59657     #define MCP_REG_NVM_CFG1_FW_USTRAP_2                                                             (0x1<<28) // Legacy strap_value[2]. Read only. Set based on new strap values to indicate either Atmel or ST.
59658     #define MCP_REG_NVM_CFG1_FW_USTRAP_2_SHIFT                                                       28
59659     #define MCP_REG_NVM_CFG1_FW_USTRAP_3                                                             (0x1<<29) // Legacy strap_value[3]. Read only. Set based on new strap values to indicate either Atmel or ST.
59660     #define MCP_REG_NVM_CFG1_FW_USTRAP_3_SHIFT                                                       29
59661     #define MCP_REG_NVM_CFG1_FW_FLASH_TYPE_EN                                                        (0x1<<30) // Legacy strap_control[1] bit. Read only set to 1, indicating FLASH has already been configured.This register has no hardware function, but can be modified by firmware.
59662     #define MCP_REG_NVM_CFG1_FW_FLASH_TYPE_EN_SHIFT                                                  30
59663     #define MCP_REG_NVM_CFG1_COMPAT_BYPASSS                                                          (0x1<<31) // Legacy bit. Acts as dummy R/W bit.
59664     #define MCP_REG_NVM_CFG1_COMPAT_BYPASSS_SHIFT                                                    31
59665 #define MCP_REG_NVM_CFG2                                                                             0xe06418UL //Access:RW   DataWidth:0x20  NVM configuration two register.  Chips: BB_A0 BB_B0 K2
59666     #define MCP_REG_NVM_CFG2_ERASE_CMD                                                               (0xff<<0) // Flash block erase command. "ready" status will be polled for after this command. Reset value is 0x20h if flash_mode=1, 0x81h if buffer_mode=1, and 0xd8h if protect_mode=1.
59667     #define MCP_REG_NVM_CFG2_ERASE_CMD_SHIFT                                                         0
59668     #define MCP_REG_NVM_CFG2_CSB_W                                                                   (0xff<<8) // Controls the delay from the CSB assertion to the first clock and from the last clock to the CSB deassertion. commands. Reset value is 0x1e in Legacy ST mode, 0x58 in Legacy Atmel mode, and 0x8 in Auto mode.
59669     #define MCP_REG_NVM_CFG2_CSB_W_SHIFT                                                             8
59670     #define MCP_REG_NVM_CFG2_STATUS_CMD                                                              (0xff<<16) // Flash status command. This command is used to poll the "ready" status of the flash part after many of the commands. Reset value is 0x9Fh if flash_mode=1, 0x57h if buffer_mode=1, and 0x5h if protect_mode =1.
59671     #define MCP_REG_NVM_CFG2_STATUS_CMD_SHIFT                                                        16
59672     #define MCP_REG_NVM_CFG2_READ_ID_CMD                                                             (0xff<<24) // Flash Read ID register command. This command is used to read the ID register from ST devices. Reset value depends on strap values. (0x57 for Atmel; 0x9f for ST/Numonyx/Macronix/Winbond)
59673     #define MCP_REG_NVM_CFG2_READ_ID_CMD_SHIFT                                                       24
59674 #define MCP_REG_NVM_CFG3                                                                             0xe0641cUL //Access:RW   DataWidth:0x20  NVM configuration three register.  Chips: BB_A0 BB_B0 K2
59675     #define MCP_REG_NVM_CFG3_BUFFER_RD_CMD                                                           (0xff<<0) // Transfer flash device page to its internal buffer command. For Atmel devices, this command is issued automatically upon the "FIRST" write. It is not issued for ST devices since they automatically do this operation internally. (0x53 for Atmel; 0x53 for ST)
59676     #define MCP_REG_NVM_CFG3_BUFFER_RD_CMD_SHIFT                                                     0
59677     #define MCP_REG_NVM_CFG3_WRITE_CMD                                                               (0xff<<8) // Command to write one byte to the flash array or SSRAM buffer, depending on the value of buffer_mode. If BUFFER_MODE is not active, then this command will poll for "ready" status when complete. For SEEPROM (flash_mode=0), this is SEEPROM write command. Bit[10:9] is address bit A1 and A0 of SEEPROM. User should modify those two bits base on the value of A1 and A0 assigned to this SEEPROM device. Reset value is 0x10 if flash_mode=1, 0x83 if buffer_mode=1, and 0x2 if protect_mode=1, 0xA0 otherwise.
59678     #define MCP_REG_NVM_CFG3_WRITE_CMD_SHIFT                                                         8
59679     #define MCP_REG_NVM_CFG3_FAST_READ_CMD                                                           (0xff<<16) // This is the fast read command. This command is used in Fast ST Mode. Following this command, any number of bytes may be read up to the end of the flash memory. This command is similar to the read command, but with an additional 8b of dummy read between the command/address and the first data read response.
59680     #define MCP_REG_NVM_CFG3_FAST_READ_CMD_SHIFT                                                     16
59681     #define MCP_REG_NVM_CFG3_READ_CMD                                                                (0xff<<24) // This is the flash/seeprom read command. Following this command, any number of bytes may be read up to the end of the flash memory. For SEEPROM (flash_mode=0), this is SEEPROM read command. Bit[26:25] is address bit A1 and A0 of SEEPROM. User should modify those two bits base on the value of A1 and A0 assigned to this SEEPROM device. Reset value is 0xFF if flash_mode=1, 0x68 if buffer_mode=1, 0x3 if protect_mode=1, and 0xA1 otherwise.
59682     #define MCP_REG_NVM_CFG3_READ_CMD_SHIFT                                                          24
59683 #define MCP_REG_NVM_SW_ARB                                                                           0xe06420UL //Access:RW   DataWidth:0x20  SPLIT: NVM arbitration register. This register provides aribtration resoures for both functions. The register is split, so arbitration depends on what function you are accessing as.  Chips: BB_A0 BB_B0 K2
59684     #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET0                                                          (0x1<<0) // Set Software Arbitration request Bit 0. This bit is set by writing a '1' to this bit position.
59685     #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET0_SHIFT                                                    0
59686     #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET1                                                          (0x1<<1) // Set Software Arbitration request Bit 1. This bit is set by writing a '1' to this bit position.
59687     #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET1_SHIFT                                                    1
59688     #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET2                                                          (0x1<<2) // Set Software Arbitration request Bit 2. This bit is set by writing a '1' to this bit position.
59689     #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET2_SHIFT                                                    2
59690     #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET3                                                          (0x1<<3) // Set Software Arbitration request Bit 3. This bit is set by writing a '1' to this bit position.
59691     #define MCP_REG_NVM_SW_ARB_ARB_REQ_SET3_SHIFT                                                    3
59692     #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR0                                                          (0x1<<4) // Write this bit as a '1' to clear req0 bit.
59693     #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR0_SHIFT                                                    4
59694     #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR1                                                          (0x1<<5) // Write this bit as a '1' to clear req1 bit.
59695     #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR1_SHIFT                                                    5
59696     #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR2                                                          (0x1<<6) // Write this bit as a '1' to clear req2 bit.
59697     #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR2_SHIFT                                                    6
59698     #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR3                                                          (0x1<<7) // Write this bit as a '1' to clear req3 bit.
59699     #define MCP_REG_NVM_SW_ARB_ARB_REQ_CLR3_SHIFT                                                    7
59700     #define MCP_REG_NVM_SW_ARB_ARB_ARB0                                                              (0x1<<8) // when REQ0 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB0 must be written to clear this bit. At that point, the next Arb bit will read as 1. At any time, only one of the ARB[7:0] bits will be read as a 1. Arb0 has highest priority, and Arb7 has lowest priority.
59701     #define MCP_REG_NVM_SW_ARB_ARB_ARB0_SHIFT                                                        8
59702     #define MCP_REG_NVM_SW_ARB_ARB_ARB1                                                              (0x1<<9) // when REQ1 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB1 must be written to clear this bit.
59703     #define MCP_REG_NVM_SW_ARB_ARB_ARB1_SHIFT                                                        9
59704     #define MCP_REG_NVM_SW_ARB_ARB_ARB2                                                              (0x1<<10) // when REQ2 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB2 must be written to clear this bit.
59705     #define MCP_REG_NVM_SW_ARB_ARB_ARB2_SHIFT                                                        10
59706     #define MCP_REG_NVM_SW_ARB_ARB_ARB3                                                              (0x1<<11) // when REQ3 arbitration is won, this bit will be read as 1, when an operation is complete, then the CLR_ARB3 must be written to clear this bit.
59707     #define MCP_REG_NVM_SW_ARB_ARB_ARB3_SHIFT                                                        11
59708     #define MCP_REG_NVM_SW_ARB_REQ0                                                                  (0x1<<12) // This is the current status of requester 0. When this bit is one, it means that REQ_SET0 has been set since REQ_CLR0.
59709     #define MCP_REG_NVM_SW_ARB_REQ0_SHIFT                                                            12
59710     #define MCP_REG_NVM_SW_ARB_REQ1                                                                  (0x1<<13) // This is the current status of requester 1. When this bit is one, it means that REQ_SET1 has been set since REQ_CLR1.
59711     #define MCP_REG_NVM_SW_ARB_REQ1_SHIFT                                                            13
59712     #define MCP_REG_NVM_SW_ARB_REQ2                                                                  (0x1<<14) // This is the current status of requester 2. When this bit is one, it means that REQ_SET2 has been set since REQ_CLR2.
59713     #define MCP_REG_NVM_SW_ARB_REQ2_SHIFT                                                            14
59714     #define MCP_REG_NVM_SW_ARB_REQ3                                                                  (0x1<<15) // This is the current status of requester 3. When this bit is one, it means that REQ_SET3 has been set since REQ_CLR3.
59715     #define MCP_REG_NVM_SW_ARB_REQ3_SHIFT                                                            15
59716 #define MCP_REG_NVM_JEDEC_ID                                                                         0xe06424UL //Access:R    DataWidth:0x20  NVM configuration three register.  Chips: BB_A0 BB_B0 K2
59717     #define MCP_REG_NVM_JEDEC_ID_EXTENDED_DEVICE_INFO_LENGTH                                         (0xff<<0) // Length of extended device info to follow.
59718     #define MCP_REG_NVM_JEDEC_ID_EXTENDED_DEVICE_INFO_LENGTH_SHIFT                                   0
59719     #define MCP_REG_NVM_JEDEC_ID_DEVICE_ID                                                           (0xffff<<8) // Device ID: Memory type = device_id[15:8] Size = device_id[7:0]
59720     #define MCP_REG_NVM_JEDEC_ID_DEVICE_ID_SHIFT                                                     8
59721     #define MCP_REG_NVM_JEDEC_ID_MANUFACTURE_ID                                                      (0xff<<24) // JEDEC manufacturer ID. Adesto/Atmel: 0x1F Macronix: 0xC2 Micron/Numonyx/St: 0x20 Winbond: 0xEF
59722     #define MCP_REG_NVM_JEDEC_ID_MANUFACTURE_ID_SHIFT                                                24
59723 #define MCP_REG_NVM_CFG5                                                                             0xe06428UL //Access:RW   DataWidth:0x20  NVM write1 configuration register.  Chips: BB_A0 BB_B0 K2
59724     #define MCP_REG_NVM_CFG5_WREN_CMD                                                                (0xff<<0) // Flash write enable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface To flash device, and make the flash device write-enabled.
59725     #define MCP_REG_NVM_CFG5_WREN_CMD_SHIFT                                                          0
59726     #define MCP_REG_NVM_CFG5_WRDI_CMD                                                                (0xff<<8) // Flash write disable command when device with protection function is used. This command will be issued by the flash interface state machine through SPI interface To flash device, and make the flash device write-disabled.
59727     #define MCP_REG_NVM_CFG5_WRDI_CMD_SHIFT                                                          8
59728     #define MCP_REG_NVM_CFG5_ERASE_ALL_CMD                                                           (0xff<<16) // Flash block erase all command. "ready" status will be polled for after this command. nvm_command.DONE will be asserted when chip erase has completed.
59729     #define MCP_REG_NVM_CFG5_ERASE_ALL_CMD_SHIFT                                                     16
59730     #define MCP_REG_NVM_CFG5_UNUSED0                                                                 (0x3f<<24) //
59731     #define MCP_REG_NVM_CFG5_UNUSED0_SHIFT                                                           24
59732     #define MCP_REG_NVM_CFG5_USE_BUFFER                                                              (0x1<<30) // When set to 1, write operations to Flash will use an internal 4KB sector buffer. Some Flash (Macronix, Winbond) only support PageProgram, which requires the Flash to be erased prior to programming. To make write operations identical across Flash devices, a buffer was added to store the sector data prior to an internally generated erase and then all data is written back to Flash including the write modifications. When cleared to 0, the buffer is unused.
59733     #define MCP_REG_NVM_CFG5_USE_BUFFER_SHIFT                                                        30
59734     #define MCP_REG_NVM_CFG5_USE_LEGACY_SPI_FSM                                                      (0x1<<31) // Set to 1 to use legacy/previous flsh_spi_fsm. Clear to 0 to use latest flsh_spi_fsm.
59735     #define MCP_REG_NVM_CFG5_USE_LEGACY_SPI_FSM_SHIFT                                                31
59736 #define MCP_REG_NVM_CFG4                                                                             0xe0642cUL //Access:RW   DataWidth:0x20  NVM configuration four register.  Chips: BB_A0 BB_B0 K2
59737     #define MCP_REG_NVM_CFG4_FLASH_SIZE                                                              (0x7<<0) // Size of the external flash device. This information is not used by FLSH hardware. It is only used by software. This value is self-configured on reset based on the external device.
59738     #define MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT                                                        0
59739     #define MCP_REG_NVM_CFG4_FLASH_VENDOR                                                            (0x1<<3) // This bit is self-configured on reset based on the strap values. It can be overriden.
59740     #define MCP_REG_NVM_CFG4_FLASH_VENDOR_SHIFT                                                      3
59741     #define MCP_REG_NVM_CFG4_MODE_256_EMPTY_BIT_LOC                                                  (0x3<<4) // Bit location for hardware to insert an empty address bit when MODE_256 is not set with Atmel devices. This value is self-configured on reset based on the external device. NOTE: Max Atmel device size is 64 Mbit due to different bus protocols.
59742     #define MCP_REG_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_SHIFT                                            4
59743     #define MCP_REG_NVM_CFG4_STATUS_BIT_POLARITY                                                     (0x1<<6) // This bit determines how the status bit of the device status register is interpreted by hardware. If 0, then 0 means "ready". If 1, then 1 means "ready". For Atmel, this defaults to 1. For ST, this defaults to 0. This value is self-configured on reset based on the strap values. It can be overriden.
59744     #define MCP_REG_NVM_CFG4_STATUS_BIT_POLARITY_SHIFT                                               6
59745     #define MCP_REG_NVM_CFG4_FAST                                                                    (0x1<<7) // Fast Mode. When this bit is set in ST mode, fast read command is used. In Atmel mode, this bit should be set when using the 0xE8 read command. It should be cleared when using the 0x68 read command. This value is self-configured on reset based on the external device.
59746     #define MCP_REG_NVM_CFG4_FAST_SHIFT                                                              7
59747     #define MCP_REG_NVM_CFG4_SI_INPUT_RELAXED_TIMING                                                 (0x1<<8) // When this bit is set, the SI input from the external flash device is latched one cycle later than normal. This bit defaults to 0.
59748     #define MCP_REG_NVM_CFG4_SI_INPUT_RELAXED_TIMING_SHIFT                                           8
59749     #define MCP_REG_NVM_CFG4_PASS_MODE_RELAXED_TIMING                                                (0x1<<9) // When this bit is set, the pass mode data is captured one cycle later than normal. If using pass mode, this bit should be set whenever the si_input_relaxed_timing bit is set. This bit defaults to 0.
59750     #define MCP_REG_NVM_CFG4_PASS_MODE_RELAXED_TIMING_SHIFT                                          9
59751     #define MCP_REG_NVM_CFG4_SR_TURNAROUND                                                           (0x1<<10) // When this bit is set, a turnaround cycle is inserted in between the address and data phases of a status read for Atmel devices. This bit should only be set when the legacy status read command (0x57) is used. This bit defaults to 0.
59752     #define MCP_REG_NVM_CFG4_SR_TURNAROUND_SHIFT                                                     10
59753     #define MCP_REG_NVM_CFG4_READ_DUMMY_CYCLES                                                       (0xf<<11) // This is the number of dummy cycles needed after the address phase before the read data is available for opcode: READ, READ_ID.
59754     #define MCP_REG_NVM_CFG4_READ_DUMMY_CYCLES_SHIFT                                                 11
59755     #define MCP_REG_NVM_CFG4_FAST_READ_DUMMY_CYCLES                                                  (0xf<<15) // This is the number of dummy cycles needed after the address phase before the read data is available for opcode: FAST_READ.
59756     #define MCP_REG_NVM_CFG4_FAST_READ_DUMMY_CYCLES_SHIFT                                            15
59757     #define MCP_REG_NVM_CFG4_SPI_SLOW_CLK_DIV                                                        (0xf<<19) // Slow SCLK used for OPCODEs that cannot be executed using SPI_CLK_DIV. It is also used during startup when no info about Flash device is known. Calculate SCLK frequency using f(SCLK) = f(core_clk)/(2*(SPI_SLOW_CLK_DIV +1)). [Ex: SPI_SLOW_CLK_DIV=0 -&gt; f(SCLK) = f(core_clk)/2]
59758     #define MCP_REG_NVM_CFG4_SPI_SLOW_CLK_DIV_SHIFT                                                  19
59759     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_BUFFER_RD                                                    (0x1<<23) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59760     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_BUFFER_RD_SHIFT                                              23
59761     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_ERASE                                                        (0x1<<24) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59762     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_ERASE_SHIFT                                                  24
59763     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_FAST_READ                                                    (0x1<<25) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59764     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_FAST_READ_SHIFT                                              25
59765     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ                                                         (0x1<<26) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59766     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ_SHIFT                                                   26
59767     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ_ID                                                      (0x1<<27) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59768     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_READ_ID_SHIFT                                                27
59769     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_STATUS                                                       (0x1<<28) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59770     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_STATUS_SHIFT                                                 28
59771     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRDI                                                         (0x1<<29) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59772     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRDI_SHIFT                                                   29
59773     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WREN                                                         (0x1<<30) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59774     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WREN_SHIFT                                                   30
59775     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRITE                                                        (0x1<<31) // Set (=1) to used slow SCLK generated from SPI_SLOW_CLK_DIV for . Clear (=0) to use regular SCLK generated from SPI_CLK_DIV. This value is updated during auto-configuration to optimum value.
59776     #define MCP_REG_NVM_CFG4_SLOW_CLK_4_WRITE_SHIFT                                                  31
59777 #define MCP_REG_NVM_RECONFIG                                                                         0xe06430UL //Access:RW   DataWidth:0x20  NVM re-configuration register.  Chips: BB_A0 BB_B0 K2
59778     #define MCP_REG_NVM_RECONFIG_ORIG_STRAP_VALUE                                                    (0xf<<0) // Strap value from iologic pins. Only bit[0] is used. Bits[3:1] are for future support.
59779     #define MCP_REG_NVM_RECONFIG_ORIG_STRAP_VALUE_SHIFT                                              0
59780     #define MCP_REG_NVM_RECONFIG_RECONFIG_STRAP_VALUE                                                (0xf<<4) // Used by software to numerically encode how the FLSH has been reconfigured. On reset, this register is set to the same value as ORIG_STRAP_VALUE. These bits have no hardware functionality.
59781     #define MCP_REG_NVM_RECONFIG_RECONFIG_STRAP_VALUE_SHIFT                                          4
59782     #define MCP_REG_NVM_RECONFIG_RESERVED                                                            (0x7fffff<<8) // Reserved for future use
59783     #define MCP_REG_NVM_RECONFIG_RESERVED_SHIFT                                                      8
59784     #define MCP_REG_NVM_RECONFIG_RECONFIG_DONE                                                       (0x1<<31) // This bit is 0 on reset. After software finishes reconfiguring FLSH, they will set this bit to 1 to indicate that FLSH has been reconfigured. This bit has no hardware functionality.
59785     #define MCP_REG_NVM_RECONFIG_RECONFIG_DONE_SHIFT                                                 31
59786 #define MCP_REG_ERNGN_EXP_ROM_CTRL                                                                   0xe06800UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59787     #define MCP_REG_ERNGN_EXP_ROM_CTRL_ENA                                                           (0x1<<0) // Enable bit for the expansion ROM engine. When '1', the expansion ROM engine will automatically service expansion ROM requests. When this bit is cleared, the engine will not service a new request and the on chip cpu will have to take over the chores.
59788     #define MCP_REG_ERNGN_EXP_ROM_CTRL_ENA_SHIFT                                                     0
59789     #define MCP_REG_ERNGN_EXP_ROM_CTRL_BFRD                                                          (0x1<<1) // When this bit is set to '1', the expansion ROM engine will utilize the buffered mode address translation mode in the flash controller to adjust the address for flash devices with 264 byte blocks, spaced every 512 bytes.
59790     #define MCP_REG_ERNGN_EXP_ROM_CTRL_BFRD_SHIFT                                                    1
59791     #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED0                                                       (0x3<<2) //
59792     #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED0_SHIFT                                                 2
59793     #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_NUM                                                       (0x3<<4) // Request number to use to arbitrate for expansion ROM access to the flash controller
59794     #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_NUM_SHIFT                                                 4
59795     #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED1                                                       (0x3ff<<6) //
59796     #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED1_SHIFT                                                 6
59797     #define MCP_REG_ERNGN_EXP_ROM_CTRL_STATE                                                         (0x3f<<16) // The current state of expansion ROM engine, for debugging purposes.
59798     #define MCP_REG_ERNGN_EXP_ROM_CTRL_STATE_SHIFT                                                   16
59799     #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED2                                                       (0x3f<<22) //
59800     #define MCP_REG_ERNGN_EXP_ROM_CTRL_UNUSED2_SHIFT                                                 22
59801     #define MCP_REG_ERNGN_EXP_ROM_CTRL_CACHE_VALID                                                   (0x1<<28) // This bit is set to '1' when the cache is valid.
59802     #define MCP_REG_ERNGN_EXP_ROM_CTRL_CACHE_VALID_SHIFT                                             28
59803     #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_TIMEOUT                                                   (0x1<<29) // This bit is set to '1' when an arbitration timeout happens.
59804     #define MCP_REG_ERNGN_EXP_ROM_CTRL_ARB_TIMEOUT_SHIFT                                             29
59805     #define MCP_REG_ERNGN_EXP_ROM_CTRL_READ_TIMEOUT                                                  (0x1<<30) // This bit is set to '1' when a read timeout happens.
59806     #define MCP_REG_ERNGN_EXP_ROM_CTRL_READ_TIMEOUT_SHIFT                                            30
59807     #define MCP_REG_ERNGN_EXP_ROM_CTRL_ACTIVE                                                        (0x1<<31) // This bit is set to '1' when the expansion ROM engine is actively operating on a expansion ROM request.
59808     #define MCP_REG_ERNGN_EXP_ROM_CTRL_ACTIVE_SHIFT                                                  31
59809 #define MCP_REG_ERNGN_EXP_ROM_BADDR                                                                  0xe06804UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59810     #define MCP_REG_ERNGN_EXP_ROM_BADDR_UNUSED0                                                      (0x3<<0) //
59811     #define MCP_REG_ERNGN_EXP_ROM_BADDR_UNUSED0_SHIFT                                                0
59812     #define MCP_REG_ERNGN_EXP_ROM_BADDR_VALUE                                                        (0x3fffff<<2) // Image base address. The expansion ROM engine fetches the values for the expansion ROM interface starting at this base address.
59813     #define MCP_REG_ERNGN_EXP_ROM_BADDR_VALUE_SHIFT                                                  2
59814 #define MCP_REG_ERNGN_EXP_ROM_CFG                                                                    0xe06808UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59815     #define MCP_REG_ERNGN_EXP_ROM_CFG_ARB_TIMEOUT_SHFT                                               (0xf<<0) // Arbitration timeout value. The value of 0x20 is shifted left number of bits determined by this value to determine the number of times the nvm_sw_arb register inside the expansion ROM interface will be polled before giving up on arbitration.
59816     #define MCP_REG_ERNGN_EXP_ROM_CFG_ARB_TIMEOUT_SHFT_SHIFT                                         0
59817     #define MCP_REG_ERNGN_EXP_ROM_CFG_READ_TIMEOUT_SHFT                                              (0xf<<4) // Read timeout value. The value of 0x20 is shifted left number of bits determined by this value to determine the number of core clocks to wait for the expansion ROM interface to complete a single word read before giving up.
59818     #define MCP_REG_ERNGN_EXP_ROM_CFG_READ_TIMEOUT_SHFT_SHIFT                                        4
59819 #define MCP_REG_ERNGN_EXP_ROM_ADR                                                                    0xe0680cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59820     #define MCP_REG_ERNGN_EXP_ROM_ADR_UNUSED0                                                        (0x3<<0) //
59821     #define MCP_REG_ERNGN_EXP_ROM_ADR_UNUSED0_SHIFT                                                  0
59822     #define MCP_REG_ERNGN_EXP_ROM_ADR_ADDRESS                                                        (0x3fffff<<2) // This value is the address requested by the current (or last) PCI ROM Expansion cycle request. When the PCI block detect a decode of the ROM BAR area, it will place the offset from the BAR value in this register and re-try the PCI bus to make the requester wait.
59823     #define MCP_REG_ERNGN_EXP_ROM_ADR_ADDRESS_SHIFT                                                  2
59824     #define MCP_REG_ERNGN_EXP_ROM_ADR_ADDR_SIZE                                                      (0x3<<24) // The size of the PCI BAR rom read request. This value ranges from 1 to 3 dwords
59825     #define MCP_REG_ERNGN_EXP_ROM_ADR_ADDR_SIZE_SHIFT                                                24
59826     #define MCP_REG_ERNGN_EXP_ROM_ADR_ACT_FUNC                                                       (0x1f<<26) // These bits indicate which function is currently accessing the expansion rom.
59827     #define MCP_REG_ERNGN_EXP_ROM_ADR_ACT_FUNC_SHIFT                                                 26
59828     #define MCP_REG_ERNGN_EXP_ROM_ADR_REQ                                                            (0x1<<31) // This bit will be set if there is a pending request for action. This bit is equivalent to the EXP_ROM_ATTN attention word bit.
59829     #define MCP_REG_ERNGN_EXP_ROM_ADR_REQ_SHIFT                                                      31
59830 #define MCP_REG_ERNGN_EXP_ROM_DATA0                                                                  0xe06810UL //Access:R    DataWidth:0x20  This register shows the first dword for the expansion ROM access. This is for debug purposes only.  Chips: BB_A0 BB_B0 K2
59831 #define MCP_REG_ERNGN_EXP_ROM_DATA1                                                                  0xe06814UL //Access:R    DataWidth:0x20  This register shows the second dword for the expansion ROM access. This is for debug purposes only.  Chips: BB_A0 BB_B0 K2
59832 #define MCP_REG_ERNGN_EXP_ROM_DATA2                                                                  0xe06818UL //Access:R    DataWidth:0x20  This register shows the third dword for the expansion ROM access. This is for debug purposes only.  Chips: BB_A0 BB_B0 K2
59833 #define MCP_REG_ERNGN_IMG_LOADER0_BADDR                                                              0xe0681cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59834     #define MCP_REG_ERNGN_IMG_LOADER0_BADDR_UNUSED0                                                  (0x3<<0) //
59835     #define MCP_REG_ERNGN_IMG_LOADER0_BADDR_UNUSED0_SHIFT                                            0
59836     #define MCP_REG_ERNGN_IMG_LOADER0_BADDR_VALUE                                                    (0x3fffff<<2) // Image base address. This register provides the base address of the image in the NVRAM that the Image Loader Engine 0 will use.
59837     #define MCP_REG_ERNGN_IMG_LOADER0_BADDR_VALUE_SHIFT                                              2
59838 #define MCP_REG_ERNGN_IMG_LOADER0_GADDR                                                              0xe06820UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59839     #define MCP_REG_ERNGN_IMG_LOADER0_GADDR_UNUSED0                                                  (0x3<<0) //
59840     #define MCP_REG_ERNGN_IMG_LOADER0_GADDR_UNUSED0_SHIFT                                            0
59841     #define MCP_REG_ERNGN_IMG_LOADER0_GADDR_VALUE                                                    (0xfffffff<<2) // This register provides the GRC address of the internal register where the data from NVRAM will be written. 24:2 will be the GRC address 29:26 will be the GRC function
59842     #define MCP_REG_ERNGN_IMG_LOADER0_GADDR_VALUE_SHIFT                                              2
59843 #define MCP_REG_ERNGN_IMG_LOADER0_CADDR                                                              0xe06824UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59844     #define MCP_REG_ERNGN_IMG_LOADER0_CADDR_UNUSED0                                                  (0x3<<0) //
59845     #define MCP_REG_ERNGN_IMG_LOADER0_CADDR_UNUSED0_SHIFT                                            0
59846     #define MCP_REG_ERNGN_IMG_LOADER0_CADDR_VALUE                                                    (0x7fffff<<2) // This register provides the GRC address of the internal register where the completion data will be written.
59847     #define MCP_REG_ERNGN_IMG_LOADER0_CADDR_VALUE_SHIFT                                              2
59848 #define MCP_REG_ERNGN_IMG_LOADER0_CDATA                                                              0xe06828UL //Access:RW   DataWidth:0x20  This register provides the value of the completion data that will be written to the completion address.  Chips: BB_A0 BB_B0 K2
59849 #define MCP_REG_ERNGN_IMG_LOADER0_CFG                                                                0xe0682cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59850     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED0                                                    (0x3<<0) //
59851     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED0_SHIFT                                              0
59852     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_XFER_SIZE                                                  (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granularity. A maximum of 64KB can be transfered with one command. A read to this register will indicate the current status of the command.
59853     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_XFER_SIZE_SHIFT                                            2
59854     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED1                                                    (0xf<<16) //
59855     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED1_SHIFT                                              16
59856     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BURST_SIZE                                                 (0xf<<20) // These bits are used for setting up the burst size of a single NVRAM arbitration cycle. NVRAM is a shared resource and every master needs to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till the access is relinquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration cycle. For ex. if xfer_size = 4KB and burst_size = 32 words, then the image loader engine will arbitrate to win the access of NVRAM 32 times.
59857     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BURST_SIZE_SHIFT                                           20
59858     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_AUTO_INC                                                   (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
59859     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_AUTO_INC_SHIFT                                             24
59860     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED2                                                    (0x7<<25) //
59861     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_UNUSED2_SHIFT                                              25
59862     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ARB_TO                                                     (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
59863     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ARB_TO_SHIFT                                               28
59864     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_READ_TO                                                    (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
59865     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_READ_TO_SHIFT                                              29
59866     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BUSY                                                       (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
59867     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_BUSY_SHIFT                                                 30
59868     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ACTIVE                                                     (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
59869     #define MCP_REG_ERNGN_IMG_LOADER0_CFG_ACTIVE_SHIFT                                               31
59870 #define MCP_REG_ERNGN_IMG_LOADER1_BADDR                                                              0xe06830UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59871     #define MCP_REG_ERNGN_IMG_LOADER1_BADDR_UNUSED0                                                  (0x3<<0) //
59872     #define MCP_REG_ERNGN_IMG_LOADER1_BADDR_UNUSED0_SHIFT                                            0
59873     #define MCP_REG_ERNGN_IMG_LOADER1_BADDR_VALUE                                                    (0x3fffff<<2) // Image base address. This register provides the base address of the image in the NVRAM that the Image Loader Engine 1 will use.
59874     #define MCP_REG_ERNGN_IMG_LOADER1_BADDR_VALUE_SHIFT                                              2
59875 #define MCP_REG_ERNGN_IMG_LOADER1_GADDR                                                              0xe06834UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59876     #define MCP_REG_ERNGN_IMG_LOADER1_GADDR_UNUSED0                                                  (0x3<<0) //
59877     #define MCP_REG_ERNGN_IMG_LOADER1_GADDR_UNUSED0_SHIFT                                            0
59878     #define MCP_REG_ERNGN_IMG_LOADER1_GADDR_VALUE                                                    (0xfffffff<<2) // This register provides the GRC address of the internal register where the data from NVRAM will be written. 24:2 will be the GRC address 29:26 will be the GRC function
59879     #define MCP_REG_ERNGN_IMG_LOADER1_GADDR_VALUE_SHIFT                                              2
59880 #define MCP_REG_ERNGN_IMG_LOADER1_CADDR                                                              0xe06838UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59881     #define MCP_REG_ERNGN_IMG_LOADER1_CADDR_UNUSED0                                                  (0x3<<0) //
59882     #define MCP_REG_ERNGN_IMG_LOADER1_CADDR_UNUSED0_SHIFT                                            0
59883     #define MCP_REG_ERNGN_IMG_LOADER1_CADDR_VALUE                                                    (0x7fffff<<2) // This register provides the GRC address of the internal register where the completion data will be written.
59884     #define MCP_REG_ERNGN_IMG_LOADER1_CADDR_VALUE_SHIFT                                              2
59885 #define MCP_REG_ERNGN_IMG_LOADER1_CDATA                                                              0xe0683cUL //Access:RW   DataWidth:0x20  This register provides the value of the completion data that will be written to the completion address.  Chips: BB_A0 BB_B0 K2
59886 #define MCP_REG_ERNGN_IMG_LOADER1_CFG                                                                0xe06840UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59887     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED0                                                    (0x3<<0) //
59888     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED0_SHIFT                                              0
59889     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_XFER_SIZE                                                  (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granularity. A maximum of 64KB can be transfered with one command. A read to this register will indicate the current status of the command.
59890     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_XFER_SIZE_SHIFT                                            2
59891     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED1                                                    (0xf<<16) //
59892     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED1_SHIFT                                              16
59893     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BURST_SIZE                                                 (0xf<<20) // These bits are used for setting up the burst size of a single NVRAM arbitration cycle. NVRAM is a shared resource and every master needs to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till the access is relinquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration cycle. For ex. if xfer_size = 4KB and burst_size = 32 words, then the image loader engine will arbitrate to win the access of NVRAM 32 times.
59894     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BURST_SIZE_SHIFT                                           20
59895     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_AUTO_INC                                                   (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
59896     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_AUTO_INC_SHIFT                                             24
59897     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED2                                                    (0x7<<25) //
59898     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_UNUSED2_SHIFT                                              25
59899     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ARB_TO                                                     (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
59900     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ARB_TO_SHIFT                                               28
59901     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_READ_TO                                                    (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
59902     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_READ_TO_SHIFT                                              29
59903     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BUSY                                                       (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
59904     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_BUSY_SHIFT                                                 30
59905     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ACTIVE                                                     (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
59906     #define MCP_REG_ERNGN_IMG_LOADER1_CFG_ACTIVE_SHIFT                                               31
59907 #define MCP_REG_ERNGN_IMG_LOADER2_BADDR                                                              0xe06844UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59908     #define MCP_REG_ERNGN_IMG_LOADER2_BADDR_UNUSED0                                                  (0x3<<0) //
59909     #define MCP_REG_ERNGN_IMG_LOADER2_BADDR_UNUSED0_SHIFT                                            0
59910     #define MCP_REG_ERNGN_IMG_LOADER2_BADDR_VALUE                                                    (0x3fffff<<2) // Image base address. This register provides the base address of the image in the NVRAM that the Image Loader Engine 2 will use.
59911     #define MCP_REG_ERNGN_IMG_LOADER2_BADDR_VALUE_SHIFT                                              2
59912 #define MCP_REG_ERNGN_IMG_LOADER2_GADDR                                                              0xe06848UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59913     #define MCP_REG_ERNGN_IMG_LOADER2_GADDR_UNUSED0                                                  (0x3<<0) //
59914     #define MCP_REG_ERNGN_IMG_LOADER2_GADDR_UNUSED0_SHIFT                                            0
59915     #define MCP_REG_ERNGN_IMG_LOADER2_GADDR_VALUE                                                    (0xfffffff<<2) // This register provides the GRC address of the internal register where the data from NVRAM will be written. 24:2 will be the GRC address 29:26 will be the GRC function
59916     #define MCP_REG_ERNGN_IMG_LOADER2_GADDR_VALUE_SHIFT                                              2
59917 #define MCP_REG_ERNGN_IMG_LOADER2_CADDR                                                              0xe0684cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59918     #define MCP_REG_ERNGN_IMG_LOADER2_CADDR_UNUSED0                                                  (0x3<<0) //
59919     #define MCP_REG_ERNGN_IMG_LOADER2_CADDR_UNUSED0_SHIFT                                            0
59920     #define MCP_REG_ERNGN_IMG_LOADER2_CADDR_VALUE                                                    (0x7fffff<<2) // This register provides the GRC address of the internal register where the completion data will be written.
59921     #define MCP_REG_ERNGN_IMG_LOADER2_CADDR_VALUE_SHIFT                                              2
59922 #define MCP_REG_ERNGN_IMG_LOADER2_CDATA                                                              0xe06850UL //Access:RW   DataWidth:0x20  This register provides the value of the completion data that will be written to the completion address.  Chips: BB_A0 BB_B0 K2
59923 #define MCP_REG_ERNGN_IMG_LOADER2_CFG                                                                0xe06854UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59924     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED0                                                    (0x3<<0) //
59925     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED0_SHIFT                                              0
59926     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_XFER_SIZE                                                  (0x3fff<<2) // These bits indicate the transfer size in 4bytes (word) granularity. A maximum of 64KB can be transfered with one command. A read to this register will indicate the current status of the command.
59927     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_XFER_SIZE_SHIFT                                            2
59928     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED1                                                    (0xf<<16) //
59929     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED1_SHIFT                                              16
59930     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BURST_SIZE                                                 (0xf<<20) // These bits are used for setting up the burst size of a single NVRAM arbitration cycle. NVRAM is a shared resource and every master needs to arbitrate for access to the NVRAM. Once a master wins arbitration, it can keep the NVRAM till the access is relinquished. Using these bits, SW/FW can limit how many words get transferred in a single arbitration cycle. For ex. if xfer_size = 4KB and burst_size = 32 words, then the image loader engine will arbitrate to win the access of NVRAM 32 times.
59931     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BURST_SIZE_SHIFT                                           20
59932     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_AUTO_INC                                                   (0x1<<24) // Setting this bit will cause the GRC address to be incremented by 4bytes for every transfer on the GRC interface for the command.
59933     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_AUTO_INC_SHIFT                                             24
59934     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED2                                                    (0x7<<25) //
59935     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_UNUSED2_SHIFT                                              25
59936     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ARB_TO                                                     (0x1<<28) // This bit indicates that there was a Arbitration timeout on this image loader and all the transfers are invalid
59937     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ARB_TO_SHIFT                                               28
59938     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_READ_TO                                                    (0x1<<29) // This bit indicates that there was a NVRAM Read timeout on this image loader and all the transfers are invalid
59939     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_READ_TO_SHIFT                                              29
59940     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BUSY                                                       (0x1<<30) // This bit indicates that this image loader engine is busy. When this bit is set, the baddr/gaddr/cfg registers should not be written to.
59941     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_BUSY_SHIFT                                                 30
59942     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ACTIVE                                                     (0x1<<31) // This bit indicates that this image loader engine is currently the active master.
59943     #define MCP_REG_ERNGN_IMG_LOADER2_CFG_ACTIVE_SHIFT                                               31
59944 #define MCP_REG_SMBUS_CONFIG                                                                         0xe08000UL //Access:RW   DataWidth:0x20  All registers in the SMB block are shared.  Chips: BB_A0 BB_B0 K2
59945     #define MCP_REG_SMBUS_CONFIG_UNUSED0                                                             (0x7f<<0) //
59946     #define MCP_REG_SMBUS_CONFIG_UNUSED0_SHIFT                                                       0
59947     #define MCP_REG_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR                                                  (0x1<<7) // When this bit is set HW will service the ARP Assign Address command, set the AR_FLAG[1:0] and AV_FLAG[1:0] flags, and program the NIC_SMB_ADDR[1:0] values.
59948     #define MCP_REG_SMBUS_CONFIG_HW_ARP_ASSIGN_ADDR_SHIFT                                            7
59949     #define MCP_REG_SMBUS_CONFIG_ARP_EN0                                                             (0x1<<8) // When this bit is set the SMBUS block will respond to ARP that is it to SMBUS Device Default Address (7'b1100001) and reslove NIC_SMB_ADDR0 using ARP.
59950     #define MCP_REG_SMBUS_CONFIG_ARP_EN0_SHIFT                                                       8
59951     #define MCP_REG_SMBUS_CONFIG_ARP_EN1                                                             (0x1<<9) // When this bit is set the SMBUS block will respond to ARP that is it to SMBUS Device Default Address (7'b1100001) and reslove NIC_SMB_ADDR1 using ARP.
59952     #define MCP_REG_SMBUS_CONFIG_ARP_EN1_SHIFT                                                       9
59953     #define MCP_REG_SMBUS_CONFIG_UNUSED1                                                             (0x3f<<10) //
59954     #define MCP_REG_SMBUS_CONFIG_UNUSED1_SHIFT                                                       10
59955     #define MCP_REG_SMBUS_CONFIG_MASTER_RTRY_CNT                                                     (0xf<<16) // This bit indicates a number of retries in case where SMBUS block acted as a master and lost SMBUS arbitration. HW will retry transaction as many times as specified in this register before it reports lost of arbitration status to the firmware. When this field is 0 firmware will not do any retries but it will report loss of arbitration on the initial attempt.
59956     #define MCP_REG_SMBUS_CONFIG_MASTER_RTRY_CNT_SHIFT                                               16
59957     #define MCP_REG_SMBUS_CONFIG_UNUSED2                                                             (0x3f<<20) //
59958     #define MCP_REG_SMBUS_CONFIG_UNUSED2_SHIFT                                                       20
59959     #define MCP_REG_SMBUS_CONFIG_TIMESTAMP_CNT_EN                                                    (0x1<<26) // When this bit is '1' the TIMESTAMP counter is enabled. When '0' the counter holds its value.
59960     #define MCP_REG_SMBUS_CONFIG_TIMESTAMP_CNT_EN_SHIFT                                              26
59961     #define MCP_REG_SMBUS_CONFIG_PROMISCOUS_MODE                                                     (0x1<<27) // When this bit is '1' the SMBUS block responds to all SMBUS transactions regardless of the slave address.
59962     #define MCP_REG_SMBUS_CONFIG_PROMISCOUS_MODE_SHIFT                                               27
59963     #define MCP_REG_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0                                                   (0x1<<28) // When this bit is '1' the SMBUS block responds to slave address 7'b0000000.
59964     #define MCP_REG_SMBUS_CONFIG_EN_NIC_SMB_ADDR_0_SHIFT                                             28
59965     #define MCP_REG_SMBUS_CONFIG_BIT_BANG_EN                                                         (0x1<<29) // When this bit is '1', the SMBUS block is placed into bit-bang mode. SMBUS interface pins are controlled using Bit-Bang Control Register.
59966     #define MCP_REG_SMBUS_CONFIG_BIT_BANG_EN_SHIFT                                                   29
59967     #define MCP_REG_SMBUS_CONFIG_SMB_EN                                                              (0x1<<30) // When this bit is '1', the SMBUS block is enabled for operation. When set the SMBUS block will abort current transaction in compliance with the SMBUS master and slave behavior at the end of the current transaction and stop responding to the SMBUS master/slave transactions.
59968     #define MCP_REG_SMBUS_CONFIG_SMB_EN_SHIFT                                                        30
59969     #define MCP_REG_SMBUS_CONFIG_RESET                                                               (0x1<<31) // When this bit is set it will reset SMBUS block to its default state.
59970     #define MCP_REG_SMBUS_CONFIG_RESET_SHIFT                                                         31
59971 #define MCP_REG_SMBUS_TIMING_CONFIG                                                                  0xe08004UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59972     #define MCP_REG_SMBUS_TIMING_CONFIG_UNUSED0                                                      (0xff<<0) //
59973     #define MCP_REG_SMBUS_TIMING_CONFIG_UNUSED0_SHIFT                                                0
59974     #define MCP_REG_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME                                              (0xff<<8) // These bits specify the time for which both SMBCLK and SMBDAT must be high before a master can assume that bus is free. Register has 1us resolution. Default is 50us.
59975     #define MCP_REG_SMBUS_TIMING_CONFIG_SMBUS_IDLE_TIME_SHIFT                                        8
59976     #define MCP_REG_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH                                       (0xff<<16) // These bits specify time for which each clock period low time will be stretched when the SMBUS block acts as a slave. Note that a cumulative clock low extend time (TLOW:SEXT) for which slave device is allowed to stretch the clock from the beginning to end of the message (that is from START to STOP) is 25ms. For example, if the message is Block Write transaction 36B long allowed periodic stretch would be 25ms/(9*36) ~= 77us. This is assuming that random slave stretching is not used. Register has 1us resolution.
59977     #define MCP_REG_SMBUS_TIMING_CONFIG_PERIODIC_SLAVE_STRETCH_SHIFT                                 16
59978     #define MCP_REG_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH                                         (0x7f<<24) // These bits specify time for which clock low time will be stretched after each byte (that is ACK bit) when the SMBUS block acts as a slave. This is useful in "legacy mode" to allow firmware time to handle the data. Note that this time contributes to the slave TLOW:SEXT time, that is combined random and periodic slave stretch should not exceed 25ms. Register has 1ms resolution. Default is 25ms.
59979     #define MCP_REG_SMBUS_TIMING_CONFIG_RANDOM_SLAVE_STRETCH_SHIFT                                   24
59980     #define MCP_REG_SMBUS_TIMING_CONFIG_MODE_400                                                     (0x1<<31) // When this bit is set the SMBUS block operates in 400KHz mode. When cleared SMBUS operates in 100KHz mode.
59981     #define MCP_REG_SMBUS_TIMING_CONFIG_MODE_400_SHIFT                                               31
59982 #define MCP_REG_SMBUS_ADDRESS                                                                        0xe08008UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
59983     #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR0                                                      (0x7f<<0) // This is the first SM Bus addresses which will be used to match for incoming messages. This address is also used for ARP that is this is the address that will be resolved using ARP when the ARP function is enabled. When the PROMISCOUS_MODE bit is '1', this value is ignored.
59984     #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR0_SHIFT                                                0
59985     #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0                                                   (0x1<<7) // When this bit is '1' NIC_SMB_ADDR0 will be used as a slave address to match for incoming messages.
59986     #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR0_SHIFT                                             7
59987     #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR1                                                      (0x7f<<8) // This is the second SM Bus addresses which will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value is ignored.
59988     #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR1_SHIFT                                                8
59989     #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1                                                   (0x1<<15) // When this bit is '1' NIC_SMB_ADDR1 will be used as a slave address to match for incoming messages.
59990     #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR1_SHIFT                                             15
59991     #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR2                                                      (0x7f<<16) // This is the third SM Bus addresses which will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value is ignored. 0x0 This address is also used for ARP. The address will be resolved using ARP when the ARP_EN1 bit is set.
59992     #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR2_SHIFT                                                16
59993     #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2                                                   (0x1<<23) // When this bit is '1' NIC_SMB_ADDR2 will be used as a slave address to match for incoming messages.
59994     #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR2_SHIFT                                             23
59995     #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR3                                                      (0x7f<<24) // This is the fourth SM Bus addresses which will be used to match for incoming messages. When the PROMISCOUS_MODE bit is '1', this value is ignored.
59996     #define MCP_REG_SMBUS_ADDRESS_NIC_SMB_ADDR3_SHIFT                                                24
59997     #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3                                                   (0x1<<31) // When this bit is '1' NIC_SMB_ADDR3 will be used as a slave address to match for incoming messages.
59998     #define MCP_REG_SMBUS_ADDRESS_EN_NIC_SMB_ADDR3_SHIFT                                             31
59999 #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL                                                            0xe0800cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60000     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED0                                                (0xff<<0) //
60001     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED0_SHIFT                                          0
60002     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD                               (0x7f<<8) // When the Master Receive FIFO hits this threshold the SMBUS block will generate an event for the control processor. When set to 0x0 event generation is disabled. Threshold is specified with the byte resolution.
60003     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_THRESHOLD_SHIFT                         8
60004     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED1                                                (0x1<<15) //
60005     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED1_SHIFT                                          15
60006     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT                                    (0x7f<<16) // Number of packets in the Master RX FIFO.
60007     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_PKT_COUNT_SHIFT                              16
60008     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED2                                                (0x7f<<23) //
60009     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_UNUSED2_SHIFT                                          23
60010     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH                                   (0x1<<30) // When this bit is set HW will flush Master TX FIFO when current TX transaction completes.
60011     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_TX_FIFO_FLUSH_SHIFT                             30
60012     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH                                   (0x1<<31) // When this bit is set HW will flush Master RX FIFO when the current RX transaction completes.
60013     #define MCP_REG_SMBUS_MASTER_FIFO_CONTROL_MASTER_RX_FIFO_FLUSH_SHIFT                             31
60014 #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL                                                             0xe08010UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60015     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED0                                                 (0xff<<0) //
60016     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED0_SHIFT                                           0
60017     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD                                 (0x7f<<8) // When the Slave Receive FIFO hits this threshold the SMBUS block will generate an event for the control processor. When set to 0x0 event generation is disabled. Threshold is specified with the byte resolution.
60018     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_THRESHOLD_SHIFT                           8
60019     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED1                                                 (0x1<<15) //
60020     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED1_SHIFT                                           15
60021     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT                                      (0x7f<<16) // Number of packets in the Slave RX FIFO.
60022     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_PKT_COUNT_SHIFT                                16
60023     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED2                                                 (0x7f<<23) //
60024     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_UNUSED2_SHIFT                                           23
60025     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH                                     (0x1<<30) // When this bit is set HW will flush Slave TX FIFO when current TX transaction completes.
60026     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_TX_FIFO_FLUSH_SHIFT                               30
60027     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH                                     (0x1<<31) // When this bit is set HW will flush Slave RX FIFO when the current RX transaction completes.
60028     #define MCP_REG_SMBUS_SLAVE_FIFO_CONTROL_SLAVE_RX_FIFO_FLUSH_SHIFT                               31
60029 #define MCP_REG_SMBUS_BIT_BANG_CONTROL                                                               0xe08014UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60030     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_UNUSED0                                                   (0xfffffff<<0) //
60031     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_UNUSED0_SHIFT                                             0
60032     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN                                             (0x1<<28) // When the SMBUS interface is configured for bit-bang mode, this bit controlls the output enable for the SMBDAT pin. When this bit is '0', the SMBDAT pin will drive low. When this bit is '1', the SMBDAT pin will float.
60033     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_OUT_EN_SHIFT                                       28
60034     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN                                                 (0x1<<29) // This bit reflects the current input value of the SMBDAT pin. When the SMBDAT pin is high, this bit will read as '1'. When the SMBDAT pin is low, this pin will read as '0'.
60035     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBDAT_IN_SHIFT                                           29
60036     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN                                             (0x1<<30) // When the SM Bus interface is configured for bit-bang mode, this bit controlls the output enable for the CLK pin. When this bit is '0', the CLK pin will drive low. When this bit is '1', the CLK pin will float.
60037     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_OUT_EN_SHIFT                                       30
60038     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN                                                 (0x1<<31) // This bit reflects the current input value of the SMBCLK pin. When the SMBCLK pin is high, this bit will read as '1'. When the SMBCLK pin is low, this pin will read as '0'.
60039     #define MCP_REG_SMBUS_BIT_BANG_CONTROL_SMBCLK_IN_SHIFT                                           31
60040 #define MCP_REG_SMBUS_WATCHDOG                                                                       0xe08018UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60041     #define MCP_REG_SMBUS_WATCHDOG_WATCHDOG                                                          (0xffff<<0) // This value counts down to zero once each second and sets the WG_TO bit when it reaches zero. The counter stops when it reaches zero.
60042     #define MCP_REG_SMBUS_WATCHDOG_WATCHDOG_SHIFT                                                    0
60043 #define MCP_REG_SMBUS_HEARTBEAT                                                                      0xe0801cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60044     #define MCP_REG_SMBUS_HEARTBEAT_HEARTBEAT                                                        (0xffff<<0) // This value counts down to zero once each second and sets the HB_TO bit when it reaches zero. The counter stops when it reaches zero.
60045     #define MCP_REG_SMBUS_HEARTBEAT_HEARTBEAT_SHIFT                                                  0
60046 #define MCP_REG_SMBUS_POLL_ASF                                                                       0xe08020UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60047     #define MCP_REG_SMBUS_POLL_ASF_POLL_ASF                                                          (0xffff<<0) // This value counts down to zero once each 5 msec. and sets the PA_TO bit when it reaches zero. The counter stops when it reaches zero.
60048     #define MCP_REG_SMBUS_POLL_ASF_POLL_ASF_SHIFT                                                    0
60049 #define MCP_REG_SMBUS_POLL_LEGACY                                                                    0xe08024UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60050     #define MCP_REG_SMBUS_POLL_LEGACY_POLL_LEGACY                                                    (0xffff<<0) // This value counts down to zero once each 250 msec. and sets the PL_TO bit when it reaches zero. The counter stops when it reaches zero.
60051     #define MCP_REG_SMBUS_POLL_LEGACY_POLL_LEGACY_SHIFT                                              0
60052 #define MCP_REG_SMBUS_RETRAN                                                                         0xe08028UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60053     #define MCP_REG_SMBUS_RETRAN_RETRAN                                                              (0xff<<0) // This value counts down to zero once each second and sets the RT_TO bit when it reaches zero. The counter stops when it reaches zero.
60054     #define MCP_REG_SMBUS_RETRAN_RETRAN_SHIFT                                                        0
60055 #define MCP_REG_SMBUS_TIMESTAMP                                                                      0xe0802cUL //Access:RW   DataWidth:0x20  This value counts up once each second and rolls to zero each time it passes 0xffffffff. This counter only counts when the TIMESTAMP_CNT_EN bit is '1'.  Chips: BB_A0 BB_B0 K2
60056 #define MCP_REG_SMBUS_MASTER_COMMAND                                                                 0xe08030UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60057     #define MCP_REG_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT                                               (0xff<<0) // This is number of bytes that SMBUS block should read from the slave in Block Write - Block Read Process Call or Block Read. If this field is 0 the SMBUS block will assume that first byte received from the slave is a Byte Count. If different than 0 HW will use this value as an indication as where to insert NACK and STOP that is end the transaction.
60058     #define MCP_REG_SMBUS_MASTER_COMMAND_RD_BYTE_COUNT_SHIFT                                         0
60059     #define MCP_REG_SMBUS_MASTER_COMMAND_PEC                                                         (0x1<<8) // PEC should be checked or calculated for this transaction.
60060     #define MCP_REG_SMBUS_MASTER_COMMAND_PEC_SHIFT                                                   8
60061     #define MCP_REG_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL                                              (0xf<<9) // SMBUS Protocol encoded as
60062     #define MCP_REG_SMBUS_MASTER_COMMAND_SMBUS_PROTOCOL_SHIFT                                        9
60063     #define MCP_REG_SMBUS_MASTER_COMMAND_UNUSED0                                                     (0xfff<<13) //
60064     #define MCP_REG_SMBUS_MASTER_COMMAND_UNUSED0_SHIFT                                               13
60065     #define MCP_REG_SMBUS_MASTER_COMMAND_STATUS                                                      (0x7<<25) // These bits encode status of the last master transaction. Valid when START_BUSY is cleared after it was set
60066     #define MCP_REG_SMBUS_MASTER_COMMAND_STATUS_SHIFT                                                25
60067     #define MCP_REG_SMBUS_MASTER_COMMAND_UNUSED1                                                     (0x3<<28) //
60068     #define MCP_REG_SMBUS_MASTER_COMMAND_UNUSED1_SHIFT                                               28
60069     #define MCP_REG_SMBUS_MASTER_COMMAND_ABORT                                                       (0x1<<30) // Transaction Abort. This bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW will abort transaction in compliance with the SMBUS rules and clear the bit when done.
60070     #define MCP_REG_SMBUS_MASTER_COMMAND_ABORT_SHIFT                                                 30
60071     #define MCP_REG_SMBUS_MASTER_COMMAND_START_BUSY                                                  (0x1<<31) // This bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activate. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results.
60072     #define MCP_REG_SMBUS_MASTER_COMMAND_START_BUSY_SHIFT                                            31
60073 #define MCP_REG_SMBUS_SLAVE_COMMAND                                                                  0xe08034UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60074     #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED0                                                      (0xff<<0) //
60075     #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED0_SHIFT                                                0
60076     #define MCP_REG_SMBUS_SLAVE_COMMAND_PEC                                                          (0x1<<8) // PEC should be calculated for this transaction.
60077     #define MCP_REG_SMBUS_SLAVE_COMMAND_PEC_SHIFT                                                    8
60078     #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED1                                                      (0x3fff<<9) //
60079     #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED1_SHIFT                                                9
60080     #define MCP_REG_SMBUS_SLAVE_COMMAND_STATUS                                                       (0x7<<23) // These bits encode status of the last slave transaction. Valid when START_BUSY is cleared after it was set
60081     #define MCP_REG_SMBUS_SLAVE_COMMAND_STATUS_SHIFT                                                 23
60082     #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED2                                                      (0xf<<26) //
60083     #define MCP_REG_SMBUS_SLAVE_COMMAND_UNUSED2_SHIFT                                                26
60084     #define MCP_REG_SMBUS_SLAVE_COMMAND_ABORT                                                        (0x1<<30) // Transaction Abort. This bit can be set at any time by the firmware or the driver in order to abort the transaction. The HW will abort transaction in compliance with the SMBUS rules and clear the bit when done. When set and the slave transaction is received the HW will ACK the address and float the bus thereafter.
60085     #define MCP_REG_SMBUS_SLAVE_COMMAND_ABORT_SHIFT                                                  30
60086     #define MCP_REG_SMBUS_SLAVE_COMMAND_START                                                        (0x1<<31) // _BUSY This bit is self clearing. When written to a '1', the currently programmed SMBUS transaction will activate. Writing this bit as a '0' has no effect. This bit must be read as a '0' before setting it to prevent un-predictable results. Used only for read response.
60087     #define MCP_REG_SMBUS_SLAVE_COMMAND_START_SHIFT                                                  31
60088 #define MCP_REG_SMBUS_EVENT_ENABLE                                                                   0xe08038UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60089     #define MCP_REG_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN                                                (0x1<<0) // When set enables Watchdog Timer to generate smbus event.
60090     #define MCP_REG_SMBUS_EVENT_ENABLE_WATCHDOG_TO_EN_SHIFT                                          0
60091     #define MCP_REG_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN                                               (0x1<<1) // When set enables Heartbeat Timer to generate smbus event.
60092     #define MCP_REG_SMBUS_EVENT_ENABLE_HEARTBEAT_TO_EN_SHIFT                                         1
60093     #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN                                                (0x1<<2) // When set enables ASF Sensor Poll Timer to generate smbus event.
60094     #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_ASF_TO_EN_SHIFT                                          2
60095     #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN                                             (0x1<<3) // When set enables Legacy Sensor Poll Timer to generate smbus event.
60096     #define MCP_REG_SMBUS_EVENT_ENABLE_POLL_LEGACY_TO_EN_SHIFT                                       3
60097     #define MCP_REG_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN                                              (0x1<<4) // When set enables Retransmit Timer to generate smbus event.
60098     #define MCP_REG_SMBUS_EVENT_ENABLE_RETRANSMIT_TO_EN_SHIFT                                        4
60099     #define MCP_REG_SMBUS_EVENT_ENABLE_UNUSED0                                                       (0x7fff<<5) //
60100     #define MCP_REG_SMBUS_EVENT_ENABLE_UNUSED0_SHIFT                                                 5
60101     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN                                            (0x1<<20) // When set enables hardware to generate smbus event any time and ARP command is received and ARP_EN0 or ARP_EN1 bit is set.
60102     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_ARP_EVENT_EN_SHIFT                                      20
60103     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN                                             (0x1<<21) // Enables SLAVE_RD_EVENT to generate smbus event.
60104     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RD_EVENT_EN_SHIFT                                       21
60105     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN                                          (0x1<<22) // When set enables generation of a smbus event when Slave Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
60106     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_TX_UNDERRUN_EN_SHIFT                                    22
60107     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN                                           (0x1<<23) // When set enables generation of a smbus event on slave START_BUSY 1 to 0 transition.
60108     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_START_BUSY_EN_SHIFT                                     23
60109     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN                                             (0x1<<24) // Enables SLAVE_RX_EVENT to generate smbus event.
60110     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_EVENT_EN_SHIFT                                       24
60111     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN                                     (0x1<<25) // When set enables SLAVE_RX_THRESHOLD_HIT to generate smbus event.
60112     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_THRESHOLD_HIT_EN_SHIFT                               25
60113     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN                                         (0x1<<26) // When set enables SLAVE_RX_FIFO_FULL to generate smbus event.
60114     #define MCP_REG_SMBUS_EVENT_ENABLE_SLAVE_RX_FIFO_FULL_EN_SHIFT                                   26
60115     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN                                         (0x1<<27) // When set enables generation of a smbus event when Master Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
60116     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_TX_UNDERRUN_EN_SHIFT                                   27
60117     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN                                          (0x1<<28) // When set enables generation of a smbus event on master START_BUSY 1 to 0 transition.
60118     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_START_BUSY_EN_SHIFT                                    28
60119     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN                                            (0x1<<29) // When set enables MASTER_RX_EVENT to generate smbus event.
60120     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_EVENT_EN_SHIFT                                      29
60121     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN                                    (0x1<<30) // When set enables MASTER_RX_THRESHOLD_HIT to generate smbus event.
60122     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_THRESHOLD_HIT_EN_SHIFT                              30
60123     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN                                        (0x1<<31) // When set enables MASTER_RX_FIFO_FULL to generate smbus event.
60124     #define MCP_REG_SMBUS_EVENT_ENABLE_MASTER_RX_FIFO_FULL_EN_SHIFT                                  31
60125 #define MCP_REG_SMBUS_EVENT_STATUS                                                                   0xe0803cUL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60126     #define MCP_REG_SMBUS_EVENT_STATUS_WATCHDOG_TO                                                   (0x1<<0) // This bit changes to '1' each time the WATCHDOG timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60127     #define MCP_REG_SMBUS_EVENT_STATUS_WATCHDOG_TO_SHIFT                                             0
60128     #define MCP_REG_SMBUS_EVENT_STATUS_HEARTBEAT_TO                                                  (0x1<<1) // This bit changes to '1' each time the HEARTBEAT timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60129     #define MCP_REG_SMBUS_EVENT_STATUS_HEARTBEAT_TO_SHIFT                                            1
60130     #define MCP_REG_SMBUS_EVENT_STATUS_POLL_ASF_TO                                                   (0x1<<2) // This bit changes to '1' each time the POLL_ASF timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60131     #define MCP_REG_SMBUS_EVENT_STATUS_POLL_ASF_TO_SHIFT                                             2
60132     #define MCP_REG_SMBUS_EVENT_STATUS_POLL_LEGACY_TO                                                (0x1<<3) // This bit changes to '1' each time the POLL_LEGACY timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60133     #define MCP_REG_SMBUS_EVENT_STATUS_POLL_LEGACY_TO_SHIFT                                          3
60134     #define MCP_REG_SMBUS_EVENT_STATUS_RETRANSMIT_TO                                                 (0x1<<4) // This bit changes to '1' each time the RETRANSMIT timer reaches zero. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60135     #define MCP_REG_SMBUS_EVENT_STATUS_RETRANSMIT_TO_SHIFT                                           4
60136     #define MCP_REG_SMBUS_EVENT_STATUS_UNUSED0                                                       (0x7fff<<5) //
60137     #define MCP_REG_SMBUS_EVENT_STATUS_UNUSED0_SHIFT                                                 5
60138     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT                                               (0x1<<20) // This bit set when slave hardware received an ARP command and ARP_EN0 or ARP_EN1 bit is set.
60139     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_ARP_EVENT_SHIFT                                         20
60140     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT                                                (0x1<<21) // This bit is set when slave hardware detected read transaction directed toward the SMBUS block. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60141     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RD_EVENT_SHIFT                                          21
60142     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN                                             (0x1<<22) // This bit is set when Slave Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
60143     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_TX_UNDERRUN_SHIFT                                       22
60144     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_START_BUSY                                              (0x1<<23) // This bit is set when slave START_BUSY transitions from 1 to 0. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor. 0x
60145     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_START_BUSY_SHIFT                                        23
60146     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT                                                (0x1<<24) // This bit is set when the slave receive FIFO holds at least one valid transaction. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60147     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_EVENT_SHIFT                                          24
60148     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT                                        (0x1<<25) // This bit is set when the slave receive FIFO is equal to or larger than the Slave RX_FIFO_THRESHOLD. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60149     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_THRESHOLD_HIT_SHIFT                                  25
60150     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL                                            (0x1<<26) // This bit is set when the slave receive FIFO become full. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60151     #define MCP_REG_SMBUS_EVENT_STATUS_SLAVE_RX_FIFO_FULL_SHIFT                                      26
60152     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN                                            (0x1<<27) // This bit is set when Master Tx FIFO becomes empty and less then PKT_LENGTH bytes were output on the SMBUS.
60153     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_TX_UNDERRUN_SHIFT                                      27
60154     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_START_BUSY                                             (0x1<<28) // This bit is set when master START_BUSY transitions from 1 to 0. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor. 0x
60155     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_START_BUSY_SHIFT                                       28
60156     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_EVENT                                               (0x1<<29) // This bit is set when the master receive FIFO holds at least one valid transaction. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60157     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_EVENT_SHIFT                                         29
60158     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT                                       (0x1<<30) // This bit is set when the master receive FIFO is equal to or larger than the Master RX_FIFO_THRESHOLD. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60159     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_THRESHOLD_HIT_SHIFT                                 30
60160     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL                                           (0x1<<31) // This bit is set when the master receive FIFO become full. Writing a '1' to this position will clear this bit. When this bit is '1', the SMB0_EVENT bit will be '1' in each processor.
60161     #define MCP_REG_SMBUS_EVENT_STATUS_MASTER_RX_FIFO_FULL_SHIFT                                     31
60162 #define MCP_REG_SMBUS_MASTER_DATA_WRITE                                                              0xe08040UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60163     #define MCP_REG_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA                                     (0xff<<0) // This is a software interface to the SMBUS Master Transmit FIFO. Software should use this register to provide data for an SMBUS write transaction. Data should be written before the SMBUS Command is programmed.
60164     #define MCP_REG_SMBUS_MASTER_DATA_WRITE_MASTER_SMBUS_WR_DATA_SHIFT                               0
60165     #define MCP_REG_SMBUS_MASTER_DATA_WRITE_UNUSED0                                                  (0x7fffff<<8) //
60166     #define MCP_REG_SMBUS_MASTER_DATA_WRITE_UNUSED0_SHIFT                                            8
60167     #define MCP_REG_SMBUS_MASTER_DATA_WRITE_WR_STATUS                                                (0x1<<31) // 0 - Byte other then last in an WMBUS transaction 1 - End of SMBUS transaction
60168     #define MCP_REG_SMBUS_MASTER_DATA_WRITE_WR_STATUS_SHIFT                                          31
60169 #define MCP_REG_SMBUS_MASTER_DATA_READ                                                               0xe08044UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60170     #define MCP_REG_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA                                      (0xff<<0) // SMBUS Read Data in Network Byte Order (MSB first). This is a software interface to the SMBUS Master Receive FIFO. Software should use this register to read data received from the SMBUS.
60171     #define MCP_REG_SMBUS_MASTER_DATA_READ_MASTER_SMBUS_RD_DATA_SHIFT                                0
60172     #define MCP_REG_SMBUS_MASTER_DATA_READ_UNUSED0                                                   (0x1fffff<<8) //
60173     #define MCP_REG_SMBUS_MASTER_DATA_READ_UNUSED0_SHIFT                                             8
60174     #define MCP_REG_SMBUS_MASTER_DATA_READ_PEC_ERR                                                   (0x1<<29) // PEC error. This bit indicates status of the PEC checking. HW will check the PEC only in case where PEC bit in SMBUS Master Command Register was set for rhe transaction This field is valid only when RD_STATUS = 2'b11.
60175     #define MCP_REG_SMBUS_MASTER_DATA_READ_PEC_ERR_SHIFT                                             29
60176     #define MCP_REG_SMBUS_MASTER_DATA_READ_RD_STATUS                                                 (0x3<<30) // Enumeration:
60177     #define MCP_REG_SMBUS_MASTER_DATA_READ_RD_STATUS_SHIFT                                           30
60178 #define MCP_REG_SMBUS_SLAVE_DATA_WRITE                                                               0xe08048UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60179     #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA                                       (0xff<<0) // This is a software interface to the SMBUS Slave Transmit FIFO. Software should use this register to provide data for an SMBUS read transaction.
60180     #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_SLAVE_SMBUS_WR_DATA_SHIFT                                 0
60181     #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_UNUSED0                                                   (0x7fffff<<8) //
60182     #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_UNUSED0_SHIFT                                             8
60183     #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_WR_STATUS                                                 (0x1<<31) // Enumeration:
60184     #define MCP_REG_SMBUS_SLAVE_DATA_WRITE_WR_STATUS_SHIFT                                           31
60185 #define MCP_REG_SMBUS_SLAVE_DATA_READ                                                                0xe0804cUL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60186     #define MCP_REG_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA                                        (0xff<<0) // This is a software interface to the SMBUS Slave Receive FIFO. Software should use this register to read data received from the SMBUS.
60187     #define MCP_REG_SMBUS_SLAVE_DATA_READ_SLAVE_SMBUS_RD_DATA_SHIFT                                  0
60188     #define MCP_REG_SMBUS_SLAVE_DATA_READ_UNUSED0                                                    (0xfffff<<8) //
60189     #define MCP_REG_SMBUS_SLAVE_DATA_READ_UNUSED0_SHIFT                                              8
60190     #define MCP_REG_SMBUS_SLAVE_DATA_READ_ERR_STATUS                                                 (0x3<<28) // This field is valid only when RD_STATUS = 2'b11.
60191     #define MCP_REG_SMBUS_SLAVE_DATA_READ_ERR_STATUS_SHIFT                                           28
60192     #define MCP_REG_SMBUS_SLAVE_DATA_READ_RD_STATUS                                                  (0x3<<30) // Enumeration:
60193     #define MCP_REG_SMBUS_SLAVE_DATA_READ_RD_STATUS_SHIFT                                            30
60194 #define MCP_REG_SMBUS_ARP_STATE                                                                      0xe08080UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60195     #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG0                                                         (0x1<<0) // This bit should be set by firmware before ARP_EN0 bit is set. This bit is typically set to '1' based on the NVRAM content that is if device supports Persistent Slave Address and cleared otherwise.
60196     #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG0_SHIFT                                                   0
60197     #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG0                                                         (0x1<<1) // This bit should be set by firmware before ARP_EN0 bit is set. This bit is typically initialized to '0'.
60198     #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG0_SHIFT                                                   1
60199     #define MCP_REG_SMBUS_ARP_STATE_UNUSED0                                                          (0x3<<2) //
60200     #define MCP_REG_SMBUS_ARP_STATE_UNUSED0_SHIFT                                                    2
60201     #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG1                                                         (0x1<<4) // This bit should be set by firmware before ARP_EN1 bit is set. This bit is typically set to '1' based on the NVRAM content that is if device supports Persistent Slave Address and cleared otherwise.
60202     #define MCP_REG_SMBUS_ARP_STATE_AV_FLAG1_SHIFT                                                   4
60203     #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG1                                                         (0x1<<5) // This bit should be set by firmware before ARP_EN1 bit is set. This bit is typically initialized to '0'.
60204     #define MCP_REG_SMBUS_ARP_STATE_AR_FLAG1_SHIFT                                                   5
60205 #define MCP_REG_SMBUS_UDID0_3                                                                        0xe08090UL //Access:RW   DataWidth:0x20  This register should be set by firmware before ARP_EN0 bit is set.  Chips: BB_A0 BB_B0 K2
60206     #define MCP_REG_SMBUS_UDID0_3_BYTE_12                                                            (0xff<<0) // UDID_0 byte 12.
60207     #define MCP_REG_SMBUS_UDID0_3_BYTE_12_SHIFT                                                      0
60208     #define MCP_REG_SMBUS_UDID0_3_BYTE_13                                                            (0xff<<8) // UDID_0 byte 13.
60209     #define MCP_REG_SMBUS_UDID0_3_BYTE_13_SHIFT                                                      8
60210     #define MCP_REG_SMBUS_UDID0_3_BYTE_14                                                            (0xff<<16) // UDID_0 byte 14.
60211     #define MCP_REG_SMBUS_UDID0_3_BYTE_14_SHIFT                                                      16
60212     #define MCP_REG_SMBUS_UDID0_3_BYTE_15                                                            (0xff<<24) // UDID_0 byte 15.
60213     #define MCP_REG_SMBUS_UDID0_3_BYTE_15_SHIFT                                                      24
60214 #define MCP_REG_SMBUS_UDID0_2                                                                        0xe08094UL //Access:RW   DataWidth:0x20  This register should be set by firmware before ARP_EN0 bit is set.  Chips: BB_A0 BB_B0 K2
60215     #define MCP_REG_SMBUS_UDID0_2_BYTE_8                                                             (0xff<<0) // UDID_0 byte 8.
60216     #define MCP_REG_SMBUS_UDID0_2_BYTE_8_SHIFT                                                       0
60217     #define MCP_REG_SMBUS_UDID0_2_BYTE_9                                                             (0xff<<8) // UDID_0 byte 9.
60218     #define MCP_REG_SMBUS_UDID0_2_BYTE_9_SHIFT                                                       8
60219     #define MCP_REG_SMBUS_UDID0_2_BYTE_10                                                            (0xff<<16) // UDID_0 byte 10.
60220     #define MCP_REG_SMBUS_UDID0_2_BYTE_10_SHIFT                                                      16
60221     #define MCP_REG_SMBUS_UDID0_2_BYTE_11                                                            (0xff<<24) // UDID_0 byte 11.
60222     #define MCP_REG_SMBUS_UDID0_2_BYTE_11_SHIFT                                                      24
60223 #define MCP_REG_SMBUS_UDID0_1                                                                        0xe08098UL //Access:RW   DataWidth:0x20  This register should be set by firmware before ARP_EN0 bit is set.  Chips: BB_A0 BB_B0 K2
60224     #define MCP_REG_SMBUS_UDID0_1_BYTE_4                                                             (0xff<<0) // UDID_0 byte 4.
60225     #define MCP_REG_SMBUS_UDID0_1_BYTE_4_SHIFT                                                       0
60226     #define MCP_REG_SMBUS_UDID0_1_BYTE_5                                                             (0xff<<8) // UDID_0 byte 5.
60227     #define MCP_REG_SMBUS_UDID0_1_BYTE_5_SHIFT                                                       8
60228     #define MCP_REG_SMBUS_UDID0_1_BYTE_6                                                             (0xff<<16) // UDID_0 byte 6.
60229     #define MCP_REG_SMBUS_UDID0_1_BYTE_6_SHIFT                                                       16
60230     #define MCP_REG_SMBUS_UDID0_1_BYTE_7                                                             (0xff<<24) // UDID_0 byte 7.
60231     #define MCP_REG_SMBUS_UDID0_1_BYTE_7_SHIFT                                                       24
60232 #define MCP_REG_SMBUS_UDID0_0                                                                        0xe0809cUL //Access:RW   DataWidth:0x20  This register should be set by firmware before ARP_EN0 bit is set.  Chips: BB_A0 BB_B0 K2
60233     #define MCP_REG_SMBUS_UDID0_0_BYTE_0                                                             (0xff<<0) // UDID_0 byte 0.
60234     #define MCP_REG_SMBUS_UDID0_0_BYTE_0_SHIFT                                                       0
60235     #define MCP_REG_SMBUS_UDID0_0_BYTE_1                                                             (0xff<<8) // UDID_0 byte 1.
60236     #define MCP_REG_SMBUS_UDID0_0_BYTE_1_SHIFT                                                       8
60237     #define MCP_REG_SMBUS_UDID0_0_BYTE_2                                                             (0xff<<16) // UDID_0 byte 2.
60238     #define MCP_REG_SMBUS_UDID0_0_BYTE_2_SHIFT                                                       16
60239     #define MCP_REG_SMBUS_UDID0_0_BYTE_3                                                             (0xff<<24) // UDID_0 byte 3.
60240     #define MCP_REG_SMBUS_UDID0_0_BYTE_3_SHIFT                                                       24
60241 #define MCP_REG_SMBUS_UDID1_3                                                                        0xe080a0UL //Access:RW   DataWidth:0x20  This register should be set by firmware before ARP_EN1 bit is set.  Chips: BB_A0 BB_B0 K2
60242     #define MCP_REG_SMBUS_UDID1_3_BYTE_12                                                            (0xff<<0) // UDID_1 byte 12.
60243     #define MCP_REG_SMBUS_UDID1_3_BYTE_12_SHIFT                                                      0
60244     #define MCP_REG_SMBUS_UDID1_3_BYTE_13                                                            (0xff<<8) // UDID_1 byte 13.
60245     #define MCP_REG_SMBUS_UDID1_3_BYTE_13_SHIFT                                                      8
60246     #define MCP_REG_SMBUS_UDID1_3_BYTE_14                                                            (0xff<<16) // UDID_1 byte 14.
60247     #define MCP_REG_SMBUS_UDID1_3_BYTE_14_SHIFT                                                      16
60248     #define MCP_REG_SMBUS_UDID1_3_BYTE_15                                                            (0xff<<24) // UDID_1 byte 15.
60249     #define MCP_REG_SMBUS_UDID1_3_BYTE_15_SHIFT                                                      24
60250 #define MCP_REG_SMBUS_UDID1_2                                                                        0xe080a4UL //Access:RW   DataWidth:0x20  This register should be set by firmware before ARP_EN1 bit is set.  Chips: BB_A0 BB_B0 K2
60251     #define MCP_REG_SMBUS_UDID1_2_BYTE_8                                                             (0xff<<0) // UDID_1 byte 8.
60252     #define MCP_REG_SMBUS_UDID1_2_BYTE_8_SHIFT                                                       0
60253     #define MCP_REG_SMBUS_UDID1_2_BYTE_9                                                             (0xff<<8) // UDID_1 byte 9.
60254     #define MCP_REG_SMBUS_UDID1_2_BYTE_9_SHIFT                                                       8
60255     #define MCP_REG_SMBUS_UDID1_2_BYTE_10                                                            (0xff<<16) // UDID_1 byte 10.
60256     #define MCP_REG_SMBUS_UDID1_2_BYTE_10_SHIFT                                                      16
60257     #define MCP_REG_SMBUS_UDID1_2_BYTE_11                                                            (0xff<<24) // UDID_1 byte 11.
60258     #define MCP_REG_SMBUS_UDID1_2_BYTE_11_SHIFT                                                      24
60259 #define MCP_REG_SMBUS_UDID1_1                                                                        0xe080a8UL //Access:RW   DataWidth:0x20  This register should be set by firmware before ARP_EN1 bit is set.  Chips: BB_A0 BB_B0 K2
60260     #define MCP_REG_SMBUS_UDID1_1_BYTE_4                                                             (0xff<<0) // UDID_1 byte 4.
60261     #define MCP_REG_SMBUS_UDID1_1_BYTE_4_SHIFT                                                       0
60262     #define MCP_REG_SMBUS_UDID1_1_BYTE_5                                                             (0xff<<8) // UDID_1 byte 5.
60263     #define MCP_REG_SMBUS_UDID1_1_BYTE_5_SHIFT                                                       8
60264     #define MCP_REG_SMBUS_UDID1_1_BYTE_6                                                             (0xff<<16) // UDID_1 byte 6.
60265     #define MCP_REG_SMBUS_UDID1_1_BYTE_6_SHIFT                                                       16
60266     #define MCP_REG_SMBUS_UDID1_1_BYTE_7                                                             (0xff<<24) // UDID_1 byte 7.
60267     #define MCP_REG_SMBUS_UDID1_1_BYTE_7_SHIFT                                                       24
60268 #define MCP_REG_SMBUS_UDID1_0                                                                        0xe080acUL //Access:RW   DataWidth:0x20  This register should be set by firmware before ARP_EN1 bit is set.  Chips: BB_A0 BB_B0 K2
60269     #define MCP_REG_SMBUS_UDID1_0_BYTE_0                                                             (0xff<<0) // UDID_1 byte 0.
60270     #define MCP_REG_SMBUS_UDID1_0_BYTE_0_SHIFT                                                       0
60271     #define MCP_REG_SMBUS_UDID1_0_BYTE_1                                                             (0xff<<8) // UDID_1 byte 1.
60272     #define MCP_REG_SMBUS_UDID1_0_BYTE_1_SHIFT                                                       8
60273     #define MCP_REG_SMBUS_UDID1_0_BYTE_2                                                             (0xff<<16) // UDID_1 byte 2.
60274     #define MCP_REG_SMBUS_UDID1_0_BYTE_2_SHIFT                                                       16
60275     #define MCP_REG_SMBUS_UDID1_0_BYTE_3                                                             (0xff<<24) // UDID_1 byte 3.
60276     #define MCP_REG_SMBUS_UDID1_0_BYTE_3_SHIFT                                                       24
60277 #define MCP_REG_SMBUS_SMB_REG_END                                                                    0xe083fcUL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60278 #define MCP_REG_TO_BMB_FIFO_COMMAND                                                                  0xe08400UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60279     #define MCP_REG_TO_BMB_FIFO_COMMAND_FLUSH                                                        (0x1<<0) // Setting this bit to '1' will flush the packet in the FIFO.
60280     #define MCP_REG_TO_BMB_FIFO_COMMAND_FLUSH_SHIFT                                                  0
60281     #define MCP_REG_TO_BMB_FIFO_COMMAND__ERROR                                                       (0x1<<1) // Setting this bit to '1' will set the error bit for the packet.
60282     #define MCP_REG_TO_BMB_FIFO_COMMAND__ERROR_SHIFT                                                 1
60283     #define MCP_REG_TO_BMB_FIFO_COMMAND_UNUSED0                                                      (0x3<<2) //
60284     #define MCP_REG_TO_BMB_FIFO_COMMAND_UNUSED0_SHIFT                                                2
60285     #define MCP_REG_TO_BMB_FIFO_COMMAND_PKT_TC                                                       (0xf<<4) // These bits indicate the read client of the packet
60286     #define MCP_REG_TO_BMB_FIFO_COMMAND_PKT_TC_SHIFT                                                 4
60287     #define MCP_REG_TO_BMB_FIFO_COMMAND_UNUSED1                                                      (0xff<<8) //
60288     #define MCP_REG_TO_BMB_FIFO_COMMAND_UNUSED1_SHIFT                                                8
60289     #define MCP_REG_TO_BMB_FIFO_COMMAND_PKT_LEN                                                      (0xffff<<16) // These bits indicate the length of the packet.
60290     #define MCP_REG_TO_BMB_FIFO_COMMAND_PKT_LEN_SHIFT                                                16
60291 #define MCP_REG_TO_BMB_FIFO_STATUS                                                                   0xe08404UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60292     #define MCP_REG_TO_BMB_FIFO_STATUS_WRITE_DONE                                                    (0x1<<0) // This bit indicates that the write to BMB has been completed.
60293     #define MCP_REG_TO_BMB_FIFO_STATUS_WRITE_DONE_SHIFT                                              0
60294 #define MCP_REG_TO_BMB_FIFO_WR_DATA                                                                  0xe08408UL //Access:RW   DataWidth:0x20  Write data  Chips: BB_A0 BB_B0 K2
60295 #define MCP_REG_TO_BMB_FIFO_SOP_DSCR0                                                                0xe08410UL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60296 #define MCP_REG_TO_BMB_FIFO_SOP_DSCR1                                                                0xe08414UL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60297 #define MCP_REG_TO_BMB_FIFO_SOP_DSCR2                                                                0xe08418UL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60298 #define MCP_REG_TO_BMB_FIFO_SOP_DSCR3                                                                0xe0841cUL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60299 #define MCP_REG_FRM_BMB_FIFO_COMMAND                                                                 0xe08420UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60300     #define MCP_REG_FRM_BMB_FIFO_COMMAND_READ_DONE                                                   (0x1<<0) // Setting this bit to '1' will indicate that FW has completed read of the packet.
60301     #define MCP_REG_FRM_BMB_FIFO_COMMAND_READ_DONE_SHIFT                                             0
60302     #define MCP_REG_FRM_BMB_FIFO_COMMAND_UNUSED0                                                     (0x7<<1) //
60303     #define MCP_REG_FRM_BMB_FIFO_COMMAND_UNUSED0_SHIFT                                               1
60304     #define MCP_REG_FRM_BMB_FIFO_COMMAND_FLUSH                                                       (0x1<<4) // Setting this bit to '1' will flush the current packet in the FIFO
60305     #define MCP_REG_FRM_BMB_FIFO_COMMAND_FLUSH_SHIFT                                                 4
60306     #define MCP_REG_FRM_BMB_FIFO_COMMAND_CLR_PKT_COUNTERS                                            (0x1<<5) // Setting this bit to '1' will clear all packet available counters in the BMB read client interface
60307     #define MCP_REG_FRM_BMB_FIFO_COMMAND_CLR_PKT_COUNTERS_SHIFT                                      5
60308 #define MCP_REG_FRM_BMB_FIFO_STATUS                                                                  0xe08424UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60309     #define MCP_REG_FRM_BMB_FIFO_STATUS_BUSY                                                         (0x1<<0) // This bit indicates that the FIFO is busy
60310     #define MCP_REG_FRM_BMB_FIFO_STATUS_BUSY_SHIFT                                                   0
60311     #define MCP_REG_FRM_BMB_FIFO_STATUS_UNUSED0                                                      (0x1<<1) //
60312     #define MCP_REG_FRM_BMB_FIFO_STATUS_UNUSED0_SHIFT                                                1
60313     #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_TC0                                                      (0x3<<2) // These bits indicate the incoming traffic class of the packet. These are bits [1:0] of the PKT_TC from BMB.
60314     #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_TC0_SHIFT                                                2
60315     #define MCP_REG_FRM_BMB_FIFO_STATUS_DATA_VALID                                                   (0x1<<4) // This bit indicates that the data is valid.
60316     #define MCP_REG_FRM_BMB_FIFO_STATUS_DATA_VALID_SHIFT                                             4
60317     #define MCP_REG_FRM_BMB_FIFO_STATUS_SOP                                                          (0x1<<5) // This bit indicates that the next data is the SOP of the packet.
60318     #define MCP_REG_FRM_BMB_FIFO_STATUS_SOP_SHIFT                                                    5
60319     #define MCP_REG_FRM_BMB_FIFO_STATUS_EOP                                                          (0x1<<6) // This bit indicates that the next data is the EOP of the packet.
60320     #define MCP_REG_FRM_BMB_FIFO_STATUS_EOP_SHIFT                                                    6
60321     #define MCP_REG_FRM_BMB_FIFO_STATUS_ERR                                                          (0x1<<7) // This bit indicates that the packet was received with an error.
60322     #define MCP_REG_FRM_BMB_FIFO_STATUS_ERR_SHIFT                                                    7
60323     #define MCP_REG_FRM_BMB_FIFO_STATUS_BYTE_VALID                                                   (0x3<<8) // These bits indicate the bytes that are valid in the 4byte data.
60324     #define MCP_REG_FRM_BMB_FIFO_STATUS_BYTE_VALID_SHIFT                                             8
60325     #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_TC1                                                      (0x3<<10) // These bits indicate the incoming traffic class of the packet. These are bits [3:2] of the PKT_TC from BMB
60326     #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_TC1_SHIFT                                                10
60327     #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_PORT                                                     (0xf<<12) // These bits indicate the write client of the packet. These are bits[3:0] of PKT_PORT from BMB
60328     #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_PORT_SHIFT                                               12
60329     #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_LEN                                                      (0xffff<<16) // These bits indicate the length of the packet
60330     #define MCP_REG_FRM_BMB_FIFO_STATUS_PKT_LEN_SHIFT                                                16
60331 #define MCP_REG_FRM_BMB_FIFO_RD_DATA                                                                 0xe0842cUL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60332 #define MCP_REG_FRM_BMB_FIFO_SOP_DSCR0                                                               0xe08430UL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60333 #define MCP_REG_FRM_BMB_FIFO_SOP_DSCR1                                                               0xe08434UL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60334 #define MCP_REG_FRM_BMB_FIFO_SOP_DSCR2                                                               0xe08438UL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60335 #define MCP_REG_FRM_BMB_FIFO_SOP_DSCR3                                                               0xe0843cUL //Access:RW   DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60336 #define MCP_REG_BMB_REG_END                                                                          0xe087fcUL //Access:R    DataWidth:0x20    Chips: BB_A0 BB_B0 K2
60337 #define MCP_REG_ROM                                                                                  0xe10000UL //Access:R    DataWidth:0x20  This location provides a location for the ROM contents to be read for debug pourposes.  Chips: BB_A0 BB_B0 K2
60338 #define MCP_REG_ROM_SIZE                                                                             320
60339 #define MCP_REG_SCRATCH                                                                              0xe20000UL //Access:RW   DataWidth:0x20  This is the supported processor scratch pad space that is visible at 0x0 by the processor. This can be modified at any time and may be used for processor-to-processor communication.  Chips: BB_A0 BB_B0 K2
60340 #define MCP_REG_SCRATCH_SIZE                                                                         57344
60341 #define XSDM_REG_ENABLE_IN1                                                                          0xf80004UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60342     #define XSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                      (0x1<<0) // Enable for input command from STORM.
60343     #define XSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                0
60344     #define XSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                   (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
60345     #define XSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                             1
60346     #define XSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                   (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
60347     #define XSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                             2
60348     #define XSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                   (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
60349     #define XSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                             3
60350     #define XSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                   (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
60351     #define XSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                             4
60352     #define XSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                   (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
60353     #define XSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                             5
60354     #define XSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                       (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
60355     #define XSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                 6
60356     #define XSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                       (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
60357     #define XSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                 7
60358     #define XSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                       (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
60359     #define XSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                 8
60360     #define XSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                    (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
60361     #define XSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                              9
60362     #define XSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                        (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
60363     #define XSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                  10
60364     #define XSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                       (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
60365     #define XSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                 11
60366     #define XSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                        (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
60367     #define XSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                  12
60368     #define XSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                        (0x1<<13) // Enable for input completion message from PRM in prm_if block.
60369     #define XSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                  13
60370     #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                  (0x1<<14) // Enable for input ack to CCFC load credit counter.
60371     #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                            14
60372     #define XSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                  (0x1<<15) // Enable for input ack to TCFC load credit counter.
60373     #define XSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                            15
60374     #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                  (0x1<<16) // Enable for input response from CCFC in CCFC block.
60375     #define XSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                            16
60376     #define XSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                    (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
60377     #define XSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                              17
60378     #define XSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                    (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
60379     #define XSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                              18
60380     #define XSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                 (0x1<<19) // Enable for input full from qm in SDM_INP block.
60381     #define XSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                           19
60382 #define XSDM_REG_ENABLE_IN2                                                                          0xf80008UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
60383     #define XSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                  (0x1<<0) // Enable for input response from TCFC in TCFC block.
60384     #define XSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                            0
60385     #define XSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                         (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
60386     #define XSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                   1
60387     #define XSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                       (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
60388     #define XSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                 2
60389 #define XSDM_REG_ENABLE_OUT1                                                                         0xf8000cUL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60390     #define XSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                      (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
60391     #define XSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                0
60392     #define XSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                   (0x1<<1) // Enable for output thread ready to the SEMI.
60393     #define XSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                             1
60394     #define XSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                   (0x1<<2) // Enable the output thread release to the SEMI.
60395     #define XSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                             2
60396     #define XSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                    (0x1<<3) // Enable for output load request to CCFC.
60397     #define XSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                              3
60398     #define XSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                    (0x1<<4) // Enable for output load request to TCFC.
60399     #define XSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                              4
60400     #define XSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                      (0x1<<5) // Enable for output increment to CCFC activity counter.
60401     #define XSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                5
60402     #define XSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                      (0x1<<6) // Enable for output decrement to TCFC activity counter.
60403     #define XSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                6
60404     #define XSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                      (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
60405     #define XSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                7
60406     #define XSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                      (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
60407     #define XSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                8
60408     #define XSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                      (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
60409     #define XSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                9
60410     #define XSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                      (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
60411     #define XSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                10
60412     #define XSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                    (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
60413     #define XSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                              11
60414     #define XSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                          (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
60415     #define XSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                    12
60416     #define XSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                     (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
60417     #define XSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                               13
60418     #define XSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                     (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
60419     #define XSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                               14
60420     #define XSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                     (0x1<<15) // Enable for output external full to SEMI block.
60421     #define XSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                               15
60422     #define XSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                 (0x1<<16) // Enable for output done to async PXP host IF.
60423     #define XSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                           16
60424     #define XSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                 (0x1<<17) // Enable the output done (ack) to PRM.
60425     #define XSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                           17
60426     #define XSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                       (0x1<<18) // Enable for output message to CM in SDM_CM block.
60427     #define XSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                 18
60428     #define XSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                 (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
60429     #define XSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                           19
60430     #define XSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                 (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
60431     #define XSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                           20
60432 #define XSDM_REG_ENABLE_OUT2                                                                         0xf80010UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
60433     #define XSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                    (0x1<<0) // Enable for output command to qm in SDM_INP block.
60434     #define XSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                              0
60435     #define XSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                     (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
60436     #define XSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                               1
60437     #define XSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
60438     #define XSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                          2
60439 #define XSDM_REG_DISABLE_ENGINE                                                                      0xf80014UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
60440     #define XSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                      (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
60441     #define XSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                0
60442     #define XSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                   (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
60443     #define XSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                             1
60444     #define XSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
60445     #define XSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                          2
60446     #define XSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
60447     #define XSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                          3
60448     #define XSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                   (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
60449     #define XSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                             4
60450     #define XSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                      (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
60451     #define XSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                5
60452     #define XSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                      (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
60453     #define XSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                6
60454     #define XSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                    (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
60455     #define XSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                              7
60456     #define XSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                      (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
60457     #define XSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                8
60458     #define XSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                     (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
60459     #define XSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                               9
60460 #define XSDM_REG_INT_STS                                                                             0xf80040UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60461     #define XSDM_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
60462     #define XSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
60463     #define XSDM_REG_INT_STS_INP_QUEUE_ERROR                                                         (0x1<<1) // Indicates that one of the input queues had a FIFO error.
60464     #define XSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                   1
60465     #define XSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                        (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
60466     #define XSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                  2
60467     #define XSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                        (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
60468     #define XSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                  3
60469     #define XSDM_REG_INT_STS_PRM_FIFO_ERROR                                                          (0x1<<4) // FIFO in PRM interface sub-module reported an error.
60470     #define XSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                    4
60471     #define XSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                    (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
60472     #define XSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                              5
60473     #define XSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                    (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
60474     #define XSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                              6
60475     #define XSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                  (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
60476     #define XSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                            7
60477     #define XSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                  (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
60478     #define XSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                            8
60479     #define XSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                     (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
60480     #define XSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                               9
60481     #define XSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                  (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
60482     #define XSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                            10
60483     #define XSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                  (0x1<<11) // BRB src pend fifo error in DMA_DST block.
60484     #define XSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                            11
60485     #define XSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                  (0x1<<12) // BRB src addr fifo error in DMA_DST block.
60486     #define XSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                            12
60487     #define XSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                      (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
60488     #define XSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                13
60489     #define XSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                  (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
60490     #define XSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                            14
60491     #define XSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                   (0x1<<15) // Read data firo in DMA_RSP block for BRB.
60492     #define XSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                             15
60493     #define XSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                               (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
60494     #define XSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                         16
60495     #define XSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                   (0x1<<17) // PXP read data fifo error in DMA_RSP block.
60496     #define XSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                             17
60497     #define XSDM_REG_INT_STS_CM_DELAY_ERROR                                                          (0x1<<18) // Delay CM fifo error in CM block.
60498     #define XSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                    18
60499     #define XSDM_REG_INT_STS_SH_DELAY_ERROR                                                          (0x1<<19) // Delay shared fifo error in CM block.
60500     #define XSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                    19
60501     #define XSDM_REG_INT_STS_CMPL_PEND_ERROR                                                         (0x1<<20) // Error in completion pending FIFO in internal write block.
60502     #define XSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                   20
60503     #define XSDM_REG_INT_STS_CPRM_PEND_ERROR                                                         (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
60504     #define XSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                   21
60505     #define XSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                        (0x1<<22) // Address fifo error in timer block.
60506     #define XSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                  22
60507     #define XSDM_REG_INT_STS_TIMER_PEND_ERROR                                                        (0x1<<23) // Pending fifo error in timer block.
60508     #define XSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                  23
60509     #define XSDM_REG_INT_STS_DORQ_DPM_ERROR                                                          (0x1<<24) // Dpm fifo error in dorq I/F block.
60510     #define XSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                    24
60511     #define XSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                      (0x1<<25) // PXP done fifo error in DMA_dst block.
60512     #define XSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                25
60513     #define XSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
60514     #define XSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_SHIFT                                              26
60515     #define XSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
60516     #define XSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_SHIFT                                              27
60517 #define XSDM_REG_INT_MASK                                                                            0xf80044UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60518     #define XSDM_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.ADDRESS_ERROR .
60519     #define XSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
60520     #define XSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.INP_QUEUE_ERROR .
60521     #define XSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                  1
60522     #define XSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DELAY_FIFO_ERROR .
60523     #define XSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                 2
60524     #define XSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.ASYNC_HOST_ERROR .
60525     #define XSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                 3
60526     #define XSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.PRM_FIFO_ERROR .
60527     #define XSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                   4
60528     #define XSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
60529     #define XSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                             5
60530     #define XSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
60531     #define XSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                             6
60532     #define XSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
60533     #define XSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                           7
60534     #define XSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
60535     #define XSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                           8
60536     #define XSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
60537     #define XSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                              9
60538     #define XSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
60539     #define XSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                           10
60540     #define XSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
60541     #define XSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                           11
60542     #define XSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
60543     #define XSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                           12
60544     #define XSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
60545     #define XSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                               13
60546     #define XSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
60547     #define XSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                           14
60548     #define XSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                  (0x1<<15) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
60549     #define XSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                            15
60550     #define XSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
60551     #define XSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                        16
60552     #define XSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
60553     #define XSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                            17
60554     #define XSDM_REG_INT_MASK_CM_DELAY_ERROR                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CM_DELAY_ERROR .
60555     #define XSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                   18
60556     #define XSDM_REG_INT_MASK_SH_DELAY_ERROR                                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.SH_DELAY_ERROR .
60557     #define XSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                   19
60558     #define XSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                        (0x1<<20) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CMPL_PEND_ERROR .
60559     #define XSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                  20
60560     #define XSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.CPRM_PEND_ERROR .
60561     #define XSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                  21
60562     #define XSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TIMER_ADDR_ERROR .
60563     #define XSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                 22
60564     #define XSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                       (0x1<<23) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.TIMER_PEND_ERROR .
60565     #define XSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                 23
60566     #define XSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DORQ_DPM_ERROR .
60567     #define XSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                   24
60568     #define XSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                     (0x1<<25) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
60569     #define XSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                               25
60570     #define XSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR                                                   (0x1<<26) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
60571     #define XSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_SHIFT                                             26
60572     #define XSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: XSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
60573     #define XSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_SHIFT                                             27
60574 #define XSDM_REG_INT_STS_WR                                                                          0xf80048UL //Access:WR   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60575     #define XSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
60576     #define XSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
60577     #define XSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                      (0x1<<1) // Indicates that one of the input queues had a FIFO error.
60578     #define XSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                1
60579     #define XSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                     (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
60580     #define XSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                               2
60581     #define XSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                     (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
60582     #define XSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                               3
60583     #define XSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                       (0x1<<4) // FIFO in PRM interface sub-module reported an error.
60584     #define XSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                 4
60585     #define XSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                 (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
60586     #define XSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                           5
60587     #define XSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                 (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
60588     #define XSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                           6
60589     #define XSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                               (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
60590     #define XSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                         7
60591     #define XSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                               (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
60592     #define XSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                         8
60593     #define XSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                  (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
60594     #define XSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                            9
60595     #define XSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                               (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
60596     #define XSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                         10
60597     #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                               (0x1<<11) // BRB src pend fifo error in DMA_DST block.
60598     #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                         11
60599     #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                               (0x1<<12) // BRB src addr fifo error in DMA_DST block.
60600     #define XSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                         12
60601     #define XSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                   (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
60602     #define XSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                             13
60603     #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                               (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
60604     #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                         14
60605     #define XSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                (0x1<<15) // Read data firo in DMA_RSP block for BRB.
60606     #define XSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                          15
60607     #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                            (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
60608     #define XSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                      16
60609     #define XSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                (0x1<<17) // PXP read data fifo error in DMA_RSP block.
60610     #define XSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                          17
60611     #define XSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                       (0x1<<18) // Delay CM fifo error in CM block.
60612     #define XSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                 18
60613     #define XSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                       (0x1<<19) // Delay shared fifo error in CM block.
60614     #define XSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                 19
60615     #define XSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                      (0x1<<20) // Error in completion pending FIFO in internal write block.
60616     #define XSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                20
60617     #define XSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                      (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
60618     #define XSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                21
60619     #define XSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                     (0x1<<22) // Address fifo error in timer block.
60620     #define XSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                               22
60621     #define XSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                     (0x1<<23) // Pending fifo error in timer block.
60622     #define XSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                               23
60623     #define XSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                       (0x1<<24) // Dpm fifo error in dorq I/F block.
60624     #define XSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                 24
60625     #define XSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                   (0x1<<25) // PXP done fifo error in DMA_dst block.
60626     #define XSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                             25
60627     #define XSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR                                                 (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
60628     #define XSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_SHIFT                                           26
60629     #define XSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR                                                 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
60630     #define XSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_SHIFT                                           27
60631 #define XSDM_REG_INT_STS_CLR                                                                         0xf8004cUL //Access:RC   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60632     #define XSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
60633     #define XSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
60634     #define XSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                     (0x1<<1) // Indicates that one of the input queues had a FIFO error.
60635     #define XSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                               1
60636     #define XSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                    (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
60637     #define XSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                              2
60638     #define XSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                    (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
60639     #define XSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                              3
60640     #define XSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                      (0x1<<4) // FIFO in PRM interface sub-module reported an error.
60641     #define XSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                4
60642     #define XSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
60643     #define XSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                          5
60644     #define XSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
60645     #define XSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                          6
60646     #define XSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                              (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
60647     #define XSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                        7
60648     #define XSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                              (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
60649     #define XSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                        8
60650     #define XSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                 (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
60651     #define XSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                           9
60652     #define XSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                              (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
60653     #define XSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                        10
60654     #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                              (0x1<<11) // BRB src pend fifo error in DMA_DST block.
60655     #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                        11
60656     #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                              (0x1<<12) // BRB src addr fifo error in DMA_DST block.
60657     #define XSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                        12
60658     #define XSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                  (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
60659     #define XSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                            13
60660     #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                              (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
60661     #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                        14
60662     #define XSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                               (0x1<<15) // Read data firo in DMA_RSP block for BRB.
60663     #define XSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                         15
60664     #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                           (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
60665     #define XSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                     16
60666     #define XSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                               (0x1<<17) // PXP read data fifo error in DMA_RSP block.
60667     #define XSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                         17
60668     #define XSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                      (0x1<<18) // Delay CM fifo error in CM block.
60669     #define XSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                18
60670     #define XSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                      (0x1<<19) // Delay shared fifo error in CM block.
60671     #define XSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                19
60672     #define XSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                     (0x1<<20) // Error in completion pending FIFO in internal write block.
60673     #define XSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                               20
60674     #define XSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                     (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
60675     #define XSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                               21
60676     #define XSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                    (0x1<<22) // Address fifo error in timer block.
60677     #define XSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                              22
60678     #define XSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                    (0x1<<23) // Pending fifo error in timer block.
60679     #define XSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                              23
60680     #define XSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                      (0x1<<24) // Dpm fifo error in dorq I/F block.
60681     #define XSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                24
60682     #define XSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                  (0x1<<25) // PXP done fifo error in DMA_dst block.
60683     #define XSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                            25
60684     #define XSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR                                                (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
60685     #define XSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_SHIFT                                          26
60686     #define XSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR                                                (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
60687     #define XSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_SHIFT                                          27
60688 #define XSDM_REG_PRTY_MASK_H_0                                                                       0xf80204UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
60689     #define XSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
60690     #define XSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           0
60691     #define XSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
60692     #define XSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           1
60693     #define XSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
60694     #define XSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           2
60695     #define XSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
60696     #define XSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           3
60697     #define XSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
60698     #define XSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           4
60699     #define XSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
60700     #define XSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                           5
60701     #define XSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
60702     #define XSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           6
60703     #define XSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
60704     #define XSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           7
60705     #define XSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
60706     #define XSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           8
60707     #define XSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<9) // This bit masks, when set, the Parity bit: XSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
60708     #define XSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           9
60709 #define XSDM_REG_MEM_ECC_EVENTS                                                                      0xf80210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
60710 #define XSDM_REG_MEM008_I_MEM_DFT_K2                                                                 0xf80218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_pxp_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
60711 #define XSDM_REG_MEM007_I_MEM_DFT_K2                                                                 0xf8021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_int_ram_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
60712 #define XSDM_REG_MEM006_I_MEM_DFT_K2                                                                 0xf80220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsdm.i_sdm_core.i_sdm_dma.i_sdm_dma_dst.i_sdm_dma_immed_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
60713 #define XSDM_REG_MEM003_I_MEM_DFT_K2                                                                 0xf80224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsdm.i_sdm_core.i_sdm_async.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
60714 #define XSDM_REG_MEM010_I_MEM_DFT_K2                                                                 0xf80228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsdm.i_sdm_core.i_sdm_timers_sram_wrap.XSDM_TIMERS_RAM_GEN_IF.i_sdm_timers_ram_xsdm.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
60715 #define XSDM_REG_MEM002_I_MEM_DFT_K2                                                                 0xf8022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsdm.i_sdm_core.i_inp_que_ram_wrap.DEFAULT_INP_QUE_RAM_GEN_IF.i_sdm_inp_que_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
60716 #define XSDM_REG_MEM004_I_MEM_DFT_K2                                                                 0xf80230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsdm.i_sdm_core.i_sdm_cmp_msg_que_ram_wrap.XSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_xsdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
60717 #define XSDM_REG_MEM001_I_MEM_DFT_K2                                                                 0xf80234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsdm.i_sdm_core.DORQ_INTERFACE_GEN_IF.i_sdm_dorq.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
60718 #define XSDM_REG_TIMER_TICK                                                                          0xf80400UL //Access:RW   DataWidth:0x20  Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.  Chips: BB_A0 BB_B0 K2
60719 #define XSDM_REG_TIMERS_TICK_ENABLE                                                                  0xf80404UL //Access:RW   DataWidth:0x1   Enable for tick counter.  Chips: BB_A0 BB_B0 K2
60720 #define XSDM_REG_OPERATION_GEN                                                                       0xf80408UL //Access:W    DataWidth:0x14  This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.  Chips: BB_A0 BB_B0 K2
60721 #define XSDM_REG_GRC_PRIVILEGE_LEVEL                                                                 0xf8040cUL //Access:RW   DataWidth:0x2   This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.  Chips: BB_A0 BB_B0 K2
60722 #define XSDM_REG_CM_MSG_CNT_ADDRESS                                                                  0xf80410UL //Access:RW   DataWidth:0xf   The internal RAM address for storing the shadow of the CM completion message counter.  Chips: BB_A0 BB_B0 K2
60723 #define XSDM_REG_DORQ_DPM_START_ADDR                                                                 0xf80414UL //Access:RW   DataWidth:0xf   The start address in the internal RAM for DORQ DPM messages.  Chips: BB_A0 BB_B0 K2
60724 #define XSDM_REG_RR_COMPLETE_REQ                                                                     0xf80418UL //Access:R    DataWidth:0xa   Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.  Chips: BB_A0 BB_B0 K2
60725 #define XSDM_REG_RR_PTR_REQ                                                                          0xf8041cUL //Access:R    DataWidth:0x9   Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.  Chips: BB_A0 BB_B0 K2
60726 #define XSDM_REG_INT_RAM_RR_REQ                                                                      0xf80420UL //Access:R    DataWidth:0x4   Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.  Chips: BB_A0 BB_B0 K2
60727 #define XSDM_REG_INP_QUEUE_ERR_VECT                                                                  0xf80424UL //Access:R    DataWidth:0x9   This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.  Chips: BB_A0 BB_B0 K2
60728 #define XSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                              0xf80428UL //Access:RW   DataWidth:0x5   This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.  Chips: BB_A0 BB_B0 K2
60729 #define XSDM_REG_ECO_RESERVED                                                                        0xf8042cUL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
60730 #define XSDM_REG_INIT_CREDIT_PXP                                                                     0xf80500UL //Access:RW   DataWidth:0x3   The initial number of messages that can be sent to the pxp interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
60731 #define XSDM_REG_INIT_CREDIT_PCI                                                                     0xf80504UL //Access:RW   DataWidth:0x2   The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
60732 #define XSDM_REG_INIT_CREDIT_TCFC_AC                                                                 0xf80508UL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
60733 #define XSDM_REG_INIT_CREDIT_CCFC_AC                                                                 0xf8050cUL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
60734 #define XSDM_REG_INIT_CREDIT_CM                                                                      0xf80510UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
60735 #define XSDM_REG_INIT_CREDIT_CM_RMT                                                                  0xf80520UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
60736 #define XSDM_REG_NUM_OF_DMA_CMD                                                                      0xf80600UL //Access:RC   DataWidth:0x20  The number of SDM DMA commands executed.  Chips: BB_A0 BB_B0 K2
60737 #define XSDM_REG_NUM_OF_TIMERS_CMD                                                                   0xf80604UL //Access:RC   DataWidth:0x20  The number of SDM timers commands executed.  Chips: BB_A0 BB_B0 K2
60738 #define XSDM_REG_NUM_OF_CCFC_LD_CMD                                                                  0xf80608UL //Access:RC   DataWidth:0x20  The number of SDM CCFC load commands executed.  Chips: BB_A0 BB_B0 K2
60739 #define XSDM_REG_NUM_OF_CCFC_AC_CMD                                                                  0xf8060cUL //Access:RC   DataWidth:0x20  The number of SDM CCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
60740 #define XSDM_REG_NUM_OF_TCFC_LD_CMD                                                                  0xf80610UL //Access:RC   DataWidth:0x20  The number of SDM TCFC load commands executed.  Chips: BB_A0 BB_B0 K2
60741 #define XSDM_REG_NUM_OF_TCFC_AC_CMD                                                                  0xf80614UL //Access:RC   DataWidth:0x20  The number of SDM TCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
60742 #define XSDM_REG_NUM_OF_INT_CMD                                                                      0xf80618UL //Access:RC   DataWidth:0x20  The number of SDM internal write commands executed.  Chips: BB_A0 BB_B0 K2
60743 #define XSDM_REG_NUM_OF_NOP_CMD                                                                      0xf8061cUL //Access:RC   DataWidth:0x20  The number of SDM NOP commands executed.  Chips: BB_A0 BB_B0 K2
60744 #define XSDM_REG_NUM_OF_GRC_CMD                                                                      0xf80620UL //Access:RC   DataWidth:0x20  The number of GRC master commands executed.  Chips: BB_A0 BB_B0 K2
60745 #define XSDM_REG_NUM_OF_PRM_REQ                                                                      0xf80624UL //Access:RC   DataWidth:0x20  The number of packet end messages received on the PRM completion interface.  Chips: BB_A0 BB_B0 K2
60746 #define XSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                0xf80628UL //Access:RC   DataWidth:0x20  The number of requests received from the pxp async if.  Chips: BB_A0 BB_B0 K2
60747 #define XSDM_REG_NUM_OF_DPM_REQ                                                                      0xf8062cUL //Access:RC   DataWidth:0x20  The number of DORQ DPM messages received.  Chips: BB_A0 BB_B0 K2
60748 #define XSDM_REG_BRB_ALMOST_FULL                                                                     0xf80700UL //Access:RW   DataWidth:0x5   Almost full signal for read data from BRB in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
60749 #define XSDM_REG_PXP_ALMOST_FULL                                                                     0xf80704UL //Access:RW   DataWidth:0x4   Almost full signal for read data from pxp in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
60750 #define XSDM_REG_DORQ_ALMOST_FULL                                                                    0xf80708UL //Access:RW   DataWidth:0x6   Almost full signal for read data from DORQ in SDM_DORQ block.  Chips: BB_A0 BB_B0 K2
60751 #define XSDM_REG_AGG_INT_CTRL                                                                        0xf80800UL //Access:RW   DataWidth:0xa   This array of registers provides controls for each of 32 aggregated interrupts; The fiels are defined as follows: agg_int_ctrl[7:0] = EventID which selects the event ID of the associated handler; agg_int_ctrl[8] = T-flag which determines if a thread is allocated for this handler in the Storm; agg_int_ctrl[9] = Mode bit; where 0=normal and 1=auto-mask-mode.  Chips: BB_A0 BB_B0 K2
60752 #define XSDM_REG_AGG_INT_CTRL_SIZE                                                                   32
60753 #define XSDM_REG_AGG_INT_STATE                                                                       0xf80a00UL //Access:R    DataWidth:0x2   This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.  Chips: BB_A0 BB_B0 K2
60754 #define XSDM_REG_AGG_INT_STATE_SIZE                                                                  32
60755 #define XSDM_REG_QUEUE_FULL                                                                          0xf80c00UL //Access:R    DataWidth:0x9   Input queue fifo full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
60756 #define XSDM_REG_INT_CMPL_PEND_FULL                                                                  0xf80c04UL //Access:R    DataWidth:0x1   Internal write completion pending full in internal write block.  Chips: BB_A0 BB_B0 K2
60757 #define XSDM_REG_INT_CPRM_PEND_FULL                                                                  0xf80c08UL //Access:R    DataWidth:0x1   Internal write completion parameter pending full in internal write block.  Chips: BB_A0 BB_B0 K2
60758 #define XSDM_REG_QM_FULL                                                                             0xf80c0cUL //Access:R    DataWidth:0x1   QM IF  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
60759 #define XSDM_REG_DELAY_FIFO_FULL                                                                     0xf80c10UL //Access:R    DataWidth:0x1   Delay FIFO  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
60760 #define XSDM_REG_TIMERS_PEND_FULL                                                                    0xf80c14UL //Access:R    DataWidth:0x1   Pending FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
60761 #define XSDM_REG_TIMERS_ADDR_FULL                                                                    0xf80c18UL //Access:R    DataWidth:0x1   Address FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
60762 #define XSDM_REG_RSP_PXP_RDATA_FULL                                                                  0xf80c1cUL //Access:R    DataWidth:0x1   PXP rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60763 #define XSDM_REG_RSP_BRB_RDATA_FULL                                                                  0xf80c20UL //Access:R    DataWidth:0x1   BRB read data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60764 #define XSDM_REG_RSP_INT_RAM_RDATA_FULL                                                              0xf80c24UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60765 #define XSDM_REG_RSP_BRB_PEND_FULL                                                                   0xf80c28UL //Access:R    DataWidth:0x1   BRB pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60766 #define XSDM_REG_RSP_INT_RAM_PEND_FULL                                                               0xf80c2cUL //Access:R    DataWidth:0x1   Int_ram pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60767 #define XSDM_REG_RSP_BRB_IF_FULL                                                                     0xf80c30UL //Access:R    DataWidth:0x1   BRB interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60768 #define XSDM_REG_RSP_PXP_IF_FULL                                                                     0xf80c34UL //Access:R    DataWidth:0x1   PXP interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60769 #define XSDM_REG_DST_PXP_IMMED_FULL                                                                  0xf80c38UL //Access:R    DataWidth:0x1   PXP immediate fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60770 #define XSDM_REG_DST_PXP_DST_PEND_FULL                                                               0xf80c3cUL //Access:R    DataWidth:0x1   PXP destination pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60771 #define XSDM_REG_DST_PXP_SRC_PEND_FULL                                                               0xf80c40UL //Access:R    DataWidth:0x1   PXP source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60772 #define XSDM_REG_DST_BRB_SRC_PEND_FULL                                                               0xf80c44UL //Access:R    DataWidth:0x1   BRB source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60773 #define XSDM_REG_DST_BRB_SRC_ADDR_FULL                                                               0xf80c48UL //Access:R    DataWidth:0x1   BRB source address fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60774 #define XSDM_REG_DST_PXP_LINK_FULL                                                                   0xf80c4cUL //Access:R    DataWidth:0x1   PXP link list full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60775 #define XSDM_REG_DST_INT_RAM_WAIT_FULL                                                               0xf80c50UL //Access:R    DataWidth:0x1   Int_ram_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60776 #define XSDM_REG_DST_PAS_BUF_WAIT_FULL                                                               0xf80c54UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60777 #define XSDM_REG_DST_PXP_IF_FULL                                                                     0xf80c58UL //Access:R    DataWidth:0x1   PXP if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60778 #define XSDM_REG_DST_INT_RAM_IF_FULL                                                                 0xf80c5cUL //Access:R    DataWidth:0x1   Int_ram if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60779 #define XSDM_REG_DST_PAS_BUF_IF_FULL                                                                 0xf80c60UL //Access:R    DataWidth:0x1   Pas_buf if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60780 #define XSDM_REG_SH_DELAY_FULL                                                                       0xf80c64UL //Access:R    DataWidth:0x1   Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
60781 #define XSDM_REG_CM_DELAY_FULL                                                                       0xf80c68UL //Access:R    DataWidth:0x1   CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
60782 #define XSDM_REG_CMSG_QUE_FULL                                                                       0xf80c6cUL //Access:R    DataWidth:0x1   Completion message queue fifo full in sdm_cm block.  Chips: BB_A0 BB_B0 K2
60783 #define XSDM_REG_CCFC_LOAD_PEND_FULL                                                                 0xf80c70UL //Access:R    DataWidth:0x1   CCFC load pending fifo full in the CCFC interface  block.  Chips: BB_A0 BB_B0 K2
60784 #define XSDM_REG_TCFC_LOAD_PEND_FULL                                                                 0xf80c74UL //Access:R    DataWidth:0x1   TCFC load pending fifo full in the TCFC interface block.  Chips: BB_A0 BB_B0 K2
60785 #define XSDM_REG_ASYNC_HOST_FULL                                                                     0xf80c78UL //Access:R    DataWidth:0x1   Async fifo full in sdm_async block.  Chips: BB_A0 BB_B0 K2
60786 #define XSDM_REG_PRM_FIFO_FULL                                                                       0xf80c7cUL //Access:R    DataWidth:0x1   PRM FIFO full in PRM interface block.  Chips: BB_A0 BB_B0 K2
60787 #define XSDM_REG_RMT_XCM_FIFO_FULL                                                                   0xf80c80UL //Access:R    DataWidth:0x1   Remote XCM FIFO full (exist only in MSDM => XCM interface).  Chips: K2
60788 #define XSDM_REG_RMT_YCM_FIFO_FULL                                                                   0xf80c84UL //Access:R    DataWidth:0x1   Remote YCM FIFO full (exist only in MSDM => YCM interface).  Chips: K2
60789 #define XSDM_REG_INT_CMPL_PEND_EMPTY                                                                 0xf80d00UL //Access:R    DataWidth:0x1   Internal write completion pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
60790 #define XSDM_REG_INT_CPRM_PEND_EMPTY                                                                 0xf80d04UL //Access:R    DataWidth:0x1   Internal write completion parameter pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
60791 #define XSDM_REG_QUEUE_EMPTY                                                                         0xf80d08UL //Access:R    DataWidth:0x9   Input queue fifo empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
60792 #define XSDM_REG_DELAY_FIFO_EMPTY                                                                    0xf80d0cUL //Access:R    DataWidth:0x1   Delay FIFO  empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
60793 #define XSDM_REG_TIMERS_PEND_EMPTY                                                                   0xf80d10UL //Access:R    DataWidth:0x1   Pending FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
60794 #define XSDM_REG_TIMERS_ADDR_EMPTY                                                                   0xf80d14UL //Access:R    DataWidth:0x1   Address FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
60795 #define XSDM_REG_RSP_PXP_RDATA_EMPTY                                                                 0xf80d18UL //Access:R    DataWidth:0x1   PXP rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60796 #define XSDM_REG_RSP_BRB_RDATA_EMPTY                                                                 0xf80d1cUL //Access:R    DataWidth:0x1   BRB read data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60797 #define XSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                             0xf80d20UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60798 #define XSDM_REG_RSP_BRB_PEND_EMPTY                                                                  0xf80d24UL //Access:R    DataWidth:0x1   BRB pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60799 #define XSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                              0xf80d28UL //Access:R    DataWidth:0x1   Int_ram pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
60800 #define XSDM_REG_DST_PXP_IMMED_EMPTY                                                                 0xf80d2cUL //Access:R    DataWidth:0x1   PXP immediate fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60801 #define XSDM_REG_DST_PXP_DST_PEND_EMPTY                                                              0xf80d30UL //Access:R    DataWidth:0x1   PXP destination pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60802 #define XSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                              0xf80d34UL //Access:R    DataWidth:0x1   PXP source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60803 #define XSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                              0xf80d38UL //Access:R    DataWidth:0x1   BRB source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60804 #define XSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                              0xf80d3cUL //Access:R    DataWidth:0x1   BRB source address fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60805 #define XSDM_REG_DST_PXP_LINK_EMPTY                                                                  0xf80d40UL //Access:R    DataWidth:0x1   PXP link list empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60806 #define XSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                              0xf80d44UL //Access:R    DataWidth:0x1   Int_ram_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60807 #define XSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                              0xf80d48UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60808 #define XSDM_REG_SH_DELAY_EMPTY                                                                      0xf80d4cUL //Access:R    DataWidth:0x1   Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
60809 #define XSDM_REG_CM_DELAY_EMPTY                                                                      0xf80d50UL //Access:R    DataWidth:0x1   CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
60810 #define XSDM_REG_CMSG_QUE_EMPTY                                                                      0xf80d54UL //Access:R    DataWidth:0x1   Completion message queue fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
60811 #define XSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                0xf80d58UL //Access:R    DataWidth:0x1   CCFC load pending fifo empty in sdm_ccfc block.  Chips: BB_A0 BB_B0 K2
60812 #define XSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                0xf80d5cUL //Access:R    DataWidth:0x1   TCFC load pending fifo empty in sdm_tcfc block.  Chips: BB_A0 BB_B0 K2
60813 #define XSDM_REG_ASYNC_HOST_EMPTY                                                                    0xf80d60UL //Access:R    DataWidth:0x1   Async fifo empty in sdm_async block.  Chips: BB_A0 BB_B0 K2
60814 #define XSDM_REG_PRM_FIFO_EMPTY                                                                      0xf80d64UL //Access:R    DataWidth:0x1   PRM FIFO empty in sdm_prm_if block.  Chips: BB_A0 BB_B0 K2
60815 #define XSDM_REG_RMT_XCM_FIFO_EMPTY                                                                  0xf80d68UL //Access:R    DataWidth:0x1   Remote XCM FIFO empty (exist only within MSDM => XCM path).  Chips: K2
60816 #define XSDM_REG_RMT_YCM_FIFO_EMPTY                                                                  0xf80d6cUL //Access:R    DataWidth:0x1   Remote YCM FIFO empty (exist only within MSDM => YCM path).  Chips: K2
60817 #define XSDM_REG_DBG_OUT_DATA                                                                        0xf80e00UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
60818 #define XSDM_REG_DBG_OUT_DATA_SIZE                                                                   8
60819 #define XSDM_REG_DBG_OUT_VALID                                                                       0xf80e20UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
60820 #define XSDM_REG_DBG_OUT_FRAME                                                                       0xf80e24UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
60821 #define XSDM_REG_DBG_SELECT                                                                          0xf80e28UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
60822 #define XSDM_REG_DBG_DWORD_ENABLE                                                                    0xf80e2cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
60823 #define XSDM_REG_DBG_SHIFT                                                                           0xf80e30UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
60824 #define XSDM_REG_DBG_FORCE_VALID                                                                     0xf80e34UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
60825 #define XSDM_REG_DBG_FORCE_FRAME                                                                     0xf80e38UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
60826 #define XSDM_REG_ASYNC_FIFO                                                                          0xf82000UL //Access:WB_R DataWidth:0x49  Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60827 #define XSDM_REG_ASYNC_FIFO_SIZE                                                                     116
60828 #define XSDM_REG_IMMED_FIFO                                                                          0xf82400UL //Access:WB_R DataWidth:0x40  Provides read-only access of the immediate data FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60829 #define XSDM_REG_IMMED_FIFO_SIZE                                                                     38
60830 #define XSDM_REG_BRB_FIFO                                                                            0xf82800UL //Access:WB_R DataWidth:0x86  Provides read-only access of the BRB response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60831 #define XSDM_REG_BRB_FIFO_SIZE                                                                       152
60832 #define XSDM_REG_PXP_FIFO                                                                            0xf82c00UL //Access:WB_R DataWidth:0x4a  Provides read-only access of the PXP response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60833 #define XSDM_REG_PXP_FIFO_SIZE                                                                       76
60834 #define XSDM_REG_INT_RAM_FIFO                                                                        0xf83000UL //Access:WB_R DataWidth:0x41  Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60835 #define XSDM_REG_INT_RAM_FIFO_SIZE                                                                   76
60836 #define XSDM_REG_DPM_FIFO                                                                            0xf83400UL //Access:WB_R DataWidth:0x51  Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60837 #define XSDM_REG_DPM_FIFO_SIZE                                                                       172
60838 #define XSDM_REG_EXT_OVERFLOW                                                                        0xf83800UL //Access:WB_R DataWidth:0x4b  Provides read-only access of the external store overflow FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60839 #define XSDM_REG_EXT_OVERFLOW_SIZE                                                                   36
60840 #define XSDM_REG_PRM_FIFO                                                                            0xf83c00UL //Access:WB_R DataWidth:0x41  Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60841 #define XSDM_REG_PRM_FIFO_SIZE                                                                       84
60842 #define XSDM_REG_TIMERS                                                                              0xf84000UL //Access:WB   DataWidth:0x39  Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
60843 #define XSDM_REG_TIMERS_SIZE                                                                         48
60844 #define XSDM_REG_INP_QUEUE                                                                           0xf85000UL //Access:WB   DataWidth:0x40  Input queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
60845 #define XSDM_REG_INP_QUEUE_SIZE                                                                      416
60846 #define XSDM_REG_CMSG_QUE                                                                            0xf88000UL //Access:WB   DataWidth:0x40  CM queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
60847 #define XSDM_REG_CMSG_QUE_SIZE                                                                       128
60848 #define YSDM_REG_ENABLE_IN1                                                                          0xf90004UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60849     #define YSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                      (0x1<<0) // Enable for input command from STORM.
60850     #define YSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                0
60851     #define YSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                   (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
60852     #define YSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                             1
60853     #define YSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                   (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
60854     #define YSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                             2
60855     #define YSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                   (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
60856     #define YSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                             3
60857     #define YSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                   (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
60858     #define YSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                             4
60859     #define YSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                   (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
60860     #define YSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                             5
60861     #define YSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                       (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
60862     #define YSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                 6
60863     #define YSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                       (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
60864     #define YSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                 7
60865     #define YSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                       (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
60866     #define YSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                 8
60867     #define YSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                    (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
60868     #define YSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                              9
60869     #define YSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                        (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
60870     #define YSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                  10
60871     #define YSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                       (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
60872     #define YSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                 11
60873     #define YSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                        (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
60874     #define YSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                  12
60875     #define YSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                        (0x1<<13) // Enable for input completion message from PRM in prm_if block.
60876     #define YSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                  13
60877     #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                  (0x1<<14) // Enable for input ack to CCFC load credit counter.
60878     #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                            14
60879     #define YSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                  (0x1<<15) // Enable for input ack to TCFC load credit counter.
60880     #define YSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                            15
60881     #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                  (0x1<<16) // Enable for input response from CCFC in CCFC block.
60882     #define YSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                            16
60883     #define YSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                    (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
60884     #define YSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                              17
60885     #define YSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                    (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
60886     #define YSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                              18
60887     #define YSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                 (0x1<<19) // Enable for input full from qm in SDM_INP block.
60888     #define YSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                           19
60889 #define YSDM_REG_ENABLE_IN2                                                                          0xf90008UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
60890     #define YSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                  (0x1<<0) // Enable for input response from TCFC in TCFC block.
60891     #define YSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                            0
60892     #define YSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                         (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
60893     #define YSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                   1
60894     #define YSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                       (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
60895     #define YSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                 2
60896 #define YSDM_REG_ENABLE_OUT1                                                                         0xf9000cUL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60897     #define YSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                      (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
60898     #define YSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                0
60899     #define YSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                   (0x1<<1) // Enable for output thread ready to the SEMI.
60900     #define YSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                             1
60901     #define YSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                   (0x1<<2) // Enable the output thread release to the SEMI.
60902     #define YSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                             2
60903     #define YSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                    (0x1<<3) // Enable for output load request to CCFC.
60904     #define YSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                              3
60905     #define YSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                    (0x1<<4) // Enable for output load request to TCFC.
60906     #define YSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                              4
60907     #define YSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                      (0x1<<5) // Enable for output increment to CCFC activity counter.
60908     #define YSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                5
60909     #define YSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                      (0x1<<6) // Enable for output decrement to TCFC activity counter.
60910     #define YSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                6
60911     #define YSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                      (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
60912     #define YSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                7
60913     #define YSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                      (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
60914     #define YSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                8
60915     #define YSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                      (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
60916     #define YSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                9
60917     #define YSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                      (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
60918     #define YSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                10
60919     #define YSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                    (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
60920     #define YSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                              11
60921     #define YSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                          (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
60922     #define YSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                    12
60923     #define YSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                     (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
60924     #define YSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                               13
60925     #define YSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                     (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
60926     #define YSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                               14
60927     #define YSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                     (0x1<<15) // Enable for output external full to SEMI block.
60928     #define YSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                               15
60929     #define YSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                 (0x1<<16) // Enable for output done to async PXP host IF.
60930     #define YSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                           16
60931     #define YSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                 (0x1<<17) // Enable the output done (ack) to PRM.
60932     #define YSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                           17
60933     #define YSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                       (0x1<<18) // Enable for output message to CM in SDM_CM block.
60934     #define YSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                 18
60935     #define YSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                 (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
60936     #define YSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                           19
60937     #define YSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                 (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
60938     #define YSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                           20
60939 #define YSDM_REG_ENABLE_OUT2                                                                         0xf90010UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
60940     #define YSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                    (0x1<<0) // Enable for output command to qm in SDM_INP block.
60941     #define YSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                              0
60942     #define YSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                     (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
60943     #define YSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                               1
60944     #define YSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
60945     #define YSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                          2
60946 #define YSDM_REG_DISABLE_ENGINE                                                                      0xf90014UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
60947     #define YSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                      (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
60948     #define YSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                0
60949     #define YSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                   (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
60950     #define YSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                             1
60951     #define YSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
60952     #define YSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                          2
60953     #define YSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
60954     #define YSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                          3
60955     #define YSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                   (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
60956     #define YSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                             4
60957     #define YSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                      (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
60958     #define YSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                5
60959     #define YSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                      (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
60960     #define YSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                6
60961     #define YSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                    (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
60962     #define YSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                              7
60963     #define YSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                      (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
60964     #define YSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                8
60965     #define YSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                     (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
60966     #define YSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                               9
60967 #define YSDM_REG_INT_STS                                                                             0xf90040UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
60968     #define YSDM_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
60969     #define YSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
60970     #define YSDM_REG_INT_STS_INP_QUEUE_ERROR                                                         (0x1<<1) // Indicates that one of the input queues had a FIFO error.
60971     #define YSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                   1
60972     #define YSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                        (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
60973     #define YSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                  2
60974     #define YSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                        (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
60975     #define YSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                  3
60976     #define YSDM_REG_INT_STS_PRM_FIFO_ERROR                                                          (0x1<<4) // FIFO in PRM interface sub-module reported an error.
60977     #define YSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                    4
60978     #define YSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                    (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
60979     #define YSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                              5
60980     #define YSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                    (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
60981     #define YSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                              6
60982     #define YSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                  (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
60983     #define YSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                            7
60984     #define YSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                  (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
60985     #define YSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                            8
60986     #define YSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                     (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
60987     #define YSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                               9
60988     #define YSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                  (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
60989     #define YSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                            10
60990     #define YSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                  (0x1<<11) // BRB src pend fifo error in DMA_DST block.
60991     #define YSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                            11
60992     #define YSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                  (0x1<<12) // BRB src addr fifo error in DMA_DST block.
60993     #define YSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                            12
60994     #define YSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                      (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
60995     #define YSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                13
60996     #define YSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                  (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
60997     #define YSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                            14
60998     #define YSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                   (0x1<<15) // Read data firo in DMA_RSP block for BRB.
60999     #define YSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                             15
61000     #define YSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                               (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
61001     #define YSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                         16
61002     #define YSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                   (0x1<<17) // PXP read data fifo error in DMA_RSP block.
61003     #define YSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                             17
61004     #define YSDM_REG_INT_STS_CM_DELAY_ERROR                                                          (0x1<<18) // Delay CM fifo error in CM block.
61005     #define YSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                    18
61006     #define YSDM_REG_INT_STS_SH_DELAY_ERROR                                                          (0x1<<19) // Delay shared fifo error in CM block.
61007     #define YSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                    19
61008     #define YSDM_REG_INT_STS_CMPL_PEND_ERROR                                                         (0x1<<20) // Error in completion pending FIFO in internal write block.
61009     #define YSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                   20
61010     #define YSDM_REG_INT_STS_CPRM_PEND_ERROR                                                         (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
61011     #define YSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                   21
61012     #define YSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                        (0x1<<22) // Address fifo error in timer block.
61013     #define YSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                  22
61014     #define YSDM_REG_INT_STS_TIMER_PEND_ERROR                                                        (0x1<<23) // Pending fifo error in timer block.
61015     #define YSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                  23
61016     #define YSDM_REG_INT_STS_DORQ_DPM_ERROR                                                          (0x1<<24) // Dpm fifo error in dorq I/F block.
61017     #define YSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                    24
61018     #define YSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                      (0x1<<25) // PXP done fifo error in DMA_dst block.
61019     #define YSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                25
61020     #define YSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61021     #define YSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_SHIFT                                              26
61022     #define YSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61023     #define YSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_SHIFT                                              27
61024 #define YSDM_REG_INT_MASK                                                                            0xf90044UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61025     #define YSDM_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.ADDRESS_ERROR .
61026     #define YSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
61027     #define YSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.INP_QUEUE_ERROR .
61028     #define YSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                  1
61029     #define YSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DELAY_FIFO_ERROR .
61030     #define YSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                 2
61031     #define YSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.ASYNC_HOST_ERROR .
61032     #define YSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                 3
61033     #define YSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.PRM_FIFO_ERROR .
61034     #define YSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                   4
61035     #define YSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
61036     #define YSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                             5
61037     #define YSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
61038     #define YSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                             6
61039     #define YSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
61040     #define YSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                           7
61041     #define YSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
61042     #define YSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                           8
61043     #define YSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
61044     #define YSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                              9
61045     #define YSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
61046     #define YSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                           10
61047     #define YSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
61048     #define YSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                           11
61049     #define YSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
61050     #define YSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                           12
61051     #define YSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
61052     #define YSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                               13
61053     #define YSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
61054     #define YSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                           14
61055     #define YSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                  (0x1<<15) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
61056     #define YSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                            15
61057     #define YSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
61058     #define YSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                        16
61059     #define YSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
61060     #define YSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                            17
61061     #define YSDM_REG_INT_MASK_CM_DELAY_ERROR                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CM_DELAY_ERROR .
61062     #define YSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                   18
61063     #define YSDM_REG_INT_MASK_SH_DELAY_ERROR                                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.SH_DELAY_ERROR .
61064     #define YSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                   19
61065     #define YSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                        (0x1<<20) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CMPL_PEND_ERROR .
61066     #define YSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                  20
61067     #define YSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.CPRM_PEND_ERROR .
61068     #define YSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                  21
61069     #define YSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TIMER_ADDR_ERROR .
61070     #define YSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                 22
61071     #define YSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                       (0x1<<23) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.TIMER_PEND_ERROR .
61072     #define YSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                 23
61073     #define YSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DORQ_DPM_ERROR .
61074     #define YSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                   24
61075     #define YSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                     (0x1<<25) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
61076     #define YSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                               25
61077     #define YSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR                                                   (0x1<<26) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
61078     #define YSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_SHIFT                                             26
61079     #define YSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: YSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
61080     #define YSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_SHIFT                                             27
61081 #define YSDM_REG_INT_STS_WR                                                                          0xf90048UL //Access:WR   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61082     #define YSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
61083     #define YSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
61084     #define YSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                      (0x1<<1) // Indicates that one of the input queues had a FIFO error.
61085     #define YSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                1
61086     #define YSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                     (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
61087     #define YSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                               2
61088     #define YSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                     (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
61089     #define YSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                               3
61090     #define YSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                       (0x1<<4) // FIFO in PRM interface sub-module reported an error.
61091     #define YSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                 4
61092     #define YSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                 (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
61093     #define YSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                           5
61094     #define YSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                 (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
61095     #define YSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                           6
61096     #define YSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                               (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
61097     #define YSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                         7
61098     #define YSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                               (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
61099     #define YSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                         8
61100     #define YSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                  (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
61101     #define YSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                            9
61102     #define YSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                               (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
61103     #define YSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                         10
61104     #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                               (0x1<<11) // BRB src pend fifo error in DMA_DST block.
61105     #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                         11
61106     #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                               (0x1<<12) // BRB src addr fifo error in DMA_DST block.
61107     #define YSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                         12
61108     #define YSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                   (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
61109     #define YSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                             13
61110     #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                               (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
61111     #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                         14
61112     #define YSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                (0x1<<15) // Read data firo in DMA_RSP block for BRB.
61113     #define YSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                          15
61114     #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                            (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
61115     #define YSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                      16
61116     #define YSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                (0x1<<17) // PXP read data fifo error in DMA_RSP block.
61117     #define YSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                          17
61118     #define YSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                       (0x1<<18) // Delay CM fifo error in CM block.
61119     #define YSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                 18
61120     #define YSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                       (0x1<<19) // Delay shared fifo error in CM block.
61121     #define YSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                 19
61122     #define YSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                      (0x1<<20) // Error in completion pending FIFO in internal write block.
61123     #define YSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                20
61124     #define YSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                      (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
61125     #define YSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                21
61126     #define YSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                     (0x1<<22) // Address fifo error in timer block.
61127     #define YSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                               22
61128     #define YSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                     (0x1<<23) // Pending fifo error in timer block.
61129     #define YSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                               23
61130     #define YSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                       (0x1<<24) // Dpm fifo error in dorq I/F block.
61131     #define YSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                 24
61132     #define YSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                   (0x1<<25) // PXP done fifo error in DMA_dst block.
61133     #define YSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                             25
61134     #define YSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR                                                 (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61135     #define YSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_SHIFT                                           26
61136     #define YSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR                                                 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61137     #define YSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_SHIFT                                           27
61138 #define YSDM_REG_INT_STS_CLR                                                                         0xf9004cUL //Access:RC   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61139     #define YSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
61140     #define YSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
61141     #define YSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                     (0x1<<1) // Indicates that one of the input queues had a FIFO error.
61142     #define YSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                               1
61143     #define YSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                    (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
61144     #define YSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                              2
61145     #define YSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                    (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
61146     #define YSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                              3
61147     #define YSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                      (0x1<<4) // FIFO in PRM interface sub-module reported an error.
61148     #define YSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                4
61149     #define YSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
61150     #define YSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                          5
61151     #define YSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
61152     #define YSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                          6
61153     #define YSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                              (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
61154     #define YSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                        7
61155     #define YSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                              (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
61156     #define YSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                        8
61157     #define YSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                 (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
61158     #define YSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                           9
61159     #define YSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                              (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
61160     #define YSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                        10
61161     #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                              (0x1<<11) // BRB src pend fifo error in DMA_DST block.
61162     #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                        11
61163     #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                              (0x1<<12) // BRB src addr fifo error in DMA_DST block.
61164     #define YSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                        12
61165     #define YSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                  (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
61166     #define YSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                            13
61167     #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                              (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
61168     #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                        14
61169     #define YSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                               (0x1<<15) // Read data firo in DMA_RSP block for BRB.
61170     #define YSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                         15
61171     #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                           (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
61172     #define YSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                     16
61173     #define YSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                               (0x1<<17) // PXP read data fifo error in DMA_RSP block.
61174     #define YSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                         17
61175     #define YSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                      (0x1<<18) // Delay CM fifo error in CM block.
61176     #define YSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                18
61177     #define YSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                      (0x1<<19) // Delay shared fifo error in CM block.
61178     #define YSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                19
61179     #define YSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                     (0x1<<20) // Error in completion pending FIFO in internal write block.
61180     #define YSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                               20
61181     #define YSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                     (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
61182     #define YSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                               21
61183     #define YSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                    (0x1<<22) // Address fifo error in timer block.
61184     #define YSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                              22
61185     #define YSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                    (0x1<<23) // Pending fifo error in timer block.
61186     #define YSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                              23
61187     #define YSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                      (0x1<<24) // Dpm fifo error in dorq I/F block.
61188     #define YSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                24
61189     #define YSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                  (0x1<<25) // PXP done fifo error in DMA_dst block.
61190     #define YSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                            25
61191     #define YSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR                                                (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61192     #define YSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_SHIFT                                          26
61193     #define YSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR                                                (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61194     #define YSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_SHIFT                                          27
61195 #define YSDM_REG_PRTY_MASK_H_0                                                                       0xf90204UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
61196     #define YSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
61197     #define YSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           0
61198     #define YSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
61199     #define YSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           1
61200     #define YSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
61201     #define YSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           2
61202     #define YSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
61203     #define YSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           3
61204     #define YSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
61205     #define YSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           4
61206     #define YSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
61207     #define YSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           5
61208     #define YSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
61209     #define YSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           6
61210     #define YSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
61211     #define YSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           7
61212     #define YSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: YSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
61213     #define YSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           8
61214 #define YSDM_REG_MEM_ECC_EVENTS                                                                      0xf90210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
61215 #define YSDM_REG_MEM007_I_MEM_DFT_K2                                                                 0xf90218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_pxp_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61216 #define YSDM_REG_MEM006_I_MEM_DFT_K2                                                                 0xf9021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_int_ram_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61217 #define YSDM_REG_MEM005_I_MEM_DFT_K2                                                                 0xf90220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysdm.i_sdm_core.i_sdm_dma.i_sdm_dma_dst.i_sdm_dma_immed_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61218 #define YSDM_REG_MEM002_I_MEM_DFT_K2                                                                 0xf90224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysdm.i_sdm_core.i_sdm_async.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61219 #define YSDM_REG_MEM009_I_MEM_DFT_K2                                                                 0xf90228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysdm.i_sdm_core.i_sdm_timers_sram_wrap.PSDM_TIMERS_RAM_GEN_IF.i_sdm_timers_ram_ysdm.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
61220 #define YSDM_REG_MEM001_I_MEM_DFT_K2                                                                 0xf9022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysdm.i_sdm_core.i_inp_que_ram_wrap.YSDM_INP_QUE_RAM_GEN_IF.i_sdm_inp_que_ram_ysdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61221 #define YSDM_REG_MEM003_I_MEM_DFT_K2                                                                 0xf90230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysdm.i_sdm_core.i_sdm_cmp_msg_que_ram_wrap.YSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_ysdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61222 #define YSDM_REG_TIMER_TICK                                                                          0xf90400UL //Access:RW   DataWidth:0x20  Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.  Chips: BB_A0 BB_B0 K2
61223 #define YSDM_REG_TIMERS_TICK_ENABLE                                                                  0xf90404UL //Access:RW   DataWidth:0x1   Enable for tick counter.  Chips: BB_A0 BB_B0 K2
61224 #define YSDM_REG_OPERATION_GEN                                                                       0xf90408UL //Access:W    DataWidth:0x14  This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.  Chips: BB_A0 BB_B0 K2
61225 #define YSDM_REG_GRC_PRIVILEGE_LEVEL                                                                 0xf9040cUL //Access:RW   DataWidth:0x2   This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.  Chips: BB_A0 BB_B0 K2
61226 #define YSDM_REG_CM_MSG_CNT_ADDRESS                                                                  0xf90410UL //Access:RW   DataWidth:0xf   The internal RAM address for storing the shadow of the CM completion message counter.  Chips: BB_A0 BB_B0 K2
61227 #define YSDM_REG_DORQ_DPM_START_ADDR                                                                 0xf90414UL //Access:RW   DataWidth:0xf   The start address in the internal RAM for DORQ DPM messages.  Chips: BB_A0 BB_B0 K2
61228 #define YSDM_REG_RR_COMPLETE_REQ                                                                     0xf90418UL //Access:R    DataWidth:0xa   Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.  Chips: BB_A0 BB_B0 K2
61229 #define YSDM_REG_RR_PTR_REQ                                                                          0xf9041cUL //Access:R    DataWidth:0x9   Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.  Chips: BB_A0 BB_B0 K2
61230 #define YSDM_REG_INT_RAM_RR_REQ                                                                      0xf90420UL //Access:R    DataWidth:0x4   Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.  Chips: BB_A0 BB_B0 K2
61231 #define YSDM_REG_INP_QUEUE_ERR_VECT                                                                  0xf90424UL //Access:R    DataWidth:0x9   This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.  Chips: BB_A0 BB_B0 K2
61232 #define YSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                              0xf90428UL //Access:RW   DataWidth:0x5   This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.  Chips: BB_A0 BB_B0 K2
61233 #define YSDM_REG_ECO_RESERVED                                                                        0xf9042cUL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
61234 #define YSDM_REG_INIT_CREDIT_PXP                                                                     0xf90500UL //Access:RW   DataWidth:0x3   The initial number of messages that can be sent to the pxp interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
61235 #define YSDM_REG_INIT_CREDIT_PCI                                                                     0xf90504UL //Access:RW   DataWidth:0x2   The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
61236 #define YSDM_REG_INIT_CREDIT_TCFC_AC                                                                 0xf90508UL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
61237 #define YSDM_REG_INIT_CREDIT_CCFC_AC                                                                 0xf9050cUL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
61238 #define YSDM_REG_INIT_CREDIT_CM                                                                      0xf90510UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
61239 #define YSDM_REG_INIT_CREDIT_CM_RMT                                                                  0xf90520UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
61240 #define YSDM_REG_INIT_CREDIT_CM_RMT_SIZE                                                             3
61241 #define YSDM_REG_NUM_OF_DMA_CMD                                                                      0xf90600UL //Access:RC   DataWidth:0x20  The number of SDM DMA commands executed.  Chips: BB_A0 BB_B0 K2
61242 #define YSDM_REG_NUM_OF_TIMERS_CMD                                                                   0xf90604UL //Access:RC   DataWidth:0x20  The number of SDM timers commands executed.  Chips: BB_A0 BB_B0 K2
61243 #define YSDM_REG_NUM_OF_CCFC_LD_CMD                                                                  0xf90608UL //Access:RC   DataWidth:0x20  The number of SDM CCFC load commands executed.  Chips: BB_A0 BB_B0 K2
61244 #define YSDM_REG_NUM_OF_CCFC_AC_CMD                                                                  0xf9060cUL //Access:RC   DataWidth:0x20  The number of SDM CCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
61245 #define YSDM_REG_NUM_OF_TCFC_LD_CMD                                                                  0xf90610UL //Access:RC   DataWidth:0x20  The number of SDM TCFC load commands executed.  Chips: BB_A0 BB_B0 K2
61246 #define YSDM_REG_NUM_OF_TCFC_AC_CMD                                                                  0xf90614UL //Access:RC   DataWidth:0x20  The number of SDM TCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
61247 #define YSDM_REG_NUM_OF_INT_CMD                                                                      0xf90618UL //Access:RC   DataWidth:0x20  The number of SDM internal write commands executed.  Chips: BB_A0 BB_B0 K2
61248 #define YSDM_REG_NUM_OF_NOP_CMD                                                                      0xf9061cUL //Access:RC   DataWidth:0x20  The number of SDM NOP commands executed.  Chips: BB_A0 BB_B0 K2
61249 #define YSDM_REG_NUM_OF_GRC_CMD                                                                      0xf90620UL //Access:RC   DataWidth:0x20  The number of GRC master commands executed.  Chips: BB_A0 BB_B0 K2
61250 #define YSDM_REG_NUM_OF_PRM_REQ                                                                      0xf90624UL //Access:RC   DataWidth:0x20  The number of packet end messages received on the PRM completion interface.  Chips: BB_A0 BB_B0 K2
61251 #define YSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                0xf90628UL //Access:RC   DataWidth:0x20  The number of requests received from the pxp async if.  Chips: BB_A0 BB_B0 K2
61252 #define YSDM_REG_NUM_OF_DPM_REQ                                                                      0xf9062cUL //Access:RC   DataWidth:0x20  The number of DORQ DPM messages received.  Chips: BB_A0 BB_B0 K2
61253 #define YSDM_REG_BRB_ALMOST_FULL                                                                     0xf90700UL //Access:RW   DataWidth:0x5   Almost full signal for read data from BRB in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
61254 #define YSDM_REG_PXP_ALMOST_FULL                                                                     0xf90704UL //Access:RW   DataWidth:0x4   Almost full signal for read data from pxp in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
61255 #define YSDM_REG_DORQ_ALMOST_FULL                                                                    0xf90708UL //Access:RW   DataWidth:0x6   Almost full signal for read data from DORQ in SDM_DORQ block.  Chips: BB_A0 BB_B0 K2
61256 #define YSDM_REG_AGG_INT_CTRL                                                                        0xf90800UL //Access:RW   DataWidth:0xa   This array of registers provides controls for each of 32 aggregated interrupts; The fiels are defined as follows: agg_int_ctrl[7:0] = EventID which selects the event ID of the associated handler; agg_int_ctrl[8] = T-flag which determines if a thread is allocated for this handler in the Storm; agg_int_ctrl[9] = Mode bit; where 0=normal and 1=auto-mask-mode.  Chips: BB_A0 BB_B0 K2
61257 #define YSDM_REG_AGG_INT_CTRL_SIZE                                                                   32
61258 #define YSDM_REG_AGG_INT_STATE                                                                       0xf90a00UL //Access:R    DataWidth:0x2   This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.  Chips: BB_A0 BB_B0 K2
61259 #define YSDM_REG_AGG_INT_STATE_SIZE                                                                  32
61260 #define YSDM_REG_QUEUE_FULL                                                                          0xf90c00UL //Access:R    DataWidth:0x9   Input queue fifo full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61261 #define YSDM_REG_INT_CMPL_PEND_FULL                                                                  0xf90c04UL //Access:R    DataWidth:0x1   Internal write completion pending full in internal write block.  Chips: BB_A0 BB_B0 K2
61262 #define YSDM_REG_INT_CPRM_PEND_FULL                                                                  0xf90c08UL //Access:R    DataWidth:0x1   Internal write completion parameter pending full in internal write block.  Chips: BB_A0 BB_B0 K2
61263 #define YSDM_REG_QM_FULL                                                                             0xf90c0cUL //Access:R    DataWidth:0x1   QM IF  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61264 #define YSDM_REG_DELAY_FIFO_FULL                                                                     0xf90c10UL //Access:R    DataWidth:0x1   Delay FIFO  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61265 #define YSDM_REG_TIMERS_PEND_FULL                                                                    0xf90c14UL //Access:R    DataWidth:0x1   Pending FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
61266 #define YSDM_REG_TIMERS_ADDR_FULL                                                                    0xf90c18UL //Access:R    DataWidth:0x1   Address FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
61267 #define YSDM_REG_RSP_PXP_RDATA_FULL                                                                  0xf90c1cUL //Access:R    DataWidth:0x1   PXP rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61268 #define YSDM_REG_RSP_BRB_RDATA_FULL                                                                  0xf90c20UL //Access:R    DataWidth:0x1   BRB read data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61269 #define YSDM_REG_RSP_INT_RAM_RDATA_FULL                                                              0xf90c24UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61270 #define YSDM_REG_RSP_BRB_PEND_FULL                                                                   0xf90c28UL //Access:R    DataWidth:0x1   BRB pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61271 #define YSDM_REG_RSP_INT_RAM_PEND_FULL                                                               0xf90c2cUL //Access:R    DataWidth:0x1   Int_ram pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61272 #define YSDM_REG_RSP_BRB_IF_FULL                                                                     0xf90c30UL //Access:R    DataWidth:0x1   BRB interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61273 #define YSDM_REG_RSP_PXP_IF_FULL                                                                     0xf90c34UL //Access:R    DataWidth:0x1   PXP interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61274 #define YSDM_REG_DST_PXP_IMMED_FULL                                                                  0xf90c38UL //Access:R    DataWidth:0x1   PXP immediate fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61275 #define YSDM_REG_DST_PXP_DST_PEND_FULL                                                               0xf90c3cUL //Access:R    DataWidth:0x1   PXP destination pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61276 #define YSDM_REG_DST_PXP_SRC_PEND_FULL                                                               0xf90c40UL //Access:R    DataWidth:0x1   PXP source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61277 #define YSDM_REG_DST_BRB_SRC_PEND_FULL                                                               0xf90c44UL //Access:R    DataWidth:0x1   BRB source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61278 #define YSDM_REG_DST_BRB_SRC_ADDR_FULL                                                               0xf90c48UL //Access:R    DataWidth:0x1   BRB source address fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61279 #define YSDM_REG_DST_PXP_LINK_FULL                                                                   0xf90c4cUL //Access:R    DataWidth:0x1   PXP link list full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61280 #define YSDM_REG_DST_INT_RAM_WAIT_FULL                                                               0xf90c50UL //Access:R    DataWidth:0x1   Int_ram_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61281 #define YSDM_REG_DST_PAS_BUF_WAIT_FULL                                                               0xf90c54UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61282 #define YSDM_REG_DST_PXP_IF_FULL                                                                     0xf90c58UL //Access:R    DataWidth:0x1   PXP if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61283 #define YSDM_REG_DST_INT_RAM_IF_FULL                                                                 0xf90c5cUL //Access:R    DataWidth:0x1   Int_ram if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61284 #define YSDM_REG_DST_PAS_BUF_IF_FULL                                                                 0xf90c60UL //Access:R    DataWidth:0x1   Pas_buf if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61285 #define YSDM_REG_SH_DELAY_FULL                                                                       0xf90c64UL //Access:R    DataWidth:0x1   Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
61286 #define YSDM_REG_CM_DELAY_FULL                                                                       0xf90c68UL //Access:R    DataWidth:0x1   CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
61287 #define YSDM_REG_CMSG_QUE_FULL                                                                       0xf90c6cUL //Access:R    DataWidth:0x1   Completion message queue fifo full in sdm_cm block.  Chips: BB_A0 BB_B0 K2
61288 #define YSDM_REG_CCFC_LOAD_PEND_FULL                                                                 0xf90c70UL //Access:R    DataWidth:0x1   CCFC load pending fifo full in the CCFC interface  block.  Chips: BB_A0 BB_B0 K2
61289 #define YSDM_REG_TCFC_LOAD_PEND_FULL                                                                 0xf90c74UL //Access:R    DataWidth:0x1   TCFC load pending fifo full in the TCFC interface block.  Chips: BB_A0 BB_B0 K2
61290 #define YSDM_REG_ASYNC_HOST_FULL                                                                     0xf90c78UL //Access:R    DataWidth:0x1   Async fifo full in sdm_async block.  Chips: BB_A0 BB_B0 K2
61291 #define YSDM_REG_PRM_FIFO_FULL                                                                       0xf90c7cUL //Access:R    DataWidth:0x1   PRM FIFO full in PRM interface block.  Chips: BB_A0 BB_B0 K2
61292 #define YSDM_REG_RMT_XCM_FIFO_FULL                                                                   0xf90c80UL //Access:R    DataWidth:0x1   Remote XCM FIFO full (exist only in MSDM => XCM interface).  Chips: K2
61293 #define YSDM_REG_RMT_YCM_FIFO_FULL                                                                   0xf90c84UL //Access:R    DataWidth:0x1   Remote YCM FIFO full (exist only in MSDM => YCM interface).  Chips: K2
61294 #define YSDM_REG_INT_CMPL_PEND_EMPTY                                                                 0xf90d00UL //Access:R    DataWidth:0x1   Internal write completion pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
61295 #define YSDM_REG_INT_CPRM_PEND_EMPTY                                                                 0xf90d04UL //Access:R    DataWidth:0x1   Internal write completion parameter pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
61296 #define YSDM_REG_QUEUE_EMPTY                                                                         0xf90d08UL //Access:R    DataWidth:0x9   Input queue fifo empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61297 #define YSDM_REG_DELAY_FIFO_EMPTY                                                                    0xf90d0cUL //Access:R    DataWidth:0x1   Delay FIFO  empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61298 #define YSDM_REG_TIMERS_PEND_EMPTY                                                                   0xf90d10UL //Access:R    DataWidth:0x1   Pending FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
61299 #define YSDM_REG_TIMERS_ADDR_EMPTY                                                                   0xf90d14UL //Access:R    DataWidth:0x1   Address FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
61300 #define YSDM_REG_RSP_PXP_RDATA_EMPTY                                                                 0xf90d18UL //Access:R    DataWidth:0x1   PXP rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61301 #define YSDM_REG_RSP_BRB_RDATA_EMPTY                                                                 0xf90d1cUL //Access:R    DataWidth:0x1   BRB read data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61302 #define YSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                             0xf90d20UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61303 #define YSDM_REG_RSP_BRB_PEND_EMPTY                                                                  0xf90d24UL //Access:R    DataWidth:0x1   BRB pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61304 #define YSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                              0xf90d28UL //Access:R    DataWidth:0x1   Int_ram pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61305 #define YSDM_REG_DST_PXP_IMMED_EMPTY                                                                 0xf90d2cUL //Access:R    DataWidth:0x1   PXP immediate fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61306 #define YSDM_REG_DST_PXP_DST_PEND_EMPTY                                                              0xf90d30UL //Access:R    DataWidth:0x1   PXP destination pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61307 #define YSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                              0xf90d34UL //Access:R    DataWidth:0x1   PXP source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61308 #define YSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                              0xf90d38UL //Access:R    DataWidth:0x1   BRB source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61309 #define YSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                              0xf90d3cUL //Access:R    DataWidth:0x1   BRB source address fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61310 #define YSDM_REG_DST_PXP_LINK_EMPTY                                                                  0xf90d40UL //Access:R    DataWidth:0x1   PXP link list empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61311 #define YSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                              0xf90d44UL //Access:R    DataWidth:0x1   Int_ram_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61312 #define YSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                              0xf90d48UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61313 #define YSDM_REG_SH_DELAY_EMPTY                                                                      0xf90d4cUL //Access:R    DataWidth:0x1   Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
61314 #define YSDM_REG_CM_DELAY_EMPTY                                                                      0xf90d50UL //Access:R    DataWidth:0x1   CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
61315 #define YSDM_REG_CMSG_QUE_EMPTY                                                                      0xf90d54UL //Access:R    DataWidth:0x1   Completion message queue fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61316 #define YSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                0xf90d58UL //Access:R    DataWidth:0x1   CCFC load pending fifo empty in sdm_ccfc block.  Chips: BB_A0 BB_B0 K2
61317 #define YSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                0xf90d5cUL //Access:R    DataWidth:0x1   TCFC load pending fifo empty in sdm_tcfc block.  Chips: BB_A0 BB_B0 K2
61318 #define YSDM_REG_ASYNC_HOST_EMPTY                                                                    0xf90d60UL //Access:R    DataWidth:0x1   Async fifo empty in sdm_async block.  Chips: BB_A0 BB_B0 K2
61319 #define YSDM_REG_PRM_FIFO_EMPTY                                                                      0xf90d64UL //Access:R    DataWidth:0x1   PRM FIFO empty in sdm_prm_if block.  Chips: BB_A0 BB_B0 K2
61320 #define YSDM_REG_RMT_XCM_FIFO_EMPTY                                                                  0xf90d68UL //Access:R    DataWidth:0x1   Remote XCM FIFO empty (exist only within MSDM => XCM path).  Chips: K2
61321 #define YSDM_REG_RMT_YCM_FIFO_EMPTY                                                                  0xf90d6cUL //Access:R    DataWidth:0x1   Remote YCM FIFO empty (exist only within MSDM => YCM path).  Chips: K2
61322 #define YSDM_REG_DBG_OUT_DATA                                                                        0xf90e00UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
61323 #define YSDM_REG_DBG_OUT_DATA_SIZE                                                                   8
61324 #define YSDM_REG_DBG_OUT_VALID                                                                       0xf90e20UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
61325 #define YSDM_REG_DBG_OUT_FRAME                                                                       0xf90e24UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
61326 #define YSDM_REG_DBG_SELECT                                                                          0xf90e28UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
61327 #define YSDM_REG_DBG_DWORD_ENABLE                                                                    0xf90e2cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
61328 #define YSDM_REG_DBG_SHIFT                                                                           0xf90e30UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
61329 #define YSDM_REG_DBG_FORCE_VALID                                                                     0xf90e34UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
61330 #define YSDM_REG_DBG_FORCE_FRAME                                                                     0xf90e38UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
61331 #define YSDM_REG_ASYNC_FIFO                                                                          0xf92000UL //Access:WB_R DataWidth:0x49  Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61332 #define YSDM_REG_ASYNC_FIFO_SIZE                                                                     116
61333 #define YSDM_REG_IMMED_FIFO                                                                          0xf92400UL //Access:WB_R DataWidth:0x40  Provides read-only access of the immediate data FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61334 #define YSDM_REG_IMMED_FIFO_SIZE                                                                     38
61335 #define YSDM_REG_BRB_FIFO                                                                            0xf92800UL //Access:WB_R DataWidth:0x86  Provides read-only access of the BRB response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61336 #define YSDM_REG_BRB_FIFO_SIZE                                                                       152
61337 #define YSDM_REG_PXP_FIFO                                                                            0xf92c00UL //Access:WB_R DataWidth:0x4a  Provides read-only access of the PXP response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61338 #define YSDM_REG_PXP_FIFO_SIZE                                                                       76
61339 #define YSDM_REG_INT_RAM_FIFO                                                                        0xf93000UL //Access:WB_R DataWidth:0x41  Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61340 #define YSDM_REG_INT_RAM_FIFO_SIZE                                                                   76
61341 #define YSDM_REG_DPM_FIFO                                                                            0xf93400UL //Access:WB_R DataWidth:0x51  Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61342 #define YSDM_REG_DPM_FIFO_SIZE                                                                       172
61343 #define YSDM_REG_EXT_OVERFLOW                                                                        0xf93800UL //Access:WB_R DataWidth:0x4b  Provides read-only access of the external store overflow FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61344 #define YSDM_REG_EXT_OVERFLOW_SIZE                                                                   36
61345 #define YSDM_REG_PRM_FIFO                                                                            0xf93c00UL //Access:WB_R DataWidth:0x41  Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61346 #define YSDM_REG_PRM_FIFO_SIZE                                                                       84
61347 #define YSDM_REG_TIMERS                                                                              0xf94000UL //Access:WB   DataWidth:0x3a  Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61348 #define YSDM_REG_TIMERS_SIZE                                                                         28
61349 #define YSDM_REG_INP_QUEUE                                                                           0xf95000UL //Access:WB   DataWidth:0x40  Input queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
61350 #define YSDM_REG_INP_QUEUE_SIZE                                                                      344
61351 #define YSDM_REG_CMSG_QUE                                                                            0xf98000UL //Access:WB   DataWidth:0x40  CM queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
61352 #define YSDM_REG_CMSG_QUE_SIZE                                                                       192
61353 #define PSDM_REG_ENABLE_IN1                                                                          0xfa0004UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61354     #define PSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                      (0x1<<0) // Enable for input command from STORM.
61355     #define PSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                0
61356     #define PSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                   (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
61357     #define PSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                             1
61358     #define PSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                   (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
61359     #define PSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                             2
61360     #define PSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                   (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
61361     #define PSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                             3
61362     #define PSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                   (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
61363     #define PSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                             4
61364     #define PSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                   (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
61365     #define PSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                             5
61366     #define PSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                       (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
61367     #define PSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                 6
61368     #define PSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                       (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
61369     #define PSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                 7
61370     #define PSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                       (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
61371     #define PSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                 8
61372     #define PSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                    (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
61373     #define PSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                              9
61374     #define PSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                        (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
61375     #define PSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                  10
61376     #define PSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                       (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
61377     #define PSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                 11
61378     #define PSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                        (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
61379     #define PSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                  12
61380     #define PSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                        (0x1<<13) // Enable for input completion message from PRM in prm_if block.
61381     #define PSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                  13
61382     #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                  (0x1<<14) // Enable for input ack to CCFC load credit counter.
61383     #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                            14
61384     #define PSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                  (0x1<<15) // Enable for input ack to TCFC load credit counter.
61385     #define PSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                            15
61386     #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                  (0x1<<16) // Enable for input response from CCFC in CCFC block.
61387     #define PSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                            16
61388     #define PSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                    (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
61389     #define PSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                              17
61390     #define PSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                    (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
61391     #define PSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                              18
61392     #define PSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                 (0x1<<19) // Enable for input full from qm in SDM_INP block.
61393     #define PSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                           19
61394 #define PSDM_REG_ENABLE_IN2                                                                          0xfa0008UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
61395     #define PSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                  (0x1<<0) // Enable for input response from TCFC in TCFC block.
61396     #define PSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                            0
61397     #define PSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                         (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
61398     #define PSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                   1
61399     #define PSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                       (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
61400     #define PSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                 2
61401 #define PSDM_REG_ENABLE_OUT1                                                                         0xfa000cUL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61402     #define PSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                      (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
61403     #define PSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                0
61404     #define PSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                   (0x1<<1) // Enable for output thread ready to the SEMI.
61405     #define PSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                             1
61406     #define PSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                   (0x1<<2) // Enable the output thread release to the SEMI.
61407     #define PSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                             2
61408     #define PSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                    (0x1<<3) // Enable for output load request to CCFC.
61409     #define PSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                              3
61410     #define PSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                    (0x1<<4) // Enable for output load request to TCFC.
61411     #define PSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                              4
61412     #define PSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                      (0x1<<5) // Enable for output increment to CCFC activity counter.
61413     #define PSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                5
61414     #define PSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                      (0x1<<6) // Enable for output decrement to TCFC activity counter.
61415     #define PSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                6
61416     #define PSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                      (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
61417     #define PSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                7
61418     #define PSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                      (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
61419     #define PSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                8
61420     #define PSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                      (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
61421     #define PSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                9
61422     #define PSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                      (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
61423     #define PSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                10
61424     #define PSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                    (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
61425     #define PSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                              11
61426     #define PSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                          (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
61427     #define PSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                    12
61428     #define PSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                     (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
61429     #define PSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                               13
61430     #define PSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                     (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
61431     #define PSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                               14
61432     #define PSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                     (0x1<<15) // Enable for output external full to SEMI block.
61433     #define PSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                               15
61434     #define PSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                 (0x1<<16) // Enable for output done to async PXP host IF.
61435     #define PSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                           16
61436     #define PSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                 (0x1<<17) // Enable the output done (ack) to PRM.
61437     #define PSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                           17
61438     #define PSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                       (0x1<<18) // Enable for output message to CM in SDM_CM block.
61439     #define PSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                 18
61440     #define PSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                 (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
61441     #define PSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                           19
61442     #define PSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                 (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
61443     #define PSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                           20
61444 #define PSDM_REG_ENABLE_OUT2                                                                         0xfa0010UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
61445     #define PSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                    (0x1<<0) // Enable for output command to qm in SDM_INP block.
61446     #define PSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                              0
61447     #define PSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                     (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
61448     #define PSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                               1
61449     #define PSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
61450     #define PSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                          2
61451 #define PSDM_REG_DISABLE_ENGINE                                                                      0xfa0014UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
61452     #define PSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                      (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
61453     #define PSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                0
61454     #define PSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                   (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
61455     #define PSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                             1
61456     #define PSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
61457     #define PSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                          2
61458     #define PSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
61459     #define PSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                          3
61460     #define PSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                   (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
61461     #define PSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                             4
61462     #define PSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                      (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
61463     #define PSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                5
61464     #define PSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                      (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
61465     #define PSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                6
61466     #define PSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                    (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
61467     #define PSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                              7
61468     #define PSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                      (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
61469     #define PSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                8
61470     #define PSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                     (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
61471     #define PSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                               9
61472 #define PSDM_REG_INT_STS                                                                             0xfa0040UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61473     #define PSDM_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
61474     #define PSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
61475     #define PSDM_REG_INT_STS_INP_QUEUE_ERROR                                                         (0x1<<1) // Indicates that one of the input queues had a FIFO error.
61476     #define PSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                   1
61477     #define PSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                        (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
61478     #define PSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                  2
61479     #define PSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                        (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
61480     #define PSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                  3
61481     #define PSDM_REG_INT_STS_PRM_FIFO_ERROR                                                          (0x1<<4) // FIFO in PRM interface sub-module reported an error.
61482     #define PSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                    4
61483     #define PSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                    (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
61484     #define PSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                              5
61485     #define PSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                    (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
61486     #define PSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                              6
61487     #define PSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                  (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
61488     #define PSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                            7
61489     #define PSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                  (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
61490     #define PSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                            8
61491     #define PSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                     (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
61492     #define PSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                               9
61493     #define PSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                  (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
61494     #define PSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                            10
61495     #define PSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                  (0x1<<11) // BRB src pend fifo error in DMA_DST block.
61496     #define PSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                            11
61497     #define PSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                  (0x1<<12) // BRB src addr fifo error in DMA_DST block.
61498     #define PSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                            12
61499     #define PSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                      (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
61500     #define PSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                13
61501     #define PSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                  (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
61502     #define PSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                            14
61503     #define PSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                   (0x1<<15) // Read data firo in DMA_RSP block for BRB.
61504     #define PSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                             15
61505     #define PSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                               (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
61506     #define PSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                         16
61507     #define PSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                   (0x1<<17) // PXP read data fifo error in DMA_RSP block.
61508     #define PSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                             17
61509     #define PSDM_REG_INT_STS_CM_DELAY_ERROR                                                          (0x1<<18) // Delay CM fifo error in CM block.
61510     #define PSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                    18
61511     #define PSDM_REG_INT_STS_SH_DELAY_ERROR                                                          (0x1<<19) // Delay shared fifo error in CM block.
61512     #define PSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                    19
61513     #define PSDM_REG_INT_STS_CMPL_PEND_ERROR                                                         (0x1<<20) // Error in completion pending FIFO in internal write block.
61514     #define PSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                   20
61515     #define PSDM_REG_INT_STS_CPRM_PEND_ERROR                                                         (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
61516     #define PSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                   21
61517     #define PSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                        (0x1<<22) // Address fifo error in timer block.
61518     #define PSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                  22
61519     #define PSDM_REG_INT_STS_TIMER_PEND_ERROR                                                        (0x1<<23) // Pending fifo error in timer block.
61520     #define PSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                  23
61521     #define PSDM_REG_INT_STS_DORQ_DPM_ERROR                                                          (0x1<<24) // Dpm fifo error in dorq I/F block.
61522     #define PSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                    24
61523     #define PSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                      (0x1<<25) // PXP done fifo error in DMA_dst block.
61524     #define PSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                25
61525     #define PSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61526     #define PSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_SHIFT                                              26
61527     #define PSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61528     #define PSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_SHIFT                                              27
61529 #define PSDM_REG_INT_MASK                                                                            0xfa0044UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61530     #define PSDM_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.ADDRESS_ERROR .
61531     #define PSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
61532     #define PSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.INP_QUEUE_ERROR .
61533     #define PSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                  1
61534     #define PSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DELAY_FIFO_ERROR .
61535     #define PSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                 2
61536     #define PSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.ASYNC_HOST_ERROR .
61537     #define PSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                 3
61538     #define PSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.PRM_FIFO_ERROR .
61539     #define PSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                   4
61540     #define PSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
61541     #define PSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                             5
61542     #define PSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
61543     #define PSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                             6
61544     #define PSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
61545     #define PSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                           7
61546     #define PSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
61547     #define PSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                           8
61548     #define PSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
61549     #define PSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                              9
61550     #define PSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
61551     #define PSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                           10
61552     #define PSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
61553     #define PSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                           11
61554     #define PSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
61555     #define PSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                           12
61556     #define PSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
61557     #define PSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                               13
61558     #define PSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
61559     #define PSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                           14
61560     #define PSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                  (0x1<<15) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
61561     #define PSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                            15
61562     #define PSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
61563     #define PSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                        16
61564     #define PSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
61565     #define PSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                            17
61566     #define PSDM_REG_INT_MASK_CM_DELAY_ERROR                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CM_DELAY_ERROR .
61567     #define PSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                   18
61568     #define PSDM_REG_INT_MASK_SH_DELAY_ERROR                                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.SH_DELAY_ERROR .
61569     #define PSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                   19
61570     #define PSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                        (0x1<<20) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CMPL_PEND_ERROR .
61571     #define PSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                  20
61572     #define PSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.CPRM_PEND_ERROR .
61573     #define PSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                  21
61574     #define PSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TIMER_ADDR_ERROR .
61575     #define PSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                 22
61576     #define PSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                       (0x1<<23) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.TIMER_PEND_ERROR .
61577     #define PSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                 23
61578     #define PSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DORQ_DPM_ERROR .
61579     #define PSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                   24
61580     #define PSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                     (0x1<<25) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
61581     #define PSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                               25
61582     #define PSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR                                                   (0x1<<26) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
61583     #define PSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_SHIFT                                             26
61584     #define PSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: PSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
61585     #define PSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_SHIFT                                             27
61586 #define PSDM_REG_INT_STS_WR                                                                          0xfa0048UL //Access:WR   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61587     #define PSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
61588     #define PSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
61589     #define PSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                      (0x1<<1) // Indicates that one of the input queues had a FIFO error.
61590     #define PSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                1
61591     #define PSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                     (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
61592     #define PSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                               2
61593     #define PSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                     (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
61594     #define PSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                               3
61595     #define PSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                       (0x1<<4) // FIFO in PRM interface sub-module reported an error.
61596     #define PSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                 4
61597     #define PSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                 (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
61598     #define PSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                           5
61599     #define PSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                 (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
61600     #define PSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                           6
61601     #define PSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                               (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
61602     #define PSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                         7
61603     #define PSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                               (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
61604     #define PSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                         8
61605     #define PSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                  (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
61606     #define PSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                            9
61607     #define PSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                               (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
61608     #define PSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                         10
61609     #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                               (0x1<<11) // BRB src pend fifo error in DMA_DST block.
61610     #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                         11
61611     #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                               (0x1<<12) // BRB src addr fifo error in DMA_DST block.
61612     #define PSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                         12
61613     #define PSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                   (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
61614     #define PSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                             13
61615     #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                               (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
61616     #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                         14
61617     #define PSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                (0x1<<15) // Read data firo in DMA_RSP block for BRB.
61618     #define PSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                          15
61619     #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                            (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
61620     #define PSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                      16
61621     #define PSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                (0x1<<17) // PXP read data fifo error in DMA_RSP block.
61622     #define PSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                          17
61623     #define PSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                       (0x1<<18) // Delay CM fifo error in CM block.
61624     #define PSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                 18
61625     #define PSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                       (0x1<<19) // Delay shared fifo error in CM block.
61626     #define PSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                 19
61627     #define PSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                      (0x1<<20) // Error in completion pending FIFO in internal write block.
61628     #define PSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                20
61629     #define PSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                      (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
61630     #define PSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                21
61631     #define PSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                     (0x1<<22) // Address fifo error in timer block.
61632     #define PSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                               22
61633     #define PSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                     (0x1<<23) // Pending fifo error in timer block.
61634     #define PSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                               23
61635     #define PSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                       (0x1<<24) // Dpm fifo error in dorq I/F block.
61636     #define PSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                 24
61637     #define PSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                   (0x1<<25) // PXP done fifo error in DMA_dst block.
61638     #define PSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                             25
61639     #define PSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR                                                 (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61640     #define PSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_SHIFT                                           26
61641     #define PSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR                                                 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61642     #define PSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_SHIFT                                           27
61643 #define PSDM_REG_INT_STS_CLR                                                                         0xfa004cUL //Access:RC   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61644     #define PSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
61645     #define PSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
61646     #define PSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                     (0x1<<1) // Indicates that one of the input queues had a FIFO error.
61647     #define PSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                               1
61648     #define PSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                    (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
61649     #define PSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                              2
61650     #define PSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                    (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
61651     #define PSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                              3
61652     #define PSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                      (0x1<<4) // FIFO in PRM interface sub-module reported an error.
61653     #define PSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                4
61654     #define PSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
61655     #define PSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                          5
61656     #define PSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
61657     #define PSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                          6
61658     #define PSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                              (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
61659     #define PSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                        7
61660     #define PSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                              (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
61661     #define PSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                        8
61662     #define PSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                 (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
61663     #define PSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                           9
61664     #define PSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                              (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
61665     #define PSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                        10
61666     #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                              (0x1<<11) // BRB src pend fifo error in DMA_DST block.
61667     #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                        11
61668     #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                              (0x1<<12) // BRB src addr fifo error in DMA_DST block.
61669     #define PSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                        12
61670     #define PSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                  (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
61671     #define PSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                            13
61672     #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                              (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
61673     #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                        14
61674     #define PSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                               (0x1<<15) // Read data firo in DMA_RSP block for BRB.
61675     #define PSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                         15
61676     #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                           (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
61677     #define PSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                     16
61678     #define PSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                               (0x1<<17) // PXP read data fifo error in DMA_RSP block.
61679     #define PSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                         17
61680     #define PSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                      (0x1<<18) // Delay CM fifo error in CM block.
61681     #define PSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                18
61682     #define PSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                      (0x1<<19) // Delay shared fifo error in CM block.
61683     #define PSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                19
61684     #define PSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                     (0x1<<20) // Error in completion pending FIFO in internal write block.
61685     #define PSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                               20
61686     #define PSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                     (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
61687     #define PSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                               21
61688     #define PSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                    (0x1<<22) // Address fifo error in timer block.
61689     #define PSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                              22
61690     #define PSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                    (0x1<<23) // Pending fifo error in timer block.
61691     #define PSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                              23
61692     #define PSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                      (0x1<<24) // Dpm fifo error in dorq I/F block.
61693     #define PSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                24
61694     #define PSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                  (0x1<<25) // PXP done fifo error in DMA_dst block.
61695     #define PSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                            25
61696     #define PSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR                                                (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61697     #define PSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_SHIFT                                          26
61698     #define PSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR                                                (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
61699     #define PSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_SHIFT                                          27
61700 #define PSDM_REG_PRTY_MASK_H_0                                                                       0xfa0204UL //Access:RW   DataWidth:0x9   Multi Field Register.  Chips: BB_A0 BB_B0 K2
61701     #define PSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
61702     #define PSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           0
61703     #define PSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
61704     #define PSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           1
61705     #define PSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
61706     #define PSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           2
61707     #define PSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
61708     #define PSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           3
61709     #define PSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
61710     #define PSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           4
61711     #define PSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
61712     #define PSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           5
61713     #define PSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
61714     #define PSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           6
61715     #define PSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
61716     #define PSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           7
61717     #define PSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: PSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
61718     #define PSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           8
61719 #define PSDM_REG_MEM_ECC_EVENTS                                                                      0xfa0210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
61720 #define PSDM_REG_MEM007_I_MEM_DFT_K2                                                                 0xfa0218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_pxp_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61721 #define PSDM_REG_MEM006_I_MEM_DFT_K2                                                                 0xfa021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_int_ram_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61722 #define PSDM_REG_MEM005_I_MEM_DFT_K2                                                                 0xfa0220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psdm.i_sdm_core.i_sdm_dma.i_sdm_dma_dst.i_sdm_dma_immed_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61723 #define PSDM_REG_MEM002_I_MEM_DFT_K2                                                                 0xfa0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psdm.i_sdm_core.i_sdm_async.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61724 #define PSDM_REG_MEM009_I_MEM_DFT_K2                                                                 0xfa0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psdm.i_sdm_core.i_sdm_timers_sram_wrap.PSDM_TIMERS_RAM_GEN_IF.i_sdm_timers_ram_psdm.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
61725 #define PSDM_REG_MEM001_I_MEM_DFT_K2                                                                 0xfa022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psdm.i_sdm_core.i_inp_que_ram_wrap.PSDM_INP_QUE_RAM_GEN_IF.i_sdm_inp_que_ram_psdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61726 #define PSDM_REG_MEM003_I_MEM_DFT_K2                                                                 0xfa0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psdm.i_sdm_core.i_sdm_cmp_msg_que_ram_wrap.PSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_psdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
61727 #define PSDM_REG_TIMER_TICK                                                                          0xfa0400UL //Access:RW   DataWidth:0x20  Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.  Chips: BB_A0 BB_B0 K2
61728 #define PSDM_REG_TIMERS_TICK_ENABLE                                                                  0xfa0404UL //Access:RW   DataWidth:0x1   Enable for tick counter.  Chips: BB_A0 BB_B0 K2
61729 #define PSDM_REG_OPERATION_GEN                                                                       0xfa0408UL //Access:W    DataWidth:0x14  This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.  Chips: BB_A0 BB_B0 K2
61730 #define PSDM_REG_GRC_PRIVILEGE_LEVEL                                                                 0xfa040cUL //Access:RW   DataWidth:0x2   This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.  Chips: BB_A0 BB_B0 K2
61731 #define PSDM_REG_CM_MSG_CNT_ADDRESS                                                                  0xfa0410UL //Access:RW   DataWidth:0xf   The internal RAM address for storing the shadow of the CM completion message counter.  Chips: BB_A0 BB_B0 K2
61732 #define PSDM_REG_DORQ_DPM_START_ADDR                                                                 0xfa0414UL //Access:RW   DataWidth:0xf   The start address in the internal RAM for DORQ DPM messages.  Chips: BB_A0 BB_B0 K2
61733 #define PSDM_REG_RR_COMPLETE_REQ                                                                     0xfa0418UL //Access:R    DataWidth:0xa   Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.  Chips: BB_A0 BB_B0 K2
61734 #define PSDM_REG_RR_PTR_REQ                                                                          0xfa041cUL //Access:R    DataWidth:0x9   Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.  Chips: BB_A0 BB_B0 K2
61735 #define PSDM_REG_INT_RAM_RR_REQ                                                                      0xfa0420UL //Access:R    DataWidth:0x4   Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.  Chips: BB_A0 BB_B0 K2
61736 #define PSDM_REG_INP_QUEUE_ERR_VECT                                                                  0xfa0424UL //Access:R    DataWidth:0x9   This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.  Chips: BB_A0 BB_B0 K2
61737 #define PSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                              0xfa0428UL //Access:RW   DataWidth:0x5   This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.  Chips: BB_A0 BB_B0 K2
61738 #define PSDM_REG_ECO_RESERVED                                                                        0xfa042cUL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
61739 #define PSDM_REG_INIT_CREDIT_PXP                                                                     0xfa0500UL //Access:RW   DataWidth:0x3   The initial number of messages that can be sent to the pxp interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
61740 #define PSDM_REG_INIT_CREDIT_PCI                                                                     0xfa0504UL //Access:RW   DataWidth:0x2   The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
61741 #define PSDM_REG_INIT_CREDIT_TCFC_AC                                                                 0xfa0508UL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
61742 #define PSDM_REG_INIT_CREDIT_CCFC_AC                                                                 0xfa050cUL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
61743 #define PSDM_REG_INIT_CREDIT_CM                                                                      0xfa0510UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
61744 #define PSDM_REG_NUM_OF_DMA_CMD                                                                      0xfa0600UL //Access:RC   DataWidth:0x20  The number of SDM DMA commands executed.  Chips: BB_A0 BB_B0 K2
61745 #define PSDM_REG_NUM_OF_TIMERS_CMD                                                                   0xfa0604UL //Access:RC   DataWidth:0x20  The number of SDM timers commands executed.  Chips: BB_A0 BB_B0 K2
61746 #define PSDM_REG_NUM_OF_CCFC_LD_CMD                                                                  0xfa0608UL //Access:RC   DataWidth:0x20  The number of SDM CCFC load commands executed.  Chips: BB_A0 BB_B0 K2
61747 #define PSDM_REG_NUM_OF_CCFC_AC_CMD                                                                  0xfa060cUL //Access:RC   DataWidth:0x20  The number of SDM CCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
61748 #define PSDM_REG_NUM_OF_TCFC_LD_CMD                                                                  0xfa0610UL //Access:RC   DataWidth:0x20  The number of SDM TCFC load commands executed.  Chips: BB_A0 BB_B0 K2
61749 #define PSDM_REG_NUM_OF_TCFC_AC_CMD                                                                  0xfa0614UL //Access:RC   DataWidth:0x20  The number of SDM TCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
61750 #define PSDM_REG_NUM_OF_INT_CMD                                                                      0xfa0618UL //Access:RC   DataWidth:0x20  The number of SDM internal write commands executed.  Chips: BB_A0 BB_B0 K2
61751 #define PSDM_REG_NUM_OF_NOP_CMD                                                                      0xfa061cUL //Access:RC   DataWidth:0x20  The number of SDM NOP commands executed.  Chips: BB_A0 BB_B0 K2
61752 #define PSDM_REG_NUM_OF_GRC_CMD                                                                      0xfa0620UL //Access:RC   DataWidth:0x20  The number of GRC master commands executed.  Chips: BB_A0 BB_B0 K2
61753 #define PSDM_REG_NUM_OF_PRM_REQ                                                                      0xfa0624UL //Access:RC   DataWidth:0x20  The number of packet end messages received on the PRM completion interface.  Chips: BB_A0 BB_B0 K2
61754 #define PSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                0xfa0628UL //Access:RC   DataWidth:0x20  The number of requests received from the pxp async if.  Chips: BB_A0 BB_B0 K2
61755 #define PSDM_REG_NUM_OF_DPM_REQ                                                                      0xfa062cUL //Access:RC   DataWidth:0x20  The number of DORQ DPM messages received.  Chips: BB_A0 BB_B0 K2
61756 #define PSDM_REG_BRB_ALMOST_FULL                                                                     0xfa0700UL //Access:RW   DataWidth:0x5   Almost full signal for read data from BRB in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
61757 #define PSDM_REG_PXP_ALMOST_FULL                                                                     0xfa0704UL //Access:RW   DataWidth:0x4   Almost full signal for read data from pxp in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
61758 #define PSDM_REG_DORQ_ALMOST_FULL                                                                    0xfa0708UL //Access:RW   DataWidth:0x6   Almost full signal for read data from DORQ in SDM_DORQ block.  Chips: BB_A0 BB_B0 K2
61759 #define PSDM_REG_AGG_INT_CTRL                                                                        0xfa0800UL //Access:RW   DataWidth:0xa   This array of registers provides controls for each of 32 aggregated interrupts; The fiels are defined as follows: agg_int_ctrl[7:0] = EventID which selects the event ID of the associated handler; agg_int_ctrl[8] = T-flag which determines if a thread is allocated for this handler in the Storm; agg_int_ctrl[9] = Mode bit; where 0=normal and 1=auto-mask-mode.  Chips: BB_A0 BB_B0 K2
61760 #define PSDM_REG_AGG_INT_CTRL_SIZE                                                                   32
61761 #define PSDM_REG_AGG_INT_STATE                                                                       0xfa0a00UL //Access:R    DataWidth:0x2   This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.  Chips: BB_A0 BB_B0 K2
61762 #define PSDM_REG_AGG_INT_STATE_SIZE                                                                  32
61763 #define PSDM_REG_QUEUE_FULL                                                                          0xfa0c00UL //Access:R    DataWidth:0x9   Input queue fifo full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61764 #define PSDM_REG_INT_CMPL_PEND_FULL                                                                  0xfa0c04UL //Access:R    DataWidth:0x1   Internal write completion pending full in internal write block.  Chips: BB_A0 BB_B0 K2
61765 #define PSDM_REG_INT_CPRM_PEND_FULL                                                                  0xfa0c08UL //Access:R    DataWidth:0x1   Internal write completion parameter pending full in internal write block.  Chips: BB_A0 BB_B0 K2
61766 #define PSDM_REG_QM_FULL                                                                             0xfa0c0cUL //Access:R    DataWidth:0x1   QM IF  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61767 #define PSDM_REG_DELAY_FIFO_FULL                                                                     0xfa0c10UL //Access:R    DataWidth:0x1   Delay FIFO  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61768 #define PSDM_REG_TIMERS_PEND_FULL                                                                    0xfa0c14UL //Access:R    DataWidth:0x1   Pending FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
61769 #define PSDM_REG_TIMERS_ADDR_FULL                                                                    0xfa0c18UL //Access:R    DataWidth:0x1   Address FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
61770 #define PSDM_REG_RSP_PXP_RDATA_FULL                                                                  0xfa0c1cUL //Access:R    DataWidth:0x1   PXP rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61771 #define PSDM_REG_RSP_BRB_RDATA_FULL                                                                  0xfa0c20UL //Access:R    DataWidth:0x1   BRB read data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61772 #define PSDM_REG_RSP_INT_RAM_RDATA_FULL                                                              0xfa0c24UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61773 #define PSDM_REG_RSP_BRB_PEND_FULL                                                                   0xfa0c28UL //Access:R    DataWidth:0x1   BRB pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61774 #define PSDM_REG_RSP_INT_RAM_PEND_FULL                                                               0xfa0c2cUL //Access:R    DataWidth:0x1   Int_ram pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61775 #define PSDM_REG_RSP_BRB_IF_FULL                                                                     0xfa0c30UL //Access:R    DataWidth:0x1   BRB interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61776 #define PSDM_REG_RSP_PXP_IF_FULL                                                                     0xfa0c34UL //Access:R    DataWidth:0x1   PXP interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61777 #define PSDM_REG_DST_PXP_IMMED_FULL                                                                  0xfa0c38UL //Access:R    DataWidth:0x1   PXP immediate fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61778 #define PSDM_REG_DST_PXP_DST_PEND_FULL                                                               0xfa0c3cUL //Access:R    DataWidth:0x1   PXP destination pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61779 #define PSDM_REG_DST_PXP_SRC_PEND_FULL                                                               0xfa0c40UL //Access:R    DataWidth:0x1   PXP source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61780 #define PSDM_REG_DST_BRB_SRC_PEND_FULL                                                               0xfa0c44UL //Access:R    DataWidth:0x1   BRB source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61781 #define PSDM_REG_DST_BRB_SRC_ADDR_FULL                                                               0xfa0c48UL //Access:R    DataWidth:0x1   BRB source address fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61782 #define PSDM_REG_DST_PXP_LINK_FULL                                                                   0xfa0c4cUL //Access:R    DataWidth:0x1   PXP link list full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61783 #define PSDM_REG_DST_INT_RAM_WAIT_FULL                                                               0xfa0c50UL //Access:R    DataWidth:0x1   Int_ram_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61784 #define PSDM_REG_DST_PAS_BUF_WAIT_FULL                                                               0xfa0c54UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61785 #define PSDM_REG_DST_PXP_IF_FULL                                                                     0xfa0c58UL //Access:R    DataWidth:0x1   PXP if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61786 #define PSDM_REG_DST_INT_RAM_IF_FULL                                                                 0xfa0c5cUL //Access:R    DataWidth:0x1   Int_ram if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61787 #define PSDM_REG_DST_PAS_BUF_IF_FULL                                                                 0xfa0c60UL //Access:R    DataWidth:0x1   Pas_buf if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61788 #define PSDM_REG_SH_DELAY_FULL                                                                       0xfa0c64UL //Access:R    DataWidth:0x1   Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
61789 #define PSDM_REG_CM_DELAY_FULL                                                                       0xfa0c68UL //Access:R    DataWidth:0x1   CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
61790 #define PSDM_REG_CMSG_QUE_FULL                                                                       0xfa0c6cUL //Access:R    DataWidth:0x1   Completion message queue fifo full in sdm_cm block.  Chips: BB_A0 BB_B0 K2
61791 #define PSDM_REG_CCFC_LOAD_PEND_FULL                                                                 0xfa0c70UL //Access:R    DataWidth:0x1   CCFC load pending fifo full in the CCFC interface  block.  Chips: BB_A0 BB_B0 K2
61792 #define PSDM_REG_TCFC_LOAD_PEND_FULL                                                                 0xfa0c74UL //Access:R    DataWidth:0x1   TCFC load pending fifo full in the TCFC interface block.  Chips: BB_A0 BB_B0 K2
61793 #define PSDM_REG_ASYNC_HOST_FULL                                                                     0xfa0c78UL //Access:R    DataWidth:0x1   Async fifo full in sdm_async block.  Chips: BB_A0 BB_B0 K2
61794 #define PSDM_REG_PRM_FIFO_FULL                                                                       0xfa0c7cUL //Access:R    DataWidth:0x1   PRM FIFO full in PRM interface block.  Chips: BB_A0 BB_B0 K2
61795 #define PSDM_REG_RMT_XCM_FIFO_FULL                                                                   0xfa0c80UL //Access:R    DataWidth:0x1   Remote XCM FIFO full (exist only in MSDM => XCM interface).  Chips: K2
61796 #define PSDM_REG_RMT_YCM_FIFO_FULL                                                                   0xfa0c84UL //Access:R    DataWidth:0x1   Remote YCM FIFO full (exist only in MSDM => YCM interface).  Chips: K2
61797 #define PSDM_REG_INT_CMPL_PEND_EMPTY                                                                 0xfa0d00UL //Access:R    DataWidth:0x1   Internal write completion pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
61798 #define PSDM_REG_INT_CPRM_PEND_EMPTY                                                                 0xfa0d04UL //Access:R    DataWidth:0x1   Internal write completion parameter pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
61799 #define PSDM_REG_QUEUE_EMPTY                                                                         0xfa0d08UL //Access:R    DataWidth:0x9   Input queue fifo empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61800 #define PSDM_REG_DELAY_FIFO_EMPTY                                                                    0xfa0d0cUL //Access:R    DataWidth:0x1   Delay FIFO  empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
61801 #define PSDM_REG_TIMERS_PEND_EMPTY                                                                   0xfa0d10UL //Access:R    DataWidth:0x1   Pending FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
61802 #define PSDM_REG_TIMERS_ADDR_EMPTY                                                                   0xfa0d14UL //Access:R    DataWidth:0x1   Address FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
61803 #define PSDM_REG_RSP_PXP_RDATA_EMPTY                                                                 0xfa0d18UL //Access:R    DataWidth:0x1   PXP rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61804 #define PSDM_REG_RSP_BRB_RDATA_EMPTY                                                                 0xfa0d1cUL //Access:R    DataWidth:0x1   BRB read data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61805 #define PSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                             0xfa0d20UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61806 #define PSDM_REG_RSP_BRB_PEND_EMPTY                                                                  0xfa0d24UL //Access:R    DataWidth:0x1   BRB pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61807 #define PSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                              0xfa0d28UL //Access:R    DataWidth:0x1   Int_ram pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
61808 #define PSDM_REG_DST_PXP_IMMED_EMPTY                                                                 0xfa0d2cUL //Access:R    DataWidth:0x1   PXP immediate fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61809 #define PSDM_REG_DST_PXP_DST_PEND_EMPTY                                                              0xfa0d30UL //Access:R    DataWidth:0x1   PXP destination pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61810 #define PSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                              0xfa0d34UL //Access:R    DataWidth:0x1   PXP source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61811 #define PSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                              0xfa0d38UL //Access:R    DataWidth:0x1   BRB source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61812 #define PSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                              0xfa0d3cUL //Access:R    DataWidth:0x1   BRB source address fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61813 #define PSDM_REG_DST_PXP_LINK_EMPTY                                                                  0xfa0d40UL //Access:R    DataWidth:0x1   PXP link list empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61814 #define PSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                              0xfa0d44UL //Access:R    DataWidth:0x1   Int_ram_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61815 #define PSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                              0xfa0d48UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61816 #define PSDM_REG_SH_DELAY_EMPTY                                                                      0xfa0d4cUL //Access:R    DataWidth:0x1   Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
61817 #define PSDM_REG_CM_DELAY_EMPTY                                                                      0xfa0d50UL //Access:R    DataWidth:0x1   CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
61818 #define PSDM_REG_CMSG_QUE_EMPTY                                                                      0xfa0d54UL //Access:R    DataWidth:0x1   Completion message queue fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
61819 #define PSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                0xfa0d58UL //Access:R    DataWidth:0x1   CCFC load pending fifo empty in sdm_ccfc block.  Chips: BB_A0 BB_B0 K2
61820 #define PSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                0xfa0d5cUL //Access:R    DataWidth:0x1   TCFC load pending fifo empty in sdm_tcfc block.  Chips: BB_A0 BB_B0 K2
61821 #define PSDM_REG_ASYNC_HOST_EMPTY                                                                    0xfa0d60UL //Access:R    DataWidth:0x1   Async fifo empty in sdm_async block.  Chips: BB_A0 BB_B0 K2
61822 #define PSDM_REG_PRM_FIFO_EMPTY                                                                      0xfa0d64UL //Access:R    DataWidth:0x1   PRM FIFO empty in sdm_prm_if block.  Chips: BB_A0 BB_B0 K2
61823 #define PSDM_REG_RMT_XCM_FIFO_EMPTY                                                                  0xfa0d68UL //Access:R    DataWidth:0x1   Remote XCM FIFO empty (exist only within MSDM => XCM path).  Chips: K2
61824 #define PSDM_REG_RMT_YCM_FIFO_EMPTY                                                                  0xfa0d6cUL //Access:R    DataWidth:0x1   Remote YCM FIFO empty (exist only within MSDM => YCM path).  Chips: K2
61825 #define PSDM_REG_DBG_OUT_DATA                                                                        0xfa0e00UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
61826 #define PSDM_REG_DBG_OUT_DATA_SIZE                                                                   8
61827 #define PSDM_REG_DBG_OUT_VALID                                                                       0xfa0e20UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
61828 #define PSDM_REG_DBG_OUT_FRAME                                                                       0xfa0e24UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
61829 #define PSDM_REG_DBG_SELECT                                                                          0xfa0e28UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
61830 #define PSDM_REG_DBG_DWORD_ENABLE                                                                    0xfa0e2cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
61831 #define PSDM_REG_DBG_SHIFT                                                                           0xfa0e30UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
61832 #define PSDM_REG_DBG_FORCE_VALID                                                                     0xfa0e34UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
61833 #define PSDM_REG_DBG_FORCE_FRAME                                                                     0xfa0e38UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
61834 #define PSDM_REG_ASYNC_FIFO                                                                          0xfa2000UL //Access:WB_R DataWidth:0x49  Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61835 #define PSDM_REG_ASYNC_FIFO_SIZE                                                                     116
61836 #define PSDM_REG_IMMED_FIFO                                                                          0xfa2400UL //Access:WB_R DataWidth:0x40  Provides read-only access of the immediate data FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61837 #define PSDM_REG_IMMED_FIFO_SIZE                                                                     38
61838 #define PSDM_REG_BRB_FIFO                                                                            0xfa2800UL //Access:WB_R DataWidth:0x86  Provides read-only access of the BRB response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61839 #define PSDM_REG_BRB_FIFO_SIZE                                                                       152
61840 #define PSDM_REG_PXP_FIFO                                                                            0xfa2c00UL //Access:WB_R DataWidth:0x4a  Provides read-only access of the PXP response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61841 #define PSDM_REG_PXP_FIFO_SIZE                                                                       76
61842 #define PSDM_REG_INT_RAM_FIFO                                                                        0xfa3000UL //Access:WB_R DataWidth:0x41  Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61843 #define PSDM_REG_INT_RAM_FIFO_SIZE                                                                   76
61844 #define PSDM_REG_DPM_FIFO                                                                            0xfa3400UL //Access:WB_R DataWidth:0x51  Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61845 #define PSDM_REG_DPM_FIFO_SIZE                                                                       172
61846 #define PSDM_REG_EXT_OVERFLOW                                                                        0xfa3800UL //Access:WB_R DataWidth:0x4b  Provides read-only access of the external store overflow FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61847 #define PSDM_REG_EXT_OVERFLOW_SIZE                                                                   36
61848 #define PSDM_REG_PRM_FIFO                                                                            0xfa3c00UL //Access:WB_R DataWidth:0x41  Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61849 #define PSDM_REG_PRM_FIFO_SIZE                                                                       84
61850 #define PSDM_REG_TIMERS                                                                              0xfa4000UL //Access:WB   DataWidth:0x39  Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
61851 #define PSDM_REG_TIMERS_SIZE                                                                         8
61852 #define PSDM_REG_INP_QUEUE                                                                           0xfa5000UL //Access:WB   DataWidth:0x40  Input queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
61853 #define PSDM_REG_INP_QUEUE_SIZE                                                                      272
61854 #define PSDM_REG_CMSG_QUE                                                                            0xfa8000UL //Access:WB   DataWidth:0x40  CM queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
61855 #define PSDM_REG_CMSG_QUE_SIZE                                                                       128
61856 #define TSDM_REG_ENABLE_IN1                                                                          0xfb0004UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61857     #define TSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                      (0x1<<0) // Enable for input command from STORM.
61858     #define TSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                0
61859     #define TSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                   (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
61860     #define TSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                             1
61861     #define TSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                   (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
61862     #define TSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                             2
61863     #define TSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                   (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
61864     #define TSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                             3
61865     #define TSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                   (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
61866     #define TSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                             4
61867     #define TSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                   (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
61868     #define TSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                             5
61869     #define TSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                       (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
61870     #define TSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                 6
61871     #define TSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                       (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
61872     #define TSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                 7
61873     #define TSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                       (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
61874     #define TSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                 8
61875     #define TSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                    (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
61876     #define TSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                              9
61877     #define TSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                        (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
61878     #define TSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                  10
61879     #define TSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                       (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
61880     #define TSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                 11
61881     #define TSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                        (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
61882     #define TSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                  12
61883     #define TSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                        (0x1<<13) // Enable for input completion message from PRM in prm_if block.
61884     #define TSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                  13
61885     #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                  (0x1<<14) // Enable for input ack to CCFC load credit counter.
61886     #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                            14
61887     #define TSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                  (0x1<<15) // Enable for input ack to TCFC load credit counter.
61888     #define TSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                            15
61889     #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                  (0x1<<16) // Enable for input response from CCFC in CCFC block.
61890     #define TSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                            16
61891     #define TSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                    (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
61892     #define TSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                              17
61893     #define TSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                    (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
61894     #define TSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                              18
61895     #define TSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                 (0x1<<19) // Enable for input full from qm in SDM_INP block.
61896     #define TSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                           19
61897 #define TSDM_REG_ENABLE_IN2                                                                          0xfb0008UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
61898     #define TSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                  (0x1<<0) // Enable for input response from TCFC in TCFC block.
61899     #define TSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                            0
61900     #define TSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                         (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
61901     #define TSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                   1
61902     #define TSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                       (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
61903     #define TSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                 2
61904 #define TSDM_REG_ENABLE_OUT1                                                                         0xfb000cUL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61905     #define TSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                      (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
61906     #define TSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                0
61907     #define TSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                   (0x1<<1) // Enable for output thread ready to the SEMI.
61908     #define TSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                             1
61909     #define TSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                   (0x1<<2) // Enable the output thread release to the SEMI.
61910     #define TSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                             2
61911     #define TSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                    (0x1<<3) // Enable for output load request to CCFC.
61912     #define TSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                              3
61913     #define TSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                    (0x1<<4) // Enable for output load request to TCFC.
61914     #define TSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                              4
61915     #define TSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                      (0x1<<5) // Enable for output increment to CCFC activity counter.
61916     #define TSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                5
61917     #define TSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                      (0x1<<6) // Enable for output decrement to TCFC activity counter.
61918     #define TSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                6
61919     #define TSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                      (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
61920     #define TSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                7
61921     #define TSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                      (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
61922     #define TSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                8
61923     #define TSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                      (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
61924     #define TSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                9
61925     #define TSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                      (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
61926     #define TSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                10
61927     #define TSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                    (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
61928     #define TSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                              11
61929     #define TSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                          (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
61930     #define TSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                    12
61931     #define TSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                     (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
61932     #define TSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                               13
61933     #define TSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                     (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
61934     #define TSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                               14
61935     #define TSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                     (0x1<<15) // Enable for output external full to SEMI block.
61936     #define TSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                               15
61937     #define TSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                 (0x1<<16) // Enable for output done to async PXP host IF.
61938     #define TSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                           16
61939     #define TSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                 (0x1<<17) // Enable the output done (ack) to PRM.
61940     #define TSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                           17
61941     #define TSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                       (0x1<<18) // Enable for output message to CM in SDM_CM block.
61942     #define TSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                 18
61943     #define TSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                 (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
61944     #define TSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                           19
61945     #define TSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                 (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
61946     #define TSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                           20
61947 #define TSDM_REG_ENABLE_OUT2                                                                         0xfb0010UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
61948     #define TSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                    (0x1<<0) // Enable for output command to qm in SDM_INP block.
61949     #define TSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                              0
61950     #define TSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                     (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
61951     #define TSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                               1
61952     #define TSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
61953     #define TSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                          2
61954 #define TSDM_REG_DISABLE_ENGINE                                                                      0xfb0014UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
61955     #define TSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                      (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
61956     #define TSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                0
61957     #define TSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                   (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
61958     #define TSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                             1
61959     #define TSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
61960     #define TSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                          2
61961     #define TSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
61962     #define TSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                          3
61963     #define TSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                   (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
61964     #define TSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                             4
61965     #define TSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                      (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
61966     #define TSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                5
61967     #define TSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                      (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
61968     #define TSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                6
61969     #define TSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                    (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
61970     #define TSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                              7
61971     #define TSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                      (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
61972     #define TSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                8
61973     #define TSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                     (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
61974     #define TSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                               9
61975 #define TSDM_REG_INT_STS                                                                             0xfb0040UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
61976     #define TSDM_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
61977     #define TSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
61978     #define TSDM_REG_INT_STS_INP_QUEUE_ERROR                                                         (0x1<<1) // Indicates that one of the input queues had a FIFO error.
61979     #define TSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                   1
61980     #define TSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                        (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
61981     #define TSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                  2
61982     #define TSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                        (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
61983     #define TSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                  3
61984     #define TSDM_REG_INT_STS_PRM_FIFO_ERROR                                                          (0x1<<4) // FIFO in PRM interface sub-module reported an error.
61985     #define TSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                    4
61986     #define TSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                    (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
61987     #define TSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                              5
61988     #define TSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                    (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
61989     #define TSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                              6
61990     #define TSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                  (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
61991     #define TSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                            7
61992     #define TSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                  (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
61993     #define TSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                            8
61994     #define TSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                     (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
61995     #define TSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                               9
61996     #define TSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                  (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
61997     #define TSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                            10
61998     #define TSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                  (0x1<<11) // BRB src pend fifo error in DMA_DST block.
61999     #define TSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                            11
62000     #define TSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                  (0x1<<12) // BRB src addr fifo error in DMA_DST block.
62001     #define TSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                            12
62002     #define TSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                      (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
62003     #define TSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                13
62004     #define TSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                  (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
62005     #define TSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                            14
62006     #define TSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                   (0x1<<15) // Read data firo in DMA_RSP block for BRB.
62007     #define TSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                             15
62008     #define TSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                               (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
62009     #define TSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                         16
62010     #define TSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                   (0x1<<17) // PXP read data fifo error in DMA_RSP block.
62011     #define TSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                             17
62012     #define TSDM_REG_INT_STS_CM_DELAY_ERROR                                                          (0x1<<18) // Delay CM fifo error in CM block.
62013     #define TSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                    18
62014     #define TSDM_REG_INT_STS_SH_DELAY_ERROR                                                          (0x1<<19) // Delay shared fifo error in CM block.
62015     #define TSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                    19
62016     #define TSDM_REG_INT_STS_CMPL_PEND_ERROR                                                         (0x1<<20) // Error in completion pending FIFO in internal write block.
62017     #define TSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                   20
62018     #define TSDM_REG_INT_STS_CPRM_PEND_ERROR                                                         (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
62019     #define TSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                   21
62020     #define TSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                        (0x1<<22) // Address fifo error in timer block.
62021     #define TSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                  22
62022     #define TSDM_REG_INT_STS_TIMER_PEND_ERROR                                                        (0x1<<23) // Pending fifo error in timer block.
62023     #define TSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                  23
62024     #define TSDM_REG_INT_STS_DORQ_DPM_ERROR                                                          (0x1<<24) // Dpm fifo error in dorq I/F block.
62025     #define TSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                    24
62026     #define TSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                      (0x1<<25) // PXP done fifo error in DMA_dst block.
62027     #define TSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                25
62028     #define TSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62029     #define TSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_SHIFT                                              26
62030     #define TSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62031     #define TSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_SHIFT                                              27
62032 #define TSDM_REG_INT_MASK                                                                            0xfb0044UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62033     #define TSDM_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.ADDRESS_ERROR .
62034     #define TSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
62035     #define TSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.INP_QUEUE_ERROR .
62036     #define TSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                  1
62037     #define TSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DELAY_FIFO_ERROR .
62038     #define TSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                 2
62039     #define TSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.ASYNC_HOST_ERROR .
62040     #define TSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                 3
62041     #define TSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.PRM_FIFO_ERROR .
62042     #define TSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                   4
62043     #define TSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
62044     #define TSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                             5
62045     #define TSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
62046     #define TSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                             6
62047     #define TSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
62048     #define TSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                           7
62049     #define TSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
62050     #define TSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                           8
62051     #define TSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
62052     #define TSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                              9
62053     #define TSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
62054     #define TSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                           10
62055     #define TSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
62056     #define TSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                           11
62057     #define TSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
62058     #define TSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                           12
62059     #define TSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
62060     #define TSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                               13
62061     #define TSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
62062     #define TSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                           14
62063     #define TSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                  (0x1<<15) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
62064     #define TSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                            15
62065     #define TSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
62066     #define TSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                        16
62067     #define TSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
62068     #define TSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                            17
62069     #define TSDM_REG_INT_MASK_CM_DELAY_ERROR                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CM_DELAY_ERROR .
62070     #define TSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                   18
62071     #define TSDM_REG_INT_MASK_SH_DELAY_ERROR                                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.SH_DELAY_ERROR .
62072     #define TSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                   19
62073     #define TSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                        (0x1<<20) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CMPL_PEND_ERROR .
62074     #define TSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                  20
62075     #define TSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.CPRM_PEND_ERROR .
62076     #define TSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                  21
62077     #define TSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TIMER_ADDR_ERROR .
62078     #define TSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                 22
62079     #define TSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                       (0x1<<23) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.TIMER_PEND_ERROR .
62080     #define TSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                 23
62081     #define TSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DORQ_DPM_ERROR .
62082     #define TSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                   24
62083     #define TSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                     (0x1<<25) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
62084     #define TSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                               25
62085     #define TSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR                                                   (0x1<<26) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
62086     #define TSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_SHIFT                                             26
62087     #define TSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: TSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
62088     #define TSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_SHIFT                                             27
62089 #define TSDM_REG_INT_STS_WR                                                                          0xfb0048UL //Access:WR   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62090     #define TSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
62091     #define TSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
62092     #define TSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                      (0x1<<1) // Indicates that one of the input queues had a FIFO error.
62093     #define TSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                1
62094     #define TSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                     (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
62095     #define TSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                               2
62096     #define TSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                     (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
62097     #define TSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                               3
62098     #define TSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                       (0x1<<4) // FIFO in PRM interface sub-module reported an error.
62099     #define TSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                 4
62100     #define TSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                 (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
62101     #define TSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                           5
62102     #define TSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                 (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
62103     #define TSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                           6
62104     #define TSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                               (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
62105     #define TSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                         7
62106     #define TSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                               (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
62107     #define TSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                         8
62108     #define TSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                  (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
62109     #define TSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                            9
62110     #define TSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                               (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
62111     #define TSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                         10
62112     #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                               (0x1<<11) // BRB src pend fifo error in DMA_DST block.
62113     #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                         11
62114     #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                               (0x1<<12) // BRB src addr fifo error in DMA_DST block.
62115     #define TSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                         12
62116     #define TSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                   (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
62117     #define TSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                             13
62118     #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                               (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
62119     #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                         14
62120     #define TSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                (0x1<<15) // Read data firo in DMA_RSP block for BRB.
62121     #define TSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                          15
62122     #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                            (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
62123     #define TSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                      16
62124     #define TSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                (0x1<<17) // PXP read data fifo error in DMA_RSP block.
62125     #define TSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                          17
62126     #define TSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                       (0x1<<18) // Delay CM fifo error in CM block.
62127     #define TSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                 18
62128     #define TSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                       (0x1<<19) // Delay shared fifo error in CM block.
62129     #define TSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                 19
62130     #define TSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                      (0x1<<20) // Error in completion pending FIFO in internal write block.
62131     #define TSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                20
62132     #define TSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                      (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
62133     #define TSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                21
62134     #define TSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                     (0x1<<22) // Address fifo error in timer block.
62135     #define TSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                               22
62136     #define TSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                     (0x1<<23) // Pending fifo error in timer block.
62137     #define TSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                               23
62138     #define TSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                       (0x1<<24) // Dpm fifo error in dorq I/F block.
62139     #define TSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                 24
62140     #define TSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                   (0x1<<25) // PXP done fifo error in DMA_dst block.
62141     #define TSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                             25
62142     #define TSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR                                                 (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62143     #define TSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_SHIFT                                           26
62144     #define TSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR                                                 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62145     #define TSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_SHIFT                                           27
62146 #define TSDM_REG_INT_STS_CLR                                                                         0xfb004cUL //Access:RC   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62147     #define TSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
62148     #define TSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
62149     #define TSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                     (0x1<<1) // Indicates that one of the input queues had a FIFO error.
62150     #define TSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                               1
62151     #define TSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                    (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
62152     #define TSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                              2
62153     #define TSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                    (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
62154     #define TSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                              3
62155     #define TSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                      (0x1<<4) // FIFO in PRM interface sub-module reported an error.
62156     #define TSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                4
62157     #define TSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
62158     #define TSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                          5
62159     #define TSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
62160     #define TSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                          6
62161     #define TSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                              (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
62162     #define TSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                        7
62163     #define TSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                              (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
62164     #define TSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                        8
62165     #define TSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                 (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
62166     #define TSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                           9
62167     #define TSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                              (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
62168     #define TSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                        10
62169     #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                              (0x1<<11) // BRB src pend fifo error in DMA_DST block.
62170     #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                        11
62171     #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                              (0x1<<12) // BRB src addr fifo error in DMA_DST block.
62172     #define TSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                        12
62173     #define TSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                  (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
62174     #define TSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                            13
62175     #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                              (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
62176     #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                        14
62177     #define TSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                               (0x1<<15) // Read data firo in DMA_RSP block for BRB.
62178     #define TSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                         15
62179     #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                           (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
62180     #define TSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                     16
62181     #define TSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                               (0x1<<17) // PXP read data fifo error in DMA_RSP block.
62182     #define TSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                         17
62183     #define TSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                      (0x1<<18) // Delay CM fifo error in CM block.
62184     #define TSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                18
62185     #define TSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                      (0x1<<19) // Delay shared fifo error in CM block.
62186     #define TSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                19
62187     #define TSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                     (0x1<<20) // Error in completion pending FIFO in internal write block.
62188     #define TSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                               20
62189     #define TSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                     (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
62190     #define TSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                               21
62191     #define TSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                    (0x1<<22) // Address fifo error in timer block.
62192     #define TSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                              22
62193     #define TSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                    (0x1<<23) // Pending fifo error in timer block.
62194     #define TSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                              23
62195     #define TSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                      (0x1<<24) // Dpm fifo error in dorq I/F block.
62196     #define TSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                24
62197     #define TSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                  (0x1<<25) // PXP done fifo error in DMA_dst block.
62198     #define TSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                            25
62199     #define TSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR                                                (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62200     #define TSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_SHIFT                                          26
62201     #define TSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR                                                (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62202     #define TSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_SHIFT                                          27
62203 #define TSDM_REG_PRTY_MASK_H_0                                                                       0xfb0204UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
62204     #define TSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
62205     #define TSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           0
62206     #define TSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
62207     #define TSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           1
62208     #define TSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
62209     #define TSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           2
62210     #define TSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
62211     #define TSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           3
62212     #define TSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
62213     #define TSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           4
62214     #define TSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
62215     #define TSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           5
62216     #define TSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
62217     #define TSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                           6
62218     #define TSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
62219     #define TSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           7
62220     #define TSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
62221     #define TSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           8
62222     #define TSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<9) // This bit masks, when set, the Parity bit: TSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
62223     #define TSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           9
62224 #define TSDM_REG_MEM_ECC_EVENTS                                                                      0xfb0210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
62225 #define TSDM_REG_MEM008_I_MEM_DFT_K2                                                                 0xfb0218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_pxp_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62226 #define TSDM_REG_MEM007_I_MEM_DFT_K2                                                                 0xfb021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_int_ram_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62227 #define TSDM_REG_MEM006_I_MEM_DFT_K2                                                                 0xfb0220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.BRB_INP_FIFO_GEN_IF.i_sdm_brb_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62228 #define TSDM_REG_MEM005_I_MEM_DFT_K2                                                                 0xfb0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsdm.i_sdm_core.i_sdm_dma.i_sdm_dma_dst.i_sdm_dma_immed_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62229 #define TSDM_REG_MEM002_I_MEM_DFT_K2                                                                 0xfb0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsdm.i_sdm_core.i_sdm_async.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62230 #define TSDM_REG_MEM010_I_MEM_DFT_K2                                                                 0xfb022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsdm.i_sdm_core.i_sdm_timers_sram_wrap.DEFAULT_TIMERS_RAM_GEN_IF.i_sdm_timers_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
62231 #define TSDM_REG_MEM001_I_MEM_DFT_K2                                                                 0xfb0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsdm.i_sdm_core.i_inp_que_ram_wrap.DEFAULT_INP_QUE_RAM_GEN_IF.i_sdm_inp_que_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62232 #define TSDM_REG_MEM003_I_MEM_DFT_K2                                                                 0xfb0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsdm.i_sdm_core.i_sdm_cmp_msg_que_ram_wrap.TSDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_tsdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62233 #define TSDM_REG_TIMER_TICK                                                                          0xfb0400UL //Access:RW   DataWidth:0x20  Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.  Chips: BB_A0 BB_B0 K2
62234 #define TSDM_REG_TIMERS_TICK_ENABLE                                                                  0xfb0404UL //Access:RW   DataWidth:0x1   Enable for tick counter.  Chips: BB_A0 BB_B0 K2
62235 #define TSDM_REG_OPERATION_GEN                                                                       0xfb0408UL //Access:W    DataWidth:0x14  This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.  Chips: BB_A0 BB_B0 K2
62236 #define TSDM_REG_GRC_PRIVILEGE_LEVEL                                                                 0xfb040cUL //Access:RW   DataWidth:0x2   This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.  Chips: BB_A0 BB_B0 K2
62237 #define TSDM_REG_CM_MSG_CNT_ADDRESS                                                                  0xfb0410UL //Access:RW   DataWidth:0xf   The internal RAM address for storing the shadow of the CM completion message counter.  Chips: BB_A0 BB_B0 K2
62238 #define TSDM_REG_DORQ_DPM_START_ADDR                                                                 0xfb0414UL //Access:RW   DataWidth:0xf   The start address in the internal RAM for DORQ DPM messages.  Chips: BB_A0 BB_B0 K2
62239 #define TSDM_REG_RR_COMPLETE_REQ                                                                     0xfb0418UL //Access:R    DataWidth:0xa   Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.  Chips: BB_A0 BB_B0 K2
62240 #define TSDM_REG_RR_PTR_REQ                                                                          0xfb041cUL //Access:R    DataWidth:0x9   Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.  Chips: BB_A0 BB_B0 K2
62241 #define TSDM_REG_INT_RAM_RR_REQ                                                                      0xfb0420UL //Access:R    DataWidth:0x4   Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.  Chips: BB_A0 BB_B0 K2
62242 #define TSDM_REG_INP_QUEUE_ERR_VECT                                                                  0xfb0424UL //Access:R    DataWidth:0x9   This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.  Chips: BB_A0 BB_B0 K2
62243 #define TSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                              0xfb0428UL //Access:RW   DataWidth:0x5   This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.  Chips: BB_A0 BB_B0 K2
62244 #define TSDM_REG_ECO_RESERVED                                                                        0xfb042cUL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
62245 #define TSDM_REG_INIT_CREDIT_PXP                                                                     0xfb0500UL //Access:RW   DataWidth:0x3   The initial number of messages that can be sent to the pxp interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
62246 #define TSDM_REG_INIT_CREDIT_PCI                                                                     0xfb0504UL //Access:RW   DataWidth:0x2   The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
62247 #define TSDM_REG_INIT_CREDIT_TCFC_AC                                                                 0xfb0508UL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
62248 #define TSDM_REG_INIT_CREDIT_CCFC_AC                                                                 0xfb050cUL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
62249 #define TSDM_REG_INIT_CREDIT_CM                                                                      0xfb0510UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
62250 #define TSDM_REG_NUM_OF_DMA_CMD                                                                      0xfb0600UL //Access:RC   DataWidth:0x20  The number of SDM DMA commands executed.  Chips: BB_A0 BB_B0 K2
62251 #define TSDM_REG_NUM_OF_TIMERS_CMD                                                                   0xfb0604UL //Access:RC   DataWidth:0x20  The number of SDM timers commands executed.  Chips: BB_A0 BB_B0 K2
62252 #define TSDM_REG_NUM_OF_CCFC_LD_CMD                                                                  0xfb0608UL //Access:RC   DataWidth:0x20  The number of SDM CCFC load commands executed.  Chips: BB_A0 BB_B0 K2
62253 #define TSDM_REG_NUM_OF_CCFC_AC_CMD                                                                  0xfb060cUL //Access:RC   DataWidth:0x20  The number of SDM CCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
62254 #define TSDM_REG_NUM_OF_TCFC_LD_CMD                                                                  0xfb0610UL //Access:RC   DataWidth:0x20  The number of SDM TCFC load commands executed.  Chips: BB_A0 BB_B0 K2
62255 #define TSDM_REG_NUM_OF_TCFC_AC_CMD                                                                  0xfb0614UL //Access:RC   DataWidth:0x20  The number of SDM TCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
62256 #define TSDM_REG_NUM_OF_INT_CMD                                                                      0xfb0618UL //Access:RC   DataWidth:0x20  The number of SDM internal write commands executed.  Chips: BB_A0 BB_B0 K2
62257 #define TSDM_REG_NUM_OF_NOP_CMD                                                                      0xfb061cUL //Access:RC   DataWidth:0x20  The number of SDM NOP commands executed.  Chips: BB_A0 BB_B0 K2
62258 #define TSDM_REG_NUM_OF_GRC_CMD                                                                      0xfb0620UL //Access:RC   DataWidth:0x20  The number of GRC master commands executed.  Chips: BB_A0 BB_B0 K2
62259 #define TSDM_REG_NUM_OF_PRM_REQ                                                                      0xfb0624UL //Access:RC   DataWidth:0x20  The number of packet end messages received on the PRM completion interface.  Chips: BB_A0 BB_B0 K2
62260 #define TSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                0xfb0628UL //Access:RC   DataWidth:0x20  The number of requests received from the pxp async if.  Chips: BB_A0 BB_B0 K2
62261 #define TSDM_REG_NUM_OF_DPM_REQ                                                                      0xfb062cUL //Access:RC   DataWidth:0x20  The number of DORQ DPM messages received.  Chips: BB_A0 BB_B0 K2
62262 #define TSDM_REG_BRB_ALMOST_FULL                                                                     0xfb0700UL //Access:RW   DataWidth:0x5   Almost full signal for read data from BRB in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
62263 #define TSDM_REG_PXP_ALMOST_FULL                                                                     0xfb0704UL //Access:RW   DataWidth:0x4   Almost full signal for read data from pxp in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
62264 #define TSDM_REG_DORQ_ALMOST_FULL                                                                    0xfb0708UL //Access:RW   DataWidth:0x6   Almost full signal for read data from DORQ in SDM_DORQ block.  Chips: BB_A0 BB_B0 K2
62265 #define TSDM_REG_AGG_INT_CTRL                                                                        0xfb0800UL //Access:RW   DataWidth:0xa   This array of registers provides controls for each of 32 aggregated interrupts; The fiels are defined as follows: agg_int_ctrl[7:0] = EventID which selects the event ID of the associated handler; agg_int_ctrl[8] = T-flag which determines if a thread is allocated for this handler in the Storm; agg_int_ctrl[9] = Mode bit; where 0=normal and 1=auto-mask-mode.  Chips: BB_A0 BB_B0 K2
62266 #define TSDM_REG_AGG_INT_CTRL_SIZE                                                                   32
62267 #define TSDM_REG_AGG_INT_STATE                                                                       0xfb0a00UL //Access:R    DataWidth:0x2   This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.  Chips: BB_A0 BB_B0 K2
62268 #define TSDM_REG_AGG_INT_STATE_SIZE                                                                  32
62269 #define TSDM_REG_QUEUE_FULL                                                                          0xfb0c00UL //Access:R    DataWidth:0x9   Input queue fifo full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62270 #define TSDM_REG_INT_CMPL_PEND_FULL                                                                  0xfb0c04UL //Access:R    DataWidth:0x1   Internal write completion pending full in internal write block.  Chips: BB_A0 BB_B0 K2
62271 #define TSDM_REG_INT_CPRM_PEND_FULL                                                                  0xfb0c08UL //Access:R    DataWidth:0x1   Internal write completion parameter pending full in internal write block.  Chips: BB_A0 BB_B0 K2
62272 #define TSDM_REG_QM_FULL                                                                             0xfb0c0cUL //Access:R    DataWidth:0x1   QM IF  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62273 #define TSDM_REG_DELAY_FIFO_FULL                                                                     0xfb0c10UL //Access:R    DataWidth:0x1   Delay FIFO  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62274 #define TSDM_REG_TIMERS_PEND_FULL                                                                    0xfb0c14UL //Access:R    DataWidth:0x1   Pending FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
62275 #define TSDM_REG_TIMERS_ADDR_FULL                                                                    0xfb0c18UL //Access:R    DataWidth:0x1   Address FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
62276 #define TSDM_REG_RSP_PXP_RDATA_FULL                                                                  0xfb0c1cUL //Access:R    DataWidth:0x1   PXP rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62277 #define TSDM_REG_RSP_BRB_RDATA_FULL                                                                  0xfb0c20UL //Access:R    DataWidth:0x1   BRB read data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62278 #define TSDM_REG_RSP_INT_RAM_RDATA_FULL                                                              0xfb0c24UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62279 #define TSDM_REG_RSP_BRB_PEND_FULL                                                                   0xfb0c28UL //Access:R    DataWidth:0x1   BRB pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62280 #define TSDM_REG_RSP_INT_RAM_PEND_FULL                                                               0xfb0c2cUL //Access:R    DataWidth:0x1   Int_ram pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62281 #define TSDM_REG_RSP_BRB_IF_FULL                                                                     0xfb0c30UL //Access:R    DataWidth:0x1   BRB interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62282 #define TSDM_REG_RSP_PXP_IF_FULL                                                                     0xfb0c34UL //Access:R    DataWidth:0x1   PXP interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62283 #define TSDM_REG_DST_PXP_IMMED_FULL                                                                  0xfb0c38UL //Access:R    DataWidth:0x1   PXP immediate fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62284 #define TSDM_REG_DST_PXP_DST_PEND_FULL                                                               0xfb0c3cUL //Access:R    DataWidth:0x1   PXP destination pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62285 #define TSDM_REG_DST_PXP_SRC_PEND_FULL                                                               0xfb0c40UL //Access:R    DataWidth:0x1   PXP source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62286 #define TSDM_REG_DST_BRB_SRC_PEND_FULL                                                               0xfb0c44UL //Access:R    DataWidth:0x1   BRB source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62287 #define TSDM_REG_DST_BRB_SRC_ADDR_FULL                                                               0xfb0c48UL //Access:R    DataWidth:0x1   BRB source address fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62288 #define TSDM_REG_DST_PXP_LINK_FULL                                                                   0xfb0c4cUL //Access:R    DataWidth:0x1   PXP link list full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62289 #define TSDM_REG_DST_INT_RAM_WAIT_FULL                                                               0xfb0c50UL //Access:R    DataWidth:0x1   Int_ram_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62290 #define TSDM_REG_DST_PAS_BUF_WAIT_FULL                                                               0xfb0c54UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62291 #define TSDM_REG_DST_PXP_IF_FULL                                                                     0xfb0c58UL //Access:R    DataWidth:0x1   PXP if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62292 #define TSDM_REG_DST_INT_RAM_IF_FULL                                                                 0xfb0c5cUL //Access:R    DataWidth:0x1   Int_ram if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62293 #define TSDM_REG_DST_PAS_BUF_IF_FULL                                                                 0xfb0c60UL //Access:R    DataWidth:0x1   Pas_buf if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62294 #define TSDM_REG_SH_DELAY_FULL                                                                       0xfb0c64UL //Access:R    DataWidth:0x1   Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
62295 #define TSDM_REG_CM_DELAY_FULL                                                                       0xfb0c68UL //Access:R    DataWidth:0x1   CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
62296 #define TSDM_REG_CMSG_QUE_FULL                                                                       0xfb0c6cUL //Access:R    DataWidth:0x1   Completion message queue fifo full in sdm_cm block.  Chips: BB_A0 BB_B0 K2
62297 #define TSDM_REG_CCFC_LOAD_PEND_FULL                                                                 0xfb0c70UL //Access:R    DataWidth:0x1   CCFC load pending fifo full in the CCFC interface  block.  Chips: BB_A0 BB_B0 K2
62298 #define TSDM_REG_TCFC_LOAD_PEND_FULL                                                                 0xfb0c74UL //Access:R    DataWidth:0x1   TCFC load pending fifo full in the TCFC interface block.  Chips: BB_A0 BB_B0 K2
62299 #define TSDM_REG_ASYNC_HOST_FULL                                                                     0xfb0c78UL //Access:R    DataWidth:0x1   Async fifo full in sdm_async block.  Chips: BB_A0 BB_B0 K2
62300 #define TSDM_REG_PRM_FIFO_FULL                                                                       0xfb0c7cUL //Access:R    DataWidth:0x1   PRM FIFO full in PRM interface block.  Chips: BB_A0 BB_B0 K2
62301 #define TSDM_REG_RMT_XCM_FIFO_FULL                                                                   0xfb0c80UL //Access:R    DataWidth:0x1   Remote XCM FIFO full (exist only in MSDM => XCM interface).  Chips: K2
62302 #define TSDM_REG_RMT_YCM_FIFO_FULL                                                                   0xfb0c84UL //Access:R    DataWidth:0x1   Remote YCM FIFO full (exist only in MSDM => YCM interface).  Chips: K2
62303 #define TSDM_REG_INT_CMPL_PEND_EMPTY                                                                 0xfb0d00UL //Access:R    DataWidth:0x1   Internal write completion pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
62304 #define TSDM_REG_INT_CPRM_PEND_EMPTY                                                                 0xfb0d04UL //Access:R    DataWidth:0x1   Internal write completion parameter pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
62305 #define TSDM_REG_QUEUE_EMPTY                                                                         0xfb0d08UL //Access:R    DataWidth:0x9   Input queue fifo empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62306 #define TSDM_REG_DELAY_FIFO_EMPTY                                                                    0xfb0d0cUL //Access:R    DataWidth:0x1   Delay FIFO  empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62307 #define TSDM_REG_TIMERS_PEND_EMPTY                                                                   0xfb0d10UL //Access:R    DataWidth:0x1   Pending FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
62308 #define TSDM_REG_TIMERS_ADDR_EMPTY                                                                   0xfb0d14UL //Access:R    DataWidth:0x1   Address FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
62309 #define TSDM_REG_RSP_PXP_RDATA_EMPTY                                                                 0xfb0d18UL //Access:R    DataWidth:0x1   PXP rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62310 #define TSDM_REG_RSP_BRB_RDATA_EMPTY                                                                 0xfb0d1cUL //Access:R    DataWidth:0x1   BRB read data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62311 #define TSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                             0xfb0d20UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62312 #define TSDM_REG_RSP_BRB_PEND_EMPTY                                                                  0xfb0d24UL //Access:R    DataWidth:0x1   BRB pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62313 #define TSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                              0xfb0d28UL //Access:R    DataWidth:0x1   Int_ram pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62314 #define TSDM_REG_DST_PXP_IMMED_EMPTY                                                                 0xfb0d2cUL //Access:R    DataWidth:0x1   PXP immediate fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62315 #define TSDM_REG_DST_PXP_DST_PEND_EMPTY                                                              0xfb0d30UL //Access:R    DataWidth:0x1   PXP destination pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62316 #define TSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                              0xfb0d34UL //Access:R    DataWidth:0x1   PXP source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62317 #define TSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                              0xfb0d38UL //Access:R    DataWidth:0x1   BRB source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62318 #define TSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                              0xfb0d3cUL //Access:R    DataWidth:0x1   BRB source address fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62319 #define TSDM_REG_DST_PXP_LINK_EMPTY                                                                  0xfb0d40UL //Access:R    DataWidth:0x1   PXP link list empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62320 #define TSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                              0xfb0d44UL //Access:R    DataWidth:0x1   Int_ram_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62321 #define TSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                              0xfb0d48UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62322 #define TSDM_REG_SH_DELAY_EMPTY                                                                      0xfb0d4cUL //Access:R    DataWidth:0x1   Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
62323 #define TSDM_REG_CM_DELAY_EMPTY                                                                      0xfb0d50UL //Access:R    DataWidth:0x1   CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
62324 #define TSDM_REG_CMSG_QUE_EMPTY                                                                      0xfb0d54UL //Access:R    DataWidth:0x1   Completion message queue fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62325 #define TSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                0xfb0d58UL //Access:R    DataWidth:0x1   CCFC load pending fifo empty in sdm_ccfc block.  Chips: BB_A0 BB_B0 K2
62326 #define TSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                0xfb0d5cUL //Access:R    DataWidth:0x1   TCFC load pending fifo empty in sdm_tcfc block.  Chips: BB_A0 BB_B0 K2
62327 #define TSDM_REG_ASYNC_HOST_EMPTY                                                                    0xfb0d60UL //Access:R    DataWidth:0x1   Async fifo empty in sdm_async block.  Chips: BB_A0 BB_B0 K2
62328 #define TSDM_REG_PRM_FIFO_EMPTY                                                                      0xfb0d64UL //Access:R    DataWidth:0x1   PRM FIFO empty in sdm_prm_if block.  Chips: BB_A0 BB_B0 K2
62329 #define TSDM_REG_RMT_XCM_FIFO_EMPTY                                                                  0xfb0d68UL //Access:R    DataWidth:0x1   Remote XCM FIFO empty (exist only within MSDM => XCM path).  Chips: K2
62330 #define TSDM_REG_RMT_YCM_FIFO_EMPTY                                                                  0xfb0d6cUL //Access:R    DataWidth:0x1   Remote YCM FIFO empty (exist only within MSDM => YCM path).  Chips: K2
62331 #define TSDM_REG_DBG_OUT_DATA                                                                        0xfb0e00UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
62332 #define TSDM_REG_DBG_OUT_DATA_SIZE                                                                   8
62333 #define TSDM_REG_DBG_OUT_VALID                                                                       0xfb0e20UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
62334 #define TSDM_REG_DBG_OUT_FRAME                                                                       0xfb0e24UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
62335 #define TSDM_REG_DBG_SELECT                                                                          0xfb0e28UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
62336 #define TSDM_REG_DBG_DWORD_ENABLE                                                                    0xfb0e2cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
62337 #define TSDM_REG_DBG_SHIFT                                                                           0xfb0e30UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
62338 #define TSDM_REG_DBG_FORCE_VALID                                                                     0xfb0e34UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
62339 #define TSDM_REG_DBG_FORCE_FRAME                                                                     0xfb0e38UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
62340 #define TSDM_REG_ASYNC_FIFO                                                                          0xfb2000UL //Access:WB_R DataWidth:0x49  Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62341 #define TSDM_REG_ASYNC_FIFO_SIZE                                                                     116
62342 #define TSDM_REG_IMMED_FIFO                                                                          0xfb2400UL //Access:WB_R DataWidth:0x40  Provides read-only access of the immediate data FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62343 #define TSDM_REG_IMMED_FIFO_SIZE                                                                     38
62344 #define TSDM_REG_BRB_FIFO                                                                            0xfb2800UL //Access:WB_R DataWidth:0x86  Provides read-only access of the BRB response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62345 #define TSDM_REG_BRB_FIFO_SIZE                                                                       152
62346 #define TSDM_REG_PXP_FIFO                                                                            0xfb2c00UL //Access:WB_R DataWidth:0x4a  Provides read-only access of the PXP response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62347 #define TSDM_REG_PXP_FIFO_SIZE                                                                       76
62348 #define TSDM_REG_INT_RAM_FIFO                                                                        0xfb3000UL //Access:WB_R DataWidth:0x41  Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62349 #define TSDM_REG_INT_RAM_FIFO_SIZE                                                                   76
62350 #define TSDM_REG_DPM_FIFO                                                                            0xfb3400UL //Access:WB_R DataWidth:0x51  Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62351 #define TSDM_REG_DPM_FIFO_SIZE                                                                       172
62352 #define TSDM_REG_EXT_OVERFLOW                                                                        0xfb3800UL //Access:WB_R DataWidth:0x4b  Provides read-only access of the external store overflow FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62353 #define TSDM_REG_EXT_OVERFLOW_SIZE                                                                   36
62354 #define TSDM_REG_PRM_FIFO                                                                            0xfb3c00UL //Access:WB_R DataWidth:0x41  Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62355 #define TSDM_REG_PRM_FIFO_SIZE                                                                       84
62356 #define TSDM_REG_TIMERS                                                                              0xfb4000UL //Access:WB   DataWidth:0x3a  Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62357 #define TSDM_REG_TIMERS_SIZE                                                                         48
62358 #define TSDM_REG_INP_QUEUE                                                                           0xfb5000UL //Access:WB   DataWidth:0x40  Input queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
62359 #define TSDM_REG_INP_QUEUE_SIZE                                                                      416
62360 #define TSDM_REG_CMSG_QUE                                                                            0xfb8000UL //Access:WB   DataWidth:0x40  CM queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
62361 #define TSDM_REG_CMSG_QUE_SIZE                                                                       192
62362 #define MSDM_REG_ENABLE_IN1                                                                          0xfc0004UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62363     #define MSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                      (0x1<<0) // Enable for input command from STORM.
62364     #define MSDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                0
62365     #define MSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                   (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
62366     #define MSDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                             1
62367     #define MSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                   (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
62368     #define MSDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                             2
62369     #define MSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                   (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
62370     #define MSDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                             3
62371     #define MSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                   (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
62372     #define MSDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                             4
62373     #define MSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                   (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
62374     #define MSDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                             5
62375     #define MSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                       (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
62376     #define MSDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                 6
62377     #define MSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                       (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
62378     #define MSDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                 7
62379     #define MSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                       (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
62380     #define MSDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                 8
62381     #define MSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                    (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
62382     #define MSDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                              9
62383     #define MSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                        (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
62384     #define MSDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                  10
62385     #define MSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                       (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
62386     #define MSDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                 11
62387     #define MSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                        (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
62388     #define MSDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                  12
62389     #define MSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                        (0x1<<13) // Enable for input completion message from PRM in prm_if block.
62390     #define MSDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                  13
62391     #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                  (0x1<<14) // Enable for input ack to CCFC load credit counter.
62392     #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                            14
62393     #define MSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                  (0x1<<15) // Enable for input ack to TCFC load credit counter.
62394     #define MSDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                            15
62395     #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                  (0x1<<16) // Enable for input response from CCFC in CCFC block.
62396     #define MSDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                            16
62397     #define MSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                    (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
62398     #define MSDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                              17
62399     #define MSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                    (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
62400     #define MSDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                              18
62401     #define MSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                 (0x1<<19) // Enable for input full from qm in SDM_INP block.
62402     #define MSDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                           19
62403 #define MSDM_REG_ENABLE_IN2                                                                          0xfc0008UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
62404     #define MSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                  (0x1<<0) // Enable for input response from TCFC in TCFC block.
62405     #define MSDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                            0
62406     #define MSDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                         (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
62407     #define MSDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                   1
62408     #define MSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                       (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
62409     #define MSDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                 2
62410 #define MSDM_REG_ENABLE_OUT1                                                                         0xfc000cUL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62411     #define MSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                      (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
62412     #define MSDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                0
62413     #define MSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                   (0x1<<1) // Enable for output thread ready to the SEMI.
62414     #define MSDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                             1
62415     #define MSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                   (0x1<<2) // Enable the output thread release to the SEMI.
62416     #define MSDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                             2
62417     #define MSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                    (0x1<<3) // Enable for output load request to CCFC.
62418     #define MSDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                              3
62419     #define MSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                    (0x1<<4) // Enable for output load request to TCFC.
62420     #define MSDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                              4
62421     #define MSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                      (0x1<<5) // Enable for output increment to CCFC activity counter.
62422     #define MSDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                5
62423     #define MSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                      (0x1<<6) // Enable for output decrement to TCFC activity counter.
62424     #define MSDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                6
62425     #define MSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                      (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
62426     #define MSDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                7
62427     #define MSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                      (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
62428     #define MSDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                8
62429     #define MSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                      (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
62430     #define MSDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                9
62431     #define MSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                      (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
62432     #define MSDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                10
62433     #define MSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                    (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
62434     #define MSDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                              11
62435     #define MSDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                          (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
62436     #define MSDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                    12
62437     #define MSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                     (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
62438     #define MSDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                               13
62439     #define MSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                     (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
62440     #define MSDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                               14
62441     #define MSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                     (0x1<<15) // Enable for output external full to SEMI block.
62442     #define MSDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                               15
62443     #define MSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                 (0x1<<16) // Enable for output done to async PXP host IF.
62444     #define MSDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                           16
62445     #define MSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                 (0x1<<17) // Enable the output done (ack) to PRM.
62446     #define MSDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                           17
62447     #define MSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                       (0x1<<18) // Enable for output message to CM in SDM_CM block.
62448     #define MSDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                 18
62449     #define MSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                 (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
62450     #define MSDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                           19
62451     #define MSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                 (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
62452     #define MSDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                           20
62453 #define MSDM_REG_ENABLE_OUT2                                                                         0xfc0010UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
62454     #define MSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                    (0x1<<0) // Enable for output command to qm in SDM_INP block.
62455     #define MSDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                              0
62456     #define MSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                     (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
62457     #define MSDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                               1
62458     #define MSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
62459     #define MSDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                          2
62460 #define MSDM_REG_DISABLE_ENGINE                                                                      0xfc0014UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
62461     #define MSDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                      (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
62462     #define MSDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                0
62463     #define MSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                   (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
62464     #define MSDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                             1
62465     #define MSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
62466     #define MSDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                          2
62467     #define MSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
62468     #define MSDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                          3
62469     #define MSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                   (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
62470     #define MSDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                             4
62471     #define MSDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                      (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
62472     #define MSDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                5
62473     #define MSDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                      (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
62474     #define MSDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                6
62475     #define MSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                    (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
62476     #define MSDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                              7
62477     #define MSDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                      (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
62478     #define MSDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                8
62479     #define MSDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                     (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
62480     #define MSDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                               9
62481 #define MSDM_REG_INT_STS                                                                             0xfc0040UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62482     #define MSDM_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
62483     #define MSDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
62484     #define MSDM_REG_INT_STS_INP_QUEUE_ERROR                                                         (0x1<<1) // Indicates that one of the input queues had a FIFO error.
62485     #define MSDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                   1
62486     #define MSDM_REG_INT_STS_DELAY_FIFO_ERROR                                                        (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
62487     #define MSDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                  2
62488     #define MSDM_REG_INT_STS_ASYNC_HOST_ERROR                                                        (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
62489     #define MSDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                  3
62490     #define MSDM_REG_INT_STS_PRM_FIFO_ERROR                                                          (0x1<<4) // FIFO in PRM interface sub-module reported an error.
62491     #define MSDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                    4
62492     #define MSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                    (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
62493     #define MSDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                              5
62494     #define MSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                    (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
62495     #define MSDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                              6
62496     #define MSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                  (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
62497     #define MSDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                            7
62498     #define MSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                  (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
62499     #define MSDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                            8
62500     #define MSDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                     (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
62501     #define MSDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                               9
62502     #define MSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                  (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
62503     #define MSDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                            10
62504     #define MSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                  (0x1<<11) // BRB src pend fifo error in DMA_DST block.
62505     #define MSDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                            11
62506     #define MSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                  (0x1<<12) // BRB src addr fifo error in DMA_DST block.
62507     #define MSDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                            12
62508     #define MSDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                      (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
62509     #define MSDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                13
62510     #define MSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                  (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
62511     #define MSDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                            14
62512     #define MSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                   (0x1<<15) // Read data firo in DMA_RSP block for BRB.
62513     #define MSDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                             15
62514     #define MSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                               (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
62515     #define MSDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                         16
62516     #define MSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                   (0x1<<17) // PXP read data fifo error in DMA_RSP block.
62517     #define MSDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                             17
62518     #define MSDM_REG_INT_STS_CM_DELAY_ERROR                                                          (0x1<<18) // Delay CM fifo error in CM block.
62519     #define MSDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                    18
62520     #define MSDM_REG_INT_STS_SH_DELAY_ERROR                                                          (0x1<<19) // Delay shared fifo error in CM block.
62521     #define MSDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                    19
62522     #define MSDM_REG_INT_STS_CMPL_PEND_ERROR                                                         (0x1<<20) // Error in completion pending FIFO in internal write block.
62523     #define MSDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                   20
62524     #define MSDM_REG_INT_STS_CPRM_PEND_ERROR                                                         (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
62525     #define MSDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                   21
62526     #define MSDM_REG_INT_STS_TIMER_ADDR_ERROR                                                        (0x1<<22) // Address fifo error in timer block.
62527     #define MSDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                  22
62528     #define MSDM_REG_INT_STS_TIMER_PEND_ERROR                                                        (0x1<<23) // Pending fifo error in timer block.
62529     #define MSDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                  23
62530     #define MSDM_REG_INT_STS_DORQ_DPM_ERROR                                                          (0x1<<24) // Dpm fifo error in dorq I/F block.
62531     #define MSDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                    24
62532     #define MSDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                      (0x1<<25) // PXP done fifo error in DMA_dst block.
62533     #define MSDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                25
62534     #define MSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62535     #define MSDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_SHIFT                                              26
62536     #define MSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62537     #define MSDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_SHIFT                                              27
62538 #define MSDM_REG_INT_MASK                                                                            0xfc0044UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62539     #define MSDM_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.ADDRESS_ERROR .
62540     #define MSDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
62541     #define MSDM_REG_INT_MASK_INP_QUEUE_ERROR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.INP_QUEUE_ERROR .
62542     #define MSDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                  1
62543     #define MSDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DELAY_FIFO_ERROR .
62544     #define MSDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                 2
62545     #define MSDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.ASYNC_HOST_ERROR .
62546     #define MSDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                 3
62547     #define MSDM_REG_INT_MASK_PRM_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.PRM_FIFO_ERROR .
62548     #define MSDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                   4
62549     #define MSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
62550     #define MSDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                             5
62551     #define MSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
62552     #define MSDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                             6
62553     #define MSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
62554     #define MSDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                           7
62555     #define MSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
62556     #define MSDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                           8
62557     #define MSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
62558     #define MSDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                              9
62559     #define MSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
62560     #define MSDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                           10
62561     #define MSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
62562     #define MSDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                           11
62563     #define MSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
62564     #define MSDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                           12
62565     #define MSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
62566     #define MSDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                               13
62567     #define MSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
62568     #define MSDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                           14
62569     #define MSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                  (0x1<<15) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
62570     #define MSDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                            15
62571     #define MSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
62572     #define MSDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                        16
62573     #define MSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
62574     #define MSDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                            17
62575     #define MSDM_REG_INT_MASK_CM_DELAY_ERROR                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CM_DELAY_ERROR .
62576     #define MSDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                   18
62577     #define MSDM_REG_INT_MASK_SH_DELAY_ERROR                                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.SH_DELAY_ERROR .
62578     #define MSDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                   19
62579     #define MSDM_REG_INT_MASK_CMPL_PEND_ERROR                                                        (0x1<<20) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CMPL_PEND_ERROR .
62580     #define MSDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                  20
62581     #define MSDM_REG_INT_MASK_CPRM_PEND_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.CPRM_PEND_ERROR .
62582     #define MSDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                  21
62583     #define MSDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TIMER_ADDR_ERROR .
62584     #define MSDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                 22
62585     #define MSDM_REG_INT_MASK_TIMER_PEND_ERROR                                                       (0x1<<23) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.TIMER_PEND_ERROR .
62586     #define MSDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                 23
62587     #define MSDM_REG_INT_MASK_DORQ_DPM_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DORQ_DPM_ERROR .
62588     #define MSDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                   24
62589     #define MSDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                     (0x1<<25) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.DST_PXP_DONE_ERROR .
62590     #define MSDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                               25
62591     #define MSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR                                                   (0x1<<26) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
62592     #define MSDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_SHIFT                                             26
62593     #define MSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: MSDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
62594     #define MSDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_SHIFT                                             27
62595 #define MSDM_REG_INT_STS_WR                                                                          0xfc0048UL //Access:WR   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62596     #define MSDM_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
62597     #define MSDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
62598     #define MSDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                      (0x1<<1) // Indicates that one of the input queues had a FIFO error.
62599     #define MSDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                1
62600     #define MSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                     (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
62601     #define MSDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                               2
62602     #define MSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                     (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
62603     #define MSDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                               3
62604     #define MSDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                       (0x1<<4) // FIFO in PRM interface sub-module reported an error.
62605     #define MSDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                 4
62606     #define MSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                 (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
62607     #define MSDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                           5
62608     #define MSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                 (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
62609     #define MSDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                           6
62610     #define MSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                               (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
62611     #define MSDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                         7
62612     #define MSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                               (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
62613     #define MSDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                         8
62614     #define MSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                  (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
62615     #define MSDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                            9
62616     #define MSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                               (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
62617     #define MSDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                         10
62618     #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                               (0x1<<11) // BRB src pend fifo error in DMA_DST block.
62619     #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                         11
62620     #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                               (0x1<<12) // BRB src addr fifo error in DMA_DST block.
62621     #define MSDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                         12
62622     #define MSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                   (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
62623     #define MSDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                             13
62624     #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                               (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
62625     #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                         14
62626     #define MSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                (0x1<<15) // Read data firo in DMA_RSP block for BRB.
62627     #define MSDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                          15
62628     #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                            (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
62629     #define MSDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                      16
62630     #define MSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                (0x1<<17) // PXP read data fifo error in DMA_RSP block.
62631     #define MSDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                          17
62632     #define MSDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                       (0x1<<18) // Delay CM fifo error in CM block.
62633     #define MSDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                 18
62634     #define MSDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                       (0x1<<19) // Delay shared fifo error in CM block.
62635     #define MSDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                 19
62636     #define MSDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                      (0x1<<20) // Error in completion pending FIFO in internal write block.
62637     #define MSDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                20
62638     #define MSDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                      (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
62639     #define MSDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                21
62640     #define MSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                     (0x1<<22) // Address fifo error in timer block.
62641     #define MSDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                               22
62642     #define MSDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                     (0x1<<23) // Pending fifo error in timer block.
62643     #define MSDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                               23
62644     #define MSDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                       (0x1<<24) // Dpm fifo error in dorq I/F block.
62645     #define MSDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                 24
62646     #define MSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                   (0x1<<25) // PXP done fifo error in DMA_dst block.
62647     #define MSDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                             25
62648     #define MSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR                                                 (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62649     #define MSDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_SHIFT                                           26
62650     #define MSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR                                                 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62651     #define MSDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_SHIFT                                           27
62652 #define MSDM_REG_INT_STS_CLR                                                                         0xfc004cUL //Access:RC   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62653     #define MSDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
62654     #define MSDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
62655     #define MSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                     (0x1<<1) // Indicates that one of the input queues had a FIFO error.
62656     #define MSDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                               1
62657     #define MSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                    (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
62658     #define MSDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                              2
62659     #define MSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                    (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
62660     #define MSDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                              3
62661     #define MSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                      (0x1<<4) // FIFO in PRM interface sub-module reported an error.
62662     #define MSDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                4
62663     #define MSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
62664     #define MSDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                          5
62665     #define MSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
62666     #define MSDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                          6
62667     #define MSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                              (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
62668     #define MSDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                        7
62669     #define MSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                              (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
62670     #define MSDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                        8
62671     #define MSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                 (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
62672     #define MSDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                           9
62673     #define MSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                              (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
62674     #define MSDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                        10
62675     #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                              (0x1<<11) // BRB src pend fifo error in DMA_DST block.
62676     #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                        11
62677     #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                              (0x1<<12) // BRB src addr fifo error in DMA_DST block.
62678     #define MSDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                        12
62679     #define MSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                  (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
62680     #define MSDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                            13
62681     #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                              (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
62682     #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                        14
62683     #define MSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                               (0x1<<15) // Read data firo in DMA_RSP block for BRB.
62684     #define MSDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                         15
62685     #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                           (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
62686     #define MSDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                     16
62687     #define MSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                               (0x1<<17) // PXP read data fifo error in DMA_RSP block.
62688     #define MSDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                         17
62689     #define MSDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                      (0x1<<18) // Delay CM fifo error in CM block.
62690     #define MSDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                18
62691     #define MSDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                      (0x1<<19) // Delay shared fifo error in CM block.
62692     #define MSDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                19
62693     #define MSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                     (0x1<<20) // Error in completion pending FIFO in internal write block.
62694     #define MSDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                               20
62695     #define MSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                     (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
62696     #define MSDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                               21
62697     #define MSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                    (0x1<<22) // Address fifo error in timer block.
62698     #define MSDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                              22
62699     #define MSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                    (0x1<<23) // Pending fifo error in timer block.
62700     #define MSDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                              23
62701     #define MSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                      (0x1<<24) // Dpm fifo error in dorq I/F block.
62702     #define MSDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                24
62703     #define MSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                  (0x1<<25) // PXP done fifo error in DMA_dst block.
62704     #define MSDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                            25
62705     #define MSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR                                                (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62706     #define MSDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_SHIFT                                          26
62707     #define MSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR                                                (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
62708     #define MSDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_SHIFT                                          27
62709 #define MSDM_REG_PRTY_MASK_H_0                                                                       0xfc0204UL //Access:RW   DataWidth:0xb   Multi Field Register.  Chips: BB_A0 BB_B0 K2
62710     #define MSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
62711     #define MSDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           0
62712     #define MSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
62713     #define MSDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           1
62714     #define MSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
62715     #define MSDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           2
62716     #define MSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
62717     #define MSDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           3
62718     #define MSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
62719     #define MSDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           4
62720     #define MSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
62721     #define MSDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           5
62722     #define MSDM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
62723     #define MSDM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                           6
62724     #define MSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
62725     #define MSDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           7
62726     #define MSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
62727     #define MSDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           8
62728     #define MSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<9) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
62729     #define MSDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           9
62730     #define MSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                 (0x1<<10) // This bit masks, when set, the Parity bit: MSDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
62731     #define MSDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                           10
62732 #define MSDM_REG_MEM_ECC_EVENTS                                                                      0xfc0210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
62733 #define MSDM_REG_MEM008_I_MEM_DFT_K2                                                                 0xfc0218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_pxp_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62734 #define MSDM_REG_MEM007_I_MEM_DFT_K2                                                                 0xfc021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_int_ram_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62735 #define MSDM_REG_MEM006_I_MEM_DFT_K2                                                                 0xfc0220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.BRB_INP_FIFO_GEN_IF.i_sdm_brb_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62736 #define MSDM_REG_MEM005_I_MEM_DFT_K2                                                                 0xfc0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_dma.i_sdm_dma_dst.i_sdm_dma_immed_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62737 #define MSDM_REG_MEM002_I_MEM_DFT_K2                                                                 0xfc0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_async.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62738 #define MSDM_REG_MEM011_I_MEM_DFT_K2                                                                 0xfc022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_timers_sram_wrap.DEFAULT_TIMERS_RAM_GEN_IF.i_sdm_timers_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
62739 #define MSDM_REG_MEM001_I_MEM_DFT_K2                                                                 0xfc0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_inp_que_ram_wrap.DEFAULT_INP_QUE_RAM_GEN_IF.i_sdm_inp_que_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62740 #define MSDM_REG_MEM003_I_MEM_DFT_K2                                                                 0xfc0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_cmp_msg_que_ram_wrap.DEFAULT_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62741 #define MSDM_REG_MEM004_I_MEM_DFT_K2                                                                 0xfc0238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_delay_fifo_wrap.MSDM_DELAY_FIFO_GEN_IF.i_sdm_delay_fifo_msdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62742 #define MSDM_REG_MEM010_I_MEM_DFT_K2                                                                 0xfc023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msdm.i_sdm_core.i_sdm_prm_fifo_wrap.MSDM_PRM_FIFO_GEN_IF.i_sdm_prm_fifo_msdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
62743 #define MSDM_REG_TIMER_TICK                                                                          0xfc0400UL //Access:RW   DataWidth:0x20  Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.  Chips: BB_A0 BB_B0 K2
62744 #define MSDM_REG_TIMERS_TICK_ENABLE                                                                  0xfc0404UL //Access:RW   DataWidth:0x1   Enable for tick counter.  Chips: BB_A0 BB_B0 K2
62745 #define MSDM_REG_OPERATION_GEN                                                                       0xfc0408UL //Access:W    DataWidth:0x14  This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.  Chips: BB_A0 BB_B0 K2
62746 #define MSDM_REG_GRC_PRIVILEGE_LEVEL                                                                 0xfc040cUL //Access:RW   DataWidth:0x2   This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.  Chips: BB_A0 BB_B0 K2
62747 #define MSDM_REG_CM_MSG_CNT_ADDRESS                                                                  0xfc0410UL //Access:RW   DataWidth:0xf   The internal RAM address for storing the shadow of the CM completion message counter.  Chips: BB_A0 BB_B0 K2
62748 #define MSDM_REG_DORQ_DPM_START_ADDR                                                                 0xfc0414UL //Access:RW   DataWidth:0xf   The start address in the internal RAM for DORQ DPM messages.  Chips: BB_A0 BB_B0 K2
62749 #define MSDM_REG_RR_COMPLETE_REQ                                                                     0xfc0418UL //Access:R    DataWidth:0xa   Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.  Chips: BB_A0 BB_B0 K2
62750 #define MSDM_REG_RR_PTR_REQ                                                                          0xfc041cUL //Access:R    DataWidth:0x9   Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.  Chips: BB_A0 BB_B0 K2
62751 #define MSDM_REG_INT_RAM_RR_REQ                                                                      0xfc0420UL //Access:R    DataWidth:0x4   Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.  Chips: BB_A0 BB_B0 K2
62752 #define MSDM_REG_INP_QUEUE_ERR_VECT                                                                  0xfc0424UL //Access:R    DataWidth:0x9   This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.  Chips: BB_A0 BB_B0 K2
62753 #define MSDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                              0xfc0428UL //Access:RW   DataWidth:0x5   This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.  Chips: BB_A0 BB_B0 K2
62754 #define MSDM_REG_ECO_RESERVED                                                                        0xfc042cUL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
62755 #define MSDM_REG_INIT_CREDIT_PXP                                                                     0xfc0500UL //Access:RW   DataWidth:0x3   The initial number of messages that can be sent to the pxp interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
62756 #define MSDM_REG_INIT_CREDIT_PCI                                                                     0xfc0504UL //Access:RW   DataWidth:0x2   The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
62757 #define MSDM_REG_INIT_CREDIT_TCFC_AC                                                                 0xfc0508UL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
62758 #define MSDM_REG_INIT_CREDIT_CCFC_AC                                                                 0xfc050cUL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
62759 #define MSDM_REG_INIT_CREDIT_CM                                                                      0xfc0510UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
62760 #define MSDM_REG_INIT_CREDIT_CM_RMT                                                                  0xfc0520UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
62761 #define MSDM_REG_INIT_CREDIT_CM_RMT_SIZE                                                             2
62762 #define MSDM_REG_NUM_OF_DMA_CMD                                                                      0xfc0600UL //Access:RC   DataWidth:0x20  The number of SDM DMA commands executed.  Chips: BB_A0 BB_B0 K2
62763 #define MSDM_REG_NUM_OF_TIMERS_CMD                                                                   0xfc0604UL //Access:RC   DataWidth:0x20  The number of SDM timers commands executed.  Chips: BB_A0 BB_B0 K2
62764 #define MSDM_REG_NUM_OF_CCFC_LD_CMD                                                                  0xfc0608UL //Access:RC   DataWidth:0x20  The number of SDM CCFC load commands executed.  Chips: BB_A0 BB_B0 K2
62765 #define MSDM_REG_NUM_OF_CCFC_AC_CMD                                                                  0xfc060cUL //Access:RC   DataWidth:0x20  The number of SDM CCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
62766 #define MSDM_REG_NUM_OF_TCFC_LD_CMD                                                                  0xfc0610UL //Access:RC   DataWidth:0x20  The number of SDM TCFC load commands executed.  Chips: BB_A0 BB_B0 K2
62767 #define MSDM_REG_NUM_OF_TCFC_AC_CMD                                                                  0xfc0614UL //Access:RC   DataWidth:0x20  The number of SDM TCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
62768 #define MSDM_REG_NUM_OF_INT_CMD                                                                      0xfc0618UL //Access:RC   DataWidth:0x20  The number of SDM internal write commands executed.  Chips: BB_A0 BB_B0 K2
62769 #define MSDM_REG_NUM_OF_NOP_CMD                                                                      0xfc061cUL //Access:RC   DataWidth:0x20  The number of SDM NOP commands executed.  Chips: BB_A0 BB_B0 K2
62770 #define MSDM_REG_NUM_OF_GRC_CMD                                                                      0xfc0620UL //Access:RC   DataWidth:0x20  The number of GRC master commands executed.  Chips: BB_A0 BB_B0 K2
62771 #define MSDM_REG_NUM_OF_PRM_REQ                                                                      0xfc0624UL //Access:RC   DataWidth:0x20  The number of packet end messages received on the PRM completion interface.  Chips: BB_A0 BB_B0 K2
62772 #define MSDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                0xfc0628UL //Access:RC   DataWidth:0x20  The number of requests received from the pxp async if.  Chips: BB_A0 BB_B0 K2
62773 #define MSDM_REG_NUM_OF_DPM_REQ                                                                      0xfc062cUL //Access:RC   DataWidth:0x20  The number of DORQ DPM messages received.  Chips: BB_A0 BB_B0 K2
62774 #define MSDM_REG_BRB_ALMOST_FULL                                                                     0xfc0700UL //Access:RW   DataWidth:0x5   Almost full signal for read data from BRB in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
62775 #define MSDM_REG_PXP_ALMOST_FULL                                                                     0xfc0704UL //Access:RW   DataWidth:0x4   Almost full signal for read data from pxp in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
62776 #define MSDM_REG_DORQ_ALMOST_FULL                                                                    0xfc0708UL //Access:RW   DataWidth:0x6   Almost full signal for read data from DORQ in SDM_DORQ block.  Chips: BB_A0 BB_B0 K2
62777 #define MSDM_REG_AGG_INT_CTRL                                                                        0xfc0800UL //Access:RW   DataWidth:0xa   This array of registers provides controls for each of 32 aggregated interrupts; The fiels are defined as follows: agg_int_ctrl[7:0] = EventID which selects the event ID of the associated handler; agg_int_ctrl[8] = T-flag which determines if a thread is allocated for this handler in the Storm; agg_int_ctrl[9] = Mode bit; where 0=normal and 1=auto-mask-mode.  Chips: BB_A0 BB_B0 K2
62778 #define MSDM_REG_AGG_INT_CTRL_SIZE                                                                   32
62779 #define MSDM_REG_AGG_INT_STATE                                                                       0xfc0a00UL //Access:R    DataWidth:0x2   This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.  Chips: BB_A0 BB_B0 K2
62780 #define MSDM_REG_AGG_INT_STATE_SIZE                                                                  32
62781 #define MSDM_REG_QUEUE_FULL                                                                          0xfc0c00UL //Access:R    DataWidth:0x9   Input queue fifo full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62782 #define MSDM_REG_INT_CMPL_PEND_FULL                                                                  0xfc0c04UL //Access:R    DataWidth:0x1   Internal write completion pending full in internal write block.  Chips: BB_A0 BB_B0 K2
62783 #define MSDM_REG_INT_CPRM_PEND_FULL                                                                  0xfc0c08UL //Access:R    DataWidth:0x1   Internal write completion parameter pending full in internal write block.  Chips: BB_A0 BB_B0 K2
62784 #define MSDM_REG_QM_FULL                                                                             0xfc0c0cUL //Access:R    DataWidth:0x1   QM IF  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62785 #define MSDM_REG_DELAY_FIFO_FULL                                                                     0xfc0c10UL //Access:R    DataWidth:0x1   Delay FIFO  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62786 #define MSDM_REG_TIMERS_PEND_FULL                                                                    0xfc0c14UL //Access:R    DataWidth:0x1   Pending FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
62787 #define MSDM_REG_TIMERS_ADDR_FULL                                                                    0xfc0c18UL //Access:R    DataWidth:0x1   Address FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
62788 #define MSDM_REG_RSP_PXP_RDATA_FULL                                                                  0xfc0c1cUL //Access:R    DataWidth:0x1   PXP rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62789 #define MSDM_REG_RSP_BRB_RDATA_FULL                                                                  0xfc0c20UL //Access:R    DataWidth:0x1   BRB read data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62790 #define MSDM_REG_RSP_INT_RAM_RDATA_FULL                                                              0xfc0c24UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62791 #define MSDM_REG_RSP_BRB_PEND_FULL                                                                   0xfc0c28UL //Access:R    DataWidth:0x1   BRB pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62792 #define MSDM_REG_RSP_INT_RAM_PEND_FULL                                                               0xfc0c2cUL //Access:R    DataWidth:0x1   Int_ram pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62793 #define MSDM_REG_RSP_BRB_IF_FULL                                                                     0xfc0c30UL //Access:R    DataWidth:0x1   BRB interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62794 #define MSDM_REG_RSP_PXP_IF_FULL                                                                     0xfc0c34UL //Access:R    DataWidth:0x1   PXP interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62795 #define MSDM_REG_DST_PXP_IMMED_FULL                                                                  0xfc0c38UL //Access:R    DataWidth:0x1   PXP immediate fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62796 #define MSDM_REG_DST_PXP_DST_PEND_FULL                                                               0xfc0c3cUL //Access:R    DataWidth:0x1   PXP destination pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62797 #define MSDM_REG_DST_PXP_SRC_PEND_FULL                                                               0xfc0c40UL //Access:R    DataWidth:0x1   PXP source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62798 #define MSDM_REG_DST_BRB_SRC_PEND_FULL                                                               0xfc0c44UL //Access:R    DataWidth:0x1   BRB source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62799 #define MSDM_REG_DST_BRB_SRC_ADDR_FULL                                                               0xfc0c48UL //Access:R    DataWidth:0x1   BRB source address fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62800 #define MSDM_REG_DST_PXP_LINK_FULL                                                                   0xfc0c4cUL //Access:R    DataWidth:0x1   PXP link list full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62801 #define MSDM_REG_DST_INT_RAM_WAIT_FULL                                                               0xfc0c50UL //Access:R    DataWidth:0x1   Int_ram_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62802 #define MSDM_REG_DST_PAS_BUF_WAIT_FULL                                                               0xfc0c54UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62803 #define MSDM_REG_DST_PXP_IF_FULL                                                                     0xfc0c58UL //Access:R    DataWidth:0x1   PXP if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62804 #define MSDM_REG_DST_INT_RAM_IF_FULL                                                                 0xfc0c5cUL //Access:R    DataWidth:0x1   Int_ram if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62805 #define MSDM_REG_DST_PAS_BUF_IF_FULL                                                                 0xfc0c60UL //Access:R    DataWidth:0x1   Pas_buf if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62806 #define MSDM_REG_SH_DELAY_FULL                                                                       0xfc0c64UL //Access:R    DataWidth:0x1   Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
62807 #define MSDM_REG_CM_DELAY_FULL                                                                       0xfc0c68UL //Access:R    DataWidth:0x1   CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
62808 #define MSDM_REG_CMSG_QUE_FULL                                                                       0xfc0c6cUL //Access:R    DataWidth:0x1   Completion message queue fifo full in sdm_cm block.  Chips: BB_A0 BB_B0 K2
62809 #define MSDM_REG_CCFC_LOAD_PEND_FULL                                                                 0xfc0c70UL //Access:R    DataWidth:0x1   CCFC load pending fifo full in the CCFC interface  block.  Chips: BB_A0 BB_B0 K2
62810 #define MSDM_REG_TCFC_LOAD_PEND_FULL                                                                 0xfc0c74UL //Access:R    DataWidth:0x1   TCFC load pending fifo full in the TCFC interface block.  Chips: BB_A0 BB_B0 K2
62811 #define MSDM_REG_ASYNC_HOST_FULL                                                                     0xfc0c78UL //Access:R    DataWidth:0x1   Async fifo full in sdm_async block.  Chips: BB_A0 BB_B0 K2
62812 #define MSDM_REG_PRM_FIFO_FULL                                                                       0xfc0c7cUL //Access:R    DataWidth:0x1   PRM FIFO full in PRM interface block.  Chips: BB_A0 BB_B0 K2
62813 #define MSDM_REG_RMT_XCM_FIFO_FULL                                                                   0xfc0c80UL //Access:R    DataWidth:0x1   Remote XCM FIFO full (exist only in MSDM => XCM interface).  Chips: K2
62814 #define MSDM_REG_RMT_YCM_FIFO_FULL                                                                   0xfc0c84UL //Access:R    DataWidth:0x1   Remote YCM FIFO full (exist only in MSDM => YCM interface).  Chips: K2
62815 #define MSDM_REG_INT_CMPL_PEND_EMPTY                                                                 0xfc0d00UL //Access:R    DataWidth:0x1   Internal write completion pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
62816 #define MSDM_REG_INT_CPRM_PEND_EMPTY                                                                 0xfc0d04UL //Access:R    DataWidth:0x1   Internal write completion parameter pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
62817 #define MSDM_REG_QUEUE_EMPTY                                                                         0xfc0d08UL //Access:R    DataWidth:0x9   Input queue fifo empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62818 #define MSDM_REG_DELAY_FIFO_EMPTY                                                                    0xfc0d0cUL //Access:R    DataWidth:0x1   Delay FIFO  empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
62819 #define MSDM_REG_TIMERS_PEND_EMPTY                                                                   0xfc0d10UL //Access:R    DataWidth:0x1   Pending FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
62820 #define MSDM_REG_TIMERS_ADDR_EMPTY                                                                   0xfc0d14UL //Access:R    DataWidth:0x1   Address FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
62821 #define MSDM_REG_RSP_PXP_RDATA_EMPTY                                                                 0xfc0d18UL //Access:R    DataWidth:0x1   PXP rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62822 #define MSDM_REG_RSP_BRB_RDATA_EMPTY                                                                 0xfc0d1cUL //Access:R    DataWidth:0x1   BRB read data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62823 #define MSDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                             0xfc0d20UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62824 #define MSDM_REG_RSP_BRB_PEND_EMPTY                                                                  0xfc0d24UL //Access:R    DataWidth:0x1   BRB pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62825 #define MSDM_REG_RSP_INT_RAM_PEND_EMPTY                                                              0xfc0d28UL //Access:R    DataWidth:0x1   Int_ram pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
62826 #define MSDM_REG_DST_PXP_IMMED_EMPTY                                                                 0xfc0d2cUL //Access:R    DataWidth:0x1   PXP immediate fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62827 #define MSDM_REG_DST_PXP_DST_PEND_EMPTY                                                              0xfc0d30UL //Access:R    DataWidth:0x1   PXP destination pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62828 #define MSDM_REG_DST_PXP_SRC_PEND_EMPTY                                                              0xfc0d34UL //Access:R    DataWidth:0x1   PXP source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62829 #define MSDM_REG_DST_BRB_SRC_PEND_EMPTY                                                              0xfc0d38UL //Access:R    DataWidth:0x1   BRB source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62830 #define MSDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                              0xfc0d3cUL //Access:R    DataWidth:0x1   BRB source address fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62831 #define MSDM_REG_DST_PXP_LINK_EMPTY                                                                  0xfc0d40UL //Access:R    DataWidth:0x1   PXP link list empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62832 #define MSDM_REG_DST_INT_RAM_WAIT_EMPTY                                                              0xfc0d44UL //Access:R    DataWidth:0x1   Int_ram_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62833 #define MSDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                              0xfc0d48UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62834 #define MSDM_REG_SH_DELAY_EMPTY                                                                      0xfc0d4cUL //Access:R    DataWidth:0x1   Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
62835 #define MSDM_REG_CM_DELAY_EMPTY                                                                      0xfc0d50UL //Access:R    DataWidth:0x1   CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
62836 #define MSDM_REG_CMSG_QUE_EMPTY                                                                      0xfc0d54UL //Access:R    DataWidth:0x1   Completion message queue fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
62837 #define MSDM_REG_CCFC_LOAD_PEND_EMPTY                                                                0xfc0d58UL //Access:R    DataWidth:0x1   CCFC load pending fifo empty in sdm_ccfc block.  Chips: BB_A0 BB_B0 K2
62838 #define MSDM_REG_TCFC_LOAD_PEND_EMPTY                                                                0xfc0d5cUL //Access:R    DataWidth:0x1   TCFC load pending fifo empty in sdm_tcfc block.  Chips: BB_A0 BB_B0 K2
62839 #define MSDM_REG_ASYNC_HOST_EMPTY                                                                    0xfc0d60UL //Access:R    DataWidth:0x1   Async fifo empty in sdm_async block.  Chips: BB_A0 BB_B0 K2
62840 #define MSDM_REG_PRM_FIFO_EMPTY                                                                      0xfc0d64UL //Access:R    DataWidth:0x1   PRM FIFO empty in sdm_prm_if block.  Chips: BB_A0 BB_B0 K2
62841 #define MSDM_REG_RMT_XCM_FIFO_EMPTY                                                                  0xfc0d68UL //Access:R    DataWidth:0x1   Remote XCM FIFO empty (exist only within MSDM => XCM path).  Chips: K2
62842 #define MSDM_REG_RMT_YCM_FIFO_EMPTY                                                                  0xfc0d6cUL //Access:R    DataWidth:0x1   Remote YCM FIFO empty (exist only within MSDM => YCM path).  Chips: K2
62843 #define MSDM_REG_DBG_OUT_DATA                                                                        0xfc0e00UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
62844 #define MSDM_REG_DBG_OUT_DATA_SIZE                                                                   8
62845 #define MSDM_REG_DBG_OUT_VALID                                                                       0xfc0e20UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
62846 #define MSDM_REG_DBG_OUT_FRAME                                                                       0xfc0e24UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
62847 #define MSDM_REG_DBG_SELECT                                                                          0xfc0e28UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
62848 #define MSDM_REG_DBG_DWORD_ENABLE                                                                    0xfc0e2cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
62849 #define MSDM_REG_DBG_SHIFT                                                                           0xfc0e30UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
62850 #define MSDM_REG_DBG_FORCE_VALID                                                                     0xfc0e34UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
62851 #define MSDM_REG_DBG_FORCE_FRAME                                                                     0xfc0e38UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
62852 #define MSDM_REG_ASYNC_FIFO                                                                          0xfc2000UL //Access:WB_R DataWidth:0x49  Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62853 #define MSDM_REG_ASYNC_FIFO_SIZE                                                                     116
62854 #define MSDM_REG_IMMED_FIFO                                                                          0xfc2400UL //Access:WB_R DataWidth:0x40  Provides read-only access of the immediate data FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62855 #define MSDM_REG_IMMED_FIFO_SIZE                                                                     38
62856 #define MSDM_REG_BRB_FIFO                                                                            0xfc2800UL //Access:WB_R DataWidth:0x86  Provides read-only access of the BRB response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62857 #define MSDM_REG_BRB_FIFO_SIZE                                                                       152
62858 #define MSDM_REG_PXP_FIFO                                                                            0xfc2c00UL //Access:WB_R DataWidth:0x4a  Provides read-only access of the PXP response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62859 #define MSDM_REG_PXP_FIFO_SIZE                                                                       76
62860 #define MSDM_REG_INT_RAM_FIFO                                                                        0xfc3000UL //Access:WB_R DataWidth:0x41  Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62861 #define MSDM_REG_INT_RAM_FIFO_SIZE                                                                   76
62862 #define MSDM_REG_DPM_FIFO                                                                            0xfc3400UL //Access:WB_R DataWidth:0x51  Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62863 #define MSDM_REG_DPM_FIFO_SIZE                                                                       172
62864 #define MSDM_REG_EXT_OVERFLOW                                                                        0xfc3800UL //Access:WB_R DataWidth:0x4b  Provides read-only access of the external store overflow FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62865 #define MSDM_REG_EXT_OVERFLOW_SIZE                                                                   36
62866 #define MSDM_REG_PRM_FIFO                                                                            0xfc3c00UL //Access:WB_R DataWidth:0x41  Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62867 #define MSDM_REG_PRM_FIFO_SIZE                                                                       84
62868 #define MSDM_REG_TIMERS                                                                              0xfc4000UL //Access:WB   DataWidth:0x3a  Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
62869 #define MSDM_REG_TIMERS_SIZE                                                                         48
62870 #define MSDM_REG_INP_QUEUE                                                                           0xfc5000UL //Access:WB   DataWidth:0x40  Input queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
62871 #define MSDM_REG_INP_QUEUE_SIZE                                                                      416
62872 #define MSDM_REG_CMSG_QUE                                                                            0xfc8000UL //Access:WB   DataWidth:0x40  CM queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
62873 #define MSDM_REG_CMSG_QUE_SIZE                                                                       576
62874 #define USDM_REG_ENABLE_IN1                                                                          0xfd0004UL //Access:RW   DataWidth:0x14  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62875     #define USDM_REG_ENABLE_IN1_EXT_STORE_IN_EN                                                      (0x1<<0) // Enable for input command from STORM.
62876     #define USDM_REG_ENABLE_IN1_EXT_STORE_IN_EN_SHIFT                                                0
62877     #define USDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN                                                   (0x1<<1) // Enable for input data from internal ram interface in DMA_RSP block.
62878     #define USDM_REG_ENABLE_IN1_INT_RAM_DATA_IN_EN_SHIFT                                             1
62879     #define USDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN                                                   (0x1<<2) // Enable for input done from internal ram interface in DMA_RSP block.
62880     #define USDM_REG_ENABLE_IN1_INT_RAM_DONE_IN_EN_SHIFT                                             2
62881     #define USDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN                                                   (0x1<<3) // Enable for input full from internal ram interface in DMA_RSP block.
62882     #define USDM_REG_ENABLE_IN1_INT_RAM_FULL_IN_EN_SHIFT                                             3
62883     #define USDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN                                                   (0x1<<4) // Enable for input done from passive buffer interface in DMA_RSP block.
62884     #define USDM_REG_ENABLE_IN1_PAS_BUF_DONE_IN_EN_SHIFT                                             4
62885     #define USDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN                                                   (0x1<<5) // Enable for input full from passive buffer interface in DMA_RSP block.
62886     #define USDM_REG_ENABLE_IN1_PAS_BUF_FULL_IN_EN_SHIFT                                             5
62887     #define USDM_REG_ENABLE_IN1_PXP_DONE_IN_EN                                                       (0x1<<6) // Enable for input done from pxp-HW interface in DMA_DST block.
62888     #define USDM_REG_ENABLE_IN1_PXP_DONE_IN_EN_SHIFT                                                 6
62889     #define USDM_REG_ENABLE_IN1_PXP_FULL_IN_EN                                                       (0x1<<7) // Enable for input full from pxp-HW interface in DMA_DST block.
62890     #define USDM_REG_ENABLE_IN1_PXP_FULL_IN_EN_SHIFT                                                 7
62891     #define USDM_REG_ENABLE_IN1_PXP_DATA_IN_EN                                                       (0x1<<8) // Enable for input data from pxp-HW interface in DMA_RSP block.
62892     #define USDM_REG_ENABLE_IN1_PXP_DATA_IN_EN_SHIFT                                                 8
62893     #define USDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN                                                    (0x1<<9) // Enable for input ack from pxp-internal write for SDM_INT block.
62894     #define USDM_REG_ENABLE_IN1_PXP_INT_ACK_IN_EN_SHIFT                                              9
62895     #define USDM_REG_ENABLE_IN1_PXP_ACK_IN_EN                                                        (0x1<<10) // Enable for input acknowledge to credit counter from pxp_HW interface.
62896     #define USDM_REG_ENABLE_IN1_PXP_ACK_IN_EN_SHIFT                                                  10
62897     #define USDM_REG_ENABLE_IN1_BRB_DATA_IN_EN                                                       (0x1<<11) // Enable for input data from BRB interface in DMA_RSP block.
62898     #define USDM_REG_ENABLE_IN1_BRB_DATA_IN_EN_SHIFT                                                 11
62899     #define USDM_REG_ENABLE_IN1_PXP_REQ_IN_EN                                                        (0x1<<12) // Enable for input message from ASYNC pxp in pxp_async block.
62900     #define USDM_REG_ENABLE_IN1_PXP_REQ_IN_EN_SHIFT                                                  12
62901     #define USDM_REG_ENABLE_IN1_PRM_REQ_IN_EN                                                        (0x1<<13) // Enable for input completion message from PRM in prm_if block.
62902     #define USDM_REG_ENABLE_IN1_PRM_REQ_IN_EN_SHIFT                                                  13
62903     #define USDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN                                                  (0x1<<14) // Enable for input ack to CCFC load credit counter.
62904     #define USDM_REG_ENABLE_IN1_CCFC_LOAD_ACK_IN_EN_SHIFT                                            14
62905     #define USDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN                                                  (0x1<<15) // Enable for input ack to TCFC load credit counter.
62906     #define USDM_REG_ENABLE_IN1_TCFC_LOAD_ACK_IN_EN_SHIFT                                            15
62907     #define USDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN                                                  (0x1<<16) // Enable for input response from CCFC in CCFC block.
62908     #define USDM_REG_ENABLE_IN1_CCFC_LOAD_RSP_IN_EN_SHIFT                                            16
62909     #define USDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN                                                    (0x1<<17) // Enable for input ack to CCFC credit counter on the A/C interface.
62910     #define USDM_REG_ENABLE_IN1_CCFC_AC_ACK_IN_EN_SHIFT                                              17
62911     #define USDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN                                                    (0x1<<18) // Enable for input ack to TCFC credit counter on the A/C interface.
62912     #define USDM_REG_ENABLE_IN1_TCFC_AC_ACK_IN_EN_SHIFT                                              18
62913     #define USDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN                                                 (0x1<<19) // Enable for input full from qm in SDM_INP block.
62914     #define USDM_REG_ENABLE_IN1_QM_EXT_WR_FULL_IN_EN_SHIFT                                           19
62915 #define USDM_REG_ENABLE_IN2                                                                          0xfd0008UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
62916     #define USDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN                                                  (0x1<<0) // Enable for input response from TCFC in TCFC block.
62917     #define USDM_REG_ENABLE_IN2_TCFC_LOAD_RSP_IN_EN_SHIFT                                            0
62918     #define USDM_REG_ENABLE_IN2_CM_ACK_IN_EN                                                         (0x1<<1) // Enable for input acknowledge from Cm  in SDM_CM block.
62919     #define USDM_REG_ENABLE_IN2_CM_ACK_IN_EN_SHIFT                                                   1
62920     #define USDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN                                                       (0x1<<2) // Enable for input DPM requests in SDM_DORQ block.
62921     #define USDM_REG_ENABLE_IN2_DORQ_REQ_IN_EN_SHIFT                                                 2
62922 #define USDM_REG_ENABLE_OUT1                                                                         0xfd000cUL //Access:RW   DataWidth:0x15  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62923     #define USDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN                                                      (0x1<<0) // Enable for output request to pxp internal write for SDM_INT block.
62924     #define USDM_REG_ENABLE_OUT1_PXP_INT_OUT_EN_SHIFT                                                0
62925     #define USDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN                                                   (0x1<<1) // Enable for output thread ready to the SEMI.
62926     #define USDM_REG_ENABLE_OUT1_THREAD_RDY_OUT_EN_SHIFT                                             1
62927     #define USDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN                                                   (0x1<<2) // Enable the output thread release to the SEMI.
62928     #define USDM_REG_ENABLE_OUT1_THREAD_RLS_OUT_EN_SHIFT                                             2
62929     #define USDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN                                                    (0x1<<3) // Enable for output load request to CCFC.
62930     #define USDM_REG_ENABLE_OUT1_CCFC_LOAD_OUT_EN_SHIFT                                              3
62931     #define USDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN                                                    (0x1<<4) // Enable for output load request to TCFC.
62932     #define USDM_REG_ENABLE_OUT1_TCFC_LOAD_OUT_EN_SHIFT                                              4
62933     #define USDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN                                                      (0x1<<5) // Enable for output increment to CCFC activity counter.
62934     #define USDM_REG_ENABLE_OUT1_CCFC_AC_OUT_EN_SHIFT                                                5
62935     #define USDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN                                                      (0x1<<6) // Enable for output decrement to TCFC activity counter.
62936     #define USDM_REG_ENABLE_OUT1_TCFC_AC_OUT_EN_SHIFT                                                6
62937     #define USDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN                                                      (0x1<<7) // Enable for output data to pxp-HW interface in DMA_REQ block.
62938     #define USDM_REG_ENABLE_OUT1_PXP_REQ_OUT_EN_SHIFT                                                7
62939     #define USDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN                                                      (0x1<<8) // Enable for output request to BRB interface in DMA_REQ block.
62940     #define USDM_REG_ENABLE_OUT1_BRB_REQ_OUT_EN_SHIFT                                                8
62941     #define USDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN                                                      (0x1<<9) // Enable for output write to int_ram in DMA_DST block.
62942     #define USDM_REG_ENABLE_OUT1_INT_RAM_OUT_EN_SHIFT                                                9
62943     #define USDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN                                                      (0x1<<10) // Enable for output write topassive buffer in DMA_DST block.
62944     #define USDM_REG_ENABLE_OUT1_PAS_BUF_OUT_EN_SHIFT                                                10
62945     #define USDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN                                                    (0x1<<11) // Enable for output write to pxp async in DMA_DST block.
62946     #define USDM_REG_ENABLE_OUT1_PXP_ASYNC_OUT_EN_SHIFT                                              11
62947     #define USDM_REG_ENABLE_OUT1_PXP_OUT_EN                                                          (0x1<<12) // Enable for output write to pxp  in DMA_DST block.
62948     #define USDM_REG_ENABLE_OUT1_PXP_OUT_EN_SHIFT                                                    12
62949     #define USDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN                                                     (0x1<<13) // Enable for output full to BRB in DMA_RSP block.
62950     #define USDM_REG_ENABLE_OUT1_BRB_FULL_OUT_EN_SHIFT                                               13
62951     #define USDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN                                                     (0x1<<14) // Enable for output full to PXP in DMA_RSP block.
62952     #define USDM_REG_ENABLE_OUT1_PXP_FULL_OUT_EN_SHIFT                                               14
62953     #define USDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN                                                     (0x1<<15) // Enable for output external full to SEMI block.
62954     #define USDM_REG_ENABLE_OUT1_EXT_FULL_OUT_EN_SHIFT                                               15
62955     #define USDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN                                                 (0x1<<16) // Enable for output done to async PXP host IF.
62956     #define USDM_REG_ENABLE_OUT1_PXP_REQ_DONE_OUT_EN_SHIFT                                           16
62957     #define USDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN                                                 (0x1<<17) // Enable the output done (ack) to PRM.
62958     #define USDM_REG_ENABLE_OUT1_PRM_REQ_DONE_OUT_EN_SHIFT                                           17
62959     #define USDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN                                                       (0x1<<18) // Enable for output message to CM in SDM_CM block.
62960     #define USDM_REG_ENABLE_OUT1_CM_MSG_OUT_EN_SHIFT                                                 18
62961     #define USDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN                                                 (0x1<<19) // Enable for output ack after placement to sdm in CCFC block.
62962     #define USDM_REG_ENABLE_OUT1_CCFC_SDM_ACK_OUT_EN_SHIFT                                           19
62963     #define USDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN                                                 (0x1<<20) // Enable for output ack after placement to sdm in TCFC block.
62964     #define USDM_REG_ENABLE_OUT1_TCFC_SDM_ACK_OUT_EN_SHIFT                                           20
62965 #define USDM_REG_ENABLE_OUT2                                                                         0xfd0010UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
62966     #define USDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN                                                    (0x1<<0) // Enable for output command to qm in SDM_INP block.
62967     #define USDM_REG_ENABLE_OUT2_QM_EXT_WR_OUT_EN_SHIFT                                              0
62968     #define USDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN                                                     (0x1<<1) // Enable for VF/PF error valid in DMA_DST block.
62969     #define USDM_REG_ENABLE_OUT2_VFPF_ERR_OUT_EN_SHIFT                                               1
62970     #define USDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN                                                (0x1<<2) // Enable for DPM request done output in SDM_DORQ block.
62971     #define USDM_REG_ENABLE_OUT2_DORQ_REQ_DONE_OUT_EN_SHIFT                                          2
62972 #define USDM_REG_DISABLE_ENGINE                                                                      0xfd0014UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
62973     #define USDM_REG_DISABLE_ENGINE_DISABLE_DMA                                                      (0x1<<0) // This bit should be set to disable the DMA exectuion engine from processing DMA commands.
62974     #define USDM_REG_DISABLE_ENGINE_DISABLE_DMA_SHIFT                                                0
62975     #define USDM_REG_DISABLE_ENGINE_DISABLE_TIMERS                                                   (0x1<<1) // This bit should be set to disable the timers' exectuion engine from processing timers' commands.
62976     #define USDM_REG_DISABLE_ENGINE_DISABLE_TIMERS_SHIFT                                             1
62977     #define USDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD                                                (0x1<<2) // This bit should be set to disable the CCFC exectuion engine from processing CCFC load commands.
62978     #define USDM_REG_DISABLE_ENGINE_DISABLE_CCFC_LOAD_SHIFT                                          2
62979     #define USDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD                                                (0x1<<3) // This bit should be set to disable the TCFC exectuion engine from processing TCFC load commands.
62980     #define USDM_REG_DISABLE_ENGINE_DISABLE_TCFC_LOAD_SHIFT                                          3
62981     #define USDM_REG_DISABLE_ENGINE_DISABLE_INT_WR                                                   (0x1<<4) // This bit should be set to disable the internal write exectuion engine from processing Internal write commands.
62982     #define USDM_REG_DISABLE_ENGINE_DISABLE_INT_WR_SHIFT                                             4
62983     #define USDM_REG_DISABLE_ENGINE_DISABLE_NOP                                                      (0x1<<5) // This bit should be set to disable the SDM NOP exectuion engine from processing NOP commands.
62984     #define USDM_REG_DISABLE_ENGINE_DISABLE_NOP_SHIFT                                                5
62985     #define USDM_REG_DISABLE_ENGINE_DISABLE_GRC                                                      (0x1<<6) // This bit should be set to disable the GRC master exectuion engine from processing GRC master commands.
62986     #define USDM_REG_DISABLE_ENGINE_DISABLE_GRC_SHIFT                                                6
62987     #define USDM_REG_DISABLE_ENGINE_DISABLE_ASYNC                                                    (0x1<<7) // This bit should be set to disable the PXP-Async interface from processing PXP-Async requests.
62988     #define USDM_REG_DISABLE_ENGINE_DISABLE_ASYNC_SHIFT                                              7
62989     #define USDM_REG_DISABLE_ENGINE_DISABLE_PRM                                                      (0x1<<8) // This bit should be set to disable the PRM interface from processing PRM completion commands.
62990     #define USDM_REG_DISABLE_ENGINE_DISABLE_PRM_SHIFT                                                8
62991     #define USDM_REG_DISABLE_ENGINE_DISABLE_DORQ                                                     (0x1<<9) // This bit should be set to disable the DORQ DPM interface from processing DPM commands.
62992     #define USDM_REG_DISABLE_ENGINE_DISABLE_DORQ_SHIFT                                               9
62993 #define USDM_REG_INT_STS                                                                             0xfd0040UL //Access:R    DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
62994     #define USDM_REG_INT_STS_ADDRESS_ERROR                                                           (0x1<<0) // Signals an unknown address to the rf module.
62995     #define USDM_REG_INT_STS_ADDRESS_ERROR_SHIFT                                                     0
62996     #define USDM_REG_INT_STS_INP_QUEUE_ERROR                                                         (0x1<<1) // Indicates that one of the input queues had a FIFO error.
62997     #define USDM_REG_INT_STS_INP_QUEUE_ERROR_SHIFT                                                   1
62998     #define USDM_REG_INT_STS_DELAY_FIFO_ERROR                                                        (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
62999     #define USDM_REG_INT_STS_DELAY_FIFO_ERROR_SHIFT                                                  2
63000     #define USDM_REG_INT_STS_ASYNC_HOST_ERROR                                                        (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
63001     #define USDM_REG_INT_STS_ASYNC_HOST_ERROR_SHIFT                                                  3
63002     #define USDM_REG_INT_STS_PRM_FIFO_ERROR                                                          (0x1<<4) // FIFO in PRM interface sub-module reported an error.
63003     #define USDM_REG_INT_STS_PRM_FIFO_ERROR_SHIFT                                                    4
63004     #define USDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR                                                    (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
63005     #define USDM_REG_INT_STS_CCFC_LOAD_PEND_ERROR_SHIFT                                              5
63006     #define USDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR                                                    (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
63007     #define USDM_REG_INT_STS_TCFC_LOAD_PEND_ERROR_SHIFT                                              6
63008     #define USDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR                                                  (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
63009     #define USDM_REG_INT_STS_DST_INT_RAM_WAIT_ERROR_SHIFT                                            7
63010     #define USDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR                                                  (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
63011     #define USDM_REG_INT_STS_DST_PAS_BUF_WAIT_ERROR_SHIFT                                            8
63012     #define USDM_REG_INT_STS_DST_PXP_IMMED_ERROR                                                     (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
63013     #define USDM_REG_INT_STS_DST_PXP_IMMED_ERROR_SHIFT                                               9
63014     #define USDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR                                                  (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
63015     #define USDM_REG_INT_STS_DST_PXP_DST_PEND_ERROR_SHIFT                                            10
63016     #define USDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR                                                  (0x1<<11) // BRB src pend fifo error in DMA_DST block.
63017     #define USDM_REG_INT_STS_DST_BRB_SRC_PEND_ERROR_SHIFT                                            11
63018     #define USDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR                                                  (0x1<<12) // BRB src addr fifo error in DMA_DST block.
63019     #define USDM_REG_INT_STS_DST_BRB_SRC_ADDR_ERROR_SHIFT                                            12
63020     #define USDM_REG_INT_STS_RSP_BRB_PEND_ERROR                                                      (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
63021     #define USDM_REG_INT_STS_RSP_BRB_PEND_ERROR_SHIFT                                                13
63022     #define USDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR                                                  (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
63023     #define USDM_REG_INT_STS_RSP_INT_RAM_PEND_ERROR_SHIFT                                            14
63024     #define USDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR                                                   (0x1<<15) // Read data firo in DMA_RSP block for BRB.
63025     #define USDM_REG_INT_STS_RSP_BRB_RD_DATA_ERROR_SHIFT                                             15
63026     #define USDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR                                               (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
63027     #define USDM_REG_INT_STS_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                         16
63028     #define USDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR                                                   (0x1<<17) // PXP read data fifo error in DMA_RSP block.
63029     #define USDM_REG_INT_STS_RSP_PXP_RD_DATA_ERROR_SHIFT                                             17
63030     #define USDM_REG_INT_STS_CM_DELAY_ERROR                                                          (0x1<<18) // Delay CM fifo error in CM block.
63031     #define USDM_REG_INT_STS_CM_DELAY_ERROR_SHIFT                                                    18
63032     #define USDM_REG_INT_STS_SH_DELAY_ERROR                                                          (0x1<<19) // Delay shared fifo error in CM block.
63033     #define USDM_REG_INT_STS_SH_DELAY_ERROR_SHIFT                                                    19
63034     #define USDM_REG_INT_STS_CMPL_PEND_ERROR                                                         (0x1<<20) // Error in completion pending FIFO in internal write block.
63035     #define USDM_REG_INT_STS_CMPL_PEND_ERROR_SHIFT                                                   20
63036     #define USDM_REG_INT_STS_CPRM_PEND_ERROR                                                         (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
63037     #define USDM_REG_INT_STS_CPRM_PEND_ERROR_SHIFT                                                   21
63038     #define USDM_REG_INT_STS_TIMER_ADDR_ERROR                                                        (0x1<<22) // Address fifo error in timer block.
63039     #define USDM_REG_INT_STS_TIMER_ADDR_ERROR_SHIFT                                                  22
63040     #define USDM_REG_INT_STS_TIMER_PEND_ERROR                                                        (0x1<<23) // Pending fifo error in timer block.
63041     #define USDM_REG_INT_STS_TIMER_PEND_ERROR_SHIFT                                                  23
63042     #define USDM_REG_INT_STS_DORQ_DPM_ERROR                                                          (0x1<<24) // Dpm fifo error in dorq I/F block.
63043     #define USDM_REG_INT_STS_DORQ_DPM_ERROR_SHIFT                                                    24
63044     #define USDM_REG_INT_STS_DST_PXP_DONE_ERROR                                                      (0x1<<25) // PXP done fifo error in DMA_dst block.
63045     #define USDM_REG_INT_STS_DST_PXP_DONE_ERROR_SHIFT                                                25
63046     #define USDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR                                                    (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
63047     #define USDM_REG_INT_STS_XCM_RMT_BUFFER_ERROR_SHIFT                                              26
63048     #define USDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR                                                    (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
63049     #define USDM_REG_INT_STS_YCM_RMT_BUFFER_ERROR_SHIFT                                              27
63050 #define USDM_REG_INT_MASK                                                                            0xfd0044UL //Access:RW   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63051     #define USDM_REG_INT_MASK_ADDRESS_ERROR                                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.ADDRESS_ERROR .
63052     #define USDM_REG_INT_MASK_ADDRESS_ERROR_SHIFT                                                    0
63053     #define USDM_REG_INT_MASK_INP_QUEUE_ERROR                                                        (0x1<<1) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.INP_QUEUE_ERROR .
63054     #define USDM_REG_INT_MASK_INP_QUEUE_ERROR_SHIFT                                                  1
63055     #define USDM_REG_INT_MASK_DELAY_FIFO_ERROR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DELAY_FIFO_ERROR .
63056     #define USDM_REG_INT_MASK_DELAY_FIFO_ERROR_SHIFT                                                 2
63057     #define USDM_REG_INT_MASK_ASYNC_HOST_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.ASYNC_HOST_ERROR .
63058     #define USDM_REG_INT_MASK_ASYNC_HOST_ERROR_SHIFT                                                 3
63059     #define USDM_REG_INT_MASK_PRM_FIFO_ERROR                                                         (0x1<<4) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.PRM_FIFO_ERROR .
63060     #define USDM_REG_INT_MASK_PRM_FIFO_ERROR_SHIFT                                                   4
63061     #define USDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CCFC_LOAD_PEND_ERROR .
63062     #define USDM_REG_INT_MASK_CCFC_LOAD_PEND_ERROR_SHIFT                                             5
63063     #define USDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR                                                   (0x1<<6) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TCFC_LOAD_PEND_ERROR .
63064     #define USDM_REG_INT_MASK_TCFC_LOAD_PEND_ERROR_SHIFT                                             6
63065     #define USDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_INT_RAM_WAIT_ERROR .
63066     #define USDM_REG_INT_MASK_DST_INT_RAM_WAIT_ERROR_SHIFT                                           7
63067     #define USDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR                                                 (0x1<<8) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PAS_BUF_WAIT_ERROR .
63068     #define USDM_REG_INT_MASK_DST_PAS_BUF_WAIT_ERROR_SHIFT                                           8
63069     #define USDM_REG_INT_MASK_DST_PXP_IMMED_ERROR                                                    (0x1<<9) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_IMMED_ERROR .
63070     #define USDM_REG_INT_MASK_DST_PXP_IMMED_ERROR_SHIFT                                              9
63071     #define USDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR                                                 (0x1<<10) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_DST_PEND_ERROR .
63072     #define USDM_REG_INT_MASK_DST_PXP_DST_PEND_ERROR_SHIFT                                           10
63073     #define USDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR                                                 (0x1<<11) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_BRB_SRC_PEND_ERROR .
63074     #define USDM_REG_INT_MASK_DST_BRB_SRC_PEND_ERROR_SHIFT                                           11
63075     #define USDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_BRB_SRC_ADDR_ERROR .
63076     #define USDM_REG_INT_MASK_DST_BRB_SRC_ADDR_ERROR_SHIFT                                           12
63077     #define USDM_REG_INT_MASK_RSP_BRB_PEND_ERROR                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_BRB_PEND_ERROR .
63078     #define USDM_REG_INT_MASK_RSP_BRB_PEND_ERROR_SHIFT                                               13
63079     #define USDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR                                                 (0x1<<14) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_INT_RAM_PEND_ERROR .
63080     #define USDM_REG_INT_MASK_RSP_INT_RAM_PEND_ERROR_SHIFT                                           14
63081     #define USDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR                                                  (0x1<<15) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_BRB_RD_DATA_ERROR .
63082     #define USDM_REG_INT_MASK_RSP_BRB_RD_DATA_ERROR_SHIFT                                            15
63083     #define USDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR                                              (0x1<<16) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_INT_RAM_RD_DATA_ERROR .
63084     #define USDM_REG_INT_MASK_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                        16
63085     #define USDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.RSP_PXP_RD_DATA_ERROR .
63086     #define USDM_REG_INT_MASK_RSP_PXP_RD_DATA_ERROR_SHIFT                                            17
63087     #define USDM_REG_INT_MASK_CM_DELAY_ERROR                                                         (0x1<<18) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CM_DELAY_ERROR .
63088     #define USDM_REG_INT_MASK_CM_DELAY_ERROR_SHIFT                                                   18
63089     #define USDM_REG_INT_MASK_SH_DELAY_ERROR                                                         (0x1<<19) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.SH_DELAY_ERROR .
63090     #define USDM_REG_INT_MASK_SH_DELAY_ERROR_SHIFT                                                   19
63091     #define USDM_REG_INT_MASK_CMPL_PEND_ERROR                                                        (0x1<<20) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CMPL_PEND_ERROR .
63092     #define USDM_REG_INT_MASK_CMPL_PEND_ERROR_SHIFT                                                  20
63093     #define USDM_REG_INT_MASK_CPRM_PEND_ERROR                                                        (0x1<<21) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.CPRM_PEND_ERROR .
63094     #define USDM_REG_INT_MASK_CPRM_PEND_ERROR_SHIFT                                                  21
63095     #define USDM_REG_INT_MASK_TIMER_ADDR_ERROR                                                       (0x1<<22) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TIMER_ADDR_ERROR .
63096     #define USDM_REG_INT_MASK_TIMER_ADDR_ERROR_SHIFT                                                 22
63097     #define USDM_REG_INT_MASK_TIMER_PEND_ERROR                                                       (0x1<<23) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.TIMER_PEND_ERROR .
63098     #define USDM_REG_INT_MASK_TIMER_PEND_ERROR_SHIFT                                                 23
63099     #define USDM_REG_INT_MASK_DORQ_DPM_ERROR                                                         (0x1<<24) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DORQ_DPM_ERROR .
63100     #define USDM_REG_INT_MASK_DORQ_DPM_ERROR_SHIFT                                                   24
63101     #define USDM_REG_INT_MASK_DST_PXP_DONE_ERROR                                                     (0x1<<25) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.DST_PXP_DONE_ERROR .
63102     #define USDM_REG_INT_MASK_DST_PXP_DONE_ERROR_SHIFT                                               25
63103     #define USDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR                                                   (0x1<<26) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.XCM_RMT_BUFFER_ERROR .
63104     #define USDM_REG_INT_MASK_XCM_RMT_BUFFER_ERROR_SHIFT                                             26
63105     #define USDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: USDM_REG_INT_STS.YCM_RMT_BUFFER_ERROR .
63106     #define USDM_REG_INT_MASK_YCM_RMT_BUFFER_ERROR_SHIFT                                             27
63107 #define USDM_REG_INT_STS_WR                                                                          0xfd0048UL //Access:WR   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63108     #define USDM_REG_INT_STS_WR_ADDRESS_ERROR                                                        (0x1<<0) // Signals an unknown address to the rf module.
63109     #define USDM_REG_INT_STS_WR_ADDRESS_ERROR_SHIFT                                                  0
63110     #define USDM_REG_INT_STS_WR_INP_QUEUE_ERROR                                                      (0x1<<1) // Indicates that one of the input queues had a FIFO error.
63111     #define USDM_REG_INT_STS_WR_INP_QUEUE_ERROR_SHIFT                                                1
63112     #define USDM_REG_INT_STS_WR_DELAY_FIFO_ERROR                                                     (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
63113     #define USDM_REG_INT_STS_WR_DELAY_FIFO_ERROR_SHIFT                                               2
63114     #define USDM_REG_INT_STS_WR_ASYNC_HOST_ERROR                                                     (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
63115     #define USDM_REG_INT_STS_WR_ASYNC_HOST_ERROR_SHIFT                                               3
63116     #define USDM_REG_INT_STS_WR_PRM_FIFO_ERROR                                                       (0x1<<4) // FIFO in PRM interface sub-module reported an error.
63117     #define USDM_REG_INT_STS_WR_PRM_FIFO_ERROR_SHIFT                                                 4
63118     #define USDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR                                                 (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
63119     #define USDM_REG_INT_STS_WR_CCFC_LOAD_PEND_ERROR_SHIFT                                           5
63120     #define USDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR                                                 (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
63121     #define USDM_REG_INT_STS_WR_TCFC_LOAD_PEND_ERROR_SHIFT                                           6
63122     #define USDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR                                               (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
63123     #define USDM_REG_INT_STS_WR_DST_INT_RAM_WAIT_ERROR_SHIFT                                         7
63124     #define USDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR                                               (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
63125     #define USDM_REG_INT_STS_WR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                         8
63126     #define USDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR                                                  (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
63127     #define USDM_REG_INT_STS_WR_DST_PXP_IMMED_ERROR_SHIFT                                            9
63128     #define USDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR                                               (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
63129     #define USDM_REG_INT_STS_WR_DST_PXP_DST_PEND_ERROR_SHIFT                                         10
63130     #define USDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR                                               (0x1<<11) // BRB src pend fifo error in DMA_DST block.
63131     #define USDM_REG_INT_STS_WR_DST_BRB_SRC_PEND_ERROR_SHIFT                                         11
63132     #define USDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR                                               (0x1<<12) // BRB src addr fifo error in DMA_DST block.
63133     #define USDM_REG_INT_STS_WR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                         12
63134     #define USDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR                                                   (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
63135     #define USDM_REG_INT_STS_WR_RSP_BRB_PEND_ERROR_SHIFT                                             13
63136     #define USDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR                                               (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
63137     #define USDM_REG_INT_STS_WR_RSP_INT_RAM_PEND_ERROR_SHIFT                                         14
63138     #define USDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR                                                (0x1<<15) // Read data firo in DMA_RSP block for BRB.
63139     #define USDM_REG_INT_STS_WR_RSP_BRB_RD_DATA_ERROR_SHIFT                                          15
63140     #define USDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR                                            (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
63141     #define USDM_REG_INT_STS_WR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                      16
63142     #define USDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR                                                (0x1<<17) // PXP read data fifo error in DMA_RSP block.
63143     #define USDM_REG_INT_STS_WR_RSP_PXP_RD_DATA_ERROR_SHIFT                                          17
63144     #define USDM_REG_INT_STS_WR_CM_DELAY_ERROR                                                       (0x1<<18) // Delay CM fifo error in CM block.
63145     #define USDM_REG_INT_STS_WR_CM_DELAY_ERROR_SHIFT                                                 18
63146     #define USDM_REG_INT_STS_WR_SH_DELAY_ERROR                                                       (0x1<<19) // Delay shared fifo error in CM block.
63147     #define USDM_REG_INT_STS_WR_SH_DELAY_ERROR_SHIFT                                                 19
63148     #define USDM_REG_INT_STS_WR_CMPL_PEND_ERROR                                                      (0x1<<20) // Error in completion pending FIFO in internal write block.
63149     #define USDM_REG_INT_STS_WR_CMPL_PEND_ERROR_SHIFT                                                20
63150     #define USDM_REG_INT_STS_WR_CPRM_PEND_ERROR                                                      (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
63151     #define USDM_REG_INT_STS_WR_CPRM_PEND_ERROR_SHIFT                                                21
63152     #define USDM_REG_INT_STS_WR_TIMER_ADDR_ERROR                                                     (0x1<<22) // Address fifo error in timer block.
63153     #define USDM_REG_INT_STS_WR_TIMER_ADDR_ERROR_SHIFT                                               22
63154     #define USDM_REG_INT_STS_WR_TIMER_PEND_ERROR                                                     (0x1<<23) // Pending fifo error in timer block.
63155     #define USDM_REG_INT_STS_WR_TIMER_PEND_ERROR_SHIFT                                               23
63156     #define USDM_REG_INT_STS_WR_DORQ_DPM_ERROR                                                       (0x1<<24) // Dpm fifo error in dorq I/F block.
63157     #define USDM_REG_INT_STS_WR_DORQ_DPM_ERROR_SHIFT                                                 24
63158     #define USDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR                                                   (0x1<<25) // PXP done fifo error in DMA_dst block.
63159     #define USDM_REG_INT_STS_WR_DST_PXP_DONE_ERROR_SHIFT                                             25
63160     #define USDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR                                                 (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
63161     #define USDM_REG_INT_STS_WR_XCM_RMT_BUFFER_ERROR_SHIFT                                           26
63162     #define USDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR                                                 (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
63163     #define USDM_REG_INT_STS_WR_YCM_RMT_BUFFER_ERROR_SHIFT                                           27
63164 #define USDM_REG_INT_STS_CLR                                                                         0xfd004cUL //Access:RC   DataWidth:0x1c  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63165     #define USDM_REG_INT_STS_CLR_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
63166     #define USDM_REG_INT_STS_CLR_ADDRESS_ERROR_SHIFT                                                 0
63167     #define USDM_REG_INT_STS_CLR_INP_QUEUE_ERROR                                                     (0x1<<1) // Indicates that one of the input queues had a FIFO error.
63168     #define USDM_REG_INT_STS_CLR_INP_QUEUE_ERROR_SHIFT                                               1
63169     #define USDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR                                                    (0x1<<2) // Delay fifo in INP_CMD block outputs errors.
63170     #define USDM_REG_INT_STS_CLR_DELAY_FIFO_ERROR_SHIFT                                              2
63171     #define USDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR                                                    (0x1<<3) // PXP_HOST fifo in ASYNC block outputs errors.
63172     #define USDM_REG_INT_STS_CLR_ASYNC_HOST_ERROR_SHIFT                                              3
63173     #define USDM_REG_INT_STS_CLR_PRM_FIFO_ERROR                                                      (0x1<<4) // FIFO in PRM interface sub-module reported an error.
63174     #define USDM_REG_INT_STS_CLR_PRM_FIFO_ERROR_SHIFT                                                4
63175     #define USDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR                                                (0x1<<5) // CCFC_LOAD_PEND fifo in CCFC block outputs errors.
63176     #define USDM_REG_INT_STS_CLR_CCFC_LOAD_PEND_ERROR_SHIFT                                          5
63177     #define USDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR                                                (0x1<<6) // TCFC_LOAD_PEND fifo in TCFC block outputs errors.
63178     #define USDM_REG_INT_STS_CLR_TCFC_LOAD_PEND_ERROR_SHIFT                                          6
63179     #define USDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR                                              (0x1<<7) // INT_ram wait fifo error in DMA_DST block.
63180     #define USDM_REG_INT_STS_CLR_DST_INT_RAM_WAIT_ERROR_SHIFT                                        7
63181     #define USDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR                                              (0x1<<8) // Passive buffer wait fifo error in DMA_DST block.
63182     #define USDM_REG_INT_STS_CLR_DST_PAS_BUF_WAIT_ERROR_SHIFT                                        8
63183     #define USDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR                                                 (0x1<<9) // PXP immediate data fifo error in DMA_DST block.
63184     #define USDM_REG_INT_STS_CLR_DST_PXP_IMMED_ERROR_SHIFT                                           9
63185     #define USDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR                                              (0x1<<10) // PXP dst pending fifo error in DMA_DST block.
63186     #define USDM_REG_INT_STS_CLR_DST_PXP_DST_PEND_ERROR_SHIFT                                        10
63187     #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR                                              (0x1<<11) // BRB src pend fifo error in DMA_DST block.
63188     #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_PEND_ERROR_SHIFT                                        11
63189     #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR                                              (0x1<<12) // BRB src addr fifo error in DMA_DST block.
63190     #define USDM_REG_INT_STS_CLR_DST_BRB_SRC_ADDR_ERROR_SHIFT                                        12
63191     #define USDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR                                                  (0x1<<13) // Pend data fifo in DMA_RSP block for BRB.
63192     #define USDM_REG_INT_STS_CLR_RSP_BRB_PEND_ERROR_SHIFT                                            13
63193     #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR                                              (0x1<<14) // Pend data fifo in DMA_RSP block for int_ram.
63194     #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_PEND_ERROR_SHIFT                                        14
63195     #define USDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR                                               (0x1<<15) // Read data firo in DMA_RSP block for BRB.
63196     #define USDM_REG_INT_STS_CLR_RSP_BRB_RD_DATA_ERROR_SHIFT                                         15
63197     #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR                                           (0x1<<16) // INT_ram read data fifo error in DMA_RSP block.
63198     #define USDM_REG_INT_STS_CLR_RSP_INT_RAM_RD_DATA_ERROR_SHIFT                                     16
63199     #define USDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR                                               (0x1<<17) // PXP read data fifo error in DMA_RSP block.
63200     #define USDM_REG_INT_STS_CLR_RSP_PXP_RD_DATA_ERROR_SHIFT                                         17
63201     #define USDM_REG_INT_STS_CLR_CM_DELAY_ERROR                                                      (0x1<<18) // Delay CM fifo error in CM block.
63202     #define USDM_REG_INT_STS_CLR_CM_DELAY_ERROR_SHIFT                                                18
63203     #define USDM_REG_INT_STS_CLR_SH_DELAY_ERROR                                                      (0x1<<19) // Delay shared fifo error in CM block.
63204     #define USDM_REG_INT_STS_CLR_SH_DELAY_ERROR_SHIFT                                                19
63205     #define USDM_REG_INT_STS_CLR_CMPL_PEND_ERROR                                                     (0x1<<20) // Error in completion pending FIFO in internal write block.
63206     #define USDM_REG_INT_STS_CLR_CMPL_PEND_ERROR_SHIFT                                               20
63207     #define USDM_REG_INT_STS_CLR_CPRM_PEND_ERROR                                                     (0x1<<21) // Error in completion parameter pending FIFO in internal write block.
63208     #define USDM_REG_INT_STS_CLR_CPRM_PEND_ERROR_SHIFT                                               21
63209     #define USDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR                                                    (0x1<<22) // Address fifo error in timer block.
63210     #define USDM_REG_INT_STS_CLR_TIMER_ADDR_ERROR_SHIFT                                              22
63211     #define USDM_REG_INT_STS_CLR_TIMER_PEND_ERROR                                                    (0x1<<23) // Pending fifo error in timer block.
63212     #define USDM_REG_INT_STS_CLR_TIMER_PEND_ERROR_SHIFT                                              23
63213     #define USDM_REG_INT_STS_CLR_DORQ_DPM_ERROR                                                      (0x1<<24) // Dpm fifo error in dorq I/F block.
63214     #define USDM_REG_INT_STS_CLR_DORQ_DPM_ERROR_SHIFT                                                24
63215     #define USDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR                                                  (0x1<<25) // PXP done fifo error in DMA_dst block.
63216     #define USDM_REG_INT_STS_CLR_DST_PXP_DONE_ERROR_SHIFT                                            25
63217     #define USDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR                                                (0x1<<26) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
63218     #define USDM_REG_INT_STS_CLR_XCM_RMT_BUFFER_ERROR_SHIFT                                          26
63219     #define USDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR                                                (0x1<<27) // small FIFO error indication. FIFO is instantiated only in the MSDM => XCM  and MSDM =>YCM interface
63220     #define USDM_REG_INT_STS_CLR_YCM_RMT_BUFFER_ERROR_SHIFT                                          27
63221 #define USDM_REG_PRTY_MASK_H_0                                                                       0xfd0204UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
63222     #define USDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                 (0x1<<0) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
63223     #define USDM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                           0
63224     #define USDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                 (0x1<<1) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
63225     #define USDM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                           1
63226     #define USDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
63227     #define USDM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                           2
63228     #define USDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
63229     #define USDM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           3
63230     #define USDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
63231     #define USDM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           4
63232     #define USDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
63233     #define USDM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                           5
63234     #define USDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
63235     #define USDM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           6
63236     #define USDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<7) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
63237     #define USDM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           7
63238     #define USDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<8) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
63239     #define USDM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           8
63240     #define USDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                 (0x1<<9) // This bit masks, when set, the Parity bit: USDM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
63241     #define USDM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                           9
63242 #define USDM_REG_MEM_ECC_EVENTS                                                                      0xfd0210UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
63243 #define USDM_REG_MEM007_I_MEM_DFT_K2                                                                 0xfd0218UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_pxp_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
63244 #define USDM_REG_MEM006_I_MEM_DFT_K2                                                                 0xfd021cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usdm.i_sdm_core.i_sdm_dma.i_sdm_dma_rsp.i_sdm_int_ram_rsp_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
63245 #define USDM_REG_MEM005_I_MEM_DFT_K2                                                                 0xfd0220UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usdm.i_sdm_core.i_sdm_dma.i_sdm_dma_dst.i_sdm_dma_immed_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
63246 #define USDM_REG_MEM002_I_MEM_DFT_K2                                                                 0xfd0224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usdm.i_sdm_core.i_sdm_async.i_fifo_mem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
63247 #define USDM_REG_MEM010_I_MEM_DFT_K2                                                                 0xfd0228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usdm.i_sdm_core.i_sdm_timers_sram_wrap.USDM_TIMERS_RAM_GEN_IF.i_sdm_timers_ram_usdm.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
63248 #define USDM_REG_MEM001_I_MEM_DFT_K2                                                                 0xfd022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usdm.i_sdm_core.i_inp_que_ram_wrap.USDM_INP_QUE_RAM_GEN_IF.i_sdm_inp_que_ram_usdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
63249 #define USDM_REG_MEM003_I_MEM_DFT_K2                                                                 0xfd0230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usdm.i_sdm_core.i_sdm_cmp_msg_que_ram_wrap.USDM_COMP_MSG_QUE_RAM_GEN_IF.i_sdm_comp_msg_que_ram_usdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
63250 #define USDM_REG_MEM009_I_MEM_DFT_K2                                                                 0xfd0234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usdm.i_sdm_core.i_sdm_prm_fifo_wrap.USDM_PRM_FIFO_GEN_IF.i_sdm_prm_fifo_usdm.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
63251 #define USDM_REG_TIMER_TICK                                                                          0xfd0400UL //Access:RW   DataWidth:0x20  Defines the number of system clock cycles that are used to define a timers clock tick cycle. Note: The minimal legal value for this register is 25, lower values can cause timers functionality issues.  Chips: BB_A0 BB_B0 K2
63252 #define USDM_REG_TIMERS_TICK_ENABLE                                                                  0xfd0404UL //Access:RW   DataWidth:0x1   Enable for tick counter.  Chips: BB_A0 BB_B0 K2
63253 #define USDM_REG_OPERATION_GEN                                                                       0xfd0408UL //Access:W    DataWidth:0x14  This register is used to assert a completion operation of choice; It includes the following completion fields: bits 19:16 are Trig; bits 15:0 are CompParams. Note that trigger types 3,5 or 8 are not supported by this interface as they require a completion message. If there is an attempt to assert an OperationGen with Trig = 3,5 or 8, the operation will be voided.  Chips: BB_A0 BB_B0 K2
63254 #define USDM_REG_GRC_PRIVILEGE_LEVEL                                                                 0xfd040cUL //Access:RW   DataWidth:0x2   This register defines the PRV (privilege level) field within the FID structure of the SDM GRC master request.  Chips: BB_A0 BB_B0 K2
63255 #define USDM_REG_CM_MSG_CNT_ADDRESS                                                                  0xfd0410UL //Access:RW   DataWidth:0xf   The internal RAM address for storing the shadow of the CM completion message counter.  Chips: BB_A0 BB_B0 K2
63256 #define USDM_REG_DORQ_DPM_START_ADDR                                                                 0xfd0414UL //Access:RW   DataWidth:0xf   The start address in the internal RAM for DORQ DPM messages.  Chips: BB_A0 BB_B0 K2
63257 #define USDM_REG_RR_COMPLETE_REQ                                                                     0xfd0418UL //Access:R    DataWidth:0xa   Provides read access to the round robin arbiter used for all completion write requests  in the completion manager: b0-PXP async b1-NOP;b2-internal write; b3-timers;b4-DMA;b5-GRC master;b6-RBC; b7-PRM interface; b8-CCFC load; b9-TCFC load.  Chips: BB_A0 BB_B0 K2
63258 #define USDM_REG_RR_PTR_REQ                                                                          0xfd041cUL //Access:R    DataWidth:0x9   Provides read access to the round robin arbiter for the completion message pointer: b0-async; b1-dma; b2 - tcfc; b3-ccfc; b4-nop; b5-timers; b6-int_wr; b7-prm; b8-grc_master.  Chips: BB_A0 BB_B0 K2
63259 #define USDM_REG_INT_RAM_RR_REQ                                                                      0xfd0420UL //Access:R    DataWidth:0x4   Provides read access to the DMA done round-robin arbiter: b0-passive buffer destination; b1-internal RAM destination;b2-PXP source/destination;b3-BRB source.  Chips: BB_A0 BB_B0 K2
63260 #define USDM_REG_INP_QUEUE_ERR_VECT                                                                  0xfd0424UL //Access:R    DataWidth:0x9   This register is intended to be read in the event of an inp_queue_error interrupt.  It contains a vector with a bit per input queue. Clearing the interrupt causes this vector to be cleared. Errors on multiple FIFOs will be aggregated between interrupt clear requests.  Chips: BB_A0 BB_B0 K2
63261 #define USDM_REG_ASYNC_CMSG_ALLOC_LIMIT                                                              0xfd0428UL //Access:RW   DataWidth:0x5   This register defines the maximum number of completion messages that can be allocated to PXP-Async transactions at any given time. If the PXP-Async interface attempts to reserve beyond this limit, it will be held off until the situation is resolved.  Chips: BB_A0 BB_B0 K2
63262 #define USDM_REG_ECO_RESERVED                                                                        0xfd042cUL //Access:RW   DataWidth:0x8   Reserved bits for ECO.  Chips: BB_A0 BB_B0 K2
63263 #define USDM_REG_INIT_CREDIT_PXP                                                                     0xfd0500UL //Access:RW   DataWidth:0x3   The initial number of messages that can be sent to the pxp interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
63264 #define USDM_REG_INIT_CREDIT_PCI                                                                     0xfd0504UL //Access:RW   DataWidth:0x2   The initial number of messages that can be sent to the PCI-Switch on the internal write interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
63265 #define USDM_REG_INIT_CREDIT_TCFC_AC                                                                 0xfd0508UL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the TCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
63266 #define USDM_REG_INIT_CREDIT_CCFC_AC                                                                 0xfd050cUL //Access:RW   DataWidth:0x4   The initial number of messages that can be sent to the CCFC activity counters interface without receiving any ACK.  Chips: BB_A0 BB_B0 K2
63267 #define USDM_REG_INIT_CREDIT_CM                                                                      0xfd0510UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to the CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
63268 #define USDM_REG_INIT_CREDIT_CM_RMT                                                                  0xfd0520UL //Access:RW   DataWidth:0x4   The initial number of cycles that can be sent to a remote CM interface without receiving any ACK in CM block.  Chips: BB_A0 BB_B0 K2
63269 #define USDM_REG_INIT_CREDIT_CM_RMT_SIZE                                                             2
63270 #define USDM_REG_NUM_OF_DMA_CMD                                                                      0xfd0600UL //Access:RC   DataWidth:0x20  The number of SDM DMA commands executed.  Chips: BB_A0 BB_B0 K2
63271 #define USDM_REG_NUM_OF_TIMERS_CMD                                                                   0xfd0604UL //Access:RC   DataWidth:0x20  The number of SDM timers commands executed.  Chips: BB_A0 BB_B0 K2
63272 #define USDM_REG_NUM_OF_CCFC_LD_CMD                                                                  0xfd0608UL //Access:RC   DataWidth:0x20  The number of SDM CCFC load commands executed.  Chips: BB_A0 BB_B0 K2
63273 #define USDM_REG_NUM_OF_CCFC_AC_CMD                                                                  0xfd060cUL //Access:RC   DataWidth:0x20  The number of SDM CCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
63274 #define USDM_REG_NUM_OF_TCFC_LD_CMD                                                                  0xfd0610UL //Access:RC   DataWidth:0x20  The number of SDM TCFC load commands executed.  Chips: BB_A0 BB_B0 K2
63275 #define USDM_REG_NUM_OF_TCFC_AC_CMD                                                                  0xfd0614UL //Access:RC   DataWidth:0x20  The number of SDM TCFC activity counter commands executed.  Chips: BB_A0 BB_B0 K2
63276 #define USDM_REG_NUM_OF_INT_CMD                                                                      0xfd0618UL //Access:RC   DataWidth:0x20  The number of SDM internal write commands executed.  Chips: BB_A0 BB_B0 K2
63277 #define USDM_REG_NUM_OF_NOP_CMD                                                                      0xfd061cUL //Access:RC   DataWidth:0x20  The number of SDM NOP commands executed.  Chips: BB_A0 BB_B0 K2
63278 #define USDM_REG_NUM_OF_GRC_CMD                                                                      0xfd0620UL //Access:RC   DataWidth:0x20  The number of GRC master commands executed.  Chips: BB_A0 BB_B0 K2
63279 #define USDM_REG_NUM_OF_PRM_REQ                                                                      0xfd0624UL //Access:RC   DataWidth:0x20  The number of packet end messages received on the PRM completion interface.  Chips: BB_A0 BB_B0 K2
63280 #define USDM_REG_NUM_OF_PXP_ASYNC_REQ                                                                0xfd0628UL //Access:RC   DataWidth:0x20  The number of requests received from the pxp async if.  Chips: BB_A0 BB_B0 K2
63281 #define USDM_REG_NUM_OF_DPM_REQ                                                                      0xfd062cUL //Access:RC   DataWidth:0x20  The number of DORQ DPM messages received.  Chips: BB_A0 BB_B0 K2
63282 #define USDM_REG_BRB_ALMOST_FULL                                                                     0xfd0700UL //Access:RW   DataWidth:0x5   Almost full signal for read data from BRB in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
63283 #define USDM_REG_PXP_ALMOST_FULL                                                                     0xfd0704UL //Access:RW   DataWidth:0x4   Almost full signal for read data from pxp in DMA_RSP block.  Chips: BB_A0 BB_B0 K2
63284 #define USDM_REG_DORQ_ALMOST_FULL                                                                    0xfd0708UL //Access:RW   DataWidth:0x6   Almost full signal for read data from DORQ in SDM_DORQ block.  Chips: BB_A0 BB_B0 K2
63285 #define USDM_REG_AGG_INT_CTRL                                                                        0xfd0800UL //Access:RW   DataWidth:0xa   This array of registers provides controls for each of 32 aggregated interrupts; The fiels are defined as follows: agg_int_ctrl[7:0] = EventID which selects the event ID of the associated handler; agg_int_ctrl[8] = T-flag which determines if a thread is allocated for this handler in the Storm; agg_int_ctrl[9] = Mode bit; where 0=normal and 1=auto-mask-mode.  Chips: BB_A0 BB_B0 K2
63286 #define USDM_REG_AGG_INT_CTRL_SIZE                                                                   32
63287 #define USDM_REG_AGG_INT_STATE                                                                       0xfd0a00UL //Access:R    DataWidth:0x2   This array of registers provides access to each of the 32 aggregated interrupt request state machines; The values read from this register mean the following; 00 = IDLE; 01 = PEND; 10 = MASK; 11 = PANDM.  Chips: BB_A0 BB_B0 K2
63288 #define USDM_REG_AGG_INT_STATE_SIZE                                                                  32
63289 #define USDM_REG_QUEUE_FULL                                                                          0xfd0c00UL //Access:R    DataWidth:0x9   Input queue fifo full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
63290 #define USDM_REG_INT_CMPL_PEND_FULL                                                                  0xfd0c04UL //Access:R    DataWidth:0x1   Internal write completion pending full in internal write block.  Chips: BB_A0 BB_B0 K2
63291 #define USDM_REG_INT_CPRM_PEND_FULL                                                                  0xfd0c08UL //Access:R    DataWidth:0x1   Internal write completion parameter pending full in internal write block.  Chips: BB_A0 BB_B0 K2
63292 #define USDM_REG_QM_FULL                                                                             0xfd0c0cUL //Access:R    DataWidth:0x1   QM IF  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
63293 #define USDM_REG_DELAY_FIFO_FULL                                                                     0xfd0c10UL //Access:R    DataWidth:0x1   Delay FIFO  full in sdm_inp block.  Chips: BB_A0 BB_B0 K2
63294 #define USDM_REG_TIMERS_PEND_FULL                                                                    0xfd0c14UL //Access:R    DataWidth:0x1   Pending FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
63295 #define USDM_REG_TIMERS_ADDR_FULL                                                                    0xfd0c18UL //Access:R    DataWidth:0x1   Address FIFO  full in sdm_timers block.  Chips: BB_A0 BB_B0 K2
63296 #define USDM_REG_RSP_PXP_RDATA_FULL                                                                  0xfd0c1cUL //Access:R    DataWidth:0x1   PXP rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63297 #define USDM_REG_RSP_BRB_RDATA_FULL                                                                  0xfd0c20UL //Access:R    DataWidth:0x1   BRB read data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63298 #define USDM_REG_RSP_INT_RAM_RDATA_FULL                                                              0xfd0c24UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63299 #define USDM_REG_RSP_BRB_PEND_FULL                                                                   0xfd0c28UL //Access:R    DataWidth:0x1   BRB pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63300 #define USDM_REG_RSP_INT_RAM_PEND_FULL                                                               0xfd0c2cUL //Access:R    DataWidth:0x1   Int_ram pending fifo  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63301 #define USDM_REG_RSP_BRB_IF_FULL                                                                     0xfd0c30UL //Access:R    DataWidth:0x1   BRB interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63302 #define USDM_REG_RSP_PXP_IF_FULL                                                                     0xfd0c34UL //Access:R    DataWidth:0x1   PXP interface is  full in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63303 #define USDM_REG_DST_PXP_IMMED_FULL                                                                  0xfd0c38UL //Access:R    DataWidth:0x1   PXP immediate fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63304 #define USDM_REG_DST_PXP_DST_PEND_FULL                                                               0xfd0c3cUL //Access:R    DataWidth:0x1   PXP destination pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63305 #define USDM_REG_DST_PXP_SRC_PEND_FULL                                                               0xfd0c40UL //Access:R    DataWidth:0x1   PXP source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63306 #define USDM_REG_DST_BRB_SRC_PEND_FULL                                                               0xfd0c44UL //Access:R    DataWidth:0x1   BRB source pending fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63307 #define USDM_REG_DST_BRB_SRC_ADDR_FULL                                                               0xfd0c48UL //Access:R    DataWidth:0x1   BRB source address fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63308 #define USDM_REG_DST_PXP_LINK_FULL                                                                   0xfd0c4cUL //Access:R    DataWidth:0x1   PXP link list full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63309 #define USDM_REG_DST_INT_RAM_WAIT_FULL                                                               0xfd0c50UL //Access:R    DataWidth:0x1   Int_ram_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63310 #define USDM_REG_DST_PAS_BUF_WAIT_FULL                                                               0xfd0c54UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63311 #define USDM_REG_DST_PXP_IF_FULL                                                                     0xfd0c58UL //Access:R    DataWidth:0x1   PXP if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63312 #define USDM_REG_DST_INT_RAM_IF_FULL                                                                 0xfd0c5cUL //Access:R    DataWidth:0x1   Int_ram if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63313 #define USDM_REG_DST_PAS_BUF_IF_FULL                                                                 0xfd0c60UL //Access:R    DataWidth:0x1   Pas_buf if full in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63314 #define USDM_REG_SH_DELAY_FULL                                                                       0xfd0c64UL //Access:R    DataWidth:0x1   Shared delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
63315 #define USDM_REG_CM_DELAY_FULL                                                                       0xfd0c68UL //Access:R    DataWidth:0x1   CM delay FIFO full in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
63316 #define USDM_REG_CMSG_QUE_FULL                                                                       0xfd0c6cUL //Access:R    DataWidth:0x1   Completion message queue fifo full in sdm_cm block.  Chips: BB_A0 BB_B0 K2
63317 #define USDM_REG_CCFC_LOAD_PEND_FULL                                                                 0xfd0c70UL //Access:R    DataWidth:0x1   CCFC load pending fifo full in the CCFC interface  block.  Chips: BB_A0 BB_B0 K2
63318 #define USDM_REG_TCFC_LOAD_PEND_FULL                                                                 0xfd0c74UL //Access:R    DataWidth:0x1   TCFC load pending fifo full in the TCFC interface block.  Chips: BB_A0 BB_B0 K2
63319 #define USDM_REG_ASYNC_HOST_FULL                                                                     0xfd0c78UL //Access:R    DataWidth:0x1   Async fifo full in sdm_async block.  Chips: BB_A0 BB_B0 K2
63320 #define USDM_REG_PRM_FIFO_FULL                                                                       0xfd0c7cUL //Access:R    DataWidth:0x1   PRM FIFO full in PRM interface block.  Chips: BB_A0 BB_B0 K2
63321 #define USDM_REG_RMT_XCM_FIFO_FULL                                                                   0xfd0c80UL //Access:R    DataWidth:0x1   Remote XCM FIFO full (exist only in MSDM => XCM interface).  Chips: K2
63322 #define USDM_REG_RMT_YCM_FIFO_FULL                                                                   0xfd0c84UL //Access:R    DataWidth:0x1   Remote YCM FIFO full (exist only in MSDM => YCM interface).  Chips: K2
63323 #define USDM_REG_INT_CMPL_PEND_EMPTY                                                                 0xfd0d00UL //Access:R    DataWidth:0x1   Internal write completion pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
63324 #define USDM_REG_INT_CPRM_PEND_EMPTY                                                                 0xfd0d04UL //Access:R    DataWidth:0x1   Internal write completion parameter pending empty in internal write block.  Chips: BB_A0 BB_B0 K2
63325 #define USDM_REG_QUEUE_EMPTY                                                                         0xfd0d08UL //Access:R    DataWidth:0x9   Input queue fifo empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
63326 #define USDM_REG_DELAY_FIFO_EMPTY                                                                    0xfd0d0cUL //Access:R    DataWidth:0x1   Delay FIFO  empty in sdm_inp block.  Chips: BB_A0 BB_B0 K2
63327 #define USDM_REG_TIMERS_PEND_EMPTY                                                                   0xfd0d10UL //Access:R    DataWidth:0x1   Pending FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
63328 #define USDM_REG_TIMERS_ADDR_EMPTY                                                                   0xfd0d14UL //Access:R    DataWidth:0x1   Address FIFO  empty in sdm_timers block.  Chips: BB_A0 BB_B0 K2
63329 #define USDM_REG_RSP_PXP_RDATA_EMPTY                                                                 0xfd0d18UL //Access:R    DataWidth:0x1   PXP rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63330 #define USDM_REG_RSP_BRB_RDATA_EMPTY                                                                 0xfd0d1cUL //Access:R    DataWidth:0x1   BRB read data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63331 #define USDM_REG_RSP_INT_RAM_RDATA_EMPTY                                                             0xfd0d20UL //Access:R    DataWidth:0x1   Int_ram rd_data fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63332 #define USDM_REG_RSP_BRB_PEND_EMPTY                                                                  0xfd0d24UL //Access:R    DataWidth:0x1   BRB pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63333 #define USDM_REG_RSP_INT_RAM_PEND_EMPTY                                                              0xfd0d28UL //Access:R    DataWidth:0x1   Int_ram pending fifo  empty in sdm_dma_rsp block.  Chips: BB_A0 BB_B0 K2
63334 #define USDM_REG_DST_PXP_IMMED_EMPTY                                                                 0xfd0d2cUL //Access:R    DataWidth:0x1   PXP immediate fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63335 #define USDM_REG_DST_PXP_DST_PEND_EMPTY                                                              0xfd0d30UL //Access:R    DataWidth:0x1   PXP destination pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63336 #define USDM_REG_DST_PXP_SRC_PEND_EMPTY                                                              0xfd0d34UL //Access:R    DataWidth:0x1   PXP source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63337 #define USDM_REG_DST_BRB_SRC_PEND_EMPTY                                                              0xfd0d38UL //Access:R    DataWidth:0x1   BRB source pending fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63338 #define USDM_REG_DST_BRB_SRC_ADDR_EMPTY                                                              0xfd0d3cUL //Access:R    DataWidth:0x1   BRB source address fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63339 #define USDM_REG_DST_PXP_LINK_EMPTY                                                                  0xfd0d40UL //Access:R    DataWidth:0x1   PXP link list empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63340 #define USDM_REG_DST_INT_RAM_WAIT_EMPTY                                                              0xfd0d44UL //Access:R    DataWidth:0x1   Int_ram_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63341 #define USDM_REG_DST_PAS_BUF_WAIT_EMPTY                                                              0xfd0d48UL //Access:R    DataWidth:0x1   Pas_buf_wait fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63342 #define USDM_REG_SH_DELAY_EMPTY                                                                      0xfd0d4cUL //Access:R    DataWidth:0x1   Shared delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all completions that have completion messages except for local CM completions, which have their own queue. This includes remote CM completions, internal write completions and internal RAM completions.  Chips: BB_A0 BB_B0 K2
63343 #define USDM_REG_CM_DELAY_EMPTY                                                                      0xfd0d50UL //Access:R    DataWidth:0x1   CM delay FIFO empty in SDM completion manager block. This FIFO is used to queue the completion parameters for all direct message completions that will be sent to the local CM.  Chips: BB_A0 BB_B0 K2
63344 #define USDM_REG_CMSG_QUE_EMPTY                                                                      0xfd0d54UL //Access:R    DataWidth:0x1   Completion message queue fifo empty in sdm_dma_dst block.  Chips: BB_A0 BB_B0 K2
63345 #define USDM_REG_CCFC_LOAD_PEND_EMPTY                                                                0xfd0d58UL //Access:R    DataWidth:0x1   CCFC load pending fifo empty in sdm_ccfc block.  Chips: BB_A0 BB_B0 K2
63346 #define USDM_REG_TCFC_LOAD_PEND_EMPTY                                                                0xfd0d5cUL //Access:R    DataWidth:0x1   TCFC load pending fifo empty in sdm_tcfc block.  Chips: BB_A0 BB_B0 K2
63347 #define USDM_REG_ASYNC_HOST_EMPTY                                                                    0xfd0d60UL //Access:R    DataWidth:0x1   Async fifo empty in sdm_async block.  Chips: BB_A0 BB_B0 K2
63348 #define USDM_REG_PRM_FIFO_EMPTY                                                                      0xfd0d64UL //Access:R    DataWidth:0x1   PRM FIFO empty in sdm_prm_if block.  Chips: BB_A0 BB_B0 K2
63349 #define USDM_REG_RMT_XCM_FIFO_EMPTY                                                                  0xfd0d68UL //Access:R    DataWidth:0x1   Remote XCM FIFO empty (exist only within MSDM => XCM path).  Chips: K2
63350 #define USDM_REG_RMT_YCM_FIFO_EMPTY                                                                  0xfd0d6cUL //Access:R    DataWidth:0x1   Remote YCM FIFO empty (exist only within MSDM => YCM path).  Chips: K2
63351 #define USDM_REG_DBG_OUT_DATA                                                                        0xfd0e00UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
63352 #define USDM_REG_DBG_OUT_DATA_SIZE                                                                   8
63353 #define USDM_REG_DBG_OUT_VALID                                                                       0xfd0e20UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
63354 #define USDM_REG_DBG_OUT_FRAME                                                                       0xfd0e24UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
63355 #define USDM_REG_DBG_SELECT                                                                          0xfd0e28UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
63356 #define USDM_REG_DBG_DWORD_ENABLE                                                                    0xfd0e2cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
63357 #define USDM_REG_DBG_SHIFT                                                                           0xfd0e30UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
63358 #define USDM_REG_DBG_FORCE_VALID                                                                     0xfd0e34UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
63359 #define USDM_REG_DBG_FORCE_FRAME                                                                     0xfd0e38UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
63360 #define USDM_REG_ASYNC_FIFO                                                                          0xfd2000UL //Access:WB_R DataWidth:0x49  Provides read-only access of the PXP-Async input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63361 #define USDM_REG_ASYNC_FIFO_SIZE                                                                     116
63362 #define USDM_REG_IMMED_FIFO                                                                          0xfd2400UL //Access:WB_R DataWidth:0x40  Provides read-only access of the immediate data FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63363 #define USDM_REG_IMMED_FIFO_SIZE                                                                     38
63364 #define USDM_REG_BRB_FIFO                                                                            0xfd2800UL //Access:WB_R DataWidth:0x86  Provides read-only access of the BRB response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63365 #define USDM_REG_BRB_FIFO_SIZE                                                                       152
63366 #define USDM_REG_PXP_FIFO                                                                            0xfd2c00UL //Access:WB_R DataWidth:0x4a  Provides read-only access of the PXP response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63367 #define USDM_REG_PXP_FIFO_SIZE                                                                       76
63368 #define USDM_REG_INT_RAM_FIFO                                                                        0xfd3000UL //Access:WB_R DataWidth:0x41  Provides read-only access of the internal RAM response FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63369 #define USDM_REG_INT_RAM_FIFO_SIZE                                                                   76
63370 #define USDM_REG_DPM_FIFO                                                                            0xfd3400UL //Access:WB_R DataWidth:0x51  Provides read-only access of the DORQ DPM input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63371 #define USDM_REG_DPM_FIFO_SIZE                                                                       172
63372 #define USDM_REG_EXT_OVERFLOW                                                                        0xfd3800UL //Access:WB_R DataWidth:0x4b  Provides read-only access of the external store overflow FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63373 #define USDM_REG_EXT_OVERFLOW_SIZE                                                                   36
63374 #define USDM_REG_PRM_FIFO                                                                            0xfd3c00UL //Access:WB_R DataWidth:0x41  Provides read-only access of the PRM completion input FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63375 #define USDM_REG_PRM_FIFO_SIZE                                                                       116
63376 #define USDM_REG_TIMERS                                                                              0xfd4000UL //Access:WB   DataWidth:0x39  Provides memory-mapped read/write access to the timers' memory. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
63377 #define USDM_REG_TIMERS_SIZE                                                                         32
63378 #define USDM_REG_INP_QUEUE                                                                           0xfd5000UL //Access:WB   DataWidth:0x40  Input queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
63379 #define USDM_REG_INP_QUEUE_SIZE                                                                      376
63380 #define USDM_REG_CMSG_QUE                                                                            0xfd8000UL //Access:WB   DataWidth:0x40  CM queue memory. Access only for debugging.  Chips: BB_A0 BB_B0 K2
63381 #define USDM_REG_CMSG_QUE_SIZE                                                                       384
63382 #define XCM_REG_INIT                                                                                 0x1000000UL //Access:RW   DataWidth:0x1   Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.  Chips: BB_A0 BB_B0 K2
63383 #define XCM_REG_QM_ACT_ST_CNT_INIT                                                                   0x1000004UL //Access:W    DataWidth:0x1   QM Active State counter initialization trigger.  Chips: BB_A0 BB_B0 K2
63384 #define XCM_REG_QM_ACT_ST_CNT_INIT_DONE                                                              0x1000008UL //Access:RC   DataWidth:0x1   QM Active State counter initialization done.  Chips: BB_A0 BB_B0 K2
63385 #define XCM_REG_DBG_SELECT                                                                           0x1000040UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
63386 #define XCM_REG_DBG_DWORD_ENABLE                                                                     0x1000044UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
63387 #define XCM_REG_DBG_SHIFT                                                                            0x1000048UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
63388 #define XCM_REG_DBG_FORCE_VALID                                                                      0x100004cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
63389 #define XCM_REG_DBG_FORCE_FRAME                                                                      0x1000050UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
63390 #define XCM_REG_DBG_OUT_DATA                                                                         0x1000060UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
63391 #define XCM_REG_DBG_OUT_DATA_SIZE                                                                    8
63392 #define XCM_REG_DBG_OUT_VALID                                                                        0x1000080UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
63393 #define XCM_REG_DBG_OUT_FRAME                                                                        0x1000084UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
63394 #define XCM_REG_INT_STS_0                                                                            0x1000180UL //Access:R    DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63395     #define XCM_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
63396     #define XCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
63397     #define XCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                      (0x1<<1) // Write to full STORM input buffer.
63398     #define XCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                1
63399     #define XCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                     (0x1<<2) // Read from empty  STORM input buffer.
63400     #define XCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                               2
63401     #define XCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR                                                       (0x1<<3) // Write to full MSDM input buffer.
63402     #define XCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT                                                 3
63403     #define XCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR                                                      (0x1<<4) // Read from empty MSDM input buffer.
63404     #define XCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR_SHIFT                                                4
63405     #define XCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR                                                       (0x1<<5) // Write to full XSDM input buffer.
63406     #define XCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR_SHIFT                                                 5
63407     #define XCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR                                                      (0x1<<6) // Read from empty XSDM input buffer.
63408     #define XCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR_SHIFT                                                6
63409     #define XCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR                                                       (0x1<<7) // Write to full YSDM input buffer.
63410     #define XCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT                                                 7
63411     #define XCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR                                                      (0x1<<8) // Read from empty  YSDM input buffer.
63412     #define XCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT                                                8
63413     #define XCM_REG_INT_STS_0_IS_USDM_OVFL_ERR                                                       (0x1<<9) // Write to full USDM input buffer.
63414     #define XCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_SHIFT                                                 9
63415     #define XCM_REG_INT_STS_0_IS_USDM_UNDER_ERR                                                      (0x1<<10) // Read from empty USDM input buffer.
63416     #define XCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_SHIFT                                                10
63417     #define XCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR                                                       (0x1<<11) // Write to full Msem input buffer.
63418     #define XCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_SHIFT                                                 11
63419     #define XCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR                                                      (0x1<<12) // Read from empty  Msem input buffer.
63420     #define XCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_SHIFT                                                12
63421     #define XCM_REG_INT_STS_0_IS_USEM_OVFL_ERR                                                       (0x1<<13) // Write to full Usem input buffer.
63422     #define XCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_SHIFT                                                 13
63423     #define XCM_REG_INT_STS_0_IS_USEM_UNDER_ERR                                                      (0x1<<14) // Read from empty Usem input buffer.
63424     #define XCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_SHIFT                                                14
63425     #define XCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR                                                       (0x1<<15) // Write to full Ysem input buffer.
63426     #define XCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_SHIFT                                                 15
63427 #define XCM_REG_INT_MASK_0                                                                           0x1000184UL //Access:RW   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63428     #define XCM_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.ADDRESS_ERROR .
63429     #define XCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
63430     #define XCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
63431     #define XCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                               1
63432     #define XCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
63433     #define XCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                              2
63434     #define XCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
63435     #define XCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT                                                3
63436     #define XCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
63437     #define XCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR_SHIFT                                               4
63438     #define XCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_XSDM_OVFL_ERR .
63439     #define XCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR_SHIFT                                                5
63440     #define XCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_XSDM_UNDER_ERR .
63441     #define XCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR_SHIFT                                               6
63442     #define XCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
63443     #define XCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT                                                7
63444     #define XCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
63445     #define XCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT                                               8
63446     #define XCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
63447     #define XCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_SHIFT                                                9
63448     #define XCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
63449     #define XCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_SHIFT                                               10
63450     #define XCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
63451     #define XCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_SHIFT                                                11
63452     #define XCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
63453     #define XCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_SHIFT                                               12
63454     #define XCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR                                                      (0x1<<13) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
63455     #define XCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_SHIFT                                                13
63456     #define XCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR                                                     (0x1<<14) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
63457     #define XCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_SHIFT                                               14
63458     #define XCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR                                                      (0x1<<15) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
63459     #define XCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_SHIFT                                                15
63460 #define XCM_REG_INT_STS_WR_0                                                                         0x1000188UL //Access:WR   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63461     #define XCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
63462     #define XCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
63463     #define XCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                   (0x1<<1) // Write to full STORM input buffer.
63464     #define XCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                             1
63465     #define XCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                  (0x1<<2) // Read from empty  STORM input buffer.
63466     #define XCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                            2
63467     #define XCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR                                                    (0x1<<3) // Write to full MSDM input buffer.
63468     #define XCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT                                              3
63469     #define XCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR                                                   (0x1<<4) // Read from empty MSDM input buffer.
63470     #define XCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR_SHIFT                                             4
63471     #define XCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR                                                    (0x1<<5) // Write to full XSDM input buffer.
63472     #define XCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR_SHIFT                                              5
63473     #define XCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR                                                   (0x1<<6) // Read from empty XSDM input buffer.
63474     #define XCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR_SHIFT                                             6
63475     #define XCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR                                                    (0x1<<7) // Write to full YSDM input buffer.
63476     #define XCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT                                              7
63477     #define XCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR                                                   (0x1<<8) // Read from empty  YSDM input buffer.
63478     #define XCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT                                             8
63479     #define XCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR                                                    (0x1<<9) // Write to full USDM input buffer.
63480     #define XCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_SHIFT                                              9
63481     #define XCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR                                                   (0x1<<10) // Read from empty USDM input buffer.
63482     #define XCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_SHIFT                                             10
63483     #define XCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR                                                    (0x1<<11) // Write to full Msem input buffer.
63484     #define XCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_SHIFT                                              11
63485     #define XCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR                                                   (0x1<<12) // Read from empty  Msem input buffer.
63486     #define XCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_SHIFT                                             12
63487     #define XCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR                                                    (0x1<<13) // Write to full Usem input buffer.
63488     #define XCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_SHIFT                                              13
63489     #define XCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR                                                   (0x1<<14) // Read from empty Usem input buffer.
63490     #define XCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_SHIFT                                             14
63491     #define XCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR                                                    (0x1<<15) // Write to full Ysem input buffer.
63492     #define XCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_SHIFT                                              15
63493 #define XCM_REG_INT_STS_CLR_0                                                                        0x100018cUL //Access:RC   DataWidth:0x10  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63494     #define XCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
63495     #define XCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
63496     #define XCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                  (0x1<<1) // Write to full STORM input buffer.
63497     #define XCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                            1
63498     #define XCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                 (0x1<<2) // Read from empty  STORM input buffer.
63499     #define XCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                           2
63500     #define XCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR                                                   (0x1<<3) // Write to full MSDM input buffer.
63501     #define XCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT                                             3
63502     #define XCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR                                                  (0x1<<4) // Read from empty MSDM input buffer.
63503     #define XCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR_SHIFT                                            4
63504     #define XCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR                                                   (0x1<<5) // Write to full XSDM input buffer.
63505     #define XCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR_SHIFT                                             5
63506     #define XCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR                                                  (0x1<<6) // Read from empty XSDM input buffer.
63507     #define XCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR_SHIFT                                            6
63508     #define XCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR                                                   (0x1<<7) // Write to full YSDM input buffer.
63509     #define XCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT                                             7
63510     #define XCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR                                                  (0x1<<8) // Read from empty  YSDM input buffer.
63511     #define XCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT                                            8
63512     #define XCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR                                                   (0x1<<9) // Write to full USDM input buffer.
63513     #define XCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_SHIFT                                             9
63514     #define XCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR                                                  (0x1<<10) // Read from empty USDM input buffer.
63515     #define XCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_SHIFT                                            10
63516     #define XCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR                                                   (0x1<<11) // Write to full Msem input buffer.
63517     #define XCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_SHIFT                                             11
63518     #define XCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR                                                  (0x1<<12) // Read from empty  Msem input buffer.
63519     #define XCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_SHIFT                                            12
63520     #define XCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR                                                   (0x1<<13) // Write to full Usem input buffer.
63521     #define XCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_SHIFT                                             13
63522     #define XCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR                                                  (0x1<<14) // Read from empty Usem input buffer.
63523     #define XCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_SHIFT                                            14
63524     #define XCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR                                                   (0x1<<15) // Write to full Ysem input buffer.
63525     #define XCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_SHIFT                                             15
63526 #define XCM_REG_INT_STS_1                                                                            0x1000190UL //Access:R    DataWidth:0x19  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63527     #define XCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR                                                      (0x1<<0) // Read from empty  Ysem input buffer.
63528     #define XCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR_SHIFT                                                0
63529     #define XCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR                                                       (0x1<<1) // Write to full Dorq input buffer.
63530     #define XCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_SHIFT                                                 1
63531     #define XCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR                                                      (0x1<<2) // Read from empty  Dorq input buffer.
63532     #define XCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_SHIFT                                                2
63533     #define XCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                        (0x1<<3) // Write to full Pbf input buffer.
63534     #define XCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                  3
63535     #define XCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                       (0x1<<4) // Read from empty Pbf input buffer.
63536     #define XCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                 4
63537     #define XCM_REG_INT_STS_1_IS_TM_OVFL_ERR                                                         (0x1<<5) // Write to full TM input buffer.
63538     #define XCM_REG_INT_STS_1_IS_TM_OVFL_ERR_SHIFT                                                   5
63539     #define XCM_REG_INT_STS_1_IS_TM_UNDER_ERR                                                        (0x1<<6) // Read from empty TM input buffer.
63540     #define XCM_REG_INT_STS_1_IS_TM_UNDER_ERR_SHIFT                                                  6
63541     #define XCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                       (0x1<<7) // Write to full QM input buffer.
63542     #define XCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                 7
63543     #define XCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                      (0x1<<8) // Read from empty QM input buffer.
63544     #define XCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                8
63545     #define XCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                       (0x1<<9) // Write to full QM input buffer.
63546     #define XCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                 9
63547     #define XCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                      (0x1<<10) // Read from empty QM input buffer.
63548     #define XCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                10
63549     #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                       (0x1<<11) // Write to full GRC input buffer bits [31:0].
63550     #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                 11
63551     #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                      (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
63552     #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                12
63553     #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                       (0x1<<13) // Write to full GRC input buffer bits [63:32].
63554     #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                 13
63555     #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                      (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
63556     #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                14
63557     #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                       (0x1<<15) // Write to full GRC input buffer bits [95:64].
63558     #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                 15
63559     #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                      (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
63560     #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                16
63561     #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                       (0x1<<17) // Write to full GRC input buffer bits [127:96].
63562     #define XCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                 17
63563     #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                      (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
63564     #define XCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                18
63565     #define XCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                       (0x1<<19) // In-process Table overflow.
63566     #define XCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                 19
63567     #define XCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL                                                  (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
63568     #define XCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                            20
63569     #define XCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL                                                   (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
63570     #define XCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                             21
63571     #define XCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                   (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
63572     #define XCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                             22
63573     #define XCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                    (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
63574     #define XCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                              23
63575     #define XCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                  (0x1<<24) // Input message first descriptor fields violation.
63576     #define XCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                            24
63577 #define XCM_REG_INT_MASK_1                                                                           0x1000194UL //Access:RW   DataWidth:0x19  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63578     #define XCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
63579     #define XCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR_SHIFT                                               0
63580     #define XCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
63581     #define XCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_SHIFT                                                1
63582     #define XCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
63583     #define XCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_SHIFT                                               2
63584     #define XCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
63585     #define XCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                 3
63586     #define XCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
63587     #define XCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                4
63588     #define XCM_REG_INT_MASK_1_IS_TM_OVFL_ERR                                                        (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
63589     #define XCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_SHIFT                                                  5
63590     #define XCM_REG_INT_MASK_1_IS_TM_UNDER_ERR                                                       (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
63591     #define XCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_SHIFT                                                 6
63592     #define XCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
63593     #define XCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                7
63594     #define XCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
63595     #define XCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                               8
63596     #define XCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
63597     #define XCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                9
63598     #define XCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
63599     #define XCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                               10
63600     #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
63601     #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                11
63602     #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
63603     #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                               12
63604     #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                      (0x1<<13) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
63605     #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                13
63606     #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                     (0x1<<14) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
63607     #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                               14
63608     #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                      (0x1<<15) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
63609     #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                15
63610     #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                     (0x1<<16) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
63611     #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                               16
63612     #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                      (0x1<<17) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
63613     #define XCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                17
63614     #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                     (0x1<<18) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
63615     #define XCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                               18
63616     #define XCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                      (0x1<<19) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
63617     #define XCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                19
63618     #define XCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL                                                 (0x1<<20) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
63619     #define XCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                           20
63620     #define XCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
63621     #define XCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                            21
63622     #define XCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                  (0x1<<22) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
63623     #define XCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                            22
63624     #define XCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                   (0x1<<23) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
63625     #define XCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                             23
63626     #define XCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                 (0x1<<24) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
63627     #define XCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                           24
63628 #define XCM_REG_INT_STS_WR_1                                                                         0x1000198UL //Access:WR   DataWidth:0x19  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63629     #define XCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR                                                   (0x1<<0) // Read from empty  Ysem input buffer.
63630     #define XCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR_SHIFT                                             0
63631     #define XCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR                                                    (0x1<<1) // Write to full Dorq input buffer.
63632     #define XCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_SHIFT                                              1
63633     #define XCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR                                                   (0x1<<2) // Read from empty  Dorq input buffer.
63634     #define XCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_SHIFT                                             2
63635     #define XCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                     (0x1<<3) // Write to full Pbf input buffer.
63636     #define XCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                               3
63637     #define XCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                    (0x1<<4) // Read from empty Pbf input buffer.
63638     #define XCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                              4
63639     #define XCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR                                                      (0x1<<5) // Write to full TM input buffer.
63640     #define XCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_SHIFT                                                5
63641     #define XCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR                                                     (0x1<<6) // Read from empty TM input buffer.
63642     #define XCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_SHIFT                                               6
63643     #define XCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                    (0x1<<7) // Write to full QM input buffer.
63644     #define XCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                              7
63645     #define XCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                   (0x1<<8) // Read from empty QM input buffer.
63646     #define XCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                             8
63647     #define XCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                    (0x1<<9) // Write to full QM input buffer.
63648     #define XCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                              9
63649     #define XCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                   (0x1<<10) // Read from empty QM input buffer.
63650     #define XCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                             10
63651     #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                    (0x1<<11) // Write to full GRC input buffer bits [31:0].
63652     #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                              11
63653     #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                   (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
63654     #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                             12
63655     #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                    (0x1<<13) // Write to full GRC input buffer bits [63:32].
63656     #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                              13
63657     #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                   (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
63658     #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                             14
63659     #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                    (0x1<<15) // Write to full GRC input buffer bits [95:64].
63660     #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                              15
63661     #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                   (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
63662     #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                             16
63663     #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                    (0x1<<17) // Write to full GRC input buffer bits [127:96].
63664     #define XCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                              17
63665     #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                   (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
63666     #define XCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                             18
63667     #define XCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                    (0x1<<19) // In-process Table overflow.
63668     #define XCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                              19
63669     #define XCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL                                               (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
63670     #define XCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                         20
63671     #define XCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL                                                (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
63672     #define XCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                          21
63673     #define XCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
63674     #define XCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                          22
63675     #define XCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                 (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
63676     #define XCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                           23
63677     #define XCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                               (0x1<<24) // Input message first descriptor fields violation.
63678     #define XCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                         24
63679 #define XCM_REG_INT_STS_CLR_1                                                                        0x100019cUL //Access:RC   DataWidth:0x19  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63680     #define XCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR                                                  (0x1<<0) // Read from empty  Ysem input buffer.
63681     #define XCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR_SHIFT                                            0
63682     #define XCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR                                                   (0x1<<1) // Write to full Dorq input buffer.
63683     #define XCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_SHIFT                                             1
63684     #define XCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR                                                  (0x1<<2) // Read from empty  Dorq input buffer.
63685     #define XCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_SHIFT                                            2
63686     #define XCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                    (0x1<<3) // Write to full Pbf input buffer.
63687     #define XCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                              3
63688     #define XCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                   (0x1<<4) // Read from empty Pbf input buffer.
63689     #define XCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                             4
63690     #define XCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR                                                     (0x1<<5) // Write to full TM input buffer.
63691     #define XCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_SHIFT                                               5
63692     #define XCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR                                                    (0x1<<6) // Read from empty TM input buffer.
63693     #define XCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_SHIFT                                              6
63694     #define XCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                   (0x1<<7) // Write to full QM input buffer.
63695     #define XCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                             7
63696     #define XCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                  (0x1<<8) // Read from empty QM input buffer.
63697     #define XCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                            8
63698     #define XCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                   (0x1<<9) // Write to full QM input buffer.
63699     #define XCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                             9
63700     #define XCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                  (0x1<<10) // Read from empty QM input buffer.
63701     #define XCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                            10
63702     #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                   (0x1<<11) // Write to full GRC input buffer bits [31:0].
63703     #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                             11
63704     #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                  (0x1<<12) // Read from empty  GRC input buffer bits [31:0].
63705     #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                            12
63706     #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                   (0x1<<13) // Write to full GRC input buffer bits [63:32].
63707     #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                             13
63708     #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                  (0x1<<14) // Read from empty  GRC input buffer bits [63:32].
63709     #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                            14
63710     #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                   (0x1<<15) // Write to full GRC input buffer bits [95:64].
63711     #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                             15
63712     #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                  (0x1<<16) // Read from empty  GRC input buffer bits [95:64].
63713     #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                            16
63714     #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                   (0x1<<17) // Write to full GRC input buffer bits [127:96].
63715     #define XCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                             17
63716     #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                  (0x1<<18) // Read from empty  GRC input buffer bits [127:96].
63717     #define XCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                            18
63718     #define XCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                   (0x1<<19) // In-process Table overflow.
63719     #define XCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                             19
63720     #define XCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL                                              (0x1<<20) // Message Processor Aggregation Connection Data buffer overflow.
63721     #define XCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                        20
63722     #define XCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL                                               (0x1<<21) // Message Processor Aggregation Connection Command buffer overflow.
63723     #define XCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                         21
63724     #define XCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                               (0x1<<22) // Message Processor Storm Connection Data buffer overflow.
63725     #define XCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                         22
63726     #define XCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                (0x1<<23) // Message Processor Storm Connection Command buffer overflow.
63727     #define XCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                          23
63728     #define XCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                              (0x1<<24) // Input message first descriptor fields violation.
63729     #define XCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                        24
63730 #define XCM_REG_INT_STS_2                                                                            0x10001a0UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
63731     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER                                           (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
63732     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER_SHIFT                                     0
63733     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL                                            (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
63734     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT                                      1
63735     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_UNDER                                             (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
63736     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_UNDER_SHIFT                                       2
63737     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_OVFL                                              (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
63738     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT                                        3
63739     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_UNDER                                                (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
63740     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_UNDER_SHIFT                                          4
63741     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_OVFL                                                 (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
63742     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_RBC_OVFL_SHIFT                                           5
63743     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_DROP_UNDER                                               (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
63744     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_DROP_UNDER_SHIFT                                         6
63745     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_ILLEG_PQNUM                                              (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
63746     #define XCM_REG_INT_STS_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT                                        7
63747 #define XCM_REG_INT_MASK_2                                                                           0x10001a4UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
63748     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER                                          (0x1<<0) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_MSG_PRCS_UNDER .
63749     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER_SHIFT                                    0
63750     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL                                           (0x1<<1) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_MSG_PRCS_OVFL .
63751     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT                                     1
63752     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_UNDER                                            (0x1<<2) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_EXT_LD_UNDER .
63753     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_UNDER_SHIFT                                      2
63754     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_OVFL                                             (0x1<<3) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_EXT_LD_OVFL .
63755     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT                                       3
63756     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_UNDER                                               (0x1<<4) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_RBC_UNDER .
63757     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_UNDER_SHIFT                                         4
63758     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_OVFL                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_RBC_OVFL .
63759     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_RBC_OVFL_SHIFT                                          5
63760     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_DROP_UNDER                                              (0x1<<6) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_DROP_UNDER .
63761     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_DROP_UNDER_SHIFT                                        6
63762     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_ILLEG_PQNUM                                             (0x1<<7) // This bit masks, when set, the Interrupt bit: XCM_REG_INT_STS_2.QM_ACT_ST_CNT_ILLEG_PQNUM .
63763     #define XCM_REG_INT_MASK_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT                                       7
63764 #define XCM_REG_INT_STS_WR_2                                                                         0x10001a8UL //Access:WR   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
63765     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER                                        (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
63766     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER_SHIFT                                  0
63767     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL                                         (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
63768     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT                                   1
63769     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_UNDER                                          (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
63770     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_UNDER_SHIFT                                    2
63771     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_OVFL                                           (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
63772     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT                                     3
63773     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_UNDER                                             (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
63774     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_UNDER_SHIFT                                       4
63775     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_OVFL                                              (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
63776     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_RBC_OVFL_SHIFT                                        5
63777     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_DROP_UNDER                                            (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
63778     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_DROP_UNDER_SHIFT                                      6
63779     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_ILLEG_PQNUM                                           (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
63780     #define XCM_REG_INT_STS_WR_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT                                     7
63781 #define XCM_REG_INT_STS_CLR_2                                                                        0x10001acUL //Access:RC   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
63782     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER                                       (0x1<<0) // QM Active State Counter underrun interrupt in case of message processing. Can happen in case of erroneous ExistInQm clears or QM drops.
63783     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_UNDER_SHIFT                                 0
63784     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL                                        (0x1<<1) // QM Active State Counter overflow interrupt in case of message processing. Can happen in case of erroneous QM registrations.
63785     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_MSG_PRCS_OVFL_SHIFT                                  1
63786     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_UNDER                                         (0x1<<2) // QM Active State Counter underrun interrupt in case of External load. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
63787     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_UNDER_SHIFT                                   2
63788     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_OVFL                                          (0x1<<3) // QM Active State Counter overflow interrupt in case of External load. Can happen in case of erroneous increment.
63789     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_EXT_LD_OVFL_SHIFT                                    3
63790     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_UNDER                                            (0x1<<4) // QM Active State Counter underrun interrupt in case of RBC access. Can happen in case of erroneous decrement or erroneous ExistInQm clears or QM drops.
63791     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_UNDER_SHIFT                                      4
63792     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_OVFL                                             (0x1<<5) // QM Active State Counter overflow interrupt in case of RBC access. Can happen in case of erroneous increment.
63793     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_RBC_OVFL_SHIFT                                       5
63794     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_DROP_UNDER                                           (0x1<<6) // QM Active State Counter underrun interrupt in case of drop. Can happen in case of erroneous decrement.
63795     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_DROP_UNDER_SHIFT                                     6
63796     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_ILLEG_PQNUM                                          (0x1<<7) // Access to illegal PQ number in QM Active State Counter (more than 447).
63797     #define XCM_REG_INT_STS_CLR_2_QM_ACT_ST_CNT_ILLEG_PQNUM_SHIFT                                    7
63798 #define XCM_REG_PRTY_MASK_H_0                                                                        0x1000204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
63799     #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_ECC_RF_INT .
63800     #define XCM_REG_PRTY_MASK_H_0_MEM036_I_ECC_RF_INT_SHIFT                                          0
63801     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT                                              (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
63802     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT                                        1
63803     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
63804     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_SHIFT                                        2
63805     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_2_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_2_RF_INT .
63806     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_2_RF_INT_SHIFT                                        3
63807     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_3_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_3_RF_INT .
63808     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_3_RF_INT_SHIFT                                        4
63809     #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM004_I_ECC_RF_INT .
63810     #define XCM_REG_PRTY_MASK_H_0_MEM004_I_ECC_RF_INT_SHIFT                                          5
63811     #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT                                              (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_0_RF_INT .
63812     #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_0_RF_INT_SHIFT                                        6
63813     #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_1_RF_INT .
63814     #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_1_RF_INT_SHIFT                                        7
63815     #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_BB_A0                                          (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_ECC_RF_INT .
63816     #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_BB_A0_SHIFT                                    0
63817     #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_K2                                             (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_ECC_RF_INT .
63818     #define XCM_REG_PRTY_MASK_H_0_MEM034_I_ECC_RF_INT_K2_SHIFT                                       8
63819     #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
63820     #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_A0_SHIFT                                      17
63821     #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
63822     #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_BB_B0_SHIFT                                      9
63823     #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
63824     #define XCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_K2_SHIFT                                         9
63825     #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
63826     #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_A0_SHIFT                                      9
63827     #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
63828     #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_B0_SHIFT                                      10
63829     #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
63830     #define XCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_SHIFT                                         10
63831     #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
63832     #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_A0_SHIFT                                      12
63833     #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
63834     #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_B0_SHIFT                                      11
63835     #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
63836     #define XCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT                                         11
63837     #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0                                            (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
63838     #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0_SHIFT                                      27
63839     #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
63840     #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0_SHIFT                                      14
63841     #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
63842     #define XCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                         12
63843     #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
63844     #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_A0_SHIFT                                      16
63845     #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
63846     #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_B0_SHIFT                                      12
63847     #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
63848     #define XCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                         13
63849     #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
63850     #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0_SHIFT                                      14
63851     #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
63852     #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0_SHIFT                                      13
63853     #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
63854     #define XCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                         14
63855     #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0                                            (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
63856     #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_BB_B0_SHIFT                                      27
63857     #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
63858     #define XCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_K2_SHIFT                                         15
63859     #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
63860     #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      18
63861     #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
63862     #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      15
63863     #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
63864     #define XCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                         16
63865     #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_A0                                            (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
63866     #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_A0_SHIFT                                      10
63867     #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
63868     #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_BB_B0_SHIFT                                      16
63869     #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
63870     #define XCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_K2_SHIFT                                         17
63871     #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
63872     #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0_SHIFT                                      13
63873     #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
63874     #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0_SHIFT                                      17
63875     #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
63876     #define XCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                         18
63877     #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
63878     #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                      19
63879     #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0                                            (0x1<<18) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
63880     #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                      18
63881     #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
63882     #define XCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                         19
63883     #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
63884     #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                      20
63885     #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<19) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
63886     #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      19
63887     #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                               (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
63888     #define XCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                         20
63889     #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
63890     #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      21
63891     #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<20) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
63892     #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      20
63893     #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                               (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
63894     #define XCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                         21
63895     #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
63896     #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_A0_SHIFT                                      11
63897     #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_B0                                            (0x1<<21) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
63898     #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_B0_SHIFT                                      21
63899     #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                               (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
63900     #define XCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                         22
63901     #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM039_I_MEM_PRTY .
63902     #define XCM_REG_PRTY_MASK_H_0_MEM039_I_MEM_PRTY_SHIFT                                            23
63903     #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_B0                                            (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
63904     #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_BB_B0_SHIFT                                      22
63905     #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2                                               (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM038_I_MEM_PRTY .
63906     #define XCM_REG_PRTY_MASK_H_0_MEM038_I_MEM_PRTY_K2_SHIFT                                         24
63907     #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_A0                                            (0x1<<22) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
63908     #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_A0_SHIFT                                      22
63909     #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_B0                                            (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
63910     #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_BB_B0_SHIFT                                      23
63911     #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2                                               (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM037_I_MEM_PRTY .
63912     #define XCM_REG_PRTY_MASK_H_0_MEM037_I_MEM_PRTY_K2_SHIFT                                         25
63913     #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0                                            (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
63914     #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0_SHIFT                                      28
63915     #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0                                            (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
63916     #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0_SHIFT                                      25
63917     #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                               (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
63918     #define XCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                         26
63919     #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
63920     #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_BB_A0_SHIFT                                      24
63921     #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2                                               (0x1<<27) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_MEM_PRTY .
63922     #define XCM_REG_PRTY_MASK_H_0_MEM035_I_MEM_PRTY_K2_SHIFT                                         27
63923     #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
63924     #define XCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_SHIFT                                            28
63925     #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                            (0x1<<28) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
63926     #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                      28
63927     #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                               (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
63928     #define XCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                         29
63929     #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0                                            (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
63930     #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0_SHIFT                                      30
63931     #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0                                            (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
63932     #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0_SHIFT                                      29
63933     #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                               (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
63934     #define XCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                         30
63935     #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM035_I_ECC_RF_INT .
63936     #define XCM_REG_PRTY_MASK_H_0_MEM035_I_ECC_RF_INT_SHIFT                                          0
63937     #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT                                              (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_0_RF_INT .
63938     #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_0_RF_INT_SHIFT                                        6
63939     #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_1_RF_INT .
63940     #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_1_RF_INT_SHIFT                                        7
63941     #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT                                                (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_ECC_RF_INT .
63942     #define XCM_REG_PRTY_MASK_H_0_MEM033_I_ECC_RF_INT_SHIFT                                          8
63943     #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_A0                                            (0x1<<23) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
63944     #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_A0_SHIFT                                      23
63945     #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_B0                                            (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
63946     #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_BB_B0_SHIFT                                      24
63947     #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_K2                                               (0x1<<24) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM036_I_MEM_PRTY .
63948     #define XCM_REG_PRTY_MASK_H_0_MEM036_I_MEM_PRTY_K2_SHIFT                                         24
63949     #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM034_I_MEM_PRTY .
63950     #define XCM_REG_PRTY_MASK_H_0_MEM034_I_MEM_PRTY_SHIFT                                            26
63951     #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0                                            (0x1<<15) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
63952     #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                      15
63953     #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0                                            (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
63954     #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                      30
63955     #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                               (0x1<<30) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
63956     #define XCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                         30
63957     #define XCM_REG_PRTY_MASK_H_0_MEM002_I_ECC_0_RF_INT                                              (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM002_I_ECC_0_RF_INT .
63958     #define XCM_REG_PRTY_MASK_H_0_MEM002_I_ECC_0_RF_INT_SHIFT                                        1
63959     #define XCM_REG_PRTY_MASK_H_0_MEM002_I_ECC_1_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM002_I_ECC_1_RF_INT .
63960     #define XCM_REG_PRTY_MASK_H_0_MEM002_I_ECC_1_RF_INT_SHIFT                                        2
63961     #define XCM_REG_PRTY_MASK_H_0_MEM002_I_ECC_2_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM002_I_ECC_2_RF_INT .
63962     #define XCM_REG_PRTY_MASK_H_0_MEM002_I_ECC_2_RF_INT_SHIFT                                        3
63963     #define XCM_REG_PRTY_MASK_H_0_MEM002_I_ECC_3_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM002_I_ECC_3_RF_INT .
63964     #define XCM_REG_PRTY_MASK_H_0_MEM002_I_ECC_3_RF_INT_SHIFT                                        4
63965     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
63966     #define XCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT                                          5
63967     #define XCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_0_RF_INT                                              (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM031_I_ECC_0_RF_INT .
63968     #define XCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_0_RF_INT_SHIFT                                        6
63969     #define XCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_1_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM031_I_ECC_1_RF_INT .
63970     #define XCM_REG_PRTY_MASK_H_0_MEM031_I_ECC_1_RF_INT_SHIFT                                        7
63971     #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_RF_INT                                                (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM032_I_ECC_RF_INT .
63972     #define XCM_REG_PRTY_MASK_H_0_MEM032_I_ECC_RF_INT_SHIFT                                          8
63973     #define XCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
63974     #define XCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            25
63975     #define XCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
63976     #define XCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_SHIFT                                            26
63977     #define XCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
63978     #define XCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_SHIFT                                            29
63979 #define XCM_REG_PRTY_MASK_H_1                                                                        0x1000214UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
63980     #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM016_I_MEM_PRTY .
63981     #define XCM_REG_PRTY_MASK_H_1_MEM016_I_MEM_PRTY_SHIFT                                            0
63982     #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
63983     #define XCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_SHIFT                                            1
63984     #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_A0                                            (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
63985     #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_A0_SHIFT                                      2
63986     #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
63987     #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_BB_B0_SHIFT                                      1
63988     #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2                                               (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
63989     #define XCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_K2_SHIFT                                         2
63990     #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
63991     #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                      3
63992     #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_B0                                            (0x1<<2) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
63993     #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                      2
63994     #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2                                               (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
63995     #define XCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_K2_SHIFT                                         3
63996     #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
63997     #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_A0_SHIFT                                      4
63998     #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
63999     #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_BB_B0_SHIFT                                      3
64000     #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2                                               (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
64001     #define XCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_K2_SHIFT                                         4
64002     #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_A0                                            (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
64003     #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_A0_SHIFT                                      5
64004     #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
64005     #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_B0_SHIFT                                      4
64006     #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
64007     #define XCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_SHIFT                                         5
64008     #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_A0                                            (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
64009     #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                      6
64010     #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_B0                                            (0x1<<5) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
64011     #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                      5
64012     #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
64013     #define XCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_K2_SHIFT                                         6
64014     #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_A0                                            (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
64015     #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_A0_SHIFT                                      7
64016     #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_B0                                            (0x1<<6) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
64017     #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_BB_B0_SHIFT                                      6
64018     #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
64019     #define XCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_K2_SHIFT                                         7
64020     #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
64021     #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_A0_SHIFT                                      8
64022     #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
64023     #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_BB_B0_SHIFT                                      7
64024     #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2                                               (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM013_I_MEM_PRTY .
64025     #define XCM_REG_PRTY_MASK_H_1_MEM013_I_MEM_PRTY_K2_SHIFT                                         8
64026     #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_B0                                            (0x1<<8) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
64027     #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_BB_B0_SHIFT                                      8
64028     #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM014_I_MEM_PRTY .
64029     #define XCM_REG_PRTY_MASK_H_1_MEM014_I_MEM_PRTY_K2_SHIFT                                         9
64030     #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
64031     #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_A0_SHIFT                                      9
64032     #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
64033     #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                      9
64034     #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
64035     #define XCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                         10
64036     #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
64037     #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                      10
64038     #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
64039     #define XCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                         11
64040     #define XCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
64041     #define XCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_SHIFT                                            0
64042     #define XCM_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
64043     #define XCM_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_SHIFT                                            0
64044     #define XCM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM006_I_MEM_PRTY .
64045     #define XCM_REG_PRTY_MASK_H_1_MEM006_I_MEM_PRTY_SHIFT                                            1
64046     #define XCM_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: XCM_REG_PRTY_STS_H_1.MEM038_I_MEM_PRTY .
64047     #define XCM_REG_PRTY_MASK_H_1_MEM038_I_MEM_PRTY_SHIFT                                            10
64048 #define XCM_REG_MEM_ECC_EVENTS                                                                       0x100022cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
64049 #define XCM_REG_MEM026_I_MEM_DFT_K2                                                                  0x1000238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_storm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64050 #define XCM_REG_MEM022_I_MEM_DFT_K2                                                                  0x100023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_msdm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64051 #define XCM_REG_MEM023_I_MEM_DFT_K2                                                                  0x1000240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_msem_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64052 #define XCM_REG_MEM028_I_MEM_DFT_K2                                                                  0x1000244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_usem_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64053 #define XCM_REG_MEM030_I_MEM_DFT_K2                                                                  0x1000248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_ysem_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64054 #define XCM_REG_MEM024_I_MEM_DFT_K2                                                                  0x100024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_pbf_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64055 #define XCM_REG_MEM027_I_MEM_DFT_K2                                                                  0x1000250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_usdm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64056 #define XCM_REG_MEM018_I_MEM_DFT_K2                                                                  0x1000254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_grc0_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64057 #define XCM_REG_MEM019_I_MEM_DFT_K2                                                                  0x1000258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_grc1_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64058 #define XCM_REG_MEM020_I_MEM_DFT_K2                                                                  0x100025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_grc2_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64059 #define XCM_REG_MEM021_I_MEM_DFT_K2                                                                  0x1000260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_is_grc3_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64060 #define XCM_REG_MEM036_I_MEM_DFT_K2                                                                  0x1000264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_xx_msg_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64061 #define XCM_REG_MEM039_I_MEM_DFT_K2                                                                  0x1000268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_xx_pref_dir.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64062 #define XCM_REG_MEM038_I_MEM_DFT_K2                                                                  0x100026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_xx_pref_byp.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64063 #define XCM_REG_MEM037_I_MEM_DFT_K2                                                                  0x1000270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_xx_pref_aggst.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64064 #define XCM_REG_MEM005_I_MEM_DFT_K2                                                                  0x1000274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_agg_con_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64065 #define XCM_REG_MEM003_I_MEM_DFT_K2                                                                  0x1000278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_agg_con_ctx_0_7.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64066 #define XCM_REG_MEM004_I_MEM_DFT_K2                                                                  0x100027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_agg_con_ctx_8.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64067 #define XCM_REG_MEM035_I_MEM_DFT_K2                                                                  0x1000280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_sm_con_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64068 #define XCM_REG_MEM033_I_MEM_DFT_K2                                                                  0x1000284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_sm_con_ctx_0_13.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64069 #define XCM_REG_MEM034_I_MEM_DFT_K2                                                                  0x1000288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_sm_con_ctx_14.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64070 #define XCM_REG_MEM031_I_MEM_DFT_K2                                                                  0x100028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_prcs_trans.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64071 #define XCM_REG_MEM006_I_MEM_DFT_K2                                                                  0x1000290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_in_prcs_msgin.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64072 #define XCM_REG_MEM015_I_MEM_DFT_K2                                                                  0x1000294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_in_prcs_qmcon.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64073 #define XCM_REG_MEM032_I_MEM_DFT_K2                                                                  0x1000298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.i_qm_act_st_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64074 #define XCM_REG_MEM001_I_MEM_DFT_K2                                                                  0x100029cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.IS_QMPOP_S_BUF_K2_.i_is_qmpop_s_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64075 #define XCM_REG_MEM002_I_MEM_DFT_K2                                                                  0x10002a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xcm.QM_ACT_ST_CNT_K2_.i_qm_act_st_cnt.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64076 #define XCM_REG_IFEN                                                                                 0x1000400UL //Access:RW   DataWidth:0x1   Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
64077 #define XCM_REG_QM_CON_BASE_EVNT_ID_0                                                                0x1000404UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64078 #define XCM_REG_QM_CON_BASE_EVNT_ID_1                                                                0x1000408UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64079 #define XCM_REG_QM_CON_BASE_EVNT_ID_2                                                                0x100040cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64080 #define XCM_REG_QM_CON_BASE_EVNT_ID_3                                                                0x1000410UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64081 #define XCM_REG_QM_CON_BASE_EVNT_ID_4                                                                0x1000414UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64082 #define XCM_REG_QM_CON_BASE_EVNT_ID_5                                                                0x1000418UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64083 #define XCM_REG_QM_CON_BASE_EVNT_ID_6                                                                0x100041cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64084 #define XCM_REG_QM_CON_BASE_EVNT_ID_7                                                                0x1000420UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64085 #define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_0                                                           0x1000424UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64086 #define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_1                                                           0x1000428UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64087 #define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_2                                                           0x100042cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64088 #define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_3                                                           0x1000430UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64089 #define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_4                                                           0x1000434UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64090 #define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_5                                                           0x1000438UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64091 #define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_6                                                           0x100043cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64092 #define XCM_REG_QM_AGG_CON_CTX_PART_SIZE_7                                                           0x1000440UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64093 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_0                                                             0x1000444UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64094 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_1                                                             0x1000448UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64095 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_2                                                             0x100044cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64096 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_3                                                             0x1000450UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64097 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_4                                                             0x1000454UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64098 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_5                                                             0x1000458UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64099 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_6                                                             0x100045cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64100 #define XCM_REG_QM_SM_CON_CTX_LDST_FLG_7                                                             0x1000460UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64101 #define XCM_REG_QM_XXLOCK_CMD_0                                                                      0x1000464UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64102 #define XCM_REG_QM_XXLOCK_CMD_1                                                                      0x1000468UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64103 #define XCM_REG_QM_XXLOCK_CMD_2                                                                      0x100046cUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64104 #define XCM_REG_QM_XXLOCK_CMD_3                                                                      0x1000470UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64105 #define XCM_REG_QM_XXLOCK_CMD_4                                                                      0x1000474UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64106 #define XCM_REG_QM_XXLOCK_CMD_5                                                                      0x1000478UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64107 #define XCM_REG_QM_XXLOCK_CMD_6                                                                      0x100047cUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64108 #define XCM_REG_QM_XXLOCK_CMD_7                                                                      0x1000480UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64109 #define XCM_REG_QM_CON_USE_ST_FLG_0                                                                  0x1000484UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64110 #define XCM_REG_QM_CON_USE_ST_FLG_1                                                                  0x1000488UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64111 #define XCM_REG_QM_CON_USE_ST_FLG_2                                                                  0x100048cUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64112 #define XCM_REG_QM_CON_USE_ST_FLG_3                                                                  0x1000490UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64113 #define XCM_REG_QM_CON_USE_ST_FLG_4                                                                  0x1000494UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64114 #define XCM_REG_QM_CON_USE_ST_FLG_5                                                                  0x1000498UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64115 #define XCM_REG_QM_CON_USE_ST_FLG_6                                                                  0x100049cUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64116 #define XCM_REG_QM_CON_USE_ST_FLG_7                                                                  0x10004a0UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64117 #define XCM_REG_TM_CON_EVNT_ID_0                                                                     0x10004a4UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64118 #define XCM_REG_TM_CON_EVNT_ID_1                                                                     0x10004a8UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64119 #define XCM_REG_TM_CON_EVNT_ID_2                                                                     0x10004acUL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64120 #define XCM_REG_TM_CON_EVNT_ID_3                                                                     0x10004b0UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64121 #define XCM_REG_TM_CON_EVNT_ID_4                                                                     0x10004b4UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64122 #define XCM_REG_TM_CON_EVNT_ID_5                                                                     0x10004b8UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64123 #define XCM_REG_TM_CON_EVNT_ID_6                                                                     0x10004bcUL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64124 #define XCM_REG_TM_CON_EVNT_ID_7                                                                     0x10004c0UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.:  Chips: BB_A0 BB_B0 K2
64125 #define XCM_REG_ERR_EVNT_ID                                                                          0x10004c4UL //Access:RW   DataWidth:0x8   The Event ID in case one of errors is set in QM input message.  Chips: BB_A0 BB_B0 K2
64126 #define XCM_REG_STORM_WEIGHT                                                                         0x1000604UL //Access:RW   DataWidth:0x3   The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64127 #define XCM_REG_MSEM_WEIGHT                                                                          0x1000608UL //Access:RW   DataWidth:0x3   The weight of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64128 #define XCM_REG_USEM_WEIGHT                                                                          0x100060cUL //Access:RW   DataWidth:0x3   The weight of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64129 #define XCM_REG_YSEM_WEIGHT                                                                          0x1000610UL //Access:RW   DataWidth:0x3   The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64130 #define XCM_REG_DORQ_WEIGHT                                                                          0x1000614UL //Access:RW   DataWidth:0x3   The weight of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64131 #define XCM_REG_PBF_WEIGHT                                                                           0x1000618UL //Access:RW   DataWidth:0x3   The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64132 #define XCM_REG_GRC_WEIGHT                                                                           0x100061cUL //Access:RW   DataWidth:0x3   The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64133 #define XCM_REG_MSDM_WEIGHT                                                                          0x1000620UL //Access:RW   DataWidth:0x3   The weight of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64134 #define XCM_REG_XSDM_WEIGHT                                                                          0x1000624UL //Access:RW   DataWidth:0x3   The weight of the XSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64135 #define XCM_REG_YSDM_WEIGHT                                                                          0x1000628UL //Access:RW   DataWidth:0x3   The weight of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64136 #define XCM_REG_USDM_WEIGHT                                                                          0x100062cUL //Access:RW   DataWidth:0x3   The weight of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64137 #define XCM_REG_QM_P_WEIGHT                                                                          0x1000630UL //Access:RW   DataWidth:0x3   The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64138 #define XCM_REG_QM_S_WEIGHT                                                                          0x1000634UL //Access:RW   DataWidth:0x3   The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64139 #define XCM_REG_TM_WEIGHT                                                                            0x1000638UL //Access:RW   DataWidth:0x3   The weight of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64140 #define XCM_REG_IA_GROUP_PR0                                                                         0x100063cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
64141 #define XCM_REG_IA_GROUP_PR1                                                                         0x1000640UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
64142 #define XCM_REG_IA_GROUP_PR2                                                                         0x1000644UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
64143 #define XCM_REG_IA_GROUP_PR3                                                                         0x1000648UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
64144 #define XCM_REG_IA_GROUP_PR4                                                                         0x100064cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
64145 #define XCM_REG_IA_GROUP_PR5                                                                         0x1000650UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
64146 #define XCM_REG_IA_ARB_SP_TIMEOUT                                                                    0x1000654UL //Access:RW   DataWidth:0x8   Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority.  Chips: BB_A0 BB_B0 K2
64147 #define XCM_REG_STORM_FRWRD_MODE                                                                     0x1000658UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64148 #define XCM_REG_MSDM_FRWRD_MODE                                                                      0x100065cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64149 #define XCM_REG_XSDM_FRWRD_MODE                                                                      0x1000660UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64150 #define XCM_REG_YSDM_FRWRD_MODE                                                                      0x1000664UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64151 #define XCM_REG_USDM_FRWRD_MODE                                                                      0x1000668UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64152 #define XCM_REG_MSEM_FRWRD_MODE                                                                      0x100066cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64153 #define XCM_REG_USEM_FRWRD_MODE                                                                      0x1000670UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64154 #define XCM_REG_YSEM_FRWRD_MODE                                                                      0x1000674UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64155 #define XCM_REG_DORQ_FRWRD_MODE                                                                      0x1000678UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64156 #define XCM_REG_PBF_FRWRD_MODE                                                                       0x100067cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
64157 #define XCM_REG_SDM_ERR_HANDLE_EN                                                                    0x1000680UL //Access:RW   DataWidth:0x1   0 - disable error handling in SDM message; 1 - enable error handling in SDM message.  Chips: BB_A0 BB_B0 K2
64158 #define XCM_REG_DIR_BYP_EN                                                                           0x1000684UL //Access:RW   DataWidth:0x1   Direct bypass enable.  Chips: BB_A0 BB_B0 K2
64159 #define XCM_REG_FI_DESC_INPUT_VIOLATE                                                                0x1000688UL //Access:R    DataWidth:0x10  Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: XxBypass message in PCM block;  Chips: BB_A0 BB_B0 K2
64160 #define XCM_REG_IA_AGG_CON_PART_FILL_LVL                                                             0x100068cUL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
64161 #define XCM_REG_IA_SM_CON_PART_FILL_LVL                                                              0x1000690UL //Access:R    DataWidth:0x3   Input Arbiter Storm Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
64162 #define XCM_REG_IA_TRANS_PART_FILL_LVL                                                               0x1000694UL //Access:R    DataWidth:0x3   Input Arbiter Transparent part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
64163 #define XCM_REG_XX_MSG_UP_BND                                                                        0x1000704UL //Access:RW   DataWidth:0x7   The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the siz of Xx protected message CM_REGISTERS_XX_MSG_SIZE_BND.XX_MSG_SIZE_BND  Chips: BB_A0 BB_B0 K2
64164 #define XCM_REG_XX_MSG_SIZE                                                                          0x1000708UL //Access:RW   DataWidth:0x9   The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to even number and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1664 PCM: 0d176 TCM: 0d1408 UCM: 0d1664 XCM: 0d256 YCM: 0d1536  Chips: BB_A0 BB_B0 K2
64165 #define XCM_REG_XX_LCID_CAM_UP_BND                                                                   0x100070cUL //Access:RW   DataWidth:0x5   The maximum number of connections in the XX protection LCID CAM.  Chips: BB_A0 BB_B0 K2
64166 #define XCM_REG_XX_FREE_CNT                                                                          0x1000710UL //Access:R    DataWidth:0x7   Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
64167 #define XCM_REG_XX_LCID_CAM_FILL_LVL                                                                 0x1000714UL //Access:R    DataWidth:0x5   Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.  Chips: BB_A0 BB_B0 K2
64168 #define XCM_REG_XX_LCID_CAM_ST_STAT                                                                  0x1000718UL //Access:RC   DataWidth:0x5   CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.  Chips: BB_A0 BB_B0 K2
64169 #define XCM_REG_XX_IA_GROUP_PR0                                                                      0x100071cUL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
64170 #define XCM_REG_XX_IA_GROUP_PR1                                                                      0x1000720UL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
64171 #define XCM_REG_XX_NON_LOCK_LCID_THR                                                                 0x1000724UL //Access:RW   DataWidth:0x5   Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.  Chips: BB_A0 BB_B0 K2
64172 #define XCM_REG_XX_LOCK_LCID_THR                                                                     0x1000728UL //Access:RW   DataWidth:0x5   Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.  Chips: BB_A0 BB_B0 K2
64173 #define XCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                 0x100072cUL //Access:RW   DataWidth:0x8   Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
64174 #define XCM_REG_XX_FREE_HEAD_PTR                                                                     0x1000730UL //Access:R    DataWidth:0x6   Xx Free Head Pointer.  Chips: BB_A0 BB_B0 K2
64175 #define XCM_REG_XX_FREE_TAIL_PTR                                                                     0x1000734UL //Access:R    DataWidth:0x6   Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
64176 #define XCM_REG_XX_NON_LOCK_CNT                                                                      0x1000738UL //Access:R    DataWidth:0x5   Xx NonLock Counter.  Chips: BB_A0 BB_B0 K2
64177 #define XCM_REG_XX_LOCK_CNT                                                                          0x100073cUL //Access:R    DataWidth:0x5   Xx Lock Counter.  Chips: BB_A0 BB_B0 K2
64178 #define XCM_REG_XX_LCID_ARB_GROUP_PR0                                                                0x1000740UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
64179 #define XCM_REG_XX_LCID_ARB_GROUP_PR1                                                                0x1000744UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
64180 #define XCM_REG_XX_LCID_ARB_GROUP_PR2                                                                0x1000748UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
64181 #define XCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                               0x100074cUL //Access:RW   DataWidth:0x8   Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
64182 #define XCM_REG_XX_FREE_THR_HIGH                                                                     0x1000750UL //Access:RW   DataWidth:0x7   Xx free messages threshold high. Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
64183 #define XCM_REG_XX_FREE_THR_LOW                                                                      0x1000754UL //Access:RW   DataWidth:0x7   Xx free messages threshold low Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
64184 #define XCM_REG_XX_CBYP_TBL_FILL_LVL                                                                 0x1000758UL //Access:R    DataWidth:0x4   Xx Connection Bypass Table fill level (in connections).  Chips: BB_A0 BB_B0 K2
64185 #define XCM_REG_XX_CBYP_TBL_ST_STAT                                                                  0x100075cUL //Access:RC   DataWidth:0x4   Xx Connection Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
64186 #define XCM_REG_XX_CBYP_TBL_UP_BND                                                                   0x1000760UL //Access:RW   DataWidth:0x4   Xx Bypass Table (Connection) maximum fill level.  Chips: BB_A0 BB_B0 K2
64187 #define XCM_REG_XX_BYP_MSG_UP_BND_0                                                                  0x1000764UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
64188 #define XCM_REG_XX_BYP_MSG_UP_BND_1                                                                  0x1000768UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
64189 #define XCM_REG_XX_BYP_MSG_UP_BND_2                                                                  0x100076cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
64190 #define XCM_REG_XX_BYP_MSG_UP_BND_3                                                                  0x1000770UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
64191 #define XCM_REG_XX_BYP_MSG_UP_BND_4                                                                  0x1000774UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
64192 #define XCM_REG_XX_BYP_MSG_UP_BND_5                                                                  0x1000778UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
64193 #define XCM_REG_XX_BYP_MSG_UP_BND_6                                                                  0x100077cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
64194 #define XCM_REG_XX_BYP_MSG_UP_BND_7                                                                  0x1000780UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
64195 #define XCM_REG_XX_BYP_LOCK_MSG_THR                                                                  0x1000784UL //Access:RW   DataWidth:0x6   Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.  Chips: BB_A0 BB_B0 K2
64196 #define XCM_REG_XX_PREF_DIR_FILL_LVL                                                                 0x1000788UL //Access:R    DataWidth:0x3   Xx LCID Arbiter direct prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
64197 #define XCM_REG_XX_PREF_AGGST_FILL_LVL                                                               0x100078cUL //Access:R    DataWidth:0x3   Xx LCID Arbiter aggregation store prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
64198 #define XCM_REG_XX_PREF_BYP_FILL_LVL                                                                 0x1000790UL //Access:R    DataWidth:0x3   Xx LCID Arbiter bypass prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
64199 #define XCM_REG_UNLOCK_MISS                                                                          0x1000794UL //Access:RC   DataWidth:0x1   Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.  Chips: BB_A0 BB_B0 K2
64200 #define XCM_REG_PRCS_AGG_CON_CURR_ST                                                                 0x1000804UL //Access:R    DataWidth:0x4   Aggregation Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
64201 #define XCM_REG_PRCS_SM_CON_CURR_ST                                                                  0x1000808UL //Access:R    DataWidth:0x2   STORM Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
64202 #define XCM_REG_N_SM_CON_CTX_LD_0                                                                    0x100080cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
64203 #define XCM_REG_N_SM_CON_CTX_LD_1                                                                    0x1000810UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
64204 #define XCM_REG_N_SM_CON_CTX_LD_2                                                                    0x1000814UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
64205 #define XCM_REG_N_SM_CON_CTX_LD_3                                                                    0x1000818UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
64206 #define XCM_REG_N_SM_CON_CTX_LD_4                                                                    0x100081cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
64207 #define XCM_REG_N_SM_CON_CTX_LD_5                                                                    0x1000820UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
64208 #define XCM_REG_N_SM_CON_CTX_LD_6                                                                    0x1000824UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
64209 #define XCM_REG_N_SM_CON_CTX_LD_7                                                                    0x1000828UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
64210 #define XCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                             0x100082cUL //Access:R    DataWidth:0x4   Aggregation Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
64211 #define XCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                              0x1000830UL //Access:R    DataWidth:0x5   Storm Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
64212 #define XCM_REG_AGG_CON_FIC_BUF_CRD                                                                  0x1000834UL //Access:RW   DataWidth:0x2   Aggregation Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
64213 #define XCM_REG_SM_CON_FIC_BUF_CRD                                                                   0x1000838UL //Access:RW   DataWidth:0x2   Storm Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
64214 #define XCM_REG_AGG_CON_BUF_CRD_AGG                                                                  0x100083cUL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
64215 #define XCM_REG_AGG_CON_BUF_CRD_AGGST                                                                0x1000840UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
64216 #define XCM_REG_SM_CON_BUF_CRD_AGGST                                                                 0x1000844UL //Access:RW   DataWidth:0x1   Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
64217 #define XCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                              0x1000848UL //Access:RW   DataWidth:0x2   Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
64218 #define XCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                               0x100084cUL //Access:RW   DataWidth:0x2   Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
64219 #define XCM_REG_TRANS_DATA_BUF_CRD_DIR                                                               0x1000850UL //Access:RW   DataWidth:0x2   Transparent data buffer credit (Direct group).  Chips: BB_A0 BB_B0 K2
64220 #define XCM_REG_AGG_CON_CTX_SIZE_0                                                                   0x1000854UL //Access:RW   DataWidth:0x4   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less or 9.  Chips: BB_A0 BB_B0 K2
64221 #define XCM_REG_AGG_CON_CTX_SIZE_1                                                                   0x1000858UL //Access:RW   DataWidth:0x4   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.  Chips: BB_A0 BB_B0 K2
64222 #define XCM_REG_AGG_CON_CTX_SIZE_2                                                                   0x100085cUL //Access:RW   DataWidth:0x4   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.  Chips: BB_A0 BB_B0 K2
64223 #define XCM_REG_AGG_CON_CTX_SIZE_3                                                                   0x1000860UL //Access:RW   DataWidth:0x4   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.  Chips: BB_A0 BB_B0 K2
64224 #define XCM_REG_AGG_CON_CTX_SIZE_4                                                                   0x1000864UL //Access:RW   DataWidth:0x4   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.  Chips: BB_A0 BB_B0 K2
64225 #define XCM_REG_AGG_CON_CTX_SIZE_5                                                                   0x1000868UL //Access:RW   DataWidth:0x4   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.  Chips: BB_A0 BB_B0 K2
64226 #define XCM_REG_AGG_CON_CTX_SIZE_6                                                                   0x100086cUL //Access:RW   DataWidth:0x4   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.  Chips: BB_A0 BB_B0 K2
64227 #define XCM_REG_AGG_CON_CTX_SIZE_7                                                                   0x1000870UL //Access:RW   DataWidth:0x4   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 9. The register values allowed: XCM: 4 REGQ aligned or 9. Other CM: 2 REGQ aligned or 9 aligned whichever is less, or 9.  Chips: BB_A0 BB_B0 K2
64228 #define XCM_REG_CM_CON_REG0_SZ                                                                       0x1000874UL //Access:RW   DataWidth:0x3   The size of AGG Connection context region 0 in REGQ. Is used to determine the number of the AG context REGQ written back; when the Reg1WbFlg isn't set.  Chips: BB_A0 BB_B0 K2
64229 #define XCM_REG_SM_CON_CTX_SIZE                                                                      0x1000878UL //Access:RW   DataWidth:0x5   STORM Connnection context per LCID size (REGQ). Default context size of 15 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 24. Maximum number of LCIDs allowed at maximum context size per LCID is 200. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(15/2))/(24/2)).  Chips: BB_A0 BB_B0 K2
64230 #define XCM_REG_CON_PHY_Q3                                                                           0x1000904UL //Access:RW   DataWidth:0xa   [9]: PQ Type (0-Other PQ; 1-TX PQ); if bit[9]=0; then [8:6] reserved; [5:0] Physical queue connection number (queue number 3); if bit[9]=1; then [8:0] Physical queue connection number (queue number 3).  Chips: BB_A0 BB_B0 K2
64231 #define XCM_REG_AGG_CON_CF0_Q                                                                        0x1000908UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64232 #define XCM_REG_AGG_CON_CF1_Q                                                                        0x100090cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64233 #define XCM_REG_AGG_CON_CF2_Q                                                                        0x1000910UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64234 #define XCM_REG_AGG_CON_CF3_Q                                                                        0x1000914UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64235 #define XCM_REG_AGG_CON_CF4_Q                                                                        0x1000918UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64236 #define XCM_REG_AGG_CON_CF5_Q                                                                        0x100091cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64237 #define XCM_REG_AGG_CON_CF6_Q                                                                        0x1000920UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64238 #define XCM_REG_AGG_CON_CF7_Q                                                                        0x1000924UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64239 #define XCM_REG_AGG_CON_CF8_Q                                                                        0x1000928UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64240 #define XCM_REG_AGG_CON_CF9_Q                                                                        0x100092cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64241 #define XCM_REG_AGG_CON_CF10_Q                                                                       0x1000930UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64242 #define XCM_REG_AGG_CON_CF11_Q                                                                       0x1000934UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64243 #define XCM_REG_AGG_CON_CF12_Q                                                                       0x1000938UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64244 #define XCM_REG_AGG_CON_CF13_Q                                                                       0x100093cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64245 #define XCM_REG_AGG_CON_CF14_Q                                                                       0x1000940UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64246 #define XCM_REG_AGG_CON_CF15_Q                                                                       0x1000944UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64247 #define XCM_REG_AGG_CON_CF16_Q                                                                       0x1000948UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64248 #define XCM_REG_AGG_CON_CF17_Q                                                                       0x100094cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64249 #define XCM_REG_AGG_CON_CF18_Q                                                                       0x1000950UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).:  Chips: BB_A0 BB_B0 K2
64250 #define XCM_REG_AGG_CON_CF19_Q                                                                       0x1000954UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64251 #define XCM_REG_AGG_CON_CF20_Q                                                                       0x1000958UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64252 #define XCM_REG_AGG_CON_CF21_Q                                                                       0x100095cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64253 #define XCM_REG_AGG_CON_CF22_Q                                                                       0x1000960UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64254 #define XCM_REG_AGG_CON_CF23_Q                                                                       0x1000964UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64255 #define XCM_REG_AGG_CON_RULE0_Q                                                                      0x1000968UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64256 #define XCM_REG_AGG_CON_RULE1_Q                                                                      0x100096cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64257 #define XCM_REG_AGG_CON_RULE2_Q                                                                      0x1000970UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64258 #define XCM_REG_AGG_CON_RULE3_Q                                                                      0x1000974UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64259 #define XCM_REG_AGG_CON_RULE4_Q                                                                      0x1000978UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64260 #define XCM_REG_AGG_CON_RULE5_Q                                                                      0x100097cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).:  Chips: BB_A0 BB_B0 K2
64261 #define XCM_REG_AGG_CON_RULE6_Q                                                                      0x1000980UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64262 #define XCM_REG_AGG_CON_RULE7_Q                                                                      0x1000984UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64263 #define XCM_REG_AGG_CON_RULE8_Q                                                                      0x1000988UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64264 #define XCM_REG_AGG_CON_RULE9_Q                                                                      0x100098cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64265 #define XCM_REG_AGG_CON_RULE10_Q                                                                     0x1000990UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64266 #define XCM_REG_AGG_CON_RULE11_Q                                                                     0x1000994UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64267 #define XCM_REG_AGG_CON_RULE12_Q                                                                     0x1000998UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64268 #define XCM_REG_AGG_CON_RULE13_Q                                                                     0x100099cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64269 #define XCM_REG_AGG_CON_RULE14_Q                                                                     0x10009a0UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64270 #define XCM_REG_AGG_CON_RULE15_Q                                                                     0x10009a4UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64271 #define XCM_REG_AGG_CON_RULE16_Q                                                                     0x10009a8UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64272 #define XCM_REG_AGG_CON_RULE17_Q                                                                     0x10009acUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64273 #define XCM_REG_AGG_CON_RULE18_Q                                                                     0x10009b0UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64274 #define XCM_REG_AGG_CON_RULE19_Q                                                                     0x10009b4UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64275 #define XCM_REG_AGG_CON_RULE20_Q                                                                     0x10009b8UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64276 #define XCM_REG_AGG_CON_RULE21_Q                                                                     0x10009bcUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64277 #define XCM_REG_AGG_CON_RULE22_Q                                                                     0x10009c0UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64278 #define XCM_REG_AGG_CON_RULE23_Q                                                                     0x10009c4UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64279 #define XCM_REG_AGG_CON_RULE24_Q                                                                     0x10009c8UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64280 #define XCM_REG_AGG_CON_RULE25_Q                                                                     0x10009ccUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
64281 #define XCM_REG_IN_PRCS_TBL_CRD_AGG                                                                  0x1000a04UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
64282 #define XCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                0x1000a08UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
64283 #define XCM_REG_IN_PRCS_TBL_FILL_LVL                                                                 0x1000a0cUL //Access:R    DataWidth:0x4   In-process Table fill level  (in messages).  Chips: BB_A0 BB_B0 K2
64284 #define XCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                              0x1000a10UL //Access:R    DataWidth:0x1   In-process Table almost full.  Chips: BB_A0 BB_B0 K2
64285 #define XCM_REG_QMCON_CURR_ST                                                                        0x1000a14UL //Access:R    DataWidth:0x3   QM connection registration FSM current state.  Chips: BB_A0 BB_B0 K2
64286 #define XCM_REG_TMCON_CURR_ST                                                                        0x1000a18UL //Access:R    DataWidth:0x1   TM connection output FSM current state.  Chips: BB_A0 BB_B0 K2
64287 #define XCM_REG_CCFC_CURR_ST                                                                         0x1000a1cUL //Access:R    DataWidth:0x1   CFC connection output FSM current state.  Chips: BB_A0 BB_B0 K2
64288 #define XCM_REG_CMPL_DIR_CURR_ST                                                                     0x1000a20UL //Access:R    DataWidth:0x4   Direct Completer FSM current state.  Chips: BB_A0 BB_B0 K2
64289 #define XCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                         0x1000a24UL //Access:RW   DataWidth:0x1   If set, Xx connection bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
64290 #define XCM_REG_DORQ_AEMPTY_THR                                                                      0x1000a28UL //Access:RW   DataWidth:0xa   DORQ Almost Empty threshold.  Chips: BB_A0
64291 #define XCM_REG_CCFC_INIT_CRD                                                                        0x1000a84UL //Access:RW   DataWidth:0x4   CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
64292 #define XCM_REG_QM_INIT_CRD0                                                                         0x1000a88UL //Access:RW   DataWidth:0x5   QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
64293 #define XCM_REG_QM_INIT_CRD1                                                                         0x1000a8cUL //Access:RW   DataWidth:0x5   QM output initial credit (XCM TX queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
64294 #define XCM_REG_TM_INIT_CRD                                                                          0x1000a90UL //Access:RW   DataWidth:0x4   Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
64295 #define XCM_REG_FIC_INIT_CRD                                                                         0x1000a94UL //Access:RW   DataWidth:0x6   FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.  Chips: BB_A0 BB_B0 K2
64296 #define XCM_REG_DIR_BYP_MSG_CNT                                                                      0x1000aa4UL //Access:RC   DataWidth:0x20  Counter of direct bypassed messages.  Chips: BB_A0 BB_B0 K2
64297 #define XCM_REG_MSDM_LENGTH_MIS                                                                      0x1000aa8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at MSDM interface.  Chips: BB_A0 BB_B0 K2
64298 #define XCM_REG_XSDM_LENGTH_MIS                                                                      0x1000aacUL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at XSDM interface.  Chips: BB_A0 BB_B0 K2
64299 #define XCM_REG_YSDM_LENGTH_MIS                                                                      0x1000ab0UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at YSDM interface.  Chips: BB_A0 BB_B0 K2
64300 #define XCM_REG_USDM_LENGTH_MIS                                                                      0x1000ab4UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at USDM interface.  Chips: BB_A0 BB_B0 K2
64301 #define XCM_REG_DORQ_LENGTH_MIS                                                                      0x1000ab8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at the dorq interface.  Chips: BB_A0 BB_B0 K2
64302 #define XCM_REG_PBF_LENGTH_MIS                                                                       0x1000abcUL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at PBF interface.  Chips: BB_A0 BB_B0 K2
64303 #define XCM_REG_GRC_BUF_EMPTY                                                                        0x1000ac0UL //Access:R    DataWidth:0x1   Input Stage GRC buffer is empty.  Chips: BB_A0 BB_B0 K2
64304 #define XCM_REG_GRC_BUF_STATUS                                                                       0x1000ac4UL //Access:R    DataWidth:0x6   Input Stage GRC buffer status.  Chips: BB_A0 BB_B0 K2
64305 #define XCM_REG_STORM_MSG_CNTR                                                                       0x1000ac8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the STORM input.  Chips: BB_A0 BB_B0 K2
64306 #define XCM_REG_MSDM_MSG_CNTR                                                                        0x1000accUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input MSDM.  Chips: BB_A0 BB_B0 K2
64307 #define XCM_REG_XSDM_MSG_CNTR                                                                        0x1000ad0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input XSDM.  Chips: BB_A0 BB_B0 K2
64308 #define XCM_REG_YSDM_MSG_CNTR                                                                        0x1000ad4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input YSDM.  Chips: BB_A0 BB_B0 K2
64309 #define XCM_REG_USDM_MSG_CNTR                                                                        0x1000ad8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input USDM.  Chips: BB_A0 BB_B0 K2
64310 #define XCM_REG_MSEM_MSG_CNTR                                                                        0x1000adcUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input MSEM.  Chips: BB_A0 BB_B0 K2
64311 #define XCM_REG_USEM_MSG_CNTR                                                                        0x1000ae0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input USEM.  Chips: BB_A0 BB_B0 K2
64312 #define XCM_REG_YSEM_MSG_CNTR                                                                        0x1000ae4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input Ysem.  Chips: BB_A0 BB_B0 K2
64313 #define XCM_REG_DORQ_MSG_CNTR                                                                        0x1000ae8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at  input DORQ.  Chips: BB_A0 BB_B0 K2
64314 #define XCM_REG_PBF_MSG_CNTR                                                                         0x1000aecUL //Access:RC   DataWidth:0x1c  Counter of the input messages at input PBF.  Chips: BB_A0 BB_B0 K2
64315 #define XCM_REG_QM_P_MSG_CNTR                                                                        0x1000af0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (primary).  Chips: BB_A0 BB_B0 K2
64316 #define XCM_REG_QM_S_MSG_CNTR                                                                        0x1000af4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (secondary).  Chips: BB_A0 BB_B0 K2
64317 #define XCM_REG_TM_MSG_CNTR                                                                          0x1000af8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the Timers input.  Chips: BB_A0 BB_B0 K2
64318 #define XCM_REG_IS_GRC                                                                               0x1000afcUL //Access:W    DataWidth:0x20  Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done  Chips: BB_A0 BB_B0 K2
64319 #define XCM_REG_IS_QM_P_FILL_LVL                                                                     0x1000b00UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
64320 #define XCM_REG_IS_QM_S_FILL_LVL                                                                     0x1000b04UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
64321 #define XCM_REG_IS_TM_FILL_LVL                                                                       0x1000b08UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in TM Input Stage.  Chips: BB_A0 BB_B0 K2
64322 #define XCM_REG_IS_STORM_FILL_LVL                                                                    0x1000b0cUL //Access:R    DataWidth:0x7   Number of QREGs (128b) of data in STORM Input Stage.  Chips: BB_A0 BB_B0 K2
64323 #define XCM_REG_IS_MSDM_FILL_LVL                                                                     0x1000b10UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in MSDM Input Stage.  Chips: BB_A0 BB_B0 K2
64324 #define XCM_REG_IS_XSDM_FILL_LVL                                                                     0x1000b14UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in XSDM Input Stage.  Chips: BB_A0 BB_B0 K2
64325 #define XCM_REG_IS_YSDM_FILL_LVL                                                                     0x1000b18UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in YSDM Input Stage.  Chips: BB_A0 BB_B0 K2
64326 #define XCM_REG_IS_USDM_FILL_LVL                                                                     0x1000b1cUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in USDM Input Stage.  Chips: BB_A0 BB_B0 K2
64327 #define XCM_REG_IS_MSEM_FILL_LVL                                                                     0x1000b20UL //Access:R    DataWidth:0x5   Number of QREGs (128b) of data in MSEM Input Stage.  Chips: BB_A0 BB_B0 K2
64328 #define XCM_REG_IS_USEM_FILL_LVL                                                                     0x1000b24UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in USEM Input Stage.  Chips: BB_A0 BB_B0 K2
64329 #define XCM_REG_IS_YSEM_FILL_LVL                                                                     0x1000b28UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in YSEM Input Stage.  Chips: BB_A0 BB_B0 K2
64330 #define XCM_REG_IS_DORQ_FILL_LVL                                                                     0x1000b2cUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in DORQ Input Stage.  Chips: BB_A0 BB_B0 K2
64331 #define XCM_REG_IS_PBF_FILL_LVL                                                                      0x1000b30UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in PBF Input Stage.  Chips: BB_A0 BB_B0 K2
64332 #define XCM_REG_QM_ACT_ST_FIFO_FILL_LVL                                                              0x1000b44UL //Access:R    DataWidth:0x4   QM Active State Counter FIFO fill level (entries).  Chips: BB_A0 BB_B0 K2
64333 #define XCM_REG_QM_ACT_CNT_RD_CURR_ST                                                                0x1000b48UL //Access:R    DataWidth:0x3   QM Active State Counter read FSM.  Chips: BB_A0 BB_B0 K2
64334 #define XCM_REG_QM_ACT_ST_CURR_ST                                                                    0x1000b4cUL //Access:R    DataWidth:0x1   QM Active State output FSM.  Chips: BB_A0 BB_B0 K2
64335 #define XCM_REG_QM_ACT_ST_CNT_ERR_DETAILS                                                            0x1000b50UL //Access:RW   DataWidth:0xb   Tracks error details of the transaction, which caused QM Active counter overflow/uder-run. Is reset on read. [0] - If set, there was under-run; [1] - If set, there was overflow; [10:2] - PQ number;  Chips: BB_A0 BB_B0 K2
64336 #define XCM_REG_FIC_MSG_CNTR                                                                         0x1000b54UL //Access:RC   DataWidth:0x1c  Counter of the output messages at FIC interfaces.  Chips: BB_A0 BB_B0 K2
64337 #define XCM_REG_QM_OUT_CNTR                                                                          0x1000b58UL //Access:RC   DataWidth:0x1c  Counter of the output QM commands.  Chips: BB_A0 BB_B0 K2
64338 #define XCM_REG_TM_OUT_CNTR                                                                          0x1000b5cUL //Access:RC   DataWidth:0x1c  Counter of the output Timers commands.  Chips: BB_A0 BB_B0 K2
64339 #define XCM_REG_DONE0_CNTR                                                                           0x1000b60UL //Access:RC   DataWidth:0x1c  Counter of the output Done0.  Chips: BB_A0 BB_B0 K2
64340 #define XCM_REG_DONE1_CNTR                                                                           0x1000b64UL //Access:RC   DataWidth:0x1c  Counter of the output Done1.  Chips: BB_A0 BB_B0 K2
64341 #define XCM_REG_DONE2_CNTR                                                                           0x1000b68UL //Access:RC   DataWidth:0x1c  Counter of the output Done2.  Chips: BB_A0 BB_B0 K2
64342 #define XCM_REG_CCFC_CNTR                                                                            0x1000b6cUL //Access:RC   DataWidth:0x1c  Counter of the output CCFC.  Chips: BB_A0 BB_B0 K2
64343 #define XCM_REG_ECO_RESERVED                                                                         0x1000b84UL //Access:RW   DataWidth:0x8   Chicken bits.  Chips: BB_A0 BB_B0 K2
64344 #define XCM_REG_IS_FOC_MSEM_NXT_INF_UNIT                                                             0x1000b88UL //Access:R    DataWidth:0x6   Debug read from MSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64345 #define XCM_REG_IS_FOC_USEM_NXT_INF_UNIT                                                             0x1000b8cUL //Access:R    DataWidth:0x6   Debug read from USEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64346 #define XCM_REG_IS_FOC_XSEM_NXT_INF_UNIT                                                             0x1000b90UL //Access:R    DataWidth:0x6   Debug read from XSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64347 #define XCM_REG_IS_FOC_YSEM_NXT_INF_UNIT                                                             0x1000b94UL //Access:R    DataWidth:0x6   Debug read from YSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64348 #define XCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                              0x1000b98UL //Access:R    DataWidth:0x6   Debug read from PBF Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64349 #define XCM_REG_IS_FOC_DORQ_NXT_INF_UNIT                                                             0x1000b9cUL //Access:R    DataWidth:0x6   Debug read from DORQ Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64350 #define XCM_REG_IS_FOC_MSDM_NXT_INF_UNIT                                                             0x1000ba0UL //Access:R    DataWidth:0x6   Debug read from MSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64351 #define XCM_REG_IS_FOC_USDM_NXT_INF_UNIT                                                             0x1000ba4UL //Access:R    DataWidth:0x6   Debug read from USDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64352 #define XCM_REG_IS_FOC_XSDM_NXT_INF_UNIT                                                             0x1000ba8UL //Access:R    DataWidth:0x6   Debug read from XSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64353 #define XCM_REG_IS_FOC_YSDM_NXT_INF_UNIT                                                             0x1000bacUL //Access:R    DataWidth:0x6   Debug read from YSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
64354 #define XCM_REG_IS_FOC_MSEM                                                                          0x1000c00UL //Access:R    DataWidth:0x20  Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64355 #define XCM_REG_IS_FOC_MSEM_SIZE                                                                     72
64356 #define XCM_REG_IS_FOC_USEM                                                                          0x1000e00UL //Access:R    DataWidth:0x20  Debug read from USEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64357 #define XCM_REG_IS_FOC_USEM_SIZE                                                                     44
64358 #define XCM_REG_IS_FOC_XSEM                                                                          0x1001000UL //Access:R    DataWidth:0x20  Debug read from XSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64359 #define XCM_REG_IS_FOC_XSEM_SIZE                                                                     256
64360 #define XCM_REG_IS_FOC_YSEM                                                                          0x1001400UL //Access:R    DataWidth:0x20  Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64361 #define XCM_REG_IS_FOC_YSEM_SIZE                                                                     32
64362 #define XCM_REG_IS_FOC_PBF                                                                           0x1001500UL //Access:R    DataWidth:0x20  Debug read from PBF Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64363 #define XCM_REG_IS_FOC_PBF_SIZE                                                                      36
64364 #define XCM_REG_IS_FOC_DORQ                                                                          0x1001600UL //Access:R    DataWidth:0x20  Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64365 #define XCM_REG_IS_FOC_DORQ_SIZE                                                                     24
64366 #define XCM_REG_IS_FOC_MSDM                                                                          0x1001680UL //Access:R    DataWidth:0x20  Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0
64367 #define XCM_REG_IS_FOC_MSDM_SIZE                                                                     20
64368 #define XCM_REG_IS_FOC_USDM                                                                          0x1001700UL //Access:R    DataWidth:0x20  Debug read from USDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64369 #define XCM_REG_IS_FOC_USDM_SIZE                                                                     28
64370 #define XCM_REG_IS_FOC_XSDM                                                                          0x1001780UL //Access:R    DataWidth:0x20  Debug read from XSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64371 #define XCM_REG_IS_FOC_XSDM_SIZE                                                                     16
64372 #define XCM_REG_IS_FOC_YSDM                                                                          0x10017c0UL //Access:R    DataWidth:0x20  Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
64373 #define XCM_REG_IS_FOC_YSDM_SIZE                                                                     12
64374 #define XCM_REG_CTX_RBC_ACCS                                                                         0x1001800UL //Access:RW   DataWidth:0x10  Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX  Chips: BB_A0 BB_B0 K2
64375 #define XCM_REG_AGG_CON_CTX                                                                          0x1001804UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
64376 #define XCM_REG_SM_CON_CTX                                                                           0x1001808UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
64377 #define XCM_REG_XX_CBYP_TBL                                                                          0x1001820UL //Access:R    DataWidth:0xf   Xx Connection Bypass Table.  Chips: BB_A0 BB_B0 K2
64378 #define XCM_REG_XX_CBYP_TBL_SIZE                                                                     8
64379 #define XCM_REG_XX_LCID_CAM                                                                          0x1001900UL //Access:R    DataWidth:0xa   Debug only. Read only access to LCID CAM in XX protection mechanism.  Chips: BB_A0 BB_B0 K2
64380 #define XCM_REG_XX_LCID_CAM_SIZE                                                                     30
64381 #define XCM_REG_XX_TBL                                                                               0x1001a00UL //Access:R    DataWidth:0x17  Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [3:1] - Connection type; LL size: PCM - [6:4]; M/T/U/X/YCM - [10:4]; Tail pointer: PCM - [8:7]; M/T/U/X/YCM - [16:11]; Next pointer: PCM - [10:9]; M/T/U/X/YCM - [22:17];  Chips: BB_A0 BB_B0 K2
64382 #define XCM_REG_XX_TBL_SIZE                                                                          30
64383 #define XCM_REG_XX_DSCR_TBL                                                                          0x1001b00UL //Access:RW   DataWidth:0x11  Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.  Chips: BB_A0 BB_B0 K2
64384 #define XCM_REG_XX_DSCR_TBL_SIZE                                                                     64
64385 #define XCM_REG_XX_MSG_RAM                                                                           0x1002000UL //Access:R    DataWidth:0x20  Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.  Chips: BB_A0 BB_B0 K2
64386 #define XCM_REG_XX_MSG_RAM_SIZE                                                                      1024
64387 #define XCM_REG_QM_ACT_ST_CNT                                                                        0x1004000UL //Access:RW   DataWidth:0x20  At write the following fields are used to implement a QM active state counter update: [19:0]: PQ counter update value. [28:20] PQ number. [29:29] Reserved. [31:30] Command type: 0 - SET; 1 - DEC; 2 - INC; The address provided is don't care. At read the address provided defines the PQ number to be accessed for read.  Chips: BB_A0 BB_B0 K2
64388 #define XCM_REG_QM_ACT_ST_CNT_SIZE                                                                   512
64389 #define YCM_REG_INIT                                                                                 0x1080000UL //Access:RW   DataWidth:0x1   Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.  Chips: BB_A0 BB_B0 K2
64390 #define YCM_REG_DBG_SELECT                                                                           0x1080040UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
64391 #define YCM_REG_DBG_DWORD_ENABLE                                                                     0x1080044UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
64392 #define YCM_REG_DBG_SHIFT                                                                            0x1080048UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
64393 #define YCM_REG_DBG_FORCE_VALID                                                                      0x108004cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
64394 #define YCM_REG_DBG_FORCE_FRAME                                                                      0x1080050UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
64395 #define YCM_REG_DBG_OUT_DATA                                                                         0x1080060UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
64396 #define YCM_REG_DBG_OUT_DATA_SIZE                                                                    8
64397 #define YCM_REG_DBG_OUT_VALID                                                                        0x1080080UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
64398 #define YCM_REG_DBG_OUT_FRAME                                                                        0x1080084UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
64399 #define YCM_REG_INT_STS_0                                                                            0x1080180UL //Access:R    DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64400     #define YCM_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
64401     #define YCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
64402     #define YCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                      (0x1<<1) // Write to full STORM input buffer.
64403     #define YCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                1
64404     #define YCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                     (0x1<<2) // Read from empty  STORM input buffer.
64405     #define YCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                               2
64406     #define YCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR                                                       (0x1<<3) // Write to full MSDM input buffer.
64407     #define YCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT                                                 3
64408     #define YCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR                                                      (0x1<<4) // Read from empty MSDM input buffer.
64409     #define YCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR_SHIFT                                                4
64410     #define YCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR                                                       (0x1<<5) // Write to full YSDM input buffer.
64411     #define YCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT                                                 5
64412     #define YCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR                                                      (0x1<<6) // Read from empty  YSDM input buffer.
64413     #define YCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT                                                6
64414     #define YCM_REG_INT_STS_0_IS_XYLD_OVFL_ERR                                                       (0x1<<7) // Write to full XYLD input buffer.
64415     #define YCM_REG_INT_STS_0_IS_XYLD_OVFL_ERR_SHIFT                                                 7
64416     #define YCM_REG_INT_STS_0_IS_XYLD_UNDER_ERR                                                      (0x1<<8) // Read from empty XYLD input buffer.
64417     #define YCM_REG_INT_STS_0_IS_XYLD_UNDER_ERR_SHIFT                                                8
64418     #define YCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR                                                       (0x1<<9) // Write to full Msem input buffer.
64419     #define YCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_SHIFT                                                 9
64420     #define YCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR                                                      (0x1<<10) // Read from empty  Msem input buffer.
64421     #define YCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_SHIFT                                                10
64422     #define YCM_REG_INT_STS_0_IS_USEM_OVFL_ERR                                                       (0x1<<11) // Write to full Usem input buffer.
64423     #define YCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_SHIFT                                                 11
64424     #define YCM_REG_INT_STS_0_IS_USEM_UNDER_ERR                                                      (0x1<<12) // Read from empty Usem input buffer.
64425     #define YCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_SHIFT                                                12
64426 #define YCM_REG_INT_MASK_0                                                                           0x1080184UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64427     #define YCM_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.ADDRESS_ERROR .
64428     #define YCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
64429     #define YCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
64430     #define YCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                               1
64431     #define YCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
64432     #define YCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                              2
64433     #define YCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
64434     #define YCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT                                                3
64435     #define YCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
64436     #define YCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR_SHIFT                                               4
64437     #define YCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
64438     #define YCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT                                                5
64439     #define YCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
64440     #define YCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT                                               6
64441     #define YCM_REG_INT_MASK_0_IS_XYLD_OVFL_ERR                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_XYLD_OVFL_ERR .
64442     #define YCM_REG_INT_MASK_0_IS_XYLD_OVFL_ERR_SHIFT                                                7
64443     #define YCM_REG_INT_MASK_0_IS_XYLD_UNDER_ERR                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_XYLD_UNDER_ERR .
64444     #define YCM_REG_INT_MASK_0_IS_XYLD_UNDER_ERR_SHIFT                                               8
64445     #define YCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
64446     #define YCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_SHIFT                                                9
64447     #define YCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
64448     #define YCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_SHIFT                                               10
64449     #define YCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
64450     #define YCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_SHIFT                                                11
64451     #define YCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
64452     #define YCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_SHIFT                                               12
64453 #define YCM_REG_INT_STS_WR_0                                                                         0x1080188UL //Access:WR   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64454     #define YCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
64455     #define YCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
64456     #define YCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                   (0x1<<1) // Write to full STORM input buffer.
64457     #define YCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                             1
64458     #define YCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                  (0x1<<2) // Read from empty  STORM input buffer.
64459     #define YCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                            2
64460     #define YCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR                                                    (0x1<<3) // Write to full MSDM input buffer.
64461     #define YCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT                                              3
64462     #define YCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR                                                   (0x1<<4) // Read from empty MSDM input buffer.
64463     #define YCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR_SHIFT                                             4
64464     #define YCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR                                                    (0x1<<5) // Write to full YSDM input buffer.
64465     #define YCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT                                              5
64466     #define YCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR                                                   (0x1<<6) // Read from empty  YSDM input buffer.
64467     #define YCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT                                             6
64468     #define YCM_REG_INT_STS_WR_0_IS_XYLD_OVFL_ERR                                                    (0x1<<7) // Write to full XYLD input buffer.
64469     #define YCM_REG_INT_STS_WR_0_IS_XYLD_OVFL_ERR_SHIFT                                              7
64470     #define YCM_REG_INT_STS_WR_0_IS_XYLD_UNDER_ERR                                                   (0x1<<8) // Read from empty XYLD input buffer.
64471     #define YCM_REG_INT_STS_WR_0_IS_XYLD_UNDER_ERR_SHIFT                                             8
64472     #define YCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR                                                    (0x1<<9) // Write to full Msem input buffer.
64473     #define YCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_SHIFT                                              9
64474     #define YCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR                                                   (0x1<<10) // Read from empty  Msem input buffer.
64475     #define YCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_SHIFT                                             10
64476     #define YCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR                                                    (0x1<<11) // Write to full Usem input buffer.
64477     #define YCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_SHIFT                                              11
64478     #define YCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR                                                   (0x1<<12) // Read from empty Usem input buffer.
64479     #define YCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_SHIFT                                             12
64480 #define YCM_REG_INT_STS_CLR_0                                                                        0x108018cUL //Access:RC   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64481     #define YCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
64482     #define YCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
64483     #define YCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                  (0x1<<1) // Write to full STORM input buffer.
64484     #define YCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                            1
64485     #define YCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                 (0x1<<2) // Read from empty  STORM input buffer.
64486     #define YCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                           2
64487     #define YCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR                                                   (0x1<<3) // Write to full MSDM input buffer.
64488     #define YCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT                                             3
64489     #define YCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR                                                  (0x1<<4) // Read from empty MSDM input buffer.
64490     #define YCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR_SHIFT                                            4
64491     #define YCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR                                                   (0x1<<5) // Write to full YSDM input buffer.
64492     #define YCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT                                             5
64493     #define YCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR                                                  (0x1<<6) // Read from empty  YSDM input buffer.
64494     #define YCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT                                            6
64495     #define YCM_REG_INT_STS_CLR_0_IS_XYLD_OVFL_ERR                                                   (0x1<<7) // Write to full XYLD input buffer.
64496     #define YCM_REG_INT_STS_CLR_0_IS_XYLD_OVFL_ERR_SHIFT                                             7
64497     #define YCM_REG_INT_STS_CLR_0_IS_XYLD_UNDER_ERR                                                  (0x1<<8) // Read from empty XYLD input buffer.
64498     #define YCM_REG_INT_STS_CLR_0_IS_XYLD_UNDER_ERR_SHIFT                                            8
64499     #define YCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR                                                   (0x1<<9) // Write to full Msem input buffer.
64500     #define YCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_SHIFT                                             9
64501     #define YCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR                                                  (0x1<<10) // Read from empty  Msem input buffer.
64502     #define YCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_SHIFT                                            10
64503     #define YCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR                                                   (0x1<<11) // Write to full Usem input buffer.
64504     #define YCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_SHIFT                                             11
64505     #define YCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR                                                  (0x1<<12) // Read from empty Usem input buffer.
64506     #define YCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_SHIFT                                            12
64507 #define YCM_REG_INT_STS_1                                                                            0x1080190UL //Access:R    DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
64508     #define YCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                        (0x1<<0) // Write to full Pbf input buffer.
64509     #define YCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                  0
64510     #define YCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                       (0x1<<1) // Read from empty Pbf input buffer.
64511     #define YCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                 1
64512     #define YCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                       (0x1<<2) // Write to full QM input buffer.
64513     #define YCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                 2
64514     #define YCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                      (0x1<<3) // Read from empty QM input buffer.
64515     #define YCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                3
64516     #define YCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                       (0x1<<4) // Write to full QM input buffer.
64517     #define YCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                 4
64518     #define YCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                      (0x1<<5) // Read from empty QM input buffer.
64519     #define YCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                5
64520     #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                       (0x1<<6) // Write to full GRC input buffer bits [31:0].
64521     #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                 6
64522     #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                      (0x1<<7) // Read from empty  GRC input buffer bits [31:0].
64523     #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                7
64524     #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                       (0x1<<8) // Write to full GRC input buffer bits [63:32].
64525     #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                 8
64526     #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                      (0x1<<9) // Read from empty  GRC input buffer bits [63:32].
64527     #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                9
64528     #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                       (0x1<<10) // Write to full GRC input buffer bits [95:64].
64529     #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                 10
64530     #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                      (0x1<<11) // Read from empty  GRC input buffer bits [95:64].
64531     #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                11
64532     #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                       (0x1<<12) // Write to full GRC input buffer bits [127:96].
64533     #define YCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                 12
64534     #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                      (0x1<<13) // Read from empty  GRC input buffer bits [127:96].
64535     #define YCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                13
64536     #define YCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                       (0x1<<14) // In-process Table overflow.
64537     #define YCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                 14
64538     #define YCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                   (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
64539     #define YCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                             15
64540     #define YCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                    (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
64541     #define YCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                              16
64542     #define YCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL                                                 (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
64543     #define YCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                           17
64544     #define YCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL                                                  (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
64545     #define YCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                            18
64546     #define YCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL                                                  (0x1<<19) // Message Processor Storm Task Data buffer overflow.
64547     #define YCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                            19
64548     #define YCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL                                                   (0x1<<20) // Message Processor Storm Task Command buffer overflow.
64549     #define YCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                             20
64550     #define YCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                  (0x1<<21) // Input message first descriptor fields violation.
64551     #define YCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                            21
64552     #define YCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE                                                  (0x1<<22) // Input message second descriptor fields violation.
64553     #define YCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_SHIFT                                            22
64554 #define YCM_REG_INT_MASK_1                                                                           0x1080194UL //Access:RW   DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
64555     #define YCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
64556     #define YCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                 0
64557     #define YCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
64558     #define YCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                1
64559     #define YCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
64560     #define YCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                2
64561     #define YCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
64562     #define YCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                               3
64563     #define YCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
64564     #define YCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                4
64565     #define YCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
64566     #define YCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                               5
64567     #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
64568     #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                6
64569     #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
64570     #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                               7
64571     #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
64572     #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                8
64573     #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
64574     #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                               9
64575     #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
64576     #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                10
64577     #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
64578     #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                               11
64579     #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
64580     #define YCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                12
64581     #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
64582     #define YCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                               13
64583     #define YCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                      (0x1<<14) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
64584     #define YCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                14
64585     #define YCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                  (0x1<<15) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
64586     #define YCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                            15
64587     #define YCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                   (0x1<<16) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
64588     #define YCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                             16
64589     #define YCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL                                                (0x1<<17) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
64590     #define YCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                          17
64591     #define YCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL                                                 (0x1<<18) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
64592     #define YCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                           18
64593     #define YCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
64594     #define YCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                           19
64595     #define YCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
64596     #define YCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                            20
64597     #define YCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                 (0x1<<21) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
64598     #define YCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                           21
64599     #define YCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
64600     #define YCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_SHIFT                                           22
64601 #define YCM_REG_INT_STS_WR_1                                                                         0x1080198UL //Access:WR   DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
64602     #define YCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                     (0x1<<0) // Write to full Pbf input buffer.
64603     #define YCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                               0
64604     #define YCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                    (0x1<<1) // Read from empty Pbf input buffer.
64605     #define YCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                              1
64606     #define YCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                    (0x1<<2) // Write to full QM input buffer.
64607     #define YCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                              2
64608     #define YCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                   (0x1<<3) // Read from empty QM input buffer.
64609     #define YCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                             3
64610     #define YCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                    (0x1<<4) // Write to full QM input buffer.
64611     #define YCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                              4
64612     #define YCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                   (0x1<<5) // Read from empty QM input buffer.
64613     #define YCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                             5
64614     #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                    (0x1<<6) // Write to full GRC input buffer bits [31:0].
64615     #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                              6
64616     #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                   (0x1<<7) // Read from empty  GRC input buffer bits [31:0].
64617     #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                             7
64618     #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                    (0x1<<8) // Write to full GRC input buffer bits [63:32].
64619     #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                              8
64620     #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                   (0x1<<9) // Read from empty  GRC input buffer bits [63:32].
64621     #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                             9
64622     #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                    (0x1<<10) // Write to full GRC input buffer bits [95:64].
64623     #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                              10
64624     #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                   (0x1<<11) // Read from empty  GRC input buffer bits [95:64].
64625     #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                             11
64626     #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                    (0x1<<12) // Write to full GRC input buffer bits [127:96].
64627     #define YCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                              12
64628     #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                   (0x1<<13) // Read from empty  GRC input buffer bits [127:96].
64629     #define YCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                             13
64630     #define YCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                    (0x1<<14) // In-process Table overflow.
64631     #define YCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                              14
64632     #define YCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
64633     #define YCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                          15
64634     #define YCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                 (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
64635     #define YCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                           16
64636     #define YCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL                                              (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
64637     #define YCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                        17
64638     #define YCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL                                               (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
64639     #define YCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                         18
64640     #define YCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL                                               (0x1<<19) // Message Processor Storm Task Data buffer overflow.
64641     #define YCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                         19
64642     #define YCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL                                                (0x1<<20) // Message Processor Storm Task Command buffer overflow.
64643     #define YCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                          20
64644     #define YCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                               (0x1<<21) // Input message first descriptor fields violation.
64645     #define YCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                         21
64646     #define YCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE                                               (0x1<<22) // Input message second descriptor fields violation.
64647     #define YCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                         22
64648 #define YCM_REG_INT_STS_CLR_1                                                                        0x108019cUL //Access:RC   DataWidth:0x17  Multi Field Register.  Chips: BB_A0 BB_B0 K2
64649     #define YCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                    (0x1<<0) // Write to full Pbf input buffer.
64650     #define YCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                              0
64651     #define YCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                   (0x1<<1) // Read from empty Pbf input buffer.
64652     #define YCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                             1
64653     #define YCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                   (0x1<<2) // Write to full QM input buffer.
64654     #define YCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                             2
64655     #define YCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                  (0x1<<3) // Read from empty QM input buffer.
64656     #define YCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                            3
64657     #define YCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                   (0x1<<4) // Write to full QM input buffer.
64658     #define YCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                             4
64659     #define YCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                  (0x1<<5) // Read from empty QM input buffer.
64660     #define YCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                            5
64661     #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                   (0x1<<6) // Write to full GRC input buffer bits [31:0].
64662     #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                             6
64663     #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                  (0x1<<7) // Read from empty  GRC input buffer bits [31:0].
64664     #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                            7
64665     #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                   (0x1<<8) // Write to full GRC input buffer bits [63:32].
64666     #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                             8
64667     #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                  (0x1<<9) // Read from empty  GRC input buffer bits [63:32].
64668     #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                            9
64669     #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                   (0x1<<10) // Write to full GRC input buffer bits [95:64].
64670     #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                             10
64671     #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                  (0x1<<11) // Read from empty  GRC input buffer bits [95:64].
64672     #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                            11
64673     #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                   (0x1<<12) // Write to full GRC input buffer bits [127:96].
64674     #define YCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                             12
64675     #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                  (0x1<<13) // Read from empty  GRC input buffer bits [127:96].
64676     #define YCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                            13
64677     #define YCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                   (0x1<<14) // In-process Table overflow.
64678     #define YCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                             14
64679     #define YCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                               (0x1<<15) // Message Processor Storm Connection Data buffer overflow.
64680     #define YCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                         15
64681     #define YCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                (0x1<<16) // Message Processor Storm Connection Command buffer overflow.
64682     #define YCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                          16
64683     #define YCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL                                             (0x1<<17) // Message Processor Aggregation Task Data buffer overflow.
64684     #define YCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                       17
64685     #define YCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL                                              (0x1<<18) // Message Processor Aggregation Task Command buffer overflow.
64686     #define YCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                        18
64687     #define YCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL                                              (0x1<<19) // Message Processor Storm Task Data buffer overflow.
64688     #define YCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                        19
64689     #define YCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL                                               (0x1<<20) // Message Processor Storm Task Command buffer overflow.
64690     #define YCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                         20
64691     #define YCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                              (0x1<<21) // Input message first descriptor fields violation.
64692     #define YCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                        21
64693     #define YCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE                                              (0x1<<22) // Input message second descriptor fields violation.
64694     #define YCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                        22
64695 #define YCM_REG_INT_STS_2                                                                            0x10801a0UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64696     #define YCM_REG_INT_STS_2_QMREG_MORE4                                                            (0x1<<0) // More than 4 QM registrations.
64697     #define YCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                      0
64698 #define YCM_REG_INT_MASK_2                                                                           0x10801a4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64699     #define YCM_REG_INT_MASK_2_QMREG_MORE4                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: YCM_REG_INT_STS_2.QMREG_MORE4 .
64700     #define YCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                     0
64701 #define YCM_REG_INT_STS_WR_2                                                                         0x10801a8UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64702     #define YCM_REG_INT_STS_WR_2_QMREG_MORE4                                                         (0x1<<0) // More than 4 QM registrations.
64703     #define YCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                   0
64704 #define YCM_REG_INT_STS_CLR_2                                                                        0x10801acUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64705     #define YCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                        (0x1<<0) // More than 4 QM registrations.
64706     #define YCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                  0
64707 #define YCM_REG_PRTY_MASK_H_0                                                                        0x1080204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
64708     #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_ECC_RF_INT .
64709     #define YCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_RF_INT_SHIFT                                          0
64710     #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT                                              (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
64711     #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT                                        1
64712     #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
64713     #define YCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_SHIFT                                        2
64714     #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT .
64715     #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_SHIFT                                        3
64716     #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_1_RF_INT .
64717     #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT_SHIFT                                        4
64718     #define YCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT .
64719     #define YCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_SHIFT                                          5
64720     #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT                                              (0x1<<6) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
64721     #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT                                        6
64722     #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
64723     #define YCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT                                        7
64724     #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT                                              (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_ECC_0_RF_INT .
64725     #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_SHIFT                                        8
64726     #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT                                              (0x1<<9) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_ECC_1_RF_INT .
64727     #define YCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_SHIFT                                        9
64728     #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
64729     #define YCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_SHIFT                                            10
64730     #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
64731     #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      26
64732     #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
64733     #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      26
64734     #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
64735     #define YCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                         11
64736     #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
64737     #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      11
64738     #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
64739     #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      11
64740     #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
64741     #define YCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                         12
64742     #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
64743     #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                      12
64744     #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
64745     #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                      12
64746     #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
64747     #define YCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                         13
64748     #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
64749     #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                      13
64750     #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
64751     #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      13
64752     #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
64753     #define YCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                         14
64754     #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
64755     #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0_SHIFT                                      14
64756     #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
64757     #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0_SHIFT                                      14
64758     #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
64759     #define YCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                         15
64760     #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                            (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
64761     #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                      15
64762     #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
64763     #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                      15
64764     #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
64765     #define YCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                         16
64766     #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
64767     #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0_SHIFT                                      16
64768     #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
64769     #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0_SHIFT                                      16
64770     #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
64771     #define YCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                         17
64772     #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
64773     #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0_SHIFT                                      17
64774     #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
64775     #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0_SHIFT                                      17
64776     #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
64777     #define YCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                         18
64778     #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
64779     #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0_SHIFT                                      18
64780     #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0                                            (0x1<<18) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
64781     #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0_SHIFT                                      18
64782     #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
64783     #define YCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                         19
64784     #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
64785     #define YCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_SHIFT                                            20
64786     #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
64787     #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0_SHIFT                                      19
64788     #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0                                            (0x1<<19) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
64789     #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0_SHIFT                                      19
64790     #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                               (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
64791     #define YCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                         21
64792     #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
64793     #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_A0_SHIFT                                      20
64794     #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0                                            (0x1<<20) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
64795     #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0_SHIFT                                      20
64796     #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                               (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
64797     #define YCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                         22
64798     #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0                                            (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
64799     #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0_SHIFT                                      22
64800     #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0                                            (0x1<<22) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
64801     #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0_SHIFT                                      22
64802     #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                               (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
64803     #define YCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                         23
64804     #define YCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
64805     #define YCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                            24
64806     #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
64807     #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                      24
64808     #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                            (0x1<<24) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
64809     #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                      24
64810     #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                               (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
64811     #define YCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                         25
64812     #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
64813     #define YCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT                                            26
64814     #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
64815     #define YCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                            27
64816     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_A0                                          (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
64817     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_A0_SHIFT                                    27
64818     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_B0                                          (0x1<<27) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
64819     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_B0_SHIFT                                    27
64820     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2                                             (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
64821     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2_SHIFT                                       28
64822     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_A0                                          (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
64823     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_A0_SHIFT                                    28
64824     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_B0                                          (0x1<<28) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
64825     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_B0_SHIFT                                    28
64826     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_K2                                             (0x1<<29) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
64827     #define YCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_K2_SHIFT                                       29
64828     #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                            (0x1<<29) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
64829     #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                      29
64830     #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0                                            (0x1<<29) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
64831     #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                      29
64832     #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                               (0x1<<30) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
64833     #define YCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                         30
64834     #define YCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
64835     #define YCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_SHIFT                                          0
64836     #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
64837     #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_SHIFT                                        3
64838     #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
64839     #define YCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_SHIFT                                        4
64840     #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
64841     #define YCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_SHIFT                                          5
64842     #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT                                              (0x1<<8) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
64843     #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_SHIFT                                        8
64844     #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT                                              (0x1<<9) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
64845     #define YCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_SHIFT                                        9
64846     #define YCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
64847     #define YCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_SHIFT                                            21
64848     #define YCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
64849     #define YCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_SHIFT                                            23
64850     #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
64851     #define YCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_SHIFT                                            25
64852     #define YCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
64853     #define YCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                            30
64854 #define YCM_REG_PRTY_MASK_H_1                                                                        0x1080214UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
64855     #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
64856     #define YCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_SHIFT                                            0
64857     #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_A0                                            (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
64858     #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_A0_SHIFT                                      0
64859     #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_B0                                            (0x1<<0) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
64860     #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_BB_B0_SHIFT                                      0
64861     #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
64862     #define YCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_K2_SHIFT                                         1
64863     #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_A0                                            (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
64864     #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_A0_SHIFT                                      1
64865     #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
64866     #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                      1
64867     #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                               (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
64868     #define YCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                         2
64869     #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_A0                                            (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
64870     #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                      2
64871     #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0                                            (0x1<<2) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
64872     #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                      2
64873     #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                               (0x1<<3) // This bit masks, when set, the Parity bit: YCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
64874     #define YCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                         3
64875 #define YCM_REG_MEM_ECC_EVENTS                                                                       0x1080234UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
64876 #define YCM_REG_MEM018_I_MEM_DFT_K2                                                                  0x108023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_is_storm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64877 #define YCM_REG_MEM016_I_MEM_DFT_K2                                                                  0x1080240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_is_msem_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64878 #define YCM_REG_MEM019_I_MEM_DFT_K2                                                                  0x1080244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_is_xyld_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64879 #define YCM_REG_MEM011_I_MEM_DFT_K2                                                                  0x1080248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_is_grc0.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64880 #define YCM_REG_MEM012_I_MEM_DFT_K2                                                                  0x108024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_is_grc1.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64881 #define YCM_REG_MEM013_I_MEM_DFT_K2                                                                  0x1080250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_is_grc2.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64882 #define YCM_REG_MEM014_I_MEM_DFT_K2                                                                  0x1080254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_is_grc3.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64883 #define YCM_REG_MEM027_I_MEM_DFT_K2                                                                  0x1080258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_xx_msg_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64884 #define YCM_REG_MEM030_I_MEM_DFT_K2                                                                  0x108025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_xx_pref_dir.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64885 #define YCM_REG_MEM029_I_MEM_DFT_K2                                                                  0x1080260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_xx_pref_byp.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64886 #define YCM_REG_MEM028_I_MEM_DFT_K2                                                                  0x1080264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_xx_pref_aggst.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64887 #define YCM_REG_MEM004_I_MEM_DFT_K2                                                                  0x1080268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_agg_con_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64888 #define YCM_REG_MEM003_I_MEM_DFT_K2                                                                  0x108026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_agg_con_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64889 #define YCM_REG_MEM024_I_MEM_DFT_K2                                                                  0x1080270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_sm_con_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64890 #define YCM_REG_MEM022_I_MEM_DFT_K2                                                                  0x1080274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_sm_con_ctx_0_1.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64891 #define YCM_REG_MEM023_I_MEM_DFT_K2                                                                  0x1080278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_sm_con_ctx_2.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64892 #define YCM_REG_MEM006_I_MEM_DFT_K2                                                                  0x108027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_agg_task_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64893 #define YCM_REG_MEM005_I_MEM_DFT_K2                                                                  0x1080280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_agg_task_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64894 #define YCM_REG_MEM026_I_MEM_DFT_K2                                                                  0x1080284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_sm_task_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64895 #define YCM_REG_MEM025_I_MEM_DFT_K2                                                                  0x1080288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_sm_task_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
64896 #define YCM_REG_MEM021_I_MEM_DFT_K2                                                                  0x108028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_prcs_trans.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64897 #define YCM_REG_MEM007_I_MEM_DFT_K2                                                                  0x1080290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ycm.i_in_prcs_msgin.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
64898 #define YCM_REG_IFEN                                                                                 0x1080400UL //Access:RW   DataWidth:0x1   Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
64899 #define YCM_REG_QM_CON_BASE_EVNT_ID_0                                                                0x1080404UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64900 #define YCM_REG_QM_CON_BASE_EVNT_ID_1                                                                0x1080408UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64901 #define YCM_REG_QM_CON_BASE_EVNT_ID_2                                                                0x108040cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64902 #define YCM_REG_QM_CON_BASE_EVNT_ID_3                                                                0x1080410UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64903 #define YCM_REG_QM_CON_BASE_EVNT_ID_4                                                                0x1080414UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64904 #define YCM_REG_QM_CON_BASE_EVNT_ID_5                                                                0x1080418UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64905 #define YCM_REG_QM_CON_BASE_EVNT_ID_6                                                                0x108041cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64906 #define YCM_REG_QM_CON_BASE_EVNT_ID_7                                                                0x1080420UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64907 #define YCM_REG_QM_TASK_BASE_EVNT_ID_0                                                               0x1080424UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64908 #define YCM_REG_QM_TASK_BASE_EVNT_ID_1                                                               0x1080428UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64909 #define YCM_REG_QM_TASK_BASE_EVNT_ID_2                                                               0x108042cUL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64910 #define YCM_REG_QM_TASK_BASE_EVNT_ID_3                                                               0x1080430UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64911 #define YCM_REG_QM_TASK_BASE_EVNT_ID_4                                                               0x1080434UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64912 #define YCM_REG_QM_TASK_BASE_EVNT_ID_5                                                               0x1080438UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64913 #define YCM_REG_QM_TASK_BASE_EVNT_ID_6                                                               0x108043cUL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64914 #define YCM_REG_QM_TASK_BASE_EVNT_ID_7                                                               0x1080440UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
64915 #define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_0                                                           0x1080444UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64916 #define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_1                                                           0x1080448UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64917 #define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_2                                                           0x108044cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64918 #define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_3                                                           0x1080450UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64919 #define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_4                                                           0x1080454UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64920 #define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_5                                                           0x1080458UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64921 #define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_6                                                           0x108045cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64922 #define YCM_REG_QM_AGG_CON_CTX_PART_SIZE_7                                                           0x1080460UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
64923 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_0                                                             0x1080464UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64924 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_1                                                             0x1080468UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64925 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_2                                                             0x108046cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64926 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_3                                                             0x1080470UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64927 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_4                                                             0x1080474UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64928 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_5                                                             0x1080478UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64929 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_6                                                             0x108047cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64930 #define YCM_REG_QM_SM_CON_CTX_LDST_FLG_7                                                             0x1080480UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
64931 #define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_0                                                          0x1080484UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
64932 #define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_1                                                          0x1080488UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
64933 #define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_2                                                          0x108048cUL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
64934 #define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_3                                                          0x1080490UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
64935 #define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_4                                                          0x1080494UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
64936 #define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_5                                                          0x1080498UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
64937 #define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_6                                                          0x108049cUL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
64938 #define YCM_REG_QM_AGG_TASK_CTX_PART_SIZE_7                                                          0x10804a0UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
64939 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_0                                                            0x10804a4UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
64940 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_1                                                            0x10804a8UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
64941 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_2                                                            0x10804acUL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
64942 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_3                                                            0x10804b0UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
64943 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_4                                                            0x10804b4UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
64944 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_5                                                            0x10804b8UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
64945 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_6                                                            0x10804bcUL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
64946 #define YCM_REG_QM_SM_TASK_CTX_LDST_FLG_7                                                            0x10804c0UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
64947 #define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_0                                                            0x10804c4UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
64948 #define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_1                                                            0x10804c8UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
64949 #define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_2                                                            0x10804ccUL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
64950 #define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_3                                                            0x10804d0UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
64951 #define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_4                                                            0x10804d4UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
64952 #define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_5                                                            0x10804d8UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
64953 #define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_6                                                            0x10804dcUL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
64954 #define YCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_7                                                            0x10804e0UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
64955 #define YCM_REG_QM_TCFC_XXLOCK_CMD_0                                                                 0x10804e4UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
64956 #define YCM_REG_QM_TCFC_XXLOCK_CMD_1                                                                 0x10804e8UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
64957 #define YCM_REG_QM_TCFC_XXLOCK_CMD_2                                                                 0x10804ecUL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
64958 #define YCM_REG_QM_TCFC_XXLOCK_CMD_3                                                                 0x10804f0UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
64959 #define YCM_REG_QM_TCFC_XXLOCK_CMD_4                                                                 0x10804f4UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
64960 #define YCM_REG_QM_TCFC_XXLOCK_CMD_5                                                                 0x10804f8UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
64961 #define YCM_REG_QM_TCFC_XXLOCK_CMD_6                                                                 0x10804fcUL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
64962 #define YCM_REG_QM_TCFC_XXLOCK_CMD_7                                                                 0x1080500UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
64963 #define YCM_REG_QM_XXLOCK_CMD_0                                                                      0x1080504UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64964 #define YCM_REG_QM_XXLOCK_CMD_1                                                                      0x1080508UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64965 #define YCM_REG_QM_XXLOCK_CMD_2                                                                      0x108050cUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64966 #define YCM_REG_QM_XXLOCK_CMD_3                                                                      0x1080510UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64967 #define YCM_REG_QM_XXLOCK_CMD_4                                                                      0x1080514UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64968 #define YCM_REG_QM_XXLOCK_CMD_5                                                                      0x1080518UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64969 #define YCM_REG_QM_XXLOCK_CMD_6                                                                      0x108051cUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64970 #define YCM_REG_QM_XXLOCK_CMD_7                                                                      0x1080520UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
64971 #define YCM_REG_QM_CON_USE_ST_FLG_0                                                                  0x1080524UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64972 #define YCM_REG_QM_CON_USE_ST_FLG_1                                                                  0x1080528UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64973 #define YCM_REG_QM_CON_USE_ST_FLG_2                                                                  0x108052cUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64974 #define YCM_REG_QM_CON_USE_ST_FLG_3                                                                  0x1080530UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64975 #define YCM_REG_QM_CON_USE_ST_FLG_4                                                                  0x1080534UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64976 #define YCM_REG_QM_CON_USE_ST_FLG_5                                                                  0x1080538UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64977 #define YCM_REG_QM_CON_USE_ST_FLG_6                                                                  0x108053cUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64978 #define YCM_REG_QM_CON_USE_ST_FLG_7                                                                  0x1080540UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
64979 #define YCM_REG_QM_TASK_USE_ST_FLG_0                                                                 0x1080544UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
64980 #define YCM_REG_QM_TASK_USE_ST_FLG_1                                                                 0x1080548UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
64981 #define YCM_REG_QM_TASK_USE_ST_FLG_2                                                                 0x108054cUL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
64982 #define YCM_REG_QM_TASK_USE_ST_FLG_3                                                                 0x1080550UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
64983 #define YCM_REG_QM_TASK_USE_ST_FLG_4                                                                 0x1080554UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
64984 #define YCM_REG_QM_TASK_USE_ST_FLG_5                                                                 0x1080558UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
64985 #define YCM_REG_QM_TASK_USE_ST_FLG_6                                                                 0x108055cUL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
64986 #define YCM_REG_QM_TASK_USE_ST_FLG_7                                                                 0x1080560UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM.  Chips: BB_A0 BB_B0 K2
64987 #define YCM_REG_ERR_EVNT_ID                                                                          0x1080564UL //Access:RW   DataWidth:0x8   The Event ID in case one of errors is set in QM input message.  Chips: BB_A0 BB_B0 K2
64988 #define YCM_REG_STORM_WEIGHT                                                                         0x1080604UL //Access:RW   DataWidth:0x3   The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64989 #define YCM_REG_MSEM_WEIGHT                                                                          0x1080608UL //Access:RW   DataWidth:0x3   The weight of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64990 #define YCM_REG_USEM_WEIGHT                                                                          0x108060cUL //Access:RW   DataWidth:0x3   The weight of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64991 #define YCM_REG_PBF_WEIGHT                                                                           0x1080610UL //Access:RW   DataWidth:0x3   The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64992 #define YCM_REG_GRC_WEIGHT                                                                           0x1080614UL //Access:RW   DataWidth:0x3   The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64993 #define YCM_REG_MSDM_WEIGHT                                                                          0x1080618UL //Access:RW   DataWidth:0x3   The weight of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64994 #define YCM_REG_YSDM_WEIGHT                                                                          0x108061cUL //Access:RW   DataWidth:0x3   The weight of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64995 #define YCM_REG_XYLD_WEIGHT                                                                          0x1080620UL //Access:RW   DataWidth:0x3   The weight of the input XYLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64996 #define YCM_REG_QM_P_WEIGHT                                                                          0x1080624UL //Access:RW   DataWidth:0x3   The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64997 #define YCM_REG_QM_S_WEIGHT                                                                          0x1080628UL //Access:RW   DataWidth:0x3   The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
64998 #define YCM_REG_IA_GROUP_PR0                                                                         0x108062cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
64999 #define YCM_REG_IA_GROUP_PR1                                                                         0x1080630UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65000 #define YCM_REG_IA_GROUP_PR2                                                                         0x1080634UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65001 #define YCM_REG_IA_GROUP_PR3                                                                         0x1080638UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65002 #define YCM_REG_IA_GROUP_PR4                                                                         0x108063cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65003 #define YCM_REG_IA_GROUP_PR5                                                                         0x1080640UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65004 #define YCM_REG_IA_ARB_SP_TIMEOUT                                                                    0x1080644UL //Access:RW   DataWidth:0x8   Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority.  Chips: BB_A0 BB_B0 K2
65005 #define YCM_REG_STORM_FRWRD_MODE                                                                     0x1080648UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65006 #define YCM_REG_MSDM_FRWRD_MODE                                                                      0x108064cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65007 #define YCM_REG_YSDM_FRWRD_MODE                                                                      0x1080650UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65008 #define YCM_REG_XYLD_FRWRD_MODE                                                                      0x1080654UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65009 #define YCM_REG_MSEM_FRWRD_MODE                                                                      0x1080658UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65010 #define YCM_REG_USEM_FRWRD_MODE                                                                      0x108065cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65011 #define YCM_REG_PBF_FRWRD_MODE                                                                       0x1080660UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65012 #define YCM_REG_SDM_ERR_HANDLE_EN                                                                    0x1080664UL //Access:RW   DataWidth:0x1   0 - disable error handling in SDM message; 1 - enable error handling in SDM message.  Chips: BB_A0 BB_B0 K2
65013 #define YCM_REG_DIR_BYP_EN                                                                           0x1080668UL //Access:RW   DataWidth:0x1   Direct bypass enable.  Chips: BB_A0 BB_B0 K2
65014 #define YCM_REG_FI_DESC_INPUT_VIOLATE                                                                0x108066cUL //Access:R    DataWidth:0x10  Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: XxBypass message in PCM block;  Chips: BB_A0 BB_B0 K2
65015 #define YCM_REG_SE_DESC_INPUT_VIOLATE                                                                0x1080670UL //Access:R    DataWidth:0xc   Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; Read only register.  Chips: BB_A0 BB_B0 K2
65016 #define YCM_REG_IA_AGG_CON_PART_FILL_LVL                                                             0x1080674UL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
65017 #define YCM_REG_IA_SM_CON_PART_FILL_LVL                                                              0x1080678UL //Access:R    DataWidth:0x3   Input Arbiter Storm Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
65018 #define YCM_REG_IA_AGG_TASK_PART_FILL_LVL                                                            0x108067cUL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Task part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
65019 #define YCM_REG_IA_SM_TASK_PART_FILL_LVL                                                             0x1080680UL //Access:R    DataWidth:0x3   Input Arbiter Storm Task part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
65020 #define YCM_REG_IA_TRANS_PART_FILL_LVL                                                               0x1080684UL //Access:R    DataWidth:0x3   Input Arbiter Transparent part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
65021 #define YCM_REG_XX_MSG_UP_BND                                                                        0x1080704UL //Access:RW   DataWidth:0x7   The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the siz of Xx protected message CM_REGISTERS_XX_MSG_SIZE_BND.XX_MSG_SIZE_BND  Chips: BB_A0 BB_B0 K2
65022 #define YCM_REG_XX_MSG_SIZE                                                                          0x1080708UL //Access:RW   DataWidth:0xb   The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to even number and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1664 PCM: 0d176 TCM: 0d1408 UCM: 0d1664 XCM: 0d256 YCM: 0d1536  Chips: BB_A0 BB_B0 K2
65023 #define YCM_REG_XX_LCID_CAM_UP_BND                                                                   0x108070cUL //Access:RW   DataWidth:0x5   The maximum number of connections in the XX protection LCID CAM.  Chips: BB_A0 BB_B0 K2
65024 #define YCM_REG_XX_FREE_CNT                                                                          0x1080710UL //Access:R    DataWidth:0x7   Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
65025 #define YCM_REG_XX_LCID_CAM_FILL_LVL                                                                 0x1080714UL //Access:R    DataWidth:0x5   Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.  Chips: BB_A0 BB_B0 K2
65026 #define YCM_REG_XX_LCID_CAM_ST_STAT                                                                  0x1080718UL //Access:RC   DataWidth:0x5   CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.  Chips: BB_A0 BB_B0 K2
65027 #define YCM_REG_XX_IA_GROUP_PR0                                                                      0x108071cUL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
65028 #define YCM_REG_XX_IA_GROUP_PR1                                                                      0x1080720UL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
65029 #define YCM_REG_XX_NON_LOCK_LCID_THR                                                                 0x1080724UL //Access:RW   DataWidth:0x5   Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.  Chips: BB_A0 BB_B0 K2
65030 #define YCM_REG_XX_LOCK_LCID_THR                                                                     0x1080728UL //Access:RW   DataWidth:0x5   Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.  Chips: BB_A0 BB_B0 K2
65031 #define YCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                 0x108072cUL //Access:RW   DataWidth:0x8   Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
65032 #define YCM_REG_XX_FREE_HEAD_PTR                                                                     0x1080730UL //Access:R    DataWidth:0x6   Xx Free Head Pointer.  Chips: BB_A0 BB_B0 K2
65033 #define YCM_REG_XX_FREE_TAIL_PTR                                                                     0x1080734UL //Access:R    DataWidth:0x6   Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
65034 #define YCM_REG_XX_NON_LOCK_CNT                                                                      0x1080738UL //Access:R    DataWidth:0x5   Xx NonLock Counter.  Chips: BB_A0 BB_B0 K2
65035 #define YCM_REG_XX_LOCK_CNT                                                                          0x108073cUL //Access:R    DataWidth:0x5   Xx Lock Counter.  Chips: BB_A0 BB_B0 K2
65036 #define YCM_REG_XX_LCID_ARB_GROUP_PR0                                                                0x1080740UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
65037 #define YCM_REG_XX_LCID_ARB_GROUP_PR1                                                                0x1080744UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
65038 #define YCM_REG_XX_LCID_ARB_GROUP_PR2                                                                0x1080748UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
65039 #define YCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                               0x108074cUL //Access:RW   DataWidth:0x8   Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
65040 #define YCM_REG_XX_FREE_THR_HIGH                                                                     0x1080750UL //Access:RW   DataWidth:0x7   Xx free messages threshold high. Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
65041 #define YCM_REG_XX_FREE_THR_LOW                                                                      0x1080754UL //Access:RW   DataWidth:0x7   Xx free messages threshold low Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
65042 #define YCM_REG_XX_CBYP_TBL_FILL_LVL                                                                 0x1080758UL //Access:R    DataWidth:0x4   Xx Connection Bypass Table fill level (in connections).  Chips: BB_A0 BB_B0 K2
65043 #define YCM_REG_XX_CBYP_TBL_ST_STAT                                                                  0x108075cUL //Access:RC   DataWidth:0x4   Xx Connection Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
65044 #define YCM_REG_XX_CBYP_TBL_UP_BND                                                                   0x1080760UL //Access:RW   DataWidth:0x4   Xx Bypass Table (Connection) maximum fill level.  Chips: BB_A0 BB_B0 K2
65045 #define YCM_REG_XX_TBYP_TBL_FILL_LVL                                                                 0x1080764UL //Access:R    DataWidth:0x5   Xx Task Bypass Table fill level (in tasks).  Chips: BB_A0 BB_B0 K2
65046 #define YCM_REG_XX_TBYP_TBL_ST_STAT                                                                  0x1080768UL //Access:RC   DataWidth:0x5   Xx Task Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
65047 #define YCM_REG_XX_TBYP_TBL_UP_BND                                                                   0x108076cUL //Access:RW   DataWidth:0x5   Xx Bypass Table (Task) maximum fill level.  Chips: BB_A0 BB_B0 K2
65048 #define YCM_REG_XX_BYP_MSG_UP_BND_0                                                                  0x1080770UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
65049 #define YCM_REG_XX_BYP_MSG_UP_BND_1                                                                  0x1080774UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
65050 #define YCM_REG_XX_BYP_MSG_UP_BND_2                                                                  0x1080778UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
65051 #define YCM_REG_XX_BYP_MSG_UP_BND_3                                                                  0x108077cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
65052 #define YCM_REG_XX_BYP_MSG_UP_BND_4                                                                  0x1080780UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
65053 #define YCM_REG_XX_BYP_MSG_UP_BND_5                                                                  0x1080784UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
65054 #define YCM_REG_XX_BYP_MSG_UP_BND_6                                                                  0x1080788UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
65055 #define YCM_REG_XX_BYP_MSG_UP_BND_7                                                                  0x108078cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
65056 #define YCM_REG_XX_BYP_LOCK_MSG_THR                                                                  0x1080790UL //Access:RW   DataWidth:0x6   Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.  Chips: BB_A0 BB_B0 K2
65057 #define YCM_REG_XX_PREF_DIR_FILL_LVL                                                                 0x1080794UL //Access:R    DataWidth:0x6   Xx LCID Arbiter direct prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
65058 #define YCM_REG_XX_PREF_AGGST_FILL_LVL                                                               0x1080798UL //Access:R    DataWidth:0x6   Xx LCID Arbiter aggregation store prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
65059 #define YCM_REG_XX_PREF_BYP_FILL_LVL                                                                 0x108079cUL //Access:R    DataWidth:0x6   Xx LCID Arbiter bypass prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
65060 #define YCM_REG_UNLOCK_MISS                                                                          0x10807a0UL //Access:RC   DataWidth:0x1   Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.  Chips: BB_A0 BB_B0 K2
65061 #define YCM_REG_PRCS_AGG_CON_CURR_ST                                                                 0x1080804UL //Access:R    DataWidth:0x4   Aggregation Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
65062 #define YCM_REG_PRCS_SM_CON_CURR_ST                                                                  0x1080808UL //Access:R    DataWidth:0x2   STORM Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
65063 #define YCM_REG_PRCS_AGG_TASK_CURR_ST                                                                0x108080cUL //Access:R    DataWidth:0x4   Aggregation Task Processor FSM.  Chips: BB_A0 BB_B0 K2
65064 #define YCM_REG_PRCS_SM_TASK_CURR_ST                                                                 0x1080810UL //Access:R    DataWidth:0x2   STORM Task Processor FSM.  Chips: BB_A0 BB_B0 K2
65065 #define YCM_REG_N_SM_CON_CTX_LD_0                                                                    0x1080814UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65066 #define YCM_REG_N_SM_CON_CTX_LD_1                                                                    0x1080818UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65067 #define YCM_REG_N_SM_CON_CTX_LD_2                                                                    0x108081cUL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65068 #define YCM_REG_N_SM_CON_CTX_LD_3                                                                    0x1080820UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65069 #define YCM_REG_N_SM_CON_CTX_LD_4                                                                    0x1080824UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65070 #define YCM_REG_N_SM_CON_CTX_LD_5                                                                    0x1080828UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65071 #define YCM_REG_N_SM_CON_CTX_LD_6                                                                    0x108082cUL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65072 #define YCM_REG_N_SM_CON_CTX_LD_7                                                                    0x1080830UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65073 #define YCM_REG_N_SM_TASK_CTX_LD_0                                                                   0x1080834UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65074 #define YCM_REG_N_SM_TASK_CTX_LD_1                                                                   0x1080838UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65075 #define YCM_REG_N_SM_TASK_CTX_LD_2                                                                   0x108083cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65076 #define YCM_REG_N_SM_TASK_CTX_LD_3                                                                   0x1080840UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65077 #define YCM_REG_N_SM_TASK_CTX_LD_4                                                                   0x1080844UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65078 #define YCM_REG_N_SM_TASK_CTX_LD_5                                                                   0x1080848UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65079 #define YCM_REG_N_SM_TASK_CTX_LD_6                                                                   0x108084cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65080 #define YCM_REG_N_SM_TASK_CTX_LD_7                                                                   0x1080850UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65081 #define YCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                             0x1080854UL //Access:R    DataWidth:0x2   Aggregation Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
65082 #define YCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                              0x1080858UL //Access:R    DataWidth:0x4   Storm Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
65083 #define YCM_REG_AGG_CON_FIC_BUF_CRD                                                                  0x108085cUL //Access:RW   DataWidth:0x2   Aggregation Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
65084 #define YCM_REG_SM_CON_FIC_BUF_CRD                                                                   0x1080860UL //Access:RW   DataWidth:0x2   Storm Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
65085 #define YCM_REG_AGG_CON_BUF_CRD_AGG                                                                  0x1080864UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
65086 #define YCM_REG_AGG_CON_BUF_CRD_AGGST                                                                0x1080868UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
65087 #define YCM_REG_SM_CON_BUF_CRD_AGGST                                                                 0x108086cUL //Access:RW   DataWidth:0x1   Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
65088 #define YCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                              0x1080870UL //Access:RW   DataWidth:0x2   Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
65089 #define YCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                               0x1080874UL //Access:RW   DataWidth:0x2   Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
65090 #define YCM_REG_AGG_TASK_FIC_BUF_FILL_LVL                                                            0x1080878UL //Access:R    DataWidth:0x2   Aggregation Task FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
65091 #define YCM_REG_SM_TASK_FIC_BUF_FILL_LVL                                                             0x108087cUL //Access:R    DataWidth:0x5   Storm Task FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
65092 #define YCM_REG_AGG_TASK_FIC_BUF_CRD                                                                 0x1080880UL //Access:RW   DataWidth:0x2   Aggregation Task FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
65093 #define YCM_REG_SM_TASK_FIC_BUF_CRD                                                                  0x1080884UL //Access:RW   DataWidth:0x2   Storm Task FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
65094 #define YCM_REG_AGG_TASK_BUF_CRD_AGG                                                                 0x1080888UL //Access:RW   DataWidth:0x3   Aggregation Task buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
65095 #define YCM_REG_AGG_TASK_BUF_CRD_AGGST                                                               0x108088cUL //Access:RW   DataWidth:0x3   Aggregation Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
65096 #define YCM_REG_SM_TASK_BUF_CRD_AGGST                                                                0x1080890UL //Access:RW   DataWidth:0x1   Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.  Chips: BB_A0 BB_B0 K2
65097 #define YCM_REG_AGG_TASK_CMD_BUF_CRD_DIR                                                             0x1080894UL //Access:RW   DataWidth:0x2   Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
65098 #define YCM_REG_SM_TASK_CMD_BUF_CRD_DIR                                                              0x1080898UL //Access:RW   DataWidth:0x2   Storm Task command buffer credit (Direct group). In sum with CM_REGISTERS_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.  Chips: BB_A0 BB_B0 K2
65099 #define YCM_REG_TRANS_DATA_BUF_CRD_DIR                                                               0x108089cUL //Access:RW   DataWidth:0x2   Transparent data buffer credit (Direct group).  Chips: BB_A0 BB_B0 K2
65100 #define YCM_REG_AGG_CON_CTX_SIZE_0                                                                   0x10808a0UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less or 0.  Chips: BB_A0 BB_B0 K2
65101 #define YCM_REG_AGG_CON_CTX_SIZE_1                                                                   0x10808a4UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.  Chips: BB_A0 BB_B0 K2
65102 #define YCM_REG_AGG_CON_CTX_SIZE_2                                                                   0x10808a8UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.  Chips: BB_A0 BB_B0 K2
65103 #define YCM_REG_AGG_CON_CTX_SIZE_3                                                                   0x10808acUL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.  Chips: BB_A0 BB_B0 K2
65104 #define YCM_REG_AGG_CON_CTX_SIZE_4                                                                   0x10808b0UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.  Chips: BB_A0 BB_B0 K2
65105 #define YCM_REG_AGG_CON_CTX_SIZE_5                                                                   0x10808b4UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.  Chips: BB_A0 BB_B0 K2
65106 #define YCM_REG_AGG_CON_CTX_SIZE_6                                                                   0x10808b8UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.  Chips: BB_A0 BB_B0 K2
65107 #define YCM_REG_AGG_CON_CTX_SIZE_7                                                                   0x10808bcUL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 0. The register values allowed: XCM: 4 REGQ aligned or 0. Other CM: 2 REGQ aligned or 0 aligned whichever is less, or 0.  Chips: BB_A0 BB_B0 K2
65108 #define YCM_REG_AGG_TASK_CTX_SIZE_0                                                                  0x10808c0UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
65109 #define YCM_REG_AGG_TASK_CTX_SIZE_1                                                                  0x10808c4UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
65110 #define YCM_REG_AGG_TASK_CTX_SIZE_2                                                                  0x10808c8UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
65111 #define YCM_REG_AGG_TASK_CTX_SIZE_3                                                                  0x10808ccUL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
65112 #define YCM_REG_AGG_TASK_CTX_SIZE_4                                                                  0x10808d0UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
65113 #define YCM_REG_AGG_TASK_CTX_SIZE_5                                                                  0x10808d4UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
65114 #define YCM_REG_AGG_TASK_CTX_SIZE_6                                                                  0x10808d8UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
65115 #define YCM_REG_AGG_TASK_CTX_SIZE_7                                                                  0x10808dcUL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
65116 #define YCM_REG_SM_CON_CTX_SIZE                                                                      0x10808e0UL //Access:RW   DataWidth:0x4   STORM Connnection context per LCID size (REGQ). Default context size of 3 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 12. Maximum number of LCIDs allowed at maximum context size per LCID is 52. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(3/2))/(12/2)).  Chips: BB_A0 BB_B0 K2
65117 #define YCM_REG_SM_TASK_CTX_SIZE                                                                     0x10808e4UL //Access:RW   DataWidth:0x5   STORM Task context per LTID size (REGQ). Default context size of 12 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 20. Maximum number of LTIDs allowed at maximum context size per LTID is 128. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER((320*INTEGER(12/2))/(20/2)).  Chips: BB_A0 BB_B0 K2
65118 #define YCM_REG_CON_PHY_Q0                                                                           0x1080904UL //Access:RW   DataWidth:0x9   Physical queue connection number (queue number 0).  Chips: BB_A0 BB_B0 K2
65119 #define YCM_REG_CON_PHY_Q1                                                                           0x1080908UL //Access:RW   DataWidth:0x9   Physical queue connection number (queue number 1).  Chips: BB_A0 BB_B0 K2
65120 #define YCM_REG_TASK_PHY_Q0                                                                          0x108090cUL //Access:RW   DataWidth:0x7   Physical queue task number (queue number 0).  Chips: BB_A0 BB_B0 K2
65121 #define YCM_REG_TASK_PHY_Q1                                                                          0x1080910UL //Access:RW   DataWidth:0x7   Physical queue task number (queue number 1).  Chips: BB_A0 BB_B0 K2
65122 #define YCM_REG_AGG_CON_CF0_Q                                                                        0x1080914UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65123 #define YCM_REG_AGG_CON_CF1_Q                                                                        0x1080918UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65124 #define YCM_REG_AGG_CON_CF2_Q                                                                        0x108091cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65125 #define YCM_REG_AGG_CON_RULE0_Q                                                                      0x1080920UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65126 #define YCM_REG_AGG_CON_RULE1_Q                                                                      0x1080924UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65127 #define YCM_REG_AGG_CON_RULE2_Q                                                                      0x1080928UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65128 #define YCM_REG_AGG_CON_RULE3_Q                                                                      0x108092cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65129 #define YCM_REG_AGG_CON_RULE4_Q                                                                      0x1080930UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65130 #define YCM_REG_AGG_TASK_CF0_Q                                                                       0x1080934UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65131 #define YCM_REG_AGG_TASK_CF1_Q                                                                       0x1080938UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65132 #define YCM_REG_AGG_TASK_RULE0_Q                                                                     0x108093cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65133 #define YCM_REG_AGG_TASK_RULE1_Q                                                                     0x1080940UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65134 #define YCM_REG_AGG_TASK_RULE2_Q                                                                     0x1080944UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65135 #define YCM_REG_AGG_TASK_RULE3_Q                                                                     0x1080948UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65136 #define YCM_REG_AGG_TASK_RULE4_Q                                                                     0x108094cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65137 #define YCM_REG_AGG_TASK_RULE5_Q                                                                     0x1080950UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65138 #define YCM_REG_AGG_TASK_RULE6_Q                                                                     0x1080954UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
65139 #define YCM_REG_IN_PRCS_TBL_CRD_AGG                                                                  0x1080a04UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
65140 #define YCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                0x1080a08UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
65141 #define YCM_REG_IN_PRCS_TBL_FILL_LVL                                                                 0x1080a0cUL //Access:R    DataWidth:0x4   In-process Table fill level  (in messages).  Chips: BB_A0 BB_B0 K2
65142 #define YCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                              0x1080a10UL //Access:R    DataWidth:0x1   In-process Table almost full.  Chips: BB_A0 BB_B0 K2
65143 #define YCM_REG_QMCON_CURR_ST                                                                        0x1080a14UL //Access:R    DataWidth:0x3   QM connection registration FSM current state.  Chips: BB_A0 BB_B0 K2
65144 #define YCM_REG_QMTASK_CURR_ST                                                                       0x1080a18UL //Access:R    DataWidth:0x3   QM task registration FSM current state.  Chips: BB_A0 BB_B0 K2
65145 #define YCM_REG_CCFC_CURR_ST                                                                         0x1080a1cUL //Access:R    DataWidth:0x1   CFC connection output FSM current state.  Chips: BB_A0 BB_B0 K2
65146 #define YCM_REG_TCFC_CURR_ST                                                                         0x1080a20UL //Access:R    DataWidth:0x1   CFC task output FSM current state.  Chips: BB_A0 BB_B0 K2
65147 #define YCM_REG_CMPL_DIR_CURR_ST                                                                     0x1080a24UL //Access:R    DataWidth:0x4   Direct Completer FSM current state.  Chips: BB_A0 BB_B0 K2
65148 #define YCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                         0x1080a28UL //Access:RW   DataWidth:0x1   If set, Xx connection bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
65149 #define YCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG                                                        0x1080a2cUL //Access:RW   DataWidth:0x1   If set, Xx task bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
65150 #define YCM_REG_CCFC_INIT_CRD                                                                        0x1080a84UL //Access:RW   DataWidth:0x4   CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
65151 #define YCM_REG_TCFC_INIT_CRD                                                                        0x1080a88UL //Access:RW   DataWidth:0x4   TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
65152 #define YCM_REG_QM_INIT_CRD0                                                                         0x1080a8cUL //Access:RW   DataWidth:0x5   QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
65153 #define YCM_REG_TCFC_INCLOCK_INIT_CRD                                                                0x1080a90UL //Access:RW   DataWidth:0x1   TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
65154 #define YCM_REG_TCFC_DEC_INIT_CRD                                                                    0x1080a94UL //Access:RW   DataWidth:0x3   TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
65155 #define YCM_REG_FIC_INIT_CRD                                                                         0x1080a98UL //Access:RW   DataWidth:0x6   FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.  Chips: BB_A0 BB_B0 K2
65156 #define YCM_REG_DIR_BYP_MSG_CNT                                                                      0x1080aa4UL //Access:RC   DataWidth:0x20  Counter of direct bypassed messages.  Chips: BB_A0 BB_B0 K2
65157 #define YCM_REG_MSDM_LENGTH_MIS                                                                      0x1080aa8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at MSDM interface.  Chips: BB_A0 BB_B0 K2
65158 #define YCM_REG_YSDM_LENGTH_MIS                                                                      0x1080aacUL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at YSDM interface.  Chips: BB_A0 BB_B0 K2
65159 #define YCM_REG_PBF_LENGTH_MIS                                                                       0x1080ab0UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at PBF interface.  Chips: BB_A0 BB_B0 K2
65160 #define YCM_REG_XYLD_LENGTH_MIS                                                                      0x1080ab4UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at XYLD interface.  Chips: BB_A0 BB_B0 K2
65161 #define YCM_REG_GRC_BUF_EMPTY                                                                        0x1080ab8UL //Access:R    DataWidth:0x1   Input Stage GRC buffer is empty.  Chips: BB_A0 BB_B0 K2
65162 #define YCM_REG_GRC_BUF_STATUS                                                                       0x1080abcUL //Access:R    DataWidth:0x6   Input Stage GRC buffer status.  Chips: BB_A0 BB_B0 K2
65163 #define YCM_REG_STORM_MSG_CNTR                                                                       0x1080ac0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the STORM input.  Chips: BB_A0 BB_B0 K2
65164 #define YCM_REG_MSDM_MSG_CNTR                                                                        0x1080ac4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input MSDM.  Chips: BB_A0 BB_B0 K2
65165 #define YCM_REG_YSDM_MSG_CNTR                                                                        0x1080ac8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input YSDM.  Chips: BB_A0 BB_B0 K2
65166 #define YCM_REG_XYLD_MSG_CNTR                                                                        0x1080accUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input XYLD.  Chips: BB_A0 BB_B0 K2
65167 #define YCM_REG_MSEM_MSG_CNTR                                                                        0x1080ad0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input MSEM.  Chips: BB_A0 BB_B0 K2
65168 #define YCM_REG_USEM_MSG_CNTR                                                                        0x1080ad4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input USEM.  Chips: BB_A0 BB_B0 K2
65169 #define YCM_REG_PBF_MSG_CNTR                                                                         0x1080ad8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input PBF.  Chips: BB_A0 BB_B0 K2
65170 #define YCM_REG_QM_P_MSG_CNTR                                                                        0x1080adcUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (primary).  Chips: BB_A0 BB_B0 K2
65171 #define YCM_REG_QM_S_MSG_CNTR                                                                        0x1080ae0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (secondary).  Chips: BB_A0 BB_B0 K2
65172 #define YCM_REG_IS_GRC                                                                               0x1080ae4UL //Access:W    DataWidth:0x20  Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done  Chips: BB_A0 BB_B0 K2
65173 #define YCM_REG_IS_QM_P_FILL_LVL                                                                     0x1080ae8UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
65174 #define YCM_REG_IS_QM_S_FILL_LVL                                                                     0x1080aecUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
65175 #define YCM_REG_IS_STORM_FILL_LVL                                                                    0x1080af0UL //Access:R    DataWidth:0x6   Number of QREGs (128b) of data in STORM Input Stage.  Chips: BB_A0 BB_B0 K2
65176 #define YCM_REG_IS_MSDM_FILL_LVL                                                                     0x1080af4UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in MSDM Input Stage.  Chips: BB_A0 BB_B0 K2
65177 #define YCM_REG_IS_YSDM_FILL_LVL                                                                     0x1080af8UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in YSDM Input Stage.  Chips: BB_A0 BB_B0 K2
65178 #define YCM_REG_IS_XYLD_FILL_LVL                                                                     0x1080afcUL //Access:R    DataWidth:0x5   Number of QREGs (128b) of data in XYLD Input Stage.  Chips: BB_A0 BB_B0 K2
65179 #define YCM_REG_IS_MSEM_FILL_LVL                                                                     0x1080b00UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in MSEM Input Stage.  Chips: BB_A0 BB_B0 K2
65180 #define YCM_REG_IS_USEM_FILL_LVL                                                                     0x1080b04UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in USEM Input Stage.  Chips: BB_A0 BB_B0 K2
65181 #define YCM_REG_IS_PBF_FILL_LVL                                                                      0x1080b08UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in PBF Input Stage.  Chips: BB_A0 BB_B0 K2
65182 #define YCM_REG_FIC_MSG_CNTR                                                                         0x1080b44UL //Access:RC   DataWidth:0x1c  Counter of the output messages at FIC interfaces.  Chips: BB_A0 BB_B0 K2
65183 #define YCM_REG_QM_OUT_CNTR                                                                          0x1080b48UL //Access:RC   DataWidth:0x1c  Counter of the output QM commands.  Chips: BB_A0 BB_B0 K2
65184 #define YCM_REG_DONE0_CNTR                                                                           0x1080b4cUL //Access:RC   DataWidth:0x1c  Counter of the output Done0.  Chips: BB_A0 BB_B0 K2
65185 #define YCM_REG_DONE1_CNTR                                                                           0x1080b50UL //Access:RC   DataWidth:0x1c  Counter of the output Done1.  Chips: BB_A0 BB_B0 K2
65186 #define YCM_REG_DONE2_CNTR                                                                           0x1080b54UL //Access:RC   DataWidth:0x1c  Counter of the output Done2.  Chips: BB_A0 BB_B0 K2
65187 #define YCM_REG_DONE3_CNTR                                                                           0x1080b58UL //Access:RC   DataWidth:0x1c  Counter of the output Done3.  Chips: BB_A0 BB_B0 K2
65188 #define YCM_REG_CCFC_CNTR                                                                            0x1080b5cUL //Access:RC   DataWidth:0x1c  Counter of the output CCFC.  Chips: BB_A0 BB_B0 K2
65189 #define YCM_REG_TCFC_CNTR                                                                            0x1080b60UL //Access:RC   DataWidth:0x1c  Counter of the output TCFC.  Chips: BB_A0 BB_B0 K2
65190 #define YCM_REG_ECO_RESERVED                                                                         0x1080b84UL //Access:RW   DataWidth:0x8   Chicken bits.  Chips: BB_A0 BB_B0 K2
65191 #define YCM_REG_IS_FOC_MSEM_NXT_INF_UNIT                                                             0x1080b88UL //Access:R    DataWidth:0x6   Debug read from MSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65192 #define YCM_REG_IS_FOC_USEM_NXT_INF_UNIT                                                             0x1080b8cUL //Access:R    DataWidth:0x6   Debug read from USEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65193 #define YCM_REG_IS_FOC_YSEM_NXT_INF_UNIT                                                             0x1080b90UL //Access:R    DataWidth:0x6   Debug read from YSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65194 #define YCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                              0x1080b94UL //Access:R    DataWidth:0x6   Debug read from PBF Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65195 #define YCM_REG_IS_FOC_MSDM_NXT_INF_UNIT                                                             0x1080b98UL //Access:R    DataWidth:0x6   Debug read from MSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65196 #define YCM_REG_IS_FOC_YSDM_NXT_INF_UNIT                                                             0x1080b9cUL //Access:R    DataWidth:0x6   Debug read from YSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65197 #define YCM_REG_IS_FOC_XYLD_NXT_INF_UNIT                                                             0x1080ba0UL //Access:R    DataWidth:0x6   Debug read from XYLD Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65198 #define YCM_REG_IS_FOC_MSEM                                                                          0x1080c00UL //Access:R    DataWidth:0x20  Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65199 #define YCM_REG_IS_FOC_MSEM_SIZE                                                                     32
65200 #define YCM_REG_IS_FOC_USEM                                                                          0x1080c80UL //Access:R    DataWidth:0x20  Debug read from USEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65201 #define YCM_REG_IS_FOC_USEM_SIZE                                                                     12
65202 #define YCM_REG_IS_FOC_YSEM                                                                          0x1081000UL //Access:R    DataWidth:0x20  Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65203 #define YCM_REG_IS_FOC_YSEM_SIZE                                                                     156
65204 #define YCM_REG_IS_FOC_PBF                                                                           0x1081400UL //Access:R    DataWidth:0x20  Debug read from PBF Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65205 #define YCM_REG_IS_FOC_PBF_SIZE                                                                      24
65206 #define YCM_REG_IS_FOC_MSDM                                                                          0x1081480UL //Access:R    DataWidth:0x20  Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65207 #define YCM_REG_IS_FOC_MSDM_SIZE                                                                     20
65208 #define YCM_REG_IS_FOC_YSDM                                                                          0x1081500UL //Access:R    DataWidth:0x20  Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65209 #define YCM_REG_IS_FOC_YSDM_SIZE                                                                     16
65210 #define YCM_REG_IS_FOC_XYLD                                                                          0x1081600UL //Access:R    DataWidth:0x20  Debug read from XYLD Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65211 #define YCM_REG_IS_FOC_XYLD_SIZE                                                                     116
65212 #define YCM_REG_CTX_RBC_ACCS                                                                         0x1081800UL //Access:RW   DataWidth:0x10  Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX  Chips: BB_A0 BB_B0 K2
65213 #define YCM_REG_AGG_CON_CTX                                                                          0x1081804UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
65214 #define YCM_REG_AGG_TASK_CTX                                                                         0x1081808UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
65215 #define YCM_REG_SM_CON_CTX                                                                           0x108180cUL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
65216 #define YCM_REG_SM_TASK_CTX                                                                          0x1081810UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
65217 #define YCM_REG_XX_CBYP_TBL                                                                          0x1081820UL //Access:R    DataWidth:0xf   Xx Connection Bypass Table.  Chips: BB_A0 BB_B0 K2
65218 #define YCM_REG_XX_CBYP_TBL_SIZE                                                                     8
65219 #define YCM_REG_XX_TBYP_TBL                                                                          0x1081900UL //Access:R    DataWidth:0xf   Xx Task Bypass Table.  Chips: BB_A0 BB_B0 K2
65220 #define YCM_REG_XX_TBYP_TBL_SIZE                                                                     22
65221 #define YCM_REG_XX_LCID_CAM                                                                          0x1081a00UL //Access:R    DataWidth:0xa   Debug only. Read only access to LCID CAM in XX protection mechanism.  Chips: BB_A0 BB_B0 K2
65222 #define YCM_REG_XX_LCID_CAM_SIZE                                                                     22
65223 #define YCM_REG_XX_TBL                                                                               0x1081b00UL //Access:R    DataWidth:0x17  Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [3:1] - Connection type; LL size: PCM - [6:4]; M/T/U/X/YCM - [10:4]; Tail pointer: PCM - [8:7]; M/T/U/X/YCM - [16:11]; Next pointer: PCM - [10:9]; M/T/U/X/YCM - [22:17];  Chips: BB_A0 BB_B0 K2
65224 #define YCM_REG_XX_TBL_SIZE                                                                          22
65225 #define YCM_REG_XX_DSCR_TBL                                                                          0x1081c00UL //Access:RW   DataWidth:0x1e  Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.  Chips: BB_A0 BB_B0 K2
65226 #define YCM_REG_XX_DSCR_TBL_SIZE                                                                     64
65227 #define YCM_REG_XX_MSG_RAM                                                                           0x1088000UL //Access:R    DataWidth:0x20  Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.  Chips: BB_A0 BB_B0 K2
65228 #define YCM_REG_XX_MSG_RAM_SIZE                                                                      6240
65229 #define PCM_REG_INIT                                                                                 0x1100000UL //Access:RW   DataWidth:0x1   Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.  Chips: BB_A0 BB_B0 K2
65230 #define PCM_REG_DBG_SELECT                                                                           0x1100040UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
65231 #define PCM_REG_DBG_DWORD_ENABLE                                                                     0x1100044UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
65232 #define PCM_REG_DBG_SHIFT                                                                            0x1100048UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
65233 #define PCM_REG_DBG_FORCE_VALID                                                                      0x110004cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
65234 #define PCM_REG_DBG_FORCE_FRAME                                                                      0x1100050UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
65235 #define PCM_REG_DBG_OUT_DATA                                                                         0x1100060UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
65236 #define PCM_REG_DBG_OUT_DATA_SIZE                                                                    8
65237 #define PCM_REG_DBG_OUT_VALID                                                                        0x1100080UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
65238 #define PCM_REG_DBG_OUT_FRAME                                                                        0x1100084UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
65239 #define PCM_REG_INT_STS_0                                                                            0x1100180UL //Access:R    DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65240     #define PCM_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
65241     #define PCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
65242     #define PCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                      (0x1<<1) // Write to full STORM input buffer.
65243     #define PCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                1
65244     #define PCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                     (0x1<<2) // Read from empty  STORM input buffer.
65245     #define PCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                               2
65246     #define PCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR                                                       (0x1<<3) // Write to full TSDM input buffer.
65247     #define PCM_REG_INT_STS_0_IS_PSDM_OVFL_ERR_SHIFT                                                 3
65248     #define PCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR                                                      (0x1<<4) // Read from empty TSDM input buffer.
65249     #define PCM_REG_INT_STS_0_IS_PSDM_UNDER_ERR_SHIFT                                                4
65250 #define PCM_REG_INT_MASK_0                                                                           0x1100184UL //Access:RW   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65251     #define PCM_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.ADDRESS_ERROR .
65252     #define PCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
65253     #define PCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
65254     #define PCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                               1
65255     #define PCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
65256     #define PCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                              2
65257     #define PCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_PSDM_OVFL_ERR .
65258     #define PCM_REG_INT_MASK_0_IS_PSDM_OVFL_ERR_SHIFT                                                3
65259     #define PCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_0.IS_PSDM_UNDER_ERR .
65260     #define PCM_REG_INT_MASK_0_IS_PSDM_UNDER_ERR_SHIFT                                               4
65261 #define PCM_REG_INT_STS_WR_0                                                                         0x1100188UL //Access:WR   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65262     #define PCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
65263     #define PCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
65264     #define PCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                   (0x1<<1) // Write to full STORM input buffer.
65265     #define PCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                             1
65266     #define PCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                  (0x1<<2) // Read from empty  STORM input buffer.
65267     #define PCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                            2
65268     #define PCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR                                                    (0x1<<3) // Write to full TSDM input buffer.
65269     #define PCM_REG_INT_STS_WR_0_IS_PSDM_OVFL_ERR_SHIFT                                              3
65270     #define PCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR                                                   (0x1<<4) // Read from empty TSDM input buffer.
65271     #define PCM_REG_INT_STS_WR_0_IS_PSDM_UNDER_ERR_SHIFT                                             4
65272 #define PCM_REG_INT_STS_CLR_0                                                                        0x110018cUL //Access:RC   DataWidth:0x5   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65273     #define PCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
65274     #define PCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
65275     #define PCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                  (0x1<<1) // Write to full STORM input buffer.
65276     #define PCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                            1
65277     #define PCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                 (0x1<<2) // Read from empty  STORM input buffer.
65278     #define PCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                           2
65279     #define PCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR                                                   (0x1<<3) // Write to full TSDM input buffer.
65280     #define PCM_REG_INT_STS_CLR_0_IS_PSDM_OVFL_ERR_SHIFT                                             3
65281     #define PCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR                                                  (0x1<<4) // Read from empty TSDM input buffer.
65282     #define PCM_REG_INT_STS_CLR_0_IS_PSDM_UNDER_ERR_SHIFT                                            4
65283 #define PCM_REG_INT_STS_1                                                                            0x1100190UL //Access:R    DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65284     #define PCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                        (0x1<<0) // Write to full Pbf input buffer.
65285     #define PCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                  0
65286     #define PCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                       (0x1<<1) // Read from empty Pbf input buffer.
65287     #define PCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                 1
65288     #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                       (0x1<<2) // Write to full GRC input buffer bits [31:0].
65289     #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                 2
65290     #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                      (0x1<<3) // Read from empty  GRC input buffer bits [31:0].
65291     #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                3
65292     #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                       (0x1<<4) // Write to full GRC input buffer bits [63:32].
65293     #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                 4
65294     #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                      (0x1<<5) // Read from empty  GRC input buffer bits [63:32].
65295     #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                5
65296     #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                       (0x1<<6) // Write to full GRC input buffer bits [95:64].
65297     #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                 6
65298     #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                      (0x1<<7) // Read from empty  GRC input buffer bits [95:64].
65299     #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                7
65300     #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                       (0x1<<8) // Write to full GRC input buffer bits [127:96].
65301     #define PCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                 8
65302     #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                      (0x1<<9) // Read from empty  GRC input buffer bits [127:96].
65303     #define PCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                9
65304     #define PCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                       (0x1<<10) // In-process Table overflow.
65305     #define PCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                 10
65306     #define PCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                   (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
65307     #define PCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                             11
65308     #define PCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                    (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
65309     #define PCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                              12
65310     #define PCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                  (0x1<<13) // Input message first descriptor fields violation.
65311     #define PCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                            13
65312 #define PCM_REG_INT_MASK_1                                                                           0x1100194UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65313     #define PCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                       (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
65314     #define PCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                 0
65315     #define PCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
65316     #define PCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                1
65317     #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
65318     #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                2
65319     #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                     (0x1<<3) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
65320     #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                               3
65321     #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
65322     #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                4
65323     #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                     (0x1<<5) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
65324     #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                               5
65325     #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
65326     #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                6
65327     #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
65328     #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                               7
65329     #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
65330     #define PCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                8
65331     #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
65332     #define PCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                               9
65333     #define PCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
65334     #define PCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                10
65335     #define PCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
65336     #define PCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                            11
65337     #define PCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                   (0x1<<12) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
65338     #define PCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                             12
65339     #define PCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                 (0x1<<13) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
65340     #define PCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                           13
65341 #define PCM_REG_INT_STS_WR_1                                                                         0x1100198UL //Access:WR   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65342     #define PCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                     (0x1<<0) // Write to full Pbf input buffer.
65343     #define PCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                               0
65344     #define PCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                    (0x1<<1) // Read from empty Pbf input buffer.
65345     #define PCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                              1
65346     #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                    (0x1<<2) // Write to full GRC input buffer bits [31:0].
65347     #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                              2
65348     #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                   (0x1<<3) // Read from empty  GRC input buffer bits [31:0].
65349     #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                             3
65350     #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                    (0x1<<4) // Write to full GRC input buffer bits [63:32].
65351     #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                              4
65352     #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                   (0x1<<5) // Read from empty  GRC input buffer bits [63:32].
65353     #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                             5
65354     #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                    (0x1<<6) // Write to full GRC input buffer bits [95:64].
65355     #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                              6
65356     #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                   (0x1<<7) // Read from empty  GRC input buffer bits [95:64].
65357     #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                             7
65358     #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                    (0x1<<8) // Write to full GRC input buffer bits [127:96].
65359     #define PCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                              8
65360     #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                   (0x1<<9) // Read from empty  GRC input buffer bits [127:96].
65361     #define PCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                             9
65362     #define PCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                    (0x1<<10) // In-process Table overflow.
65363     #define PCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                              10
65364     #define PCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
65365     #define PCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                          11
65366     #define PCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                 (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
65367     #define PCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                           12
65368     #define PCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                               (0x1<<13) // Input message first descriptor fields violation.
65369     #define PCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                         13
65370 #define PCM_REG_INT_STS_CLR_1                                                                        0x110019cUL //Access:RC   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65371     #define PCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                    (0x1<<0) // Write to full Pbf input buffer.
65372     #define PCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                              0
65373     #define PCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                   (0x1<<1) // Read from empty Pbf input buffer.
65374     #define PCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                             1
65375     #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                   (0x1<<2) // Write to full GRC input buffer bits [31:0].
65376     #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                             2
65377     #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                  (0x1<<3) // Read from empty  GRC input buffer bits [31:0].
65378     #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                            3
65379     #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                   (0x1<<4) // Write to full GRC input buffer bits [63:32].
65380     #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                             4
65381     #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                  (0x1<<5) // Read from empty  GRC input buffer bits [63:32].
65382     #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                            5
65383     #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                   (0x1<<6) // Write to full GRC input buffer bits [95:64].
65384     #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                             6
65385     #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                  (0x1<<7) // Read from empty  GRC input buffer bits [95:64].
65386     #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                            7
65387     #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                   (0x1<<8) // Write to full GRC input buffer bits [127:96].
65388     #define PCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                             8
65389     #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                  (0x1<<9) // Read from empty  GRC input buffer bits [127:96].
65390     #define PCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                            9
65391     #define PCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                   (0x1<<10) // In-process Table overflow.
65392     #define PCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                             10
65393     #define PCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                               (0x1<<11) // Message Processor Storm Connection Data buffer overflow.
65394     #define PCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                         11
65395     #define PCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                (0x1<<12) // Message Processor Storm Connection Command buffer overflow.
65396     #define PCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                          12
65397     #define PCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                              (0x1<<13) // Input message first descriptor fields violation.
65398     #define PCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                        13
65399 #define PCM_REG_INT_STS_2                                                                            0x11001a0UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65400     #define PCM_REG_INT_STS_2_QMREG_MORE4                                                            (0x1<<0) // More than 4 QM registrations.
65401     #define PCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                      0
65402 #define PCM_REG_INT_MASK_2                                                                           0x11001a4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65403     #define PCM_REG_INT_MASK_2_QMREG_MORE4                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: PCM_REG_INT_STS_2.QMREG_MORE4 .
65404     #define PCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                     0
65405 #define PCM_REG_INT_STS_WR_2                                                                         0x11001a8UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65406     #define PCM_REG_INT_STS_WR_2_QMREG_MORE4                                                         (0x1<<0) // More than 4 QM registrations.
65407     #define PCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                   0
65408 #define PCM_REG_INT_STS_CLR_2                                                                        0x11001acUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65409     #define PCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                        (0x1<<0) // More than 4 QM registrations.
65410     #define PCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                  0
65411 #define PCM_REG_PRTY_MASK_H_0                                                                        0x1100204UL //Access:RW   DataWidth:0xc   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65412     #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM012_I_ECC_RF_INT .
65413     #define PCM_REG_PRTY_MASK_H_0_MEM012_I_ECC_RF_INT_SHIFT                                          0
65414     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_0_RF_INT                                              (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_ECC_0_RF_INT .
65415     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_0_RF_INT_SHIFT                                        1
65416     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_1_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_ECC_1_RF_INT .
65417     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_ECC_1_RF_INT_SHIFT                                        2
65418     #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
65419     #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                      12
65420     #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                               (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
65421     #define PCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                         3
65422     #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
65423     #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_A0_SHIFT                                      3
65424     #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0                                            (0x1<<3) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
65425     #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_BB_B0_SHIFT                                      3
65426     #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2                                               (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
65427     #define PCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_K2_SHIFT                                         4
65428     #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
65429     #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                      4
65430     #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                            (0x1<<4) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
65431     #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                      4
65432     #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
65433     #define PCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                         5
65434     #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0                                            (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
65435     #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                      5
65436     #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0                                            (0x1<<5) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
65437     #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                      5
65438     #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
65439     #define PCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_K2_SHIFT                                         6
65440     #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0                                            (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
65441     #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_A0_SHIFT                                      6
65442     #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0                                            (0x1<<6) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
65443     #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_BB_B0_SHIFT                                      6
65444     #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2                                               (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
65445     #define PCM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_K2_SHIFT                                         7
65446     #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0                                            (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
65447     #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0_SHIFT                                      7
65448     #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0                                            (0x1<<7) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
65449     #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0_SHIFT                                      7
65450     #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                               (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
65451     #define PCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                         8
65452     #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0                                            (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
65453     #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_A0_SHIFT                                      8
65454     #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0                                            (0x1<<8) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
65455     #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_BB_B0_SHIFT                                      8
65456     #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
65457     #define PCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_K2_SHIFT                                         9
65458     #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
65459     #define PCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                            10
65460     #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
65461     #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_A0_SHIFT                                      13
65462     #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
65463     #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                      10
65464     #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
65465     #define PCM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_K2_SHIFT                                         11
65466     #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM011_I_ECC_RF_INT .
65467     #define PCM_REG_PRTY_MASK_H_0_MEM011_I_ECC_RF_INT_SHIFT                                          0
65468     #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT                                              (0x1<<1) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_ECC_0_RF_INT .
65469     #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_0_RF_INT_SHIFT                                        1
65470     #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM009_I_ECC_1_RF_INT .
65471     #define PCM_REG_PRTY_MASK_H_0_MEM009_I_ECC_1_RF_INT_SHIFT                                        2
65472     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
65473     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0_SHIFT                                      11
65474     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
65475     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0_SHIFT                                      9
65476     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
65477     #define PCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT                                         9
65478     #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY                                                  (0x1<<9) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
65479     #define PCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_SHIFT                                            9
65480     #define PCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                                  (0x1<<10) // This bit masks, when set, the Parity bit: PCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
65481     #define PCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                            10
65482 #define PCM_REG_MEM_ECC_EVENTS                                                                       0x1100224UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
65483 #define PCM_REG_MEM008_I_MEM_DFT_K2                                                                  0x110022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_is_storm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65484 #define PCM_REG_MEM006_I_MEM_DFT_K2                                                                  0x1100230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_is_pbf_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65485 #define PCM_REG_MEM002_I_MEM_DFT_K2                                                                  0x1100234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_is_grc0_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65486 #define PCM_REG_MEM003_I_MEM_DFT_K2                                                                  0x1100238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_is_grc1_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65487 #define PCM_REG_MEM004_I_MEM_DFT_K2                                                                  0x110023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_is_grc2_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65488 #define PCM_REG_MEM005_I_MEM_DFT_K2                                                                  0x1100240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_is_grc3_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65489 #define PCM_REG_MEM012_I_MEM_DFT_K2                                                                  0x1100244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_xx_msg_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
65490 #define PCM_REG_MEM014_I_MEM_DFT_K2                                                                  0x1100248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_xx_pref_dir.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65491 #define PCM_REG_MEM013_I_MEM_DFT_K2                                                                  0x110024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_xx_pref_aggst.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65492 #define PCM_REG_MEM011_I_MEM_DFT_K2                                                                  0x1100250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_sm_con_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65493 #define PCM_REG_MEM010_I_MEM_DFT_K2                                                                  0x1100254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_sm_con_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
65494 #define PCM_REG_MEM009_I_MEM_DFT_K2                                                                  0x1100258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_prcs_trans_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65495 #define PCM_REG_MEM001_I_MEM_DFT_K2                                                                  0x110025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance pcm.i_in_prcs_msgin.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
65496 #define PCM_REG_IFEN                                                                                 0x1100400UL //Access:RW   DataWidth:0x1   Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
65497 #define PCM_REG_ERR_EVNT_ID                                                                          0x1100404UL //Access:RW   DataWidth:0x8   The Event ID in case one of errors is set in QM input message.  Chips: BB_A0 BB_B0 K2
65498 #define PCM_REG_STORM_WEIGHT                                                                         0x1100604UL //Access:RW   DataWidth:0x3   The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
65499 #define PCM_REG_PBF_WEIGHT                                                                           0x1100608UL //Access:RW   DataWidth:0x3   The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
65500 #define PCM_REG_GRC_WEIGHT                                                                           0x110060cUL //Access:RW   DataWidth:0x3   The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
65501 #define PCM_REG_PSDM_WEIGHT                                                                          0x1100610UL //Access:RW   DataWidth:0x3   The weight of the input PSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
65502 #define PCM_REG_IA_GROUP_PR0                                                                         0x1100614UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65503 #define PCM_REG_IA_GROUP_PR1                                                                         0x1100618UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65504 #define PCM_REG_IA_GROUP_PR2                                                                         0x110061cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65505 #define PCM_REG_IA_GROUP_PR3                                                                         0x1100620UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65506 #define PCM_REG_IA_GROUP_PR4                                                                         0x1100624UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65507 #define PCM_REG_IA_GROUP_PR5                                                                         0x1100628UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
65508 #define PCM_REG_IA_ARB_SP_TIMEOUT                                                                    0x110062cUL //Access:RW   DataWidth:0x8   Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority.  Chips: BB_A0 BB_B0 K2
65509 #define PCM_REG_STORM_FRWRD_MODE                                                                     0x1100630UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65510 #define PCM_REG_PSDM_FRWRD_MODE                                                                      0x1100634UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65511 #define PCM_REG_PBF_FRWRD_MODE                                                                       0x1100638UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
65512 #define PCM_REG_SDM_ERR_HANDLE_EN                                                                    0x110063cUL //Access:RW   DataWidth:0x1   0 - disable error handling in SDM message; 1 - enable error handling in SDM message.  Chips: BB_A0 BB_B0 K2
65513 #define PCM_REG_DIR_BYP_EN                                                                           0x1100640UL //Access:RW   DataWidth:0x1   Direct bypass enable.  Chips: BB_A0 BB_B0 K2
65514 #define PCM_REG_FI_DESC_INPUT_VIOLATE                                                                0x1100644UL //Access:R    DataWidth:0x10  Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: XxBypass message in PCM block;  Chips: BB_A0 BB_B0 K2
65515 #define PCM_REG_IA_SM_CON_PART_FILL_LVL                                                              0x1100648UL //Access:R    DataWidth:0x3   Input Arbiter Storm Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
65516 #define PCM_REG_IA_TRANS_PART_FILL_LVL                                                               0x110064cUL //Access:R    DataWidth:0x3   Input Arbiter Transparent part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
65517 #define PCM_REG_XX_MSG_UP_BND                                                                        0x1100704UL //Access:RW   DataWidth:0x3   The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the siz of Xx protected message CM_REGISTERS_XX_MSG_SIZE_BND.XX_MSG_SIZE_BND  Chips: BB_A0 BB_B0 K2
65518 #define PCM_REG_XX_MSG_SIZE                                                                          0x1100708UL //Access:RW   DataWidth:0x8   The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to even number and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1664 PCM: 0d176 TCM: 0d1408 UCM: 0d1664 XCM: 0d256 YCM: 0d1536  Chips: BB_A0 BB_B0 K2
65519 #define PCM_REG_XX_LCID_CAM_UP_BND                                                                   0x110070cUL //Access:RW   DataWidth:0x2   The maximum number of connections in the XX protection LCID CAM.  Chips: BB_A0 BB_B0 K2
65520 #define PCM_REG_XX_FREE_CNT                                                                          0x1100710UL //Access:R    DataWidth:0x3   Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
65521 #define PCM_REG_XX_LCID_CAM_FILL_LVL                                                                 0x1100714UL //Access:R    DataWidth:0x2   Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.  Chips: BB_A0 BB_B0 K2
65522 #define PCM_REG_XX_LCID_CAM_ST_STAT                                                                  0x1100718UL //Access:RC   DataWidth:0x2   CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.  Chips: BB_A0 BB_B0 K2
65523 #define PCM_REG_XX_IA_GROUP_PR0                                                                      0x110071cUL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
65524 #define PCM_REG_XX_IA_GROUP_PR1                                                                      0x1100720UL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
65525 #define PCM_REG_XX_NON_LOCK_LCID_THR                                                                 0x1100724UL //Access:RW   DataWidth:0x2   Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.  Chips: BB_A0 BB_B0 K2
65526 #define PCM_REG_XX_LOCK_LCID_THR                                                                     0x1100728UL //Access:RW   DataWidth:0x2   Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.  Chips: BB_A0 BB_B0 K2
65527 #define PCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                 0x110072cUL //Access:RW   DataWidth:0x8   Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
65528 #define PCM_REG_XX_FREE_HEAD_PTR                                                                     0x1100730UL //Access:R    DataWidth:0x2   Xx Free Head Pointer.  Chips: BB_A0 BB_B0 K2
65529 #define PCM_REG_XX_FREE_TAIL_PTR                                                                     0x1100734UL //Access:R    DataWidth:0x2   Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
65530 #define PCM_REG_XX_NON_LOCK_CNT                                                                      0x1100738UL //Access:R    DataWidth:0x2   Xx NonLock Counter.  Chips: BB_A0 BB_B0 K2
65531 #define PCM_REG_XX_LOCK_CNT                                                                          0x110073cUL //Access:R    DataWidth:0x2   Xx Lock Counter.  Chips: BB_A0 BB_B0 K2
65532 #define PCM_REG_XX_LCID_ARB_GROUP_PR0                                                                0x1100740UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
65533 #define PCM_REG_XX_LCID_ARB_GROUP_PR1                                                                0x1100744UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
65534 #define PCM_REG_XX_LCID_ARB_GROUP_PR2                                                                0x1100748UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
65535 #define PCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                               0x110074cUL //Access:RW   DataWidth:0x8   Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
65536 #define PCM_REG_XX_FREE_THR_HIGH                                                                     0x1100750UL //Access:RW   DataWidth:0x3   Xx free messages threshold high. Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
65537 #define PCM_REG_XX_FREE_THR_LOW                                                                      0x1100754UL //Access:RW   DataWidth:0x3   Xx free messages threshold low Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
65538 #define PCM_REG_XX_PREF_DIR_FILL_LVL                                                                 0x1100758UL //Access:R    DataWidth:0x7   Xx LCID Arbiter direct prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
65539 #define PCM_REG_XX_PREF_AGGST_FILL_LVL                                                               0x110075cUL //Access:R    DataWidth:0x7   Xx LCID Arbiter aggregation store prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
65540 #define PCM_REG_UNLOCK_MISS                                                                          0x1100760UL //Access:RC   DataWidth:0x1   Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.  Chips: BB_A0 BB_B0 K2
65541 #define PCM_REG_PRCS_SM_CON_CURR_ST                                                                  0x1100804UL //Access:R    DataWidth:0x2   STORM Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
65542 #define PCM_REG_N_SM_CON_CTX_LD_0                                                                    0x1100808UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65543 #define PCM_REG_N_SM_CON_CTX_LD_1                                                                    0x110080cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65544 #define PCM_REG_N_SM_CON_CTX_LD_2                                                                    0x1100810UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65545 #define PCM_REG_N_SM_CON_CTX_LD_3                                                                    0x1100814UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65546 #define PCM_REG_N_SM_CON_CTX_LD_4                                                                    0x1100818UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65547 #define PCM_REG_N_SM_CON_CTX_LD_5                                                                    0x110081cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65548 #define PCM_REG_N_SM_CON_CTX_LD_6                                                                    0x1100820UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65549 #define PCM_REG_N_SM_CON_CTX_LD_7                                                                    0x1100824UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
65550 #define PCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                              0x1100828UL //Access:R    DataWidth:0x5   Storm Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
65551 #define PCM_REG_SM_CON_FIC_BUF_CRD                                                                   0x110082cUL //Access:RW   DataWidth:0x2   Storm Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
65552 #define PCM_REG_SM_CON_BUF_CRD_AGGST                                                                 0x1100830UL //Access:RW   DataWidth:0x1   Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
65553 #define PCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                               0x1100834UL //Access:RW   DataWidth:0x2   Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
65554 #define PCM_REG_TRANS_DATA_BUF_CRD_DIR                                                               0x1100838UL //Access:RW   DataWidth:0x2   Transparent data buffer credit (Direct group).  Chips: BB_A0 BB_B0 K2
65555 #define PCM_REG_SM_CON_CTX_SIZE                                                                      0x110083cUL //Access:RW   DataWidth:0x5   STORM Connnection context per LCID size (REGQ). Default context size of 10 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 20. Maximum number of LCIDs allowed at maximum context size per LCID is 160. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(10/2))/(20/2)).  Chips: BB_A0 BB_B0 K2
65556 #define PCM_REG_IN_PRCS_TBL_CRD_AGG                                                                  0x1100a04UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
65557 #define PCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                0x1100a08UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
65558 #define PCM_REG_IN_PRCS_TBL_FILL_LVL                                                                 0x1100a0cUL //Access:R    DataWidth:0x4   In-process Table fill level  (in messages).  Chips: BB_A0 BB_B0 K2
65559 #define PCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                              0x1100a10UL //Access:R    DataWidth:0x1   In-process Table almost full.  Chips: BB_A0 BB_B0 K2
65560 #define PCM_REG_CCFC_CURR_ST                                                                         0x1100a14UL //Access:R    DataWidth:0x1   CFC connection output FSM current state.  Chips: BB_A0 BB_B0 K2
65561 #define PCM_REG_CMPL_DIR_CURR_ST                                                                     0x1100a18UL //Access:R    DataWidth:0x4   Direct Completer FSM current state.  Chips: BB_A0 BB_B0 K2
65562 #define PCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                         0x1100a1cUL //Access:RW   DataWidth:0x1   If set, Xx connection bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
65563 #define PCM_REG_CCFC_INIT_CRD                                                                        0x1100a84UL //Access:RW   DataWidth:0x4   CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
65564 #define PCM_REG_FIC_INIT_CRD                                                                         0x1100a88UL //Access:RW   DataWidth:0x6   FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.  Chips: BB_A0 BB_B0 K2
65565 #define PCM_REG_DIR_BYP_MSG_CNT                                                                      0x1100aa4UL //Access:RC   DataWidth:0x20  Counter of direct bypassed messages.  Chips: BB_A0 BB_B0 K2
65566 #define PCM_REG_PSDM_LENGTH_MIS                                                                      0x1100aa8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at PSDM interface.  Chips: BB_A0 BB_B0 K2
65567 #define PCM_REG_PBF_LENGTH_MIS                                                                       0x1100aacUL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at PBF interface.  Chips: BB_A0 BB_B0 K2
65568 #define PCM_REG_GRC_BUF_EMPTY                                                                        0x1100ab0UL //Access:R    DataWidth:0x1   Input Stage GRC buffer is empty.  Chips: BB_A0 BB_B0 K2
65569 #define PCM_REG_GRC_BUF_STATUS                                                                       0x1100ab4UL //Access:R    DataWidth:0x6   Input Stage GRC buffer status.  Chips: BB_A0 BB_B0 K2
65570 #define PCM_REG_STORM_MSG_CNTR                                                                       0x1100ab8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the STORM input.  Chips: BB_A0 BB_B0 K2
65571 #define PCM_REG_PSDM_MSG_CNTR                                                                        0x1100abcUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input PSDM.  Chips: BB_A0 BB_B0 K2
65572 #define PCM_REG_PBF_MSG_CNTR                                                                         0x1100ac0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input PBF.  Chips: BB_A0 BB_B0 K2
65573 #define PCM_REG_IS_GRC                                                                               0x1100ac4UL //Access:W    DataWidth:0x20  Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done  Chips: BB_A0 BB_B0 K2
65574 #define PCM_REG_IS_STORM_FILL_LVL                                                                    0x1100ac8UL //Access:R    DataWidth:0x5   Number of QREGs (128b) of data in STORM Input Stage.  Chips: BB_A0 BB_B0 K2
65575 #define PCM_REG_IS_PSDM_FILL_LVL                                                                     0x1100accUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in PSDM Input Stage.  Chips: BB_A0 BB_B0 K2
65576 #define PCM_REG_IS_PBF_FILL_LVL                                                                      0x1100ad0UL //Access:R    DataWidth:0x6   Number of QREGs (128b) of data in PBF Input Stage.  Chips: BB_A0 BB_B0 K2
65577 #define PCM_REG_FIC_MSG_CNTR                                                                         0x1100b44UL //Access:RC   DataWidth:0x1c  Counter of the output messages at FIC interfaces.  Chips: BB_A0 BB_B0 K2
65578 #define PCM_REG_CCFC_CNTR                                                                            0x1100b48UL //Access:RC   DataWidth:0x1c  Counter of the output CCFC.  Chips: BB_A0 BB_B0 K2
65579 #define PCM_REG_ECO_RESERVED                                                                         0x1100b84UL //Access:RW   DataWidth:0x8   Chicken bits.  Chips: BB_A0 BB_B0 K2
65580 #define PCM_REG_IS_FOC_PSEM_NXT_INF_UNIT                                                             0x1100b88UL //Access:R    DataWidth:0x6   Debug read from PSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65581 #define PCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                              0x1100b8cUL //Access:R    DataWidth:0x6   Debug read from PBF Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65582 #define PCM_REG_IS_FOC_PSDM_NXT_INF_UNIT                                                             0x1100b90UL //Access:R    DataWidth:0x6   Debug read from PSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
65583 #define PCM_REG_IS_FOC_PSEM                                                                          0x1100c00UL //Access:R    DataWidth:0x20  Debug read from PSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65584 #define PCM_REG_IS_FOC_PSEM_SIZE                                                                     96
65585 #define PCM_REG_IS_FOC_PBF                                                                           0x1101000UL //Access:R    DataWidth:0x20  Debug read from PBF Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65586 #define PCM_REG_IS_FOC_PBF_SIZE                                                                      180
65587 #define PCM_REG_IS_FOC_PSDM                                                                          0x1101400UL //Access:R    DataWidth:0x20  Debug read from PSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
65588 #define PCM_REG_IS_FOC_PSDM_SIZE                                                                     16
65589 #define PCM_REG_CTX_RBC_ACCS                                                                         0x1101440UL //Access:RW   DataWidth:0x10  Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX  Chips: BB_A0 BB_B0 K2
65590 #define PCM_REG_SM_CON_CTX                                                                           0x1101444UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
65591 #define PCM_REG_XX_LCID_CAM                                                                          0x1101500UL //Access:R    DataWidth:0xa   Debug only. Read only access to LCID CAM in XX protection mechanism.  Chips: BB_A0 BB_B0 K2
65592 #define PCM_REG_XX_LCID_CAM_SIZE                                                                     2
65593 #define PCM_REG_XX_TBL                                                                               0x1101600UL //Access:R    DataWidth:0xb   Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [3:1] - Connection type; LL size: PCM - [6:4]; M/T/U/X/YCM - [10:4]; Tail pointer: PCM - [8:7]; M/T/U/X/YCM - [16:11]; Next pointer: PCM - [10:9]; M/T/U/X/YCM - [22:17];  Chips: BB_A0 BB_B0 K2
65594 #define PCM_REG_XX_TBL_SIZE                                                                          2
65595 #define PCM_REG_XX_DSCR_TBL                                                                          0x1101700UL //Access:RW   DataWidth:0x11  Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.  Chips: BB_A0 BB_B0 K2
65596 #define PCM_REG_XX_DSCR_TBL_SIZE                                                                     4
65597 #define PCM_REG_XX_MSG_RAM                                                                           0x1102000UL //Access:R    DataWidth:0x20  Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.  Chips: BB_A0 BB_B0 K2
65598 #define PCM_REG_XX_MSG_RAM_SIZE                                                                      704
65599 #define TCM_REG_INIT                                                                                 0x1180000UL //Access:RW   DataWidth:0x1   Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.  Chips: BB_A0 BB_B0 K2
65600 #define TCM_REG_DBG_SELECT                                                                           0x1180040UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
65601 #define TCM_REG_DBG_DWORD_ENABLE                                                                     0x1180044UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
65602 #define TCM_REG_DBG_SHIFT                                                                            0x1180048UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
65603 #define TCM_REG_DBG_FORCE_VALID                                                                      0x118004cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
65604 #define TCM_REG_DBG_FORCE_FRAME                                                                      0x1180050UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
65605 #define TCM_REG_DBG_OUT_DATA                                                                         0x1180060UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
65606 #define TCM_REG_DBG_OUT_DATA_SIZE                                                                    8
65607 #define TCM_REG_DBG_OUT_VALID                                                                        0x1180080UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
65608 #define TCM_REG_DBG_OUT_FRAME                                                                        0x1180084UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
65609 #define TCM_REG_INT_STS_0                                                                            0x1180180UL //Access:R    DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65610     #define TCM_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
65611     #define TCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
65612     #define TCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                      (0x1<<1) // Write to full STORM input buffer.
65613     #define TCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                1
65614     #define TCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                     (0x1<<2) // Read from empty  STORM input buffer.
65615     #define TCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                               2
65616     #define TCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR                                                       (0x1<<3) // Write to full TSDM input buffer.
65617     #define TCM_REG_INT_STS_0_IS_TSDM_OVFL_ERR_SHIFT                                                 3
65618     #define TCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR                                                      (0x1<<4) // Read from empty TSDM input buffer.
65619     #define TCM_REG_INT_STS_0_IS_TSDM_UNDER_ERR_SHIFT                                                4
65620     #define TCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR                                                       (0x1<<5) // Write to full Msem input buffer.
65621     #define TCM_REG_INT_STS_0_IS_MSEM_OVFL_ERR_SHIFT                                                 5
65622     #define TCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR                                                      (0x1<<6) // Read from empty  Msem input buffer.
65623     #define TCM_REG_INT_STS_0_IS_MSEM_UNDER_ERR_SHIFT                                                6
65624     #define TCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR                                                       (0x1<<7) // Write to full Ysem input buffer.
65625     #define TCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_SHIFT                                                 7
65626 #define TCM_REG_INT_MASK_0                                                                           0x1180184UL //Access:RW   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65627     #define TCM_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.ADDRESS_ERROR .
65628     #define TCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
65629     #define TCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
65630     #define TCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                               1
65631     #define TCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
65632     #define TCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                              2
65633     #define TCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_TSDM_OVFL_ERR .
65634     #define TCM_REG_INT_MASK_0_IS_TSDM_OVFL_ERR_SHIFT                                                3
65635     #define TCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_TSDM_UNDER_ERR .
65636     #define TCM_REG_INT_MASK_0_IS_TSDM_UNDER_ERR_SHIFT                                               4
65637     #define TCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSEM_OVFL_ERR .
65638     #define TCM_REG_INT_MASK_0_IS_MSEM_OVFL_ERR_SHIFT                                                5
65639     #define TCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_MSEM_UNDER_ERR .
65640     #define TCM_REG_INT_MASK_0_IS_MSEM_UNDER_ERR_SHIFT                                               6
65641     #define TCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
65642     #define TCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_SHIFT                                                7
65643 #define TCM_REG_INT_STS_WR_0                                                                         0x1180188UL //Access:WR   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65644     #define TCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
65645     #define TCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
65646     #define TCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                   (0x1<<1) // Write to full STORM input buffer.
65647     #define TCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                             1
65648     #define TCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                  (0x1<<2) // Read from empty  STORM input buffer.
65649     #define TCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                            2
65650     #define TCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR                                                    (0x1<<3) // Write to full TSDM input buffer.
65651     #define TCM_REG_INT_STS_WR_0_IS_TSDM_OVFL_ERR_SHIFT                                              3
65652     #define TCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR                                                   (0x1<<4) // Read from empty TSDM input buffer.
65653     #define TCM_REG_INT_STS_WR_0_IS_TSDM_UNDER_ERR_SHIFT                                             4
65654     #define TCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR                                                    (0x1<<5) // Write to full Msem input buffer.
65655     #define TCM_REG_INT_STS_WR_0_IS_MSEM_OVFL_ERR_SHIFT                                              5
65656     #define TCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR                                                   (0x1<<6) // Read from empty  Msem input buffer.
65657     #define TCM_REG_INT_STS_WR_0_IS_MSEM_UNDER_ERR_SHIFT                                             6
65658     #define TCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR                                                    (0x1<<7) // Write to full Ysem input buffer.
65659     #define TCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_SHIFT                                              7
65660 #define TCM_REG_INT_STS_CLR_0                                                                        0x118018cUL //Access:RC   DataWidth:0x8   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65661     #define TCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
65662     #define TCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
65663     #define TCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                  (0x1<<1) // Write to full STORM input buffer.
65664     #define TCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                            1
65665     #define TCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                 (0x1<<2) // Read from empty  STORM input buffer.
65666     #define TCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                           2
65667     #define TCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR                                                   (0x1<<3) // Write to full TSDM input buffer.
65668     #define TCM_REG_INT_STS_CLR_0_IS_TSDM_OVFL_ERR_SHIFT                                             3
65669     #define TCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR                                                  (0x1<<4) // Read from empty TSDM input buffer.
65670     #define TCM_REG_INT_STS_CLR_0_IS_TSDM_UNDER_ERR_SHIFT                                            4
65671     #define TCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR                                                   (0x1<<5) // Write to full Msem input buffer.
65672     #define TCM_REG_INT_STS_CLR_0_IS_MSEM_OVFL_ERR_SHIFT                                             5
65673     #define TCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR                                                  (0x1<<6) // Read from empty  Msem input buffer.
65674     #define TCM_REG_INT_STS_CLR_0_IS_MSEM_UNDER_ERR_SHIFT                                            6
65675     #define TCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR                                                   (0x1<<7) // Write to full Ysem input buffer.
65676     #define TCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_SHIFT                                             7
65677 #define TCM_REG_INT_STS_1                                                                            0x1180190UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
65678     #define TCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR                                                      (0x1<<0) // Read from empty  Ysem input buffer.
65679     #define TCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR_SHIFT                                                0
65680     #define TCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR                                                       (0x1<<1) // Write to full Dorq input buffer.
65681     #define TCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_SHIFT                                                 1
65682     #define TCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR                                                      (0x1<<2) // Read from empty  Dorq input buffer.
65683     #define TCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_SHIFT                                                2
65684     #define TCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                        (0x1<<3) // Write to full Pbf input buffer.
65685     #define TCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                  3
65686     #define TCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                       (0x1<<4) // Read from empty Pbf input buffer.
65687     #define TCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                 4
65688     #define TCM_REG_INT_STS_1_IS_PRS_OVFL_ERR                                                        (0x1<<5) // Write to full Pbf input buffer.
65689     #define TCM_REG_INT_STS_1_IS_PRS_OVFL_ERR_SHIFT                                                  5
65690     #define TCM_REG_INT_STS_1_IS_PRS_UNDER_ERR                                                       (0x1<<6) // Read from empty Pbf input buffer.
65691     #define TCM_REG_INT_STS_1_IS_PRS_UNDER_ERR_SHIFT                                                 6
65692     #define TCM_REG_INT_STS_1_IS_TM_OVFL_ERR                                                         (0x1<<7) // Write to full TM input buffer.
65693     #define TCM_REG_INT_STS_1_IS_TM_OVFL_ERR_SHIFT                                                   7
65694     #define TCM_REG_INT_STS_1_IS_TM_UNDER_ERR                                                        (0x1<<8) // Read from empty TM input buffer.
65695     #define TCM_REG_INT_STS_1_IS_TM_UNDER_ERR_SHIFT                                                  8
65696     #define TCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                       (0x1<<9) // Write to full QM input buffer.
65697     #define TCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                 9
65698     #define TCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                      (0x1<<10) // Read from empty QM input buffer.
65699     #define TCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                10
65700     #define TCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                       (0x1<<11) // Write to full QM input buffer.
65701     #define TCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                 11
65702     #define TCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                      (0x1<<12) // Read from empty QM input buffer.
65703     #define TCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                12
65704     #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                       (0x1<<13) // Write to full GRC input buffer bits [31:0].
65705     #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                 13
65706     #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                      (0x1<<14) // Read from empty  GRC input buffer bits [31:0].
65707     #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                14
65708     #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                       (0x1<<15) // Write to full GRC input buffer bits [63:32].
65709     #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                 15
65710     #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                      (0x1<<16) // Read from empty  GRC input buffer bits [63:32].
65711     #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                16
65712     #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                       (0x1<<17) // Write to full GRC input buffer bits [95:64].
65713     #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                 17
65714     #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                      (0x1<<18) // Read from empty  GRC input buffer bits [95:64].
65715     #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                18
65716     #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                       (0x1<<19) // Write to full GRC input buffer bits [127:96].
65717     #define TCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                 19
65718     #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                      (0x1<<20) // Read from empty  GRC input buffer bits [127:96].
65719     #define TCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                20
65720     #define TCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                       (0x1<<21) // In-process Table overflow.
65721     #define TCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                 21
65722     #define TCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL                                                  (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
65723     #define TCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                            22
65724     #define TCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL                                                   (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
65725     #define TCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                             23
65726     #define TCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                   (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
65727     #define TCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                             24
65728     #define TCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                    (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
65729     #define TCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                              25
65730     #define TCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL                                                 (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
65731     #define TCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                           26
65732     #define TCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL                                                  (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
65733     #define TCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                            27
65734     #define TCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL                                                  (0x1<<28) // Message Processor Storm Task Data buffer overflow.
65735     #define TCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                            28
65736     #define TCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL                                                   (0x1<<29) // Message Processor Storm Task Command buffer overflow.
65737     #define TCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                             29
65738     #define TCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                  (0x1<<30) // Input message first descriptor fields violation.
65739     #define TCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                            30
65740     #define TCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE                                                  (0x1<<31) // Input message second descriptor fields violation.
65741     #define TCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_SHIFT                                            31
65742 #define TCM_REG_INT_MASK_1                                                                           0x1180194UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
65743     #define TCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
65744     #define TCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR_SHIFT                                               0
65745     #define TCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR                                                      (0x1<<1) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
65746     #define TCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_SHIFT                                                1
65747     #define TCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
65748     #define TCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_SHIFT                                               2
65749     #define TCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
65750     #define TCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                 3
65751     #define TCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                      (0x1<<4) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
65752     #define TCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                4
65753     #define TCM_REG_INT_MASK_1_IS_PRS_OVFL_ERR                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PRS_OVFL_ERR .
65754     #define TCM_REG_INT_MASK_1_IS_PRS_OVFL_ERR_SHIFT                                                 5
65755     #define TCM_REG_INT_MASK_1_IS_PRS_UNDER_ERR                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_PRS_UNDER_ERR .
65756     #define TCM_REG_INT_MASK_1_IS_PRS_UNDER_ERR_SHIFT                                                6
65757     #define TCM_REG_INT_MASK_1_IS_TM_OVFL_ERR                                                        (0x1<<7) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
65758     #define TCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_SHIFT                                                  7
65759     #define TCM_REG_INT_MASK_1_IS_TM_UNDER_ERR                                                       (0x1<<8) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
65760     #define TCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_SHIFT                                                 8
65761     #define TCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
65762     #define TCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                9
65763     #define TCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
65764     #define TCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                               10
65765     #define TCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
65766     #define TCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                11
65767     #define TCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
65768     #define TCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                               12
65769     #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                      (0x1<<13) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
65770     #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                13
65771     #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                     (0x1<<14) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
65772     #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                               14
65773     #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                      (0x1<<15) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
65774     #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                15
65775     #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                     (0x1<<16) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
65776     #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                               16
65777     #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                      (0x1<<17) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
65778     #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                17
65779     #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                     (0x1<<18) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
65780     #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                               18
65781     #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                      (0x1<<19) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
65782     #define TCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                19
65783     #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                     (0x1<<20) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
65784     #define TCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                               20
65785     #define TCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                      (0x1<<21) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
65786     #define TCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                21
65787     #define TCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
65788     #define TCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                           22
65789     #define TCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL                                                  (0x1<<23) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
65790     #define TCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                            23
65791     #define TCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                  (0x1<<24) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
65792     #define TCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                            24
65793     #define TCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                   (0x1<<25) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
65794     #define TCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                             25
65795     #define TCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL                                                (0x1<<26) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
65796     #define TCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                          26
65797     #define TCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL                                                 (0x1<<27) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
65798     #define TCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                           27
65799     #define TCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL                                                 (0x1<<28) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
65800     #define TCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                           28
65801     #define TCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL                                                  (0x1<<29) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
65802     #define TCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                            29
65803     #define TCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                 (0x1<<30) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
65804     #define TCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                           30
65805     #define TCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE                                                 (0x1<<31) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
65806     #define TCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_SHIFT                                           31
65807 #define TCM_REG_INT_STS_WR_1                                                                         0x1180198UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
65808     #define TCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR                                                   (0x1<<0) // Read from empty  Ysem input buffer.
65809     #define TCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR_SHIFT                                             0
65810     #define TCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR                                                    (0x1<<1) // Write to full Dorq input buffer.
65811     #define TCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_SHIFT                                              1
65812     #define TCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR                                                   (0x1<<2) // Read from empty  Dorq input buffer.
65813     #define TCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_SHIFT                                             2
65814     #define TCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                     (0x1<<3) // Write to full Pbf input buffer.
65815     #define TCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                               3
65816     #define TCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                    (0x1<<4) // Read from empty Pbf input buffer.
65817     #define TCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                              4
65818     #define TCM_REG_INT_STS_WR_1_IS_PRS_OVFL_ERR                                                     (0x1<<5) // Write to full Pbf input buffer.
65819     #define TCM_REG_INT_STS_WR_1_IS_PRS_OVFL_ERR_SHIFT                                               5
65820     #define TCM_REG_INT_STS_WR_1_IS_PRS_UNDER_ERR                                                    (0x1<<6) // Read from empty Pbf input buffer.
65821     #define TCM_REG_INT_STS_WR_1_IS_PRS_UNDER_ERR_SHIFT                                              6
65822     #define TCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR                                                      (0x1<<7) // Write to full TM input buffer.
65823     #define TCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_SHIFT                                                7
65824     #define TCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR                                                     (0x1<<8) // Read from empty TM input buffer.
65825     #define TCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_SHIFT                                               8
65826     #define TCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                    (0x1<<9) // Write to full QM input buffer.
65827     #define TCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                              9
65828     #define TCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                   (0x1<<10) // Read from empty QM input buffer.
65829     #define TCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                             10
65830     #define TCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                    (0x1<<11) // Write to full QM input buffer.
65831     #define TCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                              11
65832     #define TCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                   (0x1<<12) // Read from empty QM input buffer.
65833     #define TCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                             12
65834     #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                    (0x1<<13) // Write to full GRC input buffer bits [31:0].
65835     #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                              13
65836     #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                   (0x1<<14) // Read from empty  GRC input buffer bits [31:0].
65837     #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                             14
65838     #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                    (0x1<<15) // Write to full GRC input buffer bits [63:32].
65839     #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                              15
65840     #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                   (0x1<<16) // Read from empty  GRC input buffer bits [63:32].
65841     #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                             16
65842     #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                    (0x1<<17) // Write to full GRC input buffer bits [95:64].
65843     #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                              17
65844     #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                   (0x1<<18) // Read from empty  GRC input buffer bits [95:64].
65845     #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                             18
65846     #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                    (0x1<<19) // Write to full GRC input buffer bits [127:96].
65847     #define TCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                              19
65848     #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                   (0x1<<20) // Read from empty  GRC input buffer bits [127:96].
65849     #define TCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                             20
65850     #define TCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                    (0x1<<21) // In-process Table overflow.
65851     #define TCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                              21
65852     #define TCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL                                               (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
65853     #define TCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                         22
65854     #define TCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL                                                (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
65855     #define TCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                          23
65856     #define TCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
65857     #define TCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                          24
65858     #define TCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                 (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
65859     #define TCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                           25
65860     #define TCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL                                              (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
65861     #define TCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                        26
65862     #define TCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL                                               (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
65863     #define TCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                         27
65864     #define TCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL                                               (0x1<<28) // Message Processor Storm Task Data buffer overflow.
65865     #define TCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                         28
65866     #define TCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL                                                (0x1<<29) // Message Processor Storm Task Command buffer overflow.
65867     #define TCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                          29
65868     #define TCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                               (0x1<<30) // Input message first descriptor fields violation.
65869     #define TCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                         30
65870     #define TCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE                                               (0x1<<31) // Input message second descriptor fields violation.
65871     #define TCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                         31
65872 #define TCM_REG_INT_STS_CLR_1                                                                        0x118019cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
65873     #define TCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR                                                  (0x1<<0) // Read from empty  Ysem input buffer.
65874     #define TCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR_SHIFT                                            0
65875     #define TCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR                                                   (0x1<<1) // Write to full Dorq input buffer.
65876     #define TCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_SHIFT                                             1
65877     #define TCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR                                                  (0x1<<2) // Read from empty  Dorq input buffer.
65878     #define TCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_SHIFT                                            2
65879     #define TCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                    (0x1<<3) // Write to full Pbf input buffer.
65880     #define TCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                              3
65881     #define TCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                   (0x1<<4) // Read from empty Pbf input buffer.
65882     #define TCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                             4
65883     #define TCM_REG_INT_STS_CLR_1_IS_PRS_OVFL_ERR                                                    (0x1<<5) // Write to full Pbf input buffer.
65884     #define TCM_REG_INT_STS_CLR_1_IS_PRS_OVFL_ERR_SHIFT                                              5
65885     #define TCM_REG_INT_STS_CLR_1_IS_PRS_UNDER_ERR                                                   (0x1<<6) // Read from empty Pbf input buffer.
65886     #define TCM_REG_INT_STS_CLR_1_IS_PRS_UNDER_ERR_SHIFT                                             6
65887     #define TCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR                                                     (0x1<<7) // Write to full TM input buffer.
65888     #define TCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_SHIFT                                               7
65889     #define TCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR                                                    (0x1<<8) // Read from empty TM input buffer.
65890     #define TCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_SHIFT                                              8
65891     #define TCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                   (0x1<<9) // Write to full QM input buffer.
65892     #define TCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                             9
65893     #define TCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                  (0x1<<10) // Read from empty QM input buffer.
65894     #define TCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                            10
65895     #define TCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                   (0x1<<11) // Write to full QM input buffer.
65896     #define TCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                             11
65897     #define TCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                  (0x1<<12) // Read from empty QM input buffer.
65898     #define TCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                            12
65899     #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                   (0x1<<13) // Write to full GRC input buffer bits [31:0].
65900     #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                             13
65901     #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                  (0x1<<14) // Read from empty  GRC input buffer bits [31:0].
65902     #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                            14
65903     #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                   (0x1<<15) // Write to full GRC input buffer bits [63:32].
65904     #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                             15
65905     #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                  (0x1<<16) // Read from empty  GRC input buffer bits [63:32].
65906     #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                            16
65907     #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                   (0x1<<17) // Write to full GRC input buffer bits [95:64].
65908     #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                             17
65909     #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                  (0x1<<18) // Read from empty  GRC input buffer bits [95:64].
65910     #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                            18
65911     #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                   (0x1<<19) // Write to full GRC input buffer bits [127:96].
65912     #define TCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                             19
65913     #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                  (0x1<<20) // Read from empty  GRC input buffer bits [127:96].
65914     #define TCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                            20
65915     #define TCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                   (0x1<<21) // In-process Table overflow.
65916     #define TCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                             21
65917     #define TCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL                                              (0x1<<22) // Message Processor Aggregation Connection Data buffer overflow.
65918     #define TCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                        22
65919     #define TCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL                                               (0x1<<23) // Message Processor Aggregation Connection Command buffer overflow.
65920     #define TCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                         23
65921     #define TCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                               (0x1<<24) // Message Processor Storm Connection Data buffer overflow.
65922     #define TCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                         24
65923     #define TCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                (0x1<<25) // Message Processor Storm Connection Command buffer overflow.
65924     #define TCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                          25
65925     #define TCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL                                             (0x1<<26) // Message Processor Aggregation Task Data buffer overflow.
65926     #define TCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                       26
65927     #define TCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL                                              (0x1<<27) // Message Processor Aggregation Task Command buffer overflow.
65928     #define TCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                        27
65929     #define TCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL                                              (0x1<<28) // Message Processor Storm Task Data buffer overflow.
65930     #define TCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                        28
65931     #define TCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL                                               (0x1<<29) // Message Processor Storm Task Command buffer overflow.
65932     #define TCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                         29
65933     #define TCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                              (0x1<<30) // Input message first descriptor fields violation.
65934     #define TCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                        30
65935     #define TCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE                                              (0x1<<31) // Input message second descriptor fields violation.
65936     #define TCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                        31
65937 #define TCM_REG_INT_STS_2                                                                            0x11801a0UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65938     #define TCM_REG_INT_STS_2_QMREG_MORE4                                                            (0x1<<0) // More than 4 QM registrations.
65939     #define TCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                      0
65940 #define TCM_REG_INT_MASK_2                                                                           0x11801a4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65941     #define TCM_REG_INT_MASK_2_QMREG_MORE4                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: TCM_REG_INT_STS_2.QMREG_MORE4 .
65942     #define TCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                     0
65943 #define TCM_REG_INT_STS_WR_2                                                                         0x11801a8UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65944     #define TCM_REG_INT_STS_WR_2_QMREG_MORE4                                                         (0x1<<0) // More than 4 QM registrations.
65945     #define TCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                   0
65946 #define TCM_REG_INT_STS_CLR_2                                                                        0x11801acUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
65947     #define TCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                        (0x1<<0) // More than 4 QM registrations.
65948     #define TCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                  0
65949 #define TCM_REG_PRTY_MASK_H_0                                                                        0x1180204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
65950     #define TCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
65951     #define TCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_SHIFT                                          0
65952     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_A0                                        (0x1<<5) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
65953     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_A0_SHIFT                                  5
65954     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_B0                                        (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
65955     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_BB_B0_SHIFT                                  1
65956     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_K2                                           (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
65957     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_K2_SHIFT                                     1
65958     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_A0                                        (0x1<<6) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
65959     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_A0_SHIFT                                  6
65960     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_B0                                        (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
65961     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_BB_B0_SHIFT                                  2
65962     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_K2                                           (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
65963     #define TCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_K2_SHIFT                                     2
65964     #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT .
65965     #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_SHIFT                                        3
65966     #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_ECC_1_RF_INT .
65967     #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT_SHIFT                                        4
65968     #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT                                              (0x1<<5) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
65969     #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT                                        5
65970     #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT                                              (0x1<<6) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
65971     #define TCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT                                        6
65972     #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
65973     #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_SHIFT                                        7
65974     #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT                                              (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
65975     #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_SHIFT                                        8
65976     #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0                                            (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
65977     #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                      27
65978     #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
65979     #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                      9
65980     #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
65981     #define TCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                         9
65982     #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
65983     #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      14
65984     #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
65985     #define TCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                         10
65986     #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
65987     #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0_SHIFT                                      13
65988     #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
65989     #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0_SHIFT                                      10
65990     #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
65991     #define TCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                         11
65992     #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0                                            (0x1<<10) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
65993     #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                      10
65994     #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
65995     #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                      11
65996     #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
65997     #define TCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                         12
65998     #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
65999     #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      15
66000     #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
66001     #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      12
66002     #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
66003     #define TCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                         13
66004     #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
66005     #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_A0_SHIFT                                      17
66006     #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
66007     #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_BB_B0_SHIFT                                      13
66008     #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
66009     #define TCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_K2_SHIFT                                         14
66010     #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
66011     #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      24
66012     #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
66013     #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      26
66014     #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
66015     #define TCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                         15
66016     #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
66017     #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                      18
66018     #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
66019     #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                      15
66020     #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
66021     #define TCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                         16
66022     #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
66023     #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0_SHIFT                                      19
66024     #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
66025     #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0_SHIFT                                      16
66026     #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
66027     #define TCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                         17
66028     #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
66029     #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0_SHIFT                                      11
66030     #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
66031     #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0_SHIFT                                      17
66032     #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
66033     #define TCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                         18
66034     #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
66035     #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0_SHIFT                                      12
66036     #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0                                            (0x1<<18) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
66037     #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0_SHIFT                                      18
66038     #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
66039     #define TCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                         19
66040     #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
66041     #define TCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_SHIFT                                            20
66042     #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0                                            (0x1<<19) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
66043     #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_BB_B0_SHIFT                                      19
66044     #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2                                               (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
66045     #define TCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_K2_SHIFT                                         21
66046     #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
66047     #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0_SHIFT                                      20
66048     #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0                                            (0x1<<20) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
66049     #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0_SHIFT                                      20
66050     #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                               (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
66051     #define TCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                         22
66052     #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0                                            (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
66053     #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0_SHIFT                                      25
66054     #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0                                            (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
66055     #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0_SHIFT                                      22
66056     #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                               (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
66057     #define TCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                         23
66058     #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_A0                                            (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
66059     #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_BB_A0_SHIFT                                      26
66060     #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2                                               (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
66061     #define TCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_K2_SHIFT                                         24
66062     #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                            (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
66063     #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                      30
66064     #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                            (0x1<<24) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
66065     #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                      24
66066     #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                               (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
66067     #define TCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                         25
66068     #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_A0                                            (0x1<<22) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
66069     #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_BB_A0_SHIFT                                      22
66070     #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2                                               (0x1<<26) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
66071     #define TCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_K2_SHIFT                                         26
66072     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
66073     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                            27
66074     #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_B0                                          (0x1<<27) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
66075     #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_BB_B0_SHIFT                                    27
66076     #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2                                             (0x1<<28) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
66077     #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_K2_SHIFT                                       28
66078     #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_B0                                          (0x1<<28) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
66079     #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_BB_B0_SHIFT                                    28
66080     #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_K2                                             (0x1<<29) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
66081     #define TCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_K2_SHIFT                                       29
66082     #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
66083     #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_A0_SHIFT                                      14
66084     #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0                                            (0x1<<29) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
66085     #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_BB_B0_SHIFT                                      29
66086     #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2                                               (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
66087     #define TCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_K2_SHIFT                                         30
66088     #define TCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
66089     #define TCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_SHIFT                                          0
66090     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB_A0                                        (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
66091     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB_A0_SHIFT                                  7
66092     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB_B0                                        (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
66093     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_BB_B0_SHIFT                                  3
66094     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_K2                                           (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
66095     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_K2_SHIFT                                     3
66096     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_BB_A0                                        (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
66097     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_BB_A0_SHIFT                                  8
66098     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_BB_B0                                        (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
66099     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_BB_B0_SHIFT                                  4
66100     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_K2                                           (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
66101     #define TCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_K2_SHIFT                                     4
66102     #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT .
66103     #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_SHIFT                                        7
66104     #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT                                              (0x1<<8) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM023_I_ECC_1_RF_INT .
66105     #define TCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_SHIFT                                        8
66106     #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
66107     #define TCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT                                            21
66108     #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
66109     #define TCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_SHIFT                                            23
66110     #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
66111     #define TCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                            25
66112     #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
66113     #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_A0_SHIFT                                      16
66114     #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0                                            (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
66115     #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_BB_B0_SHIFT                                      30
66116     #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2                                               (0x1<<30) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
66117     #define TCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_K2_SHIFT                                         30
66118     #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT .
66119     #define TCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_SHIFT                                          0
66120     #define TCM_REG_PRTY_MASK_H_0_MEM001_I_ECC_0_RF_INT                                              (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM001_I_ECC_0_RF_INT .
66121     #define TCM_REG_PRTY_MASK_H_0_MEM001_I_ECC_0_RF_INT_SHIFT                                        1
66122     #define TCM_REG_PRTY_MASK_H_0_MEM001_I_ECC_1_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM001_I_ECC_1_RF_INT .
66123     #define TCM_REG_PRTY_MASK_H_0_MEM001_I_ECC_1_RF_INT_SHIFT                                        2
66124     #define TCM_REG_PRTY_MASK_H_0_MEM019_I_ECC_0_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_ECC_0_RF_INT .
66125     #define TCM_REG_PRTY_MASK_H_0_MEM019_I_ECC_0_RF_INT_SHIFT                                        3
66126     #define TCM_REG_PRTY_MASK_H_0_MEM019_I_ECC_1_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM019_I_ECC_1_RF_INT .
66127     #define TCM_REG_PRTY_MASK_H_0_MEM019_I_ECC_1_RF_INT_SHIFT                                        4
66128     #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT                                                (0x1<<9) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM022_I_ECC_RF_INT .
66129     #define TCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_RF_INT_SHIFT                                          9
66130     #define TCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
66131     #define TCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            23
66132     #define TCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_0                                                (0x1<<28) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY_0 .
66133     #define TCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_0_SHIFT                                          28
66134     #define TCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_1                                                (0x1<<29) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY_1 .
66135     #define TCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_1_SHIFT                                          29
66136 #define TCM_REG_PRTY_MASK_H_1                                                                        0x1180214UL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66137     #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
66138     #define TCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_SHIFT                                            0
66139     #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0                                            (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
66140     #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                      0
66141     #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                               (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
66142     #define TCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                         1
66143     #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0                                            (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
66144     #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                      1
66145     #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                               (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
66146     #define TCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                         2
66147     #define TCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
66148     #define TCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_SHIFT                                            0
66149     #define TCM_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM028_I_MEM_PRTY .
66150     #define TCM_REG_PRTY_MASK_H_1_MEM028_I_MEM_PRTY_SHIFT                                            1
66151     #define TCM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: TCM_REG_PRTY_STS_H_1.MEM029_I_MEM_PRTY .
66152     #define TCM_REG_PRTY_MASK_H_1_MEM029_I_MEM_PRTY_SHIFT                                            2
66153 #define TCM_REG_MEM_ECC_EVENTS                                                                       0x118022cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
66154 #define TCM_REG_MEM018_I_MEM_DFT_K2                                                                  0x1180234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_is_storm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66155 #define TCM_REG_MEM016_I_MEM_DFT_K2                                                                  0x1180238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_is_pbf_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66156 #define TCM_REG_MEM017_I_MEM_DFT_K2                                                                  0x118023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_is_prs_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66157 #define TCM_REG_MEM020_I_MEM_DFT_K2                                                                  0x1180240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_is_ysem_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66158 #define TCM_REG_MEM011_I_MEM_DFT_K2                                                                  0x1180244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_is_grc0_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66159 #define TCM_REG_MEM012_I_MEM_DFT_K2                                                                  0x1180248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_is_grc1_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66160 #define TCM_REG_MEM013_I_MEM_DFT_K2                                                                  0x118024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_is_grc2_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66161 #define TCM_REG_MEM014_I_MEM_DFT_K2                                                                  0x1180250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_is_grc3_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66162 #define TCM_REG_MEM026_I_MEM_DFT_K2                                                                  0x1180254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_xx_msg_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
66163 #define TCM_REG_MEM029_I_MEM_DFT_K2                                                                  0x1180258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_xx_pref_dir_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66164 #define TCM_REG_MEM028_I_MEM_DFT_K2                                                                  0x118025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_xx_pref_byp_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66165 #define TCM_REG_MEM027_I_MEM_DFT_K2                                                                  0x1180260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_xx_pref_aggst_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66166 #define TCM_REG_MEM004_I_MEM_DFT_K2                                                                  0x1180264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_agg_con_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66167 #define TCM_REG_MEM003_I_MEM_DFT_K2                                                                  0x1180268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_agg_con_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
66168 #define TCM_REG_MEM023_I_MEM_DFT_K2                                                                  0x118026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_sm_con_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66169 #define TCM_REG_MEM022_I_MEM_DFT_K2                                                                  0x1180270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_sm_con_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
66170 #define TCM_REG_MEM006_I_MEM_DFT_K2                                                                  0x1180274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_agg_task_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66171 #define TCM_REG_MEM005_I_MEM_DFT_K2                                                                  0x1180278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_agg_task_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
66172 #define TCM_REG_MEM025_I_MEM_DFT_K2                                                                  0x118027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_sm_task_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66173 #define TCM_REG_MEM024_I_MEM_DFT_K2                                                                  0x1180280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_sm_task_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
66174 #define TCM_REG_MEM021_I_MEM_DFT_K2                                                                  0x1180284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_prcs_trans.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66175 #define TCM_REG_MEM007_I_MEM_DFT_K2                                                                  0x1180288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tcm.i_in_prcs_msgin.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
66176 #define TCM_REG_IFEN                                                                                 0x1180400UL //Access:RW   DataWidth:0x1   Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
66177 #define TCM_REG_QM_CON_BASE_EVNT_ID_0                                                                0x1180404UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66178 #define TCM_REG_QM_CON_BASE_EVNT_ID_1                                                                0x1180408UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66179 #define TCM_REG_QM_CON_BASE_EVNT_ID_2                                                                0x118040cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66180 #define TCM_REG_QM_CON_BASE_EVNT_ID_3                                                                0x1180410UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66181 #define TCM_REG_QM_CON_BASE_EVNT_ID_4                                                                0x1180414UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66182 #define TCM_REG_QM_CON_BASE_EVNT_ID_5                                                                0x1180418UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66183 #define TCM_REG_QM_CON_BASE_EVNT_ID_6                                                                0x118041cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66184 #define TCM_REG_QM_CON_BASE_EVNT_ID_7                                                                0x1180420UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66185 #define TCM_REG_QM_TASK_BASE_EVNT_ID_0                                                               0x1180424UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66186 #define TCM_REG_QM_TASK_BASE_EVNT_ID_1                                                               0x1180428UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66187 #define TCM_REG_QM_TASK_BASE_EVNT_ID_2                                                               0x118042cUL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66188 #define TCM_REG_QM_TASK_BASE_EVNT_ID_3                                                               0x1180430UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66189 #define TCM_REG_QM_TASK_BASE_EVNT_ID_4                                                               0x1180434UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66190 #define TCM_REG_QM_TASK_BASE_EVNT_ID_5                                                               0x1180438UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66191 #define TCM_REG_QM_TASK_BASE_EVNT_ID_6                                                               0x118043cUL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66192 #define TCM_REG_QM_TASK_BASE_EVNT_ID_7                                                               0x1180440UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66193 #define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_0                                                           0x1180444UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
66194 #define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_1                                                           0x1180448UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
66195 #define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_2                                                           0x118044cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
66196 #define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_3                                                           0x1180450UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
66197 #define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_4                                                           0x1180454UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
66198 #define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_5                                                           0x1180458UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
66199 #define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_6                                                           0x118045cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
66200 #define TCM_REG_QM_AGG_CON_CTX_PART_SIZE_7                                                           0x1180460UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
66201 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_0                                                             0x1180464UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
66202 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_1                                                             0x1180468UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
66203 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_2                                                             0x118046cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
66204 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_3                                                             0x1180470UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
66205 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_4                                                             0x1180474UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
66206 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_5                                                             0x1180478UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
66207 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_6                                                             0x118047cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
66208 #define TCM_REG_QM_SM_CON_CTX_LDST_FLG_7                                                             0x1180480UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
66209 #define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_0                                                          0x1180484UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
66210 #define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_1                                                          0x1180488UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
66211 #define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_2                                                          0x118048cUL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
66212 #define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_3                                                          0x1180490UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
66213 #define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_4                                                          0x1180494UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
66214 #define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_5                                                          0x1180498UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
66215 #define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_6                                                          0x118049cUL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
66216 #define TCM_REG_QM_AGG_TASK_CTX_PART_SIZE_7                                                          0x11804a0UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
66217 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_0                                                            0x11804a4UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
66218 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_1                                                            0x11804a8UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
66219 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_2                                                            0x11804acUL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
66220 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_3                                                            0x11804b0UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
66221 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_4                                                            0x11804b4UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
66222 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_5                                                            0x11804b8UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
66223 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_6                                                            0x11804bcUL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
66224 #define TCM_REG_QM_SM_TASK_CTX_LDST_FLG_7                                                            0x11804c0UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
66225 #define TCM_REG_QM_XXLOCK_CMD_0                                                                      0x11804c4UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
66226 #define TCM_REG_QM_XXLOCK_CMD_1                                                                      0x11804c8UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
66227 #define TCM_REG_QM_XXLOCK_CMD_2                                                                      0x11804ccUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
66228 #define TCM_REG_QM_XXLOCK_CMD_3                                                                      0x11804d0UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
66229 #define TCM_REG_QM_XXLOCK_CMD_4                                                                      0x11804d4UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
66230 #define TCM_REG_QM_XXLOCK_CMD_5                                                                      0x11804d8UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
66231 #define TCM_REG_QM_XXLOCK_CMD_6                                                                      0x11804dcUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
66232 #define TCM_REG_QM_XXLOCK_CMD_7                                                                      0x11804e0UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
66233 #define TCM_REG_QM_CON_USE_ST_FLG_0                                                                  0x11804e4UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
66234 #define TCM_REG_QM_CON_USE_ST_FLG_1                                                                  0x11804e8UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
66235 #define TCM_REG_QM_CON_USE_ST_FLG_2                                                                  0x11804ecUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
66236 #define TCM_REG_QM_CON_USE_ST_FLG_3                                                                  0x11804f0UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
66237 #define TCM_REG_QM_CON_USE_ST_FLG_4                                                                  0x11804f4UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
66238 #define TCM_REG_QM_CON_USE_ST_FLG_5                                                                  0x11804f8UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
66239 #define TCM_REG_QM_CON_USE_ST_FLG_6                                                                  0x11804fcUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
66240 #define TCM_REG_QM_CON_USE_ST_FLG_7                                                                  0x1180500UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
66241 #define TCM_REG_QM_TASK_USE_ST_FLG_0                                                                 0x1180504UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
66242 #define TCM_REG_QM_TASK_USE_ST_FLG_1                                                                 0x1180508UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
66243 #define TCM_REG_QM_TASK_USE_ST_FLG_2                                                                 0x118050cUL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
66244 #define TCM_REG_QM_TASK_USE_ST_FLG_3                                                                 0x1180510UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
66245 #define TCM_REG_QM_TASK_USE_ST_FLG_4                                                                 0x1180514UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
66246 #define TCM_REG_QM_TASK_USE_ST_FLG_5                                                                 0x1180518UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
66247 #define TCM_REG_QM_TASK_USE_ST_FLG_6                                                                 0x118051cUL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
66248 #define TCM_REG_QM_TASK_USE_ST_FLG_7                                                                 0x1180520UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM.  Chips: BB_A0 BB_B0 K2
66249 #define TCM_REG_TM_CON_EVNT_ID_0                                                                     0x1180524UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66250 #define TCM_REG_TM_CON_EVNT_ID_1                                                                     0x1180528UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66251 #define TCM_REG_TM_CON_EVNT_ID_2                                                                     0x118052cUL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66252 #define TCM_REG_TM_CON_EVNT_ID_3                                                                     0x1180530UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66253 #define TCM_REG_TM_CON_EVNT_ID_4                                                                     0x1180534UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66254 #define TCM_REG_TM_CON_EVNT_ID_5                                                                     0x1180538UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66255 #define TCM_REG_TM_CON_EVNT_ID_6                                                                     0x118053cUL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66256 #define TCM_REG_TM_CON_EVNT_ID_7                                                                     0x1180540UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.:  Chips: BB_A0 BB_B0 K2
66257 #define TCM_REG_TM_TASK_EVNT_ID_0                                                                    0x1180544UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66258 #define TCM_REG_TM_TASK_EVNT_ID_1                                                                    0x1180548UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66259 #define TCM_REG_TM_TASK_EVNT_ID_2                                                                    0x118054cUL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66260 #define TCM_REG_TM_TASK_EVNT_ID_3                                                                    0x1180550UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66261 #define TCM_REG_TM_TASK_EVNT_ID_4                                                                    0x1180554UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66262 #define TCM_REG_TM_TASK_EVNT_ID_5                                                                    0x1180558UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66263 #define TCM_REG_TM_TASK_EVNT_ID_6                                                                    0x118055cUL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66264 #define TCM_REG_TM_TASK_EVNT_ID_7                                                                    0x1180560UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
66265 #define TCM_REG_ERR_EVNT_ID                                                                          0x1180564UL //Access:RW   DataWidth:0x8   The Event ID in case one of errors is set in QM input message.  Chips: BB_A0 BB_B0 K2
66266 #define TCM_REG_STORM_WEIGHT                                                                         0x1180604UL //Access:RW   DataWidth:0x3   The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66267 #define TCM_REG_MSEM_WEIGHT                                                                          0x1180608UL //Access:RW   DataWidth:0x3   The weight of the input Msem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66268 #define TCM_REG_YSEM_WEIGHT                                                                          0x118060cUL //Access:RW   DataWidth:0x3   The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66269 #define TCM_REG_DORQ_WEIGHT                                                                          0x1180610UL //Access:RW   DataWidth:0x3   The weight of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66270 #define TCM_REG_PBF_WEIGHT                                                                           0x1180614UL //Access:RW   DataWidth:0x3   The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66271 #define TCM_REG_PRS_WEIGHT                                                                           0x1180618UL //Access:RW   DataWidth:0x3   The weight of the input PRS in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66272 #define TCM_REG_GRC_WEIGHT                                                                           0x118061cUL //Access:RW   DataWidth:0x3   The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66273 #define TCM_REG_TSDM_WEIGHT                                                                          0x1180620UL //Access:RW   DataWidth:0x3   The weight of the input TSDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66274 #define TCM_REG_QM_P_WEIGHT                                                                          0x1180624UL //Access:RW   DataWidth:0x3   The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66275 #define TCM_REG_QM_S_WEIGHT                                                                          0x1180628UL //Access:RW   DataWidth:0x3   The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66276 #define TCM_REG_TM_WEIGHT                                                                            0x118062cUL //Access:RW   DataWidth:0x3   The weight of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
66277 #define TCM_REG_IA_GROUP_PR0                                                                         0x1180630UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
66278 #define TCM_REG_IA_GROUP_PR1                                                                         0x1180634UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
66279 #define TCM_REG_IA_GROUP_PR2                                                                         0x1180638UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
66280 #define TCM_REG_IA_GROUP_PR3                                                                         0x118063cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
66281 #define TCM_REG_IA_GROUP_PR4                                                                         0x1180640UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
66282 #define TCM_REG_IA_GROUP_PR5                                                                         0x1180644UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
66283 #define TCM_REG_IA_ARB_SP_TIMEOUT                                                                    0x1180648UL //Access:RW   DataWidth:0x8   Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority.  Chips: BB_A0 BB_B0 K2
66284 #define TCM_REG_STORM_FRWRD_MODE                                                                     0x118064cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
66285 #define TCM_REG_TSDM_FRWRD_MODE                                                                      0x1180650UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
66286 #define TCM_REG_MSEM_FRWRD_MODE                                                                      0x1180654UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
66287 #define TCM_REG_YSEM_FRWRD_MODE                                                                      0x1180658UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
66288 #define TCM_REG_DORQ_FRWRD_MODE                                                                      0x118065cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
66289 #define TCM_REG_PBF_FRWRD_MODE                                                                       0x1180660UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
66290 #define TCM_REG_SDM_ERR_HANDLE_EN                                                                    0x1180664UL //Access:RW   DataWidth:0x1   0 - disable error handling in SDM message; 1 - enable error handling in SDM message.  Chips: BB_A0 BB_B0 K2
66291 #define TCM_REG_DIR_BYP_EN                                                                           0x1180668UL //Access:RW   DataWidth:0x1   Direct bypass enable.  Chips: BB_A0 BB_B0 K2
66292 #define TCM_REG_FI_DESC_INPUT_VIOLATE                                                                0x118066cUL //Access:R    DataWidth:0x10  Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: XxBypass message in PCM block;  Chips: BB_A0 BB_B0 K2
66293 #define TCM_REG_SE_DESC_INPUT_VIOLATE                                                                0x1180670UL //Access:R    DataWidth:0xc   Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; Read only register.  Chips: BB_A0 BB_B0 K2
66294 #define TCM_REG_IA_AGG_CON_PART_FILL_LVL                                                             0x1180674UL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
66295 #define TCM_REG_IA_SM_CON_PART_FILL_LVL                                                              0x1180678UL //Access:R    DataWidth:0x3   Input Arbiter Storm Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
66296 #define TCM_REG_IA_AGG_TASK_PART_FILL_LVL                                                            0x118067cUL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Task part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
66297 #define TCM_REG_IA_SM_TASK_PART_FILL_LVL                                                             0x1180680UL //Access:R    DataWidth:0x3   Input Arbiter Storm Task part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
66298 #define TCM_REG_IA_TRANS_PART_FILL_LVL                                                               0x1180684UL //Access:R    DataWidth:0x3   Input Arbiter Transparent part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
66299 #define TCM_REG_XX_MSG_UP_BND                                                                        0x1180704UL //Access:RW   DataWidth:0x7   The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the siz of Xx protected message CM_REGISTERS_XX_MSG_SIZE_BND.XX_MSG_SIZE_BND  Chips: BB_A0 BB_B0 K2
66300 #define TCM_REG_XX_MSG_SIZE                                                                          0x1180708UL //Access:RW   DataWidth:0xb   The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to even number and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1664 PCM: 0d176 TCM: 0d1408 UCM: 0d1664 XCM: 0d256 YCM: 0d1536  Chips: BB_A0 BB_B0 K2
66301 #define TCM_REG_XX_LCID_CAM_UP_BND                                                                   0x118070cUL //Access:RW   DataWidth:0x6   The maximum number of connections in the XX protection LCID CAM.  Chips: BB_A0 BB_B0 K2
66302 #define TCM_REG_XX_FREE_CNT                                                                          0x1180710UL //Access:R    DataWidth:0x7   Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
66303 #define TCM_REG_XX_LCID_CAM_FILL_LVL                                                                 0x1180714UL //Access:R    DataWidth:0x6   Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.  Chips: BB_A0 BB_B0 K2
66304 #define TCM_REG_XX_LCID_CAM_ST_STAT                                                                  0x1180718UL //Access:RC   DataWidth:0x6   CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.  Chips: BB_A0 BB_B0 K2
66305 #define TCM_REG_XX_IA_GROUP_PR0                                                                      0x118071cUL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
66306 #define TCM_REG_XX_IA_GROUP_PR1                                                                      0x1180720UL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
66307 #define TCM_REG_XX_NON_LOCK_LCID_THR                                                                 0x1180724UL //Access:RW   DataWidth:0x6   Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.  Chips: BB_A0 BB_B0 K2
66308 #define TCM_REG_XX_LOCK_LCID_THR                                                                     0x1180728UL //Access:RW   DataWidth:0x6   Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.  Chips: BB_A0 BB_B0 K2
66309 #define TCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                 0x118072cUL //Access:RW   DataWidth:0x8   Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
66310 #define TCM_REG_XX_FREE_HEAD_PTR                                                                     0x1180730UL //Access:R    DataWidth:0x6   Xx Free Head Pointer.  Chips: BB_A0 BB_B0 K2
66311 #define TCM_REG_XX_FREE_TAIL_PTR                                                                     0x1180734UL //Access:R    DataWidth:0x6   Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
66312 #define TCM_REG_XX_NON_LOCK_CNT                                                                      0x1180738UL //Access:R    DataWidth:0x6   Xx NonLock Counter.  Chips: BB_A0 BB_B0 K2
66313 #define TCM_REG_XX_LOCK_CNT                                                                          0x118073cUL //Access:R    DataWidth:0x6   Xx Lock Counter.  Chips: BB_A0 BB_B0 K2
66314 #define TCM_REG_XX_LCID_ARB_GROUP_PR0                                                                0x1180740UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
66315 #define TCM_REG_XX_LCID_ARB_GROUP_PR1                                                                0x1180744UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
66316 #define TCM_REG_XX_LCID_ARB_GROUP_PR2                                                                0x1180748UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
66317 #define TCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                               0x118074cUL //Access:RW   DataWidth:0x8   Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
66318 #define TCM_REG_XX_FREE_THR_HIGH                                                                     0x1180750UL //Access:RW   DataWidth:0x7   Xx free messages threshold high. Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
66319 #define TCM_REG_XX_FREE_THR_LOW                                                                      0x1180754UL //Access:RW   DataWidth:0x7   Xx free messages threshold low Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
66320 #define TCM_REG_XX_CBYP_TBL_FILL_LVL                                                                 0x1180758UL //Access:R    DataWidth:0x4   Xx Connection Bypass Table fill level (in connections).  Chips: BB_A0 BB_B0 K2
66321 #define TCM_REG_XX_CBYP_TBL_ST_STAT                                                                  0x118075cUL //Access:RC   DataWidth:0x4   Xx Connection Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
66322 #define TCM_REG_XX_CBYP_TBL_UP_BND                                                                   0x1180760UL //Access:RW   DataWidth:0x4   Xx Bypass Table (Connection) maximum fill level.  Chips: BB_A0 BB_B0 K2
66323 #define TCM_REG_XX_TBYP_TBL_FILL_LVL                                                                 0x1180764UL //Access:R    DataWidth:0x6   Xx Task Bypass Table fill level (in tasks).  Chips: BB_A0 BB_B0 K2
66324 #define TCM_REG_XX_TBYP_TBL_ST_STAT                                                                  0x1180768UL //Access:RC   DataWidth:0x6   Xx Task Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
66325 #define TCM_REG_XX_TBYP_TBL_UP_BND                                                                   0x118076cUL //Access:RW   DataWidth:0x6   Xx Bypass Table (Task) maximum fill level.  Chips: BB_A0 BB_B0 K2
66326 #define TCM_REG_XX_BYP_MSG_UP_BND_0                                                                  0x1180770UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
66327 #define TCM_REG_XX_BYP_MSG_UP_BND_1                                                                  0x1180774UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
66328 #define TCM_REG_XX_BYP_MSG_UP_BND_2                                                                  0x1180778UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
66329 #define TCM_REG_XX_BYP_MSG_UP_BND_3                                                                  0x118077cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
66330 #define TCM_REG_XX_BYP_MSG_UP_BND_4                                                                  0x1180780UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
66331 #define TCM_REG_XX_BYP_MSG_UP_BND_5                                                                  0x1180784UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
66332 #define TCM_REG_XX_BYP_MSG_UP_BND_6                                                                  0x1180788UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
66333 #define TCM_REG_XX_BYP_MSG_UP_BND_7                                                                  0x118078cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
66334 #define TCM_REG_XX_BYP_LOCK_MSG_THR                                                                  0x1180790UL //Access:RW   DataWidth:0x6   Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.  Chips: BB_A0 BB_B0 K2
66335 #define TCM_REG_XX_PREF_DIR_FILL_LVL                                                                 0x1180794UL //Access:R    DataWidth:0x6   Xx LCID Arbiter direct prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
66336 #define TCM_REG_XX_PREF_AGGST_FILL_LVL                                                               0x1180798UL //Access:R    DataWidth:0x6   Xx LCID Arbiter aggregation store prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
66337 #define TCM_REG_XX_PREF_BYP_FILL_LVL                                                                 0x118079cUL //Access:R    DataWidth:0x6   Xx LCID Arbiter bypass prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
66338 #define TCM_REG_UNLOCK_MISS                                                                          0x11807a0UL //Access:RC   DataWidth:0x1   Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.  Chips: BB_A0 BB_B0 K2
66339 #define TCM_REG_PRCS_AGG_CON_CURR_ST                                                                 0x1180804UL //Access:R    DataWidth:0x4   Aggregation Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
66340 #define TCM_REG_PRCS_SM_CON_CURR_ST                                                                  0x1180808UL //Access:R    DataWidth:0x2   STORM Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
66341 #define TCM_REG_PRCS_AGG_TASK_CURR_ST                                                                0x118080cUL //Access:R    DataWidth:0x4   Aggregation Task Processor FSM.  Chips: BB_A0 BB_B0 K2
66342 #define TCM_REG_PRCS_SM_TASK_CURR_ST                                                                 0x1180810UL //Access:R    DataWidth:0x2   STORM Task Processor FSM.  Chips: BB_A0 BB_B0 K2
66343 #define TCM_REG_N_SM_CON_CTX_LD_0                                                                    0x1180814UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66344 #define TCM_REG_N_SM_CON_CTX_LD_1                                                                    0x1180818UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66345 #define TCM_REG_N_SM_CON_CTX_LD_2                                                                    0x118081cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66346 #define TCM_REG_N_SM_CON_CTX_LD_3                                                                    0x1180820UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66347 #define TCM_REG_N_SM_CON_CTX_LD_4                                                                    0x1180824UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66348 #define TCM_REG_N_SM_CON_CTX_LD_5                                                                    0x1180828UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66349 #define TCM_REG_N_SM_CON_CTX_LD_6                                                                    0x118082cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66350 #define TCM_REG_N_SM_CON_CTX_LD_7                                                                    0x1180830UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66351 #define TCM_REG_N_SM_TASK_CTX_LD_0                                                                   0x1180834UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66352 #define TCM_REG_N_SM_TASK_CTX_LD_1                                                                   0x1180838UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66353 #define TCM_REG_N_SM_TASK_CTX_LD_2                                                                   0x118083cUL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66354 #define TCM_REG_N_SM_TASK_CTX_LD_3                                                                   0x1180840UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66355 #define TCM_REG_N_SM_TASK_CTX_LD_4                                                                   0x1180844UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66356 #define TCM_REG_N_SM_TASK_CTX_LD_5                                                                   0x1180848UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66357 #define TCM_REG_N_SM_TASK_CTX_LD_6                                                                   0x118084cUL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66358 #define TCM_REG_N_SM_TASK_CTX_LD_7                                                                   0x1180850UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
66359 #define TCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                             0x1180854UL //Access:R    DataWidth:0x3   Aggregation Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
66360 #define TCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                              0x1180858UL //Access:R    DataWidth:0x5   Storm Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
66361 #define TCM_REG_AGG_CON_FIC_BUF_CRD                                                                  0x118085cUL //Access:RW   DataWidth:0x2   Aggregation Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
66362 #define TCM_REG_SM_CON_FIC_BUF_CRD                                                                   0x1180860UL //Access:RW   DataWidth:0x2   Storm Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
66363 #define TCM_REG_AGG_CON_BUF_CRD_AGG                                                                  0x1180864UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
66364 #define TCM_REG_AGG_CON_BUF_CRD_AGGST                                                                0x1180868UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
66365 #define TCM_REG_SM_CON_BUF_CRD_AGGST                                                                 0x118086cUL //Access:RW   DataWidth:0x1   Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
66366 #define TCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                              0x1180870UL //Access:RW   DataWidth:0x2   Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
66367 #define TCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                               0x1180874UL //Access:RW   DataWidth:0x2   Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
66368 #define TCM_REG_AGG_TASK_FIC_BUF_FILL_LVL                                                            0x1180878UL //Access:R    DataWidth:0x2   Aggregation Task FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
66369 #define TCM_REG_SM_TASK_FIC_BUF_FILL_LVL                                                             0x118087cUL //Access:R    DataWidth:0x4   Storm Task FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
66370 #define TCM_REG_AGG_TASK_FIC_BUF_CRD                                                                 0x1180880UL //Access:RW   DataWidth:0x2   Aggregation Task FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
66371 #define TCM_REG_SM_TASK_FIC_BUF_CRD                                                                  0x1180884UL //Access:RW   DataWidth:0x2   Storm Task FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
66372 #define TCM_REG_AGG_TASK_BUF_CRD_AGG                                                                 0x1180888UL //Access:RW   DataWidth:0x3   Aggregation Task buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
66373 #define TCM_REG_AGG_TASK_BUF_CRD_AGGST                                                               0x118088cUL //Access:RW   DataWidth:0x3   Aggregation Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
66374 #define TCM_REG_SM_TASK_BUF_CRD_AGGST                                                                0x1180890UL //Access:RW   DataWidth:0x1   Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.  Chips: BB_A0 BB_B0 K2
66375 #define TCM_REG_AGG_TASK_CMD_BUF_CRD_DIR                                                             0x1180894UL //Access:RW   DataWidth:0x2   Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
66376 #define TCM_REG_SM_TASK_CMD_BUF_CRD_DIR                                                              0x1180898UL //Access:RW   DataWidth:0x2   Storm Task command buffer credit (Direct group). In sum with CM_REGISTERS_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.  Chips: BB_A0 BB_B0 K2
66377 #define TCM_REG_TRANS_DATA_BUF_CRD_DIR                                                               0x118089cUL //Access:RW   DataWidth:0x2   Transparent data buffer credit (Direct group).  Chips: BB_A0 BB_B0 K2
66378 #define TCM_REG_AGG_CON_CTX_SIZE_0                                                                   0x11808a0UL //Access:RW   DataWidth:0x3   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less or 3.  Chips: BB_A0 BB_B0 K2
66379 #define TCM_REG_AGG_CON_CTX_SIZE_1                                                                   0x11808a4UL //Access:RW   DataWidth:0x3   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
66380 #define TCM_REG_AGG_CON_CTX_SIZE_2                                                                   0x11808a8UL //Access:RW   DataWidth:0x3   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
66381 #define TCM_REG_AGG_CON_CTX_SIZE_3                                                                   0x11808acUL //Access:RW   DataWidth:0x3   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
66382 #define TCM_REG_AGG_CON_CTX_SIZE_4                                                                   0x11808b0UL //Access:RW   DataWidth:0x3   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
66383 #define TCM_REG_AGG_CON_CTX_SIZE_5                                                                   0x11808b4UL //Access:RW   DataWidth:0x3   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
66384 #define TCM_REG_AGG_CON_CTX_SIZE_6                                                                   0x11808b8UL //Access:RW   DataWidth:0x3   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
66385 #define TCM_REG_AGG_CON_CTX_SIZE_7                                                                   0x11808bcUL //Access:RW   DataWidth:0x3   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: XCM: 4 REGQ aligned or 3. Other CM: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
66386 #define TCM_REG_AGG_TASK_CTX_SIZE_0                                                                  0x11808c0UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
66387 #define TCM_REG_AGG_TASK_CTX_SIZE_1                                                                  0x11808c4UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
66388 #define TCM_REG_AGG_TASK_CTX_SIZE_2                                                                  0x11808c8UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
66389 #define TCM_REG_AGG_TASK_CTX_SIZE_3                                                                  0x11808ccUL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
66390 #define TCM_REG_AGG_TASK_CTX_SIZE_4                                                                  0x11808d0UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
66391 #define TCM_REG_AGG_TASK_CTX_SIZE_5                                                                  0x11808d4UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
66392 #define TCM_REG_AGG_TASK_CTX_SIZE_6                                                                  0x11808d8UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
66393 #define TCM_REG_AGG_TASK_CTX_SIZE_7                                                                  0x11808dcUL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
66394 #define TCM_REG_SM_CON_CTX_SIZE                                                                      0x11808e0UL //Access:RW   DataWidth:0x5   STORM Connnection context per LCID size (REGQ). Default context size of 16 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 26. Maximum number of LCIDs allowed at maximum context size per LCID is 196. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(16/2))/(26/2)).  Chips: BB_A0 BB_B0 K2
66395 #define TCM_REG_SM_TASK_CTX_SIZE                                                                     0x11808e4UL //Access:RW   DataWidth:0x4   STORM Task context per LTID size (REGQ). Default context size of 4 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 12. Maximum number of LTIDs allowed at maximum context size per LTID is 52. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER((320*INTEGER(4/2))/(12/2)).  Chips: BB_A0 BB_B0 K2
66396 #define TCM_REG_CON_PHY_Q0                                                                           0x1180904UL //Access:RW   DataWidth:0x9   Physical queue connection number (queue number 0).  Chips: BB_A0 BB_B0 K2
66397 #define TCM_REG_CON_PHY_Q1                                                                           0x1180908UL //Access:RW   DataWidth:0x9   Physical queue connection number (queue number 1).  Chips: BB_A0 BB_B0 K2
66398 #define TCM_REG_TASK_PHY_Q0                                                                          0x118090cUL //Access:RW   DataWidth:0x7   Physical queue task number (queue number 0).  Chips: BB_A0 BB_B0 K2
66399 #define TCM_REG_TASK_PHY_Q1                                                                          0x1180910UL //Access:RW   DataWidth:0x7   Physical queue task number (queue number 1).  Chips: BB_A0 BB_B0 K2
66400 #define TCM_REG_AGG_CON_CF0_Q                                                                        0x1180914UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66401 #define TCM_REG_AGG_CON_CF1_Q                                                                        0x1180918UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66402 #define TCM_REG_AGG_CON_CF2_Q                                                                        0x118091cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66403 #define TCM_REG_AGG_CON_CF3_Q                                                                        0x1180920UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66404 #define TCM_REG_AGG_CON_CF4_Q                                                                        0x1180924UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66405 #define TCM_REG_AGG_CON_CF5_Q                                                                        0x1180928UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66406 #define TCM_REG_AGG_CON_CF6_Q                                                                        0x118092cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66407 #define TCM_REG_AGG_CON_CF7_Q                                                                        0x1180930UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66408 #define TCM_REG_AGG_CON_CF8_Q                                                                        0x1180934UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66409 #define TCM_REG_AGG_CON_CF9_Q                                                                        0x1180938UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66410 #define TCM_REG_AGG_CON_CF10_Q                                                                       0x118093cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66411 #define TCM_REG_AGG_CON_RULE0_Q                                                                      0x1180940UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66412 #define TCM_REG_AGG_CON_RULE1_Q                                                                      0x1180944UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66413 #define TCM_REG_AGG_CON_RULE2_Q                                                                      0x1180948UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66414 #define TCM_REG_AGG_CON_RULE3_Q                                                                      0x118094cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66415 #define TCM_REG_AGG_CON_RULE4_Q                                                                      0x1180950UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66416 #define TCM_REG_AGG_CON_RULE5_Q                                                                      0x1180954UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).:  Chips: BB_A0 BB_B0 K2
66417 #define TCM_REG_AGG_CON_RULE6_Q                                                                      0x1180958UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66418 #define TCM_REG_AGG_CON_RULE7_Q                                                                      0x118095cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66419 #define TCM_REG_AGG_CON_RULE8_Q                                                                      0x1180960UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66420 #define TCM_REG_AGG_TASK_CF0_Q                                                                       0x1180964UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66421 #define TCM_REG_AGG_TASK_CF1_Q                                                                       0x1180968UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66422 #define TCM_REG_AGG_TASK_CF2_Q                                                                       0x118096cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66423 #define TCM_REG_AGG_TASK_CF3_Q                                                                       0x1180970UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66424 #define TCM_REG_AGG_TASK_CF4_Q                                                                       0x1180974UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66425 #define TCM_REG_AGG_TASK_CF5_Q                                                                       0x1180978UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66426 #define TCM_REG_AGG_TASK_CF6_Q                                                                       0x118097cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66427 #define TCM_REG_AGG_TASK_CF7_Q                                                                       0x1180980UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66428 #define TCM_REG_AGG_TASK_RULE0_Q                                                                     0x1180984UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66429 #define TCM_REG_AGG_TASK_RULE1_Q                                                                     0x1180988UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66430 #define TCM_REG_AGG_TASK_RULE2_Q                                                                     0x118098cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66431 #define TCM_REG_AGG_TASK_RULE3_Q                                                                     0x1180990UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66432 #define TCM_REG_AGG_TASK_RULE4_Q                                                                     0x1180994UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66433 #define TCM_REG_AGG_TASK_RULE5_Q                                                                     0x1180998UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
66434 #define TCM_REG_IN_PRCS_TBL_CRD_AGG                                                                  0x1180a04UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
66435 #define TCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                0x1180a08UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
66436 #define TCM_REG_IN_PRCS_TBL_FILL_LVL                                                                 0x1180a0cUL //Access:R    DataWidth:0x4   In-process Table fill level  (in messages).  Chips: BB_A0 BB_B0 K2
66437 #define TCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                              0x1180a10UL //Access:R    DataWidth:0x1   In-process Table almost full.  Chips: BB_A0 BB_B0 K2
66438 #define TCM_REG_QMCON_CURR_ST                                                                        0x1180a14UL //Access:R    DataWidth:0x3   QM connection registration FSM current state.  Chips: BB_A0 BB_B0 K2
66439 #define TCM_REG_QMTASK_CURR_ST                                                                       0x1180a18UL //Access:R    DataWidth:0x3   QM task registration FSM current state.  Chips: BB_A0 BB_B0 K2
66440 #define TCM_REG_TMCON_CURR_ST                                                                        0x1180a1cUL //Access:R    DataWidth:0x1   TM connection output FSM current state.  Chips: BB_A0 BB_B0 K2
66441 #define TCM_REG_TMTASK_CURR_ST                                                                       0x1180a20UL //Access:R    DataWidth:0x1   TM task output FSM current state.  Chips: BB_A0 BB_B0 K2
66442 #define TCM_REG_CCFC_CURR_ST                                                                         0x1180a24UL //Access:R    DataWidth:0x1   CFC connection output FSM current state.  Chips: BB_A0 BB_B0 K2
66443 #define TCM_REG_TCFC_CURR_ST                                                                         0x1180a28UL //Access:R    DataWidth:0x1   CFC task output FSM current state.  Chips: BB_A0 BB_B0 K2
66444 #define TCM_REG_CMPL_DIR_CURR_ST                                                                     0x1180a2cUL //Access:R    DataWidth:0x4   Direct Completer FSM current state.  Chips: BB_A0 BB_B0 K2
66445 #define TCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                         0x1180a30UL //Access:RW   DataWidth:0x1   If set, Xx connection bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
66446 #define TCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG                                                        0x1180a34UL //Access:RW   DataWidth:0x1   If set, Xx task bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
66447 #define TCM_REG_CCFC_INIT_CRD                                                                        0x1180a84UL //Access:RW   DataWidth:0x4   CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
66448 #define TCM_REG_TCFC_INIT_CRD                                                                        0x1180a88UL //Access:RW   DataWidth:0x4   TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
66449 #define TCM_REG_QM_INIT_CRD0                                                                         0x1180a8cUL //Access:RW   DataWidth:0x5   QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
66450 #define TCM_REG_TM_INIT_CRD                                                                          0x1180a90UL //Access:RW   DataWidth:0x4   Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
66451 #define TCM_REG_FIC_INIT_CRD                                                                         0x1180a94UL //Access:RW   DataWidth:0x6   FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.  Chips: BB_A0 BB_B0 K2
66452 #define TCM_REG_DIR_BYP_MSG_CNT                                                                      0x1180aa4UL //Access:RC   DataWidth:0x20  Counter of direct bypassed messages.  Chips: BB_A0 BB_B0 K2
66453 #define TCM_REG_TSDM_LENGTH_MIS                                                                      0x1180aa8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at TSDM interface.  Chips: BB_A0 BB_B0 K2
66454 #define TCM_REG_DORQ_LENGTH_MIS                                                                      0x1180aacUL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at the dorq interface.  Chips: BB_A0 BB_B0 K2
66455 #define TCM_REG_PBF_LENGTH_MIS                                                                       0x1180ab0UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at PBF interface.  Chips: BB_A0 BB_B0 K2
66456 #define TCM_REG_PRS_LENGTH_MIS                                                                       0x1180ab4UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at PRS interface.  Chips: BB_A0 BB_B0 K2
66457 #define TCM_REG_GRC_BUF_EMPTY                                                                        0x1180ab8UL //Access:R    DataWidth:0x1   Input Stage GRC buffer is empty.  Chips: BB_A0 BB_B0 K2
66458 #define TCM_REG_GRC_BUF_STATUS                                                                       0x1180abcUL //Access:R    DataWidth:0x6   Input Stage GRC buffer status.  Chips: BB_A0 BB_B0 K2
66459 #define TCM_REG_STORM_MSG_CNTR                                                                       0x1180ac0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the STORM input.  Chips: BB_A0 BB_B0 K2
66460 #define TCM_REG_TSDM_MSG_CNTR                                                                        0x1180ac4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input TSDM.  Chips: BB_A0 BB_B0 K2
66461 #define TCM_REG_MSEM_MSG_CNTR                                                                        0x1180ac8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input MSEM.  Chips: BB_A0 BB_B0 K2
66462 #define TCM_REG_YSEM_MSG_CNTR                                                                        0x1180accUL //Access:RC   DataWidth:0x1c  Counter of the input messages at input Ysem.  Chips: BB_A0 BB_B0 K2
66463 #define TCM_REG_DORQ_MSG_CNTR                                                                        0x1180ad0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at  input DORQ.  Chips: BB_A0 BB_B0 K2
66464 #define TCM_REG_PBF_MSG_CNTR                                                                         0x1180ad4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input PBF.  Chips: BB_A0 BB_B0 K2
66465 #define TCM_REG_PRS_MSG_CNTR                                                                         0x1180ad8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input PRS.  Chips: BB_A0 BB_B0 K2
66466 #define TCM_REG_QM_P_MSG_CNTR                                                                        0x1180adcUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (primary).  Chips: BB_A0 BB_B0 K2
66467 #define TCM_REG_QM_S_MSG_CNTR                                                                        0x1180ae0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (secondary).  Chips: BB_A0 BB_B0 K2
66468 #define TCM_REG_TM_MSG_CNTR                                                                          0x1180ae4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the Timers input.  Chips: BB_A0 BB_B0 K2
66469 #define TCM_REG_IS_GRC                                                                               0x1180ae8UL //Access:W    DataWidth:0x20  Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done  Chips: BB_A0 BB_B0 K2
66470 #define TCM_REG_IS_QM_P_FILL_LVL                                                                     0x1180aecUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
66471 #define TCM_REG_IS_QM_S_FILL_LVL                                                                     0x1180af0UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
66472 #define TCM_REG_IS_TM_FILL_LVL                                                                       0x1180af4UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in TM Input Stage.  Chips: BB_A0 BB_B0 K2
66473 #define TCM_REG_IS_STORM_FILL_LVL                                                                    0x1180af8UL //Access:R    DataWidth:0x6   Number of QREGs (128b) of data in STORM Input Stage.  Chips: BB_A0 BB_B0 K2
66474 #define TCM_REG_IS_TSDM_FILL_LVL                                                                     0x1180afcUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in TSDM Input Stage.  Chips: BB_A0 BB_B0 K2
66475 #define TCM_REG_IS_MSEM_FILL_LVL                                                                     0x1180b00UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in MSEM Input Stage.  Chips: BB_A0 BB_B0 K2
66476 #define TCM_REG_IS_YSEM_FILL_LVL                                                                     0x1180b04UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in YSEM Input Stage.  Chips: BB_A0 BB_B0 K2
66477 #define TCM_REG_IS_DORQ_FILL_LVL                                                                     0x1180b08UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in DORQ Input Stage.  Chips: BB_A0 BB_B0 K2
66478 #define TCM_REG_IS_PBF_FILL_LVL                                                                      0x1180b0cUL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in PBF Input Stage.  Chips: BB_A0 BB_B0 K2
66479 #define TCM_REG_IS_PRS_FILL_LVL                                                                      0x1180b10UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in PRS Input Stage.  Chips: BB_A0 BB_B0 K2
66480 #define TCM_REG_FIC_MSG_CNTR                                                                         0x1180b44UL //Access:RC   DataWidth:0x1c  Counter of the output messages at FIC interfaces.  Chips: BB_A0 BB_B0 K2
66481 #define TCM_REG_QM_OUT_CNTR                                                                          0x1180b48UL //Access:RC   DataWidth:0x1c  Counter of the output QM commands.  Chips: BB_A0 BB_B0 K2
66482 #define TCM_REG_TM_OUT_CNTR                                                                          0x1180b4cUL //Access:RC   DataWidth:0x1c  Counter of the output Timers commands.  Chips: BB_A0 BB_B0 K2
66483 #define TCM_REG_DONE0_CNTR                                                                           0x1180b50UL //Access:RC   DataWidth:0x1c  Counter of the output Done0.  Chips: BB_A0 BB_B0 K2
66484 #define TCM_REG_DONE2_CNTR                                                                           0x1180b54UL //Access:RC   DataWidth:0x1c  Counter of the output Done2.  Chips: BB_A0 BB_B0 K2
66485 #define TCM_REG_CCFC_CNTR                                                                            0x1180b58UL //Access:RC   DataWidth:0x1c  Counter of the output CCFC.  Chips: BB_A0 BB_B0 K2
66486 #define TCM_REG_TCFC_CNTR                                                                            0x1180b5cUL //Access:RC   DataWidth:0x1c  Counter of the output TCFC.  Chips: BB_A0 BB_B0 K2
66487 #define TCM_REG_ECO_RESERVED                                                                         0x1180b84UL //Access:RW   DataWidth:0x8   Chicken bits.  Chips: BB_A0 BB_B0 K2
66488 #define TCM_REG_IS_FOC_TSEM_NXT_INF_UNIT                                                             0x1180b88UL //Access:R    DataWidth:0x6   Debug read from TSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
66489 #define TCM_REG_IS_FOC_MSEM_NXT_INF_UNIT                                                             0x1180b8cUL //Access:R    DataWidth:0x6   Debug read from MSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
66490 #define TCM_REG_IS_FOC_YSEM_NXT_INF_UNIT                                                             0x1180b90UL //Access:R    DataWidth:0x6   Debug read from YSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
66491 #define TCM_REG_IS_FOC_PRS_NXT_INF_UNIT                                                              0x1180b94UL //Access:R    DataWidth:0x6   Debug read from PRS Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
66492 #define TCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                              0x1180b98UL //Access:R    DataWidth:0x6   Debug read from PBF Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
66493 #define TCM_REG_IS_FOC_DORQ_NXT_INF_UNIT                                                             0x1180b9cUL //Access:R    DataWidth:0x6   Debug read from DORQ Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
66494 #define TCM_REG_IS_FOC_TSDM_NXT_INF_UNIT                                                             0x1180ba0UL //Access:R    DataWidth:0x6   Debug read from TSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
66495 #define TCM_REG_IS_FOC_TSEM                                                                          0x1180c00UL //Access:R    DataWidth:0x20  Debug read from TSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
66496 #define TCM_REG_IS_FOC_TSEM_SIZE                                                                     180
66497 #define TCM_REG_IS_FOC_MSEM                                                                          0x1181000UL //Access:R    DataWidth:0x20  Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
66498 #define TCM_REG_IS_FOC_MSEM_SIZE                                                                     24
66499 #define TCM_REG_IS_FOC_YSEM                                                                          0x1181100UL //Access:R    DataWidth:0x20  Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
66500 #define TCM_REG_IS_FOC_YSEM_SIZE                                                                     60
66501 #define TCM_REG_IS_FOC_PRS                                                                           0x1181200UL //Access:R    DataWidth:0x20  Debug read from PRS Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
66502 #define TCM_REG_IS_FOC_PRS_SIZE                                                                      44
66503 #define TCM_REG_IS_FOC_PBF                                                                           0x1181300UL //Access:R    DataWidth:0x20  Debug read from PBF Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
66504 #define TCM_REG_IS_FOC_PBF_SIZE                                                                      44
66505 #define TCM_REG_IS_FOC_DORQ                                                                          0x1181400UL //Access:R    DataWidth:0x20  Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
66506 #define TCM_REG_IS_FOC_DORQ_SIZE                                                                     24
66507 #define TCM_REG_IS_FOC_TSDM                                                                          0x1181480UL //Access:R    DataWidth:0x20  Debug read from TSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
66508 #define TCM_REG_IS_FOC_TSDM_SIZE                                                                     16
66509 #define TCM_REG_CTX_RBC_ACCS                                                                         0x11814c0UL //Access:RW   DataWidth:0x10  Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX  Chips: BB_A0 BB_B0 K2
66510 #define TCM_REG_AGG_CON_CTX                                                                          0x11814c4UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
66511 #define TCM_REG_AGG_TASK_CTX                                                                         0x11814c8UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
66512 #define TCM_REG_SM_CON_CTX                                                                           0x11814ccUL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
66513 #define TCM_REG_SM_TASK_CTX                                                                          0x11814d0UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
66514 #define TCM_REG_XX_CBYP_TBL                                                                          0x11814e0UL //Access:R    DataWidth:0xf   Xx Connection Bypass Table.  Chips: BB_A0 BB_B0 K2
66515 #define TCM_REG_XX_CBYP_TBL_SIZE                                                                     8
66516 #define TCM_REG_XX_TBYP_TBL                                                                          0x1181500UL //Access:R    DataWidth:0xf   Xx Task Bypass Table.  Chips: BB_A0 BB_B0 K2
66517 #define TCM_REG_XX_TBYP_TBL_SIZE                                                                     32
66518 #define TCM_REG_XX_LCID_CAM                                                                          0x1181600UL //Access:R    DataWidth:0xa   Debug only. Read only access to LCID CAM in XX protection mechanism.  Chips: BB_A0 BB_B0 K2
66519 #define TCM_REG_XX_LCID_CAM_SIZE                                                                     32
66520 #define TCM_REG_XX_TBL                                                                               0x1181700UL //Access:R    DataWidth:0x17  Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [3:1] - Connection type; LL size: PCM - [6:4]; M/T/U/X/YCM - [10:4]; Tail pointer: PCM - [8:7]; M/T/U/X/YCM - [16:11]; Next pointer: PCM - [10:9]; M/T/U/X/YCM - [22:17];  Chips: BB_A0 BB_B0 K2
66521 #define TCM_REG_XX_TBL_SIZE                                                                          32
66522 #define TCM_REG_XX_DSCR_TBL                                                                          0x1181800UL //Access:RW   DataWidth:0x1e  Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.  Chips: BB_A0 BB_B0 K2
66523 #define TCM_REG_XX_DSCR_TBL_SIZE                                                                     64
66524 #define TCM_REG_XX_MSG_RAM                                                                           0x1188000UL //Access:R    DataWidth:0x20  Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.  Chips: BB_A0 BB_B0 K2
66525 #define TCM_REG_XX_MSG_RAM_SIZE                                                                      5632
66526 #define MCM_REG_INIT                                                                                 0x1200000UL //Access:RW   DataWidth:0x1   Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.  Chips: BB_A0 BB_B0 K2
66527 #define MCM_REG_DBG_SELECT                                                                           0x1200040UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
66528 #define MCM_REG_DBG_DWORD_ENABLE                                                                     0x1200044UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
66529 #define MCM_REG_DBG_SHIFT                                                                            0x1200048UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
66530 #define MCM_REG_DBG_FORCE_VALID                                                                      0x120004cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
66531 #define MCM_REG_DBG_FORCE_FRAME                                                                      0x1200050UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
66532 #define MCM_REG_DBG_OUT_DATA                                                                         0x1200060UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
66533 #define MCM_REG_DBG_OUT_DATA_SIZE                                                                    8
66534 #define MCM_REG_DBG_OUT_VALID                                                                        0x1200080UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
66535 #define MCM_REG_DBG_OUT_FRAME                                                                        0x1200084UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
66536 #define MCM_REG_INT_STS_0                                                                            0x1200180UL //Access:R    DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66537     #define MCM_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
66538     #define MCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
66539     #define MCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                      (0x1<<1) // Write to full STORM input buffer.
66540     #define MCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                1
66541     #define MCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                     (0x1<<2) // Read from empty  STORM input buffer.
66542     #define MCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                               2
66543     #define MCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR                                                       (0x1<<3) // Write to full MSDM input buffer.
66544     #define MCM_REG_INT_STS_0_IS_MSDM_OVFL_ERR_SHIFT                                                 3
66545     #define MCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR                                                      (0x1<<4) // Read from empty MSDM input buffer.
66546     #define MCM_REG_INT_STS_0_IS_MSDM_UNDER_ERR_SHIFT                                                4
66547     #define MCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR                                                       (0x1<<5) // Write to full YSDM input buffer.
66548     #define MCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT                                                 5
66549     #define MCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR                                                      (0x1<<6) // Read from empty  YSDM input buffer.
66550     #define MCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT                                                6
66551     #define MCM_REG_INT_STS_0_IS_USDM_OVFL_ERR                                                       (0x1<<7) // Write to full USDM input buffer.
66552     #define MCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_SHIFT                                                 7
66553     #define MCM_REG_INT_STS_0_IS_USDM_UNDER_ERR                                                      (0x1<<8) // Read from empty USDM input buffer.
66554     #define MCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_SHIFT                                                8
66555     #define MCM_REG_INT_STS_0_IS_TMLD_OVFL_ERR                                                       (0x1<<9) // Write to full TMLD input buffer.
66556     #define MCM_REG_INT_STS_0_IS_TMLD_OVFL_ERR_SHIFT                                                 9
66557     #define MCM_REG_INT_STS_0_IS_TMLD_UNDER_ERR                                                      (0x1<<10) // Read from empty TMLD input buffer.
66558     #define MCM_REG_INT_STS_0_IS_TMLD_UNDER_ERR_SHIFT                                                10
66559     #define MCM_REG_INT_STS_0_IS_USEM_OVFL_ERR                                                       (0x1<<11) // Write to full Usem input buffer.
66560     #define MCM_REG_INT_STS_0_IS_USEM_OVFL_ERR_SHIFT                                                 11
66561     #define MCM_REG_INT_STS_0_IS_USEM_UNDER_ERR                                                      (0x1<<12) // Read from empty Usem input buffer.
66562     #define MCM_REG_INT_STS_0_IS_USEM_UNDER_ERR_SHIFT                                                12
66563     #define MCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR                                                       (0x1<<13) // Write to full Ysem input buffer.
66564     #define MCM_REG_INT_STS_0_IS_YSEM_OVFL_ERR_SHIFT                                                 13
66565 #define MCM_REG_INT_MASK_0                                                                           0x1200184UL //Access:RW   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66566     #define MCM_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.ADDRESS_ERROR .
66567     #define MCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
66568     #define MCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
66569     #define MCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                               1
66570     #define MCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
66571     #define MCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                              2
66572     #define MCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_MSDM_OVFL_ERR .
66573     #define MCM_REG_INT_MASK_0_IS_MSDM_OVFL_ERR_SHIFT                                                3
66574     #define MCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_MSDM_UNDER_ERR .
66575     #define MCM_REG_INT_MASK_0_IS_MSDM_UNDER_ERR_SHIFT                                               4
66576     #define MCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
66577     #define MCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT                                                5
66578     #define MCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
66579     #define MCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT                                               6
66580     #define MCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
66581     #define MCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_SHIFT                                                7
66582     #define MCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
66583     #define MCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_SHIFT                                               8
66584     #define MCM_REG_INT_MASK_0_IS_TMLD_OVFL_ERR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TMLD_OVFL_ERR .
66585     #define MCM_REG_INT_MASK_0_IS_TMLD_OVFL_ERR_SHIFT                                                9
66586     #define MCM_REG_INT_MASK_0_IS_TMLD_UNDER_ERR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_TMLD_UNDER_ERR .
66587     #define MCM_REG_INT_MASK_0_IS_TMLD_UNDER_ERR_SHIFT                                               10
66588     #define MCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USEM_OVFL_ERR .
66589     #define MCM_REG_INT_MASK_0_IS_USEM_OVFL_ERR_SHIFT                                                11
66590     #define MCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_USEM_UNDER_ERR .
66591     #define MCM_REG_INT_MASK_0_IS_USEM_UNDER_ERR_SHIFT                                               12
66592     #define MCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR                                                      (0x1<<13) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_0.IS_YSEM_OVFL_ERR .
66593     #define MCM_REG_INT_MASK_0_IS_YSEM_OVFL_ERR_SHIFT                                                13
66594 #define MCM_REG_INT_STS_WR_0                                                                         0x1200188UL //Access:WR   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66595     #define MCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
66596     #define MCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
66597     #define MCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                   (0x1<<1) // Write to full STORM input buffer.
66598     #define MCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                             1
66599     #define MCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                  (0x1<<2) // Read from empty  STORM input buffer.
66600     #define MCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                            2
66601     #define MCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR                                                    (0x1<<3) // Write to full MSDM input buffer.
66602     #define MCM_REG_INT_STS_WR_0_IS_MSDM_OVFL_ERR_SHIFT                                              3
66603     #define MCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR                                                   (0x1<<4) // Read from empty MSDM input buffer.
66604     #define MCM_REG_INT_STS_WR_0_IS_MSDM_UNDER_ERR_SHIFT                                             4
66605     #define MCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR                                                    (0x1<<5) // Write to full YSDM input buffer.
66606     #define MCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT                                              5
66607     #define MCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR                                                   (0x1<<6) // Read from empty  YSDM input buffer.
66608     #define MCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT                                             6
66609     #define MCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR                                                    (0x1<<7) // Write to full USDM input buffer.
66610     #define MCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_SHIFT                                              7
66611     #define MCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR                                                   (0x1<<8) // Read from empty USDM input buffer.
66612     #define MCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_SHIFT                                             8
66613     #define MCM_REG_INT_STS_WR_0_IS_TMLD_OVFL_ERR                                                    (0x1<<9) // Write to full TMLD input buffer.
66614     #define MCM_REG_INT_STS_WR_0_IS_TMLD_OVFL_ERR_SHIFT                                              9
66615     #define MCM_REG_INT_STS_WR_0_IS_TMLD_UNDER_ERR                                                   (0x1<<10) // Read from empty TMLD input buffer.
66616     #define MCM_REG_INT_STS_WR_0_IS_TMLD_UNDER_ERR_SHIFT                                             10
66617     #define MCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR                                                    (0x1<<11) // Write to full Usem input buffer.
66618     #define MCM_REG_INT_STS_WR_0_IS_USEM_OVFL_ERR_SHIFT                                              11
66619     #define MCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR                                                   (0x1<<12) // Read from empty Usem input buffer.
66620     #define MCM_REG_INT_STS_WR_0_IS_USEM_UNDER_ERR_SHIFT                                             12
66621     #define MCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR                                                    (0x1<<13) // Write to full Ysem input buffer.
66622     #define MCM_REG_INT_STS_WR_0_IS_YSEM_OVFL_ERR_SHIFT                                              13
66623 #define MCM_REG_INT_STS_CLR_0                                                                        0x120018cUL //Access:RC   DataWidth:0xe   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66624     #define MCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
66625     #define MCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
66626     #define MCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                  (0x1<<1) // Write to full STORM input buffer.
66627     #define MCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                            1
66628     #define MCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                 (0x1<<2) // Read from empty  STORM input buffer.
66629     #define MCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                           2
66630     #define MCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR                                                   (0x1<<3) // Write to full MSDM input buffer.
66631     #define MCM_REG_INT_STS_CLR_0_IS_MSDM_OVFL_ERR_SHIFT                                             3
66632     #define MCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR                                                  (0x1<<4) // Read from empty MSDM input buffer.
66633     #define MCM_REG_INT_STS_CLR_0_IS_MSDM_UNDER_ERR_SHIFT                                            4
66634     #define MCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR                                                   (0x1<<5) // Write to full YSDM input buffer.
66635     #define MCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT                                             5
66636     #define MCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR                                                  (0x1<<6) // Read from empty  YSDM input buffer.
66637     #define MCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT                                            6
66638     #define MCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR                                                   (0x1<<7) // Write to full USDM input buffer.
66639     #define MCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_SHIFT                                             7
66640     #define MCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR                                                  (0x1<<8) // Read from empty USDM input buffer.
66641     #define MCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_SHIFT                                            8
66642     #define MCM_REG_INT_STS_CLR_0_IS_TMLD_OVFL_ERR                                                   (0x1<<9) // Write to full TMLD input buffer.
66643     #define MCM_REG_INT_STS_CLR_0_IS_TMLD_OVFL_ERR_SHIFT                                             9
66644     #define MCM_REG_INT_STS_CLR_0_IS_TMLD_UNDER_ERR                                                  (0x1<<10) // Read from empty TMLD input buffer.
66645     #define MCM_REG_INT_STS_CLR_0_IS_TMLD_UNDER_ERR_SHIFT                                            10
66646     #define MCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR                                                   (0x1<<11) // Write to full Usem input buffer.
66647     #define MCM_REG_INT_STS_CLR_0_IS_USEM_OVFL_ERR_SHIFT                                             11
66648     #define MCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR                                                  (0x1<<12) // Read from empty Usem input buffer.
66649     #define MCM_REG_INT_STS_CLR_0_IS_USEM_UNDER_ERR_SHIFT                                            12
66650     #define MCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR                                                   (0x1<<13) // Write to full Ysem input buffer.
66651     #define MCM_REG_INT_STS_CLR_0_IS_YSEM_OVFL_ERR_SHIFT                                             13
66652 #define MCM_REG_INT_STS_1                                                                            0x1200190UL //Access:R    DataWidth:0x1a  Multi Field Register.  Chips: BB_A0 BB_B0 K2
66653     #define MCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR                                                      (0x1<<0) // Read from empty  Ysem input buffer.
66654     #define MCM_REG_INT_STS_1_IS_YSEM_UNDER_ERR_SHIFT                                                0
66655     #define MCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                        (0x1<<1) // Write to full Pbf input buffer.
66656     #define MCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                  1
66657     #define MCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                       (0x1<<2) // Read from empty Pbf input buffer.
66658     #define MCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                 2
66659     #define MCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                       (0x1<<3) // Write to full QM input buffer.
66660     #define MCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                 3
66661     #define MCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                      (0x1<<4) // Read from empty QM input buffer.
66662     #define MCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                4
66663     #define MCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                       (0x1<<5) // Write to full QM input buffer.
66664     #define MCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                 5
66665     #define MCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                      (0x1<<6) // Read from empty QM input buffer.
66666     #define MCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                6
66667     #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                       (0x1<<7) // Write to full GRC input buffer bits [31:0].
66668     #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                 7
66669     #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                      (0x1<<8) // Read from empty  GRC input buffer bits [31:0].
66670     #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                8
66671     #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                       (0x1<<9) // Write to full GRC input buffer bits [63:32].
66672     #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                 9
66673     #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                      (0x1<<10) // Read from empty  GRC input buffer bits [63:32].
66674     #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                10
66675     #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                       (0x1<<11) // Write to full GRC input buffer bits [95:64].
66676     #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                 11
66677     #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                      (0x1<<12) // Read from empty  GRC input buffer bits [95:64].
66678     #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                12
66679     #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                       (0x1<<13) // Write to full GRC input buffer bits [127:96].
66680     #define MCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                 13
66681     #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                      (0x1<<14) // Read from empty  GRC input buffer bits [127:96].
66682     #define MCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                14
66683     #define MCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                       (0x1<<15) // In-process Table overflow.
66684     #define MCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                 15
66685     #define MCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL                                                  (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
66686     #define MCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                            16
66687     #define MCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL                                                   (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
66688     #define MCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                             17
66689     #define MCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                   (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
66690     #define MCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                             18
66691     #define MCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                    (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
66692     #define MCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                              19
66693     #define MCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL                                                 (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
66694     #define MCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                           20
66695     #define MCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL                                                  (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
66696     #define MCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                            21
66697     #define MCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL                                                  (0x1<<22) // Message Processor Storm Task Data buffer overflow.
66698     #define MCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                            22
66699     #define MCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL                                                   (0x1<<23) // Message Processor Storm Task Command buffer overflow.
66700     #define MCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                             23
66701     #define MCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                  (0x1<<24) // Input message first descriptor fields violation.
66702     #define MCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                            24
66703     #define MCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE                                                  (0x1<<25) // Input message second descriptor fields violation.
66704     #define MCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_SHIFT                                            25
66705 #define MCM_REG_INT_MASK_1                                                                           0x1200194UL //Access:RW   DataWidth:0x1a  Multi Field Register.  Chips: BB_A0 BB_B0 K2
66706     #define MCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR                                                     (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_YSEM_UNDER_ERR .
66707     #define MCM_REG_INT_MASK_1_IS_YSEM_UNDER_ERR_SHIFT                                               0
66708     #define MCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
66709     #define MCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                 1
66710     #define MCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                      (0x1<<2) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
66711     #define MCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                2
66712     #define MCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
66713     #define MCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                3
66714     #define MCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
66715     #define MCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                               4
66716     #define MCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
66717     #define MCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                5
66718     #define MCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
66719     #define MCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                               6
66720     #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
66721     #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                7
66722     #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
66723     #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                               8
66724     #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
66725     #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                9
66726     #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
66727     #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                               10
66728     #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
66729     #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                11
66730     #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
66731     #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                               12
66732     #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                      (0x1<<13) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
66733     #define MCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                13
66734     #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                     (0x1<<14) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
66735     #define MCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                               14
66736     #define MCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                      (0x1<<15) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
66737     #define MCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                15
66738     #define MCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL                                                 (0x1<<16) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
66739     #define MCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                           16
66740     #define MCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL                                                  (0x1<<17) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
66741     #define MCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                            17
66742     #define MCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                  (0x1<<18) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
66743     #define MCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                            18
66744     #define MCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                   (0x1<<19) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
66745     #define MCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                             19
66746     #define MCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL                                                (0x1<<20) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
66747     #define MCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                          20
66748     #define MCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL                                                 (0x1<<21) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
66749     #define MCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                           21
66750     #define MCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL                                                 (0x1<<22) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
66751     #define MCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                           22
66752     #define MCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL                                                  (0x1<<23) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
66753     #define MCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                            23
66754     #define MCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                 (0x1<<24) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
66755     #define MCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                           24
66756     #define MCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE                                                 (0x1<<25) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
66757     #define MCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_SHIFT                                           25
66758 #define MCM_REG_INT_STS_WR_1                                                                         0x1200198UL //Access:WR   DataWidth:0x1a  Multi Field Register.  Chips: BB_A0 BB_B0 K2
66759     #define MCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR                                                   (0x1<<0) // Read from empty  Ysem input buffer.
66760     #define MCM_REG_INT_STS_WR_1_IS_YSEM_UNDER_ERR_SHIFT                                             0
66761     #define MCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                     (0x1<<1) // Write to full Pbf input buffer.
66762     #define MCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                               1
66763     #define MCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                    (0x1<<2) // Read from empty Pbf input buffer.
66764     #define MCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                              2
66765     #define MCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                    (0x1<<3) // Write to full QM input buffer.
66766     #define MCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                              3
66767     #define MCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                   (0x1<<4) // Read from empty QM input buffer.
66768     #define MCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                             4
66769     #define MCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                    (0x1<<5) // Write to full QM input buffer.
66770     #define MCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                              5
66771     #define MCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                   (0x1<<6) // Read from empty QM input buffer.
66772     #define MCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                             6
66773     #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                    (0x1<<7) // Write to full GRC input buffer bits [31:0].
66774     #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                              7
66775     #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                   (0x1<<8) // Read from empty  GRC input buffer bits [31:0].
66776     #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                             8
66777     #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                    (0x1<<9) // Write to full GRC input buffer bits [63:32].
66778     #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                              9
66779     #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                   (0x1<<10) // Read from empty  GRC input buffer bits [63:32].
66780     #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                             10
66781     #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                    (0x1<<11) // Write to full GRC input buffer bits [95:64].
66782     #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                              11
66783     #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                   (0x1<<12) // Read from empty  GRC input buffer bits [95:64].
66784     #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                             12
66785     #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                    (0x1<<13) // Write to full GRC input buffer bits [127:96].
66786     #define MCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                              13
66787     #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                   (0x1<<14) // Read from empty  GRC input buffer bits [127:96].
66788     #define MCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                             14
66789     #define MCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                    (0x1<<15) // In-process Table overflow.
66790     #define MCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                              15
66791     #define MCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL                                               (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
66792     #define MCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                         16
66793     #define MCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL                                                (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
66794     #define MCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                          17
66795     #define MCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
66796     #define MCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                          18
66797     #define MCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                 (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
66798     #define MCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                           19
66799     #define MCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL                                              (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
66800     #define MCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                        20
66801     #define MCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL                                               (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
66802     #define MCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                         21
66803     #define MCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL                                               (0x1<<22) // Message Processor Storm Task Data buffer overflow.
66804     #define MCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                         22
66805     #define MCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL                                                (0x1<<23) // Message Processor Storm Task Command buffer overflow.
66806     #define MCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                          23
66807     #define MCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                               (0x1<<24) // Input message first descriptor fields violation.
66808     #define MCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                         24
66809     #define MCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE                                               (0x1<<25) // Input message second descriptor fields violation.
66810     #define MCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                         25
66811 #define MCM_REG_INT_STS_CLR_1                                                                        0x120019cUL //Access:RC   DataWidth:0x1a  Multi Field Register.  Chips: BB_A0 BB_B0 K2
66812     #define MCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR                                                  (0x1<<0) // Read from empty  Ysem input buffer.
66813     #define MCM_REG_INT_STS_CLR_1_IS_YSEM_UNDER_ERR_SHIFT                                            0
66814     #define MCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                    (0x1<<1) // Write to full Pbf input buffer.
66815     #define MCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                              1
66816     #define MCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                   (0x1<<2) // Read from empty Pbf input buffer.
66817     #define MCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                             2
66818     #define MCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                   (0x1<<3) // Write to full QM input buffer.
66819     #define MCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                             3
66820     #define MCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                  (0x1<<4) // Read from empty QM input buffer.
66821     #define MCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                            4
66822     #define MCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                   (0x1<<5) // Write to full QM input buffer.
66823     #define MCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                             5
66824     #define MCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                  (0x1<<6) // Read from empty QM input buffer.
66825     #define MCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                            6
66826     #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                   (0x1<<7) // Write to full GRC input buffer bits [31:0].
66827     #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                             7
66828     #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                  (0x1<<8) // Read from empty  GRC input buffer bits [31:0].
66829     #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                            8
66830     #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                   (0x1<<9) // Write to full GRC input buffer bits [63:32].
66831     #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                             9
66832     #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                  (0x1<<10) // Read from empty  GRC input buffer bits [63:32].
66833     #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                            10
66834     #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                   (0x1<<11) // Write to full GRC input buffer bits [95:64].
66835     #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                             11
66836     #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                  (0x1<<12) // Read from empty  GRC input buffer bits [95:64].
66837     #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                            12
66838     #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                   (0x1<<13) // Write to full GRC input buffer bits [127:96].
66839     #define MCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                             13
66840     #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                  (0x1<<14) // Read from empty  GRC input buffer bits [127:96].
66841     #define MCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                            14
66842     #define MCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                   (0x1<<15) // In-process Table overflow.
66843     #define MCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                             15
66844     #define MCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL                                              (0x1<<16) // Message Processor Aggregation Connection Data buffer overflow.
66845     #define MCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                        16
66846     #define MCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL                                               (0x1<<17) // Message Processor Aggregation Connection Command buffer overflow.
66847     #define MCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                         17
66848     #define MCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                               (0x1<<18) // Message Processor Storm Connection Data buffer overflow.
66849     #define MCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                         18
66850     #define MCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                (0x1<<19) // Message Processor Storm Connection Command buffer overflow.
66851     #define MCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                          19
66852     #define MCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL                                             (0x1<<20) // Message Processor Aggregation Task Data buffer overflow.
66853     #define MCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                       20
66854     #define MCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL                                              (0x1<<21) // Message Processor Aggregation Task Command buffer overflow.
66855     #define MCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                        21
66856     #define MCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL                                              (0x1<<22) // Message Processor Storm Task Data buffer overflow.
66857     #define MCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                        22
66858     #define MCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL                                               (0x1<<23) // Message Processor Storm Task Command buffer overflow.
66859     #define MCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                         23
66860     #define MCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                              (0x1<<24) // Input message first descriptor fields violation.
66861     #define MCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                        24
66862     #define MCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE                                              (0x1<<25) // Input message second descriptor fields violation.
66863     #define MCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                        25
66864 #define MCM_REG_INT_STS_2                                                                            0x12001a0UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66865     #define MCM_REG_INT_STS_2_QMREG_MORE4                                                            (0x1<<0) // More than 4 QM registrations.
66866     #define MCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                      0
66867 #define MCM_REG_INT_MASK_2                                                                           0x12001a4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66868     #define MCM_REG_INT_MASK_2_QMREG_MORE4                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: MCM_REG_INT_STS_2.QMREG_MORE4 .
66869     #define MCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                     0
66870 #define MCM_REG_INT_STS_WR_2                                                                         0x12001a8UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66871     #define MCM_REG_INT_STS_WR_2_QMREG_MORE4                                                         (0x1<<0) // More than 4 QM registrations.
66872     #define MCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                   0
66873 #define MCM_REG_INT_STS_CLR_2                                                                        0x12001acUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
66874     #define MCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                        (0x1<<0) // More than 4 QM registrations.
66875     #define MCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                  0
66876 #define MCM_REG_PRTY_MASK_H_0                                                                        0x1200204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
66877     #define MCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT .
66878     #define MCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_SHIFT                                          0
66879     #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM003_I_ECC_RF_INT .
66880     #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_RF_INT_SHIFT                                          1
66881     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_A0                                        (0x1<<6) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT .
66882     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_A0_SHIFT                                  6
66883     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_B0                                        (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT .
66884     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_BB_B0_SHIFT                                  2
66885     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_K2                                           (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_0_RF_INT .
66886     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_0_RF_INT_K2_SHIFT                                     2
66887     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_A0                                        (0x1<<7) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_1_RF_INT .
66888     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_A0_SHIFT                                  7
66889     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_B0                                        (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_1_RF_INT .
66890     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_BB_B0_SHIFT                                  3
66891     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_K2                                           (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM023_I_ECC_1_RF_INT .
66892     #define MCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_1_RF_INT_K2_SHIFT                                     3
66893     #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
66894     #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT                                        4
66895     #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT                                              (0x1<<5) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
66896     #define MCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT                                        5
66897     #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT                                              (0x1<<6) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_ECC_0_RF_INT .
66898     #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_SHIFT                                        6
66899     #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_ECC_1_RF_INT .
66900     #define MCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_SHIFT                                        7
66901     #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_A0                                          (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
66902     #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_A0_SHIFT                                    0
66903     #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_B0                                          (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
66904     #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_BB_B0_SHIFT                                    8
66905     #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_K2                                             (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
66906     #define MCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_K2_SHIFT                                       8
66907     #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<10) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
66908     #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      10
66909     #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<9) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
66910     #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      9
66911     #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                               (0x1<<9) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
66912     #define MCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                         9
66913     #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
66914     #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                      14
66915     #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<10) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
66916     #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      10
66917     #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                               (0x1<<10) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
66918     #define MCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                         10
66919     #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0                                            (0x1<<15) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
66920     #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                      15
66921     #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0                                            (0x1<<11) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
66922     #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                      11
66923     #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                               (0x1<<11) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
66924     #define MCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                         11
66925     #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0                                            (0x1<<9) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
66926     #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0_SHIFT                                      9
66927     #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
66928     #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0_SHIFT                                      12
66929     #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
66930     #define MCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                         12
66931     #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
66932     #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      27
66933     #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
66934     #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      13
66935     #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
66936     #define MCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                         13
66937     #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY                                                  (0x1<<14) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
66938     #define MCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_SHIFT                                            14
66939     #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
66940     #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                      13
66941     #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
66942     #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                      15
66943     #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
66944     #define MCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                         15
66945     #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0                                            (0x1<<18) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
66946     #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_A0_SHIFT                                      18
66947     #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
66948     #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_BB_B0_SHIFT                                      16
66949     #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
66950     #define MCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_K2_SHIFT                                         16
66951     #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
66952     #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_A0_SHIFT                                      19
66953     #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0                                            (0x1<<17) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
66954     #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_BB_B0_SHIFT                                      17
66955     #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2                                               (0x1<<17) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
66956     #define MCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_K2_SHIFT                                         17
66957     #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
66958     #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0_SHIFT                                      12
66959     #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0                                            (0x1<<18) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
66960     #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0_SHIFT                                      18
66961     #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
66962     #define MCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                         18
66963     #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0                                            (0x1<<11) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
66964     #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0_SHIFT                                      11
66965     #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0                                            (0x1<<19) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
66966     #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0_SHIFT                                      19
66967     #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
66968     #define MCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                         19
66969     #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY                                                  (0x1<<20) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
66970     #define MCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_SHIFT                                            20
66971     #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
66972     #define MCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_SHIFT                                            21
66973     #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
66974     #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0_SHIFT                                      20
66975     #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0                                            (0x1<<22) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
66976     #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0_SHIFT                                      22
66977     #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                               (0x1<<22) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
66978     #define MCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                         22
66979     #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0                                            (0x1<<25) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
66980     #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_A0_SHIFT                                      25
66981     #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0                                            (0x1<<23) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
66982     #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_BB_B0_SHIFT                                      23
66983     #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2                                               (0x1<<23) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
66984     #define MCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_K2_SHIFT                                         23
66985     #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                                  (0x1<<24) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
66986     #define MCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                            24
66987     #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0                                            (0x1<<30) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
66988     #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_A0_SHIFT                                      30
66989     #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0                                            (0x1<<25) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
66990     #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_BB_B0_SHIFT                                      25
66991     #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2                                               (0x1<<25) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
66992     #define MCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_K2_SHIFT                                         25
66993     #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0                                            (0x1<<22) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
66994     #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_A0_SHIFT                                      22
66995     #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0                                            (0x1<<26) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
66996     #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_BB_B0_SHIFT                                      26
66997     #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2                                               (0x1<<26) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
66998     #define MCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_K2_SHIFT                                         26
66999     #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
67000     #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_A0_SHIFT                                      24
67001     #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_B0                                            (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
67002     #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_BB_B0_SHIFT                                      27
67003     #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2                                               (0x1<<27) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
67004     #define MCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_K2_SHIFT                                         27
67005     #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0                                                (0x1<<28) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_0 .
67006     #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_0_SHIFT                                          28
67007     #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1                                                (0x1<<29) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY_1 .
67008     #define MCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_1_SHIFT                                          29
67009     #define MCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY                                                  (0x1<<30) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY .
67010     #define MCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_SHIFT                                            30
67011     #define MCM_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT                                                (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM001_I_ECC_RF_INT .
67012     #define MCM_REG_PRTY_MASK_H_0_MEM001_I_ECC_RF_INT_SHIFT                                          1
67013     #define MCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM021_I_ECC_0_RF_INT .
67014     #define MCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_0_RF_INT_SHIFT                                        2
67015     #define MCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM021_I_ECC_1_RF_INT .
67016     #define MCM_REG_PRTY_MASK_H_0_MEM021_I_ECC_1_RF_INT_SHIFT                                        3
67017     #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
67018     #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT                                        4
67019     #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT                                              (0x1<<5) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
67020     #define MCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_SHIFT                                        5
67021     #define MCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT                                                (0x1<<8) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM024_I_ECC_RF_INT .
67022     #define MCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_RF_INT_SHIFT                                          8
67023     #define MCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                  (0x1<<16) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
67024     #define MCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                            16
67025     #define MCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY .
67026     #define MCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_SHIFT                                            17
67027     #define MCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY                                                  (0x1<<21) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM028_I_MEM_PRTY .
67028     #define MCM_REG_PRTY_MASK_H_0_MEM028_I_MEM_PRTY_SHIFT                                            21
67029     #define MCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
67030     #define MCM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                            23
67031     #define MCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM025_I_MEM_PRTY .
67032     #define MCM_REG_PRTY_MASK_H_0_MEM025_I_MEM_PRTY_SHIFT                                            26
67033     #define MCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_0                                                (0x1<<28) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY_0 .
67034     #define MCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_0_SHIFT                                          28
67035     #define MCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_1                                                (0x1<<29) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY_1 .
67036     #define MCM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_1_SHIFT                                          29
67037 #define MCM_REG_PRTY_MASK_H_1                                                                        0x1200214UL //Access:RW   DataWidth:0x4   Multi Field Register.  Chips: BB_A0 BB_B0 K2
67038     #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
67039     #define MCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_SHIFT                                            0
67040     #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
67041     #define MCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_SHIFT                                            1
67042     #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
67043     #define MCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_SHIFT                                            2
67044     #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
67045     #define MCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_SHIFT                                            3
67046     #define MCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY                                                  (0x1<<0) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM007_I_MEM_PRTY .
67047     #define MCM_REG_PRTY_MASK_H_1_MEM007_I_MEM_PRTY_SHIFT                                            0
67048     #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY .
67049     #define MCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_SHIFT                                            1
67050     #define MCM_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM030_I_MEM_PRTY .
67051     #define MCM_REG_PRTY_MASK_H_1_MEM030_I_MEM_PRTY_SHIFT                                            2
67052     #define MCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: MCM_REG_PRTY_STS_H_1.MEM031_I_MEM_PRTY .
67053     #define MCM_REG_PRTY_MASK_H_1_MEM031_I_MEM_PRTY_SHIFT                                            3
67054 #define MCM_REG_MEM_ECC_EVENTS                                                                       0x1200234UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
67055 #define MCM_REG_MEM017_I_MEM_DFT_K2                                                                  0x120023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_is_storm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67056 #define MCM_REG_MEM019_I_MEM_DFT_K2                                                                  0x1200240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_is_usdm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67057 #define MCM_REG_MEM021_I_MEM_DFT_K2                                                                  0x1200244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_is_ysem_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67058 #define MCM_REG_MEM018_I_MEM_DFT_K2                                                                  0x1200248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_is_tmld_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67059 #define MCM_REG_MEM011_I_MEM_DFT_K2                                                                  0x120024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_is_grc0_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67060 #define MCM_REG_MEM012_I_MEM_DFT_K2                                                                  0x1200250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_is_grc1_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67061 #define MCM_REG_MEM013_I_MEM_DFT_K2                                                                  0x1200254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_is_grc2_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67062 #define MCM_REG_MEM014_I_MEM_DFT_K2                                                                  0x1200258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_is_grc3_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67063 #define MCM_REG_MEM028_I_MEM_DFT_K2                                                                  0x120025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_xx_msg_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
67064 #define MCM_REG_MEM031_I_MEM_DFT_K2                                                                  0x1200260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_xx_pref_dir.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67065 #define MCM_REG_MEM030_I_MEM_DFT_K2                                                                  0x1200264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_xx_pref_byp.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67066 #define MCM_REG_MEM029_I_MEM_DFT_K2                                                                  0x1200268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_xx_pref_aggst.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67067 #define MCM_REG_MEM004_I_MEM_DFT_K2                                                                  0x120026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_agg_con_data_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67068 #define MCM_REG_MEM003_I_MEM_DFT_K2                                                                  0x1200270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_agg_con_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
67069 #define MCM_REG_MEM024_I_MEM_DFT_K2                                                                  0x1200274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_sm_con_data_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67070 #define MCM_REG_MEM023_I_MEM_DFT_K2                                                                  0x1200278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_sm_con_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
67071 #define MCM_REG_MEM006_I_MEM_DFT_K2                                                                  0x120027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_agg_task_data_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67072 #define MCM_REG_MEM005_I_MEM_DFT_K2                                                                  0x1200280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_agg_task_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
67073 #define MCM_REG_MEM027_I_MEM_DFT_K2                                                                  0x1200284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_sm_task_data_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67074 #define MCM_REG_MEM025_I_MEM_DFT_K2                                                                  0x1200288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_sm_task_ctx_0_5.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
67075 #define MCM_REG_MEM026_I_MEM_DFT_K2                                                                  0x120028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_sm_task_ctx_6.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
67076 #define MCM_REG_MEM022_I_MEM_DFT_K2                                                                  0x1200290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_prcs_trans.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67077 #define MCM_REG_MEM007_I_MEM_DFT_K2                                                                  0x1200294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance mcm.i_in_prcs_msgin.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
67078 #define MCM_REG_IFEN                                                                                 0x1200400UL //Access:RW   DataWidth:0x1   Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
67079 #define MCM_REG_QM_CON_BASE_EVNT_ID_0                                                                0x1200404UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67080 #define MCM_REG_QM_CON_BASE_EVNT_ID_1                                                                0x1200408UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67081 #define MCM_REG_QM_CON_BASE_EVNT_ID_2                                                                0x120040cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67082 #define MCM_REG_QM_CON_BASE_EVNT_ID_3                                                                0x1200410UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67083 #define MCM_REG_QM_CON_BASE_EVNT_ID_4                                                                0x1200414UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67084 #define MCM_REG_QM_CON_BASE_EVNT_ID_5                                                                0x1200418UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67085 #define MCM_REG_QM_CON_BASE_EVNT_ID_6                                                                0x120041cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67086 #define MCM_REG_QM_CON_BASE_EVNT_ID_7                                                                0x1200420UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67087 #define MCM_REG_QM_TASK_BASE_EVNT_ID_0                                                               0x1200424UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67088 #define MCM_REG_QM_TASK_BASE_EVNT_ID_1                                                               0x1200428UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67089 #define MCM_REG_QM_TASK_BASE_EVNT_ID_2                                                               0x120042cUL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67090 #define MCM_REG_QM_TASK_BASE_EVNT_ID_3                                                               0x1200430UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67091 #define MCM_REG_QM_TASK_BASE_EVNT_ID_4                                                               0x1200434UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67092 #define MCM_REG_QM_TASK_BASE_EVNT_ID_5                                                               0x1200438UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67093 #define MCM_REG_QM_TASK_BASE_EVNT_ID_6                                                               0x120043cUL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67094 #define MCM_REG_QM_TASK_BASE_EVNT_ID_7                                                               0x1200440UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
67095 #define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_0                                                           0x1200444UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
67096 #define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_1                                                           0x1200448UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
67097 #define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_2                                                           0x120044cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
67098 #define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_3                                                           0x1200450UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
67099 #define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_4                                                           0x1200454UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
67100 #define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_5                                                           0x1200458UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
67101 #define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_6                                                           0x120045cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
67102 #define MCM_REG_QM_AGG_CON_CTX_PART_SIZE_7                                                           0x1200460UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
67103 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_0                                                             0x1200464UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
67104 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_1                                                             0x1200468UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
67105 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_2                                                             0x120046cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
67106 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_3                                                             0x1200470UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
67107 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_4                                                             0x1200474UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
67108 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_5                                                             0x1200478UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
67109 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_6                                                             0x120047cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
67110 #define MCM_REG_QM_SM_CON_CTX_LDST_FLG_7                                                             0x1200480UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
67111 #define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_0                                                          0x1200484UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
67112 #define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_1                                                          0x1200488UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
67113 #define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_2                                                          0x120048cUL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
67114 #define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_3                                                          0x1200490UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
67115 #define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_4                                                          0x1200494UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
67116 #define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_5                                                          0x1200498UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
67117 #define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_6                                                          0x120049cUL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
67118 #define MCM_REG_QM_AGG_TASK_CTX_PART_SIZE_7                                                          0x12004a0UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
67119 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_0                                                            0x12004a4UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
67120 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_1                                                            0x12004a8UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
67121 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_2                                                            0x12004acUL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
67122 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_3                                                            0x12004b0UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
67123 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_4                                                            0x12004b4UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
67124 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_5                                                            0x12004b8UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
67125 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_6                                                            0x12004bcUL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
67126 #define MCM_REG_QM_SM_TASK_CTX_LDST_FLG_7                                                            0x12004c0UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
67127 #define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_0                                                            0x12004c4UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
67128 #define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_1                                                            0x12004c8UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
67129 #define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_2                                                            0x12004ccUL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
67130 #define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_3                                                            0x12004d0UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
67131 #define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_4                                                            0x12004d4UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
67132 #define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_5                                                            0x12004d8UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
67133 #define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_6                                                            0x12004dcUL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
67134 #define MCM_REG_QM_TCFC_LOCK_UC_UPD_VAL_7                                                            0x12004e0UL //Access:RW   DataWidth:0x4   TCFC Lock UC Update value per task type.  Chips: BB_A0 BB_B0 K2
67135 #define MCM_REG_QM_TCFC_XXLOCK_CMD_0                                                                 0x12004e4UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
67136 #define MCM_REG_QM_TCFC_XXLOCK_CMD_1                                                                 0x12004e8UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
67137 #define MCM_REG_QM_TCFC_XXLOCK_CMD_2                                                                 0x12004ecUL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
67138 #define MCM_REG_QM_TCFC_XXLOCK_CMD_3                                                                 0x12004f0UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
67139 #define MCM_REG_QM_TCFC_XXLOCK_CMD_4                                                                 0x12004f4UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
67140 #define MCM_REG_QM_TCFC_XXLOCK_CMD_5                                                                 0x12004f8UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
67141 #define MCM_REG_QM_TCFC_XXLOCK_CMD_6                                                                 0x12004fcUL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
67142 #define MCM_REG_QM_TCFC_XXLOCK_CMD_7                                                                 0x1200500UL //Access:RW   DataWidth:0x3   TCFC Lock UC xxLock command per task type.  Chips: BB_A0 BB_B0 K2
67143 #define MCM_REG_QM_XXLOCK_CMD_0                                                                      0x1200504UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
67144 #define MCM_REG_QM_XXLOCK_CMD_1                                                                      0x1200508UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
67145 #define MCM_REG_QM_XXLOCK_CMD_2                                                                      0x120050cUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
67146 #define MCM_REG_QM_XXLOCK_CMD_3                                                                      0x1200510UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
67147 #define MCM_REG_QM_XXLOCK_CMD_4                                                                      0x1200514UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
67148 #define MCM_REG_QM_XXLOCK_CMD_5                                                                      0x1200518UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
67149 #define MCM_REG_QM_XXLOCK_CMD_6                                                                      0x120051cUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
67150 #define MCM_REG_QM_XXLOCK_CMD_7                                                                      0x1200520UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
67151 #define MCM_REG_QM_CON_USE_ST_FLG_0                                                                  0x1200524UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
67152 #define MCM_REG_QM_CON_USE_ST_FLG_1                                                                  0x1200528UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
67153 #define MCM_REG_QM_CON_USE_ST_FLG_2                                                                  0x120052cUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
67154 #define MCM_REG_QM_CON_USE_ST_FLG_3                                                                  0x1200530UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
67155 #define MCM_REG_QM_CON_USE_ST_FLG_4                                                                  0x1200534UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
67156 #define MCM_REG_QM_CON_USE_ST_FLG_5                                                                  0x1200538UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
67157 #define MCM_REG_QM_CON_USE_ST_FLG_6                                                                  0x120053cUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
67158 #define MCM_REG_QM_CON_USE_ST_FLG_7                                                                  0x1200540UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
67159 #define MCM_REG_QM_TASK_USE_ST_FLG_0                                                                 0x1200544UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
67160 #define MCM_REG_QM_TASK_USE_ST_FLG_1                                                                 0x1200548UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
67161 #define MCM_REG_QM_TASK_USE_ST_FLG_2                                                                 0x120054cUL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
67162 #define MCM_REG_QM_TASK_USE_ST_FLG_3                                                                 0x1200550UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
67163 #define MCM_REG_QM_TASK_USE_ST_FLG_4                                                                 0x1200554UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
67164 #define MCM_REG_QM_TASK_USE_ST_FLG_5                                                                 0x1200558UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
67165 #define MCM_REG_QM_TASK_USE_ST_FLG_6                                                                 0x120055cUL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
67166 #define MCM_REG_QM_TASK_USE_ST_FLG_7                                                                 0x1200560UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM.  Chips: BB_A0 BB_B0 K2
67167 #define MCM_REG_ERR_EVNT_ID                                                                          0x1200564UL //Access:RW   DataWidth:0x8   The Event ID in case one of errors is set in QM input message.  Chips: BB_A0 BB_B0 K2
67168 #define MCM_REG_STORM_WEIGHT                                                                         0x1200604UL //Access:RW   DataWidth:0x3   The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67169 #define MCM_REG_USEM_WEIGHT                                                                          0x1200608UL //Access:RW   DataWidth:0x3   The weight of the input Usem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67170 #define MCM_REG_YSEM_WEIGHT                                                                          0x120060cUL //Access:RW   DataWidth:0x3   The weight of the input Ysem in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67171 #define MCM_REG_PBF_WEIGHT                                                                           0x1200610UL //Access:RW   DataWidth:0x3   The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67172 #define MCM_REG_GRC_WEIGHT                                                                           0x1200614UL //Access:RW   DataWidth:0x3   The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67173 #define MCM_REG_MSDM_WEIGHT                                                                          0x1200618UL //Access:RW   DataWidth:0x3   The weight of the MSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67174 #define MCM_REG_YSDM_WEIGHT                                                                          0x120061cUL //Access:RW   DataWidth:0x3   The weight of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67175 #define MCM_REG_USDM_WEIGHT                                                                          0x1200620UL //Access:RW   DataWidth:0x3   The weight of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67176 #define MCM_REG_TMLD_WEIGHT                                                                          0x1200624UL //Access:RW   DataWidth:0x3   The weight of the input TMLD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67177 #define MCM_REG_QM_P_WEIGHT                                                                          0x1200628UL //Access:RW   DataWidth:0x3   The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67178 #define MCM_REG_QM_S_WEIGHT                                                                          0x120062cUL //Access:RW   DataWidth:0x3   The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
67179 #define MCM_REG_IA_GROUP_PR0                                                                         0x1200630UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
67180 #define MCM_REG_IA_GROUP_PR1                                                                         0x1200634UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
67181 #define MCM_REG_IA_GROUP_PR2                                                                         0x1200638UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
67182 #define MCM_REG_IA_GROUP_PR3                                                                         0x120063cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
67183 #define MCM_REG_IA_GROUP_PR4                                                                         0x1200640UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
67184 #define MCM_REG_IA_GROUP_PR5                                                                         0x1200644UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
67185 #define MCM_REG_IA_ARB_SP_TIMEOUT                                                                    0x1200648UL //Access:RW   DataWidth:0x8   Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority.  Chips: BB_A0 BB_B0 K2
67186 #define MCM_REG_STORM_FRWRD_MODE                                                                     0x120064cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
67187 #define MCM_REG_MSDM_FRWRD_MODE                                                                      0x1200650UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
67188 #define MCM_REG_YSDM_FRWRD_MODE                                                                      0x1200654UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
67189 #define MCM_REG_USDM_FRWRD_MODE                                                                      0x1200658UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
67190 #define MCM_REG_TMLD_FRWRD_MODE                                                                      0x120065cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
67191 #define MCM_REG_USEM_FRWRD_MODE                                                                      0x1200660UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
67192 #define MCM_REG_YSEM_FRWRD_MODE                                                                      0x1200664UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
67193 #define MCM_REG_PBF_FRWRD_MODE                                                                       0x1200668UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
67194 #define MCM_REG_SDM_ERR_HANDLE_EN                                                                    0x120066cUL //Access:RW   DataWidth:0x1   0 - disable error handling in SDM message; 1 - enable error handling in SDM message.  Chips: BB_A0 BB_B0 K2
67195 #define MCM_REG_DIR_BYP_EN                                                                           0x1200670UL //Access:RW   DataWidth:0x1   Direct bypass enable.  Chips: BB_A0 BB_B0 K2
67196 #define MCM_REG_FI_DESC_INPUT_VIOLATE                                                                0x1200674UL //Access:R    DataWidth:0x10  Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: XxBypass message in PCM block;  Chips: BB_A0 BB_B0 K2
67197 #define MCM_REG_SE_DESC_INPUT_VIOLATE                                                                0x1200678UL //Access:R    DataWidth:0xc   Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; Read only register.  Chips: BB_A0 BB_B0 K2
67198 #define MCM_REG_IA_AGG_CON_PART_FILL_LVL                                                             0x120067cUL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
67199 #define MCM_REG_IA_SM_CON_PART_FILL_LVL                                                              0x1200680UL //Access:R    DataWidth:0x3   Input Arbiter Storm Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
67200 #define MCM_REG_IA_AGG_TASK_PART_FILL_LVL                                                            0x1200684UL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Task part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
67201 #define MCM_REG_IA_SM_TASK_PART_FILL_LVL                                                             0x1200688UL //Access:R    DataWidth:0x3   Input Arbiter Storm Task part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
67202 #define MCM_REG_IA_TRANS_PART_FILL_LVL                                                               0x120068cUL //Access:R    DataWidth:0x3   Input Arbiter Transparent part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
67203 #define MCM_REG_XX_MSG_UP_BND                                                                        0x1200704UL //Access:RW   DataWidth:0x7   The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the siz of Xx protected message CM_REGISTERS_XX_MSG_SIZE_BND.XX_MSG_SIZE_BND  Chips: BB_A0 BB_B0 K2
67204 #define MCM_REG_XX_MSG_SIZE                                                                          0x1200708UL //Access:RW   DataWidth:0xb   The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to even number and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1664 PCM: 0d176 TCM: 0d1408 UCM: 0d1664 XCM: 0d256 YCM: 0d1536  Chips: BB_A0 BB_B0 K2
67205 #define MCM_REG_XX_LCID_CAM_UP_BND                                                                   0x120070cUL //Access:RW   DataWidth:0x5   The maximum number of connections in the XX protection LCID CAM.  Chips: BB_A0 BB_B0 K2
67206 #define MCM_REG_XX_FREE_CNT                                                                          0x1200710UL //Access:R    DataWidth:0x7   Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
67207 #define MCM_REG_XX_LCID_CAM_FILL_LVL                                                                 0x1200714UL //Access:R    DataWidth:0x5   Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.  Chips: BB_A0 BB_B0 K2
67208 #define MCM_REG_XX_LCID_CAM_ST_STAT                                                                  0x1200718UL //Access:RC   DataWidth:0x5   CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.  Chips: BB_A0 BB_B0 K2
67209 #define MCM_REG_XX_IA_GROUP_PR0                                                                      0x120071cUL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
67210 #define MCM_REG_XX_IA_GROUP_PR1                                                                      0x1200720UL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
67211 #define MCM_REG_XX_NON_LOCK_LCID_THR                                                                 0x1200724UL //Access:RW   DataWidth:0x5   Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.  Chips: BB_A0 BB_B0 K2
67212 #define MCM_REG_XX_LOCK_LCID_THR                                                                     0x1200728UL //Access:RW   DataWidth:0x5   Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.  Chips: BB_A0 BB_B0 K2
67213 #define MCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                 0x120072cUL //Access:RW   DataWidth:0x8   Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
67214 #define MCM_REG_XX_FREE_HEAD_PTR                                                                     0x1200730UL //Access:R    DataWidth:0x6   Xx Free Head Pointer.  Chips: BB_A0 BB_B0 K2
67215 #define MCM_REG_XX_FREE_TAIL_PTR                                                                     0x1200734UL //Access:R    DataWidth:0x6   Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
67216 #define MCM_REG_XX_NON_LOCK_CNT                                                                      0x1200738UL //Access:R    DataWidth:0x5   Xx NonLock Counter.  Chips: BB_A0 BB_B0 K2
67217 #define MCM_REG_XX_LOCK_CNT                                                                          0x120073cUL //Access:R    DataWidth:0x5   Xx Lock Counter.  Chips: BB_A0 BB_B0 K2
67218 #define MCM_REG_XX_LCID_ARB_GROUP_PR0                                                                0x1200740UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
67219 #define MCM_REG_XX_LCID_ARB_GROUP_PR1                                                                0x1200744UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
67220 #define MCM_REG_XX_LCID_ARB_GROUP_PR2                                                                0x1200748UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
67221 #define MCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                               0x120074cUL //Access:RW   DataWidth:0x8   Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
67222 #define MCM_REG_XX_FREE_THR_HIGH                                                                     0x1200750UL //Access:RW   DataWidth:0x7   Xx free messages threshold high. Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
67223 #define MCM_REG_XX_FREE_THR_LOW                                                                      0x1200754UL //Access:RW   DataWidth:0x7   Xx free messages threshold low Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
67224 #define MCM_REG_XX_CBYP_TBL_FILL_LVL                                                                 0x1200758UL //Access:R    DataWidth:0x4   Xx Connection Bypass Table fill level (in connections).  Chips: BB_A0 BB_B0 K2
67225 #define MCM_REG_XX_CBYP_TBL_ST_STAT                                                                  0x120075cUL //Access:RC   DataWidth:0x4   Xx Connection Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
67226 #define MCM_REG_XX_CBYP_TBL_UP_BND                                                                   0x1200760UL //Access:RW   DataWidth:0x4   Xx Bypass Table (Connection) maximum fill level.  Chips: BB_A0 BB_B0 K2
67227 #define MCM_REG_XX_TBYP_TBL_FILL_LVL                                                                 0x1200764UL //Access:R    DataWidth:0x5   Xx Task Bypass Table fill level (in tasks).  Chips: BB_A0 BB_B0 K2
67228 #define MCM_REG_XX_TBYP_TBL_ST_STAT                                                                  0x1200768UL //Access:RC   DataWidth:0x5   Xx Task Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
67229 #define MCM_REG_XX_TBYP_TBL_UP_BND                                                                   0x120076cUL //Access:RW   DataWidth:0x5   Xx Bypass Table (Task) maximum fill level.  Chips: BB_A0 BB_B0 K2
67230 #define MCM_REG_XX_BYP_MSG_UP_BND_0                                                                  0x1200770UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
67231 #define MCM_REG_XX_BYP_MSG_UP_BND_1                                                                  0x1200774UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
67232 #define MCM_REG_XX_BYP_MSG_UP_BND_2                                                                  0x1200778UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
67233 #define MCM_REG_XX_BYP_MSG_UP_BND_3                                                                  0x120077cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
67234 #define MCM_REG_XX_BYP_MSG_UP_BND_4                                                                  0x1200780UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
67235 #define MCM_REG_XX_BYP_MSG_UP_BND_5                                                                  0x1200784UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
67236 #define MCM_REG_XX_BYP_MSG_UP_BND_6                                                                  0x1200788UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
67237 #define MCM_REG_XX_BYP_MSG_UP_BND_7                                                                  0x120078cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
67238 #define MCM_REG_XX_BYP_LOCK_MSG_THR                                                                  0x1200790UL //Access:RW   DataWidth:0x6   Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.  Chips: BB_A0 BB_B0 K2
67239 #define MCM_REG_XX_PREF_DIR_FILL_LVL                                                                 0x1200794UL //Access:R    DataWidth:0x6   Xx LCID Arbiter direct prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
67240 #define MCM_REG_XX_PREF_AGGST_FILL_LVL                                                               0x1200798UL //Access:R    DataWidth:0x6   Xx LCID Arbiter aggregation store prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
67241 #define MCM_REG_XX_PREF_BYP_FILL_LVL                                                                 0x120079cUL //Access:R    DataWidth:0x6   Xx LCID Arbiter bypass prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
67242 #define MCM_REG_UNLOCK_MISS                                                                          0x12007a0UL //Access:RC   DataWidth:0x1   Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.  Chips: BB_A0 BB_B0 K2
67243 #define MCM_REG_PRCS_AGG_CON_CURR_ST                                                                 0x1200804UL //Access:R    DataWidth:0x4   Aggregation Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
67244 #define MCM_REG_PRCS_SM_CON_CURR_ST                                                                  0x1200808UL //Access:R    DataWidth:0x2   STORM Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
67245 #define MCM_REG_PRCS_AGG_TASK_CURR_ST                                                                0x120080cUL //Access:R    DataWidth:0x4   Aggregation Task Processor FSM.  Chips: BB_A0 BB_B0 K2
67246 #define MCM_REG_PRCS_SM_TASK_CURR_ST                                                                 0x1200810UL //Access:R    DataWidth:0x2   STORM Task Processor FSM.  Chips: BB_A0 BB_B0 K2
67247 #define MCM_REG_N_SM_CON_CTX_LD_0                                                                    0x1200814UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67248 #define MCM_REG_N_SM_CON_CTX_LD_1                                                                    0x1200818UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67249 #define MCM_REG_N_SM_CON_CTX_LD_2                                                                    0x120081cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67250 #define MCM_REG_N_SM_CON_CTX_LD_3                                                                    0x1200820UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67251 #define MCM_REG_N_SM_CON_CTX_LD_4                                                                    0x1200824UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67252 #define MCM_REG_N_SM_CON_CTX_LD_5                                                                    0x1200828UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67253 #define MCM_REG_N_SM_CON_CTX_LD_6                                                                    0x120082cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67254 #define MCM_REG_N_SM_CON_CTX_LD_7                                                                    0x1200830UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67255 #define MCM_REG_N_SM_TASK_CTX_LD_0                                                                   0x1200834UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67256 #define MCM_REG_N_SM_TASK_CTX_LD_1                                                                   0x1200838UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67257 #define MCM_REG_N_SM_TASK_CTX_LD_2                                                                   0x120083cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67258 #define MCM_REG_N_SM_TASK_CTX_LD_3                                                                   0x1200840UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67259 #define MCM_REG_N_SM_TASK_CTX_LD_4                                                                   0x1200844UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67260 #define MCM_REG_N_SM_TASK_CTX_LD_5                                                                   0x1200848UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67261 #define MCM_REG_N_SM_TASK_CTX_LD_6                                                                   0x120084cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67262 #define MCM_REG_N_SM_TASK_CTX_LD_7                                                                   0x1200850UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
67263 #define MCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                             0x1200854UL //Access:R    DataWidth:0x1   Aggregation Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
67264 #define MCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                              0x1200858UL //Access:R    DataWidth:0x5   Storm Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
67265 #define MCM_REG_AGG_CON_FIC_BUF_CRD                                                                  0x120085cUL //Access:RW   DataWidth:0x2   Aggregation Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
67266 #define MCM_REG_SM_CON_FIC_BUF_CRD                                                                   0x1200860UL //Access:RW   DataWidth:0x2   Storm Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
67267 #define MCM_REG_AGG_CON_BUF_CRD_AGG                                                                  0x1200864UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
67268 #define MCM_REG_AGG_CON_BUF_CRD_AGGST                                                                0x1200868UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
67269 #define MCM_REG_SM_CON_BUF_CRD_AGGST                                                                 0x120086cUL //Access:RW   DataWidth:0x1   Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
67270 #define MCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                              0x1200870UL //Access:RW   DataWidth:0x2   Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
67271 #define MCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                               0x1200874UL //Access:RW   DataWidth:0x2   Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
67272 #define MCM_REG_AGG_TASK_FIC_BUF_FILL_LVL                                                            0x1200878UL //Access:R    DataWidth:0x2   Aggregation Task FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
67273 #define MCM_REG_SM_TASK_FIC_BUF_FILL_LVL                                                             0x120087cUL //Access:R    DataWidth:0x5   Storm Task FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
67274 #define MCM_REG_AGG_TASK_FIC_BUF_CRD                                                                 0x1200880UL //Access:RW   DataWidth:0x2   Aggregation Task FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
67275 #define MCM_REG_SM_TASK_FIC_BUF_CRD                                                                  0x1200884UL //Access:RW   DataWidth:0x2   Storm Task FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
67276 #define MCM_REG_AGG_TASK_BUF_CRD_AGG                                                                 0x1200888UL //Access:RW   DataWidth:0x3   Aggregation Task buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
67277 #define MCM_REG_AGG_TASK_BUF_CRD_AGGST                                                               0x120088cUL //Access:RW   DataWidth:0x3   Aggregation Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
67278 #define MCM_REG_SM_TASK_BUF_CRD_AGGST                                                                0x1200890UL //Access:RW   DataWidth:0x1   Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.  Chips: BB_A0 BB_B0 K2
67279 #define MCM_REG_AGG_TASK_CMD_BUF_CRD_DIR                                                             0x1200894UL //Access:RW   DataWidth:0x2   Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
67280 #define MCM_REG_SM_TASK_CMD_BUF_CRD_DIR                                                              0x1200898UL //Access:RW   DataWidth:0x2   Storm Task command buffer credit (Direct group). In sum with CM_REGISTERS_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.  Chips: BB_A0 BB_B0 K2
67281 #define MCM_REG_TRANS_DATA_BUF_CRD_DIR                                                               0x120089cUL //Access:RW   DataWidth:0x2   Transparent data buffer credit (Direct group).  Chips: BB_A0 BB_B0 K2
67282 #define MCM_REG_AGG_CON_CTX_SIZE_0                                                                   0x12008a0UL //Access:RW   DataWidth:0x1   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less or 1.  Chips: BB_A0 BB_B0 K2
67283 #define MCM_REG_AGG_CON_CTX_SIZE_1                                                                   0x12008a4UL //Access:RW   DataWidth:0x1   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.  Chips: BB_A0 BB_B0 K2
67284 #define MCM_REG_AGG_CON_CTX_SIZE_2                                                                   0x12008a8UL //Access:RW   DataWidth:0x1   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.  Chips: BB_A0 BB_B0 K2
67285 #define MCM_REG_AGG_CON_CTX_SIZE_3                                                                   0x12008acUL //Access:RW   DataWidth:0x1   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.  Chips: BB_A0 BB_B0 K2
67286 #define MCM_REG_AGG_CON_CTX_SIZE_4                                                                   0x12008b0UL //Access:RW   DataWidth:0x1   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.  Chips: BB_A0 BB_B0 K2
67287 #define MCM_REG_AGG_CON_CTX_SIZE_5                                                                   0x12008b4UL //Access:RW   DataWidth:0x1   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.  Chips: BB_A0 BB_B0 K2
67288 #define MCM_REG_AGG_CON_CTX_SIZE_6                                                                   0x12008b8UL //Access:RW   DataWidth:0x1   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.  Chips: BB_A0 BB_B0 K2
67289 #define MCM_REG_AGG_CON_CTX_SIZE_7                                                                   0x12008bcUL //Access:RW   DataWidth:0x1   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 1. The register values allowed: XCM: 4 REGQ aligned or 1. Other CM: 2 REGQ aligned or 1 aligned whichever is less, or 1.  Chips: BB_A0 BB_B0 K2
67290 #define MCM_REG_AGG_TASK_CTX_SIZE_0                                                                  0x12008c0UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
67291 #define MCM_REG_AGG_TASK_CTX_SIZE_1                                                                  0x12008c4UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
67292 #define MCM_REG_AGG_TASK_CTX_SIZE_2                                                                  0x12008c8UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
67293 #define MCM_REG_AGG_TASK_CTX_SIZE_3                                                                  0x12008ccUL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
67294 #define MCM_REG_AGG_TASK_CTX_SIZE_4                                                                  0x12008d0UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
67295 #define MCM_REG_AGG_TASK_CTX_SIZE_5                                                                  0x12008d4UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
67296 #define MCM_REG_AGG_TASK_CTX_SIZE_6                                                                  0x12008d8UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
67297 #define MCM_REG_AGG_TASK_CTX_SIZE_7                                                                  0x12008dcUL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
67298 #define MCM_REG_SM_CON_CTX_SIZE                                                                      0x12008e0UL //Access:RW   DataWidth:0x5   STORM Connnection context per LCID size (REGQ). Default context size of 10 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 20. Maximum number of LCIDs allowed at maximum context size per LCID is 160. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(10/2))/(20/2)).  Chips: BB_A0 BB_B0 K2
67299 #define MCM_REG_SM_TASK_CTX_SIZE                                                                     0x12008e4UL //Access:RW   DataWidth:0x5   STORM Task context per LTID size (REGQ). Default context size of 7 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 20. Maximum number of LTIDs allowed at maximum context size per LTID is 64. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER((320*INTEGER(7/2))/(20/2)).  Chips: BB_A0 BB_B0 K2
67300 #define MCM_REG_CON_PHY_Q0                                                                           0x1200904UL //Access:RW   DataWidth:0x9   Physical queue connection number (queue number 0).  Chips: BB_A0 BB_B0 K2
67301 #define MCM_REG_CON_PHY_Q1                                                                           0x1200908UL //Access:RW   DataWidth:0x9   Physical queue connection number (queue number 1).  Chips: BB_A0 BB_B0 K2
67302 #define MCM_REG_TASK_PHY_Q0                                                                          0x120090cUL //Access:RW   DataWidth:0x7   Physical queue task number (queue number 0).  Chips: BB_A0 BB_B0 K2
67303 #define MCM_REG_TASK_PHY_Q1                                                                          0x1200910UL //Access:RW   DataWidth:0x7   Physical queue task number (queue number 1).  Chips: BB_A0 BB_B0 K2
67304 #define MCM_REG_AGG_CON_CF0_Q                                                                        0x1200914UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67305 #define MCM_REG_AGG_CON_CF1_Q                                                                        0x1200918UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67306 #define MCM_REG_AGG_CON_CF2_Q                                                                        0x120091cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67307 #define MCM_REG_AGG_CON_RULE0_Q                                                                      0x1200920UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67308 #define MCM_REG_AGG_CON_RULE1_Q                                                                      0x1200924UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67309 #define MCM_REG_AGG_CON_RULE2_Q                                                                      0x1200928UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67310 #define MCM_REG_AGG_CON_RULE3_Q                                                                      0x120092cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67311 #define MCM_REG_AGG_CON_RULE4_Q                                                                      0x1200930UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67312 #define MCM_REG_AGG_TASK_CF0_Q                                                                       0x1200934UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67313 #define MCM_REG_AGG_TASK_CF1_Q                                                                       0x1200938UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67314 #define MCM_REG_AGG_TASK_CF2_Q                                                                       0x120093cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67315 #define MCM_REG_AGG_TASK_RULE0_Q                                                                     0x1200940UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67316 #define MCM_REG_AGG_TASK_RULE1_Q                                                                     0x1200944UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67317 #define MCM_REG_AGG_TASK_RULE2_Q                                                                     0x1200948UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67318 #define MCM_REG_AGG_TASK_RULE3_Q                                                                     0x120094cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67319 #define MCM_REG_AGG_TASK_RULE4_Q                                                                     0x1200950UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67320 #define MCM_REG_AGG_TASK_RULE5_Q                                                                     0x1200954UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67321 #define MCM_REG_AGG_TASK_RULE6_Q                                                                     0x1200958UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
67322 #define MCM_REG_IN_PRCS_TBL_CRD_AGG                                                                  0x1200a04UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
67323 #define MCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                0x1200a08UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
67324 #define MCM_REG_IN_PRCS_TBL_FILL_LVL                                                                 0x1200a0cUL //Access:R    DataWidth:0x4   In-process Table fill level  (in messages).  Chips: BB_A0 BB_B0 K2
67325 #define MCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                              0x1200a10UL //Access:R    DataWidth:0x1   In-process Table almost full.  Chips: BB_A0 BB_B0 K2
67326 #define MCM_REG_QMCON_CURR_ST                                                                        0x1200a14UL //Access:R    DataWidth:0x3   QM connection registration FSM current state.  Chips: BB_A0 BB_B0 K2
67327 #define MCM_REG_QMTASK_CURR_ST                                                                       0x1200a18UL //Access:R    DataWidth:0x3   QM task registration FSM current state.  Chips: BB_A0 BB_B0 K2
67328 #define MCM_REG_CCFC_CURR_ST                                                                         0x1200a1cUL //Access:R    DataWidth:0x1   CFC connection output FSM current state.  Chips: BB_A0 BB_B0 K2
67329 #define MCM_REG_TCFC_CURR_ST                                                                         0x1200a20UL //Access:R    DataWidth:0x1   CFC task output FSM current state.  Chips: BB_A0 BB_B0 K2
67330 #define MCM_REG_CMPL_DIR_CURR_ST                                                                     0x1200a24UL //Access:R    DataWidth:0x4   Direct Completer FSM current state.  Chips: BB_A0 BB_B0 K2
67331 #define MCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                         0x1200a28UL //Access:RW   DataWidth:0x1   If set, Xx connection bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
67332 #define MCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG                                                        0x1200a2cUL //Access:RW   DataWidth:0x1   If set, Xx task bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
67333 #define MCM_REG_CCFC_INIT_CRD                                                                        0x1200a84UL //Access:RW   DataWidth:0x4   CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
67334 #define MCM_REG_TCFC_INIT_CRD                                                                        0x1200a88UL //Access:RW   DataWidth:0x4   TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
67335 #define MCM_REG_QM_INIT_CRD0                                                                         0x1200a8cUL //Access:RW   DataWidth:0x5   QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
67336 #define MCM_REG_TCFC_INCLOCK_INIT_CRD                                                                0x1200a90UL //Access:RW   DataWidth:0x1   TCFC UC Inc/Lock Update output initial credit. Max credit available - 1.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
67337 #define MCM_REG_TCFC_DEC_INIT_CRD                                                                    0x1200a94UL //Access:RW   DataWidth:0x3   TCFC UC Dec Update output initial credit. Max credit available - 7.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
67338 #define MCM_REG_FIC_INIT_CRD                                                                         0x1200a98UL //Access:RW   DataWidth:0x6   FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.  Chips: BB_A0 BB_B0 K2
67339 #define MCM_REG_DIR_BYP_MSG_CNT                                                                      0x1200aa4UL //Access:RC   DataWidth:0x20  Counter of direct bypassed messages.  Chips: BB_A0 BB_B0 K2
67340 #define MCM_REG_MSDM_LENGTH_MIS                                                                      0x1200aa8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at MSDM interface.  Chips: BB_A0 BB_B0 K2
67341 #define MCM_REG_YSDM_LENGTH_MIS                                                                      0x1200aacUL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at YSDM interface.  Chips: BB_A0 BB_B0 K2
67342 #define MCM_REG_USDM_LENGTH_MIS                                                                      0x1200ab0UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at USDM interface.  Chips: BB_A0 BB_B0 K2
67343 #define MCM_REG_PBF_LENGTH_MIS                                                                       0x1200ab4UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at PBF interface.  Chips: BB_A0 BB_B0 K2
67344 #define MCM_REG_TMLD_LENGTH_MIS                                                                      0x1200ab8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at TMLD interface.  Chips: BB_A0 BB_B0 K2
67345 #define MCM_REG_GRC_BUF_EMPTY                                                                        0x1200abcUL //Access:R    DataWidth:0x1   Input Stage GRC buffer is empty.  Chips: BB_A0 BB_B0 K2
67346 #define MCM_REG_GRC_BUF_STATUS                                                                       0x1200ac0UL //Access:R    DataWidth:0x6   Input Stage GRC buffer status.  Chips: BB_A0 BB_B0 K2
67347 #define MCM_REG_STORM_MSG_CNTR                                                                       0x1200ac4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the STORM input.  Chips: BB_A0 BB_B0 K2
67348 #define MCM_REG_MSDM_MSG_CNTR                                                                        0x1200ac8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input MSDM.  Chips: BB_A0 BB_B0 K2
67349 #define MCM_REG_YSDM_MSG_CNTR                                                                        0x1200accUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input YSDM.  Chips: BB_A0 BB_B0 K2
67350 #define MCM_REG_USDM_MSG_CNTR                                                                        0x1200ad0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input USDM.  Chips: BB_A0 BB_B0 K2
67351 #define MCM_REG_TMLD_MSG_CNTR                                                                        0x1200ad4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input TMLD.  Chips: BB_A0 BB_B0 K2
67352 #define MCM_REG_USEM_MSG_CNTR                                                                        0x1200ad8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input USEM.  Chips: BB_A0 BB_B0 K2
67353 #define MCM_REG_YSEM_MSG_CNTR                                                                        0x1200adcUL //Access:RC   DataWidth:0x1c  Counter of the input messages at input Ysem.  Chips: BB_A0 BB_B0 K2
67354 #define MCM_REG_PBF_MSG_CNTR                                                                         0x1200ae0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input PBF.  Chips: BB_A0 BB_B0 K2
67355 #define MCM_REG_QM_P_MSG_CNTR                                                                        0x1200ae4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (primary).  Chips: BB_A0 BB_B0 K2
67356 #define MCM_REG_QM_S_MSG_CNTR                                                                        0x1200ae8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (secondary).  Chips: BB_A0 BB_B0 K2
67357 #define MCM_REG_IS_GRC                                                                               0x1200aecUL //Access:W    DataWidth:0x20  Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done  Chips: BB_A0 BB_B0 K2
67358 #define MCM_REG_IS_QM_P_FILL_LVL                                                                     0x1200af0UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
67359 #define MCM_REG_IS_QM_S_FILL_LVL                                                                     0x1200af4UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
67360 #define MCM_REG_IS_STORM_FILL_LVL                                                                    0x1200af8UL //Access:R    DataWidth:0x6   Number of QREGs (128b) of data in STORM Input Stage.  Chips: BB_A0 BB_B0 K2
67361 #define MCM_REG_IS_MSDM_FILL_LVL                                                                     0x1200afcUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in MSDM Input Stage.  Chips: BB_A0 BB_B0 K2
67362 #define MCM_REG_IS_YSDM_FILL_LVL                                                                     0x1200b00UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in YSDM Input Stage.  Chips: BB_A0 BB_B0 K2
67363 #define MCM_REG_IS_USDM_FILL_LVL                                                                     0x1200b04UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in USDM Input Stage.  Chips: BB_A0 BB_B0 K2
67364 #define MCM_REG_IS_TMLD_FILL_LVL                                                                     0x1200b08UL //Access:R    DataWidth:0x5   Number of QREGs (128b) of data in TMLD Input Stage.  Chips: BB_A0 BB_B0 K2
67365 #define MCM_REG_IS_USEM_FILL_LVL                                                                     0x1200b0cUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in USEM Input Stage.  Chips: BB_A0 BB_B0 K2
67366 #define MCM_REG_IS_YSEM_FILL_LVL                                                                     0x1200b10UL //Access:R    DataWidth:0x5   Number of QREGs (128b) of data in YSEM Input Stage.  Chips: BB_A0 BB_B0 K2
67367 #define MCM_REG_IS_PBF_FILL_LVL                                                                      0x1200b14UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in PBF Input Stage.  Chips: BB_A0 BB_B0 K2
67368 #define MCM_REG_FIC_MSG_CNTR                                                                         0x1200b44UL //Access:RC   DataWidth:0x1c  Counter of the output messages at FIC interfaces.  Chips: BB_A0 BB_B0 K2
67369 #define MCM_REG_QM_OUT_CNTR                                                                          0x1200b48UL //Access:RC   DataWidth:0x1c  Counter of the output QM commands.  Chips: BB_A0 BB_B0 K2
67370 #define MCM_REG_DONE0_CNTR                                                                           0x1200b4cUL //Access:RC   DataWidth:0x1c  Counter of the output Done0.  Chips: BB_A0 BB_B0 K2
67371 #define MCM_REG_DONE1_CNTR                                                                           0x1200b50UL //Access:RC   DataWidth:0x1c  Counter of the output Done1.  Chips: BB_A0 BB_B0 K2
67372 #define MCM_REG_DONE2_CNTR                                                                           0x1200b54UL //Access:RC   DataWidth:0x1c  Counter of the output Done2.  Chips: BB_A0 BB_B0 K2
67373 #define MCM_REG_CCFC_CNTR                                                                            0x1200b58UL //Access:RC   DataWidth:0x1c  Counter of the output CCFC.  Chips: BB_A0 BB_B0 K2
67374 #define MCM_REG_TCFC_CNTR                                                                            0x1200b5cUL //Access:RC   DataWidth:0x1c  Counter of the output TCFC.  Chips: BB_A0 BB_B0 K2
67375 #define MCM_REG_ECO_RESERVED                                                                         0x1200b84UL //Access:RW   DataWidth:0x8   Chicken bits.  Chips: BB_A0 BB_B0 K2
67376 #define MCM_REG_IS_FOC_MSEM_NXT_INF_UNIT                                                             0x1200b88UL //Access:R    DataWidth:0x6   Debug read from MSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
67377 #define MCM_REG_IS_FOC_USEM_NXT_INF_UNIT                                                             0x1200b8cUL //Access:R    DataWidth:0x6   Debug read from USEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
67378 #define MCM_REG_IS_FOC_YSEM_NXT_INF_UNIT                                                             0x1200b90UL //Access:R    DataWidth:0x6   Debug read from YSEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
67379 #define MCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                              0x1200b94UL //Access:R    DataWidth:0x6   Debug read from PBF Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
67380 #define MCM_REG_IS_FOC_MSDM_NXT_INF_UNIT                                                             0x1200b98UL //Access:R    DataWidth:0x6   Debug read from MSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
67381 #define MCM_REG_IS_FOC_USDM_NXT_INF_UNIT                                                             0x1200b9cUL //Access:R    DataWidth:0x6   Debug read from USDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
67382 #define MCM_REG_IS_FOC_YSDM_NXT_INF_UNIT                                                             0x1200ba0UL //Access:R    DataWidth:0x6   Debug read from YSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
67383 #define MCM_REG_IS_FOC_TMLD_NXT_INF_UNIT                                                             0x1200ba4UL //Access:R    DataWidth:0x6   Debug read from TMLD Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
67384 #define MCM_REG_IS_FOC_MSEM                                                                          0x1200c00UL //Access:R    DataWidth:0x20  Debug read from MSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
67385 #define MCM_REG_IS_FOC_MSEM_SIZE                                                                     180
67386 #define MCM_REG_IS_FOC_USEM                                                                          0x1201000UL //Access:R    DataWidth:0x20  Debug read from USEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
67387 #define MCM_REG_IS_FOC_USEM_SIZE                                                                     24
67388 #define MCM_REG_IS_FOC_YSEM                                                                          0x1201200UL //Access:R    DataWidth:0x20  Debug read from YSEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
67389 #define MCM_REG_IS_FOC_YSEM_SIZE                                                                     108
67390 #define MCM_REG_IS_FOC_PBF                                                                           0x1201400UL //Access:R    DataWidth:0x20  Debug read from PBF Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
67391 #define MCM_REG_IS_FOC_PBF_SIZE                                                                      24
67392 #define MCM_REG_IS_FOC_MSDM                                                                          0x1201480UL //Access:R    DataWidth:0x20  Debug read from MSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
67393 #define MCM_REG_IS_FOC_MSDM_SIZE                                                                     20
67394 #define MCM_REG_IS_FOC_USDM                                                                          0x1201500UL //Access:R    DataWidth:0x20  Debug read from USDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
67395 #define MCM_REG_IS_FOC_USDM_SIZE                                                                     28
67396 #define MCM_REG_IS_FOC_YSDM                                                                          0x1201580UL //Access:R    DataWidth:0x20  Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
67397 #define MCM_REG_IS_FOC_YSDM_SIZE                                                                     12
67398 #define MCM_REG_IS_FOC_TMLD                                                                          0x1201600UL //Access:R    DataWidth:0x20  Debug read from TMLD Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
67399 #define MCM_REG_IS_FOC_TMLD_SIZE                                                                     124
67400 #define MCM_REG_CTX_RBC_ACCS                                                                         0x1201800UL //Access:RW   DataWidth:0x10  Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX  Chips: BB_A0 BB_B0 K2
67401 #define MCM_REG_AGG_CON_CTX                                                                          0x1201804UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
67402 #define MCM_REG_AGG_TASK_CTX                                                                         0x1201808UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
67403 #define MCM_REG_SM_CON_CTX                                                                           0x120180cUL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
67404 #define MCM_REG_SM_TASK_CTX                                                                          0x1201810UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
67405 #define MCM_REG_XX_CBYP_TBL                                                                          0x1201820UL //Access:R    DataWidth:0xf   Xx Connection Bypass Table.  Chips: BB_A0 BB_B0 K2
67406 #define MCM_REG_XX_CBYP_TBL_SIZE                                                                     8
67407 #define MCM_REG_XX_TBYP_TBL                                                                          0x1201900UL //Access:R    DataWidth:0xf   Xx Task Bypass Table.  Chips: BB_A0 BB_B0 K2
67408 #define MCM_REG_XX_TBYP_TBL_SIZE                                                                     22
67409 #define MCM_REG_XX_LCID_CAM                                                                          0x1201a00UL //Access:R    DataWidth:0xa   Debug only. Read only access to LCID CAM in XX protection mechanism.  Chips: BB_A0 BB_B0 K2
67410 #define MCM_REG_XX_LCID_CAM_SIZE                                                                     22
67411 #define MCM_REG_XX_TBL                                                                               0x1201b00UL //Access:R    DataWidth:0x17  Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [3:1] - Connection type; LL size: PCM - [6:4]; M/T/U/X/YCM - [10:4]; Tail pointer: PCM - [8:7]; M/T/U/X/YCM - [16:11]; Next pointer: PCM - [10:9]; M/T/U/X/YCM - [22:17];  Chips: BB_A0 BB_B0 K2
67412 #define MCM_REG_XX_TBL_SIZE                                                                          22
67413 #define MCM_REG_XX_DSCR_TBL                                                                          0x1201c00UL //Access:RW   DataWidth:0x1e  Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.  Chips: BB_A0 BB_B0 K2
67414 #define MCM_REG_XX_DSCR_TBL_SIZE                                                                     64
67415 #define MCM_REG_XX_MSG_RAM                                                                           0x1208000UL //Access:R    DataWidth:0x20  Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.  Chips: BB_A0 BB_B0 K2
67416 #define MCM_REG_XX_MSG_RAM_SIZE                                                                      6656
67417 #define UCM_REG_INIT                                                                                 0x1280000UL //Access:RW   DataWidth:0x1   Debug only. Initialises specific states and statuses. To initialise the state - write 1 into register; to enable working after that - write 0.  Chips: BB_A0 BB_B0 K2
67418 #define UCM_REG_MEMCTRL_WR_RD_N                                                                      0x1280040UL //Access:RW   DataWidth:0x1   wr/rd indication to CPU BIST  Chips: BB_A0 BB_B0
67419 #define UCM_REG_MEMCTRL_CMD                                                                          0x1280044UL //Access:RW   DataWidth:0x8   command to CPU BIST  Chips: BB_A0 BB_B0
67420 #define UCM_REG_MEMCTRL_ADDRESS                                                                      0x1280048UL //Access:RW   DataWidth:0x8   address to CPU BIST  Chips: BB_A0 BB_B0
67421 #define UCM_REG_MEMCTRL_STATUS                                                                       0x128004cUL //Access:R    DataWidth:0x20  status from CPU BIST  Chips: BB_A0 BB_B0 K2
67422 #define UCM_REG_DBG_SELECT                                                                           0x1280050UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
67423 #define UCM_REG_DBG_DWORD_ENABLE                                                                     0x1280054UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
67424 #define UCM_REG_DBG_SHIFT                                                                            0x1280058UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
67425 #define UCM_REG_DBG_FORCE_VALID                                                                      0x128005cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
67426 #define UCM_REG_DBG_FORCE_FRAME                                                                      0x1280060UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
67427 #define UCM_REG_DBG_OUT_DATA                                                                         0x1280080UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
67428 #define UCM_REG_DBG_OUT_DATA_SIZE                                                                    8
67429 #define UCM_REG_DBG_OUT_VALID                                                                        0x12800a0UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
67430 #define UCM_REG_DBG_OUT_FRAME                                                                        0x12800a4UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
67431 #define UCM_REG_INT_STS_0                                                                            0x1280180UL //Access:R    DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67432     #define UCM_REG_INT_STS_0_ADDRESS_ERROR                                                          (0x1<<0) // Signals an unknown address to the rf module.
67433     #define UCM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                    0
67434     #define UCM_REG_INT_STS_0_IS_STORM_OVFL_ERR                                                      (0x1<<1) // Write to full STORM input buffer.
67435     #define UCM_REG_INT_STS_0_IS_STORM_OVFL_ERR_SHIFT                                                1
67436     #define UCM_REG_INT_STS_0_IS_STORM_UNDER_ERR                                                     (0x1<<2) // Read from empty  STORM input buffer.
67437     #define UCM_REG_INT_STS_0_IS_STORM_UNDER_ERR_SHIFT                                               2
67438     #define UCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR                                                       (0x1<<3) // Write to full XSDM input buffer.
67439     #define UCM_REG_INT_STS_0_IS_XSDM_OVFL_ERR_SHIFT                                                 3
67440     #define UCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR                                                      (0x1<<4) // Read from empty XSDM input buffer.
67441     #define UCM_REG_INT_STS_0_IS_XSDM_UNDER_ERR_SHIFT                                                4
67442     #define UCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR                                                       (0x1<<5) // Write to full YSDM input buffer.
67443     #define UCM_REG_INT_STS_0_IS_YSDM_OVFL_ERR_SHIFT                                                 5
67444     #define UCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR                                                      (0x1<<6) // Read from empty  YSDM input buffer.
67445     #define UCM_REG_INT_STS_0_IS_YSDM_UNDER_ERR_SHIFT                                                6
67446     #define UCM_REG_INT_STS_0_IS_USDM_OVFL_ERR                                                       (0x1<<7) // Write to full USDM input buffer.
67447     #define UCM_REG_INT_STS_0_IS_USDM_OVFL_ERR_SHIFT                                                 7
67448     #define UCM_REG_INT_STS_0_IS_USDM_UNDER_ERR                                                      (0x1<<8) // Read from empty USDM input buffer.
67449     #define UCM_REG_INT_STS_0_IS_USDM_UNDER_ERR_SHIFT                                                8
67450     #define UCM_REG_INT_STS_0_IS_RDIF_OVFL_ERR                                                       (0x1<<9) // Write to full RDIF input buffer.
67451     #define UCM_REG_INT_STS_0_IS_RDIF_OVFL_ERR_SHIFT                                                 9
67452     #define UCM_REG_INT_STS_0_IS_RDIF_UNDER_ERR                                                      (0x1<<10) // Read from empty RDIF input buffer.
67453     #define UCM_REG_INT_STS_0_IS_RDIF_UNDER_ERR_SHIFT                                                10
67454     #define UCM_REG_INT_STS_0_IS_TDIF_OVFL_ERR                                                       (0x1<<11) // Write to full TDIF input buffer.
67455     #define UCM_REG_INT_STS_0_IS_TDIF_OVFL_ERR_SHIFT                                                 11
67456     #define UCM_REG_INT_STS_0_IS_TDIF_UNDER_ERR                                                      (0x1<<12) // Read from empty TDIF input buffer.
67457     #define UCM_REG_INT_STS_0_IS_TDIF_UNDER_ERR_SHIFT                                                12
67458     #define UCM_REG_INT_STS_0_IS_MULD_OVFL_ERR                                                       (0x1<<13) // Write to full MULD input buffer.
67459     #define UCM_REG_INT_STS_0_IS_MULD_OVFL_ERR_SHIFT                                                 13
67460     #define UCM_REG_INT_STS_0_IS_MULD_UNDER_ERR                                                      (0x1<<14) // Read from empty MULD input buffer.
67461     #define UCM_REG_INT_STS_0_IS_MULD_UNDER_ERR_SHIFT                                                14
67462     #define UCM_REG_INT_STS_0_IS_YULD_OVFL_ERR                                                       (0x1<<15) // Write to full YULD input buffer.
67463     #define UCM_REG_INT_STS_0_IS_YULD_OVFL_ERR_SHIFT                                                 15
67464     #define UCM_REG_INT_STS_0_IS_YULD_UNDER_ERR                                                      (0x1<<16) // Read from empty YULD input buffer.
67465     #define UCM_REG_INT_STS_0_IS_YULD_UNDER_ERR_SHIFT                                                16
67466 #define UCM_REG_INT_MASK_0                                                                           0x1280184UL //Access:RW   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67467     #define UCM_REG_INT_MASK_0_ADDRESS_ERROR                                                         (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.ADDRESS_ERROR .
67468     #define UCM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                   0
67469     #define UCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_STORM_OVFL_ERR .
67470     #define UCM_REG_INT_MASK_0_IS_STORM_OVFL_ERR_SHIFT                                               1
67471     #define UCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR                                                    (0x1<<2) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_STORM_UNDER_ERR .
67472     #define UCM_REG_INT_MASK_0_IS_STORM_UNDER_ERR_SHIFT                                              2
67473     #define UCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_XSDM_OVFL_ERR .
67474     #define UCM_REG_INT_MASK_0_IS_XSDM_OVFL_ERR_SHIFT                                                3
67475     #define UCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR                                                     (0x1<<4) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_XSDM_UNDER_ERR .
67476     #define UCM_REG_INT_MASK_0_IS_XSDM_UNDER_ERR_SHIFT                                               4
67477     #define UCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR                                                      (0x1<<5) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YSDM_OVFL_ERR .
67478     #define UCM_REG_INT_MASK_0_IS_YSDM_OVFL_ERR_SHIFT                                                5
67479     #define UCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR                                                     (0x1<<6) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YSDM_UNDER_ERR .
67480     #define UCM_REG_INT_MASK_0_IS_YSDM_UNDER_ERR_SHIFT                                               6
67481     #define UCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR                                                      (0x1<<7) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_USDM_OVFL_ERR .
67482     #define UCM_REG_INT_MASK_0_IS_USDM_OVFL_ERR_SHIFT                                                7
67483     #define UCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR                                                     (0x1<<8) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_USDM_UNDER_ERR .
67484     #define UCM_REG_INT_MASK_0_IS_USDM_UNDER_ERR_SHIFT                                               8
67485     #define UCM_REG_INT_MASK_0_IS_RDIF_OVFL_ERR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_RDIF_OVFL_ERR .
67486     #define UCM_REG_INT_MASK_0_IS_RDIF_OVFL_ERR_SHIFT                                                9
67487     #define UCM_REG_INT_MASK_0_IS_RDIF_UNDER_ERR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_RDIF_UNDER_ERR .
67488     #define UCM_REG_INT_MASK_0_IS_RDIF_UNDER_ERR_SHIFT                                               10
67489     #define UCM_REG_INT_MASK_0_IS_TDIF_OVFL_ERR                                                      (0x1<<11) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_TDIF_OVFL_ERR .
67490     #define UCM_REG_INT_MASK_0_IS_TDIF_OVFL_ERR_SHIFT                                                11
67491     #define UCM_REG_INT_MASK_0_IS_TDIF_UNDER_ERR                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_TDIF_UNDER_ERR .
67492     #define UCM_REG_INT_MASK_0_IS_TDIF_UNDER_ERR_SHIFT                                               12
67493     #define UCM_REG_INT_MASK_0_IS_MULD_OVFL_ERR                                                      (0x1<<13) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_MULD_OVFL_ERR .
67494     #define UCM_REG_INT_MASK_0_IS_MULD_OVFL_ERR_SHIFT                                                13
67495     #define UCM_REG_INT_MASK_0_IS_MULD_UNDER_ERR                                                     (0x1<<14) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_MULD_UNDER_ERR .
67496     #define UCM_REG_INT_MASK_0_IS_MULD_UNDER_ERR_SHIFT                                               14
67497     #define UCM_REG_INT_MASK_0_IS_YULD_OVFL_ERR                                                      (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YULD_OVFL_ERR .
67498     #define UCM_REG_INT_MASK_0_IS_YULD_OVFL_ERR_SHIFT                                                15
67499     #define UCM_REG_INT_MASK_0_IS_YULD_UNDER_ERR                                                     (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_0.IS_YULD_UNDER_ERR .
67500     #define UCM_REG_INT_MASK_0_IS_YULD_UNDER_ERR_SHIFT                                               16
67501 #define UCM_REG_INT_STS_WR_0                                                                         0x1280188UL //Access:WR   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67502     #define UCM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                       (0x1<<0) // Signals an unknown address to the rf module.
67503     #define UCM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                 0
67504     #define UCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR                                                   (0x1<<1) // Write to full STORM input buffer.
67505     #define UCM_REG_INT_STS_WR_0_IS_STORM_OVFL_ERR_SHIFT                                             1
67506     #define UCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR                                                  (0x1<<2) // Read from empty  STORM input buffer.
67507     #define UCM_REG_INT_STS_WR_0_IS_STORM_UNDER_ERR_SHIFT                                            2
67508     #define UCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR                                                    (0x1<<3) // Write to full XSDM input buffer.
67509     #define UCM_REG_INT_STS_WR_0_IS_XSDM_OVFL_ERR_SHIFT                                              3
67510     #define UCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR                                                   (0x1<<4) // Read from empty XSDM input buffer.
67511     #define UCM_REG_INT_STS_WR_0_IS_XSDM_UNDER_ERR_SHIFT                                             4
67512     #define UCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR                                                    (0x1<<5) // Write to full YSDM input buffer.
67513     #define UCM_REG_INT_STS_WR_0_IS_YSDM_OVFL_ERR_SHIFT                                              5
67514     #define UCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR                                                   (0x1<<6) // Read from empty  YSDM input buffer.
67515     #define UCM_REG_INT_STS_WR_0_IS_YSDM_UNDER_ERR_SHIFT                                             6
67516     #define UCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR                                                    (0x1<<7) // Write to full USDM input buffer.
67517     #define UCM_REG_INT_STS_WR_0_IS_USDM_OVFL_ERR_SHIFT                                              7
67518     #define UCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR                                                   (0x1<<8) // Read from empty USDM input buffer.
67519     #define UCM_REG_INT_STS_WR_0_IS_USDM_UNDER_ERR_SHIFT                                             8
67520     #define UCM_REG_INT_STS_WR_0_IS_RDIF_OVFL_ERR                                                    (0x1<<9) // Write to full RDIF input buffer.
67521     #define UCM_REG_INT_STS_WR_0_IS_RDIF_OVFL_ERR_SHIFT                                              9
67522     #define UCM_REG_INT_STS_WR_0_IS_RDIF_UNDER_ERR                                                   (0x1<<10) // Read from empty RDIF input buffer.
67523     #define UCM_REG_INT_STS_WR_0_IS_RDIF_UNDER_ERR_SHIFT                                             10
67524     #define UCM_REG_INT_STS_WR_0_IS_TDIF_OVFL_ERR                                                    (0x1<<11) // Write to full TDIF input buffer.
67525     #define UCM_REG_INT_STS_WR_0_IS_TDIF_OVFL_ERR_SHIFT                                              11
67526     #define UCM_REG_INT_STS_WR_0_IS_TDIF_UNDER_ERR                                                   (0x1<<12) // Read from empty TDIF input buffer.
67527     #define UCM_REG_INT_STS_WR_0_IS_TDIF_UNDER_ERR_SHIFT                                             12
67528     #define UCM_REG_INT_STS_WR_0_IS_MULD_OVFL_ERR                                                    (0x1<<13) // Write to full MULD input buffer.
67529     #define UCM_REG_INT_STS_WR_0_IS_MULD_OVFL_ERR_SHIFT                                              13
67530     #define UCM_REG_INT_STS_WR_0_IS_MULD_UNDER_ERR                                                   (0x1<<14) // Read from empty MULD input buffer.
67531     #define UCM_REG_INT_STS_WR_0_IS_MULD_UNDER_ERR_SHIFT                                             14
67532     #define UCM_REG_INT_STS_WR_0_IS_YULD_OVFL_ERR                                                    (0x1<<15) // Write to full YULD input buffer.
67533     #define UCM_REG_INT_STS_WR_0_IS_YULD_OVFL_ERR_SHIFT                                              15
67534     #define UCM_REG_INT_STS_WR_0_IS_YULD_UNDER_ERR                                                   (0x1<<16) // Read from empty YULD input buffer.
67535     #define UCM_REG_INT_STS_WR_0_IS_YULD_UNDER_ERR_SHIFT                                             16
67536 #define UCM_REG_INT_STS_CLR_0                                                                        0x128018cUL //Access:RC   DataWidth:0x11  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67537     #define UCM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
67538     #define UCM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                                0
67539     #define UCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR                                                  (0x1<<1) // Write to full STORM input buffer.
67540     #define UCM_REG_INT_STS_CLR_0_IS_STORM_OVFL_ERR_SHIFT                                            1
67541     #define UCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR                                                 (0x1<<2) // Read from empty  STORM input buffer.
67542     #define UCM_REG_INT_STS_CLR_0_IS_STORM_UNDER_ERR_SHIFT                                           2
67543     #define UCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR                                                   (0x1<<3) // Write to full XSDM input buffer.
67544     #define UCM_REG_INT_STS_CLR_0_IS_XSDM_OVFL_ERR_SHIFT                                             3
67545     #define UCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR                                                  (0x1<<4) // Read from empty XSDM input buffer.
67546     #define UCM_REG_INT_STS_CLR_0_IS_XSDM_UNDER_ERR_SHIFT                                            4
67547     #define UCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR                                                   (0x1<<5) // Write to full YSDM input buffer.
67548     #define UCM_REG_INT_STS_CLR_0_IS_YSDM_OVFL_ERR_SHIFT                                             5
67549     #define UCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR                                                  (0x1<<6) // Read from empty  YSDM input buffer.
67550     #define UCM_REG_INT_STS_CLR_0_IS_YSDM_UNDER_ERR_SHIFT                                            6
67551     #define UCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR                                                   (0x1<<7) // Write to full USDM input buffer.
67552     #define UCM_REG_INT_STS_CLR_0_IS_USDM_OVFL_ERR_SHIFT                                             7
67553     #define UCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR                                                  (0x1<<8) // Read from empty USDM input buffer.
67554     #define UCM_REG_INT_STS_CLR_0_IS_USDM_UNDER_ERR_SHIFT                                            8
67555     #define UCM_REG_INT_STS_CLR_0_IS_RDIF_OVFL_ERR                                                   (0x1<<9) // Write to full RDIF input buffer.
67556     #define UCM_REG_INT_STS_CLR_0_IS_RDIF_OVFL_ERR_SHIFT                                             9
67557     #define UCM_REG_INT_STS_CLR_0_IS_RDIF_UNDER_ERR                                                  (0x1<<10) // Read from empty RDIF input buffer.
67558     #define UCM_REG_INT_STS_CLR_0_IS_RDIF_UNDER_ERR_SHIFT                                            10
67559     #define UCM_REG_INT_STS_CLR_0_IS_TDIF_OVFL_ERR                                                   (0x1<<11) // Write to full TDIF input buffer.
67560     #define UCM_REG_INT_STS_CLR_0_IS_TDIF_OVFL_ERR_SHIFT                                             11
67561     #define UCM_REG_INT_STS_CLR_0_IS_TDIF_UNDER_ERR                                                  (0x1<<12) // Read from empty TDIF input buffer.
67562     #define UCM_REG_INT_STS_CLR_0_IS_TDIF_UNDER_ERR_SHIFT                                            12
67563     #define UCM_REG_INT_STS_CLR_0_IS_MULD_OVFL_ERR                                                   (0x1<<13) // Write to full MULD input buffer.
67564     #define UCM_REG_INT_STS_CLR_0_IS_MULD_OVFL_ERR_SHIFT                                             13
67565     #define UCM_REG_INT_STS_CLR_0_IS_MULD_UNDER_ERR                                                  (0x1<<14) // Read from empty MULD input buffer.
67566     #define UCM_REG_INT_STS_CLR_0_IS_MULD_UNDER_ERR_SHIFT                                            14
67567     #define UCM_REG_INT_STS_CLR_0_IS_YULD_OVFL_ERR                                                   (0x1<<15) // Write to full YULD input buffer.
67568     #define UCM_REG_INT_STS_CLR_0_IS_YULD_OVFL_ERR_SHIFT                                             15
67569     #define UCM_REG_INT_STS_CLR_0_IS_YULD_UNDER_ERR                                                  (0x1<<16) // Read from empty YULD input buffer.
67570     #define UCM_REG_INT_STS_CLR_0_IS_YULD_UNDER_ERR_SHIFT                                            16
67571 #define UCM_REG_INT_STS_1                                                                            0x1280190UL //Access:R    DataWidth:0x1d  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67572     #define UCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR                                                       (0x1<<0) // Write to full Dorq input buffer.
67573     #define UCM_REG_INT_STS_1_IS_DORQ_OVFL_ERR_SHIFT                                                 0
67574     #define UCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR                                                      (0x1<<1) // Read from empty  Dorq input buffer.
67575     #define UCM_REG_INT_STS_1_IS_DORQ_UNDER_ERR_SHIFT                                                1
67576     #define UCM_REG_INT_STS_1_IS_PBF_OVFL_ERR                                                        (0x1<<2) // Write to full Pbf input buffer.
67577     #define UCM_REG_INT_STS_1_IS_PBF_OVFL_ERR_SHIFT                                                  2
67578     #define UCM_REG_INT_STS_1_IS_PBF_UNDER_ERR                                                       (0x1<<3) // Read from empty Pbf input buffer.
67579     #define UCM_REG_INT_STS_1_IS_PBF_UNDER_ERR_SHIFT                                                 3
67580     #define UCM_REG_INT_STS_1_IS_TM_OVFL_ERR                                                         (0x1<<4) // Write to full TM input buffer.
67581     #define UCM_REG_INT_STS_1_IS_TM_OVFL_ERR_SHIFT                                                   4
67582     #define UCM_REG_INT_STS_1_IS_TM_UNDER_ERR                                                        (0x1<<5) // Read from empty TM input buffer.
67583     #define UCM_REG_INT_STS_1_IS_TM_UNDER_ERR_SHIFT                                                  5
67584     #define UCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR                                                       (0x1<<6) // Write to full QM input buffer.
67585     #define UCM_REG_INT_STS_1_IS_QM_P_OVFL_ERR_SHIFT                                                 6
67586     #define UCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR                                                      (0x1<<7) // Read from empty QM input buffer.
67587     #define UCM_REG_INT_STS_1_IS_QM_P_UNDER_ERR_SHIFT                                                7
67588     #define UCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR                                                       (0x1<<8) // Write to full QM input buffer.
67589     #define UCM_REG_INT_STS_1_IS_QM_S_OVFL_ERR_SHIFT                                                 8
67590     #define UCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR                                                      (0x1<<9) // Read from empty QM input buffer.
67591     #define UCM_REG_INT_STS_1_IS_QM_S_UNDER_ERR_SHIFT                                                9
67592     #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0                                                       (0x1<<10) // Write to full GRC input buffer bits [31:0].
67593     #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR0_SHIFT                                                 10
67594     #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0                                                      (0x1<<11) // Read from empty  GRC input buffer bits [31:0].
67595     #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR0_SHIFT                                                11
67596     #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1                                                       (0x1<<12) // Write to full GRC input buffer bits [63:32].
67597     #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR1_SHIFT                                                 12
67598     #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1                                                      (0x1<<13) // Read from empty  GRC input buffer bits [63:32].
67599     #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR1_SHIFT                                                13
67600     #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2                                                       (0x1<<14) // Write to full GRC input buffer bits [95:64].
67601     #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR2_SHIFT                                                 14
67602     #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2                                                      (0x1<<15) // Read from empty  GRC input buffer bits [95:64].
67603     #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR2_SHIFT                                                15
67604     #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3                                                       (0x1<<16) // Write to full GRC input buffer bits [127:96].
67605     #define UCM_REG_INT_STS_1_IS_GRC_OVFL_ERR3_SHIFT                                                 16
67606     #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3                                                      (0x1<<17) // Read from empty  GRC input buffer bits [127:96].
67607     #define UCM_REG_INT_STS_1_IS_GRC_UNDER_ERR3_SHIFT                                                17
67608     #define UCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL                                                       (0x1<<18) // In-process Table overflow.
67609     #define UCM_REG_INT_STS_1_IN_PRCS_TBL_OVFL_SHIFT                                                 18
67610     #define UCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL                                                  (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
67611     #define UCM_REG_INT_STS_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                            19
67612     #define UCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL                                                   (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
67613     #define UCM_REG_INT_STS_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                             20
67614     #define UCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL                                                   (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
67615     #define UCM_REG_INT_STS_1_SM_CON_DATA_BUF_OVFL_SHIFT                                             21
67616     #define UCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL                                                    (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
67617     #define UCM_REG_INT_STS_1_SM_CON_CMD_BUF_OVFL_SHIFT                                              22
67618     #define UCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL                                                 (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
67619     #define UCM_REG_INT_STS_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                           23
67620     #define UCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL                                                  (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
67621     #define UCM_REG_INT_STS_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                            24
67622     #define UCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL                                                  (0x1<<25) // Message Processor Storm Task Data buffer overflow.
67623     #define UCM_REG_INT_STS_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                            25
67624     #define UCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL                                                   (0x1<<26) // Message Processor Storm Task Command buffer overflow.
67625     #define UCM_REG_INT_STS_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                             26
67626     #define UCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE                                                  (0x1<<27) // Input message first descriptor fields violation.
67627     #define UCM_REG_INT_STS_1_FI_DESC_INPUT_VIOLATE_SHIFT                                            27
67628     #define UCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE                                                  (0x1<<28) // Input message second descriptor fields violation.
67629     #define UCM_REG_INT_STS_1_SE_DESC_INPUT_VIOLATE_SHIFT                                            28
67630 #define UCM_REG_INT_MASK_1                                                                           0x1280194UL //Access:RW   DataWidth:0x1d  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67631     #define UCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR                                                      (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_DORQ_OVFL_ERR .
67632     #define UCM_REG_INT_MASK_1_IS_DORQ_OVFL_ERR_SHIFT                                                0
67633     #define UCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR                                                     (0x1<<1) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_DORQ_UNDER_ERR .
67634     #define UCM_REG_INT_MASK_1_IS_DORQ_UNDER_ERR_SHIFT                                               1
67635     #define UCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR                                                       (0x1<<2) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_PBF_OVFL_ERR .
67636     #define UCM_REG_INT_MASK_1_IS_PBF_OVFL_ERR_SHIFT                                                 2
67637     #define UCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR                                                      (0x1<<3) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_PBF_UNDER_ERR .
67638     #define UCM_REG_INT_MASK_1_IS_PBF_UNDER_ERR_SHIFT                                                3
67639     #define UCM_REG_INT_MASK_1_IS_TM_OVFL_ERR                                                        (0x1<<4) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_TM_OVFL_ERR .
67640     #define UCM_REG_INT_MASK_1_IS_TM_OVFL_ERR_SHIFT                                                  4
67641     #define UCM_REG_INT_MASK_1_IS_TM_UNDER_ERR                                                       (0x1<<5) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_TM_UNDER_ERR .
67642     #define UCM_REG_INT_MASK_1_IS_TM_UNDER_ERR_SHIFT                                                 5
67643     #define UCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR                                                      (0x1<<6) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_P_OVFL_ERR .
67644     #define UCM_REG_INT_MASK_1_IS_QM_P_OVFL_ERR_SHIFT                                                6
67645     #define UCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR                                                     (0x1<<7) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_P_UNDER_ERR .
67646     #define UCM_REG_INT_MASK_1_IS_QM_P_UNDER_ERR_SHIFT                                               7
67647     #define UCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR                                                      (0x1<<8) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_S_OVFL_ERR .
67648     #define UCM_REG_INT_MASK_1_IS_QM_S_OVFL_ERR_SHIFT                                                8
67649     #define UCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR                                                     (0x1<<9) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_QM_S_UNDER_ERR .
67650     #define UCM_REG_INT_MASK_1_IS_QM_S_UNDER_ERR_SHIFT                                               9
67651     #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0                                                      (0x1<<10) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR0 .
67652     #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR0_SHIFT                                                10
67653     #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0                                                     (0x1<<11) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR0 .
67654     #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR0_SHIFT                                               11
67655     #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1                                                      (0x1<<12) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR1 .
67656     #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR1_SHIFT                                                12
67657     #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR1 .
67658     #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR1_SHIFT                                               13
67659     #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2                                                      (0x1<<14) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR2 .
67660     #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR2_SHIFT                                                14
67661     #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2                                                     (0x1<<15) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR2 .
67662     #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR2_SHIFT                                               15
67663     #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3                                                      (0x1<<16) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_OVFL_ERR3 .
67664     #define UCM_REG_INT_MASK_1_IS_GRC_OVFL_ERR3_SHIFT                                                16
67665     #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3                                                     (0x1<<17) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IS_GRC_UNDER_ERR3 .
67666     #define UCM_REG_INT_MASK_1_IS_GRC_UNDER_ERR3_SHIFT                                               17
67667     #define UCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL                                                      (0x1<<18) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.IN_PRCS_TBL_OVFL .
67668     #define UCM_REG_INT_MASK_1_IN_PRCS_TBL_OVFL_SHIFT                                                18
67669     #define UCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL                                                 (0x1<<19) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_CON_DATA_BUF_OVFL .
67670     #define UCM_REG_INT_MASK_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                           19
67671     #define UCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL                                                  (0x1<<20) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_CON_CMD_BUF_OVFL .
67672     #define UCM_REG_INT_MASK_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                            20
67673     #define UCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL                                                  (0x1<<21) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_CON_DATA_BUF_OVFL .
67674     #define UCM_REG_INT_MASK_1_SM_CON_DATA_BUF_OVFL_SHIFT                                            21
67675     #define UCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL                                                   (0x1<<22) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_CON_CMD_BUF_OVFL .
67676     #define UCM_REG_INT_MASK_1_SM_CON_CMD_BUF_OVFL_SHIFT                                             22
67677     #define UCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_TASK_DATA_BUF_OVFL .
67678     #define UCM_REG_INT_MASK_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                          23
67679     #define UCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL                                                 (0x1<<24) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.AGG_TASK_CMD_BUF_OVFL .
67680     #define UCM_REG_INT_MASK_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                           24
67681     #define UCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL                                                 (0x1<<25) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_TASK_DATA_BUF_OVFL .
67682     #define UCM_REG_INT_MASK_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                           25
67683     #define UCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL                                                  (0x1<<26) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SM_TASK_CMD_BUF_OVFL .
67684     #define UCM_REG_INT_MASK_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                            26
67685     #define UCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE                                                 (0x1<<27) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.FI_DESC_INPUT_VIOLATE .
67686     #define UCM_REG_INT_MASK_1_FI_DESC_INPUT_VIOLATE_SHIFT                                           27
67687     #define UCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE                                                 (0x1<<28) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_1.SE_DESC_INPUT_VIOLATE .
67688     #define UCM_REG_INT_MASK_1_SE_DESC_INPUT_VIOLATE_SHIFT                                           28
67689 #define UCM_REG_INT_STS_WR_1                                                                         0x1280198UL //Access:WR   DataWidth:0x1d  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67690     #define UCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR                                                    (0x1<<0) // Write to full Dorq input buffer.
67691     #define UCM_REG_INT_STS_WR_1_IS_DORQ_OVFL_ERR_SHIFT                                              0
67692     #define UCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR                                                   (0x1<<1) // Read from empty  Dorq input buffer.
67693     #define UCM_REG_INT_STS_WR_1_IS_DORQ_UNDER_ERR_SHIFT                                             1
67694     #define UCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR                                                     (0x1<<2) // Write to full Pbf input buffer.
67695     #define UCM_REG_INT_STS_WR_1_IS_PBF_OVFL_ERR_SHIFT                                               2
67696     #define UCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR                                                    (0x1<<3) // Read from empty Pbf input buffer.
67697     #define UCM_REG_INT_STS_WR_1_IS_PBF_UNDER_ERR_SHIFT                                              3
67698     #define UCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR                                                      (0x1<<4) // Write to full TM input buffer.
67699     #define UCM_REG_INT_STS_WR_1_IS_TM_OVFL_ERR_SHIFT                                                4
67700     #define UCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR                                                     (0x1<<5) // Read from empty TM input buffer.
67701     #define UCM_REG_INT_STS_WR_1_IS_TM_UNDER_ERR_SHIFT                                               5
67702     #define UCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR                                                    (0x1<<6) // Write to full QM input buffer.
67703     #define UCM_REG_INT_STS_WR_1_IS_QM_P_OVFL_ERR_SHIFT                                              6
67704     #define UCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR                                                   (0x1<<7) // Read from empty QM input buffer.
67705     #define UCM_REG_INT_STS_WR_1_IS_QM_P_UNDER_ERR_SHIFT                                             7
67706     #define UCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR                                                    (0x1<<8) // Write to full QM input buffer.
67707     #define UCM_REG_INT_STS_WR_1_IS_QM_S_OVFL_ERR_SHIFT                                              8
67708     #define UCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR                                                   (0x1<<9) // Read from empty QM input buffer.
67709     #define UCM_REG_INT_STS_WR_1_IS_QM_S_UNDER_ERR_SHIFT                                             9
67710     #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0                                                    (0x1<<10) // Write to full GRC input buffer bits [31:0].
67711     #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR0_SHIFT                                              10
67712     #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0                                                   (0x1<<11) // Read from empty  GRC input buffer bits [31:0].
67713     #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR0_SHIFT                                             11
67714     #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1                                                    (0x1<<12) // Write to full GRC input buffer bits [63:32].
67715     #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR1_SHIFT                                              12
67716     #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1                                                   (0x1<<13) // Read from empty  GRC input buffer bits [63:32].
67717     #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR1_SHIFT                                             13
67718     #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2                                                    (0x1<<14) // Write to full GRC input buffer bits [95:64].
67719     #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR2_SHIFT                                              14
67720     #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2                                                   (0x1<<15) // Read from empty  GRC input buffer bits [95:64].
67721     #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR2_SHIFT                                             15
67722     #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3                                                    (0x1<<16) // Write to full GRC input buffer bits [127:96].
67723     #define UCM_REG_INT_STS_WR_1_IS_GRC_OVFL_ERR3_SHIFT                                              16
67724     #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3                                                   (0x1<<17) // Read from empty  GRC input buffer bits [127:96].
67725     #define UCM_REG_INT_STS_WR_1_IS_GRC_UNDER_ERR3_SHIFT                                             17
67726     #define UCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL                                                    (0x1<<18) // In-process Table overflow.
67727     #define UCM_REG_INT_STS_WR_1_IN_PRCS_TBL_OVFL_SHIFT                                              18
67728     #define UCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL                                               (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
67729     #define UCM_REG_INT_STS_WR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                         19
67730     #define UCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL                                                (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
67731     #define UCM_REG_INT_STS_WR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                          20
67732     #define UCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL                                                (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
67733     #define UCM_REG_INT_STS_WR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                          21
67734     #define UCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL                                                 (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
67735     #define UCM_REG_INT_STS_WR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                           22
67736     #define UCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL                                              (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
67737     #define UCM_REG_INT_STS_WR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                        23
67738     #define UCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL                                               (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
67739     #define UCM_REG_INT_STS_WR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                         24
67740     #define UCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL                                               (0x1<<25) // Message Processor Storm Task Data buffer overflow.
67741     #define UCM_REG_INT_STS_WR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                         25
67742     #define UCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL                                                (0x1<<26) // Message Processor Storm Task Command buffer overflow.
67743     #define UCM_REG_INT_STS_WR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                          26
67744     #define UCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE                                               (0x1<<27) // Input message first descriptor fields violation.
67745     #define UCM_REG_INT_STS_WR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                         27
67746     #define UCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE                                               (0x1<<28) // Input message second descriptor fields violation.
67747     #define UCM_REG_INT_STS_WR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                         28
67748 #define UCM_REG_INT_STS_CLR_1                                                                        0x128019cUL //Access:RC   DataWidth:0x1d  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67749     #define UCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR                                                   (0x1<<0) // Write to full Dorq input buffer.
67750     #define UCM_REG_INT_STS_CLR_1_IS_DORQ_OVFL_ERR_SHIFT                                             0
67751     #define UCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR                                                  (0x1<<1) // Read from empty  Dorq input buffer.
67752     #define UCM_REG_INT_STS_CLR_1_IS_DORQ_UNDER_ERR_SHIFT                                            1
67753     #define UCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR                                                    (0x1<<2) // Write to full Pbf input buffer.
67754     #define UCM_REG_INT_STS_CLR_1_IS_PBF_OVFL_ERR_SHIFT                                              2
67755     #define UCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR                                                   (0x1<<3) // Read from empty Pbf input buffer.
67756     #define UCM_REG_INT_STS_CLR_1_IS_PBF_UNDER_ERR_SHIFT                                             3
67757     #define UCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR                                                     (0x1<<4) // Write to full TM input buffer.
67758     #define UCM_REG_INT_STS_CLR_1_IS_TM_OVFL_ERR_SHIFT                                               4
67759     #define UCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR                                                    (0x1<<5) // Read from empty TM input buffer.
67760     #define UCM_REG_INT_STS_CLR_1_IS_TM_UNDER_ERR_SHIFT                                              5
67761     #define UCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR                                                   (0x1<<6) // Write to full QM input buffer.
67762     #define UCM_REG_INT_STS_CLR_1_IS_QM_P_OVFL_ERR_SHIFT                                             6
67763     #define UCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR                                                  (0x1<<7) // Read from empty QM input buffer.
67764     #define UCM_REG_INT_STS_CLR_1_IS_QM_P_UNDER_ERR_SHIFT                                            7
67765     #define UCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR                                                   (0x1<<8) // Write to full QM input buffer.
67766     #define UCM_REG_INT_STS_CLR_1_IS_QM_S_OVFL_ERR_SHIFT                                             8
67767     #define UCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR                                                  (0x1<<9) // Read from empty QM input buffer.
67768     #define UCM_REG_INT_STS_CLR_1_IS_QM_S_UNDER_ERR_SHIFT                                            9
67769     #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0                                                   (0x1<<10) // Write to full GRC input buffer bits [31:0].
67770     #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR0_SHIFT                                             10
67771     #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0                                                  (0x1<<11) // Read from empty  GRC input buffer bits [31:0].
67772     #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR0_SHIFT                                            11
67773     #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1                                                   (0x1<<12) // Write to full GRC input buffer bits [63:32].
67774     #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR1_SHIFT                                             12
67775     #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1                                                  (0x1<<13) // Read from empty  GRC input buffer bits [63:32].
67776     #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR1_SHIFT                                            13
67777     #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2                                                   (0x1<<14) // Write to full GRC input buffer bits [95:64].
67778     #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR2_SHIFT                                             14
67779     #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2                                                  (0x1<<15) // Read from empty  GRC input buffer bits [95:64].
67780     #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR2_SHIFT                                            15
67781     #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3                                                   (0x1<<16) // Write to full GRC input buffer bits [127:96].
67782     #define UCM_REG_INT_STS_CLR_1_IS_GRC_OVFL_ERR3_SHIFT                                             16
67783     #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3                                                  (0x1<<17) // Read from empty  GRC input buffer bits [127:96].
67784     #define UCM_REG_INT_STS_CLR_1_IS_GRC_UNDER_ERR3_SHIFT                                            17
67785     #define UCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL                                                   (0x1<<18) // In-process Table overflow.
67786     #define UCM_REG_INT_STS_CLR_1_IN_PRCS_TBL_OVFL_SHIFT                                             18
67787     #define UCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL                                              (0x1<<19) // Message Processor Aggregation Connection Data buffer overflow.
67788     #define UCM_REG_INT_STS_CLR_1_AGG_CON_DATA_BUF_OVFL_SHIFT                                        19
67789     #define UCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL                                               (0x1<<20) // Message Processor Aggregation Connection Command buffer overflow.
67790     #define UCM_REG_INT_STS_CLR_1_AGG_CON_CMD_BUF_OVFL_SHIFT                                         20
67791     #define UCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL                                               (0x1<<21) // Message Processor Storm Connection Data buffer overflow.
67792     #define UCM_REG_INT_STS_CLR_1_SM_CON_DATA_BUF_OVFL_SHIFT                                         21
67793     #define UCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL                                                (0x1<<22) // Message Processor Storm Connection Command buffer overflow.
67794     #define UCM_REG_INT_STS_CLR_1_SM_CON_CMD_BUF_OVFL_SHIFT                                          22
67795     #define UCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL                                             (0x1<<23) // Message Processor Aggregation Task Data buffer overflow.
67796     #define UCM_REG_INT_STS_CLR_1_AGG_TASK_DATA_BUF_OVFL_SHIFT                                       23
67797     #define UCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL                                              (0x1<<24) // Message Processor Aggregation Task Command buffer overflow.
67798     #define UCM_REG_INT_STS_CLR_1_AGG_TASK_CMD_BUF_OVFL_SHIFT                                        24
67799     #define UCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL                                              (0x1<<25) // Message Processor Storm Task Data buffer overflow.
67800     #define UCM_REG_INT_STS_CLR_1_SM_TASK_DATA_BUF_OVFL_SHIFT                                        25
67801     #define UCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL                                               (0x1<<26) // Message Processor Storm Task Command buffer overflow.
67802     #define UCM_REG_INT_STS_CLR_1_SM_TASK_CMD_BUF_OVFL_SHIFT                                         26
67803     #define UCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE                                              (0x1<<27) // Input message first descriptor fields violation.
67804     #define UCM_REG_INT_STS_CLR_1_FI_DESC_INPUT_VIOLATE_SHIFT                                        27
67805     #define UCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE                                              (0x1<<28) // Input message second descriptor fields violation.
67806     #define UCM_REG_INT_STS_CLR_1_SE_DESC_INPUT_VIOLATE_SHIFT                                        28
67807 #define UCM_REG_INT_STS_2                                                                            0x12801a0UL //Access:R    DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
67808     #define UCM_REG_INT_STS_2_QMREG_MORE4                                                            (0x1<<0) // More than 4 QM registrations.
67809     #define UCM_REG_INT_STS_2_QMREG_MORE4_SHIFT                                                      0
67810 #define UCM_REG_INT_MASK_2                                                                           0x12801a4UL //Access:RW   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
67811     #define UCM_REG_INT_MASK_2_QMREG_MORE4                                                           (0x1<<0) // This bit masks, when set, the Interrupt bit: UCM_REG_INT_STS_2.QMREG_MORE4 .
67812     #define UCM_REG_INT_MASK_2_QMREG_MORE4_SHIFT                                                     0
67813 #define UCM_REG_INT_STS_WR_2                                                                         0x12801a8UL //Access:WR   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
67814     #define UCM_REG_INT_STS_WR_2_QMREG_MORE4                                                         (0x1<<0) // More than 4 QM registrations.
67815     #define UCM_REG_INT_STS_WR_2_QMREG_MORE4_SHIFT                                                   0
67816 #define UCM_REG_INT_STS_CLR_2                                                                        0x12801acUL //Access:RC   DataWidth:0x1   Multi Field Register.  Chips: BB_A0 BB_B0 K2
67817     #define UCM_REG_INT_STS_CLR_2_QMREG_MORE4                                                        (0x1<<0) // More than 4 QM registrations.
67818     #define UCM_REG_INT_STS_CLR_2_QMREG_MORE4_SHIFT                                                  0
67819 #define UCM_REG_PRTY_MASK_H_0                                                                        0x1280204UL //Access:RW   DataWidth:0x1f  Multi Field Register.  Chips: BB_A0 BB_B0 K2
67820     #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT                                                (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM030_I_ECC_RF_INT .
67821     #define UCM_REG_PRTY_MASK_H_0_MEM030_I_ECC_RF_INT_SHIFT                                          0
67822     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_A0                                        (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
67823     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_A0_SHIFT                                  6
67824     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_B0                                        (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
67825     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_BB_B0_SHIFT                                  1
67826     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_K2                                           (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
67827     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_K2_SHIFT                                     1
67828     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_A0                                        (0x1<<7) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
67829     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_A0_SHIFT                                  7
67830     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_B0                                        (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
67831     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_BB_B0_SHIFT                                  2
67832     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_K2                                           (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
67833     #define UCM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_K2_SHIFT                                     2
67834     #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_ECC_0_RF_INT .
67835     #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_0_RF_INT_SHIFT                                        3
67836     #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_ECC_1_RF_INT .
67837     #define UCM_REG_PRTY_MASK_H_0_MEM024_I_ECC_1_RF_INT_SHIFT                                        4
67838     #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM025_I_ECC_RF_INT .
67839     #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_RF_INT_SHIFT                                          5
67840     #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_0_RF_INT                                              (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_ECC_0_RF_INT .
67841     #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_0_RF_INT_SHIFT                                        6
67842     #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_1_RF_INT                                              (0x1<<7) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_ECC_1_RF_INT .
67843     #define UCM_REG_PRTY_MASK_H_0_MEM007_I_ECC_1_RF_INT_SHIFT                                        7
67844     #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT                                                (0x1<<8) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM008_I_ECC_RF_INT .
67845     #define UCM_REG_PRTY_MASK_H_0_MEM008_I_ECC_RF_INT_SHIFT                                          8
67846     #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT                                              (0x1<<9) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_0_RF_INT .
67847     #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_0_RF_INT_SHIFT                                        9
67848     #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT                                              (0x1<<10) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_ECC_1_RF_INT .
67849     #define UCM_REG_PRTY_MASK_H_0_MEM027_I_ECC_1_RF_INT_SHIFT                                        10
67850     #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_A0                                          (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT .
67851     #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_A0_SHIFT                                    0
67852     #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_B0                                          (0x1<<11) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT .
67853     #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_BB_B0_SHIFT                                    11
67854     #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_K2                                             (0x1<<11) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM028_I_ECC_RF_INT .
67855     #define UCM_REG_PRTY_MASK_H_0_MEM028_I_ECC_RF_INT_K2_SHIFT                                       11
67856     #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0                                            (0x1<<17) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
67857     #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_A0_SHIFT                                      17
67858     #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0                                            (0x1<<12) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
67859     #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_BB_B0_SHIFT                                      12
67860     #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2                                               (0x1<<12) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM020_I_MEM_PRTY .
67861     #define UCM_REG_PRTY_MASK_H_0_MEM020_I_MEM_PRTY_K2_SHIFT                                         12
67862     #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_A0                                            (0x1<<29) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
67863     #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_A0_SHIFT                                      29
67864     #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_B0                                            (0x1<<13) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
67865     #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_BB_B0_SHIFT                                      13
67866     #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2                                               (0x1<<13) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM021_I_MEM_PRTY .
67867     #define UCM_REG_PRTY_MASK_H_0_MEM021_I_MEM_PRTY_K2_SHIFT                                         13
67868     #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0                                            (0x1<<13) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
67869     #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_A0_SHIFT                                      13
67870     #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0                                            (0x1<<14) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
67871     #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_BB_B0_SHIFT                                      14
67872     #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2                                               (0x1<<14) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM019_I_MEM_PRTY .
67873     #define UCM_REG_PRTY_MASK_H_0_MEM019_I_MEM_PRTY_K2_SHIFT                                         14
67874     #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0                                            (0x1<<19) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
67875     #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_A0_SHIFT                                      19
67876     #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0                                            (0x1<<15) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
67877     #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_BB_B0_SHIFT                                      15
67878     #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2                                               (0x1<<15) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM013_I_MEM_PRTY .
67879     #define UCM_REG_PRTY_MASK_H_0_MEM013_I_MEM_PRTY_K2_SHIFT                                         15
67880     #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0                                            (0x1<<12) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
67881     #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_A0_SHIFT                                      12
67882     #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0                                            (0x1<<16) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
67883     #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_BB_B0_SHIFT                                      16
67884     #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2                                               (0x1<<16) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM018_I_MEM_PRTY .
67885     #define UCM_REG_PRTY_MASK_H_0_MEM018_I_MEM_PRTY_K2_SHIFT                                         16
67886     #define UCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY                                                  (0x1<<17) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM022_I_MEM_PRTY .
67887     #define UCM_REG_PRTY_MASK_H_0_MEM022_I_MEM_PRTY_SHIFT                                            17
67888     #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0                                            (0x1<<20) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
67889     #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_A0_SHIFT                                      20
67890     #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0                                            (0x1<<18) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
67891     #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_BB_B0_SHIFT                                      18
67892     #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2                                               (0x1<<18) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM014_I_MEM_PRTY .
67893     #define UCM_REG_PRTY_MASK_H_0_MEM014_I_MEM_PRTY_K2_SHIFT                                         18
67894     #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0                                            (0x1<<21) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
67895     #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_A0_SHIFT                                      21
67896     #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0                                            (0x1<<19) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
67897     #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_BB_B0_SHIFT                                      19
67898     #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2                                               (0x1<<19) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM015_I_MEM_PRTY .
67899     #define UCM_REG_PRTY_MASK_H_0_MEM015_I_MEM_PRTY_K2_SHIFT                                         19
67900     #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0                                            (0x1<<16) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
67901     #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_A0_SHIFT                                      16
67902     #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0                                            (0x1<<20) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
67903     #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_BB_B0_SHIFT                                      20
67904     #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2                                               (0x1<<20) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM016_I_MEM_PRTY .
67905     #define UCM_REG_PRTY_MASK_H_0_MEM016_I_MEM_PRTY_K2_SHIFT                                         20
67906     #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0                                            (0x1<<14) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
67907     #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_A0_SHIFT                                      14
67908     #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0                                            (0x1<<21) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
67909     #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_BB_B0_SHIFT                                      21
67910     #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2                                               (0x1<<21) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM017_I_MEM_PRTY .
67911     #define UCM_REG_PRTY_MASK_H_0_MEM017_I_MEM_PRTY_K2_SHIFT                                         21
67912     #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY                                                  (0x1<<22) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM033_I_MEM_PRTY .
67913     #define UCM_REG_PRTY_MASK_H_0_MEM033_I_MEM_PRTY_SHIFT                                            22
67914     #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM032_I_MEM_PRTY .
67915     #define UCM_REG_PRTY_MASK_H_0_MEM032_I_MEM_PRTY_SHIFT                                            23
67916     #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_A0                                            (0x1<<22) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
67917     #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_A0_SHIFT                                      22
67918     #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_B0                                            (0x1<<24) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
67919     #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_BB_B0_SHIFT                                      24
67920     #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2                                               (0x1<<24) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM031_I_MEM_PRTY .
67921     #define UCM_REG_PRTY_MASK_H_0_MEM031_I_MEM_PRTY_K2_SHIFT                                         24
67922     #define UCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM006_I_MEM_PRTY .
67923     #define UCM_REG_PRTY_MASK_H_0_MEM006_I_MEM_PRTY_SHIFT                                            25
67924     #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_MEM_PRTY .
67925     #define UCM_REG_PRTY_MASK_H_0_MEM026_I_MEM_PRTY_SHIFT                                            26
67926     #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM009_I_MEM_PRTY .
67927     #define UCM_REG_PRTY_MASK_H_0_MEM009_I_MEM_PRTY_SHIFT                                            27
67928     #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0                                            (0x1<<24) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
67929     #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_A0_SHIFT                                      24
67930     #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0                                            (0x1<<28) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
67931     #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_BB_B0_SHIFT                                      28
67932     #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2                                               (0x1<<28) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM029_I_MEM_PRTY .
67933     #define UCM_REG_PRTY_MASK_H_0_MEM029_I_MEM_PRTY_K2_SHIFT                                         28
67934     #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY                                                  (0x1<<29) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM023_I_MEM_PRTY .
67935     #define UCM_REG_PRTY_MASK_H_0_MEM023_I_MEM_PRTY_SHIFT                                            29
67936     #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0                                                (0x1<<30) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM010_I_MEM_PRTY_0 .
67937     #define UCM_REG_PRTY_MASK_H_0_MEM010_I_MEM_PRTY_0_SHIFT                                          30
67938     #define UCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT                                              (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM003_I_ECC_0_RF_INT .
67939     #define UCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_0_RF_INT_SHIFT                                        1
67940     #define UCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT                                              (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM003_I_ECC_1_RF_INT .
67941     #define UCM_REG_PRTY_MASK_H_0_MEM003_I_ECC_1_RF_INT_SHIFT                                        2
67942     #define UCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT                                              (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM022_I_ECC_0_RF_INT .
67943     #define UCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_0_RF_INT_SHIFT                                        3
67944     #define UCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT                                              (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM022_I_ECC_1_RF_INT .
67945     #define UCM_REG_PRTY_MASK_H_0_MEM022_I_ECC_1_RF_INT_SHIFT                                        4
67946     #define UCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT                                                (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM023_I_ECC_RF_INT .
67947     #define UCM_REG_PRTY_MASK_H_0_MEM023_I_ECC_RF_INT_SHIFT                                          5
67948     #define UCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT                                                (0x1<<8) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM006_I_ECC_RF_INT .
67949     #define UCM_REG_PRTY_MASK_H_0_MEM006_I_ECC_RF_INT_SHIFT                                          8
67950     #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT                                              (0x1<<9) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM025_I_ECC_0_RF_INT .
67951     #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_0_RF_INT_SHIFT                                        9
67952     #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT                                              (0x1<<10) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM025_I_ECC_1_RF_INT .
67953     #define UCM_REG_PRTY_MASK_H_0_MEM025_I_ECC_1_RF_INT_SHIFT                                        10
67954     #define UCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT                                                (0x1<<11) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM026_I_ECC_RF_INT .
67955     #define UCM_REG_PRTY_MASK_H_0_MEM026_I_ECC_RF_INT_SHIFT                                          11
67956     #define UCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY                                                  (0x1<<15) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM011_I_MEM_PRTY .
67957     #define UCM_REG_PRTY_MASK_H_0_MEM011_I_MEM_PRTY_SHIFT                                            15
67958     #define UCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY                                                  (0x1<<18) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM012_I_MEM_PRTY .
67959     #define UCM_REG_PRTY_MASK_H_0_MEM012_I_MEM_PRTY_SHIFT                                            18
67960     #define UCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY                                                  (0x1<<23) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM030_I_MEM_PRTY .
67961     #define UCM_REG_PRTY_MASK_H_0_MEM030_I_MEM_PRTY_SHIFT                                            23
67962     #define UCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                  (0x1<<25) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
67963     #define UCM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                            25
67964     #define UCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY                                                  (0x1<<26) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM024_I_MEM_PRTY .
67965     #define UCM_REG_PRTY_MASK_H_0_MEM024_I_MEM_PRTY_SHIFT                                            26
67966     #define UCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY                                                  (0x1<<27) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM007_I_MEM_PRTY .
67967     #define UCM_REG_PRTY_MASK_H_0_MEM007_I_MEM_PRTY_SHIFT                                            27
67968     #define UCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY                                                  (0x1<<28) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM027_I_MEM_PRTY .
67969     #define UCM_REG_PRTY_MASK_H_0_MEM027_I_MEM_PRTY_SHIFT                                            28
67970     #define UCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0                                                (0x1<<30) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_0.MEM008_I_MEM_PRTY_0 .
67971     #define UCM_REG_PRTY_MASK_H_0_MEM008_I_MEM_PRTY_0_SHIFT                                          30
67972 #define UCM_REG_PRTY_MASK_H_1                                                                        0x1280214UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
67973     #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1                                                (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY_1 .
67974     #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_1_SHIFT                                          0
67975     #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM011_I_MEM_PRTY .
67976     #define UCM_REG_PRTY_MASK_H_1_MEM011_I_MEM_PRTY_SHIFT                                            1
67977     #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM012_I_MEM_PRTY .
67978     #define UCM_REG_PRTY_MASK_H_1_MEM012_I_MEM_PRTY_SHIFT                                            2
67979     #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY                                                  (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM003_I_MEM_PRTY .
67980     #define UCM_REG_PRTY_MASK_H_1_MEM003_I_MEM_PRTY_SHIFT                                            3
67981     #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY                                                  (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM004_I_MEM_PRTY .
67982     #define UCM_REG_PRTY_MASK_H_1_MEM004_I_MEM_PRTY_SHIFT                                            4
67983     #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_A0                                            (0x1<<3) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
67984     #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_A0_SHIFT                                      3
67985     #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0                                            (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
67986     #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_BB_B0_SHIFT                                      5
67987     #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2                                               (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM001_I_MEM_PRTY .
67988     #define UCM_REG_PRTY_MASK_H_1_MEM001_I_MEM_PRTY_K2_SHIFT                                         5
67989     #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_A0                                            (0x1<<4) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
67990     #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_A0_SHIFT                                      4
67991     #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0                                            (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
67992     #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_BB_B0_SHIFT                                      6
67993     #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2                                               (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM002_I_MEM_PRTY .
67994     #define UCM_REG_PRTY_MASK_H_1_MEM002_I_MEM_PRTY_K2_SHIFT                                         6
67995     #define UCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1                                                (0x1<<0) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM008_I_MEM_PRTY_1 .
67996     #define UCM_REG_PRTY_MASK_H_1_MEM008_I_MEM_PRTY_1_SHIFT                                          0
67997     #define UCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY                                                  (0x1<<1) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM009_I_MEM_PRTY .
67998     #define UCM_REG_PRTY_MASK_H_1_MEM009_I_MEM_PRTY_SHIFT                                            1
67999     #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY                                                  (0x1<<2) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM010_I_MEM_PRTY .
68000     #define UCM_REG_PRTY_MASK_H_1_MEM010_I_MEM_PRTY_SHIFT                                            2
68001     #define UCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY                                                  (0x1<<5) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM032_I_MEM_PRTY .
68002     #define UCM_REG_PRTY_MASK_H_1_MEM032_I_MEM_PRTY_SHIFT                                            5
68003     #define UCM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY                                                  (0x1<<6) // This bit masks, when set, the Parity bit: UCM_REG_PRTY_STS_H_1.MEM033_I_MEM_PRTY .
68004     #define UCM_REG_PRTY_MASK_H_1_MEM033_I_MEM_PRTY_SHIFT                                            6
68005 #define UCM_REG_MEM_ECC_EVENTS                                                                       0x1280234UL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
68006 #define UCM_REG_MEM020_I_MEM_DFT_K2                                                                  0x128023cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_storm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68007 #define UCM_REG_MEM021_I_MEM_DFT_K2                                                                  0x1280240UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_usdm_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68008 #define UCM_REG_MEM019_I_MEM_DFT_K2                                                                  0x1280244UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_pbf_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68009 #define UCM_REG_MEM018_I_MEM_DFT_K2                                                                  0x1280248UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_muld_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68010 #define UCM_REG_MEM022_I_MEM_DFT_K2                                                                  0x128024cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_yuld_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68011 #define UCM_REG_MEM014_I_MEM_DFT_K2                                                                  0x1280250UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_grc0_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68012 #define UCM_REG_MEM015_I_MEM_DFT_K2                                                                  0x1280254UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_grc1_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68013 #define UCM_REG_MEM016_I_MEM_DFT_K2                                                                  0x1280258UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_grc2_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68014 #define UCM_REG_MEM017_I_MEM_DFT_K2                                                                  0x128025cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_is_grc3_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68015 #define UCM_REG_MEM030_I_MEM_DFT_K2                                                                  0x1280260UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_xx_msg_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68016 #define UCM_REG_MEM033_I_MEM_DFT_K2                                                                  0x1280264UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_xx_pref_dir.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68017 #define UCM_REG_MEM032_I_MEM_DFT_K2                                                                  0x1280268UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_xx_pref_byp.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68018 #define UCM_REG_MEM031_I_MEM_DFT_K2                                                                  0x128026cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_xx_pref_aggst.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68019 #define UCM_REG_MEM006_I_MEM_DFT_K2                                                                  0x1280270UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_agg_con_data_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68020 #define UCM_REG_MEM005_I_MEM_DFT_K2                                                                  0x1280274UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_agg_con_ctx.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68021 #define UCM_REG_MEM026_I_MEM_DFT_K2                                                                  0x1280278UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_sm_con_data.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68022 #define UCM_REG_MEM024_I_MEM_DFT_K2                                                                  0x128027cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_sm_con_ctx_0_11.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68023 #define UCM_REG_MEM025_I_MEM_DFT_K2                                                                  0x1280280UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_sm_con_ctx_12.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68024 #define UCM_REG_MEM009_I_MEM_DFT_K2                                                                  0x1280284UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_agg_task_data_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68025 #define UCM_REG_MEM007_I_MEM_DFT_K2                                                                  0x1280288UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_agg_task_ctx_0_1.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68026 #define UCM_REG_MEM008_I_MEM_DFT_K2                                                                  0x128028cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_agg_task_ctx_2.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68027 #define UCM_REG_MEM029_I_MEM_DFT_K2                                                                  0x1280290UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_sm_task_data_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68028 #define UCM_REG_MEM027_I_MEM_DFT_K2                                                                  0x1280294UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_sm_task_ctx_0_1.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68029 #define UCM_REG_MEM028_I_MEM_DFT_K2                                                                  0x1280298UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_sm_task_ctx_2.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68030 #define UCM_REG_MEM023_I_MEM_DFT_K2                                                                  0x128029cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_prcs_trans_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68031 #define UCM_REG_MEM010_I_MEM_DFT_K2                                                                  0x12802a0UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.i_in_prcs_msgin.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68032 #define UCM_REG_MEM003_I_MEM_DFT_K2                                                                  0x12802a4UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.IS_QMPOP_P_BUF_K2_.i_is_qmpop_p_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68033 #define UCM_REG_MEM004_I_MEM_DFT_K2                                                                  0x12802a8UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ucm.IS_QMPOP_S_BUF_K2_.i_is_qmpop_s_buf.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68034 #define UCM_REG_IFEN                                                                                 0x1280400UL //Access:RW   DataWidth:0x1   Interface enable. If 0 - the acknowledge input is disregarded; valid is deasserted; all other signals are treated as usual; if 1 - normal activity.  Chips: BB_A0 BB_B0 K2
68035 #define UCM_REG_QM_CON_BASE_EVNT_ID_0                                                                0x1280404UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68036 #define UCM_REG_QM_CON_BASE_EVNT_ID_1                                                                0x1280408UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68037 #define UCM_REG_QM_CON_BASE_EVNT_ID_2                                                                0x128040cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68038 #define UCM_REG_QM_CON_BASE_EVNT_ID_3                                                                0x1280410UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68039 #define UCM_REG_QM_CON_BASE_EVNT_ID_4                                                                0x1280414UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68040 #define UCM_REG_QM_CON_BASE_EVNT_ID_5                                                                0x1280418UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68041 #define UCM_REG_QM_CON_BASE_EVNT_ID_6                                                                0x128041cUL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68042 #define UCM_REG_QM_CON_BASE_EVNT_ID_7                                                                0x1280420UL //Access:RW   DataWidth:0x8   QM connection base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68043 #define UCM_REG_QM_TASK_BASE_EVNT_ID_0                                                               0x1280424UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68044 #define UCM_REG_QM_TASK_BASE_EVNT_ID_1                                                               0x1280428UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68045 #define UCM_REG_QM_TASK_BASE_EVNT_ID_2                                                               0x128042cUL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68046 #define UCM_REG_QM_TASK_BASE_EVNT_ID_3                                                               0x1280430UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68047 #define UCM_REG_QM_TASK_BASE_EVNT_ID_4                                                               0x1280434UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68048 #define UCM_REG_QM_TASK_BASE_EVNT_ID_5                                                               0x1280438UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68049 #define UCM_REG_QM_TASK_BASE_EVNT_ID_6                                                               0x128043cUL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68050 #define UCM_REG_QM_TASK_BASE_EVNT_ID_7                                                               0x1280440UL //Access:RW   DataWidth:0x8   QM task base Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68051 #define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_0                                                           0x1280444UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
68052 #define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_1                                                           0x1280448UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
68053 #define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_2                                                           0x128044cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
68054 #define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_3                                                           0x1280450UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
68055 #define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_4                                                           0x1280454UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
68056 #define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_5                                                           0x1280458UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
68057 #define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_6                                                           0x128045cUL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
68058 #define UCM_REG_QM_AGG_CON_CTX_PART_SIZE_7                                                           0x1280460UL //Access:RW   DataWidth:0x4   QM agggregation connection context part size per connection type.  Chips: BB_A0 BB_B0 K2
68059 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_0                                                             0x1280464UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
68060 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_1                                                             0x1280468UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
68061 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_2                                                             0x128046cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
68062 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_3                                                             0x1280470UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
68063 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_4                                                             0x1280474UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
68064 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_5                                                             0x1280478UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
68065 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_6                                                             0x128047cUL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
68066 #define UCM_REG_QM_SM_CON_CTX_LDST_FLG_7                                                             0x1280480UL //Access:RW   DataWidth:0x1   QM storm connection context load_store per connection type.  Chips: BB_A0 BB_B0 K2
68067 #define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_0                                                          0x1280484UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
68068 #define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_1                                                          0x1280488UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
68069 #define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_2                                                          0x128048cUL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
68070 #define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_3                                                          0x1280490UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
68071 #define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_4                                                          0x1280494UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
68072 #define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_5                                                          0x1280498UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
68073 #define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_6                                                          0x128049cUL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
68074 #define UCM_REG_QM_AGG_TASK_CTX_PART_SIZE_7                                                          0x12804a0UL //Access:RW   DataWidth:0x4   QM agggregation task context part size per connection type. Is 0 in case AggCtxLdStFlg=0; is greater than 0 in case AggCtxLdStFlg=1.  Chips: BB_A0 BB_B0 K2
68075 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_0                                                            0x12804a4UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
68076 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_1                                                            0x12804a8UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
68077 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_2                                                            0x12804acUL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
68078 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_3                                                            0x12804b0UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
68079 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_4                                                            0x12804b4UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
68080 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_5                                                            0x12804b8UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
68081 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_6                                                            0x12804bcUL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
68082 #define UCM_REG_QM_SM_TASK_CTX_LDST_FLG_7                                                            0x12804c0UL //Access:RW   DataWidth:0x1   QM storm task context load_store per task type.  Chips: BB_A0 BB_B0 K2
68083 #define UCM_REG_QM_XXLOCK_CMD_0                                                                      0x12804c4UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
68084 #define UCM_REG_QM_XXLOCK_CMD_1                                                                      0x12804c8UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
68085 #define UCM_REG_QM_XXLOCK_CMD_2                                                                      0x12804ccUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
68086 #define UCM_REG_QM_XXLOCK_CMD_3                                                                      0x12804d0UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
68087 #define UCM_REG_QM_XXLOCK_CMD_4                                                                      0x12804d4UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
68088 #define UCM_REG_QM_XXLOCK_CMD_5                                                                      0x12804d8UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
68089 #define UCM_REG_QM_XXLOCK_CMD_6                                                                      0x12804dcUL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
68090 #define UCM_REG_QM_XXLOCK_CMD_7                                                                      0x12804e0UL //Access:RW   DataWidth:0x3   QM XxLock command per connection type.  Chips: BB_A0 BB_B0 K2
68091 #define UCM_REG_QM_CON_USE_ST_FLG_0                                                                  0x12804e4UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
68092 #define UCM_REG_QM_CON_USE_ST_FLG_1                                                                  0x12804e8UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
68093 #define UCM_REG_QM_CON_USE_ST_FLG_2                                                                  0x12804ecUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
68094 #define UCM_REG_QM_CON_USE_ST_FLG_3                                                                  0x12804f0UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
68095 #define UCM_REG_QM_CON_USE_ST_FLG_4                                                                  0x12804f4UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
68096 #define UCM_REG_QM_CON_USE_ST_FLG_5                                                                  0x12804f8UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
68097 #define UCM_REG_QM_CON_USE_ST_FLG_6                                                                  0x12804fcUL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
68098 #define UCM_REG_QM_CON_USE_ST_FLG_7                                                                  0x1280500UL //Access:RW   DataWidth:0x1   QM Connection use state flag per connection type. Should be all 0 for PCM and YCM.  Chips: BB_A0 BB_B0 K2
68099 #define UCM_REG_QM_TASK_USE_ST_FLG_0                                                                 0x1280504UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
68100 #define UCM_REG_QM_TASK_USE_ST_FLG_1                                                                 0x1280508UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
68101 #define UCM_REG_QM_TASK_USE_ST_FLG_2                                                                 0x128050cUL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
68102 #define UCM_REG_QM_TASK_USE_ST_FLG_3                                                                 0x1280510UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
68103 #define UCM_REG_QM_TASK_USE_ST_FLG_4                                                                 0x1280514UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
68104 #define UCM_REG_QM_TASK_USE_ST_FLG_5                                                                 0x1280518UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
68105 #define UCM_REG_QM_TASK_USE_ST_FLG_6                                                                 0x128051cUL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM. in XCM.  Chips: BB_A0 BB_B0 K2
68106 #define UCM_REG_QM_TASK_USE_ST_FLG_7                                                                 0x1280520UL //Access:RW   DataWidth:0x1   QM Task use state flag per connection type. Should be all 0 for PCM and XCM.  Chips: BB_A0 BB_B0 K2
68107 #define UCM_REG_TM_CON_EVNT_ID_0                                                                     0x1280524UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68108 #define UCM_REG_TM_CON_EVNT_ID_1                                                                     0x1280528UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68109 #define UCM_REG_TM_CON_EVNT_ID_2                                                                     0x128052cUL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68110 #define UCM_REG_TM_CON_EVNT_ID_3                                                                     0x1280530UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68111 #define UCM_REG_TM_CON_EVNT_ID_4                                                                     0x1280534UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68112 #define UCM_REG_TM_CON_EVNT_ID_5                                                                     0x1280538UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68113 #define UCM_REG_TM_CON_EVNT_ID_6                                                                     0x128053cUL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68114 #define UCM_REG_TM_CON_EVNT_ID_7                                                                     0x1280540UL //Access:RW   DataWidth:0x8   TM connection Event ID per connection type.:  Chips: BB_A0 BB_B0 K2
68115 #define UCM_REG_TM_TASK_EVNT_ID_0                                                                    0x1280544UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68116 #define UCM_REG_TM_TASK_EVNT_ID_1                                                                    0x1280548UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68117 #define UCM_REG_TM_TASK_EVNT_ID_2                                                                    0x128054cUL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68118 #define UCM_REG_TM_TASK_EVNT_ID_3                                                                    0x1280550UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68119 #define UCM_REG_TM_TASK_EVNT_ID_4                                                                    0x1280554UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68120 #define UCM_REG_TM_TASK_EVNT_ID_5                                                                    0x1280558UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68121 #define UCM_REG_TM_TASK_EVNT_ID_6                                                                    0x128055cUL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68122 #define UCM_REG_TM_TASK_EVNT_ID_7                                                                    0x1280560UL //Access:RW   DataWidth:0x8   TM task Event ID per connection type.  Chips: BB_A0 BB_B0 K2
68123 #define UCM_REG_ERR_EVNT_ID                                                                          0x1280564UL //Access:RW   DataWidth:0x8   The Event ID in case one of errors is set in QM input message.  Chips: BB_A0 BB_B0 K2
68124 #define UCM_REG_STORM_WEIGHT                                                                         0x1280604UL //Access:RW   DataWidth:0x3   The weight of the local Storm input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68125 #define UCM_REG_DORQ_WEIGHT                                                                          0x1280608UL //Access:RW   DataWidth:0x3   The weight of the input Dorq in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68126 #define UCM_REG_PBF_WEIGHT                                                                           0x128060cUL //Access:RW   DataWidth:0x3   The weight of the input Pbf in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68127 #define UCM_REG_GRC_WEIGHT                                                                           0x1280610UL //Access:RW   DataWidth:0x3   The weight of the GRC input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68128 #define UCM_REG_XSDM_WEIGHT                                                                          0x1280614UL //Access:RW   DataWidth:0x3   The weight of the XSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68129 #define UCM_REG_YSDM_WEIGHT                                                                          0x1280618UL //Access:RW   DataWidth:0x3   The weight of the YSDM input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68130 #define UCM_REG_USDM_WEIGHT                                                                          0x128061cUL //Access:RW   DataWidth:0x3   The weight of the input USDM in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68131 #define UCM_REG_RDIF_WEIGHT                                                                          0x1280620UL //Access:RW   DataWidth:0x3   The weight of the input RDIF in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68132 #define UCM_REG_TDIF_WEIGHT                                                                          0x1280624UL //Access:RW   DataWidth:0x3   The weight of the input RDIF in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68133 #define UCM_REG_MULD_WEIGHT                                                                          0x1280628UL //Access:RW   DataWidth:0x3   The weight of the input MULD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.:  Chips: BB_A0 BB_B0 K2
68134 #define UCM_REG_YULD_WEIGHT                                                                          0x128062cUL //Access:RW   DataWidth:0x3   The weight of the input YULD in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68135 #define UCM_REG_QM_P_WEIGHT                                                                          0x1280630UL //Access:RW   DataWidth:0x3   The weight of the QM (primary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68136 #define UCM_REG_QM_S_WEIGHT                                                                          0x1280634UL //Access:RW   DataWidth:0x3   The weight of the QM (secondary) input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68137 #define UCM_REG_TM_WEIGHT                                                                            0x1280638UL //Access:RW   DataWidth:0x3   The weight of the Timers input in the Input Arbiter WRR mechanism. 0 stands for weight 8 (the most prioritised); 1 stands for weight 1(least prioritised); 2 stands for weight 2;etc.  Chips: BB_A0 BB_B0 K2
68138 #define UCM_REG_IA_GROUP_PR0                                                                         0x128063cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: ia_group_pr0 is the highest priority; ia_group_pr5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
68139 #define UCM_REG_IA_GROUP_PR1                                                                         0x1280640UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
68140 #define UCM_REG_IA_GROUP_PR2                                                                         0x1280644UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
68141 #define UCM_REG_IA_GROUP_PR3                                                                         0x1280648UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
68142 #define UCM_REG_IA_GROUP_PR4                                                                         0x128064cUL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
68143 #define UCM_REG_IA_GROUP_PR5                                                                         0x1280650UL //Access:RW   DataWidth:0x3   Input Arbiter group client corresponding to group priority 0. 0 - Is.Agg group 1- Is.AggSt group; 2 - Is.Dir group; 3 - Xx.Dir group; 4 - Xx.AggSt group; 5- Xx.Byp group. Each priority need to be unique. NOTE: 0 is the highest priority; 5 is the lowest priority.  Chips: BB_A0 BB_B0 K2
68144 #define UCM_REG_IA_ARB_SP_TIMEOUT                                                                    0x1280654UL //Access:RW   DataWidth:0x8   Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. Two values have special meaning: 8'h0 - constant RR; 8'h80 - constant strict priority.  Chips: BB_A0 BB_B0 K2
68145 #define UCM_REG_STORM_FRWRD_MODE                                                                     0x1280658UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68146 #define UCM_REG_XSDM_FRWRD_MODE                                                                      0x128065cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68147 #define UCM_REG_YSDM_FRWRD_MODE                                                                      0x1280660UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68148 #define UCM_REG_PSDM_FRWRD_MODE                                                                      0x1280664UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68149 #define UCM_REG_USDM_FRWRD_MODE                                                                      0x1280668UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68150 #define UCM_REG_RDIF_FRWRD_MODE                                                                      0x128066cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68151 #define UCM_REG_TDIF_FRWRD_MODE                                                                      0x1280670UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68152 #define UCM_REG_MULD_FRWRD_MODE                                                                      0x1280674UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68153 #define UCM_REG_YULD_FRWRD_MODE                                                                      0x1280678UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68154 #define UCM_REG_DORQ_FRWRD_MODE                                                                      0x128067cUL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68155 #define UCM_REG_PBF_FRWRD_MODE                                                                       0x1280680UL //Access:RW   DataWidth:0x1   Input message mode. If 0 - cut-through; if 1 - store-forward.  Chips: BB_A0 BB_B0 K2
68156 #define UCM_REG_SDM_ERR_HANDLE_EN                                                                    0x1280684UL //Access:RW   DataWidth:0x1   0 - disable error handling in SDM message; 1 - enable error handling in SDM message.  Chips: BB_A0 BB_B0 K2
68157 #define UCM_REG_DIR_BYP_EN                                                                           0x1280688UL //Access:RW   DataWidth:0x1   Direct bypass enable.  Chips: BB_A0 BB_B0 K2
68158 #define UCM_REG_FI_DESC_INPUT_VIOLATE                                                                0x128068cUL //Access:R    DataWidth:0x10  Input message first descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation:  TaskExist==0 -> XxLockCmd != XX_UNLOCK_CID_TID and XxLockCmd != XX_LOCK_CID_TID_BYPASS;  [12] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0;[13] - Violation: Agg message: Loader done with error then SmCtxLdStFlg==0; [14] - Violation: Agg Store message then Loader done with error; [15] - Violation: XxBypass message in PCM block;  Chips: BB_A0 BB_B0 K2
68159 #define UCM_REG_SE_DESC_INPUT_VIOLATE                                                                0x1280690UL //Access:R    DataWidth:0xc   Input message second descriptor fields violation: [4:0] - Global client number that violated the input; [5] - Violation: Agg/Direct message: AggCtxLdStFlg == 0  then AggDecType == NULL; [6] - Violation: Agg message: AggDecType == NULL  then AggCtxLdStFlg == 1; [7] - Violation: Agg/Direct message: AggCtxLdStFlg==0 then AggCtxPartSize==0; [8]- Violation: Agg message: In connection domain : AggCtxPartSize < NC_IAG or In task domain : AggCtxPartSize < NT_IAG; [9]- Violation: Diect message: In connection domain : AggCtxPartSize < CC_IAG or In task domain : AggCtxPartSize < CT_IAG; [10] - Violation:  Direct message: UsestateFlg==1 then AggCtxLdStFlg == 1; [11] - Violation: Agg/Direct message: AggCtxLdStFlg==1 then AggCtxPartSize>0; Read only register.  Chips: BB_A0 BB_B0 K2
68160 #define UCM_REG_IA_AGG_CON_PART_FILL_LVL                                                             0x1280694UL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
68161 #define UCM_REG_IA_SM_CON_PART_FILL_LVL                                                              0x1280698UL //Access:R    DataWidth:0x3   Input Arbiter Storm Connection part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
68162 #define UCM_REG_IA_AGG_TASK_PART_FILL_LVL                                                            0x128069cUL //Access:R    DataWidth:0x3   Input Arbiter Aggregation Task part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
68163 #define UCM_REG_IA_SM_TASK_PART_FILL_LVL                                                             0x12806a0UL //Access:R    DataWidth:0x3   Input Arbiter Storm Task part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
68164 #define UCM_REG_IA_TRANS_PART_FILL_LVL                                                               0x12806a4UL //Access:R    DataWidth:0x3   Input Arbiter Transparent part FIFO fill level (in messages).  Chips: BB_A0 BB_B0 K2
68165 #define UCM_REG_XX_MSG_UP_BND                                                                        0x1280704UL //Access:RW   DataWidth:0x7   The maximum number of Xx RAM messages; which may be stored in XX protection. Is restricted by Xx Messages RAM size and the siz of Xx protected message CM_REGISTERS_XX_MSG_SIZE_BND.XX_MSG_SIZE_BND  Chips: BB_A0 BB_B0 K2
68166 #define UCM_REG_XX_MSG_SIZE                                                                          0x1280708UL //Access:RW   DataWidth:0xb   The size of Xx protected message in Xx Messages RAM in QREGs. Upper rounded to even number and multiplied by CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND should not exceed XxMessagesRam size which is: MCM: 0d1664 PCM: 0d176 TCM: 0d1408 UCM: 0d1664 XCM: 0d256 YCM: 0d1536  Chips: BB_A0 BB_B0 K2
68167 #define UCM_REG_XX_LCID_CAM_UP_BND                                                                   0x128070cUL //Access:RW   DataWidth:0x5   The maximum number of connections in the XX protection LCID CAM.  Chips: BB_A0 BB_B0 K2
68168 #define UCM_REG_XX_FREE_CNT                                                                          0x1280710UL //Access:R    DataWidth:0x7   Used to read the XX protection Free counter. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
68169 #define UCM_REG_XX_LCID_CAM_FILL_LVL                                                                 0x1280714UL //Access:R    DataWidth:0x5   Used to read XX protection LCID CAM fill level. Fill level is calculated as the number of locked LCIDs, i.e. LCIDs that have at least one Xx locked message or LCIDs that have no Xx locked messages but haven't been unlocked yet from LCID CAM. Simple saying it calculates for number of valid entries in LCID CAM.  Chips: BB_A0 BB_B0 K2
68170 #define UCM_REG_XX_LCID_CAM_ST_STAT                                                                  0x1280718UL //Access:RC   DataWidth:0x5   CAM occupancy sticky status. The write to the register is performed by the XX internal circuitry.  Chips: BB_A0 BB_B0 K2
68171 #define UCM_REG_XX_IA_GROUP_PR0                                                                      0x128071cUL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 0. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
68172 #define UCM_REG_XX_IA_GROUP_PR1                                                                      0x1280720UL //Access:RW   DataWidth:0x1   Xx Input Arbiter group client corresponding to group priority 1. 0 - non-lock group; 1- lock group.  Chips: BB_A0 BB_B0 K2
68173 #define UCM_REG_XX_NON_LOCK_LCID_THR                                                                 0x1280724UL //Access:RW   DataWidth:0x5   Xx non-locked LCIDs threshold (maximum value). Participates in blocking decision of Xx Input Arbiter non-locked group.  Chips: BB_A0 BB_B0 K2
68174 #define UCM_REG_XX_LOCK_LCID_THR                                                                     0x1280728UL //Access:RW   DataWidth:0x5   Xx locked LCIDs threshold (maximum value). Participates in Xx Bypass global enable decision.  Chips: BB_A0 BB_B0 K2
68175 #define UCM_REG_XX_IA_ARB_SP_TIMEOUT                                                                 0x128072cUL //Access:RW   DataWidth:0x8   Xx Input Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
68176 #define UCM_REG_XX_FREE_HEAD_PTR                                                                     0x1280730UL //Access:R    DataWidth:0x6   Xx Free Head Pointer.  Chips: BB_A0 BB_B0 K2
68177 #define UCM_REG_XX_FREE_TAIL_PTR                                                                     0x1280734UL //Access:R    DataWidth:0x6   Xx Free Tail Pointer. Written on CM_REGISTERS_XX_MSG_UP_BND.XX_MSG_UP_BND  Chips: BB_A0 BB_B0 K2
68178 #define UCM_REG_XX_NON_LOCK_CNT                                                                      0x1280738UL //Access:R    DataWidth:0x5   Xx NonLock Counter.  Chips: BB_A0 BB_B0 K2
68179 #define UCM_REG_XX_LOCK_CNT                                                                          0x128073cUL //Access:R    DataWidth:0x5   Xx Lock Counter.  Chips: BB_A0 BB_B0 K2
68180 #define UCM_REG_XX_LCID_ARB_GROUP_PR0                                                                0x1280740UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 0. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
68181 #define UCM_REG_XX_LCID_ARB_GROUP_PR1                                                                0x1280744UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 1. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
68182 #define UCM_REG_XX_LCID_ARB_GROUP_PR2                                                                0x1280748UL //Access:RW   DataWidth:0x2   Xx LCID Arbiter group client corresponding to group priority 2. 0 - Xx Dir group; 1- Xx AggSt group; 2- Xx Byp group.  Chips: BB_A0 BB_B0 K2
68183 #define UCM_REG_XX_LCID_ARB_SP_TIMEOUT                                                               0x128074cUL //Access:RW   DataWidth:0x8   Xx LCID Arbiter timeout value to perform non-usual arbitration operation relative to usual once in a while. Bit [7]: if 0 - usual operation is strict priority arbitration; if 1 - usual operation is RR. Bits [6:0] - period of non-usual operation performance. E.g. bits[6:0]=0; bit[7]=0 - always strict priority; bits[6:0]=1; bit[7]=0 - strict priority; then RR; bits[6:0]=3; bit[7]=0 - 3 times strict priority; then RR.  Chips: BB_A0 BB_B0 K2
68184 #define UCM_REG_XX_FREE_THR_HIGH                                                                     0x1280750UL //Access:RW   DataWidth:0x7   Xx free messages threshold high. Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
68185 #define UCM_REG_XX_FREE_THR_LOW                                                                      0x1280754UL //Access:RW   DataWidth:0x7   Xx free messages threshold low Used in Xx Bypass global enable condition.  Chips: BB_A0 BB_B0 K2
68186 #define UCM_REG_XX_CBYP_TBL_FILL_LVL                                                                 0x1280758UL //Access:R    DataWidth:0x4   Xx Connection Bypass Table fill level (in connections).  Chips: BB_A0 BB_B0 K2
68187 #define UCM_REG_XX_CBYP_TBL_ST_STAT                                                                  0x128075cUL //Access:RC   DataWidth:0x4   Xx Connection Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
68188 #define UCM_REG_XX_CBYP_TBL_UP_BND                                                                   0x1280760UL //Access:RW   DataWidth:0x4   Xx Bypass Table (Connection) maximum fill level.  Chips: BB_A0 BB_B0 K2
68189 #define UCM_REG_XX_TBYP_TBL_FILL_LVL                                                                 0x1280764UL //Access:R    DataWidth:0x5   Xx Task Bypass Table fill level (in tasks).  Chips: BB_A0 BB_B0 K2
68190 #define UCM_REG_XX_TBYP_TBL_ST_STAT                                                                  0x1280768UL //Access:RC   DataWidth:0x5   Xx Task Bypass Table sticky status. Reset on read.  Chips: BB_A0 BB_B0 K2
68191 #define UCM_REG_XX_TBYP_TBL_UP_BND                                                                   0x128076cUL //Access:RW   DataWidth:0x5   Xx Bypass Table (Task) maximum fill level.  Chips: BB_A0 BB_B0 K2
68192 #define UCM_REG_XX_BYP_MSG_UP_BND_0                                                                  0x1280770UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
68193 #define UCM_REG_XX_BYP_MSG_UP_BND_1                                                                  0x1280774UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
68194 #define UCM_REG_XX_BYP_MSG_UP_BND_2                                                                  0x1280778UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
68195 #define UCM_REG_XX_BYP_MSG_UP_BND_3                                                                  0x128077cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
68196 #define UCM_REG_XX_BYP_MSG_UP_BND_4                                                                  0x1280780UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
68197 #define UCM_REG_XX_BYP_MSG_UP_BND_5                                                                  0x1280784UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
68198 #define UCM_REG_XX_BYP_MSG_UP_BND_6                                                                  0x1280788UL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
68199 #define UCM_REG_XX_BYP_MSG_UP_BND_7                                                                  0x128078cUL //Access:RW   DataWidth:0x5   Xx Bypass messages upper bound (per connection) - used to restrict number of messages locked in Xx Bypass per LCID.  Chips: BB_A0 BB_B0 K2
68200 #define UCM_REG_XX_BYP_LOCK_MSG_THR                                                                  0x1280790UL //Access:RW   DataWidth:0x6   Xx Bypass messages lock threshold. The number of locked messages per LCID is above this threshold is one of conditions to start XxBypass for this LCID.  Chips: BB_A0 BB_B0 K2
68201 #define UCM_REG_XX_PREF_DIR_FILL_LVL                                                                 0x1280794UL //Access:R    DataWidth:0x6   Xx LCID Arbiter direct prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
68202 #define UCM_REG_XX_PREF_AGGST_FILL_LVL                                                               0x1280798UL //Access:R    DataWidth:0x6   Xx LCID Arbiter aggregation store prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
68203 #define UCM_REG_XX_PREF_BYP_FILL_LVL                                                                 0x128079cUL //Access:R    DataWidth:0x6   Xx LCID Arbiter bypass prefetch FIFO fill level (in REGQ).  Chips: BB_A0 BB_B0 K2
68204 #define UCM_REG_UNLOCK_MISS                                                                          0x12807a0UL //Access:RC   DataWidth:0x1   Set when the error; indicating the LCID to be unlocked doesn't exist in LCID CAM.  Chips: BB_A0 BB_B0 K2
68205 #define UCM_REG_PRCS_AGG_CON_CURR_ST                                                                 0x1280804UL //Access:R    DataWidth:0x4   Aggregation Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
68206 #define UCM_REG_PRCS_SM_CON_CURR_ST                                                                  0x1280808UL //Access:R    DataWidth:0x2   STORM Connection Processor FSM.  Chips: BB_A0 BB_B0 K2
68207 #define UCM_REG_PRCS_AGG_TASK_CURR_ST                                                                0x128080cUL //Access:R    DataWidth:0x4   Aggregation Task Processor FSM.  Chips: BB_A0 BB_B0 K2
68208 #define UCM_REG_PRCS_SM_TASK_CURR_ST                                                                 0x1280810UL //Access:R    DataWidth:0x2   STORM Task Processor FSM.  Chips: BB_A0 BB_B0 K2
68209 #define UCM_REG_N_SM_CON_CTX_LD_0                                                                    0x1280814UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68210 #define UCM_REG_N_SM_CON_CTX_LD_1                                                                    0x1280818UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68211 #define UCM_REG_N_SM_CON_CTX_LD_2                                                                    0x128081cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68212 #define UCM_REG_N_SM_CON_CTX_LD_3                                                                    0x1280820UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68213 #define UCM_REG_N_SM_CON_CTX_LD_4                                                                    0x1280824UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68214 #define UCM_REG_N_SM_CON_CTX_LD_5                                                                    0x1280828UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68215 #define UCM_REG_N_SM_CON_CTX_LD_6                                                                    0x128082cUL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68216 #define UCM_REG_N_SM_CON_CTX_LD_7                                                                    0x1280830UL //Access:RW   DataWidth:0x5   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68217 #define UCM_REG_N_SM_TASK_CTX_LD_0                                                                   0x1280834UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68218 #define UCM_REG_N_SM_TASK_CTX_LD_1                                                                   0x1280838UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68219 #define UCM_REG_N_SM_TASK_CTX_LD_2                                                                   0x128083cUL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68220 #define UCM_REG_N_SM_TASK_CTX_LD_3                                                                   0x1280840UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68221 #define UCM_REG_N_SM_TASK_CTX_LD_4                                                                   0x1280844UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68222 #define UCM_REG_N_SM_TASK_CTX_LD_5                                                                   0x1280848UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68223 #define UCM_REG_N_SM_TASK_CTX_LD_6                                                                   0x128084cUL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68224 #define UCM_REG_N_SM_TASK_CTX_LD_7                                                                   0x1280850UL //Access:RW   DataWidth:0x4   The number of REGQ; loaded from the STORM context and sent to STORM; for a specific connection type. The offset of these data in the STORM context is always 0. Index _i stands for the connection type (one of 8).  Chips: BB_A0 BB_B0 K2
68225 #define UCM_REG_AGG_CON_FIC_BUF_FILL_LVL                                                             0x1280854UL //Access:R    DataWidth:0x2   Aggregation Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
68226 #define UCM_REG_SM_CON_FIC_BUF_FILL_LVL                                                              0x1280858UL //Access:R    DataWidth:0x5   Storm Connection FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
68227 #define UCM_REG_AGG_CON_FIC_BUF_CRD                                                                  0x128085cUL //Access:RW   DataWidth:0x2   Aggregation Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
68228 #define UCM_REG_SM_CON_FIC_BUF_CRD                                                                   0x1280860UL //Access:RW   DataWidth:0x2   Storm Connection FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
68229 #define UCM_REG_AGG_CON_BUF_CRD_AGG                                                                  0x1280864UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
68230 #define UCM_REG_AGG_CON_BUF_CRD_AGGST                                                                0x1280868UL //Access:RW   DataWidth:0x3   Aggregation Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG need be no more than Agregation Connection data buffer size=4. In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and CM_REGISTERS_AGG_CON_CMD_BUF_CRD_DIR.AGG_CON_CMD_BUF_CRD_DIR need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
68231 #define UCM_REG_SM_CON_BUF_CRD_AGGST                                                                 0x128086cUL //Access:RW   DataWidth:0x1   Storm Connection buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_CON_CMD_BUF_CRD_DIR.SM_CON_CMD_BUF_CRD_DIR need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
68232 #define UCM_REG_AGG_CON_CMD_BUF_CRD_DIR                                                              0x1280870UL //Access:RW   DataWidth:0x2   Aggregation Connection command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_CON_BUF_CRD_AGG.AGG_CON_BUF_CRD_AGG and XCM_REGISTERS_AGG_CON_BUF_CRD_AGGST.AGG_CON_BUF_CRD_AGGST need be no more than Agregation Connection command buffer size=6.  Chips: BB_A0 BB_B0 K2
68233 #define UCM_REG_SM_CON_CMD_BUF_CRD_DIR                                                               0x1280874UL //Access:RW   DataWidth:0x2   Storm Connection command buffer credit (Direct group). In sum with CM_REGISTERS_SM_CON_BUF_CRD_AGGST.SM_CON_BUF_CRD_AGGST need be no more than Storm Connection command buffer size=3.  Chips: BB_A0 BB_B0 K2
68234 #define UCM_REG_AGG_TASK_FIC_BUF_FILL_LVL                                                            0x1280878UL //Access:R    DataWidth:0x2   Aggregation Task FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
68235 #define UCM_REG_SM_TASK_FIC_BUF_FILL_LVL                                                             0x128087cUL //Access:R    DataWidth:0x4   Storm Task FIC buffer fill level (in messages).  Chips: BB_A0 BB_B0 K2
68236 #define UCM_REG_AGG_TASK_FIC_BUF_CRD                                                                 0x1280880UL //Access:RW   DataWidth:0x2   Aggregation Task FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
68237 #define UCM_REG_SM_TASK_FIC_BUF_CRD                                                                  0x1280884UL //Access:RW   DataWidth:0x2   Storm Task FIC buffer credit (in full message out parts).  Chips: BB_A0 BB_B0 K2
68238 #define UCM_REG_AGG_TASK_BUF_CRD_AGG                                                                 0x1280888UL //Access:RW   DataWidth:0x3   Aggregation Task buffer (data or command) credit (Aggregation group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
68239 #define UCM_REG_AGG_TASK_BUF_CRD_AGGST                                                               0x128088cUL //Access:RW   DataWidth:0x3   Aggregation Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG need be no more than Agregation Task data buffer size=4. In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_CMD_BUF_CRD_DIR.AGG_TASK_CMD_BUF_CRD_DIR need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
68240 #define UCM_REG_SM_TASK_BUF_CRD_AGGST                                                                0x1280890UL //Access:RW   DataWidth:0x1   Storm Task buffer (data or command) credit (Aggregation Store group). In sum with CM_REGISTERS_SM_TASK_CMD_BUF_CRD_DIR.SM_TASK_CMD_BUF_CRD_DIR need be no more than Storm Task command buffer size=3.  Chips: BB_A0 BB_B0 K2
68241 #define UCM_REG_AGG_TASK_CMD_BUF_CRD_DIR                                                             0x1280894UL //Access:RW   DataWidth:0x2   Aggregation Task command buffer credit (Direct group). In sum with CM_REGISTERS_AGG_TASK_BUF_CRD_AGG.AGG_TASK_BUF_CRD_AGG and CM_REGISTERS_AGG_TASK_BUF_CRD_AGGST.AGG_TASK_BUF_CRD_AGGST need be no more than Agregation Task command buffer size=6.  Chips: BB_A0 BB_B0 K2
68242 #define UCM_REG_SM_TASK_CMD_BUF_CRD_DIR                                                              0x1280898UL //Access:RW   DataWidth:0x2   Storm Task command buffer credit (Direct group). In sum with CM_REGISTERS_SM_TASK_BUF_CRD_AGGST.SM_TASK_BUF_CRD_AGGST need be no more than Storm Task command buffer size=3.  Chips: BB_A0 BB_B0 K2
68243 #define UCM_REG_TRANS_DATA_BUF_CRD_DIR                                                               0x128089cUL //Access:RW   DataWidth:0x2   Transparent data buffer credit (Direct group).  Chips: BB_A0 BB_B0 K2
68244 #define UCM_REG_AGG_CON_CTX_SIZE_0                                                                   0x12808a0UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less or 2.  Chips: BB_A0 BB_B0 K2
68245 #define UCM_REG_AGG_CON_CTX_SIZE_1                                                                   0x12808a4UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
68246 #define UCM_REG_AGG_CON_CTX_SIZE_2                                                                   0x12808a8UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
68247 #define UCM_REG_AGG_CON_CTX_SIZE_3                                                                   0x12808acUL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
68248 #define UCM_REG_AGG_CON_CTX_SIZE_4                                                                   0x12808b0UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
68249 #define UCM_REG_AGG_CON_CTX_SIZE_5                                                                   0x12808b4UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
68250 #define UCM_REG_AGG_CON_CTX_SIZE_6                                                                   0x12808b8UL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
68251 #define UCM_REG_AGG_CON_CTX_SIZE_7                                                                   0x12808bcUL //Access:RW   DataWidth:0x2   Agggregation connection context size to be read/written back per connection type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 2. The register values allowed: XCM: 4 REGQ aligned or 2. Other CM: 2 REGQ aligned or 2 aligned whichever is less, or 2.  Chips: BB_A0 BB_B0 K2
68252 #define UCM_REG_AGG_TASK_CTX_SIZE_0                                                                  0x12808c0UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
68253 #define UCM_REG_AGG_TASK_CTX_SIZE_1                                                                  0x12808c4UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
68254 #define UCM_REG_AGG_TASK_CTX_SIZE_2                                                                  0x12808c8UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
68255 #define UCM_REG_AGG_TASK_CTX_SIZE_3                                                                  0x12808ccUL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
68256 #define UCM_REG_AGG_TASK_CTX_SIZE_4                                                                  0x12808d0UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
68257 #define UCM_REG_AGG_TASK_CTX_SIZE_5                                                                  0x12808d4UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
68258 #define UCM_REG_AGG_TASK_CTX_SIZE_6                                                                  0x12808d8UL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
68259 #define UCM_REG_AGG_TASK_CTX_SIZE_7                                                                  0x12808dcUL //Access:RW   DataWidth:0x2   Agggregation task context size to be read/written back per task type (measured in REGQ). Minimum context size per LCID is 1. Maximum context size per LCID is 3. The register values allowed: 2 REGQ aligned or 3 aligned whichever is less, or 3.  Chips: BB_A0 BB_B0 K2
68260 #define UCM_REG_SM_CON_CTX_SIZE                                                                      0x12808e0UL //Access:RW   DataWidth:0x5   STORM Connnection context per LCID size (REGQ). Default context size of 13 (REGQ) complies to 320 LCIDs. Maximum context size per LCID is 24. Maximum number of LCIDs allowed at maximum context size per LCID is 160. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LCIDs allowed at non-default size: INTEGER((320*INTEGER(13/2))/(24/2)).  Chips: BB_A0 BB_B0 K2
68261 #define UCM_REG_SM_TASK_CTX_SIZE                                                                     0x12808e4UL //Access:RW   DataWidth:0x4   STORM Task context per LTID size (REGQ). Default context size of 3 (REGQ) complies to 320 LTIDs. Maximum context size per LTID is 12. Maximum number of LTIDs allowed at maximum context size per LTID is 52. If not at default value need to be 2 REGQ (256b) aligned. To calculate maximum number of LTIDs allowed at non-default size: INTEGER((320*INTEGER(3/2))/(12/2)).  Chips: BB_A0 BB_B0 K2
68262 #define UCM_REG_CON_PHY_Q0                                                                           0x1280904UL //Access:RW   DataWidth:0x9   Physical queue connection number (queue number 0).  Chips: BB_A0 BB_B0 K2
68263 #define UCM_REG_CON_PHY_Q1                                                                           0x1280908UL //Access:RW   DataWidth:0x9   Physical queue connection number (queue number 1).  Chips: BB_A0 BB_B0 K2
68264 #define UCM_REG_TASK_PHY_Q0                                                                          0x128090cUL //Access:RW   DataWidth:0x7   Physical queue task number (queue number 0).  Chips: BB_A0 BB_B0 K2
68265 #define UCM_REG_TASK_PHY_Q1                                                                          0x1280910UL //Access:RW   DataWidth:0x7   Physical queue task number (queue number 1).  Chips: BB_A0 BB_B0 K2
68266 #define UCM_REG_AGG_CON_CF0_Q                                                                        0x1280914UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68267 #define UCM_REG_AGG_CON_CF1_Q                                                                        0x1280918UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68268 #define UCM_REG_AGG_CON_CF2_Q                                                                        0x128091cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68269 #define UCM_REG_AGG_CON_CF3_Q                                                                        0x1280920UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68270 #define UCM_REG_AGG_CON_CF4_Q                                                                        0x1280924UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68271 #define UCM_REG_AGG_CON_CF5_Q                                                                        0x1280928UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68272 #define UCM_REG_AGG_CON_CF6_Q                                                                        0x128092cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68273 #define UCM_REG_AGG_CON_RULE0_Q                                                                      0x1280930UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68274 #define UCM_REG_AGG_CON_RULE1_Q                                                                      0x1280934UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68275 #define UCM_REG_AGG_CON_RULE2_Q                                                                      0x1280938UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68276 #define UCM_REG_AGG_CON_RULE3_Q                                                                      0x128093cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68277 #define UCM_REG_AGG_CON_RULE4_Q                                                                      0x1280940UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68278 #define UCM_REG_AGG_CON_RULE5_Q                                                                      0x1280944UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).:  Chips: BB_A0 BB_B0 K2
68279 #define UCM_REG_AGG_CON_RULE6_Q                                                                      0x1280948UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68280 #define UCM_REG_AGG_CON_RULE7_Q                                                                      0x128094cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68281 #define UCM_REG_AGG_CON_RULE8_Q                                                                      0x1280950UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68282 #define UCM_REG_AGG_TASK_CF0_Q                                                                       0x1280954UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68283 #define UCM_REG_AGG_TASK_CF1_Q                                                                       0x1280958UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68284 #define UCM_REG_AGG_TASK_CF2_Q                                                                       0x128095cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68285 #define UCM_REG_AGG_TASK_CF3_Q                                                                       0x1280960UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68286 #define UCM_REG_AGG_TASK_CF4_Q                                                                       0x1280964UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68287 #define UCM_REG_AGG_TASK_RULE0_Q                                                                     0x1280968UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68288 #define UCM_REG_AGG_TASK_RULE1_Q                                                                     0x128096cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68289 #define UCM_REG_AGG_TASK_RULE2_Q                                                                     0x1280970UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68290 #define UCM_REG_AGG_TASK_RULE3_Q                                                                     0x1280974UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68291 #define UCM_REG_AGG_TASK_RULE4_Q                                                                     0x1280978UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68292 #define UCM_REG_AGG_TASK_RULE5_Q                                                                     0x128097cUL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68293 #define UCM_REG_AGG_TASK_RULE6_Q                                                                     0x1280980UL //Access:RW   DataWidth:0x2   Decision rule logical queue (0 - Queue index 0 enable; 1- Queue index enable; 2 - Queue index 2 enable; 3 - Queue index enable).  Chips: BB_A0 BB_B0 K2
68294 #define UCM_REG_IN_PRCS_TBL_CRD_AGG                                                                  0x1280a04UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGGST.IN_PRCS_TBL_CRD_AGGST need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
68295 #define UCM_REG_IN_PRCS_TBL_CRD_AGGST                                                                0x1280a08UL //Access:RW   DataWidth:0x4   In-process table credit (Aggregation Store group). In sum with CM_REGISTERS_IN_PRCS_TBL_CRD_AGG.IN_PRCS_TBL_CRD_AGG need be no more than In-process table size=12.  Chips: BB_A0 BB_B0 K2
68296 #define UCM_REG_IN_PRCS_TBL_FILL_LVL                                                                 0x1280a0cUL //Access:R    DataWidth:0x4   In-process Table fill level  (in messages).  Chips: BB_A0 BB_B0 K2
68297 #define UCM_REG_IN_PRCS_TBL_ALMOST_FULL                                                              0x1280a10UL //Access:R    DataWidth:0x1   In-process Table almost full.  Chips: BB_A0 BB_B0 K2
68298 #define UCM_REG_QMCON_CURR_ST                                                                        0x1280a14UL //Access:R    DataWidth:0x3   QM connection registration FSM current state.  Chips: BB_A0 BB_B0 K2
68299 #define UCM_REG_QMTASK_CURR_ST                                                                       0x1280a18UL //Access:R    DataWidth:0x3   QM task registration FSM current state.  Chips: BB_A0 BB_B0 K2
68300 #define UCM_REG_TMCON_CURR_ST                                                                        0x1280a1cUL //Access:R    DataWidth:0x1   TM connection output FSM current state.  Chips: BB_A0 BB_B0 K2
68301 #define UCM_REG_TMTASK_CURR_ST                                                                       0x1280a20UL //Access:R    DataWidth:0x1   TM task output FSM current state.  Chips: BB_A0 BB_B0 K2
68302 #define UCM_REG_CCFC_CURR_ST                                                                         0x1280a24UL //Access:R    DataWidth:0x1   CFC connection output FSM current state.  Chips: BB_A0 BB_B0 K2
68303 #define UCM_REG_TCFC_CURR_ST                                                                         0x1280a28UL //Access:R    DataWidth:0x1   CFC task output FSM current state.  Chips: BB_A0 BB_B0 K2
68304 #define UCM_REG_CMPL_DIR_CURR_ST                                                                     0x1280a2cUL //Access:R    DataWidth:0x4   Direct Completer FSM current state.  Chips: BB_A0 BB_B0 K2
68305 #define UCM_REG_XX_BYP_CON_STATE_EVNT_ID_FLG                                                         0x1280a30UL //Access:RW   DataWidth:0x1   If set, Xx connection bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
68306 #define UCM_REG_XX_BYP_TASK_STATE_EVNT_ID_FLG                                                        0x1280a34UL //Access:RW   DataWidth:0x1   If set, Xx task bypass state will be added in calculation of CM output Event ID.  Chips: BB_A0 BB_B0 K2
68307 #define UCM_REG_CCFC_INIT_CRD                                                                        0x1280a84UL //Access:RW   DataWidth:0x4   CCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
68308 #define UCM_REG_TCFC_INIT_CRD                                                                        0x1280a88UL //Access:RW   DataWidth:0x4   TCFC output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
68309 #define UCM_REG_QM_INIT_CRD0                                                                         0x1280a8cUL //Access:RW   DataWidth:0x5   QM output initial credit (all CMS except of XCM and XCM - other queues). Max credit available - 16.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
68310 #define UCM_REG_TM_INIT_CRD                                                                          0x1280a90UL //Access:RW   DataWidth:0x4   Timers output initial credit. Max credit available - 15.Write writes the initial credit value; read returns the current value of the credit counter.  Chips: BB_A0 BB_B0 K2
68311 #define UCM_REG_FIC_INIT_CRD                                                                         0x1280a94UL //Access:RW   DataWidth:0x6   FIC output initial credit. Write writes the initial credit value; read returns the current value of the credit counter. Must be initialized to 44 at start-up.  Chips: BB_A0 BB_B0 K2
68312 #define UCM_REG_DIR_BYP_MSG_CNT                                                                      0x1280aa4UL //Access:RC   DataWidth:0x20  Counter of direct bypassed messages.  Chips: BB_A0 BB_B0 K2
68313 #define UCM_REG_XSDM_LENGTH_MIS                                                                      0x1280aa8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at XSDM interface.  Chips: BB_A0 BB_B0 K2
68314 #define UCM_REG_YSDM_LENGTH_MIS                                                                      0x1280aacUL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at YSDM interface.  Chips: BB_A0 BB_B0 K2
68315 #define UCM_REG_USDM_LENGTH_MIS                                                                      0x1280ab0UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at USDM interface.  Chips: BB_A0 BB_B0 K2
68316 #define UCM_REG_DORQ_LENGTH_MIS                                                                      0x1280ab4UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at the dorq interface.  Chips: BB_A0 BB_B0 K2
68317 #define UCM_REG_PBF_LENGTH_MIS                                                                       0x1280ab8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at PBF interface.  Chips: BB_A0 BB_B0 K2
68318 #define UCM_REG_RDIF_LENGTH_MIS                                                                      0x1280abcUL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at RDIF interface.  Chips: BB_A0 BB_B0 K2
68319 #define UCM_REG_TDIF_LENGTH_MIS                                                                      0x1280ac0UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at TDIF interface.  Chips: BB_A0 BB_B0 K2
68320 #define UCM_REG_MULD_LENGTH_MIS                                                                      0x1280ac4UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at MULD interface.  Chips: BB_A0 BB_B0 K2
68321 #define UCM_REG_YULD_LENGTH_MIS                                                                      0x1280ac8UL //Access:RC   DataWidth:0x1   Set at message length mismatch (relative to last indication) at YULD interface.  Chips: BB_A0 BB_B0 K2
68322 #define UCM_REG_GRC_BUF_EMPTY                                                                        0x1280accUL //Access:R    DataWidth:0x1   Input Stage GRC buffer is empty.  Chips: BB_A0 BB_B0 K2
68323 #define UCM_REG_GRC_BUF_STATUS                                                                       0x1280ad0UL //Access:R    DataWidth:0x6   Input Stage GRC buffer status.  Chips: BB_A0 BB_B0 K2
68324 #define UCM_REG_STORM_MSG_CNTR                                                                       0x1280ad4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the STORM input.  Chips: BB_A0 BB_B0 K2
68325 #define UCM_REG_XSDM_MSG_CNTR                                                                        0x1280ad8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input XSDM.  Chips: BB_A0 BB_B0 K2
68326 #define UCM_REG_YSDM_MSG_CNTR                                                                        0x1280adcUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input YSDM.  Chips: BB_A0 BB_B0 K2
68327 #define UCM_REG_USDM_MSG_CNTR                                                                        0x1280ae0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input USDM.  Chips: BB_A0 BB_B0 K2
68328 #define UCM_REG_RDIF_MSG_CNTR                                                                        0x1280ae4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input RDIF.  Chips: BB_A0 BB_B0 K2
68329 #define UCM_REG_TDIF_MSG_CNTR                                                                        0x1280ae8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input TDIF.  Chips: BB_A0 BB_B0 K2
68330 #define UCM_REG_MULD_MSG_CNTR                                                                        0x1280aecUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input MULD.  Chips: BB_A0 BB_B0 K2
68331 #define UCM_REG_YULD_MSG_CNTR                                                                        0x1280af0UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the input YULD.  Chips: BB_A0 BB_B0 K2
68332 #define UCM_REG_DORQ_MSG_CNTR                                                                        0x1280af4UL //Access:RC   DataWidth:0x1c  Counter of the input messages at  input DORQ.  Chips: BB_A0 BB_B0 K2
68333 #define UCM_REG_PBF_MSG_CNTR                                                                         0x1280af8UL //Access:RC   DataWidth:0x1c  Counter of the input messages at input PBF.  Chips: BB_A0 BB_B0 K2
68334 #define UCM_REG_QM_P_MSG_CNTR                                                                        0x1280afcUL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (primary).  Chips: BB_A0 BB_B0 K2
68335 #define UCM_REG_QM_S_MSG_CNTR                                                                        0x1280b00UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the QM input (secondary).  Chips: BB_A0 BB_B0 K2
68336 #define UCM_REG_TM_MSG_CNTR                                                                          0x1280b04UL //Access:RC   DataWidth:0x1c  Counter of the input messages at the Timers input.  Chips: BB_A0 BB_B0 K2
68337 #define UCM_REG_IS_GRC                                                                               0x1280b08UL //Access:W    DataWidth:0x20  Used to write the GRC message. Write only. To distinguish if the register can be accessed to write GRC message                           polling of CM_REGISTERS.GRC_BUF_EMPTY need to be done  Chips: BB_A0 BB_B0 K2
68338 #define UCM_REG_IS_QM_P_FILL_LVL                                                                     0x1280b0cUL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in QM Primary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
68339 #define UCM_REG_IS_QM_S_FILL_LVL                                                                     0x1280b10UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in QM Secondary Input Stage (except of bypass).  Chips: BB_A0 BB_B0 K2
68340 #define UCM_REG_IS_TM_FILL_LVL                                                                       0x1280b14UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in TM Input Stage.  Chips: BB_A0 BB_B0 K2
68341 #define UCM_REG_IS_STORM_FILL_LVL                                                                    0x1280b18UL //Access:R    DataWidth:0x6   Number of QREGs (128b) of data in STORM Input Stage.  Chips: BB_A0 BB_B0 K2
68342 #define UCM_REG_IS_XSDM_FILL_LVL                                                                     0x1280b1cUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in XSDM Input Stage.  Chips: BB_A0 BB_B0 K2
68343 #define UCM_REG_IS_YSDM_FILL_LVL                                                                     0x1280b20UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in YSDM Input Stage.  Chips: BB_A0 BB_B0 K2
68344 #define UCM_REG_IS_USDM_FILL_LVL                                                                     0x1280b24UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in USDM Input Stage.  Chips: BB_A0 BB_B0 K2
68345 #define UCM_REG_IS_RDIF_FILL_LVL                                                                     0x1280b28UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in RDIF Input Stage.  Chips: BB_A0 BB_B0 K2
68346 #define UCM_REG_IS_TDIF_FILL_LVL                                                                     0x1280b2cUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in TDIF Input Stage.  Chips: BB_A0 BB_B0 K2
68347 #define UCM_REG_IS_MULD_FILL_LVL                                                                     0x1280b30UL //Access:R    DataWidth:0x5   Number of QREGs (128b) of data in MULD Input Stage.  Chips: BB_A0 BB_B0 K2
68348 #define UCM_REG_IS_YULD_FILL_LVL                                                                     0x1280b34UL //Access:R    DataWidth:0x4   Number of QREGs (128b) of data in YULD Input Stage.  Chips: BB_A0 BB_B0 K2
68349 #define UCM_REG_IS_DORQ_FILL_LVL                                                                     0x1280b38UL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in DORQ Input Stage.  Chips: BB_A0 BB_B0 K2
68350 #define UCM_REG_IS_PBF_FILL_LVL                                                                      0x1280b3cUL //Access:R    DataWidth:0x3   Number of QREGs (128b) of data in PBF Input Stage.  Chips: BB_A0 BB_B0 K2
68351 #define UCM_REG_FIC_MSG_CNTR                                                                         0x1280b44UL //Access:RC   DataWidth:0x1c  Counter of the output messages at FIC interfaces.  Chips: BB_A0 BB_B0 K2
68352 #define UCM_REG_QM_OUT_CNTR                                                                          0x1280b48UL //Access:RC   DataWidth:0x1c  Counter of the output QM commands.  Chips: BB_A0 BB_B0 K2
68353 #define UCM_REG_TM_OUT_CNTR                                                                          0x1280b4cUL //Access:RC   DataWidth:0x1c  Counter of the output Timers commands.  Chips: BB_A0 BB_B0 K2
68354 #define UCM_REG_DONE0_CNTR                                                                           0x1280b50UL //Access:RC   DataWidth:0x1c  Counter of the output Done0.  Chips: BB_A0 BB_B0 K2
68355 #define UCM_REG_DONE1_CNTR                                                                           0x1280b54UL //Access:RC   DataWidth:0x1c  Counter of the output Done1.  Chips: BB_A0 BB_B0 K2
68356 #define UCM_REG_DONE2_CNTR                                                                           0x1280b58UL //Access:RC   DataWidth:0x1c  Counter of the output Done2.  Chips: BB_A0 BB_B0 K2
68357 #define UCM_REG_DONE3_CNTR                                                                           0x1280b5cUL //Access:RC   DataWidth:0x1c  Counter of the output Done3.  Chips: BB_A0 BB_B0 K2
68358 #define UCM_REG_CCFC_CNTR                                                                            0x1280b60UL //Access:RC   DataWidth:0x1c  Counter of the output CCFC.  Chips: BB_A0 BB_B0 K2
68359 #define UCM_REG_TCFC_CNTR                                                                            0x1280b64UL //Access:RC   DataWidth:0x1c  Counter of the output TCFC.  Chips: BB_A0 BB_B0 K2
68360 #define UCM_REG_ECO_RESERVED                                                                         0x1280b84UL //Access:RW   DataWidth:0x8   Chicken bits.  Chips: BB_A0 BB_B0 K2
68361 #define UCM_REG_IS_FOC_USEM_NXT_INF_UNIT                                                             0x1280b88UL //Access:R    DataWidth:0x6   Debug read from USEM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68362 #define UCM_REG_IS_FOC_PBF_NXT_INF_UNIT                                                              0x1280b8cUL //Access:R    DataWidth:0x6   Debug read from PBF Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68363 #define UCM_REG_IS_FOC_DORQ_NXT_INF_UNIT                                                             0x1280b90UL //Access:R    DataWidth:0x6   Debug read from DORQ Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68364 #define UCM_REG_IS_FOC_RDIF_NXT_INF_UNIT                                                             0x1280b94UL //Access:R    DataWidth:0x6   Debug read from RDIF Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68365 #define UCM_REG_IS_FOC_TDIF_NXT_INF_UNIT                                                             0x1280b98UL //Access:R    DataWidth:0x6   Debug read from TDIF Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68366 #define UCM_REG_IS_FOC_USDM_NXT_INF_UNIT                                                             0x1280b9cUL //Access:R    DataWidth:0x6   Debug read from USDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68367 #define UCM_REG_IS_FOC_XSDM_NXT_INF_UNIT                                                             0x1280ba0UL //Access:R    DataWidth:0x6   Debug read from XSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68368 #define UCM_REG_IS_FOC_YSDM_NXT_INF_UNIT                                                             0x1280ba4UL //Access:R    DataWidth:0x6   Debug read from YSDM Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68369 #define UCM_REG_IS_FOC_MULD_NXT_INF_UNIT                                                             0x1280ba8UL //Access:R    DataWidth:0x6   Debug read from MULD Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68370 #define UCM_REG_IS_FOC_YULD_NXT_INF_UNIT                                                             0x1280bacUL //Access:R    DataWidth:0x6   Debug read from YULD Input stage buffer: number of reads to next information unit.  Chips: BB_A0 BB_B0 K2
68371 #define UCM_REG_IS_FOC_USEM                                                                          0x1280c00UL //Access:R    DataWidth:0x20  Debug read from USEM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68372 #define UCM_REG_IS_FOC_USEM_SIZE                                                                     204
68373 #define UCM_REG_IS_FOC_PBF                                                                           0x1281000UL //Access:R    DataWidth:0x20  Debug read from PBF Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68374 #define UCM_REG_IS_FOC_PBF_SIZE                                                                      28
68375 #define UCM_REG_IS_FOC_DORQ                                                                          0x1281080UL //Access:R    DataWidth:0x20  Debug read from DORQ Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68376 #define UCM_REG_IS_FOC_DORQ_SIZE                                                                     24
68377 #define UCM_REG_IS_FOC_RDIF                                                                          0x1281100UL //Access:R    DataWidth:0x20  Debug read from RDIF Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68378 #define UCM_REG_IS_FOC_RDIF_SIZE                                                                     12
68379 #define UCM_REG_IS_FOC_TDIF                                                                          0x1281140UL //Access:R    DataWidth:0x20  Debug read from TDIF Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68380 #define UCM_REG_IS_FOC_TDIF_SIZE                                                                     12
68381 #define UCM_REG_IS_FOC_USDM                                                                          0x1281200UL //Access:R    DataWidth:0x20  Debug read from USDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68382 #define UCM_REG_IS_FOC_USDM_SIZE                                                                     36
68383 #define UCM_REG_IS_FOC_XSDM                                                                          0x1281300UL //Access:R    DataWidth:0x20  Debug read from XSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68384 #define UCM_REG_IS_FOC_XSDM_SIZE                                                                     12
68385 #define UCM_REG_IS_FOC_YSDM                                                                          0x1281340UL //Access:R    DataWidth:0x20  Debug read from YSDM Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68386 #define UCM_REG_IS_FOC_YSDM_SIZE                                                                     12
68387 #define UCM_REG_IS_FOC_MULD                                                                          0x1281400UL //Access:R    DataWidth:0x20  Debug read from MULD Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68388 #define UCM_REG_IS_FOC_MULD_SIZE                                                                     124
68389 #define UCM_REG_IS_FOC_YULD                                                                          0x1281600UL //Access:R    DataWidth:0x20  Debug read from YULD Input stage buffer with 32-bits granularity. Read only.  Chips: BB_A0 BB_B0 K2
68390 #define UCM_REG_IS_FOC_YULD_SIZE                                                                     36
68391 #define UCM_REG_CTX_RBC_ACCS                                                                         0x1281700UL //Access:RW   DataWidth:0x10  Context RBC access.[8:0] - base address (LCID/LTID); [15:9] - offset (in REGs (32b)) within LCID/LTID. The procedure to read context is: first define base address and offset; then read context with one of the following registers: CM_REGISTERS_AGG_CON_CTX.AGG_CON_CTX CM_REGISTERS_SM_CON_CTX.SM_CON_CTX CM_REGISTERS_AGG_TASK_CTX.AGG_TASK_CTX CM_REGISTERS_SM_TASK_CTX.SM_TASK_CTX  Chips: BB_A0 BB_B0 K2
68392 #define UCM_REG_AGG_CON_CTX                                                                          0x1281704UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
68393 #define UCM_REG_AGG_TASK_CTX                                                                         0x1281708UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to Aggregation Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to Aggregation Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
68394 #define UCM_REG_SM_CON_CTX                                                                           0x128170cUL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Connection context with 32-bits granularity. The address base (LCID) and offset within LCID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Connection context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
68395 #define UCM_REG_SM_TASK_CTX                                                                          0x1281710UL //Access:RW   DataWidth:0x20  Access is allowed only on idle chip. Read: Indirect access to STORM Task context with 32-bits granularity. The address base (LTID) and offset within LTID need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS Write: Indirect access to STORM Task context to initialize the whole memory row to all 0s. The address base (LCID) need to be prior defined by CM_REGISTERS_CTX_RBC_ACCS.CTX_RBC_ACCS , offset within LCID should be 0.  Chips: BB_A0 BB_B0 K2
68396 #define UCM_REG_XX_CBYP_TBL                                                                          0x1281720UL //Access:R    DataWidth:0xf   Xx Connection Bypass Table.  Chips: BB_A0 BB_B0 K2
68397 #define UCM_REG_XX_CBYP_TBL_SIZE                                                                     8
68398 #define UCM_REG_XX_TBYP_TBL                                                                          0x1281800UL //Access:R    DataWidth:0xf   Xx Task Bypass Table.  Chips: BB_A0 BB_B0 K2
68399 #define UCM_REG_XX_TBYP_TBL_SIZE                                                                     24
68400 #define UCM_REG_XX_LCID_CAM                                                                          0x1281900UL //Access:R    DataWidth:0xa   Debug only. Read only access to LCID CAM in XX protection mechanism.  Chips: BB_A0 BB_B0 K2
68401 #define UCM_REG_XX_LCID_CAM_SIZE                                                                     24
68402 #define UCM_REG_XX_TBL                                                                               0x1281a00UL //Access:R    DataWidth:0x17  Indirect access to the XX table of the XX protection mechanism. The fields are: [0] - Lock status; [3:1] - Connection type; LL size: PCM - [6:4]; M/T/U/X/YCM - [10:4]; Tail pointer: PCM - [8:7]; M/T/U/X/YCM - [16:11]; Next pointer: PCM - [10:9]; M/T/U/X/YCM - [22:17];  Chips: BB_A0 BB_B0 K2
68403 #define UCM_REG_XX_TBL_SIZE                                                                          24
68404 #define UCM_REG_XX_DSCR_TBL                                                                          0x1281b00UL //Access:RW   DataWidth:0x1e  Indirect access to the XX table of the XX protection mechanism. The fields are: [2:0] - Xx Lock command;[3] - DstStormFlg; [8:4] - Global Client Input number; Message length (MCM [13:9];PCM [14:9]; TCM [13:9]; UCM [13:9];XCM [10:9];YCM[13:9]); Next pointer (MCM [19:14]; PCM [16:15]; TCM[19:14]; UCM [19:14]; XCM [16:11]; YCM [19:14]); LTID (MCM [28:20]; PCM [25:17] - reserved; TCM[28:20]; UCM [28:20]; XCM [25:17] - reserved; YCM [28:20]). Task Domain Exist (MCM [29]; PCM [26] - reserved;TCM[29]; UCM [29]; XCM [26] - reserved; YCM [29]). A free link list in the XX descriptor table should be build. This is done by writing the following values to all effective entries in the table:xx_descr_table[i].next_pointer = i+1 (i=0 - (xx_msg_up_bnd-2)); xx_descr_table[i].next_pointer= 0 (i=xx_msg_up_bnd-1). The value of i is between 0 to the configured (not default) value of (xx_msg_up_bnd-1). The not effective entries (those which succeed the last effective entry with index (xx_msg_up_bnd-1)) can be initialized to any value for initialization procedure simplicity seek.  Chips: BB_A0 BB_B0 K2
68405 #define UCM_REG_XX_DSCR_TBL_SIZE                                                                     64
68406 #define UCM_REG_XX_MSG_RAM                                                                           0x1288000UL //Access:R    DataWidth:0x20  Indirect access to the Xx messages RAM of the XX protection mechanism. Read-only.  Chips: BB_A0 BB_B0 K2
68407 #define UCM_REG_XX_MSG_RAM_SIZE                                                                      6656
68408 #define XSEM_REG_ENABLE_IN                                                                           0x1400004UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68409     #define XSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN                                                    (0x1<<0) // Full input from external IF to LS input enable.
68410     #define XSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_SHIFT                                              0
68411     #define XSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN                                                 (0x1<<1) // Read data from external LS IF input enable.
68412     #define XSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_SHIFT                                           1
68413     #define XSEM_REG_ENABLE_IN_FIC_ENABLE_IN                                                         (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
68414     #define XSEM_REG_ENABLE_IN_FIC_ENABLE_IN_SHIFT                                                   2
68415     #define XSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN                                                     (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
68416     #define XSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_SHIFT                                               3
68417     #define XSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN                                                     (0x1<<4) // General interface input enable.
68418     #define XSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_SHIFT                                               4
68419     #define XSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN                                                     (0x1<<5) // External passive write input enable.
68420     #define XSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_SHIFT                                               5
68421     #define XSEM_REG_ENABLE_IN_RAM_ENABLE_IN                                                         (0x1<<6) // Data input enable to RAM.
68422     #define XSEM_REG_ENABLE_IN_RAM_ENABLE_IN_SHIFT                                                   6
68423     #define XSEM_REG_ENABLE_IN_STALL_ENABLE_IN                                                       (0x1<<7) // Enable for stall input from all external STORM instances.
68424     #define XSEM_REG_ENABLE_IN_STALL_ENABLE_IN_SHIFT                                                 7
68425     #define XSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN                                                  (0x1<<8) // Thread ready bus input enable.
68426     #define XSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_SHIFT                                            8
68427     #define XSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN                                                  (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
68428     #define XSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_SHIFT                                            9
68429 #define XSEM_REG_ENABLE_OUT                                                                          0x1400008UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68430     #define XSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT                                                (0x1<<0) // Read request output enable from external LS IF.
68431     #define XSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_SHIFT                                          0
68432     #define XSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT                                                (0x1<<1) // Write request output enable from external LS IF.
68433     #define XSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_SHIFT                                          1
68434     #define XSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT                                                       (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
68435     #define XSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_SHIFT                                                 2
68436     #define XSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT                                                   (0x1<<3) // Passive full output enable.
68437     #define XSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_SHIFT                                             3
68438     #define XSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT                                                       (0x1<<4) // Data output enable to RAM.
68439     #define XSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_SHIFT                                                 4
68440     #define XSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT                                                     (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
68441     #define XSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_SHIFT                                               5
68442 #define XSEM_REG_FIC_DISABLE                                                                         0x140000cUL //Access:RW   DataWidth:0x1   Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
68443 #define XSEM_REG_PAS_DISABLE                                                                         0x1400010UL //Access:RW   DataWidth:0x1   Disables input messages from the passive buffer  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
68444 #define XSEM_REG_INT_STS_0                                                                           0x1400040UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
68445     #define XSEM_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
68446     #define XSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
68447     #define XSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                        (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
68448     #define XSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                  1
68449     #define XSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                      (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
68450     #define XSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                2
68451     #define XSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                        (0x1<<3) // Error in any one of the FIC FIFO is active.
68452     #define XSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                  3
68453     #define XSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
68454     #define XSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_SHIFT                                              4
68455     #define XSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
68456     #define XSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_SHIFT                                              5
68457     #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
68458     #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                          6
68459     #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
68460     #define XSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                           7
68461     #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
68462     #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                          8
68463     #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
68464     #define XSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                           9
68465     #define XSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
68466     #define XSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_SHIFT                                             10
68467     #define XSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
68468     #define XSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                          11
68469     #define XSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
68470     #define XSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_SHIFT                                                12
68471     #define XSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
68472     #define XSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_SHIFT                                                13
68473     #define XSEM_REG_INT_STS_0_CAM_OUT_FIFO                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
68474     #define XSEM_REG_INT_STS_0_CAM_OUT_FIFO_SHIFT                                                    14
68475     #define XSEM_REG_INT_STS_0_FIN_FIFO                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
68476     #define XSEM_REG_INT_STS_0_FIN_FIFO_SHIFT                                                        15
68477     #define XSEM_REG_INT_STS_0_THREAD_FIFO_ERROR                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
68478     #define XSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_SHIFT                                               16
68479     #define XSEM_REG_INT_STS_0_THREAD_OVERRUN                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
68480     #define XSEM_REG_INT_STS_0_THREAD_OVERRUN_SHIFT                                                  17
68481     #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR                                             (0x1<<18) // Error in external store sync FIFO push logic.
68482     #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                       18
68483     #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR                                              (0x1<<19) // Error in external store sync FIFO pop logic.
68484     #define XSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                        19
68485     #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR                                              (0x1<<20) // Error in external load sync FIFO push logic.
68486     #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                        20
68487     #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR                                               (0x1<<21) // Error in external load sync FIFO pop logic.
68488     #define XSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                         21
68489     #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
68490     #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                          22
68491     #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
68492     #define XSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                           23
68493     #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
68494     #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                           24
68495     #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
68496     #define XSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                          25
68497     #define XSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
68498     #define XSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_SHIFT                                             26
68499     #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
68500     #define XSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_SHIFT                                              27
68501     #define XSEM_REG_INT_STS_0_DBG_FIFO_ERROR                                                        (0x1<<28) // Error in slow debug fifo.
68502     #define XSEM_REG_INT_STS_0_DBG_FIFO_ERROR_SHIFT                                                  28
68503     #define XSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
68504     #define XSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_SHIFT                                               29
68505     #define XSEM_REG_INT_STS_0_VFC_INTERRUPT                                                         (0x1<<30) // Error interrupt in VFC block.
68506     #define XSEM_REG_INT_STS_0_VFC_INTERRUPT_SHIFT                                                   30
68507     #define XSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
68508     #define XSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_SHIFT                                              31
68509 #define XSEM_REG_INT_MASK_0                                                                          0x1400044UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
68510     #define XSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.ADDRESS_ERROR .
68511     #define XSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
68512     #define XSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_LAST_ERROR .
68513     #define XSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                 1
68514     #define XSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
68515     #define XSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                               2
68516     #define XSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
68517     #define XSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                 3
68518     #define XSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
68519     #define XSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_SHIFT                                             4
68520     #define XSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
68521     #define XSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_SHIFT                                             5
68522     #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
68523     #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                         6
68524     #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
68525     #define XSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                          7
68526     #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
68527     #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                         8
68528     #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
68529     #define XSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                          9
68530     #define XSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
68531     #define XSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_SHIFT                                            10
68532     #define XSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
68533     #define XSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                         11
68534     #define XSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
68535     #define XSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_SHIFT                                               12
68536     #define XSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
68537     #define XSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_SHIFT                                               13
68538     #define XSEM_REG_INT_MASK_0_CAM_OUT_FIFO                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_OUT_FIFO .
68539     #define XSEM_REG_INT_MASK_0_CAM_OUT_FIFO_SHIFT                                                   14
68540     #define XSEM_REG_INT_MASK_0_FIN_FIFO                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.FIN_FIFO .
68541     #define XSEM_REG_INT_MASK_0_FIN_FIFO_SHIFT                                                       15
68542     #define XSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
68543     #define XSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_SHIFT                                              16
68544     #define XSEM_REG_INT_MASK_0_THREAD_OVERRUN                                                       (0x1<<17) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.THREAD_OVERRUN .
68545     #define XSEM_REG_INT_MASK_0_THREAD_OVERRUN_SHIFT                                                 17
68546     #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
68547     #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                      18
68548     #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
68549     #define XSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                       19
68550     #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
68551     #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                       20
68552     #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
68553     #define XSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                        21
68554     #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
68555     #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                         22
68556     #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
68557     #define XSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                          23
68558     #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR                                                (0x1<<24) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
68559     #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                          24
68560     #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
68561     #define XSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                         25
68562     #define XSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR                                                  (0x1<<26) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
68563     #define XSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_SHIFT                                            26
68564     #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
68565     #define XSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_SHIFT                                             27
68566     #define XSEM_REG_INT_MASK_0_DBG_FIFO_ERROR                                                       (0x1<<28) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
68567     #define XSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_SHIFT                                                 28
68568     #define XSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
68569     #define XSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_SHIFT                                              29
68570     #define XSEM_REG_INT_MASK_0_VFC_INTERRUPT                                                        (0x1<<30) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.VFC_INTERRUPT .
68571     #define XSEM_REG_INT_MASK_0_VFC_INTERRUPT_SHIFT                                                  30
68572     #define XSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR                                                   (0x1<<31) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
68573     #define XSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_SHIFT                                             31
68574 #define XSEM_REG_INT_STS_WR_0                                                                        0x1400048UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
68575     #define XSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
68576     #define XSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
68577     #define XSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                     (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
68578     #define XSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                               1
68579     #define XSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                   (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
68580     #define XSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                             2
68581     #define XSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                     (0x1<<3) // Error in any one of the FIC FIFO is active.
68582     #define XSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                               3
68583     #define XSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR                                                 (0x1<<4) // Error in Ext PAS_FIFO is active.
68584     #define XSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_SHIFT                                           4
68585     #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR                                                 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
68586     #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_SHIFT                                           5
68587     #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR                                             (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
68588     #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                       6
68589     #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR                                              (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
68590     #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                        7
68591     #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR                                             (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
68592     #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                       8
68593     #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR                                              (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
68594     #define XSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                        9
68595     #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR                                                (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
68596     #define XSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                          10
68597     #define XSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR                                             (0x1<<11) // Signals an unknown address in the fast-memory window.
68598     #define XSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                       11
68599     #define XSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO                                                   (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
68600     #define XSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_SHIFT                                             12
68601     #define XSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO                                                   (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
68602     #define XSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_SHIFT                                             13
68603     #define XSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO                                                       (0x1<<14) // Error in CAM_OUT fifo in cam block.
68604     #define XSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_SHIFT                                                 14
68605     #define XSEM_REG_INT_STS_WR_0_FIN_FIFO                                                           (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
68606     #define XSEM_REG_INT_STS_WR_0_FIN_FIFO_SHIFT                                                     15
68607     #define XSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR                                                  (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
68608     #define XSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_SHIFT                                            16
68609     #define XSEM_REG_INT_STS_WR_0_THREAD_OVERRUN                                                     (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
68610     #define XSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_SHIFT                                               17
68611     #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR                                          (0x1<<18) // Error in external store sync FIFO push logic.
68612     #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                    18
68613     #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR                                           (0x1<<19) // Error in external store sync FIFO pop logic.
68614     #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                     19
68615     #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR                                           (0x1<<20) // Error in external load sync FIFO push logic.
68616     #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                     20
68617     #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR                                            (0x1<<21) // Error in external load sync FIFO pop logic.
68618     #define XSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                      21
68619     #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR                                             (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
68620     #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                       22
68621     #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR                                              (0x1<<23) // Error in LS_SYNC_POP FIFO.
68622     #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                        23
68623     #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR                                              (0x1<<24) // Error in LS_SYNC_POP FIFO.
68624     #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                        24
68625     #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR                                             (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
68626     #define XSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                       25
68627     #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR                                                (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
68628     #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                          26
68629     #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR                                                 (0x1<<27) // Error in LS_SYNC_POP FIFO.
68630     #define XSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_SHIFT                                           27
68631     #define XSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR                                                     (0x1<<28) // Error in slow debug fifo.
68632     #define XSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_SHIFT                                               28
68633     #define XSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO                                                  (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
68634     #define XSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_SHIFT                                            29
68635     #define XSEM_REG_INT_STS_WR_0_VFC_INTERRUPT                                                      (0x1<<30) // Error interrupt in VFC block.
68636     #define XSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_SHIFT                                                30
68637     #define XSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR                                                 (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
68638     #define XSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_SHIFT                                           31
68639 #define XSEM_REG_INT_STS_CLR_0                                                                       0x140004cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
68640     #define XSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
68641     #define XSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
68642     #define XSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                    (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
68643     #define XSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                              1
68644     #define XSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                  (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
68645     #define XSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                            2
68646     #define XSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                    (0x1<<3) // Error in any one of the FIC FIFO is active.
68647     #define XSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                              3
68648     #define XSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR                                                (0x1<<4) // Error in Ext PAS_FIFO is active.
68649     #define XSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_SHIFT                                          4
68650     #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR                                                (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
68651     #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_SHIFT                                          5
68652     #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR                                            (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
68653     #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                      6
68654     #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR                                             (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
68655     #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                       7
68656     #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR                                            (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
68657     #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                      8
68658     #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR                                             (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
68659     #define XSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                       9
68660     #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR                                               (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
68661     #define XSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                         10
68662     #define XSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR                                            (0x1<<11) // Signals an unknown address in the fast-memory window.
68663     #define XSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                      11
68664     #define XSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO                                                  (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
68665     #define XSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_SHIFT                                            12
68666     #define XSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO                                                  (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
68667     #define XSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_SHIFT                                            13
68668     #define XSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO                                                      (0x1<<14) // Error in CAM_OUT fifo in cam block.
68669     #define XSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_SHIFT                                                14
68670     #define XSEM_REG_INT_STS_CLR_0_FIN_FIFO                                                          (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
68671     #define XSEM_REG_INT_STS_CLR_0_FIN_FIFO_SHIFT                                                    15
68672     #define XSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR                                                 (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
68673     #define XSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_SHIFT                                           16
68674     #define XSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN                                                    (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
68675     #define XSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_SHIFT                                              17
68676     #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR                                         (0x1<<18) // Error in external store sync FIFO push logic.
68677     #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                   18
68678     #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR                                          (0x1<<19) // Error in external store sync FIFO pop logic.
68679     #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                    19
68680     #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR                                          (0x1<<20) // Error in external load sync FIFO push logic.
68681     #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                    20
68682     #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR                                           (0x1<<21) // Error in external load sync FIFO pop logic.
68683     #define XSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                     21
68684     #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR                                            (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
68685     #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                      22
68686     #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR                                             (0x1<<23) // Error in LS_SYNC_POP FIFO.
68687     #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                       23
68688     #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR                                             (0x1<<24) // Error in LS_SYNC_POP FIFO.
68689     #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                       24
68690     #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR                                            (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
68691     #define XSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                      25
68692     #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR                                               (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
68693     #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                         26
68694     #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR                                                (0x1<<27) // Error in LS_SYNC_POP FIFO.
68695     #define XSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_SHIFT                                          27
68696     #define XSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR                                                    (0x1<<28) // Error in slow debug fifo.
68697     #define XSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_SHIFT                                              28
68698     #define XSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO                                                 (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
68699     #define XSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_SHIFT                                           29
68700     #define XSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT                                                     (0x1<<30) // Error interrupt in VFC block.
68701     #define XSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_SHIFT                                               30
68702     #define XSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR                                                (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
68703     #define XSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_SHIFT                                          31
68704 #define XSEM_REG_INT_STS_1                                                                           0x1400050UL //Access:R    DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68705     #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
68706     #define XSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_SHIFT                                             0
68707     #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
68708     #define XSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_SHIFT                                             1
68709     #define XSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR                                                   (0x1<<2) // The Storm detected an illegal runtime value.
68710     #define XSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_SHIFT                                             2
68711     #define XSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
68712     #define XSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                          3
68713     #define XSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
68714     #define XSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_SHIFT                                           4
68715     #define XSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
68716     #define XSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_SHIFT                                           5
68717     #define XSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
68718     #define XSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_SHIFT                                            6
68719     #define XSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
68720     #define XSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_SHIFT                                            7
68721     #define XSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
68722     #define XSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_SHIFT                                               8
68723     #define XSEM_REG_INT_STS_1_INVLD_FOC_ERROR                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
68724     #define XSEM_REG_INT_STS_1_INVLD_FOC_ERROR_SHIFT                                                 9
68725     #define XSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
68726     #define XSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_SHIFT                                                10
68727     #define XSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
68728     #define XSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_SHIFT                                             11
68729     #define XSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
68730     #define XSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_SHIFT                                            12
68731 #define XSEM_REG_INT_MASK_1                                                                          0x1400054UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68732     #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
68733     #define XSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_SHIFT                                            0
68734     #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
68735     #define XSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_SHIFT                                            1
68736     #define XSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
68737     #define XSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_SHIFT                                            2
68738     #define XSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
68739     #define XSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                         3
68740     #define XSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
68741     #define XSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_SHIFT                                          4
68742     #define XSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
68743     #define XSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_SHIFT                                          5
68744     #define XSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
68745     #define XSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_SHIFT                                           6
68746     #define XSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
68747     #define XSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_SHIFT                                           7
68748     #define XSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
68749     #define XSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_SHIFT                                              8
68750     #define XSEM_REG_INT_MASK_1_INVLD_FOC_ERROR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
68751     #define XSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_SHIFT                                                9
68752     #define XSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
68753     #define XSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_SHIFT                                               10
68754     #define XSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
68755     #define XSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_SHIFT                                            11
68756     #define XSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: XSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
68757     #define XSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_SHIFT                                           12
68758 #define XSEM_REG_INT_STS_WR_1                                                                        0x1400058UL //Access:WR   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68759     #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN                                                (0x1<<0) // An underflow error was detected in the Storm stack.
68760     #define XSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_SHIFT                                          0
68761     #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN                                                (0x1<<1) // An overflow error was detected in the Storm stack.
68762     #define XSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_SHIFT                                          1
68763     #define XSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR                                                (0x1<<2) // The Storm detected an illegal runtime value.
68764     #define XSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_SHIFT                                          2
68765     #define XSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR                                             (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
68766     #define XSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                       3
68767     #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR                                              (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
68768     #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                        4
68769     #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR                                              (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
68770     #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                        5
68771     #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR                                               (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
68772     #define XSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_SHIFT                                         6
68773     #define XSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR                                               (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
68774     #define XSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_SHIFT                                         7
68775     #define XSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR                                                  (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
68776     #define XSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_SHIFT                                            8
68777     #define XSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR                                                    (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
68778     #define XSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_SHIFT                                              9
68779     #define XSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR                                                   (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
68780     #define XSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_SHIFT                                             10
68781     #define XSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR                                                (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
68782     #define XSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_SHIFT                                          11
68783     #define XSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR                                               (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
68784     #define XSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_SHIFT                                         12
68785 #define XSEM_REG_INT_STS_CLR_1                                                                       0x140005cUL //Access:RC   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68786     #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN                                               (0x1<<0) // An underflow error was detected in the Storm stack.
68787     #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_SHIFT                                         0
68788     #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN                                               (0x1<<1) // An overflow error was detected in the Storm stack.
68789     #define XSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_SHIFT                                         1
68790     #define XSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR                                               (0x1<<2) // The Storm detected an illegal runtime value.
68791     #define XSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_SHIFT                                         2
68792     #define XSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR                                            (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
68793     #define XSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                      3
68794     #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR                                             (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
68795     #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                       4
68796     #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR                                             (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
68797     #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                       5
68798     #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR                                              (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
68799     #define XSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_SHIFT                                        6
68800     #define XSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR                                              (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
68801     #define XSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_SHIFT                                        7
68802     #define XSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR                                                 (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
68803     #define XSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_SHIFT                                           8
68804     #define XSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR                                                   (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
68805     #define XSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_SHIFT                                             9
68806     #define XSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR                                                  (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
68807     #define XSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_SHIFT                                            10
68808     #define XSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR                                               (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
68809     #define XSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_SHIFT                                         11
68810     #define XSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR                                              (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
68811     #define XSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_SHIFT                                        12
68812 #define XSEM_REG_PRTY_MASK                                                                           0x14000ccUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68813     #define XSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                  (0x1<<0) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
68814     #define XSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                            0
68815     #define XSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                 (0x1<<1) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
68816     #define XSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                           1
68817     #define XSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                  (0x1<<2) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
68818     #define XSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                            2
68819 #define XSEM_REG_PRTY_MASK_H_0                                                                       0x1400204UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68820     #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
68821     #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_SHIFT                                       0
68822     #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
68823     #define XSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_SHIFT                                       1
68824     #define XSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
68825     #define XSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           2
68826     #define XSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
68827     #define XSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           3
68828     #define XSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
68829     #define XSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           4
68830     #define XSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
68831     #define XSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           5
68832     #define XSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: XSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
68833     #define XSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           6
68834 #define XSEM_REG_MEM_ECC_EVENTS                                                                      0x140021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
68835 #define XSEM_REG_MEM005_I_MEM_DFT_K2                                                                 0x1400224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsem.i_sem_core.i_sem_slow.i_sem_slow_int_table_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
68836 #define XSEM_REG_MEM006_I_MEM_DFT_K2                                                                 0x1400228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68837 #define XSEM_REG_MEM002_I_MEM_DFT_K2                                                                 0x140022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsem.i_sem_core.i_sem_slow.i_sem_slow_ext_pas_fifo_wrap.DEFAULT_EXT_PAS_FIFO_GEN_IF.i_sem_slow_ext_pas_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68838 #define XSEM_REG_MEM004_I_MEM_DFT_K2                                                                 0x1400230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsem.i_sem_core.i_sem_slow.i_sem_slow_fic_fifo_wrap.XSEM_FIC0_FIFO_MEM_GEN_IF.i_sem_slow_fic0_fifo_xsem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68839 #define XSEM_REG_MEM003_I_MEM_DFT_K2                                                                 0x1400234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsem.i_sem_core.i_sem_slow.i_sem_slow_fic_fifo_wrap.DEFAULT_FIC1_FIFO_MEM_GEN_IF.i_sem_slow_fic1_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68840 #define XSEM_REG_MEM001_I_MEM_DFT_K2                                                                 0x1400238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance xsem.i_sem_core.i_sem_slow.i_sem_slow_dbg_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
68841 #define XSEM_REG_ARB_CYCLE_SIZE                                                                      0x1400400UL //Access:RW   DataWidth:0x5   The number of time_slots in the arbitration cycle.  Chips: BB_A0 BB_B0 K2
68842 #define XSEM_REG_VF_ERROR                                                                            0x1400408UL //Access:WR   DataWidth:0x1   This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.  Chips: BB_A0 BB_B0 K2
68843 #define XSEM_REG_PF_ERROR                                                                            0x140040cUL //Access:WR   DataWidth:0x1   This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.  Chips: BB_A0 BB_B0 K2
68844 #define XSEM_REG_VF_ERR_VECTOR                                                                       0x1400420UL //Access:WB_R DataWidth:0xc0  This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.  Chips: BB_A0 BB_B0 K2
68845 #define XSEM_REG_VF_ERR_VECTOR_SIZE                                                                  8
68846 #define XSEM_REG_PF_ERR_VECTOR                                                                       0x1400440UL //Access:R    DataWidth:0x10  This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.  Chips: BB_A0 BB_B0 K2
68847 #define XSEM_REG_CLEAR_STALL                                                                         0x1400444UL //Access:RW   DataWidth:0x1   Clear stall signal sent from local storm to external storms.  Chips: BB_A0 BB_B0 K2
68848 #define XSEM_REG_EXCEPTION_INT                                                                       0x1400448UL //Access:RW   DataWidth:0x10  Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.  Chips: BB_A0 BB_B0 K2
68849 #define XSEM_REG_EXT_STORE_FREE_ENTRIES                                                              0x140044cUL //Access:R    DataWidth:0x6   Number of free entries in the external STORE sync FIFO.  Chips: BB_A0 BB_B0 K2
68850 #define XSEM_REG_GPI_DATA                                                                            0x1400450UL //Access:R    DataWidth:0x20  Used to read the GPI input signals.  Chips: BB_A0 BB_B0 K2
68851 #define XSEM_REG_GPRE_SAMP_PERIOD                                                                    0x1400454UL //Access:RW   DataWidth:0x4   Defines the number of system clocks from one sample of GPRE sync data and the next.  Chips: BB_A0 BB_B0 K2
68852 #define XSEM_REG_ALLOW_LP_SLEEP_THRD                                                                 0x1400458UL //Access:RW   DataWidth:0x1   When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.  Chips: BB_A0 BB_B0 K2
68853 #define XSEM_REG_ECO_RESERVED                                                                        0x140045cUL //Access:RW   DataWidth:0x8   This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: BB_A0 BB_B0 K2
68854 #define XSEM_REG_FIC_GAP_VECT                                                                        0x1400500UL //Access:WB   DataWidth:0x2c  This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.  Chips: BB_A0 BB_B0 K2
68855 #define XSEM_REG_FIC_GAP_VECT_SIZE                                                                   18
68856 #define XSEM_REG_FIC_FIFO                                                                            0x1400580UL //Access:WB_R DataWidth:0x80  Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.  Chips: BB_A0 BB_B0 K2
68857 #define XSEM_REG_FIC_FIFO_SIZE                                                                       8
68858 #define XSEM_REG_FIC_MIN_MSG                                                                         0x1400600UL //Access:RW   DataWidth:0x6   Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.  Chips: BB_A0 BB_B0 K2
68859 #define XSEM_REG_FIC_MIN_MSG_SIZE                                                                    2
68860 #define XSEM_REG_FIC_EMPTY_CT_MODE                                                                   0x1400620UL //Access:RW   DataWidth:0x1   When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.  Chips: BB_A0 BB_B0 K2
68861 #define XSEM_REG_FIC_EMPTY_CT_CNT                                                                    0x1400624UL //Access:RC   DataWidth:0x18  Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.  Chips: BB_A0 BB_B0 K2
68862 #define XSEM_REG_FOC_CREDIT                                                                          0x1400680UL //Access:RW   DataWidth:0x8   Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.  Chips: BB_A0 BB_B0 K2
68863 #define XSEM_REG_FOC_CREDIT_SIZE                                                                     2
68864 #define XSEM_REG_FULL_FOC_DRA_STRT_EN                                                                0x14006c0UL //Access:RW   DataWidth:0x1   When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.  Chips: BB_A0 BB_B0 K2
68865 #define XSEM_REG_FIN_COMMAND                                                                         0x1400700UL //Access:WB_R DataWidth:0x164 Last fin command that was read from fifo. Its spelling in FIN_FIFO register.  Chips: BB_A0 BB_B0 K2
68866 #define XSEM_REG_FIN_COMMAND_SIZE                                                                    16
68867 #define XSEM_REG_FIN_FIFO                                                                            0x1400800UL //Access:WB_R DataWidth:0x164 READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.  Chips: BB_A0 BB_B0 K2
68868 #define XSEM_REG_FIN_FIFO_SIZE                                                                       16
68869 #define XSEM_REG_INVLD_PAS_WR_EN                                                                     0x1400900UL //Access:RW   DataWidth:0x1   When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.  Chips: BB_A0 BB_B0 K2
68870 #define XSEM_REG_ARBITER_REQUEST                                                                     0x1400980UL //Access:R    DataWidth:0x5   Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
68871 #define XSEM_REG_ARBITER_SELECT                                                                      0x1400984UL //Access:R    DataWidth:0x5   Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
68872 #define XSEM_REG_ARBITER_SLOT                                                                        0x1400988UL //Access:R    DataWidth:0x5   Dra arbiter last slot.  Chips: BB_A0 BB_B0 K2
68873 #define XSEM_REG_ARB_AS_DEF                                                                          0x1400a00UL //Access:RW   DataWidth:0x3   Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.  Chips: BB_A0 BB_B0 K2
68874 #define XSEM_REG_ARB_AS_DEF_SIZE                                                                     32
68875 #define XSEM_REG_ARB_TS_AS                                                                           0x1400a80UL //Access:RW   DataWidth:0x2   Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].  Chips: BB_A0 BB_B0 K2
68876 #define XSEM_REG_ARB_TS_AS_SIZE                                                                      20
68877 #define XSEM_REG_NUM_OF_THREADS                                                                      0x1400b00UL //Access:R    DataWidth:0x5   The number of curretnly free threads.  Chips: BB_A0 BB_B0 K2
68878 #define XSEM_REG_THREAD_ERROR                                                                        0x1400b04UL //Access:R    DataWidth:0x18  Thread error indication.  Chips: BB_A0 BB_B0 K2
68879 #define XSEM_REG_THREAD_RDY                                                                          0x1400b08UL //Access:R    DataWidth:0x18  Thread ready indication.  Chips: BB_A0 BB_B0 K2
68880 #define XSEM_REG_THREAD_SET_NUM                                                                      0x1400b0cUL //Access:W    DataWidth:0x5   Thread ID. Write thread ID will set ready indication for this thread ID.  Chips: BB_A0 BB_B0 K2
68881 #define XSEM_REG_THREAD_VALID                                                                        0x1400b10UL //Access:R    DataWidth:0x18  Valid sleeping threads.  Chips: BB_A0 BB_B0 K2
68882 #define XSEM_REG_THREADS_LIST                                                                        0x1400b14UL //Access:RW   DataWidth:0x18  List of free threads.  Chips: BB_A0 BB_B0 K2
68883 #define XSEM_REG_ORDER_HEAD                                                                          0x1400c00UL //Access:RW   DataWidth:0x5   This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.  Chips: BB_A0 BB_B0 K2
68884 #define XSEM_REG_ORDER_HEAD_SIZE                                                                     8
68885 #define XSEM_REG_ORDER_TAIL                                                                          0x1400c80UL //Access:RW   DataWidth:0x5   This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
68886 #define XSEM_REG_ORDER_TAIL_SIZE                                                                     8
68887 #define XSEM_REG_ORDER_EMPTY                                                                         0x1400d00UL //Access:RW   DataWidth:0x1   This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
68888 #define XSEM_REG_ORDER_EMPTY_SIZE                                                                    8
68889 #define XSEM_REG_ORDER_LL_REG                                                                        0x1400d80UL //Access:RW   DataWidth:0x5   This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..  Chips: BB_A0 BB_B0 K2
68890 #define XSEM_REG_ORDER_LL_REG_SIZE                                                                   24
68891 #define XSEM_REG_ORDER_POP_EN                                                                        0x1400e00UL //Access:RW   DataWidth:0x18  Provides access to the thread ordering queue pop-enable vector.  Chips: BB_A0 BB_B0 K2
68892 #define XSEM_REG_ORDER_WAKE_EN                                                                       0x1400e08UL //Access:RW   DataWidth:0x18  Provides access to the thread ordering queue wake-enable vector.  Chips: BB_A0 BB_B0 K2
68893 #define XSEM_REG_PF_NUM_ORDER_BASE                                                                   0x1400e10UL //Access:RW   DataWidth:0x3   This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.  Chips: BB_A0 BB_B0 K2
68894 #define XSEM_REG_DBG_ALM_FULL                                                                        0x1401000UL //Access:RW   DataWidth:0x6   Almost full for slow debug fifo.  Chips: BB_A0 BB_B0 K2
68895 #define XSEM_REG_PASSIVE_ALM_FULL                                                                    0x1401004UL //Access:RW   DataWidth:0x5   The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.  Chips: BB_A0 BB_B0 K2
68896 #define XSEM_REG_SYNC_DRA_WR_ALM_FULL                                                                0x1401008UL //Access:RW   DataWidth:0x5   Almost full for sync dra_wr fifo (data from DRA to STORM).  Chips: BB_A0 BB_B0 K2
68897 #define XSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                0x140100cUL //Access:RW   DataWidth:0x6   Almost full for sync ram_wr fifo (data from EXT_IF to STORM).  Chips: BB_A0 BB_B0 K2
68898 #define XSEM_REG_DRA_EMPTY                                                                           0x1401100UL //Access:R    DataWidth:0x1   Dra_empty.  Chips: BB_A0 BB_B0 K2
68899 #define XSEM_REG_EXT_PAS_EMPTY                                                                       0x1401104UL //Access:R    DataWidth:0x1   EXT_PAS FIFO empty in sem_slow.  Chips: BB_A0 BB_B0 K2
68900 #define XSEM_REG_FIC_EMPTY                                                                           0x1401120UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO empty in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
68901 #define XSEM_REG_FIC_EMPTY_SIZE                                                                      2
68902 #define XSEM_REG_SLOW_DBG_EMPTY                                                                      0x1401140UL //Access:R    DataWidth:0x1   DBG FIFO is empty in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
68903 #define XSEM_REG_SLOW_DRA_FIN_EMPTY                                                                  0x1401144UL //Access:R    DataWidth:0x1   FIN fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
68904 #define XSEM_REG_SLOW_DRA_RD_EMPTY                                                                   0x1401148UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
68905 #define XSEM_REG_SLOW_DRA_WR_EMPTY                                                                   0x140114cUL //Access:R    DataWidth:0x1   DRA_WR push fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
68906 #define XSEM_REG_SLOW_EXT_STORE_EMPTY                                                                0x1401150UL //Access:R    DataWidth:0x1   EXT_STORE FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68907 #define XSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                 0x1401154UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68908 #define XSEM_REG_SLOW_RAM_RD_EMPTY                                                                   0x1401158UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68909 #define XSEM_REG_SLOW_RAM_WR_EMPTY                                                                   0x140115cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68910 #define XSEM_REG_SYNC_DBG_EMPTY                                                                      0x1401160UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
68911 #define XSEM_REG_THREAD_FIFO_EMPTY                                                                   0x1401164UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
68912 #define XSEM_REG_ORD_ID_FIFO_EMPTY                                                                   0x1401168UL //Access:R    DataWidth:0x1   Indicates that the order ID fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
68913 #define XSEM_REG_EXT_PAS_FULL                                                                        0x1401200UL //Access:R    DataWidth:0x1   EXT_PAS FIFO Full in sem_slow.  Chips: BB_A0 BB_B0 K2
68914 #define XSEM_REG_EXT_STORE_IF_FULL                                                                   0x1401204UL //Access:R    DataWidth:0x1   EXT_STORE IF is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68915 #define XSEM_REG_FIC_FULL                                                                            0x1401220UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO full in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
68916 #define XSEM_REG_FIC_FULL_SIZE                                                                       2
68917 #define XSEM_REG_PAS_IF_FULL                                                                         0x1401240UL //Access:R    DataWidth:0x1   Full from passive buffer asserted toward SDM.  Chips: BB_A0 BB_B0 K2
68918 #define XSEM_REG_RAM_IF_FULL                                                                         0x1401244UL //Access:R    DataWidth:0x1   EXT_RAM IF is full in sem_slow_ls_ram.  Chips: BB_A0 BB_B0 K2
68919 #define XSEM_REG_SLOW_DBG_ALM_FULL                                                                   0x1401248UL //Access:R    DataWidth:0x1   DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.  Chips: BB_A0 BB_B0 K2
68920 #define XSEM_REG_SLOW_DBG_FULL                                                                       0x140124cUL //Access:R    DataWidth:0x1   DBG FIFO is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
68921 #define XSEM_REG_SLOW_DRA_FIN_FULL                                                                   0x1401250UL //Access:R    DataWidth:0x1   FIN fifo is full in sem_slow_dra_sync (never may be active).  Chips: BB_A0 BB_B0 K2
68922 #define XSEM_REG_SLOW_DRA_RD_FULL                                                                    0x1401254UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
68923 #define XSEM_REG_SLOW_DRA_WR_FULL                                                                    0x1401258UL //Access:R    DataWidth:0x1   DRA_WR push fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
68924 #define XSEM_REG_SLOW_EXT_STORE_FULL                                                                 0x140125cUL //Access:R    DataWidth:0x1   EXT_STORE FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68925 #define XSEM_REG_SLOW_EXT_LOAD_FULL                                                                  0x1401260UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68926 #define XSEM_REG_SLOW_RAM_RD_FULL                                                                    0x1401264UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68927 #define XSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                0x1401268UL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68928 #define XSEM_REG_SLOW_RAM_WR_FULL                                                                    0x140126cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
68929 #define XSEM_REG_SYNC_DBG_FULL                                                                       0x1401270UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is full in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
68930 #define XSEM_REG_THREAD_FIFO_FULL                                                                    0x1401274UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
68931 #define XSEM_REG_ORD_ID_FIFO_FULL                                                                    0x1401278UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
68932 #define XSEM_REG_THREAD_INTER_CNT                                                                    0x1401300UL //Access:RW   DataWidth:0x10  Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.  Chips: BB_A0 BB_B0 K2
68933 #define XSEM_REG_THREAD_INTER_CNT_ENABLE                                                             0x1401304UL //Access:RW   DataWidth:0x1   Enable for start count of thread_inter_cnt.  Chips: BB_A0 BB_B0 K2
68934 #define XSEM_REG_THREAD_ORUN_NUM                                                                     0x1401308UL //Access:R    DataWidth:0x18  Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.  Chips: BB_A0 BB_B0 K2
68935 #define XSEM_REG_SLOW_DBG_ACTIVE                                                                     0x1401400UL //Access:RW   DataWidth:0x1   Debug mode is active.  Chips: BB_A0 BB_B0 K2
68936 #define XSEM_REG_SLOW_DBG_MODE                                                                       0x1401404UL //Access:RW   DataWidth:0x3   Debug mode for slow debug bus.  Chips: BB_A0 BB_B0 K2
68937 #define XSEM_REG_DBG_FRAME_MODE                                                                      0x1401408UL //Access:RW   DataWidth:0x2   Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.  Chips: BB_A0 BB_B0 K2
68938 #define XSEM_REG_DBG_EACH_CYLE                                                                       0x140140cUL //Access:RW   DataWidth:0x1   0=output every cycle; 1= output only when there is a change.  Chips: BB_A0 BB_B0 K2
68939 #define XSEM_REG_DBG_GPRE_VECT                                                                       0x1401410UL //Access:RW   DataWidth:0x8   This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].  Chips: BB_A0 BB_B0 K2
68940 #define XSEM_REG_DBG_IF_FULL                                                                         0x1401414UL //Access:R    DataWidth:0x1   DBG IF is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
68941 #define XSEM_REG_DBG_MODE0_CFG                                                                       0x1401418UL //Access:RW   DataWidth:0x1   0=all the message; 1=partial message.  Chips: BB_A0 BB_B0 K2
68942 #define XSEM_REG_DBG_MODE0_CFG_CYCLE                                                                 0x140141cUL //Access:RW   DataWidth:0x5   In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.  Chips: BB_A0 BB_B0 K2
68943 #define XSEM_REG_DBG_MODE1_CFG                                                                       0x1401420UL //Access:RW   DataWidth:0x1   0=without the data; 1=with the data.  Chips: BB_A0 BB_B0 K2
68944 #define XSEM_REG_DBG_MSG_SRC                                                                         0x1401424UL //Access:RW   DataWidth:0x3   This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.  Chips: BB_A0 BB_B0 K2
68945 #define XSEM_REG_DBG_OUT_DATA                                                                        0x1401500UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
68946 #define XSEM_REG_DBG_OUT_DATA_SIZE                                                                   8
68947 #define XSEM_REG_DBG_OUT_VALID                                                                       0x1401520UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
68948 #define XSEM_REG_DBG_OUT_FRAME                                                                       0x1401524UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
68949 #define XSEM_REG_DBG_SELECT                                                                          0x1401528UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
68950 #define XSEM_REG_DBG_DWORD_ENABLE                                                                    0x140152cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
68951 #define XSEM_REG_DBG_SHIFT                                                                           0x1401530UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
68952 #define XSEM_REG_DBG_FORCE_VALID                                                                     0x1401534UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
68953 #define XSEM_REG_DBG_FORCE_FRAME                                                                     0x1401538UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
68954 #define XSEM_REG_EXT_PAS_FIFO                                                                        0x1408000UL //Access:WB_R DataWidth:0x4d  Provides read-only access of the external passive FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
68955 #define XSEM_REG_EXT_PAS_FIFO_SIZE                                                                   76
68956 #define XSEM_REG_INT_TABLE                                                                           0x1410000UL //Access:RW   DataWidth:0x15  Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address  Chips: BB_A0 BB_B0 K2
68957 #define XSEM_REG_INT_TABLE_SIZE                                                                      256
68958 #define XSEM_REG_PASSIVE_BUFFER                                                                      0x1420000UL //Access:WB   DataWidth:0x80  Read and write to it is just for debugging. Passive buffer memory.  Chips: BB_A0 BB_B0 K2
68959 #define XSEM_REG_PASSIVE_BUFFER_SIZE                                                                 4320
68960 #define XSEM_REG_FAST_MEMORY                                                                         0x1440000UL //Access:RW   DataWidth:0x20  See sem_fast.xls for its description.  Chips: BB_A0 BB_B0 K2
68961 #define XSEM_REG_FAST_MEMORY_SIZE                                                                    65536
68962 #define XSEM_REG_PRAM                                                                                0x1480000UL //Access:WB   DataWidth:0x30  Pram memory.  Chips: BB_A0 BB_B0 K2
68963 #define XSEM_REG_PRAM_SIZE                                                                           73728
68964 #define YSEM_REG_ENABLE_IN                                                                           0x1500004UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68965     #define YSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN                                                    (0x1<<0) // Full input from external IF to LS input enable.
68966     #define YSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_SHIFT                                              0
68967     #define YSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN                                                 (0x1<<1) // Read data from external LS IF input enable.
68968     #define YSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_SHIFT                                           1
68969     #define YSEM_REG_ENABLE_IN_FIC_ENABLE_IN                                                         (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
68970     #define YSEM_REG_ENABLE_IN_FIC_ENABLE_IN_SHIFT                                                   2
68971     #define YSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN                                                     (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
68972     #define YSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_SHIFT                                               3
68973     #define YSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN                                                     (0x1<<4) // General interface input enable.
68974     #define YSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_SHIFT                                               4
68975     #define YSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN                                                     (0x1<<5) // External passive write input enable.
68976     #define YSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_SHIFT                                               5
68977     #define YSEM_REG_ENABLE_IN_RAM_ENABLE_IN                                                         (0x1<<6) // Data input enable to RAM.
68978     #define YSEM_REG_ENABLE_IN_RAM_ENABLE_IN_SHIFT                                                   6
68979     #define YSEM_REG_ENABLE_IN_STALL_ENABLE_IN                                                       (0x1<<7) // Enable for stall input from all external STORM instances.
68980     #define YSEM_REG_ENABLE_IN_STALL_ENABLE_IN_SHIFT                                                 7
68981     #define YSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN                                                  (0x1<<8) // Thread ready bus input enable.
68982     #define YSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_SHIFT                                            8
68983     #define YSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN                                                  (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
68984     #define YSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_SHIFT                                            9
68985 #define YSEM_REG_ENABLE_OUT                                                                          0x1500008UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
68986     #define YSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT                                                (0x1<<0) // Read request output enable from external LS IF.
68987     #define YSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_SHIFT                                          0
68988     #define YSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT                                                (0x1<<1) // Write request output enable from external LS IF.
68989     #define YSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_SHIFT                                          1
68990     #define YSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT                                                       (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
68991     #define YSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_SHIFT                                                 2
68992     #define YSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT                                                   (0x1<<3) // Passive full output enable.
68993     #define YSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_SHIFT                                             3
68994     #define YSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT                                                       (0x1<<4) // Data output enable to RAM.
68995     #define YSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_SHIFT                                                 4
68996     #define YSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT                                                     (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
68997     #define YSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_SHIFT                                               5
68998 #define YSEM_REG_FIC_DISABLE                                                                         0x150000cUL //Access:RW   DataWidth:0x1   Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
68999 #define YSEM_REG_PAS_DISABLE                                                                         0x1500010UL //Access:RW   DataWidth:0x1   Disables input messages from the passive buffer  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
69000 #define YSEM_REG_INT_STS_0                                                                           0x1500040UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
69001     #define YSEM_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
69002     #define YSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
69003     #define YSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                        (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
69004     #define YSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                  1
69005     #define YSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                      (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
69006     #define YSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                2
69007     #define YSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                        (0x1<<3) // Error in any one of the FIC FIFO is active.
69008     #define YSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                  3
69009     #define YSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
69010     #define YSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_SHIFT                                              4
69011     #define YSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
69012     #define YSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_SHIFT                                              5
69013     #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
69014     #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                          6
69015     #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
69016     #define YSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                           7
69017     #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
69018     #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                          8
69019     #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
69020     #define YSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                           9
69021     #define YSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
69022     #define YSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_SHIFT                                             10
69023     #define YSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
69024     #define YSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                          11
69025     #define YSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
69026     #define YSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_SHIFT                                                12
69027     #define YSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
69028     #define YSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_SHIFT                                                13
69029     #define YSEM_REG_INT_STS_0_CAM_OUT_FIFO                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
69030     #define YSEM_REG_INT_STS_0_CAM_OUT_FIFO_SHIFT                                                    14
69031     #define YSEM_REG_INT_STS_0_FIN_FIFO                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
69032     #define YSEM_REG_INT_STS_0_FIN_FIFO_SHIFT                                                        15
69033     #define YSEM_REG_INT_STS_0_THREAD_FIFO_ERROR                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
69034     #define YSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_SHIFT                                               16
69035     #define YSEM_REG_INT_STS_0_THREAD_OVERRUN                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
69036     #define YSEM_REG_INT_STS_0_THREAD_OVERRUN_SHIFT                                                  17
69037     #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR                                             (0x1<<18) // Error in external store sync FIFO push logic.
69038     #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                       18
69039     #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR                                              (0x1<<19) // Error in external store sync FIFO pop logic.
69040     #define YSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                        19
69041     #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR                                              (0x1<<20) // Error in external load sync FIFO push logic.
69042     #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                        20
69043     #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR                                               (0x1<<21) // Error in external load sync FIFO pop logic.
69044     #define YSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                         21
69045     #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
69046     #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                          22
69047     #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
69048     #define YSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                           23
69049     #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
69050     #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                           24
69051     #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
69052     #define YSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                          25
69053     #define YSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
69054     #define YSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_SHIFT                                             26
69055     #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
69056     #define YSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_SHIFT                                              27
69057     #define YSEM_REG_INT_STS_0_DBG_FIFO_ERROR                                                        (0x1<<28) // Error in slow debug fifo.
69058     #define YSEM_REG_INT_STS_0_DBG_FIFO_ERROR_SHIFT                                                  28
69059     #define YSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
69060     #define YSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_SHIFT                                               29
69061     #define YSEM_REG_INT_STS_0_VFC_INTERRUPT                                                         (0x1<<30) // Error interrupt in VFC block.
69062     #define YSEM_REG_INT_STS_0_VFC_INTERRUPT_SHIFT                                                   30
69063     #define YSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
69064     #define YSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_SHIFT                                              31
69065 #define YSEM_REG_INT_MASK_0                                                                          0x1500044UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
69066     #define YSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.ADDRESS_ERROR .
69067     #define YSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
69068     #define YSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_LAST_ERROR .
69069     #define YSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                 1
69070     #define YSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
69071     #define YSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                               2
69072     #define YSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
69073     #define YSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                 3
69074     #define YSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
69075     #define YSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_SHIFT                                             4
69076     #define YSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
69077     #define YSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_SHIFT                                             5
69078     #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
69079     #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                         6
69080     #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
69081     #define YSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                          7
69082     #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
69083     #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                         8
69084     #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
69085     #define YSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                          9
69086     #define YSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
69087     #define YSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_SHIFT                                            10
69088     #define YSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
69089     #define YSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                         11
69090     #define YSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
69091     #define YSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_SHIFT                                               12
69092     #define YSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
69093     #define YSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_SHIFT                                               13
69094     #define YSEM_REG_INT_MASK_0_CAM_OUT_FIFO                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_OUT_FIFO .
69095     #define YSEM_REG_INT_MASK_0_CAM_OUT_FIFO_SHIFT                                                   14
69096     #define YSEM_REG_INT_MASK_0_FIN_FIFO                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.FIN_FIFO .
69097     #define YSEM_REG_INT_MASK_0_FIN_FIFO_SHIFT                                                       15
69098     #define YSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
69099     #define YSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_SHIFT                                              16
69100     #define YSEM_REG_INT_MASK_0_THREAD_OVERRUN                                                       (0x1<<17) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.THREAD_OVERRUN .
69101     #define YSEM_REG_INT_MASK_0_THREAD_OVERRUN_SHIFT                                                 17
69102     #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
69103     #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                      18
69104     #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
69105     #define YSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                       19
69106     #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
69107     #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                       20
69108     #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
69109     #define YSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                        21
69110     #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
69111     #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                         22
69112     #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
69113     #define YSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                          23
69114     #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR                                                (0x1<<24) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
69115     #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                          24
69116     #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
69117     #define YSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                         25
69118     #define YSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR                                                  (0x1<<26) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
69119     #define YSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_SHIFT                                            26
69120     #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
69121     #define YSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_SHIFT                                             27
69122     #define YSEM_REG_INT_MASK_0_DBG_FIFO_ERROR                                                       (0x1<<28) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
69123     #define YSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_SHIFT                                                 28
69124     #define YSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
69125     #define YSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_SHIFT                                              29
69126     #define YSEM_REG_INT_MASK_0_VFC_INTERRUPT                                                        (0x1<<30) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.VFC_INTERRUPT .
69127     #define YSEM_REG_INT_MASK_0_VFC_INTERRUPT_SHIFT                                                  30
69128     #define YSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR                                                   (0x1<<31) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
69129     #define YSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_SHIFT                                             31
69130 #define YSEM_REG_INT_STS_WR_0                                                                        0x1500048UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
69131     #define YSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
69132     #define YSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
69133     #define YSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                     (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
69134     #define YSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                               1
69135     #define YSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                   (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
69136     #define YSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                             2
69137     #define YSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                     (0x1<<3) // Error in any one of the FIC FIFO is active.
69138     #define YSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                               3
69139     #define YSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR                                                 (0x1<<4) // Error in Ext PAS_FIFO is active.
69140     #define YSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_SHIFT                                           4
69141     #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR                                                 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
69142     #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_SHIFT                                           5
69143     #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR                                             (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
69144     #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                       6
69145     #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR                                              (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
69146     #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                        7
69147     #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR                                             (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
69148     #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                       8
69149     #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR                                              (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
69150     #define YSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                        9
69151     #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR                                                (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
69152     #define YSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                          10
69153     #define YSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR                                             (0x1<<11) // Signals an unknown address in the fast-memory window.
69154     #define YSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                       11
69155     #define YSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO                                                   (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
69156     #define YSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_SHIFT                                             12
69157     #define YSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO                                                   (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
69158     #define YSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_SHIFT                                             13
69159     #define YSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO                                                       (0x1<<14) // Error in CAM_OUT fifo in cam block.
69160     #define YSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_SHIFT                                                 14
69161     #define YSEM_REG_INT_STS_WR_0_FIN_FIFO                                                           (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
69162     #define YSEM_REG_INT_STS_WR_0_FIN_FIFO_SHIFT                                                     15
69163     #define YSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR                                                  (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
69164     #define YSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_SHIFT                                            16
69165     #define YSEM_REG_INT_STS_WR_0_THREAD_OVERRUN                                                     (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
69166     #define YSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_SHIFT                                               17
69167     #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR                                          (0x1<<18) // Error in external store sync FIFO push logic.
69168     #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                    18
69169     #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR                                           (0x1<<19) // Error in external store sync FIFO pop logic.
69170     #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                     19
69171     #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR                                           (0x1<<20) // Error in external load sync FIFO push logic.
69172     #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                     20
69173     #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR                                            (0x1<<21) // Error in external load sync FIFO pop logic.
69174     #define YSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                      21
69175     #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR                                             (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
69176     #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                       22
69177     #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR                                              (0x1<<23) // Error in LS_SYNC_POP FIFO.
69178     #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                        23
69179     #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR                                              (0x1<<24) // Error in LS_SYNC_POP FIFO.
69180     #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                        24
69181     #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR                                             (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
69182     #define YSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                       25
69183     #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR                                                (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
69184     #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                          26
69185     #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR                                                 (0x1<<27) // Error in LS_SYNC_POP FIFO.
69186     #define YSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_SHIFT                                           27
69187     #define YSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR                                                     (0x1<<28) // Error in slow debug fifo.
69188     #define YSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_SHIFT                                               28
69189     #define YSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO                                                  (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
69190     #define YSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_SHIFT                                            29
69191     #define YSEM_REG_INT_STS_WR_0_VFC_INTERRUPT                                                      (0x1<<30) // Error interrupt in VFC block.
69192     #define YSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_SHIFT                                                30
69193     #define YSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR                                                 (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
69194     #define YSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_SHIFT                                           31
69195 #define YSEM_REG_INT_STS_CLR_0                                                                       0x150004cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
69196     #define YSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
69197     #define YSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
69198     #define YSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                    (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
69199     #define YSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                              1
69200     #define YSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                  (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
69201     #define YSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                            2
69202     #define YSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                    (0x1<<3) // Error in any one of the FIC FIFO is active.
69203     #define YSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                              3
69204     #define YSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR                                                (0x1<<4) // Error in Ext PAS_FIFO is active.
69205     #define YSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_SHIFT                                          4
69206     #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR                                                (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
69207     #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_SHIFT                                          5
69208     #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR                                            (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
69209     #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                      6
69210     #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR                                             (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
69211     #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                       7
69212     #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR                                            (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
69213     #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                      8
69214     #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR                                             (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
69215     #define YSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                       9
69216     #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR                                               (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
69217     #define YSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                         10
69218     #define YSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR                                            (0x1<<11) // Signals an unknown address in the fast-memory window.
69219     #define YSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                      11
69220     #define YSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO                                                  (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
69221     #define YSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_SHIFT                                            12
69222     #define YSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO                                                  (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
69223     #define YSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_SHIFT                                            13
69224     #define YSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO                                                      (0x1<<14) // Error in CAM_OUT fifo in cam block.
69225     #define YSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_SHIFT                                                14
69226     #define YSEM_REG_INT_STS_CLR_0_FIN_FIFO                                                          (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
69227     #define YSEM_REG_INT_STS_CLR_0_FIN_FIFO_SHIFT                                                    15
69228     #define YSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR                                                 (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
69229     #define YSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_SHIFT                                           16
69230     #define YSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN                                                    (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
69231     #define YSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_SHIFT                                              17
69232     #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR                                         (0x1<<18) // Error in external store sync FIFO push logic.
69233     #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                   18
69234     #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR                                          (0x1<<19) // Error in external store sync FIFO pop logic.
69235     #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                    19
69236     #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR                                          (0x1<<20) // Error in external load sync FIFO push logic.
69237     #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                    20
69238     #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR                                           (0x1<<21) // Error in external load sync FIFO pop logic.
69239     #define YSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                     21
69240     #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR                                            (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
69241     #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                      22
69242     #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR                                             (0x1<<23) // Error in LS_SYNC_POP FIFO.
69243     #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                       23
69244     #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR                                             (0x1<<24) // Error in LS_SYNC_POP FIFO.
69245     #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                       24
69246     #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR                                            (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
69247     #define YSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                      25
69248     #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR                                               (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
69249     #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                         26
69250     #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR                                                (0x1<<27) // Error in LS_SYNC_POP FIFO.
69251     #define YSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_SHIFT                                          27
69252     #define YSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR                                                    (0x1<<28) // Error in slow debug fifo.
69253     #define YSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_SHIFT                                              28
69254     #define YSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO                                                 (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
69255     #define YSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_SHIFT                                           29
69256     #define YSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT                                                     (0x1<<30) // Error interrupt in VFC block.
69257     #define YSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_SHIFT                                               30
69258     #define YSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR                                                (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
69259     #define YSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_SHIFT                                          31
69260 #define YSEM_REG_INT_STS_1                                                                           0x1500050UL //Access:R    DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69261     #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
69262     #define YSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_SHIFT                                             0
69263     #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
69264     #define YSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_SHIFT                                             1
69265     #define YSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR                                                   (0x1<<2) // The Storm detected an illegal runtime value.
69266     #define YSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_SHIFT                                             2
69267     #define YSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
69268     #define YSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                          3
69269     #define YSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
69270     #define YSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_SHIFT                                           4
69271     #define YSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
69272     #define YSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_SHIFT                                           5
69273     #define YSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
69274     #define YSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_SHIFT                                            6
69275     #define YSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
69276     #define YSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_SHIFT                                            7
69277     #define YSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
69278     #define YSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_SHIFT                                               8
69279     #define YSEM_REG_INT_STS_1_INVLD_FOC_ERROR                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
69280     #define YSEM_REG_INT_STS_1_INVLD_FOC_ERROR_SHIFT                                                 9
69281     #define YSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
69282     #define YSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_SHIFT                                                10
69283     #define YSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
69284     #define YSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_SHIFT                                             11
69285     #define YSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
69286     #define YSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_SHIFT                                            12
69287 #define YSEM_REG_INT_MASK_1                                                                          0x1500054UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69288     #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
69289     #define YSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_SHIFT                                            0
69290     #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
69291     #define YSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_SHIFT                                            1
69292     #define YSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
69293     #define YSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_SHIFT                                            2
69294     #define YSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
69295     #define YSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                         3
69296     #define YSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
69297     #define YSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_SHIFT                                          4
69298     #define YSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
69299     #define YSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_SHIFT                                          5
69300     #define YSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
69301     #define YSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_SHIFT                                           6
69302     #define YSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
69303     #define YSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_SHIFT                                           7
69304     #define YSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
69305     #define YSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_SHIFT                                              8
69306     #define YSEM_REG_INT_MASK_1_INVLD_FOC_ERROR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
69307     #define YSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_SHIFT                                                9
69308     #define YSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
69309     #define YSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_SHIFT                                               10
69310     #define YSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
69311     #define YSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_SHIFT                                            11
69312     #define YSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: YSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
69313     #define YSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_SHIFT                                           12
69314 #define YSEM_REG_INT_STS_WR_1                                                                        0x1500058UL //Access:WR   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69315     #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN                                                (0x1<<0) // An underflow error was detected in the Storm stack.
69316     #define YSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_SHIFT                                          0
69317     #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN                                                (0x1<<1) // An overflow error was detected in the Storm stack.
69318     #define YSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_SHIFT                                          1
69319     #define YSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR                                                (0x1<<2) // The Storm detected an illegal runtime value.
69320     #define YSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_SHIFT                                          2
69321     #define YSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR                                             (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
69322     #define YSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                       3
69323     #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR                                              (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
69324     #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                        4
69325     #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR                                              (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
69326     #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                        5
69327     #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR                                               (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
69328     #define YSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_SHIFT                                         6
69329     #define YSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR                                               (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
69330     #define YSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_SHIFT                                         7
69331     #define YSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR                                                  (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
69332     #define YSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_SHIFT                                            8
69333     #define YSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR                                                    (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
69334     #define YSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_SHIFT                                              9
69335     #define YSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR                                                   (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
69336     #define YSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_SHIFT                                             10
69337     #define YSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR                                                (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
69338     #define YSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_SHIFT                                          11
69339     #define YSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR                                               (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
69340     #define YSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_SHIFT                                         12
69341 #define YSEM_REG_INT_STS_CLR_1                                                                       0x150005cUL //Access:RC   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69342     #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN                                               (0x1<<0) // An underflow error was detected in the Storm stack.
69343     #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_SHIFT                                         0
69344     #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN                                               (0x1<<1) // An overflow error was detected in the Storm stack.
69345     #define YSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_SHIFT                                         1
69346     #define YSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR                                               (0x1<<2) // The Storm detected an illegal runtime value.
69347     #define YSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_SHIFT                                         2
69348     #define YSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR                                            (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
69349     #define YSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                      3
69350     #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR                                             (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
69351     #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                       4
69352     #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR                                             (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
69353     #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                       5
69354     #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR                                              (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
69355     #define YSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_SHIFT                                        6
69356     #define YSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR                                              (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
69357     #define YSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_SHIFT                                        7
69358     #define YSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR                                                 (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
69359     #define YSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_SHIFT                                           8
69360     #define YSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR                                                   (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
69361     #define YSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_SHIFT                                             9
69362     #define YSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR                                                  (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
69363     #define YSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_SHIFT                                            10
69364     #define YSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR                                               (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
69365     #define YSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_SHIFT                                         11
69366     #define YSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR                                              (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
69367     #define YSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_SHIFT                                        12
69368 #define YSEM_REG_PRTY_MASK                                                                           0x15000ccUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69369     #define YSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                  (0x1<<0) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
69370     #define YSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                            0
69371     #define YSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                 (0x1<<1) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
69372     #define YSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                           1
69373     #define YSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                  (0x1<<2) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
69374     #define YSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                            2
69375 #define YSEM_REG_PRTY_MASK_H_0                                                                       0x1500204UL //Access:RW   DataWidth:0x7   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69376     #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_0_RF_INT .
69377     #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_0_RF_INT_SHIFT                                       0
69378     #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM006_I_ECC_1_RF_INT .
69379     #define YSEM_REG_PRTY_MASK_H_0_MEM006_I_ECC_1_RF_INT_SHIFT                                       1
69380     #define YSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM005_I_MEM_PRTY .
69381     #define YSEM_REG_PRTY_MASK_H_0_MEM005_I_MEM_PRTY_SHIFT                                           2
69382     #define YSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
69383     #define YSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           3
69384     #define YSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
69385     #define YSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           4
69386     #define YSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
69387     #define YSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           5
69388     #define YSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<6) // This bit masks, when set, the Parity bit: YSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
69389     #define YSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           6
69390 #define YSEM_REG_MEM_ECC_EVENTS                                                                      0x150021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
69391 #define YSEM_REG_MEM005_I_MEM_DFT_K2                                                                 0x1500224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysem.i_sem_core.i_sem_slow.i_sem_slow_int_table_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
69392 #define YSEM_REG_MEM006_I_MEM_DFT_K2                                                                 0x1500228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.YSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_ysem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69393 #define YSEM_REG_MEM002_I_MEM_DFT_K2                                                                 0x150022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysem.i_sem_core.i_sem_slow.i_sem_slow_ext_pas_fifo_wrap.YSEM_EXT_PAS_FIFO_GEN_IF.i_sem_slow_ext_pas_fifo_ysem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69394 #define YSEM_REG_MEM004_I_MEM_DFT_K2                                                                 0x1500230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysem.i_sem_core.i_sem_slow.i_sem_slow_fic_fifo_wrap.YSEM_FIC0_FIFO_MEM_GEN_IF.i_sem_slow_fic0_fifo_ysem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69395 #define YSEM_REG_MEM003_I_MEM_DFT_K2                                                                 0x1500234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysem.i_sem_core.i_sem_slow.i_sem_slow_fic_fifo_wrap.DEFAULT_FIC1_FIFO_MEM_GEN_IF.i_sem_slow_fic1_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69396 #define YSEM_REG_MEM001_I_MEM_DFT_K2                                                                 0x1500238UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance ysem.i_sem_core.i_sem_slow.i_sem_slow_dbg_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69397 #define YSEM_REG_ARB_CYCLE_SIZE                                                                      0x1500400UL //Access:RW   DataWidth:0x5   The number of time_slots in the arbitration cycle.  Chips: BB_A0 BB_B0 K2
69398 #define YSEM_REG_VF_ERROR                                                                            0x1500408UL //Access:WR   DataWidth:0x1   This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.  Chips: BB_A0 BB_B0 K2
69399 #define YSEM_REG_PF_ERROR                                                                            0x150040cUL //Access:WR   DataWidth:0x1   This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.  Chips: BB_A0 BB_B0 K2
69400 #define YSEM_REG_VF_ERR_VECTOR                                                                       0x1500420UL //Access:WB_R DataWidth:0xc0  This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.  Chips: BB_A0 BB_B0 K2
69401 #define YSEM_REG_VF_ERR_VECTOR_SIZE                                                                  8
69402 #define YSEM_REG_PF_ERR_VECTOR                                                                       0x1500440UL //Access:R    DataWidth:0x10  This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.  Chips: BB_A0 BB_B0 K2
69403 #define YSEM_REG_CLEAR_STALL                                                                         0x1500444UL //Access:RW   DataWidth:0x1   Clear stall signal sent from local storm to external storms.  Chips: BB_A0 BB_B0 K2
69404 #define YSEM_REG_EXCEPTION_INT                                                                       0x1500448UL //Access:RW   DataWidth:0x10  Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.  Chips: BB_A0 BB_B0 K2
69405 #define YSEM_REG_EXT_STORE_FREE_ENTRIES                                                              0x150044cUL //Access:R    DataWidth:0x6   Number of free entries in the external STORE sync FIFO.  Chips: BB_A0 BB_B0 K2
69406 #define YSEM_REG_GPI_DATA                                                                            0x1500450UL //Access:R    DataWidth:0x20  Used to read the GPI input signals.  Chips: BB_A0 BB_B0 K2
69407 #define YSEM_REG_GPRE_SAMP_PERIOD                                                                    0x1500454UL //Access:RW   DataWidth:0x4   Defines the number of system clocks from one sample of GPRE sync data and the next.  Chips: BB_A0 BB_B0 K2
69408 #define YSEM_REG_ALLOW_LP_SLEEP_THRD                                                                 0x1500458UL //Access:RW   DataWidth:0x1   When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.  Chips: BB_A0 BB_B0 K2
69409 #define YSEM_REG_ECO_RESERVED                                                                        0x150045cUL //Access:RW   DataWidth:0x8   This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: BB_A0 BB_B0 K2
69410 #define YSEM_REG_FIC_GAP_VECT                                                                        0x1500500UL //Access:WB   DataWidth:0x2c  This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.  Chips: BB_A0 BB_B0 K2
69411 #define YSEM_REG_FIC_GAP_VECT_SIZE                                                                   18
69412 #define YSEM_REG_FIC_FIFO                                                                            0x1500580UL //Access:WB_R DataWidth:0x80  Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.  Chips: BB_A0 BB_B0 K2
69413 #define YSEM_REG_FIC_FIFO_SIZE                                                                       8
69414 #define YSEM_REG_FIC_MIN_MSG                                                                         0x1500600UL //Access:RW   DataWidth:0x6   Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.  Chips: BB_A0 BB_B0 K2
69415 #define YSEM_REG_FIC_MIN_MSG_SIZE                                                                    2
69416 #define YSEM_REG_FIC_EMPTY_CT_MODE                                                                   0x1500620UL //Access:RW   DataWidth:0x1   When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.  Chips: BB_A0 BB_B0 K2
69417 #define YSEM_REG_FIC_EMPTY_CT_CNT                                                                    0x1500624UL //Access:RC   DataWidth:0x18  Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.  Chips: BB_A0 BB_B0 K2
69418 #define YSEM_REG_FOC_CREDIT                                                                          0x1500680UL //Access:RW   DataWidth:0x8   Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.  Chips: BB_A0 BB_B0 K2
69419 #define YSEM_REG_FOC_CREDIT_SIZE                                                                     6
69420 #define YSEM_REG_FULL_FOC_DRA_STRT_EN                                                                0x15006c0UL //Access:RW   DataWidth:0x1   When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.  Chips: BB_A0 BB_B0 K2
69421 #define YSEM_REG_FIN_COMMAND                                                                         0x1500700UL //Access:WB_R DataWidth:0x164 Last fin command that was read from fifo. Its spelling in FIN_FIFO register.  Chips: BB_A0 BB_B0 K2
69422 #define YSEM_REG_FIN_COMMAND_SIZE                                                                    16
69423 #define YSEM_REG_FIN_FIFO                                                                            0x1500800UL //Access:WB_R DataWidth:0x164 READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.  Chips: BB_A0 BB_B0 K2
69424 #define YSEM_REG_FIN_FIFO_SIZE                                                                       16
69425 #define YSEM_REG_INVLD_PAS_WR_EN                                                                     0x1500900UL //Access:RW   DataWidth:0x1   When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.  Chips: BB_A0 BB_B0 K2
69426 #define YSEM_REG_ARBITER_REQUEST                                                                     0x1500980UL //Access:R    DataWidth:0x5   Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
69427 #define YSEM_REG_ARBITER_SELECT                                                                      0x1500984UL //Access:R    DataWidth:0x5   Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
69428 #define YSEM_REG_ARBITER_SLOT                                                                        0x1500988UL //Access:R    DataWidth:0x5   Dra arbiter last slot.  Chips: BB_A0 BB_B0 K2
69429 #define YSEM_REG_ARB_AS_DEF                                                                          0x1500a00UL //Access:RW   DataWidth:0x3   Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.  Chips: BB_A0 BB_B0 K2
69430 #define YSEM_REG_ARB_AS_DEF_SIZE                                                                     32
69431 #define YSEM_REG_ARB_TS_AS                                                                           0x1500a80UL //Access:RW   DataWidth:0x2   Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].  Chips: BB_A0 BB_B0 K2
69432 #define YSEM_REG_ARB_TS_AS_SIZE                                                                      20
69433 #define YSEM_REG_NUM_OF_THREADS                                                                      0x1500b00UL //Access:R    DataWidth:0x4   The number of curretnly free threads.  Chips: BB_A0 BB_B0 K2
69434 #define YSEM_REG_THREAD_ERROR                                                                        0x1500b04UL //Access:R    DataWidth:0xe   Thread error indication.  Chips: BB_A0 BB_B0 K2
69435 #define YSEM_REG_THREAD_RDY                                                                          0x1500b08UL //Access:R    DataWidth:0xe   Thread ready indication.  Chips: BB_A0 BB_B0 K2
69436 #define YSEM_REG_THREAD_SET_NUM                                                                      0x1500b0cUL //Access:W    DataWidth:0x5   Thread ID. Write thread ID will set ready indication for this thread ID.  Chips: BB_A0 BB_B0 K2
69437 #define YSEM_REG_THREAD_VALID                                                                        0x1500b10UL //Access:R    DataWidth:0xe   Valid sleeping threads.  Chips: BB_A0 BB_B0 K2
69438 #define YSEM_REG_THREADS_LIST                                                                        0x1500b14UL //Access:RW   DataWidth:0xe   List of free threads.  Chips: BB_A0 BB_B0 K2
69439 #define YSEM_REG_ORDER_HEAD                                                                          0x1500c00UL //Access:RW   DataWidth:0x4   This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.  Chips: BB_A0 BB_B0 K2
69440 #define YSEM_REG_ORDER_HEAD_SIZE                                                                     16
69441 #define YSEM_REG_ORDER_TAIL                                                                          0x1500c80UL //Access:RW   DataWidth:0x4   This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
69442 #define YSEM_REG_ORDER_TAIL_SIZE                                                                     16
69443 #define YSEM_REG_ORDER_EMPTY                                                                         0x1500d00UL //Access:RW   DataWidth:0x1   This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
69444 #define YSEM_REG_ORDER_EMPTY_SIZE                                                                    16
69445 #define YSEM_REG_ORDER_LL_REG                                                                        0x1500d80UL //Access:RW   DataWidth:0x4   This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..  Chips: BB_A0 BB_B0 K2
69446 #define YSEM_REG_ORDER_LL_REG_SIZE                                                                   14
69447 #define YSEM_REG_ORDER_POP_EN                                                                        0x1500e00UL //Access:RW   DataWidth:0xe   Provides access to the thread ordering queue pop-enable vector.  Chips: BB_A0 BB_B0 K2
69448 #define YSEM_REG_ORDER_WAKE_EN                                                                       0x1500e08UL //Access:RW   DataWidth:0xe   Provides access to the thread ordering queue wake-enable vector.  Chips: BB_A0 BB_B0 K2
69449 #define YSEM_REG_PF_NUM_ORDER_BASE                                                                   0x1500e10UL //Access:RW   DataWidth:0x4   This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.  Chips: BB_A0 BB_B0 K2
69450 #define YSEM_REG_DBG_ALM_FULL                                                                        0x1501000UL //Access:RW   DataWidth:0x6   Almost full for slow debug fifo.  Chips: BB_A0 BB_B0 K2
69451 #define YSEM_REG_PASSIVE_ALM_FULL                                                                    0x1501004UL //Access:RW   DataWidth:0x5   The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.  Chips: BB_A0 BB_B0 K2
69452 #define YSEM_REG_SYNC_DRA_WR_ALM_FULL                                                                0x1501008UL //Access:RW   DataWidth:0x5   Almost full for sync dra_wr fifo (data from DRA to STORM).  Chips: BB_A0 BB_B0 K2
69453 #define YSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                0x150100cUL //Access:RW   DataWidth:0x6   Almost full for sync ram_wr fifo (data from EXT_IF to STORM).  Chips: BB_A0 BB_B0 K2
69454 #define YSEM_REG_DRA_EMPTY                                                                           0x1501100UL //Access:R    DataWidth:0x1   Dra_empty.  Chips: BB_A0 BB_B0 K2
69455 #define YSEM_REG_EXT_PAS_EMPTY                                                                       0x1501104UL //Access:R    DataWidth:0x1   EXT_PAS FIFO empty in sem_slow.  Chips: BB_A0 BB_B0 K2
69456 #define YSEM_REG_FIC_EMPTY                                                                           0x1501120UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO empty in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
69457 #define YSEM_REG_FIC_EMPTY_SIZE                                                                      2
69458 #define YSEM_REG_SLOW_DBG_EMPTY                                                                      0x1501140UL //Access:R    DataWidth:0x1   DBG FIFO is empty in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
69459 #define YSEM_REG_SLOW_DRA_FIN_EMPTY                                                                  0x1501144UL //Access:R    DataWidth:0x1   FIN fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
69460 #define YSEM_REG_SLOW_DRA_RD_EMPTY                                                                   0x1501148UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
69461 #define YSEM_REG_SLOW_DRA_WR_EMPTY                                                                   0x150114cUL //Access:R    DataWidth:0x1   DRA_WR push fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
69462 #define YSEM_REG_SLOW_EXT_STORE_EMPTY                                                                0x1501150UL //Access:R    DataWidth:0x1   EXT_STORE FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69463 #define YSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                 0x1501154UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69464 #define YSEM_REG_SLOW_RAM_RD_EMPTY                                                                   0x1501158UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69465 #define YSEM_REG_SLOW_RAM_WR_EMPTY                                                                   0x150115cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69466 #define YSEM_REG_SYNC_DBG_EMPTY                                                                      0x1501160UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
69467 #define YSEM_REG_THREAD_FIFO_EMPTY                                                                   0x1501164UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
69468 #define YSEM_REG_ORD_ID_FIFO_EMPTY                                                                   0x1501168UL //Access:R    DataWidth:0x1   Indicates that the order ID fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
69469 #define YSEM_REG_EXT_PAS_FULL                                                                        0x1501200UL //Access:R    DataWidth:0x1   EXT_PAS FIFO Full in sem_slow.  Chips: BB_A0 BB_B0 K2
69470 #define YSEM_REG_EXT_STORE_IF_FULL                                                                   0x1501204UL //Access:R    DataWidth:0x1   EXT_STORE IF is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69471 #define YSEM_REG_FIC_FULL                                                                            0x1501220UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO full in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
69472 #define YSEM_REG_FIC_FULL_SIZE                                                                       2
69473 #define YSEM_REG_PAS_IF_FULL                                                                         0x1501240UL //Access:R    DataWidth:0x1   Full from passive buffer asserted toward SDM.  Chips: BB_A0 BB_B0 K2
69474 #define YSEM_REG_RAM_IF_FULL                                                                         0x1501244UL //Access:R    DataWidth:0x1   EXT_RAM IF is full in sem_slow_ls_ram.  Chips: BB_A0 BB_B0 K2
69475 #define YSEM_REG_SLOW_DBG_ALM_FULL                                                                   0x1501248UL //Access:R    DataWidth:0x1   DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.  Chips: BB_A0 BB_B0 K2
69476 #define YSEM_REG_SLOW_DBG_FULL                                                                       0x150124cUL //Access:R    DataWidth:0x1   DBG FIFO is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
69477 #define YSEM_REG_SLOW_DRA_FIN_FULL                                                                   0x1501250UL //Access:R    DataWidth:0x1   FIN fifo is full in sem_slow_dra_sync (never may be active).  Chips: BB_A0 BB_B0 K2
69478 #define YSEM_REG_SLOW_DRA_RD_FULL                                                                    0x1501254UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
69479 #define YSEM_REG_SLOW_DRA_WR_FULL                                                                    0x1501258UL //Access:R    DataWidth:0x1   DRA_WR push fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
69480 #define YSEM_REG_SLOW_EXT_STORE_FULL                                                                 0x150125cUL //Access:R    DataWidth:0x1   EXT_STORE FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69481 #define YSEM_REG_SLOW_EXT_LOAD_FULL                                                                  0x1501260UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69482 #define YSEM_REG_SLOW_RAM_RD_FULL                                                                    0x1501264UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69483 #define YSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                0x1501268UL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69484 #define YSEM_REG_SLOW_RAM_WR_FULL                                                                    0x150126cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
69485 #define YSEM_REG_SYNC_DBG_FULL                                                                       0x1501270UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is full in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
69486 #define YSEM_REG_THREAD_FIFO_FULL                                                                    0x1501274UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
69487 #define YSEM_REG_ORD_ID_FIFO_FULL                                                                    0x1501278UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
69488 #define YSEM_REG_THREAD_INTER_CNT                                                                    0x1501300UL //Access:RW   DataWidth:0x10  Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.  Chips: BB_A0 BB_B0 K2
69489 #define YSEM_REG_THREAD_INTER_CNT_ENABLE                                                             0x1501304UL //Access:RW   DataWidth:0x1   Enable for start count of thread_inter_cnt.  Chips: BB_A0 BB_B0 K2
69490 #define YSEM_REG_THREAD_ORUN_NUM                                                                     0x1501308UL //Access:R    DataWidth:0xe   Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.  Chips: BB_A0 BB_B0 K2
69491 #define YSEM_REG_SLOW_DBG_ACTIVE                                                                     0x1501400UL //Access:RW   DataWidth:0x1   Debug mode is active.  Chips: BB_A0 BB_B0 K2
69492 #define YSEM_REG_SLOW_DBG_MODE                                                                       0x1501404UL //Access:RW   DataWidth:0x3   Debug mode for slow debug bus.  Chips: BB_A0 BB_B0 K2
69493 #define YSEM_REG_DBG_FRAME_MODE                                                                      0x1501408UL //Access:RW   DataWidth:0x2   Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.  Chips: BB_A0 BB_B0 K2
69494 #define YSEM_REG_DBG_EACH_CYLE                                                                       0x150140cUL //Access:RW   DataWidth:0x1   0=output every cycle; 1= output only when there is a change.  Chips: BB_A0 BB_B0 K2
69495 #define YSEM_REG_DBG_GPRE_VECT                                                                       0x1501410UL //Access:RW   DataWidth:0x8   This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].  Chips: BB_A0 BB_B0 K2
69496 #define YSEM_REG_DBG_IF_FULL                                                                         0x1501414UL //Access:R    DataWidth:0x1   DBG IF is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
69497 #define YSEM_REG_DBG_MODE0_CFG                                                                       0x1501418UL //Access:RW   DataWidth:0x1   0=all the message; 1=partial message.  Chips: BB_A0 BB_B0 K2
69498 #define YSEM_REG_DBG_MODE0_CFG_CYCLE                                                                 0x150141cUL //Access:RW   DataWidth:0x5   In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.  Chips: BB_A0 BB_B0 K2
69499 #define YSEM_REG_DBG_MODE1_CFG                                                                       0x1501420UL //Access:RW   DataWidth:0x1   0=without the data; 1=with the data.  Chips: BB_A0 BB_B0 K2
69500 #define YSEM_REG_DBG_MSG_SRC                                                                         0x1501424UL //Access:RW   DataWidth:0x3   This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.  Chips: BB_A0 BB_B0 K2
69501 #define YSEM_REG_DBG_OUT_DATA                                                                        0x1501500UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
69502 #define YSEM_REG_DBG_OUT_DATA_SIZE                                                                   8
69503 #define YSEM_REG_DBG_OUT_VALID                                                                       0x1501520UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
69504 #define YSEM_REG_DBG_OUT_FRAME                                                                       0x1501524UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
69505 #define YSEM_REG_DBG_SELECT                                                                          0x1501528UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
69506 #define YSEM_REG_DBG_DWORD_ENABLE                                                                    0x150152cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
69507 #define YSEM_REG_DBG_SHIFT                                                                           0x1501530UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
69508 #define YSEM_REG_DBG_FORCE_VALID                                                                     0x1501534UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
69509 #define YSEM_REG_DBG_FORCE_FRAME                                                                     0x1501538UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
69510 #define YSEM_REG_EXT_PAS_FIFO                                                                        0x1508000UL //Access:WB_R DataWidth:0x4c  Provides read-only access of the external passive FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
69511 #define YSEM_REG_EXT_PAS_FIFO_SIZE                                                                   76
69512 #define YSEM_REG_INT_TABLE                                                                           0x1510000UL //Access:RW   DataWidth:0x15  Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address  Chips: BB_A0 BB_B0 K2
69513 #define YSEM_REG_INT_TABLE_SIZE                                                                      256
69514 #define YSEM_REG_PASSIVE_BUFFER                                                                      0x1520000UL //Access:WB   DataWidth:0x80  Read and write to it is just for debugging. Passive buffer memory.  Chips: BB_A0 BB_B0 K2
69515 #define YSEM_REG_PASSIVE_BUFFER_SIZE                                                                 2520
69516 #define YSEM_REG_FAST_MEMORY                                                                         0x1540000UL //Access:RW   DataWidth:0x20  See sem_fast.xls for its description.  Chips: BB_A0 BB_B0 K2
69517 #define YSEM_REG_FAST_MEMORY_SIZE                                                                    65536
69518 #define YSEM_REG_PRAM                                                                                0x1580000UL //Access:WB   DataWidth:0x30  Pram memory.  Chips: BB_A0 BB_B0 K2
69519 #define YSEM_REG_PRAM_SIZE                                                                           73728
69520 #define PSEM_REG_ENABLE_IN                                                                           0x1600004UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69521     #define PSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN                                                    (0x1<<0) // Full input from external IF to LS input enable.
69522     #define PSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_SHIFT                                              0
69523     #define PSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN                                                 (0x1<<1) // Read data from external LS IF input enable.
69524     #define PSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_SHIFT                                           1
69525     #define PSEM_REG_ENABLE_IN_FIC_ENABLE_IN                                                         (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
69526     #define PSEM_REG_ENABLE_IN_FIC_ENABLE_IN_SHIFT                                                   2
69527     #define PSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN                                                     (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
69528     #define PSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_SHIFT                                               3
69529     #define PSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN                                                     (0x1<<4) // General interface input enable.
69530     #define PSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_SHIFT                                               4
69531     #define PSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN                                                     (0x1<<5) // External passive write input enable.
69532     #define PSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_SHIFT                                               5
69533     #define PSEM_REG_ENABLE_IN_RAM_ENABLE_IN                                                         (0x1<<6) // Data input enable to RAM.
69534     #define PSEM_REG_ENABLE_IN_RAM_ENABLE_IN_SHIFT                                                   6
69535     #define PSEM_REG_ENABLE_IN_STALL_ENABLE_IN                                                       (0x1<<7) // Enable for stall input from all external STORM instances.
69536     #define PSEM_REG_ENABLE_IN_STALL_ENABLE_IN_SHIFT                                                 7
69537     #define PSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN                                                  (0x1<<8) // Thread ready bus input enable.
69538     #define PSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_SHIFT                                            8
69539     #define PSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN                                                  (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
69540     #define PSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_SHIFT                                            9
69541 #define PSEM_REG_ENABLE_OUT                                                                          0x1600008UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69542     #define PSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT                                                (0x1<<0) // Read request output enable from external LS IF.
69543     #define PSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_SHIFT                                          0
69544     #define PSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT                                                (0x1<<1) // Write request output enable from external LS IF.
69545     #define PSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_SHIFT                                          1
69546     #define PSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT                                                       (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
69547     #define PSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_SHIFT                                                 2
69548     #define PSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT                                                   (0x1<<3) // Passive full output enable.
69549     #define PSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_SHIFT                                             3
69550     #define PSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT                                                       (0x1<<4) // Data output enable to RAM.
69551     #define PSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_SHIFT                                                 4
69552     #define PSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT                                                     (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
69553     #define PSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_SHIFT                                               5
69554 #define PSEM_REG_FIC_DISABLE                                                                         0x160000cUL //Access:RW   DataWidth:0x1   Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
69555 #define PSEM_REG_PAS_DISABLE                                                                         0x1600010UL //Access:RW   DataWidth:0x1   Disables input messages from the passive buffer  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
69556 #define PSEM_REG_INT_STS_0                                                                           0x1600040UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
69557     #define PSEM_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
69558     #define PSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
69559     #define PSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                        (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
69560     #define PSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                  1
69561     #define PSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                      (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
69562     #define PSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                2
69563     #define PSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                        (0x1<<3) // Error in any one of the FIC FIFO is active.
69564     #define PSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                  3
69565     #define PSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
69566     #define PSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_SHIFT                                              4
69567     #define PSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
69568     #define PSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_SHIFT                                              5
69569     #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
69570     #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                          6
69571     #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
69572     #define PSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                           7
69573     #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
69574     #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                          8
69575     #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
69576     #define PSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                           9
69577     #define PSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
69578     #define PSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_SHIFT                                             10
69579     #define PSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
69580     #define PSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                          11
69581     #define PSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
69582     #define PSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_SHIFT                                                12
69583     #define PSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
69584     #define PSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_SHIFT                                                13
69585     #define PSEM_REG_INT_STS_0_CAM_OUT_FIFO                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
69586     #define PSEM_REG_INT_STS_0_CAM_OUT_FIFO_SHIFT                                                    14
69587     #define PSEM_REG_INT_STS_0_FIN_FIFO                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
69588     #define PSEM_REG_INT_STS_0_FIN_FIFO_SHIFT                                                        15
69589     #define PSEM_REG_INT_STS_0_THREAD_FIFO_ERROR                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
69590     #define PSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_SHIFT                                               16
69591     #define PSEM_REG_INT_STS_0_THREAD_OVERRUN                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
69592     #define PSEM_REG_INT_STS_0_THREAD_OVERRUN_SHIFT                                                  17
69593     #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR                                             (0x1<<18) // Error in external store sync FIFO push logic.
69594     #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                       18
69595     #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR                                              (0x1<<19) // Error in external store sync FIFO pop logic.
69596     #define PSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                        19
69597     #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR                                              (0x1<<20) // Error in external load sync FIFO push logic.
69598     #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                        20
69599     #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR                                               (0x1<<21) // Error in external load sync FIFO pop logic.
69600     #define PSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                         21
69601     #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
69602     #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                          22
69603     #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
69604     #define PSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                           23
69605     #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
69606     #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                           24
69607     #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
69608     #define PSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                          25
69609     #define PSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
69610     #define PSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_SHIFT                                             26
69611     #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
69612     #define PSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_SHIFT                                              27
69613     #define PSEM_REG_INT_STS_0_DBG_FIFO_ERROR                                                        (0x1<<28) // Error in slow debug fifo.
69614     #define PSEM_REG_INT_STS_0_DBG_FIFO_ERROR_SHIFT                                                  28
69615     #define PSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
69616     #define PSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_SHIFT                                               29
69617     #define PSEM_REG_INT_STS_0_VFC_INTERRUPT                                                         (0x1<<30) // Error interrupt in VFC block.
69618     #define PSEM_REG_INT_STS_0_VFC_INTERRUPT_SHIFT                                                   30
69619     #define PSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
69620     #define PSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_SHIFT                                              31
69621 #define PSEM_REG_INT_MASK_0                                                                          0x1600044UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
69622     #define PSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.ADDRESS_ERROR .
69623     #define PSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
69624     #define PSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_LAST_ERROR .
69625     #define PSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                 1
69626     #define PSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
69627     #define PSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                               2
69628     #define PSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
69629     #define PSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                 3
69630     #define PSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
69631     #define PSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_SHIFT                                             4
69632     #define PSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
69633     #define PSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_SHIFT                                             5
69634     #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
69635     #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                         6
69636     #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
69637     #define PSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                          7
69638     #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
69639     #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                         8
69640     #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
69641     #define PSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                          9
69642     #define PSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
69643     #define PSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_SHIFT                                            10
69644     #define PSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
69645     #define PSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                         11
69646     #define PSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
69647     #define PSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_SHIFT                                               12
69648     #define PSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
69649     #define PSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_SHIFT                                               13
69650     #define PSEM_REG_INT_MASK_0_CAM_OUT_FIFO                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_OUT_FIFO .
69651     #define PSEM_REG_INT_MASK_0_CAM_OUT_FIFO_SHIFT                                                   14
69652     #define PSEM_REG_INT_MASK_0_FIN_FIFO                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.FIN_FIFO .
69653     #define PSEM_REG_INT_MASK_0_FIN_FIFO_SHIFT                                                       15
69654     #define PSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
69655     #define PSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_SHIFT                                              16
69656     #define PSEM_REG_INT_MASK_0_THREAD_OVERRUN                                                       (0x1<<17) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.THREAD_OVERRUN .
69657     #define PSEM_REG_INT_MASK_0_THREAD_OVERRUN_SHIFT                                                 17
69658     #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
69659     #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                      18
69660     #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
69661     #define PSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                       19
69662     #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
69663     #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                       20
69664     #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
69665     #define PSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                        21
69666     #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
69667     #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                         22
69668     #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
69669     #define PSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                          23
69670     #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR                                                (0x1<<24) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
69671     #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                          24
69672     #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
69673     #define PSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                         25
69674     #define PSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR                                                  (0x1<<26) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
69675     #define PSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_SHIFT                                            26
69676     #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
69677     #define PSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_SHIFT                                             27
69678     #define PSEM_REG_INT_MASK_0_DBG_FIFO_ERROR                                                       (0x1<<28) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
69679     #define PSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_SHIFT                                                 28
69680     #define PSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
69681     #define PSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_SHIFT                                              29
69682     #define PSEM_REG_INT_MASK_0_VFC_INTERRUPT                                                        (0x1<<30) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.VFC_INTERRUPT .
69683     #define PSEM_REG_INT_MASK_0_VFC_INTERRUPT_SHIFT                                                  30
69684     #define PSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR                                                   (0x1<<31) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
69685     #define PSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_SHIFT                                             31
69686 #define PSEM_REG_INT_STS_WR_0                                                                        0x1600048UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
69687     #define PSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
69688     #define PSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
69689     #define PSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                     (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
69690     #define PSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                               1
69691     #define PSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                   (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
69692     #define PSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                             2
69693     #define PSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                     (0x1<<3) // Error in any one of the FIC FIFO is active.
69694     #define PSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                               3
69695     #define PSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR                                                 (0x1<<4) // Error in Ext PAS_FIFO is active.
69696     #define PSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_SHIFT                                           4
69697     #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR                                                 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
69698     #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_SHIFT                                           5
69699     #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR                                             (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
69700     #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                       6
69701     #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR                                              (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
69702     #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                        7
69703     #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR                                             (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
69704     #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                       8
69705     #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR                                              (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
69706     #define PSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                        9
69707     #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR                                                (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
69708     #define PSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                          10
69709     #define PSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR                                             (0x1<<11) // Signals an unknown address in the fast-memory window.
69710     #define PSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                       11
69711     #define PSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO                                                   (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
69712     #define PSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_SHIFT                                             12
69713     #define PSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO                                                   (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
69714     #define PSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_SHIFT                                             13
69715     #define PSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO                                                       (0x1<<14) // Error in CAM_OUT fifo in cam block.
69716     #define PSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_SHIFT                                                 14
69717     #define PSEM_REG_INT_STS_WR_0_FIN_FIFO                                                           (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
69718     #define PSEM_REG_INT_STS_WR_0_FIN_FIFO_SHIFT                                                     15
69719     #define PSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR                                                  (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
69720     #define PSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_SHIFT                                            16
69721     #define PSEM_REG_INT_STS_WR_0_THREAD_OVERRUN                                                     (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
69722     #define PSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_SHIFT                                               17
69723     #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR                                          (0x1<<18) // Error in external store sync FIFO push logic.
69724     #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                    18
69725     #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR                                           (0x1<<19) // Error in external store sync FIFO pop logic.
69726     #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                     19
69727     #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR                                           (0x1<<20) // Error in external load sync FIFO push logic.
69728     #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                     20
69729     #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR                                            (0x1<<21) // Error in external load sync FIFO pop logic.
69730     #define PSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                      21
69731     #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR                                             (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
69732     #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                       22
69733     #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR                                              (0x1<<23) // Error in LS_SYNC_POP FIFO.
69734     #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                        23
69735     #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR                                              (0x1<<24) // Error in LS_SYNC_POP FIFO.
69736     #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                        24
69737     #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR                                             (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
69738     #define PSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                       25
69739     #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR                                                (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
69740     #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                          26
69741     #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR                                                 (0x1<<27) // Error in LS_SYNC_POP FIFO.
69742     #define PSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_SHIFT                                           27
69743     #define PSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR                                                     (0x1<<28) // Error in slow debug fifo.
69744     #define PSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_SHIFT                                               28
69745     #define PSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO                                                  (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
69746     #define PSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_SHIFT                                            29
69747     #define PSEM_REG_INT_STS_WR_0_VFC_INTERRUPT                                                      (0x1<<30) // Error interrupt in VFC block.
69748     #define PSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_SHIFT                                                30
69749     #define PSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR                                                 (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
69750     #define PSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_SHIFT                                           31
69751 #define PSEM_REG_INT_STS_CLR_0                                                                       0x160004cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
69752     #define PSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
69753     #define PSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
69754     #define PSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                    (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
69755     #define PSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                              1
69756     #define PSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                  (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
69757     #define PSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                            2
69758     #define PSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                    (0x1<<3) // Error in any one of the FIC FIFO is active.
69759     #define PSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                              3
69760     #define PSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR                                                (0x1<<4) // Error in Ext PAS_FIFO is active.
69761     #define PSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_SHIFT                                          4
69762     #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR                                                (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
69763     #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_SHIFT                                          5
69764     #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR                                            (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
69765     #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                      6
69766     #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR                                             (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
69767     #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                       7
69768     #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR                                            (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
69769     #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                      8
69770     #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR                                             (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
69771     #define PSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                       9
69772     #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR                                               (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
69773     #define PSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                         10
69774     #define PSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR                                            (0x1<<11) // Signals an unknown address in the fast-memory window.
69775     #define PSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                      11
69776     #define PSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO                                                  (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
69777     #define PSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_SHIFT                                            12
69778     #define PSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO                                                  (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
69779     #define PSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_SHIFT                                            13
69780     #define PSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO                                                      (0x1<<14) // Error in CAM_OUT fifo in cam block.
69781     #define PSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_SHIFT                                                14
69782     #define PSEM_REG_INT_STS_CLR_0_FIN_FIFO                                                          (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
69783     #define PSEM_REG_INT_STS_CLR_0_FIN_FIFO_SHIFT                                                    15
69784     #define PSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR                                                 (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
69785     #define PSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_SHIFT                                           16
69786     #define PSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN                                                    (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
69787     #define PSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_SHIFT                                              17
69788     #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR                                         (0x1<<18) // Error in external store sync FIFO push logic.
69789     #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                   18
69790     #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR                                          (0x1<<19) // Error in external store sync FIFO pop logic.
69791     #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                    19
69792     #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR                                          (0x1<<20) // Error in external load sync FIFO push logic.
69793     #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                    20
69794     #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR                                           (0x1<<21) // Error in external load sync FIFO pop logic.
69795     #define PSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                     21
69796     #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR                                            (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
69797     #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                      22
69798     #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR                                             (0x1<<23) // Error in LS_SYNC_POP FIFO.
69799     #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                       23
69800     #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR                                             (0x1<<24) // Error in LS_SYNC_POP FIFO.
69801     #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                       24
69802     #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR                                            (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
69803     #define PSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                      25
69804     #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR                                               (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
69805     #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                         26
69806     #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR                                                (0x1<<27) // Error in LS_SYNC_POP FIFO.
69807     #define PSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_SHIFT                                          27
69808     #define PSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR                                                    (0x1<<28) // Error in slow debug fifo.
69809     #define PSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_SHIFT                                              28
69810     #define PSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO                                                 (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
69811     #define PSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_SHIFT                                           29
69812     #define PSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT                                                     (0x1<<30) // Error interrupt in VFC block.
69813     #define PSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_SHIFT                                               30
69814     #define PSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR                                                (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
69815     #define PSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_SHIFT                                          31
69816 #define PSEM_REG_INT_STS_1                                                                           0x1600050UL //Access:R    DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69817     #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
69818     #define PSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_SHIFT                                             0
69819     #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
69820     #define PSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_SHIFT                                             1
69821     #define PSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR                                                   (0x1<<2) // The Storm detected an illegal runtime value.
69822     #define PSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_SHIFT                                             2
69823     #define PSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
69824     #define PSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                          3
69825     #define PSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
69826     #define PSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_SHIFT                                           4
69827     #define PSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
69828     #define PSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_SHIFT                                           5
69829     #define PSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
69830     #define PSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_SHIFT                                            6
69831     #define PSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
69832     #define PSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_SHIFT                                            7
69833     #define PSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
69834     #define PSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_SHIFT                                               8
69835     #define PSEM_REG_INT_STS_1_INVLD_FOC_ERROR                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
69836     #define PSEM_REG_INT_STS_1_INVLD_FOC_ERROR_SHIFT                                                 9
69837     #define PSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
69838     #define PSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_SHIFT                                                10
69839     #define PSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
69840     #define PSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_SHIFT                                             11
69841     #define PSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
69842     #define PSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_SHIFT                                            12
69843 #define PSEM_REG_INT_MASK_1                                                                          0x1600054UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69844     #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
69845     #define PSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_SHIFT                                            0
69846     #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
69847     #define PSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_SHIFT                                            1
69848     #define PSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
69849     #define PSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_SHIFT                                            2
69850     #define PSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
69851     #define PSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                         3
69852     #define PSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
69853     #define PSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_SHIFT                                          4
69854     #define PSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
69855     #define PSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_SHIFT                                          5
69856     #define PSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
69857     #define PSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_SHIFT                                           6
69858     #define PSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
69859     #define PSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_SHIFT                                           7
69860     #define PSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
69861     #define PSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_SHIFT                                              8
69862     #define PSEM_REG_INT_MASK_1_INVLD_FOC_ERROR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
69863     #define PSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_SHIFT                                                9
69864     #define PSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
69865     #define PSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_SHIFT                                               10
69866     #define PSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
69867     #define PSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_SHIFT                                            11
69868     #define PSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: PSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
69869     #define PSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_SHIFT                                           12
69870 #define PSEM_REG_INT_STS_WR_1                                                                        0x1600058UL //Access:WR   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69871     #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN                                                (0x1<<0) // An underflow error was detected in the Storm stack.
69872     #define PSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_SHIFT                                          0
69873     #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN                                                (0x1<<1) // An overflow error was detected in the Storm stack.
69874     #define PSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_SHIFT                                          1
69875     #define PSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR                                                (0x1<<2) // The Storm detected an illegal runtime value.
69876     #define PSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_SHIFT                                          2
69877     #define PSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR                                             (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
69878     #define PSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                       3
69879     #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR                                              (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
69880     #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                        4
69881     #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR                                              (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
69882     #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                        5
69883     #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR                                               (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
69884     #define PSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_SHIFT                                         6
69885     #define PSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR                                               (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
69886     #define PSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_SHIFT                                         7
69887     #define PSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR                                                  (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
69888     #define PSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_SHIFT                                            8
69889     #define PSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR                                                    (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
69890     #define PSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_SHIFT                                              9
69891     #define PSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR                                                   (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
69892     #define PSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_SHIFT                                             10
69893     #define PSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR                                                (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
69894     #define PSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_SHIFT                                          11
69895     #define PSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR                                               (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
69896     #define PSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_SHIFT                                         12
69897 #define PSEM_REG_INT_STS_CLR_1                                                                       0x160005cUL //Access:RC   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69898     #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN                                               (0x1<<0) // An underflow error was detected in the Storm stack.
69899     #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_SHIFT                                         0
69900     #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN                                               (0x1<<1) // An overflow error was detected in the Storm stack.
69901     #define PSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_SHIFT                                         1
69902     #define PSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR                                               (0x1<<2) // The Storm detected an illegal runtime value.
69903     #define PSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_SHIFT                                         2
69904     #define PSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR                                            (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
69905     #define PSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                      3
69906     #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR                                             (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
69907     #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                       4
69908     #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR                                             (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
69909     #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                       5
69910     #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR                                              (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
69911     #define PSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_SHIFT                                        6
69912     #define PSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR                                              (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
69913     #define PSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_SHIFT                                        7
69914     #define PSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR                                                 (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
69915     #define PSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_SHIFT                                           8
69916     #define PSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR                                                   (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
69917     #define PSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_SHIFT                                             9
69918     #define PSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR                                                  (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
69919     #define PSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_SHIFT                                            10
69920     #define PSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR                                               (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
69921     #define PSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_SHIFT                                         11
69922     #define PSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR                                              (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
69923     #define PSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_SHIFT                                        12
69924 #define PSEM_REG_PRTY_MASK                                                                           0x16000ccUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69925     #define PSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                  (0x1<<0) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
69926     #define PSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                            0
69927     #define PSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                 (0x1<<1) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
69928     #define PSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                           1
69929     #define PSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                  (0x1<<2) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
69930     #define PSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                            2
69931 #define PSEM_REG_PRTY_MASK_H_0                                                                       0x1600204UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
69932     #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
69933     #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT                                       0
69934     #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
69935     #define PSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT                                       1
69936     #define PSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
69937     #define PSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           2
69938     #define PSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
69939     #define PSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           3
69940     #define PSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
69941     #define PSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           4
69942     #define PSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: PSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
69943     #define PSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           5
69944 #define PSEM_REG_MEM_ECC_EVENTS                                                                      0x160021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
69945 #define PSEM_REG_MEM004_I_MEM_DFT_K2                                                                 0x1600224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psem.i_sem_core.i_sem_slow.i_sem_slow_int_table_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
69946 #define PSEM_REG_MEM005_I_MEM_DFT_K2                                                                 0x1600228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.PSEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_psem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69947 #define PSEM_REG_MEM002_I_MEM_DFT_K2                                                                 0x160022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psem.i_sem_core.i_sem_slow.i_sem_slow_ext_pas_fifo_wrap.PSEM_EXT_PAS_FIFO_GEN_IF.i_sem_slow_ext_pas_fifo_psem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69948 #define PSEM_REG_MEM003_I_MEM_DFT_K2                                                                 0x1600230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psem.i_sem_core.i_sem_slow.i_sem_slow_fic_fifo_wrap.PSEM_FIC0_FIFO_MEM_GEN_IF.i_sem_slow_fic0_fifo_psem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69949 #define PSEM_REG_MEM001_I_MEM_DFT_K2                                                                 0x1600234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance psem.i_sem_core.i_sem_slow.i_sem_slow_dbg_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
69950 #define PSEM_REG_ARB_CYCLE_SIZE                                                                      0x1600400UL //Access:RW   DataWidth:0x5   The number of time_slots in the arbitration cycle.  Chips: BB_A0 BB_B0 K2
69951 #define PSEM_REG_VF_ERROR                                                                            0x1600408UL //Access:WR   DataWidth:0x1   This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.  Chips: BB_A0 BB_B0 K2
69952 #define PSEM_REG_PF_ERROR                                                                            0x160040cUL //Access:WR   DataWidth:0x1   This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.  Chips: BB_A0 BB_B0 K2
69953 #define PSEM_REG_VF_ERR_VECTOR                                                                       0x1600420UL //Access:WB_R DataWidth:0xc0  This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.  Chips: BB_A0 BB_B0 K2
69954 #define PSEM_REG_VF_ERR_VECTOR_SIZE                                                                  8
69955 #define PSEM_REG_PF_ERR_VECTOR                                                                       0x1600440UL //Access:R    DataWidth:0x10  This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.  Chips: BB_A0 BB_B0 K2
69956 #define PSEM_REG_CLEAR_STALL                                                                         0x1600444UL //Access:RW   DataWidth:0x1   Clear stall signal sent from local storm to external storms.  Chips: BB_A0 BB_B0 K2
69957 #define PSEM_REG_EXCEPTION_INT                                                                       0x1600448UL //Access:RW   DataWidth:0x10  Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.  Chips: BB_A0 BB_B0 K2
69958 #define PSEM_REG_EXT_STORE_FREE_ENTRIES                                                              0x160044cUL //Access:R    DataWidth:0x6   Number of free entries in the external STORE sync FIFO.  Chips: BB_A0 BB_B0 K2
69959 #define PSEM_REG_GPI_DATA                                                                            0x1600450UL //Access:R    DataWidth:0x20  Used to read the GPI input signals.  Chips: BB_A0 BB_B0 K2
69960 #define PSEM_REG_GPRE_SAMP_PERIOD                                                                    0x1600454UL //Access:RW   DataWidth:0x4   Defines the number of system clocks from one sample of GPRE sync data and the next.  Chips: BB_A0 BB_B0 K2
69961 #define PSEM_REG_ALLOW_LP_SLEEP_THRD                                                                 0x1600458UL //Access:RW   DataWidth:0x1   When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.  Chips: BB_A0 BB_B0 K2
69962 #define PSEM_REG_ECO_RESERVED                                                                        0x160045cUL //Access:RW   DataWidth:0x8   This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: BB_A0 BB_B0 K2
69963 #define PSEM_REG_FIC_GAP_VECT                                                                        0x1600500UL //Access:WB   DataWidth:0x2c  This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.  Chips: BB_A0 BB_B0 K2
69964 #define PSEM_REG_FIC_GAP_VECT_SIZE                                                                   18
69965 #define PSEM_REG_FIC_FIFO                                                                            0x1600580UL //Access:WB_R DataWidth:0x80  Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.  Chips: BB_A0 BB_B0 K2
69966 #define PSEM_REG_FIC_FIFO_SIZE                                                                       4
69967 #define PSEM_REG_FIC_MIN_MSG                                                                         0x1600600UL //Access:RW   DataWidth:0x6   Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.  Chips: BB_A0 BB_B0 K2
69968 #define PSEM_REG_FIC_EMPTY_CT_MODE                                                                   0x1600620UL //Access:RW   DataWidth:0x1   When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.  Chips: BB_A0 BB_B0 K2
69969 #define PSEM_REG_FIC_EMPTY_CT_CNT                                                                    0x1600624UL //Access:RC   DataWidth:0x18  Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.  Chips: BB_A0 BB_B0 K2
69970 #define PSEM_REG_FOC_CREDIT                                                                          0x1600680UL //Access:RW   DataWidth:0x8   Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.  Chips: BB_A0 BB_B0 K2
69971 #define PSEM_REG_FOC_CREDIT_SIZE                                                                     2
69972 #define PSEM_REG_FULL_FOC_DRA_STRT_EN                                                                0x16006c0UL //Access:RW   DataWidth:0x1   When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.  Chips: BB_A0 BB_B0 K2
69973 #define PSEM_REG_FIN_COMMAND                                                                         0x1600700UL //Access:WB_R DataWidth:0x164 Last fin command that was read from fifo. Its spelling in FIN_FIFO register.  Chips: BB_A0 BB_B0 K2
69974 #define PSEM_REG_FIN_COMMAND_SIZE                                                                    16
69975 #define PSEM_REG_FIN_FIFO                                                                            0x1600800UL //Access:WB_R DataWidth:0x164 READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.  Chips: BB_A0 BB_B0 K2
69976 #define PSEM_REG_FIN_FIFO_SIZE                                                                       16
69977 #define PSEM_REG_INVLD_PAS_WR_EN                                                                     0x1600900UL //Access:RW   DataWidth:0x1   When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.  Chips: BB_A0 BB_B0 K2
69978 #define PSEM_REG_ARBITER_REQUEST                                                                     0x1600980UL //Access:R    DataWidth:0x5   Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
69979 #define PSEM_REG_ARBITER_SELECT                                                                      0x1600984UL //Access:R    DataWidth:0x5   Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
69980 #define PSEM_REG_ARBITER_SLOT                                                                        0x1600988UL //Access:R    DataWidth:0x5   Dra arbiter last slot.  Chips: BB_A0 BB_B0 K2
69981 #define PSEM_REG_ARB_AS_DEF                                                                          0x1600a00UL //Access:RW   DataWidth:0x3   Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.  Chips: BB_A0 BB_B0 K2
69982 #define PSEM_REG_ARB_AS_DEF_SIZE                                                                     32
69983 #define PSEM_REG_ARB_TS_AS                                                                           0x1600a80UL //Access:RW   DataWidth:0x2   Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].  Chips: BB_A0 BB_B0 K2
69984 #define PSEM_REG_ARB_TS_AS_SIZE                                                                      20
69985 #define PSEM_REG_NUM_OF_THREADS                                                                      0x1600b00UL //Access:R    DataWidth:0x3   The number of curretnly free threads.  Chips: BB_A0 BB_B0 K2
69986 #define PSEM_REG_THREAD_ERROR                                                                        0x1600b04UL //Access:R    DataWidth:0x4   Thread error indication.  Chips: BB_A0 BB_B0 K2
69987 #define PSEM_REG_THREAD_RDY                                                                          0x1600b08UL //Access:R    DataWidth:0x4   Thread ready indication.  Chips: BB_A0 BB_B0 K2
69988 #define PSEM_REG_THREAD_SET_NUM                                                                      0x1600b0cUL //Access:W    DataWidth:0x5   Thread ID. Write thread ID will set ready indication for this thread ID.  Chips: BB_A0 BB_B0 K2
69989 #define PSEM_REG_THREAD_VALID                                                                        0x1600b10UL //Access:R    DataWidth:0x4   Valid sleeping threads.  Chips: BB_A0 BB_B0 K2
69990 #define PSEM_REG_THREADS_LIST                                                                        0x1600b14UL //Access:RW   DataWidth:0x4   List of free threads.  Chips: BB_A0 BB_B0 K2
69991 #define PSEM_REG_ORDER_HEAD                                                                          0x1600c00UL //Access:RW   DataWidth:0x2   This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.  Chips: BB_A0 BB_B0 K2
69992 #define PSEM_REG_ORDER_HEAD_SIZE                                                                     2
69993 #define PSEM_REG_ORDER_TAIL                                                                          0x1600c80UL //Access:RW   DataWidth:0x2   This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
69994 #define PSEM_REG_ORDER_TAIL_SIZE                                                                     2
69995 #define PSEM_REG_ORDER_EMPTY                                                                         0x1600d00UL //Access:RW   DataWidth:0x1   This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
69996 #define PSEM_REG_ORDER_EMPTY_SIZE                                                                    2
69997 #define PSEM_REG_ORDER_LL_REG                                                                        0x1600d80UL //Access:RW   DataWidth:0x2   This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..  Chips: BB_A0 BB_B0 K2
69998 #define PSEM_REG_ORDER_LL_REG_SIZE                                                                   4
69999 #define PSEM_REG_ORDER_POP_EN                                                                        0x1600e00UL //Access:RW   DataWidth:0x4   Provides access to the thread ordering queue pop-enable vector.  Chips: BB_A0 BB_B0 K2
70000 #define PSEM_REG_ORDER_WAKE_EN                                                                       0x1600e08UL //Access:RW   DataWidth:0x4   Provides access to the thread ordering queue wake-enable vector.  Chips: BB_A0 BB_B0 K2
70001 #define PSEM_REG_PF_NUM_ORDER_BASE                                                                   0x1600e10UL //Access:RW   DataWidth:0x1   This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.  Chips: BB_A0 BB_B0 K2
70002 #define PSEM_REG_DBG_ALM_FULL                                                                        0x1601000UL //Access:RW   DataWidth:0x6   Almost full for slow debug fifo.  Chips: BB_A0 BB_B0 K2
70003 #define PSEM_REG_PASSIVE_ALM_FULL                                                                    0x1601004UL //Access:RW   DataWidth:0x5   The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.  Chips: BB_A0 BB_B0 K2
70004 #define PSEM_REG_SYNC_DRA_WR_ALM_FULL                                                                0x1601008UL //Access:RW   DataWidth:0x5   Almost full for sync dra_wr fifo (data from DRA to STORM).  Chips: BB_A0 BB_B0 K2
70005 #define PSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                0x160100cUL //Access:RW   DataWidth:0x6   Almost full for sync ram_wr fifo (data from EXT_IF to STORM).  Chips: BB_A0 BB_B0 K2
70006 #define PSEM_REG_DRA_EMPTY                                                                           0x1601100UL //Access:R    DataWidth:0x1   Dra_empty.  Chips: BB_A0 BB_B0 K2
70007 #define PSEM_REG_EXT_PAS_EMPTY                                                                       0x1601104UL //Access:R    DataWidth:0x1   EXT_PAS FIFO empty in sem_slow.  Chips: BB_A0 BB_B0 K2
70008 #define PSEM_REG_FIC_EMPTY                                                                           0x1601120UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO empty in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
70009 #define PSEM_REG_SLOW_DBG_EMPTY                                                                      0x1601140UL //Access:R    DataWidth:0x1   DBG FIFO is empty in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
70010 #define PSEM_REG_SLOW_DRA_FIN_EMPTY                                                                  0x1601144UL //Access:R    DataWidth:0x1   FIN fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70011 #define PSEM_REG_SLOW_DRA_RD_EMPTY                                                                   0x1601148UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70012 #define PSEM_REG_SLOW_DRA_WR_EMPTY                                                                   0x160114cUL //Access:R    DataWidth:0x1   DRA_WR push fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70013 #define PSEM_REG_SLOW_EXT_STORE_EMPTY                                                                0x1601150UL //Access:R    DataWidth:0x1   EXT_STORE FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70014 #define PSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                 0x1601154UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70015 #define PSEM_REG_SLOW_RAM_RD_EMPTY                                                                   0x1601158UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70016 #define PSEM_REG_SLOW_RAM_WR_EMPTY                                                                   0x160115cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70017 #define PSEM_REG_SYNC_DBG_EMPTY                                                                      0x1601160UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
70018 #define PSEM_REG_THREAD_FIFO_EMPTY                                                                   0x1601164UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
70019 #define PSEM_REG_ORD_ID_FIFO_EMPTY                                                                   0x1601168UL //Access:R    DataWidth:0x1   Indicates that the order ID fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
70020 #define PSEM_REG_EXT_PAS_FULL                                                                        0x1601200UL //Access:R    DataWidth:0x1   EXT_PAS FIFO Full in sem_slow.  Chips: BB_A0 BB_B0 K2
70021 #define PSEM_REG_EXT_STORE_IF_FULL                                                                   0x1601204UL //Access:R    DataWidth:0x1   EXT_STORE IF is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70022 #define PSEM_REG_FIC_FULL                                                                            0x1601220UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO full in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
70023 #define PSEM_REG_PAS_IF_FULL                                                                         0x1601240UL //Access:R    DataWidth:0x1   Full from passive buffer asserted toward SDM.  Chips: BB_A0 BB_B0 K2
70024 #define PSEM_REG_RAM_IF_FULL                                                                         0x1601244UL //Access:R    DataWidth:0x1   EXT_RAM IF is full in sem_slow_ls_ram.  Chips: BB_A0 BB_B0 K2
70025 #define PSEM_REG_SLOW_DBG_ALM_FULL                                                                   0x1601248UL //Access:R    DataWidth:0x1   DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.  Chips: BB_A0 BB_B0 K2
70026 #define PSEM_REG_SLOW_DBG_FULL                                                                       0x160124cUL //Access:R    DataWidth:0x1   DBG FIFO is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
70027 #define PSEM_REG_SLOW_DRA_FIN_FULL                                                                   0x1601250UL //Access:R    DataWidth:0x1   FIN fifo is full in sem_slow_dra_sync (never may be active).  Chips: BB_A0 BB_B0 K2
70028 #define PSEM_REG_SLOW_DRA_RD_FULL                                                                    0x1601254UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70029 #define PSEM_REG_SLOW_DRA_WR_FULL                                                                    0x1601258UL //Access:R    DataWidth:0x1   DRA_WR push fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70030 #define PSEM_REG_SLOW_EXT_STORE_FULL                                                                 0x160125cUL //Access:R    DataWidth:0x1   EXT_STORE FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70031 #define PSEM_REG_SLOW_EXT_LOAD_FULL                                                                  0x1601260UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70032 #define PSEM_REG_SLOW_RAM_RD_FULL                                                                    0x1601264UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70033 #define PSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                0x1601268UL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70034 #define PSEM_REG_SLOW_RAM_WR_FULL                                                                    0x160126cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70035 #define PSEM_REG_SYNC_DBG_FULL                                                                       0x1601270UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is full in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
70036 #define PSEM_REG_THREAD_FIFO_FULL                                                                    0x1601274UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
70037 #define PSEM_REG_ORD_ID_FIFO_FULL                                                                    0x1601278UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
70038 #define PSEM_REG_THREAD_INTER_CNT                                                                    0x1601300UL //Access:RW   DataWidth:0x10  Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.  Chips: BB_A0 BB_B0 K2
70039 #define PSEM_REG_THREAD_INTER_CNT_ENABLE                                                             0x1601304UL //Access:RW   DataWidth:0x1   Enable for start count of thread_inter_cnt.  Chips: BB_A0 BB_B0 K2
70040 #define PSEM_REG_THREAD_ORUN_NUM                                                                     0x1601308UL //Access:R    DataWidth:0x4   Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.  Chips: BB_A0 BB_B0 K2
70041 #define PSEM_REG_SLOW_DBG_ACTIVE                                                                     0x1601400UL //Access:RW   DataWidth:0x1   Debug mode is active.  Chips: BB_A0 BB_B0 K2
70042 #define PSEM_REG_SLOW_DBG_MODE                                                                       0x1601404UL //Access:RW   DataWidth:0x3   Debug mode for slow debug bus.  Chips: BB_A0 BB_B0 K2
70043 #define PSEM_REG_DBG_FRAME_MODE                                                                      0x1601408UL //Access:RW   DataWidth:0x2   Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.  Chips: BB_A0 BB_B0 K2
70044 #define PSEM_REG_DBG_EACH_CYLE                                                                       0x160140cUL //Access:RW   DataWidth:0x1   0=output every cycle; 1= output only when there is a change.  Chips: BB_A0 BB_B0 K2
70045 #define PSEM_REG_DBG_GPRE_VECT                                                                       0x1601410UL //Access:RW   DataWidth:0x8   This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].  Chips: BB_A0 BB_B0 K2
70046 #define PSEM_REG_DBG_IF_FULL                                                                         0x1601414UL //Access:R    DataWidth:0x1   DBG IF is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
70047 #define PSEM_REG_DBG_MODE0_CFG                                                                       0x1601418UL //Access:RW   DataWidth:0x1   0=all the message; 1=partial message.  Chips: BB_A0 BB_B0 K2
70048 #define PSEM_REG_DBG_MODE0_CFG_CYCLE                                                                 0x160141cUL //Access:RW   DataWidth:0x5   In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.  Chips: BB_A0 BB_B0 K2
70049 #define PSEM_REG_DBG_MODE1_CFG                                                                       0x1601420UL //Access:RW   DataWidth:0x1   0=without the data; 1=with the data.  Chips: BB_A0 BB_B0 K2
70050 #define PSEM_REG_DBG_MSG_SRC                                                                         0x1601424UL //Access:RW   DataWidth:0x3   This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.  Chips: BB_A0 BB_B0 K2
70051 #define PSEM_REG_DBG_OUT_DATA                                                                        0x1601500UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
70052 #define PSEM_REG_DBG_OUT_DATA_SIZE                                                                   8
70053 #define PSEM_REG_DBG_OUT_VALID                                                                       0x1601520UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
70054 #define PSEM_REG_DBG_OUT_FRAME                                                                       0x1601524UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
70055 #define PSEM_REG_DBG_SELECT                                                                          0x1601528UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
70056 #define PSEM_REG_DBG_DWORD_ENABLE                                                                    0x160152cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
70057 #define PSEM_REG_DBG_SHIFT                                                                           0x1601530UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
70058 #define PSEM_REG_DBG_FORCE_VALID                                                                     0x1601534UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
70059 #define PSEM_REG_DBG_FORCE_FRAME                                                                     0x1601538UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
70060 #define PSEM_REG_EXT_PAS_FIFO                                                                        0x1608000UL //Access:WB_R DataWidth:0x4a  Provides read-only access of the external passive FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
70061 #define PSEM_REG_EXT_PAS_FIFO_SIZE                                                                   76
70062 #define PSEM_REG_INT_TABLE                                                                           0x1610000UL //Access:RW   DataWidth:0x15  Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address  Chips: BB_A0 BB_B0 K2
70063 #define PSEM_REG_INT_TABLE_SIZE                                                                      256
70064 #define PSEM_REG_PASSIVE_BUFFER                                                                      0x1620000UL //Access:WB   DataWidth:0x80  Read and write to it is just for debugging. Passive buffer memory.  Chips: BB_A0 BB_B0 K2
70065 #define PSEM_REG_PASSIVE_BUFFER_SIZE                                                                 720
70066 #define PSEM_REG_FAST_MEMORY                                                                         0x1640000UL //Access:RW   DataWidth:0x20  See sem_fast.xls for its description.  Chips: BB_A0 BB_B0 K2
70067 #define PSEM_REG_FAST_MEMORY_SIZE                                                                    65536
70068 #define PSEM_REG_PRAM                                                                                0x1680000UL //Access:WB   DataWidth:0x30  Pram memory.  Chips: BB_A0 BB_B0 K2
70069 #define PSEM_REG_PRAM_SIZE                                                                           73728
70070 #define TSEM_REG_ENABLE_IN                                                                           0x1700004UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70071     #define TSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN                                                    (0x1<<0) // Full input from external IF to LS input enable.
70072     #define TSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_SHIFT                                              0
70073     #define TSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN                                                 (0x1<<1) // Read data from external LS IF input enable.
70074     #define TSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_SHIFT                                           1
70075     #define TSEM_REG_ENABLE_IN_FIC_ENABLE_IN                                                         (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
70076     #define TSEM_REG_ENABLE_IN_FIC_ENABLE_IN_SHIFT                                                   2
70077     #define TSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN                                                     (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
70078     #define TSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_SHIFT                                               3
70079     #define TSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN                                                     (0x1<<4) // General interface input enable.
70080     #define TSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_SHIFT                                               4
70081     #define TSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN                                                     (0x1<<5) // External passive write input enable.
70082     #define TSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_SHIFT                                               5
70083     #define TSEM_REG_ENABLE_IN_RAM_ENABLE_IN                                                         (0x1<<6) // Data input enable to RAM.
70084     #define TSEM_REG_ENABLE_IN_RAM_ENABLE_IN_SHIFT                                                   6
70085     #define TSEM_REG_ENABLE_IN_STALL_ENABLE_IN                                                       (0x1<<7) // Enable for stall input from all external STORM instances.
70086     #define TSEM_REG_ENABLE_IN_STALL_ENABLE_IN_SHIFT                                                 7
70087     #define TSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN                                                  (0x1<<8) // Thread ready bus input enable.
70088     #define TSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_SHIFT                                            8
70089     #define TSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN                                                  (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
70090     #define TSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_SHIFT                                            9
70091 #define TSEM_REG_ENABLE_OUT                                                                          0x1700008UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70092     #define TSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT                                                (0x1<<0) // Read request output enable from external LS IF.
70093     #define TSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_SHIFT                                          0
70094     #define TSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT                                                (0x1<<1) // Write request output enable from external LS IF.
70095     #define TSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_SHIFT                                          1
70096     #define TSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT                                                       (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
70097     #define TSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_SHIFT                                                 2
70098     #define TSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT                                                   (0x1<<3) // Passive full output enable.
70099     #define TSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_SHIFT                                             3
70100     #define TSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT                                                       (0x1<<4) // Data output enable to RAM.
70101     #define TSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_SHIFT                                                 4
70102     #define TSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT                                                     (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
70103     #define TSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_SHIFT                                               5
70104 #define TSEM_REG_FIC_DISABLE                                                                         0x170000cUL //Access:RW   DataWidth:0x1   Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
70105 #define TSEM_REG_PAS_DISABLE                                                                         0x1700010UL //Access:RW   DataWidth:0x1   Disables input messages from the passive buffer  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
70106 #define TSEM_REG_INT_STS_0                                                                           0x1700040UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
70107     #define TSEM_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
70108     #define TSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
70109     #define TSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                        (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
70110     #define TSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                  1
70111     #define TSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                      (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
70112     #define TSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                2
70113     #define TSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                        (0x1<<3) // Error in any one of the FIC FIFO is active.
70114     #define TSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                  3
70115     #define TSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
70116     #define TSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_SHIFT                                              4
70117     #define TSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
70118     #define TSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_SHIFT                                              5
70119     #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
70120     #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                          6
70121     #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
70122     #define TSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                           7
70123     #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
70124     #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                          8
70125     #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
70126     #define TSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                           9
70127     #define TSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
70128     #define TSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_SHIFT                                             10
70129     #define TSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
70130     #define TSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                          11
70131     #define TSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
70132     #define TSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_SHIFT                                                12
70133     #define TSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
70134     #define TSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_SHIFT                                                13
70135     #define TSEM_REG_INT_STS_0_CAM_OUT_FIFO                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
70136     #define TSEM_REG_INT_STS_0_CAM_OUT_FIFO_SHIFT                                                    14
70137     #define TSEM_REG_INT_STS_0_FIN_FIFO                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
70138     #define TSEM_REG_INT_STS_0_FIN_FIFO_SHIFT                                                        15
70139     #define TSEM_REG_INT_STS_0_THREAD_FIFO_ERROR                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
70140     #define TSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_SHIFT                                               16
70141     #define TSEM_REG_INT_STS_0_THREAD_OVERRUN                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
70142     #define TSEM_REG_INT_STS_0_THREAD_OVERRUN_SHIFT                                                  17
70143     #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR                                             (0x1<<18) // Error in external store sync FIFO push logic.
70144     #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                       18
70145     #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR                                              (0x1<<19) // Error in external store sync FIFO pop logic.
70146     #define TSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                        19
70147     #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR                                              (0x1<<20) // Error in external load sync FIFO push logic.
70148     #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                        20
70149     #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR                                               (0x1<<21) // Error in external load sync FIFO pop logic.
70150     #define TSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                         21
70151     #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
70152     #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                          22
70153     #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
70154     #define TSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                           23
70155     #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
70156     #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                           24
70157     #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
70158     #define TSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                          25
70159     #define TSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
70160     #define TSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_SHIFT                                             26
70161     #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
70162     #define TSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_SHIFT                                              27
70163     #define TSEM_REG_INT_STS_0_DBG_FIFO_ERROR                                                        (0x1<<28) // Error in slow debug fifo.
70164     #define TSEM_REG_INT_STS_0_DBG_FIFO_ERROR_SHIFT                                                  28
70165     #define TSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
70166     #define TSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_SHIFT                                               29
70167     #define TSEM_REG_INT_STS_0_VFC_INTERRUPT                                                         (0x1<<30) // Error interrupt in VFC block.
70168     #define TSEM_REG_INT_STS_0_VFC_INTERRUPT_SHIFT                                                   30
70169     #define TSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
70170     #define TSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_SHIFT                                              31
70171 #define TSEM_REG_INT_MASK_0                                                                          0x1700044UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
70172     #define TSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.ADDRESS_ERROR .
70173     #define TSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
70174     #define TSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_LAST_ERROR .
70175     #define TSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                 1
70176     #define TSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
70177     #define TSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                               2
70178     #define TSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
70179     #define TSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                 3
70180     #define TSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
70181     #define TSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_SHIFT                                             4
70182     #define TSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
70183     #define TSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_SHIFT                                             5
70184     #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
70185     #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                         6
70186     #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
70187     #define TSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                          7
70188     #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
70189     #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                         8
70190     #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
70191     #define TSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                          9
70192     #define TSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
70193     #define TSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_SHIFT                                            10
70194     #define TSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
70195     #define TSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                         11
70196     #define TSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
70197     #define TSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_SHIFT                                               12
70198     #define TSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
70199     #define TSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_SHIFT                                               13
70200     #define TSEM_REG_INT_MASK_0_CAM_OUT_FIFO                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_OUT_FIFO .
70201     #define TSEM_REG_INT_MASK_0_CAM_OUT_FIFO_SHIFT                                                   14
70202     #define TSEM_REG_INT_MASK_0_FIN_FIFO                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.FIN_FIFO .
70203     #define TSEM_REG_INT_MASK_0_FIN_FIFO_SHIFT                                                       15
70204     #define TSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
70205     #define TSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_SHIFT                                              16
70206     #define TSEM_REG_INT_MASK_0_THREAD_OVERRUN                                                       (0x1<<17) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.THREAD_OVERRUN .
70207     #define TSEM_REG_INT_MASK_0_THREAD_OVERRUN_SHIFT                                                 17
70208     #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
70209     #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                      18
70210     #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
70211     #define TSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                       19
70212     #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
70213     #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                       20
70214     #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
70215     #define TSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                        21
70216     #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
70217     #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                         22
70218     #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
70219     #define TSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                          23
70220     #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR                                                (0x1<<24) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
70221     #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                          24
70222     #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
70223     #define TSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                         25
70224     #define TSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR                                                  (0x1<<26) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
70225     #define TSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_SHIFT                                            26
70226     #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
70227     #define TSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_SHIFT                                             27
70228     #define TSEM_REG_INT_MASK_0_DBG_FIFO_ERROR                                                       (0x1<<28) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
70229     #define TSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_SHIFT                                                 28
70230     #define TSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
70231     #define TSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_SHIFT                                              29
70232     #define TSEM_REG_INT_MASK_0_VFC_INTERRUPT                                                        (0x1<<30) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.VFC_INTERRUPT .
70233     #define TSEM_REG_INT_MASK_0_VFC_INTERRUPT_SHIFT                                                  30
70234     #define TSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR                                                   (0x1<<31) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
70235     #define TSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_SHIFT                                             31
70236 #define TSEM_REG_INT_STS_WR_0                                                                        0x1700048UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
70237     #define TSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
70238     #define TSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
70239     #define TSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                     (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
70240     #define TSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                               1
70241     #define TSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                   (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
70242     #define TSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                             2
70243     #define TSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                     (0x1<<3) // Error in any one of the FIC FIFO is active.
70244     #define TSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                               3
70245     #define TSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR                                                 (0x1<<4) // Error in Ext PAS_FIFO is active.
70246     #define TSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_SHIFT                                           4
70247     #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR                                                 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
70248     #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_SHIFT                                           5
70249     #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR                                             (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
70250     #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                       6
70251     #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR                                              (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
70252     #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                        7
70253     #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR                                             (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
70254     #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                       8
70255     #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR                                              (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
70256     #define TSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                        9
70257     #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR                                                (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
70258     #define TSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                          10
70259     #define TSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR                                             (0x1<<11) // Signals an unknown address in the fast-memory window.
70260     #define TSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                       11
70261     #define TSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO                                                   (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
70262     #define TSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_SHIFT                                             12
70263     #define TSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO                                                   (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
70264     #define TSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_SHIFT                                             13
70265     #define TSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO                                                       (0x1<<14) // Error in CAM_OUT fifo in cam block.
70266     #define TSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_SHIFT                                                 14
70267     #define TSEM_REG_INT_STS_WR_0_FIN_FIFO                                                           (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
70268     #define TSEM_REG_INT_STS_WR_0_FIN_FIFO_SHIFT                                                     15
70269     #define TSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR                                                  (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
70270     #define TSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_SHIFT                                            16
70271     #define TSEM_REG_INT_STS_WR_0_THREAD_OVERRUN                                                     (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
70272     #define TSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_SHIFT                                               17
70273     #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR                                          (0x1<<18) // Error in external store sync FIFO push logic.
70274     #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                    18
70275     #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR                                           (0x1<<19) // Error in external store sync FIFO pop logic.
70276     #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                     19
70277     #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR                                           (0x1<<20) // Error in external load sync FIFO push logic.
70278     #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                     20
70279     #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR                                            (0x1<<21) // Error in external load sync FIFO pop logic.
70280     #define TSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                      21
70281     #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR                                             (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
70282     #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                       22
70283     #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR                                              (0x1<<23) // Error in LS_SYNC_POP FIFO.
70284     #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                        23
70285     #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR                                              (0x1<<24) // Error in LS_SYNC_POP FIFO.
70286     #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                        24
70287     #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR                                             (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
70288     #define TSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                       25
70289     #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR                                                (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
70290     #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                          26
70291     #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR                                                 (0x1<<27) // Error in LS_SYNC_POP FIFO.
70292     #define TSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_SHIFT                                           27
70293     #define TSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR                                                     (0x1<<28) // Error in slow debug fifo.
70294     #define TSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_SHIFT                                               28
70295     #define TSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO                                                  (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
70296     #define TSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_SHIFT                                            29
70297     #define TSEM_REG_INT_STS_WR_0_VFC_INTERRUPT                                                      (0x1<<30) // Error interrupt in VFC block.
70298     #define TSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_SHIFT                                                30
70299     #define TSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR                                                 (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
70300     #define TSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_SHIFT                                           31
70301 #define TSEM_REG_INT_STS_CLR_0                                                                       0x170004cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
70302     #define TSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
70303     #define TSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
70304     #define TSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                    (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
70305     #define TSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                              1
70306     #define TSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                  (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
70307     #define TSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                            2
70308     #define TSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                    (0x1<<3) // Error in any one of the FIC FIFO is active.
70309     #define TSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                              3
70310     #define TSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR                                                (0x1<<4) // Error in Ext PAS_FIFO is active.
70311     #define TSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_SHIFT                                          4
70312     #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR                                                (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
70313     #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_SHIFT                                          5
70314     #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR                                            (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
70315     #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                      6
70316     #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR                                             (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
70317     #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                       7
70318     #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR                                            (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
70319     #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                      8
70320     #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR                                             (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
70321     #define TSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                       9
70322     #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR                                               (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
70323     #define TSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                         10
70324     #define TSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR                                            (0x1<<11) // Signals an unknown address in the fast-memory window.
70325     #define TSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                      11
70326     #define TSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO                                                  (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
70327     #define TSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_SHIFT                                            12
70328     #define TSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO                                                  (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
70329     #define TSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_SHIFT                                            13
70330     #define TSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO                                                      (0x1<<14) // Error in CAM_OUT fifo in cam block.
70331     #define TSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_SHIFT                                                14
70332     #define TSEM_REG_INT_STS_CLR_0_FIN_FIFO                                                          (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
70333     #define TSEM_REG_INT_STS_CLR_0_FIN_FIFO_SHIFT                                                    15
70334     #define TSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR                                                 (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
70335     #define TSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_SHIFT                                           16
70336     #define TSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN                                                    (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
70337     #define TSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_SHIFT                                              17
70338     #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR                                         (0x1<<18) // Error in external store sync FIFO push logic.
70339     #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                   18
70340     #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR                                          (0x1<<19) // Error in external store sync FIFO pop logic.
70341     #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                    19
70342     #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR                                          (0x1<<20) // Error in external load sync FIFO push logic.
70343     #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                    20
70344     #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR                                           (0x1<<21) // Error in external load sync FIFO pop logic.
70345     #define TSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                     21
70346     #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR                                            (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
70347     #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                      22
70348     #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR                                             (0x1<<23) // Error in LS_SYNC_POP FIFO.
70349     #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                       23
70350     #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR                                             (0x1<<24) // Error in LS_SYNC_POP FIFO.
70351     #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                       24
70352     #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR                                            (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
70353     #define TSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                      25
70354     #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR                                               (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
70355     #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                         26
70356     #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR                                                (0x1<<27) // Error in LS_SYNC_POP FIFO.
70357     #define TSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_SHIFT                                          27
70358     #define TSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR                                                    (0x1<<28) // Error in slow debug fifo.
70359     #define TSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_SHIFT                                              28
70360     #define TSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO                                                 (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
70361     #define TSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_SHIFT                                           29
70362     #define TSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT                                                     (0x1<<30) // Error interrupt in VFC block.
70363     #define TSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_SHIFT                                               30
70364     #define TSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR                                                (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
70365     #define TSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_SHIFT                                          31
70366 #define TSEM_REG_INT_STS_1                                                                           0x1700050UL //Access:R    DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70367     #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
70368     #define TSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_SHIFT                                             0
70369     #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
70370     #define TSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_SHIFT                                             1
70371     #define TSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR                                                   (0x1<<2) // The Storm detected an illegal runtime value.
70372     #define TSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_SHIFT                                             2
70373     #define TSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
70374     #define TSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                          3
70375     #define TSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
70376     #define TSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_SHIFT                                           4
70377     #define TSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
70378     #define TSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_SHIFT                                           5
70379     #define TSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
70380     #define TSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_SHIFT                                            6
70381     #define TSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
70382     #define TSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_SHIFT                                            7
70383     #define TSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
70384     #define TSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_SHIFT                                               8
70385     #define TSEM_REG_INT_STS_1_INVLD_FOC_ERROR                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
70386     #define TSEM_REG_INT_STS_1_INVLD_FOC_ERROR_SHIFT                                                 9
70387     #define TSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
70388     #define TSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_SHIFT                                                10
70389     #define TSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
70390     #define TSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_SHIFT                                             11
70391     #define TSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
70392     #define TSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_SHIFT                                            12
70393 #define TSEM_REG_INT_MASK_1                                                                          0x1700054UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70394     #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
70395     #define TSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_SHIFT                                            0
70396     #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
70397     #define TSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_SHIFT                                            1
70398     #define TSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
70399     #define TSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_SHIFT                                            2
70400     #define TSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
70401     #define TSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                         3
70402     #define TSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
70403     #define TSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_SHIFT                                          4
70404     #define TSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
70405     #define TSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_SHIFT                                          5
70406     #define TSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
70407     #define TSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_SHIFT                                           6
70408     #define TSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
70409     #define TSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_SHIFT                                           7
70410     #define TSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
70411     #define TSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_SHIFT                                              8
70412     #define TSEM_REG_INT_MASK_1_INVLD_FOC_ERROR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
70413     #define TSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_SHIFT                                                9
70414     #define TSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
70415     #define TSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_SHIFT                                               10
70416     #define TSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
70417     #define TSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_SHIFT                                            11
70418     #define TSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: TSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
70419     #define TSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_SHIFT                                           12
70420 #define TSEM_REG_INT_STS_WR_1                                                                        0x1700058UL //Access:WR   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70421     #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN                                                (0x1<<0) // An underflow error was detected in the Storm stack.
70422     #define TSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_SHIFT                                          0
70423     #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN                                                (0x1<<1) // An overflow error was detected in the Storm stack.
70424     #define TSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_SHIFT                                          1
70425     #define TSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR                                                (0x1<<2) // The Storm detected an illegal runtime value.
70426     #define TSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_SHIFT                                          2
70427     #define TSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR                                             (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
70428     #define TSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                       3
70429     #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR                                              (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
70430     #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                        4
70431     #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR                                              (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
70432     #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                        5
70433     #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR                                               (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
70434     #define TSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_SHIFT                                         6
70435     #define TSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR                                               (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
70436     #define TSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_SHIFT                                         7
70437     #define TSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR                                                  (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
70438     #define TSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_SHIFT                                            8
70439     #define TSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR                                                    (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
70440     #define TSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_SHIFT                                              9
70441     #define TSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR                                                   (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
70442     #define TSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_SHIFT                                             10
70443     #define TSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR                                                (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
70444     #define TSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_SHIFT                                          11
70445     #define TSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR                                               (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
70446     #define TSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_SHIFT                                         12
70447 #define TSEM_REG_INT_STS_CLR_1                                                                       0x170005cUL //Access:RC   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70448     #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN                                               (0x1<<0) // An underflow error was detected in the Storm stack.
70449     #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_SHIFT                                         0
70450     #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN                                               (0x1<<1) // An overflow error was detected in the Storm stack.
70451     #define TSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_SHIFT                                         1
70452     #define TSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR                                               (0x1<<2) // The Storm detected an illegal runtime value.
70453     #define TSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_SHIFT                                         2
70454     #define TSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR                                            (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
70455     #define TSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                      3
70456     #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR                                             (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
70457     #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                       4
70458     #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR                                             (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
70459     #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                       5
70460     #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR                                              (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
70461     #define TSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_SHIFT                                        6
70462     #define TSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR                                              (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
70463     #define TSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_SHIFT                                        7
70464     #define TSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR                                                 (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
70465     #define TSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_SHIFT                                           8
70466     #define TSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR                                                   (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
70467     #define TSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_SHIFT                                             9
70468     #define TSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR                                                  (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
70469     #define TSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_SHIFT                                            10
70470     #define TSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR                                               (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
70471     #define TSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_SHIFT                                         11
70472     #define TSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR                                              (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
70473     #define TSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_SHIFT                                        12
70474 #define TSEM_REG_PRTY_MASK                                                                           0x17000ccUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70475     #define TSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                  (0x1<<0) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
70476     #define TSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                            0
70477     #define TSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                 (0x1<<1) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
70478     #define TSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                           1
70479     #define TSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                  (0x1<<2) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
70480     #define TSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                            2
70481 #define TSEM_REG_PRTY_MASK_H_0                                                                       0x1700204UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70482     #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
70483     #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT                                       0
70484     #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
70485     #define TSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT                                       1
70486     #define TSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
70487     #define TSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           2
70488     #define TSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
70489     #define TSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           3
70490     #define TSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
70491     #define TSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           4
70492     #define TSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: TSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
70493     #define TSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           5
70494 #define TSEM_REG_MEM_ECC_EVENTS                                                                      0x170021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
70495 #define TSEM_REG_MEM004_I_MEM_DFT_K2                                                                 0x1700224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsem.i_sem_core.i_sem_slow.i_sem_slow_int_table_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
70496 #define TSEM_REG_MEM005_I_MEM_DFT_K2                                                                 0x1700228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
70497 #define TSEM_REG_MEM002_I_MEM_DFT_K2                                                                 0x170022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsem.i_sem_core.i_sem_slow.i_sem_slow_ext_pas_fifo_wrap.DEFAULT_EXT_PAS_FIFO_GEN_IF.i_sem_slow_ext_pas_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
70498 #define TSEM_REG_MEM003_I_MEM_DFT_K2                                                                 0x1700230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsem.i_sem_core.i_sem_slow.i_sem_slow_fic_fifo_wrap.DEFAULT_FIC_FIFO_MEM_GEN_IF.i_sem_slow_fic0_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
70499 #define TSEM_REG_MEM001_I_MEM_DFT_K2                                                                 0x1700234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance tsem.i_sem_core.i_sem_slow.i_sem_slow_dbg_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
70500 #define TSEM_REG_ARB_CYCLE_SIZE                                                                      0x1700400UL //Access:RW   DataWidth:0x5   The number of time_slots in the arbitration cycle.  Chips: BB_A0 BB_B0 K2
70501 #define TSEM_REG_VF_ERROR                                                                            0x1700408UL //Access:WR   DataWidth:0x1   This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.  Chips: BB_A0 BB_B0 K2
70502 #define TSEM_REG_PF_ERROR                                                                            0x170040cUL //Access:WR   DataWidth:0x1   This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.  Chips: BB_A0 BB_B0 K2
70503 #define TSEM_REG_VF_ERR_VECTOR                                                                       0x1700420UL //Access:WB_R DataWidth:0xc0  This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.  Chips: BB_A0 BB_B0 K2
70504 #define TSEM_REG_VF_ERR_VECTOR_SIZE                                                                  8
70505 #define TSEM_REG_PF_ERR_VECTOR                                                                       0x1700440UL //Access:R    DataWidth:0x10  This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.  Chips: BB_A0 BB_B0 K2
70506 #define TSEM_REG_CLEAR_STALL                                                                         0x1700444UL //Access:RW   DataWidth:0x1   Clear stall signal sent from local storm to external storms.  Chips: BB_A0 BB_B0 K2
70507 #define TSEM_REG_EXCEPTION_INT                                                                       0x1700448UL //Access:RW   DataWidth:0x10  Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.  Chips: BB_A0 BB_B0 K2
70508 #define TSEM_REG_EXT_STORE_FREE_ENTRIES                                                              0x170044cUL //Access:R    DataWidth:0x6   Number of free entries in the external STORE sync FIFO.  Chips: BB_A0 BB_B0 K2
70509 #define TSEM_REG_GPI_DATA                                                                            0x1700450UL //Access:R    DataWidth:0x20  Used to read the GPI input signals.  Chips: BB_A0 BB_B0 K2
70510 #define TSEM_REG_GPRE_SAMP_PERIOD                                                                    0x1700454UL //Access:RW   DataWidth:0x4   Defines the number of system clocks from one sample of GPRE sync data and the next.  Chips: BB_A0 BB_B0 K2
70511 #define TSEM_REG_ALLOW_LP_SLEEP_THRD                                                                 0x1700458UL //Access:RW   DataWidth:0x1   When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.  Chips: BB_A0 BB_B0 K2
70512 #define TSEM_REG_ECO_RESERVED                                                                        0x170045cUL //Access:RW   DataWidth:0x8   This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: BB_A0 BB_B0 K2
70513 #define TSEM_REG_FIC_GAP_VECT                                                                        0x1700500UL //Access:WB   DataWidth:0x2c  This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.  Chips: BB_A0 BB_B0 K2
70514 #define TSEM_REG_FIC_GAP_VECT_SIZE                                                                   18
70515 #define TSEM_REG_FIC_FIFO                                                                            0x1700580UL //Access:WB_R DataWidth:0x80  Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.  Chips: BB_A0 BB_B0 K2
70516 #define TSEM_REG_FIC_FIFO_SIZE                                                                       4
70517 #define TSEM_REG_FIC_MIN_MSG                                                                         0x1700600UL //Access:RW   DataWidth:0x6   Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.  Chips: BB_A0 BB_B0 K2
70518 #define TSEM_REG_FIC_EMPTY_CT_MODE                                                                   0x1700620UL //Access:RW   DataWidth:0x1   When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.  Chips: BB_A0 BB_B0 K2
70519 #define TSEM_REG_FIC_EMPTY_CT_CNT                                                                    0x1700624UL //Access:RC   DataWidth:0x18  Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.  Chips: BB_A0 BB_B0 K2
70520 #define TSEM_REG_FOC_CREDIT                                                                          0x1700680UL //Access:RW   DataWidth:0x8   Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.  Chips: BB_A0 BB_B0 K2
70521 #define TSEM_REG_FOC_CREDIT_SIZE                                                                     2
70522 #define TSEM_REG_FULL_FOC_DRA_STRT_EN                                                                0x17006c0UL //Access:RW   DataWidth:0x1   When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.  Chips: BB_A0 BB_B0 K2
70523 #define TSEM_REG_FIN_COMMAND                                                                         0x1700700UL //Access:WB_R DataWidth:0x164 Last fin command that was read from fifo. Its spelling in FIN_FIFO register.  Chips: BB_A0 BB_B0 K2
70524 #define TSEM_REG_FIN_COMMAND_SIZE                                                                    16
70525 #define TSEM_REG_FIN_FIFO                                                                            0x1700800UL //Access:WB_R DataWidth:0x164 READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.  Chips: BB_A0 BB_B0 K2
70526 #define TSEM_REG_FIN_FIFO_SIZE                                                                       16
70527 #define TSEM_REG_INVLD_PAS_WR_EN                                                                     0x1700900UL //Access:RW   DataWidth:0x1   When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.  Chips: BB_A0 BB_B0 K2
70528 #define TSEM_REG_ARBITER_REQUEST                                                                     0x1700980UL //Access:R    DataWidth:0x5   Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
70529 #define TSEM_REG_ARBITER_SELECT                                                                      0x1700984UL //Access:R    DataWidth:0x5   Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
70530 #define TSEM_REG_ARBITER_SLOT                                                                        0x1700988UL //Access:R    DataWidth:0x5   Dra arbiter last slot.  Chips: BB_A0 BB_B0 K2
70531 #define TSEM_REG_ARB_AS_DEF                                                                          0x1700a00UL //Access:RW   DataWidth:0x3   Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.  Chips: BB_A0 BB_B0 K2
70532 #define TSEM_REG_ARB_AS_DEF_SIZE                                                                     32
70533 #define TSEM_REG_ARB_TS_AS                                                                           0x1700a80UL //Access:RW   DataWidth:0x2   Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].  Chips: BB_A0 BB_B0 K2
70534 #define TSEM_REG_ARB_TS_AS_SIZE                                                                      20
70535 #define TSEM_REG_NUM_OF_THREADS                                                                      0x1700b00UL //Access:R    DataWidth:0x5   The number of curretnly free threads.  Chips: BB_A0 BB_B0 K2
70536 #define TSEM_REG_THREAD_ERROR                                                                        0x1700b04UL //Access:R    DataWidth:0x18  Thread error indication.  Chips: BB_A0 BB_B0 K2
70537 #define TSEM_REG_THREAD_RDY                                                                          0x1700b08UL //Access:R    DataWidth:0x18  Thread ready indication.  Chips: BB_A0 BB_B0 K2
70538 #define TSEM_REG_THREAD_SET_NUM                                                                      0x1700b0cUL //Access:W    DataWidth:0x5   Thread ID. Write thread ID will set ready indication for this thread ID.  Chips: BB_A0 BB_B0 K2
70539 #define TSEM_REG_THREAD_VALID                                                                        0x1700b10UL //Access:R    DataWidth:0x18  Valid sleeping threads.  Chips: BB_A0 BB_B0 K2
70540 #define TSEM_REG_THREADS_LIST                                                                        0x1700b14UL //Access:RW   DataWidth:0x18  List of free threads.  Chips: BB_A0 BB_B0 K2
70541 #define TSEM_REG_ORDER_HEAD                                                                          0x1700c00UL //Access:RW   DataWidth:0x5   This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.  Chips: BB_A0 BB_B0 K2
70542 #define TSEM_REG_ORDER_HEAD_SIZE                                                                     24
70543 #define TSEM_REG_ORDER_TAIL                                                                          0x1700c80UL //Access:RW   DataWidth:0x5   This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
70544 #define TSEM_REG_ORDER_TAIL_SIZE                                                                     24
70545 #define TSEM_REG_ORDER_EMPTY                                                                         0x1700d00UL //Access:RW   DataWidth:0x1   This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
70546 #define TSEM_REG_ORDER_EMPTY_SIZE                                                                    24
70547 #define TSEM_REG_ORDER_LL_REG                                                                        0x1700d80UL //Access:RW   DataWidth:0x5   This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..  Chips: BB_A0 BB_B0 K2
70548 #define TSEM_REG_ORDER_LL_REG_SIZE                                                                   24
70549 #define TSEM_REG_ORDER_POP_EN                                                                        0x1700e00UL //Access:RW   DataWidth:0x18  Provides access to the thread ordering queue pop-enable vector.  Chips: BB_A0 BB_B0 K2
70550 #define TSEM_REG_ORDER_WAKE_EN                                                                       0x1700e08UL //Access:RW   DataWidth:0x18  Provides access to the thread ordering queue wake-enable vector.  Chips: BB_A0 BB_B0 K2
70551 #define TSEM_REG_PF_NUM_ORDER_BASE                                                                   0x1700e10UL //Access:RW   DataWidth:0x5   This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.  Chips: BB_A0 BB_B0 K2
70552 #define TSEM_REG_DBG_ALM_FULL                                                                        0x1701000UL //Access:RW   DataWidth:0x6   Almost full for slow debug fifo.  Chips: BB_A0 BB_B0 K2
70553 #define TSEM_REG_PASSIVE_ALM_FULL                                                                    0x1701004UL //Access:RW   DataWidth:0x5   The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.  Chips: BB_A0 BB_B0 K2
70554 #define TSEM_REG_SYNC_DRA_WR_ALM_FULL                                                                0x1701008UL //Access:RW   DataWidth:0x5   Almost full for sync dra_wr fifo (data from DRA to STORM).  Chips: BB_A0 BB_B0 K2
70555 #define TSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                0x170100cUL //Access:RW   DataWidth:0x6   Almost full for sync ram_wr fifo (data from EXT_IF to STORM).  Chips: BB_A0 BB_B0 K2
70556 #define TSEM_REG_DRA_EMPTY                                                                           0x1701100UL //Access:R    DataWidth:0x1   Dra_empty.  Chips: BB_A0 BB_B0 K2
70557 #define TSEM_REG_EXT_PAS_EMPTY                                                                       0x1701104UL //Access:R    DataWidth:0x1   EXT_PAS FIFO empty in sem_slow.  Chips: BB_A0 BB_B0 K2
70558 #define TSEM_REG_FIC_EMPTY                                                                           0x1701120UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO empty in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
70559 #define TSEM_REG_SLOW_DBG_EMPTY                                                                      0x1701140UL //Access:R    DataWidth:0x1   DBG FIFO is empty in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
70560 #define TSEM_REG_SLOW_DRA_FIN_EMPTY                                                                  0x1701144UL //Access:R    DataWidth:0x1   FIN fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70561 #define TSEM_REG_SLOW_DRA_RD_EMPTY                                                                   0x1701148UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70562 #define TSEM_REG_SLOW_DRA_WR_EMPTY                                                                   0x170114cUL //Access:R    DataWidth:0x1   DRA_WR push fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70563 #define TSEM_REG_SLOW_EXT_STORE_EMPTY                                                                0x1701150UL //Access:R    DataWidth:0x1   EXT_STORE FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70564 #define TSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                 0x1701154UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70565 #define TSEM_REG_SLOW_RAM_RD_EMPTY                                                                   0x1701158UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70566 #define TSEM_REG_SLOW_RAM_WR_EMPTY                                                                   0x170115cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70567 #define TSEM_REG_SYNC_DBG_EMPTY                                                                      0x1701160UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
70568 #define TSEM_REG_THREAD_FIFO_EMPTY                                                                   0x1701164UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
70569 #define TSEM_REG_ORD_ID_FIFO_EMPTY                                                                   0x1701168UL //Access:R    DataWidth:0x1   Indicates that the order ID fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
70570 #define TSEM_REG_EXT_PAS_FULL                                                                        0x1701200UL //Access:R    DataWidth:0x1   EXT_PAS FIFO Full in sem_slow.  Chips: BB_A0 BB_B0 K2
70571 #define TSEM_REG_EXT_STORE_IF_FULL                                                                   0x1701204UL //Access:R    DataWidth:0x1   EXT_STORE IF is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70572 #define TSEM_REG_FIC_FULL                                                                            0x1701220UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO full in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
70573 #define TSEM_REG_PAS_IF_FULL                                                                         0x1701240UL //Access:R    DataWidth:0x1   Full from passive buffer asserted toward SDM.  Chips: BB_A0 BB_B0 K2
70574 #define TSEM_REG_RAM_IF_FULL                                                                         0x1701244UL //Access:R    DataWidth:0x1   EXT_RAM IF is full in sem_slow_ls_ram.  Chips: BB_A0 BB_B0 K2
70575 #define TSEM_REG_SLOW_DBG_ALM_FULL                                                                   0x1701248UL //Access:R    DataWidth:0x1   DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.  Chips: BB_A0 BB_B0 K2
70576 #define TSEM_REG_SLOW_DBG_FULL                                                                       0x170124cUL //Access:R    DataWidth:0x1   DBG FIFO is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
70577 #define TSEM_REG_SLOW_DRA_FIN_FULL                                                                   0x1701250UL //Access:R    DataWidth:0x1   FIN fifo is full in sem_slow_dra_sync (never may be active).  Chips: BB_A0 BB_B0 K2
70578 #define TSEM_REG_SLOW_DRA_RD_FULL                                                                    0x1701254UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70579 #define TSEM_REG_SLOW_DRA_WR_FULL                                                                    0x1701258UL //Access:R    DataWidth:0x1   DRA_WR push fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
70580 #define TSEM_REG_SLOW_EXT_STORE_FULL                                                                 0x170125cUL //Access:R    DataWidth:0x1   EXT_STORE FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70581 #define TSEM_REG_SLOW_EXT_LOAD_FULL                                                                  0x1701260UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70582 #define TSEM_REG_SLOW_RAM_RD_FULL                                                                    0x1701264UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70583 #define TSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                0x1701268UL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70584 #define TSEM_REG_SLOW_RAM_WR_FULL                                                                    0x170126cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
70585 #define TSEM_REG_SYNC_DBG_FULL                                                                       0x1701270UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is full in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
70586 #define TSEM_REG_THREAD_FIFO_FULL                                                                    0x1701274UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
70587 #define TSEM_REG_ORD_ID_FIFO_FULL                                                                    0x1701278UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
70588 #define TSEM_REG_THREAD_INTER_CNT                                                                    0x1701300UL //Access:RW   DataWidth:0x10  Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.  Chips: BB_A0 BB_B0 K2
70589 #define TSEM_REG_THREAD_INTER_CNT_ENABLE                                                             0x1701304UL //Access:RW   DataWidth:0x1   Enable for start count of thread_inter_cnt.  Chips: BB_A0 BB_B0 K2
70590 #define TSEM_REG_THREAD_ORUN_NUM                                                                     0x1701308UL //Access:R    DataWidth:0x18  Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.  Chips: BB_A0 BB_B0 K2
70591 #define TSEM_REG_SLOW_DBG_ACTIVE                                                                     0x1701400UL //Access:RW   DataWidth:0x1   Debug mode is active.  Chips: BB_A0 BB_B0 K2
70592 #define TSEM_REG_SLOW_DBG_MODE                                                                       0x1701404UL //Access:RW   DataWidth:0x3   Debug mode for slow debug bus.  Chips: BB_A0 BB_B0 K2
70593 #define TSEM_REG_DBG_FRAME_MODE                                                                      0x1701408UL //Access:RW   DataWidth:0x2   Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.  Chips: BB_A0 BB_B0 K2
70594 #define TSEM_REG_DBG_EACH_CYLE                                                                       0x170140cUL //Access:RW   DataWidth:0x1   0=output every cycle; 1= output only when there is a change.  Chips: BB_A0 BB_B0 K2
70595 #define TSEM_REG_DBG_GPRE_VECT                                                                       0x1701410UL //Access:RW   DataWidth:0x8   This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].  Chips: BB_A0 BB_B0 K2
70596 #define TSEM_REG_DBG_IF_FULL                                                                         0x1701414UL //Access:R    DataWidth:0x1   DBG IF is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
70597 #define TSEM_REG_DBG_MODE0_CFG                                                                       0x1701418UL //Access:RW   DataWidth:0x1   0=all the message; 1=partial message.  Chips: BB_A0 BB_B0 K2
70598 #define TSEM_REG_DBG_MODE0_CFG_CYCLE                                                                 0x170141cUL //Access:RW   DataWidth:0x5   In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.  Chips: BB_A0 BB_B0 K2
70599 #define TSEM_REG_DBG_MODE1_CFG                                                                       0x1701420UL //Access:RW   DataWidth:0x1   0=without the data; 1=with the data.  Chips: BB_A0 BB_B0 K2
70600 #define TSEM_REG_DBG_MSG_SRC                                                                         0x1701424UL //Access:RW   DataWidth:0x3   This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.  Chips: BB_A0 BB_B0 K2
70601 #define TSEM_REG_DBG_OUT_DATA                                                                        0x1701500UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
70602 #define TSEM_REG_DBG_OUT_DATA_SIZE                                                                   8
70603 #define TSEM_REG_DBG_OUT_VALID                                                                       0x1701520UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
70604 #define TSEM_REG_DBG_OUT_FRAME                                                                       0x1701524UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
70605 #define TSEM_REG_DBG_SELECT                                                                          0x1701528UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
70606 #define TSEM_REG_DBG_DWORD_ENABLE                                                                    0x170152cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
70607 #define TSEM_REG_DBG_SHIFT                                                                           0x1701530UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
70608 #define TSEM_REG_DBG_FORCE_VALID                                                                     0x1701534UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
70609 #define TSEM_REG_DBG_FORCE_FRAME                                                                     0x1701538UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
70610 #define TSEM_REG_EXT_PAS_FIFO                                                                        0x1708000UL //Access:WB_R DataWidth:0x4d  Provides read-only access of the external passive FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
70611 #define TSEM_REG_EXT_PAS_FIFO_SIZE                                                                   76
70612 #define TSEM_REG_INT_TABLE                                                                           0x1710000UL //Access:RW   DataWidth:0x15  Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address  Chips: BB_A0 BB_B0 K2
70613 #define TSEM_REG_INT_TABLE_SIZE                                                                      256
70614 #define TSEM_REG_PASSIVE_BUFFER                                                                      0x1720000UL //Access:WB   DataWidth:0x80  Read and write to it is just for debugging. Passive buffer memory.  Chips: BB_A0 BB_B0 K2
70615 #define TSEM_REG_PASSIVE_BUFFER_SIZE                                                                 4320
70616 #define TSEM_REG_FAST_MEMORY                                                                         0x1740000UL //Access:RW   DataWidth:0x20  See sem_fast.xls for its description.  Chips: BB_A0 BB_B0 K2
70617 #define TSEM_REG_FAST_MEMORY_SIZE                                                                    65536
70618 #define TSEM_REG_PRAM                                                                                0x1780000UL //Access:WB   DataWidth:0x30  Pram memory.  Chips: BB_A0 BB_B0 K2
70619 #define TSEM_REG_PRAM_SIZE                                                                           73728
70620 #define MSEM_REG_ENABLE_IN                                                                           0x1800004UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70621     #define MSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN                                                    (0x1<<0) // Full input from external IF to LS input enable.
70622     #define MSEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_SHIFT                                              0
70623     #define MSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN                                                 (0x1<<1) // Read data from external LS IF input enable.
70624     #define MSEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_SHIFT                                           1
70625     #define MSEM_REG_ENABLE_IN_FIC_ENABLE_IN                                                         (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
70626     #define MSEM_REG_ENABLE_IN_FIC_ENABLE_IN_SHIFT                                                   2
70627     #define MSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN                                                     (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
70628     #define MSEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_SHIFT                                               3
70629     #define MSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN                                                     (0x1<<4) // General interface input enable.
70630     #define MSEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_SHIFT                                               4
70631     #define MSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN                                                     (0x1<<5) // External passive write input enable.
70632     #define MSEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_SHIFT                                               5
70633     #define MSEM_REG_ENABLE_IN_RAM_ENABLE_IN                                                         (0x1<<6) // Data input enable to RAM.
70634     #define MSEM_REG_ENABLE_IN_RAM_ENABLE_IN_SHIFT                                                   6
70635     #define MSEM_REG_ENABLE_IN_STALL_ENABLE_IN                                                       (0x1<<7) // Enable for stall input from all external STORM instances.
70636     #define MSEM_REG_ENABLE_IN_STALL_ENABLE_IN_SHIFT                                                 7
70637     #define MSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN                                                  (0x1<<8) // Thread ready bus input enable.
70638     #define MSEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_SHIFT                                            8
70639     #define MSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN                                                  (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
70640     #define MSEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_SHIFT                                            9
70641 #define MSEM_REG_ENABLE_OUT                                                                          0x1800008UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70642     #define MSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT                                                (0x1<<0) // Read request output enable from external LS IF.
70643     #define MSEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_SHIFT                                          0
70644     #define MSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT                                                (0x1<<1) // Write request output enable from external LS IF.
70645     #define MSEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_SHIFT                                          1
70646     #define MSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT                                                       (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
70647     #define MSEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_SHIFT                                                 2
70648     #define MSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT                                                   (0x1<<3) // Passive full output enable.
70649     #define MSEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_SHIFT                                             3
70650     #define MSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT                                                       (0x1<<4) // Data output enable to RAM.
70651     #define MSEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_SHIFT                                                 4
70652     #define MSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT                                                     (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
70653     #define MSEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_SHIFT                                               5
70654 #define MSEM_REG_FIC_DISABLE                                                                         0x180000cUL //Access:RW   DataWidth:0x1   Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
70655 #define MSEM_REG_PAS_DISABLE                                                                         0x1800010UL //Access:RW   DataWidth:0x1   Disables input messages from the passive buffer  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
70656 #define MSEM_REG_INT_STS_0                                                                           0x1800040UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
70657     #define MSEM_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
70658     #define MSEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
70659     #define MSEM_REG_INT_STS_0_FIC_LAST_ERROR                                                        (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
70660     #define MSEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                  1
70661     #define MSEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                      (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
70662     #define MSEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                2
70663     #define MSEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                        (0x1<<3) // Error in any one of the FIC FIFO is active.
70664     #define MSEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                  3
70665     #define MSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
70666     #define MSEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_SHIFT                                              4
70667     #define MSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
70668     #define MSEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_SHIFT                                              5
70669     #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
70670     #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                          6
70671     #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
70672     #define MSEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                           7
70673     #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
70674     #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                          8
70675     #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
70676     #define MSEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                           9
70677     #define MSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
70678     #define MSEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_SHIFT                                             10
70679     #define MSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
70680     #define MSEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                          11
70681     #define MSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
70682     #define MSEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_SHIFT                                                12
70683     #define MSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
70684     #define MSEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_SHIFT                                                13
70685     #define MSEM_REG_INT_STS_0_CAM_OUT_FIFO                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
70686     #define MSEM_REG_INT_STS_0_CAM_OUT_FIFO_SHIFT                                                    14
70687     #define MSEM_REG_INT_STS_0_FIN_FIFO                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
70688     #define MSEM_REG_INT_STS_0_FIN_FIFO_SHIFT                                                        15
70689     #define MSEM_REG_INT_STS_0_THREAD_FIFO_ERROR                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
70690     #define MSEM_REG_INT_STS_0_THREAD_FIFO_ERROR_SHIFT                                               16
70691     #define MSEM_REG_INT_STS_0_THREAD_OVERRUN                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
70692     #define MSEM_REG_INT_STS_0_THREAD_OVERRUN_SHIFT                                                  17
70693     #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR                                             (0x1<<18) // Error in external store sync FIFO push logic.
70694     #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                       18
70695     #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR                                              (0x1<<19) // Error in external store sync FIFO pop logic.
70696     #define MSEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                        19
70697     #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR                                              (0x1<<20) // Error in external load sync FIFO push logic.
70698     #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                        20
70699     #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR                                               (0x1<<21) // Error in external load sync FIFO pop logic.
70700     #define MSEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                         21
70701     #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
70702     #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                          22
70703     #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
70704     #define MSEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                           23
70705     #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
70706     #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                           24
70707     #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
70708     #define MSEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                          25
70709     #define MSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
70710     #define MSEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_SHIFT                                             26
70711     #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
70712     #define MSEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_SHIFT                                              27
70713     #define MSEM_REG_INT_STS_0_DBG_FIFO_ERROR                                                        (0x1<<28) // Error in slow debug fifo.
70714     #define MSEM_REG_INT_STS_0_DBG_FIFO_ERROR_SHIFT                                                  28
70715     #define MSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
70716     #define MSEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_SHIFT                                               29
70717     #define MSEM_REG_INT_STS_0_VFC_INTERRUPT                                                         (0x1<<30) // Error interrupt in VFC block.
70718     #define MSEM_REG_INT_STS_0_VFC_INTERRUPT_SHIFT                                                   30
70719     #define MSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
70720     #define MSEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_SHIFT                                              31
70721 #define MSEM_REG_INT_MASK_0                                                                          0x1800044UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
70722     #define MSEM_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.ADDRESS_ERROR .
70723     #define MSEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
70724     #define MSEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_LAST_ERROR .
70725     #define MSEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                 1
70726     #define MSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
70727     #define MSEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                               2
70728     #define MSEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIC_FIFO_ERROR .
70729     #define MSEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                 3
70730     #define MSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
70731     #define MSEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_SHIFT                                             4
70732     #define MSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
70733     #define MSEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_SHIFT                                             5
70734     #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
70735     #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                         6
70736     #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
70737     #define MSEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                          7
70738     #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
70739     #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                         8
70740     #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
70741     #define MSEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                          9
70742     #define MSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
70743     #define MSEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_SHIFT                                            10
70744     #define MSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
70745     #define MSEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                         11
70746     #define MSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
70747     #define MSEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_SHIFT                                               12
70748     #define MSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
70749     #define MSEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_SHIFT                                               13
70750     #define MSEM_REG_INT_MASK_0_CAM_OUT_FIFO                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_OUT_FIFO .
70751     #define MSEM_REG_INT_MASK_0_CAM_OUT_FIFO_SHIFT                                                   14
70752     #define MSEM_REG_INT_MASK_0_FIN_FIFO                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.FIN_FIFO .
70753     #define MSEM_REG_INT_MASK_0_FIN_FIFO_SHIFT                                                       15
70754     #define MSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
70755     #define MSEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_SHIFT                                              16
70756     #define MSEM_REG_INT_MASK_0_THREAD_OVERRUN                                                       (0x1<<17) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.THREAD_OVERRUN .
70757     #define MSEM_REG_INT_MASK_0_THREAD_OVERRUN_SHIFT                                                 17
70758     #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
70759     #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                      18
70760     #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
70761     #define MSEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                       19
70762     #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
70763     #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                       20
70764     #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
70765     #define MSEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                        21
70766     #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
70767     #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                         22
70768     #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
70769     #define MSEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                          23
70770     #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR                                                (0x1<<24) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
70771     #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                          24
70772     #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
70773     #define MSEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                         25
70774     #define MSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR                                                  (0x1<<26) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
70775     #define MSEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_SHIFT                                            26
70776     #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
70777     #define MSEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_SHIFT                                             27
70778     #define MSEM_REG_INT_MASK_0_DBG_FIFO_ERROR                                                       (0x1<<28) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.DBG_FIFO_ERROR .
70779     #define MSEM_REG_INT_MASK_0_DBG_FIFO_ERROR_SHIFT                                                 28
70780     #define MSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
70781     #define MSEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_SHIFT                                              29
70782     #define MSEM_REG_INT_MASK_0_VFC_INTERRUPT                                                        (0x1<<30) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.VFC_INTERRUPT .
70783     #define MSEM_REG_INT_MASK_0_VFC_INTERRUPT_SHIFT                                                  30
70784     #define MSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR                                                   (0x1<<31) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
70785     #define MSEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_SHIFT                                             31
70786 #define MSEM_REG_INT_STS_WR_0                                                                        0x1800048UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
70787     #define MSEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
70788     #define MSEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
70789     #define MSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                     (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
70790     #define MSEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                               1
70791     #define MSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                   (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
70792     #define MSEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                             2
70793     #define MSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                     (0x1<<3) // Error in any one of the FIC FIFO is active.
70794     #define MSEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                               3
70795     #define MSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR                                                 (0x1<<4) // Error in Ext PAS_FIFO is active.
70796     #define MSEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_SHIFT                                           4
70797     #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR                                                 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
70798     #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_SHIFT                                           5
70799     #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR                                             (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
70800     #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                       6
70801     #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR                                              (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
70802     #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                        7
70803     #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR                                             (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
70804     #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                       8
70805     #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR                                              (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
70806     #define MSEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                        9
70807     #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR                                                (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
70808     #define MSEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                          10
70809     #define MSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR                                             (0x1<<11) // Signals an unknown address in the fast-memory window.
70810     #define MSEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                       11
70811     #define MSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO                                                   (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
70812     #define MSEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_SHIFT                                             12
70813     #define MSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO                                                   (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
70814     #define MSEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_SHIFT                                             13
70815     #define MSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO                                                       (0x1<<14) // Error in CAM_OUT fifo in cam block.
70816     #define MSEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_SHIFT                                                 14
70817     #define MSEM_REG_INT_STS_WR_0_FIN_FIFO                                                           (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
70818     #define MSEM_REG_INT_STS_WR_0_FIN_FIFO_SHIFT                                                     15
70819     #define MSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR                                                  (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
70820     #define MSEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_SHIFT                                            16
70821     #define MSEM_REG_INT_STS_WR_0_THREAD_OVERRUN                                                     (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
70822     #define MSEM_REG_INT_STS_WR_0_THREAD_OVERRUN_SHIFT                                               17
70823     #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR                                          (0x1<<18) // Error in external store sync FIFO push logic.
70824     #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                    18
70825     #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR                                           (0x1<<19) // Error in external store sync FIFO pop logic.
70826     #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                     19
70827     #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR                                           (0x1<<20) // Error in external load sync FIFO push logic.
70828     #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                     20
70829     #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR                                            (0x1<<21) // Error in external load sync FIFO pop logic.
70830     #define MSEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                      21
70831     #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR                                             (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
70832     #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                       22
70833     #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR                                              (0x1<<23) // Error in LS_SYNC_POP FIFO.
70834     #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                        23
70835     #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR                                              (0x1<<24) // Error in LS_SYNC_POP FIFO.
70836     #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                        24
70837     #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR                                             (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
70838     #define MSEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                       25
70839     #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR                                                (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
70840     #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                          26
70841     #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR                                                 (0x1<<27) // Error in LS_SYNC_POP FIFO.
70842     #define MSEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_SHIFT                                           27
70843     #define MSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR                                                     (0x1<<28) // Error in slow debug fifo.
70844     #define MSEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_SHIFT                                               28
70845     #define MSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO                                                  (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
70846     #define MSEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_SHIFT                                            29
70847     #define MSEM_REG_INT_STS_WR_0_VFC_INTERRUPT                                                      (0x1<<30) // Error interrupt in VFC block.
70848     #define MSEM_REG_INT_STS_WR_0_VFC_INTERRUPT_SHIFT                                                30
70849     #define MSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR                                                 (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
70850     #define MSEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_SHIFT                                           31
70851 #define MSEM_REG_INT_STS_CLR_0                                                                       0x180004cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
70852     #define MSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
70853     #define MSEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
70854     #define MSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                    (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
70855     #define MSEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                              1
70856     #define MSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                  (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
70857     #define MSEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                            2
70858     #define MSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                    (0x1<<3) // Error in any one of the FIC FIFO is active.
70859     #define MSEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                              3
70860     #define MSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR                                                (0x1<<4) // Error in Ext PAS_FIFO is active.
70861     #define MSEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_SHIFT                                          4
70862     #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR                                                (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
70863     #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_SHIFT                                          5
70864     #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR                                            (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
70865     #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                      6
70866     #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR                                             (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
70867     #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                       7
70868     #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR                                            (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
70869     #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                      8
70870     #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR                                             (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
70871     #define MSEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                       9
70872     #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR                                               (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
70873     #define MSEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                         10
70874     #define MSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR                                            (0x1<<11) // Signals an unknown address in the fast-memory window.
70875     #define MSEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                      11
70876     #define MSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO                                                  (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
70877     #define MSEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_SHIFT                                            12
70878     #define MSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO                                                  (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
70879     #define MSEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_SHIFT                                            13
70880     #define MSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO                                                      (0x1<<14) // Error in CAM_OUT fifo in cam block.
70881     #define MSEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_SHIFT                                                14
70882     #define MSEM_REG_INT_STS_CLR_0_FIN_FIFO                                                          (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
70883     #define MSEM_REG_INT_STS_CLR_0_FIN_FIFO_SHIFT                                                    15
70884     #define MSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR                                                 (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
70885     #define MSEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_SHIFT                                           16
70886     #define MSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN                                                    (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
70887     #define MSEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_SHIFT                                              17
70888     #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR                                         (0x1<<18) // Error in external store sync FIFO push logic.
70889     #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                   18
70890     #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR                                          (0x1<<19) // Error in external store sync FIFO pop logic.
70891     #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                    19
70892     #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR                                          (0x1<<20) // Error in external load sync FIFO push logic.
70893     #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                    20
70894     #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR                                           (0x1<<21) // Error in external load sync FIFO pop logic.
70895     #define MSEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                     21
70896     #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR                                            (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
70897     #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                      22
70898     #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR                                             (0x1<<23) // Error in LS_SYNC_POP FIFO.
70899     #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                       23
70900     #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR                                             (0x1<<24) // Error in LS_SYNC_POP FIFO.
70901     #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                       24
70902     #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR                                            (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
70903     #define MSEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                      25
70904     #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR                                               (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
70905     #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                         26
70906     #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR                                                (0x1<<27) // Error in LS_SYNC_POP FIFO.
70907     #define MSEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_SHIFT                                          27
70908     #define MSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR                                                    (0x1<<28) // Error in slow debug fifo.
70909     #define MSEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_SHIFT                                              28
70910     #define MSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO                                                 (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
70911     #define MSEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_SHIFT                                           29
70912     #define MSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT                                                     (0x1<<30) // Error interrupt in VFC block.
70913     #define MSEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_SHIFT                                               30
70914     #define MSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR                                                (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
70915     #define MSEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_SHIFT                                          31
70916 #define MSEM_REG_INT_STS_1                                                                           0x1800050UL //Access:R    DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70917     #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
70918     #define MSEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_SHIFT                                             0
70919     #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
70920     #define MSEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_SHIFT                                             1
70921     #define MSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR                                                   (0x1<<2) // The Storm detected an illegal runtime value.
70922     #define MSEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_SHIFT                                             2
70923     #define MSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
70924     #define MSEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                          3
70925     #define MSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
70926     #define MSEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_SHIFT                                           4
70927     #define MSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
70928     #define MSEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_SHIFT                                           5
70929     #define MSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
70930     #define MSEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_SHIFT                                            6
70931     #define MSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
70932     #define MSEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_SHIFT                                            7
70933     #define MSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
70934     #define MSEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_SHIFT                                               8
70935     #define MSEM_REG_INT_STS_1_INVLD_FOC_ERROR                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
70936     #define MSEM_REG_INT_STS_1_INVLD_FOC_ERROR_SHIFT                                                 9
70937     #define MSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
70938     #define MSEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_SHIFT                                                10
70939     #define MSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
70940     #define MSEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_SHIFT                                             11
70941     #define MSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
70942     #define MSEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_SHIFT                                            12
70943 #define MSEM_REG_INT_MASK_1                                                                          0x1800054UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70944     #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
70945     #define MSEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_SHIFT                                            0
70946     #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
70947     #define MSEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_SHIFT                                            1
70948     #define MSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
70949     #define MSEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_SHIFT                                            2
70950     #define MSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
70951     #define MSEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                         3
70952     #define MSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
70953     #define MSEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_SHIFT                                          4
70954     #define MSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
70955     #define MSEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_SHIFT                                          5
70956     #define MSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
70957     #define MSEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_SHIFT                                           6
70958     #define MSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
70959     #define MSEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_SHIFT                                           7
70960     #define MSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
70961     #define MSEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_SHIFT                                              8
70962     #define MSEM_REG_INT_MASK_1_INVLD_FOC_ERROR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.INVLD_FOC_ERROR .
70963     #define MSEM_REG_INT_MASK_1_INVLD_FOC_ERROR_SHIFT                                                9
70964     #define MSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
70965     #define MSEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_SHIFT                                               10
70966     #define MSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
70967     #define MSEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_SHIFT                                            11
70968     #define MSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: MSEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
70969     #define MSEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_SHIFT                                           12
70970 #define MSEM_REG_INT_STS_WR_1                                                                        0x1800058UL //Access:WR   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70971     #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN                                                (0x1<<0) // An underflow error was detected in the Storm stack.
70972     #define MSEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_SHIFT                                          0
70973     #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN                                                (0x1<<1) // An overflow error was detected in the Storm stack.
70974     #define MSEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_SHIFT                                          1
70975     #define MSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR                                                (0x1<<2) // The Storm detected an illegal runtime value.
70976     #define MSEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_SHIFT                                          2
70977     #define MSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR                                             (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
70978     #define MSEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                       3
70979     #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR                                              (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
70980     #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                        4
70981     #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR                                              (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
70982     #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                        5
70983     #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR                                               (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
70984     #define MSEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_SHIFT                                         6
70985     #define MSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR                                               (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
70986     #define MSEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_SHIFT                                         7
70987     #define MSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR                                                  (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
70988     #define MSEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_SHIFT                                            8
70989     #define MSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR                                                    (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
70990     #define MSEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_SHIFT                                              9
70991     #define MSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR                                                   (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
70992     #define MSEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_SHIFT                                             10
70993     #define MSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR                                                (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
70994     #define MSEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_SHIFT                                          11
70995     #define MSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR                                               (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
70996     #define MSEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_SHIFT                                         12
70997 #define MSEM_REG_INT_STS_CLR_1                                                                       0x180005cUL //Access:RC   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
70998     #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN                                               (0x1<<0) // An underflow error was detected in the Storm stack.
70999     #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_SHIFT                                         0
71000     #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN                                               (0x1<<1) // An overflow error was detected in the Storm stack.
71001     #define MSEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_SHIFT                                         1
71002     #define MSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR                                               (0x1<<2) // The Storm detected an illegal runtime value.
71003     #define MSEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_SHIFT                                         2
71004     #define MSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR                                            (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
71005     #define MSEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                      3
71006     #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR                                             (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
71007     #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                       4
71008     #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR                                             (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
71009     #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                       5
71010     #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR                                              (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
71011     #define MSEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_SHIFT                                        6
71012     #define MSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR                                              (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
71013     #define MSEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_SHIFT                                        7
71014     #define MSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR                                                 (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
71015     #define MSEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_SHIFT                                           8
71016     #define MSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR                                                   (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
71017     #define MSEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_SHIFT                                             9
71018     #define MSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR                                                  (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
71019     #define MSEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_SHIFT                                            10
71020     #define MSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR                                               (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
71021     #define MSEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_SHIFT                                         11
71022     #define MSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR                                              (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
71023     #define MSEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_SHIFT                                        12
71024 #define MSEM_REG_PRTY_MASK                                                                           0x18000ccUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71025     #define MSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                  (0x1<<0) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
71026     #define MSEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                            0
71027     #define MSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                 (0x1<<1) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
71028     #define MSEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                           1
71029     #define MSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                  (0x1<<2) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
71030     #define MSEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                            2
71031 #define MSEM_REG_PRTY_MASK_H_0                                                                       0x1800204UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71032     #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
71033     #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT                                       0
71034     #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
71035     #define MSEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT                                       1
71036     #define MSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
71037     #define MSEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           2
71038     #define MSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
71039     #define MSEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           3
71040     #define MSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
71041     #define MSEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           4
71042     #define MSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: MSEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
71043     #define MSEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           5
71044 #define MSEM_REG_MEM_ECC_EVENTS                                                                      0x180021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
71045 #define MSEM_REG_MEM004_I_MEM_DFT_K2                                                                 0x1800224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msem.i_sem_core.i_sem_slow.i_sem_slow_int_table_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
71046 #define MSEM_REG_MEM005_I_MEM_DFT_K2                                                                 0x1800228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.DEFAULT_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
71047 #define MSEM_REG_MEM002_I_MEM_DFT_K2                                                                 0x180022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msem.i_sem_core.i_sem_slow.i_sem_slow_ext_pas_fifo_wrap.DEFAULT_EXT_PAS_FIFO_GEN_IF.i_sem_slow_ext_pas_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
71048 #define MSEM_REG_MEM003_I_MEM_DFT_K2                                                                 0x1800230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msem.i_sem_core.i_sem_slow.i_sem_slow_fic_fifo_wrap.DEFAULT_FIC_FIFO_MEM_GEN_IF.i_sem_slow_fic0_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
71049 #define MSEM_REG_MEM001_I_MEM_DFT_K2                                                                 0x1800234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance msem.i_sem_core.i_sem_slow.i_sem_slow_dbg_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
71050 #define MSEM_REG_ARB_CYCLE_SIZE                                                                      0x1800400UL //Access:RW   DataWidth:0x5   The number of time_slots in the arbitration cycle.  Chips: BB_A0 BB_B0 K2
71051 #define MSEM_REG_VF_ERROR                                                                            0x1800408UL //Access:WR   DataWidth:0x1   This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.  Chips: BB_A0 BB_B0 K2
71052 #define MSEM_REG_PF_ERROR                                                                            0x180040cUL //Access:WR   DataWidth:0x1   This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.  Chips: BB_A0 BB_B0 K2
71053 #define MSEM_REG_VF_ERR_VECTOR                                                                       0x1800420UL //Access:WB_R DataWidth:0xc0  This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.  Chips: BB_A0 BB_B0 K2
71054 #define MSEM_REG_VF_ERR_VECTOR_SIZE                                                                  8
71055 #define MSEM_REG_PF_ERR_VECTOR                                                                       0x1800440UL //Access:R    DataWidth:0x10  This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.  Chips: BB_A0 BB_B0 K2
71056 #define MSEM_REG_CLEAR_STALL                                                                         0x1800444UL //Access:RW   DataWidth:0x1   Clear stall signal sent from local storm to external storms.  Chips: BB_A0 BB_B0 K2
71057 #define MSEM_REG_EXCEPTION_INT                                                                       0x1800448UL //Access:RW   DataWidth:0x10  Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.  Chips: BB_A0 BB_B0 K2
71058 #define MSEM_REG_EXT_STORE_FREE_ENTRIES                                                              0x180044cUL //Access:R    DataWidth:0x6   Number of free entries in the external STORE sync FIFO.  Chips: BB_A0 BB_B0 K2
71059 #define MSEM_REG_GPI_DATA                                                                            0x1800450UL //Access:R    DataWidth:0x20  Used to read the GPI input signals.  Chips: BB_A0 BB_B0 K2
71060 #define MSEM_REG_GPRE_SAMP_PERIOD                                                                    0x1800454UL //Access:RW   DataWidth:0x4   Defines the number of system clocks from one sample of GPRE sync data and the next.  Chips: BB_A0 BB_B0 K2
71061 #define MSEM_REG_ALLOW_LP_SLEEP_THRD                                                                 0x1800458UL //Access:RW   DataWidth:0x1   When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.  Chips: BB_A0 BB_B0 K2
71062 #define MSEM_REG_ECO_RESERVED                                                                        0x180045cUL //Access:RW   DataWidth:0x8   This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: BB_A0 BB_B0 K2
71063 #define MSEM_REG_FIC_GAP_VECT                                                                        0x1800500UL //Access:WB   DataWidth:0x2c  This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.  Chips: BB_A0 BB_B0 K2
71064 #define MSEM_REG_FIC_GAP_VECT_SIZE                                                                   18
71065 #define MSEM_REG_FIC_FIFO                                                                            0x1800580UL //Access:WB_R DataWidth:0x80  Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.  Chips: BB_A0 BB_B0 K2
71066 #define MSEM_REG_FIC_FIFO_SIZE                                                                       4
71067 #define MSEM_REG_FIC_MIN_MSG                                                                         0x1800600UL //Access:RW   DataWidth:0x6   Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.  Chips: BB_A0 BB_B0 K2
71068 #define MSEM_REG_FIC_EMPTY_CT_MODE                                                                   0x1800620UL //Access:RW   DataWidth:0x1   When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.  Chips: BB_A0 BB_B0 K2
71069 #define MSEM_REG_FIC_EMPTY_CT_CNT                                                                    0x1800624UL //Access:RC   DataWidth:0x18  Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.  Chips: BB_A0 BB_B0 K2
71070 #define MSEM_REG_FOC_CREDIT                                                                          0x1800680UL //Access:RW   DataWidth:0x8   Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.  Chips: BB_A0 BB_B0 K2
71071 #define MSEM_REG_FOC_CREDIT_SIZE                                                                     6
71072 #define MSEM_REG_FULL_FOC_DRA_STRT_EN                                                                0x18006c0UL //Access:RW   DataWidth:0x1   When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.  Chips: BB_A0 BB_B0 K2
71073 #define MSEM_REG_FIN_COMMAND                                                                         0x1800700UL //Access:WB_R DataWidth:0x164 Last fin command that was read from fifo. Its spelling in FIN_FIFO register.  Chips: BB_A0 BB_B0 K2
71074 #define MSEM_REG_FIN_COMMAND_SIZE                                                                    16
71075 #define MSEM_REG_FIN_FIFO                                                                            0x1800800UL //Access:WB_R DataWidth:0x164 READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.  Chips: BB_A0 BB_B0 K2
71076 #define MSEM_REG_FIN_FIFO_SIZE                                                                       16
71077 #define MSEM_REG_INVLD_PAS_WR_EN                                                                     0x1800900UL //Access:RW   DataWidth:0x1   When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.  Chips: BB_A0 BB_B0 K2
71078 #define MSEM_REG_ARBITER_REQUEST                                                                     0x1800980UL //Access:R    DataWidth:0x5   Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
71079 #define MSEM_REG_ARBITER_SELECT                                                                      0x1800984UL //Access:R    DataWidth:0x5   Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
71080 #define MSEM_REG_ARBITER_SLOT                                                                        0x1800988UL //Access:R    DataWidth:0x5   Dra arbiter last slot.  Chips: BB_A0 BB_B0 K2
71081 #define MSEM_REG_ARB_AS_DEF                                                                          0x1800a00UL //Access:RW   DataWidth:0x3   Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.  Chips: BB_A0 BB_B0 K2
71082 #define MSEM_REG_ARB_AS_DEF_SIZE                                                                     32
71083 #define MSEM_REG_ARB_TS_AS                                                                           0x1800a80UL //Access:RW   DataWidth:0x2   Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].  Chips: BB_A0 BB_B0 K2
71084 #define MSEM_REG_ARB_TS_AS_SIZE                                                                      20
71085 #define MSEM_REG_NUM_OF_THREADS                                                                      0x1800b00UL //Access:R    DataWidth:0x5   The number of curretnly free threads.  Chips: BB_A0 BB_B0 K2
71086 #define MSEM_REG_THREAD_ERROR                                                                        0x1800b04UL //Access:R    DataWidth:0x18  Thread error indication.  Chips: BB_A0 BB_B0 K2
71087 #define MSEM_REG_THREAD_RDY                                                                          0x1800b08UL //Access:R    DataWidth:0x18  Thread ready indication.  Chips: BB_A0 BB_B0 K2
71088 #define MSEM_REG_THREAD_SET_NUM                                                                      0x1800b0cUL //Access:W    DataWidth:0x5   Thread ID. Write thread ID will set ready indication for this thread ID.  Chips: BB_A0 BB_B0 K2
71089 #define MSEM_REG_THREAD_VALID                                                                        0x1800b10UL //Access:R    DataWidth:0x18  Valid sleeping threads.  Chips: BB_A0 BB_B0 K2
71090 #define MSEM_REG_THREADS_LIST                                                                        0x1800b14UL //Access:RW   DataWidth:0x18  List of free threads.  Chips: BB_A0 BB_B0 K2
71091 #define MSEM_REG_ORDER_HEAD                                                                          0x1800c00UL //Access:RW   DataWidth:0x5   This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.  Chips: BB_A0 BB_B0 K2
71092 #define MSEM_REG_ORDER_HEAD_SIZE                                                                     24
71093 #define MSEM_REG_ORDER_TAIL                                                                          0x1800c80UL //Access:RW   DataWidth:0x5   This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
71094 #define MSEM_REG_ORDER_TAIL_SIZE                                                                     24
71095 #define MSEM_REG_ORDER_EMPTY                                                                         0x1800d00UL //Access:RW   DataWidth:0x1   This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
71096 #define MSEM_REG_ORDER_EMPTY_SIZE                                                                    24
71097 #define MSEM_REG_ORDER_LL_REG                                                                        0x1800d80UL //Access:RW   DataWidth:0x5   This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..  Chips: BB_A0 BB_B0 K2
71098 #define MSEM_REG_ORDER_LL_REG_SIZE                                                                   24
71099 #define MSEM_REG_ORDER_POP_EN                                                                        0x1800e00UL //Access:RW   DataWidth:0x18  Provides access to the thread ordering queue pop-enable vector.  Chips: BB_A0 BB_B0 K2
71100 #define MSEM_REG_ORDER_WAKE_EN                                                                       0x1800e08UL //Access:RW   DataWidth:0x18  Provides access to the thread ordering queue wake-enable vector.  Chips: BB_A0 BB_B0 K2
71101 #define MSEM_REG_PF_NUM_ORDER_BASE                                                                   0x1800e10UL //Access:RW   DataWidth:0x5   This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.  Chips: BB_A0 BB_B0 K2
71102 #define MSEM_REG_DBG_ALM_FULL                                                                        0x1801000UL //Access:RW   DataWidth:0x6   Almost full for slow debug fifo.  Chips: BB_A0 BB_B0 K2
71103 #define MSEM_REG_PASSIVE_ALM_FULL                                                                    0x1801004UL //Access:RW   DataWidth:0x5   The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.  Chips: BB_A0 BB_B0 K2
71104 #define MSEM_REG_SYNC_DRA_WR_ALM_FULL                                                                0x1801008UL //Access:RW   DataWidth:0x5   Almost full for sync dra_wr fifo (data from DRA to STORM).  Chips: BB_A0 BB_B0 K2
71105 #define MSEM_REG_SYNC_RAM_WR_ALM_FULL                                                                0x180100cUL //Access:RW   DataWidth:0x6   Almost full for sync ram_wr fifo (data from EXT_IF to STORM).  Chips: BB_A0 BB_B0 K2
71106 #define MSEM_REG_DRA_EMPTY                                                                           0x1801100UL //Access:R    DataWidth:0x1   Dra_empty.  Chips: BB_A0 BB_B0 K2
71107 #define MSEM_REG_EXT_PAS_EMPTY                                                                       0x1801104UL //Access:R    DataWidth:0x1   EXT_PAS FIFO empty in sem_slow.  Chips: BB_A0 BB_B0 K2
71108 #define MSEM_REG_FIC_EMPTY                                                                           0x1801120UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO empty in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
71109 #define MSEM_REG_SLOW_DBG_EMPTY                                                                      0x1801140UL //Access:R    DataWidth:0x1   DBG FIFO is empty in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
71110 #define MSEM_REG_SLOW_DRA_FIN_EMPTY                                                                  0x1801144UL //Access:R    DataWidth:0x1   FIN fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71111 #define MSEM_REG_SLOW_DRA_RD_EMPTY                                                                   0x1801148UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71112 #define MSEM_REG_SLOW_DRA_WR_EMPTY                                                                   0x180114cUL //Access:R    DataWidth:0x1   DRA_WR push fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71113 #define MSEM_REG_SLOW_EXT_STORE_EMPTY                                                                0x1801150UL //Access:R    DataWidth:0x1   EXT_STORE FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71114 #define MSEM_REG_SLOW_EXT_LOAD_EMPTY                                                                 0x1801154UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71115 #define MSEM_REG_SLOW_RAM_RD_EMPTY                                                                   0x1801158UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71116 #define MSEM_REG_SLOW_RAM_WR_EMPTY                                                                   0x180115cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71117 #define MSEM_REG_SYNC_DBG_EMPTY                                                                      0x1801160UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
71118 #define MSEM_REG_THREAD_FIFO_EMPTY                                                                   0x1801164UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
71119 #define MSEM_REG_ORD_ID_FIFO_EMPTY                                                                   0x1801168UL //Access:R    DataWidth:0x1   Indicates that the order ID fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
71120 #define MSEM_REG_EXT_PAS_FULL                                                                        0x1801200UL //Access:R    DataWidth:0x1   EXT_PAS FIFO Full in sem_slow.  Chips: BB_A0 BB_B0 K2
71121 #define MSEM_REG_EXT_STORE_IF_FULL                                                                   0x1801204UL //Access:R    DataWidth:0x1   EXT_STORE IF is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71122 #define MSEM_REG_FIC_FULL                                                                            0x1801220UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO full in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
71123 #define MSEM_REG_PAS_IF_FULL                                                                         0x1801240UL //Access:R    DataWidth:0x1   Full from passive buffer asserted toward SDM.  Chips: BB_A0 BB_B0 K2
71124 #define MSEM_REG_RAM_IF_FULL                                                                         0x1801244UL //Access:R    DataWidth:0x1   EXT_RAM IF is full in sem_slow_ls_ram.  Chips: BB_A0 BB_B0 K2
71125 #define MSEM_REG_SLOW_DBG_ALM_FULL                                                                   0x1801248UL //Access:R    DataWidth:0x1   DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.  Chips: BB_A0 BB_B0 K2
71126 #define MSEM_REG_SLOW_DBG_FULL                                                                       0x180124cUL //Access:R    DataWidth:0x1   DBG FIFO is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
71127 #define MSEM_REG_SLOW_DRA_FIN_FULL                                                                   0x1801250UL //Access:R    DataWidth:0x1   FIN fifo is full in sem_slow_dra_sync (never may be active).  Chips: BB_A0 BB_B0 K2
71128 #define MSEM_REG_SLOW_DRA_RD_FULL                                                                    0x1801254UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71129 #define MSEM_REG_SLOW_DRA_WR_FULL                                                                    0x1801258UL //Access:R    DataWidth:0x1   DRA_WR push fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71130 #define MSEM_REG_SLOW_EXT_STORE_FULL                                                                 0x180125cUL //Access:R    DataWidth:0x1   EXT_STORE FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71131 #define MSEM_REG_SLOW_EXT_LOAD_FULL                                                                  0x1801260UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71132 #define MSEM_REG_SLOW_RAM_RD_FULL                                                                    0x1801264UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71133 #define MSEM_REG_SLOW_RAM_WR_ALM_FULL                                                                0x1801268UL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71134 #define MSEM_REG_SLOW_RAM_WR_FULL                                                                    0x180126cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71135 #define MSEM_REG_SYNC_DBG_FULL                                                                       0x1801270UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is full in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
71136 #define MSEM_REG_THREAD_FIFO_FULL                                                                    0x1801274UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
71137 #define MSEM_REG_ORD_ID_FIFO_FULL                                                                    0x1801278UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
71138 #define MSEM_REG_THREAD_INTER_CNT                                                                    0x1801300UL //Access:RW   DataWidth:0x10  Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.  Chips: BB_A0 BB_B0 K2
71139 #define MSEM_REG_THREAD_INTER_CNT_ENABLE                                                             0x1801304UL //Access:RW   DataWidth:0x1   Enable for start count of thread_inter_cnt.  Chips: BB_A0 BB_B0 K2
71140 #define MSEM_REG_THREAD_ORUN_NUM                                                                     0x1801308UL //Access:R    DataWidth:0x18  Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.  Chips: BB_A0 BB_B0 K2
71141 #define MSEM_REG_SLOW_DBG_ACTIVE                                                                     0x1801400UL //Access:RW   DataWidth:0x1   Debug mode is active.  Chips: BB_A0 BB_B0 K2
71142 #define MSEM_REG_SLOW_DBG_MODE                                                                       0x1801404UL //Access:RW   DataWidth:0x3   Debug mode for slow debug bus.  Chips: BB_A0 BB_B0 K2
71143 #define MSEM_REG_DBG_FRAME_MODE                                                                      0x1801408UL //Access:RW   DataWidth:0x2   Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.  Chips: BB_A0 BB_B0 K2
71144 #define MSEM_REG_DBG_EACH_CYLE                                                                       0x180140cUL //Access:RW   DataWidth:0x1   0=output every cycle; 1= output only when there is a change.  Chips: BB_A0 BB_B0 K2
71145 #define MSEM_REG_DBG_GPRE_VECT                                                                       0x1801410UL //Access:RW   DataWidth:0x8   This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].  Chips: BB_A0 BB_B0 K2
71146 #define MSEM_REG_DBG_IF_FULL                                                                         0x1801414UL //Access:R    DataWidth:0x1   DBG IF is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
71147 #define MSEM_REG_DBG_MODE0_CFG                                                                       0x1801418UL //Access:RW   DataWidth:0x1   0=all the message; 1=partial message.  Chips: BB_A0 BB_B0 K2
71148 #define MSEM_REG_DBG_MODE0_CFG_CYCLE                                                                 0x180141cUL //Access:RW   DataWidth:0x5   In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.  Chips: BB_A0 BB_B0 K2
71149 #define MSEM_REG_DBG_MODE1_CFG                                                                       0x1801420UL //Access:RW   DataWidth:0x1   0=without the data; 1=with the data.  Chips: BB_A0 BB_B0 K2
71150 #define MSEM_REG_DBG_MSG_SRC                                                                         0x1801424UL //Access:RW   DataWidth:0x3   This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.  Chips: BB_A0 BB_B0 K2
71151 #define MSEM_REG_DBG_OUT_DATA                                                                        0x1801500UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
71152 #define MSEM_REG_DBG_OUT_DATA_SIZE                                                                   8
71153 #define MSEM_REG_DBG_OUT_VALID                                                                       0x1801520UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
71154 #define MSEM_REG_DBG_OUT_FRAME                                                                       0x1801524UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
71155 #define MSEM_REG_DBG_SELECT                                                                          0x1801528UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
71156 #define MSEM_REG_DBG_DWORD_ENABLE                                                                    0x180152cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
71157 #define MSEM_REG_DBG_SHIFT                                                                           0x1801530UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
71158 #define MSEM_REG_DBG_FORCE_VALID                                                                     0x1801534UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
71159 #define MSEM_REG_DBG_FORCE_FRAME                                                                     0x1801538UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
71160 #define MSEM_REG_EXT_PAS_FIFO                                                                        0x1808000UL //Access:WB_R DataWidth:0x4d  Provides read-only access of the external passive FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
71161 #define MSEM_REG_EXT_PAS_FIFO_SIZE                                                                   76
71162 #define MSEM_REG_INT_TABLE                                                                           0x1810000UL //Access:RW   DataWidth:0x15  Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address  Chips: BB_A0 BB_B0 K2
71163 #define MSEM_REG_INT_TABLE_SIZE                                                                      256
71164 #define MSEM_REG_PASSIVE_BUFFER                                                                      0x1820000UL //Access:WB   DataWidth:0x80  Read and write to it is just for debugging. Passive buffer memory.  Chips: BB_A0 BB_B0 K2
71165 #define MSEM_REG_PASSIVE_BUFFER_SIZE                                                                 4320
71166 #define MSEM_REG_FAST_MEMORY                                                                         0x1840000UL //Access:RW   DataWidth:0x20  See sem_fast.xls for its description.  Chips: BB_A0 BB_B0 K2
71167 #define MSEM_REG_FAST_MEMORY_SIZE                                                                    65536
71168 #define MSEM_REG_PRAM                                                                                0x1880000UL //Access:WB   DataWidth:0x30  Pram memory.  Chips: BB_A0 BB_B0 K2
71169 #define MSEM_REG_PRAM_SIZE                                                                           73728
71170 #define USEM_REG_ENABLE_IN                                                                           0x1900004UL //Access:RW   DataWidth:0xa   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71171     #define USEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN                                                    (0x1<<0) // Full input from external IF to LS input enable.
71172     #define USEM_REG_ENABLE_IN_EXT_FULL_ENABLE_IN_SHIFT                                              0
71173     #define USEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN                                                 (0x1<<1) // Read data from external LS IF input enable.
71174     #define USEM_REG_ENABLE_IN_EXT_RD_DATA_ENABLE_IN_SHIFT                                           1
71175     #define USEM_REG_ENABLE_IN_FIC_ENABLE_IN                                                         (0x1<<2) // FIC input enable bit used to enable/disable messages from being received on all FIC interfaces.
71176     #define USEM_REG_ENABLE_IN_FIC_ENABLE_IN_SHIFT                                                   2
71177     #define USEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN                                                     (0x1<<3) // FOC acknowledge input enable bit used to enable/disable acknowledge response from being received on any of the FOC interfaces.
71178     #define USEM_REG_ENABLE_IN_FOC_ACK_ENABLE_IN_SHIFT                                               3
71179     #define USEM_REG_ENABLE_IN_GENERAL_ENABLE_IN                                                     (0x1<<4) // General interface input enable.
71180     #define USEM_REG_ENABLE_IN_GENERAL_ENABLE_IN_SHIFT                                               4
71181     #define USEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN                                                     (0x1<<5) // External passive write input enable.
71182     #define USEM_REG_ENABLE_IN_PASSIVE_ENABLE_IN_SHIFT                                               5
71183     #define USEM_REG_ENABLE_IN_RAM_ENABLE_IN                                                         (0x1<<6) // Data input enable to RAM.
71184     #define USEM_REG_ENABLE_IN_RAM_ENABLE_IN_SHIFT                                                   6
71185     #define USEM_REG_ENABLE_IN_STALL_ENABLE_IN                                                       (0x1<<7) // Enable for stall input from all external STORM instances.
71186     #define USEM_REG_ENABLE_IN_STALL_ENABLE_IN_SHIFT                                                 7
71187     #define USEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN                                                  (0x1<<8) // Thread ready bus input enable.
71188     #define USEM_REG_ENABLE_IN_THREAD_RDY_ENABLE_IN_SHIFT                                            8
71189     #define USEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN                                                  (0x1<<9) // Input enable for VF error indication from SDM to SEMI.
71190     #define USEM_REG_ENABLE_IN_VFPF_ERROR_ENABLE_IN_SHIFT                                            9
71191 #define USEM_REG_ENABLE_OUT                                                                          0x1900008UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71192     #define USEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT                                                (0x1<<0) // Read request output enable from external LS IF.
71193     #define USEM_REG_ENABLE_OUT_EXT_RD_REQ_ENABLE_OUT_SHIFT                                          0
71194     #define USEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT                                                (0x1<<1) // Write request output enable from external LS IF.
71195     #define USEM_REG_ENABLE_OUT_EXT_WR_REQ_ENABLE_OUT_SHIFT                                          1
71196     #define USEM_REG_ENABLE_OUT_FOC_ENABLE_OUT                                                       (0x1<<2) // FOC output otuput enable bit used to enable/disable messages from being sent out on any of the FOC interfaces.
71197     #define USEM_REG_ENABLE_OUT_FOC_ENABLE_OUT_SHIFT                                                 2
71198     #define USEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT                                                   (0x1<<3) // Passive full output enable.
71199     #define USEM_REG_ENABLE_OUT_PASSIVE_ENABLE_OUT_SHIFT                                             3
71200     #define USEM_REG_ENABLE_OUT_RAM_ENABLE_OUT                                                       (0x1<<4) // Data output enable to RAM.
71201     #define USEM_REG_ENABLE_OUT_RAM_ENABLE_OUT_SHIFT                                                 4
71202     #define USEM_REG_ENABLE_OUT_STALL_ENABLE_OUT                                                     (0x1<<5) // Stall output enable bit used to enable/disable the output stall signal toward all external Storm instances.
71203     #define USEM_REG_ENABLE_OUT_STALL_ENABLE_OUT_SHIFT                                               5
71204 #define USEM_REG_FIC_DISABLE                                                                         0x190000cUL //Access:RW   DataWidth:0x1   Disables input messages from all FIC interfaces.  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
71205 #define USEM_REG_PAS_DISABLE                                                                         0x1900010UL //Access:RW   DataWidth:0x1   Disables input messages from the passive buffer  May be updated during run_time by the microcode.  Chips: BB_A0 BB_B0 K2
71206 #define USEM_REG_INT_STS_0                                                                           0x1900040UL //Access:R    DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
71207     #define USEM_REG_INT_STS_0_ADDRESS_ERROR                                                         (0x1<<0) // Signals an unknown address to the rf module.
71208     #define USEM_REG_INT_STS_0_ADDRESS_ERROR_SHIFT                                                   0
71209     #define USEM_REG_INT_STS_0_FIC_LAST_ERROR                                                        (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
71210     #define USEM_REG_INT_STS_0_FIC_LAST_ERROR_SHIFT                                                  1
71211     #define USEM_REG_INT_STS_0_FIC_LENGTH_ERROR                                                      (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
71212     #define USEM_REG_INT_STS_0_FIC_LENGTH_ERROR_SHIFT                                                2
71213     #define USEM_REG_INT_STS_0_FIC_FIFO_ERROR                                                        (0x1<<3) // Error in any one of the FIC FIFO is active.
71214     #define USEM_REG_INT_STS_0_FIC_FIFO_ERROR_SHIFT                                                  3
71215     #define USEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR                                                    (0x1<<4) // Error in Ext PAS_FIFO is active.
71216     #define USEM_REG_INT_STS_0_PAS_BUF_FIFO_ERROR_SHIFT                                              4
71217     #define USEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR                                                    (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
71218     #define USEM_REG_INT_STS_0_SYNC_FIN_POP_ERROR_SHIFT                                              5
71219     #define USEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR                                                (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
71220     #define USEM_REG_INT_STS_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                          6
71221     #define USEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR                                                 (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
71222     #define USEM_REG_INT_STS_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                           7
71223     #define USEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR                                                (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
71224     #define USEM_REG_INT_STS_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                          8
71225     #define USEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR                                                 (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
71226     #define USEM_REG_INT_STS_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                           9
71227     #define USEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR                                                   (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
71228     #define USEM_REG_INT_STS_0_SYNC_FIN_PUSH_ERROR_SHIFT                                             10
71229     #define USEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR                                                (0x1<<11) // Signals an unknown address in the fast-memory window.
71230     #define USEM_REG_INT_STS_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                          11
71231     #define USEM_REG_INT_STS_0_CAM_LSB_INP_FIFO                                                      (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
71232     #define USEM_REG_INT_STS_0_CAM_LSB_INP_FIFO_SHIFT                                                12
71233     #define USEM_REG_INT_STS_0_CAM_MSB_INP_FIFO                                                      (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
71234     #define USEM_REG_INT_STS_0_CAM_MSB_INP_FIFO_SHIFT                                                13
71235     #define USEM_REG_INT_STS_0_CAM_OUT_FIFO                                                          (0x1<<14) // Error in CAM_OUT fifo in cam block.
71236     #define USEM_REG_INT_STS_0_CAM_OUT_FIFO_SHIFT                                                    14
71237     #define USEM_REG_INT_STS_0_FIN_FIFO                                                              (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
71238     #define USEM_REG_INT_STS_0_FIN_FIFO_SHIFT                                                        15
71239     #define USEM_REG_INT_STS_0_THREAD_FIFO_ERROR                                                     (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
71240     #define USEM_REG_INT_STS_0_THREAD_FIFO_ERROR_SHIFT                                               16
71241     #define USEM_REG_INT_STS_0_THREAD_OVERRUN                                                        (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
71242     #define USEM_REG_INT_STS_0_THREAD_OVERRUN_SHIFT                                                  17
71243     #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR                                             (0x1<<18) // Error in external store sync FIFO push logic.
71244     #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                       18
71245     #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR                                              (0x1<<19) // Error in external store sync FIFO pop logic.
71246     #define USEM_REG_INT_STS_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                        19
71247     #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR                                              (0x1<<20) // Error in external load sync FIFO push logic.
71248     #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                        20
71249     #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR                                               (0x1<<21) // Error in external load sync FIFO pop logic.
71250     #define USEM_REG_INT_STS_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                         21
71251     #define USEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR                                                (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
71252     #define USEM_REG_INT_STS_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                          22
71253     #define USEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR                                                 (0x1<<23) // Error in LS_SYNC_POP FIFO.
71254     #define USEM_REG_INT_STS_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                           23
71255     #define USEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR                                                 (0x1<<24) // Error in LS_SYNC_POP FIFO.
71256     #define USEM_REG_INT_STS_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                           24
71257     #define USEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR                                                (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
71258     #define USEM_REG_INT_STS_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                          25
71259     #define USEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR                                                   (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
71260     #define USEM_REG_INT_STS_0_SYNC_DBG_PUSH_ERROR_SHIFT                                             26
71261     #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR                                                    (0x1<<27) // Error in LS_SYNC_POP FIFO.
71262     #define USEM_REG_INT_STS_0_SYNC_DBG_POP_ERROR_SHIFT                                              27
71263     #define USEM_REG_INT_STS_0_DBG_FIFO_ERROR                                                        (0x1<<28) // Error in slow debug fifo.
71264     #define USEM_REG_INT_STS_0_DBG_FIFO_ERROR_SHIFT                                                  28
71265     #define USEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO                                                     (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
71266     #define USEM_REG_INT_STS_0_CAM_MSB2_INP_FIFO_SHIFT                                               29
71267     #define USEM_REG_INT_STS_0_VFC_INTERRUPT                                                         (0x1<<30) // Error interrupt in VFC block.
71268     #define USEM_REG_INT_STS_0_VFC_INTERRUPT_SHIFT                                                   30
71269     #define USEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR                                                    (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
71270     #define USEM_REG_INT_STS_0_VFC_OUT_FIFO_ERROR_SHIFT                                              31
71271 #define USEM_REG_INT_MASK_0                                                                          0x1900044UL //Access:RW   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
71272     #define USEM_REG_INT_MASK_0_ADDRESS_ERROR                                                        (0x1<<0) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.ADDRESS_ERROR .
71273     #define USEM_REG_INT_MASK_0_ADDRESS_ERROR_SHIFT                                                  0
71274     #define USEM_REG_INT_MASK_0_FIC_LAST_ERROR                                                       (0x1<<1) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_LAST_ERROR .
71275     #define USEM_REG_INT_MASK_0_FIC_LAST_ERROR_SHIFT                                                 1
71276     #define USEM_REG_INT_MASK_0_FIC_LENGTH_ERROR                                                     (0x1<<2) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_LENGTH_ERROR .
71277     #define USEM_REG_INT_MASK_0_FIC_LENGTH_ERROR_SHIFT                                               2
71278     #define USEM_REG_INT_MASK_0_FIC_FIFO_ERROR                                                       (0x1<<3) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIC_FIFO_ERROR .
71279     #define USEM_REG_INT_MASK_0_FIC_FIFO_ERROR_SHIFT                                                 3
71280     #define USEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR                                                   (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.PAS_BUF_FIFO_ERROR .
71281     #define USEM_REG_INT_MASK_0_PAS_BUF_FIFO_ERROR_SHIFT                                             4
71282     #define USEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR                                                   (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_FIN_POP_ERROR .
71283     #define USEM_REG_INT_MASK_0_SYNC_FIN_POP_ERROR_SHIFT                                             5
71284     #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR                                               (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_WR_PUSH_ERROR .
71285     #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                         6
71286     #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR                                                (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_WR_POP_ERROR .
71287     #define USEM_REG_INT_MASK_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                          7
71288     #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR                                               (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_RD_PUSH_ERROR .
71289     #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                         8
71290     #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR                                                (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DRA_RD_POP_ERROR .
71291     #define USEM_REG_INT_MASK_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                          9
71292     #define USEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR                                                  (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_FIN_PUSH_ERROR .
71293     #define USEM_REG_INT_MASK_0_SYNC_FIN_PUSH_ERROR_SHIFT                                            10
71294     #define USEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR                                               (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SEM_FAST_ADDRESS_ERROR .
71295     #define USEM_REG_INT_MASK_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                         11
71296     #define USEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO                                                     (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_LSB_INP_FIFO .
71297     #define USEM_REG_INT_MASK_0_CAM_LSB_INP_FIFO_SHIFT                                               12
71298     #define USEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO                                                     (0x1<<13) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_MSB_INP_FIFO .
71299     #define USEM_REG_INT_MASK_0_CAM_MSB_INP_FIFO_SHIFT                                               13
71300     #define USEM_REG_INT_MASK_0_CAM_OUT_FIFO                                                         (0x1<<14) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_OUT_FIFO .
71301     #define USEM_REG_INT_MASK_0_CAM_OUT_FIFO_SHIFT                                                   14
71302     #define USEM_REG_INT_MASK_0_FIN_FIFO                                                             (0x1<<15) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.FIN_FIFO .
71303     #define USEM_REG_INT_MASK_0_FIN_FIFO_SHIFT                                                       15
71304     #define USEM_REG_INT_MASK_0_THREAD_FIFO_ERROR                                                    (0x1<<16) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.THREAD_FIFO_ERROR .
71305     #define USEM_REG_INT_MASK_0_THREAD_FIFO_ERROR_SHIFT                                              16
71306     #define USEM_REG_INT_MASK_0_THREAD_OVERRUN                                                       (0x1<<17) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.THREAD_OVERRUN .
71307     #define USEM_REG_INT_MASK_0_THREAD_OVERRUN_SHIFT                                                 17
71308     #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR                                            (0x1<<18) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_STORE_PUSH_ERROR .
71309     #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                      18
71310     #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR                                             (0x1<<19) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_STORE_POP_ERROR .
71311     #define USEM_REG_INT_MASK_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                       19
71312     #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR                                             (0x1<<20) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_LOAD_PUSH_ERROR .
71313     #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                       20
71314     #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR                                              (0x1<<21) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_EXT_LOAD_POP_ERROR .
71315     #define USEM_REG_INT_MASK_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                        21
71316     #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR                                               (0x1<<22) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_RD_PUSH_ERROR .
71317     #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                         22
71318     #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR                                                (0x1<<23) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_RD_POP_ERROR .
71319     #define USEM_REG_INT_MASK_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                          23
71320     #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR                                                (0x1<<24) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_WR_POP_ERROR .
71321     #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                          24
71322     #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR                                               (0x1<<25) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_RAM_WR_PUSH_ERROR .
71323     #define USEM_REG_INT_MASK_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                         25
71324     #define USEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR                                                  (0x1<<26) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DBG_PUSH_ERROR .
71325     #define USEM_REG_INT_MASK_0_SYNC_DBG_PUSH_ERROR_SHIFT                                            26
71326     #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR                                                   (0x1<<27) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.SYNC_DBG_POP_ERROR .
71327     #define USEM_REG_INT_MASK_0_SYNC_DBG_POP_ERROR_SHIFT                                             27
71328     #define USEM_REG_INT_MASK_0_DBG_FIFO_ERROR                                                       (0x1<<28) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.DBG_FIFO_ERROR .
71329     #define USEM_REG_INT_MASK_0_DBG_FIFO_ERROR_SHIFT                                                 28
71330     #define USEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO                                                    (0x1<<29) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.CAM_MSB2_INP_FIFO .
71331     #define USEM_REG_INT_MASK_0_CAM_MSB2_INP_FIFO_SHIFT                                              29
71332     #define USEM_REG_INT_MASK_0_VFC_INTERRUPT                                                        (0x1<<30) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.VFC_INTERRUPT .
71333     #define USEM_REG_INT_MASK_0_VFC_INTERRUPT_SHIFT                                                  30
71334     #define USEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR                                                   (0x1<<31) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_0.VFC_OUT_FIFO_ERROR .
71335     #define USEM_REG_INT_MASK_0_VFC_OUT_FIFO_ERROR_SHIFT                                             31
71336 #define USEM_REG_INT_STS_WR_0                                                                        0x1900048UL //Access:WR   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
71337     #define USEM_REG_INT_STS_WR_0_ADDRESS_ERROR                                                      (0x1<<0) // Signals an unknown address to the rf module.
71338     #define USEM_REG_INT_STS_WR_0_ADDRESS_ERROR_SHIFT                                                0
71339     #define USEM_REG_INT_STS_WR_0_FIC_LAST_ERROR                                                     (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
71340     #define USEM_REG_INT_STS_WR_0_FIC_LAST_ERROR_SHIFT                                               1
71341     #define USEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR                                                   (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
71342     #define USEM_REG_INT_STS_WR_0_FIC_LENGTH_ERROR_SHIFT                                             2
71343     #define USEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR                                                     (0x1<<3) // Error in any one of the FIC FIFO is active.
71344     #define USEM_REG_INT_STS_WR_0_FIC_FIFO_ERROR_SHIFT                                               3
71345     #define USEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR                                                 (0x1<<4) // Error in Ext PAS_FIFO is active.
71346     #define USEM_REG_INT_STS_WR_0_PAS_BUF_FIFO_ERROR_SHIFT                                           4
71347     #define USEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR                                                 (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
71348     #define USEM_REG_INT_STS_WR_0_SYNC_FIN_POP_ERROR_SHIFT                                           5
71349     #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR                                             (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
71350     #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                       6
71351     #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR                                              (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
71352     #define USEM_REG_INT_STS_WR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                        7
71353     #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR                                             (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
71354     #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                       8
71355     #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR                                              (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
71356     #define USEM_REG_INT_STS_WR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                        9
71357     #define USEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR                                                (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
71358     #define USEM_REG_INT_STS_WR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                          10
71359     #define USEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR                                             (0x1<<11) // Signals an unknown address in the fast-memory window.
71360     #define USEM_REG_INT_STS_WR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                       11
71361     #define USEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO                                                   (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
71362     #define USEM_REG_INT_STS_WR_0_CAM_LSB_INP_FIFO_SHIFT                                             12
71363     #define USEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO                                                   (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
71364     #define USEM_REG_INT_STS_WR_0_CAM_MSB_INP_FIFO_SHIFT                                             13
71365     #define USEM_REG_INT_STS_WR_0_CAM_OUT_FIFO                                                       (0x1<<14) // Error in CAM_OUT fifo in cam block.
71366     #define USEM_REG_INT_STS_WR_0_CAM_OUT_FIFO_SHIFT                                                 14
71367     #define USEM_REG_INT_STS_WR_0_FIN_FIFO                                                           (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
71368     #define USEM_REG_INT_STS_WR_0_FIN_FIFO_SHIFT                                                     15
71369     #define USEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR                                                  (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
71370     #define USEM_REG_INT_STS_WR_0_THREAD_FIFO_ERROR_SHIFT                                            16
71371     #define USEM_REG_INT_STS_WR_0_THREAD_OVERRUN                                                     (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
71372     #define USEM_REG_INT_STS_WR_0_THREAD_OVERRUN_SHIFT                                               17
71373     #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR                                          (0x1<<18) // Error in external store sync FIFO push logic.
71374     #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                    18
71375     #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR                                           (0x1<<19) // Error in external store sync FIFO pop logic.
71376     #define USEM_REG_INT_STS_WR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                     19
71377     #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR                                           (0x1<<20) // Error in external load sync FIFO push logic.
71378     #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                     20
71379     #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR                                            (0x1<<21) // Error in external load sync FIFO pop logic.
71380     #define USEM_REG_INT_STS_WR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                      21
71381     #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR                                             (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
71382     #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                       22
71383     #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR                                              (0x1<<23) // Error in LS_SYNC_POP FIFO.
71384     #define USEM_REG_INT_STS_WR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                        23
71385     #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR                                              (0x1<<24) // Error in LS_SYNC_POP FIFO.
71386     #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                        24
71387     #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR                                             (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
71388     #define USEM_REG_INT_STS_WR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                       25
71389     #define USEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR                                                (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
71390     #define USEM_REG_INT_STS_WR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                          26
71391     #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR                                                 (0x1<<27) // Error in LS_SYNC_POP FIFO.
71392     #define USEM_REG_INT_STS_WR_0_SYNC_DBG_POP_ERROR_SHIFT                                           27
71393     #define USEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR                                                     (0x1<<28) // Error in slow debug fifo.
71394     #define USEM_REG_INT_STS_WR_0_DBG_FIFO_ERROR_SHIFT                                               28
71395     #define USEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO                                                  (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
71396     #define USEM_REG_INT_STS_WR_0_CAM_MSB2_INP_FIFO_SHIFT                                            29
71397     #define USEM_REG_INT_STS_WR_0_VFC_INTERRUPT                                                      (0x1<<30) // Error interrupt in VFC block.
71398     #define USEM_REG_INT_STS_WR_0_VFC_INTERRUPT_SHIFT                                                30
71399     #define USEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR                                                 (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
71400     #define USEM_REG_INT_STS_WR_0_VFC_OUT_FIFO_ERROR_SHIFT                                           31
71401 #define USEM_REG_INT_STS_CLR_0                                                                       0x190004cUL //Access:RC   DataWidth:0x20  Multi Field Register.  Chips: BB_A0 BB_B0 K2
71402     #define USEM_REG_INT_STS_CLR_0_ADDRESS_ERROR                                                     (0x1<<0) // Signals an unknown address to the rf module.
71403     #define USEM_REG_INT_STS_CLR_0_ADDRESS_ERROR_SHIFT                                               0
71404     #define USEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR                                                    (0x1<<1) // Last from FIC is not equal to length on any one of the FIC interfaces.
71405     #define USEM_REG_INT_STS_CLR_0_FIC_LAST_ERROR_SHIFT                                              1
71406     #define USEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR                                                  (0x1<<2) // FIC length > 44 register-quads on any one of the FIC interfaces.
71407     #define USEM_REG_INT_STS_CLR_0_FIC_LENGTH_ERROR_SHIFT                                            2
71408     #define USEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR                                                    (0x1<<3) // Error in any one of the FIC FIFO is active.
71409     #define USEM_REG_INT_STS_CLR_0_FIC_FIFO_ERROR_SHIFT                                              3
71410     #define USEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR                                                (0x1<<4) // Error in Ext PAS_FIFO is active.
71411     #define USEM_REG_INT_STS_CLR_0_PAS_BUF_FIFO_ERROR_SHIFT                                          4
71412     #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR                                                (0x1<<5) // Error in DRA_FIN_POP_SYNC_FIFO is active.
71413     #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_POP_ERROR_SHIFT                                          5
71414     #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR                                            (0x1<<6) // Error in DRA_WR_PUSH_SYNC_FIFO is active.
71415     #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_PUSH_ERROR_SHIFT                                      6
71416     #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR                                             (0x1<<7) // Error in DRA_WR_POP_SYNC_FIFO is active.
71417     #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_WR_POP_ERROR_SHIFT                                       7
71418     #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR                                            (0x1<<8) // Error in DRA_RD_PUSH_SYNC_FIFO is active.
71419     #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_PUSH_ERROR_SHIFT                                      8
71420     #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR                                             (0x1<<9) // Error in DRA_RD_POP_SYNC_FIFO is active.
71421     #define USEM_REG_INT_STS_CLR_0_SYNC_DRA_RD_POP_ERROR_SHIFT                                       9
71422     #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR                                               (0x1<<10) // Error in FIN_PUSH_SYNC_FIFO is active.
71423     #define USEM_REG_INT_STS_CLR_0_SYNC_FIN_PUSH_ERROR_SHIFT                                         10
71424     #define USEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR                                            (0x1<<11) // Signals an unknown address in the fast-memory window.
71425     #define USEM_REG_INT_STS_CLR_0_SEM_FAST_ADDRESS_ERROR_SHIFT                                      11
71426     #define USEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO                                                  (0x1<<12) // Error in CAM_LSB_INP fifo in cam block.
71427     #define USEM_REG_INT_STS_CLR_0_CAM_LSB_INP_FIFO_SHIFT                                            12
71428     #define USEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO                                                  (0x1<<13) // Error in CAM_MSB_INP fifo in cam block.
71429     #define USEM_REG_INT_STS_CLR_0_CAM_MSB_INP_FIFO_SHIFT                                            13
71430     #define USEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO                                                      (0x1<<14) // Error in CAM_OUT fifo in cam block.
71431     #define USEM_REG_INT_STS_CLR_0_CAM_OUT_FIFO_SHIFT                                                14
71432     #define USEM_REG_INT_STS_CLR_0_FIN_FIFO                                                          (0x1<<15) // Error in RD_FAST_FIN fifo in rd_fast block.
71433     #define USEM_REG_INT_STS_CLR_0_FIN_FIFO_SHIFT                                                    15
71434     #define USEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR                                                 (0x1<<16) // Error in thread fifo in sem_slow_dra_wr block.
71435     #define USEM_REG_INT_STS_CLR_0_THREAD_FIFO_ERROR_SHIFT                                           16
71436     #define USEM_REG_INT_STS_CLR_0_THREAD_OVERRUN                                                    (0x1<<17) // Thread 0 twice was active with maximum value of interrupt counter.
71437     #define USEM_REG_INT_STS_CLR_0_THREAD_OVERRUN_SHIFT                                              17
71438     #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR                                         (0x1<<18) // Error in external store sync FIFO push logic.
71439     #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_PUSH_ERROR_SHIFT                                   18
71440     #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR                                          (0x1<<19) // Error in external store sync FIFO pop logic.
71441     #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_STORE_POP_ERROR_SHIFT                                    19
71442     #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR                                          (0x1<<20) // Error in external load sync FIFO push logic.
71443     #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_PUSH_ERROR_SHIFT                                    20
71444     #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR                                           (0x1<<21) // Error in external load sync FIFO pop logic.
71445     #define USEM_REG_INT_STS_CLR_0_SYNC_EXT_LOAD_POP_ERROR_SHIFT                                     21
71446     #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR                                            (0x1<<22) // Error in LS_SYNC_PUSH FIFO.
71447     #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_PUSH_ERROR_SHIFT                                      22
71448     #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR                                             (0x1<<23) // Error in LS_SYNC_POP FIFO.
71449     #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_RD_POP_ERROR_SHIFT                                       23
71450     #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR                                             (0x1<<24) // Error in LS_SYNC_POP FIFO.
71451     #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_POP_ERROR_SHIFT                                       24
71452     #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR                                            (0x1<<25) // Error in LS_SYNC_PUSH FIFO.
71453     #define USEM_REG_INT_STS_CLR_0_SYNC_RAM_WR_PUSH_ERROR_SHIFT                                      25
71454     #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR                                               (0x1<<26) // Error in LS_SYNC_PUSH FIFO.
71455     #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_PUSH_ERROR_SHIFT                                         26
71456     #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR                                                (0x1<<27) // Error in LS_SYNC_POP FIFO.
71457     #define USEM_REG_INT_STS_CLR_0_SYNC_DBG_POP_ERROR_SHIFT                                          27
71458     #define USEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR                                                    (0x1<<28) // Error in slow debug fifo.
71459     #define USEM_REG_INT_STS_CLR_0_DBG_FIFO_ERROR_SHIFT                                              28
71460     #define USEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO                                                 (0x1<<29) // Error in CAM_MSB2_INP fifo in cam block.
71461     #define USEM_REG_INT_STS_CLR_0_CAM_MSB2_INP_FIFO_SHIFT                                           29
71462     #define USEM_REG_INT_STS_CLR_0_VFC_INTERRUPT                                                     (0x1<<30) // Error interrupt in VFC block.
71463     #define USEM_REG_INT_STS_CLR_0_VFC_INTERRUPT_SHIFT                                               30
71464     #define USEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR                                                (0x1<<31) // Error interrupt in output VFC FIFO inside SEM_PD block.
71465     #define USEM_REG_INT_STS_CLR_0_VFC_OUT_FIFO_ERROR_SHIFT                                          31
71466 #define USEM_REG_INT_STS_1                                                                           0x1900050UL //Access:R    DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71467     #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN                                                   (0x1<<0) // An underflow error was detected in the Storm stack.
71468     #define USEM_REG_INT_STS_1_STORM_STACK_UF_ATTN_SHIFT                                             0
71469     #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN                                                   (0x1<<1) // An overflow error was detected in the Storm stack.
71470     #define USEM_REG_INT_STS_1_STORM_STACK_OF_ATTN_SHIFT                                             1
71471     #define USEM_REG_INT_STS_1_STORM_RUNTIME_ERROR                                                   (0x1<<2) // The Storm detected an illegal runtime value.
71472     #define USEM_REG_INT_STS_1_STORM_RUNTIME_ERROR_SHIFT                                             2
71473     #define USEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR                                                (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
71474     #define USEM_REG_INT_STS_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                          3
71475     #define USEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR                                                 (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
71476     #define USEM_REG_INT_STS_1_THREAD_RLS_ORUN_ERROR_SHIFT                                           4
71477     #define USEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR                                                 (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
71478     #define USEM_REG_INT_STS_1_THREAD_RLS_ALOC_ERROR_SHIFT                                           5
71479     #define USEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR                                                  (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
71480     #define USEM_REG_INT_STS_1_THREAD_RLS_VLD_ERROR_SHIFT                                            6
71481     #define USEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR                                                  (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
71482     #define USEM_REG_INT_STS_1_EXT_THREAD_OOR_ERROR_SHIFT                                            7
71483     #define USEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR                                                     (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
71484     #define USEM_REG_INT_STS_1_ORD_ID_FIFO_ERROR_SHIFT                                               8
71485     #define USEM_REG_INT_STS_1_INVLD_FOC_ERROR                                                       (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
71486     #define USEM_REG_INT_STS_1_INVLD_FOC_ERROR_SHIFT                                                 9
71487     #define USEM_REG_INT_STS_1_EXT_LD_LEN_ERROR                                                      (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
71488     #define USEM_REG_INT_STS_1_EXT_LD_LEN_ERROR_SHIFT                                                10
71489     #define USEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR                                                   (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
71490     #define USEM_REG_INT_STS_1_THRD_ORD_FIFO_ERROR_SHIFT                                             11
71491     #define USEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR                                                  (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
71492     #define USEM_REG_INT_STS_1_INVLD_THRD_ORD_ERROR_SHIFT                                            12
71493 #define USEM_REG_INT_MASK_1                                                                          0x1900054UL //Access:RW   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71494     #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN                                                  (0x1<<0) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_UF_ATTN .
71495     #define USEM_REG_INT_MASK_1_STORM_STACK_UF_ATTN_SHIFT                                            0
71496     #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN                                                  (0x1<<1) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_STACK_OF_ATTN .
71497     #define USEM_REG_INT_MASK_1_STORM_STACK_OF_ATTN_SHIFT                                            1
71498     #define USEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR                                                  (0x1<<2) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.STORM_RUNTIME_ERROR .
71499     #define USEM_REG_INT_MASK_1_STORM_RUNTIME_ERROR_SHIFT                                            2
71500     #define USEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR                                               (0x1<<3) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_LOAD_PEND_WR_ERROR .
71501     #define USEM_REG_INT_MASK_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                         3
71502     #define USEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR                                                (0x1<<4) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_ORUN_ERROR .
71503     #define USEM_REG_INT_MASK_1_THREAD_RLS_ORUN_ERROR_SHIFT                                          4
71504     #define USEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR                                                (0x1<<5) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_ALOC_ERROR .
71505     #define USEM_REG_INT_MASK_1_THREAD_RLS_ALOC_ERROR_SHIFT                                          5
71506     #define USEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR                                                 (0x1<<6) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THREAD_RLS_VLD_ERROR .
71507     #define USEM_REG_INT_MASK_1_THREAD_RLS_VLD_ERROR_SHIFT                                           6
71508     #define USEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR                                                 (0x1<<7) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_THREAD_OOR_ERROR .
71509     #define USEM_REG_INT_MASK_1_EXT_THREAD_OOR_ERROR_SHIFT                                           7
71510     #define USEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR                                                    (0x1<<8) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.ORD_ID_FIFO_ERROR .
71511     #define USEM_REG_INT_MASK_1_ORD_ID_FIFO_ERROR_SHIFT                                              8
71512     #define USEM_REG_INT_MASK_1_INVLD_FOC_ERROR                                                      (0x1<<9) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.INVLD_FOC_ERROR .
71513     #define USEM_REG_INT_MASK_1_INVLD_FOC_ERROR_SHIFT                                                9
71514     #define USEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR                                                     (0x1<<10) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.EXT_LD_LEN_ERROR .
71515     #define USEM_REG_INT_MASK_1_EXT_LD_LEN_ERROR_SHIFT                                               10
71516     #define USEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR                                                  (0x1<<11) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.THRD_ORD_FIFO_ERROR .
71517     #define USEM_REG_INT_MASK_1_THRD_ORD_FIFO_ERROR_SHIFT                                            11
71518     #define USEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR                                                 (0x1<<12) // This bit masks, when set, the Interrupt bit: USEM_REG_INT_STS_1.INVLD_THRD_ORD_ERROR .
71519     #define USEM_REG_INT_MASK_1_INVLD_THRD_ORD_ERROR_SHIFT                                           12
71520 #define USEM_REG_INT_STS_WR_1                                                                        0x1900058UL //Access:WR   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71521     #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN                                                (0x1<<0) // An underflow error was detected in the Storm stack.
71522     #define USEM_REG_INT_STS_WR_1_STORM_STACK_UF_ATTN_SHIFT                                          0
71523     #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN                                                (0x1<<1) // An overflow error was detected in the Storm stack.
71524     #define USEM_REG_INT_STS_WR_1_STORM_STACK_OF_ATTN_SHIFT                                          1
71525     #define USEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR                                                (0x1<<2) // The Storm detected an illegal runtime value.
71526     #define USEM_REG_INT_STS_WR_1_STORM_RUNTIME_ERROR_SHIFT                                          2
71527     #define USEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR                                             (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
71528     #define USEM_REG_INT_STS_WR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                       3
71529     #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR                                              (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
71530     #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                        4
71531     #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR                                              (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
71532     #define USEM_REG_INT_STS_WR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                        5
71533     #define USEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR                                               (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
71534     #define USEM_REG_INT_STS_WR_1_THREAD_RLS_VLD_ERROR_SHIFT                                         6
71535     #define USEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR                                               (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
71536     #define USEM_REG_INT_STS_WR_1_EXT_THREAD_OOR_ERROR_SHIFT                                         7
71537     #define USEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR                                                  (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
71538     #define USEM_REG_INT_STS_WR_1_ORD_ID_FIFO_ERROR_SHIFT                                            8
71539     #define USEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR                                                    (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
71540     #define USEM_REG_INT_STS_WR_1_INVLD_FOC_ERROR_SHIFT                                              9
71541     #define USEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR                                                   (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
71542     #define USEM_REG_INT_STS_WR_1_EXT_LD_LEN_ERROR_SHIFT                                             10
71543     #define USEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR                                                (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
71544     #define USEM_REG_INT_STS_WR_1_THRD_ORD_FIFO_ERROR_SHIFT                                          11
71545     #define USEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR                                               (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
71546     #define USEM_REG_INT_STS_WR_1_INVLD_THRD_ORD_ERROR_SHIFT                                         12
71547 #define USEM_REG_INT_STS_CLR_1                                                                       0x190005cUL //Access:RC   DataWidth:0xd   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71548     #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN                                               (0x1<<0) // An underflow error was detected in the Storm stack.
71549     #define USEM_REG_INT_STS_CLR_1_STORM_STACK_UF_ATTN_SHIFT                                         0
71550     #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN                                               (0x1<<1) // An overflow error was detected in the Storm stack.
71551     #define USEM_REG_INT_STS_CLR_1_STORM_STACK_OF_ATTN_SHIFT                                         1
71552     #define USEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR                                               (0x1<<2) // The Storm detected an illegal runtime value.
71553     #define USEM_REG_INT_STS_CLR_1_STORM_RUNTIME_ERROR_SHIFT                                         2
71554     #define USEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR                                            (0x1<<3) // There was an attempt to make an external load request when the previous request was still incomplete.
71555     #define USEM_REG_INT_STS_CLR_1_EXT_LOAD_PEND_WR_ERROR_SHIFT                                      3
71556     #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR                                             (0x1<<4) // There was a mutually exclusividity failure detected with regard to thread releases - i.e., attempt to release a thread from the SDM that already has a pending release.
71557     #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ORUN_ERROR_SHIFT                                       4
71558     #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR                                             (0x1<<5) // There was an attempt to release a thread that was already un-allocated.
71559     #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_ALOC_ERROR_SHIFT                                       5
71560     #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR                                              (0x1<<6) // There was an attempt to release a thread that is currently sleeping (valid bit is set).
71561     #define USEM_REG_INT_STS_CLR_1_THREAD_RLS_VLD_ERROR_SHIFT                                        6
71562     #define USEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR                                              (0x1<<7) // Indicates that a DMA request cycle was received which had an out-of-range thread ID encoded into the passive buffer address.
71563     #define USEM_REG_INT_STS_CLR_1_EXT_THREAD_OOR_ERROR_SHIFT                                        7
71564     #define USEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR                                                 (0x1<<8) // Indicates an overrun or underrun error in the order ID fifo of the sem_slow_dra_wr block.
71565     #define USEM_REG_INT_STS_CLR_1_ORD_ID_FIFO_ERROR_SHIFT                                           8
71566     #define USEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR                                                   (0x1<<9) // Indicates that the Storm attempted to send a FIN command with a FOC enumeration that is invalid for the associated SEMI.
71567     #define USEM_REG_INT_STS_CLR_1_INVLD_FOC_ERROR_SHIFT                                             9
71568     #define USEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR                                                  (0x1<<10) // Indicates that the Storm requested an external load transfer in which the length was larger than the supported length, based on the external load FIFO depth.
71569     #define USEM_REG_INT_STS_CLR_1_EXT_LD_LEN_ERROR_SHIFT                                            10
71570     #define USEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR                                               (0x1<<11) // Indicates that there was an attempt to pop from a thread order queue that was already empty.
71571     #define USEM_REG_INT_STS_CLR_1_THRD_ORD_FIFO_ERROR_SHIFT                                         11
71572     #define USEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR                                              (0x1<<12) // Indicates that Storm firmware attempted to pop the currently-running thread onto a thread- order queue when it was not at the head of the queue or firmware attempted to push/pop the currently runnig thread from a queue and the currently-running thread does not have an allocated thread ID (T-bit is cleared).
71573     #define USEM_REG_INT_STS_CLR_1_INVLD_THRD_ORD_ERROR_SHIFT                                        12
71574 #define USEM_REG_PRTY_MASK                                                                           0x19000ccUL //Access:RW   DataWidth:0x3   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71575     #define USEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR                                                  (0x1<<0) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.VFC_RBC_PARITY_ERROR .
71576     #define USEM_REG_PRTY_MASK_VFC_RBC_PARITY_ERROR_SHIFT                                            0
71577     #define USEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR                                                 (0x1<<1) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.STORM_RF_PARITY_ERROR .
71578     #define USEM_REG_PRTY_MASK_STORM_RF_PARITY_ERROR_SHIFT                                           1
71579     #define USEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR                                                  (0x1<<2) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS.REG_GEN_PARITY_ERROR .
71580     #define USEM_REG_PRTY_MASK_REG_GEN_PARITY_ERROR_SHIFT                                            2
71581 #define USEM_REG_PRTY_MASK_H_0                                                                       0x1900204UL //Access:RW   DataWidth:0x6   Multi Field Register.  Chips: BB_A0 BB_B0 K2
71582     #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT                                             (0x1<<0) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM005_I_ECC_0_RF_INT .
71583     #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_0_RF_INT_SHIFT                                       0
71584     #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT                                             (0x1<<1) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM005_I_ECC_1_RF_INT .
71585     #define USEM_REG_PRTY_MASK_H_0_MEM005_I_ECC_1_RF_INT_SHIFT                                       1
71586     #define USEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY                                                 (0x1<<2) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM004_I_MEM_PRTY .
71587     #define USEM_REG_PRTY_MASK_H_0_MEM004_I_MEM_PRTY_SHIFT                                           2
71588     #define USEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY                                                 (0x1<<3) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM002_I_MEM_PRTY .
71589     #define USEM_REG_PRTY_MASK_H_0_MEM002_I_MEM_PRTY_SHIFT                                           3
71590     #define USEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY                                                 (0x1<<4) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM003_I_MEM_PRTY .
71591     #define USEM_REG_PRTY_MASK_H_0_MEM003_I_MEM_PRTY_SHIFT                                           4
71592     #define USEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY                                                 (0x1<<5) // This bit masks, when set, the Parity bit: USEM_REG_PRTY_STS_H_0.MEM001_I_MEM_PRTY .
71593     #define USEM_REG_PRTY_MASK_H_0_MEM001_I_MEM_PRTY_SHIFT                                           5
71594 #define USEM_REG_MEM_ECC_EVENTS                                                                      0x190021cUL //Access:RC   DataWidth:0x20  Count all the block memories ECC events.  Chips: BB_A0 BB_B0 K2
71595 #define USEM_REG_MEM004_I_MEM_DFT_K2                                                                 0x1900224UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usem.i_sem_core.i_sem_slow.i_sem_slow_int_table_ram.i_mem of module es_gmem_1rw. [2]=rme, [1:0]=t_strw.  Chips: K2
71596 #define USEM_REG_MEM005_I_MEM_DFT_K2                                                                 0x1900228UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usem.i_sem_core.i_sem_slow.i_sem_slow_pas_buf_ram_wrap.USEM_PAS_BUF_RAM_GEN_IF.i_sem_slow_pas_buf_ram_usem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
71597 #define USEM_REG_MEM002_I_MEM_DFT_K2                                                                 0x190022cUL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usem.i_sem_core.i_sem_slow.i_sem_slow_ext_pas_fifo_wrap.USEM_EXT_PAS_FIFO_GEN_IF.i_sem_slow_ext_pas_fifo_usem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
71598 #define USEM_REG_MEM003_I_MEM_DFT_K2                                                                 0x1900230UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usem.i_sem_core.i_sem_slow.i_sem_slow_fic_fifo_wrap.USEM_FIC0_FIFO_MEM_GEN_IF.i_sem_slow_fic0_fifo_usem.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
71599 #define USEM_REG_MEM001_I_MEM_DFT_K2                                                                 0x1900234UL //Access:RW   DataWidth:0x3   Control the DFT rme and t_strw bits of the memory instance usem.i_sem_core.i_sem_slow.i_sem_slow_dbg_fifo.i_mem of module es_gmem_1r1w. [2]=rme, [1:0]=t_strw.  Chips: K2
71600 #define USEM_REG_ARB_CYCLE_SIZE                                                                      0x1900400UL //Access:RW   DataWidth:0x5   The number of time_slots in the arbitration cycle.  Chips: BB_A0 BB_B0 K2
71601 #define USEM_REG_VF_ERROR                                                                            0x1900408UL //Access:WR   DataWidth:0x1   This VF-split register provides read/clear access to the VF error received from the SDM for a DMA transfer. Reading this register will return the VF Error for value for the corresponding VF. Writing a 1 to this register will clear the error for the corresponding VF.  Chips: BB_A0 BB_B0 K2
71602 #define USEM_REG_PF_ERROR                                                                            0x190040cUL //Access:WR   DataWidth:0x1   This PF-split register provides read/clear access to the PF error received from the SDM for a DMA transfer. Reading this register will return the PF Error for value for the corresponding PF. Writing a 1 to this register will clear the error for the corresponding PF.  Chips: BB_A0 BB_B0 K2
71603 #define USEM_REG_VF_ERR_VECTOR                                                                       0x1900420UL //Access:WB_R DataWidth:0xc0  This read-only register provides a vector of bits having an error indication per VF where the Bit position corresponds to the VFID.  Chips: BB_A0 BB_B0 K2
71604 #define USEM_REG_VF_ERR_VECTOR_SIZE                                                                  8
71605 #define USEM_REG_PF_ERR_VECTOR                                                                       0x1900440UL //Access:R    DataWidth:0x10  This read-only register provides a vector of bits having an error indication per PF where the Bit position corresponds to the PFID.  Chips: BB_A0 BB_B0 K2
71606 #define USEM_REG_CLEAR_STALL                                                                         0x1900444UL //Access:RW   DataWidth:0x1   Clear stall signal sent from local storm to external storms.  Chips: BB_A0 BB_B0 K2
71607 #define USEM_REG_EXCEPTION_INT                                                                       0x1900448UL //Access:RW   DataWidth:0x10  Provides a default PRAM address to be used for the handler in the event that the PRAM address retrieved from the interrupt table is out of range with regard to the actual PRAM size provided in the SEMI instance.  Chips: BB_A0 BB_B0 K2
71608 #define USEM_REG_EXT_STORE_FREE_ENTRIES                                                              0x190044cUL //Access:R    DataWidth:0x6   Number of free entries in the external STORE sync FIFO.  Chips: BB_A0 BB_B0 K2
71609 #define USEM_REG_GPI_DATA                                                                            0x1900450UL //Access:R    DataWidth:0x20  Used to read the GPI input signals.  Chips: BB_A0 BB_B0 K2
71610 #define USEM_REG_GPRE_SAMP_PERIOD                                                                    0x1900454UL //Access:RW   DataWidth:0x4   Defines the number of system clocks from one sample of GPRE sync data and the next.  Chips: BB_A0 BB_B0 K2
71611 #define USEM_REG_ALLOW_LP_SLEEP_THRD                                                                 0x1900458UL //Access:RW   DataWidth:0x1   When set, this bit is used to allow low-power mode to be activated while threads are sleeping in the passive buffer, as long as the SEMI/Storm remains idle.  Chips: BB_A0 BB_B0 K2
71612 #define USEM_REG_ECO_RESERVED                                                                        0x190045cUL //Access:RW   DataWidth:0x8   This register is reserved for future ECO fixes. It may be used for chicken-bits, etc.  Chips: BB_A0 BB_B0 K2
71613 #define USEM_REG_FIC_GAP_VECT                                                                        0x1900500UL //Access:WB   DataWidth:0x2c  This array of nine 44-bit vectors provides a bit per register-quad, used to define the register-quad locations that should be included in gaps (discontinuities) within the DRA transfer, where bit-0 corresponds with IORs 0-3, and so on. To indicate a gap, the corresponding bit should be cleared. These gaps have a granularity of a register- quad (four IORs). For each DRA write transfer from whom the FIC is the source, one of nine gap vectors (or a default-gap vector) will be selected, based on the GapSelect field of the corresponding interrupt table entry. Any unused upper bits of the vector will be ignored and thus, can be written with any value.  Chips: BB_A0 BB_B0 K2
71614 #define USEM_REG_FIC_GAP_VECT_SIZE                                                                   18
71615 #define USEM_REG_FIC_FIFO                                                                            0x1900580UL //Access:WB_R DataWidth:0x80  Used for debugging to read/write to/from the FIC FIFOs. The address selects which FIFO should be accessed.  Chips: BB_A0 BB_B0 K2
71616 #define USEM_REG_FIC_FIFO_SIZE                                                                       4
71617 #define USEM_REG_FIC_MIN_MSG                                                                         0x1900600UL //Access:RW   DataWidth:0x6   Per-FIC interface register array defines minimum number of cycles in the FIC interfaces after which the message can be sent to the passive register_file.  Chips: BB_A0 BB_B0 K2
71618 #define USEM_REG_FIC_EMPTY_CT_MODE                                                                   0x1900620UL //Access:RW   DataWidth:0x1   When set, enables the "empty cut-through" mode for the FIC interface. In this mode, the FIC interface will not require that the available ("go") counter is non-zero before making a transfer request to the DRA arbiter and starting a transfer.  Chips: BB_A0 BB_B0 K2
71619 #define USEM_REG_FIC_EMPTY_CT_CNT                                                                    0x1900624UL //Access:RC   DataWidth:0x18  Statistics counter used to count the number of FIC messages that have been received on any FIC interface and were allowed to start early, taking advantage of the FIC empty cut-through mode.  Chips: BB_A0 BB_B0 K2
71620 #define USEM_REG_FOC_CREDIT                                                                          0x1900680UL //Access:RW   DataWidth:0x8   Array of registers provides the initial credits on each of the associatef FOC interfaces. Reading from this register provides the current FOR credit value.  Chips: BB_A0 BB_B0 K2
71621 #define USEM_REG_FOC_CREDIT_SIZE                                                                     5
71622 #define USEM_REG_FULL_FOC_DRA_STRT_EN                                                                0x19006c0UL //Access:RW   DataWidth:0x1   When set, this bit allows the DRA read operation to start even when there are not enough credits on all the participating FOC interfaces to complete the entire transaction. The transfer will stall only when a transfer cycle is reached in which there are no interface credits, at which time the DRA transfer will remain stalled until the FOC destination(s) has at least a single credit. When this configuration is cleared, the DRA read transfer will not begin until there are enough credits on all the participating FOC interfaces for the entire transfer.  Chips: BB_A0 BB_B0 K2
71623 #define USEM_REG_FIN_COMMAND                                                                         0x1900700UL //Access:WB_R DataWidth:0x164 Last fin command that was read from fifo. Its spelling in FIN_FIFO register.  Chips: BB_A0 BB_B0 K2
71624 #define USEM_REG_FIN_COMMAND_SIZE                                                                    16
71625 #define USEM_REG_FIN_FIFO                                                                            0x1900800UL //Access:WB_R DataWidth:0x164 READ ONLY FOR DEBUGGING! [5:0]   start_rp_foc3; [11:6] start_rp_foc2;  [17:12]   start_rp_foc1; [23:18] start_rp_foc0;  [29:24]   end_rp_foc3; [35:30] end_rp_foc2; [41:36]   end_rp_foc1; [47:42]   end_rp_foc0; [53:48]   lowest rp; [59:54]   highest rp; [65:60]   store start rp; [71:66]   store end rp; [77:72]   load start rp; [83:78]   load end rp; [85:84]   priority; [101:86]  pram address; [102] pas; [103] foc3; [104] foc2; [105] foc1; [106] foc0; [107] release; [108] fin; [109]=1- fin fifo is empty; 0 - data[108:0] is valid.  Chips: BB_A0 BB_B0 K2
71626 #define USEM_REG_FIN_FIFO_SIZE                                                                       16
71627 #define USEM_REG_INVLD_PAS_WR_EN                                                                     0x1900900UL //Access:RW   DataWidth:0x1   When set, an attempt to write to the passive buffer over the external passive interface will be enabled even if the partition being written is owned by a thread whose valid bit is not set. Otherwise if cleared, the transfer will be stalled.  Chips: BB_A0 BB_B0 K2
71628 #define USEM_REG_ARBITER_REQUEST                                                                     0x1900980UL //Access:R    DataWidth:0x5   Dra arbiter last request: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
71629 #define USEM_REG_ARBITER_SELECT                                                                      0x1900984UL //Access:R    DataWidth:0x5   Dra arbiter last selection: 0-fic0; 1-fic1; 2-priority0; 3-priority1; 4-priority2.  Chips: BB_A0 BB_B0 K2
71630 #define USEM_REG_ARBITER_SLOT                                                                        0x1900988UL //Access:R    DataWidth:0x5   Dra arbiter last slot.  Chips: BB_A0 BB_B0 K2
71631 #define USEM_REG_ARB_AS_DEF                                                                          0x1900a00UL //Access:RW   DataWidth:0x3   Two-dimensional register array is used to define each of four arbitration schemes used by the main DRA arbiter. For this, bits 4:3 of the offset are used to select the arbitration scheme 0-3. Bits 2:0 of the offset are used to define the five priority sources for the selected scheme, where for each priority (0-4), an arbiter source is assigned. Valid values for these configurations are the source enumerations, where FIC0=0x0, FIC1=0x1, wake priority0=0x2, wake priority1=0x3 and wake priority2=0x4. Note that there are holes in the indirect offset address which always return zero when read. These exist at offsets 0x5-0x7, 0xd-0xf, 0x15-0x17 and 0x1d-0x1f.  Chips: BB_A0 BB_B0 K2
71632 #define USEM_REG_ARB_AS_DEF_SIZE                                                                     32
71633 #define USEM_REG_ARB_TS_AS                                                                           0x1900a80UL //Access:RW   DataWidth:0x2   Register array that defines the main DRA arbiter arbitration scheme for each of 20 time slots [0-19].  Chips: BB_A0 BB_B0 K2
71634 #define USEM_REG_ARB_TS_AS_SIZE                                                                      20
71635 #define USEM_REG_NUM_OF_THREADS                                                                      0x1900b00UL //Access:R    DataWidth:0x5   The number of curretnly free threads.  Chips: BB_A0 BB_B0 K2
71636 #define USEM_REG_THREAD_ERROR                                                                        0x1900b04UL //Access:R    DataWidth:0x10  Thread error indication.  Chips: BB_A0 BB_B0 K2
71637 #define USEM_REG_THREAD_RDY                                                                          0x1900b08UL //Access:R    DataWidth:0x10  Thread ready indication.  Chips: BB_A0 BB_B0 K2
71638 #define USEM_REG_THREAD_SET_NUM                                                                      0x1900b0cUL //Access:W    DataWidth:0x5   Thread ID. Write thread ID will set ready indication for this thread ID.  Chips: BB_A0 BB_B0 K2
71639 #define USEM_REG_THREAD_VALID                                                                        0x1900b10UL //Access:R    DataWidth:0x10  Valid sleeping threads.  Chips: BB_A0 BB_B0 K2
71640 #define USEM_REG_THREADS_LIST                                                                        0x1900b14UL //Access:RW   DataWidth:0x10  List of free threads.  Chips: BB_A0 BB_B0 K2
71641 #define USEM_REG_ORDER_HEAD                                                                          0x1900c00UL //Access:RW   DataWidth:0x4   This (indirect) register array of registers provides read/write access to the head pointers assigned to each of the thread-ordering queues.  Chips: BB_A0 BB_B0 K2
71642 #define USEM_REG_ORDER_HEAD_SIZE                                                                     16
71643 #define USEM_REG_ORDER_TAIL                                                                          0x1900c80UL //Access:RW   DataWidth:0x4   This (indirect) register array of registers provides read/write access to the tail pointers assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
71644 #define USEM_REG_ORDER_TAIL_SIZE                                                                     16
71645 #define USEM_REG_ORDER_EMPTY                                                                         0x1900d00UL //Access:RW   DataWidth:0x1   This vector provides read-only access to the empty bit assigned to each of the thread ordering queues.  Chips: BB_A0 BB_B0 K2
71646 #define USEM_REG_ORDER_EMPTY_SIZE                                                                    16
71647 #define USEM_REG_ORDER_LL_REG                                                                        0x1900d80UL //Access:RW   DataWidth:0x4   This array of registers provides read/write access to each entry of the linked-list array of the thread-ordering queue. Because the actual depth is based on the number of threads supported by the design, which is a Verilog parameter, a 64-entry window is reserved in the register address space. The valid entries start at the base of the window and extend through the number of threads supported. The value in each indirect register contains linked-list pointer to the next thread in the associated queue..  Chips: BB_A0 BB_B0 K2
71648 #define USEM_REG_ORDER_LL_REG_SIZE                                                                   16
71649 #define USEM_REG_ORDER_POP_EN                                                                        0x1900e00UL //Access:RW   DataWidth:0x10  Provides access to the thread ordering queue pop-enable vector.  Chips: BB_A0 BB_B0 K2
71650 #define USEM_REG_ORDER_WAKE_EN                                                                       0x1900e08UL //Access:RW   DataWidth:0x10  Provides access to the thread ordering queue wake-enable vector.  Chips: BB_A0 BB_B0 K2
71651 #define USEM_REG_PF_NUM_ORDER_BASE                                                                   0x1900e10UL //Access:RW   DataWidth:0x4   This field defines the base value for the ordering queue selection when the PFNum is chosen to control this selection. The value of this register is added to PFNum and the result is used to select one of 16 ordering queues.  Chips: BB_A0 BB_B0 K2
71652 #define USEM_REG_DBG_ALM_FULL                                                                        0x1901000UL //Access:RW   DataWidth:0x6   Almost full for slow debug fifo.  Chips: BB_A0 BB_B0 K2
71653 #define USEM_REG_PASSIVE_ALM_FULL                                                                    0x1901004UL //Access:RW   DataWidth:0x5   The number of free entries in the sync FIFO between the external HW and the passive buffer; below which the PassiveFull is asserted.  Chips: BB_A0 BB_B0 K2
71654 #define USEM_REG_SYNC_DRA_WR_ALM_FULL                                                                0x1901008UL //Access:RW   DataWidth:0x5   Almost full for sync dra_wr fifo (data from DRA to STORM).  Chips: BB_A0 BB_B0 K2
71655 #define USEM_REG_SYNC_RAM_WR_ALM_FULL                                                                0x190100cUL //Access:RW   DataWidth:0x6   Almost full for sync ram_wr fifo (data from EXT_IF to STORM).  Chips: BB_A0 BB_B0 K2
71656 #define USEM_REG_DRA_EMPTY                                                                           0x1901100UL //Access:R    DataWidth:0x1   Dra_empty.  Chips: BB_A0 BB_B0 K2
71657 #define USEM_REG_EXT_PAS_EMPTY                                                                       0x1901104UL //Access:R    DataWidth:0x1   EXT_PAS FIFO empty in sem_slow.  Chips: BB_A0 BB_B0 K2
71658 #define USEM_REG_FIC_EMPTY                                                                           0x1901120UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO empty in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
71659 #define USEM_REG_SLOW_DBG_EMPTY                                                                      0x1901140UL //Access:R    DataWidth:0x1   DBG FIFO is empty in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
71660 #define USEM_REG_SLOW_DRA_FIN_EMPTY                                                                  0x1901144UL //Access:R    DataWidth:0x1   FIN fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71661 #define USEM_REG_SLOW_DRA_RD_EMPTY                                                                   0x1901148UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71662 #define USEM_REG_SLOW_DRA_WR_EMPTY                                                                   0x190114cUL //Access:R    DataWidth:0x1   DRA_WR push fifo is empty in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71663 #define USEM_REG_SLOW_EXT_STORE_EMPTY                                                                0x1901150UL //Access:R    DataWidth:0x1   EXT_STORE FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71664 #define USEM_REG_SLOW_EXT_LOAD_EMPTY                                                                 0x1901154UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71665 #define USEM_REG_SLOW_RAM_RD_EMPTY                                                                   0x1901158UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71666 #define USEM_REG_SLOW_RAM_WR_EMPTY                                                                   0x190115cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is empty in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71667 #define USEM_REG_SYNC_DBG_EMPTY                                                                      0x1901160UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is empty in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
71668 #define USEM_REG_THREAD_FIFO_EMPTY                                                                   0x1901164UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
71669 #define USEM_REG_ORD_ID_FIFO_EMPTY                                                                   0x1901168UL //Access:R    DataWidth:0x1   Indicates that the order ID fifo is empty in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
71670 #define USEM_REG_EXT_PAS_FULL                                                                        0x1901200UL //Access:R    DataWidth:0x1   EXT_PAS FIFO Full in sem_slow.  Chips: BB_A0 BB_B0 K2
71671 #define USEM_REG_EXT_STORE_IF_FULL                                                                   0x1901204UL //Access:R    DataWidth:0x1   EXT_STORE IF is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71672 #define USEM_REG_FIC_FULL                                                                            0x1901220UL //Access:R    DataWidth:0x1   Array of registers reflects associated FIC FIFO full in sem_slow_fic.  Chips: BB_A0 BB_B0 K2
71673 #define USEM_REG_PAS_IF_FULL                                                                         0x1901240UL //Access:R    DataWidth:0x1   Full from passive buffer asserted toward SDM.  Chips: BB_A0 BB_B0 K2
71674 #define USEM_REG_RAM_IF_FULL                                                                         0x1901244UL //Access:R    DataWidth:0x1   EXT_RAM IF is full in sem_slow_ls_ram.  Chips: BB_A0 BB_B0 K2
71675 #define USEM_REG_SLOW_DBG_ALM_FULL                                                                   0x1901248UL //Access:R    DataWidth:0x1   DBG FIFO is almost full in sem_slow_ls_dbg according to the full threshold configuration.  Chips: BB_A0 BB_B0 K2
71676 #define USEM_REG_SLOW_DBG_FULL                                                                       0x190124cUL //Access:R    DataWidth:0x1   DBG FIFO is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
71677 #define USEM_REG_SLOW_DRA_FIN_FULL                                                                   0x1901250UL //Access:R    DataWidth:0x1   FIN fifo is full in sem_slow_dra_sync (never may be active).  Chips: BB_A0 BB_B0 K2
71678 #define USEM_REG_SLOW_DRA_RD_FULL                                                                    0x1901254UL //Access:R    DataWidth:0x1   DRA_RD pop fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71679 #define USEM_REG_SLOW_DRA_WR_FULL                                                                    0x1901258UL //Access:R    DataWidth:0x1   DRA_WR push fifo is full in sem_slow_dra_sync.  Chips: BB_A0 BB_B0 K2
71680 #define USEM_REG_SLOW_EXT_STORE_FULL                                                                 0x190125cUL //Access:R    DataWidth:0x1   EXT_STORE FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71681 #define USEM_REG_SLOW_EXT_LOAD_FULL                                                                  0x1901260UL //Access:R    DataWidth:0x1   EXT_LOAD FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71682 #define USEM_REG_SLOW_RAM_RD_FULL                                                                    0x1901264UL //Access:R    DataWidth:0x1   EXT_RD_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71683 #define USEM_REG_SLOW_RAM_WR_ALM_FULL                                                                0x1901268UL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is almost full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71684 #define USEM_REG_SLOW_RAM_WR_FULL                                                                    0x190126cUL //Access:R    DataWidth:0x1   EXT_WR_RAM FIFO is full in sem_slow_ls_ext.  Chips: BB_A0 BB_B0 K2
71685 #define USEM_REG_SYNC_DBG_FULL                                                                       0x1901270UL //Access:R    DataWidth:0x1   DBG FAST SYNC FIFO is full in sem_slow_ls_sync.  Chips: BB_A0 BB_B0 K2
71686 #define USEM_REG_THREAD_FIFO_FULL                                                                    0x1901274UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
71687 #define USEM_REG_ORD_ID_FIFO_FULL                                                                    0x1901278UL //Access:R    DataWidth:0x1   Indicates that the thread fifo is full in sem_slow_dra_wr.  Chips: BB_A0 BB_B0 K2
71688 #define USEM_REG_THREAD_INTER_CNT                                                                    0x1901300UL //Access:RW   DataWidth:0x10  Maximum value of threads interrupt counter; when it gets this value then interrupt to will be send if thread active from previous maximum value of this counter.  Chips: BB_A0 BB_B0 K2
71689 #define USEM_REG_THREAD_INTER_CNT_ENABLE                                                             0x1901304UL //Access:RW   DataWidth:0x1   Enable for start count of thread_inter_cnt.  Chips: BB_A0 BB_B0 K2
71690 #define USEM_REG_THREAD_ORUN_NUM                                                                     0x1901308UL //Access:R    DataWidth:0x10  Threads are sleeping in passive buffer more than thread_inter_cnt number of cycles.  Chips: BB_A0 BB_B0 K2
71691 #define USEM_REG_SLOW_DBG_ACTIVE                                                                     0x1901400UL //Access:RW   DataWidth:0x1   Debug mode is active.  Chips: BB_A0 BB_B0 K2
71692 #define USEM_REG_SLOW_DBG_MODE                                                                       0x1901404UL //Access:RW   DataWidth:0x3   Debug mode for slow debug bus.  Chips: BB_A0 BB_B0 K2
71693 #define USEM_REG_DBG_FRAME_MODE                                                                      0x1901408UL //Access:RW   DataWidth:0x2   Debug frame mode control for the SEMI debug bus. The following values apply: "00" - indicates mode-0, which means all four words are provided by the fast debug. "01" - indicates mode-1, which means bits 127:64 belong to fast debug and bits 63:0 belong to slow debug. "10" - indicates mode-2, which means bits 127:96 belong to fast debug and bits 95:0 belong to slow debug. "11" - indicates mode-3, which means all four words are provided by the slow debug.  Chips: BB_A0 BB_B0 K2
71694 #define USEM_REG_DBG_EACH_CYLE                                                                       0x190140cUL //Access:RW   DataWidth:0x1   0=output every cycle; 1= output only when there is a change.  Chips: BB_A0 BB_B0 K2
71695 #define USEM_REG_DBG_GPRE_VECT                                                                       0x1901410UL //Access:RW   DataWidth:0x8   This 8-bit vector is used to enable the various 8 GPRE-quads that are to be captured by the fast debug channel when they are accessed for read by the Storm during mode-6 debug (handler trace). For this, bit-0 corresponds with GPRE[0-3] and bit-7 corresponds with GPRE[28-31].  Chips: BB_A0 BB_B0 K2
71696 #define USEM_REG_DBG_IF_FULL                                                                         0x1901414UL //Access:R    DataWidth:0x1   DBG IF is full in sem_slow_ls_dbg.  Chips: BB_A0 BB_B0 K2
71697 #define USEM_REG_DBG_MODE0_CFG                                                                       0x1901418UL //Access:RW   DataWidth:0x1   0=all the message; 1=partial message.  Chips: BB_A0 BB_B0 K2
71698 #define USEM_REG_DBG_MODE0_CFG_CYCLE                                                                 0x190141cUL //Access:RW   DataWidth:0x5   In case DebugMode0Config = 1; the additional cycles to extract to the debug bus.  Chips: BB_A0 BB_B0 K2
71699 #define USEM_REG_DBG_MODE1_CFG                                                                       0x1901420UL //Access:RW   DataWidth:0x1   0=without the data; 1=with the data.  Chips: BB_A0 BB_B0 K2
71700 #define USEM_REG_DBG_MSG_SRC                                                                         0x1901424UL //Access:RW   DataWidth:0x3   This field is a mask used to enable (or filter) the various sources of DRA write debug packets. Setting a bit causes the corresponding interface to be enabled. Bit-0 corresponds with FIC0, bit-1 corresponds with FIC1 and bit-2 corresponds with DRA writes from the passive buffer. This applicable only for debug mode=0.  Chips: BB_A0 BB_B0 K2
71701 #define USEM_REG_DBG_OUT_DATA                                                                        0x1901500UL //Access:WB_R DataWidth:0x100 Dbgmux output data  Chips: BB_A0 BB_B0 K2
71702 #define USEM_REG_DBG_OUT_DATA_SIZE                                                                   8
71703 #define USEM_REG_DBG_OUT_VALID                                                                       0x1901520UL //Access:R    DataWidth:0x4   Dbgmux output valid  Chips: BB_A0 BB_B0 K2
71704 #define USEM_REG_DBG_OUT_FRAME                                                                       0x1901524UL //Access:R    DataWidth:0x4   Dbgmux output frame  Chips: BB_A0 BB_B0 K2
71705 #define USEM_REG_DBG_SELECT                                                                          0x1901528UL //Access:RW   DataWidth:0x8   DBMUX register for selecting a line to output  Chips: BB_A0 BB_B0 K2
71706 #define USEM_REG_DBG_DWORD_ENABLE                                                                    0x190152cUL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask for enabling dword (128bit line) / qword (256bit line)                           in the selected line (before shift).for selecting a line to output  Chips: BB_A0 BB_B0 K2
71707 #define USEM_REG_DBG_SHIFT                                                                           0x1901530UL //Access:RW   DataWidth:0x2   DBMUX register. Circular dword (128bit line) / qword (256bit line)                           right shifting of the selected line (after the masking).  Chips: BB_A0 BB_B0 K2
71708 #define USEM_REG_DBG_FORCE_VALID                                                                     0x1901534UL //Access:RW   DataWidth:0x4   DBMUX register. Bit mask  for forcing the valid signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
71709 #define USEM_REG_DBG_FORCE_FRAME                                                                     0x1901538UL //Access:RW   DataWidth:0x4   DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line)                           (before shift).  Chips: BB_A0 BB_B0 K2
71710 #define USEM_REG_EXT_PAS_FIFO                                                                        0x1908000UL //Access:WB_R DataWidth:0x4c  Provides read-only access of the external passive FIFO. Intended for debug purposes.  Chips: BB_A0 BB_B0 K2
71711 #define USEM_REG_EXT_PAS_FIFO_SIZE                                                                   76
71712 #define USEM_REG_INT_TABLE                                                                           0x1910000UL //Access:RW   DataWidth:0x15  Interrupt table read/write access. This register is intended to be written only when the system is idle. The fields of the interrupt table are as follows. int_table[20:17] = GapSel; int_table[16] = OrderEn; int_table[15:0] = PRAM Address  Chips: BB_A0 BB_B0 K2
71713 #define USEM_REG_INT_TABLE_SIZE                                                                      256
71714 #define USEM_REG_PASSIVE_BUFFER                                                                      0x1920000UL //Access:WB   DataWidth:0x80  Read and write to it is just for debugging. Passive buffer memory.  Chips: BB_A0 BB_B0 K2
71715 #define USEM_REG_PASSIVE_BUFFER_SIZE                                                                 2880
71716 #define USEM_REG_FAST_MEMORY                                                                         0x1940000UL //Access:RW   DataWidth:0x20  See sem_fast.xls for its description.  Chips: BB_A0 BB_B0 K2
71717 #define USEM_REG_FAST_MEMORY_SIZE                                                                    65536
71718 #define USEM_REG_PRAM                                                                                0x1980000UL //Access:WB   DataWidth:0x30  Pram memory.  Chips: BB_A0 BB_B0 K2
71719 #define USEM_REG_PRAM_SIZE                                                                           73728
71720 #define BAR0_MAP_REG_MSIX_TABLE                                                                      0x1c00000UL //Access:RW   DataWidth:0x20  MSIX table  Chips: BB_A0 BB_B0 K2
71721 #define BAR0_MAP_REG_MSIX_TABLE_SIZE                                                                 2048
71722 #define BAR0_MAP_REG_IGU_CMD                                                                         0x1c02000UL //Access:RW   DataWidth:0x20  IGU command memory  Chips: BB_A0 BB_B0 K2
71723 #define BAR0_MAP_REG_IGU_CMD_SIZE                                                                    57344
71724 #define BAR0_MAP_REG_TSDM_RAM                                                                        0x1c80000UL //Access:RW   DataWidth:0x20  TSDM RAM  Chips: BB_A0 BB_B0 K2
71725 #define BAR0_MAP_REG_TSDM_RAM_SIZE                                                                   131072
71726 #define BAR0_MAP_REG_MSDM_RAM                                                                        0x1d00000UL //Access:RW   DataWidth:0x20  MSDM RAM  Chips: BB_A0 BB_B0 K2
71727 #define BAR0_MAP_REG_MSDM_RAM_SIZE                                                                   131072
71728 #define BAR0_MAP_REG_USDM_RAM                                                                        0x1d80000UL //Access:RW   DataWidth:0x20  USDM RAM  Chips: BB_A0 BB_B0 K2
71729 #define BAR0_MAP_REG_USDM_RAM_SIZE                                                                   131072
71730 #define BAR0_MAP_REG_XSDM_RAM                                                                        0x1e00000UL //Access:RW   DataWidth:0x20  XSDM RAM  Chips: BB_A0 BB_B0 K2
71731 #define BAR0_MAP_REG_XSDM_RAM_SIZE                                                                   131072
71732 #define BAR0_MAP_REG_YSDM_RAM                                                                        0x1e80000UL //Access:RW   DataWidth:0x20  YSDM RAM  Chips: BB_A0 BB_B0 K2
71733 #define BAR0_MAP_REG_YSDM_RAM_SIZE                                                                   131072
71734 #define BAR0_MAP_REG_PSDM_RAM                                                                        0x1f00000UL //Access:RW   DataWidth:0x20  PSDM RAM  Chips: BB_A0 BB_B0 K2
71735 #define BAR0_MAP_REG_PSDM_RAM_SIZE                                                                   131072
71736 
71737 #endif
71738